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net/mlx4_en: Add interface identify support
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV		 39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
1b136de1 42#include <net/vxlan.h>
c27a02cd
YP		 43
44#include <linux/mlx4/driver.h>
45#include <linux/mlx4/device.h>
46#include <linux/mlx4/cmd.h>
47#include <linux/mlx4/cq.h>
48
49#include "mlx4_en.h"
50#include "en_port.h"
51
d317966b 52int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 53{
bc6a4744
AV		 54 struct mlx4_en_priv *priv = netdev_priv(dev);
55 int i;
d317966b 56 unsigned int offset = 0;
bc6a4744
AV		 57
58 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 59 return -EINVAL;
60
bc6a4744
AV		 61 netdev_set_num_tc(dev, up);
62
63 /* Partition Tx queues evenly amongst UP's */
bc6a4744 64 for (i = 0; i < up; i++) {
d317966b
AV		 65 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
66 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 67 }
68
897d7846
AV		 69 return 0;
70}
71
e0d1095a 72#ifdef CONFIG_NET_RX_BUSY_POLL
9e77a2b8
AV		 73/* must be called with local_bh_disable()d */
74static int mlx4_en_low_latency_recv(struct napi_struct *napi)
75{
76 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
77 struct net_device *dev = cq->dev;
78 struct mlx4_en_priv *priv = netdev_priv(dev);
41d942d5 79 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
9e77a2b8
AV		 80 int done;
81
82 if (!priv->port_up)
83 return LL_FLUSH_FAILED;
84
85 if (!mlx4_en_cq_lock_poll(cq))
86 return LL_FLUSH_BUSY;
87
88 done = mlx4_en_process_rx_cq(dev, cq, 4);
8501841a
AV		 89 if (likely(done))
90 rx_ring->cleaned += done;
91 else
92 rx_ring->misses++;
9e77a2b8
AV		 93
94 mlx4_en_cq_unlock_poll(cq);
95
96 return done;
97}
e0d1095a 98#endif /* CONFIG_NET_RX_BUSY_POLL */
9e77a2b8 99
1eb8c695
AV		 100#ifdef CONFIG_RFS_ACCEL
101
102struct mlx4_en_filter {
103 struct list_head next;
104 struct work_struct work;
105
75a353d4 106 u8 ip_proto;
1eb8c695
AV		 107 __be32 src_ip;
108 __be32 dst_ip;
109 __be16 src_port;
110 __be16 dst_port;
111
112 int rxq_index;
113 struct mlx4_en_priv *priv;
114 u32 flow_id; /* RFS infrastructure id */
115 int id; /* mlx4_en driver id */
116 u64 reg_id; /* Flow steering API id */
117 u8 activated; /* Used to prevent expiry before filter
118 * is attached
119 */
120 struct hlist_node filter_chain;
121};
122
123static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
124
75a353d4
EP		 125static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
126{
127 switch (ip_proto) {
128 case IPPROTO_UDP:
129 return MLX4_NET_TRANS_RULE_ID_UDP;
130 case IPPROTO_TCP:
131 return MLX4_NET_TRANS_RULE_ID_TCP;
132 default:
c3ca5205 133 return MLX4_NET_TRANS_RULE_NUM;
75a353d4
EP		 134 }
135};
136
1eb8c695
AV		 137static void mlx4_en_filter_work(struct work_struct *work)
138{
139 struct mlx4_en_filter *filter = container_of(work,
140 struct mlx4_en_filter,
141 work);
142 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 143 struct mlx4_spec_list spec_tcp_udp = {
144 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 145 {
146 .tcp_udp = {
147 .dst_port = filter->dst_port,
148 .dst_port_msk = (__force __be16)-1,
149 .src_port = filter->src_port,
150 .src_port_msk = (__force __be16)-1,
151 },
152 },
153 };
154 struct mlx4_spec_list spec_ip = {
155 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
156 {
157 .ipv4 = {
158 .dst_ip = filter->dst_ip,
159 .dst_ip_msk = (__force __be32)-1,
160 .src_ip = filter->src_ip,
161 .src_ip_msk = (__force __be32)-1,
162 },
163 },
164 };
165 struct mlx4_spec_list spec_eth = {
166 .id = MLX4_NET_TRANS_RULE_ID_ETH,
167 };
168 struct mlx4_net_trans_rule rule = {
169 .list = LIST_HEAD_INIT(rule.list),
170 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
171 .exclusive = 1,
172 .allow_loopback = 1,
f9162539 173 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 174 .port = priv->port,
175 .priority = MLX4_DOMAIN_RFS,
176 };
177 int rc;
1eb8c695
AV		 178 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
179
c3ca5205 180 if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) {
75a353d4
EP		 181 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
182 filter->ip_proto);
183 goto ignore;
184 }
1eb8c695
AV		 185 list_add_tail(&spec_eth.list, &rule.list);
186 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 187 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 188
1eb8c695 189 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 190 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 191 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
192
193 filter->activated = 0;
194
195 if (filter->reg_id) {
196 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
197 if (rc && rc != -ENOENT)
198 en_err(priv, "Error detaching flow. rc = %d\n", rc);
199 }
200
201 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
202 if (rc)
203 en_err(priv, "Error attaching flow. err = %d\n", rc);
204
75a353d4 205ignore:
1eb8c695
AV		 206 mlx4_en_filter_rfs_expire(priv);
207
208 filter->activated = 1;
209}
210
211static inline struct hlist_head *
212filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
213 __be16 src_port, __be16 dst_port)
214{
215 unsigned long l;
216 int bucket_idx;
217
218 l = (__force unsigned long)src_port |
219 ((__force unsigned long)dst_port << 2);
220 l ^= (__force unsigned long)(src_ip ^ dst_ip);
221
222 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
223
224 return &priv->filter_hash[bucket_idx];
225}
226
227static struct mlx4_en_filter *
228mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 229 __be32 dst_ip, u8 ip_proto, __be16 src_port,
230 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 231{
232 struct mlx4_en_filter *filter = NULL;
233
234 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
235 if (!filter)
236 return NULL;
237
238 filter->priv = priv;
239 filter->rxq_index = rxq_index;
240 INIT_WORK(&filter->work, mlx4_en_filter_work);
241
242 filter->src_ip = src_ip;
243 filter->dst_ip = dst_ip;
75a353d4 244 filter->ip_proto = ip_proto;
1eb8c695
AV		 245 filter->src_port = src_port;
246 filter->dst_port = dst_port;
247
248 filter->flow_id = flow_id;
249
ee64c0ee 250 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 251
252 list_add_tail(&filter->next, &priv->filters);
253 hlist_add_head(&filter->filter_chain,
254 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
255 dst_port));
256
257 return filter;
258}
259
260static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
261{
262 struct mlx4_en_priv *priv = filter->priv;
263 int rc;
264
265 list_del(&filter->next);
266
267 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
268 if (rc && rc != -ENOENT)
269 en_err(priv, "Error detaching flow. rc = %d\n", rc);
270
271 kfree(filter);
272}
273
274static inline struct mlx4_en_filter *
275mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 276 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 277{
1eb8c695
AV		 278 struct mlx4_en_filter *filter;
279 struct mlx4_en_filter *ret = NULL;
280
b67bfe0d 281 hlist_for_each_entry(filter,
1eb8c695
AV		 282 filter_hash_bucket(priv, src_ip, dst_ip,
283 src_port, dst_port),
284 filter_chain) {
285 if (filter->src_ip == src_ip &&
286 filter->dst_ip == dst_ip &&
75a353d4 287 filter->ip_proto == ip_proto &&
1eb8c695
AV		 288 filter->src_port == src_port &&
289 filter->dst_port == dst_port) {
290 ret = filter;
291 break;
292 }
293 }
294
295 return ret;
296}
297
298static int
299mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
300 u16 rxq_index, u32 flow_id)
301{
302 struct mlx4_en_priv *priv = netdev_priv(net_dev);
303 struct mlx4_en_filter *filter;
304 const struct iphdr *ip;
305 const __be16 *ports;
75a353d4 306 u8 ip_proto;
1eb8c695
AV		 307 __be32 src_ip;
308 __be32 dst_ip;
309 __be16 src_port;
310 __be16 dst_port;
311 int nhoff = skb_network_offset(skb);
312 int ret = 0;
313
314 if (skb->protocol != htons(ETH_P_IP))
315 return -EPROTONOSUPPORT;
316
317 ip = (const struct iphdr *)(skb->data + nhoff);
318 if (ip_is_fragment(ip))
319 return -EPROTONOSUPPORT;
320
75a353d4
EP		 321 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
322 return -EPROTONOSUPPORT;
1eb8c695
AV		 323 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
324
75a353d4 325 ip_proto = ip->protocol;
1eb8c695
AV		 326 src_ip = ip->saddr;
327 dst_ip = ip->daddr;
328 src_port = ports[0];
329 dst_port = ports[1];
330
1eb8c695 331 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 332 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
333 src_port, dst_port);
1eb8c695
AV		 334 if (filter) {
335 if (filter->rxq_index == rxq_index)
336 goto out;
337
338 filter->rxq_index = rxq_index;
339 } else {
340 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 341 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 342 src_port, dst_port, flow_id);
343 if (!filter) {
344 ret = -ENOMEM;
345 goto err;
346 }
347 }
348
349 queue_work(priv->mdev->workqueue, &filter->work);
350
351out:
352 ret = filter->id;
353err:
354 spin_unlock_bh(&priv->filters_lock);
355
356 return ret;
357}
358
41d942d5 359void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 360{
361 struct mlx4_en_filter *filter, *tmp;
362 LIST_HEAD(del_list);
363
364 spin_lock_bh(&priv->filters_lock);
365 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
366 list_move(&filter->next, &del_list);
367 hlist_del(&filter->filter_chain);
368 }
369 spin_unlock_bh(&priv->filters_lock);
370
371 list_for_each_entry_safe(filter, tmp, &del_list, next) {
372 cancel_work_sync(&filter->work);
373 mlx4_en_filter_free(filter);
374 }
375}
376
377static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
378{
379 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
380 LIST_HEAD(del_list);
381 int i = 0;
382
383 spin_lock_bh(&priv->filters_lock);
384 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
385 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
386 break;
387
388 if (filter->activated &&
389 !work_pending(&filter->work) &&
390 rps_may_expire_flow(priv->dev,
391 filter->rxq_index, filter->flow_id,
392 filter->id)) {
393 list_move(&filter->next, &del_list);
394 hlist_del(&filter->filter_chain);
395 } else
396 last_filter = filter;
397
398 i++;
399 }
400
401 if (last_filter && (&last_filter->next != priv->filters.next))
402 list_move(&priv->filters, &last_filter->next);
403
404 spin_unlock_bh(&priv->filters_lock);
405
406 list_for_each_entry_safe(filter, tmp, &del_list, next)
407 mlx4_en_filter_free(filter);
408}
409#endif
410
80d5c368
PM		 411static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
412 __be16 proto, u16 vid)
c27a02cd
YP		 413{
414 struct mlx4_en_priv *priv = netdev_priv(dev);
415 struct mlx4_en_dev *mdev = priv->mdev;
416 int err;
4c3eb3ca 417 int idx;
c27a02cd 418
f1b553fb 419 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 420
f1b553fb 421 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 422
423 /* Add VID to port VLAN filter */
424 mutex_lock(&mdev->state_lock);
425 if (mdev->device_up && priv->port_up) {
f1b553fb 426 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 427 if (err)
453a6082 428 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 429 }
4c3eb3ca 430 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 431 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 432 mutex_unlock(&mdev->state_lock);
4c3eb3ca 433
8e586137 434 return 0;
c27a02cd
YP		 435}
436
80d5c368
PM		 437static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
438 __be16 proto, u16 vid)
c27a02cd
YP		 439{
440 struct mlx4_en_priv *priv = netdev_priv(dev);
441 struct mlx4_en_dev *mdev = priv->mdev;
442 int err;
443
f1b553fb 444 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 445
f1b553fb 446 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 447
448 /* Remove VID from port VLAN filter */
449 mutex_lock(&mdev->state_lock);
2009d005 450 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 451
c27a02cd 452 if (mdev->device_up && priv->port_up) {
f1b553fb 453 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 454 if (err)
453a6082 455 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 456 }
457 mutex_unlock(&mdev->state_lock);
8e586137
JP		 458
459 return 0;
c27a02cd
YP		 460}
461
6bbb6d99
YB		 462static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
463{
bab6a9ea
YB		 464 int i;
465 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 466 dst_mac[i] = src_mac & 0xff;
467 src_mac >>= 8;
468 }
469 memset(&dst_mac[ETH_ALEN], 0, 2);
470}
471
837052d0
OG		 472
473static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
474 int qpn, u64 *reg_id)
475{
476 int err;
837052d0 477
5eff6dad
OG		 478 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
479 priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
837052d0
OG		 480 return 0; /* do nothing */
481
b95089d0
OG		 482 err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn,
483 MLX4_DOMAIN_NIC, reg_id);
837052d0
OG		 484 if (err) {
485 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
486 return err;
487 }
488 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
489 return 0;
490}
491
492
16a10ffd
YB		 493static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
494 unsigned char *mac, int *qpn, u64 *reg_id)
495{
496 struct mlx4_en_dev *mdev = priv->mdev;
497 struct mlx4_dev *dev = mdev->dev;
498 int err;
499
500 switch (dev->caps.steering_mode) {
501 case MLX4_STEERING_MODE_B0: {
502 struct mlx4_qp qp;
503 u8 gid[16] = {0};
504
505 qp.qpn = *qpn;
506 memcpy(&gid[10], mac, ETH_ALEN);
507 gid[5] = priv->port;
508
509 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
510 break;
511 }
512 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
513 struct mlx4_spec_list spec_eth = { {NULL} };
514 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
515
516 struct mlx4_net_trans_rule rule = {
517 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
518 .exclusive = 0,
519 .allow_loopback = 1,
f9162539 520 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 521 .priority = MLX4_DOMAIN_NIC,
522 };
523
524 rule.port = priv->port;
525 rule.qpn = *qpn;
526 INIT_LIST_HEAD(&rule.list);
527
528 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
529 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
530 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
531 list_add_tail(&spec_eth.list, &rule.list);
532
533 err = mlx4_flow_attach(dev, &rule, reg_id);
534 break;
535 }
536 default:
537 return -EINVAL;
538 }
539 if (err)
540 en_warn(priv, "Failed Attaching Unicast\n");
541
542 return err;
543}
544
545static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
546 unsigned char *mac, int qpn, u64 reg_id)
547{
548 struct mlx4_en_dev *mdev = priv->mdev;
549 struct mlx4_dev *dev = mdev->dev;
550
551 switch (dev->caps.steering_mode) {
552 case MLX4_STEERING_MODE_B0: {
553 struct mlx4_qp qp;
554 u8 gid[16] = {0};
555
556 qp.qpn = qpn;
557 memcpy(&gid[10], mac, ETH_ALEN);
558 gid[5] = priv->port;
559
560 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
561 break;
562 }
563 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
564 mlx4_flow_detach(dev, reg_id);
565 break;
566 }
567 default:
568 en_err(priv, "Invalid steering mode.\n");
569 }
570}
571
572static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
573{
574 struct mlx4_en_dev *mdev = priv->mdev;
575 struct mlx4_dev *dev = mdev->dev;
576 struct mlx4_mac_entry *entry;
577 int index = 0;
578 int err = 0;
c2a3d4b4 579 u64 reg_id = 0;
16a10ffd 580 int *qpn = &priv->base_qpn;
9813337a 581 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
16a10ffd
YB		 582
583 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
584 priv->dev->dev_addr);
585 index = mlx4_register_mac(dev, priv->port, mac);
586 if (index < 0) {
587 err = index;
588 en_err(priv, "Failed adding MAC: %pM\n",
589 priv->dev->dev_addr);
590 return err;
591 }
592
593 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
594 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
595 *qpn = base_qpn + index;
596 return 0;
597 }
598
d57febe1 599 err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP);
16a10ffd
YB		 600 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
601 if (err) {
602 en_err(priv, "Failed to reserve qp for mac registration\n");
603 goto qp_err;
604 }
605
606 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
607 if (err)
608 goto steer_err;
609
9ba75fb0
WY		 610 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
611 &priv->tunnel_reg_id);
612 if (err)
837052d0
OG		 613 goto tunnel_err;
614
16a10ffd
YB		 615 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
616 if (!entry) {
617 err = -ENOMEM;
618 goto alloc_err;
619 }
620 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
b94901f3 621 memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac));
16a10ffd
YB		 622 entry->reg_id = reg_id;
623
c07cb4b0
YB		 624 hlist_add_head_rcu(&entry->hlist,
625 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
16a10ffd 626
c07cb4b0 627 return 0;
16a10ffd
YB		 628
629alloc_err:
837052d0
OG		 630 if (priv->tunnel_reg_id)
631 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
632tunnel_err:
16a10ffd
YB		 633 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
634
635steer_err:
636 mlx4_qp_release_range(dev, *qpn, 1);
637
638qp_err:
639 mlx4_unregister_mac(dev, priv->port, mac);
640 return err;
641}
642
643static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
644{
645 struct mlx4_en_dev *mdev = priv->mdev;
646 struct mlx4_dev *dev = mdev->dev;
16a10ffd 647 int qpn = priv->base_qpn;
83a5a6ce 648 u64 mac;
16a10ffd 649
83a5a6ce 650 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
9813337a 651 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
83a5a6ce
YB		 652 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
653 priv->dev->dev_addr);
654 mlx4_unregister_mac(dev, priv->port, mac);
655 } else {
c07cb4b0 656 struct mlx4_mac_entry *entry;
b67bfe0d 657 struct hlist_node *tmp;
c07cb4b0 658 struct hlist_head *bucket;
83a5a6ce 659 unsigned int i;
c07cb4b0 660
83a5a6ce
YB		 661 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
662 bucket = &priv->mac_hash[i];
663 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
9813337a 664 mac = mlx4_mac_to_u64(entry->mac);
83a5a6ce
YB		 665 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
666 entry->mac);
c07cb4b0
YB		 667 mlx4_en_uc_steer_release(priv, entry->mac,
668 qpn, entry->reg_id);
c07cb4b0 669
83a5a6ce 670 mlx4_unregister_mac(dev, priv->port, mac);
c07cb4b0
YB		 671 hlist_del_rcu(&entry->hlist);
672 kfree_rcu(entry, rcu);
c07cb4b0 673 }
16a10ffd 674 }
83a5a6ce 675
837052d0
OG		 676 if (priv->tunnel_reg_id) {
677 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
678 priv->tunnel_reg_id = 0;
679 }
680
83a5a6ce
YB		 681 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
682 priv->port, qpn);
683 mlx4_qp_release_range(dev, qpn, 1);
684 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 685 }
686}
687
688static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 689 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 690{
691 struct mlx4_en_dev *mdev = priv->mdev;
692 struct mlx4_dev *dev = mdev->dev;
16a10ffd 693 int err = 0;
9813337a 694 u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
16a10ffd
YB		 695
696 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 697 struct hlist_head *bucket;
698 unsigned int mac_hash;
699 struct mlx4_mac_entry *entry;
b67bfe0d 700 struct hlist_node *tmp;
9813337a 701 u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
c07cb4b0
YB		 702
703 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 704 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 705 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
706 mlx4_en_uc_steer_release(priv, entry->mac,
707 qpn, entry->reg_id);
708 mlx4_unregister_mac(dev, priv->port,
709 prev_mac_u64);
710 hlist_del_rcu(&entry->hlist);
711 synchronize_rcu();
712 memcpy(entry->mac, new_mac, ETH_ALEN);
713 entry->reg_id = 0;
714 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
715 hlist_add_head_rcu(&entry->hlist,
716 &priv->mac_hash[mac_hash]);
717 mlx4_register_mac(dev, priv->port, new_mac_u64);
718 err = mlx4_en_uc_steer_add(priv, new_mac,
719 &qpn,
720 &entry->reg_id);
2a2083f7
OG		 721 if (err)
722 return err;
723 if (priv->tunnel_reg_id) {
724 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
725 priv->tunnel_reg_id = 0;
726 }
727 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
728 &priv->tunnel_reg_id);
c07cb4b0
YB		 729 return err;
730 }
731 }
732 return -EINVAL;
16a10ffd
YB		 733 }
734
735 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
736}
737
2695bab2
NO		 738static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv,
739 unsigned char new_mac[ETH_ALEN + 2])
c27a02cd 740{
c27a02cd
YP		 741 int err = 0;
742
c27a02cd
YP		 743 if (priv->port_up) {
744 /* Remove old MAC and insert the new one */
16a10ffd 745 err = mlx4_en_replace_mac(priv, priv->base_qpn,
2695bab2 746 new_mac, priv->current_mac);
c27a02cd 747 if (err)
453a6082 748 en_err(priv, "Failed changing HW MAC address\n");
c27a02cd 749 } else
48e551ff 750 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 751
2695bab2
NO		 752 if (!err)
753 memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac));
ee755324 754
bfa8ab47
YB		 755 return err;
756}
757
758static int mlx4_en_set_mac(struct net_device *dev, void *addr)
759{
760 struct mlx4_en_priv *priv = netdev_priv(dev);
761 struct mlx4_en_dev *mdev = priv->mdev;
762 struct sockaddr *saddr = addr;
2695bab2 763 unsigned char new_mac[ETH_ALEN + 2];
bfa8ab47
YB		 764 int err;
765
766 if (!is_valid_ether_addr(saddr->sa_data))
767 return -EADDRNOTAVAIL;
768
bfa8ab47 769 mutex_lock(&mdev->state_lock);
2695bab2
NO		 770 memcpy(new_mac, saddr->sa_data, ETH_ALEN);
771 err = mlx4_en_do_set_mac(priv, new_mac);
772 if (!err)
773 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
c27a02cd 774 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 775
776 return err;
c27a02cd
YP		 777}
778
779static void mlx4_en_clear_list(struct net_device *dev)
780{
781 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 782 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 783
6d199937
YP		 784 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
785 list_del(&mc_to_del->list);
786 kfree(mc_to_del);
787 }
c27a02cd
YP		 788}
789
790static void mlx4_en_cache_mclist(struct net_device *dev)
791{
792 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 793 struct netdev_hw_addr *ha;
6d199937 794 struct mlx4_en_mc_list *tmp;
ff6e2163 795
0e03567a 796 mlx4_en_clear_list(dev);
6d199937
YP		 797 netdev_for_each_mc_addr(ha, dev) {
798 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
799 if (!tmp) {
6d199937
YP		 800 mlx4_en_clear_list(dev);
801 return;
802 }
803 memcpy(tmp->addr, ha->addr, ETH_ALEN);
804 list_add_tail(&tmp->list, &priv->mc_list);
805 }
c27a02cd
YP		 806}
807
6d199937
YP		 808static void update_mclist_flags(struct mlx4_en_priv *priv,
809 struct list_head *dst,
810 struct list_head *src)
811{
812 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
813 bool found;
814
815 /* Find all the entries that should be removed from dst,
816 * These are the entries that are not found in src
817 */
818 list_for_each_entry(dst_tmp, dst, list) {
819 found = false;
820 list_for_each_entry(src_tmp, src, list) {
c0623e58 821 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 822 found = true;
823 break;
824 }
825 }
826 if (!found)
827 dst_tmp->action = MCLIST_REM;
828 }
829
830 /* Add entries that exist in src but not in dst
831 * mark them as need to add
832 */
833 list_for_each_entry(src_tmp, src, list) {
834 found = false;
835 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 836 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 837 dst_tmp->action = MCLIST_NONE;
838 found = true;
839 break;
840 }
841 }
842 if (!found) {
14f8dc49
JP		 843 new_mc = kmemdup(src_tmp,
844 sizeof(struct mlx4_en_mc_list),
6d199937 845 GFP_KERNEL);
14f8dc49 846 if (!new_mc)
6d199937 847 return;
14f8dc49 848
6d199937
YP		 849 new_mc->action = MCLIST_ADD;
850 list_add_tail(&new_mc->list, dst);
851 }
852 }
853}
c27a02cd 854
0eb74fdd 855static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 856{
857 struct mlx4_en_priv *priv = netdev_priv(dev);
858
859 if (!priv->port_up)
860 return;
861
0eb74fdd 862 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 863}
864
0eb74fdd
YB		 865static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
866 struct mlx4_en_dev *mdev)
c27a02cd 867{
c96d97f4 868 int err = 0;
c27a02cd 869
0eb74fdd 870 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 871 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 872 en_warn(priv, "Entering promiscuous mode\n");
873 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 874
0eb74fdd 875 /* Enable promiscouos mode */
c96d97f4 876 switch (mdev->dev->caps.steering_mode) {
592e49dd 877 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 878 err = mlx4_flow_steer_promisc_add(mdev->dev,
879 priv->port,
880 priv->base_qpn,
f9162539 881 MLX4_FS_ALL_DEFAULT);
592e49dd 882 if (err)
0eb74fdd
YB		 883 en_err(priv, "Failed enabling promiscuous mode\n");
884 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 885 break;
886
c96d97f4 887 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 888 err = mlx4_unicast_promisc_add(mdev->dev,
889 priv->base_qpn,
890 priv->port);
c96d97f4 891 if (err)
0eb74fdd
YB		 892 en_err(priv, "Failed enabling unicast promiscuous mode\n");
893
894 /* Add the default qp number as multicast
895 * promisc
896 */
897 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
898 err = mlx4_multicast_promisc_add(mdev->dev,
899 priv->base_qpn,
900 priv->port);
c96d97f4 901 if (err)
0eb74fdd
YB		 902 en_err(priv, "Failed enabling multicast promiscuous mode\n");
903 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 904 }
905 break;
c27a02cd 906
c96d97f4
HHZ		 907 case MLX4_STEERING_MODE_A0:
908 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
909 priv->port,
0eb74fdd
YB		 910 priv->base_qpn,
911 1);
1679200f 912 if (err)
0eb74fdd 913 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 914 break;
1679200f
YP		 915 }
916
0eb74fdd
YB		 917 /* Disable port multicast filter (unconditionally) */
918 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
919 0, MLX4_MCAST_DISABLE);
920 if (err)
921 en_err(priv, "Failed disabling multicast filter\n");
0eb74fdd
YB		 922 }
923}
924
925static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
926 struct mlx4_en_dev *mdev)
927{
928 int err = 0;
929
930 if (netif_msg_rx_status(priv))
931 en_warn(priv, "Leaving promiscuous mode\n");
932 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
933
934 /* Disable promiscouos mode */
935 switch (mdev->dev->caps.steering_mode) {
936 case MLX4_STEERING_MODE_DEVICE_MANAGED:
937 err = mlx4_flow_steer_promisc_remove(mdev->dev,
938 priv->port,
f9162539 939 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 940 if (err)
941 en_err(priv, "Failed disabling promiscuous mode\n");
942 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
943 break;
944
945 case MLX4_STEERING_MODE_B0:
946 err = mlx4_unicast_promisc_remove(mdev->dev,
947 priv->base_qpn,
948 priv->port);
949 if (err)
950 en_err(priv, "Failed disabling unicast promiscuous mode\n");
951 /* Disable Multicast promisc */
952 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
953 err = mlx4_multicast_promisc_remove(mdev->dev,
954 priv->base_qpn,
955 priv->port);
956 if (err)
957 en_err(priv, "Failed disabling multicast promiscuous mode\n");
958 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
959 }
960 break;
961
962 case MLX4_STEERING_MODE_A0:
963 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
964 priv->port,
965 priv->base_qpn, 0);
966 if (err)
967 en_err(priv, "Failed disabling promiscuous mode\n");
968 break;
c27a02cd 969 }
0eb74fdd
YB		 970}
971
972static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
973 struct net_device *dev,
974 struct mlx4_en_dev *mdev)
975{
976 struct mlx4_en_mc_list *mclist, *tmp;
977 u64 mcast_addr = 0;
978 u8 mc_list[16] = {0};
979 int err = 0;
980
c27a02cd
YP		 981 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
982 if (dev->flags & IFF_ALLMULTI) {
983 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
984 0, MLX4_MCAST_DISABLE);
985 if (err)
453a6082 986 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 987
988 /* Add the default qp number as multicast promisc */
989 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 990 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 991 case MLX4_STEERING_MODE_DEVICE_MANAGED:
992 err = mlx4_flow_steer_promisc_add(mdev->dev,
993 priv->port,
994 priv->base_qpn,
f9162539 995 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 996 break;
997
c96d97f4
HHZ		 998 case MLX4_STEERING_MODE_B0:
999 err = mlx4_multicast_promisc_add(mdev->dev,
1000 priv->base_qpn,
1001 priv->port);
1002 break;
1003
1004 case MLX4_STEERING_MODE_A0:
1005 break;
1006 }
1679200f
YP		 1007 if (err)
1008 en_err(priv, "Failed entering multicast promisc mode\n");
1009 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
1010 }
c27a02cd 1011 } else {
1679200f
YP		 1012 /* Disable Multicast promisc */
1013 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 1014 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1015 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1016 err = mlx4_flow_steer_promisc_remove(mdev->dev,
1017 priv->port,
f9162539 1018 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1019 break;
1020
c96d97f4
HHZ		 1021 case MLX4_STEERING_MODE_B0:
1022 err = mlx4_multicast_promisc_remove(mdev->dev,
1023 priv->base_qpn,
1024 priv->port);
1025 break;
1026
1027 case MLX4_STEERING_MODE_A0:
1028 break;
1029 }
1679200f 1030 if (err)
25985edc 1031 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 1032 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1033 }
ff6e2163 1034
c27a02cd
YP		 1035 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1036 0, MLX4_MCAST_DISABLE);
1037 if (err)
453a6082 1038 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 1039
1040 /* Flush mcast filter and init it with broadcast address */
1041 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
1042 1, MLX4_MCAST_CONFIG);
1043
1044 /* Update multicast list - we cache all addresses so they won't
1045 * change while HW is updated holding the command semaphor */
dbd501a8 1046 netif_addr_lock_bh(dev);
c27a02cd 1047 mlx4_en_cache_mclist(dev);
dbd501a8 1048 netif_addr_unlock_bh(dev);
6d199937 1049 list_for_each_entry(mclist, &priv->mc_list, list) {
9813337a 1050 mcast_addr = mlx4_mac_to_u64(mclist->addr);
c27a02cd
YP		 1051 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1052 mcast_addr, 0, MLX4_MCAST_CONFIG);
1053 }
1054 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1055 0, MLX4_MCAST_ENABLE);
1056 if (err)
453a6082 1057 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 1058
1059 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1060 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1061 if (mclist->action == MCLIST_REM) {
1062 /* detach this address and delete from list */
1063 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1064 mc_list[5] = priv->port;
1065 err = mlx4_multicast_detach(mdev->dev,
1066 &priv->rss_map.indir_qp,
1067 mc_list,
0ff1fb65
HHZ		 1068 MLX4_PROT_ETH,
1069 mclist->reg_id);
6d199937
YP		 1070 if (err)
1071 en_err(priv, "Fail to detach multicast address\n");
1072
837052d0
OG		 1073 if (mclist->tunnel_reg_id) {
1074 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1075 if (err)
1076 en_err(priv, "Failed to detach multicast address\n");
1077 }
1078
6d199937
YP		 1079 /* remove from list */
1080 list_del(&mclist->list);
1081 kfree(mclist);
9c64508a 1082 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1083 /* attach the address */
1084 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1085 /* needed for B0 steering support */
6d199937
YP		 1086 mc_list[5] = priv->port;
1087 err = mlx4_multicast_attach(mdev->dev,
1088 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1089 mc_list,
1090 priv->port, 0,
1091 MLX4_PROT_ETH,
1092 &mclist->reg_id);
6d199937
YP		 1093 if (err)
1094 en_err(priv, "Fail to attach multicast address\n");
1095
837052d0
OG		 1096 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1097 &mclist->tunnel_reg_id);
1098 if (err)
1099 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1100 }
1101 }
c27a02cd 1102 }
0eb74fdd
YB		 1103}
1104
cc5387f7
YB		 1105static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1106 struct net_device *dev,
1107 struct mlx4_en_dev *mdev)
1108{
1109 struct netdev_hw_addr *ha;
1110 struct mlx4_mac_entry *entry;
b67bfe0d 1111 struct hlist_node *tmp;
cc5387f7
YB		 1112 bool found;
1113 u64 mac;
1114 int err = 0;
1115 struct hlist_head *bucket;
1116 unsigned int i;
1117 int removed = 0;
1118 u32 prev_flags;
1119
1120 /* Note that we do not need to protect our mac_hash traversal with rcu,
1121 * since all modification code is protected by mdev->state_lock
1122 */
1123
1124 /* find what to remove */
1125 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1126 bucket = &priv->mac_hash[i];
b67bfe0d 1127 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1128 found = false;
1129 netdev_for_each_uc_addr(ha, dev) {
1130 if (ether_addr_equal_64bits(entry->mac,
1131 ha->addr)) {
1132 found = true;
1133 break;
1134 }
1135 }
1136
1137 /* MAC address of the port is not in uc list */
2695bab2
NO		 1138 if (ether_addr_equal_64bits(entry->mac,
1139 priv->current_mac))
cc5387f7
YB		 1140 found = true;
1141
1142 if (!found) {
9813337a 1143 mac = mlx4_mac_to_u64(entry->mac);
cc5387f7
YB		 1144 mlx4_en_uc_steer_release(priv, entry->mac,
1145 priv->base_qpn,
1146 entry->reg_id);
1147 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1148
1149 hlist_del_rcu(&entry->hlist);
1150 kfree_rcu(entry, rcu);
1151 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1152 entry->mac, priv->port);
1153 ++removed;
1154 }
1155 }
1156 }
1157
1158 /* if we didn't remove anything, there is no use in trying to add
1159 * again once we are in a forced promisc mode state
1160 */
1161 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1162 return;
1163
1164 prev_flags = priv->flags;
1165 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1166
1167 /* find what to add */
1168 netdev_for_each_uc_addr(ha, dev) {
1169 found = false;
1170 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1171 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1172 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1173 found = true;
1174 break;
1175 }
1176 }
1177
1178 if (!found) {
1179 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1180 if (!entry) {
1181 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1182 ha->addr, priv->port);
1183 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1184 break;
1185 }
9813337a 1186 mac = mlx4_mac_to_u64(ha->addr);
cc5387f7
YB		 1187 memcpy(entry->mac, ha->addr, ETH_ALEN);
1188 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1189 if (err < 0) {
1190 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1191 ha->addr, priv->port, err);
1192 kfree(entry);
1193 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1194 break;
1195 }
1196 err = mlx4_en_uc_steer_add(priv, ha->addr,
1197 &priv->base_qpn,
1198 &entry->reg_id);
1199 if (err) {
1200 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1201 ha->addr, priv->port, err);
1202 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1203 kfree(entry);
1204 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1205 break;
1206 } else {
1207 unsigned int mac_hash;
1208 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1209 ha->addr, priv->port);
1210 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1211 bucket = &priv->mac_hash[mac_hash];
1212 hlist_add_head_rcu(&entry->hlist, bucket);
1213 }
1214 }
1215 }
1216
1217 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1218 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1219 priv->port);
1220 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1221 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1222 priv->port);
1223 }
1224}
1225
0eb74fdd
YB		 1226static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1227{
1228 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1229 rx_mode_task);
1230 struct mlx4_en_dev *mdev = priv->mdev;
1231 struct net_device *dev = priv->dev;
1232
1233 mutex_lock(&mdev->state_lock);
1234 if (!mdev->device_up) {
1235 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1236 goto out;
1237 }
1238 if (!priv->port_up) {
1239 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1240 goto out;
1241 }
1242
1243 if (!netif_carrier_ok(dev)) {
1244 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1245 if (priv->port_state.link_state) {
1246 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1247 netif_carrier_on(dev);
1248 en_dbg(LINK, priv, "Link Up\n");
1249 }
1250 }
1251 }
1252
cc5387f7
YB		 1253 if (dev->priv_flags & IFF_UNICAST_FLT)
1254 mlx4_en_do_uc_filter(priv, dev, mdev);
1255
0eb74fdd 1256 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1257 if ((dev->flags & IFF_PROMISC) ||
1258 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1259 mlx4_en_set_promisc_mode(priv, mdev);
1260 goto out;
1261 }
1262
1263 /* Not in promiscuous mode */
1264 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1265 mlx4_en_clear_promisc_mode(priv, mdev);
1266
1267 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1268out:
1269 mutex_unlock(&mdev->state_lock);
1270}
1271
1272#ifdef CONFIG_NET_POLL_CONTROLLER
1273static void mlx4_en_netpoll(struct net_device *dev)
1274{
1275 struct mlx4_en_priv *priv = netdev_priv(dev);
1276 struct mlx4_en_cq *cq;
c27a02cd
YP		 1277 int i;
1278
1279 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1280 cq = priv->rx_cq[i];
c98235cb 1281 napi_schedule(&cq->napi);
c27a02cd
YP		 1282 }
1283}
1284#endif
1285
1286static void mlx4_en_tx_timeout(struct net_device *dev)
1287{
1288 struct mlx4_en_priv *priv = netdev_priv(dev);
1289 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1290 int i;
c27a02cd
YP		 1291
1292 if (netif_msg_timer(priv))
453a6082 1293 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1294
b944ebec
YP		 1295 for (i = 0; i < priv->tx_ring_num; i++) {
1296 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1297 continue;
1298 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
41d942d5
EE		 1299 i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn,
1300 priv->tx_ring[i]->cons, priv->tx_ring[i]->prod);
b944ebec
YP		 1301 }
1302
1e338db5 1303 priv->port_stats.tx_timeout++;
453a6082 1304 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1305 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1306}
1307
1308
1309static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev)
1310{
1311 struct mlx4_en_priv *priv = netdev_priv(dev);
1312
1313 spin_lock_bh(&priv->stats_lock);
1314 memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats));
1315 spin_unlock_bh(&priv->stats_lock);
1316
1317 return &priv->ret_stats;
1318}
1319
1320static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1321{
c27a02cd
YP		 1322 struct mlx4_en_cq *cq;
1323 int i;
1324
1325 /* If we haven't received a specific coalescing setting
98a1708d 1326 * (module param), we set the moderation parameters as follows:
c27a02cd 1327 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1328 * satisfy our coalescing target.
c27a02cd
YP		 1329 * - moder_time is set to a fixed value.
1330 */
3db36fb2 1331 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1332 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1333 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1334 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1335 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1336 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1337
1338 /* Setup cq moderation params */
1339 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1340 cq = priv->rx_cq[i];
c27a02cd
YP		 1341 cq->moder_cnt = priv->rx_frames;
1342 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1343 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1344 priv->last_moder_packets[i] = 0;
1345 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1346 }
1347
1348 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1349 cq = priv->tx_cq[i];
a19a848a
YP		 1350 cq->moder_cnt = priv->tx_frames;
1351 cq->moder_time = priv->tx_usecs;
c27a02cd
YP		 1352 }
1353
1354 /* Reset auto-moderation params */
1355 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1356 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1357 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1358 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1359 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1360 priv->adaptive_rx_coal = 1;
c27a02cd 1361 priv->last_moder_jiffies = 0;
c27a02cd 1362 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1363}
1364
1365static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1366{
1367 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1368 struct mlx4_en_cq *cq;
1369 unsigned long packets;
1370 unsigned long rate;
1371 unsigned long avg_pkt_size;
1372 unsigned long rx_packets;
1373 unsigned long rx_bytes;
c27a02cd
YP		 1374 unsigned long rx_pkt_diff;
1375 int moder_time;
6b4d8d9f 1376 int ring, err;
c27a02cd
YP		 1377
1378 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1379 return;
1380
6b4d8d9f
AG		 1381 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1382 spin_lock_bh(&priv->stats_lock);
41d942d5
EE		 1383 rx_packets = priv->rx_ring[ring]->packets;
1384 rx_bytes = priv->rx_ring[ring]->bytes;
6b4d8d9f
AG		 1385 spin_unlock_bh(&priv->stats_lock);
1386
1387 rx_pkt_diff = ((unsigned long) (rx_packets -
1388 priv->last_moder_packets[ring]));
1389 packets = rx_pkt_diff;
1390 rate = packets * HZ / period;
1391 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1392 priv->last_moder_bytes[ring])) / packets : 0;
1393
1394 /* Apply auto-moderation only when packet rate
1395 * exceeds a rate that it matters */
1396 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1397 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1398 if (rate < priv->pkt_rate_low)
1399 moder_time = priv->rx_usecs_low;
1400 else if (rate > priv->pkt_rate_high)
1401 moder_time = priv->rx_usecs_high;
1402 else
1403 moder_time = (rate - priv->pkt_rate_low) *
1404 (priv->rx_usecs_high - priv->rx_usecs_low) /
1405 (priv->pkt_rate_high - priv->pkt_rate_low) +
1406 priv->rx_usecs_low;
6b4d8d9f
AG		 1407 } else {
1408 moder_time = priv->rx_usecs_low;
c27a02cd 1409 }
c27a02cd 1410
6b4d8d9f
AG		 1411 if (moder_time != priv->last_moder_time[ring]) {
1412 priv->last_moder_time[ring] = moder_time;
41d942d5 1413 cq = priv->rx_cq[ring];
c27a02cd 1414 cq->moder_time = moder_time;
a1c6693a 1415 cq->moder_cnt = priv->rx_frames;
c27a02cd 1416 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1417 if (err)
48e551ff
YB		 1418 en_err(priv, "Failed modifying moderation for cq:%d\n",
1419 ring);
c27a02cd 1420 }
6b4d8d9f
AG		 1421 priv->last_moder_packets[ring] = rx_packets;
1422 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1423 }
1424
c27a02cd
YP		 1425 priv->last_moder_jiffies = jiffies;
1426}
1427
1428static void mlx4_en_do_get_stats(struct work_struct *work)
1429{
bf6aede7 1430 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1431 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1432 stats_task);
1433 struct mlx4_en_dev *mdev = priv->mdev;
1434 int err;
1435
c27a02cd
YP		 1436 mutex_lock(&mdev->state_lock);
1437 if (mdev->device_up) {
6123db2e
JM		 1438 if (priv->port_up) {
1439 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1440 if (err)
1441 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1442
c27a02cd 1443 mlx4_en_auto_moderation(priv);
6123db2e 1444 }
c27a02cd
YP		 1445
1446 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1447 }
d7e1a487 1448 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
2695bab2 1449 mlx4_en_do_set_mac(priv, priv->current_mac);
d7e1a487
YP		 1450 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1451 }
c27a02cd
YP		 1452 mutex_unlock(&mdev->state_lock);
1453}
1454
b6c39bfc
AV		 1455/* mlx4_en_service_task - Run service task for tasks that needed to be done
1456 * periodically
1457 */
1458static void mlx4_en_service_task(struct work_struct *work)
1459{
1460 struct delayed_work *delay = to_delayed_work(work);
1461 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1462 service_task);
1463 struct mlx4_en_dev *mdev = priv->mdev;
1464
1465 mutex_lock(&mdev->state_lock);
1466 if (mdev->device_up) {
dc8142ea
AV		 1467 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1468 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc
AV		 1469
1470 queue_delayed_work(mdev->workqueue, &priv->service_task,
1471 SERVICE_TASK_DELAY);
1472 }
1473 mutex_unlock(&mdev->state_lock);
1474}
1475
c27a02cd
YP		 1476static void mlx4_en_linkstate(struct work_struct *work)
1477{
1478 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1479 linkstate_task);
1480 struct mlx4_en_dev *mdev = priv->mdev;
1481 int linkstate = priv->link_state;
1482
1483 mutex_lock(&mdev->state_lock);
1484 /* If observable port state changed set carrier state and
1485 * report to system log */
1486 if (priv->last_link_state != linkstate) {
1487 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1488 en_info(priv, "Link Down\n");
c27a02cd
YP		 1489 netif_carrier_off(priv->dev);
1490 } else {
e5cc44b2 1491 en_info(priv, "Link Up\n");
c27a02cd
YP		 1492 netif_carrier_on(priv->dev);
1493 }
1494 }
1495 priv->last_link_state = linkstate;
1496 mutex_unlock(&mdev->state_lock);
1497}
1498
9e311e77
YA		 1499static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1500{
1501 struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx];
1502 int numa_node = priv->mdev->dev->numa_node;
1503 int ret = 0;
1504
1505 if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL))
1506 return -ENOMEM;
1507
1508 ret = cpumask_set_cpu_local_first(ring_idx, numa_node,
1509 ring->affinity_mask);
1510 if (ret)
1511 free_cpumask_var(ring->affinity_mask);
1512
1513 return ret;
1514}
1515
1516static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1517{
1518 free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask);
1519}
c27a02cd 1520
18cc42a3 1521int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1522{
1523 struct mlx4_en_priv *priv = netdev_priv(dev);
1524 struct mlx4_en_dev *mdev = priv->mdev;
1525 struct mlx4_en_cq *cq;
1526 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP		 1527 int rx_index = 0;
1528 int tx_index = 0;
c27a02cd
YP		 1529 int err = 0;
1530 int i;
1531 int j;
1679200f 1532 u8 mc_list[16] = {0};
c27a02cd
YP		 1533
1534 if (priv->port_up) {
453a6082 1535 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1536 return 0;
1537 }
1538
6d199937
YP		 1539 INIT_LIST_HEAD(&priv->mc_list);
1540 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1541 INIT_LIST_HEAD(&priv->ethtool_list);
1542 memset(&priv->ethtool_rules[0], 0,
1543 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1544
c27a02cd
YP		 1545 /* Calculate Rx buf size */
1546 dev->mtu = min(dev->mtu, priv->max_mtu);
1547 mlx4_en_calc_rx_buf(dev);
453a6082 1548 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1549
c27a02cd 1550 /* Configure rx cq's and rings */
38aab07c
YP		 1551 err = mlx4_en_activate_rx_rings(priv);
1552 if (err) {
453a6082 1553 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1554 return err;
1555 }
c27a02cd 1556 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1557 cq = priv->rx_cq[i];
c27a02cd 1558
9e77a2b8
AV		 1559 mlx4_en_cq_init_lock(cq);
1560
9e311e77
YA		 1561 err = mlx4_en_init_affinity_hint(priv, i);
1562 if (err) {
1563 en_err(priv, "Failed preparing IRQ affinity hint\n");
1564 goto cq_err;
1565 }
1566
76532d0c 1567 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1568 if (err) {
453a6082 1569 en_err(priv, "Failed activating Rx CQ\n");
9e311e77 1570 mlx4_en_free_affinity_hint(priv, i);
a4233304 1571 goto cq_err;
c27a02cd 1572 }
c3f2511f
IS		 1573
1574 for (j = 0; j < cq->size; j++) {
1575 struct mlx4_cqe *cqe = NULL;
1576
1577 cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) +
1578 priv->cqe_factor;
1579 cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1580 }
1581
c27a02cd
YP		 1582 err = mlx4_en_set_cq_moder(priv, cq);
1583 if (err) {
1a91de28 1584 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd 1585 mlx4_en_deactivate_cq(priv, cq);
9e311e77 1586 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1587 goto cq_err;
1588 }
1589 mlx4_en_arm_cq(priv, cq);
41d942d5 1590 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1591 ++rx_index;
1592 }
1593
ffe455ad
EE		 1594 /* Set qp number */
1595 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1596 err = mlx4_en_get_qp(priv);
1679200f 1597 if (err) {
ffe455ad 1598 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1599 goto cq_err;
1600 }
1601 mdev->mac_removed[priv->port] = 0;
1602
c27a02cd
YP		 1603 err = mlx4_en_config_rss_steer(priv);
1604 if (err) {
453a6082 1605 en_err(priv, "Failed configuring rss steering\n");
1679200f 1606 goto mac_err;
c27a02cd
YP		 1607 }
1608
cabdc8ee
HHZ		 1609 err = mlx4_en_create_drop_qp(priv);
1610 if (err)
1611 goto rss_err;
1612
c27a02cd
YP		 1613 /* Configure tx cq's and rings */
1614 for (i = 0; i < priv->tx_ring_num; i++) {
1615 /* Configure cq */
41d942d5 1616 cq = priv->tx_cq[i];
76532d0c 1617 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1618 if (err) {
453a6082 1619 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP		 1620 goto tx_err;
1621 }
1622 err = mlx4_en_set_cq_moder(priv, cq);
1623 if (err) {
1a91de28 1624 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd
YP		 1625 mlx4_en_deactivate_cq(priv, cq);
1626 goto tx_err;
1627 }
453a6082 1628 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP		 1629 cq->buf->wqe_index = cpu_to_be16(0xffff);
1630
1631 /* Configure ring */
41d942d5 1632 tx_ring = priv->tx_ring[i];
0e98b523 1633 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1634 i / priv->num_tx_rings_p_up);
c27a02cd 1635 if (err) {
453a6082 1636 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP		 1637 mlx4_en_deactivate_cq(priv, cq);
1638 goto tx_err;
1639 }
5b263f53 1640 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP		 1641
1642 /* Arm CQ for TX completions */
1643 mlx4_en_arm_cq(priv, cq);
1644
c27a02cd
YP		 1645 /* Set initial ownership of all Tx TXBBs to SW (1) */
1646 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1647 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1648 ++tx_index;
1649 }
1650
1651 /* Configure port */
1652 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1653 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1654 priv->prof->tx_pause,
1655 priv->prof->tx_ppp,
1656 priv->prof->rx_pause,
1657 priv->prof->rx_ppp);
c27a02cd 1658 if (err) {
48e551ff
YB		 1659 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1660 priv->port, err);
c27a02cd
YP		 1661 goto tx_err;
1662 }
1663 /* Set default qp number */
1664 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1665 if (err) {
453a6082 1666 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1667 goto tx_err;
1668 }
c27a02cd 1669
837052d0 1670 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 1671 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 1672 if (err) {
1673 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1674 err);
1675 goto tx_err;
1676 }
1677 }
1678
c27a02cd 1679 /* Init port */
453a6082 1680 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1681 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1682 if (err) {
453a6082 1683 en_err(priv, "Failed Initializing port\n");
1679200f 1684 goto tx_err;
c27a02cd
YP		 1685 }
1686
1679200f 1687 /* Attach rx QP to bradcast address */
c7bf7169 1688 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1689 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1690 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1691 priv->port, 0, MLX4_PROT_ETH,
1692 &priv->broadcast_id))
1679200f
YP		 1693 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1694
b5845f98
HX		 1695 /* Must redo promiscuous mode setup. */
1696 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1697
c27a02cd 1698 /* Schedule multicast task to populate multicast list */
0eb74fdd 1699 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1700
a66132f3 1701#ifdef CONFIG_MLX4_EN_VXLAN
9737c6ab 1702 if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1 1703 vxlan_get_rx_port(dev);
a66132f3 1704#endif
c27a02cd 1705 priv->port_up = true;
a11faac7 1706 netif_tx_start_all_queues(dev);
3484aac1
AV		 1707 netif_device_attach(dev);
1708
c27a02cd
YP		 1709 return 0;
1710
c27a02cd
YP		 1711tx_err:
1712 while (tx_index--) {
41d942d5
EE		 1713 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]);
1714 mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]);
c27a02cd 1715 }
cabdc8ee
HHZ		 1716 mlx4_en_destroy_drop_qp(priv);
1717rss_err:
c27a02cd 1718 mlx4_en_release_rss_steer(priv);
1679200f 1719mac_err:
16a10ffd 1720 mlx4_en_put_qp(priv);
c27a02cd 1721cq_err:
9e311e77 1722 while (rx_index--) {
41d942d5 1723 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
9e311e77
YA		 1724 mlx4_en_free_affinity_hint(priv, i);
1725 }
38aab07c 1726 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1727 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1728
1729 return err; /* need to close devices */
1730}
1731
1732
3484aac1 1733void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1734{
1735 struct mlx4_en_priv *priv = netdev_priv(dev);
1736 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1737 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1738 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1739 int i;
1679200f 1740 u8 mc_list[16] = {0};
c27a02cd
YP		 1741
1742 if (!priv->port_up) {
453a6082 1743 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1744 return;
1745 }
c27a02cd 1746
0cc5c8bf
EE		 1747 /* close port*/
1748 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1749
c27a02cd
YP		 1750 /* Synchronize with tx routine */
1751 netif_tx_lock_bh(dev);
3484aac1
AV		 1752 if (detach)
1753 netif_device_detach(dev);
3c05f5ef 1754 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1755 netif_tx_unlock_bh(dev);
1756
3484aac1
AV		 1757 netif_tx_disable(dev);
1758
7c287380 1759 /* Set port as not active */
3c05f5ef 1760 priv->port_up = false;
c27a02cd 1761
db0e7cba
AY		 1762 /* Promsicuous mode */
1763 if (mdev->dev->caps.steering_mode ==
1764 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1765 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1766 MLX4_EN_FLAG_MC_PROMISC);
1767 mlx4_flow_steer_promisc_remove(mdev->dev,
1768 priv->port,
f9162539 1769 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1770 mlx4_flow_steer_promisc_remove(mdev->dev,
1771 priv->port,
f9162539 1772 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1773 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1774 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1775
1776 /* Disable promiscouos mode */
1777 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1778 priv->port);
1779
1780 /* Disable Multicast promisc */
1781 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1782 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1783 priv->port);
1784 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1785 }
1786 }
1787
1679200f 1788 /* Detach All multicasts */
c7bf7169 1789 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1790 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1791 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1792 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1793 list_for_each_entry(mclist, &priv->curr_list, list) {
1794 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1795 mc_list[5] = priv->port;
1796 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1797 mc_list, MLX4_PROT_ETH, mclist->reg_id);
de123268
OG		 1798 if (mclist->tunnel_reg_id)
1799 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1679200f
YP		 1800 }
1801 mlx4_en_clear_list(dev);
6d199937
YP		 1802 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1803 list_del(&mclist->list);
1804 kfree(mclist);
1805 }
1806
1679200f
YP		 1807 /* Flush multicast filter */
1808 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1809
6efb5fac
HHZ		 1810 /* Remove flow steering rules for the port*/
1811 if (mdev->dev->caps.steering_mode ==
1812 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1813 ASSERT_RTNL();
1814 list_for_each_entry_safe(flow, tmp_flow,
1815 &priv->ethtool_list, list) {
1816 mlx4_flow_detach(mdev->dev, flow->id);
1817 list_del(&flow->list);
1818 }
1819 }
1820
cabdc8ee
HHZ		 1821 mlx4_en_destroy_drop_qp(priv);
1822
c27a02cd
YP		 1823 /* Free TX Rings */
1824 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1825 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]);
1826 mlx4_en_deactivate_cq(priv, priv->tx_cq[i]);
c27a02cd
YP		 1827 }
1828 msleep(10);
1829
1830 for (i = 0; i < priv->tx_ring_num; i++)
41d942d5 1831 mlx4_en_free_tx_buf(dev, priv->tx_ring[i]);
c27a02cd
YP		 1832
1833 /* Free RSS qps */
1834 mlx4_en_release_rss_steer(priv);
1835
ffe455ad 1836 /* Unregister Mac address for the port */
16a10ffd 1837 mlx4_en_put_qp(priv);
5930e8d0 1838 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1839 mdev->mac_removed[priv->port] = 1;
ffe455ad 1840
c27a02cd
YP		 1841 /* Free RX Rings */
1842 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1843 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8
AV		 1844
1845 local_bh_disable();
1846 while (!mlx4_en_cq_lock_napi(cq)) {
1847 pr_info("CQ %d locked\n", i);
1848 mdelay(1);
1849 }
1850 local_bh_enable();
1851
f4a36751 1852 napi_synchronize(&cq->napi);
41d942d5 1853 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1854 mlx4_en_deactivate_cq(priv, cq);
9e311e77
YA		 1855
1856 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1857 }
1858}
1859
1860static void mlx4_en_restart(struct work_struct *work)
1861{
1862 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1863 watchdog_task);
1864 struct mlx4_en_dev *mdev = priv->mdev;
1865 struct net_device *dev = priv->dev;
1866
453a6082 1867 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5
YP		 1868
1869 mutex_lock(&mdev->state_lock);
1870 if (priv->port_up) {
3484aac1 1871 mlx4_en_stop_port(dev, 1);
1e338db5 1872 if (mlx4_en_start_port(dev))
453a6082 1873 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1874 }
1875 mutex_unlock(&mdev->state_lock);
c27a02cd
YP		 1876}
1877
b477ba62 1878static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1879{
1880 struct mlx4_en_priv *priv = netdev_priv(dev);
1881 struct mlx4_en_dev *mdev = priv->mdev;
1882 int i;
c27a02cd 1883
c27a02cd 1884 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1885 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd
YP		 1886
1887 memset(&priv->stats, 0, sizeof(priv->stats));
1888 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1889 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1890 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
0b131561
MB		 1891 memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats));
1892 memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats));
1893 memset(&priv->rx_priority_flowstats, 0,
1894 sizeof(priv->rx_priority_flowstats));
1895 memset(&priv->tx_priority_flowstats, 0,
1896 sizeof(priv->tx_priority_flowstats));
c27a02cd
YP		 1897
1898 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1899 priv->tx_ring[i]->bytes = 0;
1900 priv->tx_ring[i]->packets = 0;
1901 priv->tx_ring[i]->tx_csum = 0;
c27a02cd
YP		 1902 }
1903 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1904 priv->rx_ring[i]->bytes = 0;
1905 priv->rx_ring[i]->packets = 0;
1906 priv->rx_ring[i]->csum_ok = 0;
1907 priv->rx_ring[i]->csum_none = 0;
f8c6455b 1908 priv->rx_ring[i]->csum_complete = 0;
c27a02cd 1909 }
b477ba62
EE		 1910}
1911
1912static int mlx4_en_open(struct net_device *dev)
1913{
1914 struct mlx4_en_priv *priv = netdev_priv(dev);
1915 struct mlx4_en_dev *mdev = priv->mdev;
1916 int err = 0;
1917
1918 mutex_lock(&mdev->state_lock);
1919
1920 if (!mdev->device_up) {
1921 en_err(priv, "Cannot open - device down/disabled\n");
1922 err = -EBUSY;
1923 goto out;
1924 }
1925
1926 /* Reset HW statistics and SW counters */
1927 mlx4_en_clear_stats(dev);
c27a02cd 1928
c27a02cd
YP		 1929 err = mlx4_en_start_port(dev);
1930 if (err)
453a6082 1931 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1932
1933out:
1934 mutex_unlock(&mdev->state_lock);
1935 return err;
1936}
1937
1938
1939static int mlx4_en_close(struct net_device *dev)
1940{
1941 struct mlx4_en_priv *priv = netdev_priv(dev);
1942 struct mlx4_en_dev *mdev = priv->mdev;
1943
453a6082 1944 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 1945
1946 mutex_lock(&mdev->state_lock);
1947
3484aac1 1948 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 1949 netif_carrier_off(dev);
1950
1951 mutex_unlock(&mdev->state_lock);
1952 return 0;
1953}
1954
fe0af03c 1955void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP		 1956{
1957 int i;
1958
1eb8c695
AV		 1959#ifdef CONFIG_RFS_ACCEL
1960 free_irq_cpu_rmap(priv->dev->rx_cpu_rmap);
1961 priv->dev->rx_cpu_rmap = NULL;
1962#endif
1963
c27a02cd 1964 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1965 if (priv->tx_ring && priv->tx_ring[i])
c27a02cd 1966 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
41d942d5 1967 if (priv->tx_cq && priv->tx_cq[i])
fe0af03c 1968 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP		 1969 }
1970
1971 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1972 if (priv->rx_ring[i])
68355f71
TLSC		 1973 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1974 priv->prof->rx_ring_size, priv->stride);
41d942d5 1975 if (priv->rx_cq[i])
fe0af03c 1976 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1977 }
044ca2a5
YP		 1978
1979 if (priv->base_tx_qpn) {
1980 mlx4_qp_release_range(priv->mdev->dev, priv->base_tx_qpn, priv->tx_ring_num);
1981 priv->base_tx_qpn = 0;
1982 }
c27a02cd
YP		 1983}
1984
18cc42a3 1985int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1986{
c27a02cd
YP		 1987 struct mlx4_en_port_profile *prof = priv->prof;
1988 int i;
163561a4 1989 int node;
87a5c389 1990
c27a02cd
YP		 1991 /* Create tx Rings */
1992 for (i = 0; i < priv->tx_ring_num; i++) {
163561a4 1993 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1994 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
163561a4 1995 prof->tx_ring_size, i, TX, node))
c27a02cd
YP		 1996 goto err;
1997
d03a68f8 1998 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i],
d03a68f8
IS		 1999 prof->tx_ring_size, TXBB_SIZE,
2000 node, i))
c27a02cd
YP		 2001 goto err;
2002 }
2003
2004 /* Create rx Rings */
2005 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 2006 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2007 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2008 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2009 goto err;
2010
2011 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 2012 prof->rx_ring_size, priv->stride,
2013 node))
c27a02cd
YP		 2014 goto err;
2015 }
2016
1eb8c695 2017#ifdef CONFIG_RFS_ACCEL
a229e488
AV		 2018 if (priv->mdev->dev->caps.comp_pool) {
2019 priv->dev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->mdev->dev->caps.comp_pool);
2020 if (!priv->dev->rx_cpu_rmap)
2021 goto err;
2022 }
1eb8c695
AV		 2023#endif
2024
c27a02cd
YP		 2025 return 0;
2026
2027err:
453a6082 2028 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2029 for (i = 0; i < priv->rx_ring_num; i++) {
2030 if (priv->rx_ring[i])
2031 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2032 prof->rx_ring_size,
2033 priv->stride);
2034 if (priv->rx_cq[i])
2035 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2036 }
2037 for (i = 0; i < priv->tx_ring_num; i++) {
2038 if (priv->tx_ring[i])
2039 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
2040 if (priv->tx_cq[i])
2041 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
2042 }
c27a02cd
YP		 2043 return -ENOMEM;
2044}
2045
2046
2047void mlx4_en_destroy_netdev(struct net_device *dev)
2048{
2049 struct mlx4_en_priv *priv = netdev_priv(dev);
2050 struct mlx4_en_dev *mdev = priv->mdev;
2051
453a6082 2052 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2053
2054 /* Unregister device - this will close the port if it was up */
2055 if (priv->registered)
2056 unregister_netdev(dev);
2057
2058 if (priv->allocated)
2059 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2060
2061 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2062 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2063 /* flush any pending task for this netdev */
2064 flush_workqueue(mdev->workqueue);
2065
2066 /* Detach the netdev so tasks would not attempt to access it */
2067 mutex_lock(&mdev->state_lock);
2068 mdev->pndev[priv->port] = NULL;
5da03547 2069 mdev->upper[priv->port] = NULL;
c27a02cd
YP		 2070 mutex_unlock(&mdev->state_lock);
2071
fe0af03c 2072 mlx4_en_free_resources(priv);
564c274c 2073
bc6a4744
AV		 2074 kfree(priv->tx_ring);
2075 kfree(priv->tx_cq);
2076
c27a02cd
YP		 2077 free_netdev(dev);
2078}
2079
2080static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2081{
2082 struct mlx4_en_priv *priv = netdev_priv(dev);
2083 struct mlx4_en_dev *mdev = priv->mdev;
2084 int err = 0;
2085
453a6082 2086 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2087 dev->mtu, new_mtu);
2088
2089 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 2090 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP		 2091 return -EPERM;
2092 }
2093 dev->mtu = new_mtu;
2094
2095 if (netif_running(dev)) {
2096 mutex_lock(&mdev->state_lock);
2097 if (!mdev->device_up) {
2098 /* NIC is probably restarting - let watchdog task reset
2099 * the port */
453a6082 2100 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2101 } else {
3484aac1 2102 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2103 err = mlx4_en_start_port(dev);
2104 if (err) {
453a6082 2105 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2106 priv->port);
2107 queue_work(mdev->workqueue, &priv->watchdog_task);
2108 }
2109 }
2110 mutex_unlock(&mdev->state_lock);
2111 }
2112 return 0;
2113}
2114
100dbda8 2115static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2116{
2117 struct mlx4_en_priv *priv = netdev_priv(dev);
2118 struct mlx4_en_dev *mdev = priv->mdev;
2119 struct hwtstamp_config config;
2120
2121 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2122 return -EFAULT;
2123
2124 /* reserved for future extensions */
2125 if (config.flags)
2126 return -EINVAL;
2127
2128 /* device doesn't support time stamping */
2129 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2130 return -EINVAL;
2131
2132 /* TX HW timestamp */
2133 switch (config.tx_type) {
2134 case HWTSTAMP_TX_OFF:
2135 case HWTSTAMP_TX_ON:
2136 break;
2137 default:
2138 return -ERANGE;
2139 }
2140
2141 /* RX HW timestamp */
2142 switch (config.rx_filter) {
2143 case HWTSTAMP_FILTER_NONE:
2144 break;
2145 case HWTSTAMP_FILTER_ALL:
2146 case HWTSTAMP_FILTER_SOME:
2147 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2148 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2149 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2150 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2151 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2152 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2153 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2154 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2155 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2156 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2157 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2158 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2159 config.rx_filter = HWTSTAMP_FILTER_ALL;
2160 break;
2161 default:
2162 return -ERANGE;
2163 }
2164
7787fa66 2165 if (mlx4_en_reset_config(dev, config, dev->features)) {
ec693d47
AV		 2166 config.tx_type = HWTSTAMP_TX_OFF;
2167 config.rx_filter = HWTSTAMP_FILTER_NONE;
2168 }
2169
2170 return copy_to_user(ifr->ifr_data, &config,
2171 sizeof(config)) ? -EFAULT : 0;
2172}
2173
100dbda8
BH		 2174static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2175{
2176 struct mlx4_en_priv *priv = netdev_priv(dev);
2177
2178 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2179 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2180}
2181
ec693d47
AV		 2182static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2183{
2184 switch (cmd) {
2185 case SIOCSHWTSTAMP:
100dbda8
BH		 2186 return mlx4_en_hwtstamp_set(dev, ifr);
2187 case SIOCGHWTSTAMP:
2188 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2189 default:
2190 return -EOPNOTSUPP;
2191 }
2192}
2193
60d6fe99
AV		 2194static int mlx4_en_set_features(struct net_device *netdev,
2195 netdev_features_t features)
2196{
2197 struct mlx4_en_priv *priv = netdev_priv(netdev);
537f6f95
SM		 2198 int ret = 0;
2199
2200 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2201 en_info(priv, "Turn %s RX vlan strip offload\n",
2202 (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF");
2203 ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config,
2204 features);
2205 if (ret)
2206 return ret;
2207 }
60d6fe99 2208
cfb53f36
IS		 2209 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX))
2210 en_info(priv, "Turn %s TX vlan strip offload\n",
2211 (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF");
2212
241a08c3
IS		 2213 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) {
2214 en_info(priv, "Turn %s loopback\n",
2215 (features & NETIF_F_LOOPBACK) ? "ON" : "OFF");
2216 mlx4_en_update_loopback_state(netdev, features);
2217 }
79aeaccd 2218
60d6fe99
AV		 2219 return 0;
2220
2221}
2222
8f7ba3ca
RE		 2223static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2224{
2225 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2226 struct mlx4_en_dev *mdev = en_priv->mdev;
9813337a 2227 u64 mac_u64 = mlx4_mac_to_u64(mac);
8f7ba3ca
RE		 2228
2229 if (!is_valid_ether_addr(mac))
2230 return -EINVAL;
2231
2232 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2233}
2234
3f7fb021
RE		 2235static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2236{
2237 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2238 struct mlx4_en_dev *mdev = en_priv->mdev;
2239
2240 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2241}
2242
cda373f4
IS		 2243static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2244 int max_tx_rate)
2245{
2246 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2247 struct mlx4_en_dev *mdev = en_priv->mdev;
2248
2249 return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate,
2250 max_tx_rate);
2251}
2252
e6b6a231
RE		 2253static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2254{
2255 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2256 struct mlx4_en_dev *mdev = en_priv->mdev;
2257
2258 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2259}
2260
2cccb9e4
RE		 2261static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2262{
2263 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2264 struct mlx4_en_dev *mdev = en_priv->mdev;
2265
2266 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2267}
8f7ba3ca 2268
948e306d
RE		 2269static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2270{
2271 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2272 struct mlx4_en_dev *mdev = en_priv->mdev;
2273
2274 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2275}
84c86403
HHZ		 2276
2277#define PORT_ID_BYTE_LEN 8
2278static int mlx4_en_get_phys_port_id(struct net_device *dev,
02637fce 2279 struct netdev_phys_item_id *ppid)
84c86403
HHZ		 2280{
2281 struct mlx4_en_priv *priv = netdev_priv(dev);
2282 struct mlx4_dev *mdev = priv->mdev->dev;
2283 int i;
2284 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2285
2286 if (!phys_port_id)
2287 return -EOPNOTSUPP;
2288
2289 ppid->id_len = sizeof(phys_port_id);
2290 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2291 ppid->id[i] = phys_port_id & 0xff;
2292 phys_port_id >>= 8;
2293 }
2294 return 0;
2295}
2296
a66132f3 2297#ifdef CONFIG_MLX4_EN_VXLAN
1b136de1
OG		 2298static void mlx4_en_add_vxlan_offloads(struct work_struct *work)
2299{
2300 int ret;
2301 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2302 vxlan_add_task);
2303
2304 ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port);
2305 if (ret)
2306 goto out;
2307
2308 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2309 VXLAN_STEER_BY_OUTER_MAC, 1);
2310out:
f4a1edd5 2311 if (ret) {
1b136de1 2312 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
f4a1edd5
OG		 2313 return;
2314 }
2315
2316 /* set offloads */
2317 priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2318 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL;
2319 priv->dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2320 priv->dev->features |= NETIF_F_GSO_UDP_TUNNEL;
1b136de1
OG		 2321}
2322
2323static void mlx4_en_del_vxlan_offloads(struct work_struct *work)
2324{
2325 int ret;
2326 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2327 vxlan_del_task);
f4a1edd5
OG		 2328 /* unset offloads */
2329 priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2330 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL);
2331 priv->dev->hw_features &= ~NETIF_F_GSO_UDP_TUNNEL;
2332 priv->dev->features &= ~NETIF_F_GSO_UDP_TUNNEL;
1b136de1
OG		 2333
2334 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2335 VXLAN_STEER_BY_OUTER_MAC, 0);
2336 if (ret)
2337 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
2338
2339 priv->vxlan_port = 0;
2340}
2341
2342static void mlx4_en_add_vxlan_port(struct net_device *dev,
2343 sa_family_t sa_family, __be16 port)
2344{
2345 struct mlx4_en_priv *priv = netdev_priv(dev);
2346 __be16 current_port;
2347
e326f2f1 2348 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2349 return;
2350
2351 if (sa_family == AF_INET6)
2352 return;
2353
2354 current_port = priv->vxlan_port;
2355 if (current_port && current_port != port) {
2356 en_warn(priv, "vxlan port %d configured, can't add port %d\n",
2357 ntohs(current_port), ntohs(port));
2358 return;
2359 }
2360
2361 priv->vxlan_port = port;
2362 queue_work(priv->mdev->workqueue, &priv->vxlan_add_task);
2363}
2364
2365static void mlx4_en_del_vxlan_port(struct net_device *dev,
2366 sa_family_t sa_family, __be16 port)
2367{
2368 struct mlx4_en_priv *priv = netdev_priv(dev);
2369 __be16 current_port;
2370
2371 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
2372 return;
2373
2374 if (sa_family == AF_INET6)
2375 return;
2376
2377 current_port = priv->vxlan_port;
2378 if (current_port != port) {
2379 en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port));
2380 return;
2381 }
2382
2383 queue_work(priv->mdev->workqueue, &priv->vxlan_del_task);
2384}
956bdab2 2385
5f35227e
JG		 2386static netdev_features_t mlx4_en_features_check(struct sk_buff *skb,
2387 struct net_device *dev,
2388 netdev_features_t features)
956bdab2 2389{
8cb65d00 2390 features = vlan_features_check(skb, features);
5f35227e 2391 return vxlan_features_check(skb, features);
956bdab2 2392}
a66132f3 2393#endif
1b136de1 2394
de1cf8a7 2395static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate)
c10e4fc6
OG		 2396{
2397 struct mlx4_en_priv *priv = netdev_priv(dev);
2398 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[queue_index];
2399 struct mlx4_update_qp_params params;
2400 int err;
2401
2402 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT))
2403 return -EOPNOTSUPP;
2404
2405 /* rate provided to us in Mbs, check if it fits into 12 bits, if not use Gbs */
2406 if (maxrate >> 12) {
2407 params.rate_unit = MLX4_QP_RATE_LIMIT_GBS;
2408 params.rate_val = maxrate / 1000;
2409 } else if (maxrate) {
2410 params.rate_unit = MLX4_QP_RATE_LIMIT_MBS;
2411 params.rate_val = maxrate;
2412 } else { /* zero serves to revoke the QP rate-limitation */
2413 params.rate_unit = 0;
2414 params.rate_val = 0;
2415 }
2416
2417 err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT,
2418 &params);
2419 return err;
2420}
2421
3addc568
SH		 2422static const struct net_device_ops mlx4_netdev_ops = {
2423 .ndo_open = mlx4_en_open,
2424 .ndo_stop = mlx4_en_close,
2425 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2426 .ndo_select_queue = mlx4_en_select_queue,
3addc568 2427 .ndo_get_stats = mlx4_en_get_stats,
0eb74fdd 2428 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2429 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2430 .ndo_validate_addr = eth_validate_addr,
3addc568 2431 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2432 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2433 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2434 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2435 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2436#ifdef CONFIG_NET_POLL_CONTROLLER
2437 .ndo_poll_controller = mlx4_en_netpoll,
2438#endif
60d6fe99 2439 .ndo_set_features = mlx4_en_set_features,
897d7846 2440 .ndo_setup_tc = mlx4_en_setup_tc,
1eb8c695
AV		 2441#ifdef CONFIG_RFS_ACCEL
2442 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2443#endif
e0d1095a 2444#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 2445 .ndo_busy_poll = mlx4_en_low_latency_recv,
9e77a2b8 2446#endif
84c86403 2447 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a66132f3 2448#ifdef CONFIG_MLX4_EN_VXLAN
1b136de1
OG		 2449 .ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
2450 .ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
5f35227e 2451 .ndo_features_check = mlx4_en_features_check,
a66132f3 2452#endif
c10e4fc6 2453 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
3addc568
SH		 2454};
2455
8f7ba3ca
RE		 2456static const struct net_device_ops mlx4_netdev_ops_master = {
2457 .ndo_open = mlx4_en_open,
2458 .ndo_stop = mlx4_en_close,
2459 .ndo_start_xmit = mlx4_en_xmit,
2460 .ndo_select_queue = mlx4_en_select_queue,
2461 .ndo_get_stats = mlx4_en_get_stats,
2462 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2463 .ndo_set_mac_address = mlx4_en_set_mac,
2464 .ndo_validate_addr = eth_validate_addr,
2465 .ndo_change_mtu = mlx4_en_change_mtu,
2466 .ndo_tx_timeout = mlx4_en_tx_timeout,
2467 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2468 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2469 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2470 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
cda373f4 2471 .ndo_set_vf_rate = mlx4_en_set_vf_rate,
e6b6a231 2472 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2473 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
2cccb9e4 2474 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2475#ifdef CONFIG_NET_POLL_CONTROLLER
2476 .ndo_poll_controller = mlx4_en_netpoll,
2477#endif
2478 .ndo_set_features = mlx4_en_set_features,
2479 .ndo_setup_tc = mlx4_en_setup_tc,
2480#ifdef CONFIG_RFS_ACCEL
2481 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2482#endif
84c86403 2483 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
9737c6ab
OG		 2484#ifdef CONFIG_MLX4_EN_VXLAN
2485 .ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
2486 .ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
5f35227e 2487 .ndo_features_check = mlx4_en_features_check,
9737c6ab 2488#endif
c10e4fc6 2489 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
8f7ba3ca
RE		 2490};
2491
5da03547
MS		 2492struct mlx4_en_bond {
2493 struct work_struct work;
2494 struct mlx4_en_priv *priv;
2495 int is_bonded;
2496 struct mlx4_port_map port_map;
2497};
2498
2499static void mlx4_en_bond_work(struct work_struct *work)
2500{
2501 struct mlx4_en_bond *bond = container_of(work,
2502 struct mlx4_en_bond,
2503 work);
2504 int err = 0;
2505 struct mlx4_dev *dev = bond->priv->mdev->dev;
2506
2507 if (bond->is_bonded) {
2508 if (!mlx4_is_bonded(dev)) {
2509 err = mlx4_bond(dev);
2510 if (err)
2511 en_err(bond->priv, "Fail to bond device\n");
2512 }
2513 if (!err) {
2514 err = mlx4_port_map_set(dev, &bond->port_map);
2515 if (err)
2516 en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n",
2517 bond->port_map.port1,
2518 bond->port_map.port2,
2519 err);
2520 }
2521 } else if (mlx4_is_bonded(dev)) {
2522 err = mlx4_unbond(dev);
2523 if (err)
2524 en_err(bond->priv, "Fail to unbond device\n");
2525 }
2526 dev_put(bond->priv->dev);
2527 kfree(bond);
2528}
2529
2530static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded,
2531 u8 v2p_p1, u8 v2p_p2)
2532{
2533 struct mlx4_en_bond *bond = NULL;
2534
2535 bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
2536 if (!bond)
2537 return -ENOMEM;
2538
2539 INIT_WORK(&bond->work, mlx4_en_bond_work);
2540 bond->priv = priv;
2541 bond->is_bonded = is_bonded;
2542 bond->port_map.port1 = v2p_p1;
2543 bond->port_map.port2 = v2p_p2;
2544 dev_hold(priv->dev);
2545 queue_work(priv->mdev->workqueue, &bond->work);
2546 return 0;
2547}
2548
2549int mlx4_en_netdev_event(struct notifier_block *this,
2550 unsigned long event, void *ptr)
2551{
2552 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2553 u8 port = 0;
2554 struct mlx4_en_dev *mdev;
2555 struct mlx4_dev *dev;
2556 int i, num_eth_ports = 0;
2557 bool do_bond = true;
2558 struct mlx4_en_priv *priv;
2559 u8 v2p_port1 = 0;
2560 u8 v2p_port2 = 0;
2561
2562 if (!net_eq(dev_net(ndev), &init_net))
2563 return NOTIFY_DONE;
2564
2565 mdev = container_of(this, struct mlx4_en_dev, nb);
2566 dev = mdev->dev;
2567
2568 /* Go into this mode only when two network devices set on two ports
2569 * of the same mlx4 device are slaves of the same bonding master
2570 */
2571 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
2572 ++num_eth_ports;
2573 if (!port && (mdev->pndev[i] == ndev))
2574 port = i;
2575 mdev->upper[i] = mdev->pndev[i] ?
2576 netdev_master_upper_dev_get(mdev->pndev[i]) : NULL;
2577 /* condition not met: network device is a slave */
2578 if (!mdev->upper[i])
2579 do_bond = false;
2580 if (num_eth_ports < 2)
2581 continue;
2582 /* condition not met: same master */
2583 if (mdev->upper[i] != mdev->upper[i-1])
2584 do_bond = false;
2585 }
2586 /* condition not met: 2 salves */
2587 do_bond = (num_eth_ports == 2) ? do_bond : false;
2588
2589 /* handle only events that come with enough info */
2590 if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port)
2591 return NOTIFY_DONE;
2592
2593 priv = netdev_priv(ndev);
2594 if (do_bond) {
2595 struct netdev_notifier_bonding_info *notifier_info = ptr;
2596 struct netdev_bonding_info *bonding_info =
2597 &notifier_info->bonding_info;
2598
2599 /* required mode 1, 2 or 4 */
2600 if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) &&
2601 (bonding_info->master.bond_mode != BOND_MODE_XOR) &&
2602 (bonding_info->master.bond_mode != BOND_MODE_8023AD))
2603 do_bond = false;
2604
2605 /* require exactly 2 slaves */
2606 if (bonding_info->master.num_slaves != 2)
2607 do_bond = false;
2608
2609 /* calc v2p */
2610 if (do_bond) {
2611 if (bonding_info->master.bond_mode ==
2612 BOND_MODE_ACTIVEBACKUP) {
2613 /* in active-backup mode virtual ports are
2614 * mapped to the physical port of the active
2615 * slave */
2616 if (bonding_info->slave.state ==
2617 BOND_STATE_BACKUP) {
2618 if (port == 1) {
2619 v2p_port1 = 2;
2620 v2p_port2 = 2;
2621 } else {
2622 v2p_port1 = 1;
2623 v2p_port2 = 1;
2624 }
2625 } else { /* BOND_STATE_ACTIVE */
2626 if (port == 1) {
2627 v2p_port1 = 1;
2628 v2p_port2 = 1;
2629 } else {
2630 v2p_port1 = 2;
2631 v2p_port2 = 2;
2632 }
2633 }
2634 } else { /* Active-Active */
2635 /* in active-active mode a virtual port is
2636 * mapped to the native physical port if and only
2637 * if the physical port is up */
2638 __s8 link = bonding_info->slave.link;
2639
2640 if (port == 1)
2641 v2p_port2 = 2;
2642 else
2643 v2p_port1 = 1;
2644 if ((link == BOND_LINK_UP) ||
2645 (link == BOND_LINK_FAIL)) {
2646 if (port == 1)
2647 v2p_port1 = 1;
2648 else
2649 v2p_port2 = 2;
2650 } else { /* BOND_LINK_DOWN || BOND_LINK_BACK */
2651 if (port == 1)
2652 v2p_port1 = 2;
2653 else
2654 v2p_port2 = 1;
2655 }
2656 }
2657 }
2658 }
2659
2660 mlx4_en_queue_bond_work(priv, do_bond,
2661 v2p_port1, v2p_port2);
2662
2663 return NOTIFY_DONE;
2664}
2665
0b131561
MB		 2666void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
2667 struct mlx4_en_stats_bitmap *stats_bitmap,
2668 u8 rx_ppp, u8 rx_pause,
2669 u8 tx_ppp, u8 tx_pause)
2670{
2671 int last_i = NUM_MAIN_STATS + NUM_PORT_STATS;
2672
2673 if (!mlx4_is_slave(dev) &&
2674 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) {
2675 mutex_lock(&stats_bitmap->mutex);
2676 bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS);
2677
2678 if (rx_ppp)
2679 bitmap_set(stats_bitmap->bitmap, last_i,
2680 NUM_FLOW_PRIORITY_STATS_RX);
2681 last_i += NUM_FLOW_PRIORITY_STATS_RX;
2682
2683 if (rx_pause && !(rx_ppp))
2684 bitmap_set(stats_bitmap->bitmap, last_i,
2685 NUM_FLOW_STATS_RX);
2686 last_i += NUM_FLOW_STATS_RX;
2687
2688 if (tx_ppp)
2689 bitmap_set(stats_bitmap->bitmap, last_i,
2690 NUM_FLOW_PRIORITY_STATS_TX);
2691 last_i += NUM_FLOW_PRIORITY_STATS_TX;
2692
2693 if (tx_pause && !(tx_ppp))
2694 bitmap_set(stats_bitmap->bitmap, last_i,
2695 NUM_FLOW_STATS_TX);
2696 last_i += NUM_FLOW_STATS_TX;
2697
2698 mutex_unlock(&stats_bitmap->mutex);
2699 }
2700}
2701
6fcd2735 2702void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
0b131561
MB		 2703 struct mlx4_en_stats_bitmap *stats_bitmap,
2704 u8 rx_ppp, u8 rx_pause,
2705 u8 tx_ppp, u8 tx_pause)
ffa88f37 2706{
6fcd2735
EBE		 2707 int last_i = 0;
2708
3da8a36c
EBE		 2709 mutex_init(&stats_bitmap->mutex);
2710 bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS);
6fcd2735
EBE		 2711
2712 if (mlx4_is_slave(dev)) {
3da8a36c 2713 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2714 MLX4_FIND_NETDEV_STAT(rx_packets), 1);
3da8a36c 2715 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2716 MLX4_FIND_NETDEV_STAT(tx_packets), 1);
3da8a36c 2717 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2718 MLX4_FIND_NETDEV_STAT(rx_bytes), 1);
3da8a36c 2719 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2720 MLX4_FIND_NETDEV_STAT(tx_bytes), 1);
3da8a36c 2721 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2722 MLX4_FIND_NETDEV_STAT(rx_dropped), 1);
3da8a36c 2723 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735
EBE		 2724 MLX4_FIND_NETDEV_STAT(tx_dropped), 1);
2725 } else {
3da8a36c 2726 bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS);
ffa88f37 2727 }
6fcd2735 2728 last_i += NUM_MAIN_STATS;
ffa88f37 2729
3da8a36c 2730 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS);
6fcd2735 2731 last_i += NUM_PORT_STATS;
ffa88f37 2732
0b131561
MB		 2733 mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap,
2734 rx_ppp, rx_pause,
2735 tx_ppp, tx_pause);
2736 last_i += NUM_FLOW_STATS;
2737
6fcd2735 2738 if (!mlx4_is_slave(dev))
3da8a36c 2739 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS);
ffa88f37
EBE		 2740}
2741
c27a02cd
YP		 2742int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2743 struct mlx4_en_port_profile *prof)
2744{
2745 struct net_device *dev;
2746 struct mlx4_en_priv *priv;
c07cb4b0 2747 int i;
c27a02cd 2748 int err;
ef96f7d4 2749 u64 mac_u64;
c27a02cd 2750
f1593d22 2751 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2752 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2753 if (dev == NULL)
c27a02cd 2754 return -ENOMEM;
c27a02cd 2755
d317966b
AV		 2756 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2757 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2758
872bf2fb 2759 SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev);
76a066f2 2760 dev->dev_port = port - 1;
c27a02cd
YP		 2761
2762 /*
2763 * Initialize driver private data
2764 */
2765
2766 priv = netdev_priv(dev);
2767 memset(priv, 0, sizeof(struct mlx4_en_priv));
207af6c5
EE		 2768 spin_lock_init(&priv->stats_lock);
2769 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
2770 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2771 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2772 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
2773 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
2774#ifdef CONFIG_MLX4_EN_VXLAN
2775 INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads);
2776 INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads);
2777#endif
2778#ifdef CONFIG_RFS_ACCEL
2779 INIT_LIST_HEAD(&priv->filters);
2780 spin_lock_init(&priv->filters_lock);
2781#endif
2782
c27a02cd
YP		 2783 priv->dev = dev;
2784 priv->mdev = mdev;
ebf8c9aa 2785 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 2786 priv->prof = prof;
2787 priv->port = port;
2788 priv->port_up = false;
c27a02cd 2789 priv->flags = prof->flags;
0fef9d03 2790 priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
60d6fe99
AV		 2791 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2792 MLX4_WQE_CTRL_SOLICITED);
d317966b 2793 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2794 priv->tx_ring_num = prof->tx_ring_num;
fbc6daf1 2795 priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
bd635c35 2796 netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
d317966b 2797
41d942d5 2798 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS,
d317966b 2799 GFP_KERNEL);
bc6a4744
AV		 2800 if (!priv->tx_ring) {
2801 err = -ENOMEM;
2802 goto out;
2803 }
41d942d5 2804 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS,
d317966b 2805 GFP_KERNEL);
bc6a4744
AV		 2806 if (!priv->tx_cq) {
2807 err = -ENOMEM;
2808 goto out;
2809 }
c27a02cd 2810 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2811 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
b1b6b4da 2812 priv->cqe_size = mdev->dev->caps.cqe_size;
c27a02cd
YP		 2813 priv->mac_index = -1;
2814 priv->msg_enable = MLX4_EN_MSG_LEVEL;
564c274c 2815#ifdef CONFIG_MLX4_EN_DCB
540b3a39 2816 if (!mlx4_is_slave(priv->mdev->dev)) {
3742cc65 2817 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) {
540b3a39
OG		 2818 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2819 } else {
2820 en_info(priv, "enabling only PFC DCB ops\n");
2821 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2822 }
2823 }
564c274c 2824#endif
c27a02cd 2825
c07cb4b0
YB		 2826 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2827 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2828
c27a02cd
YP		 2829 /* Query for default mac and max mtu */
2830 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99 2831
f8c6455b
SM		 2832 if (mdev->dev->caps.rx_checksum_flags_port[priv->port] &
2833 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP)
2834 priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP;
2835
6bbb6d99
YB		 2836 /* Set default MAC */
2837 dev->addr_len = ETH_ALEN;
2838 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2839 if (!is_valid_ether_addr(dev->dev_addr)) {
ef96f7d4
OG		 2840 if (mlx4_is_slave(priv->mdev->dev)) {
2841 eth_hw_addr_random(dev);
2842 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
9813337a 2843 mac_u64 = mlx4_mac_to_u64(dev->dev_addr);
ef96f7d4
OG		 2844 mdev->dev->caps.def_mac[priv->port] = mac_u64;
2845 } else {
2846 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2847 priv->port, dev->dev_addr);
2848 err = -EINVAL;
2849 goto out;
2850 }
c27a02cd
YP		 2851 }
2852
2695bab2 2853 memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));
6bbb6d99 2854
c27a02cd
YP		 2855 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2856 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2857 err = mlx4_en_alloc_resources(priv);
2858 if (err)
2859 goto out;
2860
ec693d47
AV		 2861 /* Initialize time stamping config */
2862 priv->hwtstamp_config.flags = 0;
2863 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2864 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2865
c27a02cd
YP		 2866 /* Allocate page for receive rings */
2867 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
2868 MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE);
2869 if (err) {
453a6082 2870 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 2871 goto out;
2872 }
2873 priv->allocated = 1;
2874
c27a02cd
YP		 2875 /*
2876 * Initialize netdev entry points
2877 */
8f7ba3ca
RE		 2878 if (mlx4_is_master(priv->mdev->dev))
2879 dev->netdev_ops = &mlx4_netdev_ops_master;
2880 else
2881 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2882 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH		 2883 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2884 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2885
7ad24ea4 2886 dev->ethtool_ops = &mlx4_en_ethtool_ops;
c27a02cd 2887
c27a02cd
YP		 2888 /*
2889 * Set driver features
2890 */
c8c64cff
MM		 2891 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2892 if (mdev->LSO_support)
2893 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2894
2895 dev->vlan_features = dev->hw_features;
2896
ad86107f 2897 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2898 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 2899 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2900 NETIF_F_HW_VLAN_CTAG_FILTER;
537f6f95
SM		 2901 dev->hw_features |= NETIF_F_LOOPBACK |
2902 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c27a02cd 2903
1eb8c695 2904 if (mdev->dev->caps.steering_mode ==
7d077cd3
MB		 2905 MLX4_STEERING_MODE_DEVICE_MANAGED &&
2906 mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
1eb8c695
AV		 2907 dev->hw_features |= NETIF_F_NTUPLE;
2908
cc5387f7
YB		 2909 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
2910 dev->priv_flags |= IFF_UNICAST_FLT;
2911
947cbb0a
EP		 2912 /* Setting a default hash function value */
2913 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) {
2914 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
2915 } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) {
2916 priv->rss_hash_fn = ETH_RSS_HASH_XOR;
2917 } else {
2918 en_warn(priv,
2919 "No RSS hash capabilities exposed, using Toeplitz\n");
2920 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
2921 }
2922
c27a02cd 2923 mdev->pndev[port] = dev;
5da03547 2924 mdev->upper[port] = NULL;
c27a02cd
YP		 2925
2926 netif_carrier_off(dev);
4801ae70
EE		 2927 mlx4_en_set_default_moderation(priv);
2928
453a6082
YP		 2929 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
2930 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
2931
79aeaccd
YB		 2932 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
2933
90822265 2934 /* Configure port */
5c8e9046 2935 mlx4_en_calc_rx_buf(dev);
90822265 2936 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 2937 priv->rx_skb_size + ETH_FCS_LEN,
2938 prof->tx_pause, prof->tx_ppp,
2939 prof->rx_pause, prof->rx_ppp);
90822265 2940 if (err) {
1a91de28
JP		 2941 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
2942 priv->port, err);
90822265
YP		 2943 goto out;
2944 }
2945
837052d0 2946 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 2947 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 2948 if (err) {
2949 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
2950 err);
2951 goto out;
2952 }
2953 }
2954
90822265
YP		 2955 /* Init port */
2956 en_warn(priv, "Initializing port\n");
2957 err = mlx4_INIT_PORT(mdev->dev, priv->port);
2958 if (err) {
2959 en_err(priv, "Failed Initializing port\n");
2960 goto out;
2961 }
c27a02cd 2962 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea
AV		 2963
2964 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2965 queue_delayed_work(mdev->workqueue, &priv->service_task,
2966 SERVICE_TASK_DELAY);
2967
0b131561
MB		 2968 mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap,
2969 mdev->profile.prof[priv->port].rx_ppp,
2970 mdev->profile.prof[priv->port].rx_pause,
2971 mdev->profile.prof[priv->port].tx_ppp,
2972 mdev->profile.prof[priv->port].tx_pause);
39de961a 2973
e5eda89d
IS		 2974 err = register_netdev(dev);
2975 if (err) {
2976 en_err(priv, "Netdev registration failed for port %d\n", port);
2977 goto out;
2978 }
2979
2980 priv->registered = 1;
2981
c27a02cd
YP		 2982 return 0;
2983
2984out:
2985 mlx4_en_destroy_netdev(dev);
2986 return err;
2987}
2988
537f6f95
SM		 2989int mlx4_en_reset_config(struct net_device *dev,
2990 struct hwtstamp_config ts_config,
2991 netdev_features_t features)
2992{
2993 struct mlx4_en_priv *priv = netdev_priv(dev);
2994 struct mlx4_en_dev *mdev = priv->mdev;
2995 int port_up = 0;
2996 int err = 0;
2997
2998 if (priv->hwtstamp_config.tx_type == ts_config.tx_type &&
2999 priv->hwtstamp_config.rx_filter == ts_config.rx_filter &&
3000 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX))
3001 return 0; /* Nothing to change */
3002
3003 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3004 (features & NETIF_F_HW_VLAN_CTAG_RX) &&
3005 (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) {
3006 en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n");
3007 return -EINVAL;
3008 }
3009
3010 mutex_lock(&mdev->state_lock);
3011 if (priv->port_up) {
3012 port_up = 1;
3013 mlx4_en_stop_port(dev, 1);
3014 }
3015
3016 mlx4_en_free_resources(priv);
3017
3018 en_warn(priv, "Changing device configuration rx filter(%x) rx vlan(%x)\n",
3019 ts_config.rx_filter, !!(features & NETIF_F_HW_VLAN_CTAG_RX));
3020
3021 priv->hwtstamp_config.tx_type = ts_config.tx_type;
3022 priv->hwtstamp_config.rx_filter = ts_config.rx_filter;
3023
3024 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
3025 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3026 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3027 else
3028 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3029 } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) {
3030 /* RX time-stamping is OFF, update the RX vlan offload
3031 * to the latest wanted state
3032 */
3033 if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX)
3034 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3035 else
3036 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3037 }
3038
3039 /* RX vlan offload and RX time-stamping can't co-exist !
3040 * Regardless of the caller's choice,
3041 * Turn Off RX vlan offload in case of time-stamping is ON
3042 */
3043 if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) {
3044 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
3045 en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n");
3046 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3047 }
3048
3049 err = mlx4_en_alloc_resources(priv);
3050 if (err) {
3051 en_err(priv, "Failed reallocating port resources\n");
3052 goto out;
3053 }
3054 if (port_up) {
3055 err = mlx4_en_start_port(dev);
3056 if (err)
3057 en_err(priv, "Failed starting port\n");
3058 }
3059
3060out:
3061 mutex_unlock(&mdev->state_lock);
3062 netdev_features_change(dev);
3063 return err;
3064}
Linux 6.x block layer and io_uring tree(s)