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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV		 39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
c27a02cd
YP		 42
43#include <linux/mlx4/driver.h>
44#include <linux/mlx4/device.h>
45#include <linux/mlx4/cmd.h>
46#include <linux/mlx4/cq.h>
47
48#include "mlx4_en.h"
49#include "en_port.h"
50
d317966b 51int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 52{
bc6a4744
AV		 53 struct mlx4_en_priv *priv = netdev_priv(dev);
54 int i;
d317966b 55 unsigned int offset = 0;
bc6a4744
AV		 56
57 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 58 return -EINVAL;
59
bc6a4744
AV		 60 netdev_set_num_tc(dev, up);
61
62 /* Partition Tx queues evenly amongst UP's */
bc6a4744 63 for (i = 0; i < up; i++) {
d317966b
AV		 64 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
65 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 66 }
67
897d7846
AV		 68 return 0;
69}
70
e0d1095a 71#ifdef CONFIG_NET_RX_BUSY_POLL
9e77a2b8
AV		 72/* must be called with local_bh_disable()d */
73static int mlx4_en_low_latency_recv(struct napi_struct *napi)
74{
75 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
76 struct net_device *dev = cq->dev;
77 struct mlx4_en_priv *priv = netdev_priv(dev);
41d942d5 78 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
9e77a2b8
AV		 79 int done;
80
81 if (!priv->port_up)
82 return LL_FLUSH_FAILED;
83
84 if (!mlx4_en_cq_lock_poll(cq))
85 return LL_FLUSH_BUSY;
86
87 done = mlx4_en_process_rx_cq(dev, cq, 4);
8501841a
AV		 88 if (likely(done))
89 rx_ring->cleaned += done;
90 else
91 rx_ring->misses++;
9e77a2b8
AV		 92
93 mlx4_en_cq_unlock_poll(cq);
94
95 return done;
96}
e0d1095a 97#endif /* CONFIG_NET_RX_BUSY_POLL */
9e77a2b8 98
1eb8c695
AV		 99#ifdef CONFIG_RFS_ACCEL
100
101struct mlx4_en_filter {
102 struct list_head next;
103 struct work_struct work;
104
75a353d4 105 u8 ip_proto;
1eb8c695
AV		 106 __be32 src_ip;
107 __be32 dst_ip;
108 __be16 src_port;
109 __be16 dst_port;
110
111 int rxq_index;
112 struct mlx4_en_priv *priv;
113 u32 flow_id; /* RFS infrastructure id */
114 int id; /* mlx4_en driver id */
115 u64 reg_id; /* Flow steering API id */
116 u8 activated; /* Used to prevent expiry before filter
117 * is attached
118 */
119 struct hlist_node filter_chain;
120};
121
122static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
123
75a353d4
EP		 124static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
125{
126 switch (ip_proto) {
127 case IPPROTO_UDP:
128 return MLX4_NET_TRANS_RULE_ID_UDP;
129 case IPPROTO_TCP:
130 return MLX4_NET_TRANS_RULE_ID_TCP;
131 default:
132 return -EPROTONOSUPPORT;
133 }
134};
135
1eb8c695
AV		 136static void mlx4_en_filter_work(struct work_struct *work)
137{
138 struct mlx4_en_filter *filter = container_of(work,
139 struct mlx4_en_filter,
140 work);
141 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 142 struct mlx4_spec_list spec_tcp_udp = {
143 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 144 {
145 .tcp_udp = {
146 .dst_port = filter->dst_port,
147 .dst_port_msk = (__force __be16)-1,
148 .src_port = filter->src_port,
149 .src_port_msk = (__force __be16)-1,
150 },
151 },
152 };
153 struct mlx4_spec_list spec_ip = {
154 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
155 {
156 .ipv4 = {
157 .dst_ip = filter->dst_ip,
158 .dst_ip_msk = (__force __be32)-1,
159 .src_ip = filter->src_ip,
160 .src_ip_msk = (__force __be32)-1,
161 },
162 },
163 };
164 struct mlx4_spec_list spec_eth = {
165 .id = MLX4_NET_TRANS_RULE_ID_ETH,
166 };
167 struct mlx4_net_trans_rule rule = {
168 .list = LIST_HEAD_INIT(rule.list),
169 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
170 .exclusive = 1,
171 .allow_loopback = 1,
f9162539 172 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 173 .port = priv->port,
174 .priority = MLX4_DOMAIN_RFS,
175 };
176 int rc;
1eb8c695
AV		 177 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
178
75a353d4
EP		 179 if (spec_tcp_udp.id < 0) {
180 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
181 filter->ip_proto);
182 goto ignore;
183 }
1eb8c695
AV		 184 list_add_tail(&spec_eth.list, &rule.list);
185 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 186 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 187
1eb8c695 188 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 189 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 190 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
191
192 filter->activated = 0;
193
194 if (filter->reg_id) {
195 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
196 if (rc && rc != -ENOENT)
197 en_err(priv, "Error detaching flow. rc = %d\n", rc);
198 }
199
200 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
201 if (rc)
202 en_err(priv, "Error attaching flow. err = %d\n", rc);
203
75a353d4 204ignore:
1eb8c695
AV		 205 mlx4_en_filter_rfs_expire(priv);
206
207 filter->activated = 1;
208}
209
210static inline struct hlist_head *
211filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
212 __be16 src_port, __be16 dst_port)
213{
214 unsigned long l;
215 int bucket_idx;
216
217 l = (__force unsigned long)src_port |
218 ((__force unsigned long)dst_port << 2);
219 l ^= (__force unsigned long)(src_ip ^ dst_ip);
220
221 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
222
223 return &priv->filter_hash[bucket_idx];
224}
225
226static struct mlx4_en_filter *
227mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 228 __be32 dst_ip, u8 ip_proto, __be16 src_port,
229 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 230{
231 struct mlx4_en_filter *filter = NULL;
232
233 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
234 if (!filter)
235 return NULL;
236
237 filter->priv = priv;
238 filter->rxq_index = rxq_index;
239 INIT_WORK(&filter->work, mlx4_en_filter_work);
240
241 filter->src_ip = src_ip;
242 filter->dst_ip = dst_ip;
75a353d4 243 filter->ip_proto = ip_proto;
1eb8c695
AV		 244 filter->src_port = src_port;
245 filter->dst_port = dst_port;
246
247 filter->flow_id = flow_id;
248
ee64c0ee 249 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 250
251 list_add_tail(&filter->next, &priv->filters);
252 hlist_add_head(&filter->filter_chain,
253 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
254 dst_port));
255
256 return filter;
257}
258
259static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
260{
261 struct mlx4_en_priv *priv = filter->priv;
262 int rc;
263
264 list_del(&filter->next);
265
266 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
267 if (rc && rc != -ENOENT)
268 en_err(priv, "Error detaching flow. rc = %d\n", rc);
269
270 kfree(filter);
271}
272
273static inline struct mlx4_en_filter *
274mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 275 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 276{
1eb8c695
AV		 277 struct mlx4_en_filter *filter;
278 struct mlx4_en_filter *ret = NULL;
279
b67bfe0d 280 hlist_for_each_entry(filter,
1eb8c695
AV		 281 filter_hash_bucket(priv, src_ip, dst_ip,
282 src_port, dst_port),
283 filter_chain) {
284 if (filter->src_ip == src_ip &&
285 filter->dst_ip == dst_ip &&
75a353d4 286 filter->ip_proto == ip_proto &&
1eb8c695
AV		 287 filter->src_port == src_port &&
288 filter->dst_port == dst_port) {
289 ret = filter;
290 break;
291 }
292 }
293
294 return ret;
295}
296
297static int
298mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
299 u16 rxq_index, u32 flow_id)
300{
301 struct mlx4_en_priv *priv = netdev_priv(net_dev);
302 struct mlx4_en_filter *filter;
303 const struct iphdr *ip;
304 const __be16 *ports;
75a353d4 305 u8 ip_proto;
1eb8c695
AV		 306 __be32 src_ip;
307 __be32 dst_ip;
308 __be16 src_port;
309 __be16 dst_port;
310 int nhoff = skb_network_offset(skb);
311 int ret = 0;
312
313 if (skb->protocol != htons(ETH_P_IP))
314 return -EPROTONOSUPPORT;
315
316 ip = (const struct iphdr *)(skb->data + nhoff);
317 if (ip_is_fragment(ip))
318 return -EPROTONOSUPPORT;
319
75a353d4
EP		 320 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
321 return -EPROTONOSUPPORT;
1eb8c695
AV		 322 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
323
75a353d4 324 ip_proto = ip->protocol;
1eb8c695
AV		 325 src_ip = ip->saddr;
326 dst_ip = ip->daddr;
327 src_port = ports[0];
328 dst_port = ports[1];
329
1eb8c695 330 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 331 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
332 src_port, dst_port);
1eb8c695
AV		 333 if (filter) {
334 if (filter->rxq_index == rxq_index)
335 goto out;
336
337 filter->rxq_index = rxq_index;
338 } else {
339 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 340 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 341 src_port, dst_port, flow_id);
342 if (!filter) {
343 ret = -ENOMEM;
344 goto err;
345 }
346 }
347
348 queue_work(priv->mdev->workqueue, &filter->work);
349
350out:
351 ret = filter->id;
352err:
353 spin_unlock_bh(&priv->filters_lock);
354
355 return ret;
356}
357
41d942d5 358void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 359{
360 struct mlx4_en_filter *filter, *tmp;
361 LIST_HEAD(del_list);
362
363 spin_lock_bh(&priv->filters_lock);
364 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
365 list_move(&filter->next, &del_list);
366 hlist_del(&filter->filter_chain);
367 }
368 spin_unlock_bh(&priv->filters_lock);
369
370 list_for_each_entry_safe(filter, tmp, &del_list, next) {
371 cancel_work_sync(&filter->work);
372 mlx4_en_filter_free(filter);
373 }
374}
375
376static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
377{
378 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
379 LIST_HEAD(del_list);
380 int i = 0;
381
382 spin_lock_bh(&priv->filters_lock);
383 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
384 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
385 break;
386
387 if (filter->activated &&
388 !work_pending(&filter->work) &&
389 rps_may_expire_flow(priv->dev,
390 filter->rxq_index, filter->flow_id,
391 filter->id)) {
392 list_move(&filter->next, &del_list);
393 hlist_del(&filter->filter_chain);
394 } else
395 last_filter = filter;
396
397 i++;
398 }
399
400 if (last_filter && (&last_filter->next != priv->filters.next))
401 list_move(&priv->filters, &last_filter->next);
402
403 spin_unlock_bh(&priv->filters_lock);
404
405 list_for_each_entry_safe(filter, tmp, &del_list, next)
406 mlx4_en_filter_free(filter);
407}
408#endif
409
80d5c368
PM		 410static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
411 __be16 proto, u16 vid)
c27a02cd
YP		 412{
413 struct mlx4_en_priv *priv = netdev_priv(dev);
414 struct mlx4_en_dev *mdev = priv->mdev;
415 int err;
4c3eb3ca 416 int idx;
c27a02cd 417
f1b553fb 418 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 419
f1b553fb 420 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 421
422 /* Add VID to port VLAN filter */
423 mutex_lock(&mdev->state_lock);
424 if (mdev->device_up && priv->port_up) {
f1b553fb 425 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 426 if (err)
453a6082 427 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 428 }
4c3eb3ca 429 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 430 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 431 mutex_unlock(&mdev->state_lock);
4c3eb3ca 432
8e586137 433 return 0;
c27a02cd
YP		 434}
435
80d5c368
PM		 436static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
437 __be16 proto, u16 vid)
c27a02cd
YP		 438{
439 struct mlx4_en_priv *priv = netdev_priv(dev);
440 struct mlx4_en_dev *mdev = priv->mdev;
441 int err;
442
f1b553fb 443 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 444
f1b553fb 445 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 446
447 /* Remove VID from port VLAN filter */
448 mutex_lock(&mdev->state_lock);
2009d005 449 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 450
c27a02cd 451 if (mdev->device_up && priv->port_up) {
f1b553fb 452 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 453 if (err)
453a6082 454 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 455 }
456 mutex_unlock(&mdev->state_lock);
8e586137
JP		 457
458 return 0;
c27a02cd
YP		 459}
460
6bbb6d99
YB		 461static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
462{
bab6a9ea
YB		 463 int i;
464 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 465 dst_mac[i] = src_mac & 0xff;
466 src_mac >>= 8;
467 }
468 memset(&dst_mac[ETH_ALEN], 0, 2);
469}
470
837052d0
OG		 471
472static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
473 int qpn, u64 *reg_id)
474{
475 int err;
476 struct mlx4_spec_list spec_eth_outer = { {NULL} };
477 struct mlx4_spec_list spec_vxlan = { {NULL} };
478 struct mlx4_spec_list spec_eth_inner = { {NULL} };
479
480 struct mlx4_net_trans_rule rule = {
481 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
482 .exclusive = 0,
483 .allow_loopback = 1,
484 .promisc_mode = MLX4_FS_REGULAR,
485 .priority = MLX4_DOMAIN_NIC,
486 };
487
488 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
489
490 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
491 return 0; /* do nothing */
492
493 rule.port = priv->port;
494 rule.qpn = qpn;
495 INIT_LIST_HEAD(&rule.list);
496
497 spec_eth_outer.id = MLX4_NET_TRANS_RULE_ID_ETH;
498 memcpy(spec_eth_outer.eth.dst_mac, addr, ETH_ALEN);
499 memcpy(spec_eth_outer.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
500
501 spec_vxlan.id = MLX4_NET_TRANS_RULE_ID_VXLAN; /* any vxlan header */
502 spec_eth_inner.id = MLX4_NET_TRANS_RULE_ID_ETH; /* any inner eth header */
503
504 list_add_tail(&spec_eth_outer.list, &rule.list);
505 list_add_tail(&spec_vxlan.list, &rule.list);
506 list_add_tail(&spec_eth_inner.list, &rule.list);
507
508 err = mlx4_flow_attach(priv->mdev->dev, &rule, reg_id);
509 if (err) {
510 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
511 return err;
512 }
513 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
514 return 0;
515}
516
517
16a10ffd
YB		 518static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
519 unsigned char *mac, int *qpn, u64 *reg_id)
520{
521 struct mlx4_en_dev *mdev = priv->mdev;
522 struct mlx4_dev *dev = mdev->dev;
523 int err;
524
525 switch (dev->caps.steering_mode) {
526 case MLX4_STEERING_MODE_B0: {
527 struct mlx4_qp qp;
528 u8 gid[16] = {0};
529
530 qp.qpn = *qpn;
531 memcpy(&gid[10], mac, ETH_ALEN);
532 gid[5] = priv->port;
533
534 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
535 break;
536 }
537 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
538 struct mlx4_spec_list spec_eth = { {NULL} };
539 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
540
541 struct mlx4_net_trans_rule rule = {
542 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
543 .exclusive = 0,
544 .allow_loopback = 1,
f9162539 545 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 546 .priority = MLX4_DOMAIN_NIC,
547 };
548
549 rule.port = priv->port;
550 rule.qpn = *qpn;
551 INIT_LIST_HEAD(&rule.list);
552
553 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
554 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
555 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
556 list_add_tail(&spec_eth.list, &rule.list);
557
558 err = mlx4_flow_attach(dev, &rule, reg_id);
559 break;
560 }
561 default:
562 return -EINVAL;
563 }
564 if (err)
565 en_warn(priv, "Failed Attaching Unicast\n");
566
567 return err;
568}
569
570static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
571 unsigned char *mac, int qpn, u64 reg_id)
572{
573 struct mlx4_en_dev *mdev = priv->mdev;
574 struct mlx4_dev *dev = mdev->dev;
575
576 switch (dev->caps.steering_mode) {
577 case MLX4_STEERING_MODE_B0: {
578 struct mlx4_qp qp;
579 u8 gid[16] = {0};
580
581 qp.qpn = qpn;
582 memcpy(&gid[10], mac, ETH_ALEN);
583 gid[5] = priv->port;
584
585 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
586 break;
587 }
588 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
589 mlx4_flow_detach(dev, reg_id);
590 break;
591 }
592 default:
593 en_err(priv, "Invalid steering mode.\n");
594 }
595}
596
597static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
598{
599 struct mlx4_en_dev *mdev = priv->mdev;
600 struct mlx4_dev *dev = mdev->dev;
601 struct mlx4_mac_entry *entry;
602 int index = 0;
603 int err = 0;
604 u64 reg_id;
605 int *qpn = &priv->base_qpn;
9813337a 606 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
16a10ffd
YB		 607
608 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
609 priv->dev->dev_addr);
610 index = mlx4_register_mac(dev, priv->port, mac);
611 if (index < 0) {
612 err = index;
613 en_err(priv, "Failed adding MAC: %pM\n",
614 priv->dev->dev_addr);
615 return err;
616 }
617
618 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
619 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
620 *qpn = base_qpn + index;
621 return 0;
622 }
623
624 err = mlx4_qp_reserve_range(dev, 1, 1, qpn);
625 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
626 if (err) {
627 en_err(priv, "Failed to reserve qp for mac registration\n");
628 goto qp_err;
629 }
630
631 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
632 if (err)
633 goto steer_err;
634
9ba75fb0
WY		 635 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
636 &priv->tunnel_reg_id);
637 if (err)
837052d0
OG		 638 goto tunnel_err;
639
16a10ffd
YB		 640 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
641 if (!entry) {
642 err = -ENOMEM;
643 goto alloc_err;
644 }
645 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
646 entry->reg_id = reg_id;
647
c07cb4b0
YB		 648 hlist_add_head_rcu(&entry->hlist,
649 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
16a10ffd 650
c07cb4b0 651 return 0;
16a10ffd
YB		 652
653alloc_err:
837052d0
OG		 654 if (priv->tunnel_reg_id)
655 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
656tunnel_err:
16a10ffd
YB		 657 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
658
659steer_err:
660 mlx4_qp_release_range(dev, *qpn, 1);
661
662qp_err:
663 mlx4_unregister_mac(dev, priv->port, mac);
664 return err;
665}
666
667static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
668{
669 struct mlx4_en_dev *mdev = priv->mdev;
670 struct mlx4_dev *dev = mdev->dev;
16a10ffd 671 int qpn = priv->base_qpn;
83a5a6ce 672 u64 mac;
16a10ffd 673
83a5a6ce 674 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
9813337a 675 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
83a5a6ce
YB		 676 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
677 priv->dev->dev_addr);
678 mlx4_unregister_mac(dev, priv->port, mac);
679 } else {
c07cb4b0 680 struct mlx4_mac_entry *entry;
b67bfe0d 681 struct hlist_node *tmp;
c07cb4b0 682 struct hlist_head *bucket;
83a5a6ce 683 unsigned int i;
c07cb4b0 684
83a5a6ce
YB		 685 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
686 bucket = &priv->mac_hash[i];
687 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
9813337a 688 mac = mlx4_mac_to_u64(entry->mac);
83a5a6ce
YB		 689 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
690 entry->mac);
c07cb4b0
YB		 691 mlx4_en_uc_steer_release(priv, entry->mac,
692 qpn, entry->reg_id);
c07cb4b0 693
83a5a6ce 694 mlx4_unregister_mac(dev, priv->port, mac);
c07cb4b0
YB		 695 hlist_del_rcu(&entry->hlist);
696 kfree_rcu(entry, rcu);
c07cb4b0 697 }
16a10ffd 698 }
83a5a6ce 699
837052d0
OG		 700 if (priv->tunnel_reg_id) {
701 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
702 priv->tunnel_reg_id = 0;
703 }
704
83a5a6ce
YB		 705 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
706 priv->port, qpn);
707 mlx4_qp_release_range(dev, qpn, 1);
708 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 709 }
710}
711
712static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 713 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 714{
715 struct mlx4_en_dev *mdev = priv->mdev;
716 struct mlx4_dev *dev = mdev->dev;
16a10ffd 717 int err = 0;
9813337a 718 u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
16a10ffd
YB		 719
720 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 721 struct hlist_head *bucket;
722 unsigned int mac_hash;
723 struct mlx4_mac_entry *entry;
b67bfe0d 724 struct hlist_node *tmp;
9813337a 725 u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
c07cb4b0
YB		 726
727 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 728 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 729 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
730 mlx4_en_uc_steer_release(priv, entry->mac,
731 qpn, entry->reg_id);
732 mlx4_unregister_mac(dev, priv->port,
733 prev_mac_u64);
734 hlist_del_rcu(&entry->hlist);
735 synchronize_rcu();
736 memcpy(entry->mac, new_mac, ETH_ALEN);
737 entry->reg_id = 0;
738 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
739 hlist_add_head_rcu(&entry->hlist,
740 &priv->mac_hash[mac_hash]);
741 mlx4_register_mac(dev, priv->port, new_mac_u64);
742 err = mlx4_en_uc_steer_add(priv, new_mac,
743 &qpn,
744 &entry->reg_id);
2a2083f7
OG		 745 if (err)
746 return err;
747 if (priv->tunnel_reg_id) {
748 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
749 priv->tunnel_reg_id = 0;
750 }
751 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
752 &priv->tunnel_reg_id);
c07cb4b0
YB		 753 return err;
754 }
755 }
756 return -EINVAL;
16a10ffd
YB		 757 }
758
759 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
760}
761
bfa8ab47 762static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv)
c27a02cd 763{
c27a02cd
YP		 764 int err = 0;
765
c27a02cd
YP		 766 if (priv->port_up) {
767 /* Remove old MAC and insert the new one */
16a10ffd 768 err = mlx4_en_replace_mac(priv, priv->base_qpn,
90bbb74a 769 priv->dev->dev_addr, priv->prev_mac);
c27a02cd 770 if (err)
453a6082 771 en_err(priv, "Failed changing HW MAC address\n");
6bbb6d99
YB		 772 memcpy(priv->prev_mac, priv->dev->dev_addr,
773 sizeof(priv->prev_mac));
c27a02cd 774 } else
48e551ff 775 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 776
bfa8ab47
YB		 777 return err;
778}
779
780static int mlx4_en_set_mac(struct net_device *dev, void *addr)
781{
782 struct mlx4_en_priv *priv = netdev_priv(dev);
783 struct mlx4_en_dev *mdev = priv->mdev;
784 struct sockaddr *saddr = addr;
785 int err;
786
787 if (!is_valid_ether_addr(saddr->sa_data))
788 return -EADDRNOTAVAIL;
789
790 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
791
792 mutex_lock(&mdev->state_lock);
793 err = mlx4_en_do_set_mac(priv);
c27a02cd 794 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 795
796 return err;
c27a02cd
YP		 797}
798
799static void mlx4_en_clear_list(struct net_device *dev)
800{
801 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 802 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 803
6d199937
YP		 804 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
805 list_del(&mc_to_del->list);
806 kfree(mc_to_del);
807 }
c27a02cd
YP		 808}
809
810static void mlx4_en_cache_mclist(struct net_device *dev)
811{
812 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 813 struct netdev_hw_addr *ha;
6d199937 814 struct mlx4_en_mc_list *tmp;
ff6e2163 815
0e03567a 816 mlx4_en_clear_list(dev);
6d199937
YP		 817 netdev_for_each_mc_addr(ha, dev) {
818 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
819 if (!tmp) {
6d199937
YP		 820 mlx4_en_clear_list(dev);
821 return;
822 }
823 memcpy(tmp->addr, ha->addr, ETH_ALEN);
824 list_add_tail(&tmp->list, &priv->mc_list);
825 }
c27a02cd
YP		 826}
827
6d199937
YP		 828static void update_mclist_flags(struct mlx4_en_priv *priv,
829 struct list_head *dst,
830 struct list_head *src)
831{
832 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
833 bool found;
834
835 /* Find all the entries that should be removed from dst,
836 * These are the entries that are not found in src
837 */
838 list_for_each_entry(dst_tmp, dst, list) {
839 found = false;
840 list_for_each_entry(src_tmp, src, list) {
c0623e58 841 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 842 found = true;
843 break;
844 }
845 }
846 if (!found)
847 dst_tmp->action = MCLIST_REM;
848 }
849
850 /* Add entries that exist in src but not in dst
851 * mark them as need to add
852 */
853 list_for_each_entry(src_tmp, src, list) {
854 found = false;
855 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 856 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 857 dst_tmp->action = MCLIST_NONE;
858 found = true;
859 break;
860 }
861 }
862 if (!found) {
14f8dc49
JP		 863 new_mc = kmemdup(src_tmp,
864 sizeof(struct mlx4_en_mc_list),
6d199937 865 GFP_KERNEL);
14f8dc49 866 if (!new_mc)
6d199937 867 return;
14f8dc49 868
6d199937
YP		 869 new_mc->action = MCLIST_ADD;
870 list_add_tail(&new_mc->list, dst);
871 }
872 }
873}
c27a02cd 874
0eb74fdd 875static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 876{
877 struct mlx4_en_priv *priv = netdev_priv(dev);
878
879 if (!priv->port_up)
880 return;
881
0eb74fdd 882 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 883}
884
0eb74fdd
YB		 885static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
886 struct mlx4_en_dev *mdev)
c27a02cd 887{
c96d97f4 888 int err = 0;
c27a02cd 889
0eb74fdd 890 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 891 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 892 en_warn(priv, "Entering promiscuous mode\n");
893 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 894
0eb74fdd 895 /* Enable promiscouos mode */
c96d97f4 896 switch (mdev->dev->caps.steering_mode) {
592e49dd 897 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 898 err = mlx4_flow_steer_promisc_add(mdev->dev,
899 priv->port,
900 priv->base_qpn,
f9162539 901 MLX4_FS_ALL_DEFAULT);
592e49dd 902 if (err)
0eb74fdd
YB		 903 en_err(priv, "Failed enabling promiscuous mode\n");
904 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 905 break;
906
c96d97f4 907 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 908 err = mlx4_unicast_promisc_add(mdev->dev,
909 priv->base_qpn,
910 priv->port);
c96d97f4 911 if (err)
0eb74fdd
YB		 912 en_err(priv, "Failed enabling unicast promiscuous mode\n");
913
914 /* Add the default qp number as multicast
915 * promisc
916 */
917 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
918 err = mlx4_multicast_promisc_add(mdev->dev,
919 priv->base_qpn,
920 priv->port);
c96d97f4 921 if (err)
0eb74fdd
YB		 922 en_err(priv, "Failed enabling multicast promiscuous mode\n");
923 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 924 }
925 break;
c27a02cd 926
c96d97f4
HHZ		 927 case MLX4_STEERING_MODE_A0:
928 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
929 priv->port,
0eb74fdd
YB		 930 priv->base_qpn,
931 1);
1679200f 932 if (err)
0eb74fdd 933 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 934 break;
1679200f
YP		 935 }
936
0eb74fdd
YB		 937 /* Disable port multicast filter (unconditionally) */
938 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
939 0, MLX4_MCAST_DISABLE);
940 if (err)
941 en_err(priv, "Failed disabling multicast filter\n");
942
943 /* Disable port VLAN filter */
f1b553fb 944 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 945 if (err)
0eb74fdd
YB		 946 en_err(priv, "Failed disabling VLAN filter\n");
947 }
948}
949
950static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
951 struct mlx4_en_dev *mdev)
952{
953 int err = 0;
954
955 if (netif_msg_rx_status(priv))
956 en_warn(priv, "Leaving promiscuous mode\n");
957 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
958
959 /* Disable promiscouos mode */
960 switch (mdev->dev->caps.steering_mode) {
961 case MLX4_STEERING_MODE_DEVICE_MANAGED:
962 err = mlx4_flow_steer_promisc_remove(mdev->dev,
963 priv->port,
f9162539 964 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 965 if (err)
966 en_err(priv, "Failed disabling promiscuous mode\n");
967 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
968 break;
969
970 case MLX4_STEERING_MODE_B0:
971 err = mlx4_unicast_promisc_remove(mdev->dev,
972 priv->base_qpn,
973 priv->port);
974 if (err)
975 en_err(priv, "Failed disabling unicast promiscuous mode\n");
976 /* Disable Multicast promisc */
977 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
978 err = mlx4_multicast_promisc_remove(mdev->dev,
979 priv->base_qpn,
980 priv->port);
981 if (err)
982 en_err(priv, "Failed disabling multicast promiscuous mode\n");
983 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
984 }
985 break;
986
987 case MLX4_STEERING_MODE_A0:
988 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
989 priv->port,
990 priv->base_qpn, 0);
991 if (err)
992 en_err(priv, "Failed disabling promiscuous mode\n");
993 break;
c27a02cd
YP		 994 }
995
0eb74fdd
YB		 996 /* Enable port VLAN filter */
997 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
998 if (err)
999 en_err(priv, "Failed enabling VLAN filter\n");
1000}
1001
1002static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
1003 struct net_device *dev,
1004 struct mlx4_en_dev *mdev)
1005{
1006 struct mlx4_en_mc_list *mclist, *tmp;
1007 u64 mcast_addr = 0;
1008 u8 mc_list[16] = {0};
1009 int err = 0;
1010
c27a02cd
YP		 1011 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
1012 if (dev->flags & IFF_ALLMULTI) {
1013 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1014 0, MLX4_MCAST_DISABLE);
1015 if (err)
453a6082 1016 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 1017
1018 /* Add the default qp number as multicast promisc */
1019 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 1020 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1021 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1022 err = mlx4_flow_steer_promisc_add(mdev->dev,
1023 priv->port,
1024 priv->base_qpn,
f9162539 1025 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1026 break;
1027
c96d97f4
HHZ		 1028 case MLX4_STEERING_MODE_B0:
1029 err = mlx4_multicast_promisc_add(mdev->dev,
1030 priv->base_qpn,
1031 priv->port);
1032 break;
1033
1034 case MLX4_STEERING_MODE_A0:
1035 break;
1036 }
1679200f
YP		 1037 if (err)
1038 en_err(priv, "Failed entering multicast promisc mode\n");
1039 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
1040 }
c27a02cd 1041 } else {
1679200f
YP		 1042 /* Disable Multicast promisc */
1043 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 1044 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1045 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1046 err = mlx4_flow_steer_promisc_remove(mdev->dev,
1047 priv->port,
f9162539 1048 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1049 break;
1050
c96d97f4
HHZ		 1051 case MLX4_STEERING_MODE_B0:
1052 err = mlx4_multicast_promisc_remove(mdev->dev,
1053 priv->base_qpn,
1054 priv->port);
1055 break;
1056
1057 case MLX4_STEERING_MODE_A0:
1058 break;
1059 }
1679200f 1060 if (err)
25985edc 1061 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 1062 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1063 }
ff6e2163 1064
c27a02cd
YP		 1065 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1066 0, MLX4_MCAST_DISABLE);
1067 if (err)
453a6082 1068 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 1069
1070 /* Flush mcast filter and init it with broadcast address */
1071 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
1072 1, MLX4_MCAST_CONFIG);
1073
1074 /* Update multicast list - we cache all addresses so they won't
1075 * change while HW is updated holding the command semaphor */
dbd501a8 1076 netif_addr_lock_bh(dev);
c27a02cd 1077 mlx4_en_cache_mclist(dev);
dbd501a8 1078 netif_addr_unlock_bh(dev);
6d199937 1079 list_for_each_entry(mclist, &priv->mc_list, list) {
9813337a 1080 mcast_addr = mlx4_mac_to_u64(mclist->addr);
c27a02cd
YP		 1081 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1082 mcast_addr, 0, MLX4_MCAST_CONFIG);
1083 }
1084 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1085 0, MLX4_MCAST_ENABLE);
1086 if (err)
453a6082 1087 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 1088
1089 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1090 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1091 if (mclist->action == MCLIST_REM) {
1092 /* detach this address and delete from list */
1093 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1094 mc_list[5] = priv->port;
1095 err = mlx4_multicast_detach(mdev->dev,
1096 &priv->rss_map.indir_qp,
1097 mc_list,
0ff1fb65
HHZ		 1098 MLX4_PROT_ETH,
1099 mclist->reg_id);
6d199937
YP		 1100 if (err)
1101 en_err(priv, "Fail to detach multicast address\n");
1102
837052d0
OG		 1103 if (mclist->tunnel_reg_id) {
1104 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1105 if (err)
1106 en_err(priv, "Failed to detach multicast address\n");
1107 }
1108
6d199937
YP		 1109 /* remove from list */
1110 list_del(&mclist->list);
1111 kfree(mclist);
9c64508a 1112 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1113 /* attach the address */
1114 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1115 /* needed for B0 steering support */
6d199937
YP		 1116 mc_list[5] = priv->port;
1117 err = mlx4_multicast_attach(mdev->dev,
1118 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1119 mc_list,
1120 priv->port, 0,
1121 MLX4_PROT_ETH,
1122 &mclist->reg_id);
6d199937
YP		 1123 if (err)
1124 en_err(priv, "Fail to attach multicast address\n");
1125
837052d0
OG		 1126 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1127 &mclist->tunnel_reg_id);
1128 if (err)
1129 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1130 }
1131 }
c27a02cd 1132 }
0eb74fdd
YB		 1133}
1134
cc5387f7
YB		 1135static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1136 struct net_device *dev,
1137 struct mlx4_en_dev *mdev)
1138{
1139 struct netdev_hw_addr *ha;
1140 struct mlx4_mac_entry *entry;
b67bfe0d 1141 struct hlist_node *tmp;
cc5387f7
YB		 1142 bool found;
1143 u64 mac;
1144 int err = 0;
1145 struct hlist_head *bucket;
1146 unsigned int i;
1147 int removed = 0;
1148 u32 prev_flags;
1149
1150 /* Note that we do not need to protect our mac_hash traversal with rcu,
1151 * since all modification code is protected by mdev->state_lock
1152 */
1153
1154 /* find what to remove */
1155 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1156 bucket = &priv->mac_hash[i];
b67bfe0d 1157 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1158 found = false;
1159 netdev_for_each_uc_addr(ha, dev) {
1160 if (ether_addr_equal_64bits(entry->mac,
1161 ha->addr)) {
1162 found = true;
1163 break;
1164 }
1165 }
1166
1167 /* MAC address of the port is not in uc list */
1168 if (ether_addr_equal_64bits(entry->mac, dev->dev_addr))
1169 found = true;
1170
1171 if (!found) {
9813337a 1172 mac = mlx4_mac_to_u64(entry->mac);
cc5387f7
YB		 1173 mlx4_en_uc_steer_release(priv, entry->mac,
1174 priv->base_qpn,
1175 entry->reg_id);
1176 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1177
1178 hlist_del_rcu(&entry->hlist);
1179 kfree_rcu(entry, rcu);
1180 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1181 entry->mac, priv->port);
1182 ++removed;
1183 }
1184 }
1185 }
1186
1187 /* if we didn't remove anything, there is no use in trying to add
1188 * again once we are in a forced promisc mode state
1189 */
1190 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1191 return;
1192
1193 prev_flags = priv->flags;
1194 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1195
1196 /* find what to add */
1197 netdev_for_each_uc_addr(ha, dev) {
1198 found = false;
1199 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1200 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1201 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1202 found = true;
1203 break;
1204 }
1205 }
1206
1207 if (!found) {
1208 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1209 if (!entry) {
1210 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1211 ha->addr, priv->port);
1212 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1213 break;
1214 }
9813337a 1215 mac = mlx4_mac_to_u64(ha->addr);
cc5387f7
YB		 1216 memcpy(entry->mac, ha->addr, ETH_ALEN);
1217 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1218 if (err < 0) {
1219 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1220 ha->addr, priv->port, err);
1221 kfree(entry);
1222 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1223 break;
1224 }
1225 err = mlx4_en_uc_steer_add(priv, ha->addr,
1226 &priv->base_qpn,
1227 &entry->reg_id);
1228 if (err) {
1229 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1230 ha->addr, priv->port, err);
1231 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1232 kfree(entry);
1233 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1234 break;
1235 } else {
1236 unsigned int mac_hash;
1237 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1238 ha->addr, priv->port);
1239 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1240 bucket = &priv->mac_hash[mac_hash];
1241 hlist_add_head_rcu(&entry->hlist, bucket);
1242 }
1243 }
1244 }
1245
1246 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1247 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1248 priv->port);
1249 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1250 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1251 priv->port);
1252 }
1253}
1254
0eb74fdd
YB		 1255static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1256{
1257 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1258 rx_mode_task);
1259 struct mlx4_en_dev *mdev = priv->mdev;
1260 struct net_device *dev = priv->dev;
1261
1262 mutex_lock(&mdev->state_lock);
1263 if (!mdev->device_up) {
1264 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1265 goto out;
1266 }
1267 if (!priv->port_up) {
1268 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1269 goto out;
1270 }
1271
1272 if (!netif_carrier_ok(dev)) {
1273 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1274 if (priv->port_state.link_state) {
1275 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1276 netif_carrier_on(dev);
1277 en_dbg(LINK, priv, "Link Up\n");
1278 }
1279 }
1280 }
1281
cc5387f7
YB		 1282 if (dev->priv_flags & IFF_UNICAST_FLT)
1283 mlx4_en_do_uc_filter(priv, dev, mdev);
1284
0eb74fdd 1285 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1286 if ((dev->flags & IFF_PROMISC) ||
1287 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1288 mlx4_en_set_promisc_mode(priv, mdev);
1289 goto out;
1290 }
1291
1292 /* Not in promiscuous mode */
1293 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1294 mlx4_en_clear_promisc_mode(priv, mdev);
1295
1296 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1297out:
1298 mutex_unlock(&mdev->state_lock);
1299}
1300
1301#ifdef CONFIG_NET_POLL_CONTROLLER
1302static void mlx4_en_netpoll(struct net_device *dev)
1303{
1304 struct mlx4_en_priv *priv = netdev_priv(dev);
1305 struct mlx4_en_cq *cq;
1306 unsigned long flags;
1307 int i;
1308
1309 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1310 cq = priv->rx_cq[i];
c27a02cd
YP		 1311 spin_lock_irqsave(&cq->lock, flags);
1312 napi_synchronize(&cq->napi);
1313 mlx4_en_process_rx_cq(dev, cq, 0);
1314 spin_unlock_irqrestore(&cq->lock, flags);
1315 }
1316}
1317#endif
1318
1319static void mlx4_en_tx_timeout(struct net_device *dev)
1320{
1321 struct mlx4_en_priv *priv = netdev_priv(dev);
1322 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1323 int i;
c27a02cd
YP		 1324
1325 if (netif_msg_timer(priv))
453a6082 1326 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1327
b944ebec
YP		 1328 for (i = 0; i < priv->tx_ring_num; i++) {
1329 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1330 continue;
1331 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
41d942d5
EE		 1332 i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn,
1333 priv->tx_ring[i]->cons, priv->tx_ring[i]->prod);
b944ebec
YP		 1334 }
1335
1e338db5 1336 priv->port_stats.tx_timeout++;
453a6082 1337 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1338 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1339}
1340
1341
1342static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev)
1343{
1344 struct mlx4_en_priv *priv = netdev_priv(dev);
1345
1346 spin_lock_bh(&priv->stats_lock);
1347 memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats));
1348 spin_unlock_bh(&priv->stats_lock);
1349
1350 return &priv->ret_stats;
1351}
1352
1353static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1354{
c27a02cd
YP		 1355 struct mlx4_en_cq *cq;
1356 int i;
1357
1358 /* If we haven't received a specific coalescing setting
98a1708d 1359 * (module param), we set the moderation parameters as follows:
c27a02cd 1360 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1361 * satisfy our coalescing target.
c27a02cd
YP		 1362 * - moder_time is set to a fixed value.
1363 */
3db36fb2 1364 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1365 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1366 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1367 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1368 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1369 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1370
1371 /* Setup cq moderation params */
1372 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1373 cq = priv->rx_cq[i];
c27a02cd
YP		 1374 cq->moder_cnt = priv->rx_frames;
1375 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1376 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1377 priv->last_moder_packets[i] = 0;
1378 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1379 }
1380
1381 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1382 cq = priv->tx_cq[i];
a19a848a
YP		 1383 cq->moder_cnt = priv->tx_frames;
1384 cq->moder_time = priv->tx_usecs;
c27a02cd
YP		 1385 }
1386
1387 /* Reset auto-moderation params */
1388 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1389 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1390 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1391 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1392 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1393 priv->adaptive_rx_coal = 1;
c27a02cd 1394 priv->last_moder_jiffies = 0;
c27a02cd 1395 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1396}
1397
1398static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1399{
1400 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1401 struct mlx4_en_cq *cq;
1402 unsigned long packets;
1403 unsigned long rate;
1404 unsigned long avg_pkt_size;
1405 unsigned long rx_packets;
1406 unsigned long rx_bytes;
c27a02cd
YP		 1407 unsigned long rx_pkt_diff;
1408 int moder_time;
6b4d8d9f 1409 int ring, err;
c27a02cd
YP		 1410
1411 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1412 return;
1413
6b4d8d9f
AG		 1414 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1415 spin_lock_bh(&priv->stats_lock);
41d942d5
EE		 1416 rx_packets = priv->rx_ring[ring]->packets;
1417 rx_bytes = priv->rx_ring[ring]->bytes;
6b4d8d9f
AG		 1418 spin_unlock_bh(&priv->stats_lock);
1419
1420 rx_pkt_diff = ((unsigned long) (rx_packets -
1421 priv->last_moder_packets[ring]));
1422 packets = rx_pkt_diff;
1423 rate = packets * HZ / period;
1424 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1425 priv->last_moder_bytes[ring])) / packets : 0;
1426
1427 /* Apply auto-moderation only when packet rate
1428 * exceeds a rate that it matters */
1429 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1430 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1431 if (rate < priv->pkt_rate_low)
1432 moder_time = priv->rx_usecs_low;
1433 else if (rate > priv->pkt_rate_high)
1434 moder_time = priv->rx_usecs_high;
1435 else
1436 moder_time = (rate - priv->pkt_rate_low) *
1437 (priv->rx_usecs_high - priv->rx_usecs_low) /
1438 (priv->pkt_rate_high - priv->pkt_rate_low) +
1439 priv->rx_usecs_low;
6b4d8d9f
AG		 1440 } else {
1441 moder_time = priv->rx_usecs_low;
c27a02cd 1442 }
c27a02cd 1443
6b4d8d9f
AG		 1444 if (moder_time != priv->last_moder_time[ring]) {
1445 priv->last_moder_time[ring] = moder_time;
41d942d5 1446 cq = priv->rx_cq[ring];
c27a02cd 1447 cq->moder_time = moder_time;
a1c6693a 1448 cq->moder_cnt = priv->rx_frames;
c27a02cd 1449 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1450 if (err)
48e551ff
YB		 1451 en_err(priv, "Failed modifying moderation for cq:%d\n",
1452 ring);
c27a02cd 1453 }
6b4d8d9f
AG		 1454 priv->last_moder_packets[ring] = rx_packets;
1455 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1456 }
1457
c27a02cd
YP		 1458 priv->last_moder_jiffies = jiffies;
1459}
1460
1461static void mlx4_en_do_get_stats(struct work_struct *work)
1462{
bf6aede7 1463 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1464 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1465 stats_task);
1466 struct mlx4_en_dev *mdev = priv->mdev;
1467 int err;
1468
c27a02cd
YP		 1469 mutex_lock(&mdev->state_lock);
1470 if (mdev->device_up) {
6123db2e
JM		 1471 if (priv->port_up) {
1472 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1473 if (err)
1474 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1475
c27a02cd 1476 mlx4_en_auto_moderation(priv);
6123db2e 1477 }
c27a02cd
YP		 1478
1479 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1480 }
d7e1a487 1481 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
bfa8ab47 1482 mlx4_en_do_set_mac(priv);
d7e1a487
YP		 1483 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1484 }
c27a02cd
YP		 1485 mutex_unlock(&mdev->state_lock);
1486}
1487
b6c39bfc
AV		 1488/* mlx4_en_service_task - Run service task for tasks that needed to be done
1489 * periodically
1490 */
1491static void mlx4_en_service_task(struct work_struct *work)
1492{
1493 struct delayed_work *delay = to_delayed_work(work);
1494 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1495 service_task);
1496 struct mlx4_en_dev *mdev = priv->mdev;
1497
1498 mutex_lock(&mdev->state_lock);
1499 if (mdev->device_up) {
dc8142ea
AV		 1500 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1501 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc
AV		 1502
1503 queue_delayed_work(mdev->workqueue, &priv->service_task,
1504 SERVICE_TASK_DELAY);
1505 }
1506 mutex_unlock(&mdev->state_lock);
1507}
1508
c27a02cd
YP		 1509static void mlx4_en_linkstate(struct work_struct *work)
1510{
1511 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1512 linkstate_task);
1513 struct mlx4_en_dev *mdev = priv->mdev;
1514 int linkstate = priv->link_state;
1515
1516 mutex_lock(&mdev->state_lock);
1517 /* If observable port state changed set carrier state and
1518 * report to system log */
1519 if (priv->last_link_state != linkstate) {
1520 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1521 en_info(priv, "Link Down\n");
c27a02cd
YP		 1522 netif_carrier_off(priv->dev);
1523 } else {
e5cc44b2 1524 en_info(priv, "Link Up\n");
c27a02cd
YP		 1525 netif_carrier_on(priv->dev);
1526 }
1527 }
1528 priv->last_link_state = linkstate;
1529 mutex_unlock(&mdev->state_lock);
1530}
1531
1532
18cc42a3 1533int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1534{
1535 struct mlx4_en_priv *priv = netdev_priv(dev);
1536 struct mlx4_en_dev *mdev = priv->mdev;
1537 struct mlx4_en_cq *cq;
1538 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP		 1539 int rx_index = 0;
1540 int tx_index = 0;
c27a02cd
YP		 1541 int err = 0;
1542 int i;
1543 int j;
1679200f 1544 u8 mc_list[16] = {0};
c27a02cd
YP		 1545
1546 if (priv->port_up) {
453a6082 1547 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1548 return 0;
1549 }
1550
6d199937
YP		 1551 INIT_LIST_HEAD(&priv->mc_list);
1552 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1553 INIT_LIST_HEAD(&priv->ethtool_list);
1554 memset(&priv->ethtool_rules[0], 0,
1555 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1556
c27a02cd
YP		 1557 /* Calculate Rx buf size */
1558 dev->mtu = min(dev->mtu, priv->max_mtu);
1559 mlx4_en_calc_rx_buf(dev);
453a6082 1560 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1561
c27a02cd 1562 /* Configure rx cq's and rings */
38aab07c
YP		 1563 err = mlx4_en_activate_rx_rings(priv);
1564 if (err) {
453a6082 1565 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1566 return err;
1567 }
c27a02cd 1568 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1569 cq = priv->rx_cq[i];
c27a02cd 1570
9e77a2b8
AV		 1571 mlx4_en_cq_init_lock(cq);
1572
76532d0c 1573 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1574 if (err) {
453a6082 1575 en_err(priv, "Failed activating Rx CQ\n");
a4233304 1576 goto cq_err;
c27a02cd
YP		 1577 }
1578 for (j = 0; j < cq->size; j++)
1579 cq->buf[j].owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1580 err = mlx4_en_set_cq_moder(priv, cq);
1581 if (err) {
453a6082 1582 en_err(priv, "Failed setting cq moderation parameters");
c27a02cd
YP		 1583 mlx4_en_deactivate_cq(priv, cq);
1584 goto cq_err;
1585 }
1586 mlx4_en_arm_cq(priv, cq);
41d942d5 1587 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1588 ++rx_index;
1589 }
1590
ffe455ad
EE		 1591 /* Set qp number */
1592 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1593 err = mlx4_en_get_qp(priv);
1679200f 1594 if (err) {
ffe455ad 1595 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1596 goto cq_err;
1597 }
1598 mdev->mac_removed[priv->port] = 0;
1599
c27a02cd
YP		 1600 err = mlx4_en_config_rss_steer(priv);
1601 if (err) {
453a6082 1602 en_err(priv, "Failed configuring rss steering\n");
1679200f 1603 goto mac_err;
c27a02cd
YP		 1604 }
1605
cabdc8ee
HHZ		 1606 err = mlx4_en_create_drop_qp(priv);
1607 if (err)
1608 goto rss_err;
1609
c27a02cd
YP		 1610 /* Configure tx cq's and rings */
1611 for (i = 0; i < priv->tx_ring_num; i++) {
1612 /* Configure cq */
41d942d5 1613 cq = priv->tx_cq[i];
76532d0c 1614 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1615 if (err) {
453a6082 1616 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP		 1617 goto tx_err;
1618 }
1619 err = mlx4_en_set_cq_moder(priv, cq);
1620 if (err) {
453a6082 1621 en_err(priv, "Failed setting cq moderation parameters");
c27a02cd
YP		 1622 mlx4_en_deactivate_cq(priv, cq);
1623 goto tx_err;
1624 }
453a6082 1625 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP		 1626 cq->buf->wqe_index = cpu_to_be16(0xffff);
1627
1628 /* Configure ring */
41d942d5 1629 tx_ring = priv->tx_ring[i];
0e98b523 1630 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1631 i / priv->num_tx_rings_p_up);
c27a02cd 1632 if (err) {
453a6082 1633 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP		 1634 mlx4_en_deactivate_cq(priv, cq);
1635 goto tx_err;
1636 }
5b263f53 1637 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP		 1638
1639 /* Arm CQ for TX completions */
1640 mlx4_en_arm_cq(priv, cq);
1641
c27a02cd
YP		 1642 /* Set initial ownership of all Tx TXBBs to SW (1) */
1643 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1644 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1645 ++tx_index;
1646 }
1647
1648 /* Configure port */
1649 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1650 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1651 priv->prof->tx_pause,
1652 priv->prof->tx_ppp,
1653 priv->prof->rx_pause,
1654 priv->prof->rx_ppp);
c27a02cd 1655 if (err) {
48e551ff
YB		 1656 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1657 priv->port, err);
c27a02cd
YP		 1658 goto tx_err;
1659 }
1660 /* Set default qp number */
1661 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1662 if (err) {
453a6082 1663 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1664 goto tx_err;
1665 }
c27a02cd 1666
837052d0
OG		 1667 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1668 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC);
1669 if (err) {
1670 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1671 err);
1672 goto tx_err;
1673 }
1674 }
1675
c27a02cd 1676 /* Init port */
453a6082 1677 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1678 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1679 if (err) {
453a6082 1680 en_err(priv, "Failed Initializing port\n");
1679200f 1681 goto tx_err;
c27a02cd
YP		 1682 }
1683
1679200f
YP		 1684 /* Attach rx QP to bradcast address */
1685 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1686 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1687 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1688 priv->port, 0, MLX4_PROT_ETH,
1689 &priv->broadcast_id))
1679200f
YP		 1690 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1691
b5845f98
HX		 1692 /* Must redo promiscuous mode setup. */
1693 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1694
c27a02cd 1695 /* Schedule multicast task to populate multicast list */
0eb74fdd 1696 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1697
93ece0c1
EE		 1698 mlx4_set_stats_bitmap(mdev->dev, &priv->stats_bitmap);
1699
c27a02cd 1700 priv->port_up = true;
a11faac7 1701 netif_tx_start_all_queues(dev);
3484aac1
AV		 1702 netif_device_attach(dev);
1703
c27a02cd
YP		 1704 return 0;
1705
c27a02cd
YP		 1706tx_err:
1707 while (tx_index--) {
41d942d5
EE		 1708 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]);
1709 mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]);
c27a02cd 1710 }
cabdc8ee
HHZ		 1711 mlx4_en_destroy_drop_qp(priv);
1712rss_err:
c27a02cd 1713 mlx4_en_release_rss_steer(priv);
1679200f 1714mac_err:
16a10ffd 1715 mlx4_en_put_qp(priv);
c27a02cd
YP		 1716cq_err:
1717 while (rx_index--)
41d942d5 1718 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
38aab07c 1719 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1720 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1721
1722 return err; /* need to close devices */
1723}
1724
1725
3484aac1 1726void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1727{
1728 struct mlx4_en_priv *priv = netdev_priv(dev);
1729 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1730 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1731 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1732 int i;
1679200f 1733 u8 mc_list[16] = {0};
c27a02cd
YP		 1734
1735 if (!priv->port_up) {
453a6082 1736 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1737 return;
1738 }
c27a02cd 1739
0cc5c8bf
EE		 1740 /* close port*/
1741 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1742
c27a02cd
YP		 1743 /* Synchronize with tx routine */
1744 netif_tx_lock_bh(dev);
3484aac1
AV		 1745 if (detach)
1746 netif_device_detach(dev);
3c05f5ef 1747 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1748 netif_tx_unlock_bh(dev);
1749
3484aac1
AV		 1750 netif_tx_disable(dev);
1751
7c287380 1752 /* Set port as not active */
3c05f5ef 1753 priv->port_up = false;
c27a02cd 1754
db0e7cba
AY		 1755 /* Promsicuous mode */
1756 if (mdev->dev->caps.steering_mode ==
1757 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1758 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1759 MLX4_EN_FLAG_MC_PROMISC);
1760 mlx4_flow_steer_promisc_remove(mdev->dev,
1761 priv->port,
f9162539 1762 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1763 mlx4_flow_steer_promisc_remove(mdev->dev,
1764 priv->port,
f9162539 1765 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1766 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1767 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1768
1769 /* Disable promiscouos mode */
1770 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1771 priv->port);
1772
1773 /* Disable Multicast promisc */
1774 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1775 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1776 priv->port);
1777 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1778 }
1779 }
1780
1679200f
YP		 1781 /* Detach All multicasts */
1782 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1783 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1784 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1785 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1786 list_for_each_entry(mclist, &priv->curr_list, list) {
1787 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1788 mc_list[5] = priv->port;
1789 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1790 mc_list, MLX4_PROT_ETH, mclist->reg_id);
de123268
OG		 1791 if (mclist->tunnel_reg_id)
1792 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1679200f
YP		 1793 }
1794 mlx4_en_clear_list(dev);
6d199937
YP		 1795 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1796 list_del(&mclist->list);
1797 kfree(mclist);
1798 }
1799
1679200f
YP		 1800 /* Flush multicast filter */
1801 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1802
6efb5fac
HHZ		 1803 /* Remove flow steering rules for the port*/
1804 if (mdev->dev->caps.steering_mode ==
1805 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1806 ASSERT_RTNL();
1807 list_for_each_entry_safe(flow, tmp_flow,
1808 &priv->ethtool_list, list) {
1809 mlx4_flow_detach(mdev->dev, flow->id);
1810 list_del(&flow->list);
1811 }
1812 }
1813
cabdc8ee
HHZ		 1814 mlx4_en_destroy_drop_qp(priv);
1815
c27a02cd
YP		 1816 /* Free TX Rings */
1817 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1818 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]);
1819 mlx4_en_deactivate_cq(priv, priv->tx_cq[i]);
c27a02cd
YP		 1820 }
1821 msleep(10);
1822
1823 for (i = 0; i < priv->tx_ring_num; i++)
41d942d5 1824 mlx4_en_free_tx_buf(dev, priv->tx_ring[i]);
c27a02cd
YP		 1825
1826 /* Free RSS qps */
1827 mlx4_en_release_rss_steer(priv);
1828
ffe455ad 1829 /* Unregister Mac address for the port */
16a10ffd 1830 mlx4_en_put_qp(priv);
5930e8d0 1831 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1832 mdev->mac_removed[priv->port] = 1;
ffe455ad 1833
c27a02cd
YP		 1834 /* Free RX Rings */
1835 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1836 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8
AV		 1837
1838 local_bh_disable();
1839 while (!mlx4_en_cq_lock_napi(cq)) {
1840 pr_info("CQ %d locked\n", i);
1841 mdelay(1);
1842 }
1843 local_bh_enable();
1844
9e77a2b8 1845 while (test_bit(NAPI_STATE_SCHED, &cq->napi.state))
c27a02cd 1846 msleep(1);
41d942d5 1847 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1848 mlx4_en_deactivate_cq(priv, cq);
c27a02cd
YP		 1849 }
1850}
1851
1852static void mlx4_en_restart(struct work_struct *work)
1853{
1854 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1855 watchdog_task);
1856 struct mlx4_en_dev *mdev = priv->mdev;
1857 struct net_device *dev = priv->dev;
1858
453a6082 1859 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5
YP		 1860
1861 mutex_lock(&mdev->state_lock);
1862 if (priv->port_up) {
3484aac1 1863 mlx4_en_stop_port(dev, 1);
1e338db5 1864 if (mlx4_en_start_port(dev))
453a6082 1865 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1866 }
1867 mutex_unlock(&mdev->state_lock);
c27a02cd
YP		 1868}
1869
b477ba62 1870static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1871{
1872 struct mlx4_en_priv *priv = netdev_priv(dev);
1873 struct mlx4_en_dev *mdev = priv->mdev;
1874 int i;
c27a02cd 1875
c27a02cd 1876 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1877 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd
YP		 1878
1879 memset(&priv->stats, 0, sizeof(priv->stats));
1880 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1881 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1882 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
c27a02cd
YP		 1883
1884 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1885 priv->tx_ring[i]->bytes = 0;
1886 priv->tx_ring[i]->packets = 0;
1887 priv->tx_ring[i]->tx_csum = 0;
c27a02cd
YP		 1888 }
1889 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1890 priv->rx_ring[i]->bytes = 0;
1891 priv->rx_ring[i]->packets = 0;
1892 priv->rx_ring[i]->csum_ok = 0;
1893 priv->rx_ring[i]->csum_none = 0;
c27a02cd 1894 }
b477ba62
EE		 1895}
1896
1897static int mlx4_en_open(struct net_device *dev)
1898{
1899 struct mlx4_en_priv *priv = netdev_priv(dev);
1900 struct mlx4_en_dev *mdev = priv->mdev;
1901 int err = 0;
1902
1903 mutex_lock(&mdev->state_lock);
1904
1905 if (!mdev->device_up) {
1906 en_err(priv, "Cannot open - device down/disabled\n");
1907 err = -EBUSY;
1908 goto out;
1909 }
1910
1911 /* Reset HW statistics and SW counters */
1912 mlx4_en_clear_stats(dev);
c27a02cd 1913
c27a02cd
YP		 1914 err = mlx4_en_start_port(dev);
1915 if (err)
453a6082 1916 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1917
1918out:
1919 mutex_unlock(&mdev->state_lock);
1920 return err;
1921}
1922
1923
1924static int mlx4_en_close(struct net_device *dev)
1925{
1926 struct mlx4_en_priv *priv = netdev_priv(dev);
1927 struct mlx4_en_dev *mdev = priv->mdev;
1928
453a6082 1929 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 1930
1931 mutex_lock(&mdev->state_lock);
1932
3484aac1 1933 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 1934 netif_carrier_off(dev);
1935
1936 mutex_unlock(&mdev->state_lock);
1937 return 0;
1938}
1939
fe0af03c 1940void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP		 1941{
1942 int i;
1943
1eb8c695
AV		 1944#ifdef CONFIG_RFS_ACCEL
1945 free_irq_cpu_rmap(priv->dev->rx_cpu_rmap);
1946 priv->dev->rx_cpu_rmap = NULL;
1947#endif
1948
c27a02cd 1949 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1950 if (priv->tx_ring && priv->tx_ring[i])
c27a02cd 1951 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
41d942d5 1952 if (priv->tx_cq && priv->tx_cq[i])
fe0af03c 1953 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP		 1954 }
1955
1956 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1957 if (priv->rx_ring[i])
68355f71
TLSC		 1958 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1959 priv->prof->rx_ring_size, priv->stride);
41d942d5 1960 if (priv->rx_cq[i])
fe0af03c 1961 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1962 }
044ca2a5
YP		 1963
1964 if (priv->base_tx_qpn) {
1965 mlx4_qp_release_range(priv->mdev->dev, priv->base_tx_qpn, priv->tx_ring_num);
1966 priv->base_tx_qpn = 0;
1967 }
c27a02cd
YP		 1968}
1969
18cc42a3 1970int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1971{
c27a02cd
YP		 1972 struct mlx4_en_port_profile *prof = priv->prof;
1973 int i;
044ca2a5 1974 int err;
163561a4 1975 int node;
87a5c389 1976
044ca2a5 1977 err = mlx4_qp_reserve_range(priv->mdev->dev, priv->tx_ring_num, 256, &priv->base_tx_qpn);
87a5c389
YP		 1978 if (err) {
1979 en_err(priv, "failed reserving range for TX rings\n");
1980 return err;
1981 }
c27a02cd
YP		 1982
1983 /* Create tx Rings */
1984 for (i = 0; i < priv->tx_ring_num; i++) {
163561a4 1985 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1986 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
163561a4 1987 prof->tx_ring_size, i, TX, node))
c27a02cd
YP		 1988 goto err;
1989
d03a68f8
IS		 1990 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i],
1991 priv->base_tx_qpn + i,
1992 prof->tx_ring_size, TXBB_SIZE,
1993 node, i))
c27a02cd
YP		 1994 goto err;
1995 }
1996
1997 /* Create rx Rings */
1998 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 1999 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2000 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2001 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2002 goto err;
2003
2004 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 2005 prof->rx_ring_size, priv->stride,
2006 node))
c27a02cd
YP		 2007 goto err;
2008 }
2009
1eb8c695 2010#ifdef CONFIG_RFS_ACCEL
a229e488
AV		 2011 if (priv->mdev->dev->caps.comp_pool) {
2012 priv->dev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->mdev->dev->caps.comp_pool);
2013 if (!priv->dev->rx_cpu_rmap)
2014 goto err;
2015 }
1eb8c695
AV		 2016#endif
2017
c27a02cd
YP		 2018 return 0;
2019
2020err:
453a6082 2021 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2022 for (i = 0; i < priv->rx_ring_num; i++) {
2023 if (priv->rx_ring[i])
2024 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2025 prof->rx_ring_size,
2026 priv->stride);
2027 if (priv->rx_cq[i])
2028 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2029 }
2030 for (i = 0; i < priv->tx_ring_num; i++) {
2031 if (priv->tx_ring[i])
2032 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
2033 if (priv->tx_cq[i])
2034 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
2035 }
c27a02cd
YP		 2036 return -ENOMEM;
2037}
2038
2039
2040void mlx4_en_destroy_netdev(struct net_device *dev)
2041{
2042 struct mlx4_en_priv *priv = netdev_priv(dev);
2043 struct mlx4_en_dev *mdev = priv->mdev;
2044
453a6082 2045 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2046
2047 /* Unregister device - this will close the port if it was up */
2048 if (priv->registered)
2049 unregister_netdev(dev);
2050
2051 if (priv->allocated)
2052 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2053
2054 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2055 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2056 /* flush any pending task for this netdev */
2057 flush_workqueue(mdev->workqueue);
2058
2059 /* Detach the netdev so tasks would not attempt to access it */
2060 mutex_lock(&mdev->state_lock);
2061 mdev->pndev[priv->port] = NULL;
2062 mutex_unlock(&mdev->state_lock);
2063
fe0af03c 2064 mlx4_en_free_resources(priv);
564c274c 2065
bc6a4744
AV		 2066 kfree(priv->tx_ring);
2067 kfree(priv->tx_cq);
2068
c27a02cd
YP		 2069 free_netdev(dev);
2070}
2071
2072static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2073{
2074 struct mlx4_en_priv *priv = netdev_priv(dev);
2075 struct mlx4_en_dev *mdev = priv->mdev;
2076 int err = 0;
2077
453a6082 2078 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2079 dev->mtu, new_mtu);
2080
2081 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 2082 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP		 2083 return -EPERM;
2084 }
2085 dev->mtu = new_mtu;
2086
2087 if (netif_running(dev)) {
2088 mutex_lock(&mdev->state_lock);
2089 if (!mdev->device_up) {
2090 /* NIC is probably restarting - let watchdog task reset
2091 * the port */
453a6082 2092 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2093 } else {
3484aac1 2094 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2095 err = mlx4_en_start_port(dev);
2096 if (err) {
453a6082 2097 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2098 priv->port);
2099 queue_work(mdev->workqueue, &priv->watchdog_task);
2100 }
2101 }
2102 mutex_unlock(&mdev->state_lock);
2103 }
2104 return 0;
2105}
2106
100dbda8 2107static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2108{
2109 struct mlx4_en_priv *priv = netdev_priv(dev);
2110 struct mlx4_en_dev *mdev = priv->mdev;
2111 struct hwtstamp_config config;
2112
2113 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2114 return -EFAULT;
2115
2116 /* reserved for future extensions */
2117 if (config.flags)
2118 return -EINVAL;
2119
2120 /* device doesn't support time stamping */
2121 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2122 return -EINVAL;
2123
2124 /* TX HW timestamp */
2125 switch (config.tx_type) {
2126 case HWTSTAMP_TX_OFF:
2127 case HWTSTAMP_TX_ON:
2128 break;
2129 default:
2130 return -ERANGE;
2131 }
2132
2133 /* RX HW timestamp */
2134 switch (config.rx_filter) {
2135 case HWTSTAMP_FILTER_NONE:
2136 break;
2137 case HWTSTAMP_FILTER_ALL:
2138 case HWTSTAMP_FILTER_SOME:
2139 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2140 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2141 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2142 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2143 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2144 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2145 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2146 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2147 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2148 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2149 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2150 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2151 config.rx_filter = HWTSTAMP_FILTER_ALL;
2152 break;
2153 default:
2154 return -ERANGE;
2155 }
2156
2157 if (mlx4_en_timestamp_config(dev, config.tx_type, config.rx_filter)) {
2158 config.tx_type = HWTSTAMP_TX_OFF;
2159 config.rx_filter = HWTSTAMP_FILTER_NONE;
2160 }
2161
2162 return copy_to_user(ifr->ifr_data, &config,
2163 sizeof(config)) ? -EFAULT : 0;
2164}
2165
100dbda8
BH		 2166static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2167{
2168 struct mlx4_en_priv *priv = netdev_priv(dev);
2169
2170 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2171 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2172}
2173
ec693d47
AV		 2174static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2175{
2176 switch (cmd) {
2177 case SIOCSHWTSTAMP:
100dbda8
BH		 2178 return mlx4_en_hwtstamp_set(dev, ifr);
2179 case SIOCGHWTSTAMP:
2180 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2181 default:
2182 return -EOPNOTSUPP;
2183 }
2184}
2185
60d6fe99
AV		 2186static int mlx4_en_set_features(struct net_device *netdev,
2187 netdev_features_t features)
2188{
2189 struct mlx4_en_priv *priv = netdev_priv(netdev);
2190
2191 if (features & NETIF_F_LOOPBACK)
2192 priv->ctrl_flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2193 else
2194 priv->ctrl_flags &=
2195 cpu_to_be32(~MLX4_WQE_CTRL_FORCE_LOOPBACK);
2196
79aeaccd
YB		 2197 mlx4_en_update_loopback_state(netdev, features);
2198
60d6fe99
AV		 2199 return 0;
2200
2201}
2202
8f7ba3ca
RE		 2203static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2204{
2205 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2206 struct mlx4_en_dev *mdev = en_priv->mdev;
9813337a 2207 u64 mac_u64 = mlx4_mac_to_u64(mac);
8f7ba3ca
RE		 2208
2209 if (!is_valid_ether_addr(mac))
2210 return -EINVAL;
2211
2212 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2213}
2214
3f7fb021
RE		 2215static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2216{
2217 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2218 struct mlx4_en_dev *mdev = en_priv->mdev;
2219
2220 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2221}
2222
e6b6a231
RE		 2223static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2224{
2225 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2226 struct mlx4_en_dev *mdev = en_priv->mdev;
2227
2228 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2229}
2230
2cccb9e4
RE		 2231static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2232{
2233 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2234 struct mlx4_en_dev *mdev = en_priv->mdev;
2235
2236 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2237}
8f7ba3ca 2238
948e306d
RE		 2239static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2240{
2241 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2242 struct mlx4_en_dev *mdev = en_priv->mdev;
2243
2244 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2245}
84c86403
HHZ		 2246
2247#define PORT_ID_BYTE_LEN 8
2248static int mlx4_en_get_phys_port_id(struct net_device *dev,
2249 struct netdev_phys_port_id *ppid)
2250{
2251 struct mlx4_en_priv *priv = netdev_priv(dev);
2252 struct mlx4_dev *mdev = priv->mdev->dev;
2253 int i;
2254 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2255
2256 if (!phys_port_id)
2257 return -EOPNOTSUPP;
2258
2259 ppid->id_len = sizeof(phys_port_id);
2260 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2261 ppid->id[i] = phys_port_id & 0xff;
2262 phys_port_id >>= 8;
2263 }
2264 return 0;
2265}
2266
3addc568
SH		 2267static const struct net_device_ops mlx4_netdev_ops = {
2268 .ndo_open = mlx4_en_open,
2269 .ndo_stop = mlx4_en_close,
2270 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2271 .ndo_select_queue = mlx4_en_select_queue,
3addc568 2272 .ndo_get_stats = mlx4_en_get_stats,
0eb74fdd 2273 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2274 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2275 .ndo_validate_addr = eth_validate_addr,
3addc568 2276 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2277 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2278 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2279 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2280 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2281#ifdef CONFIG_NET_POLL_CONTROLLER
2282 .ndo_poll_controller = mlx4_en_netpoll,
2283#endif
60d6fe99 2284 .ndo_set_features = mlx4_en_set_features,
897d7846 2285 .ndo_setup_tc = mlx4_en_setup_tc,
1eb8c695
AV		 2286#ifdef CONFIG_RFS_ACCEL
2287 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2288#endif
e0d1095a 2289#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 2290 .ndo_busy_poll = mlx4_en_low_latency_recv,
9e77a2b8 2291#endif
84c86403 2292 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
3addc568
SH		 2293};
2294
8f7ba3ca
RE		 2295static const struct net_device_ops mlx4_netdev_ops_master = {
2296 .ndo_open = mlx4_en_open,
2297 .ndo_stop = mlx4_en_close,
2298 .ndo_start_xmit = mlx4_en_xmit,
2299 .ndo_select_queue = mlx4_en_select_queue,
2300 .ndo_get_stats = mlx4_en_get_stats,
2301 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2302 .ndo_set_mac_address = mlx4_en_set_mac,
2303 .ndo_validate_addr = eth_validate_addr,
2304 .ndo_change_mtu = mlx4_en_change_mtu,
2305 .ndo_tx_timeout = mlx4_en_tx_timeout,
2306 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2307 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2308 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2309 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
e6b6a231 2310 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2311 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
2cccb9e4 2312 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2313#ifdef CONFIG_NET_POLL_CONTROLLER
2314 .ndo_poll_controller = mlx4_en_netpoll,
2315#endif
2316 .ndo_set_features = mlx4_en_set_features,
2317 .ndo_setup_tc = mlx4_en_setup_tc,
2318#ifdef CONFIG_RFS_ACCEL
2319 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2320#endif
84c86403 2321 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
8f7ba3ca
RE		 2322};
2323
c27a02cd
YP		 2324int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2325 struct mlx4_en_port_profile *prof)
2326{
2327 struct net_device *dev;
2328 struct mlx4_en_priv *priv;
c07cb4b0 2329 int i;
c27a02cd 2330 int err;
ef96f7d4 2331 u64 mac_u64;
c27a02cd 2332
f1593d22 2333 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2334 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2335 if (dev == NULL)
c27a02cd 2336 return -ENOMEM;
c27a02cd 2337
d317966b
AV		 2338 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2339 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2340
c27a02cd 2341 SET_NETDEV_DEV(dev, &mdev->dev->pdev->dev);
76a066f2 2342 dev->dev_port = port - 1;
c27a02cd
YP		 2343
2344 /*
2345 * Initialize driver private data
2346 */
2347
2348 priv = netdev_priv(dev);
2349 memset(priv, 0, sizeof(struct mlx4_en_priv));
2350 priv->dev = dev;
2351 priv->mdev = mdev;
ebf8c9aa 2352 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 2353 priv->prof = prof;
2354 priv->port = port;
2355 priv->port_up = false;
c27a02cd 2356 priv->flags = prof->flags;
60d6fe99
AV		 2357 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2358 MLX4_WQE_CTRL_SOLICITED);
d317966b 2359 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2360 priv->tx_ring_num = prof->tx_ring_num;
d317966b 2361
41d942d5 2362 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS,
d317966b 2363 GFP_KERNEL);
bc6a4744
AV		 2364 if (!priv->tx_ring) {
2365 err = -ENOMEM;
2366 goto out;
2367 }
41d942d5 2368 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS,
d317966b 2369 GFP_KERNEL);
bc6a4744
AV		 2370 if (!priv->tx_cq) {
2371 err = -ENOMEM;
2372 goto out;
2373 }
c27a02cd 2374 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2375 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
c27a02cd
YP		 2376 priv->mac_index = -1;
2377 priv->msg_enable = MLX4_EN_MSG_LEVEL;
2378 spin_lock_init(&priv->stats_lock);
0eb74fdd 2379 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
c27a02cd
YP		 2380 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2381 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2382 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
b6c39bfc 2383 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
564c274c 2384#ifdef CONFIG_MLX4_EN_DCB
540b3a39
OG		 2385 if (!mlx4_is_slave(priv->mdev->dev)) {
2386 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
2387 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2388 } else {
2389 en_info(priv, "enabling only PFC DCB ops\n");
2390 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2391 }
2392 }
564c274c 2393#endif
c27a02cd 2394
c07cb4b0
YB		 2395 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2396 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2397
c27a02cd
YP		 2398 /* Query for default mac and max mtu */
2399 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99
YB		 2400
2401 /* Set default MAC */
2402 dev->addr_len = ETH_ALEN;
2403 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2404 if (!is_valid_ether_addr(dev->dev_addr)) {
ef96f7d4
OG		 2405 if (mlx4_is_slave(priv->mdev->dev)) {
2406 eth_hw_addr_random(dev);
2407 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
9813337a 2408 mac_u64 = mlx4_mac_to_u64(dev->dev_addr);
ef96f7d4
OG		 2409 mdev->dev->caps.def_mac[priv->port] = mac_u64;
2410 } else {
2411 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2412 priv->port, dev->dev_addr);
2413 err = -EINVAL;
2414 goto out;
2415 }
c27a02cd
YP		 2416 }
2417
6bbb6d99
YB		 2418 memcpy(priv->prev_mac, dev->dev_addr, sizeof(priv->prev_mac));
2419
c27a02cd
YP		 2420 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2421 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2422 err = mlx4_en_alloc_resources(priv);
2423 if (err)
2424 goto out;
2425
78fb2de7
AV		 2426#ifdef CONFIG_RFS_ACCEL
2427 INIT_LIST_HEAD(&priv->filters);
2428 spin_lock_init(&priv->filters_lock);
2429#endif
2430
ec693d47
AV		 2431 /* Initialize time stamping config */
2432 priv->hwtstamp_config.flags = 0;
2433 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2434 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2435
c27a02cd
YP		 2436 /* Allocate page for receive rings */
2437 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
2438 MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE);
2439 if (err) {
453a6082 2440 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 2441 goto out;
2442 }
2443 priv->allocated = 1;
2444
c27a02cd
YP		 2445 /*
2446 * Initialize netdev entry points
2447 */
8f7ba3ca
RE		 2448 if (mlx4_is_master(priv->mdev->dev))
2449 dev->netdev_ops = &mlx4_netdev_ops_master;
2450 else
2451 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2452 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH		 2453 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2454 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2455
c27a02cd
YP		 2456 SET_ETHTOOL_OPS(dev, &mlx4_en_ethtool_ops);
2457
c27a02cd
YP		 2458 /*
2459 * Set driver features
2460 */
c8c64cff
MM		 2461 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2462 if (mdev->LSO_support)
2463 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2464
2465 dev->vlan_features = dev->hw_features;
2466
ad86107f 2467 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2468 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 2469 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2470 NETIF_F_HW_VLAN_CTAG_FILTER;
60d6fe99 2471 dev->hw_features |= NETIF_F_LOOPBACK;
c27a02cd 2472
1eb8c695
AV		 2473 if (mdev->dev->caps.steering_mode ==
2474 MLX4_STEERING_MODE_DEVICE_MANAGED)
2475 dev->hw_features |= NETIF_F_NTUPLE;
2476
cc5387f7
YB		 2477 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
2478 dev->priv_flags |= IFF_UNICAST_FLT;
2479
837052d0
OG		 2480 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2481 dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2482 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL;
2483 dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2484 dev->features |= NETIF_F_GSO_UDP_TUNNEL;
2485 }
2486
c27a02cd
YP		 2487 mdev->pndev[port] = dev;
2488
2489 netif_carrier_off(dev);
4801ae70
EE		 2490 mlx4_en_set_default_moderation(priv);
2491
c27a02cd
YP		 2492 err = register_netdev(dev);
2493 if (err) {
453a6082 2494 en_err(priv, "Netdev registration failed for port %d\n", port);
c27a02cd
YP		 2495 goto out;
2496 }
4234144f 2497 priv->registered = 1;
453a6082
YP		 2498
2499 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
2500 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
2501
79aeaccd
YB		 2502 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
2503
90822265 2504 /* Configure port */
5c8e9046 2505 mlx4_en_calc_rx_buf(dev);
90822265 2506 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 2507 priv->rx_skb_size + ETH_FCS_LEN,
2508 prof->tx_pause, prof->tx_ppp,
2509 prof->rx_pause, prof->rx_ppp);
90822265
YP		 2510 if (err) {
2511 en_err(priv, "Failed setting port general configurations "
2512 "for port %d, with error %d\n", priv->port, err);
2513 goto out;
2514 }
2515
837052d0
OG		 2516 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2517 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC);
2518 if (err) {
2519 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
2520 err);
2521 goto out;
2522 }
2523 }
2524
90822265
YP		 2525 /* Init port */
2526 en_warn(priv, "Initializing port\n");
2527 err = mlx4_INIT_PORT(mdev->dev, priv->port);
2528 if (err) {
2529 en_err(priv, "Failed Initializing port\n");
2530 goto out;
2531 }
c27a02cd 2532 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea
AV		 2533
2534 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2535 queue_delayed_work(mdev->workqueue, &priv->service_task,
2536 SERVICE_TASK_DELAY);
2537
c27a02cd
YP		 2538 return 0;
2539
2540out:
2541 mlx4_en_destroy_netdev(dev);
2542 return err;
2543}
2544
Linux 6.x block layer and io_uring tree(s)