Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/kernel.h> | |
35 | #include <linux/ethtool.h> | |
36 | #include <linux/netdevice.h> | |
af22d9de | 37 | #include <linux/mlx4/driver.h> |
7202da8b | 38 | #include <linux/mlx4/device.h> |
f90a3673 HHZ |
39 | #include <linux/in.h> |
40 | #include <net/ip.h> | |
6fcd2735 | 41 | #include <linux/bitmap.h> |
c27a02cd YP |
42 | |
43 | #include "mlx4_en.h" | |
44 | #include "en_port.h" | |
45 | ||
82067281 | 46 | #define EN_ETHTOOL_QP_ATTACH (1ull << 63) |
82067281 HHZ |
47 | #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff) |
48 | #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff) | |
c27a02cd | 49 | |
79c54b6b AV |
50 | static int mlx4_en_moderation_update(struct mlx4_en_priv *priv) |
51 | { | |
52 | int i; | |
53 | int err = 0; | |
54 | ||
55 | for (i = 0; i < priv->tx_ring_num; i++) { | |
41d942d5 EE |
56 | priv->tx_cq[i]->moder_cnt = priv->tx_frames; |
57 | priv->tx_cq[i]->moder_time = priv->tx_usecs; | |
38463e2c | 58 | if (priv->port_up) { |
41d942d5 | 59 | err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]); |
38463e2c EE |
60 | if (err) |
61 | return err; | |
62 | } | |
79c54b6b AV |
63 | } |
64 | ||
65 | if (priv->adaptive_rx_coal) | |
66 | return 0; | |
67 | ||
68 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 EE |
69 | priv->rx_cq[i]->moder_cnt = priv->rx_frames; |
70 | priv->rx_cq[i]->moder_time = priv->rx_usecs; | |
79c54b6b | 71 | priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; |
38463e2c | 72 | if (priv->port_up) { |
41d942d5 | 73 | err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]); |
38463e2c EE |
74 | if (err) |
75 | return err; | |
76 | } | |
79c54b6b AV |
77 | } |
78 | ||
79 | return err; | |
80 | } | |
81 | ||
c27a02cd YP |
82 | static void |
83 | mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) | |
84 | { | |
85 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
86 | struct mlx4_en_dev *mdev = priv->mdev; | |
87 | ||
612a94d6 RJ |
88 | strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); |
89 | strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")", | |
90 | sizeof(drvinfo->version)); | |
91 | snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), | |
92 | "%d.%d.%d", | |
c27a02cd YP |
93 | (u16) (mdev->dev->caps.fw_ver >> 32), |
94 | (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff), | |
95 | (u16) (mdev->dev->caps.fw_ver & 0xffff)); | |
872bf2fb | 96 | strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev), |
612a94d6 | 97 | sizeof(drvinfo->bus_info)); |
c27a02cd YP |
98 | } |
99 | ||
0fef9d03 AV |
100 | static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = { |
101 | "blueflame", | |
e38af4fa | 102 | "phv-bit" |
0fef9d03 AV |
103 | }; |
104 | ||
c27a02cd | 105 | static const char main_strings[][ETH_GSTRING_LEN] = { |
6fcd2735 | 106 | /* main statistics */ |
c27a02cd YP |
107 | "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", |
108 | "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", | |
109 | "rx_length_errors", "rx_over_errors", "rx_crc_errors", | |
110 | "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", | |
111 | "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", | |
112 | "tx_heartbeat_errors", "tx_window_errors", | |
113 | ||
114 | /* port statistics */ | |
fa37a958 | 115 | "tso_packets", |
9fab426d | 116 | "xmit_more", |
c27a02cd | 117 | "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed", |
f8c6455b | 118 | "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload", |
c27a02cd | 119 | |
b42de4d0 EBE |
120 | /* pf statistics */ |
121 | "pf_rx_packets", | |
122 | "pf_rx_bytes", | |
123 | "pf_tx_packets", | |
124 | "pf_tx_bytes", | |
125 | ||
0b131561 MB |
126 | /* priority flow control statistics rx */ |
127 | "rx_pause_prio_0", "rx_pause_duration_prio_0", | |
128 | "rx_pause_transition_prio_0", | |
129 | "rx_pause_prio_1", "rx_pause_duration_prio_1", | |
130 | "rx_pause_transition_prio_1", | |
131 | "rx_pause_prio_2", "rx_pause_duration_prio_2", | |
132 | "rx_pause_transition_prio_2", | |
133 | "rx_pause_prio_3", "rx_pause_duration_prio_3", | |
134 | "rx_pause_transition_prio_3", | |
135 | "rx_pause_prio_4", "rx_pause_duration_prio_4", | |
136 | "rx_pause_transition_prio_4", | |
137 | "rx_pause_prio_5", "rx_pause_duration_prio_5", | |
138 | "rx_pause_transition_prio_5", | |
139 | "rx_pause_prio_6", "rx_pause_duration_prio_6", | |
140 | "rx_pause_transition_prio_6", | |
141 | "rx_pause_prio_7", "rx_pause_duration_prio_7", | |
142 | "rx_pause_transition_prio_7", | |
143 | ||
144 | /* flow control statistics rx */ | |
145 | "rx_pause", "rx_pause_duration", "rx_pause_transition", | |
146 | ||
147 | /* priority flow control statistics tx */ | |
148 | "tx_pause_prio_0", "tx_pause_duration_prio_0", | |
149 | "tx_pause_transition_prio_0", | |
150 | "tx_pause_prio_1", "tx_pause_duration_prio_1", | |
151 | "tx_pause_transition_prio_1", | |
152 | "tx_pause_prio_2", "tx_pause_duration_prio_2", | |
153 | "tx_pause_transition_prio_2", | |
154 | "tx_pause_prio_3", "tx_pause_duration_prio_3", | |
155 | "tx_pause_transition_prio_3", | |
156 | "tx_pause_prio_4", "tx_pause_duration_prio_4", | |
157 | "tx_pause_transition_prio_4", | |
158 | "tx_pause_prio_5", "tx_pause_duration_prio_5", | |
159 | "tx_pause_transition_prio_5", | |
160 | "tx_pause_prio_6", "tx_pause_duration_prio_6", | |
161 | "tx_pause_transition_prio_6", | |
162 | "tx_pause_prio_7", "tx_pause_duration_prio_7", | |
163 | "tx_pause_transition_prio_7", | |
164 | ||
165 | /* flow control statistics tx */ | |
166 | "tx_pause", "tx_pause_duration", "tx_pause_transition", | |
167 | ||
c27a02cd | 168 | /* packet statistics */ |
a3333b35 EBE |
169 | "rx_multicast_packets", |
170 | "rx_broadcast_packets", | |
171 | "rx_jabbers", | |
172 | "rx_in_range_length_error", | |
173 | "rx_out_range_length_error", | |
174 | "tx_multicast_packets", | |
175 | "tx_broadcast_packets", | |
176 | "rx_prio_0_packets", "rx_prio_0_bytes", | |
177 | "rx_prio_1_packets", "rx_prio_1_bytes", | |
178 | "rx_prio_2_packets", "rx_prio_2_bytes", | |
179 | "rx_prio_3_packets", "rx_prio_3_bytes", | |
180 | "rx_prio_4_packets", "rx_prio_4_bytes", | |
181 | "rx_prio_5_packets", "rx_prio_5_bytes", | |
182 | "rx_prio_6_packets", "rx_prio_6_bytes", | |
183 | "rx_prio_7_packets", "rx_prio_7_bytes", | |
184 | "rx_novlan_packets", "rx_novlan_bytes", | |
185 | "tx_prio_0_packets", "tx_prio_0_bytes", | |
186 | "tx_prio_1_packets", "tx_prio_1_bytes", | |
187 | "tx_prio_2_packets", "tx_prio_2_bytes", | |
188 | "tx_prio_3_packets", "tx_prio_3_bytes", | |
189 | "tx_prio_4_packets", "tx_prio_4_bytes", | |
190 | "tx_prio_5_packets", "tx_prio_5_bytes", | |
191 | "tx_prio_6_packets", "tx_prio_6_bytes", | |
192 | "tx_prio_7_packets", "tx_prio_7_bytes", | |
193 | "tx_novlan_packets", "tx_novlan_bytes", | |
194 | ||
c27a02cd | 195 | }; |
c27a02cd | 196 | |
e7c1c2c4 | 197 | static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= { |
fd9071ec | 198 | "Interrupt Test", |
e7c1c2c4 YP |
199 | "Link Test", |
200 | "Speed Test", | |
201 | "Register Test", | |
202 | "Loopback Test", | |
203 | }; | |
204 | ||
c27a02cd YP |
205 | static u32 mlx4_en_get_msglevel(struct net_device *dev) |
206 | { | |
207 | return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable; | |
208 | } | |
209 | ||
210 | static void mlx4_en_set_msglevel(struct net_device *dev, u32 val) | |
211 | { | |
212 | ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val; | |
213 | } | |
214 | ||
215 | static void mlx4_en_get_wol(struct net_device *netdev, | |
216 | struct ethtool_wolinfo *wol) | |
217 | { | |
14c07b13 YP |
218 | struct mlx4_en_priv *priv = netdev_priv(netdev); |
219 | int err = 0; | |
220 | u64 config = 0; | |
559a9f1d | 221 | u64 mask; |
14c07b13 | 222 | |
559a9f1d OD |
223 | if ((priv->port < 1) || (priv->port > 2)) { |
224 | en_err(priv, "Failed to get WoL information\n"); | |
225 | return; | |
226 | } | |
227 | ||
228 | mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : | |
229 | MLX4_DEV_CAP_FLAG_WOL_PORT2; | |
230 | ||
231 | if (!(priv->mdev->dev->caps.flags & mask)) { | |
14c07b13 YP |
232 | wol->supported = 0; |
233 | wol->wolopts = 0; | |
234 | return; | |
235 | } | |
236 | ||
237 | err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); | |
238 | if (err) { | |
239 | en_err(priv, "Failed to get WoL information\n"); | |
240 | return; | |
241 | } | |
242 | ||
243 | if (config & MLX4_EN_WOL_MAGIC) | |
244 | wol->supported = WAKE_MAGIC; | |
245 | else | |
246 | wol->supported = 0; | |
247 | ||
248 | if (config & MLX4_EN_WOL_ENABLED) | |
249 | wol->wolopts = WAKE_MAGIC; | |
250 | else | |
251 | wol->wolopts = 0; | |
252 | } | |
253 | ||
254 | static int mlx4_en_set_wol(struct net_device *netdev, | |
255 | struct ethtool_wolinfo *wol) | |
256 | { | |
257 | struct mlx4_en_priv *priv = netdev_priv(netdev); | |
258 | u64 config = 0; | |
259 | int err = 0; | |
559a9f1d OD |
260 | u64 mask; |
261 | ||
262 | if ((priv->port < 1) || (priv->port > 2)) | |
263 | return -EOPNOTSUPP; | |
264 | ||
265 | mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : | |
266 | MLX4_DEV_CAP_FLAG_WOL_PORT2; | |
14c07b13 | 267 | |
559a9f1d | 268 | if (!(priv->mdev->dev->caps.flags & mask)) |
14c07b13 YP |
269 | return -EOPNOTSUPP; |
270 | ||
271 | if (wol->supported & ~WAKE_MAGIC) | |
272 | return -EINVAL; | |
273 | ||
274 | err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); | |
275 | if (err) { | |
276 | en_err(priv, "Failed to get WoL info, unable to modify\n"); | |
277 | return err; | |
278 | } | |
279 | ||
280 | if (wol->wolopts & WAKE_MAGIC) { | |
281 | config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED | | |
282 | MLX4_EN_WOL_MAGIC; | |
283 | } else { | |
284 | config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC); | |
285 | config |= MLX4_EN_WOL_DO_MODIFY; | |
286 | } | |
287 | ||
288 | err = mlx4_wol_write(priv->mdev->dev, config, priv->port); | |
289 | if (err) | |
290 | en_err(priv, "Failed to set WoL information\n"); | |
291 | ||
292 | return err; | |
c27a02cd YP |
293 | } |
294 | ||
6fcd2735 EBE |
295 | struct bitmap_iterator { |
296 | unsigned long *stats_bitmap; | |
297 | unsigned int count; | |
298 | unsigned int iterator; | |
299 | bool advance_array; /* if set, force no increments */ | |
300 | }; | |
301 | ||
302 | static inline void bitmap_iterator_init(struct bitmap_iterator *h, | |
303 | unsigned long *stats_bitmap, | |
304 | int count) | |
305 | { | |
306 | h->iterator = 0; | |
307 | h->advance_array = !bitmap_empty(stats_bitmap, count); | |
308 | h->count = h->advance_array ? bitmap_weight(stats_bitmap, count) | |
309 | : count; | |
310 | h->stats_bitmap = stats_bitmap; | |
311 | } | |
312 | ||
313 | static inline int bitmap_iterator_test(struct bitmap_iterator *h) | |
314 | { | |
315 | return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap); | |
316 | } | |
317 | ||
318 | static inline int bitmap_iterator_inc(struct bitmap_iterator *h) | |
319 | { | |
320 | return h->iterator++; | |
321 | } | |
322 | ||
323 | static inline unsigned int | |
324 | bitmap_iterator_count(struct bitmap_iterator *h) | |
325 | { | |
326 | return h->count; | |
327 | } | |
328 | ||
c27a02cd YP |
329 | static int mlx4_en_get_sset_count(struct net_device *dev, int sset) |
330 | { | |
331 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
6fcd2735 EBE |
332 | struct bitmap_iterator it; |
333 | ||
3da8a36c | 334 | bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); |
c27a02cd | 335 | |
e7c1c2c4 YP |
336 | switch (sset) { |
337 | case ETH_SS_STATS: | |
6fcd2735 | 338 | return bitmap_iterator_count(&it) + |
8501841a | 339 | (priv->tx_ring_num * 2) + |
d21ed3a3 | 340 | (priv->rx_ring_num * 3); |
e7c1c2c4 | 341 | case ETH_SS_TEST: |
ccf86321 OG |
342 | return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags |
343 | & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2; | |
0fef9d03 AV |
344 | case ETH_SS_PRIV_FLAGS: |
345 | return ARRAY_SIZE(mlx4_en_priv_flags); | |
e7c1c2c4 | 346 | default: |
c27a02cd | 347 | return -EOPNOTSUPP; |
e7c1c2c4 | 348 | } |
c27a02cd YP |
349 | } |
350 | ||
351 | static void mlx4_en_get_ethtool_stats(struct net_device *dev, | |
352 | struct ethtool_stats *stats, uint64_t *data) | |
353 | { | |
354 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
355 | int index = 0; | |
6fcd2735 EBE |
356 | int i; |
357 | struct bitmap_iterator it; | |
358 | ||
3da8a36c | 359 | bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); |
c27a02cd YP |
360 | |
361 | spin_lock_bh(&priv->stats_lock); | |
362 | ||
6fcd2735 EBE |
363 | for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it)) |
364 | if (bitmap_iterator_test(&it)) | |
365 | data[index++] = ((unsigned long *)&priv->stats)[i]; | |
366 | ||
367 | for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it)) | |
368 | if (bitmap_iterator_test(&it)) | |
369 | data[index++] = ((unsigned long *)&priv->port_stats)[i]; | |
370 | ||
b42de4d0 EBE |
371 | for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it)) |
372 | if (bitmap_iterator_test(&it)) | |
373 | data[index++] = | |
374 | ((unsigned long *)&priv->pf_stats)[i]; | |
375 | ||
0b131561 MB |
376 | for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX; |
377 | i++, bitmap_iterator_inc(&it)) | |
378 | if (bitmap_iterator_test(&it)) | |
379 | data[index++] = | |
380 | ((u64 *)&priv->rx_priority_flowstats)[i]; | |
381 | ||
382 | for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it)) | |
383 | if (bitmap_iterator_test(&it)) | |
384 | data[index++] = ((u64 *)&priv->rx_flowstats)[i]; | |
385 | ||
386 | for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX; | |
387 | i++, bitmap_iterator_inc(&it)) | |
388 | if (bitmap_iterator_test(&it)) | |
389 | data[index++] = | |
390 | ((u64 *)&priv->tx_priority_flowstats)[i]; | |
391 | ||
392 | for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it)) | |
393 | if (bitmap_iterator_test(&it)) | |
394 | data[index++] = ((u64 *)&priv->tx_flowstats)[i]; | |
395 | ||
6fcd2735 EBE |
396 | for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it)) |
397 | if (bitmap_iterator_test(&it)) | |
398 | data[index++] = ((unsigned long *)&priv->pkstats)[i]; | |
399 | ||
c27a02cd | 400 | for (i = 0; i < priv->tx_ring_num; i++) { |
41d942d5 EE |
401 | data[index++] = priv->tx_ring[i]->packets; |
402 | data[index++] = priv->tx_ring[i]->bytes; | |
c27a02cd YP |
403 | } |
404 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 EE |
405 | data[index++] = priv->rx_ring[i]->packets; |
406 | data[index++] = priv->rx_ring[i]->bytes; | |
d21ed3a3 | 407 | data[index++] = priv->rx_ring[i]->dropped; |
c27a02cd | 408 | } |
c27a02cd YP |
409 | spin_unlock_bh(&priv->stats_lock); |
410 | ||
411 | } | |
412 | ||
e7c1c2c4 YP |
413 | static void mlx4_en_self_test(struct net_device *dev, |
414 | struct ethtool_test *etest, u64 *buf) | |
415 | { | |
416 | mlx4_en_ex_selftest(dev, &etest->flags, buf); | |
417 | } | |
418 | ||
c27a02cd YP |
419 | static void mlx4_en_get_strings(struct net_device *dev, |
420 | uint32_t stringset, uint8_t *data) | |
421 | { | |
422 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
423 | int index = 0; | |
6fcd2735 EBE |
424 | int i, strings = 0; |
425 | struct bitmap_iterator it; | |
426 | ||
3da8a36c | 427 | bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); |
c27a02cd | 428 | |
e7c1c2c4 YP |
429 | switch (stringset) { |
430 | case ETH_SS_TEST: | |
431 | for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++) | |
432 | strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); | |
ccf86321 | 433 | if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) |
e7c1c2c4 YP |
434 | for (; i < MLX4_EN_NUM_SELF_TEST; i++) |
435 | strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); | |
436 | break; | |
437 | ||
438 | case ETH_SS_STATS: | |
439 | /* Add main counters */ | |
6fcd2735 EBE |
440 | for (i = 0; i < NUM_MAIN_STATS; i++, strings++, |
441 | bitmap_iterator_inc(&it)) | |
442 | if (bitmap_iterator_test(&it)) | |
93ece0c1 | 443 | strcpy(data + (index++) * ETH_GSTRING_LEN, |
6fcd2735 EBE |
444 | main_strings[strings]); |
445 | ||
446 | for (i = 0; i < NUM_PORT_STATS; i++, strings++, | |
447 | bitmap_iterator_inc(&it)) | |
448 | if (bitmap_iterator_test(&it)) | |
93ece0c1 | 449 | strcpy(data + (index++) * ETH_GSTRING_LEN, |
6fcd2735 | 450 | main_strings[strings]); |
b42de4d0 EBE |
451 | |
452 | for (i = 0; i < NUM_PF_STATS; i++, strings++, | |
453 | bitmap_iterator_inc(&it)) | |
454 | if (bitmap_iterator_test(&it)) | |
455 | strcpy(data + (index++) * ETH_GSTRING_LEN, | |
456 | main_strings[strings]); | |
6fcd2735 | 457 | |
0b131561 MB |
458 | for (i = 0; i < NUM_FLOW_STATS; i++, strings++, |
459 | bitmap_iterator_inc(&it)) | |
460 | if (bitmap_iterator_test(&it)) | |
461 | strcpy(data + (index++) * ETH_GSTRING_LEN, | |
462 | main_strings[strings]); | |
463 | ||
6fcd2735 EBE |
464 | for (i = 0; i < NUM_PKT_STATS; i++, strings++, |
465 | bitmap_iterator_inc(&it)) | |
466 | if (bitmap_iterator_test(&it)) | |
93ece0c1 | 467 | strcpy(data + (index++) * ETH_GSTRING_LEN, |
6fcd2735 EBE |
468 | main_strings[strings]); |
469 | ||
e7c1c2c4 YP |
470 | for (i = 0; i < priv->tx_ring_num; i++) { |
471 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
472 | "tx%d_packets", i); | |
473 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
474 | "tx%d_bytes", i); | |
475 | } | |
476 | for (i = 0; i < priv->rx_ring_num; i++) { | |
477 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
478 | "rx%d_packets", i); | |
479 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
480 | "rx%d_bytes", i); | |
d21ed3a3 EBE |
481 | sprintf(data + (index++) * ETH_GSTRING_LEN, |
482 | "rx%d_dropped", i); | |
e7c1c2c4 | 483 | } |
e7c1c2c4 | 484 | break; |
0fef9d03 AV |
485 | case ETH_SS_PRIV_FLAGS: |
486 | for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++) | |
487 | strcpy(data + i * ETH_GSTRING_LEN, | |
488 | mlx4_en_priv_flags[i]); | |
489 | break; | |
490 | ||
e7c1c2c4 | 491 | } |
c27a02cd YP |
492 | } |
493 | ||
2c762679 SM |
494 | static u32 mlx4_en_autoneg_get(struct net_device *dev) |
495 | { | |
496 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
497 | struct mlx4_en_dev *mdev = priv->mdev; | |
498 | u32 autoneg = AUTONEG_DISABLE; | |
499 | ||
500 | if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) && | |
501 | (priv->port_state.flags & MLX4_EN_PORT_ANE)) | |
502 | autoneg = AUTONEG_ENABLE; | |
503 | ||
504 | return autoneg; | |
505 | } | |
506 | ||
3d8f7cc7 DD |
507 | static void ptys2ethtool_update_supported_port(unsigned long *mask, |
508 | struct mlx4_ptys_reg *ptys_reg) | |
2c762679 SM |
509 | { |
510 | u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); | |
511 | ||
512 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) | |
513 | | MLX4_PROT_MASK(MLX4_1000BASE_T) | |
514 | | MLX4_PROT_MASK(MLX4_100BASE_TX))) { | |
3d8f7cc7 DD |
515 | __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask); |
516 | } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) | |
2c762679 SM |
517 | | MLX4_PROT_MASK(MLX4_10GBASE_SR) |
518 | | MLX4_PROT_MASK(MLX4_56GBASE_SR4) | |
519 | | MLX4_PROT_MASK(MLX4_40GBASE_CR4) | |
520 | | MLX4_PROT_MASK(MLX4_40GBASE_SR4) | |
521 | | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { | |
3d8f7cc7 DD |
522 | __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask); |
523 | } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) | |
2c762679 SM |
524 | | MLX4_PROT_MASK(MLX4_40GBASE_KR4) |
525 | | MLX4_PROT_MASK(MLX4_20GBASE_KR2) | |
526 | | MLX4_PROT_MASK(MLX4_10GBASE_KR) | |
527 | | MLX4_PROT_MASK(MLX4_10GBASE_KX4) | |
528 | | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { | |
3d8f7cc7 | 529 | __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask); |
2c762679 | 530 | } |
2c762679 SM |
531 | } |
532 | ||
533 | static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg) | |
534 | { | |
535 | u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper); | |
536 | ||
537 | if (!eth_proto) /* link down */ | |
538 | eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); | |
539 | ||
540 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) | |
541 | | MLX4_PROT_MASK(MLX4_1000BASE_T) | |
542 | | MLX4_PROT_MASK(MLX4_100BASE_TX))) { | |
543 | return PORT_TP; | |
544 | } | |
545 | ||
546 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR) | |
547 | | MLX4_PROT_MASK(MLX4_56GBASE_SR4) | |
548 | | MLX4_PROT_MASK(MLX4_40GBASE_SR4) | |
549 | | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { | |
550 | return PORT_FIBRE; | |
551 | } | |
552 | ||
553 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) | |
554 | | MLX4_PROT_MASK(MLX4_56GBASE_CR4) | |
555 | | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) { | |
556 | return PORT_DA; | |
557 | } | |
558 | ||
559 | if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) | |
560 | | MLX4_PROT_MASK(MLX4_40GBASE_KR4) | |
561 | | MLX4_PROT_MASK(MLX4_20GBASE_KR2) | |
562 | | MLX4_PROT_MASK(MLX4_10GBASE_KR) | |
563 | | MLX4_PROT_MASK(MLX4_10GBASE_KX4) | |
564 | | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { | |
565 | return PORT_NONE; | |
566 | } | |
567 | return PORT_OTHER; | |
568 | } | |
569 | ||
570 | #define MLX4_LINK_MODES_SZ \ | |
571 | (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8) | |
572 | ||
573 | enum ethtool_report { | |
574 | SUPPORTED = 0, | |
575 | ADVERTISED = 1, | |
2c762679 SM |
576 | }; |
577 | ||
3d8f7cc7 DD |
578 | struct ptys2ethtool_config { |
579 | __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); | |
580 | __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); | |
581 | u32 speed; | |
582 | }; | |
583 | ||
584 | static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg, | |
585 | enum ethtool_report report) | |
586 | { | |
587 | switch (report) { | |
588 | case SUPPORTED: | |
589 | return cfg->supported; | |
590 | case ADVERTISED: | |
591 | return cfg->advertised; | |
592 | } | |
593 | return NULL; | |
594 | } | |
595 | ||
596 | #define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \ | |
597 | ({ \ | |
598 | struct ptys2ethtool_config *cfg; \ | |
599 | const unsigned int modes[] = { __VA_ARGS__ }; \ | |
600 | unsigned int i; \ | |
601 | cfg = &ptys2ethtool_map[reg_]; \ | |
602 | cfg->speed = speed_; \ | |
603 | bitmap_zero(cfg->supported, \ | |
604 | __ETHTOOL_LINK_MODE_MASK_NBITS); \ | |
605 | bitmap_zero(cfg->advertised, \ | |
606 | __ETHTOOL_LINK_MODE_MASK_NBITS); \ | |
607 | for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ | |
608 | __set_bit(modes[i], cfg->supported); \ | |
609 | __set_bit(modes[i], cfg->advertised); \ | |
610 | } \ | |
611 | }) | |
612 | ||
2c762679 | 613 | /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */ |
3d8f7cc7 DD |
614 | static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ]; |
615 | ||
616 | void __init mlx4_en_init_ptys2ethtool_map(void) | |
617 | { | |
618 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100, | |
619 | ETHTOOL_LINK_MODE_100baseT_Full_BIT); | |
620 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000, | |
621 | ETHTOOL_LINK_MODE_1000baseT_Full_BIT); | |
622 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000, | |
623 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); | |
624 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000, | |
625 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); | |
626 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000, | |
627 | ETHTOOL_LINK_MODE_10000baseT_Full_BIT); | |
628 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000, | |
629 | ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); | |
630 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000, | |
631 | ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); | |
632 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000, | |
633 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); | |
634 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000, | |
635 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); | |
636 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000, | |
637 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); | |
638 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000, | |
639 | ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT, | |
640 | ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); | |
641 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000, | |
642 | ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); | |
643 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000, | |
644 | ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); | |
645 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000, | |
646 | ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); | |
647 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000, | |
648 | ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); | |
649 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000, | |
650 | ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT); | |
651 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000, | |
652 | ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT); | |
2c762679 SM |
653 | }; |
654 | ||
3d8f7cc7 DD |
655 | static void ptys2ethtool_update_link_modes(unsigned long *link_modes, |
656 | u32 eth_proto, | |
657 | enum ethtool_report report) | |
2c762679 SM |
658 | { |
659 | int i; | |
2c762679 SM |
660 | for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { |
661 | if (eth_proto & MLX4_PROT_MASK(i)) | |
3d8f7cc7 DD |
662 | bitmap_or(link_modes, link_modes, |
663 | ptys2ethtool_link_mode(&ptys2ethtool_map[i], | |
664 | report), | |
665 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
2c762679 | 666 | } |
2c762679 SM |
667 | } |
668 | ||
3d8f7cc7 DD |
669 | static u32 ethtool2ptys_link_modes(const unsigned long *link_modes, |
670 | enum ethtool_report report) | |
d48b3ab4 SM |
671 | { |
672 | int i; | |
673 | u32 ptys_modes = 0; | |
674 | ||
675 | for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { | |
3d8f7cc7 DD |
676 | if (bitmap_intersects( |
677 | ptys2ethtool_link_mode(&ptys2ethtool_map[i], | |
678 | report), | |
679 | link_modes, | |
680 | __ETHTOOL_LINK_MODE_MASK_NBITS)) | |
d48b3ab4 SM |
681 | ptys_modes |= 1 << i; |
682 | } | |
683 | return ptys_modes; | |
684 | } | |
685 | ||
686 | /* Convert actual speed (SPEED_XXX) to ptys link modes */ | |
687 | static u32 speed2ptys_link_modes(u32 speed) | |
688 | { | |
689 | int i; | |
690 | u32 ptys_modes = 0; | |
691 | ||
692 | for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { | |
3d8f7cc7 | 693 | if (ptys2ethtool_map[i].speed == speed) |
d48b3ab4 SM |
694 | ptys_modes |= 1 << i; |
695 | } | |
696 | return ptys_modes; | |
697 | } | |
698 | ||
3d8f7cc7 DD |
699 | static int |
700 | ethtool_get_ptys_link_ksettings(struct net_device *dev, | |
701 | struct ethtool_link_ksettings *link_ksettings) | |
2c762679 SM |
702 | { |
703 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
704 | struct mlx4_ptys_reg ptys_reg; | |
705 | u32 eth_proto; | |
706 | int ret; | |
707 | ||
708 | memset(&ptys_reg, 0, sizeof(ptys_reg)); | |
709 | ptys_reg.local_port = priv->port; | |
710 | ptys_reg.proto_mask = MLX4_PTYS_EN; | |
711 | ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, | |
712 | MLX4_ACCESS_REG_QUERY, &ptys_reg); | |
713 | if (ret) { | |
714 | en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)", | |
715 | ret); | |
716 | return ret; | |
717 | } | |
718 | en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n", | |
719 | ptys_reg.proto_mask); | |
720 | en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n", | |
721 | be32_to_cpu(ptys_reg.eth_proto_cap)); | |
722 | en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n", | |
723 | be32_to_cpu(ptys_reg.eth_proto_admin)); | |
724 | en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n", | |
725 | be32_to_cpu(ptys_reg.eth_proto_oper)); | |
726 | en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n", | |
727 | be32_to_cpu(ptys_reg.eth_proto_lp_adv)); | |
728 | ||
3d8f7cc7 DD |
729 | /* reset supported/advertising masks */ |
730 | ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); | |
731 | ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); | |
2c762679 | 732 | |
3d8f7cc7 DD |
733 | ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported, |
734 | &ptys_reg); | |
2c762679 SM |
735 | |
736 | eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap); | |
3d8f7cc7 DD |
737 | ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported, |
738 | eth_proto, SUPPORTED); | |
2c762679 SM |
739 | |
740 | eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin); | |
3d8f7cc7 DD |
741 | ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising, |
742 | eth_proto, ADVERTISED); | |
2c762679 | 743 | |
3d8f7cc7 DD |
744 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, |
745 | Pause); | |
746 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, | |
747 | Asym_Pause); | |
2c762679 | 748 | |
3d8f7cc7 DD |
749 | if (priv->prof->tx_pause) |
750 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
751 | advertising, Pause); | |
752 | if (priv->prof->tx_pause ^ priv->prof->rx_pause) | |
753 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
754 | advertising, Asym_Pause); | |
2c762679 | 755 | |
3d8f7cc7 | 756 | link_ksettings->base.port = ptys_get_active_port(&ptys_reg); |
2c762679 SM |
757 | |
758 | if (mlx4_en_autoneg_get(dev)) { | |
3d8f7cc7 DD |
759 | ethtool_link_ksettings_add_link_mode(link_ksettings, |
760 | supported, Autoneg); | |
761 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
762 | advertising, Autoneg); | |
2c762679 SM |
763 | } |
764 | ||
3d8f7cc7 DD |
765 | link_ksettings->base.autoneg |
766 | = (priv->port_state.flags & MLX4_EN_PORT_ANC) ? | |
2c762679 SM |
767 | AUTONEG_ENABLE : AUTONEG_DISABLE; |
768 | ||
769 | eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv); | |
2c762679 | 770 | |
3d8f7cc7 DD |
771 | ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising); |
772 | ptys2ethtool_update_link_modes( | |
773 | link_ksettings->link_modes.lp_advertising, | |
774 | eth_proto, ADVERTISED); | |
775 | if (priv->port_state.flags & MLX4_EN_PORT_ANC) | |
776 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
777 | lp_advertising, Autoneg); | |
2c762679 | 778 | |
3d8f7cc7 DD |
779 | link_ksettings->base.phy_address = 0; |
780 | link_ksettings->base.mdio_support = 0; | |
781 | link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID; | |
782 | link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; | |
2c762679 SM |
783 | |
784 | return ret; | |
785 | } | |
786 | ||
3d8f7cc7 DD |
787 | static void |
788 | ethtool_get_default_link_ksettings( | |
789 | struct net_device *dev, struct ethtool_link_ksettings *link_ksettings) | |
c27a02cd | 790 | { |
7699517d YP |
791 | struct mlx4_en_priv *priv = netdev_priv(dev); |
792 | int trans_type; | |
793 | ||
3d8f7cc7 DD |
794 | link_ksettings->base.autoneg = AUTONEG_DISABLE; |
795 | ||
796 | ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); | |
797 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, | |
798 | 10000baseT_Full); | |
7699517d | 799 | |
3d8f7cc7 DD |
800 | ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); |
801 | ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, | |
802 | 10000baseT_Full); | |
803 | ||
804 | trans_type = priv->port_state.transceiver; | |
7699517d | 805 | if (trans_type > 0 && trans_type <= 0xC) { |
3d8f7cc7 DD |
806 | link_ksettings->base.port = PORT_FIBRE; |
807 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
808 | supported, FIBRE); | |
809 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
810 | advertising, FIBRE); | |
7699517d | 811 | } else if (trans_type == 0x80 || trans_type == 0) { |
3d8f7cc7 DD |
812 | link_ksettings->base.port = PORT_TP; |
813 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
814 | supported, TP); | |
815 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
816 | advertising, TP); | |
7699517d | 817 | } else { |
3d8f7cc7 | 818 | link_ksettings->base.port = -1; |
7699517d | 819 | } |
2c762679 SM |
820 | } |
821 | ||
3d8f7cc7 DD |
822 | static int |
823 | mlx4_en_get_link_ksettings(struct net_device *dev, | |
824 | struct ethtool_link_ksettings *link_ksettings) | |
2c762679 SM |
825 | { |
826 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
827 | int ret = -EINVAL; | |
828 | ||
829 | if (mlx4_en_QUERY_PORT(priv->mdev, priv->port)) | |
830 | return -ENOMEM; | |
831 | ||
832 | en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n", | |
833 | priv->port_state.flags & MLX4_EN_PORT_ANC, | |
834 | priv->port_state.flags & MLX4_EN_PORT_ANE); | |
835 | ||
836 | if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) | |
3d8f7cc7 | 837 | ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings); |
2c762679 | 838 | if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */ |
3d8f7cc7 | 839 | ethtool_get_default_link_ksettings(dev, link_ksettings); |
2c762679 SM |
840 | |
841 | if (netif_carrier_ok(dev)) { | |
3d8f7cc7 DD |
842 | link_ksettings->base.speed = priv->port_state.link_speed; |
843 | link_ksettings->base.duplex = DUPLEX_FULL; | |
2c762679 | 844 | } else { |
3d8f7cc7 DD |
845 | link_ksettings->base.speed = SPEED_UNKNOWN; |
846 | link_ksettings->base.duplex = DUPLEX_UNKNOWN; | |
2c762679 | 847 | } |
c27a02cd YP |
848 | return 0; |
849 | } | |
850 | ||
d48b3ab4 SM |
851 | /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */ |
852 | static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed, | |
853 | __be32 proto_cap) | |
854 | { | |
855 | __be32 proto_admin = 0; | |
856 | ||
857 | if (!speed) { /* Speed = 0 ==> Reset Link modes */ | |
858 | proto_admin = proto_cap; | |
859 | en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n", | |
860 | be32_to_cpu(proto_cap)); | |
861 | } else { | |
862 | u32 ptys_link_modes = speed2ptys_link_modes(speed); | |
863 | ||
864 | proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap; | |
865 | en_info(priv, "Setting Speed to %d\n", speed); | |
866 | } | |
867 | return proto_admin; | |
868 | } | |
869 | ||
3d8f7cc7 DD |
870 | static int |
871 | mlx4_en_set_link_ksettings(struct net_device *dev, | |
872 | const struct ethtool_link_ksettings *link_ksettings) | |
c27a02cd | 873 | { |
d48b3ab4 SM |
874 | struct mlx4_en_priv *priv = netdev_priv(dev); |
875 | struct mlx4_ptys_reg ptys_reg; | |
876 | __be32 proto_admin; | |
877 | int ret; | |
878 | ||
3d8f7cc7 DD |
879 | u32 ptys_adv = ethtool2ptys_link_modes( |
880 | link_ksettings->link_modes.advertising, ADVERTISED); | |
881 | const int speed = link_ksettings->base.speed; | |
d48b3ab4 | 882 | |
3d8f7cc7 DD |
883 | en_dbg(DRV, priv, |
884 | "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n", | |
885 | speed, __ETHTOOL_LINK_MODE_MASK_NBITS, | |
886 | link_ksettings->link_modes.advertising, | |
887 | link_ksettings->base.autoneg, | |
888 | link_ksettings->base.duplex); | |
d48b3ab4 | 889 | |
3d8f7cc7 DD |
890 | if (!(priv->mdev->dev->caps.flags2 & |
891 | MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) || | |
892 | (link_ksettings->base.duplex == DUPLEX_HALF)) | |
c27a02cd YP |
893 | return -EINVAL; |
894 | ||
d48b3ab4 SM |
895 | memset(&ptys_reg, 0, sizeof(ptys_reg)); |
896 | ptys_reg.local_port = priv->port; | |
897 | ptys_reg.proto_mask = MLX4_PTYS_EN; | |
898 | ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, | |
899 | MLX4_ACCESS_REG_QUERY, &ptys_reg); | |
900 | if (ret) { | |
901 | en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n", | |
902 | ret); | |
903 | return 0; | |
904 | } | |
905 | ||
3d8f7cc7 | 906 | proto_admin = link_ksettings->base.autoneg == AUTONEG_ENABLE ? |
5a228c03 SM |
907 | cpu_to_be32(ptys_adv) : |
908 | speed_set_ptys_admin(priv, speed, | |
909 | ptys_reg.eth_proto_cap); | |
d48b3ab4 SM |
910 | |
911 | proto_admin &= ptys_reg.eth_proto_cap; | |
d48b3ab4 SM |
912 | if (!proto_admin) { |
913 | en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n"); | |
914 | return -EINVAL; /* nothing to change due to bad input */ | |
915 | } | |
916 | ||
5a228c03 SM |
917 | if (proto_admin == ptys_reg.eth_proto_admin) |
918 | return 0; /* Nothing to change */ | |
919 | ||
d48b3ab4 SM |
920 | en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n", |
921 | be32_to_cpu(proto_admin)); | |
922 | ||
923 | ptys_reg.eth_proto_admin = proto_admin; | |
924 | ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE, | |
925 | &ptys_reg); | |
926 | if (ret) { | |
927 | en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)", | |
928 | be32_to_cpu(ptys_reg.eth_proto_admin), ret); | |
929 | return ret; | |
930 | } | |
931 | ||
d48b3ab4 SM |
932 | mutex_lock(&priv->mdev->state_lock); |
933 | if (priv->port_up) { | |
5a228c03 | 934 | en_warn(priv, "Port link mode changed, restarting port...\n"); |
d48b3ab4 SM |
935 | mlx4_en_stop_port(dev, 1); |
936 | if (mlx4_en_start_port(dev)) | |
937 | en_err(priv, "Failed restarting port %d\n", priv->port); | |
938 | } | |
939 | mutex_unlock(&priv->mdev->state_lock); | |
c27a02cd YP |
940 | return 0; |
941 | } | |
942 | ||
943 | static int mlx4_en_get_coalesce(struct net_device *dev, | |
944 | struct ethtool_coalesce *coal) | |
945 | { | |
946 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
947 | ||
a19a848a YP |
948 | coal->tx_coalesce_usecs = priv->tx_usecs; |
949 | coal->tx_max_coalesced_frames = priv->tx_frames; | |
fbc6daf1 AV |
950 | coal->tx_max_coalesced_frames_irq = priv->tx_work_limit; |
951 | ||
c27a02cd YP |
952 | coal->rx_coalesce_usecs = priv->rx_usecs; |
953 | coal->rx_max_coalesced_frames = priv->rx_frames; | |
954 | ||
955 | coal->pkt_rate_low = priv->pkt_rate_low; | |
956 | coal->rx_coalesce_usecs_low = priv->rx_usecs_low; | |
957 | coal->pkt_rate_high = priv->pkt_rate_high; | |
958 | coal->rx_coalesce_usecs_high = priv->rx_usecs_high; | |
959 | coal->rate_sample_interval = priv->sample_interval; | |
960 | coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal; | |
fbc6daf1 | 961 | |
c27a02cd YP |
962 | return 0; |
963 | } | |
964 | ||
965 | static int mlx4_en_set_coalesce(struct net_device *dev, | |
966 | struct ethtool_coalesce *coal) | |
967 | { | |
968 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd | 969 | |
fbc6daf1 AV |
970 | if (!coal->tx_max_coalesced_frames_irq) |
971 | return -EINVAL; | |
972 | ||
c27a02cd YP |
973 | priv->rx_frames = (coal->rx_max_coalesced_frames == |
974 | MLX4_EN_AUTO_CONF) ? | |
3db36fb2 | 975 | MLX4_EN_RX_COAL_TARGET : |
c27a02cd YP |
976 | coal->rx_max_coalesced_frames; |
977 | priv->rx_usecs = (coal->rx_coalesce_usecs == | |
978 | MLX4_EN_AUTO_CONF) ? | |
979 | MLX4_EN_RX_COAL_TIME : | |
980 | coal->rx_coalesce_usecs; | |
981 | ||
a19a848a YP |
982 | /* Setting TX coalescing parameters */ |
983 | if (coal->tx_coalesce_usecs != priv->tx_usecs || | |
984 | coal->tx_max_coalesced_frames != priv->tx_frames) { | |
985 | priv->tx_usecs = coal->tx_coalesce_usecs; | |
986 | priv->tx_frames = coal->tx_max_coalesced_frames; | |
a19a848a YP |
987 | } |
988 | ||
c27a02cd YP |
989 | /* Set adaptive coalescing params */ |
990 | priv->pkt_rate_low = coal->pkt_rate_low; | |
991 | priv->rx_usecs_low = coal->rx_coalesce_usecs_low; | |
992 | priv->pkt_rate_high = coal->pkt_rate_high; | |
993 | priv->rx_usecs_high = coal->rx_coalesce_usecs_high; | |
994 | priv->sample_interval = coal->rate_sample_interval; | |
995 | priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce; | |
fbc6daf1 | 996 | priv->tx_work_limit = coal->tx_max_coalesced_frames_irq; |
c27a02cd | 997 | |
79c54b6b | 998 | return mlx4_en_moderation_update(priv); |
c27a02cd YP |
999 | } |
1000 | ||
1001 | static int mlx4_en_set_pauseparam(struct net_device *dev, | |
1002 | struct ethtool_pauseparam *pause) | |
1003 | { | |
1004 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1005 | struct mlx4_en_dev *mdev = priv->mdev; | |
1006 | int err; | |
1007 | ||
278d436a IV |
1008 | if (pause->autoneg) |
1009 | return -EINVAL; | |
1010 | ||
d53b93f2 YP |
1011 | priv->prof->tx_pause = pause->tx_pause != 0; |
1012 | priv->prof->rx_pause = pause->rx_pause != 0; | |
c27a02cd YP |
1013 | err = mlx4_SET_PORT_general(mdev->dev, priv->port, |
1014 | priv->rx_skb_size + ETH_FCS_LEN, | |
d53b93f2 YP |
1015 | priv->prof->tx_pause, |
1016 | priv->prof->tx_ppp, | |
1017 | priv->prof->rx_pause, | |
1018 | priv->prof->rx_ppp); | |
c27a02cd | 1019 | if (err) |
453a6082 | 1020 | en_err(priv, "Failed setting pause params\n"); |
0b131561 MB |
1021 | else |
1022 | mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap, | |
1023 | priv->prof->rx_ppp, | |
1024 | priv->prof->rx_pause, | |
1025 | priv->prof->tx_ppp, | |
1026 | priv->prof->tx_pause); | |
c27a02cd YP |
1027 | |
1028 | return err; | |
1029 | } | |
1030 | ||
1031 | static void mlx4_en_get_pauseparam(struct net_device *dev, | |
1032 | struct ethtool_pauseparam *pause) | |
1033 | { | |
1034 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd | 1035 | |
d53b93f2 YP |
1036 | pause->tx_pause = priv->prof->tx_pause; |
1037 | pause->rx_pause = priv->prof->rx_pause; | |
c27a02cd YP |
1038 | } |
1039 | ||
18cc42a3 YP |
1040 | static int mlx4_en_set_ringparam(struct net_device *dev, |
1041 | struct ethtool_ringparam *param) | |
1042 | { | |
1043 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1044 | struct mlx4_en_dev *mdev = priv->mdev; | |
1045 | u32 rx_size, tx_size; | |
1046 | int port_up = 0; | |
1047 | int err = 0; | |
1048 | ||
1049 | if (param->rx_jumbo_pending || param->rx_mini_pending) | |
1050 | return -EINVAL; | |
1051 | ||
1052 | rx_size = roundup_pow_of_two(param->rx_pending); | |
1053 | rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE); | |
bd531e36 | 1054 | rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE); |
18cc42a3 YP |
1055 | tx_size = roundup_pow_of_two(param->tx_pending); |
1056 | tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE); | |
bd531e36 | 1057 | tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE); |
18cc42a3 | 1058 | |
41d942d5 EE |
1059 | if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size : |
1060 | priv->rx_ring[0]->size) && | |
1061 | tx_size == priv->tx_ring[0]->size) | |
18cc42a3 YP |
1062 | return 0; |
1063 | ||
1064 | mutex_lock(&mdev->state_lock); | |
1065 | if (priv->port_up) { | |
1066 | port_up = 1; | |
3484aac1 | 1067 | mlx4_en_stop_port(dev, 1); |
18cc42a3 YP |
1068 | } |
1069 | ||
fe0af03c | 1070 | mlx4_en_free_resources(priv); |
18cc42a3 YP |
1071 | |
1072 | priv->prof->tx_ring_size = tx_size; | |
1073 | priv->prof->rx_ring_size = rx_size; | |
1074 | ||
1075 | err = mlx4_en_alloc_resources(priv); | |
1076 | if (err) { | |
453a6082 | 1077 | en_err(priv, "Failed reallocating port resources\n"); |
18cc42a3 YP |
1078 | goto out; |
1079 | } | |
1080 | if (port_up) { | |
1081 | err = mlx4_en_start_port(dev); | |
1082 | if (err) | |
453a6082 | 1083 | en_err(priv, "Failed starting port\n"); |
18cc42a3 YP |
1084 | } |
1085 | ||
79c54b6b | 1086 | err = mlx4_en_moderation_update(priv); |
6b4d8d9f | 1087 | |
18cc42a3 YP |
1088 | out: |
1089 | mutex_unlock(&mdev->state_lock); | |
1090 | return err; | |
1091 | } | |
1092 | ||
c27a02cd YP |
1093 | static void mlx4_en_get_ringparam(struct net_device *dev, |
1094 | struct ethtool_ringparam *param) | |
1095 | { | |
1096 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
1097 | |
1098 | memset(param, 0, sizeof(*param)); | |
bd531e36 YP |
1099 | param->rx_max_pending = MLX4_EN_MAX_RX_SIZE; |
1100 | param->tx_max_pending = MLX4_EN_MAX_TX_SIZE; | |
bc081cec | 1101 | param->rx_pending = priv->port_up ? |
41d942d5 EE |
1102 | priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size; |
1103 | param->tx_pending = priv->tx_ring[0]->size; | |
c27a02cd YP |
1104 | } |
1105 | ||
93d3e367 YP |
1106 | static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev) |
1107 | { | |
1108 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1109 | ||
1110 | return priv->rx_ring_num; | |
1111 | } | |
1112 | ||
b9d1ab7e ED |
1113 | static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev) |
1114 | { | |
1115 | return MLX4_EN_RSS_KEY_SIZE; | |
1116 | } | |
1117 | ||
947cbb0a EP |
1118 | static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc) |
1119 | { | |
1120 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1121 | ||
1122 | /* check if requested function is supported by the device */ | |
b3706909 AV |
1123 | if (hfunc == ETH_RSS_HASH_TOP) { |
1124 | if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) | |
1125 | return -EINVAL; | |
1126 | if (!(dev->features & NETIF_F_RXHASH)) | |
1127 | en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n"); | |
1128 | return 0; | |
1129 | } else if (hfunc == ETH_RSS_HASH_XOR) { | |
1130 | if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR)) | |
1131 | return -EINVAL; | |
1132 | if (dev->features & NETIF_F_RXHASH) | |
1133 | en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n"); | |
1134 | return 0; | |
1135 | } | |
947cbb0a | 1136 | |
b3706909 | 1137 | return -EINVAL; |
947cbb0a EP |
1138 | } |
1139 | ||
892311f6 EP |
1140 | static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key, |
1141 | u8 *hfunc) | |
93d3e367 YP |
1142 | { |
1143 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1144 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1145 | int rss_rings; | |
1146 | size_t n = priv->rx_ring_num; | |
1147 | int err = 0; | |
1148 | ||
1149 | rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num; | |
d5ec899a | 1150 | rss_rings = 1 << ilog2(rss_rings); |
93d3e367 YP |
1151 | |
1152 | while (n--) { | |
892311f6 EP |
1153 | if (!ring_index) |
1154 | break; | |
93d3e367 YP |
1155 | ring_index[n] = rss_map->qps[n % rss_rings].qpn - |
1156 | rss_map->base_qpn; | |
1157 | } | |
b9d1ab7e | 1158 | if (key) |
bd635c35 | 1159 | memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE); |
892311f6 | 1160 | if (hfunc) |
947cbb0a | 1161 | *hfunc = priv->rss_hash_fn; |
93d3e367 YP |
1162 | return err; |
1163 | } | |
1164 | ||
fe62d001 | 1165 | static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index, |
892311f6 | 1166 | const u8 *key, const u8 hfunc) |
93d3e367 YP |
1167 | { |
1168 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1169 | struct mlx4_en_dev *mdev = priv->mdev; | |
1170 | int port_up = 0; | |
1171 | int err = 0; | |
1172 | int i; | |
1173 | int rss_rings = 0; | |
1174 | ||
1175 | /* Calculate RSS table size and make sure flows are spread evenly | |
1176 | * between rings | |
1177 | */ | |
1178 | for (i = 0; i < priv->rx_ring_num; i++) { | |
bd635c35 ED |
1179 | if (!ring_index) |
1180 | continue; | |
93d3e367 YP |
1181 | if (i > 0 && !ring_index[i] && !rss_rings) |
1182 | rss_rings = i; | |
1183 | ||
1184 | if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num))) | |
1185 | return -EINVAL; | |
1186 | } | |
1187 | ||
1188 | if (!rss_rings) | |
1189 | rss_rings = priv->rx_ring_num; | |
1190 | ||
1191 | /* RSS table size must be an order of 2 */ | |
1192 | if (!is_power_of_2(rss_rings)) | |
1193 | return -EINVAL; | |
1194 | ||
947cbb0a EP |
1195 | if (hfunc != ETH_RSS_HASH_NO_CHANGE) { |
1196 | err = mlx4_en_check_rxfh_func(dev, hfunc); | |
1197 | if (err) | |
1198 | return err; | |
1199 | } | |
1200 | ||
93d3e367 YP |
1201 | mutex_lock(&mdev->state_lock); |
1202 | if (priv->port_up) { | |
1203 | port_up = 1; | |
3484aac1 | 1204 | mlx4_en_stop_port(dev, 1); |
93d3e367 YP |
1205 | } |
1206 | ||
bd635c35 ED |
1207 | if (ring_index) |
1208 | priv->prof->rss_rings = rss_rings; | |
1209 | if (key) | |
1210 | memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE); | |
b3706909 AV |
1211 | if (hfunc != ETH_RSS_HASH_NO_CHANGE) |
1212 | priv->rss_hash_fn = hfunc; | |
947cbb0a | 1213 | |
93d3e367 YP |
1214 | if (port_up) { |
1215 | err = mlx4_en_start_port(dev); | |
1216 | if (err) | |
1217 | en_err(priv, "Failed starting port\n"); | |
1218 | } | |
1219 | ||
1220 | mutex_unlock(&mdev->state_lock); | |
1221 | return err; | |
1222 | } | |
1223 | ||
82067281 HHZ |
1224 | #define all_zeros_or_all_ones(field) \ |
1225 | ((field) == 0 || (field) == (__force typeof(field))-1) | |
1226 | ||
1227 | static int mlx4_en_validate_flow(struct net_device *dev, | |
1228 | struct ethtool_rxnfc *cmd) | |
1229 | { | |
1230 | struct ethtool_usrip4_spec *l3_mask; | |
1231 | struct ethtool_tcpip4_spec *l4_mask; | |
1232 | struct ethhdr *eth_mask; | |
82067281 HHZ |
1233 | |
1234 | if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) | |
1235 | return -EINVAL; | |
1236 | ||
520dfe3a YB |
1237 | if (cmd->fs.flow_type & FLOW_MAC_EXT) { |
1238 | /* dest mac mask must be ff:ff:ff:ff:ff:ff */ | |
1239 | if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest)) | |
1240 | return -EINVAL; | |
1241 | } | |
1242 | ||
1243 | switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { | |
82067281 HHZ |
1244 | case TCP_V4_FLOW: |
1245 | case UDP_V4_FLOW: | |
1246 | if (cmd->fs.m_u.tcp_ip4_spec.tos) | |
1247 | return -EINVAL; | |
1248 | l4_mask = &cmd->fs.m_u.tcp_ip4_spec; | |
1249 | /* don't allow mask which isn't all 0 or 1 */ | |
1250 | if (!all_zeros_or_all_ones(l4_mask->ip4src) || | |
1251 | !all_zeros_or_all_ones(l4_mask->ip4dst) || | |
1252 | !all_zeros_or_all_ones(l4_mask->psrc) || | |
1253 | !all_zeros_or_all_ones(l4_mask->pdst)) | |
1254 | return -EINVAL; | |
1255 | break; | |
1256 | case IP_USER_FLOW: | |
1257 | l3_mask = &cmd->fs.m_u.usr_ip4_spec; | |
1258 | if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto || | |
1259 | cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 || | |
1260 | (!l3_mask->ip4src && !l3_mask->ip4dst) || | |
1261 | !all_zeros_or_all_ones(l3_mask->ip4src) || | |
1262 | !all_zeros_or_all_ones(l3_mask->ip4dst)) | |
1263 | return -EINVAL; | |
1264 | break; | |
1265 | case ETHER_FLOW: | |
1266 | eth_mask = &cmd->fs.m_u.ether_spec; | |
1267 | /* source mac mask must not be set */ | |
c402b947 | 1268 | if (!is_zero_ether_addr(eth_mask->h_source)) |
82067281 HHZ |
1269 | return -EINVAL; |
1270 | ||
1271 | /* dest mac mask must be ff:ff:ff:ff:ff:ff */ | |
c402b947 | 1272 | if (!is_broadcast_ether_addr(eth_mask->h_dest)) |
82067281 HHZ |
1273 | return -EINVAL; |
1274 | ||
1275 | if (!all_zeros_or_all_ones(eth_mask->h_proto)) | |
1276 | return -EINVAL; | |
1277 | break; | |
1278 | default: | |
1279 | return -EINVAL; | |
1280 | } | |
1281 | ||
1282 | if ((cmd->fs.flow_type & FLOW_EXT)) { | |
1283 | if (cmd->fs.m_ext.vlan_etype || | |
8258bd27 HHZ |
1284 | !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == |
1285 | 0 || | |
1286 | (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == | |
1287 | cpu_to_be16(VLAN_VID_MASK))) | |
82067281 | 1288 | return -EINVAL; |
8258bd27 | 1289 | |
69d7126b HHZ |
1290 | if (cmd->fs.m_ext.vlan_tci) { |
1291 | if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID) | |
1292 | return -EINVAL; | |
8258bd27 | 1293 | |
69d7126b | 1294 | } |
82067281 HHZ |
1295 | } |
1296 | ||
1297 | return 0; | |
1298 | } | |
1299 | ||
f90a3673 HHZ |
1300 | static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd, |
1301 | struct list_head *rule_list_h, | |
1302 | struct mlx4_spec_list *spec_l2, | |
1303 | unsigned char *mac) | |
1304 | { | |
1305 | int err = 0; | |
1306 | __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16); | |
1307 | ||
1308 | spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH; | |
1309 | memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN); | |
1310 | memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN); | |
1311 | ||
8258bd27 HHZ |
1312 | if ((cmd->fs.flow_type & FLOW_EXT) && |
1313 | (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) { | |
f90a3673 | 1314 | spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci; |
8258bd27 | 1315 | spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK); |
f90a3673 HHZ |
1316 | } |
1317 | ||
1318 | list_add_tail(&spec_l2->list, rule_list_h); | |
1319 | ||
1320 | return err; | |
1321 | } | |
1322 | ||
1323 | static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv, | |
1324 | struct ethtool_rxnfc *cmd, | |
1325 | struct list_head *rule_list_h, | |
1326 | struct mlx4_spec_list *spec_l2, | |
1327 | __be32 ipv4_dst) | |
1328 | { | |
f9d96862 | 1329 | #ifdef CONFIG_INET |
f90a3673 HHZ |
1330 | unsigned char mac[ETH_ALEN]; |
1331 | ||
1332 | if (!ipv4_is_multicast(ipv4_dst)) { | |
6bbb6d99 | 1333 | if (cmd->fs.flow_type & FLOW_MAC_EXT) |
f90a3673 | 1334 | memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN); |
6bbb6d99 YB |
1335 | else |
1336 | memcpy(&mac, priv->dev->dev_addr, ETH_ALEN); | |
f90a3673 HHZ |
1337 | } else { |
1338 | ip_eth_mc_map(ipv4_dst, mac); | |
1339 | } | |
1340 | ||
1341 | return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]); | |
f9d96862 HHZ |
1342 | #else |
1343 | return -EINVAL; | |
1344 | #endif | |
f90a3673 HHZ |
1345 | } |
1346 | ||
82067281 | 1347 | static int add_ip_rule(struct mlx4_en_priv *priv, |
f90a3673 HHZ |
1348 | struct ethtool_rxnfc *cmd, |
1349 | struct list_head *list_h) | |
82067281 | 1350 | { |
377d9739 | 1351 | int err; |
f90a3673 HHZ |
1352 | struct mlx4_spec_list *spec_l2 = NULL; |
1353 | struct mlx4_spec_list *spec_l3 = NULL; | |
82067281 HHZ |
1354 | struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec; |
1355 | ||
f90a3673 HHZ |
1356 | spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); |
1357 | spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); | |
1358 | if (!spec_l2 || !spec_l3) { | |
377d9739 HHZ |
1359 | err = -ENOMEM; |
1360 | goto free_spec; | |
82067281 HHZ |
1361 | } |
1362 | ||
377d9739 HHZ |
1363 | err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2, |
1364 | cmd->fs.h_u. | |
1365 | usr_ip4_spec.ip4dst); | |
1366 | if (err) | |
1367 | goto free_spec; | |
82067281 HHZ |
1368 | spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; |
1369 | spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src; | |
1370 | if (l3_mask->ip4src) | |
1371 | spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1372 | spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst; | |
1373 | if (l3_mask->ip4dst) | |
1374 | spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1375 | list_add_tail(&spec_l3->list, list_h); | |
1376 | ||
1377 | return 0; | |
377d9739 HHZ |
1378 | |
1379 | free_spec: | |
1380 | kfree(spec_l2); | |
1381 | kfree(spec_l3); | |
1382 | return err; | |
82067281 HHZ |
1383 | } |
1384 | ||
1385 | static int add_tcp_udp_rule(struct mlx4_en_priv *priv, | |
1386 | struct ethtool_rxnfc *cmd, | |
1387 | struct list_head *list_h, int proto) | |
1388 | { | |
377d9739 | 1389 | int err; |
f90a3673 HHZ |
1390 | struct mlx4_spec_list *spec_l2 = NULL; |
1391 | struct mlx4_spec_list *spec_l3 = NULL; | |
1392 | struct mlx4_spec_list *spec_l4 = NULL; | |
82067281 HHZ |
1393 | struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec; |
1394 | ||
f90a3673 HHZ |
1395 | spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); |
1396 | spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); | |
1397 | spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL); | |
1398 | if (!spec_l2 || !spec_l3 || !spec_l4) { | |
377d9739 HHZ |
1399 | err = -ENOMEM; |
1400 | goto free_spec; | |
82067281 HHZ |
1401 | } |
1402 | ||
1403 | spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; | |
1404 | ||
1405 | if (proto == TCP_V4_FLOW) { | |
377d9739 HHZ |
1406 | err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, |
1407 | spec_l2, | |
1408 | cmd->fs.h_u. | |
1409 | tcp_ip4_spec.ip4dst); | |
1410 | if (err) | |
1411 | goto free_spec; | |
82067281 HHZ |
1412 | spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP; |
1413 | spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src; | |
1414 | spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst; | |
1415 | spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc; | |
1416 | spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst; | |
1417 | } else { | |
377d9739 HHZ |
1418 | err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, |
1419 | spec_l2, | |
1420 | cmd->fs.h_u. | |
1421 | udp_ip4_spec.ip4dst); | |
1422 | if (err) | |
1423 | goto free_spec; | |
82067281 HHZ |
1424 | spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP; |
1425 | spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src; | |
1426 | spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst; | |
1427 | spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc; | |
1428 | spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst; | |
1429 | } | |
1430 | ||
1431 | if (l4_mask->ip4src) | |
1432 | spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1433 | if (l4_mask->ip4dst) | |
1434 | spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1435 | ||
1436 | if (l4_mask->psrc) | |
1437 | spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK; | |
1438 | if (l4_mask->pdst) | |
1439 | spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK; | |
1440 | ||
1441 | list_add_tail(&spec_l3->list, list_h); | |
1442 | list_add_tail(&spec_l4->list, list_h); | |
1443 | ||
1444 | return 0; | |
377d9739 HHZ |
1445 | |
1446 | free_spec: | |
1447 | kfree(spec_l2); | |
1448 | kfree(spec_l3); | |
1449 | kfree(spec_l4); | |
1450 | return err; | |
82067281 HHZ |
1451 | } |
1452 | ||
1453 | static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev, | |
1454 | struct ethtool_rxnfc *cmd, | |
1455 | struct list_head *rule_list_h) | |
1456 | { | |
1457 | int err; | |
82067281 | 1458 | struct ethhdr *eth_spec; |
82067281 | 1459 | struct mlx4_spec_list *spec_l2; |
f90a3673 | 1460 | struct mlx4_en_priv *priv = netdev_priv(dev); |
82067281 HHZ |
1461 | |
1462 | err = mlx4_en_validate_flow(dev, cmd); | |
1463 | if (err) | |
1464 | return err; | |
1465 | ||
520dfe3a | 1466 | switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { |
82067281 | 1467 | case ETHER_FLOW: |
f90a3673 HHZ |
1468 | spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); |
1469 | if (!spec_l2) | |
1470 | return -ENOMEM; | |
1471 | ||
82067281 | 1472 | eth_spec = &cmd->fs.h_u.ether_spec; |
f90a3673 HHZ |
1473 | mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, |
1474 | ð_spec->h_dest[0]); | |
82067281 HHZ |
1475 | spec_l2->eth.ether_type = eth_spec->h_proto; |
1476 | if (eth_spec->h_proto) | |
1477 | spec_l2->eth.ether_type_enable = 1; | |
1478 | break; | |
1479 | case IP_USER_FLOW: | |
1480 | err = add_ip_rule(priv, cmd, rule_list_h); | |
1481 | break; | |
1482 | case TCP_V4_FLOW: | |
1483 | err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW); | |
1484 | break; | |
1485 | case UDP_V4_FLOW: | |
1486 | err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW); | |
1487 | break; | |
1488 | } | |
1489 | ||
1490 | return err; | |
1491 | } | |
1492 | ||
1493 | static int mlx4_en_flow_replace(struct net_device *dev, | |
1494 | struct ethtool_rxnfc *cmd) | |
1495 | { | |
1496 | int err; | |
1497 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1498 | struct ethtool_flow_id *loc_rule; | |
1499 | struct mlx4_spec_list *spec, *tmp_spec; | |
1500 | u32 qpn; | |
1501 | u64 reg_id; | |
1502 | ||
1503 | struct mlx4_net_trans_rule rule = { | |
1504 | .queue_mode = MLX4_NET_TRANS_Q_FIFO, | |
1505 | .exclusive = 0, | |
1506 | .allow_loopback = 1, | |
f9162539 | 1507 | .promisc_mode = MLX4_FS_REGULAR, |
82067281 HHZ |
1508 | }; |
1509 | ||
1510 | rule.port = priv->port; | |
1511 | rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location; | |
1512 | INIT_LIST_HEAD(&rule.list); | |
1513 | ||
1514 | /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */ | |
1515 | if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC) | |
cabdc8ee | 1516 | qpn = priv->drop_qp.qpn; |
82067281 HHZ |
1517 | else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) { |
1518 | qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1); | |
1519 | } else { | |
1520 | if (cmd->fs.ring_cookie >= priv->rx_ring_num) { | |
1a91de28 | 1521 | en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n", |
82067281 HHZ |
1522 | cmd->fs.ring_cookie); |
1523 | return -EINVAL; | |
1524 | } | |
1525 | qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn; | |
1526 | if (!qpn) { | |
1a91de28 | 1527 | en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n", |
82067281 HHZ |
1528 | cmd->fs.ring_cookie); |
1529 | return -EINVAL; | |
1530 | } | |
1531 | } | |
1532 | rule.qpn = qpn; | |
1533 | err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list); | |
1534 | if (err) | |
1535 | goto out_free_list; | |
1536 | ||
1537 | loc_rule = &priv->ethtool_rules[cmd->fs.location]; | |
1538 | if (loc_rule->id) { | |
1539 | err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id); | |
1540 | if (err) { | |
1541 | en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n", | |
1542 | cmd->fs.location, loc_rule->id); | |
1543 | goto out_free_list; | |
1544 | } | |
1545 | loc_rule->id = 0; | |
1546 | memset(&loc_rule->flow_spec, 0, | |
1547 | sizeof(struct ethtool_rx_flow_spec)); | |
0d256c0e | 1548 | list_del(&loc_rule->list); |
82067281 HHZ |
1549 | } |
1550 | err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id); | |
1551 | if (err) { | |
1a91de28 | 1552 | en_err(priv, "Fail to attach network rule at location %d\n", |
82067281 HHZ |
1553 | cmd->fs.location); |
1554 | goto out_free_list; | |
1555 | } | |
1556 | loc_rule->id = reg_id; | |
1557 | memcpy(&loc_rule->flow_spec, &cmd->fs, | |
1558 | sizeof(struct ethtool_rx_flow_spec)); | |
0d256c0e | 1559 | list_add_tail(&loc_rule->list, &priv->ethtool_list); |
82067281 HHZ |
1560 | |
1561 | out_free_list: | |
1562 | list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) { | |
1563 | list_del(&spec->list); | |
1564 | kfree(spec); | |
1565 | } | |
1566 | return err; | |
1567 | } | |
1568 | ||
1569 | static int mlx4_en_flow_detach(struct net_device *dev, | |
1570 | struct ethtool_rxnfc *cmd) | |
1571 | { | |
1572 | int err = 0; | |
1573 | struct ethtool_flow_id *rule; | |
1574 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1575 | ||
1576 | if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) | |
1577 | return -EINVAL; | |
1578 | ||
1579 | rule = &priv->ethtool_rules[cmd->fs.location]; | |
1580 | if (!rule->id) { | |
1581 | err = -ENOENT; | |
1582 | goto out; | |
1583 | } | |
1584 | ||
1585 | err = mlx4_flow_detach(priv->mdev->dev, rule->id); | |
1586 | if (err) { | |
1587 | en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n", | |
1588 | cmd->fs.location, rule->id); | |
1589 | goto out; | |
1590 | } | |
1591 | rule->id = 0; | |
1592 | memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec)); | |
0d256c0e | 1593 | list_del(&rule->list); |
82067281 HHZ |
1594 | out: |
1595 | return err; | |
1596 | ||
1597 | } | |
1598 | ||
1599 | static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, | |
1600 | int loc) | |
1601 | { | |
1602 | int err = 0; | |
1603 | struct ethtool_flow_id *rule; | |
1604 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1605 | ||
1606 | if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) | |
1607 | return -EINVAL; | |
1608 | ||
1609 | rule = &priv->ethtool_rules[loc]; | |
1610 | if (rule->id) | |
1611 | memcpy(&cmd->fs, &rule->flow_spec, | |
1612 | sizeof(struct ethtool_rx_flow_spec)); | |
1613 | else | |
1614 | err = -ENOENT; | |
1615 | ||
1616 | return err; | |
1617 | } | |
1618 | ||
1619 | static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv) | |
1620 | { | |
1621 | ||
1622 | int i, res = 0; | |
1623 | for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { | |
1624 | if (priv->ethtool_rules[i].id) | |
1625 | res++; | |
1626 | } | |
1627 | return res; | |
1628 | ||
1629 | } | |
1630 | ||
93d3e367 YP |
1631 | static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, |
1632 | u32 *rule_locs) | |
1633 | { | |
1634 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
82067281 | 1635 | struct mlx4_en_dev *mdev = priv->mdev; |
93d3e367 | 1636 | int err = 0; |
82067281 HHZ |
1637 | int i = 0, priority = 0; |
1638 | ||
1639 | if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT || | |
1640 | cmd->cmd == ETHTOOL_GRXCLSRULE || | |
1641 | cmd->cmd == ETHTOOL_GRXCLSRLALL) && | |
280fce1e HHZ |
1642 | (mdev->dev->caps.steering_mode != |
1643 | MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)) | |
82067281 | 1644 | return -EINVAL; |
93d3e367 YP |
1645 | |
1646 | switch (cmd->cmd) { | |
1647 | case ETHTOOL_GRXRINGS: | |
1648 | cmd->data = priv->rx_ring_num; | |
1649 | break; | |
82067281 HHZ |
1650 | case ETHTOOL_GRXCLSRLCNT: |
1651 | cmd->rule_cnt = mlx4_en_get_num_flows(priv); | |
1652 | break; | |
1653 | case ETHTOOL_GRXCLSRULE: | |
1654 | err = mlx4_en_get_flow(dev, cmd, cmd->fs.location); | |
1655 | break; | |
1656 | case ETHTOOL_GRXCLSRLALL: | |
1657 | while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) { | |
1658 | err = mlx4_en_get_flow(dev, cmd, i); | |
1659 | if (!err) | |
1660 | rule_locs[priority++] = i; | |
1661 | i++; | |
1662 | } | |
1663 | err = 0; | |
1664 | break; | |
93d3e367 YP |
1665 | default: |
1666 | err = -EOPNOTSUPP; | |
1667 | break; | |
1668 | } | |
1669 | ||
1670 | return err; | |
1671 | } | |
1672 | ||
82067281 HHZ |
1673 | static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) |
1674 | { | |
1675 | int err = 0; | |
1676 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1677 | struct mlx4_en_dev *mdev = priv->mdev; | |
1678 | ||
280fce1e HHZ |
1679 | if (mdev->dev->caps.steering_mode != |
1680 | MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up) | |
82067281 HHZ |
1681 | return -EINVAL; |
1682 | ||
1683 | switch (cmd->cmd) { | |
1684 | case ETHTOOL_SRXCLSRLINS: | |
1685 | err = mlx4_en_flow_replace(dev, cmd); | |
1686 | break; | |
1687 | case ETHTOOL_SRXCLSRLDEL: | |
1688 | err = mlx4_en_flow_detach(dev, cmd); | |
1689 | break; | |
1690 | default: | |
1691 | en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd); | |
1692 | return -EINVAL; | |
1693 | } | |
1694 | ||
1695 | return err; | |
1696 | } | |
1697 | ||
d317966b AV |
1698 | static void mlx4_en_get_channels(struct net_device *dev, |
1699 | struct ethtool_channels *channel) | |
1700 | { | |
1701 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1702 | ||
1703 | memset(channel, 0, sizeof(*channel)); | |
1704 | ||
1705 | channel->max_rx = MAX_RX_RINGS; | |
1706 | channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP; | |
1707 | ||
1708 | channel->rx_count = priv->rx_ring_num; | |
1709 | channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP; | |
1710 | } | |
1711 | ||
1712 | static int mlx4_en_set_channels(struct net_device *dev, | |
1713 | struct ethtool_channels *channel) | |
1714 | { | |
1715 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1716 | struct mlx4_en_dev *mdev = priv->mdev; | |
da26a625 | 1717 | int port_up = 0; |
d317966b AV |
1718 | int err = 0; |
1719 | ||
1720 | if (channel->other_count || channel->combined_count || | |
1721 | channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP || | |
1722 | channel->rx_count > MAX_RX_RINGS || | |
1723 | !channel->tx_count || !channel->rx_count) | |
1724 | return -EINVAL; | |
1725 | ||
1726 | mutex_lock(&mdev->state_lock); | |
1727 | if (priv->port_up) { | |
1728 | port_up = 1; | |
3484aac1 | 1729 | mlx4_en_stop_port(dev, 1); |
d317966b AV |
1730 | } |
1731 | ||
1732 | mlx4_en_free_resources(priv); | |
1733 | ||
1734 | priv->num_tx_rings_p_up = channel->tx_count; | |
1735 | priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP; | |
1736 | priv->rx_ring_num = channel->rx_count; | |
1737 | ||
1738 | err = mlx4_en_alloc_resources(priv); | |
1739 | if (err) { | |
1740 | en_err(priv, "Failed reallocating port resources\n"); | |
1741 | goto out; | |
1742 | } | |
1743 | ||
1744 | netif_set_real_num_tx_queues(dev, priv->tx_ring_num); | |
1745 | netif_set_real_num_rx_queues(dev, priv->rx_ring_num); | |
1746 | ||
f5b6345b IS |
1747 | if (dev->num_tc) |
1748 | mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP); | |
d317966b AV |
1749 | |
1750 | en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num); | |
1751 | en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num); | |
1752 | ||
1753 | if (port_up) { | |
1754 | err = mlx4_en_start_port(dev); | |
1755 | if (err) | |
1756 | en_err(priv, "Failed starting port\n"); | |
1757 | } | |
1758 | ||
1759 | err = mlx4_en_moderation_update(priv); | |
1760 | ||
1761 | out: | |
1762 | mutex_unlock(&mdev->state_lock); | |
1763 | return err; | |
1764 | } | |
1765 | ||
ec693d47 AV |
1766 | static int mlx4_en_get_ts_info(struct net_device *dev, |
1767 | struct ethtool_ts_info *info) | |
1768 | { | |
1769 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1770 | struct mlx4_en_dev *mdev = priv->mdev; | |
1771 | int ret; | |
1772 | ||
1773 | ret = ethtool_op_get_ts_info(dev, info); | |
1774 | if (ret) | |
1775 | return ret; | |
1776 | ||
1777 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { | |
1778 | info->so_timestamping |= | |
1779 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1780 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1781 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1782 | ||
1783 | info->tx_types = | |
1784 | (1 << HWTSTAMP_TX_OFF) | | |
1785 | (1 << HWTSTAMP_TX_ON); | |
1786 | ||
1787 | info->rx_filters = | |
1788 | (1 << HWTSTAMP_FILTER_NONE) | | |
1789 | (1 << HWTSTAMP_FILTER_ALL); | |
ad7d4eae SB |
1790 | |
1791 | if (mdev->ptp_clock) | |
1792 | info->phc_index = ptp_clock_index(mdev->ptp_clock); | |
ec693d47 AV |
1793 | } |
1794 | ||
1795 | return ret; | |
1796 | } | |
1797 | ||
3f6148e7 | 1798 | static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags) |
0fef9d03 AV |
1799 | { |
1800 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
e38af4fa | 1801 | struct mlx4_en_dev *mdev = priv->mdev; |
0fef9d03 AV |
1802 | bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); |
1803 | bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
e38af4fa HHZ |
1804 | bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV); |
1805 | bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV); | |
0fef9d03 | 1806 | int i; |
e38af4fa | 1807 | int ret = 0; |
0fef9d03 | 1808 | |
7c509a48 HHZ |
1809 | if (bf_enabled_new != bf_enabled_old) { |
1810 | if (bf_enabled_new) { | |
1811 | bool bf_supported = true; | |
0fef9d03 | 1812 | |
7c509a48 HHZ |
1813 | for (i = 0; i < priv->tx_ring_num; i++) |
1814 | bf_supported &= priv->tx_ring[i]->bf_alloced; | |
0fef9d03 | 1815 | |
7c509a48 HHZ |
1816 | if (!bf_supported) { |
1817 | en_err(priv, "BlueFlame is not supported\n"); | |
1818 | return -EINVAL; | |
1819 | } | |
0fef9d03 | 1820 | |
7c509a48 HHZ |
1821 | priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME; |
1822 | } else { | |
1823 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
0fef9d03 AV |
1824 | } |
1825 | ||
7c509a48 HHZ |
1826 | for (i = 0; i < priv->tx_ring_num; i++) |
1827 | priv->tx_ring[i]->bf_enabled = bf_enabled_new; | |
0fef9d03 | 1828 | |
7c509a48 HHZ |
1829 | en_info(priv, "BlueFlame %s\n", |
1830 | bf_enabled_new ? "Enabled" : "Disabled"); | |
1831 | } | |
0fef9d03 | 1832 | |
e38af4fa HHZ |
1833 | if (phv_enabled_new != phv_enabled_old) { |
1834 | ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new); | |
1835 | if (ret) | |
1836 | return ret; | |
1837 | else if (phv_enabled_new) | |
1838 | priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV; | |
1839 | else | |
1840 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV; | |
1841 | en_info(priv, "PHV bit %s\n", | |
1842 | phv_enabled_new ? "Enabled" : "Disabled"); | |
1843 | } | |
0fef9d03 AV |
1844 | return 0; |
1845 | } | |
1846 | ||
3f6148e7 | 1847 | static u32 mlx4_en_get_priv_flags(struct net_device *dev) |
0fef9d03 AV |
1848 | { |
1849 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1850 | ||
1851 | return priv->pflags; | |
1852 | } | |
1853 | ||
1556b874 ED |
1854 | static int mlx4_en_get_tunable(struct net_device *dev, |
1855 | const struct ethtool_tunable *tuna, | |
1856 | void *data) | |
1857 | { | |
1858 | const struct mlx4_en_priv *priv = netdev_priv(dev); | |
1859 | int ret = 0; | |
1860 | ||
1861 | switch (tuna->id) { | |
1862 | case ETHTOOL_TX_COPYBREAK: | |
1863 | *(u32 *)data = priv->prof->inline_thold; | |
1864 | break; | |
1865 | default: | |
1866 | ret = -EINVAL; | |
1867 | break; | |
1868 | } | |
1869 | ||
1870 | return ret; | |
1871 | } | |
1872 | ||
1873 | static int mlx4_en_set_tunable(struct net_device *dev, | |
1874 | const struct ethtool_tunable *tuna, | |
1875 | const void *data) | |
1876 | { | |
1877 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1878 | int val, ret = 0; | |
1879 | ||
1880 | switch (tuna->id) { | |
1881 | case ETHTOOL_TX_COPYBREAK: | |
1882 | val = *(u32 *)data; | |
1883 | if (val < MIN_PKT_LEN || val > MAX_INLINE) | |
1884 | ret = -EINVAL; | |
1885 | else | |
1886 | priv->prof->inline_thold = val; | |
1887 | break; | |
1888 | default: | |
1889 | ret = -EINVAL; | |
1890 | break; | |
1891 | } | |
1892 | ||
1893 | return ret; | |
1894 | } | |
1895 | ||
7202da8b SM |
1896 | static int mlx4_en_get_module_info(struct net_device *dev, |
1897 | struct ethtool_modinfo *modinfo) | |
1898 | { | |
1899 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1900 | struct mlx4_en_dev *mdev = priv->mdev; | |
1901 | int ret; | |
1902 | u8 data[4]; | |
1903 | ||
1904 | /* Read first 2 bytes to get Module & REV ID */ | |
1905 | ret = mlx4_get_module_info(mdev->dev, priv->port, | |
1906 | 0/*offset*/, 2/*size*/, data); | |
1907 | if (ret < 2) | |
1908 | return -EIO; | |
1909 | ||
1910 | switch (data[0] /* identifier */) { | |
1911 | case MLX4_MODULE_ID_QSFP: | |
1912 | modinfo->type = ETH_MODULE_SFF_8436; | |
1913 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1914 | break; | |
1915 | case MLX4_MODULE_ID_QSFP_PLUS: | |
1916 | if (data[1] >= 0x3) { /* revision id */ | |
1917 | modinfo->type = ETH_MODULE_SFF_8636; | |
1918 | modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; | |
1919 | } else { | |
1920 | modinfo->type = ETH_MODULE_SFF_8436; | |
1921 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1922 | } | |
1923 | break; | |
1924 | case MLX4_MODULE_ID_QSFP28: | |
1925 | modinfo->type = ETH_MODULE_SFF_8636; | |
1926 | modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; | |
1927 | break; | |
1928 | case MLX4_MODULE_ID_SFP: | |
1929 | modinfo->type = ETH_MODULE_SFF_8472; | |
1930 | modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; | |
1931 | break; | |
1932 | default: | |
1933 | return -ENOSYS; | |
1934 | } | |
1935 | ||
1936 | return 0; | |
1937 | } | |
1938 | ||
1939 | static int mlx4_en_get_module_eeprom(struct net_device *dev, | |
1940 | struct ethtool_eeprom *ee, | |
1941 | u8 *data) | |
1942 | { | |
1943 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1944 | struct mlx4_en_dev *mdev = priv->mdev; | |
1945 | int offset = ee->offset; | |
1946 | int i = 0, ret; | |
1947 | ||
1948 | if (ee->len == 0) | |
1949 | return -EINVAL; | |
1950 | ||
1951 | memset(data, 0, ee->len); | |
1952 | ||
1953 | while (i < ee->len) { | |
1954 | en_dbg(DRV, priv, | |
1955 | "mlx4_get_module_info i(%d) offset(%d) len(%d)\n", | |
1956 | i, offset, ee->len - i); | |
1957 | ||
1958 | ret = mlx4_get_module_info(mdev->dev, priv->port, | |
1959 | offset, ee->len - i, data + i); | |
1960 | ||
1961 | if (!ret) /* Done reading */ | |
1962 | return 0; | |
1963 | ||
1964 | if (ret < 0) { | |
1965 | en_err(priv, | |
1966 | "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n", | |
1967 | i, offset, ee->len - i, ret); | |
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | i += ret; | |
1972 | offset += ret; | |
1973 | } | |
1974 | return 0; | |
1975 | } | |
0fef9d03 | 1976 | |
51af33cf IS |
1977 | static int mlx4_en_set_phys_id(struct net_device *dev, |
1978 | enum ethtool_phys_id_state state) | |
1979 | { | |
1980 | int err; | |
1981 | u16 beacon_duration; | |
1982 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1983 | struct mlx4_en_dev *mdev = priv->mdev; | |
1984 | ||
1985 | if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON)) | |
1986 | return -EOPNOTSUPP; | |
1987 | ||
1988 | switch (state) { | |
1989 | case ETHTOOL_ID_ACTIVE: | |
1990 | beacon_duration = PORT_BEACON_MAX_LIMIT; | |
1991 | break; | |
1992 | case ETHTOOL_ID_INACTIVE: | |
1993 | beacon_duration = 0; | |
1994 | break; | |
1995 | default: | |
1996 | return -EOPNOTSUPP; | |
1997 | } | |
1998 | ||
1999 | err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration); | |
2000 | return err; | |
2001 | } | |
2002 | ||
c27a02cd YP |
2003 | const struct ethtool_ops mlx4_en_ethtool_ops = { |
2004 | .get_drvinfo = mlx4_en_get_drvinfo, | |
3d8f7cc7 DD |
2005 | .get_link_ksettings = mlx4_en_get_link_ksettings, |
2006 | .set_link_ksettings = mlx4_en_set_link_ksettings, | |
c27a02cd | 2007 | .get_link = ethtool_op_get_link, |
c27a02cd YP |
2008 | .get_strings = mlx4_en_get_strings, |
2009 | .get_sset_count = mlx4_en_get_sset_count, | |
2010 | .get_ethtool_stats = mlx4_en_get_ethtool_stats, | |
e7c1c2c4 | 2011 | .self_test = mlx4_en_self_test, |
51af33cf | 2012 | .set_phys_id = mlx4_en_set_phys_id, |
c27a02cd | 2013 | .get_wol = mlx4_en_get_wol, |
14c07b13 | 2014 | .set_wol = mlx4_en_set_wol, |
c27a02cd YP |
2015 | .get_msglevel = mlx4_en_get_msglevel, |
2016 | .set_msglevel = mlx4_en_set_msglevel, | |
2017 | .get_coalesce = mlx4_en_get_coalesce, | |
2018 | .set_coalesce = mlx4_en_set_coalesce, | |
2019 | .get_pauseparam = mlx4_en_get_pauseparam, | |
2020 | .set_pauseparam = mlx4_en_set_pauseparam, | |
2021 | .get_ringparam = mlx4_en_get_ringparam, | |
18cc42a3 | 2022 | .set_ringparam = mlx4_en_set_ringparam, |
93d3e367 | 2023 | .get_rxnfc = mlx4_en_get_rxnfc, |
82067281 | 2024 | .set_rxnfc = mlx4_en_set_rxnfc, |
93d3e367 | 2025 | .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size, |
b9d1ab7e | 2026 | .get_rxfh_key_size = mlx4_en_get_rxfh_key_size, |
fe62d001 BH |
2027 | .get_rxfh = mlx4_en_get_rxfh, |
2028 | .set_rxfh = mlx4_en_set_rxfh, | |
d317966b AV |
2029 | .get_channels = mlx4_en_get_channels, |
2030 | .set_channels = mlx4_en_set_channels, | |
ec693d47 | 2031 | .get_ts_info = mlx4_en_get_ts_info, |
0fef9d03 AV |
2032 | .set_priv_flags = mlx4_en_set_priv_flags, |
2033 | .get_priv_flags = mlx4_en_get_priv_flags, | |
1556b874 ED |
2034 | .get_tunable = mlx4_en_get_tunable, |
2035 | .set_tunable = mlx4_en_set_tunable, | |
7202da8b SM |
2036 | .get_module_info = mlx4_en_get_module_info, |
2037 | .get_module_eeprom = mlx4_en_get_module_eeprom | |
c27a02cd YP |
2038 | }; |
2039 | ||
2040 | ||
2041 | ||
2042 | ||
2043 |