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net/mlx4_en: Use PTYS register to query ethtool settings
[linux-block.git] / drivers / net / ethernet / mellanox / mlx4 / en_ethtool.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/ethtool.h>
36#include <linux/netdevice.h>
af22d9de 37#include <linux/mlx4/driver.h>
7202da8b 38#include <linux/mlx4/device.h>
f90a3673
HHZ		 39#include <linux/in.h>
40#include <net/ip.h>
c27a02cd
YP		 41
42#include "mlx4_en.h"
43#include "en_port.h"
44
82067281 45#define EN_ETHTOOL_QP_ATTACH (1ull << 63)
82067281
HHZ		 46#define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
47#define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
c27a02cd 48
79c54b6b
AV		 49static int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
50{
51 int i;
52 int err = 0;
53
54 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 55 priv->tx_cq[i]->moder_cnt = priv->tx_frames;
56 priv->tx_cq[i]->moder_time = priv->tx_usecs;
38463e2c 57 if (priv->port_up) {
41d942d5 58 err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]);
38463e2c
EE		 59 if (err)
60 return err;
61 }
79c54b6b
AV		 62 }
63
64 if (priv->adaptive_rx_coal)
65 return 0;
66
67 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 68 priv->rx_cq[i]->moder_cnt = priv->rx_frames;
69 priv->rx_cq[i]->moder_time = priv->rx_usecs;
79c54b6b 70 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
38463e2c 71 if (priv->port_up) {
41d942d5 72 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
38463e2c
EE		 73 if (err)
74 return err;
75 }
79c54b6b
AV		 76 }
77
78 return err;
79}
80
c27a02cd
YP		 81static void
82mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
83{
84 struct mlx4_en_priv *priv = netdev_priv(dev);
85 struct mlx4_en_dev *mdev = priv->mdev;
86
612a94d6
RJ		 87 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
88 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")",
89 sizeof(drvinfo->version));
90 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
91 "%d.%d.%d",
c27a02cd
YP		 92 (u16) (mdev->dev->caps.fw_ver >> 32),
93 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
94 (u16) (mdev->dev->caps.fw_ver & 0xffff));
612a94d6
RJ		 95 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->pdev),
96 sizeof(drvinfo->bus_info));
c27a02cd
YP		 97 drvinfo->n_stats = 0;
98 drvinfo->regdump_len = 0;
99 drvinfo->eedump_len = 0;
100}
101
0fef9d03
AV		 102static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
103 "blueflame",
104};
105
c27a02cd
YP		 106static const char main_strings[][ETH_GSTRING_LEN] = {
107 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
108 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
109 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
110 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
111 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
112 "tx_heartbeat_errors", "tx_window_errors",
113
114 /* port statistics */
fa37a958 115 "tso_packets",
9fab426d 116 "xmit_more",
c27a02cd
YP		 117 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed",
118 "rx_csum_good", "rx_csum_none", "tx_chksum_offload",
119
120 /* packet statistics */
121 "broadcast", "rx_prio_0", "rx_prio_1", "rx_prio_2", "rx_prio_3",
122 "rx_prio_4", "rx_prio_5", "rx_prio_6", "rx_prio_7", "tx_prio_0",
123 "tx_prio_1", "tx_prio_2", "tx_prio_3", "tx_prio_4", "tx_prio_5",
124 "tx_prio_6", "tx_prio_7",
125};
d61702f1 126#define NUM_MAIN_STATS 21
c27a02cd
YP		 127#define NUM_ALL_STATS (NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PKT_STATS + NUM_PERF_STATS)
128
e7c1c2c4 129static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
fd9071ec 130 "Interrupt Test",
e7c1c2c4
YP		 131 "Link Test",
132 "Speed Test",
133 "Register Test",
134 "Loopback Test",
135};
136
c27a02cd
YP		 137static u32 mlx4_en_get_msglevel(struct net_device *dev)
138{
139 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
140}
141
142static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
143{
144 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
145}
146
147static void mlx4_en_get_wol(struct net_device *netdev,
148 struct ethtool_wolinfo *wol)
149{
14c07b13
YP		 150 struct mlx4_en_priv *priv = netdev_priv(netdev);
151 int err = 0;
152 u64 config = 0;
559a9f1d 153 u64 mask;
14c07b13 154
559a9f1d
OD		 155 if ((priv->port < 1) || (priv->port > 2)) {
156 en_err(priv, "Failed to get WoL information\n");
157 return;
158 }
159
160 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
161 MLX4_DEV_CAP_FLAG_WOL_PORT2;
162
163 if (!(priv->mdev->dev->caps.flags & mask)) {
14c07b13
YP		 164 wol->supported = 0;
165 wol->wolopts = 0;
166 return;
167 }
168
169 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
170 if (err) {
171 en_err(priv, "Failed to get WoL information\n");
172 return;
173 }
174
175 if (config & MLX4_EN_WOL_MAGIC)
176 wol->supported = WAKE_MAGIC;
177 else
178 wol->supported = 0;
179
180 if (config & MLX4_EN_WOL_ENABLED)
181 wol->wolopts = WAKE_MAGIC;
182 else
183 wol->wolopts = 0;
184}
185
186static int mlx4_en_set_wol(struct net_device *netdev,
187 struct ethtool_wolinfo *wol)
188{
189 struct mlx4_en_priv *priv = netdev_priv(netdev);
190 u64 config = 0;
191 int err = 0;
559a9f1d
OD		 192 u64 mask;
193
194 if ((priv->port < 1) || (priv->port > 2))
195 return -EOPNOTSUPP;
196
197 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
198 MLX4_DEV_CAP_FLAG_WOL_PORT2;
14c07b13 199
559a9f1d 200 if (!(priv->mdev->dev->caps.flags & mask))
14c07b13
YP		 201 return -EOPNOTSUPP;
202
203 if (wol->supported & ~WAKE_MAGIC)
204 return -EINVAL;
205
206 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
207 if (err) {
208 en_err(priv, "Failed to get WoL info, unable to modify\n");
209 return err;
210 }
211
212 if (wol->wolopts & WAKE_MAGIC) {
213 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
214 MLX4_EN_WOL_MAGIC;
215 } else {
216 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
217 config |= MLX4_EN_WOL_DO_MODIFY;
218 }
219
220 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
221 if (err)
222 en_err(priv, "Failed to set WoL information\n");
223
224 return err;
c27a02cd
YP		 225}
226
227static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
228{
229 struct mlx4_en_priv *priv = netdev_priv(dev);
93ece0c1 230 int bit_count = hweight64(priv->stats_bitmap);
c27a02cd 231
e7c1c2c4
YP		 232 switch (sset) {
233 case ETH_SS_STATS:
93ece0c1 234 return (priv->stats_bitmap ? bit_count : NUM_ALL_STATS) +
8501841a 235 (priv->tx_ring_num * 2) +
e0d1095a 236#ifdef CONFIG_NET_RX_BUSY_POLL
8501841a
AV		 237 (priv->rx_ring_num * 5);
238#else
239 (priv->rx_ring_num * 2);
240#endif
e7c1c2c4 241 case ETH_SS_TEST:
ccf86321
OG		 242 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
243 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
0fef9d03
AV		 244 case ETH_SS_PRIV_FLAGS:
245 return ARRAY_SIZE(mlx4_en_priv_flags);
e7c1c2c4 246 default:
c27a02cd 247 return -EOPNOTSUPP;
e7c1c2c4 248 }
c27a02cd
YP		 249}
250
251static void mlx4_en_get_ethtool_stats(struct net_device *dev,
252 struct ethtool_stats *stats, uint64_t *data)
253{
254 struct mlx4_en_priv *priv = netdev_priv(dev);
255 int index = 0;
93ece0c1 256 int i, j = 0;
c27a02cd
YP		 257
258 spin_lock_bh(&priv->stats_lock);
259
93ece0c1
EE		 260 if (!(priv->stats_bitmap)) {
261 for (i = 0; i < NUM_MAIN_STATS; i++)
262 data[index++] =
263 ((unsigned long *) &priv->stats)[i];
264 for (i = 0; i < NUM_PORT_STATS; i++)
265 data[index++] =
266 ((unsigned long *) &priv->port_stats)[i];
267 for (i = 0; i < NUM_PKT_STATS; i++)
268 data[index++] =
269 ((unsigned long *) &priv->pkstats)[i];
270 } else {
271 for (i = 0; i < NUM_MAIN_STATS; i++) {
272 if ((priv->stats_bitmap >> j) & 1)
273 data[index++] =
274 ((unsigned long *) &priv->stats)[i];
275 j++;
276 }
277 for (i = 0; i < NUM_PORT_STATS; i++) {
278 if ((priv->stats_bitmap >> j) & 1)
279 data[index++] =
280 ((unsigned long *) &priv->port_stats)[i];
281 j++;
282 }
283 }
c27a02cd 284 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 285 data[index++] = priv->tx_ring[i]->packets;
286 data[index++] = priv->tx_ring[i]->bytes;
c27a02cd
YP		 287 }
288 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 289 data[index++] = priv->rx_ring[i]->packets;
290 data[index++] = priv->rx_ring[i]->bytes;
e0d1095a 291#ifdef CONFIG_NET_RX_BUSY_POLL
41d942d5
EE		 292 data[index++] = priv->rx_ring[i]->yields;
293 data[index++] = priv->rx_ring[i]->misses;
294 data[index++] = priv->rx_ring[i]->cleaned;
8501841a 295#endif
c27a02cd 296 }
c27a02cd
YP		 297 spin_unlock_bh(&priv->stats_lock);
298
299}
300
e7c1c2c4
YP		 301static void mlx4_en_self_test(struct net_device *dev,
302 struct ethtool_test *etest, u64 *buf)
303{
304 mlx4_en_ex_selftest(dev, &etest->flags, buf);
305}
306
c27a02cd
YP		 307static void mlx4_en_get_strings(struct net_device *dev,
308 uint32_t stringset, uint8_t *data)
309{
310 struct mlx4_en_priv *priv = netdev_priv(dev);
311 int index = 0;
312 int i;
313
e7c1c2c4
YP		 314 switch (stringset) {
315 case ETH_SS_TEST:
316 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
317 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
ccf86321 318 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
e7c1c2c4
YP		 319 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
320 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
321 break;
322
323 case ETH_SS_STATS:
324 /* Add main counters */
93ece0c1
EE		 325 if (!priv->stats_bitmap) {
326 for (i = 0; i < NUM_MAIN_STATS; i++)
327 strcpy(data + (index++) * ETH_GSTRING_LEN,
328 main_strings[i]);
329 for (i = 0; i < NUM_PORT_STATS; i++)
330 strcpy(data + (index++) * ETH_GSTRING_LEN,
331 main_strings[i +
332 NUM_MAIN_STATS]);
333 for (i = 0; i < NUM_PKT_STATS; i++)
334 strcpy(data + (index++) * ETH_GSTRING_LEN,
335 main_strings[i +
336 NUM_MAIN_STATS +
337 NUM_PORT_STATS]);
338 } else
339 for (i = 0; i < NUM_MAIN_STATS + NUM_PORT_STATS; i++) {
340 if ((priv->stats_bitmap >> i) & 1) {
341 strcpy(data +
342 (index++) * ETH_GSTRING_LEN,
343 main_strings[i]);
344 }
345 if (!(priv->stats_bitmap >> i))
346 break;
347 }
e7c1c2c4
YP		 348 for (i = 0; i < priv->tx_ring_num; i++) {
349 sprintf(data + (index++) * ETH_GSTRING_LEN,
350 "tx%d_packets", i);
351 sprintf(data + (index++) * ETH_GSTRING_LEN,
352 "tx%d_bytes", i);
353 }
354 for (i = 0; i < priv->rx_ring_num; i++) {
355 sprintf(data + (index++) * ETH_GSTRING_LEN,
356 "rx%d_packets", i);
357 sprintf(data + (index++) * ETH_GSTRING_LEN,
358 "rx%d_bytes", i);
e0d1095a 359#ifdef CONFIG_NET_RX_BUSY_POLL
8501841a
AV		 360 sprintf(data + (index++) * ETH_GSTRING_LEN,
361 "rx%d_napi_yield", i);
362 sprintf(data + (index++) * ETH_GSTRING_LEN,
363 "rx%d_misses", i);
364 sprintf(data + (index++) * ETH_GSTRING_LEN,
365 "rx%d_cleaned", i);
366#endif
e7c1c2c4 367 }
e7c1c2c4 368 break;
0fef9d03
AV		 369 case ETH_SS_PRIV_FLAGS:
370 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
371 strcpy(data + i * ETH_GSTRING_LEN,
372 mlx4_en_priv_flags[i]);
373 break;
374
e7c1c2c4 375 }
c27a02cd
YP		 376}
377
2c762679
SM		 378static u32 mlx4_en_autoneg_get(struct net_device *dev)
379{
380 struct mlx4_en_priv *priv = netdev_priv(dev);
381 struct mlx4_en_dev *mdev = priv->mdev;
382 u32 autoneg = AUTONEG_DISABLE;
383
384 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
385 (priv->port_state.flags & MLX4_EN_PORT_ANE))
386 autoneg = AUTONEG_ENABLE;
387
388 return autoneg;
389}
390
391static u32 ptys_get_supported_port(struct mlx4_ptys_reg *ptys_reg)
392{
393 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
394
395 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
396 | MLX4_PROT_MASK(MLX4_1000BASE_T)
397 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
398 return SUPPORTED_TP;
399 }
400
401 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
402 | MLX4_PROT_MASK(MLX4_10GBASE_SR)
403 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
404 | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
405 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
406 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
407 return SUPPORTED_FIBRE;
408 }
409
410 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
411 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
412 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
413 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
414 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
415 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
416 return SUPPORTED_Backplane;
417 }
418 return 0;
419}
420
421static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
422{
423 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
424
425 if (!eth_proto) /* link down */
426 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
427
428 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
429 | MLX4_PROT_MASK(MLX4_1000BASE_T)
430 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
431 return PORT_TP;
432 }
433
434 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
435 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
436 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
437 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
438 return PORT_FIBRE;
439 }
440
441 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
442 | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
443 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
444 return PORT_DA;
445 }
446
447 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
448 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
449 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
450 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
451 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
452 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
453 return PORT_NONE;
454 }
455 return PORT_OTHER;
456}
457
458#define MLX4_LINK_MODES_SZ \
459 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
460
461enum ethtool_report {
462 SUPPORTED = 0,
463 ADVERTISED = 1,
464 SPEED = 2
465};
466
467/* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
468static u32 ptys2ethtool_map[MLX4_LINK_MODES_SZ][3] = {
469 [MLX4_100BASE_TX] = {
470 SUPPORTED_100baseT_Full,
471 ADVERTISED_100baseT_Full,
472 SPEED_100
473 },
474
475 [MLX4_1000BASE_T] = {
476 SUPPORTED_1000baseT_Full,
477 ADVERTISED_1000baseT_Full,
478 SPEED_1000
479 },
480 [MLX4_1000BASE_CX_SGMII] = {
481 SUPPORTED_1000baseKX_Full,
482 ADVERTISED_1000baseKX_Full,
483 SPEED_1000
484 },
485 [MLX4_1000BASE_KX] = {
486 SUPPORTED_1000baseKX_Full,
487 ADVERTISED_1000baseKX_Full,
488 SPEED_1000
489 },
490
491 [MLX4_10GBASE_T] = {
492 SUPPORTED_10000baseT_Full,
493 ADVERTISED_10000baseT_Full,
494 SPEED_10000
495 },
496 [MLX4_10GBASE_CX4] = {
497 SUPPORTED_10000baseKX4_Full,
498 ADVERTISED_10000baseKX4_Full,
499 SPEED_10000
500 },
501 [MLX4_10GBASE_KX4] = {
502 SUPPORTED_10000baseKX4_Full,
503 ADVERTISED_10000baseKX4_Full,
504 SPEED_10000
505 },
506 [MLX4_10GBASE_KR] = {
507 SUPPORTED_10000baseKR_Full,
508 ADVERTISED_10000baseKR_Full,
509 SPEED_10000
510 },
511 [MLX4_10GBASE_CR] = {
512 SUPPORTED_10000baseKR_Full,
513 ADVERTISED_10000baseKR_Full,
514 SPEED_10000
515 },
516 [MLX4_10GBASE_SR] = {
517 SUPPORTED_10000baseKR_Full,
518 ADVERTISED_10000baseKR_Full,
519 SPEED_10000
520 },
521
522 [MLX4_20GBASE_KR2] = {
523 SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full,
524 ADVERTISED_20000baseMLD2_Full | ADVERTISED_20000baseKR2_Full,
525 SPEED_20000
526 },
527
528 [MLX4_40GBASE_CR4] = {
529 SUPPORTED_40000baseCR4_Full,
530 ADVERTISED_40000baseCR4_Full,
531 SPEED_40000
532 },
533 [MLX4_40GBASE_KR4] = {
534 SUPPORTED_40000baseKR4_Full,
535 ADVERTISED_40000baseKR4_Full,
536 SPEED_40000
537 },
538 [MLX4_40GBASE_SR4] = {
539 SUPPORTED_40000baseSR4_Full,
540 ADVERTISED_40000baseSR4_Full,
541 SPEED_40000
542 },
543
544 [MLX4_56GBASE_KR4] = {
545 SUPPORTED_56000baseKR4_Full,
546 ADVERTISED_56000baseKR4_Full,
547 SPEED_56000
548 },
549 [MLX4_56GBASE_CR4] = {
550 SUPPORTED_56000baseCR4_Full,
551 ADVERTISED_56000baseCR4_Full,
552 SPEED_56000
553 },
554 [MLX4_56GBASE_SR4] = {
555 SUPPORTED_56000baseSR4_Full,
556 ADVERTISED_56000baseSR4_Full,
557 SPEED_56000
558 },
559};
560
561static u32 ptys2ethtool_link_modes(u32 eth_proto, enum ethtool_report report)
562{
563 int i;
564 u32 link_modes = 0;
565
566 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
567 if (eth_proto & MLX4_PROT_MASK(i))
568 link_modes |= ptys2ethtool_map[i][report];
569 }
570 return link_modes;
571}
572
573static int ethtool_get_ptys_settings(struct net_device *dev,
574 struct ethtool_cmd *cmd)
575{
576 struct mlx4_en_priv *priv = netdev_priv(dev);
577 struct mlx4_ptys_reg ptys_reg;
578 u32 eth_proto;
579 int ret;
580
581 memset(&ptys_reg, 0, sizeof(ptys_reg));
582 ptys_reg.local_port = priv->port;
583 ptys_reg.proto_mask = MLX4_PTYS_EN;
584 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
585 MLX4_ACCESS_REG_QUERY, &ptys_reg);
586 if (ret) {
587 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
588 ret);
589 return ret;
590 }
591 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
592 ptys_reg.proto_mask);
593 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
594 be32_to_cpu(ptys_reg.eth_proto_cap));
595 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
596 be32_to_cpu(ptys_reg.eth_proto_admin));
597 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
598 be32_to_cpu(ptys_reg.eth_proto_oper));
599 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
600 be32_to_cpu(ptys_reg.eth_proto_lp_adv));
601
602 cmd->supported = 0;
603 cmd->advertising = 0;
604
605 cmd->supported |= ptys_get_supported_port(&ptys_reg);
606
607 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
608 cmd->supported |= ptys2ethtool_link_modes(eth_proto, SUPPORTED);
609
610 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
611 cmd->advertising |= ptys2ethtool_link_modes(eth_proto, ADVERTISED);
612
613 cmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
614 cmd->advertising |= (priv->prof->tx_pause) ? ADVERTISED_Pause : 0;
615
616 cmd->advertising |= (priv->prof->tx_pause ^ priv->prof->rx_pause) ?
617 ADVERTISED_Asym_Pause : 0;
618
619 cmd->port = ptys_get_active_port(&ptys_reg);
620 cmd->transceiver = (SUPPORTED_TP & cmd->supported) ?
621 XCVR_EXTERNAL : XCVR_INTERNAL;
622
623 if (mlx4_en_autoneg_get(dev)) {
624 cmd->supported |= SUPPORTED_Autoneg;
625 cmd->advertising |= ADVERTISED_Autoneg;
626 }
627
628 cmd->autoneg = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
629 AUTONEG_ENABLE : AUTONEG_DISABLE;
630
631 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
632 cmd->lp_advertising = ptys2ethtool_link_modes(eth_proto, ADVERTISED);
633
634 cmd->lp_advertising |= (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
635 ADVERTISED_Autoneg : 0;
636
637 cmd->phy_address = 0;
638 cmd->mdio_support = 0;
639 cmd->maxtxpkt = 0;
640 cmd->maxrxpkt = 0;
641 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
642 cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
643
644 return ret;
645}
646
647static void ethtool_get_default_settings(struct net_device *dev,
648 struct ethtool_cmd *cmd)
c27a02cd 649{
7699517d
YP		 650 struct mlx4_en_priv *priv = netdev_priv(dev);
651 int trans_type;
652
c27a02cd
YP		 653 cmd->autoneg = AUTONEG_DISABLE;
654 cmd->supported = SUPPORTED_10000baseT_Full;
7699517d 655 cmd->advertising = ADVERTISED_10000baseT_Full;
2c762679 656 trans_type = priv->port_state.transceiver;
7699517d
YP		 657
658 if (trans_type > 0 && trans_type <= 0xC) {
659 cmd->port = PORT_FIBRE;
660 cmd->transceiver = XCVR_EXTERNAL;
661 cmd->supported |= SUPPORTED_FIBRE;
662 cmd->advertising |= ADVERTISED_FIBRE;
663 } else if (trans_type == 0x80 || trans_type == 0) {
664 cmd->port = PORT_TP;
665 cmd->transceiver = XCVR_INTERNAL;
666 cmd->supported |= SUPPORTED_TP;
667 cmd->advertising |= ADVERTISED_TP;
668 } else {
669 cmd->port = -1;
670 cmd->transceiver = -1;
671 }
2c762679
SM		 672}
673
674static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
675{
676 struct mlx4_en_priv *priv = netdev_priv(dev);
677 int ret = -EINVAL;
678
679 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
680 return -ENOMEM;
681
682 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
683 priv->port_state.flags & MLX4_EN_PORT_ANC,
684 priv->port_state.flags & MLX4_EN_PORT_ANE);
685
686 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
687 ret = ethtool_get_ptys_settings(dev, cmd);
688 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
689 ethtool_get_default_settings(dev, cmd);
690
691 if (netif_carrier_ok(dev)) {
692 ethtool_cmd_speed_set(cmd, priv->port_state.link_speed);
693 cmd->duplex = DUPLEX_FULL;
694 } else {
695 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
696 cmd->duplex = DUPLEX_UNKNOWN;
697 }
c27a02cd
YP		 698 return 0;
699}
700
701static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
702{
703 if ((cmd->autoneg == AUTONEG_ENABLE) ||
25db0338
DD		 704 (ethtool_cmd_speed(cmd) != SPEED_10000) ||
705 (cmd->duplex != DUPLEX_FULL))
c27a02cd
YP		 706 return -EINVAL;
707
708 /* Nothing to change */
709 return 0;
710}
711
712static int mlx4_en_get_coalesce(struct net_device *dev,
713 struct ethtool_coalesce *coal)
714{
715 struct mlx4_en_priv *priv = netdev_priv(dev);
716
a19a848a
YP		 717 coal->tx_coalesce_usecs = priv->tx_usecs;
718 coal->tx_max_coalesced_frames = priv->tx_frames;
fbc6daf1
AV		 719 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
720
c27a02cd
YP		 721 coal->rx_coalesce_usecs = priv->rx_usecs;
722 coal->rx_max_coalesced_frames = priv->rx_frames;
723
724 coal->pkt_rate_low = priv->pkt_rate_low;
725 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
726 coal->pkt_rate_high = priv->pkt_rate_high;
727 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
728 coal->rate_sample_interval = priv->sample_interval;
729 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
fbc6daf1 730
c27a02cd
YP		 731 return 0;
732}
733
734static int mlx4_en_set_coalesce(struct net_device *dev,
735 struct ethtool_coalesce *coal)
736{
737 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd 738
fbc6daf1
AV		 739 if (!coal->tx_max_coalesced_frames_irq)
740 return -EINVAL;
741
c27a02cd
YP		 742 priv->rx_frames = (coal->rx_max_coalesced_frames ==
743 MLX4_EN_AUTO_CONF) ?
3db36fb2 744 MLX4_EN_RX_COAL_TARGET :
c27a02cd
YP		 745 coal->rx_max_coalesced_frames;
746 priv->rx_usecs = (coal->rx_coalesce_usecs ==
747 MLX4_EN_AUTO_CONF) ?
748 MLX4_EN_RX_COAL_TIME :
749 coal->rx_coalesce_usecs;
750
a19a848a
YP		 751 /* Setting TX coalescing parameters */
752 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
753 coal->tx_max_coalesced_frames != priv->tx_frames) {
754 priv->tx_usecs = coal->tx_coalesce_usecs;
755 priv->tx_frames = coal->tx_max_coalesced_frames;
a19a848a
YP		 756 }
757
c27a02cd
YP		 758 /* Set adaptive coalescing params */
759 priv->pkt_rate_low = coal->pkt_rate_low;
760 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
761 priv->pkt_rate_high = coal->pkt_rate_high;
762 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
763 priv->sample_interval = coal->rate_sample_interval;
764 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
fbc6daf1 765 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
c27a02cd 766
79c54b6b 767 return mlx4_en_moderation_update(priv);
c27a02cd
YP		 768}
769
770static int mlx4_en_set_pauseparam(struct net_device *dev,
771 struct ethtool_pauseparam *pause)
772{
773 struct mlx4_en_priv *priv = netdev_priv(dev);
774 struct mlx4_en_dev *mdev = priv->mdev;
775 int err;
776
278d436a
IV		 777 if (pause->autoneg)
778 return -EINVAL;
779
d53b93f2
YP		 780 priv->prof->tx_pause = pause->tx_pause != 0;
781 priv->prof->rx_pause = pause->rx_pause != 0;
c27a02cd
YP		 782 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
783 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 784 priv->prof->tx_pause,
785 priv->prof->tx_ppp,
786 priv->prof->rx_pause,
787 priv->prof->rx_ppp);
c27a02cd 788 if (err)
453a6082 789 en_err(priv, "Failed setting pause params\n");
c27a02cd
YP		 790
791 return err;
792}
793
794static void mlx4_en_get_pauseparam(struct net_device *dev,
795 struct ethtool_pauseparam *pause)
796{
797 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd 798
d53b93f2
YP		 799 pause->tx_pause = priv->prof->tx_pause;
800 pause->rx_pause = priv->prof->rx_pause;
c27a02cd
YP		 801}
802
18cc42a3
YP		 803static int mlx4_en_set_ringparam(struct net_device *dev,
804 struct ethtool_ringparam *param)
805{
806 struct mlx4_en_priv *priv = netdev_priv(dev);
807 struct mlx4_en_dev *mdev = priv->mdev;
808 u32 rx_size, tx_size;
809 int port_up = 0;
810 int err = 0;
811
812 if (param->rx_jumbo_pending || param->rx_mini_pending)
813 return -EINVAL;
814
815 rx_size = roundup_pow_of_two(param->rx_pending);
816 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
bd531e36 817 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
18cc42a3
YP		 818 tx_size = roundup_pow_of_two(param->tx_pending);
819 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
bd531e36 820 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
18cc42a3 821
41d942d5
EE		 822 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
823 priv->rx_ring[0]->size) &&
824 tx_size == priv->tx_ring[0]->size)
18cc42a3
YP		 825 return 0;
826
827 mutex_lock(&mdev->state_lock);
828 if (priv->port_up) {
829 port_up = 1;
3484aac1 830 mlx4_en_stop_port(dev, 1);
18cc42a3
YP		 831 }
832
fe0af03c 833 mlx4_en_free_resources(priv);
18cc42a3
YP		 834
835 priv->prof->tx_ring_size = tx_size;
836 priv->prof->rx_ring_size = rx_size;
837
838 err = mlx4_en_alloc_resources(priv);
839 if (err) {
453a6082 840 en_err(priv, "Failed reallocating port resources\n");
18cc42a3
YP		 841 goto out;
842 }
843 if (port_up) {
844 err = mlx4_en_start_port(dev);
845 if (err)
453a6082 846 en_err(priv, "Failed starting port\n");
18cc42a3
YP		 847 }
848
79c54b6b 849 err = mlx4_en_moderation_update(priv);
6b4d8d9f 850
18cc42a3
YP		 851out:
852 mutex_unlock(&mdev->state_lock);
853 return err;
854}
855
c27a02cd
YP		 856static void mlx4_en_get_ringparam(struct net_device *dev,
857 struct ethtool_ringparam *param)
858{
859 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd
YP		 860
861 memset(param, 0, sizeof(*param));
bd531e36
YP		 862 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
863 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
bc081cec 864 param->rx_pending = priv->port_up ?
41d942d5
EE		 865 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
866 param->tx_pending = priv->tx_ring[0]->size;
c27a02cd
YP		 867}
868
93d3e367
YP		 869static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
870{
871 struct mlx4_en_priv *priv = netdev_priv(dev);
872
873 return priv->rx_ring_num;
874}
875
fe62d001 876static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key)
93d3e367
YP		 877{
878 struct mlx4_en_priv *priv = netdev_priv(dev);
879 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
880 int rss_rings;
881 size_t n = priv->rx_ring_num;
882 int err = 0;
883
884 rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num;
885
886 while (n--) {
887 ring_index[n] = rss_map->qps[n % rss_rings].qpn -
888 rss_map->base_qpn;
889 }
890
891 return err;
892}
893
fe62d001
BH		 894static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
895 const u8 *key)
93d3e367
YP		 896{
897 struct mlx4_en_priv *priv = netdev_priv(dev);
898 struct mlx4_en_dev *mdev = priv->mdev;
899 int port_up = 0;
900 int err = 0;
901 int i;
902 int rss_rings = 0;
903
904 /* Calculate RSS table size and make sure flows are spread evenly
905 * between rings
906 */
907 for (i = 0; i < priv->rx_ring_num; i++) {
908 if (i > 0 && !ring_index[i] && !rss_rings)
909 rss_rings = i;
910
911 if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num)))
912 return -EINVAL;
913 }
914
915 if (!rss_rings)
916 rss_rings = priv->rx_ring_num;
917
918 /* RSS table size must be an order of 2 */
919 if (!is_power_of_2(rss_rings))
920 return -EINVAL;
921
922 mutex_lock(&mdev->state_lock);
923 if (priv->port_up) {
924 port_up = 1;
3484aac1 925 mlx4_en_stop_port(dev, 1);
93d3e367
YP		 926 }
927
928 priv->prof->rss_rings = rss_rings;
929
930 if (port_up) {
931 err = mlx4_en_start_port(dev);
932 if (err)
933 en_err(priv, "Failed starting port\n");
934 }
935
936 mutex_unlock(&mdev->state_lock);
937 return err;
938}
939
82067281
HHZ		 940#define all_zeros_or_all_ones(field) \
941 ((field) == 0 || (field) == (__force typeof(field))-1)
942
943static int mlx4_en_validate_flow(struct net_device *dev,
944 struct ethtool_rxnfc *cmd)
945{
946 struct ethtool_usrip4_spec *l3_mask;
947 struct ethtool_tcpip4_spec *l4_mask;
948 struct ethhdr *eth_mask;
82067281
HHZ		 949
950 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
951 return -EINVAL;
952
520dfe3a
YB		 953 if (cmd->fs.flow_type & FLOW_MAC_EXT) {
954 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
955 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
956 return -EINVAL;
957 }
958
959 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
82067281
HHZ		 960 case TCP_V4_FLOW:
961 case UDP_V4_FLOW:
962 if (cmd->fs.m_u.tcp_ip4_spec.tos)
963 return -EINVAL;
964 l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
965 /* don't allow mask which isn't all 0 or 1 */
966 if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
967 !all_zeros_or_all_ones(l4_mask->ip4dst) ||
968 !all_zeros_or_all_ones(l4_mask->psrc) ||
969 !all_zeros_or_all_ones(l4_mask->pdst))
970 return -EINVAL;
971 break;
972 case IP_USER_FLOW:
973 l3_mask = &cmd->fs.m_u.usr_ip4_spec;
974 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
975 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
976 (!l3_mask->ip4src && !l3_mask->ip4dst) ||
977 !all_zeros_or_all_ones(l3_mask->ip4src) ||
978 !all_zeros_or_all_ones(l3_mask->ip4dst))
979 return -EINVAL;
980 break;
981 case ETHER_FLOW:
982 eth_mask = &cmd->fs.m_u.ether_spec;
983 /* source mac mask must not be set */
c402b947 984 if (!is_zero_ether_addr(eth_mask->h_source))
82067281
HHZ		 985 return -EINVAL;
986
987 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
c402b947 988 if (!is_broadcast_ether_addr(eth_mask->h_dest))
82067281
HHZ		 989 return -EINVAL;
990
991 if (!all_zeros_or_all_ones(eth_mask->h_proto))
992 return -EINVAL;
993 break;
994 default:
995 return -EINVAL;
996 }
997
998 if ((cmd->fs.flow_type & FLOW_EXT)) {
999 if (cmd->fs.m_ext.vlan_etype ||
8258bd27
HHZ		 1000 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1001 0 ||
1002 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1003 cpu_to_be16(VLAN_VID_MASK)))
82067281 1004 return -EINVAL;
8258bd27 1005
69d7126b
HHZ		 1006 if (cmd->fs.m_ext.vlan_tci) {
1007 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1008 return -EINVAL;
8258bd27 1009
69d7126b 1010 }
82067281
HHZ		 1011 }
1012
1013 return 0;
1014}
1015
f90a3673
HHZ		 1016static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1017 struct list_head *rule_list_h,
1018 struct mlx4_spec_list *spec_l2,
1019 unsigned char *mac)
1020{
1021 int err = 0;
1022 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1023
1024 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1025 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1026 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1027
8258bd27
HHZ		 1028 if ((cmd->fs.flow_type & FLOW_EXT) &&
1029 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
f90a3673 1030 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
8258bd27 1031 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
f90a3673
HHZ		 1032 }
1033
1034 list_add_tail(&spec_l2->list, rule_list_h);
1035
1036 return err;
1037}
1038
1039static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1040 struct ethtool_rxnfc *cmd,
1041 struct list_head *rule_list_h,
1042 struct mlx4_spec_list *spec_l2,
1043 __be32 ipv4_dst)
1044{
f9d96862 1045#ifdef CONFIG_INET
f90a3673
HHZ		 1046 unsigned char mac[ETH_ALEN];
1047
1048 if (!ipv4_is_multicast(ipv4_dst)) {
6bbb6d99 1049 if (cmd->fs.flow_type & FLOW_MAC_EXT)
f90a3673 1050 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
6bbb6d99
YB		 1051 else
1052 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
f90a3673
HHZ		 1053 } else {
1054 ip_eth_mc_map(ipv4_dst, mac);
1055 }
1056
1057 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
f9d96862
HHZ		 1058#else
1059 return -EINVAL;
1060#endif
f90a3673
HHZ		 1061}
1062
82067281 1063static int add_ip_rule(struct mlx4_en_priv *priv,
f90a3673
HHZ		 1064 struct ethtool_rxnfc *cmd,
1065 struct list_head *list_h)
82067281 1066{
377d9739 1067 int err;
f90a3673
HHZ		 1068 struct mlx4_spec_list *spec_l2 = NULL;
1069 struct mlx4_spec_list *spec_l3 = NULL;
82067281
HHZ		 1070 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1071
f90a3673
HHZ		 1072 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1073 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1074 if (!spec_l2 || !spec_l3) {
377d9739
HHZ		 1075 err = -ENOMEM;
1076 goto free_spec;
82067281
HHZ		 1077 }
1078
377d9739
HHZ		 1079 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1080 cmd->fs.h_u.
1081 usr_ip4_spec.ip4dst);
1082 if (err)
1083 goto free_spec;
82067281
HHZ		 1084 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1085 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1086 if (l3_mask->ip4src)
1087 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1088 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1089 if (l3_mask->ip4dst)
1090 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1091 list_add_tail(&spec_l3->list, list_h);
1092
1093 return 0;
377d9739
HHZ		 1094
1095free_spec:
1096 kfree(spec_l2);
1097 kfree(spec_l3);
1098 return err;
82067281
HHZ		 1099}
1100
1101static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1102 struct ethtool_rxnfc *cmd,
1103 struct list_head *list_h, int proto)
1104{
377d9739 1105 int err;
f90a3673
HHZ		 1106 struct mlx4_spec_list *spec_l2 = NULL;
1107 struct mlx4_spec_list *spec_l3 = NULL;
1108 struct mlx4_spec_list *spec_l4 = NULL;
82067281
HHZ		 1109 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1110
f90a3673
HHZ		 1111 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1112 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1113 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1114 if (!spec_l2 || !spec_l3 || !spec_l4) {
377d9739
HHZ		 1115 err = -ENOMEM;
1116 goto free_spec;
82067281
HHZ		 1117 }
1118
1119 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1120
1121 if (proto == TCP_V4_FLOW) {
377d9739
HHZ		 1122 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1123 spec_l2,
1124 cmd->fs.h_u.
1125 tcp_ip4_spec.ip4dst);
1126 if (err)
1127 goto free_spec;
82067281
HHZ		 1128 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1129 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1130 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1131 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1132 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1133 } else {
377d9739
HHZ		 1134 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1135 spec_l2,
1136 cmd->fs.h_u.
1137 udp_ip4_spec.ip4dst);
1138 if (err)
1139 goto free_spec;
82067281
HHZ		 1140 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1141 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1142 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1143 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1144 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1145 }
1146
1147 if (l4_mask->ip4src)
1148 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1149 if (l4_mask->ip4dst)
1150 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1151
1152 if (l4_mask->psrc)
1153 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1154 if (l4_mask->pdst)
1155 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1156
1157 list_add_tail(&spec_l3->list, list_h);
1158 list_add_tail(&spec_l4->list, list_h);
1159
1160 return 0;
377d9739
HHZ		 1161
1162free_spec:
1163 kfree(spec_l2);
1164 kfree(spec_l3);
1165 kfree(spec_l4);
1166 return err;
82067281
HHZ		 1167}
1168
1169static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1170 struct ethtool_rxnfc *cmd,
1171 struct list_head *rule_list_h)
1172{
1173 int err;
82067281 1174 struct ethhdr *eth_spec;
82067281 1175 struct mlx4_spec_list *spec_l2;
f90a3673 1176 struct mlx4_en_priv *priv = netdev_priv(dev);
82067281
HHZ		 1177
1178 err = mlx4_en_validate_flow(dev, cmd);
1179 if (err)
1180 return err;
1181
520dfe3a 1182 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
82067281 1183 case ETHER_FLOW:
f90a3673
HHZ		 1184 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1185 if (!spec_l2)
1186 return -ENOMEM;
1187
82067281 1188 eth_spec = &cmd->fs.h_u.ether_spec;
f90a3673
HHZ		 1189 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1190 &eth_spec->h_dest[0]);
82067281
HHZ		 1191 spec_l2->eth.ether_type = eth_spec->h_proto;
1192 if (eth_spec->h_proto)
1193 spec_l2->eth.ether_type_enable = 1;
1194 break;
1195 case IP_USER_FLOW:
1196 err = add_ip_rule(priv, cmd, rule_list_h);
1197 break;
1198 case TCP_V4_FLOW:
1199 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1200 break;
1201 case UDP_V4_FLOW:
1202 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1203 break;
1204 }
1205
1206 return err;
1207}
1208
1209static int mlx4_en_flow_replace(struct net_device *dev,
1210 struct ethtool_rxnfc *cmd)
1211{
1212 int err;
1213 struct mlx4_en_priv *priv = netdev_priv(dev);
1214 struct ethtool_flow_id *loc_rule;
1215 struct mlx4_spec_list *spec, *tmp_spec;
1216 u32 qpn;
1217 u64 reg_id;
1218
1219 struct mlx4_net_trans_rule rule = {
1220 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1221 .exclusive = 0,
1222 .allow_loopback = 1,
f9162539 1223 .promisc_mode = MLX4_FS_REGULAR,
82067281
HHZ		 1224 };
1225
1226 rule.port = priv->port;
1227 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1228 INIT_LIST_HEAD(&rule.list);
1229
1230 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
1231 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
cabdc8ee 1232 qpn = priv->drop_qp.qpn;
82067281
HHZ		 1233 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1234 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1235 } else {
1236 if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1a91de28 1237 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
82067281
HHZ		 1238 cmd->fs.ring_cookie);
1239 return -EINVAL;
1240 }
1241 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1242 if (!qpn) {
1a91de28 1243 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
82067281
HHZ		 1244 cmd->fs.ring_cookie);
1245 return -EINVAL;
1246 }
1247 }
1248 rule.qpn = qpn;
1249 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1250 if (err)
1251 goto out_free_list;
1252
1253 loc_rule = &priv->ethtool_rules[cmd->fs.location];
1254 if (loc_rule->id) {
1255 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1256 if (err) {
1257 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1258 cmd->fs.location, loc_rule->id);
1259 goto out_free_list;
1260 }
1261 loc_rule->id = 0;
1262 memset(&loc_rule->flow_spec, 0,
1263 sizeof(struct ethtool_rx_flow_spec));
0d256c0e 1264 list_del(&loc_rule->list);
82067281
HHZ		 1265 }
1266 err = mlx4_flow_attach(priv->mdev->dev, &rule, &reg_id);
1267 if (err) {
1a91de28 1268 en_err(priv, "Fail to attach network rule at location %d\n",
82067281
HHZ		 1269 cmd->fs.location);
1270 goto out_free_list;
1271 }
1272 loc_rule->id = reg_id;
1273 memcpy(&loc_rule->flow_spec, &cmd->fs,
1274 sizeof(struct ethtool_rx_flow_spec));
0d256c0e 1275 list_add_tail(&loc_rule->list, &priv->ethtool_list);
82067281
HHZ		 1276
1277out_free_list:
1278 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1279 list_del(&spec->list);
1280 kfree(spec);
1281 }
1282 return err;
1283}
1284
1285static int mlx4_en_flow_detach(struct net_device *dev,
1286 struct ethtool_rxnfc *cmd)
1287{
1288 int err = 0;
1289 struct ethtool_flow_id *rule;
1290 struct mlx4_en_priv *priv = netdev_priv(dev);
1291
1292 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1293 return -EINVAL;
1294
1295 rule = &priv->ethtool_rules[cmd->fs.location];
1296 if (!rule->id) {
1297 err = -ENOENT;
1298 goto out;
1299 }
1300
1301 err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1302 if (err) {
1303 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1304 cmd->fs.location, rule->id);
1305 goto out;
1306 }
1307 rule->id = 0;
1308 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
0d256c0e 1309 list_del(&rule->list);
82067281
HHZ		 1310out:
1311 return err;
1312
1313}
1314
1315static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1316 int loc)
1317{
1318 int err = 0;
1319 struct ethtool_flow_id *rule;
1320 struct mlx4_en_priv *priv = netdev_priv(dev);
1321
1322 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1323 return -EINVAL;
1324
1325 rule = &priv->ethtool_rules[loc];
1326 if (rule->id)
1327 memcpy(&cmd->fs, &rule->flow_spec,
1328 sizeof(struct ethtool_rx_flow_spec));
1329 else
1330 err = -ENOENT;
1331
1332 return err;
1333}
1334
1335static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1336{
1337
1338 int i, res = 0;
1339 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1340 if (priv->ethtool_rules[i].id)
1341 res++;
1342 }
1343 return res;
1344
1345}
1346
93d3e367
YP		 1347static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1348 u32 *rule_locs)
1349{
1350 struct mlx4_en_priv *priv = netdev_priv(dev);
82067281 1351 struct mlx4_en_dev *mdev = priv->mdev;
93d3e367 1352 int err = 0;
82067281
HHZ		 1353 int i = 0, priority = 0;
1354
1355 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1356 cmd->cmd == ETHTOOL_GRXCLSRULE ||
1357 cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
280fce1e
HHZ		 1358 (mdev->dev->caps.steering_mode !=
1359 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
82067281 1360 return -EINVAL;
93d3e367
YP		 1361
1362 switch (cmd->cmd) {
1363 case ETHTOOL_GRXRINGS:
1364 cmd->data = priv->rx_ring_num;
1365 break;
82067281
HHZ		 1366 case ETHTOOL_GRXCLSRLCNT:
1367 cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1368 break;
1369 case ETHTOOL_GRXCLSRULE:
1370 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1371 break;
1372 case ETHTOOL_GRXCLSRLALL:
1373 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1374 err = mlx4_en_get_flow(dev, cmd, i);
1375 if (!err)
1376 rule_locs[priority++] = i;
1377 i++;
1378 }
1379 err = 0;
1380 break;
93d3e367
YP		 1381 default:
1382 err = -EOPNOTSUPP;
1383 break;
1384 }
1385
1386 return err;
1387}
1388
82067281
HHZ		 1389static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1390{
1391 int err = 0;
1392 struct mlx4_en_priv *priv = netdev_priv(dev);
1393 struct mlx4_en_dev *mdev = priv->mdev;
1394
280fce1e
HHZ		 1395 if (mdev->dev->caps.steering_mode !=
1396 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
82067281
HHZ		 1397 return -EINVAL;
1398
1399 switch (cmd->cmd) {
1400 case ETHTOOL_SRXCLSRLINS:
1401 err = mlx4_en_flow_replace(dev, cmd);
1402 break;
1403 case ETHTOOL_SRXCLSRLDEL:
1404 err = mlx4_en_flow_detach(dev, cmd);
1405 break;
1406 default:
1407 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1408 return -EINVAL;
1409 }
1410
1411 return err;
1412}
1413
d317966b
AV		 1414static void mlx4_en_get_channels(struct net_device *dev,
1415 struct ethtool_channels *channel)
1416{
1417 struct mlx4_en_priv *priv = netdev_priv(dev);
1418
1419 memset(channel, 0, sizeof(*channel));
1420
1421 channel->max_rx = MAX_RX_RINGS;
1422 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
1423
1424 channel->rx_count = priv->rx_ring_num;
1425 channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP;
1426}
1427
1428static int mlx4_en_set_channels(struct net_device *dev,
1429 struct ethtool_channels *channel)
1430{
1431 struct mlx4_en_priv *priv = netdev_priv(dev);
1432 struct mlx4_en_dev *mdev = priv->mdev;
da26a625 1433 int port_up = 0;
d317966b
AV		 1434 int err = 0;
1435
1436 if (channel->other_count || channel->combined_count ||
1437 channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP ||
1438 channel->rx_count > MAX_RX_RINGS ||
1439 !channel->tx_count || !channel->rx_count)
1440 return -EINVAL;
1441
1442 mutex_lock(&mdev->state_lock);
1443 if (priv->port_up) {
1444 port_up = 1;
3484aac1 1445 mlx4_en_stop_port(dev, 1);
d317966b
AV		 1446 }
1447
1448 mlx4_en_free_resources(priv);
1449
1450 priv->num_tx_rings_p_up = channel->tx_count;
1451 priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP;
1452 priv->rx_ring_num = channel->rx_count;
1453
1454 err = mlx4_en_alloc_resources(priv);
1455 if (err) {
1456 en_err(priv, "Failed reallocating port resources\n");
1457 goto out;
1458 }
1459
1460 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
1461 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1462
f5b6345b
IS		 1463 if (dev->num_tc)
1464 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP);
d317966b
AV		 1465
1466 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num);
1467 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1468
1469 if (port_up) {
1470 err = mlx4_en_start_port(dev);
1471 if (err)
1472 en_err(priv, "Failed starting port\n");
1473 }
1474
1475 err = mlx4_en_moderation_update(priv);
1476
1477out:
1478 mutex_unlock(&mdev->state_lock);
1479 return err;
1480}
1481
ec693d47
AV		 1482static int mlx4_en_get_ts_info(struct net_device *dev,
1483 struct ethtool_ts_info *info)
1484{
1485 struct mlx4_en_priv *priv = netdev_priv(dev);
1486 struct mlx4_en_dev *mdev = priv->mdev;
1487 int ret;
1488
1489 ret = ethtool_op_get_ts_info(dev, info);
1490 if (ret)
1491 return ret;
1492
1493 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1494 info->so_timestamping |=
1495 SOF_TIMESTAMPING_TX_HARDWARE |
1496 SOF_TIMESTAMPING_RX_HARDWARE |
1497 SOF_TIMESTAMPING_RAW_HARDWARE;
1498
1499 info->tx_types =
1500 (1 << HWTSTAMP_TX_OFF) |
1501 (1 << HWTSTAMP_TX_ON);
1502
1503 info->rx_filters =
1504 (1 << HWTSTAMP_FILTER_NONE) |
1505 (1 << HWTSTAMP_FILTER_ALL);
ad7d4eae
SB		 1506
1507 if (mdev->ptp_clock)
1508 info->phc_index = ptp_clock_index(mdev->ptp_clock);
ec693d47
AV		 1509 }
1510
1511 return ret;
1512}
1513
3f6148e7 1514static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
0fef9d03
AV		 1515{
1516 struct mlx4_en_priv *priv = netdev_priv(dev);
1517 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1518 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1519 int i;
1520
1521 if (bf_enabled_new == bf_enabled_old)
1522 return 0; /* Nothing to do */
1523
1524 if (bf_enabled_new) {
1525 bool bf_supported = true;
1526
1527 for (i = 0; i < priv->tx_ring_num; i++)
1528 bf_supported &= priv->tx_ring[i]->bf_alloced;
1529
1530 if (!bf_supported) {
1531 en_err(priv, "BlueFlame is not supported\n");
1532 return -EINVAL;
1533 }
1534
1535 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1536 } else {
1537 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1538 }
1539
1540 for (i = 0; i < priv->tx_ring_num; i++)
1541 priv->tx_ring[i]->bf_enabled = bf_enabled_new;
1542
1543 en_info(priv, "BlueFlame %s\n",
1544 bf_enabled_new ? "Enabled" : "Disabled");
1545
1546 return 0;
1547}
1548
3f6148e7 1549static u32 mlx4_en_get_priv_flags(struct net_device *dev)
0fef9d03
AV		 1550{
1551 struct mlx4_en_priv *priv = netdev_priv(dev);
1552
1553 return priv->pflags;
1554}
1555
1556b874
ED		 1556static int mlx4_en_get_tunable(struct net_device *dev,
1557 const struct ethtool_tunable *tuna,
1558 void *data)
1559{
1560 const struct mlx4_en_priv *priv = netdev_priv(dev);
1561 int ret = 0;
1562
1563 switch (tuna->id) {
1564 case ETHTOOL_TX_COPYBREAK:
1565 *(u32 *)data = priv->prof->inline_thold;
1566 break;
1567 default:
1568 ret = -EINVAL;
1569 break;
1570 }
1571
1572 return ret;
1573}
1574
1575static int mlx4_en_set_tunable(struct net_device *dev,
1576 const struct ethtool_tunable *tuna,
1577 const void *data)
1578{
1579 struct mlx4_en_priv *priv = netdev_priv(dev);
1580 int val, ret = 0;
1581
1582 switch (tuna->id) {
1583 case ETHTOOL_TX_COPYBREAK:
1584 val = *(u32 *)data;
1585 if (val < MIN_PKT_LEN || val > MAX_INLINE)
1586 ret = -EINVAL;
1587 else
1588 priv->prof->inline_thold = val;
1589 break;
1590 default:
1591 ret = -EINVAL;
1592 break;
1593 }
1594
1595 return ret;
1596}
1597
7202da8b
SM		 1598static int mlx4_en_get_module_info(struct net_device *dev,
1599 struct ethtool_modinfo *modinfo)
1600{
1601 struct mlx4_en_priv *priv = netdev_priv(dev);
1602 struct mlx4_en_dev *mdev = priv->mdev;
1603 int ret;
1604 u8 data[4];
1605
1606 /* Read first 2 bytes to get Module & REV ID */
1607 ret = mlx4_get_module_info(mdev->dev, priv->port,
1608 0/*offset*/, 2/*size*/, data);
1609 if (ret < 2)
1610 return -EIO;
1611
1612 switch (data[0] /* identifier */) {
1613 case MLX4_MODULE_ID_QSFP:
1614 modinfo->type = ETH_MODULE_SFF_8436;
1615 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1616 break;
1617 case MLX4_MODULE_ID_QSFP_PLUS:
1618 if (data[1] >= 0x3) { /* revision id */
1619 modinfo->type = ETH_MODULE_SFF_8636;
1620 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1621 } else {
1622 modinfo->type = ETH_MODULE_SFF_8436;
1623 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1624 }
1625 break;
1626 case MLX4_MODULE_ID_QSFP28:
1627 modinfo->type = ETH_MODULE_SFF_8636;
1628 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1629 break;
1630 case MLX4_MODULE_ID_SFP:
1631 modinfo->type = ETH_MODULE_SFF_8472;
1632 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1633 break;
1634 default:
1635 return -ENOSYS;
1636 }
1637
1638 return 0;
1639}
1640
1641static int mlx4_en_get_module_eeprom(struct net_device *dev,
1642 struct ethtool_eeprom *ee,
1643 u8 *data)
1644{
1645 struct mlx4_en_priv *priv = netdev_priv(dev);
1646 struct mlx4_en_dev *mdev = priv->mdev;
1647 int offset = ee->offset;
1648 int i = 0, ret;
1649
1650 if (ee->len == 0)
1651 return -EINVAL;
1652
1653 memset(data, 0, ee->len);
1654
1655 while (i < ee->len) {
1656 en_dbg(DRV, priv,
1657 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
1658 i, offset, ee->len - i);
1659
1660 ret = mlx4_get_module_info(mdev->dev, priv->port,
1661 offset, ee->len - i, data + i);
1662
1663 if (!ret) /* Done reading */
1664 return 0;
1665
1666 if (ret < 0) {
1667 en_err(priv,
1668 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
1669 i, offset, ee->len - i, ret);
1670 return 0;
1671 }
1672
1673 i += ret;
1674 offset += ret;
1675 }
1676 return 0;
1677}
0fef9d03 1678
c27a02cd
YP		 1679const struct ethtool_ops mlx4_en_ethtool_ops = {
1680 .get_drvinfo = mlx4_en_get_drvinfo,
1681 .get_settings = mlx4_en_get_settings,
1682 .set_settings = mlx4_en_set_settings,
c27a02cd 1683 .get_link = ethtool_op_get_link,
c27a02cd
YP		 1684 .get_strings = mlx4_en_get_strings,
1685 .get_sset_count = mlx4_en_get_sset_count,
1686 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
e7c1c2c4 1687 .self_test = mlx4_en_self_test,
c27a02cd 1688 .get_wol = mlx4_en_get_wol,
14c07b13 1689 .set_wol = mlx4_en_set_wol,
c27a02cd
YP		 1690 .get_msglevel = mlx4_en_get_msglevel,
1691 .set_msglevel = mlx4_en_set_msglevel,
1692 .get_coalesce = mlx4_en_get_coalesce,
1693 .set_coalesce = mlx4_en_set_coalesce,
1694 .get_pauseparam = mlx4_en_get_pauseparam,
1695 .set_pauseparam = mlx4_en_set_pauseparam,
1696 .get_ringparam = mlx4_en_get_ringparam,
18cc42a3 1697 .set_ringparam = mlx4_en_set_ringparam,
93d3e367 1698 .get_rxnfc = mlx4_en_get_rxnfc,
82067281 1699 .set_rxnfc = mlx4_en_set_rxnfc,
93d3e367 1700 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
fe62d001
BH		 1701 .get_rxfh = mlx4_en_get_rxfh,
1702 .set_rxfh = mlx4_en_set_rxfh,
d317966b
AV		 1703 .get_channels = mlx4_en_get_channels,
1704 .set_channels = mlx4_en_set_channels,
ec693d47 1705 .get_ts_info = mlx4_en_get_ts_info,
0fef9d03
AV		 1706 .set_priv_flags = mlx4_en_set_priv_flags,
1707 .get_priv_flags = mlx4_en_get_priv_flags,
1556b874
ED		 1708 .get_tunable = mlx4_en_get_tunable,
1709 .set_tunable = mlx4_en_set_tunable,
7202da8b
SM		 1710 .get_module_info = mlx4_en_get_module_info,
1711 .get_module_eeprom = mlx4_en_get_module_eeprom
c27a02cd
YP		 1712};
1713
1714
1715
1716
1717
Linux 6.x block layer and io_uring tree(s)