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net/mlx4_core: Fix HW2SW_EQ to conform to the firmware spec
[linux-block.git] / drivers / net / ethernet / mellanox / mlx4 / cmd.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/sched.h>
5a0e3ad6 36#include <linux/slab.h>
ee40fa06 37#include <linux/export.h>
225c7b1f
RD		 38#include <linux/pci.h>
39#include <linux/errno.h>
40
41#include <linux/mlx4/cmd.h>
948e306d 42#include <linux/mlx4/device.h>
e8f081aa 43#include <linux/semaphore.h>
0a9a0188 44#include <rdma/ib_smi.h>
55ad3592 45#include <linux/delay.h>
225c7b1f
RD		 46
47#include <asm/io.h>
48
49#include "mlx4.h"
e8f081aa 50#include "fw.h"
225c7b1f
RD		 51
52#define CMD_POLL_TOKEN 0xffff
e8f081aa
YP		 53#define INBOX_MASK 0xffffffffffffff00ULL
54
55#define CMD_CHAN_VER 1
56#define CMD_CHAN_IF_REV 1
225c7b1f
RD		 57
58enum {
59 /* command completed successfully: */
60 CMD_STAT_OK = 0x00,
61 /* Internal error (such as a bus error) occurred while processing command: */
62 CMD_STAT_INTERNAL_ERR = 0x01,
63 /* Operation/command not supported or opcode modifier not supported: */
64 CMD_STAT_BAD_OP = 0x02,
65 /* Parameter not supported or parameter out of range: */
66 CMD_STAT_BAD_PARAM = 0x03,
67 /* System not enabled or bad system state: */
68 CMD_STAT_BAD_SYS_STATE = 0x04,
69 /* Attempt to access reserved or unallocaterd resource: */
70 CMD_STAT_BAD_RESOURCE = 0x05,
71 /* Requested resource is currently executing a command, or is otherwise busy: */
72 CMD_STAT_RESOURCE_BUSY = 0x06,
73 /* Required capability exceeds device limits: */
74 CMD_STAT_EXCEED_LIM = 0x08,
75 /* Resource is not in the appropriate state or ownership: */
76 CMD_STAT_BAD_RES_STATE = 0x09,
77 /* Index out of range: */
78 CMD_STAT_BAD_INDEX = 0x0a,
79 /* FW image corrupted: */
80 CMD_STAT_BAD_NVMEM = 0x0b,
899698da
JM		 81 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
82 CMD_STAT_ICM_ERROR = 0x0c,
225c7b1f
RD		 83 /* Attempt to modify a QP/EE which is not in the presumed state: */
84 CMD_STAT_BAD_QP_STATE = 0x10,
85 /* Bad segment parameters (Address/Size): */
86 CMD_STAT_BAD_SEG_PARAM = 0x20,
87 /* Memory Region has Memory Windows bound to: */
88 CMD_STAT_REG_BOUND = 0x21,
89 /* HCA local attached memory not present: */
90 CMD_STAT_LAM_NOT_PRE = 0x22,
91 /* Bad management packet (silently discarded): */
92 CMD_STAT_BAD_PKT = 0x30,
93 /* More outstanding CQEs in CQ than new CQ size: */
cc4ac2e7
YP		 94 CMD_STAT_BAD_SIZE = 0x40,
95 /* Multi Function device support required: */
96 CMD_STAT_MULTI_FUNC_REQ = 0x50,
225c7b1f
RD		 97};
98
99enum {
100 HCR_IN_PARAM_OFFSET = 0x00,
101 HCR_IN_MODIFIER_OFFSET = 0x08,
102 HCR_OUT_PARAM_OFFSET = 0x0c,
103 HCR_TOKEN_OFFSET = 0x14,
104 HCR_STATUS_OFFSET = 0x18,
105
106 HCR_OPMOD_SHIFT = 12,
107 HCR_T_BIT = 21,
108 HCR_E_BIT = 22,
109 HCR_GO_BIT = 23
110};
111
112enum {
36ce10d3 113 GO_BIT_TIMEOUT_MSECS = 10000
225c7b1f
RD		 114};
115
b01978ca
JM		 116enum mlx4_vlan_transition {
117 MLX4_VLAN_TRANSITION_VST_VST = 0,
118 MLX4_VLAN_TRANSITION_VST_VGT = 1,
119 MLX4_VLAN_TRANSITION_VGT_VST = 2,
120 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
121};
122
123
225c7b1f
RD		 124struct mlx4_cmd_context {
125 struct completion done;
126 int result;
127 int next;
128 u64 out_param;
129 u16 token;
e8f081aa 130 u8 fw_status;
225c7b1f
RD		 131};
132
e8f081aa
YP		 133static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
134 struct mlx4_vhcr_cmd *in_vhcr);
135
ca281211
RD		 136static int mlx4_status_to_errno(u8 status)
137{
225c7b1f
RD		 138 static const int trans_table[] = {
139 [CMD_STAT_INTERNAL_ERR] = -EIO,
140 [CMD_STAT_BAD_OP] = -EPERM,
141 [CMD_STAT_BAD_PARAM] = -EINVAL,
142 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
143 [CMD_STAT_BAD_RESOURCE] = -EBADF,
144 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
145 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
146 [CMD_STAT_BAD_RES_STATE] = -EBADF,
147 [CMD_STAT_BAD_INDEX] = -EBADF,
148 [CMD_STAT_BAD_NVMEM] = -EFAULT,
899698da 149 [CMD_STAT_ICM_ERROR] = -ENFILE,
225c7b1f
RD		 150 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
151 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
152 [CMD_STAT_REG_BOUND] = -EBUSY,
153 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
154 [CMD_STAT_BAD_PKT] = -EINVAL,
155 [CMD_STAT_BAD_SIZE] = -ENOMEM,
cc4ac2e7 156 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
225c7b1f
RD		 157 };
158
159 if (status >= ARRAY_SIZE(trans_table) ||
160 (status != CMD_STAT_OK && trans_table[status] == 0))
161 return -EIO;
162
163 return trans_table[status];
164}
165
72be84f1
YP		 166static u8 mlx4_errno_to_status(int errno)
167{
168 switch (errno) {
169 case -EPERM:
170 return CMD_STAT_BAD_OP;
171 case -EINVAL:
172 return CMD_STAT_BAD_PARAM;
173 case -ENXIO:
174 return CMD_STAT_BAD_SYS_STATE;
175 case -EBUSY:
176 return CMD_STAT_RESOURCE_BUSY;
177 case -ENOMEM:
178 return CMD_STAT_EXCEED_LIM;
179 case -ENFILE:
180 return CMD_STAT_ICM_ERROR;
181 default:
182 return CMD_STAT_INTERNAL_ERR;
183 }
184}
185
f5aef5aa
YH		 186static int mlx4_internal_err_ret_value(struct mlx4_dev *dev, u16 op,
187 u8 op_modifier)
188{
189 switch (op) {
190 case MLX4_CMD_UNMAP_ICM:
191 case MLX4_CMD_UNMAP_ICM_AUX:
192 case MLX4_CMD_UNMAP_FA:
193 case MLX4_CMD_2RST_QP:
194 case MLX4_CMD_HW2SW_EQ:
195 case MLX4_CMD_HW2SW_CQ:
196 case MLX4_CMD_HW2SW_SRQ:
197 case MLX4_CMD_HW2SW_MPT:
198 case MLX4_CMD_CLOSE_HCA:
199 case MLX4_QP_FLOW_STEERING_DETACH:
200 case MLX4_CMD_FREE_RES:
201 case MLX4_CMD_CLOSE_PORT:
202 return CMD_STAT_OK;
203
204 case MLX4_CMD_QP_ATTACH:
205 /* On Detach case return success */
206 if (op_modifier == 0)
207 return CMD_STAT_OK;
208 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
209
210 default:
211 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
212 }
213}
214
215static int mlx4_closing_cmd_fatal_error(u16 op, u8 fw_status)
216{
217 /* Any error during the closing commands below is considered fatal */
218 if (op == MLX4_CMD_CLOSE_HCA ||
219 op == MLX4_CMD_HW2SW_EQ ||
220 op == MLX4_CMD_HW2SW_CQ ||
221 op == MLX4_CMD_2RST_QP ||
222 op == MLX4_CMD_HW2SW_SRQ ||
223 op == MLX4_CMD_SYNC_TPT ||
224 op == MLX4_CMD_UNMAP_ICM ||
225 op == MLX4_CMD_UNMAP_ICM_AUX ||
226 op == MLX4_CMD_UNMAP_FA)
227 return 1;
228 /* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
229 * CMD_STAT_REG_BOUND.
230 * This status indicates that memory region has memory windows bound to it
231 * which may result from invalid user space usage and is not fatal.
232 */
233 if (op == MLX4_CMD_HW2SW_MPT && fw_status != CMD_STAT_REG_BOUND)
234 return 1;
235 return 0;
236}
237
238static int mlx4_cmd_reset_flow(struct mlx4_dev *dev, u16 op, u8 op_modifier,
239 int err)
240{
241 /* Only if reset flow is really active return code is based on
242 * command, otherwise current error code is returned.
243 */
244 if (mlx4_internal_err_reset) {
245 mlx4_enter_error_state(dev->persist);
246 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
247 }
248
249 return err;
250}
251
e8f081aa
YP		 252static int comm_pending(struct mlx4_dev *dev)
253{
254 struct mlx4_priv *priv = mlx4_priv(dev);
255 u32 status = readl(&priv->mfunc.comm->slave_read);
256
257 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
258}
259
0cd93027 260static int mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
e8f081aa
YP		 261{
262 struct mlx4_priv *priv = mlx4_priv(dev);
263 u32 val;
264
0cd93027
YH		 265 /* To avoid writing to unknown addresses after the device state was
266 * changed to internal error and the function was rest,
267 * check the INTERNAL_ERROR flag which is updated under
268 * device_state_mutex lock.
269 */
270 mutex_lock(&dev->persist->device_state_mutex);
271
272 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
273 mutex_unlock(&dev->persist->device_state_mutex);
274 return -EIO;
275 }
276
e8f081aa
YP		 277 priv->cmd.comm_toggle ^= 1;
278 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
279 __raw_writel((__force u32) cpu_to_be32(val),
280 &priv->mfunc.comm->slave_write);
281 mmiowb();
0cd93027
YH		 282 mutex_unlock(&dev->persist->device_state_mutex);
283 return 0;
e8f081aa
YP		 284}
285
e8f081aa
YP		 286static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
287 unsigned long timeout)
288{
289 struct mlx4_priv *priv = mlx4_priv(dev);
290 unsigned long end;
291 int err = 0;
292 int ret_from_pending = 0;
293
294 /* First, verify that the master reports correct status */
295 if (comm_pending(dev)) {
1a91de28 296 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
e8f081aa
YP		 297 priv->cmd.comm_toggle, cmd);
298 return -EAGAIN;
299 }
300
301 /* Write command */
302 down(&priv->cmd.poll_sem);
0cd93027
YH		 303 if (mlx4_comm_cmd_post(dev, cmd, param)) {
304 /* Only in case the device state is INTERNAL_ERROR,
305 * mlx4_comm_cmd_post returns with an error
306 */
307 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
308 goto out;
309 }
e8f081aa
YP		 310
311 end = msecs_to_jiffies(timeout) + jiffies;
312 while (comm_pending(dev) && time_before(jiffies, end))
313 cond_resched();
314 ret_from_pending = comm_pending(dev);
315 if (ret_from_pending) {
316 /* check if the slave is trying to boot in the middle of
317 * FLR process. The only non-zero result in the RESET command
318 * is MLX4_DELAY_RESET_SLAVE*/
319 if ((MLX4_COMM_CMD_RESET == cmd)) {
e8f081aa 320 err = MLX4_DELAY_RESET_SLAVE;
0cd93027 321 goto out;
e8f081aa 322 } else {
0cd93027
YH		 323 mlx4_warn(dev, "Communication channel command 0x%x timed out\n",
324 cmd);
325 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
e8f081aa
YP		 326 }
327 }
328
0cd93027
YH		 329 if (err)
330 mlx4_enter_error_state(dev->persist);
331out:
e8f081aa
YP		 332 up(&priv->cmd.poll_sem);
333 return err;
334}
335
0cd93027
YH		 336static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 vhcr_cmd,
337 u16 param, u16 op, unsigned long timeout)
e8f081aa
YP		 338{
339 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
340 struct mlx4_cmd_context *context;
58a3de05 341 unsigned long end;
e8f081aa
YP		 342 int err = 0;
343
344 down(&cmd->event_sem);
345
346 spin_lock(&cmd->context_lock);
347 BUG_ON(cmd->free_head < 0);
348 context = &cmd->context[cmd->free_head];
349 context->token += cmd->token_mask + 1;
350 cmd->free_head = context->next;
351 spin_unlock(&cmd->context_lock);
352
f5aef5aa 353 reinit_completion(&context->done);
e8f081aa 354
0cd93027
YH		 355 if (mlx4_comm_cmd_post(dev, vhcr_cmd, param)) {
356 /* Only in case the device state is INTERNAL_ERROR,
357 * mlx4_comm_cmd_post returns with an error
358 */
359 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
360 goto out;
361 }
e8f081aa
YP		 362
363 if (!wait_for_completion_timeout(&context->done,
364 msecs_to_jiffies(timeout))) {
0cd93027
YH		 365 mlx4_warn(dev, "communication channel command 0x%x (op=0x%x) timed out\n",
366 vhcr_cmd, op);
367 goto out_reset;
e8f081aa
YP		 368 }
369
370 err = context->result;
371 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
372 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
0cd93027
YH		 373 vhcr_cmd, context->fw_status);
374 if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
375 goto out_reset;
e8f081aa
YP		 376 }
377
58a3de05
EE		 378 /* wait for comm channel ready
379 * this is necessary for prevention the race
380 * when switching between event to polling mode
0cd93027
YH		 381 * Skipping this section in case the device is in FATAL_ERROR state,
382 * In this state, no commands are sent via the comm channel until
383 * the device has returned from reset.
58a3de05 384 */
0cd93027
YH		 385 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
386 end = msecs_to_jiffies(timeout) + jiffies;
387 while (comm_pending(dev) && time_before(jiffies, end))
388 cond_resched();
389 }
390 goto out;
58a3de05 391
0cd93027
YH		 392out_reset:
393 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
394 mlx4_enter_error_state(dev->persist);
395out:
e8f081aa
YP		 396 spin_lock(&cmd->context_lock);
397 context->next = cmd->free_head;
398 cmd->free_head = context - cmd->context;
399 spin_unlock(&cmd->context_lock);
400
401 up(&cmd->event_sem);
402 return err;
403}
404
ab9c17a0 405int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
0cd93027 406 u16 op, unsigned long timeout)
e8f081aa 407{
0cd93027
YH		 408 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
409 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
410
e8f081aa 411 if (mlx4_priv(dev)->cmd.use_events)
0cd93027 412 return mlx4_comm_cmd_wait(dev, cmd, param, op, timeout);
e8f081aa
YP		 413 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
414}
415
225c7b1f
RD		 416static int cmd_pending(struct mlx4_dev *dev)
417{
57dbf29a
KSS		 418 u32 status;
419
872bf2fb 420 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 421 return -EIO;
422
423 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
225c7b1f
RD		 424
425 return (status & swab32(1 << HCR_GO_BIT)) ||
426 (mlx4_priv(dev)->cmd.toggle ==
427 !!(status & swab32(1 << HCR_T_BIT)));
428}
429
430static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
431 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
432 int event)
433{
434 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
435 u32 __iomem *hcr = cmd->hcr;
f5aef5aa 436 int ret = -EIO;
225c7b1f
RD		 437 unsigned long end;
438
f5aef5aa
YH		 439 mutex_lock(&dev->persist->device_state_mutex);
440 /* To avoid writing to unknown addresses after the device state was
441 * changed to internal error and the chip was reset,
442 * check the INTERNAL_ERROR flag which is updated under
443 * device_state_mutex lock.
444 */
445 if (pci_channel_offline(dev->persist->pdev) ||
446 (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
57dbf29a
KSS		 447 /*
448 * Device is going through error recovery
449 * and cannot accept commands.
450 */
57dbf29a
KSS		 451 goto out;
452 }
453
225c7b1f
RD		 454 end = jiffies;
455 if (event)
36ce10d3 456 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
225c7b1f
RD		 457
458 while (cmd_pending(dev)) {
872bf2fb 459 if (pci_channel_offline(dev->persist->pdev)) {
57dbf29a
KSS		 460 /*
461 * Device is going through error recovery
462 * and cannot accept commands.
463 */
57dbf29a
KSS		 464 goto out;
465 }
466
e8f081aa
YP		 467 if (time_after_eq(jiffies, end)) {
468 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
225c7b1f 469 goto out;
e8f081aa 470 }
225c7b1f
RD		 471 cond_resched();
472 }
473
474 /*
475 * We use writel (instead of something like memcpy_toio)
476 * because writes of less than 32 bits to the HCR don't work
477 * (and some architectures such as ia64 implement memcpy_toio
478 * in terms of writeb).
479 */
480 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
481 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
482 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
483 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
484 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
485 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
486
487 /* __raw_writel may not order writes. */
488 wmb();
489
490 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
491 (cmd->toggle << HCR_T_BIT) |
492 (event ? (1 << HCR_E_BIT) : 0) |
493 (op_modifier << HCR_OPMOD_SHIFT) |
e8f081aa 494 op), hcr + 6);
2e61c646
RD		 495
496 /*
497 * Make sure that our HCR writes don't get mixed in with
498 * writes from another CPU starting a FW command.
499 */
500 mmiowb();
501
225c7b1f
RD		 502 cmd->toggle = cmd->toggle ^ 1;
503
504 ret = 0;
505
506out:
f5aef5aa
YH		 507 if (ret)
508 mlx4_warn(dev, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
509 op, ret, in_param, in_modifier, op_modifier);
510 mutex_unlock(&dev->persist->device_state_mutex);
511
225c7b1f
RD		 512 return ret;
513}
514
e8f081aa
YP		 515static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
516 int out_is_imm, u32 in_modifier, u8 op_modifier,
517 u16 op, unsigned long timeout)
518{
519 struct mlx4_priv *priv = mlx4_priv(dev);
520 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
521 int ret;
522
f3d4c89e
RD		 523 mutex_lock(&priv->cmd.slave_cmd_mutex);
524
e8f081aa
YP		 525 vhcr->in_param = cpu_to_be64(in_param);
526 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
527 vhcr->in_modifier = cpu_to_be32(in_modifier);
528 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
529 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
530 vhcr->status = 0;
531 vhcr->flags = !!(priv->cmd.use_events) << 6;
f3d4c89e 532
e8f081aa
YP		 533 if (mlx4_is_master(dev)) {
534 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
535 if (!ret) {
536 if (out_is_imm) {
537 if (out_param)
538 *out_param =
539 be64_to_cpu(vhcr->out_param);
540 else {
1a91de28
JP		 541 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
542 op);
72be84f1 543 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 544 }
545 }
72be84f1 546 ret = mlx4_status_to_errno(vhcr->status);
e8f081aa 547 }
0cd93027
YH		 548 if (ret &&
549 dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
550 ret = mlx4_internal_err_ret_value(dev, op, op_modifier);
e8f081aa 551 } else {
0cd93027 552 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, op,
e8f081aa
YP		 553 MLX4_COMM_TIME + timeout);
554 if (!ret) {
555 if (out_is_imm) {
556 if (out_param)
557 *out_param =
558 be64_to_cpu(vhcr->out_param);
559 else {
1a91de28
JP		 560 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
561 op);
72be84f1 562 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 563 }
564 }
72be84f1 565 ret = mlx4_status_to_errno(vhcr->status);
0cd93027
YH		 566 } else {
567 if (dev->persist->state &
568 MLX4_DEVICE_STATE_INTERNAL_ERROR)
569 ret = mlx4_internal_err_ret_value(dev, op,
570 op_modifier);
571 else
572 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", op);
573 }
e8f081aa 574 }
f3d4c89e
RD		 575
576 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 577 return ret;
578}
579
225c7b1f
RD		 580static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
581 int out_is_imm, u32 in_modifier, u8 op_modifier,
582 u16 op, unsigned long timeout)
583{
584 struct mlx4_priv *priv = mlx4_priv(dev);
585 void __iomem *hcr = priv->cmd.hcr;
586 int err = 0;
587 unsigned long end;
e8f081aa 588 u32 stat;
225c7b1f
RD		 589
590 down(&priv->cmd.poll_sem);
591
f5aef5aa 592 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
57dbf29a
KSS		 593 /*
594 * Device is going through error recovery
595 * and cannot accept commands.
596 */
f5aef5aa 597 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
57dbf29a
KSS		 598 goto out;
599 }
600
c05a116f
EP		 601 if (out_is_imm && !out_param) {
602 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
603 op);
604 err = -EINVAL;
605 goto out;
606 }
607
225c7b1f
RD		 608 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
609 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
610 if (err)
f5aef5aa 611 goto out_reset;
225c7b1f
RD		 612
613 end = msecs_to_jiffies(timeout) + jiffies;
57dbf29a 614 while (cmd_pending(dev) && time_before(jiffies, end)) {
872bf2fb 615 if (pci_channel_offline(dev->persist->pdev)) {
57dbf29a
KSS		 616 /*
617 * Device is going through error recovery
618 * and cannot accept commands.
619 */
620 err = -EIO;
f5aef5aa
YH		 621 goto out_reset;
622 }
623
624 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
625 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
57dbf29a
KSS		 626 goto out;
627 }
628
225c7b1f 629 cond_resched();
57dbf29a 630 }
225c7b1f
RD		 631
632 if (cmd_pending(dev)) {
674925ed
DB		 633 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
634 op);
f5aef5aa
YH		 635 err = -EIO;
636 goto out_reset;
225c7b1f
RD		 637 }
638
639 if (out_is_imm)
640 *out_param =
641 (u64) be32_to_cpu((__force __be32)
642 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
643 (u64) be32_to_cpu((__force __be32)
644 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
e8f081aa
YP		 645 stat = be32_to_cpu((__force __be32)
646 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
647 err = mlx4_status_to_errno(stat);
f5aef5aa 648 if (err) {
e8f081aa
YP		 649 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
650 op, stat);
f5aef5aa
YH		 651 if (mlx4_closing_cmd_fatal_error(op, stat))
652 goto out_reset;
653 goto out;
654 }
225c7b1f 655
f5aef5aa
YH		 656out_reset:
657 if (err)
658 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
225c7b1f
RD		 659out:
660 up(&priv->cmd.poll_sem);
661 return err;
662}
663
664void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
665{
666 struct mlx4_priv *priv = mlx4_priv(dev);
667 struct mlx4_cmd_context *context =
668 &priv->cmd.context[token & priv->cmd.token_mask];
669
670 /* previously timed out command completing at long last */
671 if (token != context->token)
672 return;
673
e8f081aa 674 context->fw_status = status;
225c7b1f
RD		 675 context->result = mlx4_status_to_errno(status);
676 context->out_param = out_param;
677
225c7b1f
RD		 678 complete(&context->done);
679}
680
681static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
682 int out_is_imm, u32 in_modifier, u8 op_modifier,
683 u16 op, unsigned long timeout)
684{
685 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
686 struct mlx4_cmd_context *context;
687 int err = 0;
688
689 down(&cmd->event_sem);
690
691 spin_lock(&cmd->context_lock);
692 BUG_ON(cmd->free_head < 0);
693 context = &cmd->context[cmd->free_head];
0981582d 694 context->token += cmd->token_mask + 1;
225c7b1f
RD		 695 cmd->free_head = context->next;
696 spin_unlock(&cmd->context_lock);
697
c05a116f
EP		 698 if (out_is_imm && !out_param) {
699 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
700 op);
701 err = -EINVAL;
702 goto out;
703 }
704
f5aef5aa 705 reinit_completion(&context->done);
225c7b1f 706
f5aef5aa
YH		 707 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
708 in_modifier, op_modifier, op, context->token, 1);
709 if (err)
710 goto out_reset;
225c7b1f 711
e8f081aa
YP		 712 if (!wait_for_completion_timeout(&context->done,
713 msecs_to_jiffies(timeout))) {
674925ed
DB		 714 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
715 op);
f5aef5aa
YH		 716 err = -EIO;
717 goto out_reset;
225c7b1f
RD		 718 }
719
720 err = context->result;
e8f081aa 721 if (err) {
1daa4303
JM		 722 /* Since we do not want to have this error message always
723 * displayed at driver start when there are ConnectX2 HCAs
724 * on the host, we deprecate the error message for this
725 * specific command/input_mod/opcode_mod/fw-status to be debug.
726 */
727 if (op == MLX4_CMD_SET_PORT && in_modifier == 1 &&
728 op_modifier == 0 && context->fw_status == CMD_STAT_BAD_SIZE)
729 mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
730 op, context->fw_status);
731 else
732 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
733 op, context->fw_status);
f5aef5aa
YH		 734 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
735 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
736 else if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
737 goto out_reset;
738
225c7b1f 739 goto out;
e8f081aa 740 }
225c7b1f
RD		 741
742 if (out_is_imm)
743 *out_param = context->out_param;
744
f5aef5aa
YH		 745out_reset:
746 if (err)
747 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
225c7b1f
RD		 748out:
749 spin_lock(&cmd->context_lock);
750 context->next = cmd->free_head;
751 cmd->free_head = context - cmd->context;
752 spin_unlock(&cmd->context_lock);
753
754 up(&cmd->event_sem);
755 return err;
756}
757
758int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
759 int out_is_imm, u32 in_modifier, u8 op_modifier,
f9baff50 760 u16 op, unsigned long timeout, int native)
225c7b1f 761{
872bf2fb 762 if (pci_channel_offline(dev->persist->pdev))
f5aef5aa 763 return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO);
57dbf29a 764
e8f081aa 765 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
f5aef5aa
YH		 766 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
767 return mlx4_internal_err_ret_value(dev, op,
768 op_modifier);
e8f081aa
YP		 769 if (mlx4_priv(dev)->cmd.use_events)
770 return mlx4_cmd_wait(dev, in_param, out_param,
771 out_is_imm, in_modifier,
772 op_modifier, op, timeout);
773 else
774 return mlx4_cmd_poll(dev, in_param, out_param,
775 out_is_imm, in_modifier,
776 op_modifier, op, timeout);
777 }
778 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
779 in_modifier, op_modifier, op, timeout);
225c7b1f
RD		 780}
781EXPORT_SYMBOL_GPL(__mlx4_cmd);
782
e8f081aa 783
55ad3592 784int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
e8f081aa
YP		 785{
786 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
787 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
788}
789
790static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
791 int slave, u64 slave_addr,
792 int size, int is_read)
793{
794 u64 in_param;
795 u64 out_param;
796
797 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
798 (slave & ~0x7f) | (size & 0xff)) {
1a91de28
JP		 799 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
800 slave_addr, master_addr, slave, size);
e8f081aa
YP		 801 return -EINVAL;
802 }
803
804 if (is_read) {
805 in_param = (u64) slave | slave_addr;
806 out_param = (u64) dev->caps.function | master_addr;
807 } else {
808 in_param = (u64) dev->caps.function | master_addr;
809 out_param = (u64) slave | slave_addr;
810 }
811
812 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
813 MLX4_CMD_ACCESS_MEM,
814 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
815}
816
0a9a0188
JM		 817static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
818 struct mlx4_cmd_mailbox *inbox,
819 struct mlx4_cmd_mailbox *outbox)
820{
821 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
822 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
823 int err;
824 int i;
825
826 if (index & 0x1f)
827 return -EINVAL;
828
829 in_mad->attr_mod = cpu_to_be32(index / 32);
830
831 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
832 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
833 MLX4_CMD_NATIVE);
834 if (err)
835 return err;
836
837 for (i = 0; i < 32; ++i)
838 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
839
840 return err;
841}
842
843static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
844 struct mlx4_cmd_mailbox *inbox,
845 struct mlx4_cmd_mailbox *outbox)
846{
847 int i;
848 int err;
849
850 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
851 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
852 if (err)
853 return err;
854 }
855
856 return 0;
857}
858#define PORT_CAPABILITY_LOCATION_IN_SMP 20
859#define PORT_STATE_OFFSET 32
860
861static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
862{
a0c64a17
JM		 863 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
864 return IB_PORT_ACTIVE;
865 else
866 return IB_PORT_DOWN;
0a9a0188
JM		 867}
868
869static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
870 struct mlx4_vhcr *vhcr,
871 struct mlx4_cmd_mailbox *inbox,
872 struct mlx4_cmd_mailbox *outbox,
873 struct mlx4_cmd_info *cmd)
874{
875 struct ib_smp *smp = inbox->buf;
876 u32 index;
877 u8 port;
97982f5a 878 u8 opcode_modifier;
0a9a0188
JM		 879 u16 *table;
880 int err;
881 int vidx, pidx;
97982f5a 882 int network_view;
0a9a0188
JM		 883 struct mlx4_priv *priv = mlx4_priv(dev);
884 struct ib_smp *outsmp = outbox->buf;
885 __be16 *outtab = (__be16 *)(outsmp->data);
886 __be32 slave_cap_mask;
afa8fd1d 887 __be64 slave_node_guid;
97982f5a 888
0a9a0188
JM		 889 port = vhcr->in_modifier;
890
97982f5a
JM		 891 /* network-view bit is for driver use only, and should not be passed to FW */
892 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
893 network_view = !!(vhcr->op_modifier & 0x8);
894
0a9a0188
JM		 895 if (smp->base_version == 1 &&
896 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
897 smp->class_version == 1) {
97982f5a
JM		 898 /* host view is paravirtualized */
899 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
0a9a0188
JM		 900 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
901 index = be32_to_cpu(smp->attr_mod);
902 if (port < 1 || port > dev->caps.num_ports)
903 return -EINVAL;
904 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
905 if (!table)
906 return -ENOMEM;
907 /* need to get the full pkey table because the paravirtualized
908 * pkeys may be scattered among several pkey blocks.
909 */
910 err = get_full_pkey_table(dev, port, table, inbox, outbox);
911 if (!err) {
912 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
913 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
914 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
915 }
916 }
917 kfree(table);
918 return err;
919 }
920 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
921 /*get the slave specific caps:*/
922 /*do the command */
923 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 924 vhcr->in_modifier, opcode_modifier,
0a9a0188
JM		 925 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
926 /* modify the response for slaves */
927 if (!err && slave != mlx4_master_func_num(dev)) {
928 u8 *state = outsmp->data + PORT_STATE_OFFSET;
929
930 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
931 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
932 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
933 }
934 return err;
935 }
936 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
937 /* compute slave's gid block */
938 smp->attr_mod = cpu_to_be32(slave / 8);
939 /* execute cmd */
940 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 941 vhcr->in_modifier, opcode_modifier,
0a9a0188
JM		 942 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
943 if (!err) {
944 /* if needed, move slave gid to index 0 */
945 if (slave % 8)
946 memcpy(outsmp->data,
947 outsmp->data + (slave % 8) * 8, 8);
948 /* delete all other gids */
949 memset(outsmp->data + 8, 0, 56);
950 }
951 return err;
952 }
afa8fd1d
JM		 953 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
954 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 955 vhcr->in_modifier, opcode_modifier,
afa8fd1d
JM		 956 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
957 if (!err) {
958 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
959 memcpy(outsmp->data + 12, &slave_node_guid, 8);
960 }
961 return err;
962 }
0a9a0188
JM		 963 }
964 }
97982f5a
JM		 965
966 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
967 * These are the MADs used by ib verbs (such as ib_query_gids).
968 */
0a9a0188 969 if (slave != mlx4_master_func_num(dev) &&
97982f5a
JM		 970 !mlx4_vf_smi_enabled(dev, slave, port)) {
971 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
972 smp->method == IB_MGMT_METHOD_GET) || network_view) {
973 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
974 slave, smp->method, smp->mgmt_class,
975 network_view ? "Network" : "Host",
976 be16_to_cpu(smp->attr_id));
977 return -EPERM;
978 }
0a9a0188 979 }
97982f5a 980
0a9a0188 981 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 982 vhcr->in_modifier, opcode_modifier,
0a9a0188
JM		 983 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
984}
985
b7475794 986static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
fe6f700d
YP		 987 struct mlx4_vhcr *vhcr,
988 struct mlx4_cmd_mailbox *inbox,
989 struct mlx4_cmd_mailbox *outbox,
990 struct mlx4_cmd_info *cmd)
991{
992 return -EPERM;
993}
994
e8f081aa
YP		 995int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
996 struct mlx4_vhcr *vhcr,
997 struct mlx4_cmd_mailbox *inbox,
998 struct mlx4_cmd_mailbox *outbox,
999 struct mlx4_cmd_info *cmd)
1000{
1001 u64 in_param;
1002 u64 out_param;
1003 int err;
1004
1005 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
1006 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
1007 if (cmd->encode_slave_id) {
1008 in_param &= 0xffffffffffffff00ll;
1009 in_param |= slave;
1010 }
1011
1012 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
1013 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
1014 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1015
1016 if (cmd->out_is_imm)
1017 vhcr->out_param = out_param;
1018
1019 return err;
1020}
1021
1022static struct mlx4_cmd_info cmd_info[] = {
1023 {
1024 .opcode = MLX4_CMD_QUERY_FW,
1025 .has_inbox = false,
1026 .has_outbox = true,
1027 .out_is_imm = false,
1028 .encode_slave_id = false,
1029 .verify = NULL,
b91cb3eb 1030 .wrapper = mlx4_QUERY_FW_wrapper
e8f081aa
YP		 1031 },
1032 {
1033 .opcode = MLX4_CMD_QUERY_HCA,
1034 .has_inbox = false,
1035 .has_outbox = true,
1036 .out_is_imm = false,
1037 .encode_slave_id = false,
1038 .verify = NULL,
1039 .wrapper = NULL
1040 },
1041 {
1042 .opcode = MLX4_CMD_QUERY_DEV_CAP,
1043 .has_inbox = false,
1044 .has_outbox = true,
1045 .out_is_imm = false,
1046 .encode_slave_id = false,
1047 .verify = NULL,
b91cb3eb 1048 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
e8f081aa 1049 },
c82e9aa0
EC		 1050 {
1051 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
1052 .has_inbox = false,
1053 .has_outbox = true,
1054 .out_is_imm = false,
1055 .encode_slave_id = false,
1056 .verify = NULL,
1057 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
1058 },
1059 {
1060 .opcode = MLX4_CMD_QUERY_ADAPTER,
1061 .has_inbox = false,
1062 .has_outbox = true,
1063 .out_is_imm = false,
1064 .encode_slave_id = false,
1065 .verify = NULL,
1066 .wrapper = NULL
1067 },
1068 {
1069 .opcode = MLX4_CMD_INIT_PORT,
1070 .has_inbox = false,
1071 .has_outbox = false,
1072 .out_is_imm = false,
1073 .encode_slave_id = false,
1074 .verify = NULL,
1075 .wrapper = mlx4_INIT_PORT_wrapper
1076 },
1077 {
1078 .opcode = MLX4_CMD_CLOSE_PORT,
1079 .has_inbox = false,
1080 .has_outbox = false,
1081 .out_is_imm = false,
1082 .encode_slave_id = false,
1083 .verify = NULL,
1084 .wrapper = mlx4_CLOSE_PORT_wrapper
1085 },
1086 {
1087 .opcode = MLX4_CMD_QUERY_PORT,
1088 .has_inbox = false,
1089 .has_outbox = true,
1090 .out_is_imm = false,
1091 .encode_slave_id = false,
1092 .verify = NULL,
1093 .wrapper = mlx4_QUERY_PORT_wrapper
1094 },
ffe455ad
EE		 1095 {
1096 .opcode = MLX4_CMD_SET_PORT,
1097 .has_inbox = true,
1098 .has_outbox = false,
1099 .out_is_imm = false,
1100 .encode_slave_id = false,
1101 .verify = NULL,
1102 .wrapper = mlx4_SET_PORT_wrapper
1103 },
c82e9aa0
EC		 1104 {
1105 .opcode = MLX4_CMD_MAP_EQ,
1106 .has_inbox = false,
1107 .has_outbox = false,
1108 .out_is_imm = false,
1109 .encode_slave_id = false,
1110 .verify = NULL,
1111 .wrapper = mlx4_MAP_EQ_wrapper
1112 },
1113 {
1114 .opcode = MLX4_CMD_SW2HW_EQ,
1115 .has_inbox = true,
1116 .has_outbox = false,
1117 .out_is_imm = false,
1118 .encode_slave_id = true,
1119 .verify = NULL,
1120 .wrapper = mlx4_SW2HW_EQ_wrapper
1121 },
1122 {
1123 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
1124 .has_inbox = false,
1125 .has_outbox = false,
1126 .out_is_imm = false,
1127 .encode_slave_id = false,
1128 .verify = NULL,
1129 .wrapper = NULL
1130 },
1131 {
1132 .opcode = MLX4_CMD_NOP,
1133 .has_inbox = false,
1134 .has_outbox = false,
1135 .out_is_imm = false,
1136 .encode_slave_id = false,
1137 .verify = NULL,
1138 .wrapper = NULL
1139 },
d18f141a
OG		 1140 {
1141 .opcode = MLX4_CMD_CONFIG_DEV,
1142 .has_inbox = false,
d475c95b 1143 .has_outbox = true,
d18f141a
OG		 1144 .out_is_imm = false,
1145 .encode_slave_id = false,
1146 .verify = NULL,
d475c95b 1147 .wrapper = mlx4_CONFIG_DEV_wrapper
d18f141a 1148 },
c82e9aa0
EC		 1149 {
1150 .opcode = MLX4_CMD_ALLOC_RES,
1151 .has_inbox = false,
1152 .has_outbox = false,
1153 .out_is_imm = true,
1154 .encode_slave_id = false,
1155 .verify = NULL,
1156 .wrapper = mlx4_ALLOC_RES_wrapper
1157 },
1158 {
1159 .opcode = MLX4_CMD_FREE_RES,
1160 .has_inbox = false,
1161 .has_outbox = false,
1162 .out_is_imm = false,
1163 .encode_slave_id = false,
1164 .verify = NULL,
1165 .wrapper = mlx4_FREE_RES_wrapper
1166 },
1167 {
1168 .opcode = MLX4_CMD_SW2HW_MPT,
1169 .has_inbox = true,
1170 .has_outbox = false,
1171 .out_is_imm = false,
1172 .encode_slave_id = true,
1173 .verify = NULL,
1174 .wrapper = mlx4_SW2HW_MPT_wrapper
1175 },
1176 {
1177 .opcode = MLX4_CMD_QUERY_MPT,
1178 .has_inbox = false,
1179 .has_outbox = true,
1180 .out_is_imm = false,
1181 .encode_slave_id = false,
1182 .verify = NULL,
1183 .wrapper = mlx4_QUERY_MPT_wrapper
1184 },
1185 {
1186 .opcode = MLX4_CMD_HW2SW_MPT,
1187 .has_inbox = false,
1188 .has_outbox = false,
1189 .out_is_imm = false,
1190 .encode_slave_id = false,
1191 .verify = NULL,
1192 .wrapper = mlx4_HW2SW_MPT_wrapper
1193 },
1194 {
1195 .opcode = MLX4_CMD_READ_MTT,
1196 .has_inbox = false,
1197 .has_outbox = true,
1198 .out_is_imm = false,
1199 .encode_slave_id = false,
1200 .verify = NULL,
1201 .wrapper = NULL
1202 },
1203 {
1204 .opcode = MLX4_CMD_WRITE_MTT,
1205 .has_inbox = true,
1206 .has_outbox = false,
1207 .out_is_imm = false,
1208 .encode_slave_id = false,
1209 .verify = NULL,
1210 .wrapper = mlx4_WRITE_MTT_wrapper
1211 },
1212 {
1213 .opcode = MLX4_CMD_SYNC_TPT,
1214 .has_inbox = true,
1215 .has_outbox = false,
1216 .out_is_imm = false,
1217 .encode_slave_id = false,
1218 .verify = NULL,
1219 .wrapper = NULL
1220 },
1221 {
1222 .opcode = MLX4_CMD_HW2SW_EQ,
1223 .has_inbox = false,
30a5da5b 1224 .has_outbox = false,
c82e9aa0
EC		 1225 .out_is_imm = false,
1226 .encode_slave_id = true,
1227 .verify = NULL,
1228 .wrapper = mlx4_HW2SW_EQ_wrapper
1229 },
1230 {
1231 .opcode = MLX4_CMD_QUERY_EQ,
1232 .has_inbox = false,
1233 .has_outbox = true,
1234 .out_is_imm = false,
1235 .encode_slave_id = true,
1236 .verify = NULL,
1237 .wrapper = mlx4_QUERY_EQ_wrapper
1238 },
1239 {
1240 .opcode = MLX4_CMD_SW2HW_CQ,
1241 .has_inbox = true,
1242 .has_outbox = false,
1243 .out_is_imm = false,
1244 .encode_slave_id = true,
1245 .verify = NULL,
1246 .wrapper = mlx4_SW2HW_CQ_wrapper
1247 },
1248 {
1249 .opcode = MLX4_CMD_HW2SW_CQ,
1250 .has_inbox = false,
1251 .has_outbox = false,
1252 .out_is_imm = false,
1253 .encode_slave_id = false,
1254 .verify = NULL,
1255 .wrapper = mlx4_HW2SW_CQ_wrapper
1256 },
1257 {
1258 .opcode = MLX4_CMD_QUERY_CQ,
1259 .has_inbox = false,
1260 .has_outbox = true,
1261 .out_is_imm = false,
1262 .encode_slave_id = false,
1263 .verify = NULL,
1264 .wrapper = mlx4_QUERY_CQ_wrapper
1265 },
1266 {
1267 .opcode = MLX4_CMD_MODIFY_CQ,
1268 .has_inbox = true,
1269 .has_outbox = false,
1270 .out_is_imm = true,
1271 .encode_slave_id = false,
1272 .verify = NULL,
1273 .wrapper = mlx4_MODIFY_CQ_wrapper
1274 },
1275 {
1276 .opcode = MLX4_CMD_SW2HW_SRQ,
1277 .has_inbox = true,
1278 .has_outbox = false,
1279 .out_is_imm = false,
1280 .encode_slave_id = true,
1281 .verify = NULL,
1282 .wrapper = mlx4_SW2HW_SRQ_wrapper
1283 },
1284 {
1285 .opcode = MLX4_CMD_HW2SW_SRQ,
1286 .has_inbox = false,
1287 .has_outbox = false,
1288 .out_is_imm = false,
1289 .encode_slave_id = false,
1290 .verify = NULL,
1291 .wrapper = mlx4_HW2SW_SRQ_wrapper
1292 },
1293 {
1294 .opcode = MLX4_CMD_QUERY_SRQ,
1295 .has_inbox = false,
1296 .has_outbox = true,
1297 .out_is_imm = false,
1298 .encode_slave_id = false,
1299 .verify = NULL,
1300 .wrapper = mlx4_QUERY_SRQ_wrapper
1301 },
1302 {
1303 .opcode = MLX4_CMD_ARM_SRQ,
1304 .has_inbox = false,
1305 .has_outbox = false,
1306 .out_is_imm = false,
1307 .encode_slave_id = false,
1308 .verify = NULL,
1309 .wrapper = mlx4_ARM_SRQ_wrapper
1310 },
1311 {
1312 .opcode = MLX4_CMD_RST2INIT_QP,
1313 .has_inbox = true,
1314 .has_outbox = false,
1315 .out_is_imm = false,
1316 .encode_slave_id = true,
1317 .verify = NULL,
1318 .wrapper = mlx4_RST2INIT_QP_wrapper
1319 },
1320 {
1321 .opcode = MLX4_CMD_INIT2INIT_QP,
1322 .has_inbox = true,
1323 .has_outbox = false,
1324 .out_is_imm = false,
1325 .encode_slave_id = false,
1326 .verify = NULL,
54679e14 1327 .wrapper = mlx4_INIT2INIT_QP_wrapper
c82e9aa0
EC		 1328 },
1329 {
1330 .opcode = MLX4_CMD_INIT2RTR_QP,
1331 .has_inbox = true,
1332 .has_outbox = false,
1333 .out_is_imm = false,
1334 .encode_slave_id = false,
1335 .verify = NULL,
1336 .wrapper = mlx4_INIT2RTR_QP_wrapper
1337 },
1338 {
1339 .opcode = MLX4_CMD_RTR2RTS_QP,
1340 .has_inbox = true,
1341 .has_outbox = false,
1342 .out_is_imm = false,
1343 .encode_slave_id = false,
1344 .verify = NULL,
54679e14 1345 .wrapper = mlx4_RTR2RTS_QP_wrapper
c82e9aa0
EC		 1346 },
1347 {
1348 .opcode = MLX4_CMD_RTS2RTS_QP,
1349 .has_inbox = true,
1350 .has_outbox = false,
1351 .out_is_imm = false,
1352 .encode_slave_id = false,
1353 .verify = NULL,
54679e14 1354 .wrapper = mlx4_RTS2RTS_QP_wrapper
c82e9aa0
EC		 1355 },
1356 {
1357 .opcode = MLX4_CMD_SQERR2RTS_QP,
1358 .has_inbox = true,
1359 .has_outbox = false,
1360 .out_is_imm = false,
1361 .encode_slave_id = false,
1362 .verify = NULL,
54679e14 1363 .wrapper = mlx4_SQERR2RTS_QP_wrapper
c82e9aa0
EC		 1364 },
1365 {
1366 .opcode = MLX4_CMD_2ERR_QP,
1367 .has_inbox = false,
1368 .has_outbox = false,
1369 .out_is_imm = false,
1370 .encode_slave_id = false,
1371 .verify = NULL,
1372 .wrapper = mlx4_GEN_QP_wrapper
1373 },
1374 {
1375 .opcode = MLX4_CMD_RTS2SQD_QP,
1376 .has_inbox = false,
1377 .has_outbox = false,
1378 .out_is_imm = false,
1379 .encode_slave_id = false,
1380 .verify = NULL,
1381 .wrapper = mlx4_GEN_QP_wrapper
1382 },
1383 {
1384 .opcode = MLX4_CMD_SQD2SQD_QP,
1385 .has_inbox = true,
1386 .has_outbox = false,
1387 .out_is_imm = false,
1388 .encode_slave_id = false,
1389 .verify = NULL,
54679e14 1390 .wrapper = mlx4_SQD2SQD_QP_wrapper
c82e9aa0
EC		 1391 },
1392 {
1393 .opcode = MLX4_CMD_SQD2RTS_QP,
1394 .has_inbox = true,
1395 .has_outbox = false,
1396 .out_is_imm = false,
1397 .encode_slave_id = false,
1398 .verify = NULL,
54679e14 1399 .wrapper = mlx4_SQD2RTS_QP_wrapper
c82e9aa0
EC		 1400 },
1401 {
1402 .opcode = MLX4_CMD_2RST_QP,
1403 .has_inbox = false,
1404 .has_outbox = false,
1405 .out_is_imm = false,
1406 .encode_slave_id = false,
1407 .verify = NULL,
1408 .wrapper = mlx4_2RST_QP_wrapper
1409 },
1410 {
1411 .opcode = MLX4_CMD_QUERY_QP,
1412 .has_inbox = false,
1413 .has_outbox = true,
1414 .out_is_imm = false,
1415 .encode_slave_id = false,
1416 .verify = NULL,
1417 .wrapper = mlx4_GEN_QP_wrapper
1418 },
1419 {
1420 .opcode = MLX4_CMD_SUSPEND_QP,
1421 .has_inbox = false,
1422 .has_outbox = false,
1423 .out_is_imm = false,
1424 .encode_slave_id = false,
1425 .verify = NULL,
1426 .wrapper = mlx4_GEN_QP_wrapper
1427 },
1428 {
1429 .opcode = MLX4_CMD_UNSUSPEND_QP,
1430 .has_inbox = false,
1431 .has_outbox = false,
1432 .out_is_imm = false,
1433 .encode_slave_id = false,
1434 .verify = NULL,
1435 .wrapper = mlx4_GEN_QP_wrapper
1436 },
b01978ca
JM		 1437 {
1438 .opcode = MLX4_CMD_UPDATE_QP,
ce8d9e0d 1439 .has_inbox = true,
b01978ca
JM		 1440 .has_outbox = false,
1441 .out_is_imm = false,
1442 .encode_slave_id = false,
1443 .verify = NULL,
ce8d9e0d 1444 .wrapper = mlx4_UPDATE_QP_wrapper
b01978ca 1445 },
fe6f700d
YP		 1446 {
1447 .opcode = MLX4_CMD_GET_OP_REQ,
1448 .has_inbox = false,
1449 .has_outbox = false,
1450 .out_is_imm = false,
1451 .encode_slave_id = false,
1452 .verify = NULL,
b7475794 1453 .wrapper = mlx4_CMD_EPERM_wrapper,
fe6f700d 1454 },
0a9a0188
JM		 1455 {
1456 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1457 .has_inbox = false,
1458 .has_outbox = false,
1459 .out_is_imm = false,
1460 .encode_slave_id = false,
1461 .verify = NULL, /* XXX verify: only demux can do this */
1462 .wrapper = NULL
1463 },
1464 {
1465 .opcode = MLX4_CMD_MAD_IFC,
1466 .has_inbox = true,
1467 .has_outbox = true,
1468 .out_is_imm = false,
1469 .encode_slave_id = false,
1470 .verify = NULL,
1471 .wrapper = mlx4_MAD_IFC_wrapper
1472 },
114840c3
JM		 1473 {
1474 .opcode = MLX4_CMD_MAD_DEMUX,
1475 .has_inbox = false,
1476 .has_outbox = false,
1477 .out_is_imm = false,
1478 .encode_slave_id = false,
1479 .verify = NULL,
1480 .wrapper = mlx4_CMD_EPERM_wrapper
1481 },
c82e9aa0
EC		 1482 {
1483 .opcode = MLX4_CMD_QUERY_IF_STAT,
1484 .has_inbox = false,
1485 .has_outbox = true,
1486 .out_is_imm = false,
1487 .encode_slave_id = false,
1488 .verify = NULL,
1489 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1490 },
adbc7ac5
SM		 1491 {
1492 .opcode = MLX4_CMD_ACCESS_REG,
1493 .has_inbox = true,
1494 .has_outbox = true,
1495 .out_is_imm = false,
1496 .encode_slave_id = false,
1497 .verify = NULL,
6e806699 1498 .wrapper = mlx4_ACCESS_REG_wrapper,
adbc7ac5 1499 },
c82e9aa0
EC		 1500 /* Native multicast commands are not available for guests */
1501 {
1502 .opcode = MLX4_CMD_QP_ATTACH,
1503 .has_inbox = true,
1504 .has_outbox = false,
1505 .out_is_imm = false,
1506 .encode_slave_id = false,
1507 .verify = NULL,
1508 .wrapper = mlx4_QP_ATTACH_wrapper
1509 },
0ec2c0f8
EE		 1510 {
1511 .opcode = MLX4_CMD_PROMISC,
1512 .has_inbox = false,
1513 .has_outbox = false,
1514 .out_is_imm = false,
1515 .encode_slave_id = false,
1516 .verify = NULL,
1517 .wrapper = mlx4_PROMISC_wrapper
1518 },
ffe455ad
EE		 1519 /* Ethernet specific commands */
1520 {
1521 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1522 .has_inbox = true,
1523 .has_outbox = false,
1524 .out_is_imm = false,
1525 .encode_slave_id = false,
1526 .verify = NULL,
1527 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1528 },
1529 {
1530 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1531 .has_inbox = false,
1532 .has_outbox = false,
1533 .out_is_imm = false,
1534 .encode_slave_id = false,
1535 .verify = NULL,
1536 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1537 },
1538 {
1539 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1540 .has_inbox = false,
1541 .has_outbox = true,
1542 .out_is_imm = false,
1543 .encode_slave_id = false,
1544 .verify = NULL,
1545 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1546 },
c82e9aa0
EC		 1547 {
1548 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1549 .has_inbox = false,
1550 .has_outbox = false,
1551 .out_is_imm = false,
1552 .encode_slave_id = false,
1553 .verify = NULL,
1554 .wrapper = NULL
1555 },
8fcfb4db
HHZ		 1556 /* flow steering commands */
1557 {
1558 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1559 .has_inbox = true,
1560 .has_outbox = false,
1561 .out_is_imm = true,
1562 .encode_slave_id = false,
1563 .verify = NULL,
1564 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1565 },
1566 {
1567 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1568 .has_inbox = false,
1569 .has_outbox = false,
1570 .out_is_imm = false,
1571 .encode_slave_id = false,
1572 .verify = NULL,
1573 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1574 },
4de65803
MB		 1575 {
1576 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1577 .has_inbox = false,
1578 .has_outbox = false,
1579 .out_is_imm = false,
1580 .encode_slave_id = false,
1581 .verify = NULL,
b7475794 1582 .wrapper = mlx4_CMD_EPERM_wrapper
4de65803 1583 },
e8f081aa
YP		 1584};
1585
1586static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1587 struct mlx4_vhcr_cmd *in_vhcr)
1588{
1589 struct mlx4_priv *priv = mlx4_priv(dev);
1590 struct mlx4_cmd_info *cmd = NULL;
1591 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1592 struct mlx4_vhcr *vhcr;
1593 struct mlx4_cmd_mailbox *inbox = NULL;
1594 struct mlx4_cmd_mailbox *outbox = NULL;
1595 u64 in_param;
1596 u64 out_param;
1597 int ret = 0;
1598 int i;
72be84f1 1599 int err = 0;
e8f081aa
YP		 1600
1601 /* Create sw representation of Virtual HCR */
1602 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1603 if (!vhcr)
1604 return -ENOMEM;
1605
1606 /* DMA in the vHCR */
1607 if (!in_vhcr) {
1608 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1609 priv->mfunc.master.slave_state[slave].vhcr_dma,
1610 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1611 MLX4_ACCESS_MEM_ALIGN), 1);
1612 if (ret) {
0cd93027
YH		 1613 if (!(dev->persist->state &
1614 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1615 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1616 __func__, ret);
e8f081aa
YP		 1617 kfree(vhcr);
1618 return ret;
1619 }
1620 }
1621
1622 /* Fill SW VHCR fields */
1623 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1624 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1625 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1626 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1627 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1628 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1629 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1630
1631 /* Lookup command */
1632 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1633 if (vhcr->op == cmd_info[i].opcode) {
1634 cmd = &cmd_info[i];
1635 break;
1636 }
1637 }
1638 if (!cmd) {
1639 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1640 vhcr->op, slave);
72be84f1 1641 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 1642 goto out_status;
1643 }
1644
1645 /* Read inbox */
1646 if (cmd->has_inbox) {
1647 vhcr->in_param &= INBOX_MASK;
1648 inbox = mlx4_alloc_cmd_mailbox(dev);
1649 if (IS_ERR(inbox)) {
72be84f1 1650 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1651 inbox = NULL;
72be84f1 1652 goto out_status;
e8f081aa
YP		 1653 }
1654
0cd93027
YH		 1655 ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1656 vhcr->in_param,
1657 MLX4_MAILBOX_SIZE, 1);
1658 if (ret) {
1659 if (!(dev->persist->state &
1660 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1661 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1662 __func__, cmd->opcode);
72be84f1
YP		 1663 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1664 goto out_status;
e8f081aa
YP		 1665 }
1666 }
1667
1668 /* Apply permission and bound checks if applicable */
1669 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1a91de28
JP		 1670 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1671 vhcr->op, slave, vhcr->in_modifier);
72be84f1 1672 vhcr_cmd->status = CMD_STAT_BAD_OP;
e8f081aa
YP		 1673 goto out_status;
1674 }
1675
1676 /* Allocate outbox */
1677 if (cmd->has_outbox) {
1678 outbox = mlx4_alloc_cmd_mailbox(dev);
1679 if (IS_ERR(outbox)) {
72be84f1 1680 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1681 outbox = NULL;
72be84f1 1682 goto out_status;
e8f081aa
YP		 1683 }
1684 }
1685
1686 /* Execute the command! */
1687 if (cmd->wrapper) {
72be84f1
YP		 1688 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1689 cmd);
e8f081aa
YP		 1690 if (cmd->out_is_imm)
1691 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1692 } else {
1693 in_param = cmd->has_inbox ? (u64) inbox->dma :
1694 vhcr->in_param;
1695 out_param = cmd->has_outbox ? (u64) outbox->dma :
1696 vhcr->out_param;
72be84f1
YP		 1697 err = __mlx4_cmd(dev, in_param, &out_param,
1698 cmd->out_is_imm, vhcr->in_modifier,
1699 vhcr->op_modifier, vhcr->op,
1700 MLX4_CMD_TIME_CLASS_A,
1701 MLX4_CMD_NATIVE);
e8f081aa
YP		 1702
1703 if (cmd->out_is_imm) {
1704 vhcr->out_param = out_param;
1705 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1706 }
1707 }
1708
72be84f1 1709 if (err) {
0cd93027
YH		 1710 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR))
1711 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1712 vhcr->op, slave, vhcr->errno, err);
72be84f1
YP		 1713 vhcr_cmd->status = mlx4_errno_to_status(err);
1714 goto out_status;
1715 }
1716
1717
e8f081aa 1718 /* Write outbox if command completed successfully */
72be84f1 1719 if (cmd->has_outbox && !vhcr_cmd->status) {
e8f081aa
YP		 1720 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1721 vhcr->out_param,
1722 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1723 if (ret) {
72be84f1
YP		 1724 /* If we failed to write back the outbox after the
1725 *command was successfully executed, we must fail this
1726 * slave, as it is now in undefined state */
0cd93027
YH		 1727 if (!(dev->persist->state &
1728 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1729 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
e8f081aa
YP		 1730 goto out;
1731 }
1732 }
1733
1734out_status:
1735 /* DMA back vhcr result */
1736 if (!in_vhcr) {
1737 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1738 priv->mfunc.master.slave_state[slave].vhcr_dma,
1739 ALIGN(sizeof(struct mlx4_vhcr),
1740 MLX4_ACCESS_MEM_ALIGN),
1741 MLX4_CMD_WRAPPED);
1742 if (ret)
1743 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1744 __func__);
1745 else if (vhcr->e_bit &&
1746 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1a91de28
JP		 1747 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1748 slave);
e8f081aa
YP		 1749 }
1750
1751out:
1752 kfree(vhcr);
1753 mlx4_free_cmd_mailbox(dev, inbox);
1754 mlx4_free_cmd_mailbox(dev, outbox);
1755 return ret;
1756}
1757
f094668c 1758static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
b01978ca
JM		 1759 int slave, int port)
1760{
1761 struct mlx4_vport_oper_state *vp_oper;
1762 struct mlx4_vport_state *vp_admin;
1763 struct mlx4_vf_immed_vlan_work *work;
0a6eac24 1764 struct mlx4_dev *dev = &(priv->dev);
b01978ca
JM		 1765 int err;
1766 int admin_vlan_ix = NO_INDX;
1767
1768 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1769 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1770
1771 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
0a6eac24
RE		 1772 vp_oper->state.default_qos == vp_admin->default_qos &&
1773 vp_oper->state.link_state == vp_admin->link_state)
b01978ca
JM		 1774 return 0;
1775
0a6eac24 1776 if (!(priv->mfunc.master.slave_state[slave].active &&
f0f829bf 1777 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
0a6eac24
RE		 1778 /* even if the UPDATE_QP command isn't supported, we still want
1779 * to set this VF link according to the admin directive
1780 */
1781 vp_oper->state.link_state = vp_admin->link_state;
1782 return -1;
1783 }
1784
1785 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1786 slave, port);
1a91de28
JP		 1787 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1788 vp_admin->default_vlan, vp_admin->default_qos,
1789 vp_admin->link_state);
0a6eac24 1790
b01978ca
JM		 1791 work = kzalloc(sizeof(*work), GFP_KERNEL);
1792 if (!work)
1793 return -ENOMEM;
1794
1795 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
f0f829bf
RE		 1796 if (MLX4_VGT != vp_admin->default_vlan) {
1797 err = __mlx4_register_vlan(&priv->dev, port,
1798 vp_admin->default_vlan,
1799 &admin_vlan_ix);
1800 if (err) {
1801 kfree(work);
1a91de28 1802 mlx4_warn(&priv->dev,
f0f829bf
RE		 1803 "No vlan resources slave %d, port %d\n",
1804 slave, port);
1805 return err;
1806 }
1807 } else {
1808 admin_vlan_ix = NO_INDX;
b01978ca
JM		 1809 }
1810 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1a91de28 1811 mlx4_dbg(&priv->dev,
b01978ca
JM		 1812 "alloc vlan %d idx %d slave %d port %d\n",
1813 (int)(vp_admin->default_vlan),
1814 admin_vlan_ix, slave, port);
1815 }
1816
1817 /* save original vlan ix and vlan id */
1818 work->orig_vlan_id = vp_oper->state.default_vlan;
1819 work->orig_vlan_ix = vp_oper->vlan_idx;
1820
1821 /* handle new qos */
1822 if (vp_oper->state.default_qos != vp_admin->default_qos)
1823 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1824
1825 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1826 vp_oper->vlan_idx = admin_vlan_ix;
1827
1828 vp_oper->state.default_vlan = vp_admin->default_vlan;
1829 vp_oper->state.default_qos = vp_admin->default_qos;
0a6eac24
RE		 1830 vp_oper->state.link_state = vp_admin->link_state;
1831
1832 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1833 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
b01978ca
JM		 1834
1835 /* iterate over QPs owned by this slave, using UPDATE_QP */
1836 work->port = port;
1837 work->slave = slave;
1838 work->qos = vp_oper->state.default_qos;
1839 work->vlan_id = vp_oper->state.default_vlan;
1840 work->vlan_ix = vp_oper->vlan_idx;
1841 work->priv = priv;
1842 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1843 queue_work(priv->mfunc.master.comm_wq, &work->work);
1844
1845 return 0;
1846}
1847
1848
0eb62b93
RE		 1849static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1850{
3f7fb021
RE		 1851 int port, err;
1852 struct mlx4_vport_state *vp_admin;
1853 struct mlx4_vport_oper_state *vp_oper;
449fc488
MB		 1854 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1855 &priv->dev, slave);
1856 int min_port = find_first_bit(actv_ports.ports,
1857 priv->dev.caps.num_ports) + 1;
1858 int max_port = min_port - 1 +
1859 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1860
1861 for (port = min_port; port <= max_port; port++) {
1862 if (!test_bit(port - 1, actv_ports.ports))
1863 continue;
99ec41d0
JM		 1864 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1865 priv->mfunc.master.vf_admin[slave].enable_smi[port];
3f7fb021
RE		 1866 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1867 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1868 vp_oper->state = *vp_admin;
1869 if (MLX4_VGT != vp_admin->default_vlan) {
1870 err = __mlx4_register_vlan(&priv->dev, port,
1871 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1872 if (err) {
1873 vp_oper->vlan_idx = NO_INDX;
1a91de28 1874 mlx4_warn(&priv->dev,
1a84db56 1875 "No vlan resources slave %d, port %d\n",
3f7fb021
RE		 1876 slave, port);
1877 return err;
1878 }
1a91de28 1879 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
3f7fb021
RE		 1880 (int)(vp_oper->state.default_vlan),
1881 vp_oper->vlan_idx, slave, port);
1882 }
e6b6a231
RE		 1883 if (vp_admin->spoofchk) {
1884 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1885 port,
1886 vp_admin->mac);
1887 if (0 > vp_oper->mac_idx) {
1888 err = vp_oper->mac_idx;
1889 vp_oper->mac_idx = NO_INDX;
1a91de28 1890 mlx4_warn(&priv->dev,
1a84db56 1891 "No mac resources slave %d, port %d\n",
e6b6a231
RE		 1892 slave, port);
1893 return err;
1894 }
1a91de28 1895 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
e6b6a231
RE		 1896 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1897 }
0eb62b93
RE		 1898 }
1899 return 0;
1900}
1901
3f7fb021
RE		 1902static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1903{
1904 int port;
1905 struct mlx4_vport_oper_state *vp_oper;
449fc488
MB		 1906 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1907 &priv->dev, slave);
1908 int min_port = find_first_bit(actv_ports.ports,
1909 priv->dev.caps.num_ports) + 1;
1910 int max_port = min_port - 1 +
1911 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1912
3f7fb021 1913
449fc488
MB		 1914 for (port = min_port; port <= max_port; port++) {
1915 if (!test_bit(port - 1, actv_ports.ports))
1916 continue;
99ec41d0
JM		 1917 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1918 MLX4_VF_SMI_DISABLED;
3f7fb021
RE		 1919 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1920 if (NO_INDX != vp_oper->vlan_idx) {
1921 __mlx4_unregister_vlan(&priv->dev,
2009d005 1922 port, vp_oper->state.default_vlan);
3f7fb021
RE		 1923 vp_oper->vlan_idx = NO_INDX;
1924 }
e6b6a231 1925 if (NO_INDX != vp_oper->mac_idx) {
c32b7dfb 1926 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
e6b6a231
RE		 1927 vp_oper->mac_idx = NO_INDX;
1928 }
3f7fb021
RE		 1929 }
1930 return;
1931}
1932
e8f081aa
YP		 1933static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1934 u16 param, u8 toggle)
1935{
1936 struct mlx4_priv *priv = mlx4_priv(dev);
1937 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1938 u32 reply;
e8f081aa 1939 u8 is_going_down = 0;
803143fb 1940 int i;
311f813a 1941 unsigned long flags;
e8f081aa
YP		 1942
1943 slave_state[slave].comm_toggle ^= 1;
1944 reply = (u32) slave_state[slave].comm_toggle << 31;
1945 if (toggle != slave_state[slave].comm_toggle) {
1a91de28
JP		 1946 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
1947 toggle, slave);
e8f081aa
YP		 1948 goto reset_slave;
1949 }
1950 if (cmd == MLX4_COMM_CMD_RESET) {
1951 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1952 slave_state[slave].active = false;
2c957ff2 1953 slave_state[slave].old_vlan_api = false;
3f7fb021 1954 mlx4_master_deactivate_admin_state(priv, slave);
803143fb
MA		 1955 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1956 slave_state[slave].event_eq[i].eqn = -1;
1957 slave_state[slave].event_eq[i].token = 0;
1958 }
e8f081aa
YP		 1959 /*check if we are in the middle of FLR process,
1960 if so return "retry" status to the slave*/
162344ed 1961 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
e8f081aa 1962 goto inform_slave_state;
e8f081aa 1963
fc06573d
JM		 1964 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1965
e8f081aa
YP		 1966 /* write the version in the event field */
1967 reply |= mlx4_comm_get_version();
1968
1969 goto reset_slave;
1970 }
1971 /*command from slave in the middle of FLR*/
1972 if (cmd != MLX4_COMM_CMD_RESET &&
1973 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1a91de28
JP		 1974 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
1975 slave, cmd);
e8f081aa
YP		 1976 return;
1977 }
1978
1979 switch (cmd) {
1980 case MLX4_COMM_CMD_VHCR0:
1981 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1982 goto reset_slave;
1983 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1984 priv->mfunc.master.slave_state[slave].cookie = 0;
1985 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1986 break;
1987 case MLX4_COMM_CMD_VHCR1:
1988 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1989 goto reset_slave;
1990 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1991 break;
1992 case MLX4_COMM_CMD_VHCR2:
1993 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1994 goto reset_slave;
1995 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1996 break;
1997 case MLX4_COMM_CMD_VHCR_EN:
1998 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1999 goto reset_slave;
2000 slave_state[slave].vhcr_dma |= param;
3f7fb021
RE		 2001 if (mlx4_master_activate_admin_state(priv, slave))
2002 goto reset_slave;
e8f081aa 2003 slave_state[slave].active = true;
fc06573d 2004 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
e8f081aa
YP		 2005 break;
2006 case MLX4_COMM_CMD_VHCR_POST:
2007 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
55ad3592
YH		 2008 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) {
2009 mlx4_warn(dev, "slave:%d is out of sync, cmd=0x%x, last command=0x%x, reset is needed\n",
2010 slave, cmd, slave_state[slave].last_cmd);
e8f081aa 2011 goto reset_slave;
55ad3592 2012 }
f3d4c89e
RD		 2013
2014 mutex_lock(&priv->cmd.slave_cmd_mutex);
e8f081aa 2015 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1a91de28
JP		 2016 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
2017 slave);
f3d4c89e 2018 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 2019 goto reset_slave;
2020 }
f3d4c89e 2021 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 2022 break;
2023 default:
2024 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
2025 goto reset_slave;
2026 }
311f813a 2027 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 2028 if (!slave_state[slave].is_slave_going_down)
2029 slave_state[slave].last_cmd = cmd;
2030 else
2031 is_going_down = 1;
311f813a 2032 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa 2033 if (is_going_down) {
1a91de28 2034 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
e8f081aa
YP		 2035 cmd, slave);
2036 return;
2037 }
2038 __raw_writel((__force u32) cpu_to_be32(reply),
2039 &priv->mfunc.comm[slave].slave_read);
2040 mmiowb();
2041
2042 return;
2043
2044reset_slave:
c82e9aa0 2045 /* cleanup any slave resources */
55ad3592
YH		 2046 if (dev->persist->interface_state & MLX4_INTERFACE_STATE_UP)
2047 mlx4_delete_all_resources_for_slave(dev, slave);
2048
2049 if (cmd != MLX4_COMM_CMD_RESET) {
2050 mlx4_warn(dev, "Turn on internal error to force reset, slave=%d, cmd=0x%x\n",
2051 slave, cmd);
2052 /* Turn on internal error letting slave reset itself immeditaly,
2053 * otherwise it might take till timeout on command is passed
2054 */
2055 reply |= ((u32)COMM_CHAN_EVENT_INTERNAL_ERR);
2056 }
2057
311f813a 2058 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 2059 if (!slave_state[slave].is_slave_going_down)
2060 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
311f813a 2061 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 2062 /*with slave in the middle of flr, no need to clean resources again.*/
2063inform_slave_state:
2064 memset(&slave_state[slave].event_eq, 0,
2065 sizeof(struct mlx4_slave_event_eq_info));
2066 __raw_writel((__force u32) cpu_to_be32(reply),
2067 &priv->mfunc.comm[slave].slave_read);
2068 wmb();
2069}
2070
2071/* master command processing */
2072void mlx4_master_comm_channel(struct work_struct *work)
2073{
2074 struct mlx4_mfunc_master_ctx *master =
2075 container_of(work,
2076 struct mlx4_mfunc_master_ctx,
2077 comm_work);
2078 struct mlx4_mfunc *mfunc =
2079 container_of(master, struct mlx4_mfunc, master);
2080 struct mlx4_priv *priv =
2081 container_of(mfunc, struct mlx4_priv, mfunc);
2082 struct mlx4_dev *dev = &priv->dev;
2083 __be32 *bit_vec;
2084 u32 comm_cmd;
2085 u32 vec;
2086 int i, j, slave;
2087 int toggle;
2088 int served = 0;
2089 int reported = 0;
2090 u32 slt;
2091
2092 bit_vec = master->comm_arm_bit_vector;
2093 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
2094 vec = be32_to_cpu(bit_vec[i]);
2095 for (j = 0; j < 32; j++) {
2096 if (!(vec & (1 << j)))
2097 continue;
2098 ++reported;
2099 slave = (i * 32) + j;
2100 comm_cmd = swab32(readl(
2101 &mfunc->comm[slave].slave_write));
2102 slt = swab32(readl(&mfunc->comm[slave].slave_read))
2103 >> 31;
2104 toggle = comm_cmd >> 31;
2105 if (toggle != slt) {
2106 if (master->slave_state[slave].comm_toggle
2107 != slt) {
c20862c8
AV		 2108 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
2109 slave, slt,
2110 master->slave_state[slave].comm_toggle);
e8f081aa
YP		 2111 master->slave_state[slave].comm_toggle =
2112 slt;
2113 }
2114 mlx4_master_do_cmd(dev, slave,
2115 comm_cmd >> 16 & 0xff,
2116 comm_cmd & 0xffff, toggle);
2117 ++served;
2118 }
2119 }
2120 }
2121
2122 if (reported && reported != served)
1a91de28 2123 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
e8f081aa
YP		 2124 reported, served);
2125
2126 if (mlx4_ARM_COMM_CHANNEL(dev))
2127 mlx4_warn(dev, "Failed to arm comm channel events\n");
2128}
2129
ab9c17a0
JM		 2130static int sync_toggles(struct mlx4_dev *dev)
2131{
2132 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592
YH		 2133 u32 wr_toggle;
2134 u32 rd_toggle;
ab9c17a0
JM		 2135 unsigned long end;
2136
55ad3592
YH		 2137 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write));
2138 if (wr_toggle == 0xffffffff)
2139 end = jiffies + msecs_to_jiffies(30000);
2140 else
2141 end = jiffies + msecs_to_jiffies(5000);
ab9c17a0
JM		 2142
2143 while (time_before(jiffies, end)) {
55ad3592
YH		 2144 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2145 if (wr_toggle == 0xffffffff || rd_toggle == 0xffffffff) {
2146 /* PCI might be offline */
2147 msleep(100);
2148 wr_toggle = swab32(readl(&priv->mfunc.comm->
2149 slave_write));
2150 continue;
2151 }
2152
2153 if (rd_toggle >> 31 == wr_toggle >> 31) {
2154 priv->cmd.comm_toggle = rd_toggle >> 31;
ab9c17a0
JM		 2155 return 0;
2156 }
2157
2158 cond_resched();
2159 }
2160
2161 /*
2162 * we could reach here if for example the previous VM using this
2163 * function misbehaved and left the channel with unsynced state. We
2164 * should fix this here and give this VM a chance to use a properly
2165 * synced channel
2166 */
2167 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
2168 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
2169 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
2170 priv->cmd.comm_toggle = 0;
2171
2172 return 0;
2173}
2174
2175int mlx4_multi_func_init(struct mlx4_dev *dev)
2176{
2177 struct mlx4_priv *priv = mlx4_priv(dev);
2178 struct mlx4_slave_state *s_state;
803143fb 2179 int i, j, err, port;
ab9c17a0 2180
ab9c17a0
JM		 2181 if (mlx4_is_master(dev))
2182 priv->mfunc.comm =
872bf2fb
YH		 2183 ioremap(pci_resource_start(dev->persist->pdev,
2184 priv->fw.comm_bar) +
ab9c17a0
JM		 2185 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
2186 else
2187 priv->mfunc.comm =
872bf2fb 2188 ioremap(pci_resource_start(dev->persist->pdev, 2) +
ab9c17a0
JM		 2189 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
2190 if (!priv->mfunc.comm) {
1a91de28 2191 mlx4_err(dev, "Couldn't map communication vector\n");
ab9c17a0
JM		 2192 goto err_vhcr;
2193 }
2194
2195 if (mlx4_is_master(dev)) {
2196 priv->mfunc.master.slave_state =
2197 kzalloc(dev->num_slaves *
2198 sizeof(struct mlx4_slave_state), GFP_KERNEL);
2199 if (!priv->mfunc.master.slave_state)
2200 goto err_comm;
2201
0eb62b93
RE		 2202 priv->mfunc.master.vf_admin =
2203 kzalloc(dev->num_slaves *
2204 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
2205 if (!priv->mfunc.master.vf_admin)
2206 goto err_comm_admin;
2207
2208 priv->mfunc.master.vf_oper =
2209 kzalloc(dev->num_slaves *
2210 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
2211 if (!priv->mfunc.master.vf_oper)
2212 goto err_comm_oper;
2213
ab9c17a0
JM		 2214 for (i = 0; i < dev->num_slaves; ++i) {
2215 s_state = &priv->mfunc.master.slave_state[i];
2216 s_state->last_cmd = MLX4_COMM_CMD_RESET;
803143fb
MA		 2217 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2218 s_state->event_eq[j].eqn = -1;
ab9c17a0
JM		 2219 __raw_writel((__force u32) 0,
2220 &priv->mfunc.comm[i].slave_write);
2221 __raw_writel((__force u32) 0,
2222 &priv->mfunc.comm[i].slave_read);
2223 mmiowb();
2224 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2225 s_state->vlan_filter[port] =
2226 kzalloc(sizeof(struct mlx4_vlan_fltr),
2227 GFP_KERNEL);
2228 if (!s_state->vlan_filter[port]) {
2229 if (--port)
2230 kfree(s_state->vlan_filter[port]);
2231 goto err_slaves;
2232 }
2233 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
0eb62b93 2234 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
3f7fb021 2235 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
0eb62b93
RE		 2236 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
2237 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
ab9c17a0
JM		 2238 }
2239 spin_lock_init(&s_state->lock);
2240 }
2241
08ff3235 2242 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
ab9c17a0
JM		 2243 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2244 INIT_WORK(&priv->mfunc.master.comm_work,
2245 mlx4_master_comm_channel);
2246 INIT_WORK(&priv->mfunc.master.slave_event_work,
2247 mlx4_gen_slave_eqe);
2248 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2249 mlx4_master_handle_slave_flr);
2250 spin_lock_init(&priv->mfunc.master.slave_state_lock);
992e8e6e 2251 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
ab9c17a0
JM		 2252 priv->mfunc.master.comm_wq =
2253 create_singlethread_workqueue("mlx4_comm");
2254 if (!priv->mfunc.master.comm_wq)
2255 goto err_slaves;
2256
2257 if (mlx4_init_resource_tracker(dev))
2258 goto err_thread;
2259
ab9c17a0
JM		 2260 } else {
2261 err = sync_toggles(dev);
2262 if (err) {
2263 mlx4_err(dev, "Couldn't sync toggles\n");
2264 goto err_comm;
2265 }
ab9c17a0
JM		 2266 }
2267 return 0;
2268
ab9c17a0
JM		 2269err_thread:
2270 flush_workqueue(priv->mfunc.master.comm_wq);
2271 destroy_workqueue(priv->mfunc.master.comm_wq);
2272err_slaves:
2273 while (--i) {
2274 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2275 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2276 }
0eb62b93
RE		 2277 kfree(priv->mfunc.master.vf_oper);
2278err_comm_oper:
2279 kfree(priv->mfunc.master.vf_admin);
2280err_comm_admin:
ab9c17a0
JM		 2281 kfree(priv->mfunc.master.slave_state);
2282err_comm:
2283 iounmap(priv->mfunc.comm);
2284err_vhcr:
872bf2fb
YH		 2285 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2286 priv->mfunc.vhcr,
2287 priv->mfunc.vhcr_dma);
ab9c17a0
JM		 2288 priv->mfunc.vhcr = NULL;
2289 return -ENOMEM;
2290}
2291
225c7b1f
RD		 2292int mlx4_cmd_init(struct mlx4_dev *dev)
2293{
2294 struct mlx4_priv *priv = mlx4_priv(dev);
ffc39f6d
MB		 2295 int flags = 0;
2296
2297 if (!priv->cmd.initialized) {
ffc39f6d
MB		 2298 mutex_init(&priv->cmd.slave_cmd_mutex);
2299 sema_init(&priv->cmd.poll_sem, 1);
2300 priv->cmd.use_events = 0;
2301 priv->cmd.toggle = 1;
2302 priv->cmd.initialized = 1;
2303 flags |= MLX4_CMD_CLEANUP_STRUCT;
2304 }
225c7b1f 2305
ffc39f6d 2306 if (!mlx4_is_slave(dev) && !priv->cmd.hcr) {
872bf2fb
YH		 2307 priv->cmd.hcr = ioremap(pci_resource_start(dev->persist->pdev,
2308 0) + MLX4_HCR_BASE, MLX4_HCR_SIZE);
e8f081aa 2309 if (!priv->cmd.hcr) {
1a91de28 2310 mlx4_err(dev, "Couldn't map command register\n");
ffc39f6d 2311 goto err;
e8f081aa 2312 }
ffc39f6d 2313 flags |= MLX4_CMD_CLEANUP_HCR;
225c7b1f
RD		 2314 }
2315
ffc39f6d 2316 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) {
872bf2fb
YH		 2317 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev,
2318 PAGE_SIZE,
f3d4c89e
RD		 2319 &priv->mfunc.vhcr_dma,
2320 GFP_KERNEL);
d0320f75 2321 if (!priv->mfunc.vhcr)
ffc39f6d
MB		 2322 goto err;
2323
2324 flags |= MLX4_CMD_CLEANUP_VHCR;
f3d4c89e
RD		 2325 }
2326
ffc39f6d 2327 if (!priv->cmd.pool) {
872bf2fb
YH		 2328 priv->cmd.pool = pci_pool_create("mlx4_cmd",
2329 dev->persist->pdev,
ffc39f6d
MB		 2330 MLX4_MAILBOX_SIZE,
2331 MLX4_MAILBOX_SIZE, 0);
2332 if (!priv->cmd.pool)
2333 goto err;
225c7b1f 2334
ffc39f6d
MB		 2335 flags |= MLX4_CMD_CLEANUP_POOL;
2336 }
e8f081aa 2337
ffc39f6d 2338 return 0;
f3d4c89e 2339
ffc39f6d
MB		 2340err:
2341 mlx4_cmd_cleanup(dev, flags);
e8f081aa 2342 return -ENOMEM;
225c7b1f
RD		 2343}
2344
55ad3592
YH		 2345void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev)
2346{
2347 struct mlx4_priv *priv = mlx4_priv(dev);
2348 int slave;
2349 u32 slave_read;
2350
2351 /* Report an internal error event to all
2352 * communication channels.
2353 */
2354 for (slave = 0; slave < dev->num_slaves; slave++) {
2355 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read));
2356 slave_read |= (u32)COMM_CHAN_EVENT_INTERNAL_ERR;
2357 __raw_writel((__force u32)cpu_to_be32(slave_read),
2358 &priv->mfunc.comm[slave].slave_read);
2359 /* Make sure that our comm channel write doesn't
2360 * get mixed in with writes from another CPU.
2361 */
2362 mmiowb();
2363 }
2364}
2365
ab9c17a0
JM		 2366void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2367{
2368 struct mlx4_priv *priv = mlx4_priv(dev);
2369 int i, port;
2370
2371 if (mlx4_is_master(dev)) {
2372 flush_workqueue(priv->mfunc.master.comm_wq);
2373 destroy_workqueue(priv->mfunc.master.comm_wq);
2374 for (i = 0; i < dev->num_slaves; i++) {
2375 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2376 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2377 }
2378 kfree(priv->mfunc.master.slave_state);
0eb62b93
RE		 2379 kfree(priv->mfunc.master.vf_admin);
2380 kfree(priv->mfunc.master.vf_oper);
55ad3592 2381 dev->num_slaves = 0;
ab9c17a0 2382 }
f08ad06c
EE		 2383
2384 iounmap(priv->mfunc.comm);
ab9c17a0
JM		 2385}
2386
ffc39f6d 2387void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask)
225c7b1f
RD		 2388{
2389 struct mlx4_priv *priv = mlx4_priv(dev);
2390
ffc39f6d
MB		 2391 if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) {
2392 pci_pool_destroy(priv->cmd.pool);
2393 priv->cmd.pool = NULL;
2394 }
e8f081aa 2395
ffc39f6d
MB		 2396 if (!mlx4_is_slave(dev) && priv->cmd.hcr &&
2397 (cleanup_mask & MLX4_CMD_CLEANUP_HCR)) {
e8f081aa 2398 iounmap(priv->cmd.hcr);
ffc39f6d
MB		 2399 priv->cmd.hcr = NULL;
2400 }
2401 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr &&
2402 (cleanup_mask & MLX4_CMD_CLEANUP_VHCR)) {
872bf2fb 2403 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
f3d4c89e 2404 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
ffc39f6d
MB		 2405 priv->mfunc.vhcr = NULL;
2406 }
2407 if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT))
2408 priv->cmd.initialized = 0;
225c7b1f
RD		 2409}
2410
2411/*
2412 * Switch to using events to issue FW commands (can only be called
2413 * after event queue for command events has been initialized).
2414 */
2415int mlx4_cmd_use_events(struct mlx4_dev *dev)
2416{
2417 struct mlx4_priv *priv = mlx4_priv(dev);
2418 int i;
e8f081aa 2419 int err = 0;
225c7b1f
RD		 2420
2421 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2422 sizeof (struct mlx4_cmd_context),
2423 GFP_KERNEL);
2424 if (!priv->cmd.context)
2425 return -ENOMEM;
2426
2427 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2428 priv->cmd.context[i].token = i;
2429 priv->cmd.context[i].next = i + 1;
f5aef5aa
YH		 2430 /* To support fatal error flow, initialize all
2431 * cmd contexts to allow simulating completions
2432 * with complete() at any time.
2433 */
2434 init_completion(&priv->cmd.context[i].done);
225c7b1f
RD		 2435 }
2436
2437 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2438 priv->cmd.free_head = 0;
2439
2440 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2441 spin_lock_init(&priv->cmd.context_lock);
2442
2443 for (priv->cmd.token_mask = 1;
2444 priv->cmd.token_mask < priv->cmd.max_cmds;
2445 priv->cmd.token_mask <<= 1)
2446 ; /* nothing */
2447 --priv->cmd.token_mask;
2448
225c7b1f 2449 down(&priv->cmd.poll_sem);
e8f081aa 2450 priv->cmd.use_events = 1;
225c7b1f 2451
e8f081aa 2452 return err;
225c7b1f
RD		 2453}
2454
2455/*
2456 * Switch back to polling (used when shutting down the device)
2457 */
2458void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2459{
2460 struct mlx4_priv *priv = mlx4_priv(dev);
2461 int i;
2462
2463 priv->cmd.use_events = 0;
2464
2465 for (i = 0; i < priv->cmd.max_cmds; ++i)
2466 down(&priv->cmd.event_sem);
2467
2468 kfree(priv->cmd.context);
2469
2470 up(&priv->cmd.poll_sem);
2471}
2472
2473struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2474{
2475 struct mlx4_cmd_mailbox *mailbox;
2476
2477 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2478 if (!mailbox)
2479 return ERR_PTR(-ENOMEM);
2480
2481 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2482 &mailbox->dma);
2483 if (!mailbox->buf) {
2484 kfree(mailbox);
2485 return ERR_PTR(-ENOMEM);
2486 }
2487
571b8b92
JM		 2488 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2489
225c7b1f
RD		 2490 return mailbox;
2491}
2492EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2493
e8f081aa
YP		 2494void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2495 struct mlx4_cmd_mailbox *mailbox)
225c7b1f
RD		 2496{
2497 if (!mailbox)
2498 return;
2499
2500 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2501 kfree(mailbox);
2502}
2503EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
e8f081aa
YP		 2504
2505u32 mlx4_comm_get_version(void)
2506{
2507 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2508}
8f7ba3ca
RE		 2509
2510static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2511{
872bf2fb
YH		 2512 if ((vf < 0) || (vf >= dev->persist->num_vfs)) {
2513 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n",
2514 vf, dev->persist->num_vfs);
8f7ba3ca
RE		 2515 return -EINVAL;
2516 }
2517
2518 return vf+1;
2519}
2520
f74462ac
MB		 2521int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2522{
872bf2fb 2523 if (slave < 1 || slave > dev->persist->num_vfs) {
f74462ac
MB		 2524 mlx4_err(dev,
2525 "Bad slave number:%d (number of activated slaves: %lu)\n",
2526 slave, dev->num_slaves);
2527 return -EINVAL;
2528 }
2529 return slave - 1;
2530}
2531
f5aef5aa
YH		 2532void mlx4_cmd_wake_completions(struct mlx4_dev *dev)
2533{
2534 struct mlx4_priv *priv = mlx4_priv(dev);
2535 struct mlx4_cmd_context *context;
2536 int i;
2537
2538 spin_lock(&priv->cmd.context_lock);
2539 if (priv->cmd.context) {
2540 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2541 context = &priv->cmd.context[i];
2542 context->fw_status = CMD_STAT_INTERNAL_ERR;
2543 context->result =
2544 mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
2545 complete(&context->done);
2546 }
2547 }
2548 spin_unlock(&priv->cmd.context_lock);
2549}
2550
f74462ac
MB		 2551struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2552{
2553 struct mlx4_active_ports actv_ports;
2554 int vf;
2555
2556 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2557
2558 if (slave == 0) {
2559 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2560 return actv_ports;
2561 }
2562
2563 vf = mlx4_get_vf_indx(dev, slave);
2564 if (vf < 0)
2565 return actv_ports;
2566
2567 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2568 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2569 dev->caps.num_ports));
2570
2571 return actv_ports;
2572}
2573EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2574
2575int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2576{
2577 unsigned n;
2578 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2579 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2580
2581 if (port <= 0 || port > m)
2582 return -EINVAL;
2583
2584 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2585 if (port <= n)
2586 port = n + 1;
2587
2588 return port;
2589}
2590EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2591
2592int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2593{
2594 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2595 if (test_bit(port - 1, actv_ports.ports))
2596 return port -
2597 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2598
2599 return -1;
2600}
2601EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2602
2603struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2604 int port)
2605{
2606 unsigned i;
2607 struct mlx4_slaves_pport slaves_pport;
2608
2609 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2610
2611 if (port <= 0 || port > dev->caps.num_ports)
2612 return slaves_pport;
2613
872bf2fb 2614 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
f74462ac
MB		 2615 struct mlx4_active_ports actv_ports =
2616 mlx4_get_active_ports(dev, i);
2617 if (test_bit(port - 1, actv_ports.ports))
2618 set_bit(i, slaves_pport.slaves);
2619 }
2620
2621 return slaves_pport;
2622}
2623EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2624
2625struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2626 struct mlx4_dev *dev,
2627 const struct mlx4_active_ports *crit_ports)
2628{
2629 unsigned i;
2630 struct mlx4_slaves_pport slaves_pport;
2631
2632 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2633
872bf2fb 2634 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
f74462ac
MB		 2635 struct mlx4_active_ports actv_ports =
2636 mlx4_get_active_ports(dev, i);
2637 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2638 dev->caps.num_ports))
2639 set_bit(i, slaves_pport.slaves);
2640 }
2641
2642 return slaves_pport;
2643}
2644EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2645
a91c772f
MB		 2646static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port)
2647{
2648 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2649 int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports)
2650 + 1;
2651 int max_port = min_port +
2652 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2653
2654 if (port < min_port)
2655 port = min_port;
2656 else if (port >= max_port)
2657 port = max_port - 1;
2658
2659 return port;
2660}
2661
8f7ba3ca
RE		 2662int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2663{
2664 struct mlx4_priv *priv = mlx4_priv(dev);
2665 struct mlx4_vport_state *s_info;
2666 int slave;
2667
2668 if (!mlx4_is_master(dev))
2669 return -EPROTONOSUPPORT;
2670
2671 slave = mlx4_get_slave_indx(dev, vf);
2672 if (slave < 0)
2673 return -EINVAL;
2674
a91c772f 2675 port = mlx4_slaves_closest_port(dev, slave, port);
8f7ba3ca
RE		 2676 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2677 s_info->mac = mac;
2678 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2679 vf, port, s_info->mac);
2680 return 0;
2681}
2682EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
3f7fb021 2683
b01978ca 2684
3f7fb021
RE		 2685int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2686{
2687 struct mlx4_priv *priv = mlx4_priv(dev);
b01978ca 2688 struct mlx4_vport_state *vf_admin;
3f7fb021
RE		 2689 int slave;
2690
2691 if ((!mlx4_is_master(dev)) ||
2692 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2693 return -EPROTONOSUPPORT;
2694
2695 if ((vlan > 4095) || (qos > 7))
2696 return -EINVAL;
2697
2698 slave = mlx4_get_slave_indx(dev, vf);
2699 if (slave < 0)
2700 return -EINVAL;
2701
a91c772f 2702 port = mlx4_slaves_closest_port(dev, slave, port);
b01978ca 2703 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
b01978ca 2704
3f7fb021 2705 if ((0 == vlan) && (0 == qos))
b01978ca 2706 vf_admin->default_vlan = MLX4_VGT;
3f7fb021 2707 else
b01978ca
JM		 2708 vf_admin->default_vlan = vlan;
2709 vf_admin->default_qos = qos;
2710
0a6eac24
RE		 2711 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2712 mlx4_info(dev,
2713 "updating vf %d port %d config will take effect on next VF restart\n",
b01978ca 2714 vf, port);
3f7fb021
RE		 2715 return 0;
2716}
2717EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
e6b6a231 2718
5ea8bbfc
JM		 2719 /* mlx4_get_slave_default_vlan -
2720 * return true if VST ( default vlan)
2721 * if VST, will return vlan & qos (if not NULL)
2722 */
2723bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
2724 u16 *vlan, u8 *qos)
2725{
2726 struct mlx4_vport_oper_state *vp_oper;
2727 struct mlx4_priv *priv;
2728
2729 priv = mlx4_priv(dev);
a91c772f 2730 port = mlx4_slaves_closest_port(dev, slave, port);
5ea8bbfc
JM		 2731 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2732
2733 if (MLX4_VGT != vp_oper->state.default_vlan) {
2734 if (vlan)
2735 *vlan = vp_oper->state.default_vlan;
2736 if (qos)
2737 *qos = vp_oper->state.default_qos;
2738 return true;
2739 }
2740 return false;
2741}
2742EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
2743
e6b6a231
RE		 2744int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2745{
2746 struct mlx4_priv *priv = mlx4_priv(dev);
2747 struct mlx4_vport_state *s_info;
2748 int slave;
2749
2750 if ((!mlx4_is_master(dev)) ||
2751 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2752 return -EPROTONOSUPPORT;
2753
2754 slave = mlx4_get_slave_indx(dev, vf);
2755 if (slave < 0)
2756 return -EINVAL;
2757
a91c772f 2758 port = mlx4_slaves_closest_port(dev, slave, port);
e6b6a231
RE		 2759 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2760 s_info->spoofchk = setting;
2761
2762 return 0;
2763}
2764EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2cccb9e4
RE		 2765
2766int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2767{
2768 struct mlx4_priv *priv = mlx4_priv(dev);
2769 struct mlx4_vport_state *s_info;
2770 int slave;
2771
2772 if (!mlx4_is_master(dev))
2773 return -EPROTONOSUPPORT;
2774
2775 slave = mlx4_get_slave_indx(dev, vf);
2776 if (slave < 0)
2777 return -EINVAL;
2778
2779 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2780 ivf->vf = vf;
2781
2782 /* need to convert it to a func */
2783 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2784 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2785 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2786 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2787 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2788 ivf->mac[5] = ((s_info->mac) & 0xff);
2789
ed616689
SC		 2790 ivf->vlan = s_info->default_vlan;
2791 ivf->qos = s_info->default_qos;
2792 ivf->max_tx_rate = s_info->tx_rate;
2793 ivf->min_tx_rate = 0;
2794 ivf->spoofchk = s_info->spoofchk;
2795 ivf->linkstate = s_info->link_state;
2cccb9e4
RE		 2796
2797 return 0;
2798}
2799EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
948e306d
RE		 2800
2801int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2802{
2803 struct mlx4_priv *priv = mlx4_priv(dev);
2804 struct mlx4_vport_state *s_info;
948e306d
RE		 2805 int slave;
2806 u8 link_stat_event;
2807
2808 slave = mlx4_get_slave_indx(dev, vf);
2809 if (slave < 0)
2810 return -EINVAL;
2811
a91c772f 2812 port = mlx4_slaves_closest_port(dev, slave, port);
948e306d
RE		 2813 switch (link_state) {
2814 case IFLA_VF_LINK_STATE_AUTO:
2815 /* get current link state */
2816 if (!priv->sense.do_sense_port[port])
2817 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2818 else
2819 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2820 break;
2821
2822 case IFLA_VF_LINK_STATE_ENABLE:
2823 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2824 break;
2825
2826 case IFLA_VF_LINK_STATE_DISABLE:
2827 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2828 break;
2829
2830 default:
2831 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2832 link_state, slave, port);
2833 return -EINVAL;
2834 };
948e306d 2835 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
948e306d 2836 s_info->link_state = link_state;
948e306d
RE		 2837
2838 /* send event */
2839 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
0a6eac24
RE		 2840
2841 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2842 mlx4_dbg(dev,
2843 "updating vf %d port %d no link state HW enforcment\n",
2844 vf, port);
948e306d
RE		 2845 return 0;
2846}
2847EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
97982f5a
JM		 2848
2849int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
2850{
99ec41d0
JM		 2851 struct mlx4_priv *priv = mlx4_priv(dev);
2852
2853 if (slave < 1 || slave >= dev->num_slaves ||
2854 port < 1 || port > MLX4_MAX_PORTS)
2855 return 0;
2856
2857 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
2858 MLX4_VF_SMI_ENABLED;
97982f5a
JM		 2859}
2860EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
65fed8a8
JM		 2861
2862int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
2863{
2864 struct mlx4_priv *priv = mlx4_priv(dev);
2865
2866 if (slave == mlx4_master_func_num(dev))
2867 return 1;
2868
2869 if (slave < 1 || slave >= dev->num_slaves ||
2870 port < 1 || port > MLX4_MAX_PORTS)
2871 return 0;
2872
2873 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
2874 MLX4_VF_SMI_ENABLED;
2875}
2876EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
2877
2878int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
2879 int enabled)
2880{
2881 struct mlx4_priv *priv = mlx4_priv(dev);
2882
2883 if (slave == mlx4_master_func_num(dev))
2884 return 0;
2885
2886 if (slave < 1 || slave >= dev->num_slaves ||
2887 port < 1 || port > MLX4_MAX_PORTS ||
2888 enabled < 0 || enabled > 1)
2889 return -EINVAL;
2890
2891 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
2892 return 0;
2893}
2894EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);
Linux 6.x block layer and io_uring tree(s)