projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
dev_ioctl: split out ndo_eth_ioctl
[linux-2.6-block.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
8e8e69d6
TG		 1// SPDX-License-Identifier: GPL-2.0-only
2/*
656e7052
JC		 3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9#include <linux/of_device.h>
10#include <linux/of_mdio.h>
11#include <linux/of_net.h>
12#include <linux/mfd/syscon.h>
13#include <linux/regmap.h>
14#include <linux/clk.h>
26a2ad8a 15#include <linux/pm_runtime.h>
656e7052
JC		 16#include <linux/if_vlan.h>
17#include <linux/reset.h>
18#include <linux/tcp.h>
70dba204 19#include <linux/interrupt.h>
140995c9 20#include <linux/pinctrl/devinfo.h>
b8fc9f30 21#include <linux/phylink.h>
fa817272 22#include <linux/jhash.h>
d5c53da2 23#include <net/dsa.h>
656e7052
JC		 24
25#include "mtk_eth_soc.h"
26
27static int mtk_msg_level = -1;
28module_param_named(msg_level, mtk_msg_level, int, 0);
29MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31#define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34/* strings used by ethtool */
35static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38} mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51};
52
549e5495 53static const char * const mtk_clks_source_name[] = {
d438e298
SW		 54 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
55 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
56 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
57 "sgmii_ck", "eth2pll",
549e5495
SW		 58};
59
656e7052
JC		 60void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
61{
62 __raw_writel(val, eth->base + reg);
63}
64
65u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
66{
67 return __raw_readl(eth->base + reg);
68}
69
2f864990 70static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
a5d75538
RD		 71{
72 u32 val;
73
74 val = mtk_r32(eth, reg);
75 val &= ~mask;
76 val |= set;
77 mtk_w32(eth, val, reg);
78 return reg;
79}
80
656e7052
JC		 81static int mtk_mdio_busy_wait(struct mtk_eth *eth)
82{
83 unsigned long t_start = jiffies;
84
85 while (1) {
86 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
87 return 0;
88 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
89 break;
3630d519 90 cond_resched();
656e7052
JC		 91 }
92
93 dev_err(eth->dev, "mdio: MDIO timeout\n");
94 return -1;
95}
96
379672de
WY		 97static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
98 u32 phy_register, u32 write_data)
656e7052
JC		 99{
100 if (mtk_mdio_busy_wait(eth))
101 return -1;
102
103 write_data &= 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
106 (phy_register << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return -1;
112
113 return 0;
114}
115
379672de 116static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
656e7052
JC		 117{
118 u32 d;
119
120 if (mtk_mdio_busy_wait(eth))
121 return 0xffff;
122
123 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
124 (phy_reg << PHY_IAC_REG_SHIFT) |
125 (phy_addr << PHY_IAC_ADDR_SHIFT),
126 MTK_PHY_IAC);
127
128 if (mtk_mdio_busy_wait(eth))
129 return 0xffff;
130
131 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
132
133 return d;
134}
135
136static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
137 int phy_reg, u16 val)
138{
139 struct mtk_eth *eth = bus->priv;
140
141 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
142}
143
144static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
145{
146 struct mtk_eth *eth = bus->priv;
147
148 return _mtk_mdio_read(eth, phy_addr, phy_reg);
149}
150
8efaa653
RD		 151static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
152 phy_interface_t interface)
153{
154 u32 val;
155
cce581a0
RD		 156 /* Check DDR memory type.
157 * Currently TRGMII mode with DDR2 memory is not supported.
158 */
8efaa653 159 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
cce581a0
RD		 160 if (interface == PHY_INTERFACE_MODE_TRGMII &&
161 val & SYSCFG_DRAM_TYPE_DDR2) {
8efaa653
RD		 162 dev_err(eth->dev,
163 "TRGMII mode with DDR2 memory is not supported!\n");
164 return -EOPNOTSUPP;
165 }
166
167 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
168 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
169
170 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
171 ETHSYS_TRGMII_MT7621_MASK, val);
172
173 return 0;
174}
175
19016d93
RD		 176static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
177 phy_interface_t interface, int speed)
f430dea7
SW		 178{
179 u32 val;
180 int ret;
181
19016d93
RD		 182 if (interface == PHY_INTERFACE_MODE_TRGMII) {
183 mtk_w32(eth, TRGMII_MODE, INTF_MODE);
184 val = 500000000;
185 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
186 if (ret)
187 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
188 return;
189 }
190
f430dea7
SW		 191 val = (speed == SPEED_1000) ?
192 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
193 mtk_w32(eth, val, INTF_MODE);
194
195 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
196 ETHSYS_TRGMII_CLK_SEL362_5,
197 ETHSYS_TRGMII_CLK_SEL362_5);
198
199 val = (speed == SPEED_1000) ? 250000000 : 500000000;
200 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
201 if (ret)
202 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
203
204 val = (speed == SPEED_1000) ?
205 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
206 mtk_w32(eth, val, TRGMII_RCK_CTRL);
207
208 val = (speed == SPEED_1000) ?
209 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
210 mtk_w32(eth, val, TRGMII_TCK_CTRL);
211}
212
b8fc9f30
RD		 213static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
214 const struct phylink_link_state *state)
656e7052 215{
b8fc9f30
RD		 216 struct mtk_mac *mac = container_of(config, struct mtk_mac,
217 phylink_config);
218 struct mtk_eth *eth = mac->hw;
a5d75538 219 u32 mcr_cur, mcr_new, sid, i;
7e538372 220 int val, ge_mode, err;
b8fc9f30
RD		 221
222 /* MT76x8 has no hardware settings between for the MAC */
223 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
224 mac->interface != state->interface) {
225 /* Setup soc pin functions */
226 switch (state->interface) {
227 case PHY_INTERFACE_MODE_TRGMII:
228 if (mac->id)
229 goto err_phy;
230 if (!MTK_HAS_CAPS(mac->hw->soc->caps,
231 MTK_GMAC1_TRGMII))
232 goto err_phy;
df561f66 233 fallthrough;
b8fc9f30
RD		 234 case PHY_INTERFACE_MODE_RGMII_TXID:
235 case PHY_INTERFACE_MODE_RGMII_RXID:
236 case PHY_INTERFACE_MODE_RGMII_ID:
237 case PHY_INTERFACE_MODE_RGMII:
b8fc9f30 238 case PHY_INTERFACE_MODE_MII:
b8fc9f30 239 case PHY_INTERFACE_MODE_REVMII:
b8fc9f30 240 case PHY_INTERFACE_MODE_RMII:
7e538372
RD		 241 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
242 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
243 if (err)
244 goto init_err;
245 }
246 break;
247 case PHY_INTERFACE_MODE_1000BASEX:
248 case PHY_INTERFACE_MODE_2500BASEX:
249 case PHY_INTERFACE_MODE_SGMII:
250 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
251 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
252 if (err)
253 goto init_err;
254 }
255 break;
256 case PHY_INTERFACE_MODE_GMII:
257 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
258 err = mtk_gmac_gephy_path_setup(eth, mac->id);
259 if (err)
260 goto init_err;
261 }
b8fc9f30
RD		 262 break;
263 default:
264 goto err_phy;
265 }
656e7052 266
b8fc9f30 267 /* Setup clock for 1st gmac */
7e538372
RD		 268 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
269 !phy_interface_mode_is_8023z(state->interface) &&
b8fc9f30
RD		 270 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
271 if (MTK_HAS_CAPS(mac->hw->soc->caps,
272 MTK_TRGMII_MT7621_CLK)) {
273 if (mt7621_gmac0_rgmii_adjust(mac->hw,
274 state->interface))
275 goto err_phy;
276 } else {
19016d93
RD		 277 mtk_gmac0_rgmii_adjust(mac->hw,
278 state->interface,
279 state->speed);
a5d75538
RD		 280
281 /* mt7623_pad_clk_setup */
282 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
283 mtk_w32(mac->hw,
284 TD_DM_DRVP(8) | TD_DM_DRVN(8),
285 TRGMII_TD_ODT(i));
286
287 /* Assert/release MT7623 RXC reset */
288 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
289 TRGMII_RCK_CTRL);
290 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
b8fc9f30
RD		 291 }
292 }
dce6fa42 293
7e538372
RD		 294 ge_mode = 0;
295 switch (state->interface) {
296 case PHY_INTERFACE_MODE_MII:
4e3eff5b 297 case PHY_INTERFACE_MODE_GMII:
7e538372
RD		 298 ge_mode = 1;
299 break;
300 case PHY_INTERFACE_MODE_REVMII:
301 ge_mode = 2;
302 break;
303 case PHY_INTERFACE_MODE_RMII:
304 if (mac->id)
305 goto err_phy;
306 ge_mode = 3;
307 break;
308 default:
309 break;
310 }
311
b8fc9f30
RD		 312 /* put the gmac into the right mode */
313 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
314 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
315 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
316 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
317
318 mac->interface = state->interface;
319 }
320
7e538372
RD		 321 /* SGMII */
322 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
323 phy_interface_mode_is_8023z(state->interface)) {
324 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
325 * being setup done.
326 */
327 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
328
329 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
330 SYSCFG0_SGMII_MASK,
331 ~(u32)SYSCFG0_SGMII_MASK);
332
333 /* Decide how GMAC and SGMIISYS be mapped */
334 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
335 0 : mac->id;
336
337 /* Setup SGMIISYS with the determined property */
338 if (state->interface != PHY_INTERFACE_MODE_SGMII)
339 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid,
340 state);
341 else if (phylink_autoneg_inband(mode))
342 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
343
344 if (err)
345 goto init_err;
346
347 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
348 SYSCFG0_SGMII_MASK, val);
349 } else if (phylink_autoneg_inband(mode)) {
350 dev_err(eth->dev,
351 "In-band mode not supported in non SGMII mode!\n");
352 return;
353 }
354
b8fc9f30
RD		 355 /* Setup gmac */
356 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
357 mcr_new = mcr_cur;
4fd59792 358 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
b8fc9f30
RD		 359 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK;
360
b8fc9f30
RD		 361 /* Only update control register when needed! */
362 if (mcr_new != mcr_cur)
363 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
656e7052 364
b8fc9f30 365 return;
656e7052 366
b8fc9f30
RD		 367err_phy:
368 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
369 mac->id, phy_modes(state->interface));
7e538372
RD		 370 return;
371
372init_err:
373 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
374 mac->id, phy_modes(state->interface), err);
b8fc9f30 375}
08ef55c6 376
d46b7e4f
RK		 377static void mtk_mac_pcs_get_state(struct phylink_config *config,
378 struct phylink_link_state *state)
b8fc9f30
RD		 379{
380 struct mtk_mac *mac = container_of(config, struct mtk_mac,
381 phylink_config);
382 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
08ef55c6 383
b8fc9f30
RD		 384 state->link = (pmsr & MAC_MSR_LINK);
385 state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
08ef55c6 386
b8fc9f30
RD		 387 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
388 case 0:
389 state->speed = SPEED_10;
390 break;
391 case MAC_MSR_SPEED_100:
392 state->speed = SPEED_100;
393 break;
394 case MAC_MSR_SPEED_1000:
395 state->speed = SPEED_1000;
396 break;
397 default:
398 state->speed = SPEED_UNKNOWN;
399 break;
08ef55c6 400 }
656e7052 401
b8fc9f30
RD		 402 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
403 if (pmsr & MAC_MSR_RX_FC)
404 state->pause |= MLO_PAUSE_RX;
405 if (pmsr & MAC_MSR_TX_FC)
406 state->pause |= MLO_PAUSE_TX;
656e7052
JC		 407}
408
b8fc9f30 409static void mtk_mac_an_restart(struct phylink_config *config)
656e7052 410{
7e538372
RD		 411 struct mtk_mac *mac = container_of(config, struct mtk_mac,
412 phylink_config);
413
414 mtk_sgmii_restart_an(mac->hw, mac->id);
b8fc9f30 415}
656e7052 416
b8fc9f30
RD		 417static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
418 phy_interface_t interface)
419{
420 struct mtk_mac *mac = container_of(config, struct mtk_mac,
421 phylink_config);
422 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
656e7052 423
b8fc9f30
RD		 424 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
425 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
656e7052
JC		 426}
427
91a208f2
RK		 428static void mtk_mac_link_up(struct phylink_config *config,
429 struct phy_device *phy,
430 unsigned int mode, phy_interface_t interface,
431 int speed, int duplex, bool tx_pause, bool rx_pause)
656e7052 432{
b8fc9f30
RD		 433 struct mtk_mac *mac = container_of(config, struct mtk_mac,
434 phylink_config);
435 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
656e7052 436
75674e31
RK		 437 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
438 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
439 MAC_MCR_FORCE_RX_FC);
440
441 /* Configure speed */
442 switch (speed) {
443 case SPEED_2500:
444 case SPEED_1000:
445 mcr |= MAC_MCR_SPEED_1000;
446 break;
447 case SPEED_100:
448 mcr |= MAC_MCR_SPEED_100;
449 break;
450 }
451
452 /* Configure duplex */
453 if (duplex == DUPLEX_FULL)
454 mcr |= MAC_MCR_FORCE_DPX;
455
456 /* Configure pause modes - phylink will avoid these for half duplex */
457 if (tx_pause)
458 mcr |= MAC_MCR_FORCE_TX_FC;
459 if (rx_pause)
460 mcr |= MAC_MCR_FORCE_RX_FC;
461
b8fc9f30
RD		 462 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
463 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
464}
656e7052 465
b8fc9f30
RD		 466static void mtk_validate(struct phylink_config *config,
467 unsigned long *supported,
468 struct phylink_link_state *state)
469{
470 struct mtk_mac *mac = container_of(config, struct mtk_mac,
471 phylink_config);
472 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
656e7052 473
b8fc9f30
RD		 474 if (state->interface != PHY_INTERFACE_MODE_NA &&
475 state->interface != PHY_INTERFACE_MODE_MII &&
476 state->interface != PHY_INTERFACE_MODE_GMII &&
477 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) &&
478 phy_interface_mode_is_rgmii(state->interface)) &&
479 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) &&
7e538372
RD		 480 !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) &&
481 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) &&
482 (state->interface == PHY_INTERFACE_MODE_SGMII ||
483 phy_interface_mode_is_8023z(state->interface)))) {
b8fc9f30
RD		 484 linkmode_zero(supported);
485 return;
296c9120 486 }
656e7052 487
b8fc9f30
RD		 488 phylink_set_port_modes(mask);
489 phylink_set(mask, Autoneg);
f6f7d9c0 490
7e538372
RD		 491 switch (state->interface) {
492 case PHY_INTERFACE_MODE_TRGMII:
b8fc9f30 493 phylink_set(mask, 1000baseT_Full);
7e538372
RD		 494 break;
495 case PHY_INTERFACE_MODE_1000BASEX:
496 case PHY_INTERFACE_MODE_2500BASEX:
497 phylink_set(mask, 1000baseX_Full);
498 phylink_set(mask, 2500baseX_Full);
499 break;
500 case PHY_INTERFACE_MODE_GMII:
501 case PHY_INTERFACE_MODE_RGMII:
502 case PHY_INTERFACE_MODE_RGMII_ID:
503 case PHY_INTERFACE_MODE_RGMII_RXID:
504 case PHY_INTERFACE_MODE_RGMII_TXID:
505 phylink_set(mask, 1000baseT_Half);
df561f66 506 fallthrough;
7e538372
RD		 507 case PHY_INTERFACE_MODE_SGMII:
508 phylink_set(mask, 1000baseT_Full);
509 phylink_set(mask, 1000baseX_Full);
df561f66 510 fallthrough;
7e538372
RD		 511 case PHY_INTERFACE_MODE_MII:
512 case PHY_INTERFACE_MODE_RMII:
513 case PHY_INTERFACE_MODE_REVMII:
514 case PHY_INTERFACE_MODE_NA:
515 default:
b8fc9f30
RD		 516 phylink_set(mask, 10baseT_Half);
517 phylink_set(mask, 10baseT_Full);
518 phylink_set(mask, 100baseT_Half);
519 phylink_set(mask, 100baseT_Full);
7e538372
RD		 520 break;
521 }
b8fc9f30 522
7e538372
RD		 523 if (state->interface == PHY_INTERFACE_MODE_NA) {
524 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
b8fc9f30
RD		 525 phylink_set(mask, 1000baseT_Full);
526 phylink_set(mask, 1000baseX_Full);
7e538372
RD		 527 phylink_set(mask, 2500baseX_Full);
528 }
529 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) {
530 phylink_set(mask, 1000baseT_Full);
531 phylink_set(mask, 1000baseT_Half);
532 phylink_set(mask, 1000baseX_Full);
533 }
534 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) {
535 phylink_set(mask, 1000baseT_Full);
536 phylink_set(mask, 1000baseT_Half);
b8fc9f30
RD		 537 }
538 }
e8c2993a 539
b8fc9f30
RD		 540 phylink_set(mask, Pause);
541 phylink_set(mask, Asym_Pause);
8ca7f4fe 542
b8fc9f30
RD		 543 linkmode_and(supported, supported, mask);
544 linkmode_and(state->advertising, state->advertising, mask);
7e538372
RD		 545
546 /* We can only operate at 2500BaseX or 1000BaseX. If requested
547 * to advertise both, only report advertising at 2500BaseX.
548 */
549 phylink_helper_basex_speed(state);
656e7052
JC		 550}
551
b8fc9f30
RD		 552static const struct phylink_mac_ops mtk_phylink_ops = {
553 .validate = mtk_validate,
d46b7e4f 554 .mac_pcs_get_state = mtk_mac_pcs_get_state,
b8fc9f30
RD		 555 .mac_an_restart = mtk_mac_an_restart,
556 .mac_config = mtk_mac_config,
557 .mac_link_down = mtk_mac_link_down,
558 .mac_link_up = mtk_mac_link_up,
559};
560
656e7052
JC		 561static int mtk_mdio_init(struct mtk_eth *eth)
562{
563 struct device_node *mii_np;
1e515b7f 564 int ret;
656e7052
JC		 565
566 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
567 if (!mii_np) {
568 dev_err(eth->dev, "no %s child node found", "mdio-bus");
569 return -ENODEV;
570 }
571
572 if (!of_device_is_available(mii_np)) {
aa6e8a54 573 ret = -ENODEV;
656e7052
JC		 574 goto err_put_node;
575 }
576
1e515b7f 577 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
656e7052 578 if (!eth->mii_bus) {
1e515b7f 579 ret = -ENOMEM;
656e7052
JC		 580 goto err_put_node;
581 }
582
583 eth->mii_bus->name = "mdio";
584 eth->mii_bus->read = mtk_mdio_read;
585 eth->mii_bus->write = mtk_mdio_write;
586 eth->mii_bus->priv = eth;
587 eth->mii_bus->parent = eth->dev;
588
21c328dc 589 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
1e515b7f 590 ret = of_mdiobus_register(eth->mii_bus, mii_np);
656e7052
JC		 591
592err_put_node:
593 of_node_put(mii_np);
1e515b7f 594 return ret;
656e7052
JC		 595}
596
597static void mtk_mdio_cleanup(struct mtk_eth *eth)
598{
599 if (!eth->mii_bus)
600 return;
601
602 mdiobus_unregister(eth->mii_bus);
656e7052
JC		 603}
604
5cce0322 605static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
656e7052 606{
7bc9ccec 607 unsigned long flags;
656e7052
JC		 608 u32 val;
609
5cce0322 610 spin_lock_irqsave(&eth->tx_irq_lock, flags);
296c9120
SR		 611 val = mtk_r32(eth, eth->tx_int_mask_reg);
612 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg);
5cce0322 613 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
656e7052
JC		 614}
615
5cce0322 616static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
656e7052 617{
7bc9ccec 618 unsigned long flags;
656e7052
JC		 619 u32 val;
620
5cce0322 621 spin_lock_irqsave(&eth->tx_irq_lock, flags);
296c9120
SR		 622 val = mtk_r32(eth, eth->tx_int_mask_reg);
623 mtk_w32(eth, val | mask, eth->tx_int_mask_reg);
5cce0322
JC		 624 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
625}
626
627static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
628{
629 unsigned long flags;
630 u32 val;
631
632 spin_lock_irqsave(&eth->rx_irq_lock, flags);
633 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
634 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
635 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
636}
637
638static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
639{
640 unsigned long flags;
641 u32 val;
642
643 spin_lock_irqsave(&eth->rx_irq_lock, flags);
644 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
645 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
646 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
656e7052
JC		 647}
648
649static int mtk_set_mac_address(struct net_device *dev, void *p)
650{
651 int ret = eth_mac_addr(dev, p);
652 struct mtk_mac *mac = netdev_priv(dev);
296c9120 653 struct mtk_eth *eth = mac->hw;
656e7052 654 const char *macaddr = dev->dev_addr;
656e7052
JC		 655
656 if (ret)
657 return ret;
658
dce6fa42
SW		 659 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
660 return -EBUSY;
661
e3e9652a 662 spin_lock_bh(&mac->hw->page_lock);
296c9120
SR		 663 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
664 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
665 MT7628_SDM_MAC_ADRH);
666 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
667 (macaddr[4] << 8) | macaddr[5],
668 MT7628_SDM_MAC_ADRL);
669 } else {
670 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
671 MTK_GDMA_MAC_ADRH(mac->id));
672 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
673 (macaddr[4] << 8) | macaddr[5],
674 MTK_GDMA_MAC_ADRL(mac->id));
675 }
e3e9652a 676 spin_unlock_bh(&mac->hw->page_lock);
656e7052
JC		 677
678 return 0;
679}
680
681void mtk_stats_update_mac(struct mtk_mac *mac)
682{
683 struct mtk_hw_stats *hw_stats = mac->hw_stats;
ad79fd2c 684 struct mtk_eth *eth = mac->hw;
656e7052
JC		 685
686 u64_stats_update_begin(&hw_stats->syncp);
687
ad79fd2c
SR		 688 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
689 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
690 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
691 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
692 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
693 hw_stats->rx_checksum_errors +=
694 mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
695 } else {
696 unsigned int offs = hw_stats->reg_offset;
697 u64 stats;
698
699 hw_stats->rx_bytes += mtk_r32(mac->hw,
700 MTK_GDM1_RX_GBCNT_L + offs);
701 stats = mtk_r32(mac->hw, MTK_GDM1_RX_GBCNT_H + offs);
702 if (stats)
703 hw_stats->rx_bytes += (stats << 32);
704 hw_stats->rx_packets +=
705 mtk_r32(mac->hw, MTK_GDM1_RX_GPCNT + offs);
706 hw_stats->rx_overflow +=
707 mtk_r32(mac->hw, MTK_GDM1_RX_OERCNT + offs);
708 hw_stats->rx_fcs_errors +=
709 mtk_r32(mac->hw, MTK_GDM1_RX_FERCNT + offs);
710 hw_stats->rx_short_errors +=
711 mtk_r32(mac->hw, MTK_GDM1_RX_SERCNT + offs);
712 hw_stats->rx_long_errors +=
713 mtk_r32(mac->hw, MTK_GDM1_RX_LENCNT + offs);
714 hw_stats->rx_checksum_errors +=
715 mtk_r32(mac->hw, MTK_GDM1_RX_CERCNT + offs);
716 hw_stats->rx_flow_control_packets +=
717 mtk_r32(mac->hw, MTK_GDM1_RX_FCCNT + offs);
718 hw_stats->tx_skip +=
719 mtk_r32(mac->hw, MTK_GDM1_TX_SKIPCNT + offs);
720 hw_stats->tx_collisions +=
721 mtk_r32(mac->hw, MTK_GDM1_TX_COLCNT + offs);
722 hw_stats->tx_bytes +=
723 mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_L + offs);
724 stats = mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_H + offs);
725 if (stats)
726 hw_stats->tx_bytes += (stats << 32);
727 hw_stats->tx_packets +=
728 mtk_r32(mac->hw, MTK_GDM1_TX_GPCNT + offs);
729 }
730
656e7052
JC		 731 u64_stats_update_end(&hw_stats->syncp);
732}
733
734static void mtk_stats_update(struct mtk_eth *eth)
735{
736 int i;
737
738 for (i = 0; i < MTK_MAC_COUNT; i++) {
739 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
740 continue;
741 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
742 mtk_stats_update_mac(eth->mac[i]);
743 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
744 }
745 }
746}
747
bc1f4470 748static void mtk_get_stats64(struct net_device *dev,
749 struct rtnl_link_stats64 *storage)
656e7052
JC		 750{
751 struct mtk_mac *mac = netdev_priv(dev);
752 struct mtk_hw_stats *hw_stats = mac->hw_stats;
753 unsigned int start;
754
755 if (netif_running(dev) && netif_device_present(dev)) {
8d32e062 756 if (spin_trylock_bh(&hw_stats->stats_lock)) {
656e7052 757 mtk_stats_update_mac(mac);
8d32e062 758 spin_unlock_bh(&hw_stats->stats_lock);
656e7052
JC		 759 }
760 }
761
762 do {
763 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
764 storage->rx_packets = hw_stats->rx_packets;
765 storage->tx_packets = hw_stats->tx_packets;
766 storage->rx_bytes = hw_stats->rx_bytes;
767 storage->tx_bytes = hw_stats->tx_bytes;
768 storage->collisions = hw_stats->tx_collisions;
769 storage->rx_length_errors = hw_stats->rx_short_errors +
770 hw_stats->rx_long_errors;
771 storage->rx_over_errors = hw_stats->rx_overflow;
772 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
773 storage->rx_errors = hw_stats->rx_checksum_errors;
774 storage->tx_aborted_errors = hw_stats->tx_skip;
775 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
776
777 storage->tx_errors = dev->stats.tx_errors;
778 storage->rx_dropped = dev->stats.rx_dropped;
779 storage->tx_dropped = dev->stats.tx_dropped;
656e7052
JC		 780}
781
782static inline int mtk_max_frag_size(int mtu)
783{
784 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
4fd59792
DQ		 785 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K)
786 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
656e7052
JC		 787
788 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
789 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
790}
791
792static inline int mtk_max_buf_size(int frag_size)
793{
794 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
795 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
796
4fd59792 797 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K);
656e7052
JC		 798
799 return buf_size;
800}
801
816ac3e6 802static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd,
656e7052
JC		 803 struct mtk_rx_dma *dma_rxd)
804{
656e7052 805 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
816ac3e6
FF		 806 if (!(rxd->rxd2 & RX_DMA_DONE))
807 return false;
808
809 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
656e7052
JC		 810 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
811 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
816ac3e6
FF		 812
813 return true;
656e7052
JC		 814}
815
816/* the qdma core needs scratch memory to be setup */
817static int mtk_init_fq_dma(struct mtk_eth *eth)
818{
605e4fe4 819 dma_addr_t phy_ring_tail;
656e7052
JC		 820 int cnt = MTK_DMA_SIZE;
821 dma_addr_t dma_addr;
822 int i;
823
750afb08
LC		 824 eth->scratch_ring = dma_alloc_coherent(eth->dev,
825 cnt * sizeof(struct mtk_tx_dma),
826 &eth->phy_scratch_ring,
827 GFP_ATOMIC);
656e7052
JC		 828 if (unlikely(!eth->scratch_ring))
829 return -ENOMEM;
830
831 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
832 GFP_KERNEL);
562c5a70
JC		 833 if (unlikely(!eth->scratch_head))
834 return -ENOMEM;
835
656e7052
JC		 836 dma_addr = dma_map_single(eth->dev,
837 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
838 DMA_FROM_DEVICE);
839 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
840 return -ENOMEM;
841
605e4fe4 842 phy_ring_tail = eth->phy_scratch_ring +
656e7052
JC		 843 (sizeof(struct mtk_tx_dma) * (cnt - 1));
844
845 for (i = 0; i < cnt; i++) {
846 eth->scratch_ring[i].txd1 =
847 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
848 if (i < cnt - 1)
605e4fe4 849 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
656e7052
JC		 850 ((i + 1) * sizeof(struct mtk_tx_dma)));
851 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
852 }
853
605e4fe4 854 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
656e7052
JC		 855 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
856 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
857 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
858
859 return 0;
860}
861
862static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
863{
864 void *ret = ring->dma;
865
866 return ret + (desc - ring->phys);
867}
868
869static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
870 struct mtk_tx_dma *txd)
871{
872 int idx = txd - ring->dma;
873
874 return &ring->buf[idx];
875}
876
296c9120
SR		 877static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
878 struct mtk_tx_dma *dma)
879{
880 return ring->dma_pdma - ring->dma + dma;
881}
882
883static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma)
884{
885 return ((void *)dma - (void *)ring->dma) / sizeof(*dma);
886}
887
c30c4a82
FF		 888static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
889 bool napi)
656e7052 890{
296c9120
SR		 891 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
892 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
893 dma_unmap_single(eth->dev,
894 dma_unmap_addr(tx_buf, dma_addr0),
895 dma_unmap_len(tx_buf, dma_len0),
896 DMA_TO_DEVICE);
897 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
898 dma_unmap_page(eth->dev,
899 dma_unmap_addr(tx_buf, dma_addr0),
900 dma_unmap_len(tx_buf, dma_len0),
901 DMA_TO_DEVICE);
902 }
903 } else {
904 if (dma_unmap_len(tx_buf, dma_len0)) {
905 dma_unmap_page(eth->dev,
906 dma_unmap_addr(tx_buf, dma_addr0),
907 dma_unmap_len(tx_buf, dma_len0),
908 DMA_TO_DEVICE);
909 }
910
911 if (dma_unmap_len(tx_buf, dma_len1)) {
912 dma_unmap_page(eth->dev,
913 dma_unmap_addr(tx_buf, dma_addr1),
914 dma_unmap_len(tx_buf, dma_len1),
915 DMA_TO_DEVICE);
916 }
656e7052 917 }
296c9120 918
656e7052
JC		 919 tx_buf->flags = 0;
920 if (tx_buf->skb &&
c30c4a82
FF		 921 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) {
922 if (napi)
923 napi_consume_skb(tx_buf->skb, napi);
924 else
925 dev_kfree_skb_any(tx_buf->skb);
926 }
656e7052
JC		 927 tx_buf->skb = NULL;
928}
929
296c9120
SR		 930static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
931 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
932 size_t size, int idx)
933{
934 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
935 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
936 dma_unmap_len_set(tx_buf, dma_len0, size);
937 } else {
938 if (idx & 1) {
939 txd->txd3 = mapped_addr;
940 txd->txd2 |= TX_DMA_PLEN1(size);
941 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
942 dma_unmap_len_set(tx_buf, dma_len1, size);
943 } else {
944 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
945 txd->txd1 = mapped_addr;
946 txd->txd2 = TX_DMA_PLEN0(size);
947 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
948 dma_unmap_len_set(tx_buf, dma_len0, size);
949 }
950 }
951}
952
656e7052
JC		 953static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
954 int tx_num, struct mtk_tx_ring *ring, bool gso)
955{
956 struct mtk_mac *mac = netdev_priv(dev);
957 struct mtk_eth *eth = mac->hw;
958 struct mtk_tx_dma *itxd, *txd;
296c9120 959 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
81d2dd09 960 struct mtk_tx_buf *itx_buf, *tx_buf;
656e7052
JC		 961 dma_addr_t mapped_addr;
962 unsigned int nr_frags;
963 int i, n_desc = 1;
c6f1dc4d 964 u32 txd4 = 0, fport;
296c9120 965 int k = 0;
656e7052
JC		 966
967 itxd = ring->next_free;
296c9120 968 itxd_pdma = qdma_to_pdma(ring, itxd);
656e7052
JC		 969 if (itxd == ring->last_free)
970 return -ENOMEM;
971
972 /* set the forward port */
c6f1dc4d
SW		 973 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
974 txd4 |= fport;
656e7052 975
81d2dd09
SW		 976 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
977 memset(itx_buf, 0, sizeof(*itx_buf));
656e7052
JC		 978
979 if (gso)
980 txd4 |= TX_DMA_TSO;
981
982 /* TX Checksum offload */
983 if (skb->ip_summed == CHECKSUM_PARTIAL)
984 txd4 |= TX_DMA_CHKSUM;
985
986 /* VLAN header offload */
987 if (skb_vlan_tag_present(skb))
988 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
989
55a4e778 990 mapped_addr = dma_map_single(eth->dev, skb->data,
656e7052 991 skb_headlen(skb), DMA_TO_DEVICE);
55a4e778 992 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 993 return -ENOMEM;
994
656e7052 995 WRITE_ONCE(itxd->txd1, mapped_addr);
81d2dd09 996 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
134d2152
SW		 997 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
998 MTK_TX_FLAGS_FPORT1;
296c9120
SR		 999 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb),
1000 k++);
656e7052
JC		 1001
1002 /* TX SG offload */
1003 txd = itxd;
296c9120 1004 txd_pdma = qdma_to_pdma(ring, txd);
656e7052 1005 nr_frags = skb_shinfo(skb)->nr_frags;
296c9120 1006
656e7052 1007 for (i = 0; i < nr_frags; i++) {
d7840976 1008 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
656e7052
JC		 1009 unsigned int offset = 0;
1010 int frag_size = skb_frag_size(frag);
1011
1012 while (frag_size) {
1013 bool last_frag = false;
1014 unsigned int frag_map_size;
296c9120
SR		 1015 bool new_desc = true;
1016
1017 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) ||
1018 (i & 0x1)) {
1019 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1020 txd_pdma = qdma_to_pdma(ring, txd);
1021 if (txd == ring->last_free)
1022 goto err_dma;
1023
1024 n_desc++;
1025 } else {
1026 new_desc = false;
1027 }
656e7052 1028
656e7052 1029
656e7052 1030 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
55a4e778 1031 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
656e7052
JC		 1032 frag_map_size,
1033 DMA_TO_DEVICE);
55a4e778 1034 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 1035 goto err_dma;
1036
1037 if (i == nr_frags - 1 &&
1038 (frag_size - frag_map_size) == 0)
1039 last_frag = true;
1040
1041 WRITE_ONCE(txd->txd1, mapped_addr);
1042 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
1043 TX_DMA_PLEN0(frag_map_size) |
369f0453 1044 last_frag * TX_DMA_LS0));
c6f1dc4d 1045 WRITE_ONCE(txd->txd4, fport);
656e7052 1046
656e7052 1047 tx_buf = mtk_desc_to_tx_buf(ring, txd);
296c9120
SR		 1048 if (new_desc)
1049 memset(tx_buf, 0, sizeof(*tx_buf));
81d2dd09 1050 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
656e7052 1051 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
134d2152
SW		 1052 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
1053 MTK_TX_FLAGS_FPORT1;
1054
296c9120
SR		 1055 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr,
1056 frag_map_size, k++);
1057
656e7052
JC		 1058 frag_size -= frag_map_size;
1059 offset += frag_map_size;
1060 }
1061 }
1062
1063 /* store skb to cleanup */
81d2dd09 1064 itx_buf->skb = skb;
656e7052
JC		 1065
1066 WRITE_ONCE(itxd->txd4, txd4);
1067 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
1068 (!nr_frags * TX_DMA_LS0)));
296c9120
SR		 1069 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1070 if (k & 0x1)
1071 txd_pdma->txd2 |= TX_DMA_LS0;
1072 else
1073 txd_pdma->txd2 |= TX_DMA_LS1;
1074 }
656e7052 1075
656e7052
JC		 1076 netdev_sent_queue(dev, skb->len);
1077 skb_tx_timestamp(skb);
1078
1079 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1080 atomic_sub(n_desc, &ring->free_count);
1081
1082 /* make sure that all changes to the dma ring are flushed before we
1083 * continue
1084 */
1085 wmb();
1086
296c9120
SR		 1087 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1088 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) ||
1089 !netdev_xmit_more())
1090 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
1091 } else {
1092 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd),
1093 ring->dma_size);
1094 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1095 }
656e7052
JC		 1096
1097 return 0;
1098
1099err_dma:
1100 do {
2fae723c 1101 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
656e7052
JC		 1102
1103 /* unmap dma */
c30c4a82 1104 mtk_tx_unmap(eth, tx_buf, false);
656e7052
JC		 1105
1106 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
296c9120
SR		 1107 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1108 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1109
656e7052 1110 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
296c9120 1111 itxd_pdma = qdma_to_pdma(ring, itxd);
656e7052
JC		 1112 } while (itxd != txd);
1113
1114 return -ENOMEM;
1115}
1116
1117static inline int mtk_cal_txd_req(struct sk_buff *skb)
1118{
1119 int i, nfrags;
d7840976 1120 skb_frag_t *frag;
656e7052
JC		 1121
1122 nfrags = 1;
1123 if (skb_is_gso(skb)) {
1124 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1125 frag = &skb_shinfo(skb)->frags[i];
92493a2f
MWO		 1126 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1127 MTK_TX_DMA_BUF_LEN);
656e7052
JC		 1128 }
1129 } else {
1130 nfrags += skb_shinfo(skb)->nr_frags;
1131 }
1132
beeb4ca4 1133 return nfrags;
656e7052
JC		 1134}
1135
ad3cba98
JC		 1136static int mtk_queue_stopped(struct mtk_eth *eth)
1137{
1138 int i;
1139
1140 for (i = 0; i < MTK_MAC_COUNT; i++) {
1141 if (!eth->netdev[i])
1142 continue;
1143 if (netif_queue_stopped(eth->netdev[i]))
1144 return 1;
1145 }
1146
1147 return 0;
1148}
1149
13c822f6
JC		 1150static void mtk_wake_queue(struct mtk_eth *eth)
1151{
1152 int i;
1153
1154 for (i = 0; i < MTK_MAC_COUNT; i++) {
1155 if (!eth->netdev[i])
1156 continue;
1157 netif_wake_queue(eth->netdev[i]);
1158 }
1159}
1160
e910a399 1161static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
656e7052
JC		 1162{
1163 struct mtk_mac *mac = netdev_priv(dev);
1164 struct mtk_eth *eth = mac->hw;
1165 struct mtk_tx_ring *ring = &eth->tx_ring;
1166 struct net_device_stats *stats = &dev->stats;
1167 bool gso = false;
1168 int tx_num;
1169
34c2e4c9
JC		 1170 /* normally we can rely on the stack not calling this more than once,
1171 * however we have 2 queues running on the same ring so we need to lock
1172 * the ring access
1173 */
e3e9652a 1174 spin_lock(&eth->page_lock);
34c2e4c9 1175
dce6fa42
SW		 1176 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
1177 goto drop;
1178
656e7052
JC		 1179 tx_num = mtk_cal_txd_req(skb);
1180 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
16ef6707 1181 netif_stop_queue(dev);
656e7052
JC		 1182 netif_err(eth, tx_queued, dev,
1183 "Tx Ring full when queue awake!\n");
e3e9652a 1184 spin_unlock(&eth->page_lock);
656e7052
JC		 1185 return NETDEV_TX_BUSY;
1186 }
1187
1188 /* TSO: fill MSS info in tcp checksum field */
1189 if (skb_is_gso(skb)) {
1190 if (skb_cow_head(skb, 0)) {
1191 netif_warn(eth, tx_err, dev,
1192 "GSO expand head fail.\n");
1193 goto drop;
1194 }
1195
1196 if (skb_shinfo(skb)->gso_type &
1197 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1198 gso = true;
1199 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1200 }
1201 }
1202
1203 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1204 goto drop;
1205
82c6544d 1206 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
16ef6707 1207 netif_stop_queue(dev);
82c6544d 1208
e3e9652a 1209 spin_unlock(&eth->page_lock);
656e7052
JC		 1210
1211 return NETDEV_TX_OK;
1212
1213drop:
e3e9652a 1214 spin_unlock(&eth->page_lock);
656e7052 1215 stats->tx_dropped++;
81ad2b7d 1216 dev_kfree_skb_any(skb);
656e7052
JC		 1217 return NETDEV_TX_OK;
1218}
1219
ee406810
NC		 1220static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1221{
1222 int i;
1223 struct mtk_rx_ring *ring;
1224 int idx;
1225
1226 if (!eth->hwlro)
1227 return &eth->rx_ring[0];
1228
1229 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1230 ring = &eth->rx_ring[i];
08df5fa6 1231 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
ee406810
NC		 1232 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
1233 ring->calc_idx_update = true;
1234 return ring;
1235 }
1236 }
1237
1238 return NULL;
1239}
1240
1241static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1242{
1243 struct mtk_rx_ring *ring;
1244 int i;
1245
1246 if (!eth->hwlro) {
1247 ring = &eth->rx_ring[0];
1248 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1249 } else {
1250 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1251 ring = &eth->rx_ring[i];
1252 if (ring->calc_idx_update) {
1253 ring->calc_idx_update = false;
1254 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1255 }
1256 }
1257 }
1258}
1259
656e7052 1260static int mtk_poll_rx(struct napi_struct *napi, int budget,
eece71e8 1261 struct mtk_eth *eth)
656e7052 1262{
e9229ffd 1263 struct dim_sample dim_sample = {};
ee406810
NC		 1264 struct mtk_rx_ring *ring;
1265 int idx;
656e7052
JC		 1266 struct sk_buff *skb;
1267 u8 *data, *new_data;
1268 struct mtk_rx_dma *rxd, trxd;
e9229ffd 1269 int done = 0, bytes = 0;
656e7052
JC		 1270
1271 while (done < budget) {
1272 struct net_device *netdev;
1273 unsigned int pktlen;
1274 dma_addr_t dma_addr;
fa817272 1275 u32 hash;
296c9120 1276 int mac;
656e7052 1277
ee406810
NC		 1278 ring = mtk_get_rx_ring(eth);
1279 if (unlikely(!ring))
1280 goto rx_done;
1281
08df5fa6 1282 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
656e7052
JC		 1283 rxd = &ring->dma[idx];
1284 data = ring->data[idx];
1285
816ac3e6 1286 if (!mtk_rx_get_desc(&trxd, rxd))
656e7052
JC		 1287 break;
1288
1289 /* find out which mac the packet come from. values start at 1 */
d5c53da2
FF		 1290 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) ||
1291 (trxd.rxd4 & RX_DMA_SPECIAL_TAG))
296c9120 1292 mac = 0;
d5c53da2
FF		 1293 else
1294 mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
1295 RX_DMA_FPORT_MASK) - 1;
656e7052 1296
6c7fce6f
SW		 1297 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
1298 !eth->netdev[mac]))
1299 goto release_desc;
1300
656e7052
JC		 1301 netdev = eth->netdev[mac];
1302
dce6fa42
SW		 1303 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
1304 goto release_desc;
1305
656e7052
JC		 1306 /* alloc new buffer */
1307 new_data = napi_alloc_frag(ring->frag_size);
1308 if (unlikely(!new_data)) {
1309 netdev->stats.rx_dropped++;
1310 goto release_desc;
1311 }
55a4e778 1312 dma_addr = dma_map_single(eth->dev,
296c9120
SR		 1313 new_data + NET_SKB_PAD +
1314 eth->ip_align,
656e7052
JC		 1315 ring->buf_size,
1316 DMA_FROM_DEVICE);
55a4e778 1317 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
656e7052 1318 skb_free_frag(new_data);
94321a9f 1319 netdev->stats.rx_dropped++;
656e7052
JC		 1320 goto release_desc;
1321 }
1322
5196c417
FF		 1323 dma_unmap_single(eth->dev, trxd.rxd1,
1324 ring->buf_size, DMA_FROM_DEVICE);
1325
656e7052
JC		 1326 /* receive data */
1327 skb = build_skb(data, ring->frag_size);
1328 if (unlikely(!skb)) {
787082ab 1329 skb_free_frag(data);
94321a9f 1330 netdev->stats.rx_dropped++;
787082ab 1331 goto skip_rx;
656e7052
JC		 1332 }
1333 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1334
656e7052
JC		 1335 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1336 skb->dev = netdev;
1337 skb_put(skb, pktlen);
296c9120 1338 if (trxd.rxd4 & eth->rx_dma_l4_valid)
656e7052
JC		 1339 skb->ip_summed = CHECKSUM_UNNECESSARY;
1340 else
1341 skb_checksum_none_assert(skb);
1342 skb->protocol = eth_type_trans(skb, netdev);
e9229ffd 1343 bytes += pktlen;
656e7052 1344
fa817272
FF		 1345 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
1346 if (hash != MTK_RXD4_FOE_ENTRY) {
1347 hash = jhash_1word(hash, 0);
1348 skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
1349 }
1350
656e7052 1351 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3f57d8c4 1352 (trxd.rxd2 & RX_DMA_VTAG))
656e7052
JC		 1353 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1354 RX_DMA_VID(trxd.rxd3));
a2d5e7b4 1355 skb_record_rx_queue(skb, 0);
656e7052
JC		 1356 napi_gro_receive(napi, skb);
1357
787082ab 1358skip_rx:
656e7052
JC		 1359 ring->data[idx] = new_data;
1360 rxd->rxd1 = (unsigned int)dma_addr;
1361
1362release_desc:
296c9120
SR		 1363 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1364 rxd->rxd2 = RX_DMA_LSO;
1365 else
1366 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
656e7052
JC		 1367
1368 ring->calc_idx = idx;
635372ad 1369
656e7052
JC		 1370 done++;
1371 }
1372
ee406810 1373rx_done:
41156cea
SW		 1374 if (done) {
1375 /* make sure that all changes to the dma ring are flushed before
1376 * we continue
1377 */
1378 wmb();
ee406810 1379 mtk_update_rx_cpu_idx(eth);
41156cea 1380 }
656e7052 1381
e9229ffd
FF		 1382 eth->rx_packets += done;
1383 eth->rx_bytes += bytes;
1384 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes,
1385 &dim_sample);
1386 net_dim(&eth->rx_dim, dim_sample);
1387
656e7052
JC		 1388 return done;
1389}
1390
296c9120
SR		 1391static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
1392 unsigned int *done, unsigned int *bytes)
656e7052
JC		 1393{
1394 struct mtk_tx_ring *ring = &eth->tx_ring;
1395 struct mtk_tx_dma *desc;
1396 struct sk_buff *skb;
1397 struct mtk_tx_buf *tx_buf;
656e7052 1398 u32 cpu, dma;
656e7052 1399
4e6bf609 1400 cpu = ring->last_free_ptr;
656e7052
JC		 1401 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1402
1403 desc = mtk_qdma_phys_to_virt(ring, cpu);
1404
1405 while ((cpu != dma) && budget) {
1406 u32 next_cpu = desc->txd2;
134d2152 1407 int mac = 0;
656e7052
JC		 1408
1409 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1410 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1411 break;
1412
656e7052 1413 tx_buf = mtk_desc_to_tx_buf(ring, desc);
134d2152
SW		 1414 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1415 mac = 1;
1416
656e7052 1417 skb = tx_buf->skb;
f03b06f3 1418 if (!skb)
656e7052 1419 break;
656e7052
JC		 1420
1421 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1422 bytes[mac] += skb->len;
1423 done[mac]++;
1424 budget--;
1425 }
c30c4a82 1426 mtk_tx_unmap(eth, tx_buf, true);
656e7052 1427
656e7052
JC		 1428 ring->last_free = desc;
1429 atomic_inc(&ring->free_count);
1430
1431 cpu = next_cpu;
1432 }
1433
4e6bf609 1434 ring->last_free_ptr = cpu;
656e7052
JC		 1435 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1436
296c9120
SR		 1437 return budget;
1438}
1439
1440static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
1441 unsigned int *done, unsigned int *bytes)
1442{
1443 struct mtk_tx_ring *ring = &eth->tx_ring;
1444 struct mtk_tx_dma *desc;
1445 struct sk_buff *skb;
1446 struct mtk_tx_buf *tx_buf;
1447 u32 cpu, dma;
1448
1449 cpu = ring->cpu_idx;
1450 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
1451
1452 while ((cpu != dma) && budget) {
1453 tx_buf = &ring->buf[cpu];
1454 skb = tx_buf->skb;
1455 if (!skb)
1456 break;
1457
1458 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1459 bytes[0] += skb->len;
1460 done[0]++;
1461 budget--;
1462 }
1463
c30c4a82 1464 mtk_tx_unmap(eth, tx_buf, true);
296c9120
SR		 1465
1466 desc = &ring->dma[cpu];
1467 ring->last_free = desc;
1468 atomic_inc(&ring->free_count);
1469
1470 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
1471 }
1472
1473 ring->cpu_idx = cpu;
1474
1475 return budget;
1476}
1477
1478static int mtk_poll_tx(struct mtk_eth *eth, int budget)
1479{
1480 struct mtk_tx_ring *ring = &eth->tx_ring;
e9229ffd 1481 struct dim_sample dim_sample = {};
296c9120
SR		 1482 unsigned int done[MTK_MAX_DEVS];
1483 unsigned int bytes[MTK_MAX_DEVS];
1484 int total = 0, i;
1485
1486 memset(done, 0, sizeof(done));
1487 memset(bytes, 0, sizeof(bytes));
1488
1489 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1490 budget = mtk_poll_tx_qdma(eth, budget, done, bytes);
1491 else
1492 budget = mtk_poll_tx_pdma(eth, budget, done, bytes);
1493
656e7052
JC		 1494 for (i = 0; i < MTK_MAC_COUNT; i++) {
1495 if (!eth->netdev[i] || !done[i])
1496 continue;
1497 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1498 total += done[i];
e9229ffd
FF		 1499 eth->tx_packets += done[i];
1500 eth->tx_bytes += bytes[i];
656e7052
JC		 1501 }
1502
e9229ffd
FF		 1503 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
1504 &dim_sample);
1505 net_dim(&eth->tx_dim, dim_sample);
1506
ad3cba98
JC		 1507 if (mtk_queue_stopped(eth) &&
1508 (atomic_read(&ring->free_count) > ring->thresh))
13c822f6 1509 mtk_wake_queue(eth);
656e7052
JC		 1510
1511 return total;
1512}
1513
80673029 1514static void mtk_handle_status_irq(struct mtk_eth *eth)
656e7052 1515{
80673029 1516 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
656e7052 1517
eece71e8 1518 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
656e7052 1519 mtk_stats_update(eth);
eece71e8
JC		 1520 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1521 MTK_INT_STATUS2);
656e7052 1522 }
80673029
JC		 1523}
1524
1525static int mtk_napi_tx(struct napi_struct *napi, int budget)
1526{
1527 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
80673029
JC		 1528 int tx_done = 0;
1529
296c9120
SR		 1530 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1531 mtk_handle_status_irq(eth);
1532 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg);
80673029
JC		 1533 tx_done = mtk_poll_tx(eth, budget);
1534
1535 if (unlikely(netif_msg_intr(eth))) {
80673029 1536 dev_info(eth->dev,
db2c7b35
IL		 1537 "done tx %d, intr 0x%08x/0x%x\n", tx_done,
1538 mtk_r32(eth, eth->tx_int_status_reg),
1539 mtk_r32(eth, eth->tx_int_mask_reg));
80673029
JC		 1540 }
1541
1542 if (tx_done == budget)
1543 return budget;
1544
db2c7b35 1545 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT)
80673029
JC		 1546 return budget;
1547
db2c7b35 1548 if (napi_complete_done(napi, tx_done))
16769a89 1549 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
80673029
JC		 1550
1551 return tx_done;
1552}
1553
1554static int mtk_napi_rx(struct napi_struct *napi, int budget)
1555{
1556 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
db2c7b35 1557 int rx_done_total = 0;
80673029
JC		 1558
1559 mtk_handle_status_irq(eth);
41156cea 1560
db2c7b35
IL		 1561 do {
1562 int rx_done;
656e7052 1563
db2c7b35
IL		 1564 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1565 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
1566 rx_done_total += rx_done;
656e7052 1567
db2c7b35
IL		 1568 if (unlikely(netif_msg_intr(eth))) {
1569 dev_info(eth->dev,
1570 "done rx %d, intr 0x%08x/0x%x\n", rx_done,
1571 mtk_r32(eth, MTK_PDMA_INT_STATUS),
1572 mtk_r32(eth, MTK_PDMA_INT_MASK));
1573 }
1574
1575 if (rx_done_total == budget)
1576 return budget;
1577
1578 } while (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT);
16769a89 1579
db2c7b35 1580 if (napi_complete_done(napi, rx_done_total))
16769a89 1581 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
656e7052 1582
db2c7b35 1583 return rx_done_total;
656e7052
JC		 1584}
1585
1586static int mtk_tx_alloc(struct mtk_eth *eth)
1587{
1588 struct mtk_tx_ring *ring = &eth->tx_ring;
1589 int i, sz = sizeof(*ring->dma);
1590
1591 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1592 GFP_KERNEL);
1593 if (!ring->buf)
1594 goto no_tx_mem;
1595
750afb08
LC		 1596 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1597 &ring->phys, GFP_ATOMIC);
656e7052
JC		 1598 if (!ring->dma)
1599 goto no_tx_mem;
1600
656e7052
JC		 1601 for (i = 0; i < MTK_DMA_SIZE; i++) {
1602 int next = (i + 1) % MTK_DMA_SIZE;
1603 u32 next_ptr = ring->phys + next * sz;
1604
1605 ring->dma[i].txd2 = next_ptr;
1606 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1607 }
1608
296c9120
SR		 1609 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
1610 * only as the framework. The real HW descriptors are the PDMA
1611 * descriptors in ring->dma_pdma.
1612 */
1613 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1614 ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1615 &ring->phys_pdma,
1616 GFP_ATOMIC);
1617 if (!ring->dma_pdma)
1618 goto no_tx_mem;
1619
1620 for (i = 0; i < MTK_DMA_SIZE; i++) {
1621 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
1622 ring->dma_pdma[i].txd4 = 0;
1623 }
1624 }
1625
1626 ring->dma_size = MTK_DMA_SIZE;
656e7052
JC		 1627 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1628 ring->next_free = &ring->dma[0];
12c97c13 1629 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
4e6bf609 1630 ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz));
04698ccc 1631 ring->thresh = MAX_SKB_FRAGS;
656e7052
JC		 1632
1633 /* make sure that all changes to the dma ring are flushed before we
1634 * continue
1635 */
1636 wmb();
1637
296c9120
SR		 1638 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1639 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1640 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1641 mtk_w32(eth,
1642 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1643 MTK_QTX_CRX_PTR);
4e6bf609 1644 mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR);
296c9120
SR		 1645 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES,
1646 MTK_QTX_CFG(0));
1647 } else {
1648 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
1649 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0);
1650 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
1651 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX);
1652 }
656e7052
JC		 1653
1654 return 0;
1655
1656no_tx_mem:
1657 return -ENOMEM;
1658}
1659
1660static void mtk_tx_clean(struct mtk_eth *eth)
1661{
1662 struct mtk_tx_ring *ring = &eth->tx_ring;
1663 int i;
1664
1665 if (ring->buf) {
1666 for (i = 0; i < MTK_DMA_SIZE; i++)
c30c4a82 1667 mtk_tx_unmap(eth, &ring->buf[i], false);
656e7052
JC		 1668 kfree(ring->buf);
1669 ring->buf = NULL;
1670 }
1671
1672 if (ring->dma) {
1673 dma_free_coherent(eth->dev,
1674 MTK_DMA_SIZE * sizeof(*ring->dma),
1675 ring->dma,
1676 ring->phys);
1677 ring->dma = NULL;
1678 }
296c9120
SR		 1679
1680 if (ring->dma_pdma) {
1681 dma_free_coherent(eth->dev,
1682 MTK_DMA_SIZE * sizeof(*ring->dma_pdma),
1683 ring->dma_pdma,
1684 ring->phys_pdma);
1685 ring->dma_pdma = NULL;
1686 }
656e7052
JC		 1687}
1688
ee406810 1689static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
656e7052 1690{
6427dc1d 1691 struct mtk_rx_ring *ring;
ee406810 1692 int rx_data_len, rx_dma_size;
656e7052 1693 int i;
6427dc1d
JC		 1694 u32 offset = 0;
1695
1696 if (rx_flag == MTK_RX_FLAGS_QDMA) {
1697 if (ring_no)
1698 return -EINVAL;
1699 ring = &eth->rx_ring_qdma;
1700 offset = 0x1000;
1701 } else {
1702 ring = &eth->rx_ring[ring_no];
1703 }
656e7052 1704
ee406810
NC		 1705 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1706 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1707 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1708 } else {
1709 rx_data_len = ETH_DATA_LEN;
1710 rx_dma_size = MTK_DMA_SIZE;
1711 }
1712
1713 ring->frag_size = mtk_max_frag_size(rx_data_len);
656e7052 1714 ring->buf_size = mtk_max_buf_size(ring->frag_size);
ee406810 1715 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
656e7052
JC		 1716 GFP_KERNEL);
1717 if (!ring->data)
1718 return -ENOMEM;
1719
ee406810 1720 for (i = 0; i < rx_dma_size; i++) {
656e7052
JC		 1721 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1722 if (!ring->data[i])
1723 return -ENOMEM;
1724 }
1725
750afb08
LC		 1726 ring->dma = dma_alloc_coherent(eth->dev,
1727 rx_dma_size * sizeof(*ring->dma),
1728 &ring->phys, GFP_ATOMIC);
656e7052
JC		 1729 if (!ring->dma)
1730 return -ENOMEM;
1731
ee406810 1732 for (i = 0; i < rx_dma_size; i++) {
656e7052 1733 dma_addr_t dma_addr = dma_map_single(eth->dev,
296c9120 1734 ring->data[i] + NET_SKB_PAD + eth->ip_align,
656e7052
JC		 1735 ring->buf_size,
1736 DMA_FROM_DEVICE);
1737 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1738 return -ENOMEM;
1739 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1740
296c9120
SR		 1741 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1742 ring->dma[i].rxd2 = RX_DMA_LSO;
1743 else
1744 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
656e7052 1745 }
ee406810
NC		 1746 ring->dma_size = rx_dma_size;
1747 ring->calc_idx_update = false;
1748 ring->calc_idx = rx_dma_size - 1;
1749 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
656e7052
JC		 1750 /* make sure that all changes to the dma ring are flushed before we
1751 * continue
1752 */
1753 wmb();
1754
6427dc1d
JC		 1755 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1756 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1757 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1758 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
656e7052
JC		 1759
1760 return 0;
1761}
1762
6427dc1d 1763static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
656e7052 1764{
656e7052
JC		 1765 int i;
1766
1767 if (ring->data && ring->dma) {
ee406810 1768 for (i = 0; i < ring->dma_size; i++) {
656e7052
JC		 1769 if (!ring->data[i])
1770 continue;
1771 if (!ring->dma[i].rxd1)
1772 continue;
1773 dma_unmap_single(eth->dev,
1774 ring->dma[i].rxd1,
1775 ring->buf_size,
1776 DMA_FROM_DEVICE);
1777 skb_free_frag(ring->data[i]);
1778 }
1779 kfree(ring->data);
1780 ring->data = NULL;
1781 }
1782
1783 if (ring->dma) {
1784 dma_free_coherent(eth->dev,
ee406810 1785 ring->dma_size * sizeof(*ring->dma),
656e7052
JC		 1786 ring->dma,
1787 ring->phys);
1788 ring->dma = NULL;
1789 }
1790}
1791
ee406810
NC		 1792static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1793{
1794 int i;
1795 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1796 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1797
1798 /* set LRO rings to auto-learn modes */
1799 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1800
1801 /* validate LRO ring */
1802 ring_ctrl_dw2 |= MTK_RING_VLD;
1803
1804 /* set AGE timer (unit: 20us) */
1805 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1806 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1807
1808 /* set max AGG timer (unit: 20us) */
1809 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1810
1811 /* set max LRO AGG count */
1812 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1813 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1814
1815 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1816 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1817 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1818 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1819 }
1820
1821 /* IPv4 checksum update enable */
1822 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1823
1824 /* switch priority comparison to packet count mode */
1825 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1826
1827 /* bandwidth threshold setting */
1828 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1829
1830 /* auto-learn score delta setting */
1831 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1832
1833 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1834 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1835 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1836
1837 /* set HW LRO mode & the max aggregation count for rx packets */
1838 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1839
1840 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1841 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1842
1843 /* enable HW LRO */
1844 lro_ctrl_dw0 |= MTK_LRO_EN;
1845
1846 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1847 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1848
1849 return 0;
1850}
1851
1852static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1853{
1854 int i;
1855 u32 val;
1856
1857 /* relinquish lro rings, flush aggregated packets */
1858 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1859
1860 /* wait for relinquishments done */
1861 for (i = 0; i < 10; i++) {
1862 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1863 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1864 msleep(20);
1865 continue;
1866 }
ca3ba106 1867 break;
ee406810
NC		 1868 }
1869
1870 /* invalidate lro rings */
1871 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1872 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1873
1874 /* disable HW LRO */
1875 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1876}
1877
7aab747e
NC		 1878static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1879{
1880 u32 reg_val;
1881
1882 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1883
1884 /* invalidate the IP setting */
1885 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1886
1887 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1888
1889 /* validate the IP setting */
1890 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1891}
1892
1893static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1894{
1895 u32 reg_val;
1896
1897 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1898
1899 /* invalidate the IP setting */
1900 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1901
1902 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1903}
1904
1905static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1906{
1907 int cnt = 0;
1908 int i;
1909
1910 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1911 if (mac->hwlro_ip[i])
1912 cnt++;
1913 }
1914
1915 return cnt;
1916}
1917
1918static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1919 struct ethtool_rxnfc *cmd)
1920{
1921 struct ethtool_rx_flow_spec *fsp =
1922 (struct ethtool_rx_flow_spec *)&cmd->fs;
1923 struct mtk_mac *mac = netdev_priv(dev);
1924 struct mtk_eth *eth = mac->hw;
1925 int hwlro_idx;
1926
1927 if ((fsp->flow_type != TCP_V4_FLOW) ||
1928 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1929 (fsp->location > 1))
1930 return -EINVAL;
1931
1932 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1933 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1934
1935 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1936
1937 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1938
1939 return 0;
1940}
1941
1942static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1943 struct ethtool_rxnfc *cmd)
1944{
1945 struct ethtool_rx_flow_spec *fsp =
1946 (struct ethtool_rx_flow_spec *)&cmd->fs;
1947 struct mtk_mac *mac = netdev_priv(dev);
1948 struct mtk_eth *eth = mac->hw;
1949 int hwlro_idx;
1950
1951 if (fsp->location > 1)
1952 return -EINVAL;
1953
1954 mac->hwlro_ip[fsp->location] = 0;
1955 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1956
1957 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1958
1959 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1960
1961 return 0;
1962}
1963
1964static void mtk_hwlro_netdev_disable(struct net_device *dev)
1965{
1966 struct mtk_mac *mac = netdev_priv(dev);
1967 struct mtk_eth *eth = mac->hw;
1968 int i, hwlro_idx;
1969
1970 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1971 mac->hwlro_ip[i] = 0;
1972 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1973
1974 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1975 }
1976
1977 mac->hwlro_ip_cnt = 0;
1978}
1979
1980static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1981 struct ethtool_rxnfc *cmd)
1982{
1983 struct mtk_mac *mac = netdev_priv(dev);
1984 struct ethtool_rx_flow_spec *fsp =
1985 (struct ethtool_rx_flow_spec *)&cmd->fs;
1986
1987 /* only tcp dst ipv4 is meaningful, others are meaningless */
1988 fsp->flow_type = TCP_V4_FLOW;
1989 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1990 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1991
1992 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1993 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1994 fsp->h_u.tcp_ip4_spec.psrc = 0;
1995 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1996 fsp->h_u.tcp_ip4_spec.pdst = 0;
1997 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1998 fsp->h_u.tcp_ip4_spec.tos = 0;
1999 fsp->m_u.tcp_ip4_spec.tos = 0xff;
2000
2001 return 0;
2002}
2003
2004static int mtk_hwlro_get_fdir_all(struct net_device *dev,
2005 struct ethtool_rxnfc *cmd,
2006 u32 *rule_locs)
2007{
2008 struct mtk_mac *mac = netdev_priv(dev);
2009 int cnt = 0;
2010 int i;
2011
2012 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2013 if (mac->hwlro_ip[i]) {
2014 rule_locs[cnt] = i;
2015 cnt++;
2016 }
2017 }
2018
2019 cmd->rule_cnt = cnt;
2020
2021 return 0;
2022}
2023
2024static netdev_features_t mtk_fix_features(struct net_device *dev,
2025 netdev_features_t features)
2026{
2027 if (!(features & NETIF_F_LRO)) {
2028 struct mtk_mac *mac = netdev_priv(dev);
2029 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2030
2031 if (ip_cnt) {
2032 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
2033
2034 features |= NETIF_F_LRO;
2035 }
2036 }
2037
2038 return features;
2039}
2040
2041static int mtk_set_features(struct net_device *dev, netdev_features_t features)
2042{
2043 int err = 0;
2044
2045 if (!((dev->features ^ features) & NETIF_F_LRO))
2046 return 0;
2047
2048 if (!(features & NETIF_F_LRO))
2049 mtk_hwlro_netdev_disable(dev);
2050
2051 return err;
2052}
2053
656e7052
JC		 2054/* wait for DMA to finish whatever it is doing before we start using it again */
2055static int mtk_dma_busy_wait(struct mtk_eth *eth)
2056{
3bc8e0af
IL		 2057 unsigned int reg;
2058 int ret;
2059 u32 val;
656e7052 2060
3bc8e0af
IL		 2061 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2062 reg = MTK_QDMA_GLO_CFG;
2063 else
2064 reg = MTK_PDMA_GLO_CFG;
296c9120 2065
3bc8e0af
IL		 2066 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
2067 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
2068 5, MTK_DMA_BUSY_TIMEOUT_US);
2069 if (ret)
2070 dev_err(eth->dev, "DMA init timeout\n");
656e7052 2071
3bc8e0af 2072 return ret;
656e7052
JC		 2073}
2074
2075static int mtk_dma_init(struct mtk_eth *eth)
2076{
2077 int err;
ee406810 2078 u32 i;
656e7052
JC		 2079
2080 if (mtk_dma_busy_wait(eth))
2081 return -EBUSY;
2082
296c9120
SR		 2083 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2084 /* QDMA needs scratch memory for internal reordering of the
2085 * descriptors
2086 */
2087 err = mtk_init_fq_dma(eth);
2088 if (err)
2089 return err;
2090 }
656e7052
JC		 2091
2092 err = mtk_tx_alloc(eth);
2093 if (err)
2094 return err;
2095
296c9120
SR		 2096 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2097 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
2098 if (err)
2099 return err;
2100 }
6427dc1d 2101
ee406810 2102 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
656e7052
JC		 2103 if (err)
2104 return err;
2105
ee406810
NC		 2106 if (eth->hwlro) {
2107 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2108 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
2109 if (err)
2110 return err;
2111 }
2112 err = mtk_hwlro_rx_init(eth);
2113 if (err)
2114 return err;
2115 }
2116
296c9120
SR		 2117 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2118 /* Enable random early drop and set drop threshold
2119 * automatically
2120 */
2121 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
2122 FC_THRES_MIN, MTK_QDMA_FC_THRES);
2123 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
2124 }
656e7052
JC		 2125
2126 return 0;
2127}
2128
2129static void mtk_dma_free(struct mtk_eth *eth)
2130{
2131 int i;
2132
2133 for (i = 0; i < MTK_MAC_COUNT; i++)
2134 if (eth->netdev[i])
2135 netdev_reset_queue(eth->netdev[i]);
605e4fe4
JC		 2136 if (eth->scratch_ring) {
2137 dma_free_coherent(eth->dev,
2138 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
2139 eth->scratch_ring,
2140 eth->phy_scratch_ring);
2141 eth->scratch_ring = NULL;
2142 eth->phy_scratch_ring = 0;
2143 }
656e7052 2144 mtk_tx_clean(eth);
6427dc1d
JC		 2145 mtk_rx_clean(eth, &eth->rx_ring[0]);
2146 mtk_rx_clean(eth, &eth->rx_ring_qdma);
ee406810
NC		 2147
2148 if (eth->hwlro) {
2149 mtk_hwlro_rx_uninit(eth);
2150 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
6427dc1d 2151 mtk_rx_clean(eth, &eth->rx_ring[i]);
ee406810
NC		 2152 }
2153
656e7052
JC		 2154 kfree(eth->scratch_head);
2155}
2156
0290bd29 2157static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
656e7052
JC		 2158{
2159 struct mtk_mac *mac = netdev_priv(dev);
2160 struct mtk_eth *eth = mac->hw;
2161
2162 eth->netdev[mac->id]->stats.tx_errors++;
2163 netif_err(eth, tx_err, dev,
2164 "transmit timed out\n");
7c78b4ad 2165 schedule_work(&eth->pending_work);
656e7052
JC		 2166}
2167
80673029 2168static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
656e7052
JC		 2169{
2170 struct mtk_eth *eth = _eth;
656e7052 2171
e9229ffd 2172 eth->rx_events++;
80673029
JC		 2173 if (likely(napi_schedule_prep(&eth->rx_napi))) {
2174 __napi_schedule(&eth->rx_napi);
5cce0322 2175 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
80673029 2176 }
656e7052 2177
80673029
JC		 2178 return IRQ_HANDLED;
2179}
2180
2181static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
2182{
2183 struct mtk_eth *eth = _eth;
2184
e9229ffd 2185 eth->tx_events++;
80673029
JC		 2186 if (likely(napi_schedule_prep(&eth->tx_napi))) {
2187 __napi_schedule(&eth->tx_napi);
5cce0322 2188 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
656e7052 2189 }
656e7052
JC		 2190
2191 return IRQ_HANDLED;
2192}
2193
889bcbde
BM		 2194static irqreturn_t mtk_handle_irq(int irq, void *_eth)
2195{
2196 struct mtk_eth *eth = _eth;
2197
2198 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) {
2199 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT)
2200 mtk_handle_irq_rx(irq, _eth);
2201 }
296c9120
SR		 2202 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) {
2203 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT)
889bcbde
BM		 2204 mtk_handle_irq_tx(irq, _eth);
2205 }
2206
2207 return IRQ_HANDLED;
2208}
2209
656e7052
JC		 2210#ifdef CONFIG_NET_POLL_CONTROLLER
2211static void mtk_poll_controller(struct net_device *dev)
2212{
2213 struct mtk_mac *mac = netdev_priv(dev);
2214 struct mtk_eth *eth = mac->hw;
656e7052 2215
5cce0322
JC		 2216 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2217 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
8186f6e3 2218 mtk_handle_irq_rx(eth->irq[2], dev);
5cce0322
JC		 2219 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2220 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
656e7052
JC		 2221}
2222#endif
2223
2224static int mtk_start_dma(struct mtk_eth *eth)
2225{
880c2d4b 2226 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
656e7052
JC		 2227 int err;
2228
2229 err = mtk_dma_init(eth);
2230 if (err) {
2231 mtk_dma_free(eth);
2232 return err;
2233 }
2234
296c9120
SR		 2235 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2236 mtk_w32(eth,
2237 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
59555a8d 2238 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
296c9120
SR		 2239 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
2240 MTK_RX_BT_32DWORDS,
2241 MTK_QDMA_GLO_CFG);
656e7052 2242
296c9120
SR		 2243 mtk_w32(eth,
2244 MTK_RX_DMA_EN | rx_2b_offset |
2245 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
2246 MTK_PDMA_GLO_CFG);
2247 } else {
2248 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
2249 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
2250 MTK_PDMA_GLO_CFG);
2251 }
bacfd110 2252
656e7052
JC		 2253 return 0;
2254}
2255
8d3f4a95
M		 2256static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
2257{
2258 int i;
2259
5ac9eda0
M		 2260 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2261 return;
2262
8d3f4a95
M		 2263 for (i = 0; i < MTK_MAC_COUNT; i++) {
2264 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
2265
2266 /* default setup the forward port to send frame to PDMA */
2267 val &= ~0xffff;
2268
2269 /* Enable RX checksum */
2270 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2271
2272 val |= config;
2273
d5c53da2
FF		 2274 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]))
2275 val |= MTK_GDMA_SPECIAL_TAG;
2276
8d3f4a95
M		 2277 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2278 }
2279 /* Reset and enable PSE */
2280 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
2281 mtk_w32(eth, 0, MTK_RST_GL);
2282}
2283
656e7052
JC		 2284static int mtk_open(struct net_device *dev)
2285{
2286 struct mtk_mac *mac = netdev_priv(dev);
2287 struct mtk_eth *eth = mac->hw;
b8fc9f30
RD		 2288 int err;
2289
2290 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
2291 if (err) {
2292 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
2293 err);
2294 return err;
2295 }
656e7052
JC		 2296
2297 /* we run 2 netdevs on the same dma ring so we only bring it up once */
c6d4e63e 2298 if (!refcount_read(&eth->dma_refcnt)) {
ba37b7ca
FF		 2299 u32 gdm_config = MTK_GDMA_TO_PDMA;
2300 int err;
656e7052 2301
ba37b7ca 2302 err = mtk_start_dma(eth);
656e7052
JC		 2303 if (err)
2304 return err;
2305
ba37b7ca
FF		 2306 if (eth->soc->offload_version && mtk_ppe_start(&eth->ppe) == 0)
2307 gdm_config = MTK_GDMA_TO_PPE;
2308
2309 mtk_gdm_config(eth, gdm_config);
5ac9eda0 2310
80673029 2311 napi_enable(&eth->tx_napi);
656e7052 2312 napi_enable(&eth->rx_napi);
5cce0322
JC		 2313 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2314 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
c6d4e63e 2315 refcount_set(&eth->dma_refcnt, 1);
656e7052 2316 }
c6d4e63e
ER		 2317 else
2318 refcount_inc(&eth->dma_refcnt);
656e7052 2319
b8fc9f30 2320 phylink_start(mac->phylink);
656e7052 2321 netif_start_queue(dev);
656e7052
JC		 2322 return 0;
2323}
2324
2325static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
2326{
656e7052
JC		 2327 u32 val;
2328 int i;
2329
2330 /* stop the dma engine */
e3e9652a 2331 spin_lock_bh(&eth->page_lock);
656e7052
JC		 2332 val = mtk_r32(eth, glo_cfg);
2333 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
2334 glo_cfg);
e3e9652a 2335 spin_unlock_bh(&eth->page_lock);
656e7052
JC		 2336
2337 /* wait for dma stop */
2338 for (i = 0; i < 10; i++) {
2339 val = mtk_r32(eth, glo_cfg);
2340 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
2341 msleep(20);
2342 continue;
2343 }
2344 break;
2345 }
2346}
2347
2348static int mtk_stop(struct net_device *dev)
2349{
2350 struct mtk_mac *mac = netdev_priv(dev);
2351 struct mtk_eth *eth = mac->hw;
2352
b8fc9f30
RD		 2353 phylink_stop(mac->phylink);
2354
656e7052 2355 netif_tx_disable(dev);
b8fc9f30
RD		 2356
2357 phylink_disconnect_phy(mac->phylink);
656e7052
JC		 2358
2359 /* only shutdown DMA if this is the last user */
c6d4e63e 2360 if (!refcount_dec_and_test(&eth->dma_refcnt))
656e7052
JC		 2361 return 0;
2362
8d66a818
M		 2363 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
2364
5cce0322
JC		 2365 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2366 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
80673029 2367 napi_disable(&eth->tx_napi);
656e7052
JC		 2368 napi_disable(&eth->rx_napi);
2369
e9229ffd
FF		 2370 cancel_work_sync(&eth->rx_dim.work);
2371 cancel_work_sync(&eth->tx_dim.work);
2372
296c9120
SR		 2373 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2374 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
6bf563d5 2375 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
656e7052
JC		 2376
2377 mtk_dma_free(eth);
2378
ba37b7ca
FF		 2379 if (eth->soc->offload_version)
2380 mtk_ppe_stop(&eth->ppe);
2381
656e7052
JC		 2382 return 0;
2383}
2384
2a8307aa
SW		 2385static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
2386{
2387 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
2388 reset_bits,
2389 reset_bits);
2390
2391 usleep_range(1000, 1100);
2392 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
2393 reset_bits,
2394 ~reset_bits);
2395 mdelay(10);
2396}
2397
2ec50f57
SW		 2398static void mtk_clk_disable(struct mtk_eth *eth)
2399{
2400 int clk;
2401
2402 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
2403 clk_disable_unprepare(eth->clks[clk]);
2404}
2405
2406static int mtk_clk_enable(struct mtk_eth *eth)
2407{
2408 int clk, ret;
2409
2410 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
2411 ret = clk_prepare_enable(eth->clks[clk]);
2412 if (ret)
2413 goto err_disable_clks;
2414 }
2415
2416 return 0;
2417
2418err_disable_clks:
2419 while (--clk >= 0)
2420 clk_disable_unprepare(eth->clks[clk]);
2421
2422 return ret;
2423}
2424
e9229ffd
FF		 2425static void mtk_dim_rx(struct work_struct *work)
2426{
2427 struct dim *dim = container_of(work, struct dim, work);
2428 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
2429 struct dim_cq_moder cur_profile;
2430 u32 val, cur;
2431
2432 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode,
2433 dim->profile_ix);
2434 spin_lock_bh(&eth->dim_lock);
2435
2436 val = mtk_r32(eth, MTK_PDMA_DELAY_INT);
2437 val &= MTK_PDMA_DELAY_TX_MASK;
2438 val |= MTK_PDMA_DELAY_RX_EN;
2439
2440 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
2441 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT;
2442
2443 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
2444 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
2445
2446 mtk_w32(eth, val, MTK_PDMA_DELAY_INT);
430bfe05
SR		 2447 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2448 mtk_w32(eth, val, MTK_QDMA_DELAY_INT);
e9229ffd
FF		 2449
2450 spin_unlock_bh(&eth->dim_lock);
2451
2452 dim->state = DIM_START_MEASURE;
2453}
2454
2455static void mtk_dim_tx(struct work_struct *work)
2456{
2457 struct dim *dim = container_of(work, struct dim, work);
2458 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
2459 struct dim_cq_moder cur_profile;
2460 u32 val, cur;
2461
2462 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode,
2463 dim->profile_ix);
2464 spin_lock_bh(&eth->dim_lock);
2465
2466 val = mtk_r32(eth, MTK_PDMA_DELAY_INT);
2467 val &= MTK_PDMA_DELAY_RX_MASK;
2468 val |= MTK_PDMA_DELAY_TX_EN;
2469
2470 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
2471 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT;
2472
2473 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
2474 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
2475
2476 mtk_w32(eth, val, MTK_PDMA_DELAY_INT);
430bfe05
SR		 2477 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2478 mtk_w32(eth, val, MTK_QDMA_DELAY_INT);
e9229ffd
FF		 2479
2480 spin_unlock_bh(&eth->dim_lock);
2481
2482 dim->state = DIM_START_MEASURE;
2483}
2484
9ea4d311 2485static int mtk_hw_init(struct mtk_eth *eth)
656e7052 2486{
2ec50f57 2487 int i, val, ret;
9ea4d311
SW		 2488
2489 if (test_and_set_bit(MTK_HW_INIT, &eth->state))
2490 return 0;
85574dbf 2491
26a2ad8a
SW		 2492 pm_runtime_enable(eth->dev);
2493 pm_runtime_get_sync(eth->dev);
2494
2ec50f57
SW		 2495 ret = mtk_clk_enable(eth);
2496 if (ret)
2497 goto err_disable_pm;
2498
296c9120
SR		 2499 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2500 ret = device_reset(eth->dev);
2501 if (ret) {
2502 dev_err(eth->dev, "MAC reset failed!\n");
2503 goto err_disable_pm;
2504 }
2505
430bfe05
SR		 2506 /* set interrupt delays based on current Net DIM sample */
2507 mtk_dim_rx(&eth->rx_dim.work);
2508 mtk_dim_tx(&eth->tx_dim.work);
2509
296c9120
SR		 2510 /* disable delay and normal interrupt */
2511 mtk_tx_irq_disable(eth, ~0);
2512 mtk_rx_irq_disable(eth, ~0);
2513
2514 return 0;
2515 }
2516
2517 /* Non-MT7628 handling... */
2a8307aa
SW		 2518 ethsys_reset(eth, RSTCTRL_FE);
2519 ethsys_reset(eth, RSTCTRL_PPE);
656e7052 2520
243dc5fb
SW		 2521 if (eth->pctl) {
2522 /* Set GE2 driving and slew rate */
2523 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
656e7052 2524
243dc5fb
SW		 2525 /* set GE2 TDSEL */
2526 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
656e7052 2527
243dc5fb
SW		 2528 /* set GE2 TUNE */
2529 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
2530 }
656e7052 2531
7352e252 2532 /* Set linkdown as the default for each GMAC. Its own MCR would be set
b8fc9f30
RD		 2533 * up with the more appropriate value when mtk_mac_config call is being
2534 * invoked.
7352e252
SW		 2535 */
2536 for (i = 0; i < MTK_MAC_COUNT; i++)
b8fc9f30 2537 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
656e7052 2538
87e3df49
SW		 2539 /* Indicates CDM to parse the MTK special tag from CPU
2540 * which also is working out for untag packets.
2541 */
2542 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
2543 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
2544
656e7052
JC		 2545 /* Enable RX VLan Offloading */
2546 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
2547
e9229ffd
FF		 2548 /* set interrupt delays based on current Net DIM sample */
2549 mtk_dim_rx(&eth->rx_dim.work);
2550 mtk_dim_tx(&eth->tx_dim.work);
671d41e6 2551
656e7052 2552 /* disable delay and normal interrupt */
5cce0322
JC		 2553 mtk_tx_irq_disable(eth, ~0);
2554 mtk_rx_irq_disable(eth, ~0);
656e7052
JC		 2555
2556 /* FE int grouping */
80673029
JC		 2557 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
2558 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
2559 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
2560 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
2561 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
656e7052 2562
656e7052 2563 return 0;
2ec50f57
SW		 2564
2565err_disable_pm:
2566 pm_runtime_put_sync(eth->dev);
2567 pm_runtime_disable(eth->dev);
2568
2569 return ret;
656e7052
JC		 2570}
2571
bf253fb7
SW		 2572static int mtk_hw_deinit(struct mtk_eth *eth)
2573{
9ea4d311
SW		 2574 if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
2575 return 0;
2576
2ec50f57 2577 mtk_clk_disable(eth);
bf253fb7 2578
26a2ad8a
SW		 2579 pm_runtime_put_sync(eth->dev);
2580 pm_runtime_disable(eth->dev);
2581
bf253fb7
SW		 2582 return 0;
2583}
2584
656e7052
JC		 2585static int __init mtk_init(struct net_device *dev)
2586{
2587 struct mtk_mac *mac = netdev_priv(dev);
2588 struct mtk_eth *eth = mac->hw;
83216e39 2589 int ret;
656e7052 2590
83216e39
MW		 2591 ret = of_get_mac_address(mac->of_node, dev->dev_addr);
2592 if (ret) {
2593 /* If the mac address is invalid, use random mac address */
e3c36e48 2594 eth_hw_addr_random(dev);
656e7052
JC		 2595 dev_err(eth->dev, "generated random MAC address %pM\n",
2596 dev->dev_addr);
656e7052
JC		 2597 }
2598
b8fc9f30 2599 return 0;
656e7052
JC		 2600}
2601
2602static void mtk_uninit(struct net_device *dev)
2603{
2604 struct mtk_mac *mac = netdev_priv(dev);
2605 struct mtk_eth *eth = mac->hw;
2606
b8fc9f30 2607 phylink_disconnect_phy(mac->phylink);
5cce0322
JC		 2608 mtk_tx_irq_disable(eth, ~0);
2609 mtk_rx_irq_disable(eth, ~0);
656e7052
JC		 2610}
2611
4fd59792
DQ		 2612static int mtk_change_mtu(struct net_device *dev, int new_mtu)
2613{
2614 int length = new_mtu + MTK_RX_ETH_HLEN;
2615 struct mtk_mac *mac = netdev_priv(dev);
2616 struct mtk_eth *eth = mac->hw;
2617 u32 mcr_cur, mcr_new;
2618
2619 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2620 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
2621 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK;
2622
2623 if (length <= 1518)
2624 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518);
2625 else if (length <= 1536)
2626 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536);
2627 else if (length <= 1552)
2628 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552);
2629 else
2630 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048);
2631
2632 if (mcr_new != mcr_cur)
2633 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
2634 }
2635
2636 dev->mtu = new_mtu;
2637
2638 return 0;
2639}
2640
656e7052
JC		 2641static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2642{
b8fc9f30
RD		 2643 struct mtk_mac *mac = netdev_priv(dev);
2644
656e7052
JC		 2645 switch (cmd) {
2646 case SIOCGMIIPHY:
2647 case SIOCGMIIREG:
2648 case SIOCSMIIREG:
b8fc9f30 2649 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
656e7052
JC		 2650 default:
2651 break;
2652 }
2653
2654 return -EOPNOTSUPP;
2655}
2656
2657static void mtk_pending_work(struct work_struct *work)
2658{
7c78b4ad 2659 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
e7d425dc
JC		 2660 int err, i;
2661 unsigned long restart = 0;
656e7052
JC		 2662
2663 rtnl_lock();
656e7052 2664
dce6fa42
SW		 2665 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2666
2667 while (test_and_set_bit_lock(MTK_RESETTING, &eth->state))
2668 cpu_relax();
2669
2670 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
e7d425dc
JC		 2671 /* stop all devices to make sure that dma is properly shut down */
2672 for (i = 0; i < MTK_MAC_COUNT; i++) {
7c78b4ad 2673 if (!eth->netdev[i])
e7d425dc
JC		 2674 continue;
2675 mtk_stop(eth->netdev[i]);
2676 __set_bit(i, &restart);
2677 }
dce6fa42 2678 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
e7d425dc 2679
9ea4d311
SW		 2680 /* restart underlying hardware such as power, clock, pin mux
2681 * and the connected phy
2682 */
2683 mtk_hw_deinit(eth);
2684
2685 if (eth->dev->pins)
2686 pinctrl_select_state(eth->dev->pins->p,
2687 eth->dev->pins->default_state);
2688 mtk_hw_init(eth);
2689
e7d425dc
JC		 2690 /* restart DMA and enable IRQs */
2691 for (i = 0; i < MTK_MAC_COUNT; i++) {
2692 if (!test_bit(i, &restart))
2693 continue;
2694 err = mtk_open(eth->netdev[i]);
2695 if (err) {
2696 netif_alert(eth, ifup, eth->netdev[i],
2697 "Driver up/down cycle failed, closing device.\n");
2698 dev_close(eth->netdev[i]);
2699 }
656e7052 2700 }
dce6fa42
SW		 2701
2702 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2703
2704 clear_bit_unlock(MTK_RESETTING, &eth->state);
2705
656e7052
JC		 2706 rtnl_unlock();
2707}
2708
8a8a9e89 2709static int mtk_free_dev(struct mtk_eth *eth)
656e7052
JC		 2710{
2711 int i;
2712
2713 for (i = 0; i < MTK_MAC_COUNT; i++) {
656e7052
JC		 2714 if (!eth->netdev[i])
2715 continue;
8a8a9e89
SW		 2716 free_netdev(eth->netdev[i]);
2717 }
2718
2719 return 0;
2720}
656e7052 2721
8a8a9e89
SW		 2722static int mtk_unreg_dev(struct mtk_eth *eth)
2723{
2724 int i;
2725
2726 for (i = 0; i < MTK_MAC_COUNT; i++) {
2727 if (!eth->netdev[i])
2728 continue;
656e7052 2729 unregister_netdev(eth->netdev[i]);
656e7052 2730 }
8a8a9e89
SW		 2731
2732 return 0;
2733}
2734
2735static int mtk_cleanup(struct mtk_eth *eth)
2736{
2737 mtk_unreg_dev(eth);
2738 mtk_free_dev(eth);
7c78b4ad 2739 cancel_work_sync(&eth->pending_work);
656e7052
JC		 2740
2741 return 0;
2742}
2743
3a82e78c
BX		 2744static int mtk_get_link_ksettings(struct net_device *ndev,
2745 struct ethtool_link_ksettings *cmd)
656e7052 2746{
3e60b748 2747 struct mtk_mac *mac = netdev_priv(ndev);
656e7052 2748
dce6fa42
SW		 2749 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2750 return -EBUSY;
2751
b8fc9f30 2752 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
656e7052
JC		 2753}
2754
3a82e78c
BX		 2755static int mtk_set_link_ksettings(struct net_device *ndev,
2756 const struct ethtool_link_ksettings *cmd)
656e7052 2757{
3e60b748 2758 struct mtk_mac *mac = netdev_priv(ndev);
656e7052 2759
3e60b748
SW		 2760 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2761 return -EBUSY;
656e7052 2762
b8fc9f30 2763 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
656e7052
JC		 2764}
2765
2766static void mtk_get_drvinfo(struct net_device *dev,
2767 struct ethtool_drvinfo *info)
2768{
2769 struct mtk_mac *mac = netdev_priv(dev);
2770
2771 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2772 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2773 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2774}
2775
2776static u32 mtk_get_msglevel(struct net_device *dev)
2777{
2778 struct mtk_mac *mac = netdev_priv(dev);
2779
2780 return mac->hw->msg_enable;
2781}
2782
2783static void mtk_set_msglevel(struct net_device *dev, u32 value)
2784{
2785 struct mtk_mac *mac = netdev_priv(dev);
2786
2787 mac->hw->msg_enable = value;
2788}
2789
2790static int mtk_nway_reset(struct net_device *dev)
2791{
2792 struct mtk_mac *mac = netdev_priv(dev);
2793
dce6fa42
SW		 2794 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2795 return -EBUSY;
2796
b8fc9f30
RD		 2797 if (!mac->phylink)
2798 return -ENOTSUPP;
656e7052 2799
b8fc9f30 2800 return phylink_ethtool_nway_reset(mac->phylink);
656e7052
JC		 2801}
2802
2803static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2804{
2805 int i;
2806
2807 switch (stringset) {
2808 case ETH_SS_STATS:
2809 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2810 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2811 data += ETH_GSTRING_LEN;
2812 }
2813 break;
2814 }
2815}
2816
2817static int mtk_get_sset_count(struct net_device *dev, int sset)
2818{
2819 switch (sset) {
2820 case ETH_SS_STATS:
2821 return ARRAY_SIZE(mtk_ethtool_stats);
2822 default:
2823 return -EOPNOTSUPP;
2824 }
2825}
2826
2827static void mtk_get_ethtool_stats(struct net_device *dev,
2828 struct ethtool_stats *stats, u64 *data)
2829{
2830 struct mtk_mac *mac = netdev_priv(dev);
2831 struct mtk_hw_stats *hwstats = mac->hw_stats;
2832 u64 *data_src, *data_dst;
2833 unsigned int start;
2834 int i;
2835
dce6fa42
SW		 2836 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2837 return;
2838
656e7052 2839 if (netif_running(dev) && netif_device_present(dev)) {
8d32e062 2840 if (spin_trylock_bh(&hwstats->stats_lock)) {
656e7052 2841 mtk_stats_update_mac(mac);
8d32e062 2842 spin_unlock_bh(&hwstats->stats_lock);
656e7052
JC		 2843 }
2844 }
2845
94d308d0
SW		 2846 data_src = (u64 *)hwstats;
2847
656e7052 2848 do {
656e7052
JC		 2849 data_dst = data;
2850 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2851
2852 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2853 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2854 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2855}
2856
7aab747e
NC		 2857static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2858 u32 *rule_locs)
2859{
2860 int ret = -EOPNOTSUPP;
2861
2862 switch (cmd->cmd) {
2863 case ETHTOOL_GRXRINGS:
9e4f56f1 2864 if (dev->hw_features & NETIF_F_LRO) {
7aab747e
NC		 2865 cmd->data = MTK_MAX_RX_RING_NUM;
2866 ret = 0;
2867 }
2868 break;
2869 case ETHTOOL_GRXCLSRLCNT:
9e4f56f1 2870 if (dev->hw_features & NETIF_F_LRO) {
7aab747e
NC		 2871 struct mtk_mac *mac = netdev_priv(dev);
2872
2873 cmd->rule_cnt = mac->hwlro_ip_cnt;
2874 ret = 0;
2875 }
2876 break;
2877 case ETHTOOL_GRXCLSRULE:
9e4f56f1 2878 if (dev->hw_features & NETIF_F_LRO)
7aab747e
NC		 2879 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2880 break;
2881 case ETHTOOL_GRXCLSRLALL:
9e4f56f1 2882 if (dev->hw_features & NETIF_F_LRO)
7aab747e
NC		 2883 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2884 rule_locs);
2885 break;
2886 default:
2887 break;
2888 }
2889
2890 return ret;
2891}
2892
2893static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2894{
2895 int ret = -EOPNOTSUPP;
2896
2897 switch (cmd->cmd) {
2898 case ETHTOOL_SRXCLSRLINS:
9e4f56f1 2899 if (dev->hw_features & NETIF_F_LRO)
7aab747e
NC		 2900 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2901 break;
2902 case ETHTOOL_SRXCLSRLDEL:
9e4f56f1 2903 if (dev->hw_features & NETIF_F_LRO)
7aab747e
NC		 2904 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2905 break;
2906 default:
2907 break;
2908 }
2909
2910 return ret;
2911}
2912
6a38cb15 2913static const struct ethtool_ops mtk_ethtool_ops = {
3e60b748
SW		 2914 .get_link_ksettings = mtk_get_link_ksettings,
2915 .set_link_ksettings = mtk_set_link_ksettings,
656e7052
JC		 2916 .get_drvinfo = mtk_get_drvinfo,
2917 .get_msglevel = mtk_get_msglevel,
2918 .set_msglevel = mtk_set_msglevel,
2919 .nway_reset = mtk_nway_reset,
b8fc9f30 2920 .get_link = ethtool_op_get_link,
656e7052
JC		 2921 .get_strings = mtk_get_strings,
2922 .get_sset_count = mtk_get_sset_count,
2923 .get_ethtool_stats = mtk_get_ethtool_stats,
7aab747e
NC		 2924 .get_rxnfc = mtk_get_rxnfc,
2925 .set_rxnfc = mtk_set_rxnfc,
656e7052
JC		 2926};
2927
2928static const struct net_device_ops mtk_netdev_ops = {
2929 .ndo_init = mtk_init,
2930 .ndo_uninit = mtk_uninit,
2931 .ndo_open = mtk_open,
2932 .ndo_stop = mtk_stop,
2933 .ndo_start_xmit = mtk_start_xmit,
2934 .ndo_set_mac_address = mtk_set_mac_address,
2935 .ndo_validate_addr = eth_validate_addr,
a7605370 2936 .ndo_eth_ioctl = mtk_do_ioctl,
4fd59792 2937 .ndo_change_mtu = mtk_change_mtu,
656e7052
JC		 2938 .ndo_tx_timeout = mtk_tx_timeout,
2939 .ndo_get_stats64 = mtk_get_stats64,
7aab747e
NC		 2940 .ndo_fix_features = mtk_fix_features,
2941 .ndo_set_features = mtk_set_features,
656e7052
JC		 2942#ifdef CONFIG_NET_POLL_CONTROLLER
2943 .ndo_poll_controller = mtk_poll_controller,
2944#endif
502e84e2 2945 .ndo_setup_tc = mtk_eth_setup_tc,
656e7052
JC		 2946};
2947
2948static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2949{
656e7052 2950 const __be32 *_id = of_get_property(np, "reg", NULL);
0c65b2b9 2951 phy_interface_t phy_mode;
b8fc9f30 2952 struct phylink *phylink;
b8fc9f30 2953 struct mtk_mac *mac;
0c65b2b9 2954 int id, err;
656e7052
JC		 2955
2956 if (!_id) {
2957 dev_err(eth->dev, "missing mac id\n");
2958 return -EINVAL;
2959 }
2960
2961 id = be32_to_cpup(_id);
2962 if (id >= MTK_MAC_COUNT) {
2963 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2964 return -EINVAL;
2965 }
2966
2967 if (eth->netdev[id]) {
2968 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2969 return -EINVAL;
2970 }
2971
2972 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2973 if (!eth->netdev[id]) {
2974 dev_err(eth->dev, "alloc_etherdev failed\n");
2975 return -ENOMEM;
2976 }
2977 mac = netdev_priv(eth->netdev[id]);
2978 eth->mac[id] = mac;
2979 mac->id = id;
2980 mac->hw = eth;
2981 mac->of_node = np;
656e7052 2982
ee406810
NC		 2983 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2984 mac->hwlro_ip_cnt = 0;
2985
656e7052
JC		 2986 mac->hw_stats = devm_kzalloc(eth->dev,
2987 sizeof(*mac->hw_stats),
2988 GFP_KERNEL);
2989 if (!mac->hw_stats) {
2990 dev_err(eth->dev, "failed to allocate counter memory\n");
2991 err = -ENOMEM;
2992 goto free_netdev;
2993 }
2994 spin_lock_init(&mac->hw_stats->stats_lock);
d7005652 2995 u64_stats_init(&mac->hw_stats->syncp);
656e7052
JC		 2996 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2997
b8fc9f30 2998 /* phylink create */
0c65b2b9
AL		 2999 err = of_get_phy_mode(np, &phy_mode);
3000 if (err) {
b8fc9f30 3001 dev_err(eth->dev, "incorrect phy-mode\n");
b8fc9f30
RD		 3002 goto free_netdev;
3003 }
3004
3005 /* mac config is not set */
3006 mac->interface = PHY_INTERFACE_MODE_NA;
3007 mac->mode = MLO_AN_PHY;
3008 mac->speed = SPEED_UNKNOWN;
3009
3010 mac->phylink_config.dev = &eth->netdev[id]->dev;
3011 mac->phylink_config.type = PHYLINK_NETDEV;
3012
3013 phylink = phylink_create(&mac->phylink_config,
3014 of_fwnode_handle(mac->of_node),
3015 phy_mode, &mtk_phylink_ops);
3016 if (IS_ERR(phylink)) {
3017 err = PTR_ERR(phylink);
3018 goto free_netdev;
3019 }
3020
3021 mac->phylink = phylink;
3022
656e7052 3023 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
eaadf9fd 3024 eth->netdev[id]->watchdog_timeo = 5 * HZ;
656e7052
JC		 3025 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
3026 eth->netdev[id]->base_addr = (unsigned long)eth->base;
ee406810 3027
296c9120 3028 eth->netdev[id]->hw_features = eth->soc->hw_features;
ee406810
NC		 3029 if (eth->hwlro)
3030 eth->netdev[id]->hw_features |= NETIF_F_LRO;
3031
296c9120 3032 eth->netdev[id]->vlan_features = eth->soc->hw_features &
656e7052 3033 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
296c9120 3034 eth->netdev[id]->features |= eth->soc->hw_features;
656e7052
JC		 3035 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
3036
80673029 3037 eth->netdev[id]->irq = eth->irq[0];
3174b3b5
SW		 3038 eth->netdev[id]->dev.of_node = np;
3039
4fd59792
DQ		 3040 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3041 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
3042 else
3043 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
555a8933 3044
656e7052
JC		 3045 return 0;
3046
3047free_netdev:
3048 free_netdev(eth->netdev[id]);
3049 return err;
3050}
3051
3052static int mtk_probe(struct platform_device *pdev)
3053{
656e7052 3054 struct device_node *mac_np;
656e7052 3055 struct mtk_eth *eth;
b8fc9f30 3056 int err, i;
656e7052 3057
656e7052
JC		 3058 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
3059 if (!eth)
3060 return -ENOMEM;
3061
eda7d46d 3062 eth->soc = of_device_get_match_data(&pdev->dev);
2ec50f57 3063
549e5495 3064 eth->dev = &pdev->dev;
566495de 3065 eth->base = devm_platform_ioremap_resource(pdev, 0);
621e49f6
VZ		 3066 if (IS_ERR(eth->base))
3067 return PTR_ERR(eth->base);
656e7052 3068
296c9120
SR		 3069 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3070 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK;
3071 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS;
3072 } else {
3073 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK;
3074 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS;
3075 }
3076
3077 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3078 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA;
3079 eth->ip_align = NET_IP_ALIGN;
3080 } else {
3081 eth->rx_dma_l4_valid = RX_DMA_L4_VALID;
3082 }
3083
656e7052 3084 spin_lock_init(&eth->page_lock);
5cce0322
JC		 3085 spin_lock_init(&eth->tx_irq_lock);
3086 spin_lock_init(&eth->rx_irq_lock);
e9229ffd
FF		 3087 spin_lock_init(&eth->dim_lock);
3088
3089 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
3090 INIT_WORK(&eth->rx_dim.work, mtk_dim_rx);
3091
3092 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
3093 INIT_WORK(&eth->tx_dim.work, mtk_dim_tx);
656e7052 3094
296c9120
SR		 3095 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3096 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
3097 "mediatek,ethsys");
3098 if (IS_ERR(eth->ethsys)) {
3099 dev_err(&pdev->dev, "no ethsys regmap found\n");
3100 return PTR_ERR(eth->ethsys);
3101 }
656e7052
JC		 3102 }
3103
7093f9d8
SW		 3104 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
3105 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
3106 "mediatek,infracfg");
3107 if (IS_ERR(eth->infra)) {
3108 dev_err(&pdev->dev, "no infracfg regmap found\n");
3109 return PTR_ERR(eth->infra);
3110 }
3111 }
3112
42c03844 3113 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
9ffee4a8
SW		 3114 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
3115 GFP_KERNEL);
3116 if (!eth->sgmii)
3117 return -ENOMEM;
3118
3119 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
3120 eth->soc->ana_rgc3);
3121
3122 if (err)
3123 return err;
42c03844
SW		 3124 }
3125
243dc5fb
SW		 3126 if (eth->soc->required_pctl) {
3127 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
3128 "mediatek,pctl");
3129 if (IS_ERR(eth->pctl)) {
3130 dev_err(&pdev->dev, "no pctl regmap found\n");
3131 return PTR_ERR(eth->pctl);
3132 }
656e7052
JC		 3133 }
3134
80673029 3135 for (i = 0; i < 3; i++) {
889bcbde
BM		 3136 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
3137 eth->irq[i] = eth->irq[0];
3138 else
3139 eth->irq[i] = platform_get_irq(pdev, i);
80673029
JC		 3140 if (eth->irq[i] < 0) {
3141 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
3142 return -ENXIO;
3143 }
656e7052 3144 }
549e5495
SW		 3145 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
3146 eth->clks[i] = devm_clk_get(eth->dev,
3147 mtk_clks_source_name[i]);
3148 if (IS_ERR(eth->clks[i])) {
3149 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
3150 return -EPROBE_DEFER;
2ec50f57
SW		 3151 if (eth->soc->required_clks & BIT(i)) {
3152 dev_err(&pdev->dev, "clock %s not found\n",
3153 mtk_clks_source_name[i]);
3154 return -EINVAL;
3155 }
3156 eth->clks[i] = NULL;
549e5495
SW		 3157 }
3158 }
656e7052 3159
656e7052 3160 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
7c78b4ad 3161 INIT_WORK(&eth->pending_work, mtk_pending_work);
656e7052
JC		 3162
3163 err = mtk_hw_init(eth);
3164 if (err)
3165 return err;
3166
2d14ba72 3167 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
983e1a6c 3168
656e7052
JC		 3169 for_each_child_of_node(pdev->dev.of_node, mac_np) {
3170 if (!of_device_is_compatible(mac_np,
3171 "mediatek,eth-mac"))
3172 continue;
3173
3174 if (!of_device_is_available(mac_np))
3175 continue;
3176
3177 err = mtk_add_mac(eth, mac_np);
cf36dd2f
ND		 3178 if (err) {
3179 of_node_put(mac_np);
8a8a9e89 3180 goto err_deinit_hw;
cf36dd2f 3181 }
656e7052
JC		 3182 }
3183
889bcbde
BM		 3184 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
3185 err = devm_request_irq(eth->dev, eth->irq[0],
3186 mtk_handle_irq, 0,
3187 dev_name(eth->dev), eth);
3188 } else {
3189 err = devm_request_irq(eth->dev, eth->irq[1],
3190 mtk_handle_irq_tx, 0,
3191 dev_name(eth->dev), eth);
3192 if (err)
3193 goto err_free_dev;
85574dbf 3194
889bcbde
BM		 3195 err = devm_request_irq(eth->dev, eth->irq[2],
3196 mtk_handle_irq_rx, 0,
3197 dev_name(eth->dev), eth);
3198 }
85574dbf
SW		 3199 if (err)
3200 goto err_free_dev;
3201
296c9120
SR		 3202 /* No MT7628/88 support yet */
3203 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3204 err = mtk_mdio_init(eth);
3205 if (err)
3206 goto err_free_dev;
3207 }
85574dbf 3208
ba37b7ca
FF		 3209 if (eth->soc->offload_version) {
3210 err = mtk_ppe_init(&eth->ppe, eth->dev,
3211 eth->base + MTK_ETH_PPE_BASE, 2);
3212 if (err)
3213 goto err_free_dev;
502e84e2
FF		 3214
3215 err = mtk_eth_offload_init(eth);
3216 if (err)
3217 goto err_free_dev;
ba37b7ca
FF		 3218 }
3219
85574dbf
SW		 3220 for (i = 0; i < MTK_MAX_DEVS; i++) {
3221 if (!eth->netdev[i])
3222 continue;
3223
3224 err = register_netdev(eth->netdev[i]);
3225 if (err) {
3226 dev_err(eth->dev, "error bringing up device\n");
8a8a9e89 3227 goto err_deinit_mdio;
85574dbf
SW		 3228 } else
3229 netif_info(eth, probe, eth->netdev[i],
3230 "mediatek frame engine at 0x%08lx, irq %d\n",
3231 eth->netdev[i]->base_addr, eth->irq[0]);
3232 }
3233
656e7052
JC		 3234 /* we run 2 devices on the same DMA ring so we need a dummy device
3235 * for NAPI to work
3236 */
3237 init_dummy_netdev(&eth->dummy_dev);
80673029
JC		 3238 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
3239 MTK_NAPI_WEIGHT);
3240 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
656e7052
JC		 3241 MTK_NAPI_WEIGHT);
3242
3243 platform_set_drvdata(pdev, eth);
3244
3245 return 0;
3246
8a8a9e89
SW		 3247err_deinit_mdio:
3248 mtk_mdio_cleanup(eth);
656e7052 3249err_free_dev:
8a8a9e89
SW		 3250 mtk_free_dev(eth);
3251err_deinit_hw:
3252 mtk_hw_deinit(eth);
3253
656e7052
JC		 3254 return err;
3255}
3256
3257static int mtk_remove(struct platform_device *pdev)
3258{
3259 struct mtk_eth *eth = platform_get_drvdata(pdev);
b8fc9f30 3260 struct mtk_mac *mac;
79e9a414
SW		 3261 int i;
3262
3263 /* stop all devices to make sure that dma is properly shut down */
3264 for (i = 0; i < MTK_MAC_COUNT; i++) {
3265 if (!eth->netdev[i])
3266 continue;
3267 mtk_stop(eth->netdev[i]);
b8fc9f30
RD		 3268 mac = netdev_priv(eth->netdev[i]);
3269 phylink_disconnect_phy(mac->phylink);
79e9a414 3270 }
656e7052 3271
bf253fb7 3272 mtk_hw_deinit(eth);
656e7052 3273
80673029 3274 netif_napi_del(&eth->tx_napi);
656e7052
JC		 3275 netif_napi_del(&eth->rx_napi);
3276 mtk_cleanup(eth);
e82f7148 3277 mtk_mdio_cleanup(eth);
656e7052
JC		 3278
3279 return 0;
3280}
3281
2ec50f57 3282static const struct mtk_soc_data mt2701_data = {
7093f9d8 3283 .caps = MT7623_CAPS | MTK_HWLRO,
296c9120 3284 .hw_features = MTK_HW_FEATURES,
243dc5fb
SW		 3285 .required_clks = MT7623_CLKS_BITMAP,
3286 .required_pctl = true,
2ec50f57
SW		 3287};
3288
889bcbde 3289static const struct mtk_soc_data mt7621_data = {
8efaa653 3290 .caps = MT7621_CAPS,
296c9120 3291 .hw_features = MTK_HW_FEATURES,
889bcbde
BM		 3292 .required_clks = MT7621_CLKS_BITMAP,
3293 .required_pctl = false,
ba37b7ca 3294 .offload_version = 2,
889bcbde
BM		 3295};
3296
42c03844 3297static const struct mtk_soc_data mt7622_data = {
9ffee4a8 3298 .ana_rgc3 = 0x2028,
7093f9d8 3299 .caps = MT7622_CAPS | MTK_HWLRO,
296c9120 3300 .hw_features = MTK_HW_FEATURES,
243dc5fb
SW		 3301 .required_clks = MT7622_CLKS_BITMAP,
3302 .required_pctl = false,
ba37b7ca 3303 .offload_version = 2,
42c03844
SW		 3304};
3305
2ec50f57 3306static const struct mtk_soc_data mt7623_data = {
7093f9d8 3307 .caps = MT7623_CAPS | MTK_HWLRO,
296c9120 3308 .hw_features = MTK_HW_FEATURES,
243dc5fb
SW		 3309 .required_clks = MT7623_CLKS_BITMAP,
3310 .required_pctl = true,
917e2e6c 3311 .offload_version = 2,
2ec50f57
SW		 3312};
3313
d438e298
SW		 3314static const struct mtk_soc_data mt7629_data = {
3315 .ana_rgc3 = 0x128,
3316 .caps = MT7629_CAPS | MTK_HWLRO,
296c9120 3317 .hw_features = MTK_HW_FEATURES,
d438e298
SW		 3318 .required_clks = MT7629_CLKS_BITMAP,
3319 .required_pctl = false,
3320};
3321
296c9120
SR		 3322static const struct mtk_soc_data rt5350_data = {
3323 .caps = MT7628_CAPS,
3324 .hw_features = MTK_HW_FEATURES_MT7628,
3325 .required_clks = MT7628_CLKS_BITMAP,
3326 .required_pctl = false,
3327};
3328
656e7052 3329const struct of_device_id of_mtk_match[] = {
2ec50f57 3330 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
889bcbde 3331 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
42c03844 3332 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
2ec50f57 3333 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
d438e298 3334 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
296c9120 3335 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
656e7052
JC		 3336 {},
3337};
7077dc41 3338MODULE_DEVICE_TABLE(of, of_mtk_match);
656e7052
JC		 3339
3340static struct platform_driver mtk_driver = {
3341 .probe = mtk_probe,
3342 .remove = mtk_remove,
3343 .driver = {
3344 .name = "mtk_soc_eth",
656e7052
JC		 3345 .of_match_table = of_mtk_match,
3346 },
3347};
3348
3349module_platform_driver(mtk_driver);
3350
3351MODULE_LICENSE("GPL");
3352MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3353MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux 6.x block layer and io_uring tree(s)