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net/ncsi: remove duplicated include from ncsi-netlink.c
[linux-2.6-block.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
26a2ad8a 21#include <linux/pm_runtime.h>
656e7052
JC		 22#include <linux/if_vlan.h>
23#include <linux/reset.h>
24#include <linux/tcp.h>
70dba204 25#include <linux/interrupt.h>
140995c9 26#include <linux/pinctrl/devinfo.h>
656e7052
JC		 27
28#include "mtk_eth_soc.h"
29
30static int mtk_msg_level = -1;
31module_param_named(msg_level, mtk_msg_level, int, 0);
32MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
33
34#define MTK_ETHTOOL_STAT(x) { #x, \
35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
36
37/* strings used by ethtool */
38static const struct mtk_ethtool_stats {
39 char str[ETH_GSTRING_LEN];
40 u32 offset;
41} mtk_ethtool_stats[] = {
42 MTK_ETHTOOL_STAT(tx_bytes),
43 MTK_ETHTOOL_STAT(tx_packets),
44 MTK_ETHTOOL_STAT(tx_skip),
45 MTK_ETHTOOL_STAT(tx_collisions),
46 MTK_ETHTOOL_STAT(rx_bytes),
47 MTK_ETHTOOL_STAT(rx_packets),
48 MTK_ETHTOOL_STAT(rx_overflow),
49 MTK_ETHTOOL_STAT(rx_fcs_errors),
50 MTK_ETHTOOL_STAT(rx_short_errors),
51 MTK_ETHTOOL_STAT(rx_long_errors),
52 MTK_ETHTOOL_STAT(rx_checksum_errors),
53 MTK_ETHTOOL_STAT(rx_flow_control_packets),
54};
55
549e5495 56static const char * const mtk_clks_source_name[] = {
42c03844
SW		 57 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m",
58 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll"
549e5495
SW		 59};
60
656e7052
JC		 61void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
62{
63 __raw_writel(val, eth->base + reg);
64}
65
66u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
67{
68 return __raw_readl(eth->base + reg);
69}
70
71static int mtk_mdio_busy_wait(struct mtk_eth *eth)
72{
73 unsigned long t_start = jiffies;
74
75 while (1) {
76 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
77 return 0;
78 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
79 break;
80 usleep_range(10, 20);
81 }
82
83 dev_err(eth->dev, "mdio: MDIO timeout\n");
84 return -1;
85}
86
379672de
WY		 87static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
88 u32 phy_register, u32 write_data)
656e7052
JC		 89{
90 if (mtk_mdio_busy_wait(eth))
91 return -1;
92
93 write_data &= 0xffff;
94
95 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
96 (phy_register << PHY_IAC_REG_SHIFT) |
97 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
98 MTK_PHY_IAC);
99
100 if (mtk_mdio_busy_wait(eth))
101 return -1;
102
103 return 0;
104}
105
379672de 106static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
656e7052
JC		 107{
108 u32 d;
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
114 (phy_reg << PHY_IAC_REG_SHIFT) |
115 (phy_addr << PHY_IAC_ADDR_SHIFT),
116 MTK_PHY_IAC);
117
118 if (mtk_mdio_busy_wait(eth))
119 return 0xffff;
120
121 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
122
123 return d;
124}
125
126static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
127 int phy_reg, u16 val)
128{
129 struct mtk_eth *eth = bus->priv;
130
131 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
132}
133
134static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
135{
136 struct mtk_eth *eth = bus->priv;
137
138 return _mtk_mdio_read(eth, phy_addr, phy_reg);
139}
140
f430dea7
SW		 141static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
142{
143 u32 val;
144 int ret;
145
146 val = (speed == SPEED_1000) ?
147 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
148 mtk_w32(eth, val, INTF_MODE);
149
150 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
151 ETHSYS_TRGMII_CLK_SEL362_5,
152 ETHSYS_TRGMII_CLK_SEL362_5);
153
154 val = (speed == SPEED_1000) ? 250000000 : 500000000;
155 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
156 if (ret)
157 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
158
159 val = (speed == SPEED_1000) ?
160 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
161 mtk_w32(eth, val, TRGMII_RCK_CTRL);
162
163 val = (speed == SPEED_1000) ?
164 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
165 mtk_w32(eth, val, TRGMII_TCK_CTRL);
166}
167
42c03844
SW		 168static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)
169{
170 u32 val;
171
172 /* Setup the link timer and QPHY power up inside SGMIISYS */
173 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER,
174 SGMII_LINK_TIMER_DEFAULT);
175
176 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val);
177 val |= SGMII_REMOTE_FAULT_DIS;
178 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val);
179
180 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val);
181 val |= SGMII_AN_RESTART;
182 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val);
183
184 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
185 val &= ~SGMII_PHYA_PWD;
186 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val);
187
188 /* Determine MUX for which GMAC uses the SGMII interface */
189 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) {
190 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
191 val &= ~SYSCFG0_SGMII_MASK;
192 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2;
193 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
194
195 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n",
196 mac_id);
197 }
198
199 /* Setup the GMAC1 going through SGMII path when SoC also support
200 * ESW on GMAC1
201 */
202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) &&
203 !mac_id) {
204 mtk_w32(eth, 0, MTK_MAC_MISC);
205 dev_info(eth->dev, "setup gmac1 going through sgmii");
206 }
207}
208
656e7052
JC		 209static void mtk_phy_link_adjust(struct net_device *dev)
210{
211 struct mtk_mac *mac = netdev_priv(dev);
08ef55c6
JC		 212 u16 lcl_adv = 0, rmt_adv = 0;
213 u8 flowctrl;
656e7052
JC		 214 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
215 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
216 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
217 MAC_MCR_BACKPR_EN;
218
dce6fa42
SW		 219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
220 return;
221
2364c5c5 222 switch (dev->phydev->speed) {
656e7052
JC		 223 case SPEED_1000:
224 mcr |= MAC_MCR_SPEED_1000;
225 break;
226 case SPEED_100:
227 mcr |= MAC_MCR_SPEED_100;
228 break;
229 };
230
2ec50f57
SW		 231 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
232 !mac->id && !mac->trgmii)
2364c5c5 233 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
f430dea7 234
2364c5c5 235 if (dev->phydev->link)
656e7052
JC		 236 mcr |= MAC_MCR_FORCE_LINK;
237
2364c5c5 238 if (dev->phydev->duplex) {
656e7052
JC		 239 mcr |= MAC_MCR_FORCE_DPX;
240
2364c5c5 241 if (dev->phydev->pause)
08ef55c6 242 rmt_adv = LPA_PAUSE_CAP;
2364c5c5 243 if (dev->phydev->asym_pause)
08ef55c6
JC		 244 rmt_adv |= LPA_PAUSE_ASYM;
245
2364c5c5 246 if (dev->phydev->advertising & ADVERTISED_Pause)
08ef55c6 247 lcl_adv |= ADVERTISE_PAUSE_CAP;
2364c5c5 248 if (dev->phydev->advertising & ADVERTISED_Asym_Pause)
08ef55c6
JC		 249 lcl_adv |= ADVERTISE_PAUSE_ASYM;
250
251 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
252
253 if (flowctrl & FLOW_CTRL_TX)
254 mcr |= MAC_MCR_FORCE_TX_FC;
255 if (flowctrl & FLOW_CTRL_RX)
256 mcr |= MAC_MCR_FORCE_RX_FC;
257
258 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
259 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
260 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
261 }
656e7052
JC		 262
263 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
264
2364c5c5 265 if (dev->phydev->link)
656e7052
JC		 266 netif_carrier_on(dev);
267 else
268 netif_carrier_off(dev);
5969c427
JC		 269
270 if (!of_phy_is_fixed_link(mac->of_node))
271 phy_print_status(dev->phydev);
656e7052
JC		 272}
273
274static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
275 struct device_node *phy_node)
276{
656e7052 277 struct phy_device *phydev;
a2b2a19f 278 int phy_mode;
656e7052 279
656e7052
JC		 280 phy_mode = of_get_phy_mode(phy_node);
281 if (phy_mode < 0) {
282 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
283 return -EINVAL;
284 }
285
286 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
287 mtk_phy_link_adjust, 0, phy_mode);
977bc20c 288 if (!phydev) {
656e7052 289 dev_err(eth->dev, "could not connect to PHY\n");
977bc20c 290 return -ENODEV;
656e7052
JC		 291 }
292
293 dev_info(eth->dev,
294 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
295 mac->id, phydev_name(phydev), phydev->phy_id,
296 phydev->drv->name);
297
656e7052
JC		 298 return 0;
299}
300
2364c5c5 301static int mtk_phy_connect(struct net_device *dev)
656e7052 302{
2364c5c5
SW		 303 struct mtk_mac *mac = netdev_priv(dev);
304 struct mtk_eth *eth;
656e7052 305 struct device_node *np;
9ea4d311 306 u32 val;
656e7052 307
2364c5c5 308 eth = mac->hw;
656e7052 309 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
0c72c50f
JC		 310 if (!np && of_phy_is_fixed_link(mac->of_node))
311 if (!of_phy_register_fixed_link(mac->of_node))
312 np = of_node_get(mac->of_node);
656e7052
JC		 313 if (!np)
314 return -ENODEV;
315
42c03844 316 mac->ge_mode = 0;
656e7052 317 switch (of_get_phy_mode(np)) {
572de608
SW		 318 case PHY_INTERFACE_MODE_TRGMII:
319 mac->trgmii = true;
37920fce
JC		 320 case PHY_INTERFACE_MODE_RGMII_TXID:
321 case PHY_INTERFACE_MODE_RGMII_RXID:
322 case PHY_INTERFACE_MODE_RGMII_ID:
656e7052 323 case PHY_INTERFACE_MODE_RGMII:
42c03844
SW		 324 break;
325 case PHY_INTERFACE_MODE_SGMII:
326 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII))
327 mtk_gmac_sgmii_hw_setup(eth, mac->id);
656e7052
JC		 328 break;
329 case PHY_INTERFACE_MODE_MII:
9ea4d311 330 mac->ge_mode = 1;
656e7052 331 break;
8ca7f4fe 332 case PHY_INTERFACE_MODE_REVMII:
9ea4d311 333 mac->ge_mode = 2;
656e7052 334 break;
8ca7f4fe 335 case PHY_INTERFACE_MODE_RMII:
336 if (!mac->id)
337 goto err_phy;
9ea4d311 338 mac->ge_mode = 3;
8ca7f4fe 339 break;
656e7052 340 default:
8ca7f4fe 341 goto err_phy;
656e7052
JC		 342 }
343
344 /* put the gmac into the right mode */
345 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
346 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
9ea4d311 347 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
656e7052
JC		 348 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
349
2364c5c5 350 /* couple phydev to net_device */
f6f7d9c0
SW		 351 if (mtk_phy_connect_node(eth, mac, np))
352 goto err_phy;
353
2364c5c5
SW		 354 dev->phydev->autoneg = AUTONEG_ENABLE;
355 dev->phydev->speed = 0;
356 dev->phydev->duplex = 0;
b2025c7c 357
358 if (of_phy_is_fixed_link(mac->of_node))
2364c5c5 359 dev->phydev->supported |=
b2025c7c 360 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
361
2364c5c5 362 dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
08ef55c6 363 SUPPORTED_Asym_Pause;
2364c5c5 364 dev->phydev->advertising = dev->phydev->supported |
656e7052 365 ADVERTISED_Autoneg;
2364c5c5 366 phy_start_aneg(dev->phydev);
656e7052 367
e8c2993a 368 of_node_put(np);
369
656e7052 370 return 0;
8ca7f4fe 371
372err_phy:
16a67eb3
JH		 373 if (of_phy_is_fixed_link(mac->of_node))
374 of_phy_deregister_fixed_link(mac->of_node);
8ca7f4fe 375 of_node_put(np);
f6f7d9c0 376 dev_err(eth->dev, "%s: invalid phy\n", __func__);
8ca7f4fe 377 return -EINVAL;
656e7052
JC		 378}
379
380static int mtk_mdio_init(struct mtk_eth *eth)
381{
382 struct device_node *mii_np;
1e515b7f 383 int ret;
656e7052
JC		 384
385 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
386 if (!mii_np) {
387 dev_err(eth->dev, "no %s child node found", "mdio-bus");
388 return -ENODEV;
389 }
390
391 if (!of_device_is_available(mii_np)) {
aa6e8a54 392 ret = -ENODEV;
656e7052
JC		 393 goto err_put_node;
394 }
395
1e515b7f 396 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
656e7052 397 if (!eth->mii_bus) {
1e515b7f 398 ret = -ENOMEM;
656e7052
JC		 399 goto err_put_node;
400 }
401
402 eth->mii_bus->name = "mdio";
403 eth->mii_bus->read = mtk_mdio_read;
404 eth->mii_bus->write = mtk_mdio_write;
405 eth->mii_bus->priv = eth;
406 eth->mii_bus->parent = eth->dev;
407
408 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
1e515b7f 409 ret = of_mdiobus_register(eth->mii_bus, mii_np);
656e7052
JC		 410
411err_put_node:
412 of_node_put(mii_np);
1e515b7f 413 return ret;
656e7052
JC		 414}
415
416static void mtk_mdio_cleanup(struct mtk_eth *eth)
417{
418 if (!eth->mii_bus)
419 return;
420
421 mdiobus_unregister(eth->mii_bus);
656e7052
JC		 422}
423
5cce0322 424static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
656e7052 425{
7bc9ccec 426 unsigned long flags;
656e7052
JC		 427 u32 val;
428
5cce0322
JC		 429 spin_lock_irqsave(&eth->tx_irq_lock, flags);
430 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
431 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
432 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
656e7052
JC		 433}
434
5cce0322 435static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
656e7052 436{
7bc9ccec 437 unsigned long flags;
656e7052
JC		 438 u32 val;
439
5cce0322
JC		 440 spin_lock_irqsave(&eth->tx_irq_lock, flags);
441 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
442 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
443 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
444}
445
446static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
447{
448 unsigned long flags;
449 u32 val;
450
451 spin_lock_irqsave(&eth->rx_irq_lock, flags);
452 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
453 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
454 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
455}
456
457static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
458{
459 unsigned long flags;
460 u32 val;
461
462 spin_lock_irqsave(&eth->rx_irq_lock, flags);
463 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
464 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
465 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
656e7052
JC		 466}
467
468static int mtk_set_mac_address(struct net_device *dev, void *p)
469{
470 int ret = eth_mac_addr(dev, p);
471 struct mtk_mac *mac = netdev_priv(dev);
472 const char *macaddr = dev->dev_addr;
656e7052
JC		 473
474 if (ret)
475 return ret;
476
dce6fa42
SW		 477 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
478 return -EBUSY;
479
e3e9652a 480 spin_lock_bh(&mac->hw->page_lock);
656e7052
JC		 481 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
482 MTK_GDMA_MAC_ADRH(mac->id));
483 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
484 (macaddr[4] << 8) | macaddr[5],
485 MTK_GDMA_MAC_ADRL(mac->id));
e3e9652a 486 spin_unlock_bh(&mac->hw->page_lock);
656e7052
JC		 487
488 return 0;
489}
490
491void mtk_stats_update_mac(struct mtk_mac *mac)
492{
493 struct mtk_hw_stats *hw_stats = mac->hw_stats;
494 unsigned int base = MTK_GDM1_TX_GBCNT;
495 u64 stats;
496
497 base += hw_stats->reg_offset;
498
499 u64_stats_update_begin(&hw_stats->syncp);
500
501 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
502 stats = mtk_r32(mac->hw, base + 0x04);
503 if (stats)
504 hw_stats->rx_bytes += (stats << 32);
505 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
506 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
507 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
508 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
509 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
510 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
511 hw_stats->rx_flow_control_packets +=
512 mtk_r32(mac->hw, base + 0x24);
513 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
514 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
515 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
516 stats = mtk_r32(mac->hw, base + 0x34);
517 if (stats)
518 hw_stats->tx_bytes += (stats << 32);
519 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
520 u64_stats_update_end(&hw_stats->syncp);
521}
522
523static void mtk_stats_update(struct mtk_eth *eth)
524{
525 int i;
526
527 for (i = 0; i < MTK_MAC_COUNT; i++) {
528 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
529 continue;
530 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
531 mtk_stats_update_mac(eth->mac[i]);
532 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
533 }
534 }
535}
536
bc1f4470 537static void mtk_get_stats64(struct net_device *dev,
538 struct rtnl_link_stats64 *storage)
656e7052
JC		 539{
540 struct mtk_mac *mac = netdev_priv(dev);
541 struct mtk_hw_stats *hw_stats = mac->hw_stats;
542 unsigned int start;
543
544 if (netif_running(dev) && netif_device_present(dev)) {
8d32e062 545 if (spin_trylock_bh(&hw_stats->stats_lock)) {
656e7052 546 mtk_stats_update_mac(mac);
8d32e062 547 spin_unlock_bh(&hw_stats->stats_lock);
656e7052
JC		 548 }
549 }
550
551 do {
552 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
553 storage->rx_packets = hw_stats->rx_packets;
554 storage->tx_packets = hw_stats->tx_packets;
555 storage->rx_bytes = hw_stats->rx_bytes;
556 storage->tx_bytes = hw_stats->tx_bytes;
557 storage->collisions = hw_stats->tx_collisions;
558 storage->rx_length_errors = hw_stats->rx_short_errors +
559 hw_stats->rx_long_errors;
560 storage->rx_over_errors = hw_stats->rx_overflow;
561 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
562 storage->rx_errors = hw_stats->rx_checksum_errors;
563 storage->tx_aborted_errors = hw_stats->tx_skip;
564 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
565
566 storage->tx_errors = dev->stats.tx_errors;
567 storage->rx_dropped = dev->stats.rx_dropped;
568 storage->tx_dropped = dev->stats.tx_dropped;
656e7052
JC		 569}
570
571static inline int mtk_max_frag_size(int mtu)
572{
573 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
574 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
575 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
576
577 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
578 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
579}
580
581static inline int mtk_max_buf_size(int frag_size)
582{
583 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
584 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
585
586 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
587
588 return buf_size;
589}
590
591static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
592 struct mtk_rx_dma *dma_rxd)
593{
594 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
595 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
596 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
597 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
598}
599
600/* the qdma core needs scratch memory to be setup */
601static int mtk_init_fq_dma(struct mtk_eth *eth)
602{
605e4fe4 603 dma_addr_t phy_ring_tail;
656e7052
JC		 604 int cnt = MTK_DMA_SIZE;
605 dma_addr_t dma_addr;
606 int i;
607
6c21da20
SW		 608 eth->scratch_ring = dma_zalloc_coherent(eth->dev,
609 cnt * sizeof(struct mtk_tx_dma),
610 &eth->phy_scratch_ring,
611 GFP_ATOMIC);
656e7052
JC		 612 if (unlikely(!eth->scratch_ring))
613 return -ENOMEM;
614
615 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
616 GFP_KERNEL);
562c5a70
JC		 617 if (unlikely(!eth->scratch_head))
618 return -ENOMEM;
619
656e7052
JC		 620 dma_addr = dma_map_single(eth->dev,
621 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
622 DMA_FROM_DEVICE);
623 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
624 return -ENOMEM;
625
605e4fe4 626 phy_ring_tail = eth->phy_scratch_ring +
656e7052
JC		 627 (sizeof(struct mtk_tx_dma) * (cnt - 1));
628
629 for (i = 0; i < cnt; i++) {
630 eth->scratch_ring[i].txd1 =
631 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
632 if (i < cnt - 1)
605e4fe4 633 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
656e7052
JC		 634 ((i + 1) * sizeof(struct mtk_tx_dma)));
635 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
636 }
637
605e4fe4 638 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
656e7052
JC		 639 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
640 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
641 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
642
643 return 0;
644}
645
646static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
647{
648 void *ret = ring->dma;
649
650 return ret + (desc - ring->phys);
651}
652
653static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
654 struct mtk_tx_dma *txd)
655{
656 int idx = txd - ring->dma;
657
658 return &ring->buf[idx];
659}
660
55a4e778 661static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
656e7052
JC		 662{
663 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
55a4e778 664 dma_unmap_single(eth->dev,
656e7052
JC		 665 dma_unmap_addr(tx_buf, dma_addr0),
666 dma_unmap_len(tx_buf, dma_len0),
667 DMA_TO_DEVICE);
668 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
55a4e778 669 dma_unmap_page(eth->dev,
656e7052
JC		 670 dma_unmap_addr(tx_buf, dma_addr0),
671 dma_unmap_len(tx_buf, dma_len0),
672 DMA_TO_DEVICE);
673 }
674 tx_buf->flags = 0;
675 if (tx_buf->skb &&
676 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
677 dev_kfree_skb_any(tx_buf->skb);
678 tx_buf->skb = NULL;
679}
680
681static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
682 int tx_num, struct mtk_tx_ring *ring, bool gso)
683{
684 struct mtk_mac *mac = netdev_priv(dev);
685 struct mtk_eth *eth = mac->hw;
686 struct mtk_tx_dma *itxd, *txd;
81d2dd09 687 struct mtk_tx_buf *itx_buf, *tx_buf;
656e7052
JC		 688 dma_addr_t mapped_addr;
689 unsigned int nr_frags;
690 int i, n_desc = 1;
c6f1dc4d 691 u32 txd4 = 0, fport;
656e7052
JC		 692
693 itxd = ring->next_free;
694 if (itxd == ring->last_free)
695 return -ENOMEM;
696
697 /* set the forward port */
c6f1dc4d
SW		 698 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
699 txd4 |= fport;
656e7052 700
81d2dd09
SW		 701 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
702 memset(itx_buf, 0, sizeof(*itx_buf));
656e7052
JC		 703
704 if (gso)
705 txd4 |= TX_DMA_TSO;
706
707 /* TX Checksum offload */
708 if (skb->ip_summed == CHECKSUM_PARTIAL)
709 txd4 |= TX_DMA_CHKSUM;
710
711 /* VLAN header offload */
712 if (skb_vlan_tag_present(skb))
713 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
714
55a4e778 715 mapped_addr = dma_map_single(eth->dev, skb->data,
656e7052 716 skb_headlen(skb), DMA_TO_DEVICE);
55a4e778 717 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 718 return -ENOMEM;
719
656e7052 720 WRITE_ONCE(itxd->txd1, mapped_addr);
81d2dd09 721 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
134d2152
SW		 722 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
723 MTK_TX_FLAGS_FPORT1;
81d2dd09
SW		 724 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr);
725 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb));
656e7052
JC		 726
727 /* TX SG offload */
728 txd = itxd;
729 nr_frags = skb_shinfo(skb)->nr_frags;
730 for (i = 0; i < nr_frags; i++) {
731 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
732 unsigned int offset = 0;
733 int frag_size = skb_frag_size(frag);
734
735 while (frag_size) {
736 bool last_frag = false;
737 unsigned int frag_map_size;
738
739 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
740 if (txd == ring->last_free)
741 goto err_dma;
742
743 n_desc++;
744 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
55a4e778 745 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
656e7052
JC		 746 frag_map_size,
747 DMA_TO_DEVICE);
55a4e778 748 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 749 goto err_dma;
750
751 if (i == nr_frags - 1 &&
752 (frag_size - frag_map_size) == 0)
753 last_frag = true;
754
755 WRITE_ONCE(txd->txd1, mapped_addr);
756 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
757 TX_DMA_PLEN0(frag_map_size) |
369f0453 758 last_frag * TX_DMA_LS0));
c6f1dc4d 759 WRITE_ONCE(txd->txd4, fport);
656e7052 760
656e7052
JC		 761 tx_buf = mtk_desc_to_tx_buf(ring, txd);
762 memset(tx_buf, 0, sizeof(*tx_buf));
81d2dd09 763 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
656e7052 764 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
134d2152
SW		 765 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
766 MTK_TX_FLAGS_FPORT1;
767
656e7052
JC		 768 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
769 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
770 frag_size -= frag_map_size;
771 offset += frag_map_size;
772 }
773 }
774
775 /* store skb to cleanup */
81d2dd09 776 itx_buf->skb = skb;
656e7052
JC		 777
778 WRITE_ONCE(itxd->txd4, txd4);
779 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
780 (!nr_frags * TX_DMA_LS0)));
781
656e7052
JC		 782 netdev_sent_queue(dev, skb->len);
783 skb_tx_timestamp(skb);
784
785 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
786 atomic_sub(n_desc, &ring->free_count);
787
788 /* make sure that all changes to the dma ring are flushed before we
789 * continue
790 */
791 wmb();
792
793 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
794 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
795
796 return 0;
797
798err_dma:
799 do {
2fae723c 800 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
656e7052
JC		 801
802 /* unmap dma */
55a4e778 803 mtk_tx_unmap(eth, tx_buf);
656e7052
JC		 804
805 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
806 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
807 } while (itxd != txd);
808
809 return -ENOMEM;
810}
811
812static inline int mtk_cal_txd_req(struct sk_buff *skb)
813{
814 int i, nfrags;
815 struct skb_frag_struct *frag;
816
817 nfrags = 1;
818 if (skb_is_gso(skb)) {
819 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
820 frag = &skb_shinfo(skb)->frags[i];
821 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
822 }
823 } else {
824 nfrags += skb_shinfo(skb)->nr_frags;
825 }
826
beeb4ca4 827 return nfrags;
656e7052
JC		 828}
829
ad3cba98
JC		 830static int mtk_queue_stopped(struct mtk_eth *eth)
831{
832 int i;
833
834 for (i = 0; i < MTK_MAC_COUNT; i++) {
835 if (!eth->netdev[i])
836 continue;
837 if (netif_queue_stopped(eth->netdev[i]))
838 return 1;
839 }
840
841 return 0;
842}
843
13c822f6
JC		 844static void mtk_wake_queue(struct mtk_eth *eth)
845{
846 int i;
847
848 for (i = 0; i < MTK_MAC_COUNT; i++) {
849 if (!eth->netdev[i])
850 continue;
851 netif_wake_queue(eth->netdev[i]);
852 }
853}
854
855static void mtk_stop_queue(struct mtk_eth *eth)
856{
857 int i;
858
859 for (i = 0; i < MTK_MAC_COUNT; i++) {
860 if (!eth->netdev[i])
861 continue;
862 netif_stop_queue(eth->netdev[i]);
863 }
864}
865
656e7052
JC		 866static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
867{
868 struct mtk_mac *mac = netdev_priv(dev);
869 struct mtk_eth *eth = mac->hw;
870 struct mtk_tx_ring *ring = &eth->tx_ring;
871 struct net_device_stats *stats = &dev->stats;
872 bool gso = false;
873 int tx_num;
874
34c2e4c9
JC		 875 /* normally we can rely on the stack not calling this more than once,
876 * however we have 2 queues running on the same ring so we need to lock
877 * the ring access
878 */
e3e9652a 879 spin_lock(&eth->page_lock);
34c2e4c9 880
dce6fa42
SW		 881 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
882 goto drop;
883
656e7052
JC		 884 tx_num = mtk_cal_txd_req(skb);
885 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
13c822f6 886 mtk_stop_queue(eth);
656e7052
JC		 887 netif_err(eth, tx_queued, dev,
888 "Tx Ring full when queue awake!\n");
e3e9652a 889 spin_unlock(&eth->page_lock);
656e7052
JC		 890 return NETDEV_TX_BUSY;
891 }
892
893 /* TSO: fill MSS info in tcp checksum field */
894 if (skb_is_gso(skb)) {
895 if (skb_cow_head(skb, 0)) {
896 netif_warn(eth, tx_err, dev,
897 "GSO expand head fail.\n");
898 goto drop;
899 }
900
901 if (skb_shinfo(skb)->gso_type &
902 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
903 gso = true;
904 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
905 }
906 }
907
908 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
909 goto drop;
910
82c6544d 911 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
13c822f6 912 mtk_stop_queue(eth);
82c6544d 913
e3e9652a 914 spin_unlock(&eth->page_lock);
656e7052
JC		 915
916 return NETDEV_TX_OK;
917
918drop:
e3e9652a 919 spin_unlock(&eth->page_lock);
656e7052 920 stats->tx_dropped++;
81ad2b7d 921 dev_kfree_skb_any(skb);
656e7052
JC		 922 return NETDEV_TX_OK;
923}
924
ee406810
NC		 925static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
926{
927 int i;
928 struct mtk_rx_ring *ring;
929 int idx;
930
931 if (!eth->hwlro)
932 return &eth->rx_ring[0];
933
934 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
935 ring = &eth->rx_ring[i];
936 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
937 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
938 ring->calc_idx_update = true;
939 return ring;
940 }
941 }
942
943 return NULL;
944}
945
946static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
947{
948 struct mtk_rx_ring *ring;
949 int i;
950
951 if (!eth->hwlro) {
952 ring = &eth->rx_ring[0];
953 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
954 } else {
955 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
956 ring = &eth->rx_ring[i];
957 if (ring->calc_idx_update) {
958 ring->calc_idx_update = false;
959 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
960 }
961 }
962 }
963}
964
656e7052 965static int mtk_poll_rx(struct napi_struct *napi, int budget,
eece71e8 966 struct mtk_eth *eth)
656e7052 967{
ee406810
NC		 968 struct mtk_rx_ring *ring;
969 int idx;
656e7052
JC		 970 struct sk_buff *skb;
971 u8 *data, *new_data;
972 struct mtk_rx_dma *rxd, trxd;
973 int done = 0;
974
975 while (done < budget) {
976 struct net_device *netdev;
977 unsigned int pktlen;
978 dma_addr_t dma_addr;
979 int mac = 0;
980
ee406810
NC		 981 ring = mtk_get_rx_ring(eth);
982 if (unlikely(!ring))
983 goto rx_done;
984
985 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
656e7052
JC		 986 rxd = &ring->dma[idx];
987 data = ring->data[idx];
988
989 mtk_rx_get_desc(&trxd, rxd);
990 if (!(trxd.rxd2 & RX_DMA_DONE))
991 break;
992
993 /* find out which mac the packet come from. values start at 1 */
994 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
995 RX_DMA_FPORT_MASK;
996 mac--;
997
6c7fce6f
SW		 998 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
999 !eth->netdev[mac]))
1000 goto release_desc;
1001
656e7052
JC		 1002 netdev = eth->netdev[mac];
1003
dce6fa42
SW		 1004 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
1005 goto release_desc;
1006
656e7052
JC		 1007 /* alloc new buffer */
1008 new_data = napi_alloc_frag(ring->frag_size);
1009 if (unlikely(!new_data)) {
1010 netdev->stats.rx_dropped++;
1011 goto release_desc;
1012 }
55a4e778 1013 dma_addr = dma_map_single(eth->dev,
656e7052
JC		 1014 new_data + NET_SKB_PAD,
1015 ring->buf_size,
1016 DMA_FROM_DEVICE);
55a4e778 1017 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
656e7052 1018 skb_free_frag(new_data);
94321a9f 1019 netdev->stats.rx_dropped++;
656e7052
JC		 1020 goto release_desc;
1021 }
1022
1023 /* receive data */
1024 skb = build_skb(data, ring->frag_size);
1025 if (unlikely(!skb)) {
1b430799 1026 skb_free_frag(new_data);
94321a9f 1027 netdev->stats.rx_dropped++;
656e7052
JC		 1028 goto release_desc;
1029 }
1030 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1031
55a4e778 1032 dma_unmap_single(eth->dev, trxd.rxd1,
656e7052
JC		 1033 ring->buf_size, DMA_FROM_DEVICE);
1034 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1035 skb->dev = netdev;
1036 skb_put(skb, pktlen);
1037 if (trxd.rxd4 & RX_DMA_L4_VALID)
1038 skb->ip_summed = CHECKSUM_UNNECESSARY;
1039 else
1040 skb_checksum_none_assert(skb);
1041 skb->protocol = eth_type_trans(skb, netdev);
1042
1043 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1044 RX_DMA_VID(trxd.rxd3))
1045 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1046 RX_DMA_VID(trxd.rxd3));
a2d5e7b4 1047 skb_record_rx_queue(skb, 0);
656e7052
JC		 1048 napi_gro_receive(napi, skb);
1049
1050 ring->data[idx] = new_data;
1051 rxd->rxd1 = (unsigned int)dma_addr;
1052
1053release_desc:
1054 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
1055
1056 ring->calc_idx = idx;
635372ad 1057
656e7052
JC		 1058 done++;
1059 }
1060
ee406810 1061rx_done:
41156cea
SW		 1062 if (done) {
1063 /* make sure that all changes to the dma ring are flushed before
1064 * we continue
1065 */
1066 wmb();
ee406810 1067 mtk_update_rx_cpu_idx(eth);
41156cea 1068 }
656e7052
JC		 1069
1070 return done;
1071}
1072
80673029 1073static int mtk_poll_tx(struct mtk_eth *eth, int budget)
656e7052
JC		 1074{
1075 struct mtk_tx_ring *ring = &eth->tx_ring;
1076 struct mtk_tx_dma *desc;
1077 struct sk_buff *skb;
1078 struct mtk_tx_buf *tx_buf;
80673029 1079 unsigned int done[MTK_MAX_DEVS];
656e7052
JC		 1080 unsigned int bytes[MTK_MAX_DEVS];
1081 u32 cpu, dma;
80673029 1082 int total = 0, i;
656e7052
JC		 1083
1084 memset(done, 0, sizeof(done));
1085 memset(bytes, 0, sizeof(bytes));
1086
1087 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1088 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1089
1090 desc = mtk_qdma_phys_to_virt(ring, cpu);
1091
1092 while ((cpu != dma) && budget) {
1093 u32 next_cpu = desc->txd2;
134d2152 1094 int mac = 0;
656e7052
JC		 1095
1096 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1097 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1098 break;
1099
656e7052 1100 tx_buf = mtk_desc_to_tx_buf(ring, desc);
134d2152
SW		 1101 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1102 mac = 1;
1103
656e7052 1104 skb = tx_buf->skb;
f03b06f3 1105 if (!skb)
656e7052 1106 break;
656e7052
JC		 1107
1108 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1109 bytes[mac] += skb->len;
1110 done[mac]++;
1111 budget--;
1112 }
55a4e778 1113 mtk_tx_unmap(eth, tx_buf);
656e7052 1114
656e7052
JC		 1115 ring->last_free = desc;
1116 atomic_inc(&ring->free_count);
1117
1118 cpu = next_cpu;
1119 }
1120
1121 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1122
1123 for (i = 0; i < MTK_MAC_COUNT; i++) {
1124 if (!eth->netdev[i] || !done[i])
1125 continue;
1126 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1127 total += done[i];
1128 }
1129
ad3cba98
JC		 1130 if (mtk_queue_stopped(eth) &&
1131 (atomic_read(&ring->free_count) > ring->thresh))
13c822f6 1132 mtk_wake_queue(eth);
656e7052
JC		 1133
1134 return total;
1135}
1136
80673029 1137static void mtk_handle_status_irq(struct mtk_eth *eth)
656e7052 1138{
80673029 1139 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
656e7052 1140
eece71e8 1141 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
656e7052 1142 mtk_stats_update(eth);
eece71e8
JC		 1143 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1144 MTK_INT_STATUS2);
656e7052 1145 }
80673029
JC		 1146}
1147
1148static int mtk_napi_tx(struct napi_struct *napi, int budget)
1149{
1150 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1151 u32 status, mask;
1152 int tx_done = 0;
1153
1154 mtk_handle_status_irq(eth);
1155 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1156 tx_done = mtk_poll_tx(eth, budget);
1157
1158 if (unlikely(netif_msg_intr(eth))) {
1159 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1160 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1161 dev_info(eth->dev,
1162 "done tx %d, intr 0x%08x/0x%x\n",
1163 tx_done, status, mask);
1164 }
1165
1166 if (tx_done == budget)
1167 return budget;
1168
1169 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1170 if (status & MTK_TX_DONE_INT)
1171 return budget;
1172
1173 napi_complete(napi);
5cce0322 1174 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
80673029
JC		 1175
1176 return tx_done;
1177}
1178
1179static int mtk_napi_rx(struct napi_struct *napi, int budget)
1180{
1181 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1182 u32 status, mask;
1183 int rx_done = 0;
41156cea 1184 int remain_budget = budget;
80673029
JC		 1185
1186 mtk_handle_status_irq(eth);
41156cea
SW		 1187
1188poll_again:
bacfd110 1189 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
41156cea 1190 rx_done = mtk_poll_rx(napi, remain_budget, eth);
656e7052
JC		 1191
1192 if (unlikely(netif_msg_intr(eth))) {
bacfd110
NC		 1193 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1194 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
80673029
JC		 1195 dev_info(eth->dev,
1196 "done rx %d, intr 0x%08x/0x%x\n",
1197 rx_done, status, mask);
656e7052 1198 }
41156cea 1199 if (rx_done == remain_budget)
656e7052
JC		 1200 return budget;
1201
bacfd110 1202 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
41156cea
SW		 1203 if (status & MTK_RX_DONE_INT) {
1204 remain_budget -= rx_done;
1205 goto poll_again;
1206 }
656e7052 1207 napi_complete(napi);
5cce0322 1208 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
656e7052 1209
41156cea 1210 return rx_done + budget - remain_budget;
656e7052
JC		 1211}
1212
1213static int mtk_tx_alloc(struct mtk_eth *eth)
1214{
1215 struct mtk_tx_ring *ring = &eth->tx_ring;
1216 int i, sz = sizeof(*ring->dma);
1217
1218 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1219 GFP_KERNEL);
1220 if (!ring->buf)
1221 goto no_tx_mem;
1222
0a78c380
Y		 1223 ring->dma = dma_zalloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1224 &ring->phys, GFP_ATOMIC);
656e7052
JC		 1225 if (!ring->dma)
1226 goto no_tx_mem;
1227
656e7052
JC		 1228 for (i = 0; i < MTK_DMA_SIZE; i++) {
1229 int next = (i + 1) % MTK_DMA_SIZE;
1230 u32 next_ptr = ring->phys + next * sz;
1231
1232 ring->dma[i].txd2 = next_ptr;
1233 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1234 }
1235
1236 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1237 ring->next_free = &ring->dma[0];
12c97c13 1238 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
04698ccc 1239 ring->thresh = MAX_SKB_FRAGS;
656e7052
JC		 1240
1241 /* make sure that all changes to the dma ring are flushed before we
1242 * continue
1243 */
1244 wmb();
1245
1246 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1247 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1248 mtk_w32(eth,
1249 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1250 MTK_QTX_CRX_PTR);
1251 mtk_w32(eth,
1252 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1253 MTK_QTX_DRX_PTR);
bacfd110 1254 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
656e7052
JC		 1255
1256 return 0;
1257
1258no_tx_mem:
1259 return -ENOMEM;
1260}
1261
1262static void mtk_tx_clean(struct mtk_eth *eth)
1263{
1264 struct mtk_tx_ring *ring = &eth->tx_ring;
1265 int i;
1266
1267 if (ring->buf) {
1268 for (i = 0; i < MTK_DMA_SIZE; i++)
55a4e778 1269 mtk_tx_unmap(eth, &ring->buf[i]);
656e7052
JC		 1270 kfree(ring->buf);
1271 ring->buf = NULL;
1272 }
1273
1274 if (ring->dma) {
1275 dma_free_coherent(eth->dev,
1276 MTK_DMA_SIZE * sizeof(*ring->dma),
1277 ring->dma,
1278 ring->phys);
1279 ring->dma = NULL;
1280 }
1281}
1282
ee406810 1283static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
656e7052 1284{
6427dc1d 1285 struct mtk_rx_ring *ring;
ee406810 1286 int rx_data_len, rx_dma_size;
656e7052 1287 int i;
6427dc1d
JC		 1288 u32 offset = 0;
1289
1290 if (rx_flag == MTK_RX_FLAGS_QDMA) {
1291 if (ring_no)
1292 return -EINVAL;
1293 ring = &eth->rx_ring_qdma;
1294 offset = 0x1000;
1295 } else {
1296 ring = &eth->rx_ring[ring_no];
1297 }
656e7052 1298
ee406810
NC		 1299 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1300 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1301 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1302 } else {
1303 rx_data_len = ETH_DATA_LEN;
1304 rx_dma_size = MTK_DMA_SIZE;
1305 }
1306
1307 ring->frag_size = mtk_max_frag_size(rx_data_len);
656e7052 1308 ring->buf_size = mtk_max_buf_size(ring->frag_size);
ee406810 1309 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
656e7052
JC		 1310 GFP_KERNEL);
1311 if (!ring->data)
1312 return -ENOMEM;
1313
ee406810 1314 for (i = 0; i < rx_dma_size; i++) {
656e7052
JC		 1315 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1316 if (!ring->data[i])
1317 return -ENOMEM;
1318 }
1319
6c21da20
SW		 1320 ring->dma = dma_zalloc_coherent(eth->dev,
1321 rx_dma_size * sizeof(*ring->dma),
1322 &ring->phys, GFP_ATOMIC);
656e7052
JC		 1323 if (!ring->dma)
1324 return -ENOMEM;
1325
ee406810 1326 for (i = 0; i < rx_dma_size; i++) {
656e7052
JC		 1327 dma_addr_t dma_addr = dma_map_single(eth->dev,
1328 ring->data[i] + NET_SKB_PAD,
1329 ring->buf_size,
1330 DMA_FROM_DEVICE);
1331 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1332 return -ENOMEM;
1333 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1334
1335 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1336 }
ee406810
NC		 1337 ring->dma_size = rx_dma_size;
1338 ring->calc_idx_update = false;
1339 ring->calc_idx = rx_dma_size - 1;
1340 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
656e7052
JC		 1341 /* make sure that all changes to the dma ring are flushed before we
1342 * continue
1343 */
1344 wmb();
1345
6427dc1d
JC		 1346 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1347 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1348 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1349 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
656e7052
JC		 1350
1351 return 0;
1352}
1353
6427dc1d 1354static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
656e7052 1355{
656e7052
JC		 1356 int i;
1357
1358 if (ring->data && ring->dma) {
ee406810 1359 for (i = 0; i < ring->dma_size; i++) {
656e7052
JC		 1360 if (!ring->data[i])
1361 continue;
1362 if (!ring->dma[i].rxd1)
1363 continue;
1364 dma_unmap_single(eth->dev,
1365 ring->dma[i].rxd1,
1366 ring->buf_size,
1367 DMA_FROM_DEVICE);
1368 skb_free_frag(ring->data[i]);
1369 }
1370 kfree(ring->data);
1371 ring->data = NULL;
1372 }
1373
1374 if (ring->dma) {
1375 dma_free_coherent(eth->dev,
ee406810 1376 ring->dma_size * sizeof(*ring->dma),
656e7052
JC		 1377 ring->dma,
1378 ring->phys);
1379 ring->dma = NULL;
1380 }
1381}
1382
ee406810
NC		 1383static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1384{
1385 int i;
1386 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1387 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1388
1389 /* set LRO rings to auto-learn modes */
1390 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1391
1392 /* validate LRO ring */
1393 ring_ctrl_dw2 |= MTK_RING_VLD;
1394
1395 /* set AGE timer (unit: 20us) */
1396 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1397 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1398
1399 /* set max AGG timer (unit: 20us) */
1400 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1401
1402 /* set max LRO AGG count */
1403 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1404 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1405
1406 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1407 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1408 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1409 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1410 }
1411
1412 /* IPv4 checksum update enable */
1413 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1414
1415 /* switch priority comparison to packet count mode */
1416 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1417
1418 /* bandwidth threshold setting */
1419 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1420
1421 /* auto-learn score delta setting */
1422 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1423
1424 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1425 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1426 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1427
1428 /* set HW LRO mode & the max aggregation count for rx packets */
1429 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1430
1431 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1432 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1433
1434 /* enable HW LRO */
1435 lro_ctrl_dw0 |= MTK_LRO_EN;
1436
1437 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1438 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1439
1440 return 0;
1441}
1442
1443static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1444{
1445 int i;
1446 u32 val;
1447
1448 /* relinquish lro rings, flush aggregated packets */
1449 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1450
1451 /* wait for relinquishments done */
1452 for (i = 0; i < 10; i++) {
1453 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1454 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1455 msleep(20);
1456 continue;
1457 }
ca3ba106 1458 break;
ee406810
NC		 1459 }
1460
1461 /* invalidate lro rings */
1462 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1463 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1464
1465 /* disable HW LRO */
1466 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1467}
1468
7aab747e
NC		 1469static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1470{
1471 u32 reg_val;
1472
1473 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1474
1475 /* invalidate the IP setting */
1476 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1477
1478 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1479
1480 /* validate the IP setting */
1481 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1482}
1483
1484static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1485{
1486 u32 reg_val;
1487
1488 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1489
1490 /* invalidate the IP setting */
1491 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1492
1493 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1494}
1495
1496static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1497{
1498 int cnt = 0;
1499 int i;
1500
1501 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1502 if (mac->hwlro_ip[i])
1503 cnt++;
1504 }
1505
1506 return cnt;
1507}
1508
1509static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1510 struct ethtool_rxnfc *cmd)
1511{
1512 struct ethtool_rx_flow_spec *fsp =
1513 (struct ethtool_rx_flow_spec *)&cmd->fs;
1514 struct mtk_mac *mac = netdev_priv(dev);
1515 struct mtk_eth *eth = mac->hw;
1516 int hwlro_idx;
1517
1518 if ((fsp->flow_type != TCP_V4_FLOW) ||
1519 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1520 (fsp->location > 1))
1521 return -EINVAL;
1522
1523 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1524 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1525
1526 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1527
1528 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1529
1530 return 0;
1531}
1532
1533static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1534 struct ethtool_rxnfc *cmd)
1535{
1536 struct ethtool_rx_flow_spec *fsp =
1537 (struct ethtool_rx_flow_spec *)&cmd->fs;
1538 struct mtk_mac *mac = netdev_priv(dev);
1539 struct mtk_eth *eth = mac->hw;
1540 int hwlro_idx;
1541
1542 if (fsp->location > 1)
1543 return -EINVAL;
1544
1545 mac->hwlro_ip[fsp->location] = 0;
1546 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1547
1548 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1549
1550 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1551
1552 return 0;
1553}
1554
1555static void mtk_hwlro_netdev_disable(struct net_device *dev)
1556{
1557 struct mtk_mac *mac = netdev_priv(dev);
1558 struct mtk_eth *eth = mac->hw;
1559 int i, hwlro_idx;
1560
1561 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1562 mac->hwlro_ip[i] = 0;
1563 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1564
1565 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1566 }
1567
1568 mac->hwlro_ip_cnt = 0;
1569}
1570
1571static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1572 struct ethtool_rxnfc *cmd)
1573{
1574 struct mtk_mac *mac = netdev_priv(dev);
1575 struct ethtool_rx_flow_spec *fsp =
1576 (struct ethtool_rx_flow_spec *)&cmd->fs;
1577
1578 /* only tcp dst ipv4 is meaningful, others are meaningless */
1579 fsp->flow_type = TCP_V4_FLOW;
1580 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1581 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1582
1583 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1584 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1585 fsp->h_u.tcp_ip4_spec.psrc = 0;
1586 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1587 fsp->h_u.tcp_ip4_spec.pdst = 0;
1588 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1589 fsp->h_u.tcp_ip4_spec.tos = 0;
1590 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1591
1592 return 0;
1593}
1594
1595static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1596 struct ethtool_rxnfc *cmd,
1597 u32 *rule_locs)
1598{
1599 struct mtk_mac *mac = netdev_priv(dev);
1600 int cnt = 0;
1601 int i;
1602
1603 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1604 if (mac->hwlro_ip[i]) {
1605 rule_locs[cnt] = i;
1606 cnt++;
1607 }
1608 }
1609
1610 cmd->rule_cnt = cnt;
1611
1612 return 0;
1613}
1614
1615static netdev_features_t mtk_fix_features(struct net_device *dev,
1616 netdev_features_t features)
1617{
1618 if (!(features & NETIF_F_LRO)) {
1619 struct mtk_mac *mac = netdev_priv(dev);
1620 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1621
1622 if (ip_cnt) {
1623 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1624
1625 features |= NETIF_F_LRO;
1626 }
1627 }
1628
1629 return features;
1630}
1631
1632static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1633{
1634 int err = 0;
1635
1636 if (!((dev->features ^ features) & NETIF_F_LRO))
1637 return 0;
1638
1639 if (!(features & NETIF_F_LRO))
1640 mtk_hwlro_netdev_disable(dev);
1641
1642 return err;
1643}
1644
656e7052
JC		 1645/* wait for DMA to finish whatever it is doing before we start using it again */
1646static int mtk_dma_busy_wait(struct mtk_eth *eth)
1647{
1648 unsigned long t_start = jiffies;
1649
1650 while (1) {
1651 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1652 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1653 return 0;
1654 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1655 break;
1656 }
1657
1658 dev_err(eth->dev, "DMA init timeout\n");
1659 return -1;
1660}
1661
1662static int mtk_dma_init(struct mtk_eth *eth)
1663{
1664 int err;
ee406810 1665 u32 i;
656e7052
JC		 1666
1667 if (mtk_dma_busy_wait(eth))
1668 return -EBUSY;
1669
1670 /* QDMA needs scratch memory for internal reordering of the
1671 * descriptors
1672 */
1673 err = mtk_init_fq_dma(eth);
1674 if (err)
1675 return err;
1676
1677 err = mtk_tx_alloc(eth);
1678 if (err)
1679 return err;
1680
6427dc1d
JC		 1681 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
1682 if (err)
1683 return err;
1684
ee406810 1685 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
656e7052
JC		 1686 if (err)
1687 return err;
1688
ee406810
NC		 1689 if (eth->hwlro) {
1690 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1691 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1692 if (err)
1693 return err;
1694 }
1695 err = mtk_hwlro_rx_init(eth);
1696 if (err)
1697 return err;
1698 }
1699
656e7052
JC		 1700 /* Enable random early drop and set drop threshold automatically */
1701 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1702 MTK_QDMA_FC_THRES);
1703 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1704
1705 return 0;
1706}
1707
1708static void mtk_dma_free(struct mtk_eth *eth)
1709{
1710 int i;
1711
1712 for (i = 0; i < MTK_MAC_COUNT; i++)
1713 if (eth->netdev[i])
1714 netdev_reset_queue(eth->netdev[i]);
605e4fe4
JC		 1715 if (eth->scratch_ring) {
1716 dma_free_coherent(eth->dev,
1717 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1718 eth->scratch_ring,
1719 eth->phy_scratch_ring);
1720 eth->scratch_ring = NULL;
1721 eth->phy_scratch_ring = 0;
1722 }
656e7052 1723 mtk_tx_clean(eth);
6427dc1d
JC		 1724 mtk_rx_clean(eth, &eth->rx_ring[0]);
1725 mtk_rx_clean(eth, &eth->rx_ring_qdma);
ee406810
NC		 1726
1727 if (eth->hwlro) {
1728 mtk_hwlro_rx_uninit(eth);
1729 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
6427dc1d 1730 mtk_rx_clean(eth, &eth->rx_ring[i]);
ee406810
NC		 1731 }
1732
656e7052
JC		 1733 kfree(eth->scratch_head);
1734}
1735
1736static void mtk_tx_timeout(struct net_device *dev)
1737{
1738 struct mtk_mac *mac = netdev_priv(dev);
1739 struct mtk_eth *eth = mac->hw;
1740
1741 eth->netdev[mac->id]->stats.tx_errors++;
1742 netif_err(eth, tx_err, dev,
1743 "transmit timed out\n");
7c78b4ad 1744 schedule_work(&eth->pending_work);
656e7052
JC		 1745}
1746
80673029 1747static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
656e7052
JC		 1748{
1749 struct mtk_eth *eth = _eth;
656e7052 1750
80673029
JC		 1751 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1752 __napi_schedule(&eth->rx_napi);
5cce0322 1753 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
80673029 1754 }
656e7052 1755
80673029
JC		 1756 return IRQ_HANDLED;
1757}
1758
1759static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1760{
1761 struct mtk_eth *eth = _eth;
1762
1763 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1764 __napi_schedule(&eth->tx_napi);
5cce0322 1765 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
656e7052 1766 }
656e7052
JC		 1767
1768 return IRQ_HANDLED;
1769}
1770
1771#ifdef CONFIG_NET_POLL_CONTROLLER
1772static void mtk_poll_controller(struct net_device *dev)
1773{
1774 struct mtk_mac *mac = netdev_priv(dev);
1775 struct mtk_eth *eth = mac->hw;
656e7052 1776
5cce0322
JC		 1777 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1778 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
8186f6e3 1779 mtk_handle_irq_rx(eth->irq[2], dev);
5cce0322
JC		 1780 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1781 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
656e7052
JC		 1782}
1783#endif
1784
1785static int mtk_start_dma(struct mtk_eth *eth)
1786{
1787 int err;
1788
1789 err = mtk_dma_init(eth);
1790 if (err) {
1791 mtk_dma_free(eth);
1792 return err;
1793 }
1794
1795 mtk_w32(eth,
bacfd110 1796 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
6427dc1d
JC		 1797 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
1798 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1799 MTK_RX_BT_32DWORDS,
656e7052
JC		 1800 MTK_QDMA_GLO_CFG);
1801
bacfd110
NC		 1802 mtk_w32(eth,
1803 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1804 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1805 MTK_PDMA_GLO_CFG);
1806
656e7052
JC		 1807 return 0;
1808}
1809
1810static int mtk_open(struct net_device *dev)
1811{
1812 struct mtk_mac *mac = netdev_priv(dev);
1813 struct mtk_eth *eth = mac->hw;
1814
1815 /* we run 2 netdevs on the same dma ring so we only bring it up once */
c6d4e63e 1816 if (!refcount_read(&eth->dma_refcnt)) {
656e7052
JC		 1817 int err = mtk_start_dma(eth);
1818
1819 if (err)
1820 return err;
1821
80673029 1822 napi_enable(&eth->tx_napi);
656e7052 1823 napi_enable(&eth->rx_napi);
5cce0322
JC		 1824 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1825 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
c6d4e63e 1826 refcount_set(&eth->dma_refcnt, 1);
656e7052 1827 }
c6d4e63e
ER		 1828 else
1829 refcount_inc(&eth->dma_refcnt);
656e7052 1830
2364c5c5 1831 phy_start(dev->phydev);
656e7052
JC		 1832 netif_start_queue(dev);
1833
1834 return 0;
1835}
1836
1837static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1838{
656e7052
JC		 1839 u32 val;
1840 int i;
1841
1842 /* stop the dma engine */
e3e9652a 1843 spin_lock_bh(&eth->page_lock);
656e7052
JC		 1844 val = mtk_r32(eth, glo_cfg);
1845 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1846 glo_cfg);
e3e9652a 1847 spin_unlock_bh(&eth->page_lock);
656e7052
JC		 1848
1849 /* wait for dma stop */
1850 for (i = 0; i < 10; i++) {
1851 val = mtk_r32(eth, glo_cfg);
1852 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1853 msleep(20);
1854 continue;
1855 }
1856 break;
1857 }
1858}
1859
1860static int mtk_stop(struct net_device *dev)
1861{
1862 struct mtk_mac *mac = netdev_priv(dev);
1863 struct mtk_eth *eth = mac->hw;
1864
1865 netif_tx_disable(dev);
2364c5c5 1866 phy_stop(dev->phydev);
656e7052
JC		 1867
1868 /* only shutdown DMA if this is the last user */
c6d4e63e 1869 if (!refcount_dec_and_test(&eth->dma_refcnt))
656e7052
JC		 1870 return 0;
1871
5cce0322
JC		 1872 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1873 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
80673029 1874 napi_disable(&eth->tx_napi);
656e7052
JC		 1875 napi_disable(&eth->rx_napi);
1876
1877 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
6bf563d5 1878 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
656e7052
JC		 1879
1880 mtk_dma_free(eth);
1881
1882 return 0;
1883}
1884
2a8307aa
SW		 1885static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1886{
1887 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1888 reset_bits,
1889 reset_bits);
1890
1891 usleep_range(1000, 1100);
1892 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1893 reset_bits,
1894 ~reset_bits);
1895 mdelay(10);
1896}
1897
2ec50f57
SW		 1898static void mtk_clk_disable(struct mtk_eth *eth)
1899{
1900 int clk;
1901
1902 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
1903 clk_disable_unprepare(eth->clks[clk]);
1904}
1905
1906static int mtk_clk_enable(struct mtk_eth *eth)
1907{
1908 int clk, ret;
1909
1910 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
1911 ret = clk_prepare_enable(eth->clks[clk]);
1912 if (ret)
1913 goto err_disable_clks;
1914 }
1915
1916 return 0;
1917
1918err_disable_clks:
1919 while (--clk >= 0)
1920 clk_disable_unprepare(eth->clks[clk]);
1921
1922 return ret;
1923}
1924
9ea4d311 1925static int mtk_hw_init(struct mtk_eth *eth)
656e7052 1926{
2ec50f57 1927 int i, val, ret;
9ea4d311
SW		 1928
1929 if (test_and_set_bit(MTK_HW_INIT, &eth->state))
1930 return 0;
85574dbf 1931
26a2ad8a
SW		 1932 pm_runtime_enable(eth->dev);
1933 pm_runtime_get_sync(eth->dev);
1934
2ec50f57
SW		 1935 ret = mtk_clk_enable(eth);
1936 if (ret)
1937 goto err_disable_pm;
1938
2a8307aa
SW		 1939 ethsys_reset(eth, RSTCTRL_FE);
1940 ethsys_reset(eth, RSTCTRL_PPE);
656e7052 1941
9ea4d311
SW		 1942 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1943 for (i = 0; i < MTK_MAC_COUNT; i++) {
1944 if (!eth->mac[i])
1945 continue;
1946 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1947 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1948 }
1949 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1950
243dc5fb
SW		 1951 if (eth->pctl) {
1952 /* Set GE2 driving and slew rate */
1953 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
656e7052 1954
243dc5fb
SW		 1955 /* set GE2 TDSEL */
1956 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
656e7052 1957
243dc5fb
SW		 1958 /* set GE2 TUNE */
1959 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1960 }
656e7052 1961
7352e252
SW		 1962 /* Set linkdown as the default for each GMAC. Its own MCR would be set
1963 * up with the more appropriate value when mtk_phy_link_adjust call is
1964 * being invoked.
1965 */
1966 for (i = 0; i < MTK_MAC_COUNT; i++)
1967 mtk_w32(eth, 0, MTK_MAC_MCR(i));
656e7052 1968
87e3df49
SW		 1969 /* Indicates CDM to parse the MTK special tag from CPU
1970 * which also is working out for untag packets.
1971 */
1972 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
1973 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
1974
656e7052
JC		 1975 /* Enable RX VLan Offloading */
1976 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1977
671d41e6
JC		 1978 /* enable interrupt delay for RX */
1979 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
1980
656e7052
JC		 1981 /* disable delay and normal interrupt */
1982 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
5cce0322
JC		 1983 mtk_tx_irq_disable(eth, ~0);
1984 mtk_rx_irq_disable(eth, ~0);
656e7052
JC		 1985 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1986 mtk_w32(eth, 0, MTK_RST_GL);
1987
1988 /* FE int grouping */
80673029
JC		 1989 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1990 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1991 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1992 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1993 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
656e7052
JC		 1994
1995 for (i = 0; i < 2; i++) {
1996 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1997
9c08435e 1998 /* setup the forward port to send frame to PDMA */
656e7052 1999 val &= ~0xffff;
656e7052
JC		 2000
2001 /* Enable RX checksum */
2002 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2003
2004 /* setup the mac dma */
2005 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2006 }
2007
2008 return 0;
2ec50f57
SW		 2009
2010err_disable_pm:
2011 pm_runtime_put_sync(eth->dev);
2012 pm_runtime_disable(eth->dev);
2013
2014 return ret;
656e7052
JC		 2015}
2016
bf253fb7
SW		 2017static int mtk_hw_deinit(struct mtk_eth *eth)
2018{
9ea4d311
SW		 2019 if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
2020 return 0;
2021
2ec50f57 2022 mtk_clk_disable(eth);
bf253fb7 2023
26a2ad8a
SW		 2024 pm_runtime_put_sync(eth->dev);
2025 pm_runtime_disable(eth->dev);
2026
bf253fb7
SW		 2027 return 0;
2028}
2029
656e7052
JC		 2030static int __init mtk_init(struct net_device *dev)
2031{
2032 struct mtk_mac *mac = netdev_priv(dev);
2033 struct mtk_eth *eth = mac->hw;
2034 const char *mac_addr;
2035
2036 mac_addr = of_get_mac_address(mac->of_node);
2037 if (mac_addr)
2038 ether_addr_copy(dev->dev_addr, mac_addr);
2039
2040 /* If the mac address is invalid, use random mac address */
2041 if (!is_valid_ether_addr(dev->dev_addr)) {
e3c36e48 2042 eth_hw_addr_random(dev);
656e7052
JC		 2043 dev_err(eth->dev, "generated random MAC address %pM\n",
2044 dev->dev_addr);
656e7052
JC		 2045 }
2046
2364c5c5 2047 return mtk_phy_connect(dev);
656e7052
JC		 2048}
2049
2050static void mtk_uninit(struct net_device *dev)
2051{
2052 struct mtk_mac *mac = netdev_priv(dev);
2053 struct mtk_eth *eth = mac->hw;
2054
2364c5c5 2055 phy_disconnect(dev->phydev);
16a67eb3
JH		 2056 if (of_phy_is_fixed_link(mac->of_node))
2057 of_phy_deregister_fixed_link(mac->of_node);
5cce0322
JC		 2058 mtk_tx_irq_disable(eth, ~0);
2059 mtk_rx_irq_disable(eth, ~0);
656e7052
JC		 2060}
2061
2062static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2063{
656e7052
JC		 2064 switch (cmd) {
2065 case SIOCGMIIPHY:
2066 case SIOCGMIIREG:
2067 case SIOCSMIIREG:
2364c5c5 2068 return phy_mii_ioctl(dev->phydev, ifr, cmd);
656e7052
JC		 2069 default:
2070 break;
2071 }
2072
2073 return -EOPNOTSUPP;
2074}
2075
2076static void mtk_pending_work(struct work_struct *work)
2077{
7c78b4ad 2078 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
e7d425dc
JC		 2079 int err, i;
2080 unsigned long restart = 0;
656e7052
JC		 2081
2082 rtnl_lock();
656e7052 2083
dce6fa42
SW		 2084 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2085
2086 while (test_and_set_bit_lock(MTK_RESETTING, &eth->state))
2087 cpu_relax();
2088
2089 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
e7d425dc
JC		 2090 /* stop all devices to make sure that dma is properly shut down */
2091 for (i = 0; i < MTK_MAC_COUNT; i++) {
7c78b4ad 2092 if (!eth->netdev[i])
e7d425dc
JC		 2093 continue;
2094 mtk_stop(eth->netdev[i]);
2095 __set_bit(i, &restart);
2096 }
dce6fa42 2097 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
e7d425dc 2098
9ea4d311
SW		 2099 /* restart underlying hardware such as power, clock, pin mux
2100 * and the connected phy
2101 */
2102 mtk_hw_deinit(eth);
2103
2104 if (eth->dev->pins)
2105 pinctrl_select_state(eth->dev->pins->p,
2106 eth->dev->pins->default_state);
2107 mtk_hw_init(eth);
2108
2109 for (i = 0; i < MTK_MAC_COUNT; i++) {
2110 if (!eth->mac[i] ||
2111 of_phy_is_fixed_link(eth->mac[i]->of_node))
2112 continue;
2364c5c5 2113 err = phy_init_hw(eth->netdev[i]->phydev);
9ea4d311
SW		 2114 if (err)
2115 dev_err(eth->dev, "%s: PHY init failed.\n",
2116 eth->netdev[i]->name);
2117 }
2118
e7d425dc
JC		 2119 /* restart DMA and enable IRQs */
2120 for (i = 0; i < MTK_MAC_COUNT; i++) {
2121 if (!test_bit(i, &restart))
2122 continue;
2123 err = mtk_open(eth->netdev[i]);
2124 if (err) {
2125 netif_alert(eth, ifup, eth->netdev[i],
2126 "Driver up/down cycle failed, closing device.\n");
2127 dev_close(eth->netdev[i]);
2128 }
656e7052 2129 }
dce6fa42
SW		 2130
2131 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2132
2133 clear_bit_unlock(MTK_RESETTING, &eth->state);
2134
656e7052
JC		 2135 rtnl_unlock();
2136}
2137
8a8a9e89 2138static int mtk_free_dev(struct mtk_eth *eth)
656e7052
JC		 2139{
2140 int i;
2141
2142 for (i = 0; i < MTK_MAC_COUNT; i++) {
656e7052
JC		 2143 if (!eth->netdev[i])
2144 continue;
8a8a9e89
SW		 2145 free_netdev(eth->netdev[i]);
2146 }
2147
2148 return 0;
2149}
656e7052 2150
8a8a9e89
SW		 2151static int mtk_unreg_dev(struct mtk_eth *eth)
2152{
2153 int i;
2154
2155 for (i = 0; i < MTK_MAC_COUNT; i++) {
2156 if (!eth->netdev[i])
2157 continue;
656e7052 2158 unregister_netdev(eth->netdev[i]);
656e7052 2159 }
8a8a9e89
SW		 2160
2161 return 0;
2162}
2163
2164static int mtk_cleanup(struct mtk_eth *eth)
2165{
2166 mtk_unreg_dev(eth);
2167 mtk_free_dev(eth);
7c78b4ad 2168 cancel_work_sync(&eth->pending_work);
656e7052
JC		 2169
2170 return 0;
2171}
2172
3a82e78c
BX		 2173static int mtk_get_link_ksettings(struct net_device *ndev,
2174 struct ethtool_link_ksettings *cmd)
656e7052 2175{
3e60b748 2176 struct mtk_mac *mac = netdev_priv(ndev);
656e7052 2177
dce6fa42
SW		 2178 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2179 return -EBUSY;
2180
5514174f 2181 phy_ethtool_ksettings_get(ndev->phydev, cmd);
2182
2183 return 0;
656e7052
JC		 2184}
2185
3a82e78c
BX		 2186static int mtk_set_link_ksettings(struct net_device *ndev,
2187 const struct ethtool_link_ksettings *cmd)
656e7052 2188{
3e60b748 2189 struct mtk_mac *mac = netdev_priv(ndev);
656e7052 2190
3e60b748
SW		 2191 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2192 return -EBUSY;
656e7052 2193
3e60b748 2194 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
656e7052
JC		 2195}
2196
2197static void mtk_get_drvinfo(struct net_device *dev,
2198 struct ethtool_drvinfo *info)
2199{
2200 struct mtk_mac *mac = netdev_priv(dev);
2201
2202 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2203 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2204 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2205}
2206
2207static u32 mtk_get_msglevel(struct net_device *dev)
2208{
2209 struct mtk_mac *mac = netdev_priv(dev);
2210
2211 return mac->hw->msg_enable;
2212}
2213
2214static void mtk_set_msglevel(struct net_device *dev, u32 value)
2215{
2216 struct mtk_mac *mac = netdev_priv(dev);
2217
2218 mac->hw->msg_enable = value;
2219}
2220
2221static int mtk_nway_reset(struct net_device *dev)
2222{
2223 struct mtk_mac *mac = netdev_priv(dev);
2224
dce6fa42
SW		 2225 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2226 return -EBUSY;
2227
2364c5c5 2228 return genphy_restart_aneg(dev->phydev);
656e7052
JC		 2229}
2230
2231static u32 mtk_get_link(struct net_device *dev)
2232{
2233 struct mtk_mac *mac = netdev_priv(dev);
2234 int err;
2235
dce6fa42
SW		 2236 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2237 return -EBUSY;
2238
2364c5c5 2239 err = genphy_update_link(dev->phydev);
656e7052
JC		 2240 if (err)
2241 return ethtool_op_get_link(dev);
2242
2364c5c5 2243 return dev->phydev->link;
656e7052
JC		 2244}
2245
2246static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2247{
2248 int i;
2249
2250 switch (stringset) {
2251 case ETH_SS_STATS:
2252 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2253 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2254 data += ETH_GSTRING_LEN;
2255 }
2256 break;
2257 }
2258}
2259
2260static int mtk_get_sset_count(struct net_device *dev, int sset)
2261{
2262 switch (sset) {
2263 case ETH_SS_STATS:
2264 return ARRAY_SIZE(mtk_ethtool_stats);
2265 default:
2266 return -EOPNOTSUPP;
2267 }
2268}
2269
2270static void mtk_get_ethtool_stats(struct net_device *dev,
2271 struct ethtool_stats *stats, u64 *data)
2272{
2273 struct mtk_mac *mac = netdev_priv(dev);
2274 struct mtk_hw_stats *hwstats = mac->hw_stats;
2275 u64 *data_src, *data_dst;
2276 unsigned int start;
2277 int i;
2278
dce6fa42
SW		 2279 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2280 return;
2281
656e7052 2282 if (netif_running(dev) && netif_device_present(dev)) {
8d32e062 2283 if (spin_trylock_bh(&hwstats->stats_lock)) {
656e7052 2284 mtk_stats_update_mac(mac);
8d32e062 2285 spin_unlock_bh(&hwstats->stats_lock);
656e7052
JC		 2286 }
2287 }
2288
94d308d0
SW		 2289 data_src = (u64 *)hwstats;
2290
656e7052 2291 do {
656e7052
JC		 2292 data_dst = data;
2293 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2294
2295 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2296 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2297 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2298}
2299
7aab747e
NC		 2300static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2301 u32 *rule_locs)
2302{
2303 int ret = -EOPNOTSUPP;
2304
2305 switch (cmd->cmd) {
2306 case ETHTOOL_GRXRINGS:
2307 if (dev->features & NETIF_F_LRO) {
2308 cmd->data = MTK_MAX_RX_RING_NUM;
2309 ret = 0;
2310 }
2311 break;
2312 case ETHTOOL_GRXCLSRLCNT:
2313 if (dev->features & NETIF_F_LRO) {
2314 struct mtk_mac *mac = netdev_priv(dev);
2315
2316 cmd->rule_cnt = mac->hwlro_ip_cnt;
2317 ret = 0;
2318 }
2319 break;
2320 case ETHTOOL_GRXCLSRULE:
2321 if (dev->features & NETIF_F_LRO)
2322 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2323 break;
2324 case ETHTOOL_GRXCLSRLALL:
2325 if (dev->features & NETIF_F_LRO)
2326 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2327 rule_locs);
2328 break;
2329 default:
2330 break;
2331 }
2332
2333 return ret;
2334}
2335
2336static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2337{
2338 int ret = -EOPNOTSUPP;
2339
2340 switch (cmd->cmd) {
2341 case ETHTOOL_SRXCLSRLINS:
2342 if (dev->features & NETIF_F_LRO)
2343 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2344 break;
2345 case ETHTOOL_SRXCLSRLDEL:
2346 if (dev->features & NETIF_F_LRO)
2347 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2348 break;
2349 default:
2350 break;
2351 }
2352
2353 return ret;
2354}
2355
6a38cb15 2356static const struct ethtool_ops mtk_ethtool_ops = {
3e60b748
SW		 2357 .get_link_ksettings = mtk_get_link_ksettings,
2358 .set_link_ksettings = mtk_set_link_ksettings,
656e7052
JC		 2359 .get_drvinfo = mtk_get_drvinfo,
2360 .get_msglevel = mtk_get_msglevel,
2361 .set_msglevel = mtk_set_msglevel,
2362 .nway_reset = mtk_nway_reset,
2363 .get_link = mtk_get_link,
2364 .get_strings = mtk_get_strings,
2365 .get_sset_count = mtk_get_sset_count,
2366 .get_ethtool_stats = mtk_get_ethtool_stats,
7aab747e
NC		 2367 .get_rxnfc = mtk_get_rxnfc,
2368 .set_rxnfc = mtk_set_rxnfc,
656e7052
JC		 2369};
2370
2371static const struct net_device_ops mtk_netdev_ops = {
2372 .ndo_init = mtk_init,
2373 .ndo_uninit = mtk_uninit,
2374 .ndo_open = mtk_open,
2375 .ndo_stop = mtk_stop,
2376 .ndo_start_xmit = mtk_start_xmit,
2377 .ndo_set_mac_address = mtk_set_mac_address,
2378 .ndo_validate_addr = eth_validate_addr,
2379 .ndo_do_ioctl = mtk_do_ioctl,
656e7052
JC		 2380 .ndo_tx_timeout = mtk_tx_timeout,
2381 .ndo_get_stats64 = mtk_get_stats64,
7aab747e
NC		 2382 .ndo_fix_features = mtk_fix_features,
2383 .ndo_set_features = mtk_set_features,
656e7052
JC		 2384#ifdef CONFIG_NET_POLL_CONTROLLER
2385 .ndo_poll_controller = mtk_poll_controller,
2386#endif
2387};
2388
2389static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2390{
2391 struct mtk_mac *mac;
2392 const __be32 *_id = of_get_property(np, "reg", NULL);
2393 int id, err;
2394
2395 if (!_id) {
2396 dev_err(eth->dev, "missing mac id\n");
2397 return -EINVAL;
2398 }
2399
2400 id = be32_to_cpup(_id);
2401 if (id >= MTK_MAC_COUNT) {
2402 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2403 return -EINVAL;
2404 }
2405
2406 if (eth->netdev[id]) {
2407 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2408 return -EINVAL;
2409 }
2410
2411 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2412 if (!eth->netdev[id]) {
2413 dev_err(eth->dev, "alloc_etherdev failed\n");
2414 return -ENOMEM;
2415 }
2416 mac = netdev_priv(eth->netdev[id]);
2417 eth->mac[id] = mac;
2418 mac->id = id;
2419 mac->hw = eth;
2420 mac->of_node = np;
656e7052 2421
ee406810
NC		 2422 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2423 mac->hwlro_ip_cnt = 0;
2424
656e7052
JC		 2425 mac->hw_stats = devm_kzalloc(eth->dev,
2426 sizeof(*mac->hw_stats),
2427 GFP_KERNEL);
2428 if (!mac->hw_stats) {
2429 dev_err(eth->dev, "failed to allocate counter memory\n");
2430 err = -ENOMEM;
2431 goto free_netdev;
2432 }
2433 spin_lock_init(&mac->hw_stats->stats_lock);
d7005652 2434 u64_stats_init(&mac->hw_stats->syncp);
656e7052
JC		 2435 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2436
2437 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
eaadf9fd 2438 eth->netdev[id]->watchdog_timeo = 5 * HZ;
656e7052
JC		 2439 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2440 eth->netdev[id]->base_addr = (unsigned long)eth->base;
ee406810
NC		 2441
2442 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2443 if (eth->hwlro)
2444 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2445
656e7052
JC		 2446 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2447 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2448 eth->netdev[id]->features |= MTK_HW_FEATURES;
2449 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2450
80673029 2451 eth->netdev[id]->irq = eth->irq[0];
3174b3b5
SW		 2452 eth->netdev[id]->dev.of_node = np;
2453
656e7052
JC		 2454 return 0;
2455
2456free_netdev:
2457 free_netdev(eth->netdev[id]);
2458 return err;
2459}
2460
2461static int mtk_probe(struct platform_device *pdev)
2462{
2463 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2464 struct device_node *mac_np;
656e7052
JC		 2465 struct mtk_eth *eth;
2466 int err;
80673029 2467 int i;
656e7052 2468
656e7052
JC		 2469 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2470 if (!eth)
2471 return -ENOMEM;
2472
eda7d46d 2473 eth->soc = of_device_get_match_data(&pdev->dev);
2ec50f57 2474
549e5495 2475 eth->dev = &pdev->dev;
656e7052 2476 eth->base = devm_ioremap_resource(&pdev->dev, res);
621e49f6
VZ		 2477 if (IS_ERR(eth->base))
2478 return PTR_ERR(eth->base);
656e7052
JC		 2479
2480 spin_lock_init(&eth->page_lock);
5cce0322
JC		 2481 spin_lock_init(&eth->tx_irq_lock);
2482 spin_lock_init(&eth->rx_irq_lock);
656e7052
JC		 2483
2484 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2485 "mediatek,ethsys");
2486 if (IS_ERR(eth->ethsys)) {
2487 dev_err(&pdev->dev, "no ethsys regmap found\n");
2488 return PTR_ERR(eth->ethsys);
2489 }
2490
42c03844
SW		 2491 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
2492 eth->sgmiisys =
2493 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2494 "mediatek,sgmiisys");
2495 if (IS_ERR(eth->sgmiisys)) {
2496 dev_err(&pdev->dev, "no sgmiisys regmap found\n");
2497 return PTR_ERR(eth->sgmiisys);
2498 }
2499 }
2500
243dc5fb
SW		 2501 if (eth->soc->required_pctl) {
2502 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2503 "mediatek,pctl");
2504 if (IS_ERR(eth->pctl)) {
2505 dev_err(&pdev->dev, "no pctl regmap found\n");
2506 return PTR_ERR(eth->pctl);
2507 }
656e7052
JC		 2508 }
2509
80673029
JC		 2510 for (i = 0; i < 3; i++) {
2511 eth->irq[i] = platform_get_irq(pdev, i);
2512 if (eth->irq[i] < 0) {
2513 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2514 return -ENXIO;
2515 }
656e7052 2516 }
549e5495
SW		 2517 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2518 eth->clks[i] = devm_clk_get(eth->dev,
2519 mtk_clks_source_name[i]);
2520 if (IS_ERR(eth->clks[i])) {
2521 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2522 return -EPROBE_DEFER;
2ec50f57
SW		 2523 if (eth->soc->required_clks & BIT(i)) {
2524 dev_err(&pdev->dev, "clock %s not found\n",
2525 mtk_clks_source_name[i]);
2526 return -EINVAL;
2527 }
2528 eth->clks[i] = NULL;
549e5495
SW		 2529 }
2530 }
656e7052 2531
656e7052 2532 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
7c78b4ad 2533 INIT_WORK(&eth->pending_work, mtk_pending_work);
656e7052
JC		 2534
2535 err = mtk_hw_init(eth);
2536 if (err)
2537 return err;
2538
2d14ba72 2539 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
983e1a6c 2540
656e7052
JC		 2541 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2542 if (!of_device_is_compatible(mac_np,
2543 "mediatek,eth-mac"))
2544 continue;
2545
2546 if (!of_device_is_available(mac_np))
2547 continue;
2548
2549 err = mtk_add_mac(eth, mac_np);
2550 if (err)
8a8a9e89 2551 goto err_deinit_hw;
656e7052
JC		 2552 }
2553
85574dbf
SW		 2554 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
2555 dev_name(eth->dev), eth);
2556 if (err)
2557 goto err_free_dev;
2558
2559 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
2560 dev_name(eth->dev), eth);
2561 if (err)
2562 goto err_free_dev;
2563
2564 err = mtk_mdio_init(eth);
2565 if (err)
2566 goto err_free_dev;
2567
2568 for (i = 0; i < MTK_MAX_DEVS; i++) {
2569 if (!eth->netdev[i])
2570 continue;
2571
2572 err = register_netdev(eth->netdev[i]);
2573 if (err) {
2574 dev_err(eth->dev, "error bringing up device\n");
8a8a9e89 2575 goto err_deinit_mdio;
85574dbf
SW		 2576 } else
2577 netif_info(eth, probe, eth->netdev[i],
2578 "mediatek frame engine at 0x%08lx, irq %d\n",
2579 eth->netdev[i]->base_addr, eth->irq[0]);
2580 }
2581
656e7052
JC		 2582 /* we run 2 devices on the same DMA ring so we need a dummy device
2583 * for NAPI to work
2584 */
2585 init_dummy_netdev(&eth->dummy_dev);
80673029
JC		 2586 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
2587 MTK_NAPI_WEIGHT);
2588 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
656e7052
JC		 2589 MTK_NAPI_WEIGHT);
2590
2591 platform_set_drvdata(pdev, eth);
2592
2593 return 0;
2594
8a8a9e89
SW		 2595err_deinit_mdio:
2596 mtk_mdio_cleanup(eth);
656e7052 2597err_free_dev:
8a8a9e89
SW		 2598 mtk_free_dev(eth);
2599err_deinit_hw:
2600 mtk_hw_deinit(eth);
2601
656e7052
JC		 2602 return err;
2603}
2604
2605static int mtk_remove(struct platform_device *pdev)
2606{
2607 struct mtk_eth *eth = platform_get_drvdata(pdev);
79e9a414
SW		 2608 int i;
2609
2610 /* stop all devices to make sure that dma is properly shut down */
2611 for (i = 0; i < MTK_MAC_COUNT; i++) {
2612 if (!eth->netdev[i])
2613 continue;
2614 mtk_stop(eth->netdev[i]);
2615 }
656e7052 2616
bf253fb7 2617 mtk_hw_deinit(eth);
656e7052 2618
80673029 2619 netif_napi_del(&eth->tx_napi);
656e7052
JC		 2620 netif_napi_del(&eth->rx_napi);
2621 mtk_cleanup(eth);
e82f7148 2622 mtk_mdio_cleanup(eth);
656e7052
JC		 2623
2624 return 0;
2625}
2626
2ec50f57 2627static const struct mtk_soc_data mt2701_data = {
2d14ba72 2628 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO,
243dc5fb
SW		 2629 .required_clks = MT7623_CLKS_BITMAP,
2630 .required_pctl = true,
2ec50f57
SW		 2631};
2632
42c03844 2633static const struct mtk_soc_data mt7622_data = {
2d14ba72 2634 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO,
243dc5fb
SW		 2635 .required_clks = MT7622_CLKS_BITMAP,
2636 .required_pctl = false,
42c03844
SW		 2637};
2638
2ec50f57 2639static const struct mtk_soc_data mt7623_data = {
2d14ba72 2640 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO,
243dc5fb
SW		 2641 .required_clks = MT7623_CLKS_BITMAP,
2642 .required_pctl = true,
2ec50f57
SW		 2643};
2644
656e7052 2645const struct of_device_id of_mtk_match[] = {
2ec50f57 2646 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
42c03844 2647 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
2ec50f57 2648 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
656e7052
JC		 2649 {},
2650};
7077dc41 2651MODULE_DEVICE_TABLE(of, of_mtk_match);
656e7052
JC		 2652
2653static struct platform_driver mtk_driver = {
2654 .probe = mtk_probe,
2655 .remove = mtk_remove,
2656 .driver = {
2657 .name = "mtk_soc_eth",
656e7052
JC		 2658 .of_match_table = of_mtk_match,
2659 },
2660};
2661
2662module_platform_driver(mtk_driver);
2663
2664MODULE_LICENSE("GPL");
2665MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2666MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux 6.x block layer and io_uring tree(s)