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net: ethernet: mediatek: add more resets for internal ethernet circuit block
[linux-2.6-block.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
26a2ad8a 21#include <linux/pm_runtime.h>
656e7052
JC		 22#include <linux/if_vlan.h>
23#include <linux/reset.h>
24#include <linux/tcp.h>
25
26#include "mtk_eth_soc.h"
27
28static int mtk_msg_level = -1;
29module_param_named(msg_level, mtk_msg_level, int, 0);
30MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31
32#define MTK_ETHTOOL_STAT(x) { #x, \
33 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
34
35/* strings used by ethtool */
36static const struct mtk_ethtool_stats {
37 char str[ETH_GSTRING_LEN];
38 u32 offset;
39} mtk_ethtool_stats[] = {
40 MTK_ETHTOOL_STAT(tx_bytes),
41 MTK_ETHTOOL_STAT(tx_packets),
42 MTK_ETHTOOL_STAT(tx_skip),
43 MTK_ETHTOOL_STAT(tx_collisions),
44 MTK_ETHTOOL_STAT(rx_bytes),
45 MTK_ETHTOOL_STAT(rx_packets),
46 MTK_ETHTOOL_STAT(rx_overflow),
47 MTK_ETHTOOL_STAT(rx_fcs_errors),
48 MTK_ETHTOOL_STAT(rx_short_errors),
49 MTK_ETHTOOL_STAT(rx_long_errors),
50 MTK_ETHTOOL_STAT(rx_checksum_errors),
51 MTK_ETHTOOL_STAT(rx_flow_control_packets),
52};
53
549e5495
SW		 54static const char * const mtk_clks_source_name[] = {
55 "ethif", "esw", "gp1", "gp2"
56};
57
656e7052
JC		 58void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
59{
60 __raw_writel(val, eth->base + reg);
61}
62
63u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
64{
65 return __raw_readl(eth->base + reg);
66}
67
68static int mtk_mdio_busy_wait(struct mtk_eth *eth)
69{
70 unsigned long t_start = jiffies;
71
72 while (1) {
73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
74 return 0;
75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
76 break;
77 usleep_range(10, 20);
78 }
79
80 dev_err(eth->dev, "mdio: MDIO timeout\n");
81 return -1;
82}
83
379672de
WY		 84static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
85 u32 phy_register, u32 write_data)
656e7052
JC		 86{
87 if (mtk_mdio_busy_wait(eth))
88 return -1;
89
90 write_data &= 0xffff;
91
92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
93 (phy_register << PHY_IAC_REG_SHIFT) |
94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
95 MTK_PHY_IAC);
96
97 if (mtk_mdio_busy_wait(eth))
98 return -1;
99
100 return 0;
101}
102
379672de 103static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
656e7052
JC		 104{
105 u32 d;
106
107 if (mtk_mdio_busy_wait(eth))
108 return 0xffff;
109
110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
111 (phy_reg << PHY_IAC_REG_SHIFT) |
112 (phy_addr << PHY_IAC_ADDR_SHIFT),
113 MTK_PHY_IAC);
114
115 if (mtk_mdio_busy_wait(eth))
116 return 0xffff;
117
118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
119
120 return d;
121}
122
123static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
124 int phy_reg, u16 val)
125{
126 struct mtk_eth *eth = bus->priv;
127
128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
129}
130
131static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
132{
133 struct mtk_eth *eth = bus->priv;
134
135 return _mtk_mdio_read(eth, phy_addr, phy_reg);
136}
137
138static void mtk_phy_link_adjust(struct net_device *dev)
139{
140 struct mtk_mac *mac = netdev_priv(dev);
08ef55c6
JC		 141 u16 lcl_adv = 0, rmt_adv = 0;
142 u8 flowctrl;
656e7052
JC		 143 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
144 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
145 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
146 MAC_MCR_BACKPR_EN;
147
148 switch (mac->phy_dev->speed) {
149 case SPEED_1000:
150 mcr |= MAC_MCR_SPEED_1000;
151 break;
152 case SPEED_100:
153 mcr |= MAC_MCR_SPEED_100;
154 break;
155 };
156
157 if (mac->phy_dev->link)
158 mcr |= MAC_MCR_FORCE_LINK;
159
08ef55c6 160 if (mac->phy_dev->duplex) {
656e7052
JC		 161 mcr |= MAC_MCR_FORCE_DPX;
162
08ef55c6
JC		 163 if (mac->phy_dev->pause)
164 rmt_adv = LPA_PAUSE_CAP;
165 if (mac->phy_dev->asym_pause)
166 rmt_adv |= LPA_PAUSE_ASYM;
167
168 if (mac->phy_dev->advertising & ADVERTISED_Pause)
169 lcl_adv |= ADVERTISE_PAUSE_CAP;
170 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
171 lcl_adv |= ADVERTISE_PAUSE_ASYM;
172
173 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
174
175 if (flowctrl & FLOW_CTRL_TX)
176 mcr |= MAC_MCR_FORCE_TX_FC;
177 if (flowctrl & FLOW_CTRL_RX)
178 mcr |= MAC_MCR_FORCE_RX_FC;
179
180 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
181 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
182 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
183 }
656e7052
JC		 184
185 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
186
187 if (mac->phy_dev->link)
188 netif_carrier_on(dev);
189 else
190 netif_carrier_off(dev);
191}
192
193static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
194 struct device_node *phy_node)
195{
196 const __be32 *_addr = NULL;
197 struct phy_device *phydev;
198 int phy_mode, addr;
199
200 _addr = of_get_property(phy_node, "reg", NULL);
201
202 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
203 pr_err("%s: invalid phy address\n", phy_node->name);
204 return -EINVAL;
205 }
206 addr = be32_to_cpu(*_addr);
207 phy_mode = of_get_phy_mode(phy_node);
208 if (phy_mode < 0) {
209 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
210 return -EINVAL;
211 }
212
213 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
214 mtk_phy_link_adjust, 0, phy_mode);
977bc20c 215 if (!phydev) {
656e7052 216 dev_err(eth->dev, "could not connect to PHY\n");
977bc20c 217 return -ENODEV;
656e7052
JC		 218 }
219
220 dev_info(eth->dev,
221 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
222 mac->id, phydev_name(phydev), phydev->phy_id,
223 phydev->drv->name);
224
225 mac->phy_dev = phydev;
226
227 return 0;
228}
229
230static int mtk_phy_connect(struct mtk_mac *mac)
231{
232 struct mtk_eth *eth = mac->hw;
233 struct device_node *np;
9ea4d311 234 u32 val;
656e7052
JC		 235
236 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
0c72c50f
JC		 237 if (!np && of_phy_is_fixed_link(mac->of_node))
238 if (!of_phy_register_fixed_link(mac->of_node))
239 np = of_node_get(mac->of_node);
656e7052
JC		 240 if (!np)
241 return -ENODEV;
242
243 switch (of_get_phy_mode(np)) {
37920fce
JC		 244 case PHY_INTERFACE_MODE_RGMII_TXID:
245 case PHY_INTERFACE_MODE_RGMII_RXID:
246 case PHY_INTERFACE_MODE_RGMII_ID:
656e7052 247 case PHY_INTERFACE_MODE_RGMII:
9ea4d311 248 mac->ge_mode = 0;
656e7052
JC		 249 break;
250 case PHY_INTERFACE_MODE_MII:
9ea4d311 251 mac->ge_mode = 1;
656e7052 252 break;
8ca7f4fe 253 case PHY_INTERFACE_MODE_REVMII:
9ea4d311 254 mac->ge_mode = 2;
656e7052 255 break;
8ca7f4fe 256 case PHY_INTERFACE_MODE_RMII:
257 if (!mac->id)
258 goto err_phy;
9ea4d311 259 mac->ge_mode = 3;
8ca7f4fe 260 break;
656e7052 261 default:
8ca7f4fe 262 goto err_phy;
656e7052
JC		 263 }
264
265 /* put the gmac into the right mode */
266 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
267 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
9ea4d311 268 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
656e7052
JC		 269 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
270
271 mtk_phy_connect_node(eth, mac, np);
272 mac->phy_dev->autoneg = AUTONEG_ENABLE;
273 mac->phy_dev->speed = 0;
274 mac->phy_dev->duplex = 0;
b2025c7c 275
276 if (of_phy_is_fixed_link(mac->of_node))
277 mac->phy_dev->supported |=
278 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
279
08ef55c6
JC		 280 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
281 SUPPORTED_Asym_Pause;
656e7052
JC		 282 mac->phy_dev->advertising = mac->phy_dev->supported |
283 ADVERTISED_Autoneg;
284 phy_start_aneg(mac->phy_dev);
285
e8c2993a 286 of_node_put(np);
287
656e7052 288 return 0;
8ca7f4fe 289
290err_phy:
291 of_node_put(np);
292 dev_err(eth->dev, "invalid phy_mode\n");
293 return -EINVAL;
656e7052
JC		 294}
295
296static int mtk_mdio_init(struct mtk_eth *eth)
297{
298 struct device_node *mii_np;
1e515b7f 299 int ret;
656e7052
JC		 300
301 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
302 if (!mii_np) {
303 dev_err(eth->dev, "no %s child node found", "mdio-bus");
304 return -ENODEV;
305 }
306
307 if (!of_device_is_available(mii_np)) {
aa6e8a54 308 ret = -ENODEV;
656e7052
JC		 309 goto err_put_node;
310 }
311
1e515b7f 312 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
656e7052 313 if (!eth->mii_bus) {
1e515b7f 314 ret = -ENOMEM;
656e7052
JC		 315 goto err_put_node;
316 }
317
318 eth->mii_bus->name = "mdio";
319 eth->mii_bus->read = mtk_mdio_read;
320 eth->mii_bus->write = mtk_mdio_write;
321 eth->mii_bus->priv = eth;
322 eth->mii_bus->parent = eth->dev;
323
324 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
1e515b7f 325 ret = of_mdiobus_register(eth->mii_bus, mii_np);
656e7052
JC		 326
327err_put_node:
328 of_node_put(mii_np);
1e515b7f 329 return ret;
656e7052
JC		 330}
331
332static void mtk_mdio_cleanup(struct mtk_eth *eth)
333{
334 if (!eth->mii_bus)
335 return;
336
337 mdiobus_unregister(eth->mii_bus);
656e7052
JC		 338}
339
bacfd110
NC		 340static inline void mtk_irq_disable(struct mtk_eth *eth,
341 unsigned reg, u32 mask)
656e7052 342{
7bc9ccec 343 unsigned long flags;
656e7052
JC		 344 u32 val;
345
7bc9ccec 346 spin_lock_irqsave(&eth->irq_lock, flags);
bacfd110
NC		 347 val = mtk_r32(eth, reg);
348 mtk_w32(eth, val & ~mask, reg);
7bc9ccec 349 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 350}
351
bacfd110
NC		 352static inline void mtk_irq_enable(struct mtk_eth *eth,
353 unsigned reg, u32 mask)
656e7052 354{
7bc9ccec 355 unsigned long flags;
656e7052
JC		 356 u32 val;
357
7bc9ccec 358 spin_lock_irqsave(&eth->irq_lock, flags);
bacfd110
NC		 359 val = mtk_r32(eth, reg);
360 mtk_w32(eth, val | mask, reg);
7bc9ccec 361 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 362}
363
364static int mtk_set_mac_address(struct net_device *dev, void *p)
365{
366 int ret = eth_mac_addr(dev, p);
367 struct mtk_mac *mac = netdev_priv(dev);
368 const char *macaddr = dev->dev_addr;
656e7052
JC		 369
370 if (ret)
371 return ret;
372
e3e9652a 373 spin_lock_bh(&mac->hw->page_lock);
656e7052
JC		 374 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
375 MTK_GDMA_MAC_ADRH(mac->id));
376 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
377 (macaddr[4] << 8) | macaddr[5],
378 MTK_GDMA_MAC_ADRL(mac->id));
e3e9652a 379 spin_unlock_bh(&mac->hw->page_lock);
656e7052
JC		 380
381 return 0;
382}
383
384void mtk_stats_update_mac(struct mtk_mac *mac)
385{
386 struct mtk_hw_stats *hw_stats = mac->hw_stats;
387 unsigned int base = MTK_GDM1_TX_GBCNT;
388 u64 stats;
389
390 base += hw_stats->reg_offset;
391
392 u64_stats_update_begin(&hw_stats->syncp);
393
394 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
395 stats = mtk_r32(mac->hw, base + 0x04);
396 if (stats)
397 hw_stats->rx_bytes += (stats << 32);
398 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
399 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
400 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
401 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
402 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
403 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
404 hw_stats->rx_flow_control_packets +=
405 mtk_r32(mac->hw, base + 0x24);
406 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
407 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
408 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
409 stats = mtk_r32(mac->hw, base + 0x34);
410 if (stats)
411 hw_stats->tx_bytes += (stats << 32);
412 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
413 u64_stats_update_end(&hw_stats->syncp);
414}
415
416static void mtk_stats_update(struct mtk_eth *eth)
417{
418 int i;
419
420 for (i = 0; i < MTK_MAC_COUNT; i++) {
421 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
422 continue;
423 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
424 mtk_stats_update_mac(eth->mac[i]);
425 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
426 }
427 }
428}
429
430static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
431 struct rtnl_link_stats64 *storage)
432{
433 struct mtk_mac *mac = netdev_priv(dev);
434 struct mtk_hw_stats *hw_stats = mac->hw_stats;
435 unsigned int start;
436
437 if (netif_running(dev) && netif_device_present(dev)) {
438 if (spin_trylock(&hw_stats->stats_lock)) {
439 mtk_stats_update_mac(mac);
440 spin_unlock(&hw_stats->stats_lock);
441 }
442 }
443
444 do {
445 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
446 storage->rx_packets = hw_stats->rx_packets;
447 storage->tx_packets = hw_stats->tx_packets;
448 storage->rx_bytes = hw_stats->rx_bytes;
449 storage->tx_bytes = hw_stats->tx_bytes;
450 storage->collisions = hw_stats->tx_collisions;
451 storage->rx_length_errors = hw_stats->rx_short_errors +
452 hw_stats->rx_long_errors;
453 storage->rx_over_errors = hw_stats->rx_overflow;
454 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
455 storage->rx_errors = hw_stats->rx_checksum_errors;
456 storage->tx_aborted_errors = hw_stats->tx_skip;
457 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
458
459 storage->tx_errors = dev->stats.tx_errors;
460 storage->rx_dropped = dev->stats.rx_dropped;
461 storage->tx_dropped = dev->stats.tx_dropped;
462
463 return storage;
464}
465
466static inline int mtk_max_frag_size(int mtu)
467{
468 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
469 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
470 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
471
472 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
473 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
474}
475
476static inline int mtk_max_buf_size(int frag_size)
477{
478 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
479 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
480
481 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
482
483 return buf_size;
484}
485
486static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
487 struct mtk_rx_dma *dma_rxd)
488{
489 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
490 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
491 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
492 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
493}
494
495/* the qdma core needs scratch memory to be setup */
496static int mtk_init_fq_dma(struct mtk_eth *eth)
497{
605e4fe4 498 dma_addr_t phy_ring_tail;
656e7052
JC		 499 int cnt = MTK_DMA_SIZE;
500 dma_addr_t dma_addr;
501 int i;
502
503 eth->scratch_ring = dma_alloc_coherent(eth->dev,
504 cnt * sizeof(struct mtk_tx_dma),
605e4fe4 505 &eth->phy_scratch_ring,
656e7052
JC		 506 GFP_ATOMIC | __GFP_ZERO);
507 if (unlikely(!eth->scratch_ring))
508 return -ENOMEM;
509
510 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
511 GFP_KERNEL);
562c5a70
JC		 512 if (unlikely(!eth->scratch_head))
513 return -ENOMEM;
514
656e7052
JC		 515 dma_addr = dma_map_single(eth->dev,
516 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
517 DMA_FROM_DEVICE);
518 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
519 return -ENOMEM;
520
521 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
605e4fe4 522 phy_ring_tail = eth->phy_scratch_ring +
656e7052
JC		 523 (sizeof(struct mtk_tx_dma) * (cnt - 1));
524
525 for (i = 0; i < cnt; i++) {
526 eth->scratch_ring[i].txd1 =
527 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
528 if (i < cnt - 1)
605e4fe4 529 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
656e7052
JC		 530 ((i + 1) * sizeof(struct mtk_tx_dma)));
531 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
532 }
533
605e4fe4 534 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
656e7052
JC		 535 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
536 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
537 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
538
539 return 0;
540}
541
542static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
543{
544 void *ret = ring->dma;
545
546 return ret + (desc - ring->phys);
547}
548
549static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
550 struct mtk_tx_dma *txd)
551{
552 int idx = txd - ring->dma;
553
554 return &ring->buf[idx];
555}
556
55a4e778 557static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
656e7052
JC		 558{
559 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
55a4e778 560 dma_unmap_single(eth->dev,
656e7052
JC		 561 dma_unmap_addr(tx_buf, dma_addr0),
562 dma_unmap_len(tx_buf, dma_len0),
563 DMA_TO_DEVICE);
564 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
55a4e778 565 dma_unmap_page(eth->dev,
656e7052
JC		 566 dma_unmap_addr(tx_buf, dma_addr0),
567 dma_unmap_len(tx_buf, dma_len0),
568 DMA_TO_DEVICE);
569 }
570 tx_buf->flags = 0;
571 if (tx_buf->skb &&
572 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
573 dev_kfree_skb_any(tx_buf->skb);
574 tx_buf->skb = NULL;
575}
576
577static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
578 int tx_num, struct mtk_tx_ring *ring, bool gso)
579{
580 struct mtk_mac *mac = netdev_priv(dev);
581 struct mtk_eth *eth = mac->hw;
582 struct mtk_tx_dma *itxd, *txd;
583 struct mtk_tx_buf *tx_buf;
656e7052
JC		 584 dma_addr_t mapped_addr;
585 unsigned int nr_frags;
586 int i, n_desc = 1;
c6f1dc4d 587 u32 txd4 = 0, fport;
656e7052
JC		 588
589 itxd = ring->next_free;
590 if (itxd == ring->last_free)
591 return -ENOMEM;
592
593 /* set the forward port */
c6f1dc4d
SW		 594 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
595 txd4 |= fport;
656e7052
JC		 596
597 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
598 memset(tx_buf, 0, sizeof(*tx_buf));
599
600 if (gso)
601 txd4 |= TX_DMA_TSO;
602
603 /* TX Checksum offload */
604 if (skb->ip_summed == CHECKSUM_PARTIAL)
605 txd4 |= TX_DMA_CHKSUM;
606
607 /* VLAN header offload */
608 if (skb_vlan_tag_present(skb))
609 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
610
55a4e778 611 mapped_addr = dma_map_single(eth->dev, skb->data,
656e7052 612 skb_headlen(skb), DMA_TO_DEVICE);
55a4e778 613 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 614 return -ENOMEM;
615
656e7052
JC		 616 WRITE_ONCE(itxd->txd1, mapped_addr);
617 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
618 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
619 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
620
621 /* TX SG offload */
622 txd = itxd;
623 nr_frags = skb_shinfo(skb)->nr_frags;
624 for (i = 0; i < nr_frags; i++) {
625 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
626 unsigned int offset = 0;
627 int frag_size = skb_frag_size(frag);
628
629 while (frag_size) {
630 bool last_frag = false;
631 unsigned int frag_map_size;
632
633 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
634 if (txd == ring->last_free)
635 goto err_dma;
636
637 n_desc++;
638 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
55a4e778 639 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
656e7052
JC		 640 frag_map_size,
641 DMA_TO_DEVICE);
55a4e778 642 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 643 goto err_dma;
644
645 if (i == nr_frags - 1 &&
646 (frag_size - frag_map_size) == 0)
647 last_frag = true;
648
649 WRITE_ONCE(txd->txd1, mapped_addr);
650 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
651 TX_DMA_PLEN0(frag_map_size) |
369f0453 652 last_frag * TX_DMA_LS0));
c6f1dc4d 653 WRITE_ONCE(txd->txd4, fport);
656e7052
JC		 654
655 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
656 tx_buf = mtk_desc_to_tx_buf(ring, txd);
657 memset(tx_buf, 0, sizeof(*tx_buf));
658
659 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
660 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
661 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
662 frag_size -= frag_map_size;
663 offset += frag_map_size;
664 }
665 }
666
667 /* store skb to cleanup */
668 tx_buf->skb = skb;
669
670 WRITE_ONCE(itxd->txd4, txd4);
671 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
672 (!nr_frags * TX_DMA_LS0)));
673
656e7052
JC		 674 netdev_sent_queue(dev, skb->len);
675 skb_tx_timestamp(skb);
676
677 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
678 atomic_sub(n_desc, &ring->free_count);
679
680 /* make sure that all changes to the dma ring are flushed before we
681 * continue
682 */
683 wmb();
684
685 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
686 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
687
688 return 0;
689
690err_dma:
691 do {
2fae723c 692 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
656e7052
JC		 693
694 /* unmap dma */
55a4e778 695 mtk_tx_unmap(eth, tx_buf);
656e7052
JC		 696
697 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
698 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
699 } while (itxd != txd);
700
701 return -ENOMEM;
702}
703
704static inline int mtk_cal_txd_req(struct sk_buff *skb)
705{
706 int i, nfrags;
707 struct skb_frag_struct *frag;
708
709 nfrags = 1;
710 if (skb_is_gso(skb)) {
711 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
712 frag = &skb_shinfo(skb)->frags[i];
713 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
714 }
715 } else {
716 nfrags += skb_shinfo(skb)->nr_frags;
717 }
718
beeb4ca4 719 return nfrags;
656e7052
JC		 720}
721
ad3cba98
JC		 722static int mtk_queue_stopped(struct mtk_eth *eth)
723{
724 int i;
725
726 for (i = 0; i < MTK_MAC_COUNT; i++) {
727 if (!eth->netdev[i])
728 continue;
729 if (netif_queue_stopped(eth->netdev[i]))
730 return 1;
731 }
732
733 return 0;
734}
735
13c822f6
JC		 736static void mtk_wake_queue(struct mtk_eth *eth)
737{
738 int i;
739
740 for (i = 0; i < MTK_MAC_COUNT; i++) {
741 if (!eth->netdev[i])
742 continue;
743 netif_wake_queue(eth->netdev[i]);
744 }
745}
746
747static void mtk_stop_queue(struct mtk_eth *eth)
748{
749 int i;
750
751 for (i = 0; i < MTK_MAC_COUNT; i++) {
752 if (!eth->netdev[i])
753 continue;
754 netif_stop_queue(eth->netdev[i]);
755 }
756}
757
656e7052
JC		 758static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
759{
760 struct mtk_mac *mac = netdev_priv(dev);
761 struct mtk_eth *eth = mac->hw;
762 struct mtk_tx_ring *ring = &eth->tx_ring;
763 struct net_device_stats *stats = &dev->stats;
764 bool gso = false;
765 int tx_num;
766
34c2e4c9
JC		 767 /* normally we can rely on the stack not calling this more than once,
768 * however we have 2 queues running on the same ring so we need to lock
769 * the ring access
770 */
e3e9652a 771 spin_lock(&eth->page_lock);
34c2e4c9 772
656e7052
JC		 773 tx_num = mtk_cal_txd_req(skb);
774 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
13c822f6 775 mtk_stop_queue(eth);
656e7052
JC		 776 netif_err(eth, tx_queued, dev,
777 "Tx Ring full when queue awake!\n");
e3e9652a 778 spin_unlock(&eth->page_lock);
656e7052
JC		 779 return NETDEV_TX_BUSY;
780 }
781
782 /* TSO: fill MSS info in tcp checksum field */
783 if (skb_is_gso(skb)) {
784 if (skb_cow_head(skb, 0)) {
785 netif_warn(eth, tx_err, dev,
786 "GSO expand head fail.\n");
787 goto drop;
788 }
789
790 if (skb_shinfo(skb)->gso_type &
791 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
792 gso = true;
793 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
794 }
795 }
796
797 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
798 goto drop;
799
82c6544d 800 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
13c822f6 801 mtk_stop_queue(eth);
82c6544d 802
e3e9652a 803 spin_unlock(&eth->page_lock);
656e7052
JC		 804
805 return NETDEV_TX_OK;
806
807drop:
e3e9652a 808 spin_unlock(&eth->page_lock);
656e7052
JC		 809 stats->tx_dropped++;
810 dev_kfree_skb(skb);
811 return NETDEV_TX_OK;
812}
813
814static int mtk_poll_rx(struct napi_struct *napi, int budget,
eece71e8 815 struct mtk_eth *eth)
656e7052
JC		 816{
817 struct mtk_rx_ring *ring = &eth->rx_ring;
818 int idx = ring->calc_idx;
819 struct sk_buff *skb;
820 u8 *data, *new_data;
821 struct mtk_rx_dma *rxd, trxd;
822 int done = 0;
823
824 while (done < budget) {
825 struct net_device *netdev;
826 unsigned int pktlen;
827 dma_addr_t dma_addr;
828 int mac = 0;
829
830 idx = NEXT_RX_DESP_IDX(idx);
831 rxd = &ring->dma[idx];
832 data = ring->data[idx];
833
834 mtk_rx_get_desc(&trxd, rxd);
835 if (!(trxd.rxd2 & RX_DMA_DONE))
836 break;
837
838 /* find out which mac the packet come from. values start at 1 */
839 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
840 RX_DMA_FPORT_MASK;
841 mac--;
842
843 netdev = eth->netdev[mac];
844
845 /* alloc new buffer */
846 new_data = napi_alloc_frag(ring->frag_size);
847 if (unlikely(!new_data)) {
848 netdev->stats.rx_dropped++;
849 goto release_desc;
850 }
55a4e778 851 dma_addr = dma_map_single(eth->dev,
656e7052
JC		 852 new_data + NET_SKB_PAD,
853 ring->buf_size,
854 DMA_FROM_DEVICE);
55a4e778 855 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
656e7052 856 skb_free_frag(new_data);
94321a9f 857 netdev->stats.rx_dropped++;
656e7052
JC		 858 goto release_desc;
859 }
860
861 /* receive data */
862 skb = build_skb(data, ring->frag_size);
863 if (unlikely(!skb)) {
1b430799 864 skb_free_frag(new_data);
94321a9f 865 netdev->stats.rx_dropped++;
656e7052
JC		 866 goto release_desc;
867 }
868 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
869
55a4e778 870 dma_unmap_single(eth->dev, trxd.rxd1,
656e7052
JC		 871 ring->buf_size, DMA_FROM_DEVICE);
872 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
873 skb->dev = netdev;
874 skb_put(skb, pktlen);
875 if (trxd.rxd4 & RX_DMA_L4_VALID)
876 skb->ip_summed = CHECKSUM_UNNECESSARY;
877 else
878 skb_checksum_none_assert(skb);
879 skb->protocol = eth_type_trans(skb, netdev);
880
881 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
882 RX_DMA_VID(trxd.rxd3))
883 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
884 RX_DMA_VID(trxd.rxd3));
885 napi_gro_receive(napi, skb);
886
887 ring->data[idx] = new_data;
888 rxd->rxd1 = (unsigned int)dma_addr;
889
890release_desc:
891 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
892
893 ring->calc_idx = idx;
635372ad 894
656e7052
JC		 895 done++;
896 }
897
41156cea
SW		 898 if (done) {
899 /* make sure that all changes to the dma ring are flushed before
900 * we continue
901 */
902 wmb();
903 mtk_w32(eth, ring->calc_idx, MTK_PRX_CRX_IDX0);
904 }
656e7052
JC		 905
906 return done;
907}
908
80673029 909static int mtk_poll_tx(struct mtk_eth *eth, int budget)
656e7052
JC		 910{
911 struct mtk_tx_ring *ring = &eth->tx_ring;
912 struct mtk_tx_dma *desc;
913 struct sk_buff *skb;
914 struct mtk_tx_buf *tx_buf;
80673029 915 unsigned int done[MTK_MAX_DEVS];
656e7052
JC		 916 unsigned int bytes[MTK_MAX_DEVS];
917 u32 cpu, dma;
918 static int condition;
80673029 919 int total = 0, i;
656e7052
JC		 920
921 memset(done, 0, sizeof(done));
922 memset(bytes, 0, sizeof(bytes));
923
924 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
925 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
926
927 desc = mtk_qdma_phys_to_virt(ring, cpu);
928
929 while ((cpu != dma) && budget) {
930 u32 next_cpu = desc->txd2;
931 int mac;
932
933 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
934 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
935 break;
936
937 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
938 TX_DMA_FPORT_MASK;
939 mac--;
940
941 tx_buf = mtk_desc_to_tx_buf(ring, desc);
942 skb = tx_buf->skb;
943 if (!skb) {
944 condition = 1;
945 break;
946 }
947
948 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
949 bytes[mac] += skb->len;
950 done[mac]++;
951 budget--;
952 }
55a4e778 953 mtk_tx_unmap(eth, tx_buf);
656e7052 954
656e7052
JC		 955 ring->last_free = desc;
956 atomic_inc(&ring->free_count);
957
958 cpu = next_cpu;
959 }
960
961 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
962
963 for (i = 0; i < MTK_MAC_COUNT; i++) {
964 if (!eth->netdev[i] || !done[i])
965 continue;
966 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
967 total += done[i];
968 }
969
ad3cba98
JC		 970 if (mtk_queue_stopped(eth) &&
971 (atomic_read(&ring->free_count) > ring->thresh))
13c822f6 972 mtk_wake_queue(eth);
656e7052
JC		 973
974 return total;
975}
976
80673029 977static void mtk_handle_status_irq(struct mtk_eth *eth)
656e7052 978{
80673029 979 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
656e7052 980
eece71e8 981 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
656e7052 982 mtk_stats_update(eth);
eece71e8
JC		 983 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
984 MTK_INT_STATUS2);
656e7052 985 }
80673029
JC		 986}
987
988static int mtk_napi_tx(struct napi_struct *napi, int budget)
989{
990 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
991 u32 status, mask;
992 int tx_done = 0;
993
994 mtk_handle_status_irq(eth);
995 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
996 tx_done = mtk_poll_tx(eth, budget);
997
998 if (unlikely(netif_msg_intr(eth))) {
999 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1000 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1001 dev_info(eth->dev,
1002 "done tx %d, intr 0x%08x/0x%x\n",
1003 tx_done, status, mask);
1004 }
1005
1006 if (tx_done == budget)
1007 return budget;
1008
1009 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1010 if (status & MTK_TX_DONE_INT)
1011 return budget;
1012
1013 napi_complete(napi);
bacfd110 1014 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
80673029
JC		 1015
1016 return tx_done;
1017}
1018
1019static int mtk_napi_rx(struct napi_struct *napi, int budget)
1020{
1021 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1022 u32 status, mask;
1023 int rx_done = 0;
41156cea 1024 int remain_budget = budget;
80673029
JC		 1025
1026 mtk_handle_status_irq(eth);
41156cea
SW		 1027
1028poll_again:
bacfd110 1029 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
41156cea 1030 rx_done = mtk_poll_rx(napi, remain_budget, eth);
656e7052
JC		 1031
1032 if (unlikely(netif_msg_intr(eth))) {
bacfd110
NC		 1033 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1034 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
80673029
JC		 1035 dev_info(eth->dev,
1036 "done rx %d, intr 0x%08x/0x%x\n",
1037 rx_done, status, mask);
656e7052 1038 }
41156cea 1039 if (rx_done == remain_budget)
656e7052
JC		 1040 return budget;
1041
bacfd110 1042 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
41156cea
SW		 1043 if (status & MTK_RX_DONE_INT) {
1044 remain_budget -= rx_done;
1045 goto poll_again;
1046 }
656e7052 1047 napi_complete(napi);
bacfd110 1048 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052 1049
41156cea 1050 return rx_done + budget - remain_budget;
656e7052
JC		 1051}
1052
1053static int mtk_tx_alloc(struct mtk_eth *eth)
1054{
1055 struct mtk_tx_ring *ring = &eth->tx_ring;
1056 int i, sz = sizeof(*ring->dma);
1057
1058 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1059 GFP_KERNEL);
1060 if (!ring->buf)
1061 goto no_tx_mem;
1062
1063 ring->dma = dma_alloc_coherent(eth->dev,
1064 MTK_DMA_SIZE * sz,
1065 &ring->phys,
1066 GFP_ATOMIC | __GFP_ZERO);
1067 if (!ring->dma)
1068 goto no_tx_mem;
1069
1070 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1071 for (i = 0; i < MTK_DMA_SIZE; i++) {
1072 int next = (i + 1) % MTK_DMA_SIZE;
1073 u32 next_ptr = ring->phys + next * sz;
1074
1075 ring->dma[i].txd2 = next_ptr;
1076 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1077 }
1078
1079 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1080 ring->next_free = &ring->dma[0];
12c97c13 1081 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
04698ccc 1082 ring->thresh = MAX_SKB_FRAGS;
656e7052
JC		 1083
1084 /* make sure that all changes to the dma ring are flushed before we
1085 * continue
1086 */
1087 wmb();
1088
1089 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1090 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1091 mtk_w32(eth,
1092 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1093 MTK_QTX_CRX_PTR);
1094 mtk_w32(eth,
1095 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1096 MTK_QTX_DRX_PTR);
bacfd110 1097 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
656e7052
JC		 1098
1099 return 0;
1100
1101no_tx_mem:
1102 return -ENOMEM;
1103}
1104
1105static void mtk_tx_clean(struct mtk_eth *eth)
1106{
1107 struct mtk_tx_ring *ring = &eth->tx_ring;
1108 int i;
1109
1110 if (ring->buf) {
1111 for (i = 0; i < MTK_DMA_SIZE; i++)
55a4e778 1112 mtk_tx_unmap(eth, &ring->buf[i]);
656e7052
JC		 1113 kfree(ring->buf);
1114 ring->buf = NULL;
1115 }
1116
1117 if (ring->dma) {
1118 dma_free_coherent(eth->dev,
1119 MTK_DMA_SIZE * sizeof(*ring->dma),
1120 ring->dma,
1121 ring->phys);
1122 ring->dma = NULL;
1123 }
1124}
1125
1126static int mtk_rx_alloc(struct mtk_eth *eth)
1127{
1128 struct mtk_rx_ring *ring = &eth->rx_ring;
1129 int i;
1130
1131 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1132 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1133 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1134 GFP_KERNEL);
1135 if (!ring->data)
1136 return -ENOMEM;
1137
1138 for (i = 0; i < MTK_DMA_SIZE; i++) {
1139 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1140 if (!ring->data[i])
1141 return -ENOMEM;
1142 }
1143
1144 ring->dma = dma_alloc_coherent(eth->dev,
1145 MTK_DMA_SIZE * sizeof(*ring->dma),
1146 &ring->phys,
1147 GFP_ATOMIC | __GFP_ZERO);
1148 if (!ring->dma)
1149 return -ENOMEM;
1150
1151 for (i = 0; i < MTK_DMA_SIZE; i++) {
1152 dma_addr_t dma_addr = dma_map_single(eth->dev,
1153 ring->data[i] + NET_SKB_PAD,
1154 ring->buf_size,
1155 DMA_FROM_DEVICE);
1156 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1157 return -ENOMEM;
1158 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1159
1160 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1161 }
1162 ring->calc_idx = MTK_DMA_SIZE - 1;
1163 /* make sure that all changes to the dma ring are flushed before we
1164 * continue
1165 */
1166 wmb();
1167
bacfd110
NC		 1168 mtk_w32(eth, eth->rx_ring.phys, MTK_PRX_BASE_PTR0);
1169 mtk_w32(eth, MTK_DMA_SIZE, MTK_PRX_MAX_CNT0);
1170 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_PRX_CRX_IDX0);
1171 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_PDMA_RST_IDX);
656e7052
JC		 1172
1173 return 0;
1174}
1175
1176static void mtk_rx_clean(struct mtk_eth *eth)
1177{
1178 struct mtk_rx_ring *ring = &eth->rx_ring;
1179 int i;
1180
1181 if (ring->data && ring->dma) {
1182 for (i = 0; i < MTK_DMA_SIZE; i++) {
1183 if (!ring->data[i])
1184 continue;
1185 if (!ring->dma[i].rxd1)
1186 continue;
1187 dma_unmap_single(eth->dev,
1188 ring->dma[i].rxd1,
1189 ring->buf_size,
1190 DMA_FROM_DEVICE);
1191 skb_free_frag(ring->data[i]);
1192 }
1193 kfree(ring->data);
1194 ring->data = NULL;
1195 }
1196
1197 if (ring->dma) {
1198 dma_free_coherent(eth->dev,
1199 MTK_DMA_SIZE * sizeof(*ring->dma),
1200 ring->dma,
1201 ring->phys);
1202 ring->dma = NULL;
1203 }
1204}
1205
1206/* wait for DMA to finish whatever it is doing before we start using it again */
1207static int mtk_dma_busy_wait(struct mtk_eth *eth)
1208{
1209 unsigned long t_start = jiffies;
1210
1211 while (1) {
1212 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1213 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1214 return 0;
1215 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1216 break;
1217 }
1218
1219 dev_err(eth->dev, "DMA init timeout\n");
1220 return -1;
1221}
1222
1223static int mtk_dma_init(struct mtk_eth *eth)
1224{
1225 int err;
1226
1227 if (mtk_dma_busy_wait(eth))
1228 return -EBUSY;
1229
1230 /* QDMA needs scratch memory for internal reordering of the
1231 * descriptors
1232 */
1233 err = mtk_init_fq_dma(eth);
1234 if (err)
1235 return err;
1236
1237 err = mtk_tx_alloc(eth);
1238 if (err)
1239 return err;
1240
1241 err = mtk_rx_alloc(eth);
1242 if (err)
1243 return err;
1244
1245 /* Enable random early drop and set drop threshold automatically */
1246 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1247 MTK_QDMA_FC_THRES);
1248 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1249
1250 return 0;
1251}
1252
1253static void mtk_dma_free(struct mtk_eth *eth)
1254{
1255 int i;
1256
1257 for (i = 0; i < MTK_MAC_COUNT; i++)
1258 if (eth->netdev[i])
1259 netdev_reset_queue(eth->netdev[i]);
605e4fe4
JC		 1260 if (eth->scratch_ring) {
1261 dma_free_coherent(eth->dev,
1262 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1263 eth->scratch_ring,
1264 eth->phy_scratch_ring);
1265 eth->scratch_ring = NULL;
1266 eth->phy_scratch_ring = 0;
1267 }
656e7052
JC		 1268 mtk_tx_clean(eth);
1269 mtk_rx_clean(eth);
1270 kfree(eth->scratch_head);
1271}
1272
1273static void mtk_tx_timeout(struct net_device *dev)
1274{
1275 struct mtk_mac *mac = netdev_priv(dev);
1276 struct mtk_eth *eth = mac->hw;
1277
1278 eth->netdev[mac->id]->stats.tx_errors++;
1279 netif_err(eth, tx_err, dev,
1280 "transmit timed out\n");
7c78b4ad 1281 schedule_work(&eth->pending_work);
656e7052
JC		 1282}
1283
80673029 1284static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
656e7052
JC		 1285{
1286 struct mtk_eth *eth = _eth;
656e7052 1287
80673029
JC		 1288 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1289 __napi_schedule(&eth->rx_napi);
bacfd110 1290 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
80673029 1291 }
656e7052 1292
80673029
JC		 1293 return IRQ_HANDLED;
1294}
1295
1296static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1297{
1298 struct mtk_eth *eth = _eth;
1299
1300 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1301 __napi_schedule(&eth->tx_napi);
bacfd110 1302 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
656e7052 1303 }
656e7052
JC		 1304
1305 return IRQ_HANDLED;
1306}
1307
1308#ifdef CONFIG_NET_POLL_CONTROLLER
1309static void mtk_poll_controller(struct net_device *dev)
1310{
1311 struct mtk_mac *mac = netdev_priv(dev);
1312 struct mtk_eth *eth = mac->hw;
656e7052 1313
bacfd110
NC		 1314 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1315 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
8186f6e3 1316 mtk_handle_irq_rx(eth->irq[2], dev);
bacfd110
NC		 1317 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1318 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052
JC		 1319}
1320#endif
1321
1322static int mtk_start_dma(struct mtk_eth *eth)
1323{
1324 int err;
1325
1326 err = mtk_dma_init(eth);
1327 if (err) {
1328 mtk_dma_free(eth);
1329 return err;
1330 }
1331
1332 mtk_w32(eth,
bacfd110
NC		 1333 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1334 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
656e7052
JC		 1335 MTK_QDMA_GLO_CFG);
1336
bacfd110
NC		 1337 mtk_w32(eth,
1338 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1339 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1340 MTK_PDMA_GLO_CFG);
1341
656e7052
JC		 1342 return 0;
1343}
1344
1345static int mtk_open(struct net_device *dev)
1346{
1347 struct mtk_mac *mac = netdev_priv(dev);
1348 struct mtk_eth *eth = mac->hw;
1349
1350 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1351 if (!atomic_read(&eth->dma_refcnt)) {
1352 int err = mtk_start_dma(eth);
1353
1354 if (err)
1355 return err;
1356
80673029 1357 napi_enable(&eth->tx_napi);
656e7052 1358 napi_enable(&eth->rx_napi);
bacfd110
NC		 1359 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1360 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052
JC		 1361 }
1362 atomic_inc(&eth->dma_refcnt);
1363
1364 phy_start(mac->phy_dev);
1365 netif_start_queue(dev);
1366
1367 return 0;
1368}
1369
1370static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1371{
656e7052
JC		 1372 u32 val;
1373 int i;
1374
1375 /* stop the dma engine */
e3e9652a 1376 spin_lock_bh(&eth->page_lock);
656e7052
JC		 1377 val = mtk_r32(eth, glo_cfg);
1378 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1379 glo_cfg);
e3e9652a 1380 spin_unlock_bh(&eth->page_lock);
656e7052
JC		 1381
1382 /* wait for dma stop */
1383 for (i = 0; i < 10; i++) {
1384 val = mtk_r32(eth, glo_cfg);
1385 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1386 msleep(20);
1387 continue;
1388 }
1389 break;
1390 }
1391}
1392
1393static int mtk_stop(struct net_device *dev)
1394{
1395 struct mtk_mac *mac = netdev_priv(dev);
1396 struct mtk_eth *eth = mac->hw;
1397
1398 netif_tx_disable(dev);
1399 phy_stop(mac->phy_dev);
1400
1401 /* only shutdown DMA if this is the last user */
1402 if (!atomic_dec_and_test(&eth->dma_refcnt))
1403 return 0;
1404
bacfd110
NC		 1405 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1406 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
80673029 1407 napi_disable(&eth->tx_napi);
656e7052
JC		 1408 napi_disable(&eth->rx_napi);
1409
1410 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1411
1412 mtk_dma_free(eth);
1413
1414 return 0;
1415}
1416
2a8307aa
SW		 1417static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1418{
1419 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1420 reset_bits,
1421 reset_bits);
1422
1423 usleep_range(1000, 1100);
1424 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1425 reset_bits,
1426 ~reset_bits);
1427 mdelay(10);
1428}
1429
9ea4d311 1430static int mtk_hw_init(struct mtk_eth *eth)
656e7052 1431{
9ea4d311
SW		 1432 int i, val;
1433
1434 if (test_and_set_bit(MTK_HW_INIT, &eth->state))
1435 return 0;
85574dbf 1436
26a2ad8a
SW		 1437 pm_runtime_enable(eth->dev);
1438 pm_runtime_get_sync(eth->dev);
1439
85574dbf
SW		 1440 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);
1441 clk_prepare_enable(eth->clks[MTK_CLK_ESW]);
1442 clk_prepare_enable(eth->clks[MTK_CLK_GP1]);
1443 clk_prepare_enable(eth->clks[MTK_CLK_GP2]);
2a8307aa
SW		 1444 ethsys_reset(eth, RSTCTRL_FE);
1445 ethsys_reset(eth, RSTCTRL_PPE);
656e7052 1446
9ea4d311
SW		 1447 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1448 for (i = 0; i < MTK_MAC_COUNT; i++) {
1449 if (!eth->mac[i])
1450 continue;
1451 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1452 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1453 }
1454 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1455
656e7052
JC		 1456 /* Set GE2 driving and slew rate */
1457 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1458
1459 /* set GE2 TDSEL */
1460 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1461
1462 /* set GE2 TUNE */
1463 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1464
1465 /* GE1, Force 1000M/FD, FC ON */
1466 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1467
1468 /* GE2, Force 1000M/FD, FC ON */
1469 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1470
1471 /* Enable RX VLan Offloading */
1472 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1473
656e7052
JC		 1474 /* disable delay and normal interrupt */
1475 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
bacfd110
NC		 1476 mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
1477 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1478 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
656e7052
JC		 1479 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1480 mtk_w32(eth, 0, MTK_RST_GL);
1481
1482 /* FE int grouping */
80673029
JC		 1483 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1484 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1485 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1486 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1487 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
656e7052
JC		 1488
1489 for (i = 0; i < 2; i++) {
1490 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1491
9c08435e 1492 /* setup the forward port to send frame to PDMA */
656e7052 1493 val &= ~0xffff;
656e7052
JC		 1494
1495 /* Enable RX checksum */
1496 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1497
1498 /* setup the mac dma */
1499 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1500 }
1501
1502 return 0;
1503}
1504
bf253fb7
SW		 1505static int mtk_hw_deinit(struct mtk_eth *eth)
1506{
9ea4d311
SW		 1507 if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
1508 return 0;
1509
bf253fb7
SW		 1510 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]);
1511 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]);
1512 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]);
1513 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]);
1514
26a2ad8a
SW		 1515 pm_runtime_put_sync(eth->dev);
1516 pm_runtime_disable(eth->dev);
1517
bf253fb7
SW		 1518 return 0;
1519}
1520
656e7052
JC		 1521static int __init mtk_init(struct net_device *dev)
1522{
1523 struct mtk_mac *mac = netdev_priv(dev);
1524 struct mtk_eth *eth = mac->hw;
1525 const char *mac_addr;
1526
1527 mac_addr = of_get_mac_address(mac->of_node);
1528 if (mac_addr)
1529 ether_addr_copy(dev->dev_addr, mac_addr);
1530
1531 /* If the mac address is invalid, use random mac address */
1532 if (!is_valid_ether_addr(dev->dev_addr)) {
1533 random_ether_addr(dev->dev_addr);
1534 dev_err(eth->dev, "generated random MAC address %pM\n",
1535 dev->dev_addr);
1536 dev->addr_assign_type = NET_ADDR_RANDOM;
1537 }
1538
1539 return mtk_phy_connect(mac);
1540}
1541
1542static void mtk_uninit(struct net_device *dev)
1543{
1544 struct mtk_mac *mac = netdev_priv(dev);
1545 struct mtk_eth *eth = mac->hw;
1546
1547 phy_disconnect(mac->phy_dev);
1548 mtk_mdio_cleanup(eth);
bacfd110
NC		 1549 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1550 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
80673029
JC		 1551 free_irq(eth->irq[1], dev);
1552 free_irq(eth->irq[2], dev);
656e7052
JC		 1553}
1554
1555static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1556{
1557 struct mtk_mac *mac = netdev_priv(dev);
1558
1559 switch (cmd) {
1560 case SIOCGMIIPHY:
1561 case SIOCGMIIREG:
1562 case SIOCSMIIREG:
1563 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1564 default:
1565 break;
1566 }
1567
1568 return -EOPNOTSUPP;
1569}
1570
1571static void mtk_pending_work(struct work_struct *work)
1572{
7c78b4ad 1573 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
e7d425dc
JC		 1574 int err, i;
1575 unsigned long restart = 0;
656e7052
JC		 1576
1577 rtnl_lock();
656e7052 1578
e7d425dc
JC		 1579 /* stop all devices to make sure that dma is properly shut down */
1580 for (i = 0; i < MTK_MAC_COUNT; i++) {
7c78b4ad 1581 if (!eth->netdev[i])
e7d425dc
JC		 1582 continue;
1583 mtk_stop(eth->netdev[i]);
1584 __set_bit(i, &restart);
1585 }
1586
9ea4d311
SW		 1587 /* restart underlying hardware such as power, clock, pin mux
1588 * and the connected phy
1589 */
1590 mtk_hw_deinit(eth);
1591
1592 if (eth->dev->pins)
1593 pinctrl_select_state(eth->dev->pins->p,
1594 eth->dev->pins->default_state);
1595 mtk_hw_init(eth);
1596
1597 for (i = 0; i < MTK_MAC_COUNT; i++) {
1598 if (!eth->mac[i] ||
1599 of_phy_is_fixed_link(eth->mac[i]->of_node))
1600 continue;
1601 err = phy_init_hw(eth->mac[i]->phy_dev);
1602 if (err)
1603 dev_err(eth->dev, "%s: PHY init failed.\n",
1604 eth->netdev[i]->name);
1605 }
1606
e7d425dc
JC		 1607 /* restart DMA and enable IRQs */
1608 for (i = 0; i < MTK_MAC_COUNT; i++) {
1609 if (!test_bit(i, &restart))
1610 continue;
1611 err = mtk_open(eth->netdev[i]);
1612 if (err) {
1613 netif_alert(eth, ifup, eth->netdev[i],
1614 "Driver up/down cycle failed, closing device.\n");
1615 dev_close(eth->netdev[i]);
1616 }
656e7052
JC		 1617 }
1618 rtnl_unlock();
1619}
1620
8a8a9e89 1621static int mtk_free_dev(struct mtk_eth *eth)
656e7052
JC		 1622{
1623 int i;
1624
1625 for (i = 0; i < MTK_MAC_COUNT; i++) {
656e7052
JC		 1626 if (!eth->netdev[i])
1627 continue;
8a8a9e89
SW		 1628 free_netdev(eth->netdev[i]);
1629 }
1630
1631 return 0;
1632}
656e7052 1633
8a8a9e89
SW		 1634static int mtk_unreg_dev(struct mtk_eth *eth)
1635{
1636 int i;
1637
1638 for (i = 0; i < MTK_MAC_COUNT; i++) {
1639 if (!eth->netdev[i])
1640 continue;
656e7052 1641 unregister_netdev(eth->netdev[i]);
656e7052 1642 }
8a8a9e89
SW		 1643
1644 return 0;
1645}
1646
1647static int mtk_cleanup(struct mtk_eth *eth)
1648{
1649 mtk_unreg_dev(eth);
1650 mtk_free_dev(eth);
7c78b4ad 1651 cancel_work_sync(&eth->pending_work);
656e7052
JC		 1652
1653 return 0;
1654}
1655
1656static int mtk_get_settings(struct net_device *dev,
1657 struct ethtool_cmd *cmd)
1658{
1659 struct mtk_mac *mac = netdev_priv(dev);
1660 int err;
1661
1662 err = phy_read_status(mac->phy_dev);
1663 if (err)
1664 return -ENODEV;
1665
1666 return phy_ethtool_gset(mac->phy_dev, cmd);
1667}
1668
1669static int mtk_set_settings(struct net_device *dev,
1670 struct ethtool_cmd *cmd)
1671{
1672 struct mtk_mac *mac = netdev_priv(dev);
1673
1674 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1675 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1676 cmd->phy_address);
1677 if (!mac->phy_dev)
1678 return -ENODEV;
1679 }
1680
1681 return phy_ethtool_sset(mac->phy_dev, cmd);
1682}
1683
1684static void mtk_get_drvinfo(struct net_device *dev,
1685 struct ethtool_drvinfo *info)
1686{
1687 struct mtk_mac *mac = netdev_priv(dev);
1688
1689 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1690 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1691 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1692}
1693
1694static u32 mtk_get_msglevel(struct net_device *dev)
1695{
1696 struct mtk_mac *mac = netdev_priv(dev);
1697
1698 return mac->hw->msg_enable;
1699}
1700
1701static void mtk_set_msglevel(struct net_device *dev, u32 value)
1702{
1703 struct mtk_mac *mac = netdev_priv(dev);
1704
1705 mac->hw->msg_enable = value;
1706}
1707
1708static int mtk_nway_reset(struct net_device *dev)
1709{
1710 struct mtk_mac *mac = netdev_priv(dev);
1711
1712 return genphy_restart_aneg(mac->phy_dev);
1713}
1714
1715static u32 mtk_get_link(struct net_device *dev)
1716{
1717 struct mtk_mac *mac = netdev_priv(dev);
1718 int err;
1719
1720 err = genphy_update_link(mac->phy_dev);
1721 if (err)
1722 return ethtool_op_get_link(dev);
1723
1724 return mac->phy_dev->link;
1725}
1726
1727static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1728{
1729 int i;
1730
1731 switch (stringset) {
1732 case ETH_SS_STATS:
1733 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1734 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1735 data += ETH_GSTRING_LEN;
1736 }
1737 break;
1738 }
1739}
1740
1741static int mtk_get_sset_count(struct net_device *dev, int sset)
1742{
1743 switch (sset) {
1744 case ETH_SS_STATS:
1745 return ARRAY_SIZE(mtk_ethtool_stats);
1746 default:
1747 return -EOPNOTSUPP;
1748 }
1749}
1750
1751static void mtk_get_ethtool_stats(struct net_device *dev,
1752 struct ethtool_stats *stats, u64 *data)
1753{
1754 struct mtk_mac *mac = netdev_priv(dev);
1755 struct mtk_hw_stats *hwstats = mac->hw_stats;
1756 u64 *data_src, *data_dst;
1757 unsigned int start;
1758 int i;
1759
1760 if (netif_running(dev) && netif_device_present(dev)) {
1761 if (spin_trylock(&hwstats->stats_lock)) {
1762 mtk_stats_update_mac(mac);
1763 spin_unlock(&hwstats->stats_lock);
1764 }
1765 }
1766
1767 do {
bacfd110 1768 data_src = (u64 *)hwstats;
656e7052
JC		 1769 data_dst = data;
1770 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1771
1772 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1773 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1774 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1775}
1776
6a38cb15 1777static const struct ethtool_ops mtk_ethtool_ops = {
656e7052
JC		 1778 .get_settings = mtk_get_settings,
1779 .set_settings = mtk_set_settings,
1780 .get_drvinfo = mtk_get_drvinfo,
1781 .get_msglevel = mtk_get_msglevel,
1782 .set_msglevel = mtk_set_msglevel,
1783 .nway_reset = mtk_nway_reset,
1784 .get_link = mtk_get_link,
1785 .get_strings = mtk_get_strings,
1786 .get_sset_count = mtk_get_sset_count,
1787 .get_ethtool_stats = mtk_get_ethtool_stats,
1788};
1789
1790static const struct net_device_ops mtk_netdev_ops = {
1791 .ndo_init = mtk_init,
1792 .ndo_uninit = mtk_uninit,
1793 .ndo_open = mtk_open,
1794 .ndo_stop = mtk_stop,
1795 .ndo_start_xmit = mtk_start_xmit,
1796 .ndo_set_mac_address = mtk_set_mac_address,
1797 .ndo_validate_addr = eth_validate_addr,
1798 .ndo_do_ioctl = mtk_do_ioctl,
1799 .ndo_change_mtu = eth_change_mtu,
1800 .ndo_tx_timeout = mtk_tx_timeout,
1801 .ndo_get_stats64 = mtk_get_stats64,
1802#ifdef CONFIG_NET_POLL_CONTROLLER
1803 .ndo_poll_controller = mtk_poll_controller,
1804#endif
1805};
1806
1807static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1808{
1809 struct mtk_mac *mac;
1810 const __be32 *_id = of_get_property(np, "reg", NULL);
1811 int id, err;
1812
1813 if (!_id) {
1814 dev_err(eth->dev, "missing mac id\n");
1815 return -EINVAL;
1816 }
1817
1818 id = be32_to_cpup(_id);
1819 if (id >= MTK_MAC_COUNT) {
1820 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1821 return -EINVAL;
1822 }
1823
1824 if (eth->netdev[id]) {
1825 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1826 return -EINVAL;
1827 }
1828
1829 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1830 if (!eth->netdev[id]) {
1831 dev_err(eth->dev, "alloc_etherdev failed\n");
1832 return -ENOMEM;
1833 }
1834 mac = netdev_priv(eth->netdev[id]);
1835 eth->mac[id] = mac;
1836 mac->id = id;
1837 mac->hw = eth;
1838 mac->of_node = np;
656e7052
JC		 1839
1840 mac->hw_stats = devm_kzalloc(eth->dev,
1841 sizeof(*mac->hw_stats),
1842 GFP_KERNEL);
1843 if (!mac->hw_stats) {
1844 dev_err(eth->dev, "failed to allocate counter memory\n");
1845 err = -ENOMEM;
1846 goto free_netdev;
1847 }
1848 spin_lock_init(&mac->hw_stats->stats_lock);
d7005652 1849 u64_stats_init(&mac->hw_stats->syncp);
656e7052
JC		 1850 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1851
1852 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
eaadf9fd 1853 eth->netdev[id]->watchdog_timeo = 5 * HZ;
656e7052
JC		 1854 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1855 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1856 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1857 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1858 eth->netdev[id]->features |= MTK_HW_FEATURES;
1859 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1860
80673029 1861 eth->netdev[id]->irq = eth->irq[0];
656e7052
JC		 1862 return 0;
1863
1864free_netdev:
1865 free_netdev(eth->netdev[id]);
1866 return err;
1867}
1868
1869static int mtk_probe(struct platform_device *pdev)
1870{
1871 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1872 struct device_node *mac_np;
1873 const struct of_device_id *match;
1874 struct mtk_soc_data *soc;
1875 struct mtk_eth *eth;
1876 int err;
80673029 1877 int i;
656e7052 1878
656e7052
JC		 1879 match = of_match_device(of_mtk_match, &pdev->dev);
1880 soc = (struct mtk_soc_data *)match->data;
1881
1882 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1883 if (!eth)
1884 return -ENOMEM;
1885
549e5495 1886 eth->dev = &pdev->dev;
656e7052 1887 eth->base = devm_ioremap_resource(&pdev->dev, res);
621e49f6
VZ		 1888 if (IS_ERR(eth->base))
1889 return PTR_ERR(eth->base);
656e7052
JC		 1890
1891 spin_lock_init(&eth->page_lock);
7bc9ccec 1892 spin_lock_init(&eth->irq_lock);
656e7052
JC		 1893
1894 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1895 "mediatek,ethsys");
1896 if (IS_ERR(eth->ethsys)) {
1897 dev_err(&pdev->dev, "no ethsys regmap found\n");
1898 return PTR_ERR(eth->ethsys);
1899 }
1900
1901 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1902 "mediatek,pctl");
1903 if (IS_ERR(eth->pctl)) {
1904 dev_err(&pdev->dev, "no pctl regmap found\n");
1905 return PTR_ERR(eth->pctl);
1906 }
1907
80673029
JC		 1908 for (i = 0; i < 3; i++) {
1909 eth->irq[i] = platform_get_irq(pdev, i);
1910 if (eth->irq[i] < 0) {
1911 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
1912 return -ENXIO;
1913 }
656e7052 1914 }
549e5495
SW		 1915 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
1916 eth->clks[i] = devm_clk_get(eth->dev,
1917 mtk_clks_source_name[i]);
1918 if (IS_ERR(eth->clks[i])) {
1919 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
1920 return -EPROBE_DEFER;
1921 return -ENODEV;
1922 }
1923 }
656e7052 1924
656e7052 1925 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
7c78b4ad 1926 INIT_WORK(&eth->pending_work, mtk_pending_work);
656e7052
JC		 1927
1928 err = mtk_hw_init(eth);
1929 if (err)
1930 return err;
1931
1932 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1933 if (!of_device_is_compatible(mac_np,
1934 "mediatek,eth-mac"))
1935 continue;
1936
1937 if (!of_device_is_available(mac_np))
1938 continue;
1939
1940 err = mtk_add_mac(eth, mac_np);
1941 if (err)
8a8a9e89 1942 goto err_deinit_hw;
656e7052
JC		 1943 }
1944
85574dbf
SW		 1945 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
1946 dev_name(eth->dev), eth);
1947 if (err)
1948 goto err_free_dev;
1949
1950 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
1951 dev_name(eth->dev), eth);
1952 if (err)
1953 goto err_free_dev;
1954
1955 err = mtk_mdio_init(eth);
1956 if (err)
1957 goto err_free_dev;
1958
1959 for (i = 0; i < MTK_MAX_DEVS; i++) {
1960 if (!eth->netdev[i])
1961 continue;
1962
1963 err = register_netdev(eth->netdev[i]);
1964 if (err) {
1965 dev_err(eth->dev, "error bringing up device\n");
8a8a9e89 1966 goto err_deinit_mdio;
85574dbf
SW		 1967 } else
1968 netif_info(eth, probe, eth->netdev[i],
1969 "mediatek frame engine at 0x%08lx, irq %d\n",
1970 eth->netdev[i]->base_addr, eth->irq[0]);
1971 }
1972
656e7052
JC		 1973 /* we run 2 devices on the same DMA ring so we need a dummy device
1974 * for NAPI to work
1975 */
1976 init_dummy_netdev(&eth->dummy_dev);
80673029
JC		 1977 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
1978 MTK_NAPI_WEIGHT);
1979 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
656e7052
JC		 1980 MTK_NAPI_WEIGHT);
1981
1982 platform_set_drvdata(pdev, eth);
1983
1984 return 0;
1985
8a8a9e89
SW		 1986err_deinit_mdio:
1987 mtk_mdio_cleanup(eth);
656e7052 1988err_free_dev:
8a8a9e89
SW		 1989 mtk_free_dev(eth);
1990err_deinit_hw:
1991 mtk_hw_deinit(eth);
1992
656e7052
JC		 1993 return err;
1994}
1995
1996static int mtk_remove(struct platform_device *pdev)
1997{
1998 struct mtk_eth *eth = platform_get_drvdata(pdev);
79e9a414
SW		 1999 int i;
2000
2001 /* stop all devices to make sure that dma is properly shut down */
2002 for (i = 0; i < MTK_MAC_COUNT; i++) {
2003 if (!eth->netdev[i])
2004 continue;
2005 mtk_stop(eth->netdev[i]);
2006 }
656e7052 2007
bf253fb7 2008 mtk_hw_deinit(eth);
656e7052 2009
80673029 2010 netif_napi_del(&eth->tx_napi);
656e7052
JC		 2011 netif_napi_del(&eth->rx_napi);
2012 mtk_cleanup(eth);
656e7052
JC		 2013
2014 return 0;
2015}
2016
2017const struct of_device_id of_mtk_match[] = {
2018 { .compatible = "mediatek,mt7623-eth" },
2019 {},
2020};
2021
2022static struct platform_driver mtk_driver = {
2023 .probe = mtk_probe,
2024 .remove = mtk_remove,
2025 .driver = {
2026 .name = "mtk_soc_eth",
656e7052
JC		 2027 .of_match_table = of_mtk_match,
2028 },
2029};
2030
2031module_platform_driver(mtk_driver);
2032
2033MODULE_LICENSE("GPL");
2034MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2035MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux 6.x block layer and io_uring tree(s)