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net: mediatek: fix threshold value
[linux-2.6-block.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
21#include <linux/if_vlan.h>
22#include <linux/reset.h>
23#include <linux/tcp.h>
24
25#include "mtk_eth_soc.h"
26
27static int mtk_msg_level = -1;
28module_param_named(msg_level, mtk_msg_level, int, 0);
29MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31#define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34/* strings used by ethtool */
35static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38} mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51};
52
53void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54{
55 __raw_writel(val, eth->base + reg);
56}
57
58u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59{
60 return __raw_readl(eth->base + reg);
61}
62
63static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64{
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77}
78
79u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
81{
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96}
97
98u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
99{
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116}
117
118static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120{
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124}
125
126static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127{
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131}
132
133static void mtk_phy_link_adjust(struct net_device *dev)
134{
135 struct mtk_mac *mac = netdev_priv(dev);
08ef55c6
JC		 136 u16 lcl_adv = 0, rmt_adv = 0;
137 u8 flowctrl;
656e7052
JC		 138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
141 MAC_MCR_BACKPR_EN;
142
143 switch (mac->phy_dev->speed) {
144 case SPEED_1000:
145 mcr |= MAC_MCR_SPEED_1000;
146 break;
147 case SPEED_100:
148 mcr |= MAC_MCR_SPEED_100;
149 break;
150 };
151
152 if (mac->phy_dev->link)
153 mcr |= MAC_MCR_FORCE_LINK;
154
08ef55c6 155 if (mac->phy_dev->duplex) {
656e7052
JC		 156 mcr |= MAC_MCR_FORCE_DPX;
157
08ef55c6
JC		 158 if (mac->phy_dev->pause)
159 rmt_adv = LPA_PAUSE_CAP;
160 if (mac->phy_dev->asym_pause)
161 rmt_adv |= LPA_PAUSE_ASYM;
162
163 if (mac->phy_dev->advertising & ADVERTISED_Pause)
164 lcl_adv |= ADVERTISE_PAUSE_CAP;
165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
166 lcl_adv |= ADVERTISE_PAUSE_ASYM;
167
168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
169
170 if (flowctrl & FLOW_CTRL_TX)
171 mcr |= MAC_MCR_FORCE_TX_FC;
172 if (flowctrl & FLOW_CTRL_RX)
173 mcr |= MAC_MCR_FORCE_RX_FC;
174
175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
178 }
656e7052
JC		 179
180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
181
182 if (mac->phy_dev->link)
183 netif_carrier_on(dev);
184 else
185 netif_carrier_off(dev);
186}
187
188static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
189 struct device_node *phy_node)
190{
191 const __be32 *_addr = NULL;
192 struct phy_device *phydev;
193 int phy_mode, addr;
194
195 _addr = of_get_property(phy_node, "reg", NULL);
196
197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
198 pr_err("%s: invalid phy address\n", phy_node->name);
199 return -EINVAL;
200 }
201 addr = be32_to_cpu(*_addr);
202 phy_mode = of_get_phy_mode(phy_node);
203 if (phy_mode < 0) {
204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
205 return -EINVAL;
206 }
207
208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
209 mtk_phy_link_adjust, 0, phy_mode);
977bc20c 210 if (!phydev) {
656e7052 211 dev_err(eth->dev, "could not connect to PHY\n");
977bc20c 212 return -ENODEV;
656e7052
JC		 213 }
214
215 dev_info(eth->dev,
216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
217 mac->id, phydev_name(phydev), phydev->phy_id,
218 phydev->drv->name);
219
220 mac->phy_dev = phydev;
221
222 return 0;
223}
224
225static int mtk_phy_connect(struct mtk_mac *mac)
226{
227 struct mtk_eth *eth = mac->hw;
228 struct device_node *np;
229 u32 val, ge_mode;
230
231 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
0c72c50f
JC		 232 if (!np && of_phy_is_fixed_link(mac->of_node))
233 if (!of_phy_register_fixed_link(mac->of_node))
234 np = of_node_get(mac->of_node);
656e7052
JC		 235 if (!np)
236 return -ENODEV;
237
238 switch (of_get_phy_mode(np)) {
37920fce
JC		 239 case PHY_INTERFACE_MODE_RGMII_TXID:
240 case PHY_INTERFACE_MODE_RGMII_RXID:
241 case PHY_INTERFACE_MODE_RGMII_ID:
656e7052
JC		 242 case PHY_INTERFACE_MODE_RGMII:
243 ge_mode = 0;
244 break;
245 case PHY_INTERFACE_MODE_MII:
246 ge_mode = 1;
247 break;
248 case PHY_INTERFACE_MODE_RMII:
249 ge_mode = 2;
250 break;
251 default:
252 dev_err(eth->dev, "invalid phy_mode\n");
253 return -1;
254 }
255
256 /* put the gmac into the right mode */
257 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
258 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
259 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
260 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
261
262 mtk_phy_connect_node(eth, mac, np);
263 mac->phy_dev->autoneg = AUTONEG_ENABLE;
264 mac->phy_dev->speed = 0;
265 mac->phy_dev->duplex = 0;
08ef55c6
JC		 266 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
267 SUPPORTED_Asym_Pause;
656e7052
JC		 268 mac->phy_dev->advertising = mac->phy_dev->supported |
269 ADVERTISED_Autoneg;
270 phy_start_aneg(mac->phy_dev);
271
272 return 0;
273}
274
275static int mtk_mdio_init(struct mtk_eth *eth)
276{
277 struct device_node *mii_np;
278 int err;
279
280 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
281 if (!mii_np) {
282 dev_err(eth->dev, "no %s child node found", "mdio-bus");
283 return -ENODEV;
284 }
285
286 if (!of_device_is_available(mii_np)) {
287 err = 0;
288 goto err_put_node;
289 }
290
291 eth->mii_bus = mdiobus_alloc();
292 if (!eth->mii_bus) {
293 err = -ENOMEM;
294 goto err_put_node;
295 }
296
297 eth->mii_bus->name = "mdio";
298 eth->mii_bus->read = mtk_mdio_read;
299 eth->mii_bus->write = mtk_mdio_write;
300 eth->mii_bus->priv = eth;
301 eth->mii_bus->parent = eth->dev;
302
303 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
304 err = of_mdiobus_register(eth->mii_bus, mii_np);
305 if (err)
306 goto err_free_bus;
307
308 return 0;
309
310err_free_bus:
207bdf18 311 mdiobus_free(eth->mii_bus);
656e7052
JC		 312
313err_put_node:
314 of_node_put(mii_np);
315 eth->mii_bus = NULL;
316 return err;
317}
318
319static void mtk_mdio_cleanup(struct mtk_eth *eth)
320{
321 if (!eth->mii_bus)
322 return;
323
324 mdiobus_unregister(eth->mii_bus);
325 of_node_put(eth->mii_bus->dev.of_node);
207bdf18 326 mdiobus_free(eth->mii_bus);
656e7052
JC		 327}
328
329static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
330{
331 u32 val;
332
333 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
334 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
335 /* flush write */
336 mtk_r32(eth, MTK_QDMA_INT_MASK);
337}
338
339static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
340{
341 u32 val;
342
343 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
344 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
345 /* flush write */
346 mtk_r32(eth, MTK_QDMA_INT_MASK);
347}
348
349static int mtk_set_mac_address(struct net_device *dev, void *p)
350{
351 int ret = eth_mac_addr(dev, p);
352 struct mtk_mac *mac = netdev_priv(dev);
353 const char *macaddr = dev->dev_addr;
354 unsigned long flags;
355
356 if (ret)
357 return ret;
358
359 spin_lock_irqsave(&mac->hw->page_lock, flags);
360 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
361 MTK_GDMA_MAC_ADRH(mac->id));
362 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
363 (macaddr[4] << 8) | macaddr[5],
364 MTK_GDMA_MAC_ADRL(mac->id));
365 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
366
367 return 0;
368}
369
370void mtk_stats_update_mac(struct mtk_mac *mac)
371{
372 struct mtk_hw_stats *hw_stats = mac->hw_stats;
373 unsigned int base = MTK_GDM1_TX_GBCNT;
374 u64 stats;
375
376 base += hw_stats->reg_offset;
377
378 u64_stats_update_begin(&hw_stats->syncp);
379
380 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
381 stats = mtk_r32(mac->hw, base + 0x04);
382 if (stats)
383 hw_stats->rx_bytes += (stats << 32);
384 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
385 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
386 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
387 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
388 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
389 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
390 hw_stats->rx_flow_control_packets +=
391 mtk_r32(mac->hw, base + 0x24);
392 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
393 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
394 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
395 stats = mtk_r32(mac->hw, base + 0x34);
396 if (stats)
397 hw_stats->tx_bytes += (stats << 32);
398 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
399 u64_stats_update_end(&hw_stats->syncp);
400}
401
402static void mtk_stats_update(struct mtk_eth *eth)
403{
404 int i;
405
406 for (i = 0; i < MTK_MAC_COUNT; i++) {
407 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
408 continue;
409 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
410 mtk_stats_update_mac(eth->mac[i]);
411 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
412 }
413 }
414}
415
416static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
417 struct rtnl_link_stats64 *storage)
418{
419 struct mtk_mac *mac = netdev_priv(dev);
420 struct mtk_hw_stats *hw_stats = mac->hw_stats;
421 unsigned int start;
422
423 if (netif_running(dev) && netif_device_present(dev)) {
424 if (spin_trylock(&hw_stats->stats_lock)) {
425 mtk_stats_update_mac(mac);
426 spin_unlock(&hw_stats->stats_lock);
427 }
428 }
429
430 do {
431 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
432 storage->rx_packets = hw_stats->rx_packets;
433 storage->tx_packets = hw_stats->tx_packets;
434 storage->rx_bytes = hw_stats->rx_bytes;
435 storage->tx_bytes = hw_stats->tx_bytes;
436 storage->collisions = hw_stats->tx_collisions;
437 storage->rx_length_errors = hw_stats->rx_short_errors +
438 hw_stats->rx_long_errors;
439 storage->rx_over_errors = hw_stats->rx_overflow;
440 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
441 storage->rx_errors = hw_stats->rx_checksum_errors;
442 storage->tx_aborted_errors = hw_stats->tx_skip;
443 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
444
445 storage->tx_errors = dev->stats.tx_errors;
446 storage->rx_dropped = dev->stats.rx_dropped;
447 storage->tx_dropped = dev->stats.tx_dropped;
448
449 return storage;
450}
451
452static inline int mtk_max_frag_size(int mtu)
453{
454 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
455 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
456 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
457
458 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
459 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
460}
461
462static inline int mtk_max_buf_size(int frag_size)
463{
464 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
465 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
466
467 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
468
469 return buf_size;
470}
471
472static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
473 struct mtk_rx_dma *dma_rxd)
474{
475 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
476 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
477 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
478 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
479}
480
481/* the qdma core needs scratch memory to be setup */
482static int mtk_init_fq_dma(struct mtk_eth *eth)
483{
605e4fe4 484 dma_addr_t phy_ring_tail;
656e7052
JC		 485 int cnt = MTK_DMA_SIZE;
486 dma_addr_t dma_addr;
487 int i;
488
489 eth->scratch_ring = dma_alloc_coherent(eth->dev,
490 cnt * sizeof(struct mtk_tx_dma),
605e4fe4 491 &eth->phy_scratch_ring,
656e7052
JC		 492 GFP_ATOMIC | __GFP_ZERO);
493 if (unlikely(!eth->scratch_ring))
494 return -ENOMEM;
495
496 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
497 GFP_KERNEL);
562c5a70
JC		 498 if (unlikely(!eth->scratch_head))
499 return -ENOMEM;
500
656e7052
JC		 501 dma_addr = dma_map_single(eth->dev,
502 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
503 DMA_FROM_DEVICE);
504 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
505 return -ENOMEM;
506
507 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
605e4fe4 508 phy_ring_tail = eth->phy_scratch_ring +
656e7052
JC		 509 (sizeof(struct mtk_tx_dma) * (cnt - 1));
510
511 for (i = 0; i < cnt; i++) {
512 eth->scratch_ring[i].txd1 =
513 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
514 if (i < cnt - 1)
605e4fe4 515 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
656e7052
JC		 516 ((i + 1) * sizeof(struct mtk_tx_dma)));
517 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
518 }
519
605e4fe4 520 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
656e7052
JC		 521 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
522 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
523 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
524
525 return 0;
526}
527
528static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
529{
530 void *ret = ring->dma;
531
532 return ret + (desc - ring->phys);
533}
534
535static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
536 struct mtk_tx_dma *txd)
537{
538 int idx = txd - ring->dma;
539
540 return &ring->buf[idx];
541}
542
543static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
544{
545 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
546 dma_unmap_single(dev,
547 dma_unmap_addr(tx_buf, dma_addr0),
548 dma_unmap_len(tx_buf, dma_len0),
549 DMA_TO_DEVICE);
550 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
551 dma_unmap_page(dev,
552 dma_unmap_addr(tx_buf, dma_addr0),
553 dma_unmap_len(tx_buf, dma_len0),
554 DMA_TO_DEVICE);
555 }
556 tx_buf->flags = 0;
557 if (tx_buf->skb &&
558 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
559 dev_kfree_skb_any(tx_buf->skb);
560 tx_buf->skb = NULL;
561}
562
563static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
564 int tx_num, struct mtk_tx_ring *ring, bool gso)
565{
566 struct mtk_mac *mac = netdev_priv(dev);
567 struct mtk_eth *eth = mac->hw;
568 struct mtk_tx_dma *itxd, *txd;
569 struct mtk_tx_buf *tx_buf;
656e7052
JC		 570 dma_addr_t mapped_addr;
571 unsigned int nr_frags;
572 int i, n_desc = 1;
573 u32 txd4 = 0;
574
575 itxd = ring->next_free;
576 if (itxd == ring->last_free)
577 return -ENOMEM;
578
579 /* set the forward port */
580 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
581
582 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
583 memset(tx_buf, 0, sizeof(*tx_buf));
584
585 if (gso)
586 txd4 |= TX_DMA_TSO;
587
588 /* TX Checksum offload */
589 if (skb->ip_summed == CHECKSUM_PARTIAL)
590 txd4 |= TX_DMA_CHKSUM;
591
592 /* VLAN header offload */
593 if (skb_vlan_tag_present(skb))
594 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
595
596 mapped_addr = dma_map_single(&dev->dev, skb->data,
597 skb_headlen(skb), DMA_TO_DEVICE);
598 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
599 return -ENOMEM;
600
656e7052
JC		 601 WRITE_ONCE(itxd->txd1, mapped_addr);
602 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
603 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
604 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
605
606 /* TX SG offload */
607 txd = itxd;
608 nr_frags = skb_shinfo(skb)->nr_frags;
609 for (i = 0; i < nr_frags; i++) {
610 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
611 unsigned int offset = 0;
612 int frag_size = skb_frag_size(frag);
613
614 while (frag_size) {
615 bool last_frag = false;
616 unsigned int frag_map_size;
617
618 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
619 if (txd == ring->last_free)
620 goto err_dma;
621
622 n_desc++;
623 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
624 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
625 frag_map_size,
626 DMA_TO_DEVICE);
627 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
628 goto err_dma;
629
630 if (i == nr_frags - 1 &&
631 (frag_size - frag_map_size) == 0)
632 last_frag = true;
633
634 WRITE_ONCE(txd->txd1, mapped_addr);
635 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
636 TX_DMA_PLEN0(frag_map_size) |
369f0453 637 last_frag * TX_DMA_LS0));
656e7052
JC		 638 WRITE_ONCE(txd->txd4, 0);
639
640 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
641 tx_buf = mtk_desc_to_tx_buf(ring, txd);
642 memset(tx_buf, 0, sizeof(*tx_buf));
643
644 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
645 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
646 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
647 frag_size -= frag_map_size;
648 offset += frag_map_size;
649 }
650 }
651
652 /* store skb to cleanup */
653 tx_buf->skb = skb;
654
655 WRITE_ONCE(itxd->txd4, txd4);
656 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
657 (!nr_frags * TX_DMA_LS0)));
658
656e7052
JC		 659 netdev_sent_queue(dev, skb->len);
660 skb_tx_timestamp(skb);
661
662 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
663 atomic_sub(n_desc, &ring->free_count);
664
665 /* make sure that all changes to the dma ring are flushed before we
666 * continue
667 */
668 wmb();
669
670 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
671 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
672
673 return 0;
674
675err_dma:
676 do {
2fae723c 677 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
656e7052
JC		 678
679 /* unmap dma */
680 mtk_tx_unmap(&dev->dev, tx_buf);
681
682 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
683 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
684 } while (itxd != txd);
685
686 return -ENOMEM;
687}
688
689static inline int mtk_cal_txd_req(struct sk_buff *skb)
690{
691 int i, nfrags;
692 struct skb_frag_struct *frag;
693
694 nfrags = 1;
695 if (skb_is_gso(skb)) {
696 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
697 frag = &skb_shinfo(skb)->frags[i];
698 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
699 }
700 } else {
701 nfrags += skb_shinfo(skb)->nr_frags;
702 }
703
beeb4ca4 704 return nfrags;
656e7052
JC		 705}
706
13c822f6
JC		 707static void mtk_wake_queue(struct mtk_eth *eth)
708{
709 int i;
710
711 for (i = 0; i < MTK_MAC_COUNT; i++) {
712 if (!eth->netdev[i])
713 continue;
714 netif_wake_queue(eth->netdev[i]);
715 }
716}
717
718static void mtk_stop_queue(struct mtk_eth *eth)
719{
720 int i;
721
722 for (i = 0; i < MTK_MAC_COUNT; i++) {
723 if (!eth->netdev[i])
724 continue;
725 netif_stop_queue(eth->netdev[i]);
726 }
727}
728
656e7052
JC		 729static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
730{
731 struct mtk_mac *mac = netdev_priv(dev);
732 struct mtk_eth *eth = mac->hw;
733 struct mtk_tx_ring *ring = &eth->tx_ring;
734 struct net_device_stats *stats = &dev->stats;
34c2e4c9 735 unsigned long flags;
656e7052
JC		 736 bool gso = false;
737 int tx_num;
738
34c2e4c9
JC		 739 /* normally we can rely on the stack not calling this more than once,
740 * however we have 2 queues running on the same ring so we need to lock
741 * the ring access
742 */
743 spin_lock_irqsave(&eth->page_lock, flags);
744
656e7052
JC		 745 tx_num = mtk_cal_txd_req(skb);
746 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
13c822f6 747 mtk_stop_queue(eth);
656e7052
JC		 748 netif_err(eth, tx_queued, dev,
749 "Tx Ring full when queue awake!\n");
34c2e4c9 750 spin_unlock_irqrestore(&eth->page_lock, flags);
656e7052
JC		 751 return NETDEV_TX_BUSY;
752 }
753
754 /* TSO: fill MSS info in tcp checksum field */
755 if (skb_is_gso(skb)) {
756 if (skb_cow_head(skb, 0)) {
757 netif_warn(eth, tx_err, dev,
758 "GSO expand head fail.\n");
759 goto drop;
760 }
761
762 if (skb_shinfo(skb)->gso_type &
763 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
764 gso = true;
765 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
766 }
767 }
768
769 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
770 goto drop;
771
772 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) {
13c822f6 773 mtk_stop_queue(eth);
656e7052
JC		 774 if (unlikely(atomic_read(&ring->free_count) >
775 ring->thresh))
13c822f6 776 mtk_wake_queue(eth);
656e7052 777 }
34c2e4c9 778 spin_unlock_irqrestore(&eth->page_lock, flags);
656e7052
JC		 779
780 return NETDEV_TX_OK;
781
782drop:
34c2e4c9 783 spin_unlock_irqrestore(&eth->page_lock, flags);
656e7052
JC		 784 stats->tx_dropped++;
785 dev_kfree_skb(skb);
786 return NETDEV_TX_OK;
787}
788
789static int mtk_poll_rx(struct napi_struct *napi, int budget,
790 struct mtk_eth *eth, u32 rx_intr)
791{
792 struct mtk_rx_ring *ring = &eth->rx_ring;
793 int idx = ring->calc_idx;
794 struct sk_buff *skb;
795 u8 *data, *new_data;
796 struct mtk_rx_dma *rxd, trxd;
797 int done = 0;
798
799 while (done < budget) {
800 struct net_device *netdev;
801 unsigned int pktlen;
802 dma_addr_t dma_addr;
803 int mac = 0;
804
805 idx = NEXT_RX_DESP_IDX(idx);
806 rxd = &ring->dma[idx];
807 data = ring->data[idx];
808
809 mtk_rx_get_desc(&trxd, rxd);
810 if (!(trxd.rxd2 & RX_DMA_DONE))
811 break;
812
813 /* find out which mac the packet come from. values start at 1 */
814 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
815 RX_DMA_FPORT_MASK;
816 mac--;
817
818 netdev = eth->netdev[mac];
819
820 /* alloc new buffer */
821 new_data = napi_alloc_frag(ring->frag_size);
822 if (unlikely(!new_data)) {
823 netdev->stats.rx_dropped++;
824 goto release_desc;
825 }
826 dma_addr = dma_map_single(&eth->netdev[mac]->dev,
827 new_data + NET_SKB_PAD,
828 ring->buf_size,
829 DMA_FROM_DEVICE);
830 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
831 skb_free_frag(new_data);
94321a9f 832 netdev->stats.rx_dropped++;
656e7052
JC		 833 goto release_desc;
834 }
835
836 /* receive data */
837 skb = build_skb(data, ring->frag_size);
838 if (unlikely(!skb)) {
839 put_page(virt_to_head_page(new_data));
94321a9f 840 netdev->stats.rx_dropped++;
656e7052
JC		 841 goto release_desc;
842 }
843 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
844
845 dma_unmap_single(&netdev->dev, trxd.rxd1,
846 ring->buf_size, DMA_FROM_DEVICE);
847 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
848 skb->dev = netdev;
849 skb_put(skb, pktlen);
850 if (trxd.rxd4 & RX_DMA_L4_VALID)
851 skb->ip_summed = CHECKSUM_UNNECESSARY;
852 else
853 skb_checksum_none_assert(skb);
854 skb->protocol = eth_type_trans(skb, netdev);
855
856 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
857 RX_DMA_VID(trxd.rxd3))
858 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
859 RX_DMA_VID(trxd.rxd3));
860 napi_gro_receive(napi, skb);
861
862 ring->data[idx] = new_data;
863 rxd->rxd1 = (unsigned int)dma_addr;
864
865release_desc:
866 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
867
868 ring->calc_idx = idx;
869 /* make sure that all changes to the dma ring are flushed before
870 * we continue
871 */
872 wmb();
873 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
874 done++;
875 }
876
877 if (done < budget)
878 mtk_w32(eth, rx_intr, MTK_QMTK_INT_STATUS);
879
880 return done;
881}
882
883static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
884{
885 struct mtk_tx_ring *ring = &eth->tx_ring;
886 struct mtk_tx_dma *desc;
887 struct sk_buff *skb;
888 struct mtk_tx_buf *tx_buf;
889 int total = 0, done[MTK_MAX_DEVS];
890 unsigned int bytes[MTK_MAX_DEVS];
891 u32 cpu, dma;
892 static int condition;
893 int i;
894
895 memset(done, 0, sizeof(done));
896 memset(bytes, 0, sizeof(bytes));
897
898 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
899 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
900
901 desc = mtk_qdma_phys_to_virt(ring, cpu);
902
903 while ((cpu != dma) && budget) {
904 u32 next_cpu = desc->txd2;
905 int mac;
906
907 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
908 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
909 break;
910
911 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
912 TX_DMA_FPORT_MASK;
913 mac--;
914
915 tx_buf = mtk_desc_to_tx_buf(ring, desc);
916 skb = tx_buf->skb;
917 if (!skb) {
918 condition = 1;
919 break;
920 }
921
922 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
923 bytes[mac] += skb->len;
924 done[mac]++;
925 budget--;
926 }
927 mtk_tx_unmap(eth->dev, tx_buf);
928
929 ring->last_free->txd2 = next_cpu;
930 ring->last_free = desc;
931 atomic_inc(&ring->free_count);
932
933 cpu = next_cpu;
934 }
935
936 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
937
938 for (i = 0; i < MTK_MAC_COUNT; i++) {
939 if (!eth->netdev[i] || !done[i])
940 continue;
941 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
942 total += done[i];
943 }
944
945 /* read hw index again make sure no new tx packet */
946 if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
947 *tx_again = true;
948 else
949 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
950
951 if (!total)
952 return 0;
953
13c822f6
JC		 954 if (atomic_read(&ring->free_count) > ring->thresh)
955 mtk_wake_queue(eth);
656e7052
JC		 956
957 return total;
958}
959
960static int mtk_poll(struct napi_struct *napi, int budget)
961{
962 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
963 u32 status, status2, mask, tx_intr, rx_intr, status_intr;
964 int tx_done, rx_done;
965 bool tx_again = false;
966
967 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
968 status2 = mtk_r32(eth, MTK_INT_STATUS2);
969 tx_intr = MTK_TX_DONE_INT;
970 rx_intr = MTK_RX_DONE_INT;
971 status_intr = (MTK_GDM1_AF | MTK_GDM2_AF);
972 tx_done = 0;
973 rx_done = 0;
974 tx_again = 0;
975
976 if (status & tx_intr)
977 tx_done = mtk_poll_tx(eth, budget, &tx_again);
978
979 if (status & rx_intr)
980 rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
981
982 if (unlikely(status2 & status_intr)) {
983 mtk_stats_update(eth);
984 mtk_w32(eth, status_intr, MTK_INT_STATUS2);
985 }
986
987 if (unlikely(netif_msg_intr(eth))) {
988 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
989 netdev_info(eth->netdev[0],
990 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
991 tx_done, rx_done, status, mask);
992 }
993
994 if (tx_again || rx_done == budget)
995 return budget;
996
997 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
998 if (status & (tx_intr | rx_intr))
999 return budget;
1000
1001 napi_complete(napi);
1002 mtk_irq_enable(eth, tx_intr | rx_intr);
1003
1004 return rx_done;
1005}
1006
1007static int mtk_tx_alloc(struct mtk_eth *eth)
1008{
1009 struct mtk_tx_ring *ring = &eth->tx_ring;
1010 int i, sz = sizeof(*ring->dma);
1011
1012 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1013 GFP_KERNEL);
1014 if (!ring->buf)
1015 goto no_tx_mem;
1016
1017 ring->dma = dma_alloc_coherent(eth->dev,
1018 MTK_DMA_SIZE * sz,
1019 &ring->phys,
1020 GFP_ATOMIC | __GFP_ZERO);
1021 if (!ring->dma)
1022 goto no_tx_mem;
1023
1024 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1025 for (i = 0; i < MTK_DMA_SIZE; i++) {
1026 int next = (i + 1) % MTK_DMA_SIZE;
1027 u32 next_ptr = ring->phys + next * sz;
1028
1029 ring->dma[i].txd2 = next_ptr;
1030 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1031 }
1032
1033 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1034 ring->next_free = &ring->dma[0];
1035 ring->last_free = &ring->dma[MTK_DMA_SIZE - 2];
04698ccc 1036 ring->thresh = MAX_SKB_FRAGS;
656e7052
JC		 1037
1038 /* make sure that all changes to the dma ring are flushed before we
1039 * continue
1040 */
1041 wmb();
1042
1043 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1044 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1045 mtk_w32(eth,
1046 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1047 MTK_QTX_CRX_PTR);
1048 mtk_w32(eth,
1049 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1050 MTK_QTX_DRX_PTR);
1051
1052 return 0;
1053
1054no_tx_mem:
1055 return -ENOMEM;
1056}
1057
1058static void mtk_tx_clean(struct mtk_eth *eth)
1059{
1060 struct mtk_tx_ring *ring = &eth->tx_ring;
1061 int i;
1062
1063 if (ring->buf) {
1064 for (i = 0; i < MTK_DMA_SIZE; i++)
1065 mtk_tx_unmap(eth->dev, &ring->buf[i]);
1066 kfree(ring->buf);
1067 ring->buf = NULL;
1068 }
1069
1070 if (ring->dma) {
1071 dma_free_coherent(eth->dev,
1072 MTK_DMA_SIZE * sizeof(*ring->dma),
1073 ring->dma,
1074 ring->phys);
1075 ring->dma = NULL;
1076 }
1077}
1078
1079static int mtk_rx_alloc(struct mtk_eth *eth)
1080{
1081 struct mtk_rx_ring *ring = &eth->rx_ring;
1082 int i;
1083
1084 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1085 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1086 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1087 GFP_KERNEL);
1088 if (!ring->data)
1089 return -ENOMEM;
1090
1091 for (i = 0; i < MTK_DMA_SIZE; i++) {
1092 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1093 if (!ring->data[i])
1094 return -ENOMEM;
1095 }
1096
1097 ring->dma = dma_alloc_coherent(eth->dev,
1098 MTK_DMA_SIZE * sizeof(*ring->dma),
1099 &ring->phys,
1100 GFP_ATOMIC | __GFP_ZERO);
1101 if (!ring->dma)
1102 return -ENOMEM;
1103
1104 for (i = 0; i < MTK_DMA_SIZE; i++) {
1105 dma_addr_t dma_addr = dma_map_single(eth->dev,
1106 ring->data[i] + NET_SKB_PAD,
1107 ring->buf_size,
1108 DMA_FROM_DEVICE);
1109 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1110 return -ENOMEM;
1111 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1112
1113 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1114 }
1115 ring->calc_idx = MTK_DMA_SIZE - 1;
1116 /* make sure that all changes to the dma ring are flushed before we
1117 * continue
1118 */
1119 wmb();
1120
1121 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1122 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1123 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1124 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1125 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1126
1127 return 0;
1128}
1129
1130static void mtk_rx_clean(struct mtk_eth *eth)
1131{
1132 struct mtk_rx_ring *ring = &eth->rx_ring;
1133 int i;
1134
1135 if (ring->data && ring->dma) {
1136 for (i = 0; i < MTK_DMA_SIZE; i++) {
1137 if (!ring->data[i])
1138 continue;
1139 if (!ring->dma[i].rxd1)
1140 continue;
1141 dma_unmap_single(eth->dev,
1142 ring->dma[i].rxd1,
1143 ring->buf_size,
1144 DMA_FROM_DEVICE);
1145 skb_free_frag(ring->data[i]);
1146 }
1147 kfree(ring->data);
1148 ring->data = NULL;
1149 }
1150
1151 if (ring->dma) {
1152 dma_free_coherent(eth->dev,
1153 MTK_DMA_SIZE * sizeof(*ring->dma),
1154 ring->dma,
1155 ring->phys);
1156 ring->dma = NULL;
1157 }
1158}
1159
1160/* wait for DMA to finish whatever it is doing before we start using it again */
1161static int mtk_dma_busy_wait(struct mtk_eth *eth)
1162{
1163 unsigned long t_start = jiffies;
1164
1165 while (1) {
1166 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1167 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1168 return 0;
1169 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1170 break;
1171 }
1172
1173 dev_err(eth->dev, "DMA init timeout\n");
1174 return -1;
1175}
1176
1177static int mtk_dma_init(struct mtk_eth *eth)
1178{
1179 int err;
1180
1181 if (mtk_dma_busy_wait(eth))
1182 return -EBUSY;
1183
1184 /* QDMA needs scratch memory for internal reordering of the
1185 * descriptors
1186 */
1187 err = mtk_init_fq_dma(eth);
1188 if (err)
1189 return err;
1190
1191 err = mtk_tx_alloc(eth);
1192 if (err)
1193 return err;
1194
1195 err = mtk_rx_alloc(eth);
1196 if (err)
1197 return err;
1198
1199 /* Enable random early drop and set drop threshold automatically */
1200 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1201 MTK_QDMA_FC_THRES);
1202 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1203
1204 return 0;
1205}
1206
1207static void mtk_dma_free(struct mtk_eth *eth)
1208{
1209 int i;
1210
1211 for (i = 0; i < MTK_MAC_COUNT; i++)
1212 if (eth->netdev[i])
1213 netdev_reset_queue(eth->netdev[i]);
605e4fe4
JC		 1214 if (eth->scratch_ring) {
1215 dma_free_coherent(eth->dev,
1216 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1217 eth->scratch_ring,
1218 eth->phy_scratch_ring);
1219 eth->scratch_ring = NULL;
1220 eth->phy_scratch_ring = 0;
1221 }
656e7052
JC		 1222 mtk_tx_clean(eth);
1223 mtk_rx_clean(eth);
1224 kfree(eth->scratch_head);
1225}
1226
1227static void mtk_tx_timeout(struct net_device *dev)
1228{
1229 struct mtk_mac *mac = netdev_priv(dev);
1230 struct mtk_eth *eth = mac->hw;
1231
1232 eth->netdev[mac->id]->stats.tx_errors++;
1233 netif_err(eth, tx_err, dev,
1234 "transmit timed out\n");
7c78b4ad 1235 schedule_work(&eth->pending_work);
656e7052
JC		 1236}
1237
1238static irqreturn_t mtk_handle_irq(int irq, void *_eth)
1239{
1240 struct mtk_eth *eth = _eth;
1241 u32 status;
1242
1243 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1244 if (unlikely(!status))
1245 return IRQ_NONE;
1246
1247 if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) {
1248 if (likely(napi_schedule_prep(&eth->rx_napi)))
1249 __napi_schedule(&eth->rx_napi);
1250 } else {
1251 mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
1252 }
1253 mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT));
1254
1255 return IRQ_HANDLED;
1256}
1257
1258#ifdef CONFIG_NET_POLL_CONTROLLER
1259static void mtk_poll_controller(struct net_device *dev)
1260{
1261 struct mtk_mac *mac = netdev_priv(dev);
1262 struct mtk_eth *eth = mac->hw;
1263 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1264
1265 mtk_irq_disable(eth, int_mask);
1266 mtk_handle_irq(dev->irq, dev);
1267 mtk_irq_enable(eth, int_mask);
1268}
1269#endif
1270
1271static int mtk_start_dma(struct mtk_eth *eth)
1272{
1273 int err;
1274
1275 err = mtk_dma_init(eth);
1276 if (err) {
1277 mtk_dma_free(eth);
1278 return err;
1279 }
1280
1281 mtk_w32(eth,
1282 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1283 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
6675086d 1284 MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
656e7052
JC		 1285 MTK_QDMA_GLO_CFG);
1286
1287 return 0;
1288}
1289
1290static int mtk_open(struct net_device *dev)
1291{
1292 struct mtk_mac *mac = netdev_priv(dev);
1293 struct mtk_eth *eth = mac->hw;
1294
1295 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1296 if (!atomic_read(&eth->dma_refcnt)) {
1297 int err = mtk_start_dma(eth);
1298
1299 if (err)
1300 return err;
1301
1302 napi_enable(&eth->rx_napi);
1303 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1304 }
1305 atomic_inc(&eth->dma_refcnt);
1306
1307 phy_start(mac->phy_dev);
1308 netif_start_queue(dev);
1309
1310 return 0;
1311}
1312
1313static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1314{
1315 unsigned long flags;
1316 u32 val;
1317 int i;
1318
1319 /* stop the dma engine */
1320 spin_lock_irqsave(&eth->page_lock, flags);
1321 val = mtk_r32(eth, glo_cfg);
1322 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1323 glo_cfg);
1324 spin_unlock_irqrestore(&eth->page_lock, flags);
1325
1326 /* wait for dma stop */
1327 for (i = 0; i < 10; i++) {
1328 val = mtk_r32(eth, glo_cfg);
1329 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1330 msleep(20);
1331 continue;
1332 }
1333 break;
1334 }
1335}
1336
1337static int mtk_stop(struct net_device *dev)
1338{
1339 struct mtk_mac *mac = netdev_priv(dev);
1340 struct mtk_eth *eth = mac->hw;
1341
1342 netif_tx_disable(dev);
1343 phy_stop(mac->phy_dev);
1344
1345 /* only shutdown DMA if this is the last user */
1346 if (!atomic_dec_and_test(&eth->dma_refcnt))
1347 return 0;
1348
1349 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1350 napi_disable(&eth->rx_napi);
1351
1352 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1353
1354 mtk_dma_free(eth);
1355
1356 return 0;
1357}
1358
1359static int __init mtk_hw_init(struct mtk_eth *eth)
1360{
1361 int err, i;
1362
1363 /* reset the frame engine */
1364 reset_control_assert(eth->rstc);
1365 usleep_range(10, 20);
1366 reset_control_deassert(eth->rstc);
1367 usleep_range(10, 20);
1368
1369 /* Set GE2 driving and slew rate */
1370 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1371
1372 /* set GE2 TDSEL */
1373 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1374
1375 /* set GE2 TUNE */
1376 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1377
1378 /* GE1, Force 1000M/FD, FC ON */
1379 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1380
1381 /* GE2, Force 1000M/FD, FC ON */
1382 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1383
1384 /* Enable RX VLan Offloading */
1385 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1386
1387 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
1388 dev_name(eth->dev), eth);
1389 if (err)
1390 return err;
1391
1392 err = mtk_mdio_init(eth);
1393 if (err)
1394 return err;
1395
1396 /* disable delay and normal interrupt */
1397 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
2ff0bb61 1398 mtk_irq_disable(eth, ~0);
656e7052
JC		 1399 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1400 mtk_w32(eth, 0, MTK_RST_GL);
1401
1402 /* FE int grouping */
1403 mtk_w32(eth, 0, MTK_FE_INT_GRP);
1404
1405 for (i = 0; i < 2; i++) {
1406 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1407
1408 /* setup the forward port to send frame to QDMA */
1409 val &= ~0xffff;
1410 val |= 0x5555;
1411
1412 /* Enable RX checksum */
1413 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1414
1415 /* setup the mac dma */
1416 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1417 }
1418
1419 return 0;
1420}
1421
1422static int __init mtk_init(struct net_device *dev)
1423{
1424 struct mtk_mac *mac = netdev_priv(dev);
1425 struct mtk_eth *eth = mac->hw;
1426 const char *mac_addr;
1427
1428 mac_addr = of_get_mac_address(mac->of_node);
1429 if (mac_addr)
1430 ether_addr_copy(dev->dev_addr, mac_addr);
1431
1432 /* If the mac address is invalid, use random mac address */
1433 if (!is_valid_ether_addr(dev->dev_addr)) {
1434 random_ether_addr(dev->dev_addr);
1435 dev_err(eth->dev, "generated random MAC address %pM\n",
1436 dev->dev_addr);
1437 dev->addr_assign_type = NET_ADDR_RANDOM;
1438 }
1439
1440 return mtk_phy_connect(mac);
1441}
1442
1443static void mtk_uninit(struct net_device *dev)
1444{
1445 struct mtk_mac *mac = netdev_priv(dev);
1446 struct mtk_eth *eth = mac->hw;
1447
1448 phy_disconnect(mac->phy_dev);
1449 mtk_mdio_cleanup(eth);
1450 mtk_irq_disable(eth, ~0);
1451 free_irq(dev->irq, dev);
1452}
1453
1454static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1455{
1456 struct mtk_mac *mac = netdev_priv(dev);
1457
1458 switch (cmd) {
1459 case SIOCGMIIPHY:
1460 case SIOCGMIIREG:
1461 case SIOCSMIIREG:
1462 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1463 default:
1464 break;
1465 }
1466
1467 return -EOPNOTSUPP;
1468}
1469
1470static void mtk_pending_work(struct work_struct *work)
1471{
7c78b4ad 1472 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
e7d425dc
JC		 1473 int err, i;
1474 unsigned long restart = 0;
656e7052
JC		 1475
1476 rtnl_lock();
656e7052 1477
e7d425dc
JC		 1478 /* stop all devices to make sure that dma is properly shut down */
1479 for (i = 0; i < MTK_MAC_COUNT; i++) {
7c78b4ad 1480 if (!eth->netdev[i])
e7d425dc
JC		 1481 continue;
1482 mtk_stop(eth->netdev[i]);
1483 __set_bit(i, &restart);
1484 }
1485
1486 /* restart DMA and enable IRQs */
1487 for (i = 0; i < MTK_MAC_COUNT; i++) {
1488 if (!test_bit(i, &restart))
1489 continue;
1490 err = mtk_open(eth->netdev[i]);
1491 if (err) {
1492 netif_alert(eth, ifup, eth->netdev[i],
1493 "Driver up/down cycle failed, closing device.\n");
1494 dev_close(eth->netdev[i]);
1495 }
656e7052
JC		 1496 }
1497 rtnl_unlock();
1498}
1499
1500static int mtk_cleanup(struct mtk_eth *eth)
1501{
1502 int i;
1503
1504 for (i = 0; i < MTK_MAC_COUNT; i++) {
656e7052
JC		 1505 if (!eth->netdev[i])
1506 continue;
1507
1508 unregister_netdev(eth->netdev[i]);
1509 free_netdev(eth->netdev[i]);
656e7052 1510 }
7c78b4ad 1511 cancel_work_sync(&eth->pending_work);
656e7052
JC		 1512
1513 return 0;
1514}
1515
1516static int mtk_get_settings(struct net_device *dev,
1517 struct ethtool_cmd *cmd)
1518{
1519 struct mtk_mac *mac = netdev_priv(dev);
1520 int err;
1521
1522 err = phy_read_status(mac->phy_dev);
1523 if (err)
1524 return -ENODEV;
1525
1526 return phy_ethtool_gset(mac->phy_dev, cmd);
1527}
1528
1529static int mtk_set_settings(struct net_device *dev,
1530 struct ethtool_cmd *cmd)
1531{
1532 struct mtk_mac *mac = netdev_priv(dev);
1533
1534 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1535 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1536 cmd->phy_address);
1537 if (!mac->phy_dev)
1538 return -ENODEV;
1539 }
1540
1541 return phy_ethtool_sset(mac->phy_dev, cmd);
1542}
1543
1544static void mtk_get_drvinfo(struct net_device *dev,
1545 struct ethtool_drvinfo *info)
1546{
1547 struct mtk_mac *mac = netdev_priv(dev);
1548
1549 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1550 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1551 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1552}
1553
1554static u32 mtk_get_msglevel(struct net_device *dev)
1555{
1556 struct mtk_mac *mac = netdev_priv(dev);
1557
1558 return mac->hw->msg_enable;
1559}
1560
1561static void mtk_set_msglevel(struct net_device *dev, u32 value)
1562{
1563 struct mtk_mac *mac = netdev_priv(dev);
1564
1565 mac->hw->msg_enable = value;
1566}
1567
1568static int mtk_nway_reset(struct net_device *dev)
1569{
1570 struct mtk_mac *mac = netdev_priv(dev);
1571
1572 return genphy_restart_aneg(mac->phy_dev);
1573}
1574
1575static u32 mtk_get_link(struct net_device *dev)
1576{
1577 struct mtk_mac *mac = netdev_priv(dev);
1578 int err;
1579
1580 err = genphy_update_link(mac->phy_dev);
1581 if (err)
1582 return ethtool_op_get_link(dev);
1583
1584 return mac->phy_dev->link;
1585}
1586
1587static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1588{
1589 int i;
1590
1591 switch (stringset) {
1592 case ETH_SS_STATS:
1593 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1594 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1595 data += ETH_GSTRING_LEN;
1596 }
1597 break;
1598 }
1599}
1600
1601static int mtk_get_sset_count(struct net_device *dev, int sset)
1602{
1603 switch (sset) {
1604 case ETH_SS_STATS:
1605 return ARRAY_SIZE(mtk_ethtool_stats);
1606 default:
1607 return -EOPNOTSUPP;
1608 }
1609}
1610
1611static void mtk_get_ethtool_stats(struct net_device *dev,
1612 struct ethtool_stats *stats, u64 *data)
1613{
1614 struct mtk_mac *mac = netdev_priv(dev);
1615 struct mtk_hw_stats *hwstats = mac->hw_stats;
1616 u64 *data_src, *data_dst;
1617 unsigned int start;
1618 int i;
1619
1620 if (netif_running(dev) && netif_device_present(dev)) {
1621 if (spin_trylock(&hwstats->stats_lock)) {
1622 mtk_stats_update_mac(mac);
1623 spin_unlock(&hwstats->stats_lock);
1624 }
1625 }
1626
1627 do {
1628 data_src = (u64*)hwstats;
1629 data_dst = data;
1630 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1631
1632 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1633 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1634 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1635}
1636
1637static struct ethtool_ops mtk_ethtool_ops = {
1638 .get_settings = mtk_get_settings,
1639 .set_settings = mtk_set_settings,
1640 .get_drvinfo = mtk_get_drvinfo,
1641 .get_msglevel = mtk_get_msglevel,
1642 .set_msglevel = mtk_set_msglevel,
1643 .nway_reset = mtk_nway_reset,
1644 .get_link = mtk_get_link,
1645 .get_strings = mtk_get_strings,
1646 .get_sset_count = mtk_get_sset_count,
1647 .get_ethtool_stats = mtk_get_ethtool_stats,
1648};
1649
1650static const struct net_device_ops mtk_netdev_ops = {
1651 .ndo_init = mtk_init,
1652 .ndo_uninit = mtk_uninit,
1653 .ndo_open = mtk_open,
1654 .ndo_stop = mtk_stop,
1655 .ndo_start_xmit = mtk_start_xmit,
1656 .ndo_set_mac_address = mtk_set_mac_address,
1657 .ndo_validate_addr = eth_validate_addr,
1658 .ndo_do_ioctl = mtk_do_ioctl,
1659 .ndo_change_mtu = eth_change_mtu,
1660 .ndo_tx_timeout = mtk_tx_timeout,
1661 .ndo_get_stats64 = mtk_get_stats64,
1662#ifdef CONFIG_NET_POLL_CONTROLLER
1663 .ndo_poll_controller = mtk_poll_controller,
1664#endif
1665};
1666
1667static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1668{
1669 struct mtk_mac *mac;
1670 const __be32 *_id = of_get_property(np, "reg", NULL);
1671 int id, err;
1672
1673 if (!_id) {
1674 dev_err(eth->dev, "missing mac id\n");
1675 return -EINVAL;
1676 }
1677
1678 id = be32_to_cpup(_id);
1679 if (id >= MTK_MAC_COUNT) {
1680 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1681 return -EINVAL;
1682 }
1683
1684 if (eth->netdev[id]) {
1685 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1686 return -EINVAL;
1687 }
1688
1689 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1690 if (!eth->netdev[id]) {
1691 dev_err(eth->dev, "alloc_etherdev failed\n");
1692 return -ENOMEM;
1693 }
1694 mac = netdev_priv(eth->netdev[id]);
1695 eth->mac[id] = mac;
1696 mac->id = id;
1697 mac->hw = eth;
1698 mac->of_node = np;
656e7052
JC		 1699
1700 mac->hw_stats = devm_kzalloc(eth->dev,
1701 sizeof(*mac->hw_stats),
1702 GFP_KERNEL);
1703 if (!mac->hw_stats) {
1704 dev_err(eth->dev, "failed to allocate counter memory\n");
1705 err = -ENOMEM;
1706 goto free_netdev;
1707 }
1708 spin_lock_init(&mac->hw_stats->stats_lock);
1709 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1710
1711 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
82500aa0 1712 eth->netdev[id]->watchdog_timeo = HZ;
656e7052
JC		 1713 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1714 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1715 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1716 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1717 eth->netdev[id]->features |= MTK_HW_FEATURES;
1718 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1719
1720 err = register_netdev(eth->netdev[id]);
1721 if (err) {
1722 dev_err(eth->dev, "error bringing up device\n");
1723 goto free_netdev;
1724 }
1725 eth->netdev[id]->irq = eth->irq;
1726 netif_info(eth, probe, eth->netdev[id],
1727 "mediatek frame engine at 0x%08lx, irq %d\n",
1728 eth->netdev[id]->base_addr, eth->netdev[id]->irq);
1729
1730 return 0;
1731
1732free_netdev:
1733 free_netdev(eth->netdev[id]);
1734 return err;
1735}
1736
1737static int mtk_probe(struct platform_device *pdev)
1738{
1739 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1740 struct device_node *mac_np;
1741 const struct of_device_id *match;
1742 struct mtk_soc_data *soc;
1743 struct mtk_eth *eth;
1744 int err;
1745
656e7052
JC		 1746 match = of_match_device(of_mtk_match, &pdev->dev);
1747 soc = (struct mtk_soc_data *)match->data;
1748
1749 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1750 if (!eth)
1751 return -ENOMEM;
1752
1753 eth->base = devm_ioremap_resource(&pdev->dev, res);
621e49f6
VZ		 1754 if (IS_ERR(eth->base))
1755 return PTR_ERR(eth->base);
656e7052
JC		 1756
1757 spin_lock_init(&eth->page_lock);
1758
1759 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1760 "mediatek,ethsys");
1761 if (IS_ERR(eth->ethsys)) {
1762 dev_err(&pdev->dev, "no ethsys regmap found\n");
1763 return PTR_ERR(eth->ethsys);
1764 }
1765
1766 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1767 "mediatek,pctl");
1768 if (IS_ERR(eth->pctl)) {
1769 dev_err(&pdev->dev, "no pctl regmap found\n");
1770 return PTR_ERR(eth->pctl);
1771 }
1772
1773 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1774 if (IS_ERR(eth->rstc)) {
1775 dev_err(&pdev->dev, "no eth reset found\n");
1776 return PTR_ERR(eth->rstc);
1777 }
1778
1779 eth->irq = platform_get_irq(pdev, 0);
1780 if (eth->irq < 0) {
1781 dev_err(&pdev->dev, "no IRQ resource found\n");
1782 return -ENXIO;
1783 }
1784
1785 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1786 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1787 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1788 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1789 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1790 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1791 return -ENODEV;
1792
1793 clk_prepare_enable(eth->clk_ethif);
1794 clk_prepare_enable(eth->clk_esw);
1795 clk_prepare_enable(eth->clk_gp1);
1796 clk_prepare_enable(eth->clk_gp2);
1797
1798 eth->dev = &pdev->dev;
1799 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
7c78b4ad 1800 INIT_WORK(&eth->pending_work, mtk_pending_work);
656e7052
JC		 1801
1802 err = mtk_hw_init(eth);
1803 if (err)
1804 return err;
1805
1806 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1807 if (!of_device_is_compatible(mac_np,
1808 "mediatek,eth-mac"))
1809 continue;
1810
1811 if (!of_device_is_available(mac_np))
1812 continue;
1813
1814 err = mtk_add_mac(eth, mac_np);
1815 if (err)
1816 goto err_free_dev;
1817 }
1818
1819 /* we run 2 devices on the same DMA ring so we need a dummy device
1820 * for NAPI to work
1821 */
1822 init_dummy_netdev(&eth->dummy_dev);
1823 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_poll,
1824 MTK_NAPI_WEIGHT);
1825
1826 platform_set_drvdata(pdev, eth);
1827
1828 return 0;
1829
1830err_free_dev:
1831 mtk_cleanup(eth);
1832 return err;
1833}
1834
1835static int mtk_remove(struct platform_device *pdev)
1836{
1837 struct mtk_eth *eth = platform_get_drvdata(pdev);
1838
1839 clk_disable_unprepare(eth->clk_ethif);
1840 clk_disable_unprepare(eth->clk_esw);
1841 clk_disable_unprepare(eth->clk_gp1);
1842 clk_disable_unprepare(eth->clk_gp2);
1843
1844 netif_napi_del(&eth->rx_napi);
1845 mtk_cleanup(eth);
1846 platform_set_drvdata(pdev, NULL);
1847
1848 return 0;
1849}
1850
1851const struct of_device_id of_mtk_match[] = {
1852 { .compatible = "mediatek,mt7623-eth" },
1853 {},
1854};
1855
1856static struct platform_driver mtk_driver = {
1857 .probe = mtk_probe,
1858 .remove = mtk_remove,
1859 .driver = {
1860 .name = "mtk_soc_eth",
1861 .owner = THIS_MODULE,
1862 .of_match_table = of_mtk_match,
1863 },
1864};
1865
1866module_platform_driver(mtk_driver);
1867
1868MODULE_LICENSE("GPL");
1869MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1870MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux 6.x block layer and io_uring tree(s)