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net: introduce and use netdev_features_t for device features sets
[linux-block.git] / drivers / net / ethernet / marvell / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
a6b7a407 35#include <linux/interrupt.h>
cd28ab6a 36#include <linux/ip.h>
5a0e3ad6 37#include <linux/slab.h>
c9bdd4b5 38#include <net/ip.h>
cd28ab6a
SH		 39#include <linux/tcp.h>
40#include <linux/in.h>
41#include <linux/delay.h>
91c86df5 42#include <linux/workqueue.h>
d1f13708 43#include <linux/if_vlan.h>
d70cd51a 44#include <linux/prefetch.h>
3cf26753 45#include <linux/debugfs.h>
ef743d33 46#include <linux/mii.h>
cd28ab6a
SH		 47
48#include <asm/irq.h>
49
50#include "sky2.h"
51
52#define DRV_NAME "sky2"
4ec8f0ca 53#define DRV_VERSION "1.29"
cd28ab6a
SH		 54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 65
ee5f68fe 66/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 69#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
efe91932 70#define TX_MAX_PENDING 1024
ee5f68fe 71#define TX_DEF_PENDING 127
cd28ab6a 72
cd28ab6a
SH		 73#define TX_WATCHDOG (5 * HZ)
74#define NAPI_WEIGHT 64
75#define PHY_RETRIES 1000
76
f4331a6d
SH		 77#define SKY2_EEPROM_MAGIC 0x9955aabb
78
060b946c 79#define RING_NEXT(x, s) (((x)+1) & ((s)-1))
cb5d9547 80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e6cac9ba 98static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0 150static void sky2_set_multicast(struct net_device *dev);
0bdb0bd0 151static irqreturn_t sky2_intr(int irq, void *dev_id);
d1b139c0 152
af043aa5 153/* Access to PHY via serial interconnect */
ef743d33 154static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 155{
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 163 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
164 if (ctrl == 0xffff)
165 goto io_error;
166
167 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 168 return 0;
af043aa5
SH		 169
170 udelay(10);
cd28ab6a 171 }
ef743d33 172
060b946c 173 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 174 return -ETIMEDOUT;
af043aa5
SH		 175
176io_error:
177 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
178 return -EIO;
cd28ab6a
SH		 179}
180
ef743d33 181static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 182{
183 int i;
184
793b883e 185 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 186 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
187
188 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 189 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
190 if (ctrl == 0xffff)
191 goto io_error;
192
193 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 194 *val = gma_read16(hw, port, GM_SMI_DATA);
195 return 0;
196 }
197
af043aa5 198 udelay(10);
cd28ab6a
SH		 199 }
200
af043aa5 201 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 202 return -ETIMEDOUT;
af043aa5
SH		 203io_error:
204 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
205 return -EIO;
ef743d33 206}
207
af043aa5 208static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 209{
210 u16 v;
af043aa5 211 __gm_phy_read(hw, port, reg, &v);
ef743d33 212 return v;
cd28ab6a
SH		 213}
214
5afa0a9c 215
ae306cca
SH		 216static void sky2_power_on(struct sky2_hw *hw)
217{
218 /* switch power to VCC (WA for VAUX problem) */
219 sky2_write8(hw, B0_POWER_CTRL,
220 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 221
ae306cca
SH		 222 /* disable Core Clock Division, */
223 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 224
4b7c47aa 225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 226 /* enable bits are inverted */
227 sky2_write8(hw, B2_Y2_CLK_GATE,
228 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
229 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
230 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 else
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 233
ea76e635 234 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 235 u32 reg;
5afa0a9c 236
b32f40c4 237 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 238
b32f40c4 239 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 240 /* set all bits to 0 except bits 15..12 and 8 */
241 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 242 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 243
b32f40c4 244 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 245 /* set all bits to 0 except bits 28 & 27 */
246 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 247 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 248
b32f40c4 249 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 250
5f8ae5c5 251 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
252
8f70920f
SH		 253 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
254 reg = sky2_read32(hw, B2_GP_IO);
255 reg |= GLB_GPIO_STAT_RACE_DIS;
256 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 257
258 sky2_read32(hw, B2_GP_IO);
5afa0a9c 259 }
10547ae2
SH		 260
261 /* Turn on "driver loaded" LED */
262 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 263}
5afa0a9c 264
ae306cca
SH		 265static void sky2_power_aux(struct sky2_hw *hw)
266{
4b7c47aa 267 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 268 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
269 else
270 /* enable bits are inverted */
271 sky2_write8(hw, B2_Y2_CLK_GATE,
272 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
273 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
274 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
275
c23ddf8f
SH		 276 /* switch power to VAUX if supported and PME from D3cold */
277 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
278 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 279 sky2_write8(hw, B0_POWER_CTRL,
280 (PC_VAUX_ENA | PC_VCC_ENA |
281 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 282
283 /* turn off "driver loaded LED" */
284 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c 285}
286
d3bcfbeb 287static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 288{
289 u16 reg;
290
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 293
cd28ab6a
SH		 294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302}
303
16ad91e1
SH		 304/* flow control to advertise bits */
305static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310};
311
312/* flow control to advertise bits when using 1000BaseX */
313static const u16 fiber_fc_adv[] = {
df3fe1f3 314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 318};
319
320/* flow control to GMA disable bits */
321static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326};
327
328
cd28ab6a
SH		 329static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330{
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 333
0ea065e5 334 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 339 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
53419c68 342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 343 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 344 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
53419c68
SH		 347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 354 if (sky2_is_copper(hw)) {
05745c4a 355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
cd28ab6a
SH		 368 } else {
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374
53419c68 375 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 376 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
377 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 378 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
381 }
382 }
cd28ab6a
SH		 383 } else {
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
386
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 388 }
cd28ab6a 389
b89165f2
SH		 390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391
392 /* special setup for PHY 88E1112 Fiber */
ea76e635 393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 395
b89165f2
SH		 396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 406
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 411 }
b89165f2
SH		 412
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 414 }
415
7800fddc 416 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 417 ct1000 = 0;
418 adv = PHY_AN_CSMA;
2eaba1a2 419 reg = 0;
cd28ab6a 420
0ea065e5 421 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 422 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
709c6e7b 435
b89165f2
SH		 436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 441 }
cd28ab6a
SH		 442
443 /* Restart Auto-negotiation */
444 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
445 } else {
446 /* forced speed/duplex settings */
447 ct1000 = PHY_M_1000C_MSE;
448
0ea065e5
SH		 449 /* Disable auto update for duplex flow control and duplex */
450 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 451
452 switch (sky2->speed) {
453 case SPEED_1000:
454 ctrl |= PHY_CT_SP1000;
2eaba1a2 455 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 456 break;
457 case SPEED_100:
458 ctrl |= PHY_CT_SP100;
2eaba1a2 459 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 460 break;
461 }
462
2eaba1a2
SH		 463 if (sky2->duplex == DUPLEX_FULL) {
464 reg |= GM_GPCR_DUP_FULL;
465 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 466 } else if (sky2->speed < SPEED_1000)
467 sky2->flow_mode = FC_NONE;
0ea065e5 468 }
2eaba1a2 469
0ea065e5
SH		 470 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
471 if (sky2_is_copper(hw))
472 adv |= copper_fc_adv[sky2->flow_mode];
473 else
474 adv |= fiber_fc_adv[sky2->flow_mode];
475 } else {
476 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 477 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 478
479 /* Forward pause packets to GMAC? */
16ad91e1 480 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
482 else
483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 484 }
485
2eaba1a2
SH		 486 gma_write16(hw, port, GM_GP_CTRL, reg);
487
05745c4a 488 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 489 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
490
491 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
492 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
493
494 /* Setup Phy LED's */
495 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
496 ledover = 0;
497
498 switch (hw->chip_id) {
499 case CHIP_ID_YUKON_FE:
500 /* on 88E3082 these bits are at 11..9 (shifted left) */
501 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
502
503 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
504
505 /* delete ACT LED control bits */
506 ctrl &= ~PHY_M_FELP_LED1_MSK;
507 /* change ACT LED control to blink mode */
508 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
509 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
510 break;
511
05745c4a
SH		 512 case CHIP_ID_YUKON_FE_P:
513 /* Enable Link Partner Next Page */
514 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
515 ctrl |= PHY_M_PC_ENA_LIP_NP;
516
517 /* disable Energy Detect and enable scrambler */
518 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
519 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
520
521 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
522 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
523 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
524 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
525
526 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
527 break;
528
cd28ab6a 529 case CHIP_ID_YUKON_XL:
793b883e 530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 531
532 /* select page 3 to access LED control register */
533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
534
535 /* set LED Function Control register */
ed6d32c7
SH		 536 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
537 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
538 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
539 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
540 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 541
542 /* set Polarity Control register */
543 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 544 (PHY_M_POLC_LS1_P_MIX(4) |
545 PHY_M_POLC_IS0_P_MIX(4) |
546 PHY_M_POLC_LOS_CTRL(2) |
547 PHY_M_POLC_INIT_CTRL(2) |
548 PHY_M_POLC_STA1_CTRL(2) |
549 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 550
551 /* restore page register */
793b883e 552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 553 break;
93745494 554
ed6d32c7 555 case CHIP_ID_YUKON_EC_U:
93745494 556 case CHIP_ID_YUKON_EX:
ed4d4161 557 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 558 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
559
560 /* select page 3 to access LED control register */
561 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
562
563 /* set LED Function Control register */
564 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
565 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
566 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
567 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
568 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
569
570 /* set Blink Rate in LED Timer Control Register */
571 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
572 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
573 /* restore page register */
574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
575 break;
cd28ab6a
SH		 576
577 default:
578 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
579 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 580
cd28ab6a 581 /* turn off the Rx LED (LED_RX) */
a84d0a3d 582 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 583 }
584
0ce8b98d 585 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 586 /* apply fixes in PHY AFE */
ed6d32c7
SH		 587 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
588
977bdf06 589 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 590 gm_phy_write(hw, port, 0x18, 0xaa99);
591 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 592
0ce8b98d
SH		 593 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
594 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
595 gm_phy_write(hw, port, 0x18, 0xa204);
596 gm_phy_write(hw, port, 0x17, 0x2002);
597 }
977bdf06
SH		 598
599 /* set page register to 0 */
9467a8fc 600 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 601 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
602 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
603 /* apply workaround for integrated resistors calibration */
604 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
605 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 606 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
607 /* apply fixes in PHY AFE */
608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
609
610 /* apply RDAC termination workaround */
611 gm_phy_write(hw, port, 24, 0x2800);
612 gm_phy_write(hw, port, 23, 0x2001);
613
614 /* set page register back to 0 */
615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 616 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
617 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 618 /* no effect on Yukon-XL */
977bdf06 619 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 620
8e95a202
JP		 621 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
622 sky2->speed == SPEED_100) {
977bdf06 623 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 624 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 625 }
cd28ab6a 626
977bdf06
SH		 627 if (ledover)
628 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
629
4fb99cd6 630 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
631 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
632 int i;
633 /* This a phy register setup workaround copied from vendor driver. */
634 static const struct {
635 u16 reg, val;
636 } eee_afe[] = {
637 { 0x156, 0x58ce },
638 { 0x153, 0x99eb },
639 { 0x141, 0x8064 },
640 /* { 0x155, 0x130b },*/
641 { 0x000, 0x0000 },
642 { 0x151, 0x8433 },
643 { 0x14b, 0x8c44 },
644 { 0x14c, 0x0f90 },
645 { 0x14f, 0x39aa },
646 /* { 0x154, 0x2f39 },*/
647 { 0x14d, 0xba33 },
648 { 0x144, 0x0048 },
649 { 0x152, 0x2010 },
650 /* { 0x158, 0x1223 },*/
651 { 0x140, 0x4444 },
652 { 0x154, 0x2f3b },
653 { 0x158, 0xb203 },
654 { 0x157, 0x2029 },
655 };
656
657 /* Start Workaround for OptimaEEE Rev.Z0 */
658 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
659
660 gm_phy_write(hw, port, 1, 0x4099);
661 gm_phy_write(hw, port, 3, 0x1120);
662 gm_phy_write(hw, port, 11, 0x113c);
663 gm_phy_write(hw, port, 14, 0x8100);
664 gm_phy_write(hw, port, 15, 0x112a);
665 gm_phy_write(hw, port, 17, 0x1008);
666
667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
668 gm_phy_write(hw, port, 1, 0x20b0);
669
670 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
671
672 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
673 /* apply AFE settings */
674 gm_phy_write(hw, port, 17, eee_afe[i].val);
675 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
676 }
677
678 /* End Workaround for OptimaEEE */
679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
680
681 /* Enable 10Base-Te (EEE) */
682 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
683 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
684 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
685 reg | PHY_M_10B_TE_ENABLE);
686 }
977bdf06 687 }
2eaba1a2 688
d571b694 689 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 690 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 691 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
692 else
693 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
694}
695
b96936da
SH		 696static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
697static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
698
699static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 700{
701 u32 reg1;
d3bcfbeb 702
a40ccc68 703 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 704 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 705 reg1 &= ~phy_power[port];
d3bcfbeb 706
4b7c47aa 707 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ff35164e
SH		 708 reg1 |= coma_mode[port];
709
b32f40c4 710 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 712 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 713
714 if (hw->chip_id == CHIP_ID_YUKON_FE)
715 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
716 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
717 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 718}
167f53d0 719
b96936da
SH		 720static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
721{
722 u32 reg1;
db99b988
SH		 723 u16 ctrl;
724
725 /* release GPHY Control reset */
726 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
727
728 /* release GMAC reset */
729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
730
731 if (hw->flags & SKY2_HW_NEWER_PHY) {
732 /* select page 2 to access MAC control register */
733 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
734
735 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
736 /* allow GMII Power Down */
737 ctrl &= ~PHY_M_MAC_GMIF_PUP;
738 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
739
740 /* set page register back to 0 */
741 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
742 }
743
744 /* setup General Purpose Control Register */
745 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 746 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
747 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
748 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 749
750 if (hw->chip_id != CHIP_ID_YUKON_EC) {
751 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 752 /* select page 2 to access MAC control register */
753 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 754
e484d5f5 755 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 756 /* enable Power Down */
757 ctrl |= PHY_M_PC_POW_D_ENA;
758 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 759
760 /* set page register back to 0 */
761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 762 }
763
764 /* set IEEE compatible Power Down Mode (dev. #4.99) */
765 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
766 }
b96936da 767
a40ccc68 768 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 769 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 770 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 771 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 772 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 773}
774
8e11680f 775/* configure IPG according to used link speed */
776static void sky2_set_ipg(struct sky2_port *sky2)
777{
778 u16 reg;
779
780 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
781 reg &= ~GM_SMOD_IPG_MSK;
782 if (sky2->speed > SPEED_100)
783 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
784 else
785 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
786 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
787}
788
38000a94
BP		 789/* Enable Rx/Tx */
790static void sky2_enable_rx_tx(struct sky2_port *sky2)
791{
792 struct sky2_hw *hw = sky2->hw;
793 unsigned port = sky2->port;
794 u16 reg;
795
796 reg = gma_read16(hw, port, GM_GP_CTRL);
797 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
798 gma_write16(hw, port, GM_GP_CTRL, reg);
799}
800
1b537565
SH		 801/* Force a renegotiation */
802static void sky2_phy_reinit(struct sky2_port *sky2)
803{
e07b1aa8 804 spin_lock_bh(&sky2->phy_lock);
1b537565 805 sky2_phy_init(sky2->hw, sky2->port);
38000a94 806 sky2_enable_rx_tx(sky2);
e07b1aa8 807 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 808}
809
e3173832
SH		 810/* Put device in state to listen for Wake On Lan */
811static void sky2_wol_init(struct sky2_port *sky2)
812{
813 struct sky2_hw *hw = sky2->hw;
814 unsigned port = sky2->port;
815 enum flow_control save_mode;
816 u16 ctrl;
e3173832
SH		 817
818 /* Bring hardware out of reset */
819 sky2_write16(hw, B0_CTST, CS_RST_CLR);
820 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
821
822 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
824
825 /* Force to 10/100
826 * sky2_reset will re-enable on resume
827 */
828 save_mode = sky2->flow_mode;
829 ctrl = sky2->advertising;
830
831 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
832 sky2->flow_mode = FC_NONE;
b96936da
SH		 833
834 spin_lock_bh(&sky2->phy_lock);
835 sky2_phy_power_up(hw, port);
836 sky2_phy_init(hw, port);
837 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 838
839 sky2->flow_mode = save_mode;
840 sky2->advertising = ctrl;
841
842 /* Set GMAC to no flow control and auto update for speed/duplex */
843 gma_write16(hw, port, GM_GP_CTRL,
844 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
845 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
846
847 /* Set WOL address */
848 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
849 sky2->netdev->dev_addr, ETH_ALEN);
850
851 /* Turn on appropriate WOL control bits */
852 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
853 ctrl = 0;
854 if (sky2->wol & WAKE_PHY)
855 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
856 else
857 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
858
859 if (sky2->wol & WAKE_MAGIC)
860 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
861 else
a419aef8 862 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 863
864 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
865 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
866
5f8ae5c5 867 /* Disable PiG firmware */
868 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
869
e3173832
SH		 870 /* block receiver */
871 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 872}
873
69161611
SH		 874static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
875{
05745c4a
SH		 876 struct net_device *dev = hw->dev[port];
877
ed4d4161
SH		 878 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
879 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 880 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 881 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 882 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
883 } else if (dev->mtu > ETH_DATA_LEN) {
884 /* set Tx GMAC FIFO Almost Empty Threshold */
885 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
886 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 887
44dde56d 888 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
889 } else
890 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 891}
892
cd28ab6a
SH		 893static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
894{
895 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
896 u16 reg;
25cccecc 897 u32 rx_reg;
cd28ab6a
SH		 898 int i;
899 const u8 *addr = hw->dev[port]->dev_addr;
900
f350339c
SH		 901 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
902 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 903
904 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
905
4b7c47aa 906 if (hw->chip_id == CHIP_ID_YUKON_XL &&
907 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
908 port == 1) {
cd28ab6a
SH		 909 /* WA DEV_472 -- looks like crossed wires on port 2 */
910 /* clear GMAC 1 Control reset */
911 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
912 do {
913 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
914 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
915 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
916 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
917 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
918 }
919
793b883e 920 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 921
2eaba1a2
SH		 922 /* Enable Transmit FIFO Underrun */
923 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
924
e07b1aa8 925 spin_lock_bh(&sky2->phy_lock);
b96936da 926 sky2_phy_power_up(hw, port);
cd28ab6a 927 sky2_phy_init(hw, port);
e07b1aa8 928 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 929
930 /* MIB clear */
931 reg = gma_read16(hw, port, GM_PHY_ADDR);
932 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
933
43f2f104
SH		 934 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
935 gma_read16(hw, port, i);
cd28ab6a
SH		 936 gma_write16(hw, port, GM_PHY_ADDR, reg);
937
938 /* transmit control */
939 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
940
941 /* receive control reg: unicast + multicast + no FCS */
942 gma_write16(hw, port, GM_RX_CTRL,
793b883e 943 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 944
945 /* transmit flow control */
946 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
947
948 /* transmit parameter */
949 gma_write16(hw, port, GM_TX_PARAM,
950 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
951 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
952 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
953 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
954
955 /* serial mode register */
956 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
8e11680f 957 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
cd28ab6a 958
6b1a3aef 959 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 960 reg |= GM_SMOD_JUMBO_ENA;
961
c1cd0a85 962 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
963 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
964 reg |= GM_NEW_FLOW_CTRL;
965
cd28ab6a
SH		 966 gma_write16(hw, port, GM_SERIAL_MODE, reg);
967
cd28ab6a
SH		 968 /* virtual address for data */
969 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
970
793b883e
SH		 971 /* physical address: used for pause frames */
972 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
973
974 /* ignore counter overflows */
cd28ab6a
SH		 975 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
976 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
977 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
978
979 /* Configure Rx MAC FIFO */
980 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 981 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 982 if (hw->chip_id == CHIP_ID_YUKON_EX ||
983 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 984 rx_reg |= GMF_RX_OVER_ON;
69161611 985
25cccecc 986 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 987
798fdd07
SH		 988 if (hw->chip_id == CHIP_ID_YUKON_XL) {
989 /* Hardware errata - clear flush mask */
990 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
991 } else {
992 /* Flush Rx MAC FIFO on any flow control or error */
993 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
994 }
cd28ab6a 995
8df9a876 996 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 997 reg = RX_GMF_FL_THR_DEF + 1;
998 /* Another magic mystery workaround from sk98lin */
999 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1000 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1001 reg = 0x178;
1002 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 1003
1004 /* Configure Tx MAC FIFO */
1005 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1006 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 1007
25985edc 1008 /* On chips without ram buffer, pause is controlled by MAC level */
39dbd958 1009 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 1010 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 1011 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1012 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 1013 reg = 1568 / 8;
1014 else
1015 reg = 1024 / 8;
1016 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1017 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 1018
69161611 1019 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 1020 }
1021
e970d1f8
SH		 1022 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1023 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1024 /* disable dynamic watermark */
1025 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1026 reg &= ~TX_DYN_WM_ENA;
1027 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1028 }
cd28ab6a
SH		 1029}
1030
67712901
SH		 1031/* Assign Ram Buffer allocation to queue */
1032static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 1033{
67712901
SH		 1034 u32 end;
1035
1036 /* convert from K bytes to qwords used for hw register */
1037 start *= 1024/8;
1038 space *= 1024/8;
1039 end = start + space - 1;
793b883e 1040
cd28ab6a
SH		 1041 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1042 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1043 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1044 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1045 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1046
1047 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 1048 u32 tp = space - space/4;
793b883e 1049
1c28f6ba
SH		 1050 /* On receive queue's set the thresholds
1051 * give receiver priority when > 3/4 full
1052 * send pause when down to 2K
1053 */
1054 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1055 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 1056
1c28f6ba
SH		 1057 tp = space - 2048/8;
1058 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1059 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 1060 } else {
1061 /* Enable store & forward on Tx queue's because
1062 * Tx FIFO is only 1K on Yukon
1063 */
1064 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1065 }
1066
1067 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 1068 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 1069}
1070
cd28ab6a 1071/* Setup Bus Memory Interface */
af4ed7e6 1072static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 1073{
1074 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1075 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1076 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1077 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1078}
1079
cd28ab6a
SH		 1080/* Setup prefetch unit registers. This is the interface between
1081 * hardware and driver list elements
1082 */
8cc048e3 1083static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1084 dma_addr_t addr, u32 last)
cd28ab6a 1085{
cd28ab6a
SH		 1086 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1087 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1088 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1089 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1090 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1091 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1092
1093 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1094}
1095
9b289c33 1096static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1097{
9b289c33 1098 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1099
ee5f68fe 1100 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1101 le->ctrl = 0;
793b883e
SH		 1102 return le;
1103}
cd28ab6a 1104
88f5f0ca
SH		 1105static void tx_init(struct sky2_port *sky2)
1106{
1107 struct sky2_tx_le *le;
1108
1109 sky2->tx_prod = sky2->tx_cons = 0;
1110 sky2->tx_tcpsum = 0;
1111 sky2->tx_last_mss = 0;
1112
9b289c33 1113 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1114 le->addr = 0;
1115 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1116 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1117}
1118
290d4de5
SH		 1119/* Update chip's next pointer */
1120static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1121{
50432cb5 1122 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1123 wmb();
50432cb5
SH		 1124 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1125
1126 /* Synchronize I/O on since next processor may write to tail */
1127 mmiowb();
cd28ab6a
SH		 1128}
1129
793b883e 1130
cd28ab6a
SH		 1131static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1132{
1133 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1134 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1135 le->ctrl = 0;
cd28ab6a
SH		 1136 return le;
1137}
1138
060b946c 1139static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
39ef110b
MM		 1140{
1141 unsigned size;
1142
1143 /* Space needed for frame data + headers rounded up */
1144 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1145
1146 /* Stopping point for hardware truncation */
1147 return (size - 8) / sizeof(u32);
1148}
1149
060b946c 1150static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
39ef110b
MM		 1151{
1152 struct rx_ring_info *re;
1153 unsigned size;
1154
1155 /* Space needed for frame data + headers rounded up */
1156 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1157
1158 sky2->rx_nfrags = size >> PAGE_SHIFT;
1159 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1160
1161 /* Compute residue after pages */
1162 size -= sky2->rx_nfrags << PAGE_SHIFT;
1163
1164 /* Optimize to handle small packets and headers */
1165 if (size < copybreak)
1166 size = copybreak;
1167 if (size < ETH_HLEN)
1168 size = ETH_HLEN;
1169
1170 return size;
1171}
1172
14d0263f 1173/* Build description to hardware for one receive segment */
060b946c 1174static void sky2_rx_add(struct sky2_port *sky2, u8 op,
14d0263f 1175 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1176{
1177 struct sky2_rx_le *le;
1178
86c6887e 1179 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1180 le = sky2_next_rx(sky2);
86c6887e 1181 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1182 le->opcode = OP_ADDR64 | HW_OWNER;
1183 }
793b883e 1184
cd28ab6a 1185 le = sky2_next_rx(sky2);
d6e74b6b 1186 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1187 le->length = cpu_to_le16(len);
14d0263f 1188 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1189}
1190
14d0263f
SH		 1191/* Build description to hardware for one possibly fragmented skb */
1192static void sky2_rx_submit(struct sky2_port *sky2,
1193 const struct rx_ring_info *re)
1194{
1195 int i;
1196
1197 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1198
1199 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1200 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1201}
1202
1203
454e6cb6 1204static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1205 unsigned size)
1206{
1207 struct sk_buff *skb = re->skb;
1208 int i;
1209
1210 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1211 if (pci_dma_mapping_error(pdev, re->data_addr))
1212 goto mapping_error;
454e6cb6 1213
7cd26ce5 1214 dma_unmap_len_set(re, data_size, size);
14d0263f 1215
3fbd9187 1216 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 1217 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3fbd9187 1218
950a5a4f 1219 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
9e903e08 1220 skb_frag_size(frag),
5d6bcdfe 1221 DMA_FROM_DEVICE);
3fbd9187 1222
5d6bcdfe 1223 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
3fbd9187 1224 goto map_page_error;
1225 }
454e6cb6 1226 return 0;
3fbd9187 1227
1228map_page_error:
1229 while (--i >= 0) {
1230 pci_unmap_page(pdev, re->frag_addr[i],
9e903e08 1231 skb_frag_size(&skb_shinfo(skb)->frags[i]),
3fbd9187 1232 PCI_DMA_FROMDEVICE);
1233 }
1234
7cd26ce5 1235 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
3fbd9187 1236 PCI_DMA_FROMDEVICE);
1237
1238mapping_error:
1239 if (net_ratelimit())
1240 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1241 skb->dev->name);
1242 return -EIO;
14d0263f
SH		 1243}
1244
1245static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1246{
1247 struct sk_buff *skb = re->skb;
1248 int i;
1249
7cd26ce5 1250 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
14d0263f
SH		 1251 PCI_DMA_FROMDEVICE);
1252
1253 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1254 pci_unmap_page(pdev, re->frag_addr[i],
9e903e08 1255 skb_frag_size(&skb_shinfo(skb)->frags[i]),
14d0263f
SH		 1256 PCI_DMA_FROMDEVICE);
1257}
793b883e 1258
cd28ab6a
SH		 1259/* Tell chip where to start receive checksum.
1260 * Actually has two checksums, but set both same to avoid possible byte
1261 * order problems.
1262 */
793b883e 1263static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1264{
ea76e635 1265 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1266
ea76e635
SH		 1267 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1268 le->ctrl = 0;
1269 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1270
ea76e635
SH		 1271 sky2_write32(sky2->hw,
1272 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
f5d64037 1273 (sky2->netdev->features & NETIF_F_RXCSUM)
0ea065e5 1274 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1275}
1276
bf73130d 1277/* Enable/disable receive hash calculation (RSS) */
c8f44aff 1278static void rx_set_rss(struct net_device *dev, netdev_features_t features)
bf73130d
SH		 1279{
1280 struct sky2_port *sky2 = netdev_priv(dev);
1281 struct sky2_hw *hw = sky2->hw;
1282 int i, nkeys = 4;
1283
1284 /* Supports IPv6 and other modes */
1285 if (hw->flags & SKY2_HW_NEW_LE) {
1286 nkeys = 10;
1287 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1288 }
1289
1290 /* Program RSS initial values */
f5d64037 1291 if (features & NETIF_F_RXHASH) {
bf73130d
SH		 1292 u32 key[nkeys];
1293
1294 get_random_bytes(key, nkeys * sizeof(u32));
1295 for (i = 0; i < nkeys; i++)
1296 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1297 key[i]);
1298
1299 /* Need to turn on (undocumented) flag to make hashing work */
1300 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1301 RX_STFW_ENA);
1302
1303 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1304 BMU_ENA_RX_RSS_HASH);
1305 } else
1306 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1307 BMU_DIS_RX_RSS_HASH);
1308}
1309
6b1a3aef 1310/*
1311 * The RX Stop command will not work for Yukon-2 if the BMU does not
1312 * reach the end of packet and since we can't make sure that we have
1313 * incoming data, we must reset the BMU while it is not doing a DMA
1314 * transfer. Since it is possible that the RX path is still active,
1315 * the RX RAM buffer will be stopped first, so any possible incoming
1316 * data will not trigger a DMA. After the RAM buffer is stopped, the
1317 * BMU is polled until any DMA in progress is ended and only then it
1318 * will be reset.
1319 */
1320static void sky2_rx_stop(struct sky2_port *sky2)
1321{
1322 struct sky2_hw *hw = sky2->hw;
1323 unsigned rxq = rxqaddr[sky2->port];
1324 int i;
1325
1326 /* disable the RAM Buffer receive queue */
1327 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1328
1329 for (i = 0; i < 0xffff; i++)
1330 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1331 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1332 goto stopped;
1333
ada1db5c 1334 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef 1335stopped:
1336 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1337
1338 /* reset the Rx prefetch unit */
1339 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1340 mmiowb();
6b1a3aef 1341}
793b883e 1342
d571b694 1343/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1344static void sky2_rx_clean(struct sky2_port *sky2)
1345{
1346 unsigned i;
1347
1348 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1349 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1350 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1351
1352 if (re->skb) {
14d0263f 1353 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1354 kfree_skb(re->skb);
1355 re->skb = NULL;
1356 }
1357 }
1358}
1359
ef743d33 1360/* Basic MII support */
1361static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1362{
1363 struct mii_ioctl_data *data = if_mii(ifr);
1364 struct sky2_port *sky2 = netdev_priv(dev);
1365 struct sky2_hw *hw = sky2->hw;
1366 int err = -EOPNOTSUPP;
1367
1368 if (!netif_running(dev))
1369 return -ENODEV; /* Phy still in reset */
1370
d89e1343 1371 switch (cmd) {
ef743d33 1372 case SIOCGMIIPHY:
1373 data->phy_id = PHY_ADDR_MARV;
1374
1375 /* fallthru */
1376 case SIOCGMIIREG: {
1377 u16 val = 0;
91c86df5 1378
e07b1aa8 1379 spin_lock_bh(&sky2->phy_lock);
ef743d33 1380 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1381 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1382
ef743d33 1383 data->val_out = val;
1384 break;
1385 }
1386
1387 case SIOCSMIIREG:
e07b1aa8 1388 spin_lock_bh(&sky2->phy_lock);
ef743d33 1389 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1390 data->val_in);
e07b1aa8 1391 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1392 break;
1393 }
1394 return err;
1395}
1396
f5d64037 1397#define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
d494eacd 1398
c8f44aff 1399static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
d494eacd
SH		 1400{
1401 struct sky2_port *sky2 = netdev_priv(dev);
1402 struct sky2_hw *hw = sky2->hw;
1403 u16 port = sky2->port;
1404
f5d64037 1405 if (features & NETIF_F_HW_VLAN_RX)
86aa7785
SH		 1406 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1407 RX_VLAN_STRIP_ON);
1408 else
1409 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1410 RX_VLAN_STRIP_OFF);
d494eacd 1411
f5d64037 1412 if (features & NETIF_F_HW_VLAN_TX) {
86aa7785
SH		 1413 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1414 TX_VLAN_TAG_ON);
f5d64037
MM		 1415
1416 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1417 } else {
86aa7785
SH		 1418 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1419 TX_VLAN_TAG_OFF);
d1f13708 1420
86aa7785 1421 /* Can't do transmit offload of vlan without hw vlan */
f5d64037 1422 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
86aa7785 1423 }
d1f13708 1424}
d1f13708 1425
bd1c6869
SH		 1426/* Amount of required worst case padding in rx buffer */
1427static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1428{
1429 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1430}
1431
82788c7a 1432/*
14d0263f
SH		 1433 * Allocate an skb for receiving. If the MTU is large enough
1434 * make the skb non-linear with a fragment list of pages.
82788c7a 1435 */
68ac3191 1436static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
82788c7a
SH		 1437{
1438 struct sk_buff *skb;
14d0263f 1439 int i;
82788c7a 1440
68ac3191
ED		 1441 skb = __netdev_alloc_skb(sky2->netdev,
1442 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1443 gfp);
bd1c6869
SH		 1444 if (!skb)
1445 goto nomem;
1446
39dbd958 1447 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1448 unsigned char *start;
1449 /*
1450 * Workaround for a bug in FIFO that cause hang
1451 * if the FIFO if the receive buffer is not 64 byte aligned.
1452 * The buffer returned from netdev_alloc_skb is
1453 * aligned except if slab debugging is enabled.
1454 */
f03b8654
SH		 1455 start = PTR_ALIGN(skb->data, 8);
1456 skb_reserve(skb, start - skb->data);
bd1c6869 1457 } else
f03b8654 1458 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1459
1460 for (i = 0; i < sky2->rx_nfrags; i++) {
68ac3191 1461 struct page *page = alloc_page(gfp);
14d0263f
SH		 1462
1463 if (!page)
1464 goto free_partial;
1465 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1466 }
1467
1468 return skb;
14d0263f
SH		 1469free_partial:
1470 kfree_skb(skb);
1471nomem:
1472 return NULL;
82788c7a
SH		 1473}
1474
55c9dd35
SH		 1475static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1476{
1477 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1478}
1479
200ac492
MM		 1480static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1481{
1482 struct sky2_hw *hw = sky2->hw;
1483 unsigned i;
1484
1485 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1486
1487 /* Fill Rx ring */
1488 for (i = 0; i < sky2->rx_pending; i++) {
1489 struct rx_ring_info *re = sky2->rx_ring + i;
1490
68ac3191 1491 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
200ac492
MM		 1492 if (!re->skb)
1493 return -ENOMEM;
1494
1495 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1496 dev_kfree_skb(re->skb);
1497 re->skb = NULL;
1498 return -ENOMEM;
1499 }
1500 }
1501 return 0;
1502}
1503
cd28ab6a 1504/*
200ac492 1505 * Setup receiver buffer pool.
14d0263f
SH		 1506 * Normal case this ends up creating one list element for skb
1507 * in the receive ring. Worst case if using large MTU and each
1508 * allocation falls on a different 64 bit region, that results
1509 * in 6 list elements per ring entry.
1510 * One element is used for checksum enable/disable, and one
1511 * extra to avoid wrap.
cd28ab6a 1512 */
200ac492 1513static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1514{
6b1a3aef 1515 struct sky2_hw *hw = sky2->hw;
14d0263f 1516 struct rx_ring_info *re;
6b1a3aef 1517 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1518 unsigned i, thresh;
cd28ab6a 1519
6b1a3aef 1520 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1521 sky2_qset(hw, rxq);
977bdf06 1522
c3905bc4 1523 /* On PCI express lowering the watermark gives better performance */
1a10ccae 1524 if (pci_is_pcie(hw->pdev))
c3905bc4
SH		 1525 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1526
1527 /* These chips have no ram buffer?
1528 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1529 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c1cd0a85 1530 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
f449c7c1 1531 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1532
6b1a3aef 1533 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1534
ea76e635
SH		 1535 if (!(hw->flags & SKY2_HW_NEW_LE))
1536 rx_set_checksum(sky2);
14d0263f 1537
bf73130d 1538 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
f5d64037 1539 rx_set_rss(sky2->netdev, sky2->netdev->features);
bf73130d 1540
200ac492 1541 /* submit Rx ring */
793b883e 1542 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1543 re = sky2->rx_ring + i;
14d0263f 1544 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1545 }
1546
a1433ac4
SH		 1547 /*
1548 * The receiver hangs if it receives frames larger than the
1549 * packet buffer. As a workaround, truncate oversize frames, but
1550 * the register is limited to 9 bits, so if you do frames > 2052
1551 * you better get the MTU right!
1552 */
39ef110b 1553 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1554 if (thresh > 0x1ff)
1555 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1556 else {
1557 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1558 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1559 }
1560
6b1a3aef 1561 /* Tell chip about available buffers */
55c9dd35 1562 sky2_rx_update(sky2, rxq);
877c8570
SH		 1563
1564 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1565 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1566 /*
1567 * Disable flushing of non ASF packets;
1568 * must be done after initializing the BMUs;
1569 * drivers without ASF support should do this too, otherwise
1570 * it may happen that they cannot run on ASF devices;
1571 * remember that the MAC FIFO isn't reset during initialization.
1572 */
1573 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1574 }
1575
1576 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1577 /* Enable RX Home Address & Routing Header checksum fix */
1578 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1579 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1580
1581 /* Enable TX Home Address & Routing Header checksum fix */
1582 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1583 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1584 }
cd28ab6a
SH		 1585}
1586
90bbebb4
MM		 1587static int sky2_alloc_buffers(struct sky2_port *sky2)
1588{
1589 struct sky2_hw *hw = sky2->hw;
1590
1591 /* must be power of 2 */
1592 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1593 sky2->tx_ring_size *
1594 sizeof(struct sky2_tx_le),
1595 &sky2->tx_le_map);
1596 if (!sky2->tx_le)
1597 goto nomem;
1598
1599 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1600 GFP_KERNEL);
1601 if (!sky2->tx_ring)
1602 goto nomem;
1603
1604 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1605 &sky2->rx_le_map);
1606 if (!sky2->rx_le)
1607 goto nomem;
1608 memset(sky2->rx_le, 0, RX_LE_BYTES);
1609
1610 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1611 GFP_KERNEL);
1612 if (!sky2->rx_ring)
1613 goto nomem;
1614
200ac492 1615 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1616nomem:
1617 return -ENOMEM;
1618}
1619
1620static void sky2_free_buffers(struct sky2_port *sky2)
1621{
1622 struct sky2_hw *hw = sky2->hw;
1623
200ac492
MM		 1624 sky2_rx_clean(sky2);
1625
90bbebb4
MM		 1626 if (sky2->rx_le) {
1627 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1628 sky2->rx_le, sky2->rx_le_map);
1629 sky2->rx_le = NULL;
1630 }
1631 if (sky2->tx_le) {
1632 pci_free_consistent(hw->pdev,
1633 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1634 sky2->tx_le, sky2->tx_le_map);
1635 sky2->tx_le = NULL;
1636 }
1637 kfree(sky2->tx_ring);
1638 kfree(sky2->rx_ring);
1639
1640 sky2->tx_ring = NULL;
1641 sky2->rx_ring = NULL;
1642}
1643
ea0f71e5 1644static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1645{
cd28ab6a
SH		 1646 struct sky2_hw *hw = sky2->hw;
1647 unsigned port = sky2->port;
ea0f71e5
MM		 1648 u32 ramsize;
1649 int cap;
843a46f4 1650 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1651
ea0f71e5
MM		 1652 tx_init(sky2);
1653
ee7abb04
SH		 1654 /*
1655 * On dual port PCI-X card, there is an problem where status
1656 * can be received out of order due to split transactions
843a46f4 1657 */
ee7abb04
SH		 1658 if (otherdev && netif_running(otherdev) &&
1659 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1660 u16 cmd;
1661
b32f40c4 1662 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1663 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1664 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1665 }
cd28ab6a 1666
cd28ab6a
SH		 1667 sky2_mac_init(hw, port);
1668
e0c28116
SH		 1669 /* Register is number of 4K blocks on internal RAM buffer. */
1670 ramsize = sky2_read8(hw, B2_E_0) * 4;
1671 if (ramsize > 0) {
67712901 1672 u32 rxspace;
cd28ab6a 1673
ada1db5c 1674 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1675 if (ramsize < 16)
1676 rxspace = ramsize / 2;
1677 else
1678 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1679
67712901
SH		 1680 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1681 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1682
1683 /* Make sure SyncQ is disabled */
1684 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1685 RB_RST_SET);
1686 }
793b883e 1687
af4ed7e6 1688 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1689
69161611
SH		 1690 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1691 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1692 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1693
977bdf06 1694 /* Set almost empty threshold */
8e95a202
JP		 1695 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1696 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1697 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1698
6b1a3aef 1699 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1700 sky2->tx_ring_size - 1);
cd28ab6a 1701
f5d64037
MM		 1702 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1703 netdev_update_features(sky2->netdev);
d494eacd 1704
200ac492 1705 sky2_rx_start(sky2);
ea0f71e5
MM		 1706}
1707
0bdb0bd0 1708/* Setup device IRQ and enable napi to process */
1709static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1710{
1711 struct pci_dev *pdev = hw->pdev;
1712 int err;
1713
1714 err = request_irq(pdev->irq, sky2_intr,
1715 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1716 name, hw);
1717 if (err)
1718 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1719 else {
1720 napi_enable(&hw->napi);
1721 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1722 sky2_read32(hw, B0_IMSK);
1723 }
1724
1725 return err;
1726}
1727
1728
ea0f71e5
MM		 1729/* Bring up network interface. */
1730static int sky2_up(struct net_device *dev)
1731{
1732 struct sky2_port *sky2 = netdev_priv(dev);
1733 struct sky2_hw *hw = sky2->hw;
1734 unsigned port = sky2->port;
1735 u32 imask;
1736 int err;
1737
1738 netif_carrier_off(dev);
1739
1740 err = sky2_alloc_buffers(sky2);
1741 if (err)
1742 goto err_out;
1743
0bdb0bd0 1744 /* With single port, IRQ is setup when device is brought up */
1745 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1746 goto err_out;
1747
ea0f71e5 1748 sky2_hw_up(sky2);
cd28ab6a 1749
cd28ab6a 1750 /* Enable interrupts from phy/mac for port */
e07b1aa8 1751 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1752 imask |= portirq_msk[port];
e07b1aa8 1753 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1754 sky2_read32(hw, B0_IMSK);
e07b1aa8 1755
6c35abae 1756 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1757
cd28ab6a
SH		 1758 return 0;
1759
1760err_out:
90bbebb4 1761 sky2_free_buffers(sky2);
cd28ab6a
SH		 1762 return err;
1763}
1764
793b883e 1765/* Modular subtraction in ring */
ee5f68fe 1766static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1767{
ee5f68fe 1768 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1769}
cd28ab6a 1770
793b883e
SH		 1771/* Number of list elements available for next tx */
1772static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1773{
ee5f68fe 1774 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1775}
1776
793b883e 1777/* Estimate of number of transmit list elements required */
28bd181a 1778static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1779{
793b883e
SH		 1780 unsigned count;
1781
07e31637
SH		 1782 count = (skb_shinfo(skb)->nr_frags + 1)
1783 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1784
89114afd 1785 if (skb_is_gso(skb))
793b883e 1786 ++count;
07e31637
SH		 1787 else if (sizeof(dma_addr_t) == sizeof(u32))
1788 ++count; /* possible vlan */
793b883e 1789
84fa7933 1790 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1791 ++count;
1792
1793 return count;
cd28ab6a
SH		 1794}
1795
f6815077 1796static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1797{
1798 if (re->flags & TX_MAP_SINGLE)
7cd26ce5
FT		 1799 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1800 dma_unmap_len(re, maplen),
6b84daca
SH		 1801 PCI_DMA_TODEVICE);
1802 else if (re->flags & TX_MAP_PAGE)
7cd26ce5
FT		 1803 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1804 dma_unmap_len(re, maplen),
6b84daca 1805 PCI_DMA_TODEVICE);
f6815077 1806 re->flags = 0;
6b84daca
SH		 1807}
1808
793b883e
SH		 1809/*
1810 * Put one packet in ring for transmit.
1811 * A single packet can generate multiple list elements, and
1812 * the number of ring elements will probably be less than the number
1813 * of list elements used.
1814 */
61357325
SH		 1815static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1816 struct net_device *dev)
cd28ab6a
SH		 1817{
1818 struct sky2_port *sky2 = netdev_priv(dev);
1819 struct sky2_hw *hw = sky2->hw;
d1f13708 1820 struct sky2_tx_le *le = NULL;
6cdbbdf3 1821 struct tx_ring_info *re;
9b289c33 1822 unsigned i, len;
cd28ab6a 1823 dma_addr_t mapping;
5dce95e5
SH		 1824 u32 upper;
1825 u16 slot;
cd28ab6a
SH		 1826 u16 mss;
1827 u8 ctrl;
1828
2bb8c262
SH		 1829 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1830 return NETDEV_TX_BUSY;
cd28ab6a 1831
cd28ab6a
SH		 1832 len = skb_headlen(skb);
1833 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1834
454e6cb6
SH		 1835 if (pci_dma_mapping_error(hw->pdev, mapping))
1836 goto mapping_error;
1837
9b289c33 1838 slot = sky2->tx_prod;
6c35abae
JP		 1839 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1840 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1841
86c6887e 1842 /* Send high bits if needed */
5dce95e5
SH		 1843 upper = upper_32_bits(mapping);
1844 if (upper != sky2->tx_last_upper) {
9b289c33 1845 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1846 le->addr = cpu_to_le32(upper);
1847 sky2->tx_last_upper = upper;
793b883e 1848 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1849 }
cd28ab6a
SH		 1850
1851 /* Check for TCP Segmentation Offload */
7967168c 1852 mss = skb_shinfo(skb)->gso_size;
793b883e 1853 if (mss != 0) {
ea76e635
SH		 1854
1855 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1856 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1857
1858 if (mss != sky2->tx_last_mss) {
9b289c33 1859 le = get_tx_le(sky2, &slot);
69161611 1860 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1861
1862 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1863 le->opcode = OP_MSS | HW_OWNER;
1864 else
1865 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1866 sky2->tx_last_mss = mss;
1867 }
cd28ab6a
SH		 1868 }
1869
cd28ab6a 1870 ctrl = 0;
86aa7785 1871
d1f13708 1872 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
eab6d18d 1873 if (vlan_tx_tag_present(skb)) {
d1f13708 1874 if (!le) {
9b289c33 1875 le = get_tx_le(sky2, &slot);
f65b138c 1876 le->addr = 0;
d1f13708 1877 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1878 } else
1879 le->opcode |= OP_VLAN;
1880 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1881 ctrl |= INS_VLAN;
1882 }
d1f13708 1883
1884 /* Handle TCP checksum offload */
84fa7933 1885 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1886 /* On Yukon EX (some versions) encoding change. */
ea76e635 1887 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1888 ctrl |= CALSUM; /* auto checksum */
1889 else {
1890 const unsigned offset = skb_transport_offset(skb);
1891 u32 tcpsum;
1892
1893 tcpsum = offset << 16; /* sum start */
1894 tcpsum |= offset + skb->csum_offset; /* sum write */
1895
1896 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1897 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1898 ctrl |= UDPTCP;
1899
1900 if (tcpsum != sky2->tx_tcpsum) {
1901 sky2->tx_tcpsum = tcpsum;
1902
9b289c33 1903 le = get_tx_le(sky2, &slot);
69161611
SH		 1904 le->addr = cpu_to_le32(tcpsum);
1905 le->length = 0; /* initial checksum value */
1906 le->ctrl = 1; /* one packet */
1907 le->opcode = OP_TCPLISW | HW_OWNER;
1908 }
1d179332 1909 }
cd28ab6a
SH		 1910 }
1911
6b84daca
SH		 1912 re = sky2->tx_ring + slot;
1913 re->flags = TX_MAP_SINGLE;
7cd26ce5
FT		 1914 dma_unmap_addr_set(re, mapaddr, mapping);
1915 dma_unmap_len_set(re, maplen, len);
6b84daca 1916
9b289c33 1917 le = get_tx_le(sky2, &slot);
d6e74b6b 1918 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1919 le->length = cpu_to_le16(len);
1920 le->ctrl = ctrl;
793b883e 1921 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1922
cd28ab6a
SH		 1923
1924 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1925 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a 1926
950a5a4f 1927 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
9e903e08 1928 skb_frag_size(frag), DMA_TO_DEVICE);
86c6887e 1929
5d6bcdfe 1930 if (dma_mapping_error(&hw->pdev->dev, mapping))
454e6cb6
SH		 1931 goto mapping_unwind;
1932
5dce95e5
SH		 1933 upper = upper_32_bits(mapping);
1934 if (upper != sky2->tx_last_upper) {
9b289c33 1935 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1936 le->addr = cpu_to_le32(upper);
1937 sky2->tx_last_upper = upper;
793b883e 1938 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1939 }
1940
6b84daca
SH		 1941 re = sky2->tx_ring + slot;
1942 re->flags = TX_MAP_PAGE;
7cd26ce5 1943 dma_unmap_addr_set(re, mapaddr, mapping);
9e903e08 1944 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
6b84daca 1945
9b289c33 1946 le = get_tx_le(sky2, &slot);
d6e74b6b 1947 le->addr = cpu_to_le32(lower_32_bits(mapping));
9e903e08 1948 le->length = cpu_to_le16(skb_frag_size(frag));
cd28ab6a 1949 le->ctrl = ctrl;
793b883e 1950 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1951 }
6cdbbdf3 1952
6b84daca 1953 re->skb = skb;
cd28ab6a
SH		 1954 le->ctrl |= EOP;
1955
9b289c33
MM		 1956 sky2->tx_prod = slot;
1957
97bda706 1958 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1959 netif_stop_queue(dev);
b19666d9 1960
290d4de5 1961 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1962
cd28ab6a 1963 return NETDEV_TX_OK;
454e6cb6
SH		 1964
1965mapping_unwind:
ee5f68fe 1966 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1967 re = sky2->tx_ring + i;
1968
6b84daca 1969 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1970 }
1971
454e6cb6
SH		 1972mapping_error:
1973 if (net_ratelimit())
1974 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1975 dev_kfree_skb(skb);
1976 return NETDEV_TX_OK;
cd28ab6a
SH		 1977}
1978
cd28ab6a 1979/*
793b883e
SH		 1980 * Free ring elements from starting at tx_cons until "done"
1981 *
481cea4a
SH		 1982 * NB:
1983 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1984 * buffers so make sure not to free skb to early.
481cea4a
SH		 1985 * 2. This may run in parallel start_xmit because the it only
1986 * looks at the tail of the queue of FIFO (tx_cons), not
1987 * the head (tx_prod)
cd28ab6a 1988 */
d11c13e7 1989static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1990{
d11c13e7 1991 struct net_device *dev = sky2->netdev;
291ea614 1992 unsigned idx;
cd28ab6a 1993
ee5f68fe 1994 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1995
291ea614 1996 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1997 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1998 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1999 struct sk_buff *skb = re->skb;
291ea614 2000
6b84daca 2001 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 2002
6b84daca 2003 if (skb) {
6c35abae
JP		 2004 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2005 "tx done %u\n", idx);
3cf26753 2006
0885a30b 2007 u64_stats_update_begin(&sky2->tx_stats.syncp);
2008 ++sky2->tx_stats.packets;
2009 sky2->tx_stats.bytes += skb->len;
2010 u64_stats_update_end(&sky2->tx_stats.syncp);
bd1c6869 2011
f6815077 2012 re->skb = NULL;
724b6942 2013 dev_kfree_skb_any(skb);
2bf56fe2 2014
ee5f68fe 2015 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 2016 }
793b883e 2017 }
793b883e 2018
291ea614 2019 sky2->tx_cons = idx;
50432cb5 2020 smp_mb();
cd28ab6a
SH		 2021}
2022
264bb4fa 2023static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 2024{
a510996b
MM		 2025 /* Disable Force Sync bit and Enable Alloc bit */
2026 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2027 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2028
2029 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2030 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2031 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2032
2033 /* Reset the PCI FIFO of the async Tx queue */
2034 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2035 BMU_RST_SET | BMU_FIFO_RST);
2036
2037 /* Reset the Tx prefetch units */
2038 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2039 PREF_UNIT_RST_SET);
2040
2041 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2042 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2043}
2044
f2b31cb3 2045static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 2046{
cd28ab6a
SH		 2047 struct sky2_hw *hw = sky2->hw;
2048 unsigned port = sky2->port;
f2b31cb3 2049 u16 ctrl;
cd28ab6a 2050
d104acaf
SH		 2051 /* Force flow control off */
2052 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 2053
cd28ab6a
SH		 2054 /* Stop transmitter */
2055 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2056 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2057
2058 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 2059 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 2060
2061 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 2062 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 2063 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2064
2065 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2066
2067 /* Workaround shared GMAC reset */
8e95a202
JP		 2068 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2069 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 2070 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2071
cd28ab6a 2072 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 2073
fb914ebf 2074 /* Force any delayed status interrupt and NAPI */
6c83504f
SH		 2075 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2076 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2077 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2078 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2079
a947a39d
MM		 2080 sky2_rx_stop(sky2);
2081
0da6d7b3 2082 spin_lock_bh(&sky2->phy_lock);
b96936da 2083 sky2_phy_power_down(hw, port);
0da6d7b3 2084 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 2085
264bb4fa
MM		 2086 sky2_tx_reset(hw, port);
2087
481cea4a
SH		 2088 /* Free any pending frames stuck in HW queue */
2089 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 2090}
2091
2092/* Network shutdown */
2093static int sky2_down(struct net_device *dev)
2094{
2095 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 2096 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 2097
2098 /* Never really got started! */
2099 if (!sky2->tx_le)
2100 return 0;
2101
6c35abae 2102 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 2103
8a0c9228
MM		 2104 /* Disable port IRQ */
2105 sky2_write32(hw, B0_IMSK,
2106 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2107 sky2_read32(hw, B0_IMSK);
2108
0bdb0bd0 2109 if (hw->ports == 1) {
2110 napi_disable(&hw->napi);
2111 free_irq(hw->pdev->irq, hw);
2112 } else {
2113 synchronize_irq(hw->pdev->irq);
2114 napi_synchronize(&hw->napi);
2115 }
8a0c9228 2116
f2b31cb3 2117 sky2_hw_down(sky2);
481cea4a 2118
90bbebb4 2119 sky2_free_buffers(sky2);
1b537565 2120
cd28ab6a
SH		 2121 return 0;
2122}
2123
2124static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2125{
ea76e635 2126 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 2127 return SPEED_1000;
2128
05745c4a
SH		 2129 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2130 if (aux & PHY_M_PS_SPEED_100)
2131 return SPEED_100;
2132 else
2133 return SPEED_10;
2134 }
cd28ab6a
SH		 2135
2136 switch (aux & PHY_M_PS_SPEED_MSK) {
2137 case PHY_M_PS_SPEED_1000:
2138 return SPEED_1000;
2139 case PHY_M_PS_SPEED_100:
2140 return SPEED_100;
2141 default:
2142 return SPEED_10;
2143 }
2144}
2145
2146static void sky2_link_up(struct sky2_port *sky2)
2147{
2148 struct sky2_hw *hw = sky2->hw;
2149 unsigned port = sky2->port;
16ad91e1
SH		 2150 static const char *fc_name[] = {
2151 [FC_NONE] = "none",
2152 [FC_TX] = "tx",
2153 [FC_RX] = "rx",
2154 [FC_BOTH] = "both",
2155 };
cd28ab6a 2156
8e11680f 2157 sky2_set_ipg(sky2);
2158
38000a94 2159 sky2_enable_rx_tx(sky2);
cd28ab6a
SH		 2160
2161 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2162
2163 netif_carrier_on(sky2->netdev);
cd28ab6a 2164
75e80683 2165 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2166
cd28ab6a 2167 /* Turn on link LED */
793b883e 2168 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2169 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2170
6c35abae
JP		 2171 netif_info(sky2, link, sky2->netdev,
2172 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2173 sky2->speed,
2174 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2175 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2176}
2177
2178static void sky2_link_down(struct sky2_port *sky2)
2179{
2180 struct sky2_hw *hw = sky2->hw;
2181 unsigned port = sky2->port;
2182 u16 reg;
2183
2184 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2185
2186 reg = gma_read16(hw, port, GM_GP_CTRL);
2187 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2188 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2189
cd28ab6a 2190 netif_carrier_off(sky2->netdev);
cd28ab6a 2191
809aaaae 2192 /* Turn off link LED */
cd28ab6a
SH		 2193 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2194
6c35abae 2195 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2196
cd28ab6a
SH		 2197 sky2_phy_init(hw, port);
2198}
2199
16ad91e1
SH		 2200static enum flow_control sky2_flow(int rx, int tx)
2201{
2202 if (rx)
2203 return tx ? FC_BOTH : FC_RX;
2204 else
2205 return tx ? FC_TX : FC_NONE;
2206}
2207
793b883e
SH		 2208static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2209{
2210 struct sky2_hw *hw = sky2->hw;
2211 unsigned port = sky2->port;
da4c1ff4 2212 u16 advert, lpa;
793b883e 2213
da4c1ff4 2214 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2215 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2216 if (lpa & PHY_M_AN_RF) {
ada1db5c 2217 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2218 return -1;
2219 }
2220
793b883e 2221 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2222 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2223 return -1;
2224 }
2225
793b883e 2226 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2227 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2228
da4c1ff4
SH		 2229 /* Since the pause result bits seem to in different positions on
2230 * different chips. look at registers.
2231 */
ea76e635 2232 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2233 /* Shift for bits in fiber PHY */
2234 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2235 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2236
2237 if (advert & ADVERTISE_1000XPAUSE)
2238 advert |= ADVERTISE_PAUSE_CAP;
2239 if (advert & ADVERTISE_1000XPSE_ASYM)
2240 advert |= ADVERTISE_PAUSE_ASYM;
2241 if (lpa & LPA_1000XPAUSE)
2242 lpa |= LPA_PAUSE_CAP;
2243 if (lpa & LPA_1000XPAUSE_ASYM)
2244 lpa |= LPA_PAUSE_ASYM;
2245 }
793b883e 2246
da4c1ff4
SH		 2247 sky2->flow_status = FC_NONE;
2248 if (advert & ADVERTISE_PAUSE_CAP) {
2249 if (lpa & LPA_PAUSE_CAP)
2250 sky2->flow_status = FC_BOTH;
2251 else if (advert & ADVERTISE_PAUSE_ASYM)
2252 sky2->flow_status = FC_RX;
2253 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2254 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2255 sky2->flow_status = FC_TX;
2256 }
793b883e 2257
8e95a202
JP		 2258 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2259 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2260 sky2->flow_status = FC_NONE;
2eaba1a2 2261
da4c1ff4 2262 if (sky2->flow_status & FC_TX)
793b883e
SH		 2263 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2264 else
2265 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2266
2267 return 0;
2268}
cd28ab6a 2269
e07b1aa8
SH		 2270/* Interrupt from PHY */
2271static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2272{
e07b1aa8
SH		 2273 struct net_device *dev = hw->dev[port];
2274 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2275 u16 istatus, phystat;
2276
ebc646f6
SH		 2277 if (!netif_running(dev))
2278 return;
2279
e07b1aa8
SH		 2280 spin_lock(&sky2->phy_lock);
2281 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2282 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2283
6c35abae
JP		 2284 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2285 istatus, phystat);
cd28ab6a 2286
0ea065e5 2287 if (istatus & PHY_M_IS_AN_COMPL) {
9badba25 2288 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2289 !netif_carrier_ok(dev))
793b883e
SH		 2290 sky2_link_up(sky2);
2291 goto out;
2292 }
cd28ab6a 2293
793b883e
SH		 2294 if (istatus & PHY_M_IS_LSP_CHANGE)
2295 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2296
793b883e
SH		 2297 if (istatus & PHY_M_IS_DUP_CHANGE)
2298 sky2->duplex =
2299 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2300
793b883e
SH		 2301 if (istatus & PHY_M_IS_LST_CHANGE) {
2302 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2303 sky2_link_up(sky2);
793b883e
SH		 2304 else
2305 sky2_link_down(sky2);
cd28ab6a 2306 }
793b883e 2307out:
e07b1aa8 2308 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2309}
2310
0f5aac70
SH		 2311/* Special quick link interrupt (Yukon-2 Optima only) */
2312static void sky2_qlink_intr(struct sky2_hw *hw)
2313{
2314 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2315 u32 imask;
2316 u16 phy;
2317
2318 /* disable irq */
2319 imask = sky2_read32(hw, B0_IMSK);
2320 imask &= ~Y2_IS_PHY_QLNK;
2321 sky2_write32(hw, B0_IMSK, imask);
2322
2323 /* reset PHY Link Detect */
2324 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2325 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2326 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2327 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2328
2329 sky2_link_up(sky2);
2330}
2331
62335ab0 2332/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2333 * and tx queue is full (stopped).
2334 */
cd28ab6a
SH		 2335static void sky2_tx_timeout(struct net_device *dev)
2336{
2337 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2338 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2339
6c35abae 2340 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2341
ada1db5c
JP		 2342 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2343 sky2->tx_cons, sky2->tx_prod,
2344 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2345 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2346
81906791
SH		 2347 /* can't restart safely under softirq */
2348 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2349}
2350
2351static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2352{
6b1a3aef 2353 struct sky2_port *sky2 = netdev_priv(dev);
2354 struct sky2_hw *hw = sky2->hw;
b628ed98 2355 unsigned port = sky2->port;
6b1a3aef 2356 int err;
2357 u16 ctl, mode;
e07b1aa8 2358 u32 imask;
cd28ab6a 2359
44dde56d 2360 /* MTU size outside the spec */
cd28ab6a
SH		 2361 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2362 return -EINVAL;
2363
44dde56d 2364 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2365 if (new_mtu > ETH_DATA_LEN &&
2366 (hw->chip_id == CHIP_ID_YUKON_FE ||
2367 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2368 return -EINVAL;
2369
6b1a3aef 2370 if (!netif_running(dev)) {
2371 dev->mtu = new_mtu;
f5d64037 2372 netdev_update_features(dev);
6b1a3aef 2373 return 0;
2374 }
2375
e07b1aa8 2376 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2377 sky2_write32(hw, B0_IMSK, 0);
2378
018d1c66 2379 dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 2380 napi_disable(&hw->napi);
df01093b 2381 netif_tx_disable(dev);
018d1c66 2382
e07b1aa8
SH		 2383 synchronize_irq(hw->pdev->irq);
2384
39dbd958 2385 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2386 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2387
2388 ctl = gma_read16(hw, port, GM_GP_CTRL);
2389 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2390 sky2_rx_stop(sky2);
2391 sky2_rx_clean(sky2);
cd28ab6a
SH		 2392
2393 dev->mtu = new_mtu;
f5d64037 2394 netdev_update_features(dev);
14d0263f 2395
8e11680f 2396 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2397 if (sky2->speed > SPEED_100)
2398 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2399 else
2400 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
6b1a3aef 2401
2402 if (dev->mtu > ETH_DATA_LEN)
2403 mode |= GM_SMOD_JUMBO_ENA;
2404
b628ed98 2405 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2406
b628ed98 2407 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2408
200ac492
MM		 2409 err = sky2_alloc_rx_skbs(sky2);
2410 if (!err)
2411 sky2_rx_start(sky2);
2412 else
2413 sky2_rx_clean(sky2);
e07b1aa8 2414 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2415
d1d08d12 2416 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2417 napi_enable(&hw->napi);
2418
1b537565
SH		 2419 if (err)
2420 dev_close(dev);
2421 else {
b628ed98 2422 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2423
1b537565
SH		 2424 netif_wake_queue(dev);
2425 }
2426
cd28ab6a
SH		 2427 return err;
2428}
2429
14d0263f
SH		 2430/* For small just reuse existing skb for next receive */
2431static struct sk_buff *receive_copy(struct sky2_port *sky2,
2432 const struct rx_ring_info *re,
2433 unsigned length)
2434{
2435 struct sk_buff *skb;
2436
89d71a66 2437 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2438 if (likely(skb)) {
14d0263f
SH		 2439 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2440 length, PCI_DMA_FROMDEVICE);
d626f62b 2441 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2442 skb->ip_summed = re->skb->ip_summed;
2443 skb->csum = re->skb->csum;
2444 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2445 length, PCI_DMA_FROMDEVICE);
2446 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2447 skb_put(skb, length);
14d0263f
SH		 2448 }
2449 return skb;
2450}
2451
2452/* Adjust length of skb with fragments to match received data */
2453static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2454 unsigned int length)
2455{
2456 int i, num_frags;
2457 unsigned int size;
2458
2459 /* put header into skb */
2460 size = min(length, hdr_space);
2461 skb->tail += size;
2462 skb->len += size;
2463 length -= size;
2464
2465 num_frags = skb_shinfo(skb)->nr_frags;
2466 for (i = 0; i < num_frags; i++) {
2467 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2468
2469 if (length == 0) {
2470 /* don't need this page */
950a5a4f 2471 __skb_frag_unref(frag);
14d0263f
SH		 2472 --skb_shinfo(skb)->nr_frags;
2473 } else {
2474 size = min(length, (unsigned) PAGE_SIZE);
2475
9e903e08 2476 skb_frag_size_set(frag, size);
14d0263f 2477 skb->data_len += size;
7ae60b3f 2478 skb->truesize += PAGE_SIZE;
14d0263f
SH		 2479 skb->len += size;
2480 length -= size;
2481 }
2482 }
2483}
2484
2485/* Normal packet - take skb from ring element and put in a new one */
2486static struct sk_buff *receive_new(struct sky2_port *sky2,
2487 struct rx_ring_info *re,
2488 unsigned int length)
2489{
3fbd9187 2490 struct sk_buff *skb;
2491 struct rx_ring_info nre;
14d0263f
SH		 2492 unsigned hdr_space = sky2->rx_data_size;
2493
68ac3191 2494 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
3fbd9187 2495 if (unlikely(!nre.skb))
2496 goto nobuf;
2497
2498 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2499 goto nomap;
14d0263f
SH		 2500
2501 skb = re->skb;
2502 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2503 prefetch(skb->data);
3fbd9187 2504 *re = nre;
14d0263f
SH		 2505
2506 if (skb_shinfo(skb)->nr_frags)
2507 skb_put_frags(skb, hdr_space, length);
2508 else
489b10c1 2509 skb_put(skb, length);
14d0263f 2510 return skb;
3fbd9187 2511
2512nomap:
2513 dev_kfree_skb(nre.skb);
2514nobuf:
2515 return NULL;
14d0263f
SH		 2516}
2517
cd28ab6a
SH		 2518/*
2519 * Receive one packet.
d571b694 2520 * For larger packets, get new buffer.
cd28ab6a 2521 */
497d7c86 2522static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2523 u16 length, u32 status)
2524{
497d7c86 2525 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2526 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2527 struct sk_buff *skb = NULL;
d6532232
SH		 2528 u16 count = (status & GMR_FS_LEN) >> 16;
2529
86aa7785
SH		 2530 if (status & GMR_FS_VLAN)
2531 count -= VLAN_HLEN; /* Account for vlan tag */
cd28ab6a 2532
6c35abae
JP		 2533 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2534 "rx slot %u status 0x%x len %d\n",
2535 sky2->rx_next, status, length);
cd28ab6a 2536
793b883e 2537 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2538 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2539
3b12e014
SH		 2540 /* This chip has hardware problems that generates bogus status.
2541 * So do only marginal checking and expect higher level protocols
2542 * to handle crap frames.
2543 */
2544 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2545 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2546 length != count)
2547 goto okay;
2548
42eeea01 2549 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2550 goto error;
2551
42eeea01 2552 if (!(status & GMR_FS_RX_OK))
2553 goto resubmit;
2554
d6532232
SH		 2555 /* if length reported by DMA does not match PHY, packet was truncated */
2556 if (length != count)
0885a30b 2557 goto error;
71749531 2558
3b12e014 2559okay:
14d0263f
SH		 2560 if (length < copybreak)
2561 skb = receive_copy(sky2, re, length);
2562 else
2563 skb = receive_new(sky2, re, length);
90c30335
SH		 2564
2565 dev->stats.rx_dropped += (skb == NULL);
2566
793b883e 2567resubmit:
14d0263f 2568 sky2_rx_submit(sky2, re);
79e57d32 2569
cd28ab6a
SH		 2570 return skb;
2571
2572error:
7138a0f5 2573 ++dev->stats.rx_errors;
6e15b712 2574
6c35abae
JP		 2575 if (net_ratelimit())
2576 netif_info(sky2, rx_err, dev,
2577 "rx error, status 0x%x length %d\n", status, length);
793b883e 2578
793b883e 2579 goto resubmit;
cd28ab6a
SH		 2580}
2581
e07b1aa8
SH		 2582/* Transmit complete */
2583static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2584{
e07b1aa8 2585 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2586
8a0c9228 2587 if (netif_running(dev)) {
e07b1aa8 2588 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2589
2590 /* Wake unless it's detached, and called e.g. from sky2_down() */
2591 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2592 netif_wake_queue(dev);
2593 }
cd28ab6a
SH		 2594}
2595
37e5a243
SH		 2596static inline void sky2_skb_rx(const struct sky2_port *sky2,
2597 u32 status, struct sk_buff *skb)
2598{
86aa7785
SH		 2599 if (status & GMR_FS_VLAN)
2600 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
2601
37e5a243
SH		 2602 if (skb->ip_summed == CHECKSUM_NONE)
2603 netif_receive_skb(skb);
2604 else
2605 napi_gro_receive(&sky2->hw->napi, skb);
2606}
2607
bf15fe99
SH		 2608static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2609 unsigned packets, unsigned bytes)
2610{
0885a30b 2611 struct net_device *dev = hw->dev[port];
2612 struct sky2_port *sky2 = netdev_priv(dev);
bf15fe99 2613
0885a30b 2614 if (packets == 0)
2615 return;
2616
2617 u64_stats_update_begin(&sky2->rx_stats.syncp);
2618 sky2->rx_stats.packets += packets;
2619 sky2->rx_stats.bytes += bytes;
2620 u64_stats_update_end(&sky2->rx_stats.syncp);
2621
2622 dev->last_rx = jiffies;
2623 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
bf15fe99
SH		 2624}
2625
375c5688 2626static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2627{
2628 /* If this happens then driver assuming wrong format for chip type */
2629 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2630
2631 /* Both checksum counters are programmed to start at
2632 * the same offset, so unless there is a problem they
2633 * should match. This failure is an early indication that
2634 * hardware receive checksumming won't work.
2635 */
2636 if (likely((u16)(status >> 16) == (u16)status)) {
2637 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2638 skb->ip_summed = CHECKSUM_COMPLETE;
2639 skb->csum = le16_to_cpu(status);
2640 } else {
2641 dev_notice(&sky2->hw->pdev->dev,
2642 "%s: receive checksum problem (status = %#x)\n",
2643 sky2->netdev->name, status);
2644
f5d64037
MM		 2645 /* Disable checksum offload
2646 * It will be reenabled on next ndo_set_features, but if it's
2647 * really broken, will get disabled again
2648 */
2649 sky2->netdev->features &= ~NETIF_F_RXCSUM;
375c5688 2650 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2651 BMU_DIS_RX_CHKSUM);
2652 }
2653}
2654
bf73130d
SH		 2655static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2656{
2657 struct sk_buff *skb;
2658
2659 skb = sky2->rx_ring[sky2->rx_next].skb;
2660 skb->rxhash = le32_to_cpu(status);
2661}
2662
e07b1aa8 2663/* Process status response ring */
26691830 2664static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2665{
e07b1aa8 2666 int work_done = 0;
bf15fe99
SH		 2667 unsigned int total_bytes[2] = { 0 };
2668 unsigned int total_packets[2] = { 0 };
a8fd6266 2669
af2a58ac 2670 rmb();
26691830 2671 do {
55c9dd35 2672 struct sky2_port *sky2;
13210ce5 2673 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2674 unsigned port;
13210ce5 2675 struct net_device *dev;
cd28ab6a 2676 struct sk_buff *skb;
cd28ab6a
SH		 2677 u32 status;
2678 u16 length;
ab5adecb
SH		 2679 u8 opcode = le->opcode;
2680
2681 if (!(opcode & HW_OWNER))
2682 break;
cd28ab6a 2683
efe91932 2684 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
bea86103 2685
ab5adecb 2686 port = le->css & CSS_LINK_BIT;
69161611 2687 dev = hw->dev[port];
13210ce5 2688 sky2 = netdev_priv(dev);
f65b138c
SH		 2689 length = le16_to_cpu(le->length);
2690 status = le32_to_cpu(le->status);
cd28ab6a 2691
ab5adecb
SH		 2692 le->opcode = 0;
2693 switch (opcode & ~HW_OWNER) {
cd28ab6a 2694 case OP_RXSTAT:
bf15fe99
SH		 2695 total_packets[port]++;
2696 total_bytes[port] += length;
90c30335 2697
497d7c86 2698 skb = sky2_receive(dev, length, status);
90c30335 2699 if (!skb)
55c9dd35 2700 break;
13210ce5 2701
69161611 2702 /* This chip reports checksum status differently */
05745c4a 2703 if (hw->flags & SKY2_HW_NEW_LE) {
f5d64037 2704 if ((dev->features & NETIF_F_RXCSUM) &&
69161611
SH		 2705 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2706 (le->css & CSS_TCPUDPCSOK))
2707 skb->ip_summed = CHECKSUM_UNNECESSARY;
2708 else
2709 skb->ip_summed = CHECKSUM_NONE;
2710 }
2711
13210ce5 2712 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2713
37e5a243 2714 sky2_skb_rx(sky2, status, skb);
13210ce5 2715
22e11703 2716 /* Stop after net poll weight */
13210ce5 2717 if (++work_done >= to_do)
2718 goto exit_loop;
cd28ab6a
SH		 2719 break;
2720
d1f13708 2721 case OP_RXVLAN:
2722 sky2->rx_tag = length;
2723 break;
2724
2725 case OP_RXCHKSVLAN:
2726 sky2->rx_tag = length;
2727 /* fall through */
cd28ab6a 2728 case OP_RXCHKS:
f5d64037 2729 if (likely(dev->features & NETIF_F_RXCSUM))
375c5688 2730 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2731 break;
2732
bf73130d
SH		 2733 case OP_RSS_HASH:
2734 sky2_rx_hash(sky2, status);
2735 break;
2736
cd28ab6a 2737 case OP_TXINDEXLE:
13b97b74 2738 /* TX index reports status for both ports */
f55925d7 2739 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2740 if (hw->dev[1])
2741 sky2_tx_done(hw->dev[1],
2742 ((status >> 24) & 0xff)
2743 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2744 break;
2745
cd28ab6a
SH		 2746 default:
2747 if (net_ratelimit())
ada1db5c 2748 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2749 }
26691830 2750 } while (hw->st_idx != idx);
cd28ab6a 2751
fe2a24df
SH		 2752 /* Fully processed status ring so clear irq */
2753 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2754
13210ce5 2755exit_loop:
bf15fe99
SH		 2756 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2757 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2758
e07b1aa8 2759 return work_done;
cd28ab6a
SH		 2760}
2761
2762static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2763{
2764 struct net_device *dev = hw->dev[port];
2765
3be92a70 2766 if (net_ratelimit())
ada1db5c 2767 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2768
2769 if (status & Y2_IS_PAR_RD1) {
3be92a70 2770 if (net_ratelimit())
ada1db5c 2771 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2772 /* Clear IRQ */
2773 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2774 }
2775
2776 if (status & Y2_IS_PAR_WR1) {
3be92a70 2777 if (net_ratelimit())
ada1db5c 2778 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2779
2780 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2781 }
2782
2783 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2784 if (net_ratelimit())
ada1db5c 2785 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2786 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2787 }
2788
2789 if (status & Y2_IS_PAR_RX1) {
3be92a70 2790 if (net_ratelimit())
ada1db5c 2791 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2792 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2793 }
2794
2795 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2796 if (net_ratelimit())
ada1db5c 2797 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2798 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2799 }
2800}
2801
2802static void sky2_hw_intr(struct sky2_hw *hw)
2803{
555382cb 2804 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2805 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2806 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2807
2808 status &= hwmsk;
cd28ab6a 2809
793b883e 2810 if (status & Y2_IS_TIST_OV)
cd28ab6a 2811 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2812
2813 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2814 u16 pci_err;
2815
a40ccc68 2816 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2817 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2818 if (net_ratelimit())
555382cb 2819 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2820 pci_err);
cd28ab6a 2821
b32f40c4 2822 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2823 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2824 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2825 }
2826
2827 if (status & Y2_IS_PCI_EXP) {
d571b694 2828 /* PCI-Express uncorrectable Error occurred */
555382cb 2829 u32 err;
cd28ab6a 2830
a40ccc68 2831 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2832 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2833 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2834 0xfffffffful);
3be92a70 2835 if (net_ratelimit())
555382cb 2836 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2837
7782c8c4 2838 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2839 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2840 }
2841
2842 if (status & Y2_HWE_L1_MASK)
2843 sky2_hw_error(hw, 0, status);
2844 status >>= 8;
2845 if (status & Y2_HWE_L1_MASK)
2846 sky2_hw_error(hw, 1, status);
2847}
2848
2849static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2850{
2851 struct net_device *dev = hw->dev[port];
2852 struct sky2_port *sky2 = netdev_priv(dev);
2853 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2854
6c35abae 2855 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2856
a3caeada
SH		 2857 if (status & GM_IS_RX_CO_OV)
2858 gma_read16(hw, port, GM_RX_IRQ_SRC);
2859
2860 if (status & GM_IS_TX_CO_OV)
2861 gma_read16(hw, port, GM_TX_IRQ_SRC);
2862
cd28ab6a 2863 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2864 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2865 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2866 }
2867
2868 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2869 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2870 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2871 }
cd28ab6a
SH		 2872}
2873
40b01727 2874/* This should never happen it is a bug. */
c119731d 2875static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2876{
2877 struct net_device *dev = hw->dev[port];
c119731d 2878 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2879
ada1db5c 2880 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2881 dev->name, (unsigned) q, (unsigned) idx,
2882 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2883
40b01727 2884 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2885}
cd28ab6a 2886
75e80683
SH		 2887static int sky2_rx_hung(struct net_device *dev)
2888{
2889 struct sky2_port *sky2 = netdev_priv(dev);
2890 struct sky2_hw *hw = sky2->hw;
2891 unsigned port = sky2->port;
2892 unsigned rxq = rxqaddr[port];
2893 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2894 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2895 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2896 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2897
2898 /* If idle and MAC or PCI is stuck */
2899 if (sky2->check.last == dev->last_rx &&
2900 ((mac_rp == sky2->check.mac_rp &&
2901 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2902 /* Check if the PCI RX hang */
2903 (fifo_rp == sky2->check.fifo_rp &&
2904 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2905 netdev_printk(KERN_DEBUG, dev,
2906 "hung mac %d:%d fifo %d (%d:%d)\n",
2907 mac_lev, mac_rp, fifo_lev,
2908 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2909 return 1;
2910 } else {
2911 sky2->check.last = dev->last_rx;
2912 sky2->check.mac_rp = mac_rp;
2913 sky2->check.mac_lev = mac_lev;
2914 sky2->check.fifo_rp = fifo_rp;
2915 sky2->check.fifo_lev = fifo_lev;
2916 return 0;
2917 }
2918}
2919
32c2c300 2920static void sky2_watchdog(unsigned long arg)
d27ed387 2921{
01bd7564 2922 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2923
75e80683 2924 /* Check for lost IRQ once a second */
32c2c300 2925 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2926 napi_schedule(&hw->napi);
75e80683
SH		 2927 } else {
2928 int i, active = 0;
2929
2930 for (i = 0; i < hw->ports; i++) {
bea3348e 2931 struct net_device *dev = hw->dev[i];
75e80683
SH		 2932 if (!netif_running(dev))
2933 continue;
2934 ++active;
2935
2936 /* For chips with Rx FIFO, check if stuck */
39dbd958 2937 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2938 sky2_rx_hung(dev)) {
ada1db5c 2939 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2940 schedule_work(&hw->restart_work);
2941 return;
2942 }
2943 }
2944
2945 if (active == 0)
2946 return;
32c2c300 2947 }
01bd7564 2948
75e80683 2949 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2950}
2951
40b01727
SH		 2952/* Hardware/software error handling */
2953static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2954{
40b01727
SH		 2955 if (net_ratelimit())
2956 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2957
1e5f1283
SH		 2958 if (status & Y2_IS_HW_ERR)
2959 sky2_hw_intr(hw);
d257924e 2960
1e5f1283
SH		 2961 if (status & Y2_IS_IRQ_MAC1)
2962 sky2_mac_intr(hw, 0);
cd28ab6a 2963
1e5f1283
SH		 2964 if (status & Y2_IS_IRQ_MAC2)
2965 sky2_mac_intr(hw, 1);
cd28ab6a 2966
1e5f1283 2967 if (status & Y2_IS_CHK_RX1)
c119731d 2968 sky2_le_error(hw, 0, Q_R1);
d257924e 2969
1e5f1283 2970 if (status & Y2_IS_CHK_RX2)
c119731d 2971 sky2_le_error(hw, 1, Q_R2);
d257924e 2972
1e5f1283 2973 if (status & Y2_IS_CHK_TXA1)
c119731d 2974 sky2_le_error(hw, 0, Q_XA1);
d257924e 2975
1e5f1283 2976 if (status & Y2_IS_CHK_TXA2)
c119731d 2977 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2978}
2979
bea3348e 2980static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2981{
bea3348e 2982 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2983 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2984 int work_done = 0;
26691830 2985 u16 idx;
40b01727
SH		 2986
2987 if (unlikely(status & Y2_IS_ERROR))
2988 sky2_err_intr(hw, status);
2989
2990 if (status & Y2_IS_IRQ_PHY1)
2991 sky2_phy_intr(hw, 0);
2992
2993 if (status & Y2_IS_IRQ_PHY2)
2994 sky2_phy_intr(hw, 1);
cd28ab6a 2995
0f5aac70
SH		 2996 if (status & Y2_IS_PHY_QLNK)
2997 sky2_qlink_intr(hw);
2998
26691830
SH		 2999 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3000 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 3001
3002 if (work_done >= work_limit)
26691830
SH		 3003 goto done;
3004 }
6f535763 3005
26691830
SH		 3006 napi_complete(napi);
3007 sky2_read32(hw, B0_Y2_SP_LISR);
3008done:
6f535763 3009
bea3348e 3010 return work_done;
e07b1aa8
SH		 3011}
3012
7d12e780 3013static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 3014{
3015 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 3016 u32 status;
3017
3018 /* Reading this mask interrupts as side effect */
3019 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3020 if (status == 0 || status == ~0)
3021 return IRQ_NONE;
793b883e 3022
e07b1aa8 3023 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 3024
3025 napi_schedule(&hw->napi);
793b883e 3026
cd28ab6a
SH		 3027 return IRQ_HANDLED;
3028}
3029
3030#ifdef CONFIG_NET_POLL_CONTROLLER
3031static void sky2_netpoll(struct net_device *dev)
3032{
3033 struct sky2_port *sky2 = netdev_priv(dev);
3034
bea3348e 3035 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 3036}
3037#endif
3038
3039/* Chip internal frequency for clock calculations */
05745c4a 3040static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 3041{
793b883e 3042 switch (hw->chip_id) {
cd28ab6a 3043 case CHIP_ID_YUKON_EC:
5a5b1ea0 3044 case CHIP_ID_YUKON_EC_U:
93745494 3045 case CHIP_ID_YUKON_EX:
ed4d4161 3046 case CHIP_ID_YUKON_SUPR:
0ce8b98d 3047 case CHIP_ID_YUKON_UL_2:
0f5aac70 3048 case CHIP_ID_YUKON_OPT:
4fb99cd6 3049 case CHIP_ID_YUKON_PRM:
3050 case CHIP_ID_YUKON_OP_2:
05745c4a
SH		 3051 return 125;
3052
cd28ab6a 3053 case CHIP_ID_YUKON_FE:
05745c4a
SH		 3054 return 100;
3055
3056 case CHIP_ID_YUKON_FE_P:
3057 return 50;
3058
3059 case CHIP_ID_YUKON_XL:
3060 return 156;
3061
3062 default:
3063 BUG();
cd28ab6a
SH		 3064 }
3065}
3066
fb17358f 3067static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 3068{
fb17358f 3069 return sky2_mhz(hw) * us;
cd28ab6a
SH		 3070}
3071
fb17358f 3072static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 3073{
fb17358f 3074 return clk / sky2_mhz(hw);
cd28ab6a
SH		 3075}
3076
fb17358f 3077
e3173832 3078static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 3079{
b89165f2 3080 u8 t8;
cd28ab6a 3081
167f53d0 3082 /* Enable all clocks and check for bad PCI access */
b32f40c4 3083 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 3084
cd28ab6a 3085 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 3086
cd28ab6a 3087 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 3088 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3089
060b946c 3090 switch (hw->chip_id) {
ea76e635 3091 case CHIP_ID_YUKON_XL:
39dbd958 3092 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
bf73130d
SH		 3093 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3094 hw->flags |= SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3095 break;
3096
3097 case CHIP_ID_YUKON_EC_U:
3098 hw->flags = SKY2_HW_GIGABIT
3099 | SKY2_HW_NEWER_PHY
3100 | SKY2_HW_ADV_POWER_CTL;
3101 break;
3102
3103 case CHIP_ID_YUKON_EX:
3104 hw->flags = SKY2_HW_GIGABIT
3105 | SKY2_HW_NEWER_PHY
3106 | SKY2_HW_NEW_LE
aa5ca96c 3107 | SKY2_HW_ADV_POWER_CTL
3108 | SKY2_HW_RSS_CHKSUM;
ea76e635
SH		 3109
3110 /* New transmit checksum */
3111 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3112 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3113 break;
3114
3115 case CHIP_ID_YUKON_EC:
3116 /* This rev is really old, and requires untested workarounds */
3117 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3118 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3119 return -EOPNOTSUPP;
3120 }
bf73130d 3121 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3122 break;
3123
3124 case CHIP_ID_YUKON_FE:
bf73130d 3125 hw->flags = SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3126 break;
3127
05745c4a
SH		 3128 case CHIP_ID_YUKON_FE_P:
3129 hw->flags = SKY2_HW_NEWER_PHY
3130 | SKY2_HW_NEW_LE
3131 | SKY2_HW_AUTO_TX_SUM
3132 | SKY2_HW_ADV_POWER_CTL;
86aa7785
SH		 3133
3134 /* The workaround for status conflicts VLAN tag detection. */
3135 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
aa5ca96c 3136 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
05745c4a 3137 break;
ed4d4161
SH		 3138
3139 case CHIP_ID_YUKON_SUPR:
3140 hw->flags = SKY2_HW_GIGABIT
3141 | SKY2_HW_NEWER_PHY
3142 | SKY2_HW_NEW_LE
3143 | SKY2_HW_AUTO_TX_SUM
3144 | SKY2_HW_ADV_POWER_CTL;
aa5ca96c 3145
3146 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3147 hw->flags |= SKY2_HW_RSS_CHKSUM;
ed4d4161
SH		 3148 break;
3149
0ce8b98d 3150 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3151 hw->flags = SKY2_HW_GIGABIT
3152 | SKY2_HW_ADV_POWER_CTL;
3153 break;
3154
0f5aac70 3155 case CHIP_ID_YUKON_OPT:
4fb99cd6 3156 case CHIP_ID_YUKON_PRM:
3157 case CHIP_ID_YUKON_OP_2:
0ce8b98d 3158 hw->flags = SKY2_HW_GIGABIT
b338682d 3159 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3160 | SKY2_HW_ADV_POWER_CTL;
3161 break;
3162
ea76e635 3163 default:
b02a9258
SH		 3164 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3165 hw->chip_id);
cd28ab6a
SH		 3166 return -EOPNOTSUPP;
3167 }
3168
ea76e635
SH		 3169 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3170 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3171 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3172
e3173832
SH		 3173 hw->ports = 1;
3174 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3175 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3176 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3177 ++hw->ports;
3178 }
3179
74a61ebf
MM		 3180 if (sky2_read8(hw, B2_E_0))
3181 hw->flags |= SKY2_HW_RAM_BUFFER;
3182
e3173832
SH		 3183 return 0;
3184}
3185
3186static void sky2_reset(struct sky2_hw *hw)
3187{
555382cb 3188 struct pci_dev *pdev = hw->pdev;
e3173832 3189 u16 status;
1a10ccae 3190 int i;
555382cb 3191 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3192
cd28ab6a 3193 /* disable ASF */
acd12dde 3194 if (hw->chip_id == CHIP_ID_YUKON_EX
3195 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3196 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3197 status = sky2_read16(hw, HCU_CCSR);
3198 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3199 HCU_CCSR_UC_STATE_MSK);
acd12dde 3200 /*
3201 * CPU clock divider shouldn't be used because
3202 * - ASF firmware may malfunction
3203 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3204 */
3205 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3206 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3207 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3208 } else
3209 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3210 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3211
3212 /* do a SW reset */
3213 sky2_write8(hw, B0_CTST, CS_RST_SET);
3214 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3215
ac93a394
SH		 3216 /* allow writes to PCI config */
3217 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3218
cd28ab6a 3219 /* clear PCI errors, if any */
b32f40c4 3220 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3221 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3222 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3223
3224 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3225
1a10ccae 3226 if (pci_is_pcie(pdev)) {
7782c8c4
SH		 3227 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3228 0xfffffffful);
555382cb
SH		 3229
3230 /* If error bit is stuck on ignore it */
3231 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3232 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3233 else
555382cb
SH		 3234 hwe_mask |= Y2_IS_PCI_EXP;
3235 }
cd28ab6a 3236
ae306cca 3237 sky2_power_on(hw);
a40ccc68 3238 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3239
3240 for (i = 0; i < hw->ports; i++) {
3241 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3242 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3243
ed4d4161
SH		 3244 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3245 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3246 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3247 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3248 | GMC_BYP_RETR_ON);
877c8570
SH		 3249
3250 }
3251
3252 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3253 /* enable MACSec clock gating */
3254 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3255 }
3256
4fb99cd6 3257 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3258 hw->chip_id == CHIP_ID_YUKON_PRM ||
3259 hw->chip_id == CHIP_ID_YUKON_OP_2) {
0f5aac70
SH		 3260 u16 reg;
3261 u32 msk;
3262
4fb99cd6 3263 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
0f5aac70
SH		 3264 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3265 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3266
3267 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3268 reg = 10;
4fb99cd6 3269
3270 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3271 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
0f5aac70
SH		 3272 } else {
3273 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3274 reg = 3;
3275 }
3276
3277 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
4fb99cd6 3278 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
0f5aac70
SH		 3279
3280 /* reset PHY Link Detect */
a40ccc68 3281 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3282 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3283
0f5aac70
SH		 3284 /* enable PHY Quick Link */
3285 msk = sky2_read32(hw, B0_IMSK);
3286 msk |= Y2_IS_PHY_QLNK;
3287 sky2_write32(hw, B0_IMSK, msk);
3288
3289 /* check if PSMv2 was running before */
3290 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
1a10ccae 3291 if (reg & PCI_EXP_LNKCTL_ASPMC)
0f5aac70 3292 /* restore the PCIe Link Control register */
1a10ccae
JM		 3293 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3294 reg);
3295
a40ccc68 3296 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3297
3298 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3299 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3300 }
3301
793b883e
SH		 3302 /* Clear I2C IRQ noise */
3303 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3304
3305 /* turn off hardware timer (unused) */
3306 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3307 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3308
69634ee7
SH		 3309 /* Turn off descriptor polling */
3310 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3311
3312 /* Turn off receive timestamp */
3313 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3314 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3315
3316 /* enable the Tx Arbiters */
3317 for (i = 0; i < hw->ports; i++)
3318 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3319
3320 /* Initialize ram interface */
3321 for (i = 0; i < hw->ports; i++) {
793b883e 3322 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3323
3324 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3325 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3326 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3327 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3328 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3329 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3330 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3331 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3332 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3333 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3334 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3335 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3336 }
3337
555382cb 3338 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3339
cd28ab6a 3340 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3341 sky2_gmac_reset(hw, i);
cd28ab6a 3342
efe91932 3343 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
cd28ab6a
SH		 3344 hw->st_idx = 0;
3345
3346 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3347 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3348
3349 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3350 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3351
3352 /* Set the list last index */
efe91932 3353 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
cd28ab6a 3354
290d4de5
SH		 3355 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3356 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3357
290d4de5
SH		 3358 /* set Status-FIFO ISR watermark */
3359 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3360 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3361 else
3362 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3363
290d4de5 3364 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3365 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3366 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3367
793b883e 3368 /* enable status unit */
cd28ab6a
SH		 3369 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3370
3371 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3372 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3373 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3374}
3375
af18d8b8
SH		 3376/* Take device down (offline).
3377 * Equivalent to doing dev_stop() but this does not
25985edc 3378 * inform upper layers of the transition.
af18d8b8
SH		 3379 */
3380static void sky2_detach(struct net_device *dev)
3381{
3382 if (netif_running(dev)) {
c36531b9 3383 netif_tx_lock(dev);
af18d8b8 3384 netif_device_detach(dev); /* stop txq */
c36531b9 3385 netif_tx_unlock(dev);
af18d8b8
SH		 3386 sky2_down(dev);
3387 }
3388}
3389
3390/* Bring device back after doing sky2_detach */
3391static int sky2_reattach(struct net_device *dev)
3392{
3393 int err = 0;
3394
3395 if (netif_running(dev)) {
3396 err = sky2_up(dev);
3397 if (err) {
ada1db5c 3398 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3399 dev_close(dev);
3400 } else {
3401 netif_device_attach(dev);
3402 sky2_set_multicast(dev);
3403 }
3404 }
3405
3406 return err;
3407}
3408
d72ff8fa 3409static void sky2_all_down(struct sky2_hw *hw)
81906791 3410{
af18d8b8 3411 int i;
81906791 3412
d72ff8fa 3413 sky2_read32(hw, B0_IMSK);
8cfcbe99 3414 sky2_write32(hw, B0_IMSK, 0);
93135a3b
MM		 3415 synchronize_irq(hw->pdev->irq);
3416 napi_disable(&hw->napi);
8a0c9228
MM		 3417
3418 for (i = 0; i < hw->ports; i++) {
3419 struct net_device *dev = hw->dev[i];
3420 struct sky2_port *sky2 = netdev_priv(dev);
3421
3422 if (!netif_running(dev))
3423 continue;
3424
3425 netif_carrier_off(dev);
3426 netif_tx_disable(dev);
3427 sky2_hw_down(sky2);
3428 }
d72ff8fa 3429}
8a0c9228 3430
d72ff8fa
MM		 3431static void sky2_all_up(struct sky2_hw *hw)
3432{
3433 u32 imask = Y2_IS_BASE;
3434 int i;
81906791 3435
8a0c9228
MM		 3436 for (i = 0; i < hw->ports; i++) {
3437 struct net_device *dev = hw->dev[i];
3438 struct sky2_port *sky2 = netdev_priv(dev);
3439
3440 if (!netif_running(dev))
3441 continue;
3442
3443 sky2_hw_up(sky2);
37652522 3444 sky2_set_multicast(dev);
d72ff8fa 3445 imask |= portirq_msk[i];
8a0c9228
MM		 3446 netif_wake_queue(dev);
3447 }
3448
3449 sky2_write32(hw, B0_IMSK, imask);
3450 sky2_read32(hw, B0_IMSK);
3451
3452 sky2_read32(hw, B0_Y2_SP_LISR);
3453 napi_enable(&hw->napi);
d72ff8fa
MM		 3454}
3455
3456static void sky2_restart(struct work_struct *work)
3457{
3458 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3459
3460 rtnl_lock();
3461
3462 sky2_all_down(hw);
3463 sky2_reset(hw);
3464 sky2_all_up(hw);
81906791 3465
81906791
SH		 3466 rtnl_unlock();
3467}
3468
e3173832
SH		 3469static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3470{
3471 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3472}
3473
3474static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3475{
3476 const struct sky2_port *sky2 = netdev_priv(dev);
3477
3478 wol->supported = sky2_wol_supported(sky2->hw);
3479 wol->wolopts = sky2->wol;
3480}
3481
3482static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3483{
3484 struct sky2_port *sky2 = netdev_priv(dev);
3485 struct sky2_hw *hw = sky2->hw;
0f333d10
RW		 3486 bool enable_wakeup = false;
3487 int i;
cd28ab6a 3488
8e95a202
JP		 3489 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3490 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3491 return -EOPNOTSUPP;
3492
3493 sky2->wol = wol->wolopts;
0f333d10
RW		 3494
3495 for (i = 0; i < hw->ports; i++) {
3496 struct net_device *dev = hw->dev[i];
3497 struct sky2_port *sky2 = netdev_priv(dev);
3498
3499 if (sky2->wol)
3500 enable_wakeup = true;
3501 }
3502 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3503
cd28ab6a
SH		 3504 return 0;
3505}
3506
28bd181a 3507static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3508{
b89165f2
SH		 3509 if (sky2_is_copper(hw)) {
3510 u32 modes = SUPPORTED_10baseT_Half
3511 | SUPPORTED_10baseT_Full
3512 | SUPPORTED_100baseT_Half
2aca31e7 3513 | SUPPORTED_100baseT_Full;
cd28ab6a 3514
ea76e635 3515 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3516 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3517 | SUPPORTED_1000baseT_Full;
3518 return modes;
cd28ab6a 3519 } else
2aca31e7
SH		 3520 return SUPPORTED_1000baseT_Half
3521 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 3522}
3523
793b883e 3524static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3525{
3526 struct sky2_port *sky2 = netdev_priv(dev);
3527 struct sky2_hw *hw = sky2->hw;
3528
3529 ecmd->transceiver = XCVR_INTERNAL;
3530 ecmd->supported = sky2_supported_modes(hw);
3531 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3532 if (sky2_is_copper(hw)) {
cd28ab6a 3533 ecmd->port = PORT_TP;
70739497 3534 ethtool_cmd_speed_set(ecmd, sky2->speed);
2aca31e7 3535 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
b89165f2 3536 } else {
70739497 3537 ethtool_cmd_speed_set(ecmd, SPEED_1000);
cd28ab6a 3538 ecmd->port = PORT_FIBRE;
2aca31e7 3539 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
b89165f2 3540 }
cd28ab6a
SH		 3541
3542 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3543 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3544 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3545 ecmd->duplex = sky2->duplex;
3546 return 0;
3547}
3548
3549static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3550{
3551 struct sky2_port *sky2 = netdev_priv(dev);
3552 const struct sky2_hw *hw = sky2->hw;
3553 u32 supported = sky2_supported_modes(hw);
3554
3555 if (ecmd->autoneg == AUTONEG_ENABLE) {
2aca31e7
SH		 3556 if (ecmd->advertising & ~supported)
3557 return -EINVAL;
3558
3559 if (sky2_is_copper(hw))
3560 sky2->advertising = ecmd->advertising |
3561 ADVERTISED_TP |
3562 ADVERTISED_Autoneg;
3563 else
3564 sky2->advertising = ecmd->advertising |
3565 ADVERTISED_FIBRE |
3566 ADVERTISED_Autoneg;
3567
0ea065e5 3568 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3569 sky2->duplex = -1;
3570 sky2->speed = -1;
3571 } else {
3572 u32 setting;
25db0338 3573 u32 speed = ethtool_cmd_speed(ecmd);
cd28ab6a 3574
25db0338 3575 switch (speed) {
cd28ab6a
SH		 3576 case SPEED_1000:
3577 if (ecmd->duplex == DUPLEX_FULL)
3578 setting = SUPPORTED_1000baseT_Full;
3579 else if (ecmd->duplex == DUPLEX_HALF)
3580 setting = SUPPORTED_1000baseT_Half;
3581 else
3582 return -EINVAL;
3583 break;
3584 case SPEED_100:
3585 if (ecmd->duplex == DUPLEX_FULL)
3586 setting = SUPPORTED_100baseT_Full;
3587 else if (ecmd->duplex == DUPLEX_HALF)
3588 setting = SUPPORTED_100baseT_Half;
3589 else
3590 return -EINVAL;
3591 break;
3592
3593 case SPEED_10:
3594 if (ecmd->duplex == DUPLEX_FULL)
3595 setting = SUPPORTED_10baseT_Full;
3596 else if (ecmd->duplex == DUPLEX_HALF)
3597 setting = SUPPORTED_10baseT_Half;
3598 else
3599 return -EINVAL;
3600 break;
3601 default:
3602 return -EINVAL;
3603 }
3604
3605 if ((setting & supported) == 0)
3606 return -EINVAL;
3607
25db0338 3608 sky2->speed = speed;
cd28ab6a 3609 sky2->duplex = ecmd->duplex;
0ea065e5 3610 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3611 }
3612
d1b139c0 3613 if (netif_running(dev)) {
1b537565 3614 sky2_phy_reinit(sky2);
d1b139c0
SH		 3615 sky2_set_multicast(dev);
3616 }
cd28ab6a
SH		 3617
3618 return 0;
3619}
3620
3621static void sky2_get_drvinfo(struct net_device *dev,
3622 struct ethtool_drvinfo *info)
3623{
3624 struct sky2_port *sky2 = netdev_priv(dev);
3625
68aad78c
RJ		 3626 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
3627 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3628 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
3629 strlcpy(info->bus_info, pci_name(sky2->hw->pdev),
3630 sizeof(info->bus_info));
cd28ab6a
SH		 3631}
3632
3633static const struct sky2_stat {
793b883e
SH		 3634 char name[ETH_GSTRING_LEN];
3635 u16 offset;
cd28ab6a
SH		 3636} sky2_stats[] = {
3637 { "tx_bytes", GM_TXO_OK_HI },
3638 { "rx_bytes", GM_RXO_OK_HI },
3639 { "tx_broadcast", GM_TXF_BC_OK },
3640 { "rx_broadcast", GM_RXF_BC_OK },
3641 { "tx_multicast", GM_TXF_MC_OK },
3642 { "rx_multicast", GM_RXF_MC_OK },
3643 { "tx_unicast", GM_TXF_UC_OK },
3644 { "rx_unicast", GM_RXF_UC_OK },
3645 { "tx_mac_pause", GM_TXF_MPAUSE },
3646 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3647 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3648 { "late_collision",GM_TXF_LAT_COL },
3649 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3650 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3651 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3652
d2604540 3653 { "rx_short", GM_RXF_SHT },
cd28ab6a 3654 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3655 { "rx_64_byte_packets", GM_RXF_64B },
3656 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3657 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3658 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3659 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3660 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3661 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3662 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3663 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3664 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3665 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3666
3667 { "tx_64_byte_packets", GM_TXF_64B },
3668 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3669 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3670 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3671 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3672 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3673 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3674 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3675};
3676
cd28ab6a
SH		 3677static u32 sky2_get_msglevel(struct net_device *netdev)
3678{
3679 struct sky2_port *sky2 = netdev_priv(netdev);
3680 return sky2->msg_enable;
3681}
3682
9a7ae0a9
SH		 3683static int sky2_nway_reset(struct net_device *dev)
3684{
3685 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3686
0ea065e5 3687 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3688 return -EINVAL;
3689
1b537565 3690 sky2_phy_reinit(sky2);
d1b139c0 3691 sky2_set_multicast(dev);
9a7ae0a9
SH		 3692
3693 return 0;
3694}
3695
793b883e 3696static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3697{
3698 struct sky2_hw *hw = sky2->hw;
3699 unsigned port = sky2->port;
3700 int i;
3701
0885a30b 3702 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3703 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
cd28ab6a 3704
793b883e 3705 for (i = 2; i < count; i++)
0885a30b 3706 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
cd28ab6a
SH		 3707}
3708
cd28ab6a
SH		 3709static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3710{
3711 struct sky2_port *sky2 = netdev_priv(netdev);
3712 sky2->msg_enable = value;
3713}
3714
b9f2c044 3715static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3716{
b9f2c044
JG		 3717 switch (sset) {
3718 case ETH_SS_STATS:
3719 return ARRAY_SIZE(sky2_stats);
3720 default:
3721 return -EOPNOTSUPP;
3722 }
cd28ab6a
SH		 3723}
3724
3725static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3726 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3727{
3728 struct sky2_port *sky2 = netdev_priv(dev);
3729
793b883e 3730 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3731}
3732
793b883e 3733static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3734{
3735 int i;
3736
3737 switch (stringset) {
3738 case ETH_SS_STATS:
3739 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3740 memcpy(data + i * ETH_GSTRING_LEN,
3741 sky2_stats[i].name, ETH_GSTRING_LEN);
3742 break;
3743 }
3744}
3745
cd28ab6a
SH		 3746static int sky2_set_mac_address(struct net_device *dev, void *p)
3747{
3748 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3749 struct sky2_hw *hw = sky2->hw;
3750 unsigned port = sky2->port;
3751 const struct sockaddr *addr = p;
cd28ab6a
SH		 3752
3753 if (!is_valid_ether_addr(addr->sa_data))
3754 return -EADDRNOTAVAIL;
3755
cd28ab6a 3756 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3757 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3758 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3759 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3760 dev->dev_addr, ETH_ALEN);
1b537565 3761
a8ab1ec0
SH		 3762 /* virtual address for data */
3763 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3764
3765 /* physical address: used for pause frames */
3766 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3767
3768 return 0;
cd28ab6a
SH		 3769}
3770
060b946c 3771static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
a052b52f
SH		 3772{
3773 u32 bit;
3774
3775 bit = ether_crc(ETH_ALEN, addr) & 63;
3776 filter[bit >> 3] |= 1 << (bit & 7);
3777}
3778
cd28ab6a
SH		 3779static void sky2_set_multicast(struct net_device *dev)
3780{
3781 struct sky2_port *sky2 = netdev_priv(dev);
3782 struct sky2_hw *hw = sky2->hw;
3783 unsigned port = sky2->port;
22bedad3 3784 struct netdev_hw_addr *ha;
cd28ab6a
SH		 3785 u16 reg;
3786 u8 filter[8];
a052b52f
SH		 3787 int rx_pause;
3788 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3789
a052b52f 3790 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3791 memset(filter, 0, sizeof(filter));
3792
3793 reg = gma_read16(hw, port, GM_RX_CTRL);
3794 reg |= GM_RXCR_UCF_ENA;
3795
d571b694 3796 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3797 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3798 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3799 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3800 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3801 reg &= ~GM_RXCR_MCF_ENA;
3802 else {
cd28ab6a
SH		 3803 reg |= GM_RXCR_MCF_ENA;
3804
a052b52f
SH		 3805 if (rx_pause)
3806 sky2_add_filter(filter, pause_mc_addr);
3807
22bedad3
JP		 3808 netdev_for_each_mc_addr(ha, dev)
3809 sky2_add_filter(filter, ha->addr);
cd28ab6a
SH		 3810 }
3811
cd28ab6a 3812 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3813 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3814 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3815 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3816 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3817 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3818 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3819 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3820
3821 gma_write16(hw, port, GM_RX_CTRL, reg);
3822}
3823
0885a30b 3824static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3825 struct rtnl_link_stats64 *stats)
3826{
3827 struct sky2_port *sky2 = netdev_priv(dev);
3828 struct sky2_hw *hw = sky2->hw;
3829 unsigned port = sky2->port;
3830 unsigned int start;
3831 u64 _bytes, _packets;
3832
3833 do {
3834 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3835 _bytes = sky2->rx_stats.bytes;
3836 _packets = sky2->rx_stats.packets;
3837 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3838
3839 stats->rx_packets = _packets;
3840 stats->rx_bytes = _bytes;
3841
3842 do {
3843 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3844 _bytes = sky2->tx_stats.bytes;
3845 _packets = sky2->tx_stats.packets;
3846 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3847
3848 stats->tx_packets = _packets;
3849 stats->tx_bytes = _bytes;
3850
3851 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3852 + get_stats32(hw, port, GM_RXF_BC_OK);
3853
3854 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3855
3856 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3857 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3858 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3859 + get_stats32(hw, port, GM_RXE_FRAG);
3860 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3861
3862 stats->rx_dropped = dev->stats.rx_dropped;
3863 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3864 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3865
3866 return stats;
3867}
3868
cd28ab6a
SH		 3869/* Can have one global because blinking is controlled by
3870 * ethtool and that is always under RTNL mutex
3871 */
a84d0a3d 3872static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3873{
a84d0a3d
SH		 3874 struct sky2_hw *hw = sky2->hw;
3875 unsigned port = sky2->port;
793b883e 3876
a84d0a3d
SH		 3877 spin_lock_bh(&sky2->phy_lock);
3878 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3879 hw->chip_id == CHIP_ID_YUKON_EX ||
3880 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3881 u16 pg;
793b883e
SH		 3882 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3883 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3884
a84d0a3d
SH		 3885 switch (mode) {
3886 case MO_LED_OFF:
3887 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3888 PHY_M_LEDC_LOS_CTRL(8) |
3889 PHY_M_LEDC_INIT_CTRL(8) |
3890 PHY_M_LEDC_STA1_CTRL(8) |
3891 PHY_M_LEDC_STA0_CTRL(8));
3892 break;
3893 case MO_LED_ON:
3894 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3895 PHY_M_LEDC_LOS_CTRL(9) |
3896 PHY_M_LEDC_INIT_CTRL(9) |
3897 PHY_M_LEDC_STA1_CTRL(9) |
3898 PHY_M_LEDC_STA0_CTRL(9));
3899 break;
3900 case MO_LED_BLINK:
3901 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3902 PHY_M_LEDC_LOS_CTRL(0xa) |
3903 PHY_M_LEDC_INIT_CTRL(0xa) |
3904 PHY_M_LEDC_STA1_CTRL(0xa) |
3905 PHY_M_LEDC_STA0_CTRL(0xa));
3906 break;
3907 case MO_LED_NORM:
3908 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3909 PHY_M_LEDC_LOS_CTRL(1) |
3910 PHY_M_LEDC_INIT_CTRL(8) |
3911 PHY_M_LEDC_STA1_CTRL(7) |
3912 PHY_M_LEDC_STA0_CTRL(7));
3913 }
793b883e 3914
a84d0a3d
SH		 3915 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3916 } else
7d2e3cb7 3917 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3918 PHY_M_LED_MO_DUP(mode) |
3919 PHY_M_LED_MO_10(mode) |
3920 PHY_M_LED_MO_100(mode) |
3921 PHY_M_LED_MO_1000(mode) |
3922 PHY_M_LED_MO_RX(mode) |
3923 PHY_M_LED_MO_TX(mode));
3924
3925 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3926}
3927
3928/* blink LED's for finding board */
74e532ff 3929static int sky2_set_phys_id(struct net_device *dev,
3930 enum ethtool_phys_id_state state)
cd28ab6a
SH		 3931{
3932 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3933
74e532ff 3934 switch (state) {
3935 case ETHTOOL_ID_ACTIVE:
fce55922 3936 return 1; /* cycle on/off once per second */
74e532ff 3937 case ETHTOOL_ID_INACTIVE:
3938 sky2_led(sky2, MO_LED_NORM);
3939 break;
3940 case ETHTOOL_ID_ON:
a84d0a3d 3941 sky2_led(sky2, MO_LED_ON);
74e532ff 3942 break;
3943 case ETHTOOL_ID_OFF:
a84d0a3d 3944 sky2_led(sky2, MO_LED_OFF);
74e532ff 3945 break;
793b883e 3946 }
cd28ab6a
SH		 3947
3948 return 0;
3949}
3950
3951static void sky2_get_pauseparam(struct net_device *dev,
3952 struct ethtool_pauseparam *ecmd)
3953{
3954 struct sky2_port *sky2 = netdev_priv(dev);
3955
16ad91e1
SH		 3956 switch (sky2->flow_mode) {
3957 case FC_NONE:
3958 ecmd->tx_pause = ecmd->rx_pause = 0;
3959 break;
3960 case FC_TX:
3961 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3962 break;
3963 case FC_RX:
3964 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3965 break;
3966 case FC_BOTH:
3967 ecmd->tx_pause = ecmd->rx_pause = 1;
3968 }
3969
0ea065e5
SH		 3970 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3971 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3972}
3973
3974static int sky2_set_pauseparam(struct net_device *dev,
3975 struct ethtool_pauseparam *ecmd)
3976{
3977 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3978
0ea065e5
SH		 3979 if (ecmd->autoneg == AUTONEG_ENABLE)
3980 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3981 else
3982 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3983
16ad91e1 3984 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3985
16ad91e1
SH		 3986 if (netif_running(dev))
3987 sky2_phy_reinit(sky2);
cd28ab6a 3988
2eaba1a2 3989 return 0;
cd28ab6a
SH		 3990}
3991
fb17358f
SH		 3992static int sky2_get_coalesce(struct net_device *dev,
3993 struct ethtool_coalesce *ecmd)
3994{
3995 struct sky2_port *sky2 = netdev_priv(dev);
3996 struct sky2_hw *hw = sky2->hw;
3997
3998 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3999 ecmd->tx_coalesce_usecs = 0;
4000 else {
4001 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4002 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4003 }
4004 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4005
4006 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4007 ecmd->rx_coalesce_usecs = 0;
4008 else {
4009 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4010 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4011 }
4012 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4013
4014 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4015 ecmd->rx_coalesce_usecs_irq = 0;
4016 else {
4017 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4018 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4019 }
4020
4021 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4022
4023 return 0;
4024}
4025
4026/* Note: this affect both ports */
4027static int sky2_set_coalesce(struct net_device *dev,
4028 struct ethtool_coalesce *ecmd)
4029{
4030 struct sky2_port *sky2 = netdev_priv(dev);
4031 struct sky2_hw *hw = sky2->hw;
77b3d6a2 4032 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 4033
77b3d6a2
SH		 4034 if (ecmd->tx_coalesce_usecs > tmax ||
4035 ecmd->rx_coalesce_usecs > tmax ||
4036 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 4037 return -EINVAL;
4038
ee5f68fe 4039 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 4040 return -EINVAL;
ff81fbbe 4041 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 4042 return -EINVAL;
060b946c 4043 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
fb17358f
SH		 4044 return -EINVAL;
4045
4046 if (ecmd->tx_coalesce_usecs == 0)
4047 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4048 else {
4049 sky2_write32(hw, STAT_TX_TIMER_INI,
4050 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4051 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4052 }
4053 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4054
4055 if (ecmd->rx_coalesce_usecs == 0)
4056 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4057 else {
4058 sky2_write32(hw, STAT_LEV_TIMER_INI,
4059 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4060 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4061 }
4062 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4063
4064 if (ecmd->rx_coalesce_usecs_irq == 0)
4065 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4066 else {
d28d4870 4067 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 4068 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4069 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4070 }
4071 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4072 return 0;
4073}
4074
793b883e
SH		 4075static void sky2_get_ringparam(struct net_device *dev,
4076 struct ethtool_ringparam *ering)
4077{
4078 struct sky2_port *sky2 = netdev_priv(dev);
4079
4080 ering->rx_max_pending = RX_MAX_PENDING;
ee5f68fe 4081 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 4082
4083 ering->rx_pending = sky2->rx_pending;
793b883e
SH		 4084 ering->tx_pending = sky2->tx_pending;
4085}
4086
4087static int sky2_set_ringparam(struct net_device *dev,
4088 struct ethtool_ringparam *ering)
4089{
4090 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 4091
4092 if (ering->rx_pending > RX_MAX_PENDING ||
4093 ering->rx_pending < 8 ||
ee5f68fe
SH		 4094 ering->tx_pending < TX_MIN_PENDING ||
4095 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 4096 return -EINVAL;
4097
af18d8b8 4098 sky2_detach(dev);
793b883e
SH		 4099
4100 sky2->rx_pending = ering->rx_pending;
4101 sky2->tx_pending = ering->tx_pending;
ee5f68fe 4102 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 4103
af18d8b8 4104 return sky2_reattach(dev);
793b883e
SH		 4105}
4106
793b883e
SH		 4107static int sky2_get_regs_len(struct net_device *dev)
4108{
6e4cbb34 4109 return 0x4000;
793b883e
SH		 4110}
4111
c32bbff8
MM		 4112static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4113{
4114 /* This complicated switch statement is to make sure and
4115 * only access regions that are unreserved.
4116 * Some blocks are only valid on dual port cards.
4117 */
4118 switch (b) {
4119 /* second port */
4120 case 5: /* Tx Arbiter 2 */
4121 case 9: /* RX2 */
4122 case 14 ... 15: /* TX2 */
4123 case 17: case 19: /* Ram Buffer 2 */
4124 case 22 ... 23: /* Tx Ram Buffer 2 */
4125 case 25: /* Rx MAC Fifo 1 */
4126 case 27: /* Tx MAC Fifo 2 */
4127 case 31: /* GPHY 2 */
4128 case 40 ... 47: /* Pattern Ram 2 */
4129 case 52: case 54: /* TCP Segmentation 2 */
4130 case 112 ... 116: /* GMAC 2 */
4131 return hw->ports > 1;
4132
4133 case 0: /* Control */
4134 case 2: /* Mac address */
4135 case 4: /* Tx Arbiter 1 */
4136 case 7: /* PCI express reg */
4137 case 8: /* RX1 */
4138 case 12 ... 13: /* TX1 */
4139 case 16: case 18:/* Rx Ram Buffer 1 */
4140 case 20 ... 21: /* Tx Ram Buffer 1 */
4141 case 24: /* Rx MAC Fifo 1 */
4142 case 26: /* Tx MAC Fifo 1 */
4143 case 28 ... 29: /* Descriptor and status unit */
4144 case 30: /* GPHY 1*/
4145 case 32 ... 39: /* Pattern Ram 1 */
4146 case 48: case 50: /* TCP Segmentation 1 */
4147 case 56 ... 60: /* PCI space */
4148 case 80 ... 84: /* GMAC 1 */
4149 return 1;
4150
4151 default:
4152 return 0;
4153 }
4154}
4155
793b883e
SH		 4156/*
4157 * Returns copy of control register region
3ead5db7 4158 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 4159 */
4160static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4161 void *p)
4162{
4163 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 4164 const void __iomem *io = sky2->hw->regs;
295b54c4 4165 unsigned int b;
793b883e
SH		 4166
4167 regs->version = 1;
793b883e 4168
295b54c4 4169 for (b = 0; b < 128; b++) {
c32bbff8
MM		 4170 /* skip poisonous diagnostic ram region in block 3 */
4171 if (b == 3)
295b54c4 4172 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 4173 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 4174 memcpy_fromio(p, io, 128);
c32bbff8 4175 else
295b54c4 4176 memset(p, 0, 128);
3ead5db7 4177
295b54c4
SH		 4178 p += 128;
4179 io += 128;
4180 }
793b883e 4181}
cd28ab6a 4182
f4331a6d
SH		 4183static int sky2_get_eeprom_len(struct net_device *dev)
4184{
4185 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4186 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4187 u16 reg2;
4188
b32f40c4 4189 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4190 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4191}
4192
1413235c 4193static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4194{
1413235c 4195 unsigned long start = jiffies;
f4331a6d 4196
1413235c
SH		 4197 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4198 /* Can take up to 10.6 ms for write */
4199 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4200 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4201 return -ETIMEDOUT;
4202 }
4203 mdelay(1);
4204 }
167f53d0 4205
1413235c
SH		 4206 return 0;
4207}
167f53d0 4208
1413235c
SH		 4209static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4210 u16 offset, size_t length)
4211{
4212 int rc = 0;
4213
4214 while (length > 0) {
4215 u32 val;
4216
4217 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4218 rc = sky2_vpd_wait(hw, cap, 0);
4219 if (rc)
4220 break;
4221
4222 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4223
4224 memcpy(data, &val, min(sizeof(val), length));
4225 offset += sizeof(u32);
4226 data += sizeof(u32);
4227 length -= sizeof(u32);
4228 }
4229
4230 return rc;
f4331a6d
SH		 4231}
4232
1413235c
SH		 4233static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4234 u16 offset, unsigned int length)
f4331a6d 4235{
1413235c
SH		 4236 unsigned int i;
4237 int rc = 0;
4238
4239 for (i = 0; i < length; i += sizeof(u32)) {
4240 u32 val = *(u32 *)(data + i);
4241
4242 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4243 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4244
4245 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4246 if (rc)
4247 break;
4248 }
4249 return rc;
f4331a6d
SH		 4250}
4251
4252static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4253 u8 *data)
4254{
4255 struct sky2_port *sky2 = netdev_priv(dev);
4256 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4257
4258 if (!cap)
4259 return -EINVAL;
4260
4261 eeprom->magic = SKY2_EEPROM_MAGIC;
4262
1413235c 4263 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4264}
4265
4266static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4267 u8 *data)
4268{
4269 struct sky2_port *sky2 = netdev_priv(dev);
4270 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4271
4272 if (!cap)
4273 return -EINVAL;
4274
4275 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4276 return -EINVAL;
4277
1413235c
SH		 4278 /* Partial writes not supported */
4279 if ((eeprom->offset & 3) || (eeprom->len & 3))
4280 return -EINVAL;
f4331a6d 4281
1413235c 4282 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4283}
4284
c8f44aff
MM		 4285static netdev_features_t sky2_fix_features(struct net_device *dev,
4286 netdev_features_t features)
bf73130d 4287{
f5d64037
MM		 4288 const struct sky2_port *sky2 = netdev_priv(dev);
4289 const struct sky2_hw *hw = sky2->hw;
bf73130d 4290
f5d64037
MM		 4291 /* In order to do Jumbo packets on these chips, need to turn off the
4292 * transmit store/forward. Therefore checksum offload won't work.
4293 */
aa5ca96c 4294 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4295 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
f5d64037 4296 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
aa5ca96c 4297 }
4298
4299 /* Some hardware requires receive checksum for RSS to work. */
4300 if ( (features & NETIF_F_RXHASH) &&
4301 !(features & NETIF_F_RXCSUM) &&
4302 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4303 netdev_info(dev, "receive hashing forces receive checksum\n");
4304 features |= NETIF_F_RXCSUM;
4305 }
86aa7785 4306
f5d64037
MM		 4307 return features;
4308}
86aa7785 4309
c8f44aff 4310static int sky2_set_features(struct net_device *dev, netdev_features_t features)
f5d64037
MM		 4311{
4312 struct sky2_port *sky2 = netdev_priv(dev);
c8f44aff 4313 netdev_features_t changed = dev->features ^ features;
86aa7785 4314
f5d64037 4315 if (changed & NETIF_F_RXCSUM) {
c8f44aff 4316 int on = !!(features & NETIF_F_RXCSUM);
f5d64037
MM		 4317 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4318 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4319 }
bf73130d 4320
f5d64037
MM		 4321 if (changed & NETIF_F_RXHASH)
4322 rx_set_rss(dev, features);
86aa7785 4323
f5d64037
MM		 4324 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4325 sky2_vlan_mode(dev, features);
bf73130d
SH		 4326
4327 return 0;
4328}
f4331a6d 4329
7282d491 4330static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4331 .get_settings = sky2_get_settings,
4332 .set_settings = sky2_set_settings,
4333 .get_drvinfo = sky2_get_drvinfo,
4334 .get_wol = sky2_get_wol,
4335 .set_wol = sky2_set_wol,
4336 .get_msglevel = sky2_get_msglevel,
4337 .set_msglevel = sky2_set_msglevel,
4338 .nway_reset = sky2_nway_reset,
4339 .get_regs_len = sky2_get_regs_len,
4340 .get_regs = sky2_get_regs,
4341 .get_link = ethtool_op_get_link,
4342 .get_eeprom_len = sky2_get_eeprom_len,
4343 .get_eeprom = sky2_get_eeprom,
4344 .set_eeprom = sky2_set_eeprom,
f4331a6d
SH		 4345 .get_strings = sky2_get_strings,
4346 .get_coalesce = sky2_get_coalesce,
4347 .set_coalesce = sky2_set_coalesce,
4348 .get_ringparam = sky2_get_ringparam,
4349 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4350 .get_pauseparam = sky2_get_pauseparam,
4351 .set_pauseparam = sky2_set_pauseparam,
74e532ff 4352 .set_phys_id = sky2_set_phys_id,
b9f2c044 4353 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4354 .get_ethtool_stats = sky2_get_ethtool_stats,
4355};
4356
3cf26753
SH		 4357#ifdef CONFIG_SKY2_DEBUG
4358
4359static struct dentry *sky2_debug;
4360
e4c2abe2
SH		 4361
4362/*
4363 * Read and parse the first part of Vital Product Data
4364 */
4365#define VPD_SIZE 128
4366#define VPD_MAGIC 0x82
4367
4368static const struct vpd_tag {
4369 char tag[2];
4370 char *label;
4371} vpd_tags[] = {
4372 { "PN", "Part Number" },
4373 { "EC", "Engineering Level" },
4374 { "MN", "Manufacturer" },
4375 { "SN", "Serial Number" },
4376 { "YA", "Asset Tag" },
4377 { "VL", "First Error Log Message" },
4378 { "VF", "Second Error Log Message" },
4379 { "VB", "Boot Agent ROM Configuration" },
4380 { "VE", "EFI UNDI Configuration" },
4381};
4382
4383static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4384{
4385 size_t vpd_size;
4386 loff_t offs;
4387 u8 len;
4388 unsigned char *buf;
4389 u16 reg2;
4390
4391 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4392 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4393
4394 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4395 buf = kmalloc(vpd_size, GFP_KERNEL);
4396 if (!buf) {
4397 seq_puts(seq, "no memory!\n");
4398 return;
4399 }
4400
4401 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4402 seq_puts(seq, "VPD read failed\n");
4403 goto out;
4404 }
4405
4406 if (buf[0] != VPD_MAGIC) {
4407 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4408 goto out;
4409 }
4410 len = buf[1];
4411 if (len == 0 || len > vpd_size - 4) {
4412 seq_printf(seq, "Invalid id length: %d\n", len);
4413 goto out;
4414 }
4415
4416 seq_printf(seq, "%.*s\n", len, buf + 3);
4417 offs = len + 3;
4418
4419 while (offs < vpd_size - 4) {
4420 int i;
4421
4422 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4423 break;
4424 len = buf[offs + 2];
4425 if (offs + len + 3 >= vpd_size)
4426 break;
4427
4428 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4429 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4430 seq_printf(seq, " %s: %.*s\n",
4431 vpd_tags[i].label, len, buf + offs + 3);
4432 break;
4433 }
4434 }
4435 offs += len + 3;
4436 }
4437out:
4438 kfree(buf);
4439}
4440
3cf26753
SH		 4441static int sky2_debug_show(struct seq_file *seq, void *v)
4442{
4443 struct net_device *dev = seq->private;
4444 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4445 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4446 unsigned port = sky2->port;
4447 unsigned idx, last;
4448 int sop;
4449
e4c2abe2 4450 sky2_show_vpd(seq, hw);
3cf26753 4451
e4c2abe2 4452 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4453 sky2_read32(hw, B0_ISRC),
4454 sky2_read32(hw, B0_IMSK),
4455 sky2_read32(hw, B0_Y2_SP_ICR));
4456
e4c2abe2
SH		 4457 if (!netif_running(dev)) {
4458 seq_printf(seq, "network not running\n");
4459 return 0;
4460 }
4461
bea3348e 4462 napi_disable(&hw->napi);
3cf26753
SH		 4463 last = sky2_read16(hw, STAT_PUT_IDX);
4464
efe91932 4465 seq_printf(seq, "Status ring %u\n", hw->st_size);
3cf26753
SH		 4466 if (hw->st_idx == last)
4467 seq_puts(seq, "Status ring (empty)\n");
4468 else {
4469 seq_puts(seq, "Status ring\n");
efe91932 4470 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4471 idx = RING_NEXT(idx, hw->st_size)) {
3cf26753
SH		 4472 const struct sky2_status_le *le = hw->st_le + idx;
4473 seq_printf(seq, "[%d] %#x %d %#x\n",
4474 idx, le->opcode, le->length, le->status);
4475 }
4476 seq_puts(seq, "\n");
4477 }
4478
4479 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4480 sky2->tx_cons, sky2->tx_prod,
4481 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4482 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4483
4484 /* Dump contents of tx ring */
4485 sop = 1;
ee5f68fe
SH		 4486 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4487 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4488 const struct sky2_tx_le *le = sky2->tx_le + idx;
4489 u32 a = le32_to_cpu(le->addr);
4490
4491 if (sop)
4492 seq_printf(seq, "%u:", idx);
4493 sop = 0;
4494
060b946c 4495 switch (le->opcode & ~HW_OWNER) {
3cf26753
SH		 4496 case OP_ADDR64:
4497 seq_printf(seq, " %#x:", a);
4498 break;
4499 case OP_LRGLEN:
4500 seq_printf(seq, " mtu=%d", a);
4501 break;
4502 case OP_VLAN:
4503 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4504 break;
4505 case OP_TCPLISW:
4506 seq_printf(seq, " csum=%#x", a);
4507 break;
4508 case OP_LARGESEND:
4509 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4510 break;
4511 case OP_PACKET:
4512 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4513 break;
4514 case OP_BUFFER:
4515 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4516 break;
4517 default:
4518 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4519 a, le16_to_cpu(le->length));
4520 }
4521
4522 if (le->ctrl & EOP) {
4523 seq_putc(seq, '\n');
4524 sop = 1;
4525 }
4526 }
4527
4528 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4529 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4530 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4531 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4532
d1d08d12 4533 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4534 napi_enable(&hw->napi);
3cf26753
SH		 4535 return 0;
4536}
4537
4538static int sky2_debug_open(struct inode *inode, struct file *file)
4539{
4540 return single_open(file, sky2_debug_show, inode->i_private);
4541}
4542
4543static const struct file_operations sky2_debug_fops = {
4544 .owner = THIS_MODULE,
4545 .open = sky2_debug_open,
4546 .read = seq_read,
4547 .llseek = seq_lseek,
4548 .release = single_release,
4549};
4550
4551/*
4552 * Use network device events to create/remove/rename
4553 * debugfs file entries
4554 */
4555static int sky2_device_event(struct notifier_block *unused,
4556 unsigned long event, void *ptr)
4557{
4558 struct net_device *dev = ptr;
5b296bc9 4559 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4560
1436b301 4561 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4562 return NOTIFY_DONE;
3cf26753 4563
060b946c 4564 switch (event) {
5b296bc9
SH		 4565 case NETDEV_CHANGENAME:
4566 if (sky2->debugfs) {
4567 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4568 sky2_debug, dev->name);
4569 }
4570 break;
3cf26753 4571
5b296bc9
SH		 4572 case NETDEV_GOING_DOWN:
4573 if (sky2->debugfs) {
ada1db5c 4574 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4575 debugfs_remove(sky2->debugfs);
4576 sky2->debugfs = NULL;
3cf26753 4577 }
5b296bc9
SH		 4578 break;
4579
4580 case NETDEV_UP:
4581 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4582 sky2_debug, dev,
4583 &sky2_debug_fops);
4584 if (IS_ERR(sky2->debugfs))
4585 sky2->debugfs = NULL;
3cf26753
SH		 4586 }
4587
4588 return NOTIFY_DONE;
4589}
4590
4591static struct notifier_block sky2_notifier = {
4592 .notifier_call = sky2_device_event,
4593};
4594
4595
4596static __init void sky2_debug_init(void)
4597{
4598 struct dentry *ent;
4599
4600 ent = debugfs_create_dir("sky2", NULL);
4601 if (!ent || IS_ERR(ent))
4602 return;
4603
4604 sky2_debug = ent;
4605 register_netdevice_notifier(&sky2_notifier);
4606}
4607
4608static __exit void sky2_debug_cleanup(void)
4609{
4610 if (sky2_debug) {
4611 unregister_netdevice_notifier(&sky2_notifier);
4612 debugfs_remove(sky2_debug);
4613 sky2_debug = NULL;
4614 }
4615}
4616
4617#else
4618#define sky2_debug_init()
4619#define sky2_debug_cleanup()
4620#endif
4621
1436b301
SH		 4622/* Two copies of network device operations to handle special case of
4623 not allowing netpoll on second port */
4624static const struct net_device_ops sky2_netdev_ops[2] = {
4625 {
4626 .ndo_open = sky2_up,
4627 .ndo_stop = sky2_down,
00829823 4628 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4629 .ndo_do_ioctl = sky2_ioctl,
4630 .ndo_validate_addr = eth_validate_addr,
4631 .ndo_set_mac_address = sky2_set_mac_address,
afc4b13d 4632 .ndo_set_rx_mode = sky2_set_multicast,
1436b301 4633 .ndo_change_mtu = sky2_change_mtu,
f5d64037
MM		 4634 .ndo_fix_features = sky2_fix_features,
4635 .ndo_set_features = sky2_set_features,
1436b301 4636 .ndo_tx_timeout = sky2_tx_timeout,
0885a30b 4637 .ndo_get_stats64 = sky2_get_stats,
1436b301
SH		 4638#ifdef CONFIG_NET_POLL_CONTROLLER
4639 .ndo_poll_controller = sky2_netpoll,
4640#endif
4641 },
4642 {
4643 .ndo_open = sky2_up,
4644 .ndo_stop = sky2_down,
00829823 4645 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4646 .ndo_do_ioctl = sky2_ioctl,
4647 .ndo_validate_addr = eth_validate_addr,
4648 .ndo_set_mac_address = sky2_set_mac_address,
afc4b13d 4649 .ndo_set_rx_mode = sky2_set_multicast,
1436b301 4650 .ndo_change_mtu = sky2_change_mtu,
f5d64037
MM		 4651 .ndo_fix_features = sky2_fix_features,
4652 .ndo_set_features = sky2_set_features,
1436b301 4653 .ndo_tx_timeout = sky2_tx_timeout,
0885a30b 4654 .ndo_get_stats64 = sky2_get_stats,
1436b301
SH		 4655 },
4656};
3cf26753 4657
cd28ab6a
SH		 4658/* Initialize network device */
4659static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4660 unsigned port,
be63a21c 4661 int highmem, int wol)
cd28ab6a
SH		 4662{
4663 struct sky2_port *sky2;
4664 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4665
4666 if (!dev) {
898eb71c 4667 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4668 return NULL;
4669 }
4670
cd28ab6a 4671 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4672 dev->irq = hw->pdev->irq;
cd28ab6a 4673 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4674 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4675 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4676
4677 sky2 = netdev_priv(dev);
4678 sky2->netdev = dev;
4679 sky2->hw = hw;
4680 sky2->msg_enable = netif_msg_init(debug, default_msg);
4681
cd28ab6a 4682 /* Auto speed and flow control */
0ea065e5
SH		 4683 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4684 if (hw->chip_id != CHIP_ID_YUKON_XL)
f5d64037 4685 dev->hw_features |= NETIF_F_RXCSUM;
0ea065e5 4686
16ad91e1
SH		 4687 sky2->flow_mode = FC_BOTH;
4688
cd28ab6a
SH		 4689 sky2->duplex = -1;
4690 sky2->speed = -1;
4691 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4692 sky2->wol = wol;
75d070c5 4693
e07b1aa8 4694 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4695
793b883e 4696 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4697 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4698 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4699
4700 hw->dev[port] = dev;
4701
4702 sky2->port = port;
4703
f5d64037 4704 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
86aa7785 4705
cd28ab6a
SH		 4706 if (highmem)
4707 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4708
bf73130d
SH		 4709 /* Enable receive hashing unless hardware is known broken */
4710 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
f5d64037
MM		 4711 dev->hw_features |= NETIF_F_RXHASH;
4712
4713 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4714 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4715 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4716 }
bf73130d 4717
f5d64037 4718 dev->features |= dev->hw_features;
d1f13708 4719
cd28ab6a 4720 /* read the mac address */
793b883e 4721 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4722 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4723
cd28ab6a
SH		 4724 return dev;
4725}
4726
28bd181a 4727static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4728{
4729 const struct sky2_port *sky2 = netdev_priv(dev);
4730
6c35abae 4731 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4732}
4733
fb2690a9 4734/* Handle software interrupt used during MSI test */
7d12e780 4735static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4736{
4737 struct sky2_hw *hw = dev_id;
4738 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4739
4740 if (status == 0)
4741 return IRQ_NONE;
4742
4743 if (status & Y2_IS_IRQ_SW) {
ea76e635 4744 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4745 wake_up(&hw->msi_wait);
4746 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4747 }
4748 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4749
4750 return IRQ_HANDLED;
4751}
4752
4753/* Test interrupt path by forcing a a software IRQ */
4754static int __devinit sky2_test_msi(struct sky2_hw *hw)
4755{
4756 struct pci_dev *pdev = hw->pdev;
4757 int err;
4758
060b946c 4759 init_waitqueue_head(&hw->msi_wait);
bb507fe1 4760
fb2690a9
SH		 4761 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4762
b0a20ded 4763 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4764 if (err) {
b02a9258 4765 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4766 return err;
4767 }
4768
fb2690a9 4769 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4770 sky2_read8(hw, B0_CTST);
fb2690a9 4771
ea76e635 4772 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4773
ea76e635 4774 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4775 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4776 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4777 "switching to INTx mode.\n");
fb2690a9
SH		 4778
4779 err = -EOPNOTSUPP;
4780 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4781 }
4782
4783 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4784 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4785
4786 free_irq(pdev->irq, hw);
4787
4788 return err;
4789}
4790
c7127a34
SH		 4791/* This driver supports yukon2 chipset only */
4792static const char *sky2_name(u8 chipid, char *buf, int sz)
4793{
4794 const char *name[] = {
4795 "XL", /* 0xb3 */
4796 "EC Ultra", /* 0xb4 */
4797 "Extreme", /* 0xb5 */
4798 "EC", /* 0xb6 */
4799 "FE", /* 0xb7 */
4800 "FE+", /* 0xb8 */
4801 "Supreme", /* 0xb9 */
0ce8b98d 4802 "UL 2", /* 0xba */
0f5aac70
SH		 4803 "Unknown", /* 0xbb */
4804 "Optima", /* 0xbc */
4fb99cd6 4805 "Optima Prime", /* 0xbd */
4806 "Optima 2", /* 0xbe */
c7127a34
SH		 4807 };
4808
4fb99cd6 4809 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
c7127a34
SH		 4810 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4811 else
4812 snprintf(buf, sz, "(chip %#x)", chipid);
4813 return buf;
4814}
4815
cd28ab6a
SH		 4816static int __devinit sky2_probe(struct pci_dev *pdev,
4817 const struct pci_device_id *ent)
4818{
0bdb0bd0 4819 struct net_device *dev, *dev1;
cd28ab6a 4820 struct sky2_hw *hw;
be63a21c 4821 int err, using_dac = 0, wol_default;
3834507d 4822 u32 reg;
c7127a34 4823 char buf1[16];
cd28ab6a 4824
793b883e
SH		 4825 err = pci_enable_device(pdev);
4826 if (err) {
b02a9258 4827 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4828 goto err_out;
4829 }
4830
6cc90a5a
SH		 4831 /* Get configuration information
4832 * Note: only regular PCI config access once to test for HW issues
4833 * other PCI access through shared memory for speed and to
4834 * avoid MMCONFIG problems.
4835 */
4836 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4837 if (err) {
4838 dev_err(&pdev->dev, "PCI read config failed\n");
4839 goto err_out;
4840 }
4841
4842 if (~reg == 0) {
4843 dev_err(&pdev->dev, "PCI configuration read error\n");
4844 goto err_out;
4845 }
4846
793b883e
SH		 4847 err = pci_request_regions(pdev, DRV_NAME);
4848 if (err) {
b02a9258 4849 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4850 goto err_out_disable;
cd28ab6a
SH		 4851 }
4852
4853 pci_set_master(pdev);
4854
d1f3d4dd 4855 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4856 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4857 using_dac = 1;
6a35528a 4858 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4859 if (err < 0) {
b02a9258
SH		 4860 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4861 "for consistent allocations\n");
d1f3d4dd
SH		 4862 goto err_out_free_regions;
4863 }
d1f3d4dd 4864 } else {
284901a9 4865 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4866 if (err) {
b02a9258 4867 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4868 goto err_out_free_regions;
4869 }
4870 }
d1f3d4dd 4871
3834507d
SH		 4872
4873#ifdef __BIG_ENDIAN
4874 /* The sk98lin vendor driver uses hardware byte swapping but
4875 * this driver uses software swapping.
4876 */
4877 reg &= ~PCI_REV_DESC;
060b946c 4878 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3834507d
SH		 4879 if (err) {
4880 dev_err(&pdev->dev, "PCI write config failed\n");
4881 goto err_out_free_regions;
4882 }
4883#endif
4884
9d731d77 4885 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4886
cd28ab6a 4887 err = -ENOMEM;
66466797
SH		 4888
4889 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4890 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4891 if (!hw) {
b02a9258 4892 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4893 goto err_out_free_regions;
4894 }
4895
cd28ab6a 4896 hw->pdev = pdev;
66466797 4897 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4898
4899 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4900 if (!hw->regs) {
b02a9258 4901 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4902 goto err_out_free_hw;
4903 }
4904
e3173832 4905 err = sky2_init(hw);
cd28ab6a 4906 if (err)
793b883e 4907 goto err_out_iounmap;
cd28ab6a 4908
efe91932 4909 /* ring for status responses */
bf73130d 4910 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
efe91932 4911 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4912 &hw->st_dma);
4913 if (!hw->st_le)
4914 goto err_out_reset;
4915
c844d483
SH		 4916 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4917 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4918
e3173832
SH		 4919 sky2_reset(hw);
4920
be63a21c 4921 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4922 if (!dev) {
4923 err = -ENOMEM;
cd28ab6a 4924 goto err_out_free_pci;
7f60c64b 4925 }
cd28ab6a 4926
9fa1b1f3
SH		 4927 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4928 err = sky2_test_msi(hw);
4929 if (err == -EOPNOTSUPP)
4930 pci_disable_msi(pdev);
4931 else if (err)
4932 goto err_out_free_netdev;
4933 }
4934
793b883e
SH		 4935 err = register_netdev(dev);
4936 if (err) {
b02a9258 4937 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4938 goto err_out_free_netdev;
4939 }
4940
33cb7d33
BP		 4941 netif_carrier_off(dev);
4942
6de16237
SH		 4943 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4944
cd28ab6a
SH		 4945 sky2_show_addr(dev);
4946
7f60c64b 4947 if (hw->ports > 1) {
be63a21c 4948 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
0bdb0bd0 4949 if (!dev1) {
4950 err = -ENOMEM;
4951 goto err_out_unregister;
ca519274 4952 }
0bdb0bd0 4953
4954 err = register_netdev(dev1);
4955 if (err) {
4956 dev_err(&pdev->dev, "cannot register second net device\n");
4957 goto err_out_free_dev1;
4958 }
4959
4960 err = sky2_setup_irq(hw, hw->irq_name);
4961 if (err)
4962 goto err_out_unregister_dev1;
4963
4964 sky2_show_addr(dev1);
cd28ab6a
SH		 4965 }
4966
32c2c300 4967 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4968 INIT_WORK(&hw->restart_work, sky2_restart);
4969
793b883e 4970 pci_set_drvdata(pdev, hw);
1ae861e6 4971 pdev->d3_delay = 150;
793b883e 4972
cd28ab6a
SH		 4973 return 0;
4974
0bdb0bd0 4975err_out_unregister_dev1:
4976 unregister_netdev(dev1);
4977err_out_free_dev1:
4978 free_netdev(dev1);
793b883e 4979err_out_unregister:
ea76e635 4980 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4981 pci_disable_msi(pdev);
793b883e 4982 unregister_netdev(dev);
cd28ab6a
SH		 4983err_out_free_netdev:
4984 free_netdev(dev);
cd28ab6a 4985err_out_free_pci:
efe91932 4986 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4987 hw->st_le, hw->st_dma);
4988err_out_reset:
793b883e 4989 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4990err_out_iounmap:
4991 iounmap(hw->regs);
4992err_out_free_hw:
4993 kfree(hw);
4994err_out_free_regions:
4995 pci_release_regions(pdev);
44a1d2e5 4996err_out_disable:
cd28ab6a 4997 pci_disable_device(pdev);
cd28ab6a 4998err_out:
549a68c3 4999 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 5000 return err;
5001}
5002
5003static void __devexit sky2_remove(struct pci_dev *pdev)
5004{
793b883e 5005 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 5006 int i;
cd28ab6a 5007
793b883e 5008 if (!hw)
cd28ab6a
SH		 5009 return;
5010
32c2c300 5011 del_timer_sync(&hw->watchdog_timer);
6de16237 5012 cancel_work_sync(&hw->restart_work);
d27ed387 5013
b877fe28 5014 for (i = hw->ports-1; i >= 0; --i)
6de16237 5015 unregister_netdev(hw->dev[i]);
81906791 5016
d27ed387 5017 sky2_write32(hw, B0_IMSK, 0);
0bdb0bd0 5018 sky2_read32(hw, B0_IMSK);
cd28ab6a 5019
ae306cca
SH		 5020 sky2_power_aux(hw);
5021
793b883e 5022 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 5023 sky2_read8(hw, B0_CTST);
cd28ab6a 5024
0bdb0bd0 5025 if (hw->ports > 1) {
5026 napi_disable(&hw->napi);
5027 free_irq(pdev->irq, hw);
5028 }
5029
ea76e635 5030 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 5031 pci_disable_msi(pdev);
efe91932 5032 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5033 hw->st_le, hw->st_dma);
cd28ab6a
SH		 5034 pci_release_regions(pdev);
5035 pci_disable_device(pdev);
793b883e 5036
b877fe28 5037 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 5038 free_netdev(hw->dev[i]);
5039
cd28ab6a
SH		 5040 iounmap(hw->regs);
5041 kfree(hw);
5afa0a9c 5042
cd28ab6a
SH		 5043 pci_set_drvdata(pdev, NULL);
5044}
5045
0f333d10 5046static int sky2_suspend(struct device *dev)
cd28ab6a 5047{
0f333d10 5048 struct pci_dev *pdev = to_pci_dev(dev);
793b883e 5049 struct sky2_hw *hw = pci_get_drvdata(pdev);
0f333d10 5050 int i;
cd28ab6a 5051
549a68c3
SH		 5052 if (!hw)
5053 return 0;
5054
063a0b38
SH		 5055 del_timer_sync(&hw->watchdog_timer);
5056 cancel_work_sync(&hw->restart_work);
5057
19720737 5058 rtnl_lock();
3403aca2
MM		 5059
5060 sky2_all_down(hw);
f05267e7 5061 for (i = 0; i < hw->ports; i++) {
cd28ab6a 5062 struct net_device *dev = hw->dev[i];
e3173832 5063 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 5064
e3173832
SH		 5065 if (sky2->wol)
5066 sky2_wol_init(sky2);
cd28ab6a
SH		 5067 }
5068
ae306cca 5069 sky2_power_aux(hw);
19720737 5070 rtnl_unlock();
e3173832 5071
2ccc99b7 5072 return 0;
cd28ab6a
SH		 5073}
5074
94252763 5075#ifdef CONFIG_PM_SLEEP
0f333d10 5076static int sky2_resume(struct device *dev)
cd28ab6a 5077{
0f333d10 5078 struct pci_dev *pdev = to_pci_dev(dev);
793b883e 5079 struct sky2_hw *hw = pci_get_drvdata(pdev);
3403aca2 5080 int err;
cd28ab6a 5081
549a68c3
SH		 5082 if (!hw)
5083 return 0;
5084
1ad5b4a5 5085 /* Re-enable all clocks */
a0db28b8 5086 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5087 if (err) {
5088 dev_err(&pdev->dev, "PCI write config failed\n");
5089 goto out;
5090 }
1ad5b4a5 5091
3403aca2 5092 rtnl_lock();
e3173832 5093 sky2_reset(hw);
3403aca2 5094 sky2_all_up(hw);
af18d8b8 5095 rtnl_unlock();
eb35cf60 5096
ae306cca 5097 return 0;
08c06d8a 5098out:
af18d8b8 5099
b02a9258 5100 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 5101 pci_disable_device(pdev);
08c06d8a 5102 return err;
cd28ab6a 5103}
0f333d10
RW		 5104
5105static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5106#define SKY2_PM_OPS (&sky2_pm_ops)
5107
5108#else
5109
5110#define SKY2_PM_OPS NULL
cd28ab6a
SH		 5111#endif
5112
e3173832
SH		 5113static void sky2_shutdown(struct pci_dev *pdev)
5114{
0f333d10
RW		 5115 sky2_suspend(&pdev->dev);
5116 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5117 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 5118}
5119
cd28ab6a 5120static struct pci_driver sky2_driver = {
793b883e
SH		 5121 .name = DRV_NAME,
5122 .id_table = sky2_id_table,
5123 .probe = sky2_probe,
5124 .remove = __devexit_p(sky2_remove),
e3173832 5125 .shutdown = sky2_shutdown,
0f333d10 5126 .driver.pm = SKY2_PM_OPS,
cd28ab6a
SH		 5127};
5128
5129static int __init sky2_init_module(void)
5130{
ada1db5c 5131 pr_info("driver version " DRV_VERSION "\n");
c844d483 5132
3cf26753 5133 sky2_debug_init();
50241c4c 5134 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 5135}
5136
5137static void __exit sky2_cleanup_module(void)
5138{
5139 pci_unregister_driver(&sky2_driver);
3cf26753 5140 sky2_debug_cleanup();
cd28ab6a
SH		 5141}
5142
5143module_init(sky2_init_module);
5144module_exit(sky2_cleanup_module);
5145
5146MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 5147MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 5148MODULE_LICENSE("GPL");
5f4f9dc1 5149MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)