Commit | Line | Data |
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3f518509 MW |
1 | /* |
2 | * Driver for Marvell PPv2 network controller for Armada 375 SoC. | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * | |
6 | * Marcin Wojtas <mw@semihalf.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
a75edc7c | 13 | #include <linux/acpi.h> |
3f518509 MW |
14 | #include <linux/kernel.h> |
15 | #include <linux/netdevice.h> | |
16 | #include <linux/etherdevice.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/skbuff.h> | |
19 | #include <linux/inetdevice.h> | |
20 | #include <linux/mbus.h> | |
21 | #include <linux/module.h> | |
f84bf386 | 22 | #include <linux/mfd/syscon.h> |
3f518509 MW |
23 | #include <linux/interrupt.h> |
24 | #include <linux/cpumask.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/of_mdio.h> | |
28 | #include <linux/of_net.h> | |
29 | #include <linux/of_address.h> | |
faca9247 | 30 | #include <linux/of_device.h> |
3f518509 | 31 | #include <linux/phy.h> |
542897d9 | 32 | #include <linux/phy/phy.h> |
3f518509 | 33 | #include <linux/clk.h> |
edc660fa MW |
34 | #include <linux/hrtimer.h> |
35 | #include <linux/ktime.h> | |
f84bf386 | 36 | #include <linux/regmap.h> |
3f518509 MW |
37 | #include <uapi/linux/ppp_defs.h> |
38 | #include <net/ip.h> | |
39 | #include <net/ipv6.h> | |
186cd4d4 | 40 | #include <net/tso.h> |
3f518509 | 41 | |
7c10f974 | 42 | /* Fifo Registers */ |
3f518509 MW |
43 | #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) |
44 | #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) | |
45 | #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 | |
46 | #define MVPP2_RX_FIFO_INIT_REG 0x64 | |
93ff130f | 47 | #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) |
7c10f974 | 48 | #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) |
3f518509 MW |
49 | |
50 | /* RX DMA Top Registers */ | |
51 | #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) | |
52 | #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) | |
53 | #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) | |
54 | #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) | |
55 | #define MVPP2_POOL_BUF_SIZE_OFFSET 5 | |
56 | #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) | |
57 | #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff | |
58 | #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) | |
59 | #define MVPP2_RXQ_POOL_SHORT_OFFS 20 | |
5eac892a TP |
60 | #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 |
61 | #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 | |
3f518509 | 62 | #define MVPP2_RXQ_POOL_LONG_OFFS 24 |
5eac892a TP |
63 | #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 |
64 | #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 | |
3f518509 MW |
65 | #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 |
66 | #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 | |
67 | #define MVPP2_RXQ_DISABLE_MASK BIT(31) | |
68 | ||
56beda3d MC |
69 | /* Top Registers */ |
70 | #define MVPP2_MH_REG(port) (0x5040 + 4 * (port)) | |
71 | #define MVPP2_DSA_EXTENDED BIT(5) | |
72 | ||
3f518509 MW |
73 | /* Parser Registers */ |
74 | #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 | |
75 | #define MVPP2_PRS_PORT_LU_MAX 0xf | |
76 | #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) | |
77 | #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) | |
78 | #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) | |
79 | #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) | |
80 | #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) | |
81 | #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) | |
82 | #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) | |
83 | #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) | |
84 | #define MVPP2_PRS_TCAM_IDX_REG 0x1100 | |
85 | #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) | |
86 | #define MVPP2_PRS_TCAM_INV_MASK BIT(31) | |
87 | #define MVPP2_PRS_SRAM_IDX_REG 0x1200 | |
88 | #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) | |
89 | #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 | |
90 | #define MVPP2_PRS_TCAM_EN_MASK BIT(0) | |
91 | ||
1d7d15d7 AT |
92 | /* RSS Registers */ |
93 | #define MVPP22_RSS_INDEX 0x1500 | |
8a7b741e | 94 | #define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx) |
1d7d15d7 AT |
95 | #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8) |
96 | #define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16) | |
97 | #define MVPP22_RSS_TABLE_ENTRY 0x1508 | |
98 | #define MVPP22_RSS_TABLE 0x1510 | |
99 | #define MVPP22_RSS_TABLE_POINTER(p) (p) | |
100 | #define MVPP22_RSS_WIDTH 0x150c | |
101 | ||
3f518509 MW |
102 | /* Classifier Registers */ |
103 | #define MVPP2_CLS_MODE_REG 0x1800 | |
104 | #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) | |
105 | #define MVPP2_CLS_PORT_WAY_REG 0x1810 | |
106 | #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) | |
107 | #define MVPP2_CLS_LKP_INDEX_REG 0x1814 | |
108 | #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 | |
109 | #define MVPP2_CLS_LKP_TBL_REG 0x1818 | |
110 | #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff | |
111 | #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) | |
112 | #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 | |
113 | #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 | |
114 | #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 | |
115 | #define MVPP2_CLS_FLOW_TBL2_REG 0x182c | |
116 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) | |
117 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 | |
118 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 | |
119 | #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) | |
120 | #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 | |
121 | #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) | |
122 | ||
123 | /* Descriptor Manager Top Registers */ | |
124 | #define MVPP2_RXQ_NUM_REG 0x2040 | |
125 | #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 | |
b02f31fb | 126 | #define MVPP22_DESC_ADDR_OFFS 8 |
3f518509 MW |
127 | #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 |
128 | #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 | |
129 | #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) | |
130 | #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 | |
131 | #define MVPP2_RXQ_NUM_NEW_OFFSET 16 | |
132 | #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) | |
133 | #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff | |
134 | #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 | |
135 | #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 | |
136 | #define MVPP2_RXQ_THRESH_REG 0x204c | |
137 | #define MVPP2_OCCUPIED_THRESH_OFFSET 0 | |
138 | #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff | |
139 | #define MVPP2_RXQ_INDEX_REG 0x2050 | |
140 | #define MVPP2_TXQ_NUM_REG 0x2080 | |
141 | #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 | |
142 | #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 | |
143 | #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 | |
213f428f TP |
144 | #define MVPP2_TXQ_THRESH_REG 0x2094 |
145 | #define MVPP2_TXQ_THRESH_OFFSET 16 | |
146 | #define MVPP2_TXQ_THRESH_MASK 0x3fff | |
3f518509 | 147 | #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 |
3f518509 MW |
148 | #define MVPP2_TXQ_INDEX_REG 0x2098 |
149 | #define MVPP2_TXQ_PREF_BUF_REG 0x209c | |
150 | #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) | |
151 | #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) | |
152 | #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) | |
153 | #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) | |
154 | #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) | |
155 | #define MVPP2_TXQ_PENDING_REG 0x20a0 | |
156 | #define MVPP2_TXQ_PENDING_MASK 0x3fff | |
157 | #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 | |
158 | #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) | |
159 | #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 | |
160 | #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 | |
161 | #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 | |
162 | #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 | |
163 | #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 | |
164 | #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff | |
165 | #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 | |
166 | #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 | |
167 | #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) | |
b02f31fb | 168 | #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 |
3f518509 MW |
169 | #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) |
170 | #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 | |
171 | #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) | |
172 | #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff | |
173 | #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) | |
174 | ||
175 | /* MBUS bridge registers */ | |
176 | #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) | |
177 | #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) | |
178 | #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) | |
179 | #define MVPP2_BASE_ADDR_ENABLE 0x4060 | |
180 | ||
6763ce31 TP |
181 | /* AXI Bridge Registers */ |
182 | #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 | |
183 | #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 | |
184 | #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 | |
185 | #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 | |
186 | #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 | |
187 | #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c | |
188 | #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 | |
189 | #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 | |
190 | #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 | |
191 | #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 | |
192 | #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 | |
193 | #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 | |
194 | ||
195 | /* Values for AXI Bridge registers */ | |
196 | #define MVPP22_AXI_ATTR_CACHE_OFFS 0 | |
197 | #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 | |
198 | ||
199 | #define MVPP22_AXI_CODE_CACHE_OFFS 0 | |
200 | #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 | |
201 | ||
202 | #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 | |
203 | #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 | |
204 | #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb | |
205 | ||
206 | #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 | |
207 | #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 | |
208 | ||
3f518509 | 209 | /* Interrupt Cause and Mask registers */ |
213f428f TP |
210 | #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) |
211 | #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0 | |
212 | ||
3f518509 | 213 | #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) |
ab42676a | 214 | #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 |
eb1e93a1 | 215 | #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) |
a73fef10 | 216 | |
81b6630f | 217 | #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 |
a73fef10 | 218 | #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf |
81b6630f AT |
219 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 |
220 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 | |
a73fef10 TP |
221 | |
222 | #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf | |
81b6630f | 223 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 |
a73fef10 | 224 | |
81b6630f AT |
225 | #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 |
226 | #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f | |
227 | #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 | |
228 | #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 | |
a73fef10 | 229 | |
3f518509 MW |
230 | #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) |
231 | #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) | |
232 | #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) | |
233 | #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) | |
234 | #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff | |
235 | #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 | |
213f428f | 236 | #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 |
3f518509 MW |
237 | #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) |
238 | #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) | |
239 | #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) | |
240 | #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) | |
241 | #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) | |
242 | #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) | |
243 | #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) | |
244 | #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc | |
245 | #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff | |
246 | #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 | |
247 | #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) | |
248 | #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 | |
249 | ||
250 | /* Buffer Manager registers */ | |
251 | #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) | |
252 | #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 | |
253 | #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) | |
254 | #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 | |
255 | #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) | |
256 | #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 | |
257 | #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) | |
258 | #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 | |
259 | #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) | |
260 | #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) | |
261 | #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff | |
effbf5f5 | 262 | #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8 |
3f518509 MW |
263 | #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) |
264 | #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) | |
265 | #define MVPP2_BM_START_MASK BIT(0) | |
266 | #define MVPP2_BM_STOP_MASK BIT(1) | |
267 | #define MVPP2_BM_STATE_MASK BIT(4) | |
268 | #define MVPP2_BM_LOW_THRESH_OFFS 8 | |
269 | #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 | |
270 | #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ | |
271 | MVPP2_BM_LOW_THRESH_OFFS) | |
272 | #define MVPP2_BM_HIGH_THRESH_OFFS 16 | |
273 | #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 | |
274 | #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ | |
275 | MVPP2_BM_HIGH_THRESH_OFFS) | |
276 | #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) | |
277 | #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) | |
278 | #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) | |
279 | #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) | |
280 | #define MVPP2_BM_BPPE_FULL_MASK BIT(3) | |
281 | #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) | |
282 | #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) | |
283 | #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) | |
284 | #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) | |
285 | #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 | |
d01524d8 TP |
286 | #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444 |
287 | #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff | |
288 | #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 | |
289 | #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 | |
3f518509 MW |
290 | #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) |
291 | #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) | |
292 | #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) | |
293 | #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) | |
294 | #define MVPP2_BM_VIRT_RLS_REG 0x64c0 | |
d01524d8 TP |
295 | #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 |
296 | #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff | |
81b6630f | 297 | #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 |
d01524d8 | 298 | #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 |
3f518509 MW |
299 | |
300 | /* TX Scheduler registers */ | |
301 | #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 | |
302 | #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 | |
303 | #define MVPP2_TXP_SCHED_ENQ_MASK 0xff | |
304 | #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 | |
305 | #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 | |
306 | #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 | |
307 | #define MVPP2_TXP_SCHED_MTU_REG 0x801c | |
308 | #define MVPP2_TXP_MTU_MAX 0x7FFFF | |
309 | #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 | |
310 | #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff | |
311 | #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 | |
312 | #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) | |
313 | #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 | |
314 | #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff | |
315 | #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) | |
316 | #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff | |
317 | #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 | |
318 | #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) | |
319 | #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) | |
320 | #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
321 | #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) | |
322 | #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff | |
323 | ||
324 | /* TX general registers */ | |
325 | #define MVPP2_TX_SNOOP_REG 0x8800 | |
326 | #define MVPP2_TX_PORT_FLUSH_REG 0x8810 | |
327 | #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) | |
328 | ||
329 | /* LMS registers */ | |
330 | #define MVPP2_SRC_ADDR_MIDDLE 0x24 | |
331 | #define MVPP2_SRC_ADDR_HIGH 0x28 | |
08a23755 MW |
332 | #define MVPP2_PHY_AN_CFG0_REG 0x34 |
333 | #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) | |
3f518509 | 334 | #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c |
31d7677b | 335 | #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 |
3f518509 MW |
336 | |
337 | /* Per-port registers */ | |
338 | #define MVPP2_GMAC_CTRL_0_REG 0x0 | |
81b6630f | 339 | #define MVPP2_GMAC_PORT_EN_MASK BIT(0) |
3919357f | 340 | #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) |
81b6630f AT |
341 | #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 |
342 | #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
343 | #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) | |
3f518509 | 344 | #define MVPP2_GMAC_CTRL_1_REG 0x4 |
81b6630f AT |
345 | #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) |
346 | #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) | |
347 | #define MVPP2_GMAC_PCS_LB_EN_BIT 6 | |
348 | #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) | |
349 | #define MVPP2_GMAC_SA_LOW_OFFS 7 | |
3f518509 | 350 | #define MVPP2_GMAC_CTRL_2_REG 0x8 |
81b6630f | 351 | #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) |
3919357f | 352 | #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) |
81b6630f | 353 | #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) |
c7dfc8c8 | 354 | #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) |
3919357f | 355 | #define MVPP2_GMAC_DISABLE_PADDING BIT(5) |
81b6630f | 356 | #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) |
3f518509 | 357 | #define MVPP2_GMAC_AUTONEG_CONFIG 0xc |
81b6630f AT |
358 | #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) |
359 | #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) | |
3919357f AT |
360 | #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) |
361 | #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) | |
81b6630f AT |
362 | #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) |
363 | #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) | |
364 | #define MVPP2_GMAC_AN_SPEED_EN BIT(7) | |
365 | #define MVPP2_GMAC_FC_ADV_EN BIT(9) | |
3919357f | 366 | #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) |
81b6630f AT |
367 | #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
368 | #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) | |
fd3651b2 AT |
369 | #define MVPP2_GMAC_STATUS0 0x10 |
370 | #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) | |
3f518509 | 371 | #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c |
81b6630f AT |
372 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 |
373 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 | |
374 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ | |
3f518509 | 375 | MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) |
fd3651b2 AT |
376 | #define MVPP22_GMAC_INT_STAT 0x20 |
377 | #define MVPP22_GMAC_INT_STAT_LINK BIT(1) | |
378 | #define MVPP22_GMAC_INT_MASK 0x24 | |
379 | #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1) | |
26975821 | 380 | #define MVPP22_GMAC_CTRL_4_REG 0x90 |
81b6630f AT |
381 | #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) |
382 | #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) | |
1068ec79 | 383 | #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) |
81b6630f | 384 | #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) |
fd3651b2 AT |
385 | #define MVPP22_GMAC_INT_SUM_MASK 0xa4 |
386 | #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) | |
26975821 TP |
387 | |
388 | /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, | |
389 | * relative to port->base. | |
390 | */ | |
725757ae | 391 | #define MVPP22_XLG_CTRL0_REG 0x100 |
81b6630f AT |
392 | #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) |
393 | #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) | |
77321959 | 394 | #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) |
81b6630f | 395 | #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) |
76eb1b1d | 396 | #define MVPP22_XLG_CTRL1_REG 0x104 |
ec15ecde | 397 | #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0 |
76eb1b1d | 398 | #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff |
fd3651b2 AT |
399 | #define MVPP22_XLG_STATUS 0x10c |
400 | #define MVPP22_XLG_STATUS_LINK_UP BIT(0) | |
401 | #define MVPP22_XLG_INT_STAT 0x114 | |
402 | #define MVPP22_XLG_INT_STAT_LINK BIT(1) | |
403 | #define MVPP22_XLG_INT_MASK 0x118 | |
404 | #define MVPP22_XLG_INT_MASK_LINK BIT(1) | |
26975821 | 405 | #define MVPP22_XLG_CTRL3_REG 0x11c |
81b6630f AT |
406 | #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) |
407 | #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) | |
408 | #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) | |
fd3651b2 AT |
409 | #define MVPP22_XLG_EXT_INT_MASK 0x15c |
410 | #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) | |
411 | #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) | |
77321959 AT |
412 | #define MVPP22_XLG_CTRL4_REG 0x184 |
413 | #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) | |
414 | #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) | |
415 | #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) | |
416 | ||
26975821 TP |
417 | /* SMI registers. PPv2.2 only, relative to priv->iface_base. */ |
418 | #define MVPP22_SMI_MISC_CFG_REG 0x1204 | |
81b6630f | 419 | #define MVPP22_SMI_POLLING_EN BIT(10) |
3f518509 | 420 | |
a786841d TP |
421 | #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) |
422 | ||
3f518509 MW |
423 | #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff |
424 | ||
425 | /* Descriptor ring Macros */ | |
426 | #define MVPP2_QUEUE_NEXT_DESC(q, index) \ | |
427 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
428 | ||
f84bf386 AT |
429 | /* XPCS registers. PPv2.2 only */ |
430 | #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000) | |
431 | #define MVPP22_MPCS_CTRL 0x14 | |
432 | #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10) | |
433 | #define MVPP22_MPCS_CLK_RESET 0x14c | |
434 | #define MAC_CLK_RESET_SD_TX BIT(0) | |
435 | #define MAC_CLK_RESET_SD_RX BIT(1) | |
436 | #define MAC_CLK_RESET_MAC BIT(2) | |
437 | #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) | |
438 | #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) | |
439 | ||
440 | /* XPCS registers. PPv2.2 only */ | |
441 | #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) | |
442 | #define MVPP22_XPCS_CFG0 0x0 | |
443 | #define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3) | |
444 | #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5) | |
445 | ||
446 | /* System controller registers. Accessed through a regmap. */ | |
447 | #define GENCONF_SOFT_RESET1 0x1108 | |
448 | #define GENCONF_SOFT_RESET1_GOP BIT(6) | |
449 | #define GENCONF_PORT_CTRL0 0x1110 | |
450 | #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) | |
451 | #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) | |
452 | #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) | |
453 | #define GENCONF_PORT_CTRL1 0x1114 | |
454 | #define GENCONF_PORT_CTRL1_EN(p) BIT(p) | |
455 | #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) | |
456 | #define GENCONF_CTRL0 0x1120 | |
457 | #define GENCONF_CTRL0_PORT0_RGMII BIT(0) | |
458 | #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) | |
459 | #define GENCONF_CTRL0_PORT1_RGMII BIT(2) | |
460 | ||
3f518509 MW |
461 | /* Various constants */ |
462 | ||
463 | /* Coalescing */ | |
86162281 | 464 | #define MVPP2_TXDONE_COAL_PKTS_THRESH 64 |
edc660fa | 465 | #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL |
213f428f | 466 | #define MVPP2_TXDONE_COAL_USEC 1000 |
3f518509 | 467 | #define MVPP2_RX_COAL_PKTS 32 |
86162281 | 468 | #define MVPP2_RX_COAL_USEC 64 |
3f518509 MW |
469 | |
470 | /* The two bytes Marvell header. Either contains a special value used | |
471 | * by Marvell switches when a specific hardware mode is enabled (not | |
472 | * supported by this driver) or is filled automatically by zeroes on | |
473 | * the RX side. Those two bytes being at the front of the Ethernet | |
474 | * header, they allow to have the IP header aligned on a 4 bytes | |
475 | * boundary automatically: the hardware skips those two bytes on its | |
476 | * own. | |
477 | */ | |
478 | #define MVPP2_MH_SIZE 2 | |
479 | #define MVPP2_ETH_TYPE_LEN 2 | |
480 | #define MVPP2_PPPOE_HDR_SIZE 8 | |
481 | #define MVPP2_VLAN_TAG_LEN 4 | |
56beda3d | 482 | #define MVPP2_VLAN_TAG_EDSA_LEN 8 |
3f518509 MW |
483 | |
484 | /* Lbtd 802.3 type */ | |
485 | #define MVPP2_IP_LBDT_TYPE 0xfffa | |
486 | ||
3f518509 MW |
487 | #define MVPP2_TX_CSUM_MAX_SIZE 9800 |
488 | ||
489 | /* Timeout constants */ | |
490 | #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 | |
491 | #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 | |
492 | ||
493 | #define MVPP2_TX_MTU_MAX 0x7ffff | |
494 | ||
495 | /* Maximum number of T-CONTs of PON port */ | |
496 | #define MVPP2_MAX_TCONT 16 | |
497 | ||
498 | /* Maximum number of supported ports */ | |
499 | #define MVPP2_MAX_PORTS 4 | |
500 | ||
501 | /* Maximum number of TXQs used by single port */ | |
502 | #define MVPP2_MAX_TXQ 8 | |
503 | ||
1d17db08 AT |
504 | /* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO |
505 | * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data), | |
506 | * multiply this value by two to count the maximum number of skb descs needed. | |
507 | */ | |
508 | #define MVPP2_MAX_TSO_SEGS 300 | |
509 | #define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
510 | ||
3f518509 MW |
511 | /* Dfault number of RXQs in use */ |
512 | #define MVPP2_DEFAULT_RXQ 4 | |
513 | ||
3f518509 | 514 | /* Max number of Rx descriptors */ |
7cf87e4a YM |
515 | #define MVPP2_MAX_RXD_MAX 1024 |
516 | #define MVPP2_MAX_RXD_DFLT 128 | |
3f518509 MW |
517 | |
518 | /* Max number of Tx descriptors */ | |
7cf87e4a YM |
519 | #define MVPP2_MAX_TXD_MAX 2048 |
520 | #define MVPP2_MAX_TXD_DFLT 1024 | |
3f518509 MW |
521 | |
522 | /* Amount of Tx descriptors that can be reserved at once by CPU */ | |
523 | #define MVPP2_CPU_DESC_CHUNK 64 | |
524 | ||
525 | /* Max number of Tx descriptors in each aggregated queue */ | |
526 | #define MVPP2_AGGR_TXQ_SIZE 256 | |
527 | ||
528 | /* Descriptor aligned size */ | |
529 | #define MVPP2_DESC_ALIGNED_SIZE 32 | |
530 | ||
531 | /* Descriptor alignment mask */ | |
532 | #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) | |
533 | ||
534 | /* RX FIFO constants */ | |
2d1d7df8 AT |
535 | #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000 |
536 | #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000 | |
537 | #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000 | |
538 | #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200 | |
539 | #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80 | |
540 | #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 | |
541 | #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 | |
3f518509 | 542 | |
7c10f974 AT |
543 | /* TX FIFO constants */ |
544 | #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa | |
545 | #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 | |
93ff130f YM |
546 | #define MVPP2_TX_FIFO_THRESHOLD_MIN 256 |
547 | #define MVPP2_TX_FIFO_THRESHOLD_10KB \ | |
548 | (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) | |
549 | #define MVPP2_TX_FIFO_THRESHOLD_3KB \ | |
550 | (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) | |
7c10f974 | 551 | |
3f518509 MW |
552 | /* RX buffer constants */ |
553 | #define MVPP2_SKB_SHINFO_SIZE \ | |
554 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) | |
555 | ||
556 | #define MVPP2_RX_PKT_SIZE(mtu) \ | |
557 | ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ | |
4a0a12d2 | 558 | ETH_HLEN + ETH_FCS_LEN, cache_line_size()) |
3f518509 MW |
559 | |
560 | #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) | |
561 | #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) | |
562 | #define MVPP2_RX_MAX_PKT_SIZE(total_size) \ | |
563 | ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE) | |
564 | ||
565 | #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) | |
566 | ||
567 | /* IPv6 max L3 address size */ | |
568 | #define MVPP2_MAX_L3_ADDR_SIZE 16 | |
569 | ||
570 | /* Port flags */ | |
571 | #define MVPP2_F_LOOPBACK BIT(0) | |
572 | ||
573 | /* Marvell tag types */ | |
574 | enum mvpp2_tag_type { | |
575 | MVPP2_TAG_TYPE_NONE = 0, | |
576 | MVPP2_TAG_TYPE_MH = 1, | |
577 | MVPP2_TAG_TYPE_DSA = 2, | |
578 | MVPP2_TAG_TYPE_EDSA = 3, | |
579 | MVPP2_TAG_TYPE_VLAN = 4, | |
580 | MVPP2_TAG_TYPE_LAST = 5 | |
581 | }; | |
582 | ||
583 | /* Parser constants */ | |
584 | #define MVPP2_PRS_TCAM_SRAM_SIZE 256 | |
585 | #define MVPP2_PRS_TCAM_WORDS 6 | |
586 | #define MVPP2_PRS_SRAM_WORDS 4 | |
587 | #define MVPP2_PRS_FLOW_ID_SIZE 64 | |
588 | #define MVPP2_PRS_FLOW_ID_MASK 0x3f | |
589 | #define MVPP2_PRS_TCAM_ENTRY_INVALID 1 | |
590 | #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5) | |
591 | #define MVPP2_PRS_IPV4_HEAD 0x40 | |
592 | #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0 | |
593 | #define MVPP2_PRS_IPV4_MC 0xe0 | |
594 | #define MVPP2_PRS_IPV4_MC_MASK 0xf0 | |
595 | #define MVPP2_PRS_IPV4_BC_MASK 0xff | |
596 | #define MVPP2_PRS_IPV4_IHL 0x5 | |
597 | #define MVPP2_PRS_IPV4_IHL_MASK 0xf | |
598 | #define MVPP2_PRS_IPV6_MC 0xff | |
599 | #define MVPP2_PRS_IPV6_MC_MASK 0xff | |
600 | #define MVPP2_PRS_IPV6_HOP_MASK 0xff | |
601 | #define MVPP2_PRS_TCAM_PROTO_MASK 0xff | |
602 | #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f | |
603 | #define MVPP2_PRS_DBL_VLANS_MAX 100 | |
604 | ||
605 | /* Tcam structure: | |
606 | * - lookup ID - 4 bits | |
607 | * - port ID - 1 byte | |
608 | * - additional information - 1 byte | |
609 | * - header data - 8 bytes | |
610 | * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0). | |
611 | */ | |
612 | #define MVPP2_PRS_AI_BITS 8 | |
613 | #define MVPP2_PRS_PORT_MASK 0xff | |
614 | #define MVPP2_PRS_LU_MASK 0xf | |
615 | #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \ | |
616 | (((offs) - ((offs) % 2)) * 2 + ((offs) % 2)) | |
617 | #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \ | |
618 | (((offs) * 2) - ((offs) % 2) + 2) | |
619 | #define MVPP2_PRS_TCAM_AI_BYTE 16 | |
620 | #define MVPP2_PRS_TCAM_PORT_BYTE 17 | |
621 | #define MVPP2_PRS_TCAM_LU_BYTE 20 | |
622 | #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2) | |
623 | #define MVPP2_PRS_TCAM_INV_WORD 5 | |
56beda3d MC |
624 | |
625 | #define MVPP2_PRS_VID_TCAM_BYTE 2 | |
626 | ||
627 | /* There is a TCAM range reserved for VLAN filtering entries, range size is 33 | |
628 | * 10 VLAN ID filter entries per port | |
629 | * 1 default VLAN filter entry per port | |
630 | * It is assumed that there are 3 ports for filter, not including loopback port | |
631 | */ | |
632 | #define MVPP2_PRS_VLAN_FILT_MAX 11 | |
633 | #define MVPP2_PRS_VLAN_FILT_RANGE_SIZE 33 | |
634 | ||
635 | #define MVPP2_PRS_VLAN_FILT_MAX_ENTRY (MVPP2_PRS_VLAN_FILT_MAX - 2) | |
636 | #define MVPP2_PRS_VLAN_FILT_DFLT_ENTRY (MVPP2_PRS_VLAN_FILT_MAX - 1) | |
637 | ||
3f518509 MW |
638 | /* Tcam entries ID */ |
639 | #define MVPP2_PE_DROP_ALL 0 | |
640 | #define MVPP2_PE_FIRST_FREE_TID 1 | |
56beda3d MC |
641 | |
642 | /* VLAN filtering range */ | |
643 | #define MVPP2_PE_VID_FILT_RANGE_END (MVPP2_PRS_TCAM_SRAM_SIZE - 31) | |
644 | #define MVPP2_PE_VID_FILT_RANGE_START (MVPP2_PE_VID_FILT_RANGE_END - \ | |
645 | MVPP2_PRS_VLAN_FILT_RANGE_SIZE + 1) | |
646 | #define MVPP2_PE_LAST_FREE_TID (MVPP2_PE_VID_FILT_RANGE_START - 1) | |
3f518509 MW |
647 | #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30) |
648 | #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29) | |
649 | #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28) | |
650 | #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27) | |
651 | #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26) | |
56beda3d MC |
652 | #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 21) |
653 | #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 20) | |
654 | #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 19) | |
655 | #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18) | |
656 | #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17) | |
657 | #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16) | |
658 | #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15) | |
659 | #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14) | |
660 | #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13) | |
661 | #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 12) | |
662 | #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 11) | |
663 | #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 10) | |
664 | #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 9) | |
665 | #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8) | |
666 | #define MVPP2_PE_VID_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 7) | |
667 | #define MVPP2_PE_VID_EDSA_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 6) | |
3f518509 MW |
668 | #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5) |
669 | #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4) | |
670 | #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3) | |
671 | #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2) | |
672 | #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1) | |
673 | ||
56beda3d MC |
674 | #define MVPP2_PRS_VID_PORT_FIRST(port) (MVPP2_PE_VID_FILT_RANGE_START + \ |
675 | ((port) * MVPP2_PRS_VLAN_FILT_MAX)) | |
676 | #define MVPP2_PRS_VID_PORT_LAST(port) (MVPP2_PRS_VID_PORT_FIRST(port) \ | |
677 | + MVPP2_PRS_VLAN_FILT_MAX_ENTRY) | |
678 | /* Index of default vid filter for given port */ | |
679 | #define MVPP2_PRS_VID_PORT_DFLT(port) (MVPP2_PRS_VID_PORT_FIRST(port) \ | |
680 | + MVPP2_PRS_VLAN_FILT_DFLT_ENTRY) | |
681 | ||
3f518509 MW |
682 | /* Sram structure |
683 | * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0). | |
684 | */ | |
685 | #define MVPP2_PRS_SRAM_RI_OFFS 0 | |
686 | #define MVPP2_PRS_SRAM_RI_WORD 0 | |
687 | #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32 | |
688 | #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1 | |
689 | #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32 | |
690 | #define MVPP2_PRS_SRAM_SHIFT_OFFS 64 | |
691 | #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72 | |
692 | #define MVPP2_PRS_SRAM_UDF_OFFS 73 | |
693 | #define MVPP2_PRS_SRAM_UDF_BITS 8 | |
694 | #define MVPP2_PRS_SRAM_UDF_MASK 0xff | |
695 | #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81 | |
696 | #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82 | |
697 | #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7 | |
698 | #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1 | |
699 | #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4 | |
700 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85 | |
701 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3 | |
702 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1 | |
703 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2 | |
704 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3 | |
705 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87 | |
706 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2 | |
707 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3 | |
708 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0 | |
709 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2 | |
710 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3 | |
711 | #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89 | |
712 | #define MVPP2_PRS_SRAM_AI_OFFS 90 | |
713 | #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98 | |
714 | #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8 | |
715 | #define MVPP2_PRS_SRAM_AI_MASK 0xff | |
716 | #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106 | |
717 | #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf | |
718 | #define MVPP2_PRS_SRAM_LU_DONE_BIT 110 | |
719 | #define MVPP2_PRS_SRAM_LU_GEN_BIT 111 | |
720 | ||
721 | /* Sram result info bits assignment */ | |
722 | #define MVPP2_PRS_RI_MAC_ME_MASK 0x1 | |
723 | #define MVPP2_PRS_RI_DSA_MASK 0x2 | |
8138affc TP |
724 | #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3)) |
725 | #define MVPP2_PRS_RI_VLAN_NONE 0x0 | |
3f518509 MW |
726 | #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) |
727 | #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) | |
728 | #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) | |
729 | #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70 | |
730 | #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) | |
8138affc TP |
731 | #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) |
732 | #define MVPP2_PRS_RI_L2_UCAST 0x0 | |
3f518509 MW |
733 | #define MVPP2_PRS_RI_L2_MCAST BIT(9) |
734 | #define MVPP2_PRS_RI_L2_BCAST BIT(10) | |
735 | #define MVPP2_PRS_RI_PPPOE_MASK 0x800 | |
8138affc TP |
736 | #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14)) |
737 | #define MVPP2_PRS_RI_L3_UN 0x0 | |
3f518509 MW |
738 | #define MVPP2_PRS_RI_L3_IP4 BIT(12) |
739 | #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) | |
740 | #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) | |
741 | #define MVPP2_PRS_RI_L3_IP6 BIT(14) | |
742 | #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) | |
743 | #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) | |
8138affc TP |
744 | #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16)) |
745 | #define MVPP2_PRS_RI_L3_UCAST 0x0 | |
3f518509 MW |
746 | #define MVPP2_PRS_RI_L3_MCAST BIT(15) |
747 | #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) | |
748 | #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000 | |
aff3da39 | 749 | #define MVPP2_PRS_RI_IP_FRAG_TRUE BIT(17) |
3f518509 MW |
750 | #define MVPP2_PRS_RI_UDF3_MASK 0x300000 |
751 | #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21) | |
752 | #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000 | |
753 | #define MVPP2_PRS_RI_L4_TCP BIT(22) | |
754 | #define MVPP2_PRS_RI_L4_UDP BIT(23) | |
755 | #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23)) | |
756 | #define MVPP2_PRS_RI_UDF7_MASK 0x60000000 | |
757 | #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29) | |
758 | #define MVPP2_PRS_RI_DROP_MASK 0x80000000 | |
759 | ||
760 | /* Sram additional info bits assignment */ | |
761 | #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0) | |
762 | #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0) | |
763 | #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1) | |
764 | #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2) | |
765 | #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3) | |
766 | #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4) | |
767 | #define MVPP2_PRS_SINGLE_VLAN_AI 0 | |
768 | #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7) | |
56beda3d | 769 | #define MVPP2_PRS_EDSA_VID_AI_BIT BIT(0) |
3f518509 MW |
770 | |
771 | /* DSA/EDSA type */ | |
772 | #define MVPP2_PRS_TAGGED true | |
773 | #define MVPP2_PRS_UNTAGGED false | |
774 | #define MVPP2_PRS_EDSA true | |
775 | #define MVPP2_PRS_DSA false | |
776 | ||
777 | /* MAC entries, shadow udf */ | |
778 | enum mvpp2_prs_udf { | |
779 | MVPP2_PRS_UDF_MAC_DEF, | |
780 | MVPP2_PRS_UDF_MAC_RANGE, | |
781 | MVPP2_PRS_UDF_L2_DEF, | |
782 | MVPP2_PRS_UDF_L2_DEF_COPY, | |
783 | MVPP2_PRS_UDF_L2_USER, | |
784 | }; | |
785 | ||
786 | /* Lookup ID */ | |
787 | enum mvpp2_prs_lookup { | |
788 | MVPP2_PRS_LU_MH, | |
789 | MVPP2_PRS_LU_MAC, | |
790 | MVPP2_PRS_LU_DSA, | |
791 | MVPP2_PRS_LU_VLAN, | |
56beda3d | 792 | MVPP2_PRS_LU_VID, |
3f518509 MW |
793 | MVPP2_PRS_LU_L2, |
794 | MVPP2_PRS_LU_PPPOE, | |
795 | MVPP2_PRS_LU_IP4, | |
796 | MVPP2_PRS_LU_IP6, | |
797 | MVPP2_PRS_LU_FLOWS, | |
798 | MVPP2_PRS_LU_LAST, | |
799 | }; | |
800 | ||
801 | /* L3 cast enum */ | |
802 | enum mvpp2_prs_l3_cast { | |
803 | MVPP2_PRS_L3_UNI_CAST, | |
804 | MVPP2_PRS_L3_MULTI_CAST, | |
805 | MVPP2_PRS_L3_BROAD_CAST | |
806 | }; | |
807 | ||
808 | /* Classifier constants */ | |
809 | #define MVPP2_CLS_FLOWS_TBL_SIZE 512 | |
810 | #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3 | |
811 | #define MVPP2_CLS_LKP_TBL_SIZE 64 | |
1d7d15d7 AT |
812 | #define MVPP2_CLS_RX_QUEUES 256 |
813 | ||
814 | /* RSS constants */ | |
815 | #define MVPP22_RSS_TABLE_ENTRIES 32 | |
3f518509 MW |
816 | |
817 | /* BM constants */ | |
576193f2 | 818 | #define MVPP2_BM_JUMBO_BUF_NUM 512 |
3f518509 MW |
819 | #define MVPP2_BM_LONG_BUF_NUM 1024 |
820 | #define MVPP2_BM_SHORT_BUF_NUM 2048 | |
821 | #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) | |
822 | #define MVPP2_BM_POOL_PTR_ALIGN 128 | |
3f518509 MW |
823 | |
824 | /* BM cookie (32 bits) definition */ | |
825 | #define MVPP2_BM_COOKIE_POOL_OFFS 8 | |
826 | #define MVPP2_BM_COOKIE_CPU_OFFS 24 | |
827 | ||
01d04936 SC |
828 | #define MVPP2_BM_SHORT_FRAME_SIZE 512 |
829 | #define MVPP2_BM_LONG_FRAME_SIZE 2048 | |
576193f2 | 830 | #define MVPP2_BM_JUMBO_FRAME_SIZE 10240 |
3f518509 MW |
831 | /* BM short pool packet size |
832 | * These value assure that for SWF the total number | |
833 | * of bytes allocated for each buffer will be 512 | |
834 | */ | |
01d04936 SC |
835 | #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE) |
836 | #define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE) | |
576193f2 | 837 | #define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE) |
3f518509 | 838 | |
a786841d TP |
839 | #define MVPP21_ADDR_SPACE_SZ 0 |
840 | #define MVPP22_ADDR_SPACE_SZ SZ_64K | |
841 | ||
df089aa0 | 842 | #define MVPP2_MAX_THREADS 8 |
591f4cfa | 843 | #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS |
a786841d | 844 | |
01d04936 SC |
845 | enum mvpp2_bm_pool_log_num { |
846 | MVPP2_BM_SHORT, | |
847 | MVPP2_BM_LONG, | |
576193f2 | 848 | MVPP2_BM_JUMBO, |
01d04936 | 849 | MVPP2_BM_POOLS_NUM |
3f518509 MW |
850 | }; |
851 | ||
01d04936 SC |
852 | static struct { |
853 | int pkt_size; | |
854 | int buf_num; | |
855 | } mvpp2_pools[MVPP2_BM_POOLS_NUM]; | |
856 | ||
118d6298 MR |
857 | /* GMAC MIB Counters register definitions */ |
858 | #define MVPP21_MIB_COUNTERS_OFFSET 0x1000 | |
859 | #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400 | |
860 | #define MVPP22_MIB_COUNTERS_OFFSET 0x0 | |
861 | #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100 | |
862 | ||
863 | #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0 | |
864 | #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8 | |
865 | #define MVPP2_MIB_CRC_ERRORS_SENT 0xc | |
866 | #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10 | |
867 | #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18 | |
868 | #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c | |
869 | #define MVPP2_MIB_FRAMES_64_OCTETS 0x20 | |
870 | #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24 | |
871 | #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28 | |
872 | #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c | |
873 | #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30 | |
874 | #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 | |
875 | #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38 | |
876 | #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40 | |
877 | #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48 | |
878 | #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c | |
879 | #define MVPP2_MIB_FC_SENT 0x54 | |
880 | #define MVPP2_MIB_FC_RCVD 0x58 | |
881 | #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c | |
882 | #define MVPP2_MIB_UNDERSIZE_RCVD 0x60 | |
883 | #define MVPP2_MIB_FRAGMENTS_RCVD 0x64 | |
884 | #define MVPP2_MIB_OVERSIZE_RCVD 0x68 | |
885 | #define MVPP2_MIB_JABBER_RCVD 0x6c | |
886 | #define MVPP2_MIB_MAC_RCV_ERROR 0x70 | |
887 | #define MVPP2_MIB_BAD_CRC_EVENT 0x74 | |
888 | #define MVPP2_MIB_COLLISION 0x78 | |
889 | #define MVPP2_MIB_LATE_COLLISION 0x7c | |
890 | ||
891 | #define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ) | |
892 | ||
3f518509 MW |
893 | /* Definitions */ |
894 | ||
895 | /* Shared Packet Processor resources */ | |
896 | struct mvpp2 { | |
897 | /* Shared registers' base addresses */ | |
3f518509 | 898 | void __iomem *lms_base; |
a786841d TP |
899 | void __iomem *iface_base; |
900 | ||
df089aa0 TP |
901 | /* On PPv2.2, each "software thread" can access the base |
902 | * register through a separate address space, each 64 KB apart | |
903 | * from each other. Typically, such address spaces will be | |
904 | * used per CPU. | |
a786841d | 905 | */ |
df089aa0 | 906 | void __iomem *swth_base[MVPP2_MAX_THREADS]; |
3f518509 | 907 | |
f84bf386 AT |
908 | /* On PPv2.2, some port control registers are located into the system |
909 | * controller space. These registers are accessible through a regmap. | |
910 | */ | |
911 | struct regmap *sysctrl_base; | |
912 | ||
3f518509 MW |
913 | /* Common clocks */ |
914 | struct clk *pp_clk; | |
915 | struct clk *gop_clk; | |
fceb55d4 | 916 | struct clk *mg_clk; |
4792ea04 | 917 | struct clk *axi_clk; |
3f518509 MW |
918 | |
919 | /* List of pointers to port structures */ | |
118d6298 | 920 | int port_count; |
bf147153 | 921 | struct mvpp2_port *port_list[MVPP2_MAX_PORTS]; |
3f518509 MW |
922 | |
923 | /* Aggregated TXQs */ | |
924 | struct mvpp2_tx_queue *aggr_txqs; | |
925 | ||
926 | /* BM pools */ | |
927 | struct mvpp2_bm_pool *bm_pools; | |
928 | ||
929 | /* PRS shadow table */ | |
930 | struct mvpp2_prs_shadow *prs_shadow; | |
931 | /* PRS auxiliary table for double vlan entries control */ | |
932 | bool *prs_double_vlans; | |
933 | ||
934 | /* Tclk value */ | |
935 | u32 tclk; | |
faca9247 TP |
936 | |
937 | /* HW version */ | |
938 | enum { MVPP21, MVPP22 } hw_version; | |
59b9a31e TP |
939 | |
940 | /* Maximum number of RXQs per port */ | |
941 | unsigned int max_port_rxqs; | |
118d6298 | 942 | |
e5c500eb | 943 | /* Workqueue to gather hardware statistics */ |
118d6298 MR |
944 | char queue_name[30]; |
945 | struct workqueue_struct *stats_queue; | |
3f518509 MW |
946 | }; |
947 | ||
948 | struct mvpp2_pcpu_stats { | |
949 | struct u64_stats_sync syncp; | |
950 | u64 rx_packets; | |
951 | u64 rx_bytes; | |
952 | u64 tx_packets; | |
953 | u64 tx_bytes; | |
954 | }; | |
955 | ||
edc660fa MW |
956 | /* Per-CPU port control */ |
957 | struct mvpp2_port_pcpu { | |
958 | struct hrtimer tx_done_timer; | |
959 | bool timer_scheduled; | |
960 | /* Tasklet for egress finalization */ | |
961 | struct tasklet_struct tx_done_tasklet; | |
962 | }; | |
963 | ||
591f4cfa TP |
964 | struct mvpp2_queue_vector { |
965 | int irq; | |
966 | struct napi_struct napi; | |
967 | enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type; | |
968 | int sw_thread_id; | |
969 | u16 sw_thread_mask; | |
970 | int first_rxq; | |
971 | int nrxqs; | |
972 | u32 pending_cause_rx; | |
973 | struct mvpp2_port *port; | |
974 | }; | |
975 | ||
3f518509 MW |
976 | struct mvpp2_port { |
977 | u8 id; | |
978 | ||
a786841d TP |
979 | /* Index of the port from the "group of ports" complex point |
980 | * of view | |
981 | */ | |
982 | int gop_id; | |
983 | ||
fd3651b2 AT |
984 | int link_irq; |
985 | ||
3f518509 MW |
986 | struct mvpp2 *priv; |
987 | ||
24812221 MW |
988 | /* Firmware node associated to the port */ |
989 | struct fwnode_handle *fwnode; | |
990 | ||
3f518509 MW |
991 | /* Per-port registers' base address */ |
992 | void __iomem *base; | |
118d6298 | 993 | void __iomem *stats_base; |
3f518509 MW |
994 | |
995 | struct mvpp2_rx_queue **rxqs; | |
09f83975 | 996 | unsigned int nrxqs; |
3f518509 | 997 | struct mvpp2_tx_queue **txqs; |
09f83975 | 998 | unsigned int ntxqs; |
3f518509 MW |
999 | struct net_device *dev; |
1000 | ||
1001 | int pkt_size; | |
1002 | ||
edc660fa MW |
1003 | /* Per-CPU port control */ |
1004 | struct mvpp2_port_pcpu __percpu *pcpu; | |
1005 | ||
3f518509 MW |
1006 | /* Flags */ |
1007 | unsigned long flags; | |
1008 | ||
1009 | u16 tx_ring_size; | |
1010 | u16 rx_ring_size; | |
1011 | struct mvpp2_pcpu_stats __percpu *stats; | |
118d6298 | 1012 | u64 *ethtool_stats; |
3f518509 | 1013 | |
e5c500eb MR |
1014 | /* Per-port work and its lock to gather hardware statistics */ |
1015 | struct mutex gather_stats_lock; | |
1016 | struct delayed_work stats_work; | |
1017 | ||
3f518509 MW |
1018 | phy_interface_t phy_interface; |
1019 | struct device_node *phy_node; | |
542897d9 | 1020 | struct phy *comphy; |
3f518509 MW |
1021 | unsigned int link; |
1022 | unsigned int duplex; | |
1023 | unsigned int speed; | |
1024 | ||
1025 | struct mvpp2_bm_pool *pool_long; | |
1026 | struct mvpp2_bm_pool *pool_short; | |
1027 | ||
1028 | /* Index of first port's physical RXQ */ | |
1029 | u8 first_rxq; | |
591f4cfa TP |
1030 | |
1031 | struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS]; | |
1032 | unsigned int nqvecs; | |
213f428f TP |
1033 | bool has_tx_irqs; |
1034 | ||
1035 | u32 tx_time_coal; | |
3f518509 MW |
1036 | }; |
1037 | ||
1038 | /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the | |
1039 | * layout of the transmit and reception DMA descriptors, and their | |
1040 | * layout is therefore defined by the hardware design | |
1041 | */ | |
1042 | ||
1043 | #define MVPP2_TXD_L3_OFF_SHIFT 0 | |
1044 | #define MVPP2_TXD_IP_HLEN_SHIFT 8 | |
1045 | #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) | |
1046 | #define MVPP2_TXD_L4_CSUM_NOT BIT(14) | |
1047 | #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) | |
1048 | #define MVPP2_TXD_PADDING_DISABLE BIT(23) | |
1049 | #define MVPP2_TXD_L4_UDP BIT(24) | |
1050 | #define MVPP2_TXD_L3_IP6 BIT(26) | |
1051 | #define MVPP2_TXD_L_DESC BIT(28) | |
1052 | #define MVPP2_TXD_F_DESC BIT(29) | |
1053 | ||
1054 | #define MVPP2_RXD_ERR_SUMMARY BIT(15) | |
1055 | #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) | |
1056 | #define MVPP2_RXD_ERR_CRC 0x0 | |
1057 | #define MVPP2_RXD_ERR_OVERRUN BIT(13) | |
1058 | #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) | |
1059 | #define MVPP2_RXD_BM_POOL_ID_OFFS 16 | |
1060 | #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) | |
1061 | #define MVPP2_RXD_HWF_SYNC BIT(21) | |
1062 | #define MVPP2_RXD_L4_CSUM_OK BIT(22) | |
1063 | #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) | |
1064 | #define MVPP2_RXD_L4_TCP BIT(25) | |
1065 | #define MVPP2_RXD_L4_UDP BIT(26) | |
1066 | #define MVPP2_RXD_L3_IP4 BIT(28) | |
1067 | #define MVPP2_RXD_L3_IP6 BIT(30) | |
1068 | #define MVPP2_RXD_BUF_HDR BIT(31) | |
1069 | ||
054f6372 TP |
1070 | /* HW TX descriptor for PPv2.1 */ |
1071 | struct mvpp21_tx_desc { | |
3f518509 MW |
1072 | u32 command; /* Options used by HW for packet transmitting.*/ |
1073 | u8 packet_offset; /* the offset from the buffer beginning */ | |
1074 | u8 phys_txq; /* destination queue ID */ | |
1075 | u16 data_size; /* data size of transmitted packet in bytes */ | |
20396136 | 1076 | u32 buf_dma_addr; /* physical addr of transmitted buffer */ |
3f518509 MW |
1077 | u32 buf_cookie; /* cookie for access to TX buffer in tx path */ |
1078 | u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ | |
1079 | u32 reserved2; /* reserved (for future use) */ | |
1080 | }; | |
1081 | ||
054f6372 TP |
1082 | /* HW RX descriptor for PPv2.1 */ |
1083 | struct mvpp21_rx_desc { | |
3f518509 MW |
1084 | u32 status; /* info about received packet */ |
1085 | u16 reserved1; /* parser_info (for future use, PnC) */ | |
1086 | u16 data_size; /* size of received packet in bytes */ | |
20396136 | 1087 | u32 buf_dma_addr; /* physical address of the buffer */ |
3f518509 MW |
1088 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
1089 | u16 reserved2; /* gem_port_id (for future use, PON) */ | |
1090 | u16 reserved3; /* csum_l4 (for future use, PnC) */ | |
1091 | u8 reserved4; /* bm_qset (for future use, BM) */ | |
1092 | u8 reserved5; | |
1093 | u16 reserved6; /* classify_info (for future use, PnC) */ | |
1094 | u32 reserved7; /* flow_id (for future use, PnC) */ | |
1095 | u32 reserved8; | |
1096 | }; | |
1097 | ||
e7c5359f TP |
1098 | /* HW TX descriptor for PPv2.2 */ |
1099 | struct mvpp22_tx_desc { | |
1100 | u32 command; | |
1101 | u8 packet_offset; | |
1102 | u8 phys_txq; | |
1103 | u16 data_size; | |
1104 | u64 reserved1; | |
1105 | u64 buf_dma_addr_ptp; | |
1106 | u64 buf_cookie_misc; | |
1107 | }; | |
1108 | ||
1109 | /* HW RX descriptor for PPv2.2 */ | |
1110 | struct mvpp22_rx_desc { | |
1111 | u32 status; | |
1112 | u16 reserved1; | |
1113 | u16 data_size; | |
1114 | u32 reserved2; | |
1115 | u32 reserved3; | |
1116 | u64 buf_dma_addr_key_hash; | |
1117 | u64 buf_cookie_misc; | |
1118 | }; | |
1119 | ||
054f6372 TP |
1120 | /* Opaque type used by the driver to manipulate the HW TX and RX |
1121 | * descriptors | |
1122 | */ | |
1123 | struct mvpp2_tx_desc { | |
1124 | union { | |
1125 | struct mvpp21_tx_desc pp21; | |
e7c5359f | 1126 | struct mvpp22_tx_desc pp22; |
054f6372 TP |
1127 | }; |
1128 | }; | |
1129 | ||
1130 | struct mvpp2_rx_desc { | |
1131 | union { | |
1132 | struct mvpp21_rx_desc pp21; | |
e7c5359f | 1133 | struct mvpp22_rx_desc pp22; |
054f6372 TP |
1134 | }; |
1135 | }; | |
1136 | ||
8354491c TP |
1137 | struct mvpp2_txq_pcpu_buf { |
1138 | /* Transmitted SKB */ | |
1139 | struct sk_buff *skb; | |
1140 | ||
1141 | /* Physical address of transmitted buffer */ | |
20396136 | 1142 | dma_addr_t dma; |
8354491c TP |
1143 | |
1144 | /* Size transmitted */ | |
1145 | size_t size; | |
1146 | }; | |
1147 | ||
3f518509 MW |
1148 | /* Per-CPU Tx queue control */ |
1149 | struct mvpp2_txq_pcpu { | |
1150 | int cpu; | |
1151 | ||
1152 | /* Number of Tx DMA descriptors in the descriptor ring */ | |
1153 | int size; | |
1154 | ||
1155 | /* Number of currently used Tx DMA descriptor in the | |
1156 | * descriptor ring | |
1157 | */ | |
1158 | int count; | |
1159 | ||
1d17db08 AT |
1160 | int wake_threshold; |
1161 | int stop_threshold; | |
1162 | ||
3f518509 MW |
1163 | /* Number of Tx DMA descriptors reserved for each CPU */ |
1164 | int reserved_num; | |
1165 | ||
8354491c TP |
1166 | /* Infos about transmitted buffers */ |
1167 | struct mvpp2_txq_pcpu_buf *buffs; | |
71ce391d | 1168 | |
3f518509 MW |
1169 | /* Index of last TX DMA descriptor that was inserted */ |
1170 | int txq_put_index; | |
1171 | ||
1172 | /* Index of the TX DMA descriptor to be cleaned up */ | |
1173 | int txq_get_index; | |
186cd4d4 AT |
1174 | |
1175 | /* DMA buffer for TSO headers */ | |
1176 | char *tso_headers; | |
1177 | dma_addr_t tso_headers_dma; | |
3f518509 MW |
1178 | }; |
1179 | ||
1180 | struct mvpp2_tx_queue { | |
1181 | /* Physical number of this Tx queue */ | |
1182 | u8 id; | |
1183 | ||
1184 | /* Logical number of this Tx queue */ | |
1185 | u8 log_id; | |
1186 | ||
1187 | /* Number of Tx DMA descriptors in the descriptor ring */ | |
1188 | int size; | |
1189 | ||
1190 | /* Number of currently used Tx DMA descriptor in the descriptor ring */ | |
1191 | int count; | |
1192 | ||
1193 | /* Per-CPU control of physical Tx queues */ | |
1194 | struct mvpp2_txq_pcpu __percpu *pcpu; | |
1195 | ||
3f518509 MW |
1196 | u32 done_pkts_coal; |
1197 | ||
1198 | /* Virtual address of thex Tx DMA descriptors array */ | |
1199 | struct mvpp2_tx_desc *descs; | |
1200 | ||
1201 | /* DMA address of the Tx DMA descriptors array */ | |
20396136 | 1202 | dma_addr_t descs_dma; |
3f518509 MW |
1203 | |
1204 | /* Index of the last Tx DMA descriptor */ | |
1205 | int last_desc; | |
1206 | ||
1207 | /* Index of the next Tx DMA descriptor to process */ | |
1208 | int next_desc_to_proc; | |
1209 | }; | |
1210 | ||
1211 | struct mvpp2_rx_queue { | |
1212 | /* RX queue number, in the range 0-31 for physical RXQs */ | |
1213 | u8 id; | |
1214 | ||
1215 | /* Num of rx descriptors in the rx descriptor ring */ | |
1216 | int size; | |
1217 | ||
1218 | u32 pkts_coal; | |
1219 | u32 time_coal; | |
1220 | ||
1221 | /* Virtual address of the RX DMA descriptors array */ | |
1222 | struct mvpp2_rx_desc *descs; | |
1223 | ||
1224 | /* DMA address of the RX DMA descriptors array */ | |
20396136 | 1225 | dma_addr_t descs_dma; |
3f518509 MW |
1226 | |
1227 | /* Index of the last RX DMA descriptor */ | |
1228 | int last_desc; | |
1229 | ||
1230 | /* Index of the next RX DMA descriptor to process */ | |
1231 | int next_desc_to_proc; | |
1232 | ||
1233 | /* ID of port to which physical RXQ is mapped */ | |
1234 | int port; | |
1235 | ||
1236 | /* Port's logic RXQ number to which physical RXQ is mapped */ | |
1237 | int logic_rxq; | |
1238 | }; | |
1239 | ||
1240 | union mvpp2_prs_tcam_entry { | |
1241 | u32 word[MVPP2_PRS_TCAM_WORDS]; | |
1242 | u8 byte[MVPP2_PRS_TCAM_WORDS * 4]; | |
1243 | }; | |
1244 | ||
1245 | union mvpp2_prs_sram_entry { | |
1246 | u32 word[MVPP2_PRS_SRAM_WORDS]; | |
1247 | u8 byte[MVPP2_PRS_SRAM_WORDS * 4]; | |
1248 | }; | |
1249 | ||
1250 | struct mvpp2_prs_entry { | |
1251 | u32 index; | |
1252 | union mvpp2_prs_tcam_entry tcam; | |
1253 | union mvpp2_prs_sram_entry sram; | |
1254 | }; | |
1255 | ||
1256 | struct mvpp2_prs_shadow { | |
1257 | bool valid; | |
1258 | bool finish; | |
1259 | ||
1260 | /* Lookup ID */ | |
1261 | int lu; | |
1262 | ||
1263 | /* User defined offset */ | |
1264 | int udf; | |
1265 | ||
1266 | /* Result info */ | |
1267 | u32 ri; | |
1268 | u32 ri_mask; | |
1269 | }; | |
1270 | ||
1271 | struct mvpp2_cls_flow_entry { | |
1272 | u32 index; | |
1273 | u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS]; | |
1274 | }; | |
1275 | ||
1276 | struct mvpp2_cls_lookup_entry { | |
1277 | u32 lkpid; | |
1278 | u32 way; | |
1279 | u32 data; | |
1280 | }; | |
1281 | ||
1282 | struct mvpp2_bm_pool { | |
1283 | /* Pool number in the range 0-7 */ | |
1284 | int id; | |
3f518509 MW |
1285 | |
1286 | /* Buffer Pointers Pool External (BPPE) size */ | |
1287 | int size; | |
d01524d8 TP |
1288 | /* BPPE size in bytes */ |
1289 | int size_bytes; | |
3f518509 MW |
1290 | /* Number of buffers for this pool */ |
1291 | int buf_num; | |
1292 | /* Pool buffer size */ | |
1293 | int buf_size; | |
1294 | /* Packet size */ | |
1295 | int pkt_size; | |
0e037281 | 1296 | int frag_size; |
3f518509 MW |
1297 | |
1298 | /* BPPE virtual base address */ | |
1299 | u32 *virt_addr; | |
20396136 TP |
1300 | /* BPPE DMA base address */ |
1301 | dma_addr_t dma_addr; | |
3f518509 MW |
1302 | |
1303 | /* Ports using BM pool */ | |
1304 | u32 port_map; | |
3f518509 MW |
1305 | }; |
1306 | ||
20920267 AT |
1307 | #define IS_TSO_HEADER(txq_pcpu, addr) \ |
1308 | ((addr) >= (txq_pcpu)->tso_headers_dma && \ | |
1309 | (addr) < (txq_pcpu)->tso_headers_dma + \ | |
1310 | (txq_pcpu)->size * TSO_HEADER_SIZE) | |
1311 | ||
213f428f TP |
1312 | /* Queue modes */ |
1313 | #define MVPP2_QDIST_SINGLE_MODE 0 | |
1314 | #define MVPP2_QDIST_MULTI_MODE 1 | |
1315 | ||
1316 | static int queue_mode = MVPP2_QDIST_SINGLE_MODE; | |
1317 | ||
1318 | module_param(queue_mode, int, 0444); | |
1319 | MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); | |
1320 | ||
3f518509 MW |
1321 | #define MVPP2_DRIVER_NAME "mvpp2" |
1322 | #define MVPP2_DRIVER_VERSION "1.0" | |
1323 | ||
1324 | /* Utility/helper methods */ | |
1325 | ||
1326 | static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) | |
1327 | { | |
df089aa0 | 1328 | writel(data, priv->swth_base[0] + offset); |
3f518509 MW |
1329 | } |
1330 | ||
1331 | static u32 mvpp2_read(struct mvpp2 *priv, u32 offset) | |
1332 | { | |
df089aa0 | 1333 | return readl(priv->swth_base[0] + offset); |
a786841d TP |
1334 | } |
1335 | ||
1336 | /* These accessors should be used to access: | |
1337 | * | |
1338 | * - per-CPU registers, where each CPU has its own copy of the | |
1339 | * register. | |
1340 | * | |
1341 | * MVPP2_BM_VIRT_ALLOC_REG | |
1342 | * MVPP2_BM_ADDR_HIGH_ALLOC | |
1343 | * MVPP22_BM_ADDR_HIGH_RLS_REG | |
1344 | * MVPP2_BM_VIRT_RLS_REG | |
1345 | * MVPP2_ISR_RX_TX_CAUSE_REG | |
1346 | * MVPP2_ISR_RX_TX_MASK_REG | |
1347 | * MVPP2_TXQ_NUM_REG | |
1348 | * MVPP2_AGGR_TXQ_UPDATE_REG | |
1349 | * MVPP2_TXQ_RSVD_REQ_REG | |
1350 | * MVPP2_TXQ_RSVD_RSLT_REG | |
1351 | * MVPP2_TXQ_SENT_REG | |
1352 | * MVPP2_RXQ_NUM_REG | |
1353 | * | |
1354 | * - global registers that must be accessed through a specific CPU | |
1355 | * window, because they are related to an access to a per-CPU | |
1356 | * register | |
1357 | * | |
1358 | * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) | |
1359 | * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) | |
1360 | * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) | |
1361 | * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) | |
1362 | * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) | |
1363 | * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) | |
1364 | * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) | |
1365 | * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) | |
1366 | * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) | |
1367 | * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) | |
1368 | * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) | |
1369 | * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) | |
1370 | * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) | |
1371 | */ | |
1372 | static void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, | |
1373 | u32 offset, u32 data) | |
1374 | { | |
df089aa0 | 1375 | writel(data, priv->swth_base[cpu] + offset); |
a786841d TP |
1376 | } |
1377 | ||
1378 | static u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, | |
1379 | u32 offset) | |
1380 | { | |
df089aa0 | 1381 | return readl(priv->swth_base[cpu] + offset); |
3f518509 MW |
1382 | } |
1383 | ||
ac3dd277 TP |
1384 | static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, |
1385 | struct mvpp2_tx_desc *tx_desc) | |
1386 | { | |
e7c5359f TP |
1387 | if (port->priv->hw_version == MVPP21) |
1388 | return tx_desc->pp21.buf_dma_addr; | |
1389 | else | |
1390 | return tx_desc->pp22.buf_dma_addr_ptp & GENMASK_ULL(40, 0); | |
ac3dd277 TP |
1391 | } |
1392 | ||
1393 | static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, | |
1394 | struct mvpp2_tx_desc *tx_desc, | |
1395 | dma_addr_t dma_addr) | |
1396 | { | |
6eb5d375 AT |
1397 | dma_addr_t addr, offset; |
1398 | ||
1399 | addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; | |
1400 | offset = dma_addr & MVPP2_TX_DESC_ALIGN; | |
1401 | ||
e7c5359f | 1402 | if (port->priv->hw_version == MVPP21) { |
6eb5d375 AT |
1403 | tx_desc->pp21.buf_dma_addr = addr; |
1404 | tx_desc->pp21.packet_offset = offset; | |
e7c5359f | 1405 | } else { |
6eb5d375 | 1406 | u64 val = (u64)addr; |
e7c5359f TP |
1407 | |
1408 | tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0); | |
1409 | tx_desc->pp22.buf_dma_addr_ptp |= val; | |
6eb5d375 | 1410 | tx_desc->pp22.packet_offset = offset; |
e7c5359f | 1411 | } |
ac3dd277 TP |
1412 | } |
1413 | ||
1414 | static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, | |
1415 | struct mvpp2_tx_desc *tx_desc) | |
1416 | { | |
e7c5359f TP |
1417 | if (port->priv->hw_version == MVPP21) |
1418 | return tx_desc->pp21.data_size; | |
1419 | else | |
1420 | return tx_desc->pp22.data_size; | |
ac3dd277 TP |
1421 | } |
1422 | ||
1423 | static void mvpp2_txdesc_size_set(struct mvpp2_port *port, | |
1424 | struct mvpp2_tx_desc *tx_desc, | |
1425 | size_t size) | |
1426 | { | |
e7c5359f TP |
1427 | if (port->priv->hw_version == MVPP21) |
1428 | tx_desc->pp21.data_size = size; | |
1429 | else | |
1430 | tx_desc->pp22.data_size = size; | |
ac3dd277 TP |
1431 | } |
1432 | ||
1433 | static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, | |
1434 | struct mvpp2_tx_desc *tx_desc, | |
1435 | unsigned int txq) | |
1436 | { | |
e7c5359f TP |
1437 | if (port->priv->hw_version == MVPP21) |
1438 | tx_desc->pp21.phys_txq = txq; | |
1439 | else | |
1440 | tx_desc->pp22.phys_txq = txq; | |
ac3dd277 TP |
1441 | } |
1442 | ||
1443 | static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, | |
1444 | struct mvpp2_tx_desc *tx_desc, | |
1445 | unsigned int command) | |
1446 | { | |
e7c5359f TP |
1447 | if (port->priv->hw_version == MVPP21) |
1448 | tx_desc->pp21.command = command; | |
1449 | else | |
1450 | tx_desc->pp22.command = command; | |
ac3dd277 TP |
1451 | } |
1452 | ||
ac3dd277 TP |
1453 | static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, |
1454 | struct mvpp2_tx_desc *tx_desc) | |
1455 | { | |
e7c5359f TP |
1456 | if (port->priv->hw_version == MVPP21) |
1457 | return tx_desc->pp21.packet_offset; | |
1458 | else | |
1459 | return tx_desc->pp22.packet_offset; | |
ac3dd277 TP |
1460 | } |
1461 | ||
1462 | static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, | |
1463 | struct mvpp2_rx_desc *rx_desc) | |
1464 | { | |
e7c5359f TP |
1465 | if (port->priv->hw_version == MVPP21) |
1466 | return rx_desc->pp21.buf_dma_addr; | |
1467 | else | |
1468 | return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0); | |
ac3dd277 TP |
1469 | } |
1470 | ||
1471 | static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, | |
1472 | struct mvpp2_rx_desc *rx_desc) | |
1473 | { | |
e7c5359f TP |
1474 | if (port->priv->hw_version == MVPP21) |
1475 | return rx_desc->pp21.buf_cookie; | |
1476 | else | |
1477 | return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0); | |
ac3dd277 TP |
1478 | } |
1479 | ||
1480 | static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, | |
1481 | struct mvpp2_rx_desc *rx_desc) | |
1482 | { | |
e7c5359f TP |
1483 | if (port->priv->hw_version == MVPP21) |
1484 | return rx_desc->pp21.data_size; | |
1485 | else | |
1486 | return rx_desc->pp22.data_size; | |
ac3dd277 TP |
1487 | } |
1488 | ||
1489 | static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, | |
1490 | struct mvpp2_rx_desc *rx_desc) | |
1491 | { | |
e7c5359f TP |
1492 | if (port->priv->hw_version == MVPP21) |
1493 | return rx_desc->pp21.status; | |
1494 | else | |
1495 | return rx_desc->pp22.status; | |
ac3dd277 TP |
1496 | } |
1497 | ||
3f518509 MW |
1498 | static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) |
1499 | { | |
1500 | txq_pcpu->txq_get_index++; | |
1501 | if (txq_pcpu->txq_get_index == txq_pcpu->size) | |
1502 | txq_pcpu->txq_get_index = 0; | |
1503 | } | |
1504 | ||
ac3dd277 TP |
1505 | static void mvpp2_txq_inc_put(struct mvpp2_port *port, |
1506 | struct mvpp2_txq_pcpu *txq_pcpu, | |
71ce391d MW |
1507 | struct sk_buff *skb, |
1508 | struct mvpp2_tx_desc *tx_desc) | |
3f518509 | 1509 | { |
8354491c TP |
1510 | struct mvpp2_txq_pcpu_buf *tx_buf = |
1511 | txq_pcpu->buffs + txq_pcpu->txq_put_index; | |
1512 | tx_buf->skb = skb; | |
ac3dd277 TP |
1513 | tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); |
1514 | tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + | |
1515 | mvpp2_txdesc_offset_get(port, tx_desc); | |
3f518509 MW |
1516 | txq_pcpu->txq_put_index++; |
1517 | if (txq_pcpu->txq_put_index == txq_pcpu->size) | |
1518 | txq_pcpu->txq_put_index = 0; | |
1519 | } | |
1520 | ||
1521 | /* Get number of physical egress port */ | |
1522 | static inline int mvpp2_egress_port(struct mvpp2_port *port) | |
1523 | { | |
1524 | return MVPP2_MAX_TCONT + port->id; | |
1525 | } | |
1526 | ||
1527 | /* Get number of physical TXQ */ | |
1528 | static inline int mvpp2_txq_phys(int port, int txq) | |
1529 | { | |
1530 | return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; | |
1531 | } | |
1532 | ||
1533 | /* Parser configuration routines */ | |
1534 | ||
1535 | /* Update parser tcam and sram hw entries */ | |
1536 | static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) | |
1537 | { | |
1538 | int i; | |
1539 | ||
1540 | if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) | |
1541 | return -EINVAL; | |
1542 | ||
1543 | /* Clear entry invalidation bit */ | |
1544 | pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; | |
1545 | ||
1546 | /* Write tcam index - indirect access */ | |
1547 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); | |
1548 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
1549 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); | |
1550 | ||
1551 | /* Write sram index - indirect access */ | |
1552 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); | |
1553 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
1554 | mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); | |
1555 | ||
1556 | return 0; | |
1557 | } | |
1558 | ||
1559 | /* Read tcam entry from hw */ | |
1560 | static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) | |
1561 | { | |
1562 | int i; | |
1563 | ||
1564 | if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) | |
1565 | return -EINVAL; | |
1566 | ||
1567 | /* Write tcam index - indirect access */ | |
1568 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); | |
1569 | ||
1570 | pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, | |
1571 | MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD)); | |
1572 | if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) | |
1573 | return MVPP2_PRS_TCAM_ENTRY_INVALID; | |
1574 | ||
1575 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
1576 | pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); | |
1577 | ||
1578 | /* Write sram index - indirect access */ | |
1579 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); | |
1580 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
1581 | pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); | |
1582 | ||
1583 | return 0; | |
1584 | } | |
1585 | ||
1586 | /* Invalidate tcam hw entry */ | |
1587 | static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index) | |
1588 | { | |
1589 | /* Write index - indirect access */ | |
1590 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); | |
1591 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD), | |
1592 | MVPP2_PRS_TCAM_INV_MASK); | |
1593 | } | |
1594 | ||
1595 | /* Enable shadow table entry and set its lookup ID */ | |
1596 | static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu) | |
1597 | { | |
1598 | priv->prs_shadow[index].valid = true; | |
1599 | priv->prs_shadow[index].lu = lu; | |
1600 | } | |
1601 | ||
1602 | /* Update ri fields in shadow table entry */ | |
1603 | static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index, | |
1604 | unsigned int ri, unsigned int ri_mask) | |
1605 | { | |
1606 | priv->prs_shadow[index].ri_mask = ri_mask; | |
1607 | priv->prs_shadow[index].ri = ri; | |
1608 | } | |
1609 | ||
1610 | /* Update lookup field in tcam sw entry */ | |
1611 | static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) | |
1612 | { | |
1613 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE); | |
1614 | ||
1615 | pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; | |
1616 | pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; | |
1617 | } | |
1618 | ||
1619 | /* Update mask for single port in tcam sw entry */ | |
1620 | static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, | |
1621 | unsigned int port, bool add) | |
1622 | { | |
1623 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1624 | ||
1625 | if (add) | |
1626 | pe->tcam.byte[enable_off] &= ~(1 << port); | |
1627 | else | |
1628 | pe->tcam.byte[enable_off] |= 1 << port; | |
1629 | } | |
1630 | ||
1631 | /* Update port map in tcam sw entry */ | |
1632 | static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, | |
1633 | unsigned int ports) | |
1634 | { | |
1635 | unsigned char port_mask = MVPP2_PRS_PORT_MASK; | |
1636 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1637 | ||
1638 | pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; | |
1639 | pe->tcam.byte[enable_off] &= ~port_mask; | |
1640 | pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; | |
1641 | } | |
1642 | ||
1643 | /* Obtain port map from tcam sw entry */ | |
1644 | static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) | |
1645 | { | |
1646 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1647 | ||
1648 | return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; | |
1649 | } | |
1650 | ||
1651 | /* Set byte of data and its enable bits in tcam sw entry */ | |
1652 | static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, | |
1653 | unsigned int offs, unsigned char byte, | |
1654 | unsigned char enable) | |
1655 | { | |
1656 | pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; | |
1657 | pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; | |
1658 | } | |
1659 | ||
1660 | /* Get byte of data and its enable bits from tcam sw entry */ | |
1661 | static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, | |
1662 | unsigned int offs, unsigned char *byte, | |
1663 | unsigned char *enable) | |
1664 | { | |
1665 | *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; | |
1666 | *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; | |
1667 | } | |
1668 | ||
1669 | /* Compare tcam data bytes with a pattern */ | |
1670 | static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, | |
1671 | u16 data) | |
1672 | { | |
1673 | int off = MVPP2_PRS_TCAM_DATA_BYTE(offs); | |
1674 | u16 tcam_data; | |
1675 | ||
ef4816f0 | 1676 | tcam_data = (pe->tcam.byte[off + 1] << 8) | pe->tcam.byte[off]; |
3f518509 MW |
1677 | if (tcam_data != data) |
1678 | return false; | |
1679 | return true; | |
1680 | } | |
1681 | ||
1682 | /* Update ai bits in tcam sw entry */ | |
1683 | static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, | |
1684 | unsigned int bits, unsigned int enable) | |
1685 | { | |
1686 | int i, ai_idx = MVPP2_PRS_TCAM_AI_BYTE; | |
1687 | ||
1688 | for (i = 0; i < MVPP2_PRS_AI_BITS; i++) { | |
1689 | ||
1690 | if (!(enable & BIT(i))) | |
1691 | continue; | |
1692 | ||
1693 | if (bits & BIT(i)) | |
1694 | pe->tcam.byte[ai_idx] |= 1 << i; | |
1695 | else | |
1696 | pe->tcam.byte[ai_idx] &= ~(1 << i); | |
1697 | } | |
1698 | ||
1699 | pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable; | |
1700 | } | |
1701 | ||
1702 | /* Get ai bits from tcam sw entry */ | |
1703 | static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) | |
1704 | { | |
1705 | return pe->tcam.byte[MVPP2_PRS_TCAM_AI_BYTE]; | |
1706 | } | |
1707 | ||
1708 | /* Set ethertype in tcam sw entry */ | |
1709 | static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, | |
1710 | unsigned short ethertype) | |
1711 | { | |
1712 | mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); | |
1713 | mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); | |
1714 | } | |
1715 | ||
56beda3d MC |
1716 | /* Set vid in tcam sw entry */ |
1717 | static void mvpp2_prs_match_vid(struct mvpp2_prs_entry *pe, int offset, | |
1718 | unsigned short vid) | |
1719 | { | |
1720 | mvpp2_prs_tcam_data_byte_set(pe, offset + 0, (vid & 0xf00) >> 8, 0xf); | |
1721 | mvpp2_prs_tcam_data_byte_set(pe, offset + 1, vid & 0xff, 0xff); | |
1722 | } | |
1723 | ||
3f518509 MW |
1724 | /* Set bits in sram sw entry */ |
1725 | static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, | |
1726 | int val) | |
1727 | { | |
1728 | pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); | |
1729 | } | |
1730 | ||
1731 | /* Clear bits in sram sw entry */ | |
1732 | static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, | |
1733 | int val) | |
1734 | { | |
1735 | pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); | |
1736 | } | |
1737 | ||
1738 | /* Update ri bits in sram sw entry */ | |
1739 | static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, | |
1740 | unsigned int bits, unsigned int mask) | |
1741 | { | |
1742 | unsigned int i; | |
1743 | ||
1744 | for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) { | |
1745 | int ri_off = MVPP2_PRS_SRAM_RI_OFFS; | |
1746 | ||
1747 | if (!(mask & BIT(i))) | |
1748 | continue; | |
1749 | ||
1750 | if (bits & BIT(i)) | |
1751 | mvpp2_prs_sram_bits_set(pe, ri_off + i, 1); | |
1752 | else | |
1753 | mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1); | |
1754 | ||
1755 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); | |
1756 | } | |
1757 | } | |
1758 | ||
1759 | /* Obtain ri bits from sram sw entry */ | |
1760 | static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) | |
1761 | { | |
1762 | return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD]; | |
1763 | } | |
1764 | ||
1765 | /* Update ai bits in sram sw entry */ | |
1766 | static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, | |
1767 | unsigned int bits, unsigned int mask) | |
1768 | { | |
1769 | unsigned int i; | |
1770 | int ai_off = MVPP2_PRS_SRAM_AI_OFFS; | |
1771 | ||
1772 | for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) { | |
1773 | ||
1774 | if (!(mask & BIT(i))) | |
1775 | continue; | |
1776 | ||
1777 | if (bits & BIT(i)) | |
1778 | mvpp2_prs_sram_bits_set(pe, ai_off + i, 1); | |
1779 | else | |
1780 | mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1); | |
1781 | ||
1782 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); | |
1783 | } | |
1784 | } | |
1785 | ||
1786 | /* Read ai bits from sram sw entry */ | |
1787 | static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) | |
1788 | { | |
1789 | u8 bits; | |
1790 | int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS); | |
1791 | int ai_en_off = ai_off + 1; | |
1792 | int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8; | |
1793 | ||
1794 | bits = (pe->sram.byte[ai_off] >> ai_shift) | | |
1795 | (pe->sram.byte[ai_en_off] << (8 - ai_shift)); | |
1796 | ||
1797 | return bits; | |
1798 | } | |
1799 | ||
1800 | /* In sram sw entry set lookup ID field of the tcam key to be used in the next | |
1801 | * lookup interation | |
1802 | */ | |
1803 | static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, | |
1804 | unsigned int lu) | |
1805 | { | |
1806 | int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS; | |
1807 | ||
1808 | mvpp2_prs_sram_bits_clear(pe, sram_next_off, | |
1809 | MVPP2_PRS_SRAM_NEXT_LU_MASK); | |
1810 | mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); | |
1811 | } | |
1812 | ||
1813 | /* In the sram sw entry set sign and value of the next lookup offset | |
1814 | * and the offset value generated to the classifier | |
1815 | */ | |
1816 | static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, | |
1817 | unsigned int op) | |
1818 | { | |
1819 | /* Set sign */ | |
1820 | if (shift < 0) { | |
1821 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); | |
1822 | shift = 0 - shift; | |
1823 | } else { | |
1824 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); | |
1825 | } | |
1826 | ||
1827 | /* Set value */ | |
1828 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = | |
1829 | (unsigned char)shift; | |
1830 | ||
1831 | /* Reset and set operation */ | |
1832 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, | |
1833 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK); | |
1834 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); | |
1835 | ||
1836 | /* Set base offset as current */ | |
1837 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); | |
1838 | } | |
1839 | ||
1840 | /* In the sram sw entry set sign and value of the user defined offset | |
1841 | * generated to the classifier | |
1842 | */ | |
1843 | static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, | |
1844 | unsigned int type, int offset, | |
1845 | unsigned int op) | |
1846 | { | |
1847 | /* Set sign */ | |
1848 | if (offset < 0) { | |
1849 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); | |
1850 | offset = 0 - offset; | |
1851 | } else { | |
1852 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); | |
1853 | } | |
1854 | ||
1855 | /* Set value */ | |
1856 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, | |
1857 | MVPP2_PRS_SRAM_UDF_MASK); | |
1858 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset); | |
1859 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + | |
1860 | MVPP2_PRS_SRAM_UDF_BITS)] &= | |
1861 | ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); | |
1862 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + | |
1863 | MVPP2_PRS_SRAM_UDF_BITS)] |= | |
1864 | (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); | |
1865 | ||
1866 | /* Set offset type */ | |
1867 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, | |
1868 | MVPP2_PRS_SRAM_UDF_TYPE_MASK); | |
1869 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); | |
1870 | ||
1871 | /* Set offset operation */ | |
1872 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, | |
1873 | MVPP2_PRS_SRAM_OP_SEL_UDF_MASK); | |
1874 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op); | |
1875 | ||
1876 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + | |
1877 | MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &= | |
1878 | ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >> | |
1879 | (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); | |
1880 | ||
1881 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + | |
1882 | MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |= | |
1883 | (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); | |
1884 | ||
1885 | /* Set base offset as current */ | |
1886 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); | |
1887 | } | |
1888 | ||
1889 | /* Find parser flow entry */ | |
1890 | static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow) | |
1891 | { | |
1892 | struct mvpp2_prs_entry *pe; | |
1893 | int tid; | |
1894 | ||
1895 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
1896 | if (!pe) | |
1897 | return NULL; | |
1898 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); | |
1899 | ||
1900 | /* Go through the all entires with MVPP2_PRS_LU_FLOWS */ | |
1901 | for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) { | |
1902 | u8 bits; | |
1903 | ||
1904 | if (!priv->prs_shadow[tid].valid || | |
1905 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS) | |
1906 | continue; | |
1907 | ||
1908 | pe->index = tid; | |
1909 | mvpp2_prs_hw_read(priv, pe); | |
1910 | bits = mvpp2_prs_sram_ai_get(pe); | |
1911 | ||
1912 | /* Sram store classification lookup ID in AI bits [5:0] */ | |
1913 | if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow) | |
1914 | return pe; | |
1915 | } | |
1916 | kfree(pe); | |
1917 | ||
1918 | return NULL; | |
1919 | } | |
1920 | ||
1921 | /* Return first free tcam index, seeking from start to end */ | |
1922 | static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start, | |
1923 | unsigned char end) | |
1924 | { | |
1925 | int tid; | |
1926 | ||
1927 | if (start > end) | |
1928 | swap(start, end); | |
1929 | ||
1930 | if (end >= MVPP2_PRS_TCAM_SRAM_SIZE) | |
1931 | end = MVPP2_PRS_TCAM_SRAM_SIZE - 1; | |
1932 | ||
1933 | for (tid = start; tid <= end; tid++) { | |
1934 | if (!priv->prs_shadow[tid].valid) | |
1935 | return tid; | |
1936 | } | |
1937 | ||
1938 | return -EINVAL; | |
1939 | } | |
1940 | ||
1941 | /* Enable/disable dropping all mac da's */ | |
1942 | static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) | |
1943 | { | |
1944 | struct mvpp2_prs_entry pe; | |
1945 | ||
1946 | if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) { | |
1947 | /* Entry exist - update port only */ | |
1948 | pe.index = MVPP2_PE_DROP_ALL; | |
1949 | mvpp2_prs_hw_read(priv, &pe); | |
1950 | } else { | |
1951 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1952 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1953 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
1954 | pe.index = MVPP2_PE_DROP_ALL; | |
1955 | ||
1956 | /* Non-promiscuous mode for all ports - DROP unknown packets */ | |
1957 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, | |
1958 | MVPP2_PRS_RI_DROP_MASK); | |
1959 | ||
1960 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
1961 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
1962 | ||
1963 | /* Update shadow table */ | |
1964 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
1965 | ||
1966 | /* Mask all ports */ | |
1967 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
1968 | } | |
1969 | ||
1970 | /* Update port mask */ | |
1971 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
1972 | ||
1973 | mvpp2_prs_hw_write(priv, &pe); | |
1974 | } | |
1975 | ||
1976 | /* Set port to promiscuous mode */ | |
1977 | static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add) | |
1978 | { | |
1979 | struct mvpp2_prs_entry pe; | |
1980 | ||
dbedd44e | 1981 | /* Promiscuous mode - Accept unknown packets */ |
3f518509 MW |
1982 | |
1983 | if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) { | |
1984 | /* Entry exist - update port only */ | |
1985 | pe.index = MVPP2_PE_MAC_PROMISCUOUS; | |
1986 | mvpp2_prs_hw_read(priv, &pe); | |
1987 | } else { | |
1988 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1989 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1990 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
1991 | pe.index = MVPP2_PE_MAC_PROMISCUOUS; | |
1992 | ||
1993 | /* Continue - set next lookup */ | |
1994 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); | |
1995 | ||
1996 | /* Set result info bits */ | |
1997 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, | |
1998 | MVPP2_PRS_RI_L2_CAST_MASK); | |
1999 | ||
2000 | /* Shift to ethertype */ | |
2001 | mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, | |
2002 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2003 | ||
2004 | /* Mask all ports */ | |
2005 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
2006 | ||
2007 | /* Update shadow table */ | |
2008 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2009 | } | |
2010 | ||
2011 | /* Update port mask */ | |
2012 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
2013 | ||
2014 | mvpp2_prs_hw_write(priv, &pe); | |
2015 | } | |
2016 | ||
2017 | /* Accept multicast */ | |
2018 | static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index, | |
2019 | bool add) | |
2020 | { | |
2021 | struct mvpp2_prs_entry pe; | |
2022 | unsigned char da_mc; | |
2023 | ||
2024 | /* Ethernet multicast address first byte is | |
2025 | * 0x01 for IPv4 and 0x33 for IPv6 | |
2026 | */ | |
2027 | da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33; | |
2028 | ||
2029 | if (priv->prs_shadow[index].valid) { | |
2030 | /* Entry exist - update port only */ | |
2031 | pe.index = index; | |
2032 | mvpp2_prs_hw_read(priv, &pe); | |
2033 | } else { | |
2034 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 2035 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2036 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
2037 | pe.index = index; | |
2038 | ||
2039 | /* Continue - set next lookup */ | |
2040 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); | |
2041 | ||
2042 | /* Set result info bits */ | |
2043 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST, | |
2044 | MVPP2_PRS_RI_L2_CAST_MASK); | |
2045 | ||
2046 | /* Update tcam entry data first byte */ | |
2047 | mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff); | |
2048 | ||
2049 | /* Shift to ethertype */ | |
2050 | mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, | |
2051 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2052 | ||
2053 | /* Mask all ports */ | |
2054 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
2055 | ||
2056 | /* Update shadow table */ | |
2057 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2058 | } | |
2059 | ||
2060 | /* Update port mask */ | |
2061 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
2062 | ||
2063 | mvpp2_prs_hw_write(priv, &pe); | |
2064 | } | |
2065 | ||
2066 | /* Set entry for dsa packets */ | |
2067 | static void mvpp2_prs_dsa_tag_set(struct mvpp2 *priv, int port, bool add, | |
2068 | bool tagged, bool extend) | |
2069 | { | |
2070 | struct mvpp2_prs_entry pe; | |
2071 | int tid, shift; | |
2072 | ||
2073 | if (extend) { | |
2074 | tid = tagged ? MVPP2_PE_EDSA_TAGGED : MVPP2_PE_EDSA_UNTAGGED; | |
2075 | shift = 8; | |
2076 | } else { | |
2077 | tid = tagged ? MVPP2_PE_DSA_TAGGED : MVPP2_PE_DSA_UNTAGGED; | |
2078 | shift = 4; | |
2079 | } | |
2080 | ||
2081 | if (priv->prs_shadow[tid].valid) { | |
2082 | /* Entry exist - update port only */ | |
2083 | pe.index = tid; | |
2084 | mvpp2_prs_hw_read(priv, &pe); | |
2085 | } else { | |
2086 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 2087 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2088 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
2089 | pe.index = tid; | |
2090 | ||
3f518509 MW |
2091 | /* Update shadow table */ |
2092 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); | |
2093 | ||
2094 | if (tagged) { | |
2095 | /* Set tagged bit in DSA tag */ | |
2096 | mvpp2_prs_tcam_data_byte_set(&pe, 0, | |
56beda3d MC |
2097 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT, |
2098 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT); | |
2099 | ||
2100 | /* Set ai bits for next iteration */ | |
2101 | if (extend) | |
2102 | mvpp2_prs_sram_ai_update(&pe, 1, | |
2103 | MVPP2_PRS_SRAM_AI_MASK); | |
2104 | else | |
2105 | mvpp2_prs_sram_ai_update(&pe, 0, | |
2106 | MVPP2_PRS_SRAM_AI_MASK); | |
2107 | ||
2108 | /* If packet is tagged continue check vid filtering */ | |
2109 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); | |
3f518509 | 2110 | } else { |
56beda3d MC |
2111 | /* Shift 4 bytes for DSA tag or 8 bytes for EDSA tag*/ |
2112 | mvpp2_prs_sram_shift_set(&pe, shift, | |
2113 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2114 | ||
3f518509 MW |
2115 | /* Set result info bits to 'no vlans' */ |
2116 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
2117 | MVPP2_PRS_RI_VLAN_MASK); | |
2118 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2119 | } | |
2120 | ||
2121 | /* Mask all ports */ | |
2122 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
2123 | } | |
2124 | ||
2125 | /* Update port mask */ | |
2126 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
2127 | ||
2128 | mvpp2_prs_hw_write(priv, &pe); | |
2129 | } | |
2130 | ||
2131 | /* Set entry for dsa ethertype */ | |
2132 | static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2 *priv, int port, | |
2133 | bool add, bool tagged, bool extend) | |
2134 | { | |
2135 | struct mvpp2_prs_entry pe; | |
2136 | int tid, shift, port_mask; | |
2137 | ||
2138 | if (extend) { | |
2139 | tid = tagged ? MVPP2_PE_ETYPE_EDSA_TAGGED : | |
2140 | MVPP2_PE_ETYPE_EDSA_UNTAGGED; | |
2141 | port_mask = 0; | |
2142 | shift = 8; | |
2143 | } else { | |
2144 | tid = tagged ? MVPP2_PE_ETYPE_DSA_TAGGED : | |
2145 | MVPP2_PE_ETYPE_DSA_UNTAGGED; | |
2146 | port_mask = MVPP2_PRS_PORT_MASK; | |
2147 | shift = 4; | |
2148 | } | |
2149 | ||
2150 | if (priv->prs_shadow[tid].valid) { | |
2151 | /* Entry exist - update port only */ | |
2152 | pe.index = tid; | |
2153 | mvpp2_prs_hw_read(priv, &pe); | |
2154 | } else { | |
2155 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 2156 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2157 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
2158 | pe.index = tid; | |
2159 | ||
2160 | /* Set ethertype */ | |
2161 | mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); | |
2162 | mvpp2_prs_match_etype(&pe, 2, 0); | |
2163 | ||
2164 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, | |
2165 | MVPP2_PRS_RI_DSA_MASK); | |
2166 | /* Shift ethertype + 2 byte reserved + tag*/ | |
2167 | mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, | |
2168 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2169 | ||
2170 | /* Update shadow table */ | |
2171 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); | |
2172 | ||
2173 | if (tagged) { | |
2174 | /* Set tagged bit in DSA tag */ | |
2175 | mvpp2_prs_tcam_data_byte_set(&pe, | |
2176 | MVPP2_ETH_TYPE_LEN + 2 + 3, | |
2177 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT, | |
2178 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT); | |
2179 | /* Clear all ai bits for next iteration */ | |
2180 | mvpp2_prs_sram_ai_update(&pe, 0, | |
2181 | MVPP2_PRS_SRAM_AI_MASK); | |
2182 | /* If packet is tagged continue check vlans */ | |
2183 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
2184 | } else { | |
2185 | /* Set result info bits to 'no vlans' */ | |
2186 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
2187 | MVPP2_PRS_RI_VLAN_MASK); | |
2188 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2189 | } | |
2190 | /* Mask/unmask all ports, depending on dsa type */ | |
2191 | mvpp2_prs_tcam_port_map_set(&pe, port_mask); | |
2192 | } | |
2193 | ||
2194 | /* Update port mask */ | |
2195 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
2196 | ||
2197 | mvpp2_prs_hw_write(priv, &pe); | |
2198 | } | |
2199 | ||
2200 | /* Search for existing single/triple vlan entry */ | |
2201 | static struct mvpp2_prs_entry *mvpp2_prs_vlan_find(struct mvpp2 *priv, | |
2202 | unsigned short tpid, int ai) | |
2203 | { | |
2204 | struct mvpp2_prs_entry *pe; | |
2205 | int tid; | |
2206 | ||
2207 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2208 | if (!pe) | |
2209 | return NULL; | |
2210 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); | |
2211 | ||
2212 | /* Go through the all entries with MVPP2_PRS_LU_VLAN */ | |
2213 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
2214 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
2215 | unsigned int ri_bits, ai_bits; | |
2216 | bool match; | |
2217 | ||
2218 | if (!priv->prs_shadow[tid].valid || | |
2219 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN) | |
2220 | continue; | |
2221 | ||
2222 | pe->index = tid; | |
2223 | ||
2224 | mvpp2_prs_hw_read(priv, pe); | |
2225 | match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid)); | |
2226 | if (!match) | |
2227 | continue; | |
2228 | ||
2229 | /* Get vlan type */ | |
2230 | ri_bits = mvpp2_prs_sram_ri_get(pe); | |
2231 | ri_bits &= MVPP2_PRS_RI_VLAN_MASK; | |
2232 | ||
2233 | /* Get current ai value from tcam */ | |
2234 | ai_bits = mvpp2_prs_tcam_ai_get(pe); | |
2235 | /* Clear double vlan bit */ | |
2236 | ai_bits &= ~MVPP2_PRS_DBL_VLAN_AI_BIT; | |
2237 | ||
2238 | if (ai != ai_bits) | |
2239 | continue; | |
2240 | ||
2241 | if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE || | |
2242 | ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE) | |
2243 | return pe; | |
2244 | } | |
2245 | kfree(pe); | |
2246 | ||
2247 | return NULL; | |
2248 | } | |
2249 | ||
2250 | /* Add/update single/triple vlan entry */ | |
2251 | static int mvpp2_prs_vlan_add(struct mvpp2 *priv, unsigned short tpid, int ai, | |
2252 | unsigned int port_map) | |
2253 | { | |
2254 | struct mvpp2_prs_entry *pe; | |
2255 | int tid_aux, tid; | |
43737473 | 2256 | int ret = 0; |
3f518509 MW |
2257 | |
2258 | pe = mvpp2_prs_vlan_find(priv, tpid, ai); | |
2259 | ||
2260 | if (!pe) { | |
2261 | /* Create new tcam entry */ | |
2262 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_LAST_FREE_TID, | |
2263 | MVPP2_PE_FIRST_FREE_TID); | |
2264 | if (tid < 0) | |
2265 | return tid; | |
2266 | ||
2267 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2268 | if (!pe) | |
2269 | return -ENOMEM; | |
2270 | ||
2271 | /* Get last double vlan tid */ | |
2272 | for (tid_aux = MVPP2_PE_LAST_FREE_TID; | |
2273 | tid_aux >= MVPP2_PE_FIRST_FREE_TID; tid_aux--) { | |
2274 | unsigned int ri_bits; | |
2275 | ||
2276 | if (!priv->prs_shadow[tid_aux].valid || | |
2277 | priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN) | |
2278 | continue; | |
2279 | ||
2280 | pe->index = tid_aux; | |
2281 | mvpp2_prs_hw_read(priv, pe); | |
2282 | ri_bits = mvpp2_prs_sram_ri_get(pe); | |
2283 | if ((ri_bits & MVPP2_PRS_RI_VLAN_MASK) == | |
2284 | MVPP2_PRS_RI_VLAN_DOUBLE) | |
2285 | break; | |
2286 | } | |
2287 | ||
43737473 SM |
2288 | if (tid <= tid_aux) { |
2289 | ret = -EINVAL; | |
f9fd0e34 | 2290 | goto free_pe; |
43737473 | 2291 | } |
3f518509 | 2292 | |
bd6aaf55 | 2293 | memset(pe, 0, sizeof(*pe)); |
3f518509 MW |
2294 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); |
2295 | pe->index = tid; | |
2296 | ||
2297 | mvpp2_prs_match_etype(pe, 0, tpid); | |
2298 | ||
56beda3d MC |
2299 | /* VLAN tag detected, proceed with VID filtering */ |
2300 | mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_VID); | |
2301 | ||
3f518509 MW |
2302 | /* Clear all ai bits for next iteration */ |
2303 | mvpp2_prs_sram_ai_update(pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2304 | ||
2305 | if (ai == MVPP2_PRS_SINGLE_VLAN_AI) { | |
2306 | mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_SINGLE, | |
2307 | MVPP2_PRS_RI_VLAN_MASK); | |
2308 | } else { | |
2309 | ai |= MVPP2_PRS_DBL_VLAN_AI_BIT; | |
2310 | mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_TRIPLE, | |
2311 | MVPP2_PRS_RI_VLAN_MASK); | |
2312 | } | |
2313 | mvpp2_prs_tcam_ai_update(pe, ai, MVPP2_PRS_SRAM_AI_MASK); | |
2314 | ||
2315 | mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); | |
2316 | } | |
2317 | /* Update ports' mask */ | |
2318 | mvpp2_prs_tcam_port_map_set(pe, port_map); | |
2319 | ||
2320 | mvpp2_prs_hw_write(priv, pe); | |
f9fd0e34 | 2321 | free_pe: |
3f518509 MW |
2322 | kfree(pe); |
2323 | ||
43737473 | 2324 | return ret; |
3f518509 MW |
2325 | } |
2326 | ||
2327 | /* Get first free double vlan ai number */ | |
2328 | static int mvpp2_prs_double_vlan_ai_free_get(struct mvpp2 *priv) | |
2329 | { | |
2330 | int i; | |
2331 | ||
2332 | for (i = 1; i < MVPP2_PRS_DBL_VLANS_MAX; i++) { | |
2333 | if (!priv->prs_double_vlans[i]) | |
2334 | return i; | |
2335 | } | |
2336 | ||
2337 | return -EINVAL; | |
2338 | } | |
2339 | ||
2340 | /* Search for existing double vlan entry */ | |
2341 | static struct mvpp2_prs_entry *mvpp2_prs_double_vlan_find(struct mvpp2 *priv, | |
2342 | unsigned short tpid1, | |
2343 | unsigned short tpid2) | |
2344 | { | |
2345 | struct mvpp2_prs_entry *pe; | |
2346 | int tid; | |
2347 | ||
2348 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2349 | if (!pe) | |
2350 | return NULL; | |
2351 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); | |
2352 | ||
2353 | /* Go through the all entries with MVPP2_PRS_LU_VLAN */ | |
2354 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
2355 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
2356 | unsigned int ri_mask; | |
2357 | bool match; | |
2358 | ||
2359 | if (!priv->prs_shadow[tid].valid || | |
2360 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN) | |
2361 | continue; | |
2362 | ||
2363 | pe->index = tid; | |
2364 | mvpp2_prs_hw_read(priv, pe); | |
2365 | ||
2366 | match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid1)) | |
2367 | && mvpp2_prs_tcam_data_cmp(pe, 4, swab16(tpid2)); | |
2368 | ||
2369 | if (!match) | |
2370 | continue; | |
2371 | ||
2372 | ri_mask = mvpp2_prs_sram_ri_get(pe) & MVPP2_PRS_RI_VLAN_MASK; | |
2373 | if (ri_mask == MVPP2_PRS_RI_VLAN_DOUBLE) | |
2374 | return pe; | |
2375 | } | |
2376 | kfree(pe); | |
2377 | ||
2378 | return NULL; | |
2379 | } | |
2380 | ||
2381 | /* Add or update double vlan entry */ | |
2382 | static int mvpp2_prs_double_vlan_add(struct mvpp2 *priv, unsigned short tpid1, | |
2383 | unsigned short tpid2, | |
2384 | unsigned int port_map) | |
2385 | { | |
2386 | struct mvpp2_prs_entry *pe; | |
43737473 | 2387 | int tid_aux, tid, ai, ret = 0; |
3f518509 MW |
2388 | |
2389 | pe = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2); | |
2390 | ||
2391 | if (!pe) { | |
2392 | /* Create new tcam entry */ | |
2393 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2394 | MVPP2_PE_LAST_FREE_TID); | |
2395 | if (tid < 0) | |
2396 | return tid; | |
2397 | ||
2398 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2399 | if (!pe) | |
2400 | return -ENOMEM; | |
2401 | ||
2402 | /* Set ai value for new double vlan entry */ | |
2403 | ai = mvpp2_prs_double_vlan_ai_free_get(priv); | |
43737473 SM |
2404 | if (ai < 0) { |
2405 | ret = ai; | |
c9a7e120 | 2406 | goto free_pe; |
43737473 | 2407 | } |
3f518509 MW |
2408 | |
2409 | /* Get first single/triple vlan tid */ | |
2410 | for (tid_aux = MVPP2_PE_FIRST_FREE_TID; | |
2411 | tid_aux <= MVPP2_PE_LAST_FREE_TID; tid_aux++) { | |
2412 | unsigned int ri_bits; | |
2413 | ||
2414 | if (!priv->prs_shadow[tid_aux].valid || | |
2415 | priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN) | |
2416 | continue; | |
2417 | ||
2418 | pe->index = tid_aux; | |
2419 | mvpp2_prs_hw_read(priv, pe); | |
2420 | ri_bits = mvpp2_prs_sram_ri_get(pe); | |
2421 | ri_bits &= MVPP2_PRS_RI_VLAN_MASK; | |
2422 | if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE || | |
2423 | ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE) | |
2424 | break; | |
2425 | } | |
2426 | ||
43737473 SM |
2427 | if (tid >= tid_aux) { |
2428 | ret = -ERANGE; | |
c9a7e120 | 2429 | goto free_pe; |
43737473 | 2430 | } |
3f518509 | 2431 | |
bd6aaf55 | 2432 | memset(pe, 0, sizeof(*pe)); |
3f518509 MW |
2433 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); |
2434 | pe->index = tid; | |
2435 | ||
2436 | priv->prs_double_vlans[ai] = true; | |
2437 | ||
2438 | mvpp2_prs_match_etype(pe, 0, tpid1); | |
2439 | mvpp2_prs_match_etype(pe, 4, tpid2); | |
2440 | ||
2441 | mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_VLAN); | |
56beda3d MC |
2442 | /* Shift 4 bytes - skip outer vlan tag */ |
2443 | mvpp2_prs_sram_shift_set(pe, MVPP2_VLAN_TAG_LEN, | |
3f518509 MW |
2444 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); |
2445 | mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_DOUBLE, | |
2446 | MVPP2_PRS_RI_VLAN_MASK); | |
2447 | mvpp2_prs_sram_ai_update(pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, | |
2448 | MVPP2_PRS_SRAM_AI_MASK); | |
2449 | ||
2450 | mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); | |
2451 | } | |
2452 | ||
2453 | /* Update ports' mask */ | |
2454 | mvpp2_prs_tcam_port_map_set(pe, port_map); | |
2455 | mvpp2_prs_hw_write(priv, pe); | |
c9a7e120 | 2456 | free_pe: |
3f518509 | 2457 | kfree(pe); |
43737473 | 2458 | return ret; |
3f518509 MW |
2459 | } |
2460 | ||
2461 | /* IPv4 header parsing for fragmentation and L4 offset */ | |
2462 | static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto, | |
2463 | unsigned int ri, unsigned int ri_mask) | |
2464 | { | |
2465 | struct mvpp2_prs_entry pe; | |
2466 | int tid; | |
2467 | ||
2468 | if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) && | |
2469 | (proto != IPPROTO_IGMP)) | |
2470 | return -EINVAL; | |
2471 | ||
aff3da39 | 2472 | /* Not fragmented packet */ |
3f518509 MW |
2473 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, |
2474 | MVPP2_PE_LAST_FREE_TID); | |
2475 | if (tid < 0) | |
2476 | return tid; | |
2477 | ||
c5b2ce24 | 2478 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2479 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
2480 | pe.index = tid; | |
2481 | ||
2482 | /* Set next lu to IPv4 */ | |
2483 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
2484 | mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2485 | /* Set L4 offset */ | |
2486 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
2487 | sizeof(struct iphdr) - 4, | |
2488 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2489 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
2490 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
aff3da39 SC |
2491 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); |
2492 | ||
2493 | mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, | |
2494 | MVPP2_PRS_TCAM_PROTO_MASK_L); | |
2495 | mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, | |
2496 | MVPP2_PRS_TCAM_PROTO_MASK); | |
3f518509 MW |
2497 | |
2498 | mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); | |
2499 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); | |
2500 | /* Unmask all ports */ | |
2501 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2502 | ||
2503 | /* Update shadow table and hw entry */ | |
2504 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2505 | mvpp2_prs_hw_write(priv, &pe); | |
2506 | ||
aff3da39 | 2507 | /* Fragmented packet */ |
3f518509 MW |
2508 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, |
2509 | MVPP2_PE_LAST_FREE_TID); | |
2510 | if (tid < 0) | |
2511 | return tid; | |
2512 | ||
2513 | pe.index = tid; | |
2514 | /* Clear ri before updating */ | |
2515 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
2516 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
2517 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); | |
2518 | ||
aff3da39 SC |
2519 | mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE, |
2520 | ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); | |
2521 | ||
2522 | mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0); | |
2523 | mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0); | |
3f518509 MW |
2524 | |
2525 | /* Update shadow table and hw entry */ | |
2526 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2527 | mvpp2_prs_hw_write(priv, &pe); | |
2528 | ||
2529 | return 0; | |
2530 | } | |
2531 | ||
2532 | /* IPv4 L3 multicast or broadcast */ | |
2533 | static int mvpp2_prs_ip4_cast(struct mvpp2 *priv, unsigned short l3_cast) | |
2534 | { | |
2535 | struct mvpp2_prs_entry pe; | |
2536 | int mask, tid; | |
2537 | ||
2538 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2539 | MVPP2_PE_LAST_FREE_TID); | |
2540 | if (tid < 0) | |
2541 | return tid; | |
2542 | ||
c5b2ce24 | 2543 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2544 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
2545 | pe.index = tid; | |
2546 | ||
2547 | switch (l3_cast) { | |
2548 | case MVPP2_PRS_L3_MULTI_CAST: | |
2549 | mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, | |
2550 | MVPP2_PRS_IPV4_MC_MASK); | |
2551 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, | |
2552 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2553 | break; | |
2554 | case MVPP2_PRS_L3_BROAD_CAST: | |
2555 | mask = MVPP2_PRS_IPV4_BC_MASK; | |
2556 | mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); | |
2557 | mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); | |
2558 | mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); | |
2559 | mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); | |
2560 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, | |
2561 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2562 | break; | |
2563 | default: | |
2564 | return -EINVAL; | |
2565 | } | |
2566 | ||
2567 | /* Finished: go to flowid generation */ | |
2568 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2569 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2570 | ||
2571 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
2572 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
2573 | /* Unmask all ports */ | |
2574 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2575 | ||
2576 | /* Update shadow table and hw entry */ | |
2577 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2578 | mvpp2_prs_hw_write(priv, &pe); | |
2579 | ||
2580 | return 0; | |
2581 | } | |
2582 | ||
2583 | /* Set entries for protocols over IPv6 */ | |
2584 | static int mvpp2_prs_ip6_proto(struct mvpp2 *priv, unsigned short proto, | |
2585 | unsigned int ri, unsigned int ri_mask) | |
2586 | { | |
2587 | struct mvpp2_prs_entry pe; | |
2588 | int tid; | |
2589 | ||
2590 | if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) && | |
2591 | (proto != IPPROTO_ICMPV6) && (proto != IPPROTO_IPIP)) | |
2592 | return -EINVAL; | |
2593 | ||
2594 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2595 | MVPP2_PE_LAST_FREE_TID); | |
2596 | if (tid < 0) | |
2597 | return tid; | |
2598 | ||
c5b2ce24 | 2599 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2600 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
2601 | pe.index = tid; | |
2602 | ||
2603 | /* Finished: go to flowid generation */ | |
2604 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2605 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2606 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); | |
2607 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
2608 | sizeof(struct ipv6hdr) - 6, | |
2609 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2610 | ||
2611 | mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); | |
2612 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
2613 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2614 | /* Unmask all ports */ | |
2615 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2616 | ||
2617 | /* Write HW */ | |
2618 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
2619 | mvpp2_prs_hw_write(priv, &pe); | |
2620 | ||
2621 | return 0; | |
2622 | } | |
2623 | ||
2624 | /* IPv6 L3 multicast entry */ | |
2625 | static int mvpp2_prs_ip6_cast(struct mvpp2 *priv, unsigned short l3_cast) | |
2626 | { | |
2627 | struct mvpp2_prs_entry pe; | |
2628 | int tid; | |
2629 | ||
2630 | if (l3_cast != MVPP2_PRS_L3_MULTI_CAST) | |
2631 | return -EINVAL; | |
2632 | ||
2633 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2634 | MVPP2_PE_LAST_FREE_TID); | |
2635 | if (tid < 0) | |
2636 | return tid; | |
2637 | ||
c5b2ce24 | 2638 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2639 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
2640 | pe.index = tid; | |
2641 | ||
2642 | /* Finished: go to flowid generation */ | |
2643 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
2644 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, | |
2645 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2646 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
2647 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2648 | /* Shift back to IPv6 NH */ | |
2649 | mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2650 | ||
2651 | mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, | |
2652 | MVPP2_PRS_IPV6_MC_MASK); | |
2653 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2654 | /* Unmask all ports */ | |
2655 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2656 | ||
2657 | /* Update shadow table and hw entry */ | |
2658 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
2659 | mvpp2_prs_hw_write(priv, &pe); | |
2660 | ||
2661 | return 0; | |
2662 | } | |
2663 | ||
2664 | /* Parser per-port initialization */ | |
2665 | static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, | |
2666 | int lu_max, int offset) | |
2667 | { | |
2668 | u32 val; | |
2669 | ||
2670 | /* Set lookup ID */ | |
2671 | val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG); | |
2672 | val &= ~MVPP2_PRS_PORT_LU_MASK(port); | |
2673 | val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); | |
2674 | mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val); | |
2675 | ||
2676 | /* Set maximum number of loops for packet received from port */ | |
2677 | val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); | |
2678 | val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); | |
2679 | val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); | |
2680 | mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); | |
2681 | ||
2682 | /* Set initial offset for packet header extraction for the first | |
2683 | * searching loop | |
2684 | */ | |
2685 | val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); | |
2686 | val &= ~MVPP2_PRS_INIT_OFF_MASK(port); | |
2687 | val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); | |
2688 | mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); | |
2689 | } | |
2690 | ||
2691 | /* Default flow entries initialization for all ports */ | |
2692 | static void mvpp2_prs_def_flow_init(struct mvpp2 *priv) | |
2693 | { | |
2694 | struct mvpp2_prs_entry pe; | |
2695 | int port; | |
2696 | ||
2697 | for (port = 0; port < MVPP2_MAX_PORTS; port++) { | |
c5b2ce24 | 2698 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2699 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); |
2700 | pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; | |
2701 | ||
2702 | /* Mask all ports */ | |
2703 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
2704 | ||
2705 | /* Set flow ID*/ | |
2706 | mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); | |
2707 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); | |
2708 | ||
2709 | /* Update shadow table and hw entry */ | |
2710 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); | |
2711 | mvpp2_prs_hw_write(priv, &pe); | |
2712 | } | |
2713 | } | |
2714 | ||
2715 | /* Set default entry for Marvell Header field */ | |
2716 | static void mvpp2_prs_mh_init(struct mvpp2 *priv) | |
2717 | { | |
2718 | struct mvpp2_prs_entry pe; | |
2719 | ||
c5b2ce24 | 2720 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2721 | |
2722 | pe.index = MVPP2_PE_MH_DEFAULT; | |
2723 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); | |
2724 | mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, | |
2725 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2726 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); | |
2727 | ||
2728 | /* Unmask all ports */ | |
2729 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2730 | ||
2731 | /* Update shadow table and hw entry */ | |
2732 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); | |
2733 | mvpp2_prs_hw_write(priv, &pe); | |
2734 | } | |
2735 | ||
2736 | /* Set default entires (place holder) for promiscuous, non-promiscuous and | |
2737 | * multicast MAC addresses | |
2738 | */ | |
2739 | static void mvpp2_prs_mac_init(struct mvpp2 *priv) | |
2740 | { | |
2741 | struct mvpp2_prs_entry pe; | |
2742 | ||
c5b2ce24 | 2743 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2744 | |
2745 | /* Non-promiscuous mode for all ports - DROP unknown packets */ | |
2746 | pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; | |
2747 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); | |
2748 | ||
2749 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, | |
2750 | MVPP2_PRS_RI_DROP_MASK); | |
2751 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2752 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2753 | ||
2754 | /* Unmask all ports */ | |
2755 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2756 | ||
2757 | /* Update shadow table and hw entry */ | |
2758 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2759 | mvpp2_prs_hw_write(priv, &pe); | |
2760 | ||
2761 | /* place holders only - no ports */ | |
2762 | mvpp2_prs_mac_drop_all_set(priv, 0, false); | |
2763 | mvpp2_prs_mac_promisc_set(priv, 0, false); | |
20746d71 AT |
2764 | mvpp2_prs_mac_multi_set(priv, 0, MVPP2_PE_MAC_MC_ALL, false); |
2765 | mvpp2_prs_mac_multi_set(priv, 0, MVPP2_PE_MAC_MC_IP6, false); | |
3f518509 MW |
2766 | } |
2767 | ||
2768 | /* Set default entries for various types of dsa packets */ | |
2769 | static void mvpp2_prs_dsa_init(struct mvpp2 *priv) | |
2770 | { | |
2771 | struct mvpp2_prs_entry pe; | |
2772 | ||
2773 | /* None tagged EDSA entry - place holder */ | |
2774 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED, | |
2775 | MVPP2_PRS_EDSA); | |
2776 | ||
2777 | /* Tagged EDSA entry - place holder */ | |
2778 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
2779 | ||
2780 | /* None tagged DSA entry - place holder */ | |
2781 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED, | |
2782 | MVPP2_PRS_DSA); | |
2783 | ||
2784 | /* Tagged DSA entry - place holder */ | |
2785 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
2786 | ||
2787 | /* None tagged EDSA ethertype entry - place holder*/ | |
2788 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false, | |
2789 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
2790 | ||
2791 | /* Tagged EDSA ethertype entry - place holder*/ | |
2792 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false, | |
2793 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
2794 | ||
2795 | /* None tagged DSA ethertype entry */ | |
2796 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true, | |
2797 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
2798 | ||
2799 | /* Tagged DSA ethertype entry */ | |
2800 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true, | |
2801 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
2802 | ||
2803 | /* Set default entry, in case DSA or EDSA tag not found */ | |
c5b2ce24 | 2804 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2805 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
2806 | pe.index = MVPP2_PE_DSA_DEFAULT; | |
2807 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
2808 | ||
2809 | /* Shift 0 bytes */ | |
2810 | mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2811 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2812 | ||
2813 | /* Clear all sram ai bits for next iteration */ | |
2814 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2815 | ||
2816 | /* Unmask all ports */ | |
2817 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2818 | ||
2819 | mvpp2_prs_hw_write(priv, &pe); | |
2820 | } | |
2821 | ||
56beda3d MC |
2822 | /* Initialize parser entries for VID filtering */ |
2823 | static void mvpp2_prs_vid_init(struct mvpp2 *priv) | |
2824 | { | |
2825 | struct mvpp2_prs_entry pe; | |
2826 | ||
2827 | memset(&pe, 0, sizeof(pe)); | |
2828 | ||
2829 | /* Set default vid entry */ | |
2830 | pe.index = MVPP2_PE_VID_FLTR_DEFAULT; | |
2831 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); | |
2832 | ||
2833 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_EDSA_VID_AI_BIT); | |
2834 | ||
2835 | /* Skip VLAN header - Set offset to 4 bytes */ | |
2836 | mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, | |
2837 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2838 | ||
2839 | /* Clear all ai bits for next iteration */ | |
2840 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2841 | ||
2842 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2843 | ||
2844 | /* Unmask all ports */ | |
2845 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2846 | ||
2847 | /* Update shadow table and hw entry */ | |
2848 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); | |
2849 | mvpp2_prs_hw_write(priv, &pe); | |
2850 | ||
2851 | /* Set default vid entry for extended DSA*/ | |
2852 | memset(&pe, 0, sizeof(pe)); | |
2853 | ||
2854 | /* Set default vid entry */ | |
2855 | pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT; | |
2856 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); | |
2857 | ||
2858 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_EDSA_VID_AI_BIT, | |
2859 | MVPP2_PRS_EDSA_VID_AI_BIT); | |
2860 | ||
2861 | /* Skip VLAN header - Set offset to 8 bytes */ | |
2862 | mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN, | |
2863 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2864 | ||
2865 | /* Clear all ai bits for next iteration */ | |
2866 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2867 | ||
2868 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2869 | ||
2870 | /* Unmask all ports */ | |
2871 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2872 | ||
2873 | /* Update shadow table and hw entry */ | |
2874 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); | |
2875 | mvpp2_prs_hw_write(priv, &pe); | |
2876 | } | |
2877 | ||
3f518509 MW |
2878 | /* Match basic ethertypes */ |
2879 | static int mvpp2_prs_etype_init(struct mvpp2 *priv) | |
2880 | { | |
2881 | struct mvpp2_prs_entry pe; | |
2882 | int tid; | |
2883 | ||
2884 | /* Ethertype: PPPoE */ | |
2885 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2886 | MVPP2_PE_LAST_FREE_TID); | |
2887 | if (tid < 0) | |
2888 | return tid; | |
2889 | ||
c5b2ce24 | 2890 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2891 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2892 | pe.index = tid; | |
2893 | ||
2894 | mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); | |
2895 | ||
2896 | mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, | |
2897 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2898 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); | |
2899 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, | |
2900 | MVPP2_PRS_RI_PPPOE_MASK); | |
2901 | ||
2902 | /* Update shadow table and hw entry */ | |
2903 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2904 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2905 | priv->prs_shadow[pe.index].finish = false; | |
2906 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, | |
2907 | MVPP2_PRS_RI_PPPOE_MASK); | |
2908 | mvpp2_prs_hw_write(priv, &pe); | |
2909 | ||
2910 | /* Ethertype: ARP */ | |
2911 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2912 | MVPP2_PE_LAST_FREE_TID); | |
2913 | if (tid < 0) | |
2914 | return tid; | |
2915 | ||
c5b2ce24 | 2916 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2917 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2918 | pe.index = tid; | |
2919 | ||
2920 | mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); | |
2921 | ||
2922 | /* Generate flow in the next iteration*/ | |
2923 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2924 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2925 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, | |
2926 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2927 | /* Set L3 offset */ | |
2928 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2929 | MVPP2_ETH_TYPE_LEN, | |
2930 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2931 | ||
2932 | /* Update shadow table and hw entry */ | |
2933 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2934 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2935 | priv->prs_shadow[pe.index].finish = true; | |
2936 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, | |
2937 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2938 | mvpp2_prs_hw_write(priv, &pe); | |
2939 | ||
2940 | /* Ethertype: LBTD */ | |
2941 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2942 | MVPP2_PE_LAST_FREE_TID); | |
2943 | if (tid < 0) | |
2944 | return tid; | |
2945 | ||
c5b2ce24 | 2946 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2947 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2948 | pe.index = tid; | |
2949 | ||
2950 | mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); | |
2951 | ||
2952 | /* Generate flow in the next iteration*/ | |
2953 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2954 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2955 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
2956 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
2957 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
2958 | MVPP2_PRS_RI_UDF3_MASK); | |
2959 | /* Set L3 offset */ | |
2960 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2961 | MVPP2_ETH_TYPE_LEN, | |
2962 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2963 | ||
2964 | /* Update shadow table and hw entry */ | |
2965 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2966 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2967 | priv->prs_shadow[pe.index].finish = true; | |
2968 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
2969 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
2970 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
2971 | MVPP2_PRS_RI_UDF3_MASK); | |
2972 | mvpp2_prs_hw_write(priv, &pe); | |
2973 | ||
2974 | /* Ethertype: IPv4 without options */ | |
2975 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2976 | MVPP2_PE_LAST_FREE_TID); | |
2977 | if (tid < 0) | |
2978 | return tid; | |
2979 | ||
c5b2ce24 | 2980 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2981 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2982 | pe.index = tid; | |
2983 | ||
2984 | mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); | |
2985 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
2986 | MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL, | |
2987 | MVPP2_PRS_IPV4_HEAD_MASK | | |
2988 | MVPP2_PRS_IPV4_IHL_MASK); | |
2989 | ||
2990 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
2991 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, | |
2992 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2993 | /* Skip eth_type + 4 bytes of IP header */ | |
2994 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
2995 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2996 | /* Set L3 offset */ | |
2997 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2998 | MVPP2_ETH_TYPE_LEN, | |
2999 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3000 | ||
3001 | /* Update shadow table and hw entry */ | |
3002 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
3003 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
3004 | priv->prs_shadow[pe.index].finish = false; | |
3005 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, | |
3006 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3007 | mvpp2_prs_hw_write(priv, &pe); | |
3008 | ||
3009 | /* Ethertype: IPv4 with options */ | |
3010 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3011 | MVPP2_PE_LAST_FREE_TID); | |
3012 | if (tid < 0) | |
3013 | return tid; | |
3014 | ||
3015 | pe.index = tid; | |
3016 | ||
3017 | /* Clear tcam data before updating */ | |
3018 | pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0; | |
3019 | pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0; | |
3020 | ||
3021 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
3022 | MVPP2_PRS_IPV4_HEAD, | |
3023 | MVPP2_PRS_IPV4_HEAD_MASK); | |
3024 | ||
3025 | /* Clear ri before updating */ | |
3026 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
3027 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
3028 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, | |
3029 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3030 | ||
3031 | /* Update shadow table and hw entry */ | |
3032 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
3033 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
3034 | priv->prs_shadow[pe.index].finish = false; | |
3035 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, | |
3036 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3037 | mvpp2_prs_hw_write(priv, &pe); | |
3038 | ||
3039 | /* Ethertype: IPv6 without options */ | |
3040 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3041 | MVPP2_PE_LAST_FREE_TID); | |
3042 | if (tid < 0) | |
3043 | return tid; | |
3044 | ||
c5b2ce24 | 3045 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3046 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
3047 | pe.index = tid; | |
3048 | ||
3049 | mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); | |
3050 | ||
3051 | /* Skip DIP of IPV6 header */ | |
3052 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + | |
3053 | MVPP2_MAX_L3_ADDR_SIZE, | |
3054 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3055 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3056 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, | |
3057 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3058 | /* Set L3 offset */ | |
3059 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3060 | MVPP2_ETH_TYPE_LEN, | |
3061 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3062 | ||
3063 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
3064 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
3065 | priv->prs_shadow[pe.index].finish = false; | |
3066 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, | |
3067 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3068 | mvpp2_prs_hw_write(priv, &pe); | |
3069 | ||
3070 | /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */ | |
3071 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
3072 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); | |
3073 | pe.index = MVPP2_PE_ETH_TYPE_UN; | |
3074 | ||
3075 | /* Unmask all ports */ | |
3076 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3077 | ||
3078 | /* Generate flow in the next iteration*/ | |
3079 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3080 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3081 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, | |
3082 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3083 | /* Set L3 offset even it's unknown L3 */ | |
3084 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3085 | MVPP2_ETH_TYPE_LEN, | |
3086 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3087 | ||
3088 | /* Update shadow table and hw entry */ | |
3089 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
3090 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
3091 | priv->prs_shadow[pe.index].finish = true; | |
3092 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, | |
3093 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3094 | mvpp2_prs_hw_write(priv, &pe); | |
3095 | ||
3096 | return 0; | |
3097 | } | |
3098 | ||
3099 | /* Configure vlan entries and detect up to 2 successive VLAN tags. | |
3100 | * Possible options: | |
3101 | * 0x8100, 0x88A8 | |
3102 | * 0x8100, 0x8100 | |
3103 | * 0x8100 | |
3104 | * 0x88A8 | |
3105 | */ | |
3106 | static int mvpp2_prs_vlan_init(struct platform_device *pdev, struct mvpp2 *priv) | |
3107 | { | |
3108 | struct mvpp2_prs_entry pe; | |
3109 | int err; | |
3110 | ||
3111 | priv->prs_double_vlans = devm_kcalloc(&pdev->dev, sizeof(bool), | |
3112 | MVPP2_PRS_DBL_VLANS_MAX, | |
3113 | GFP_KERNEL); | |
3114 | if (!priv->prs_double_vlans) | |
3115 | return -ENOMEM; | |
3116 | ||
3117 | /* Double VLAN: 0x8100, 0x88A8 */ | |
3118 | err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021AD, | |
3119 | MVPP2_PRS_PORT_MASK); | |
3120 | if (err) | |
3121 | return err; | |
3122 | ||
3123 | /* Double VLAN: 0x8100, 0x8100 */ | |
3124 | err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021Q, | |
3125 | MVPP2_PRS_PORT_MASK); | |
3126 | if (err) | |
3127 | return err; | |
3128 | ||
3129 | /* Single VLAN: 0x88a8 */ | |
3130 | err = mvpp2_prs_vlan_add(priv, ETH_P_8021AD, MVPP2_PRS_SINGLE_VLAN_AI, | |
3131 | MVPP2_PRS_PORT_MASK); | |
3132 | if (err) | |
3133 | return err; | |
3134 | ||
3135 | /* Single VLAN: 0x8100 */ | |
3136 | err = mvpp2_prs_vlan_add(priv, ETH_P_8021Q, MVPP2_PRS_SINGLE_VLAN_AI, | |
3137 | MVPP2_PRS_PORT_MASK); | |
3138 | if (err) | |
3139 | return err; | |
3140 | ||
3141 | /* Set default double vlan entry */ | |
c5b2ce24 | 3142 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3143 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); |
3144 | pe.index = MVPP2_PE_VLAN_DBL; | |
3145 | ||
56beda3d MC |
3146 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); |
3147 | ||
3f518509 MW |
3148 | /* Clear ai for next iterations */ |
3149 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
3150 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, | |
3151 | MVPP2_PRS_RI_VLAN_MASK); | |
3152 | ||
3153 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, | |
3154 | MVPP2_PRS_DBL_VLAN_AI_BIT); | |
3155 | /* Unmask all ports */ | |
3156 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3157 | ||
3158 | /* Update shadow table and hw entry */ | |
3159 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); | |
3160 | mvpp2_prs_hw_write(priv, &pe); | |
3161 | ||
3162 | /* Set default vlan none entry */ | |
c5b2ce24 | 3163 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3164 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); |
3165 | pe.index = MVPP2_PE_VLAN_NONE; | |
3166 | ||
3167 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
3168 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
3169 | MVPP2_PRS_RI_VLAN_MASK); | |
3170 | ||
3171 | /* Unmask all ports */ | |
3172 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3173 | ||
3174 | /* Update shadow table and hw entry */ | |
3175 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); | |
3176 | mvpp2_prs_hw_write(priv, &pe); | |
3177 | ||
3178 | return 0; | |
3179 | } | |
3180 | ||
3181 | /* Set entries for PPPoE ethertype */ | |
3182 | static int mvpp2_prs_pppoe_init(struct mvpp2 *priv) | |
3183 | { | |
3184 | struct mvpp2_prs_entry pe; | |
3185 | int tid; | |
3186 | ||
3187 | /* IPv4 over PPPoE with options */ | |
3188 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3189 | MVPP2_PE_LAST_FREE_TID); | |
3190 | if (tid < 0) | |
3191 | return tid; | |
3192 | ||
c5b2ce24 | 3193 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3194 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
3195 | pe.index = tid; | |
3196 | ||
3197 | mvpp2_prs_match_etype(&pe, 0, PPP_IP); | |
3198 | ||
3199 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
3200 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, | |
3201 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3202 | /* Skip eth_type + 4 bytes of IP header */ | |
3203 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
3204 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3205 | /* Set L3 offset */ | |
3206 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3207 | MVPP2_ETH_TYPE_LEN, | |
3208 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3209 | ||
3210 | /* Update shadow table and hw entry */ | |
3211 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3212 | mvpp2_prs_hw_write(priv, &pe); | |
3213 | ||
3214 | /* IPv4 over PPPoE without options */ | |
3215 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3216 | MVPP2_PE_LAST_FREE_TID); | |
3217 | if (tid < 0) | |
3218 | return tid; | |
3219 | ||
3220 | pe.index = tid; | |
3221 | ||
3222 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
3223 | MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL, | |
3224 | MVPP2_PRS_IPV4_HEAD_MASK | | |
3225 | MVPP2_PRS_IPV4_IHL_MASK); | |
3226 | ||
3227 | /* Clear ri before updating */ | |
3228 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
3229 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
3230 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, | |
3231 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3232 | ||
3233 | /* Update shadow table and hw entry */ | |
3234 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3235 | mvpp2_prs_hw_write(priv, &pe); | |
3236 | ||
3237 | /* IPv6 over PPPoE */ | |
3238 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3239 | MVPP2_PE_LAST_FREE_TID); | |
3240 | if (tid < 0) | |
3241 | return tid; | |
3242 | ||
c5b2ce24 | 3243 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3244 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
3245 | pe.index = tid; | |
3246 | ||
3247 | mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); | |
3248 | ||
3249 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3250 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, | |
3251 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3252 | /* Skip eth_type + 4 bytes of IPv6 header */ | |
3253 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
3254 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3255 | /* Set L3 offset */ | |
3256 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3257 | MVPP2_ETH_TYPE_LEN, | |
3258 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3259 | ||
3260 | /* Update shadow table and hw entry */ | |
3261 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3262 | mvpp2_prs_hw_write(priv, &pe); | |
3263 | ||
3264 | /* Non-IP over PPPoE */ | |
3265 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3266 | MVPP2_PE_LAST_FREE_TID); | |
3267 | if (tid < 0) | |
3268 | return tid; | |
3269 | ||
c5b2ce24 | 3270 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3271 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
3272 | pe.index = tid; | |
3273 | ||
3274 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, | |
3275 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3276 | ||
3277 | /* Finished: go to flowid generation */ | |
3278 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3279 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3280 | /* Set L3 offset even if it's unknown L3 */ | |
3281 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3282 | MVPP2_ETH_TYPE_LEN, | |
3283 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3284 | ||
3285 | /* Update shadow table and hw entry */ | |
3286 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3287 | mvpp2_prs_hw_write(priv, &pe); | |
3288 | ||
3289 | return 0; | |
3290 | } | |
3291 | ||
3292 | /* Initialize entries for IPv4 */ | |
3293 | static int mvpp2_prs_ip4_init(struct mvpp2 *priv) | |
3294 | { | |
3295 | struct mvpp2_prs_entry pe; | |
3296 | int err; | |
3297 | ||
3298 | /* Set entries for TCP, UDP and IGMP over IPv4 */ | |
3299 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_TCP, MVPP2_PRS_RI_L4_TCP, | |
3300 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3301 | if (err) | |
3302 | return err; | |
3303 | ||
3304 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_UDP, MVPP2_PRS_RI_L4_UDP, | |
3305 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3306 | if (err) | |
3307 | return err; | |
3308 | ||
3309 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_IGMP, | |
3310 | MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
3311 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
3312 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
3313 | MVPP2_PRS_RI_UDF3_MASK); | |
3314 | if (err) | |
3315 | return err; | |
3316 | ||
3317 | /* IPv4 Broadcast */ | |
3318 | err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_BROAD_CAST); | |
3319 | if (err) | |
3320 | return err; | |
3321 | ||
3322 | /* IPv4 Multicast */ | |
3323 | err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_MULTI_CAST); | |
3324 | if (err) | |
3325 | return err; | |
3326 | ||
3327 | /* Default IPv4 entry for unknown protocols */ | |
c5b2ce24 | 3328 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3329 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
3330 | pe.index = MVPP2_PE_IP4_PROTO_UN; | |
3331 | ||
3332 | /* Set next lu to IPv4 */ | |
3333 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
3334 | mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3335 | /* Set L4 offset */ | |
3336 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
3337 | sizeof(struct iphdr) - 4, | |
3338 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3339 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
3340 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3341 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3342 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3343 | ||
3344 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3345 | /* Unmask all ports */ | |
3346 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3347 | ||
3348 | /* Update shadow table and hw entry */ | |
3349 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3350 | mvpp2_prs_hw_write(priv, &pe); | |
3351 | ||
3352 | /* Default IPv4 entry for unicast address */ | |
c5b2ce24 | 3353 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3354 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
3355 | pe.index = MVPP2_PE_IP4_ADDR_UN; | |
3356 | ||
3357 | /* Finished: go to flowid generation */ | |
3358 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3359 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3360 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, | |
3361 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
3362 | ||
3363 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
3364 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3365 | /* Unmask all ports */ | |
3366 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3367 | ||
3368 | /* Update shadow table and hw entry */ | |
3369 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3370 | mvpp2_prs_hw_write(priv, &pe); | |
3371 | ||
3372 | return 0; | |
3373 | } | |
3374 | ||
3375 | /* Initialize entries for IPv6 */ | |
3376 | static int mvpp2_prs_ip6_init(struct mvpp2 *priv) | |
3377 | { | |
3378 | struct mvpp2_prs_entry pe; | |
3379 | int tid, err; | |
3380 | ||
3381 | /* Set entries for TCP, UDP and ICMP over IPv6 */ | |
3382 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_TCP, | |
3383 | MVPP2_PRS_RI_L4_TCP, | |
3384 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3385 | if (err) | |
3386 | return err; | |
3387 | ||
3388 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_UDP, | |
3389 | MVPP2_PRS_RI_L4_UDP, | |
3390 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3391 | if (err) | |
3392 | return err; | |
3393 | ||
3394 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_ICMPV6, | |
3395 | MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
3396 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
3397 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
3398 | MVPP2_PRS_RI_UDF3_MASK); | |
3399 | if (err) | |
3400 | return err; | |
3401 | ||
3402 | /* IPv4 is the last header. This is similar case as 6-TCP or 17-UDP */ | |
3403 | /* Result Info: UDF7=1, DS lite */ | |
3404 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_IPIP, | |
3405 | MVPP2_PRS_RI_UDF7_IP6_LITE, | |
3406 | MVPP2_PRS_RI_UDF7_MASK); | |
3407 | if (err) | |
3408 | return err; | |
3409 | ||
3410 | /* IPv6 multicast */ | |
3411 | err = mvpp2_prs_ip6_cast(priv, MVPP2_PRS_L3_MULTI_CAST); | |
3412 | if (err) | |
3413 | return err; | |
3414 | ||
3415 | /* Entry for checking hop limit */ | |
3416 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3417 | MVPP2_PE_LAST_FREE_TID); | |
3418 | if (tid < 0) | |
3419 | return tid; | |
3420 | ||
c5b2ce24 | 3421 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3422 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
3423 | pe.index = tid; | |
3424 | ||
3425 | /* Finished: go to flowid generation */ | |
3426 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3427 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3428 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | | |
3429 | MVPP2_PRS_RI_DROP_MASK, | |
3430 | MVPP2_PRS_RI_L3_PROTO_MASK | | |
3431 | MVPP2_PRS_RI_DROP_MASK); | |
3432 | ||
3433 | mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); | |
3434 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3435 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3436 | ||
3437 | /* Update shadow table and hw entry */ | |
3438 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3439 | mvpp2_prs_hw_write(priv, &pe); | |
3440 | ||
3441 | /* Default IPv6 entry for unknown protocols */ | |
c5b2ce24 | 3442 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3443 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
3444 | pe.index = MVPP2_PE_IP6_PROTO_UN; | |
3445 | ||
3446 | /* Finished: go to flowid generation */ | |
3447 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3448 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3449 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3450 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3451 | /* Set L4 offset relatively to our current place */ | |
3452 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
3453 | sizeof(struct ipv6hdr) - 4, | |
3454 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3455 | ||
3456 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3457 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3458 | /* Unmask all ports */ | |
3459 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3460 | ||
3461 | /* Update shadow table and hw entry */ | |
3462 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3463 | mvpp2_prs_hw_write(priv, &pe); | |
3464 | ||
3465 | /* Default IPv6 entry for unknown ext protocols */ | |
3466 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
3467 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3468 | pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; | |
3469 | ||
3470 | /* Finished: go to flowid generation */ | |
3471 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3472 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3473 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3474 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3475 | ||
3476 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, | |
3477 | MVPP2_PRS_IPV6_EXT_AI_BIT); | |
3478 | /* Unmask all ports */ | |
3479 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3480 | ||
3481 | /* Update shadow table and hw entry */ | |
3482 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3483 | mvpp2_prs_hw_write(priv, &pe); | |
3484 | ||
3485 | /* Default IPv6 entry for unicast address */ | |
3486 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
3487 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3488 | pe.index = MVPP2_PE_IP6_ADDR_UN; | |
3489 | ||
3490 | /* Finished: go to IPv6 again */ | |
3491 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3492 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, | |
3493 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
3494 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3495 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3496 | /* Shift back to IPV6 NH */ | |
3497 | mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3498 | ||
3499 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3500 | /* Unmask all ports */ | |
3501 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3502 | ||
3503 | /* Update shadow table and hw entry */ | |
3504 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
3505 | mvpp2_prs_hw_write(priv, &pe); | |
3506 | ||
3507 | return 0; | |
3508 | } | |
3509 | ||
56beda3d MC |
3510 | /* Find tcam entry with matched pair <vid,port> */ |
3511 | static int mvpp2_prs_vid_range_find(struct mvpp2 *priv, int pmap, u16 vid, | |
3512 | u16 mask) | |
3513 | { | |
3514 | unsigned char byte[2], enable[2]; | |
3515 | struct mvpp2_prs_entry pe; | |
3516 | u16 rvid, rmask; | |
3517 | int tid; | |
3518 | ||
3519 | /* Go through the all entries with MVPP2_PRS_LU_VID */ | |
3520 | for (tid = MVPP2_PE_VID_FILT_RANGE_START; | |
3521 | tid <= MVPP2_PE_VID_FILT_RANGE_END; tid++) { | |
3522 | if (!priv->prs_shadow[tid].valid || | |
3523 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VID) | |
3524 | continue; | |
3525 | ||
3526 | pe.index = tid; | |
3527 | ||
3528 | mvpp2_prs_hw_read(priv, &pe); | |
3529 | mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]); | |
3530 | mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]); | |
3531 | ||
3532 | rvid = ((byte[0] & 0xf) << 8) + byte[1]; | |
3533 | rmask = ((enable[0] & 0xf) << 8) + enable[1]; | |
3534 | ||
3535 | if (rvid != vid || rmask != mask) | |
3536 | continue; | |
3537 | ||
3538 | return tid; | |
3539 | } | |
3540 | ||
3541 | return 0; | |
3542 | } | |
3543 | ||
3544 | /* Write parser entry for VID filtering */ | |
3545 | static int mvpp2_prs_vid_entry_add(struct mvpp2_port *port, u16 vid) | |
3546 | { | |
3547 | unsigned int vid_start = MVPP2_PE_VID_FILT_RANGE_START + | |
3548 | port->id * MVPP2_PRS_VLAN_FILT_MAX; | |
3549 | unsigned int mask = 0xfff, reg_val, shift; | |
3550 | struct mvpp2 *priv = port->priv; | |
3551 | struct mvpp2_prs_entry pe; | |
3552 | int tid; | |
3553 | ||
3554 | /* Scan TCAM and see if entry with this <vid,port> already exist */ | |
3555 | tid = mvpp2_prs_vid_range_find(priv, (1 << port->id), vid, mask); | |
3556 | ||
3557 | reg_val = mvpp2_read(priv, MVPP2_MH_REG(port->id)); | |
3558 | if (reg_val & MVPP2_DSA_EXTENDED) | |
3559 | shift = MVPP2_VLAN_TAG_EDSA_LEN; | |
3560 | else | |
3561 | shift = MVPP2_VLAN_TAG_LEN; | |
3562 | ||
3563 | /* No such entry */ | |
3564 | if (!tid) { | |
3565 | memset(&pe, 0, sizeof(pe)); | |
3566 | ||
3567 | /* Go through all entries from first to last in vlan range */ | |
3568 | tid = mvpp2_prs_tcam_first_free(priv, vid_start, | |
3569 | vid_start + | |
3570 | MVPP2_PRS_VLAN_FILT_MAX_ENTRY); | |
3571 | ||
3572 | /* There isn't room for a new VID filter */ | |
3573 | if (tid < 0) | |
3574 | return tid; | |
3575 | ||
3576 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); | |
3577 | pe.index = tid; | |
3578 | ||
3579 | /* Mask all ports */ | |
3580 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
3581 | } else { | |
3582 | mvpp2_prs_hw_read(priv, &pe); | |
3583 | } | |
3584 | ||
3585 | /* Enable the current port */ | |
3586 | mvpp2_prs_tcam_port_set(&pe, port->id, true); | |
3587 | ||
3588 | /* Continue - set next lookup */ | |
3589 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
3590 | ||
3591 | /* Skip VLAN header - Set offset to 4 or 8 bytes */ | |
3592 | mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3593 | ||
3594 | /* Set match on VID */ | |
3595 | mvpp2_prs_match_vid(&pe, MVPP2_PRS_VID_TCAM_BYTE, vid); | |
3596 | ||
3597 | /* Clear all ai bits for next iteration */ | |
3598 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
3599 | ||
3600 | /* Update shadow table */ | |
3601 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); | |
3602 | mvpp2_prs_hw_write(priv, &pe); | |
3603 | ||
3604 | return 0; | |
3605 | } | |
3606 | ||
3607 | /* Write parser entry for VID filtering */ | |
3608 | static void mvpp2_prs_vid_entry_remove(struct mvpp2_port *port, u16 vid) | |
3609 | { | |
3610 | struct mvpp2 *priv = port->priv; | |
3611 | int tid; | |
3612 | ||
3613 | /* Scan TCAM and see if entry with this <vid,port> already exist */ | |
3614 | tid = mvpp2_prs_vid_range_find(priv, (1 << port->id), vid, 0xfff); | |
3615 | ||
3616 | /* No such entry */ | |
3617 | if (tid) | |
3618 | return; | |
3619 | ||
3620 | mvpp2_prs_hw_inv(priv, tid); | |
3621 | priv->prs_shadow[tid].valid = false; | |
3622 | } | |
3623 | ||
3624 | /* Remove all existing VID filters on this port */ | |
3625 | static void mvpp2_prs_vid_remove_all(struct mvpp2_port *port) | |
3626 | { | |
3627 | struct mvpp2 *priv = port->priv; | |
3628 | int tid; | |
3629 | ||
3630 | for (tid = MVPP2_PRS_VID_PORT_FIRST(port->id); | |
3631 | tid <= MVPP2_PRS_VID_PORT_LAST(port->id); tid++) { | |
3632 | if (priv->prs_shadow[tid].valid) | |
3633 | mvpp2_prs_vid_entry_remove(port, tid); | |
3634 | } | |
3635 | } | |
3636 | ||
3637 | /* Remove VID filering entry for this port */ | |
3638 | static void mvpp2_prs_vid_disable_filtering(struct mvpp2_port *port) | |
3639 | { | |
3640 | unsigned int tid = MVPP2_PRS_VID_PORT_DFLT(port->id); | |
3641 | struct mvpp2 *priv = port->priv; | |
3642 | ||
3643 | /* Invalidate the guard entry */ | |
3644 | mvpp2_prs_hw_inv(priv, tid); | |
3645 | ||
3646 | priv->prs_shadow[tid].valid = false; | |
3647 | } | |
3648 | ||
3649 | /* Add guard entry that drops packets when no VID is matched on this port */ | |
3650 | static void mvpp2_prs_vid_enable_filtering(struct mvpp2_port *port) | |
3651 | { | |
3652 | unsigned int tid = MVPP2_PRS_VID_PORT_DFLT(port->id); | |
3653 | struct mvpp2 *priv = port->priv; | |
3654 | unsigned int reg_val, shift; | |
3655 | struct mvpp2_prs_entry pe; | |
3656 | ||
3657 | if (priv->prs_shadow[tid].valid) | |
3658 | return; | |
3659 | ||
3660 | memset(&pe, 0, sizeof(pe)); | |
3661 | ||
3662 | pe.index = tid; | |
3663 | ||
3664 | reg_val = mvpp2_read(priv, MVPP2_MH_REG(port->id)); | |
3665 | if (reg_val & MVPP2_DSA_EXTENDED) | |
3666 | shift = MVPP2_VLAN_TAG_EDSA_LEN; | |
3667 | else | |
3668 | shift = MVPP2_VLAN_TAG_LEN; | |
3669 | ||
3670 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); | |
3671 | ||
3672 | /* Mask all ports */ | |
3673 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
3674 | ||
3675 | /* Update port mask */ | |
3676 | mvpp2_prs_tcam_port_set(&pe, port->id, true); | |
3677 | ||
3678 | /* Continue - set next lookup */ | |
3679 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
3680 | ||
3681 | /* Skip VLAN header - Set offset to 4 or 8 bytes */ | |
3682 | mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3683 | ||
3684 | /* Drop VLAN packets that don't belong to any VIDs on this port */ | |
3685 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, | |
3686 | MVPP2_PRS_RI_DROP_MASK); | |
3687 | ||
3688 | /* Clear all ai bits for next iteration */ | |
3689 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
3690 | ||
3691 | /* Update shadow table */ | |
3692 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); | |
3693 | mvpp2_prs_hw_write(priv, &pe); | |
3694 | } | |
3695 | ||
3f518509 MW |
3696 | /* Parser default initialization */ |
3697 | static int mvpp2_prs_default_init(struct platform_device *pdev, | |
3698 | struct mvpp2 *priv) | |
3699 | { | |
3700 | int err, index, i; | |
3701 | ||
3702 | /* Enable tcam table */ | |
3703 | mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK); | |
3704 | ||
3705 | /* Clear all tcam and sram entries */ | |
3706 | for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) { | |
3707 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); | |
3708 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
3709 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0); | |
3710 | ||
3711 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index); | |
3712 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
3713 | mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); | |
3714 | } | |
3715 | ||
3716 | /* Invalidate all tcam entries */ | |
3717 | for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) | |
3718 | mvpp2_prs_hw_inv(priv, index); | |
3719 | ||
3720 | priv->prs_shadow = devm_kcalloc(&pdev->dev, MVPP2_PRS_TCAM_SRAM_SIZE, | |
37df25e8 | 3721 | sizeof(*priv->prs_shadow), |
3f518509 MW |
3722 | GFP_KERNEL); |
3723 | if (!priv->prs_shadow) | |
3724 | return -ENOMEM; | |
3725 | ||
3726 | /* Always start from lookup = 0 */ | |
3727 | for (index = 0; index < MVPP2_MAX_PORTS; index++) | |
3728 | mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH, | |
3729 | MVPP2_PRS_PORT_LU_MAX, 0); | |
3730 | ||
3731 | mvpp2_prs_def_flow_init(priv); | |
3732 | ||
3733 | mvpp2_prs_mh_init(priv); | |
3734 | ||
3735 | mvpp2_prs_mac_init(priv); | |
3736 | ||
3737 | mvpp2_prs_dsa_init(priv); | |
3738 | ||
56beda3d MC |
3739 | mvpp2_prs_vid_init(priv); |
3740 | ||
3f518509 MW |
3741 | err = mvpp2_prs_etype_init(priv); |
3742 | if (err) | |
3743 | return err; | |
3744 | ||
3745 | err = mvpp2_prs_vlan_init(pdev, priv); | |
3746 | if (err) | |
3747 | return err; | |
3748 | ||
3749 | err = mvpp2_prs_pppoe_init(priv); | |
3750 | if (err) | |
3751 | return err; | |
3752 | ||
3753 | err = mvpp2_prs_ip6_init(priv); | |
3754 | if (err) | |
3755 | return err; | |
3756 | ||
3757 | err = mvpp2_prs_ip4_init(priv); | |
3758 | if (err) | |
3759 | return err; | |
3760 | ||
3761 | return 0; | |
3762 | } | |
3763 | ||
3764 | /* Compare MAC DA with tcam entry data */ | |
3765 | static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, | |
3766 | const u8 *da, unsigned char *mask) | |
3767 | { | |
3768 | unsigned char tcam_byte, tcam_mask; | |
3769 | int index; | |
3770 | ||
3771 | for (index = 0; index < ETH_ALEN; index++) { | |
3772 | mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); | |
3773 | if (tcam_mask != mask[index]) | |
3774 | return false; | |
3775 | ||
3776 | if ((tcam_mask & tcam_byte) != (da[index] & mask[index])) | |
3777 | return false; | |
3778 | } | |
3779 | ||
3780 | return true; | |
3781 | } | |
3782 | ||
3783 | /* Find tcam entry with matched pair <MAC DA, port> */ | |
3784 | static struct mvpp2_prs_entry * | |
3785 | mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da, | |
3786 | unsigned char *mask, int udf_type) | |
3787 | { | |
3788 | struct mvpp2_prs_entry *pe; | |
3789 | int tid; | |
3790 | ||
239dd4ee | 3791 | pe = kzalloc(sizeof(*pe), GFP_ATOMIC); |
3f518509 MW |
3792 | if (!pe) |
3793 | return NULL; | |
3794 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); | |
3795 | ||
3796 | /* Go through the all entires with MVPP2_PRS_LU_MAC */ | |
3797 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
3798 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
3799 | unsigned int entry_pmap; | |
3800 | ||
3801 | if (!priv->prs_shadow[tid].valid || | |
3802 | (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || | |
3803 | (priv->prs_shadow[tid].udf != udf_type)) | |
3804 | continue; | |
3805 | ||
3806 | pe->index = tid; | |
3807 | mvpp2_prs_hw_read(priv, pe); | |
3808 | entry_pmap = mvpp2_prs_tcam_port_map_get(pe); | |
3809 | ||
3810 | if (mvpp2_prs_mac_range_equals(pe, da, mask) && | |
3811 | entry_pmap == pmap) | |
3812 | return pe; | |
3813 | } | |
3814 | kfree(pe); | |
3815 | ||
3816 | return NULL; | |
3817 | } | |
3818 | ||
3819 | /* Update parser's mac da entry */ | |
3820 | static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, | |
3821 | const u8 *da, bool add) | |
3822 | { | |
3823 | struct mvpp2_prs_entry *pe; | |
3824 | unsigned int pmap, len, ri; | |
3825 | unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
3826 | int tid; | |
3827 | ||
3828 | /* Scan TCAM and see if entry with this <MAC DA, port> already exist */ | |
3829 | pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, | |
3830 | MVPP2_PRS_UDF_MAC_DEF); | |
3831 | ||
3832 | /* No such entry */ | |
3833 | if (!pe) { | |
3834 | if (!add) | |
3835 | return 0; | |
3836 | ||
3837 | /* Create new TCAM entry */ | |
3838 | /* Find first range mac entry*/ | |
3839 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
3840 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) | |
3841 | if (priv->prs_shadow[tid].valid && | |
3842 | (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) && | |
3843 | (priv->prs_shadow[tid].udf == | |
3844 | MVPP2_PRS_UDF_MAC_RANGE)) | |
3845 | break; | |
3846 | ||
3847 | /* Go through the all entries from first to last */ | |
3848 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3849 | tid - 1); | |
3850 | if (tid < 0) | |
3851 | return tid; | |
3852 | ||
239dd4ee | 3853 | pe = kzalloc(sizeof(*pe), GFP_ATOMIC); |
3f518509 | 3854 | if (!pe) |
c2bb7bc5 | 3855 | return -ENOMEM; |
3f518509 MW |
3856 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); |
3857 | pe->index = tid; | |
3858 | ||
3859 | /* Mask all ports */ | |
3860 | mvpp2_prs_tcam_port_map_set(pe, 0); | |
3861 | } | |
3862 | ||
3863 | /* Update port mask */ | |
3864 | mvpp2_prs_tcam_port_set(pe, port, add); | |
3865 | ||
3866 | /* Invalidate the entry if no ports are left enabled */ | |
3867 | pmap = mvpp2_prs_tcam_port_map_get(pe); | |
3868 | if (pmap == 0) { | |
3869 | if (add) { | |
3870 | kfree(pe); | |
c2bb7bc5 | 3871 | return -EINVAL; |
3f518509 MW |
3872 | } |
3873 | mvpp2_prs_hw_inv(priv, pe->index); | |
3874 | priv->prs_shadow[pe->index].valid = false; | |
3875 | kfree(pe); | |
3876 | return 0; | |
3877 | } | |
3878 | ||
3879 | /* Continue - set next lookup */ | |
3880 | mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA); | |
3881 | ||
3882 | /* Set match on DA */ | |
3883 | len = ETH_ALEN; | |
3884 | while (len--) | |
3885 | mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff); | |
3886 | ||
3887 | /* Set result info bits */ | |
3888 | if (is_broadcast_ether_addr(da)) | |
3889 | ri = MVPP2_PRS_RI_L2_BCAST; | |
3890 | else if (is_multicast_ether_addr(da)) | |
3891 | ri = MVPP2_PRS_RI_L2_MCAST; | |
3892 | else | |
3893 | ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK; | |
3894 | ||
3895 | mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | | |
3896 | MVPP2_PRS_RI_MAC_ME_MASK); | |
3897 | mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | | |
3898 | MVPP2_PRS_RI_MAC_ME_MASK); | |
3899 | ||
3900 | /* Shift to ethertype */ | |
3901 | mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN, | |
3902 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3903 | ||
3904 | /* Update shadow table and hw entry */ | |
3905 | priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; | |
3906 | mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); | |
3907 | mvpp2_prs_hw_write(priv, pe); | |
3908 | ||
3909 | kfree(pe); | |
3910 | ||
3911 | return 0; | |
3912 | } | |
3913 | ||
3914 | static int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da) | |
3915 | { | |
3916 | struct mvpp2_port *port = netdev_priv(dev); | |
3917 | int err; | |
3918 | ||
3919 | /* Remove old parser entry */ | |
3920 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, dev->dev_addr, | |
3921 | false); | |
3922 | if (err) | |
3923 | return err; | |
3924 | ||
3925 | /* Add new parser entry */ | |
3926 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true); | |
3927 | if (err) | |
3928 | return err; | |
3929 | ||
3930 | /* Set addr in the device */ | |
3931 | ether_addr_copy(dev->dev_addr, da); | |
3932 | ||
3933 | return 0; | |
3934 | } | |
3935 | ||
3936 | /* Delete all port's multicast simple (not range) entries */ | |
3937 | static void mvpp2_prs_mcast_del_all(struct mvpp2 *priv, int port) | |
3938 | { | |
3939 | struct mvpp2_prs_entry pe; | |
3940 | int index, tid; | |
3941 | ||
3942 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
3943 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
3944 | unsigned char da[ETH_ALEN], da_mask[ETH_ALEN]; | |
3945 | ||
3946 | if (!priv->prs_shadow[tid].valid || | |
3947 | (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || | |
3948 | (priv->prs_shadow[tid].udf != MVPP2_PRS_UDF_MAC_DEF)) | |
3949 | continue; | |
3950 | ||
3951 | /* Only simple mac entries */ | |
3952 | pe.index = tid; | |
3953 | mvpp2_prs_hw_read(priv, &pe); | |
3954 | ||
3955 | /* Read mac addr from entry */ | |
3956 | for (index = 0; index < ETH_ALEN; index++) | |
3957 | mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], | |
3958 | &da_mask[index]); | |
3959 | ||
3960 | if (is_multicast_ether_addr(da) && !is_broadcast_ether_addr(da)) | |
3961 | /* Delete this entry */ | |
3962 | mvpp2_prs_mac_da_accept(priv, port, da, false); | |
3963 | } | |
3964 | } | |
3965 | ||
3966 | static int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type) | |
3967 | { | |
3968 | switch (type) { | |
3969 | case MVPP2_TAG_TYPE_EDSA: | |
3970 | /* Add port to EDSA entries */ | |
3971 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3972 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3973 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3974 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3975 | /* Remove port from DSA entries */ | |
3976 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3977 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3978 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3979 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3980 | break; | |
3981 | ||
3982 | case MVPP2_TAG_TYPE_DSA: | |
3983 | /* Add port to DSA entries */ | |
3984 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3985 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3986 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3987 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3988 | /* Remove port from EDSA entries */ | |
3989 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3990 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3991 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3992 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3993 | break; | |
3994 | ||
3995 | case MVPP2_TAG_TYPE_MH: | |
3996 | case MVPP2_TAG_TYPE_NONE: | |
3997 | /* Remove port form EDSA and DSA entries */ | |
3998 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3999 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
4000 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
4001 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
4002 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
4003 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
4004 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
4005 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
4006 | break; | |
4007 | ||
4008 | default: | |
4009 | if ((type < 0) || (type > MVPP2_TAG_TYPE_EDSA)) | |
4010 | return -EINVAL; | |
4011 | } | |
4012 | ||
4013 | return 0; | |
4014 | } | |
4015 | ||
4016 | /* Set prs flow for the port */ | |
4017 | static int mvpp2_prs_def_flow(struct mvpp2_port *port) | |
4018 | { | |
4019 | struct mvpp2_prs_entry *pe; | |
4020 | int tid; | |
4021 | ||
4022 | pe = mvpp2_prs_flow_find(port->priv, port->id); | |
4023 | ||
4024 | /* Such entry not exist */ | |
4025 | if (!pe) { | |
4026 | /* Go through the all entires from last to first */ | |
4027 | tid = mvpp2_prs_tcam_first_free(port->priv, | |
4028 | MVPP2_PE_LAST_FREE_TID, | |
4029 | MVPP2_PE_FIRST_FREE_TID); | |
4030 | if (tid < 0) | |
4031 | return tid; | |
4032 | ||
4033 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
4034 | if (!pe) | |
4035 | return -ENOMEM; | |
4036 | ||
4037 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); | |
4038 | pe->index = tid; | |
4039 | ||
4040 | /* Set flow ID*/ | |
4041 | mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); | |
4042 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); | |
4043 | ||
4044 | /* Update shadow table */ | |
4045 | mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); | |
4046 | } | |
4047 | ||
4048 | mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); | |
4049 | mvpp2_prs_hw_write(port->priv, pe); | |
4050 | kfree(pe); | |
4051 | ||
4052 | return 0; | |
4053 | } | |
4054 | ||
4055 | /* Classifier configuration routines */ | |
4056 | ||
4057 | /* Update classification flow table registers */ | |
4058 | static void mvpp2_cls_flow_write(struct mvpp2 *priv, | |
4059 | struct mvpp2_cls_flow_entry *fe) | |
4060 | { | |
4061 | mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); | |
4062 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); | |
4063 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); | |
4064 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); | |
4065 | } | |
4066 | ||
4067 | /* Update classification lookup table register */ | |
4068 | static void mvpp2_cls_lookup_write(struct mvpp2 *priv, | |
4069 | struct mvpp2_cls_lookup_entry *le) | |
4070 | { | |
4071 | u32 val; | |
4072 | ||
4073 | val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid; | |
4074 | mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); | |
4075 | mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); | |
4076 | } | |
4077 | ||
4078 | /* Classifier default initialization */ | |
4079 | static void mvpp2_cls_init(struct mvpp2 *priv) | |
4080 | { | |
4081 | struct mvpp2_cls_lookup_entry le; | |
4082 | struct mvpp2_cls_flow_entry fe; | |
4083 | int index; | |
4084 | ||
4085 | /* Enable classifier */ | |
4086 | mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK); | |
4087 | ||
4088 | /* Clear classifier flow table */ | |
e8f967c3 | 4089 | memset(&fe.data, 0, sizeof(fe.data)); |
3f518509 MW |
4090 | for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) { |
4091 | fe.index = index; | |
4092 | mvpp2_cls_flow_write(priv, &fe); | |
4093 | } | |
4094 | ||
4095 | /* Clear classifier lookup table */ | |
4096 | le.data = 0; | |
4097 | for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) { | |
4098 | le.lkpid = index; | |
4099 | le.way = 0; | |
4100 | mvpp2_cls_lookup_write(priv, &le); | |
4101 | ||
4102 | le.way = 1; | |
4103 | mvpp2_cls_lookup_write(priv, &le); | |
4104 | } | |
4105 | } | |
4106 | ||
4107 | static void mvpp2_cls_port_config(struct mvpp2_port *port) | |
4108 | { | |
4109 | struct mvpp2_cls_lookup_entry le; | |
4110 | u32 val; | |
4111 | ||
4112 | /* Set way for the port */ | |
4113 | val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); | |
4114 | val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); | |
4115 | mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); | |
4116 | ||
4117 | /* Pick the entry to be accessed in lookup ID decoding table | |
4118 | * according to the way and lkpid. | |
4119 | */ | |
4120 | le.lkpid = port->id; | |
4121 | le.way = 0; | |
4122 | le.data = 0; | |
4123 | ||
4124 | /* Set initial CPU queue for receiving packets */ | |
4125 | le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK; | |
4126 | le.data |= port->first_rxq; | |
4127 | ||
4128 | /* Disable classification engines */ | |
4129 | le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK; | |
4130 | ||
4131 | /* Update lookup ID table entry */ | |
4132 | mvpp2_cls_lookup_write(port->priv, &le); | |
4133 | } | |
4134 | ||
4135 | /* Set CPU queue number for oversize packets */ | |
4136 | static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) | |
4137 | { | |
4138 | u32 val; | |
4139 | ||
4140 | mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), | |
4141 | port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); | |
4142 | ||
4143 | mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), | |
4144 | (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); | |
4145 | ||
4146 | val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); | |
4147 | val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); | |
4148 | mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); | |
4149 | } | |
4150 | ||
0e037281 TP |
4151 | static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) |
4152 | { | |
4153 | if (likely(pool->frag_size <= PAGE_SIZE)) | |
4154 | return netdev_alloc_frag(pool->frag_size); | |
4155 | else | |
4156 | return kmalloc(pool->frag_size, GFP_ATOMIC); | |
4157 | } | |
4158 | ||
4159 | static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) | |
4160 | { | |
4161 | if (likely(pool->frag_size <= PAGE_SIZE)) | |
4162 | skb_free_frag(data); | |
4163 | else | |
4164 | kfree(data); | |
4165 | } | |
4166 | ||
3f518509 MW |
4167 | /* Buffer Manager configuration routines */ |
4168 | ||
4169 | /* Create pool */ | |
4170 | static int mvpp2_bm_pool_create(struct platform_device *pdev, | |
4171 | struct mvpp2 *priv, | |
4172 | struct mvpp2_bm_pool *bm_pool, int size) | |
4173 | { | |
3f518509 MW |
4174 | u32 val; |
4175 | ||
d01524d8 TP |
4176 | /* Number of buffer pointers must be a multiple of 16, as per |
4177 | * hardware constraints | |
4178 | */ | |
4179 | if (!IS_ALIGNED(size, 16)) | |
4180 | return -EINVAL; | |
4181 | ||
4182 | /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 | |
4183 | * bytes per buffer pointer | |
4184 | */ | |
4185 | if (priv->hw_version == MVPP21) | |
4186 | bm_pool->size_bytes = 2 * sizeof(u32) * size; | |
4187 | else | |
4188 | bm_pool->size_bytes = 2 * sizeof(u64) * size; | |
4189 | ||
4190 | bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, | |
20396136 | 4191 | &bm_pool->dma_addr, |
3f518509 MW |
4192 | GFP_KERNEL); |
4193 | if (!bm_pool->virt_addr) | |
4194 | return -ENOMEM; | |
4195 | ||
d3158807 TP |
4196 | if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, |
4197 | MVPP2_BM_POOL_PTR_ALIGN)) { | |
d01524d8 TP |
4198 | dma_free_coherent(&pdev->dev, bm_pool->size_bytes, |
4199 | bm_pool->virt_addr, bm_pool->dma_addr); | |
3f518509 MW |
4200 | dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", |
4201 | bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); | |
4202 | return -ENOMEM; | |
4203 | } | |
4204 | ||
4205 | mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), | |
d01524d8 | 4206 | lower_32_bits(bm_pool->dma_addr)); |
3f518509 MW |
4207 | mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); |
4208 | ||
4209 | val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); | |
4210 | val |= MVPP2_BM_START_MASK; | |
4211 | mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); | |
4212 | ||
3f518509 MW |
4213 | bm_pool->size = size; |
4214 | bm_pool->pkt_size = 0; | |
4215 | bm_pool->buf_num = 0; | |
3f518509 MW |
4216 | |
4217 | return 0; | |
4218 | } | |
4219 | ||
4220 | /* Set pool buffer size */ | |
4221 | static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, | |
4222 | struct mvpp2_bm_pool *bm_pool, | |
4223 | int buf_size) | |
4224 | { | |
4225 | u32 val; | |
4226 | ||
4227 | bm_pool->buf_size = buf_size; | |
4228 | ||
4229 | val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); | |
4230 | mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); | |
4231 | } | |
4232 | ||
d01524d8 TP |
4233 | static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, |
4234 | struct mvpp2_bm_pool *bm_pool, | |
4235 | dma_addr_t *dma_addr, | |
4236 | phys_addr_t *phys_addr) | |
4237 | { | |
a704bb5c | 4238 | int cpu = get_cpu(); |
a786841d TP |
4239 | |
4240 | *dma_addr = mvpp2_percpu_read(priv, cpu, | |
4241 | MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); | |
4242 | *phys_addr = mvpp2_percpu_read(priv, cpu, MVPP2_BM_VIRT_ALLOC_REG); | |
d01524d8 TP |
4243 | |
4244 | if (priv->hw_version == MVPP22) { | |
4245 | u32 val; | |
4246 | u32 dma_addr_highbits, phys_addr_highbits; | |
4247 | ||
a786841d | 4248 | val = mvpp2_percpu_read(priv, cpu, MVPP22_BM_ADDR_HIGH_ALLOC); |
d01524d8 TP |
4249 | dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); |
4250 | phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> | |
4251 | MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; | |
4252 | ||
4253 | if (sizeof(dma_addr_t) == 8) | |
4254 | *dma_addr |= (u64)dma_addr_highbits << 32; | |
4255 | ||
4256 | if (sizeof(phys_addr_t) == 8) | |
4257 | *phys_addr |= (u64)phys_addr_highbits << 32; | |
4258 | } | |
a704bb5c TP |
4259 | |
4260 | put_cpu(); | |
d01524d8 TP |
4261 | } |
4262 | ||
7861f12b | 4263 | /* Free all buffers from the pool */ |
4229d502 | 4264 | static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, |
effbf5f5 | 4265 | struct mvpp2_bm_pool *bm_pool, int buf_num) |
3f518509 MW |
4266 | { |
4267 | int i; | |
4268 | ||
effbf5f5 SC |
4269 | if (buf_num > bm_pool->buf_num) { |
4270 | WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", | |
4271 | bm_pool->id, buf_num); | |
4272 | buf_num = bm_pool->buf_num; | |
4273 | } | |
4274 | ||
4275 | for (i = 0; i < buf_num; i++) { | |
20396136 | 4276 | dma_addr_t buf_dma_addr; |
4e4a105f TP |
4277 | phys_addr_t buf_phys_addr; |
4278 | void *data; | |
3f518509 | 4279 | |
d01524d8 TP |
4280 | mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, |
4281 | &buf_dma_addr, &buf_phys_addr); | |
4229d502 | 4282 | |
20396136 | 4283 | dma_unmap_single(dev, buf_dma_addr, |
4229d502 MW |
4284 | bm_pool->buf_size, DMA_FROM_DEVICE); |
4285 | ||
4e4a105f TP |
4286 | data = (void *)phys_to_virt(buf_phys_addr); |
4287 | if (!data) | |
3f518509 | 4288 | break; |
0e037281 | 4289 | |
4e4a105f | 4290 | mvpp2_frag_free(bm_pool, data); |
3f518509 MW |
4291 | } |
4292 | ||
4293 | /* Update BM driver with number of buffers removed from pool */ | |
4294 | bm_pool->buf_num -= i; | |
3f518509 MW |
4295 | } |
4296 | ||
effbf5f5 | 4297 | /* Check number of buffers in BM pool */ |
6e61e10a | 4298 | static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) |
effbf5f5 SC |
4299 | { |
4300 | int buf_num = 0; | |
4301 | ||
4302 | buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & | |
4303 | MVPP22_BM_POOL_PTRS_NUM_MASK; | |
4304 | buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & | |
4305 | MVPP2_BM_BPPI_PTR_NUM_MASK; | |
4306 | ||
4307 | /* HW has one buffer ready which is not reflected in the counters */ | |
4308 | if (buf_num) | |
4309 | buf_num += 1; | |
4310 | ||
4311 | return buf_num; | |
4312 | } | |
4313 | ||
3f518509 MW |
4314 | /* Cleanup pool */ |
4315 | static int mvpp2_bm_pool_destroy(struct platform_device *pdev, | |
4316 | struct mvpp2 *priv, | |
4317 | struct mvpp2_bm_pool *bm_pool) | |
4318 | { | |
effbf5f5 | 4319 | int buf_num; |
3f518509 MW |
4320 | u32 val; |
4321 | ||
effbf5f5 SC |
4322 | buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); |
4323 | mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num); | |
4324 | ||
4325 | /* Check buffer counters after free */ | |
4326 | buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); | |
4327 | if (buf_num) { | |
4328 | WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", | |
4329 | bm_pool->id, bm_pool->buf_num); | |
3f518509 MW |
4330 | return 0; |
4331 | } | |
4332 | ||
4333 | val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); | |
4334 | val |= MVPP2_BM_STOP_MASK; | |
4335 | mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); | |
4336 | ||
d01524d8 | 4337 | dma_free_coherent(&pdev->dev, bm_pool->size_bytes, |
3f518509 | 4338 | bm_pool->virt_addr, |
20396136 | 4339 | bm_pool->dma_addr); |
3f518509 MW |
4340 | return 0; |
4341 | } | |
4342 | ||
4343 | static int mvpp2_bm_pools_init(struct platform_device *pdev, | |
4344 | struct mvpp2 *priv) | |
4345 | { | |
4346 | int i, err, size; | |
4347 | struct mvpp2_bm_pool *bm_pool; | |
4348 | ||
4349 | /* Create all pools with maximum size */ | |
4350 | size = MVPP2_BM_POOL_SIZE_MAX; | |
4351 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
4352 | bm_pool = &priv->bm_pools[i]; | |
4353 | bm_pool->id = i; | |
4354 | err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); | |
4355 | if (err) | |
4356 | goto err_unroll_pools; | |
4357 | mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); | |
4358 | } | |
4359 | return 0; | |
4360 | ||
4361 | err_unroll_pools: | |
4362 | dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); | |
4363 | for (i = i - 1; i >= 0; i--) | |
4364 | mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); | |
4365 | return err; | |
4366 | } | |
4367 | ||
4368 | static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) | |
4369 | { | |
4370 | int i, err; | |
4371 | ||
4372 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
4373 | /* Mask BM all interrupts */ | |
4374 | mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); | |
4375 | /* Clear BM cause register */ | |
4376 | mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); | |
4377 | } | |
4378 | ||
4379 | /* Allocate and initialize BM pools */ | |
4380 | priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, | |
81f915eb | 4381 | sizeof(*priv->bm_pools), GFP_KERNEL); |
3f518509 MW |
4382 | if (!priv->bm_pools) |
4383 | return -ENOMEM; | |
4384 | ||
4385 | err = mvpp2_bm_pools_init(pdev, priv); | |
4386 | if (err < 0) | |
4387 | return err; | |
4388 | return 0; | |
4389 | } | |
4390 | ||
01d04936 SC |
4391 | static void mvpp2_setup_bm_pool(void) |
4392 | { | |
4393 | /* Short pool */ | |
4394 | mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; | |
4395 | mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; | |
4396 | ||
4397 | /* Long pool */ | |
4398 | mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; | |
4399 | mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; | |
576193f2 SC |
4400 | |
4401 | /* Jumbo pool */ | |
4402 | mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; | |
4403 | mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; | |
01d04936 SC |
4404 | } |
4405 | ||
3f518509 MW |
4406 | /* Attach long pool to rxq */ |
4407 | static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, | |
4408 | int lrxq, int long_pool) | |
4409 | { | |
5eac892a | 4410 | u32 val, mask; |
3f518509 MW |
4411 | int prxq; |
4412 | ||
4413 | /* Get queue physical ID */ | |
4414 | prxq = port->rxqs[lrxq]->id; | |
4415 | ||
5eac892a TP |
4416 | if (port->priv->hw_version == MVPP21) |
4417 | mask = MVPP21_RXQ_POOL_LONG_MASK; | |
4418 | else | |
4419 | mask = MVPP22_RXQ_POOL_LONG_MASK; | |
3f518509 | 4420 | |
5eac892a TP |
4421 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); |
4422 | val &= ~mask; | |
4423 | val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; | |
3f518509 MW |
4424 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); |
4425 | } | |
4426 | ||
4427 | /* Attach short pool to rxq */ | |
4428 | static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, | |
4429 | int lrxq, int short_pool) | |
4430 | { | |
5eac892a | 4431 | u32 val, mask; |
3f518509 MW |
4432 | int prxq; |
4433 | ||
4434 | /* Get queue physical ID */ | |
4435 | prxq = port->rxqs[lrxq]->id; | |
4436 | ||
5eac892a TP |
4437 | if (port->priv->hw_version == MVPP21) |
4438 | mask = MVPP21_RXQ_POOL_SHORT_MASK; | |
4439 | else | |
4440 | mask = MVPP22_RXQ_POOL_SHORT_MASK; | |
3f518509 | 4441 | |
5eac892a TP |
4442 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); |
4443 | val &= ~mask; | |
4444 | val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; | |
3f518509 MW |
4445 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); |
4446 | } | |
4447 | ||
0e037281 TP |
4448 | static void *mvpp2_buf_alloc(struct mvpp2_port *port, |
4449 | struct mvpp2_bm_pool *bm_pool, | |
20396136 | 4450 | dma_addr_t *buf_dma_addr, |
4e4a105f | 4451 | phys_addr_t *buf_phys_addr, |
0e037281 | 4452 | gfp_t gfp_mask) |
3f518509 | 4453 | { |
20396136 | 4454 | dma_addr_t dma_addr; |
0e037281 | 4455 | void *data; |
3f518509 | 4456 | |
0e037281 TP |
4457 | data = mvpp2_frag_alloc(bm_pool); |
4458 | if (!data) | |
3f518509 MW |
4459 | return NULL; |
4460 | ||
20396136 TP |
4461 | dma_addr = dma_map_single(port->dev->dev.parent, data, |
4462 | MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), | |
4463 | DMA_FROM_DEVICE); | |
4464 | if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { | |
0e037281 | 4465 | mvpp2_frag_free(bm_pool, data); |
3f518509 MW |
4466 | return NULL; |
4467 | } | |
20396136 | 4468 | *buf_dma_addr = dma_addr; |
4e4a105f | 4469 | *buf_phys_addr = virt_to_phys(data); |
3f518509 | 4470 | |
0e037281 | 4471 | return data; |
3f518509 MW |
4472 | } |
4473 | ||
3f518509 MW |
4474 | /* Release buffer to BM */ |
4475 | static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, | |
20396136 | 4476 | dma_addr_t buf_dma_addr, |
4e4a105f | 4477 | phys_addr_t buf_phys_addr) |
3f518509 | 4478 | { |
a704bb5c | 4479 | int cpu = get_cpu(); |
a786841d | 4480 | |
d01524d8 TP |
4481 | if (port->priv->hw_version == MVPP22) { |
4482 | u32 val = 0; | |
4483 | ||
4484 | if (sizeof(dma_addr_t) == 8) | |
4485 | val |= upper_32_bits(buf_dma_addr) & | |
4486 | MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; | |
4487 | ||
4488 | if (sizeof(phys_addr_t) == 8) | |
4489 | val |= (upper_32_bits(buf_phys_addr) | |
4490 | << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & | |
4491 | MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; | |
4492 | ||
a786841d TP |
4493 | mvpp2_percpu_write(port->priv, cpu, |
4494 | MVPP22_BM_ADDR_HIGH_RLS_REG, val); | |
d01524d8 TP |
4495 | } |
4496 | ||
4e4a105f TP |
4497 | /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply |
4498 | * returned in the "cookie" field of the RX | |
4499 | * descriptor. Instead of storing the virtual address, we | |
4500 | * store the physical address | |
4501 | */ | |
a786841d TP |
4502 | mvpp2_percpu_write(port->priv, cpu, |
4503 | MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); | |
4504 | mvpp2_percpu_write(port->priv, cpu, | |
4505 | MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); | |
a704bb5c TP |
4506 | |
4507 | put_cpu(); | |
3f518509 MW |
4508 | } |
4509 | ||
3f518509 MW |
4510 | /* Allocate buffers for the pool */ |
4511 | static int mvpp2_bm_bufs_add(struct mvpp2_port *port, | |
4512 | struct mvpp2_bm_pool *bm_pool, int buf_num) | |
4513 | { | |
3f518509 | 4514 | int i, buf_size, total_size; |
20396136 | 4515 | dma_addr_t dma_addr; |
4e4a105f | 4516 | phys_addr_t phys_addr; |
0e037281 | 4517 | void *buf; |
3f518509 MW |
4518 | |
4519 | buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); | |
4520 | total_size = MVPP2_RX_TOTAL_SIZE(buf_size); | |
4521 | ||
4522 | if (buf_num < 0 || | |
4523 | (buf_num + bm_pool->buf_num > bm_pool->size)) { | |
4524 | netdev_err(port->dev, | |
4525 | "cannot allocate %d buffers for pool %d\n", | |
4526 | buf_num, bm_pool->id); | |
4527 | return 0; | |
4528 | } | |
4529 | ||
3f518509 | 4530 | for (i = 0; i < buf_num; i++) { |
4e4a105f TP |
4531 | buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, |
4532 | &phys_addr, GFP_KERNEL); | |
0e037281 | 4533 | if (!buf) |
3f518509 MW |
4534 | break; |
4535 | ||
20396136 | 4536 | mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, |
4e4a105f | 4537 | phys_addr); |
3f518509 MW |
4538 | } |
4539 | ||
4540 | /* Update BM driver with number of buffers added to pool */ | |
4541 | bm_pool->buf_num += i; | |
3f518509 MW |
4542 | |
4543 | netdev_dbg(port->dev, | |
01d04936 | 4544 | "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", |
3f518509 MW |
4545 | bm_pool->id, bm_pool->pkt_size, buf_size, total_size); |
4546 | ||
4547 | netdev_dbg(port->dev, | |
01d04936 | 4548 | "pool %d: %d of %d buffers added\n", |
3f518509 MW |
4549 | bm_pool->id, i, buf_num); |
4550 | return i; | |
4551 | } | |
4552 | ||
4553 | /* Notify the driver that BM pool is being used as specific type and return the | |
4554 | * pool pointer on success | |
4555 | */ | |
4556 | static struct mvpp2_bm_pool * | |
01d04936 | 4557 | mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) |
3f518509 | 4558 | { |
3f518509 MW |
4559 | struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; |
4560 | int num; | |
4561 | ||
01d04936 SC |
4562 | if (pool >= MVPP2_BM_POOLS_NUM) { |
4563 | netdev_err(port->dev, "Invalid pool %d\n", pool); | |
3f518509 MW |
4564 | return NULL; |
4565 | } | |
4566 | ||
3f518509 MW |
4567 | /* Allocate buffers in case BM pool is used as long pool, but packet |
4568 | * size doesn't match MTU or BM pool hasn't being used yet | |
4569 | */ | |
01d04936 | 4570 | if (new_pool->pkt_size == 0) { |
3f518509 MW |
4571 | int pkts_num; |
4572 | ||
4573 | /* Set default buffer number or free all the buffers in case | |
4574 | * the pool is not empty | |
4575 | */ | |
4576 | pkts_num = new_pool->buf_num; | |
4577 | if (pkts_num == 0) | |
01d04936 | 4578 | pkts_num = mvpp2_pools[pool].buf_num; |
3f518509 | 4579 | else |
4229d502 | 4580 | mvpp2_bm_bufs_free(port->dev->dev.parent, |
effbf5f5 | 4581 | port->priv, new_pool, pkts_num); |
3f518509 MW |
4582 | |
4583 | new_pool->pkt_size = pkt_size; | |
0e037281 TP |
4584 | new_pool->frag_size = |
4585 | SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + | |
4586 | MVPP2_SKB_SHINFO_SIZE; | |
3f518509 MW |
4587 | |
4588 | /* Allocate buffers for this pool */ | |
4589 | num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); | |
4590 | if (num != pkts_num) { | |
4591 | WARN(1, "pool %d: %d of %d allocated\n", | |
4592 | new_pool->id, num, pkts_num); | |
3f518509 MW |
4593 | return NULL; |
4594 | } | |
4595 | } | |
4596 | ||
4597 | mvpp2_bm_pool_bufsize_set(port->priv, new_pool, | |
4598 | MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); | |
4599 | ||
3f518509 MW |
4600 | return new_pool; |
4601 | } | |
4602 | ||
4603 | /* Initialize pools for swf */ | |
4604 | static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) | |
4605 | { | |
3f518509 | 4606 | int rxq; |
576193f2 SC |
4607 | enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; |
4608 | ||
4609 | /* If port pkt_size is higher than 1518B: | |
4610 | * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool | |
4611 | * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool | |
4612 | */ | |
4613 | if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { | |
4614 | long_log_pool = MVPP2_BM_JUMBO; | |
4615 | short_log_pool = MVPP2_BM_LONG; | |
4616 | } else { | |
4617 | long_log_pool = MVPP2_BM_LONG; | |
4618 | short_log_pool = MVPP2_BM_SHORT; | |
4619 | } | |
3f518509 MW |
4620 | |
4621 | if (!port->pool_long) { | |
4622 | port->pool_long = | |
576193f2 SC |
4623 | mvpp2_bm_pool_use(port, long_log_pool, |
4624 | mvpp2_pools[long_log_pool].pkt_size); | |
3f518509 MW |
4625 | if (!port->pool_long) |
4626 | return -ENOMEM; | |
4627 | ||
576193f2 | 4628 | port->pool_long->port_map |= BIT(port->id); |
3f518509 | 4629 | |
09f83975 | 4630 | for (rxq = 0; rxq < port->nrxqs; rxq++) |
3f518509 MW |
4631 | mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); |
4632 | } | |
4633 | ||
4634 | if (!port->pool_short) { | |
4635 | port->pool_short = | |
576193f2 SC |
4636 | mvpp2_bm_pool_use(port, short_log_pool, |
4637 | mvpp2_pools[long_log_pool].pkt_size); | |
3f518509 MW |
4638 | if (!port->pool_short) |
4639 | return -ENOMEM; | |
4640 | ||
576193f2 | 4641 | port->pool_short->port_map |= BIT(port->id); |
3f518509 | 4642 | |
09f83975 | 4643 | for (rxq = 0; rxq < port->nrxqs; rxq++) |
3f518509 MW |
4644 | mvpp2_rxq_short_pool_set(port, rxq, |
4645 | port->pool_short->id); | |
4646 | } | |
4647 | ||
4648 | return 0; | |
4649 | } | |
4650 | ||
4651 | static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) | |
4652 | { | |
4653 | struct mvpp2_port *port = netdev_priv(dev); | |
576193f2 SC |
4654 | enum mvpp2_bm_pool_log_num new_long_pool; |
4655 | int pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
3f518509 | 4656 | |
576193f2 SC |
4657 | /* If port MTU is higher than 1518B: |
4658 | * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool | |
4659 | * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool | |
4660 | */ | |
4661 | if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) | |
4662 | new_long_pool = MVPP2_BM_JUMBO; | |
4663 | else | |
4664 | new_long_pool = MVPP2_BM_LONG; | |
4665 | ||
4666 | if (new_long_pool != port->pool_long->id) { | |
4667 | /* Remove port from old short & long pool */ | |
4668 | port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, | |
4669 | port->pool_long->pkt_size); | |
4670 | port->pool_long->port_map &= ~BIT(port->id); | |
4671 | port->pool_long = NULL; | |
4672 | ||
4673 | port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, | |
4674 | port->pool_short->pkt_size); | |
4675 | port->pool_short->port_map &= ~BIT(port->id); | |
4676 | port->pool_short = NULL; | |
4677 | ||
4678 | port->pkt_size = pkt_size; | |
4679 | ||
4680 | /* Add port to new short & long pool */ | |
4681 | mvpp2_swf_bm_pool_init(port); | |
4682 | ||
4683 | /* Update L4 checksum when jumbo enable/disable on port */ | |
4684 | if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { | |
4685 | dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); | |
4686 | dev->hw_features &= ~(NETIF_F_IP_CSUM | | |
4687 | NETIF_F_IPV6_CSUM); | |
4688 | } else { | |
4689 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; | |
4690 | dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; | |
4691 | } | |
3f518509 MW |
4692 | } |
4693 | ||
3f518509 | 4694 | dev->mtu = mtu; |
576193f2 SC |
4695 | dev->wanted_features = dev->features; |
4696 | ||
3f518509 MW |
4697 | netdev_update_features(dev); |
4698 | return 0; | |
4699 | } | |
4700 | ||
4701 | static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) | |
4702 | { | |
591f4cfa TP |
4703 | int i, sw_thread_mask = 0; |
4704 | ||
4705 | for (i = 0; i < port->nqvecs; i++) | |
4706 | sw_thread_mask |= port->qvecs[i].sw_thread_mask; | |
3f518509 | 4707 | |
3f518509 | 4708 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), |
591f4cfa | 4709 | MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); |
3f518509 MW |
4710 | } |
4711 | ||
4712 | static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) | |
4713 | { | |
591f4cfa TP |
4714 | int i, sw_thread_mask = 0; |
4715 | ||
4716 | for (i = 0; i < port->nqvecs; i++) | |
4717 | sw_thread_mask |= port->qvecs[i].sw_thread_mask; | |
4718 | ||
4719 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), | |
4720 | MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); | |
4721 | } | |
4722 | ||
4723 | static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) | |
4724 | { | |
4725 | struct mvpp2_port *port = qvec->port; | |
3f518509 | 4726 | |
3f518509 | 4727 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), |
591f4cfa TP |
4728 | MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); |
4729 | } | |
4730 | ||
4731 | static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) | |
4732 | { | |
4733 | struct mvpp2_port *port = qvec->port; | |
4734 | ||
4735 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), | |
4736 | MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); | |
3f518509 MW |
4737 | } |
4738 | ||
e0af22d9 TP |
4739 | /* Mask the current CPU's Rx/Tx interrupts |
4740 | * Called by on_each_cpu(), guaranteed to run with migration disabled, | |
4741 | * using smp_processor_id() is OK. | |
4742 | */ | |
3f518509 MW |
4743 | static void mvpp2_interrupts_mask(void *arg) |
4744 | { | |
4745 | struct mvpp2_port *port = arg; | |
4746 | ||
a786841d TP |
4747 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
4748 | MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); | |
3f518509 MW |
4749 | } |
4750 | ||
e0af22d9 TP |
4751 | /* Unmask the current CPU's Rx/Tx interrupts. |
4752 | * Called by on_each_cpu(), guaranteed to run with migration disabled, | |
4753 | * using smp_processor_id() is OK. | |
4754 | */ | |
3f518509 MW |
4755 | static void mvpp2_interrupts_unmask(void *arg) |
4756 | { | |
4757 | struct mvpp2_port *port = arg; | |
213f428f TP |
4758 | u32 val; |
4759 | ||
4760 | val = MVPP2_CAUSE_MISC_SUM_MASK | | |
4761 | MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; | |
4762 | if (port->has_tx_irqs) | |
4763 | val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; | |
3f518509 | 4764 | |
a786841d | 4765 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
213f428f TP |
4766 | MVPP2_ISR_RX_TX_MASK_REG(port->id), val); |
4767 | } | |
4768 | ||
4769 | static void | |
4770 | mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) | |
4771 | { | |
4772 | u32 val; | |
4773 | int i; | |
4774 | ||
4775 | if (port->priv->hw_version != MVPP22) | |
4776 | return; | |
4777 | ||
4778 | if (mask) | |
4779 | val = 0; | |
4780 | else | |
4781 | val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; | |
4782 | ||
4783 | for (i = 0; i < port->nqvecs; i++) { | |
4784 | struct mvpp2_queue_vector *v = port->qvecs + i; | |
4785 | ||
4786 | if (v->type != MVPP2_QUEUE_VECTOR_SHARED) | |
4787 | continue; | |
4788 | ||
4789 | mvpp2_percpu_write(port->priv, v->sw_thread_id, | |
4790 | MVPP2_ISR_RX_TX_MASK_REG(port->id), val); | |
4791 | } | |
3f518509 MW |
4792 | } |
4793 | ||
4794 | /* Port configuration routines */ | |
4795 | ||
f84bf386 AT |
4796 | static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) |
4797 | { | |
4798 | struct mvpp2 *priv = port->priv; | |
4799 | u32 val; | |
4800 | ||
4801 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); | |
4802 | val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; | |
4803 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); | |
4804 | ||
4805 | regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); | |
4806 | if (port->gop_id == 2) | |
4807 | val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; | |
4808 | else if (port->gop_id == 3) | |
4809 | val |= GENCONF_CTRL0_PORT1_RGMII_MII; | |
4810 | regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); | |
4811 | } | |
4812 | ||
4813 | static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) | |
4814 | { | |
4815 | struct mvpp2 *priv = port->priv; | |
4816 | u32 val; | |
4817 | ||
4818 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); | |
4819 | val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | | |
4820 | GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; | |
4821 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); | |
4822 | ||
4823 | if (port->gop_id > 1) { | |
4824 | regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); | |
4825 | if (port->gop_id == 2) | |
4826 | val &= ~GENCONF_CTRL0_PORT0_RGMII; | |
4827 | else if (port->gop_id == 3) | |
4828 | val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; | |
4829 | regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); | |
4830 | } | |
4831 | } | |
4832 | ||
4833 | static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) | |
4834 | { | |
4835 | struct mvpp2 *priv = port->priv; | |
4836 | void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); | |
4837 | void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); | |
4838 | u32 val; | |
4839 | ||
4840 | /* XPCS */ | |
4841 | val = readl(xpcs + MVPP22_XPCS_CFG0); | |
4842 | val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | | |
4843 | MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); | |
4844 | val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); | |
4845 | writel(val, xpcs + MVPP22_XPCS_CFG0); | |
4846 | ||
4847 | /* MPCS */ | |
4848 | val = readl(mpcs + MVPP22_MPCS_CTRL); | |
4849 | val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; | |
4850 | writel(val, mpcs + MVPP22_MPCS_CTRL); | |
4851 | ||
4852 | val = readl(mpcs + MVPP22_MPCS_CLK_RESET); | |
4853 | val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC | | |
4854 | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); | |
4855 | val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); | |
4856 | writel(val, mpcs + MVPP22_MPCS_CLK_RESET); | |
4857 | ||
4858 | val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; | |
4859 | val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX; | |
4860 | writel(val, mpcs + MVPP22_MPCS_CLK_RESET); | |
4861 | } | |
4862 | ||
4863 | static int mvpp22_gop_init(struct mvpp2_port *port) | |
4864 | { | |
4865 | struct mvpp2 *priv = port->priv; | |
4866 | u32 val; | |
4867 | ||
4868 | if (!priv->sysctrl_base) | |
4869 | return 0; | |
4870 | ||
4871 | switch (port->phy_interface) { | |
4872 | case PHY_INTERFACE_MODE_RGMII: | |
4873 | case PHY_INTERFACE_MODE_RGMII_ID: | |
4874 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
4875 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
4876 | if (port->gop_id == 0) | |
4877 | goto invalid_conf; | |
4878 | mvpp22_gop_init_rgmii(port); | |
4879 | break; | |
4880 | case PHY_INTERFACE_MODE_SGMII: | |
4881 | mvpp22_gop_init_sgmii(port); | |
4882 | break; | |
4883 | case PHY_INTERFACE_MODE_10GKR: | |
4884 | if (port->gop_id != 0) | |
4885 | goto invalid_conf; | |
4886 | mvpp22_gop_init_10gkr(port); | |
4887 | break; | |
4888 | default: | |
4889 | goto unsupported_conf; | |
4890 | } | |
4891 | ||
4892 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); | |
4893 | val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | | |
4894 | GENCONF_PORT_CTRL1_EN(port->gop_id); | |
4895 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); | |
4896 | ||
4897 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); | |
4898 | val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; | |
4899 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); | |
4900 | ||
4901 | regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); | |
4902 | val |= GENCONF_SOFT_RESET1_GOP; | |
4903 | regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); | |
4904 | ||
4905 | unsupported_conf: | |
4906 | return 0; | |
4907 | ||
4908 | invalid_conf: | |
4909 | netdev_err(port->dev, "Invalid port configuration\n"); | |
4910 | return -EINVAL; | |
4911 | } | |
4912 | ||
fd3651b2 AT |
4913 | static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) |
4914 | { | |
4915 | u32 val; | |
4916 | ||
4917 | if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
4918 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4919 | /* Enable the GMAC link status irq for this port */ | |
4920 | val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4921 | val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; | |
4922 | writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4923 | } | |
4924 | ||
4925 | if (port->gop_id == 0) { | |
4926 | /* Enable the XLG/GIG irqs for this port */ | |
4927 | val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); | |
4928 | if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) | |
4929 | val |= MVPP22_XLG_EXT_INT_MASK_XLG; | |
4930 | else | |
4931 | val |= MVPP22_XLG_EXT_INT_MASK_GIG; | |
4932 | writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); | |
4933 | } | |
4934 | } | |
4935 | ||
4936 | static void mvpp22_gop_mask_irq(struct mvpp2_port *port) | |
4937 | { | |
4938 | u32 val; | |
4939 | ||
4940 | if (port->gop_id == 0) { | |
4941 | val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); | |
4942 | val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | | |
4943 | MVPP22_XLG_EXT_INT_MASK_GIG); | |
4944 | writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); | |
4945 | } | |
4946 | ||
4947 | if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
4948 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4949 | val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4950 | val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; | |
4951 | writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4952 | } | |
4953 | } | |
4954 | ||
4955 | static void mvpp22_gop_setup_irq(struct mvpp2_port *port) | |
4956 | { | |
4957 | u32 val; | |
4958 | ||
4959 | if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
4960 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4961 | val = readl(port->base + MVPP22_GMAC_INT_MASK); | |
4962 | val |= MVPP22_GMAC_INT_MASK_LINK_STAT; | |
4963 | writel(val, port->base + MVPP22_GMAC_INT_MASK); | |
4964 | } | |
4965 | ||
4966 | if (port->gop_id == 0) { | |
4967 | val = readl(port->base + MVPP22_XLG_INT_MASK); | |
4968 | val |= MVPP22_XLG_INT_MASK_LINK; | |
4969 | writel(val, port->base + MVPP22_XLG_INT_MASK); | |
4970 | } | |
4971 | ||
4972 | mvpp22_gop_unmask_irq(port); | |
4973 | } | |
4974 | ||
542897d9 AT |
4975 | static int mvpp22_comphy_init(struct mvpp2_port *port) |
4976 | { | |
4977 | enum phy_mode mode; | |
4978 | int ret; | |
4979 | ||
4980 | if (!port->comphy) | |
4981 | return 0; | |
4982 | ||
4983 | switch (port->phy_interface) { | |
4984 | case PHY_INTERFACE_MODE_SGMII: | |
4985 | mode = PHY_MODE_SGMII; | |
4986 | break; | |
4987 | case PHY_INTERFACE_MODE_10GKR: | |
4988 | mode = PHY_MODE_10GKR; | |
4989 | break; | |
4990 | default: | |
4991 | return -EINVAL; | |
4992 | } | |
4993 | ||
4994 | ret = phy_set_mode(port->comphy, mode); | |
4995 | if (ret) | |
4996 | return ret; | |
4997 | ||
4998 | return phy_power_on(port->comphy); | |
4999 | } | |
5000 | ||
3919357f AT |
5001 | static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port) |
5002 | { | |
5003 | u32 val; | |
5004 | ||
5005 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
5006 | val = readl(port->base + MVPP22_GMAC_CTRL_4_REG); | |
5007 | val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL | | |
5008 | MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; | |
5009 | val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; | |
5010 | writel(val, port->base + MVPP22_GMAC_CTRL_4_REG); | |
1df2270d | 5011 | } else if (phy_interface_mode_is_rgmii(port->phy_interface)) { |
3919357f AT |
5012 | val = readl(port->base + MVPP22_GMAC_CTRL_4_REG); |
5013 | val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | | |
5014 | MVPP22_CTRL4_SYNC_BYPASS_DIS | | |
5015 | MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; | |
5016 | val &= ~MVPP22_CTRL4_DP_CLK_SEL; | |
5017 | writel(val, port->base + MVPP22_GMAC_CTRL_4_REG); | |
3919357f AT |
5018 | } |
5019 | ||
5020 | /* The port is connected to a copper PHY */ | |
5021 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
5022 | val &= ~MVPP2_GMAC_PORT_TYPE_MASK; | |
5023 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
5024 | ||
5025 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5026 | val |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | | |
5027 | MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | | |
5028 | MVPP2_GMAC_AN_DUPLEX_EN; | |
5029 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) | |
5030 | val |= MVPP2_GMAC_IN_BAND_AUTONEG; | |
5031 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5032 | } | |
5033 | ||
5034 | static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port) | |
5035 | { | |
5036 | u32 val; | |
5037 | ||
5038 | /* Force link down */ | |
5039 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5040 | val &= ~MVPP2_GMAC_FORCE_LINK_PASS; | |
5041 | val |= MVPP2_GMAC_FORCE_LINK_DOWN; | |
5042 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5043 | ||
5044 | /* Set the GMAC in a reset state */ | |
5045 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
5046 | val |= MVPP2_GMAC_PORT_RESET_MASK; | |
5047 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
5048 | ||
5049 | /* Configure the PCS and in-band AN */ | |
5050 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
5051 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
5052 | val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK; | |
1df2270d | 5053 | } else if (phy_interface_mode_is_rgmii(port->phy_interface)) { |
3919357f | 5054 | val &= ~MVPP2_GMAC_PCS_ENABLE_MASK; |
3919357f AT |
5055 | } |
5056 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
5057 | ||
5058 | mvpp2_port_mii_gmac_configure_mode(port); | |
5059 | ||
5060 | /* Unset the GMAC reset state */ | |
5061 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
5062 | val &= ~MVPP2_GMAC_PORT_RESET_MASK; | |
5063 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
5064 | ||
5065 | /* Stop forcing link down */ | |
5066 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5067 | val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; | |
5068 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5069 | } | |
5070 | ||
77321959 AT |
5071 | static void mvpp2_port_mii_xlg_configure(struct mvpp2_port *port) |
5072 | { | |
5073 | u32 val; | |
5074 | ||
5075 | if (port->gop_id != 0) | |
5076 | return; | |
5077 | ||
5078 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
5079 | val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; | |
5080 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
5081 | ||
5082 | val = readl(port->base + MVPP22_XLG_CTRL4_REG); | |
5083 | val &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; | |
5084 | val |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC; | |
5085 | writel(val, port->base + MVPP22_XLG_CTRL4_REG); | |
5086 | } | |
5087 | ||
26975821 TP |
5088 | static void mvpp22_port_mii_set(struct mvpp2_port *port) |
5089 | { | |
5090 | u32 val; | |
5091 | ||
26975821 TP |
5092 | /* Only GOP port 0 has an XLG MAC */ |
5093 | if (port->gop_id == 0) { | |
5094 | val = readl(port->base + MVPP22_XLG_CTRL3_REG); | |
5095 | val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; | |
725757ae AT |
5096 | |
5097 | if (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
5098 | port->phy_interface == PHY_INTERFACE_MODE_10GKR) | |
5099 | val |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; | |
5100 | else | |
5101 | val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; | |
5102 | ||
26975821 TP |
5103 | writel(val, port->base + MVPP22_XLG_CTRL3_REG); |
5104 | } | |
26975821 TP |
5105 | } |
5106 | ||
3f518509 MW |
5107 | static void mvpp2_port_mii_set(struct mvpp2_port *port) |
5108 | { | |
26975821 TP |
5109 | if (port->priv->hw_version == MVPP22) |
5110 | mvpp22_port_mii_set(port); | |
5111 | ||
1df2270d | 5112 | if (phy_interface_mode_is_rgmii(port->phy_interface) || |
3919357f AT |
5113 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) |
5114 | mvpp2_port_mii_gmac_configure(port); | |
77321959 AT |
5115 | else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) |
5116 | mvpp2_port_mii_xlg_configure(port); | |
08a23755 | 5117 | } |
3f518509 | 5118 | |
08a23755 MW |
5119 | static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) |
5120 | { | |
5121 | u32 val; | |
5122 | ||
5123 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5124 | val |= MVPP2_GMAC_FC_ADV_EN; | |
5125 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
3f518509 MW |
5126 | } |
5127 | ||
5128 | static void mvpp2_port_enable(struct mvpp2_port *port) | |
5129 | { | |
5130 | u32 val; | |
5131 | ||
725757ae AT |
5132 | /* Only GOP port 0 has an XLG MAC */ |
5133 | if (port->gop_id == 0 && | |
5134 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
5135 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { | |
5136 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
5137 | val |= MVPP22_XLG_CTRL0_PORT_EN | | |
5138 | MVPP22_XLG_CTRL0_MAC_RESET_DIS; | |
5139 | val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; | |
5140 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
5141 | } else { | |
5142 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
5143 | val |= MVPP2_GMAC_PORT_EN_MASK; | |
5144 | val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; | |
5145 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
5146 | } | |
3f518509 MW |
5147 | } |
5148 | ||
5149 | static void mvpp2_port_disable(struct mvpp2_port *port) | |
5150 | { | |
5151 | u32 val; | |
5152 | ||
725757ae AT |
5153 | /* Only GOP port 0 has an XLG MAC */ |
5154 | if (port->gop_id == 0 && | |
5155 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
5156 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { | |
5157 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
5158 | val &= ~(MVPP22_XLG_CTRL0_PORT_EN | | |
5159 | MVPP22_XLG_CTRL0_MAC_RESET_DIS); | |
5160 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
5161 | } else { | |
5162 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
5163 | val &= ~(MVPP2_GMAC_PORT_EN_MASK); | |
5164 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
5165 | } | |
3f518509 MW |
5166 | } |
5167 | ||
5168 | /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ | |
5169 | static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) | |
5170 | { | |
5171 | u32 val; | |
5172 | ||
5173 | val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & | |
5174 | ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; | |
5175 | writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); | |
5176 | } | |
5177 | ||
5178 | /* Configure loopback port */ | |
5179 | static void mvpp2_port_loopback_set(struct mvpp2_port *port) | |
5180 | { | |
5181 | u32 val; | |
5182 | ||
5183 | val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); | |
5184 | ||
5185 | if (port->speed == 1000) | |
5186 | val |= MVPP2_GMAC_GMII_LB_EN_MASK; | |
5187 | else | |
5188 | val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; | |
5189 | ||
5190 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) | |
5191 | val |= MVPP2_GMAC_PCS_LB_EN_MASK; | |
5192 | else | |
5193 | val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; | |
5194 | ||
5195 | writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); | |
5196 | } | |
5197 | ||
118d6298 MR |
5198 | struct mvpp2_ethtool_counter { |
5199 | unsigned int offset; | |
5200 | const char string[ETH_GSTRING_LEN]; | |
5201 | bool reg_is_64b; | |
5202 | }; | |
5203 | ||
5204 | static u64 mvpp2_read_count(struct mvpp2_port *port, | |
5205 | const struct mvpp2_ethtool_counter *counter) | |
5206 | { | |
5207 | u64 val; | |
5208 | ||
5209 | val = readl(port->stats_base + counter->offset); | |
5210 | if (counter->reg_is_64b) | |
5211 | val += (u64)readl(port->stats_base + counter->offset + 4) << 32; | |
5212 | ||
5213 | return val; | |
5214 | } | |
5215 | ||
5216 | /* Due to the fact that software statistics and hardware statistics are, by | |
5217 | * design, incremented at different moments in the chain of packet processing, | |
5218 | * it is very likely that incoming packets could have been dropped after being | |
5219 | * counted by hardware but before reaching software statistics (most probably | |
5220 | * multicast packets), and in the oppposite way, during transmission, FCS bytes | |
5221 | * are added in between as well as TSO skb will be split and header bytes added. | |
5222 | * Hence, statistics gathered from userspace with ifconfig (software) and | |
5223 | * ethtool (hardware) cannot be compared. | |
5224 | */ | |
5225 | static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = { | |
5226 | { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, | |
5227 | { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, | |
5228 | { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, | |
5229 | { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, | |
5230 | { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, | |
5231 | { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, | |
5232 | { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, | |
5233 | { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, | |
5234 | { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, | |
5235 | { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, | |
5236 | { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, | |
5237 | { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, | |
5238 | { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, | |
5239 | { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, | |
5240 | { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, | |
5241 | { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, | |
5242 | { MVPP2_MIB_FC_SENT, "fc_sent" }, | |
5243 | { MVPP2_MIB_FC_RCVD, "fc_received" }, | |
5244 | { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, | |
5245 | { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, | |
5246 | { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, | |
5247 | { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, | |
5248 | { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, | |
5249 | { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, | |
5250 | { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, | |
5251 | { MVPP2_MIB_COLLISION, "collision" }, | |
5252 | { MVPP2_MIB_LATE_COLLISION, "late_collision" }, | |
5253 | }; | |
5254 | ||
5255 | static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, | |
5256 | u8 *data) | |
5257 | { | |
5258 | if (sset == ETH_SS_STATS) { | |
5259 | int i; | |
5260 | ||
5261 | for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) | |
5262 | memcpy(data + i * ETH_GSTRING_LEN, | |
5263 | &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN); | |
5264 | } | |
5265 | } | |
5266 | ||
5267 | static void mvpp2_gather_hw_statistics(struct work_struct *work) | |
5268 | { | |
5269 | struct delayed_work *del_work = to_delayed_work(work); | |
e5c500eb MR |
5270 | struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, |
5271 | stats_work); | |
118d6298 | 5272 | u64 *pstats; |
e5c500eb | 5273 | int i; |
118d6298 | 5274 | |
e5c500eb | 5275 | mutex_lock(&port->gather_stats_lock); |
118d6298 | 5276 | |
e5c500eb MR |
5277 | pstats = port->ethtool_stats; |
5278 | for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) | |
5279 | *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); | |
118d6298 MR |
5280 | |
5281 | /* No need to read again the counters right after this function if it | |
5282 | * was called asynchronously by the user (ie. use of ethtool). | |
5283 | */ | |
e5c500eb MR |
5284 | cancel_delayed_work(&port->stats_work); |
5285 | queue_delayed_work(port->priv->stats_queue, &port->stats_work, | |
118d6298 MR |
5286 | MVPP2_MIB_COUNTERS_STATS_DELAY); |
5287 | ||
e5c500eb | 5288 | mutex_unlock(&port->gather_stats_lock); |
118d6298 MR |
5289 | } |
5290 | ||
5291 | static void mvpp2_ethtool_get_stats(struct net_device *dev, | |
5292 | struct ethtool_stats *stats, u64 *data) | |
5293 | { | |
5294 | struct mvpp2_port *port = netdev_priv(dev); | |
5295 | ||
e5c500eb MR |
5296 | /* Update statistics for the given port, then take the lock to avoid |
5297 | * concurrent accesses on the ethtool_stats structure during its copy. | |
5298 | */ | |
5299 | mvpp2_gather_hw_statistics(&port->stats_work.work); | |
118d6298 | 5300 | |
e5c500eb | 5301 | mutex_lock(&port->gather_stats_lock); |
118d6298 MR |
5302 | memcpy(data, port->ethtool_stats, |
5303 | sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs)); | |
e5c500eb | 5304 | mutex_unlock(&port->gather_stats_lock); |
118d6298 MR |
5305 | } |
5306 | ||
5307 | static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) | |
5308 | { | |
5309 | if (sset == ETH_SS_STATS) | |
5310 | return ARRAY_SIZE(mvpp2_ethtool_regs); | |
5311 | ||
5312 | return -EOPNOTSUPP; | |
5313 | } | |
5314 | ||
3f518509 MW |
5315 | static void mvpp2_port_reset(struct mvpp2_port *port) |
5316 | { | |
5317 | u32 val; | |
118d6298 MR |
5318 | unsigned int i; |
5319 | ||
5320 | /* Read the GOP statistics to reset the hardware counters */ | |
5321 | for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) | |
5322 | mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); | |
3f518509 MW |
5323 | |
5324 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & | |
5325 | ~MVPP2_GMAC_PORT_RESET_MASK; | |
5326 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
5327 | ||
5328 | while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & | |
5329 | MVPP2_GMAC_PORT_RESET_MASK) | |
5330 | continue; | |
5331 | } | |
5332 | ||
5333 | /* Change maximum receive size of the port */ | |
5334 | static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) | |
5335 | { | |
5336 | u32 val; | |
5337 | ||
5338 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
5339 | val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; | |
5340 | val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << | |
5341 | MVPP2_GMAC_MAX_RX_SIZE_OFFS); | |
5342 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
5343 | } | |
5344 | ||
76eb1b1d SC |
5345 | /* Change maximum receive size of the port */ |
5346 | static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) | |
5347 | { | |
5348 | u32 val; | |
5349 | ||
5350 | val = readl(port->base + MVPP22_XLG_CTRL1_REG); | |
5351 | val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; | |
5352 | val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << | |
ec15ecde | 5353 | MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; |
76eb1b1d SC |
5354 | writel(val, port->base + MVPP22_XLG_CTRL1_REG); |
5355 | } | |
5356 | ||
3f518509 MW |
5357 | /* Set defaults to the MVPP2 port */ |
5358 | static void mvpp2_defaults_set(struct mvpp2_port *port) | |
5359 | { | |
5360 | int tx_port_num, val, queue, ptxq, lrxq; | |
5361 | ||
3d9017d9 TP |
5362 | if (port->priv->hw_version == MVPP21) { |
5363 | /* Configure port to loopback if needed */ | |
5364 | if (port->flags & MVPP2_F_LOOPBACK) | |
5365 | mvpp2_port_loopback_set(port); | |
5366 | ||
5367 | /* Update TX FIFO MIN Threshold */ | |
5368 | val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); | |
5369 | val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; | |
5370 | /* Min. TX threshold must be less than minimal packet length */ | |
5371 | val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); | |
5372 | writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); | |
5373 | } | |
3f518509 MW |
5374 | |
5375 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
5376 | tx_port_num = mvpp2_egress_port(port); | |
5377 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, | |
5378 | tx_port_num); | |
5379 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); | |
5380 | ||
5381 | /* Close bandwidth for all queues */ | |
5382 | for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) { | |
5383 | ptxq = mvpp2_txq_phys(port->id, queue); | |
5384 | mvpp2_write(port->priv, | |
5385 | MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0); | |
5386 | } | |
5387 | ||
5388 | /* Set refill period to 1 usec, refill tokens | |
5389 | * and bucket size to maximum | |
5390 | */ | |
5391 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, | |
5392 | port->priv->tclk / USEC_PER_SEC); | |
5393 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); | |
5394 | val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; | |
5395 | val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); | |
5396 | val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; | |
5397 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); | |
5398 | val = MVPP2_TXP_TOKEN_SIZE_MAX; | |
5399 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); | |
5400 | ||
5401 | /* Set MaximumLowLatencyPacketSize value to 256 */ | |
5402 | mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), | |
5403 | MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | | |
5404 | MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); | |
5405 | ||
5406 | /* Enable Rx cache snoop */ | |
09f83975 | 5407 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
5408 | queue = port->rxqs[lrxq]->id; |
5409 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
5410 | val |= MVPP2_SNOOP_PKT_SIZE_MASK | | |
5411 | MVPP2_SNOOP_BUF_HDR_MASK; | |
5412 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
5413 | } | |
5414 | ||
5415 | /* At default, mask all interrupts to all present cpus */ | |
5416 | mvpp2_interrupts_disable(port); | |
5417 | } | |
5418 | ||
5419 | /* Enable/disable receiving packets */ | |
5420 | static void mvpp2_ingress_enable(struct mvpp2_port *port) | |
5421 | { | |
5422 | u32 val; | |
5423 | int lrxq, queue; | |
5424 | ||
09f83975 | 5425 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
5426 | queue = port->rxqs[lrxq]->id; |
5427 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
5428 | val &= ~MVPP2_RXQ_DISABLE_MASK; | |
5429 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
5430 | } | |
5431 | } | |
5432 | ||
5433 | static void mvpp2_ingress_disable(struct mvpp2_port *port) | |
5434 | { | |
5435 | u32 val; | |
5436 | int lrxq, queue; | |
5437 | ||
09f83975 | 5438 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
5439 | queue = port->rxqs[lrxq]->id; |
5440 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
5441 | val |= MVPP2_RXQ_DISABLE_MASK; | |
5442 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
5443 | } | |
5444 | } | |
5445 | ||
5446 | /* Enable transmit via physical egress queue | |
5447 | * - HW starts take descriptors from DRAM | |
5448 | */ | |
5449 | static void mvpp2_egress_enable(struct mvpp2_port *port) | |
5450 | { | |
5451 | u32 qmap; | |
5452 | int queue; | |
5453 | int tx_port_num = mvpp2_egress_port(port); | |
5454 | ||
5455 | /* Enable all initialized TXs. */ | |
5456 | qmap = 0; | |
09f83975 | 5457 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
5458 | struct mvpp2_tx_queue *txq = port->txqs[queue]; |
5459 | ||
dbbb2f03 | 5460 | if (txq->descs) |
3f518509 MW |
5461 | qmap |= (1 << queue); |
5462 | } | |
5463 | ||
5464 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
5465 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); | |
5466 | } | |
5467 | ||
5468 | /* Disable transmit via physical egress queue | |
5469 | * - HW doesn't take descriptors from DRAM | |
5470 | */ | |
5471 | static void mvpp2_egress_disable(struct mvpp2_port *port) | |
5472 | { | |
5473 | u32 reg_data; | |
5474 | int delay; | |
5475 | int tx_port_num = mvpp2_egress_port(port); | |
5476 | ||
5477 | /* Issue stop command for active channels only */ | |
5478 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
5479 | reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & | |
5480 | MVPP2_TXP_SCHED_ENQ_MASK; | |
5481 | if (reg_data != 0) | |
5482 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, | |
5483 | (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); | |
5484 | ||
5485 | /* Wait for all Tx activity to terminate. */ | |
5486 | delay = 0; | |
5487 | do { | |
5488 | if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { | |
5489 | netdev_warn(port->dev, | |
5490 | "Tx stop timed out, status=0x%08x\n", | |
5491 | reg_data); | |
5492 | break; | |
5493 | } | |
5494 | mdelay(1); | |
5495 | delay++; | |
5496 | ||
5497 | /* Check port TX Command register that all | |
5498 | * Tx queues are stopped | |
5499 | */ | |
5500 | reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); | |
5501 | } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); | |
5502 | } | |
5503 | ||
5504 | /* Rx descriptors helper methods */ | |
5505 | ||
5506 | /* Get number of Rx descriptors occupied by received packets */ | |
5507 | static inline int | |
5508 | mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) | |
5509 | { | |
5510 | u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); | |
5511 | ||
5512 | return val & MVPP2_RXQ_OCCUPIED_MASK; | |
5513 | } | |
5514 | ||
5515 | /* Update Rx queue status with the number of occupied and available | |
5516 | * Rx descriptor slots. | |
5517 | */ | |
5518 | static inline void | |
5519 | mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, | |
5520 | int used_count, int free_count) | |
5521 | { | |
5522 | /* Decrement the number of used descriptors and increment count | |
5523 | * increment the number of free descriptors. | |
5524 | */ | |
5525 | u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); | |
5526 | ||
5527 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); | |
5528 | } | |
5529 | ||
5530 | /* Get pointer to next RX descriptor to be processed by SW */ | |
5531 | static inline struct mvpp2_rx_desc * | |
5532 | mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) | |
5533 | { | |
5534 | int rx_desc = rxq->next_desc_to_proc; | |
5535 | ||
5536 | rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); | |
5537 | prefetch(rxq->descs + rxq->next_desc_to_proc); | |
5538 | return rxq->descs + rx_desc; | |
5539 | } | |
5540 | ||
5541 | /* Set rx queue offset */ | |
5542 | static void mvpp2_rxq_offset_set(struct mvpp2_port *port, | |
5543 | int prxq, int offset) | |
5544 | { | |
5545 | u32 val; | |
5546 | ||
5547 | /* Convert offset from bytes to units of 32 bytes */ | |
5548 | offset = offset >> 5; | |
5549 | ||
5550 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); | |
5551 | val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; | |
5552 | ||
5553 | /* Offset is in */ | |
5554 | val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & | |
5555 | MVPP2_RXQ_PACKET_OFFSET_MASK); | |
5556 | ||
5557 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); | |
5558 | } | |
5559 | ||
3f518509 MW |
5560 | /* Tx descriptors helper methods */ |
5561 | ||
3f518509 MW |
5562 | /* Get pointer to next Tx descriptor to be processed (send) by HW */ |
5563 | static struct mvpp2_tx_desc * | |
5564 | mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) | |
5565 | { | |
5566 | int tx_desc = txq->next_desc_to_proc; | |
5567 | ||
5568 | txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); | |
5569 | return txq->descs + tx_desc; | |
5570 | } | |
5571 | ||
e0af22d9 TP |
5572 | /* Update HW with number of aggregated Tx descriptors to be sent |
5573 | * | |
5574 | * Called only from mvpp2_tx(), so migration is disabled, using | |
5575 | * smp_processor_id() is OK. | |
5576 | */ | |
3f518509 MW |
5577 | static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) |
5578 | { | |
5579 | /* aggregated access - relevant TXQ number is written in TX desc */ | |
a786841d TP |
5580 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
5581 | MVPP2_AGGR_TXQ_UPDATE_REG, pending); | |
3f518509 MW |
5582 | } |
5583 | ||
5584 | ||
5585 | /* Check if there are enough free descriptors in aggregated txq. | |
5586 | * If not, update the number of occupied descriptors and repeat the check. | |
e0af22d9 TP |
5587 | * |
5588 | * Called only from mvpp2_tx(), so migration is disabled, using | |
5589 | * smp_processor_id() is OK. | |
3f518509 MW |
5590 | */ |
5591 | static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv, | |
5592 | struct mvpp2_tx_queue *aggr_txq, int num) | |
5593 | { | |
02856a3b | 5594 | if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { |
3f518509 MW |
5595 | /* Update number of occupied aggregated Tx descriptors */ |
5596 | int cpu = smp_processor_id(); | |
5597 | u32 val = mvpp2_read(priv, MVPP2_AGGR_TXQ_STATUS_REG(cpu)); | |
5598 | ||
5599 | aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; | |
5600 | } | |
5601 | ||
02856a3b | 5602 | if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) |
3f518509 MW |
5603 | return -ENOMEM; |
5604 | ||
5605 | return 0; | |
5606 | } | |
5607 | ||
e0af22d9 TP |
5608 | /* Reserved Tx descriptors allocation request |
5609 | * | |
5610 | * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called | |
5611 | * only by mvpp2_tx(), so migration is disabled, using | |
5612 | * smp_processor_id() is OK. | |
5613 | */ | |
3f518509 MW |
5614 | static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv, |
5615 | struct mvpp2_tx_queue *txq, int num) | |
5616 | { | |
5617 | u32 val; | |
a786841d | 5618 | int cpu = smp_processor_id(); |
3f518509 MW |
5619 | |
5620 | val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; | |
a786841d | 5621 | mvpp2_percpu_write(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val); |
3f518509 | 5622 | |
a786841d | 5623 | val = mvpp2_percpu_read(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG); |
3f518509 MW |
5624 | |
5625 | return val & MVPP2_TXQ_RSVD_RSLT_MASK; | |
5626 | } | |
5627 | ||
5628 | /* Check if there are enough reserved descriptors for transmission. | |
5629 | * If not, request chunk of reserved descriptors and check again. | |
5630 | */ | |
5631 | static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv, | |
5632 | struct mvpp2_tx_queue *txq, | |
5633 | struct mvpp2_txq_pcpu *txq_pcpu, | |
5634 | int num) | |
5635 | { | |
5636 | int req, cpu, desc_count; | |
5637 | ||
5638 | if (txq_pcpu->reserved_num >= num) | |
5639 | return 0; | |
5640 | ||
5641 | /* Not enough descriptors reserved! Update the reserved descriptor | |
5642 | * count and check again. | |
5643 | */ | |
5644 | ||
5645 | desc_count = 0; | |
5646 | /* Compute total of used descriptors */ | |
5647 | for_each_present_cpu(cpu) { | |
5648 | struct mvpp2_txq_pcpu *txq_pcpu_aux; | |
5649 | ||
5650 | txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu); | |
5651 | desc_count += txq_pcpu_aux->count; | |
5652 | desc_count += txq_pcpu_aux->reserved_num; | |
5653 | } | |
5654 | ||
5655 | req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); | |
5656 | desc_count += req; | |
5657 | ||
5658 | if (desc_count > | |
5659 | (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK))) | |
5660 | return -ENOMEM; | |
5661 | ||
5662 | txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req); | |
5663 | ||
5664 | /* OK, the descriptor cound has been updated: check again. */ | |
5665 | if (txq_pcpu->reserved_num < num) | |
5666 | return -ENOMEM; | |
5667 | return 0; | |
5668 | } | |
5669 | ||
5670 | /* Release the last allocated Tx descriptor. Useful to handle DMA | |
5671 | * mapping failures in the Tx path. | |
5672 | */ | |
5673 | static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) | |
5674 | { | |
5675 | if (txq->next_desc_to_proc == 0) | |
5676 | txq->next_desc_to_proc = txq->last_desc - 1; | |
5677 | else | |
5678 | txq->next_desc_to_proc--; | |
5679 | } | |
5680 | ||
5681 | /* Set Tx descriptors fields relevant for CSUM calculation */ | |
5682 | static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto, | |
5683 | int ip_hdr_len, int l4_proto) | |
5684 | { | |
5685 | u32 command; | |
5686 | ||
5687 | /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
5688 | * G_L4_chk, L4_type required only for checksum calculation | |
5689 | */ | |
5690 | command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); | |
5691 | command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); | |
5692 | command |= MVPP2_TXD_IP_CSUM_DISABLE; | |
5693 | ||
5694 | if (l3_proto == swab16(ETH_P_IP)) { | |
5695 | command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ | |
5696 | command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ | |
5697 | } else { | |
5698 | command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ | |
5699 | } | |
5700 | ||
5701 | if (l4_proto == IPPROTO_TCP) { | |
5702 | command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ | |
5703 | command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ | |
5704 | } else if (l4_proto == IPPROTO_UDP) { | |
5705 | command |= MVPP2_TXD_L4_UDP; /* enable UDP */ | |
5706 | command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ | |
5707 | } else { | |
5708 | command |= MVPP2_TXD_L4_CSUM_NOT; | |
5709 | } | |
5710 | ||
5711 | return command; | |
5712 | } | |
5713 | ||
5714 | /* Get number of sent descriptors and decrement counter. | |
5715 | * The number of sent descriptors is returned. | |
5716 | * Per-CPU access | |
e0af22d9 TP |
5717 | * |
5718 | * Called only from mvpp2_txq_done(), called from mvpp2_tx() | |
5719 | * (migration disabled) and from the TX completion tasklet (migration | |
5720 | * disabled) so using smp_processor_id() is OK. | |
3f518509 MW |
5721 | */ |
5722 | static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, | |
5723 | struct mvpp2_tx_queue *txq) | |
5724 | { | |
5725 | u32 val; | |
5726 | ||
5727 | /* Reading status reg resets transmitted descriptor counter */ | |
a786841d TP |
5728 | val = mvpp2_percpu_read(port->priv, smp_processor_id(), |
5729 | MVPP2_TXQ_SENT_REG(txq->id)); | |
3f518509 MW |
5730 | |
5731 | return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> | |
5732 | MVPP2_TRANSMITTED_COUNT_OFFSET; | |
5733 | } | |
5734 | ||
e0af22d9 TP |
5735 | /* Called through on_each_cpu(), so runs on all CPUs, with migration |
5736 | * disabled, therefore using smp_processor_id() is OK. | |
5737 | */ | |
3f518509 MW |
5738 | static void mvpp2_txq_sent_counter_clear(void *arg) |
5739 | { | |
5740 | struct mvpp2_port *port = arg; | |
5741 | int queue; | |
5742 | ||
09f83975 | 5743 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
5744 | int id = port->txqs[queue]->id; |
5745 | ||
a786841d TP |
5746 | mvpp2_percpu_read(port->priv, smp_processor_id(), |
5747 | MVPP2_TXQ_SENT_REG(id)); | |
3f518509 MW |
5748 | } |
5749 | } | |
5750 | ||
5751 | /* Set max sizes for Tx queues */ | |
5752 | static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) | |
5753 | { | |
5754 | u32 val, size, mtu; | |
5755 | int txq, tx_port_num; | |
5756 | ||
5757 | mtu = port->pkt_size * 8; | |
5758 | if (mtu > MVPP2_TXP_MTU_MAX) | |
5759 | mtu = MVPP2_TXP_MTU_MAX; | |
5760 | ||
5761 | /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ | |
5762 | mtu = 3 * mtu; | |
5763 | ||
5764 | /* Indirect access to registers */ | |
5765 | tx_port_num = mvpp2_egress_port(port); | |
5766 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
5767 | ||
5768 | /* Set MTU */ | |
5769 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); | |
5770 | val &= ~MVPP2_TXP_MTU_MAX; | |
5771 | val |= mtu; | |
5772 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); | |
5773 | ||
5774 | /* TXP token size and all TXQs token size must be larger that MTU */ | |
5775 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); | |
5776 | size = val & MVPP2_TXP_TOKEN_SIZE_MAX; | |
5777 | if (size < mtu) { | |
5778 | size = mtu; | |
5779 | val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; | |
5780 | val |= size; | |
5781 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); | |
5782 | } | |
5783 | ||
09f83975 | 5784 | for (txq = 0; txq < port->ntxqs; txq++) { |
3f518509 MW |
5785 | val = mvpp2_read(port->priv, |
5786 | MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); | |
5787 | size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; | |
5788 | ||
5789 | if (size < mtu) { | |
5790 | size = mtu; | |
5791 | val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; | |
5792 | val |= size; | |
5793 | mvpp2_write(port->priv, | |
5794 | MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), | |
5795 | val); | |
5796 | } | |
5797 | } | |
5798 | } | |
5799 | ||
5800 | /* Set the number of packets that will be received before Rx interrupt | |
5801 | * will be generated by HW. | |
5802 | */ | |
5803 | static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, | |
d63f9e41 | 5804 | struct mvpp2_rx_queue *rxq) |
3f518509 | 5805 | { |
a704bb5c | 5806 | int cpu = get_cpu(); |
a786841d | 5807 | |
f8b0d5f8 TP |
5808 | if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) |
5809 | rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; | |
3f518509 | 5810 | |
a786841d TP |
5811 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
5812 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG, | |
5813 | rxq->pkts_coal); | |
a704bb5c TP |
5814 | |
5815 | put_cpu(); | |
3f518509 MW |
5816 | } |
5817 | ||
213f428f TP |
5818 | /* For some reason in the LSP this is done on each CPU. Why ? */ |
5819 | static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, | |
5820 | struct mvpp2_tx_queue *txq) | |
5821 | { | |
5822 | int cpu = get_cpu(); | |
5823 | u32 val; | |
5824 | ||
5825 | if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) | |
5826 | txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; | |
5827 | ||
5828 | val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); | |
5829 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); | |
5830 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_THRESH_REG, val); | |
5831 | ||
5832 | put_cpu(); | |
5833 | } | |
5834 | ||
ab42676a TP |
5835 | static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) |
5836 | { | |
5837 | u64 tmp = (u64)clk_hz * usec; | |
5838 | ||
5839 | do_div(tmp, USEC_PER_SEC); | |
5840 | ||
5841 | return tmp > U32_MAX ? U32_MAX : tmp; | |
5842 | } | |
5843 | ||
5844 | static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) | |
5845 | { | |
5846 | u64 tmp = (u64)cycles * USEC_PER_SEC; | |
5847 | ||
5848 | do_div(tmp, clk_hz); | |
5849 | ||
5850 | return tmp > U32_MAX ? U32_MAX : tmp; | |
5851 | } | |
5852 | ||
3f518509 MW |
5853 | /* Set the time delay in usec before Rx interrupt */ |
5854 | static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, | |
d63f9e41 | 5855 | struct mvpp2_rx_queue *rxq) |
3f518509 | 5856 | { |
ab42676a TP |
5857 | unsigned long freq = port->priv->tclk; |
5858 | u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); | |
5859 | ||
5860 | if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { | |
5861 | rxq->time_coal = | |
5862 | mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); | |
5863 | ||
5864 | /* re-evaluate to get actual register value */ | |
5865 | val = mvpp2_usec_to_cycles(rxq->time_coal, freq); | |
5866 | } | |
3f518509 | 5867 | |
3f518509 | 5868 | mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); |
3f518509 MW |
5869 | } |
5870 | ||
213f428f TP |
5871 | static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) |
5872 | { | |
5873 | unsigned long freq = port->priv->tclk; | |
5874 | u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); | |
5875 | ||
5876 | if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { | |
5877 | port->tx_time_coal = | |
5878 | mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); | |
5879 | ||
5880 | /* re-evaluate to get actual register value */ | |
5881 | val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); | |
5882 | } | |
5883 | ||
5884 | mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); | |
5885 | } | |
5886 | ||
3f518509 MW |
5887 | /* Free Tx queue skbuffs */ |
5888 | static void mvpp2_txq_bufs_free(struct mvpp2_port *port, | |
5889 | struct mvpp2_tx_queue *txq, | |
5890 | struct mvpp2_txq_pcpu *txq_pcpu, int num) | |
5891 | { | |
5892 | int i; | |
5893 | ||
5894 | for (i = 0; i < num; i++) { | |
8354491c TP |
5895 | struct mvpp2_txq_pcpu_buf *tx_buf = |
5896 | txq_pcpu->buffs + txq_pcpu->txq_get_index; | |
3f518509 | 5897 | |
20920267 AT |
5898 | if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma)) |
5899 | dma_unmap_single(port->dev->dev.parent, tx_buf->dma, | |
5900 | tx_buf->size, DMA_TO_DEVICE); | |
36fb7435 TP |
5901 | if (tx_buf->skb) |
5902 | dev_kfree_skb_any(tx_buf->skb); | |
5903 | ||
5904 | mvpp2_txq_inc_get(txq_pcpu); | |
3f518509 MW |
5905 | } |
5906 | } | |
5907 | ||
5908 | static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, | |
5909 | u32 cause) | |
5910 | { | |
5911 | int queue = fls(cause) - 1; | |
5912 | ||
5913 | return port->rxqs[queue]; | |
5914 | } | |
5915 | ||
5916 | static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, | |
5917 | u32 cause) | |
5918 | { | |
edc660fa | 5919 | int queue = fls(cause) - 1; |
3f518509 MW |
5920 | |
5921 | return port->txqs[queue]; | |
5922 | } | |
5923 | ||
5924 | /* Handle end of transmission */ | |
5925 | static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, | |
5926 | struct mvpp2_txq_pcpu *txq_pcpu) | |
5927 | { | |
5928 | struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); | |
5929 | int tx_done; | |
5930 | ||
5931 | if (txq_pcpu->cpu != smp_processor_id()) | |
5932 | netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); | |
5933 | ||
5934 | tx_done = mvpp2_txq_sent_desc_proc(port, txq); | |
5935 | if (!tx_done) | |
5936 | return; | |
5937 | mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); | |
5938 | ||
5939 | txq_pcpu->count -= tx_done; | |
5940 | ||
5941 | if (netif_tx_queue_stopped(nq)) | |
1d17db08 | 5942 | if (txq_pcpu->count <= txq_pcpu->wake_threshold) |
3f518509 MW |
5943 | netif_tx_wake_queue(nq); |
5944 | } | |
5945 | ||
213f428f TP |
5946 | static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, |
5947 | int cpu) | |
edc660fa MW |
5948 | { |
5949 | struct mvpp2_tx_queue *txq; | |
5950 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5951 | unsigned int tx_todo = 0; | |
5952 | ||
5953 | while (cause) { | |
5954 | txq = mvpp2_get_tx_queue(port, cause); | |
5955 | if (!txq) | |
5956 | break; | |
5957 | ||
213f428f | 5958 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); |
edc660fa MW |
5959 | |
5960 | if (txq_pcpu->count) { | |
5961 | mvpp2_txq_done(port, txq, txq_pcpu); | |
5962 | tx_todo += txq_pcpu->count; | |
5963 | } | |
5964 | ||
5965 | cause &= ~(1 << txq->log_id); | |
5966 | } | |
5967 | return tx_todo; | |
5968 | } | |
5969 | ||
3f518509 MW |
5970 | /* Rx/Tx queue initialization/cleanup methods */ |
5971 | ||
5972 | /* Allocate and initialize descriptors for aggr TXQ */ | |
5973 | static int mvpp2_aggr_txq_init(struct platform_device *pdev, | |
85affd7e | 5974 | struct mvpp2_tx_queue *aggr_txq, int cpu, |
3f518509 MW |
5975 | struct mvpp2 *priv) |
5976 | { | |
b02f31fb TP |
5977 | u32 txq_dma; |
5978 | ||
3f518509 | 5979 | /* Allocate memory for TX descriptors */ |
a154f8e3 | 5980 | aggr_txq->descs = dma_zalloc_coherent(&pdev->dev, |
85affd7e | 5981 | MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, |
20396136 | 5982 | &aggr_txq->descs_dma, GFP_KERNEL); |
3f518509 MW |
5983 | if (!aggr_txq->descs) |
5984 | return -ENOMEM; | |
5985 | ||
02856a3b | 5986 | aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; |
3f518509 MW |
5987 | |
5988 | /* Aggr TXQ no reset WA */ | |
5989 | aggr_txq->next_desc_to_proc = mvpp2_read(priv, | |
5990 | MVPP2_AGGR_TXQ_INDEX_REG(cpu)); | |
5991 | ||
b02f31fb TP |
5992 | /* Set Tx descriptors queue starting address indirect |
5993 | * access | |
5994 | */ | |
5995 | if (priv->hw_version == MVPP21) | |
5996 | txq_dma = aggr_txq->descs_dma; | |
5997 | else | |
5998 | txq_dma = aggr_txq->descs_dma >> | |
5999 | MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; | |
6000 | ||
6001 | mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma); | |
85affd7e AT |
6002 | mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), |
6003 | MVPP2_AGGR_TXQ_SIZE); | |
3f518509 MW |
6004 | |
6005 | return 0; | |
6006 | } | |
6007 | ||
6008 | /* Create a specified Rx queue */ | |
6009 | static int mvpp2_rxq_init(struct mvpp2_port *port, | |
6010 | struct mvpp2_rx_queue *rxq) | |
6011 | ||
6012 | { | |
b02f31fb | 6013 | u32 rxq_dma; |
a786841d | 6014 | int cpu; |
b02f31fb | 6015 | |
3f518509 MW |
6016 | rxq->size = port->rx_ring_size; |
6017 | ||
6018 | /* Allocate memory for RX descriptors */ | |
6019 | rxq->descs = dma_alloc_coherent(port->dev->dev.parent, | |
6020 | rxq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 6021 | &rxq->descs_dma, GFP_KERNEL); |
3f518509 MW |
6022 | if (!rxq->descs) |
6023 | return -ENOMEM; | |
6024 | ||
3f518509 MW |
6025 | rxq->last_desc = rxq->size - 1; |
6026 | ||
6027 | /* Zero occupied and non-occupied counters - direct access */ | |
6028 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); | |
6029 | ||
6030 | /* Set Rx descriptors queue starting address - indirect access */ | |
a704bb5c | 6031 | cpu = get_cpu(); |
a786841d | 6032 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
b02f31fb TP |
6033 | if (port->priv->hw_version == MVPP21) |
6034 | rxq_dma = rxq->descs_dma; | |
6035 | else | |
6036 | rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; | |
a786841d TP |
6037 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); |
6038 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); | |
6039 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0); | |
a704bb5c | 6040 | put_cpu(); |
3f518509 MW |
6041 | |
6042 | /* Set Offset */ | |
6043 | mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); | |
6044 | ||
6045 | /* Set coalescing pkts and time */ | |
d63f9e41 TP |
6046 | mvpp2_rx_pkts_coal_set(port, rxq); |
6047 | mvpp2_rx_time_coal_set(port, rxq); | |
3f518509 MW |
6048 | |
6049 | /* Add number of descriptors ready for receiving packets */ | |
6050 | mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); | |
6051 | ||
6052 | return 0; | |
6053 | } | |
6054 | ||
6055 | /* Push packets received by the RXQ to BM pool */ | |
6056 | static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, | |
6057 | struct mvpp2_rx_queue *rxq) | |
6058 | { | |
6059 | int rx_received, i; | |
6060 | ||
6061 | rx_received = mvpp2_rxq_received(port, rxq->id); | |
6062 | if (!rx_received) | |
6063 | return; | |
6064 | ||
6065 | for (i = 0; i < rx_received; i++) { | |
6066 | struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); | |
56b8aae9 TP |
6067 | u32 status = mvpp2_rxdesc_status_get(port, rx_desc); |
6068 | int pool; | |
6069 | ||
6070 | pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> | |
6071 | MVPP2_RXD_BM_POOL_ID_OFFS; | |
3f518509 | 6072 | |
7d7627ba | 6073 | mvpp2_bm_pool_put(port, pool, |
ac3dd277 TP |
6074 | mvpp2_rxdesc_dma_addr_get(port, rx_desc), |
6075 | mvpp2_rxdesc_cookie_get(port, rx_desc)); | |
3f518509 MW |
6076 | } |
6077 | mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); | |
6078 | } | |
6079 | ||
6080 | /* Cleanup Rx queue */ | |
6081 | static void mvpp2_rxq_deinit(struct mvpp2_port *port, | |
6082 | struct mvpp2_rx_queue *rxq) | |
6083 | { | |
a786841d TP |
6084 | int cpu; |
6085 | ||
3f518509 MW |
6086 | mvpp2_rxq_drop_pkts(port, rxq); |
6087 | ||
6088 | if (rxq->descs) | |
6089 | dma_free_coherent(port->dev->dev.parent, | |
6090 | rxq->size * MVPP2_DESC_ALIGNED_SIZE, | |
6091 | rxq->descs, | |
20396136 | 6092 | rxq->descs_dma); |
3f518509 MW |
6093 | |
6094 | rxq->descs = NULL; | |
6095 | rxq->last_desc = 0; | |
6096 | rxq->next_desc_to_proc = 0; | |
20396136 | 6097 | rxq->descs_dma = 0; |
3f518509 MW |
6098 | |
6099 | /* Clear Rx descriptors queue starting address and size; | |
6100 | * free descriptor number | |
6101 | */ | |
6102 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); | |
a704bb5c | 6103 | cpu = get_cpu(); |
a786841d TP |
6104 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
6105 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0); | |
6106 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0); | |
a704bb5c | 6107 | put_cpu(); |
3f518509 MW |
6108 | } |
6109 | ||
6110 | /* Create and initialize a Tx queue */ | |
6111 | static int mvpp2_txq_init(struct mvpp2_port *port, | |
6112 | struct mvpp2_tx_queue *txq) | |
6113 | { | |
6114 | u32 val; | |
6115 | int cpu, desc, desc_per_txq, tx_port_num; | |
6116 | struct mvpp2_txq_pcpu *txq_pcpu; | |
6117 | ||
6118 | txq->size = port->tx_ring_size; | |
6119 | ||
6120 | /* Allocate memory for Tx descriptors */ | |
6121 | txq->descs = dma_alloc_coherent(port->dev->dev.parent, | |
6122 | txq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 6123 | &txq->descs_dma, GFP_KERNEL); |
3f518509 MW |
6124 | if (!txq->descs) |
6125 | return -ENOMEM; | |
6126 | ||
3f518509 MW |
6127 | txq->last_desc = txq->size - 1; |
6128 | ||
6129 | /* Set Tx descriptors queue starting address - indirect access */ | |
a704bb5c | 6130 | cpu = get_cpu(); |
a786841d TP |
6131 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
6132 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, | |
6133 | txq->descs_dma); | |
6134 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, | |
6135 | txq->size & MVPP2_TXQ_DESC_SIZE_MASK); | |
6136 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_INDEX_REG, 0); | |
6137 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_RSVD_CLR_REG, | |
6138 | txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); | |
6139 | val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PENDING_REG); | |
3f518509 | 6140 | val &= ~MVPP2_TXQ_PENDING_MASK; |
a786841d | 6141 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PENDING_REG, val); |
3f518509 MW |
6142 | |
6143 | /* Calculate base address in prefetch buffer. We reserve 16 descriptors | |
6144 | * for each existing TXQ. | |
6145 | * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT | |
6146 | * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS | |
6147 | */ | |
6148 | desc_per_txq = 16; | |
6149 | desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + | |
6150 | (txq->log_id * desc_per_txq); | |
6151 | ||
a786841d TP |
6152 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, |
6153 | MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | | |
6154 | MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); | |
a704bb5c | 6155 | put_cpu(); |
3f518509 MW |
6156 | |
6157 | /* WRR / EJP configuration - indirect access */ | |
6158 | tx_port_num = mvpp2_egress_port(port); | |
6159 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
6160 | ||
6161 | val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); | |
6162 | val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; | |
6163 | val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); | |
6164 | val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; | |
6165 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); | |
6166 | ||
6167 | val = MVPP2_TXQ_TOKEN_SIZE_MAX; | |
6168 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), | |
6169 | val); | |
6170 | ||
6171 | for_each_present_cpu(cpu) { | |
6172 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
6173 | txq_pcpu->size = txq->size; | |
02c91ece ME |
6174 | txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, |
6175 | sizeof(*txq_pcpu->buffs), | |
6176 | GFP_KERNEL); | |
8354491c | 6177 | if (!txq_pcpu->buffs) |
ba2d8d88 | 6178 | return -ENOMEM; |
3f518509 MW |
6179 | |
6180 | txq_pcpu->count = 0; | |
6181 | txq_pcpu->reserved_num = 0; | |
6182 | txq_pcpu->txq_put_index = 0; | |
6183 | txq_pcpu->txq_get_index = 0; | |
b70d4a51 | 6184 | txq_pcpu->tso_headers = NULL; |
186cd4d4 | 6185 | |
1d17db08 AT |
6186 | txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; |
6187 | txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; | |
6188 | ||
186cd4d4 AT |
6189 | txq_pcpu->tso_headers = |
6190 | dma_alloc_coherent(port->dev->dev.parent, | |
822eaf7c | 6191 | txq_pcpu->size * TSO_HEADER_SIZE, |
186cd4d4 AT |
6192 | &txq_pcpu->tso_headers_dma, |
6193 | GFP_KERNEL); | |
6194 | if (!txq_pcpu->tso_headers) | |
ba2d8d88 | 6195 | return -ENOMEM; |
3f518509 MW |
6196 | } |
6197 | ||
6198 | return 0; | |
6199 | } | |
6200 | ||
6201 | /* Free allocated TXQ resources */ | |
6202 | static void mvpp2_txq_deinit(struct mvpp2_port *port, | |
6203 | struct mvpp2_tx_queue *txq) | |
6204 | { | |
6205 | struct mvpp2_txq_pcpu *txq_pcpu; | |
6206 | int cpu; | |
6207 | ||
6208 | for_each_present_cpu(cpu) { | |
6209 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
8354491c | 6210 | kfree(txq_pcpu->buffs); |
186cd4d4 | 6211 | |
b70d4a51 AT |
6212 | if (txq_pcpu->tso_headers) |
6213 | dma_free_coherent(port->dev->dev.parent, | |
6214 | txq_pcpu->size * TSO_HEADER_SIZE, | |
6215 | txq_pcpu->tso_headers, | |
6216 | txq_pcpu->tso_headers_dma); | |
6217 | ||
6218 | txq_pcpu->tso_headers = NULL; | |
3f518509 MW |
6219 | } |
6220 | ||
6221 | if (txq->descs) | |
6222 | dma_free_coherent(port->dev->dev.parent, | |
6223 | txq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 6224 | txq->descs, txq->descs_dma); |
3f518509 MW |
6225 | |
6226 | txq->descs = NULL; | |
6227 | txq->last_desc = 0; | |
6228 | txq->next_desc_to_proc = 0; | |
20396136 | 6229 | txq->descs_dma = 0; |
3f518509 MW |
6230 | |
6231 | /* Set minimum bandwidth for disabled TXQs */ | |
6232 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); | |
6233 | ||
6234 | /* Set Tx descriptors queue starting address and size */ | |
a704bb5c | 6235 | cpu = get_cpu(); |
a786841d TP |
6236 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
6237 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0); | |
6238 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0); | |
a704bb5c | 6239 | put_cpu(); |
3f518509 MW |
6240 | } |
6241 | ||
6242 | /* Cleanup Tx ports */ | |
6243 | static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) | |
6244 | { | |
6245 | struct mvpp2_txq_pcpu *txq_pcpu; | |
6246 | int delay, pending, cpu; | |
6247 | u32 val; | |
6248 | ||
a704bb5c | 6249 | cpu = get_cpu(); |
a786841d TP |
6250 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
6251 | val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG); | |
3f518509 | 6252 | val |= MVPP2_TXQ_DRAIN_EN_MASK; |
a786841d | 6253 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); |
3f518509 MW |
6254 | |
6255 | /* The napi queue has been stopped so wait for all packets | |
6256 | * to be transmitted. | |
6257 | */ | |
6258 | delay = 0; | |
6259 | do { | |
6260 | if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { | |
6261 | netdev_warn(port->dev, | |
6262 | "port %d: cleaning queue %d timed out\n", | |
6263 | port->id, txq->log_id); | |
6264 | break; | |
6265 | } | |
6266 | mdelay(1); | |
6267 | delay++; | |
6268 | ||
a786841d TP |
6269 | pending = mvpp2_percpu_read(port->priv, cpu, |
6270 | MVPP2_TXQ_PENDING_REG); | |
6271 | pending &= MVPP2_TXQ_PENDING_MASK; | |
3f518509 MW |
6272 | } while (pending); |
6273 | ||
6274 | val &= ~MVPP2_TXQ_DRAIN_EN_MASK; | |
a786841d | 6275 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); |
a704bb5c | 6276 | put_cpu(); |
3f518509 MW |
6277 | |
6278 | for_each_present_cpu(cpu) { | |
6279 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
6280 | ||
6281 | /* Release all packets */ | |
6282 | mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); | |
6283 | ||
6284 | /* Reset queue */ | |
6285 | txq_pcpu->count = 0; | |
6286 | txq_pcpu->txq_put_index = 0; | |
6287 | txq_pcpu->txq_get_index = 0; | |
6288 | } | |
6289 | } | |
6290 | ||
6291 | /* Cleanup all Tx queues */ | |
6292 | static void mvpp2_cleanup_txqs(struct mvpp2_port *port) | |
6293 | { | |
6294 | struct mvpp2_tx_queue *txq; | |
6295 | int queue; | |
6296 | u32 val; | |
6297 | ||
6298 | val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); | |
6299 | ||
6300 | /* Reset Tx ports and delete Tx queues */ | |
6301 | val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); | |
6302 | mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); | |
6303 | ||
09f83975 | 6304 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
6305 | txq = port->txqs[queue]; |
6306 | mvpp2_txq_clean(port, txq); | |
6307 | mvpp2_txq_deinit(port, txq); | |
6308 | } | |
6309 | ||
6310 | on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); | |
6311 | ||
6312 | val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); | |
6313 | mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); | |
6314 | } | |
6315 | ||
6316 | /* Cleanup all Rx queues */ | |
6317 | static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) | |
6318 | { | |
6319 | int queue; | |
6320 | ||
09f83975 | 6321 | for (queue = 0; queue < port->nrxqs; queue++) |
3f518509 MW |
6322 | mvpp2_rxq_deinit(port, port->rxqs[queue]); |
6323 | } | |
6324 | ||
6325 | /* Init all Rx queues for port */ | |
6326 | static int mvpp2_setup_rxqs(struct mvpp2_port *port) | |
6327 | { | |
6328 | int queue, err; | |
6329 | ||
09f83975 | 6330 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
6331 | err = mvpp2_rxq_init(port, port->rxqs[queue]); |
6332 | if (err) | |
6333 | goto err_cleanup; | |
6334 | } | |
6335 | return 0; | |
6336 | ||
6337 | err_cleanup: | |
6338 | mvpp2_cleanup_rxqs(port); | |
6339 | return err; | |
6340 | } | |
6341 | ||
6342 | /* Init all tx queues for port */ | |
6343 | static int mvpp2_setup_txqs(struct mvpp2_port *port) | |
6344 | { | |
6345 | struct mvpp2_tx_queue *txq; | |
6346 | int queue, err; | |
6347 | ||
09f83975 | 6348 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
6349 | txq = port->txqs[queue]; |
6350 | err = mvpp2_txq_init(port, txq); | |
6351 | if (err) | |
6352 | goto err_cleanup; | |
6353 | } | |
6354 | ||
213f428f TP |
6355 | if (port->has_tx_irqs) { |
6356 | mvpp2_tx_time_coal_set(port); | |
6357 | for (queue = 0; queue < port->ntxqs; queue++) { | |
6358 | txq = port->txqs[queue]; | |
6359 | mvpp2_tx_pkts_coal_set(port, txq); | |
6360 | } | |
6361 | } | |
6362 | ||
3f518509 MW |
6363 | on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); |
6364 | return 0; | |
6365 | ||
6366 | err_cleanup: | |
6367 | mvpp2_cleanup_txqs(port); | |
6368 | return err; | |
6369 | } | |
6370 | ||
6371 | /* The callback for per-port interrupt */ | |
6372 | static irqreturn_t mvpp2_isr(int irq, void *dev_id) | |
6373 | { | |
591f4cfa | 6374 | struct mvpp2_queue_vector *qv = dev_id; |
3f518509 | 6375 | |
591f4cfa | 6376 | mvpp2_qvec_interrupt_disable(qv); |
3f518509 | 6377 | |
591f4cfa | 6378 | napi_schedule(&qv->napi); |
3f518509 MW |
6379 | |
6380 | return IRQ_HANDLED; | |
6381 | } | |
6382 | ||
fd3651b2 AT |
6383 | /* Per-port interrupt for link status changes */ |
6384 | static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) | |
6385 | { | |
6386 | struct mvpp2_port *port = (struct mvpp2_port *)dev_id; | |
6387 | struct net_device *dev = port->dev; | |
6388 | bool event = false, link = false; | |
6389 | u32 val; | |
6390 | ||
6391 | mvpp22_gop_mask_irq(port); | |
6392 | ||
6393 | if (port->gop_id == 0 && | |
6394 | port->phy_interface == PHY_INTERFACE_MODE_10GKR) { | |
6395 | val = readl(port->base + MVPP22_XLG_INT_STAT); | |
6396 | if (val & MVPP22_XLG_INT_STAT_LINK) { | |
6397 | event = true; | |
6398 | val = readl(port->base + MVPP22_XLG_STATUS); | |
6399 | if (val & MVPP22_XLG_STATUS_LINK_UP) | |
6400 | link = true; | |
6401 | } | |
6402 | } else if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
6403 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
6404 | val = readl(port->base + MVPP22_GMAC_INT_STAT); | |
6405 | if (val & MVPP22_GMAC_INT_STAT_LINK) { | |
6406 | event = true; | |
6407 | val = readl(port->base + MVPP2_GMAC_STATUS0); | |
6408 | if (val & MVPP2_GMAC_STATUS0_LINK_UP) | |
6409 | link = true; | |
6410 | } | |
6411 | } | |
6412 | ||
6413 | if (!netif_running(dev) || !event) | |
6414 | goto handled; | |
6415 | ||
6416 | if (link) { | |
6417 | mvpp2_interrupts_enable(port); | |
6418 | ||
6419 | mvpp2_egress_enable(port); | |
6420 | mvpp2_ingress_enable(port); | |
6421 | netif_carrier_on(dev); | |
6422 | netif_tx_wake_all_queues(dev); | |
6423 | } else { | |
6424 | netif_tx_stop_all_queues(dev); | |
6425 | netif_carrier_off(dev); | |
6426 | mvpp2_ingress_disable(port); | |
6427 | mvpp2_egress_disable(port); | |
6428 | ||
6429 | mvpp2_interrupts_disable(port); | |
6430 | } | |
6431 | ||
6432 | handled: | |
6433 | mvpp22_gop_unmask_irq(port); | |
6434 | return IRQ_HANDLED; | |
6435 | } | |
6436 | ||
65a2c09a AT |
6437 | static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port, |
6438 | struct phy_device *phydev) | |
6439 | { | |
6440 | u32 val; | |
6441 | ||
6442 | if (port->phy_interface != PHY_INTERFACE_MODE_RGMII && | |
6443 | port->phy_interface != PHY_INTERFACE_MODE_RGMII_ID && | |
6444 | port->phy_interface != PHY_INTERFACE_MODE_RGMII_RXID && | |
6445 | port->phy_interface != PHY_INTERFACE_MODE_RGMII_TXID && | |
6446 | port->phy_interface != PHY_INTERFACE_MODE_SGMII) | |
6447 | return; | |
6448 | ||
6449 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
6450 | val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | | |
6451 | MVPP2_GMAC_CONFIG_GMII_SPEED | | |
6452 | MVPP2_GMAC_CONFIG_FULL_DUPLEX | | |
6453 | MVPP2_GMAC_AN_SPEED_EN | | |
6454 | MVPP2_GMAC_AN_DUPLEX_EN); | |
6455 | ||
6456 | if (phydev->duplex) | |
6457 | val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; | |
6458 | ||
6459 | if (phydev->speed == SPEED_1000) | |
6460 | val |= MVPP2_GMAC_CONFIG_GMII_SPEED; | |
6461 | else if (phydev->speed == SPEED_100) | |
6462 | val |= MVPP2_GMAC_CONFIG_MII_SPEED; | |
6463 | ||
6464 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
65a2c09a AT |
6465 | } |
6466 | ||
3f518509 MW |
6467 | /* Adjust link */ |
6468 | static void mvpp2_link_event(struct net_device *dev) | |
6469 | { | |
6470 | struct mvpp2_port *port = netdev_priv(dev); | |
8e07269d | 6471 | struct phy_device *phydev = dev->phydev; |
89273bc0 | 6472 | bool link_reconfigured = false; |
3f518509 MW |
6473 | u32 val; |
6474 | ||
6475 | if (phydev->link) { | |
89273bc0 AT |
6476 | if (port->phy_interface != phydev->interface && port->comphy) { |
6477 | /* disable current port for reconfiguration */ | |
6478 | mvpp2_interrupts_disable(port); | |
6479 | netif_carrier_off(port->dev); | |
6480 | mvpp2_port_disable(port); | |
6481 | phy_power_off(port->comphy); | |
6482 | ||
6483 | /* comphy reconfiguration */ | |
6484 | port->phy_interface = phydev->interface; | |
6485 | mvpp22_comphy_init(port); | |
6486 | ||
6487 | /* gop/mac reconfiguration */ | |
6488 | mvpp22_gop_init(port); | |
6489 | mvpp2_port_mii_set(port); | |
6490 | ||
6491 | link_reconfigured = true; | |
6492 | } | |
6493 | ||
3f518509 MW |
6494 | if ((port->speed != phydev->speed) || |
6495 | (port->duplex != phydev->duplex)) { | |
65a2c09a | 6496 | mvpp2_gmac_set_autoneg(port, phydev); |
3f518509 MW |
6497 | |
6498 | port->duplex = phydev->duplex; | |
6499 | port->speed = phydev->speed; | |
6500 | } | |
6501 | } | |
6502 | ||
89273bc0 | 6503 | if (phydev->link != port->link || link_reconfigured) { |
3f518509 | 6504 | port->link = phydev->link; |
3f518509 | 6505 | |
3f518509 | 6506 | if (phydev->link) { |
65a2c09a AT |
6507 | if (port->phy_interface == PHY_INTERFACE_MODE_RGMII || |
6508 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || | |
6509 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || | |
6510 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID || | |
6511 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
6512 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
6513 | val |= (MVPP2_GMAC_FORCE_LINK_PASS | | |
6514 | MVPP2_GMAC_FORCE_LINK_DOWN); | |
6515 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
6516 | } | |
f55744ad AT |
6517 | |
6518 | mvpp2_interrupts_enable(port); | |
6519 | mvpp2_port_enable(port); | |
6520 | ||
3f518509 MW |
6521 | mvpp2_egress_enable(port); |
6522 | mvpp2_ingress_enable(port); | |
f55744ad AT |
6523 | netif_carrier_on(dev); |
6524 | netif_tx_wake_all_queues(dev); | |
3f518509 | 6525 | } else { |
968b211c AT |
6526 | port->duplex = -1; |
6527 | port->speed = 0; | |
6528 | ||
f55744ad AT |
6529 | netif_tx_stop_all_queues(dev); |
6530 | netif_carrier_off(dev); | |
3f518509 MW |
6531 | mvpp2_ingress_disable(port); |
6532 | mvpp2_egress_disable(port); | |
f55744ad AT |
6533 | |
6534 | mvpp2_port_disable(port); | |
6535 | mvpp2_interrupts_disable(port); | |
3f518509 | 6536 | } |
968b211c | 6537 | |
3f518509 MW |
6538 | phy_print_status(phydev); |
6539 | } | |
6540 | } | |
6541 | ||
edc660fa MW |
6542 | static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) |
6543 | { | |
6544 | ktime_t interval; | |
6545 | ||
6546 | if (!port_pcpu->timer_scheduled) { | |
6547 | port_pcpu->timer_scheduled = true; | |
8b0e1953 | 6548 | interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; |
edc660fa MW |
6549 | hrtimer_start(&port_pcpu->tx_done_timer, interval, |
6550 | HRTIMER_MODE_REL_PINNED); | |
6551 | } | |
6552 | } | |
6553 | ||
6554 | static void mvpp2_tx_proc_cb(unsigned long data) | |
6555 | { | |
6556 | struct net_device *dev = (struct net_device *)data; | |
6557 | struct mvpp2_port *port = netdev_priv(dev); | |
6558 | struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); | |
6559 | unsigned int tx_todo, cause; | |
6560 | ||
6561 | if (!netif_running(dev)) | |
6562 | return; | |
6563 | port_pcpu->timer_scheduled = false; | |
6564 | ||
6565 | /* Process all the Tx queues */ | |
09f83975 | 6566 | cause = (1 << port->ntxqs) - 1; |
213f428f | 6567 | tx_todo = mvpp2_tx_done(port, cause, smp_processor_id()); |
edc660fa MW |
6568 | |
6569 | /* Set the timer in case not all the packets were processed */ | |
6570 | if (tx_todo) | |
6571 | mvpp2_timer_set(port_pcpu); | |
6572 | } | |
6573 | ||
6574 | static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) | |
6575 | { | |
6576 | struct mvpp2_port_pcpu *port_pcpu = container_of(timer, | |
6577 | struct mvpp2_port_pcpu, | |
6578 | tx_done_timer); | |
6579 | ||
6580 | tasklet_schedule(&port_pcpu->tx_done_tasklet); | |
6581 | ||
6582 | return HRTIMER_NORESTART; | |
6583 | } | |
6584 | ||
3f518509 MW |
6585 | /* Main RX/TX processing routines */ |
6586 | ||
6587 | /* Display more error info */ | |
6588 | static void mvpp2_rx_error(struct mvpp2_port *port, | |
6589 | struct mvpp2_rx_desc *rx_desc) | |
6590 | { | |
ac3dd277 TP |
6591 | u32 status = mvpp2_rxdesc_status_get(port, rx_desc); |
6592 | size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); | |
3f518509 MW |
6593 | |
6594 | switch (status & MVPP2_RXD_ERR_CODE_MASK) { | |
6595 | case MVPP2_RXD_ERR_CRC: | |
ac3dd277 TP |
6596 | netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n", |
6597 | status, sz); | |
3f518509 MW |
6598 | break; |
6599 | case MVPP2_RXD_ERR_OVERRUN: | |
ac3dd277 TP |
6600 | netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n", |
6601 | status, sz); | |
3f518509 MW |
6602 | break; |
6603 | case MVPP2_RXD_ERR_RESOURCE: | |
ac3dd277 TP |
6604 | netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n", |
6605 | status, sz); | |
3f518509 MW |
6606 | break; |
6607 | } | |
6608 | } | |
6609 | ||
6610 | /* Handle RX checksum offload */ | |
6611 | static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, | |
6612 | struct sk_buff *skb) | |
6613 | { | |
6614 | if (((status & MVPP2_RXD_L3_IP4) && | |
6615 | !(status & MVPP2_RXD_IP4_HEADER_ERR)) || | |
6616 | (status & MVPP2_RXD_L3_IP6)) | |
6617 | if (((status & MVPP2_RXD_L4_UDP) || | |
6618 | (status & MVPP2_RXD_L4_TCP)) && | |
6619 | (status & MVPP2_RXD_L4_CSUM_OK)) { | |
6620 | skb->csum = 0; | |
6621 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
6622 | return; | |
6623 | } | |
6624 | ||
6625 | skb->ip_summed = CHECKSUM_NONE; | |
6626 | } | |
6627 | ||
6628 | /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ | |
6629 | static int mvpp2_rx_refill(struct mvpp2_port *port, | |
56b8aae9 | 6630 | struct mvpp2_bm_pool *bm_pool, int pool) |
3f518509 | 6631 | { |
20396136 | 6632 | dma_addr_t dma_addr; |
4e4a105f | 6633 | phys_addr_t phys_addr; |
0e037281 | 6634 | void *buf; |
3f518509 | 6635 | |
3f518509 | 6636 | /* No recycle or too many buffers are in use, so allocate a new skb */ |
4e4a105f TP |
6637 | buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, |
6638 | GFP_ATOMIC); | |
0e037281 | 6639 | if (!buf) |
3f518509 MW |
6640 | return -ENOMEM; |
6641 | ||
7d7627ba | 6642 | mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); |
7ef7e1d9 | 6643 | |
3f518509 MW |
6644 | return 0; |
6645 | } | |
6646 | ||
6647 | /* Handle tx checksum */ | |
6648 | static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) | |
6649 | { | |
6650 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
6651 | int ip_hdr_len = 0; | |
6652 | u8 l4_proto; | |
6653 | ||
6654 | if (skb->protocol == htons(ETH_P_IP)) { | |
6655 | struct iphdr *ip4h = ip_hdr(skb); | |
6656 | ||
6657 | /* Calculate IPv4 checksum and L4 checksum */ | |
6658 | ip_hdr_len = ip4h->ihl; | |
6659 | l4_proto = ip4h->protocol; | |
6660 | } else if (skb->protocol == htons(ETH_P_IPV6)) { | |
6661 | struct ipv6hdr *ip6h = ipv6_hdr(skb); | |
6662 | ||
6663 | /* Read l4_protocol from one of IPv6 extra headers */ | |
6664 | if (skb_network_header_len(skb) > 0) | |
6665 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
6666 | l4_proto = ip6h->nexthdr; | |
6667 | } else { | |
6668 | return MVPP2_TXD_L4_CSUM_NOT; | |
6669 | } | |
6670 | ||
6671 | return mvpp2_txq_desc_csum(skb_network_offset(skb), | |
6672 | skb->protocol, ip_hdr_len, l4_proto); | |
6673 | } | |
6674 | ||
6675 | return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; | |
6676 | } | |
6677 | ||
3f518509 | 6678 | /* Main rx processing */ |
591f4cfa TP |
6679 | static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, |
6680 | int rx_todo, struct mvpp2_rx_queue *rxq) | |
3f518509 MW |
6681 | { |
6682 | struct net_device *dev = port->dev; | |
b5015854 MW |
6683 | int rx_received; |
6684 | int rx_done = 0; | |
3f518509 MW |
6685 | u32 rcvd_pkts = 0; |
6686 | u32 rcvd_bytes = 0; | |
6687 | ||
6688 | /* Get number of received packets and clamp the to-do */ | |
6689 | rx_received = mvpp2_rxq_received(port, rxq->id); | |
6690 | if (rx_todo > rx_received) | |
6691 | rx_todo = rx_received; | |
6692 | ||
b5015854 | 6693 | while (rx_done < rx_todo) { |
3f518509 MW |
6694 | struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); |
6695 | struct mvpp2_bm_pool *bm_pool; | |
6696 | struct sk_buff *skb; | |
0e037281 | 6697 | unsigned int frag_size; |
20396136 | 6698 | dma_addr_t dma_addr; |
ac3dd277 | 6699 | phys_addr_t phys_addr; |
56b8aae9 | 6700 | u32 rx_status; |
3f518509 | 6701 | int pool, rx_bytes, err; |
0e037281 | 6702 | void *data; |
3f518509 | 6703 | |
b5015854 | 6704 | rx_done++; |
ac3dd277 TP |
6705 | rx_status = mvpp2_rxdesc_status_get(port, rx_desc); |
6706 | rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); | |
6707 | rx_bytes -= MVPP2_MH_SIZE; | |
6708 | dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); | |
6709 | phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); | |
6710 | data = (void *)phys_to_virt(phys_addr); | |
6711 | ||
56b8aae9 TP |
6712 | pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> |
6713 | MVPP2_RXD_BM_POOL_ID_OFFS; | |
3f518509 | 6714 | bm_pool = &port->priv->bm_pools[pool]; |
3f518509 MW |
6715 | |
6716 | /* In case of an error, release the requested buffer pointer | |
6717 | * to the Buffer Manager. This request process is controlled | |
6718 | * by the hardware, and the information about the buffer is | |
6719 | * comprised by the RX descriptor. | |
6720 | */ | |
6721 | if (rx_status & MVPP2_RXD_ERR_SUMMARY) { | |
8a52488b | 6722 | err_drop_frame: |
3f518509 MW |
6723 | dev->stats.rx_errors++; |
6724 | mvpp2_rx_error(port, rx_desc); | |
b5015854 | 6725 | /* Return the buffer to the pool */ |
7d7627ba | 6726 | mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); |
3f518509 MW |
6727 | continue; |
6728 | } | |
6729 | ||
0e037281 TP |
6730 | if (bm_pool->frag_size > PAGE_SIZE) |
6731 | frag_size = 0; | |
6732 | else | |
6733 | frag_size = bm_pool->frag_size; | |
6734 | ||
6735 | skb = build_skb(data, frag_size); | |
6736 | if (!skb) { | |
6737 | netdev_warn(port->dev, "skb build failed\n"); | |
6738 | goto err_drop_frame; | |
6739 | } | |
3f518509 | 6740 | |
56b8aae9 | 6741 | err = mvpp2_rx_refill(port, bm_pool, pool); |
b5015854 MW |
6742 | if (err) { |
6743 | netdev_err(port->dev, "failed to refill BM pools\n"); | |
6744 | goto err_drop_frame; | |
6745 | } | |
6746 | ||
20396136 | 6747 | dma_unmap_single(dev->dev.parent, dma_addr, |
4229d502 MW |
6748 | bm_pool->buf_size, DMA_FROM_DEVICE); |
6749 | ||
3f518509 MW |
6750 | rcvd_pkts++; |
6751 | rcvd_bytes += rx_bytes; | |
3f518509 | 6752 | |
0e037281 | 6753 | skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); |
3f518509 MW |
6754 | skb_put(skb, rx_bytes); |
6755 | skb->protocol = eth_type_trans(skb, dev); | |
6756 | mvpp2_rx_csum(port, rx_status, skb); | |
6757 | ||
591f4cfa | 6758 | napi_gro_receive(napi, skb); |
3f518509 MW |
6759 | } |
6760 | ||
6761 | if (rcvd_pkts) { | |
6762 | struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); | |
6763 | ||
6764 | u64_stats_update_begin(&stats->syncp); | |
6765 | stats->rx_packets += rcvd_pkts; | |
6766 | stats->rx_bytes += rcvd_bytes; | |
6767 | u64_stats_update_end(&stats->syncp); | |
6768 | } | |
6769 | ||
6770 | /* Update Rx queue management counters */ | |
6771 | wmb(); | |
b5015854 | 6772 | mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); |
3f518509 MW |
6773 | |
6774 | return rx_todo; | |
6775 | } | |
6776 | ||
6777 | static inline void | |
ac3dd277 | 6778 | tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, |
3f518509 MW |
6779 | struct mvpp2_tx_desc *desc) |
6780 | { | |
20920267 AT |
6781 | struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu); |
6782 | ||
ac3dd277 TP |
6783 | dma_addr_t buf_dma_addr = |
6784 | mvpp2_txdesc_dma_addr_get(port, desc); | |
6785 | size_t buf_sz = | |
6786 | mvpp2_txdesc_size_get(port, desc); | |
20920267 AT |
6787 | if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) |
6788 | dma_unmap_single(port->dev->dev.parent, buf_dma_addr, | |
6789 | buf_sz, DMA_TO_DEVICE); | |
3f518509 MW |
6790 | mvpp2_txq_desc_put(txq); |
6791 | } | |
6792 | ||
6793 | /* Handle tx fragmentation processing */ | |
6794 | static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, | |
6795 | struct mvpp2_tx_queue *aggr_txq, | |
6796 | struct mvpp2_tx_queue *txq) | |
6797 | { | |
6798 | struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu); | |
6799 | struct mvpp2_tx_desc *tx_desc; | |
6800 | int i; | |
20396136 | 6801 | dma_addr_t buf_dma_addr; |
3f518509 MW |
6802 | |
6803 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6804 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6805 | void *addr = page_address(frag->page.p) + frag->page_offset; | |
6806 | ||
6807 | tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
ac3dd277 TP |
6808 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); |
6809 | mvpp2_txdesc_size_set(port, tx_desc, frag->size); | |
3f518509 | 6810 | |
20396136 | 6811 | buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, |
ac3dd277 TP |
6812 | frag->size, |
6813 | DMA_TO_DEVICE); | |
20396136 | 6814 | if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { |
3f518509 | 6815 | mvpp2_txq_desc_put(txq); |
32bae631 | 6816 | goto cleanup; |
3f518509 MW |
6817 | } |
6818 | ||
6eb5d375 | 6819 | mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); |
3f518509 MW |
6820 | |
6821 | if (i == (skb_shinfo(skb)->nr_frags - 1)) { | |
6822 | /* Last descriptor */ | |
ac3dd277 TP |
6823 | mvpp2_txdesc_cmd_set(port, tx_desc, |
6824 | MVPP2_TXD_L_DESC); | |
6825 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
3f518509 MW |
6826 | } else { |
6827 | /* Descriptor in the middle: Not First, Not Last */ | |
ac3dd277 TP |
6828 | mvpp2_txdesc_cmd_set(port, tx_desc, 0); |
6829 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
3f518509 MW |
6830 | } |
6831 | } | |
6832 | ||
6833 | return 0; | |
32bae631 | 6834 | cleanup: |
3f518509 MW |
6835 | /* Release all descriptors that were used to map fragments of |
6836 | * this packet, as well as the corresponding DMA mappings | |
6837 | */ | |
6838 | for (i = i - 1; i >= 0; i--) { | |
6839 | tx_desc = txq->descs + i; | |
ac3dd277 | 6840 | tx_desc_unmap_put(port, txq, tx_desc); |
3f518509 MW |
6841 | } |
6842 | ||
6843 | return -ENOMEM; | |
6844 | } | |
6845 | ||
186cd4d4 AT |
6846 | static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, |
6847 | struct net_device *dev, | |
6848 | struct mvpp2_tx_queue *txq, | |
6849 | struct mvpp2_tx_queue *aggr_txq, | |
6850 | struct mvpp2_txq_pcpu *txq_pcpu, | |
6851 | int hdr_sz) | |
6852 | { | |
6853 | struct mvpp2_port *port = netdev_priv(dev); | |
6854 | struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
6855 | dma_addr_t addr; | |
6856 | ||
6857 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); | |
6858 | mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); | |
6859 | ||
6860 | addr = txq_pcpu->tso_headers_dma + | |
6861 | txq_pcpu->txq_put_index * TSO_HEADER_SIZE; | |
6eb5d375 | 6862 | mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); |
186cd4d4 AT |
6863 | |
6864 | mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | | |
6865 | MVPP2_TXD_F_DESC | | |
6866 | MVPP2_TXD_PADDING_DISABLE); | |
6867 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
6868 | } | |
6869 | ||
6870 | static inline int mvpp2_tso_put_data(struct sk_buff *skb, | |
6871 | struct net_device *dev, struct tso_t *tso, | |
6872 | struct mvpp2_tx_queue *txq, | |
6873 | struct mvpp2_tx_queue *aggr_txq, | |
6874 | struct mvpp2_txq_pcpu *txq_pcpu, | |
6875 | int sz, bool left, bool last) | |
6876 | { | |
6877 | struct mvpp2_port *port = netdev_priv(dev); | |
6878 | struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
6879 | dma_addr_t buf_dma_addr; | |
6880 | ||
6881 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); | |
6882 | mvpp2_txdesc_size_set(port, tx_desc, sz); | |
6883 | ||
6884 | buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, | |
6885 | DMA_TO_DEVICE); | |
6886 | if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { | |
6887 | mvpp2_txq_desc_put(txq); | |
6888 | return -ENOMEM; | |
6889 | } | |
6890 | ||
6eb5d375 | 6891 | mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); |
186cd4d4 AT |
6892 | |
6893 | if (!left) { | |
6894 | mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); | |
6895 | if (last) { | |
6896 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
6897 | return 0; | |
6898 | } | |
6899 | } else { | |
6900 | mvpp2_txdesc_cmd_set(port, tx_desc, 0); | |
6901 | } | |
6902 | ||
6903 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
6904 | return 0; | |
6905 | } | |
6906 | ||
6907 | static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
6908 | struct mvpp2_tx_queue *txq, | |
6909 | struct mvpp2_tx_queue *aggr_txq, | |
6910 | struct mvpp2_txq_pcpu *txq_pcpu) | |
6911 | { | |
6912 | struct mvpp2_port *port = netdev_priv(dev); | |
6913 | struct tso_t tso; | |
6914 | int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
6915 | int i, len, descs = 0; | |
6916 | ||
6917 | /* Check number of available descriptors */ | |
6918 | if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, | |
6919 | tso_count_descs(skb)) || | |
6920 | mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu, | |
6921 | tso_count_descs(skb))) | |
6922 | return 0; | |
6923 | ||
6924 | tso_start(skb, &tso); | |
6925 | len = skb->len - hdr_sz; | |
6926 | while (len > 0) { | |
6927 | int left = min_t(int, skb_shinfo(skb)->gso_size, len); | |
6928 | char *hdr = txq_pcpu->tso_headers + | |
6929 | txq_pcpu->txq_put_index * TSO_HEADER_SIZE; | |
6930 | ||
6931 | len -= left; | |
6932 | descs++; | |
6933 | ||
6934 | tso_build_hdr(skb, hdr, &tso, left, len == 0); | |
6935 | mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); | |
6936 | ||
6937 | while (left > 0) { | |
6938 | int sz = min_t(int, tso.size, left); | |
6939 | left -= sz; | |
6940 | descs++; | |
6941 | ||
6942 | if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, | |
6943 | txq_pcpu, sz, left, len == 0)) | |
6944 | goto release; | |
6945 | tso_build_data(skb, &tso, sz); | |
6946 | } | |
6947 | } | |
6948 | ||
6949 | return descs; | |
6950 | ||
6951 | release: | |
6952 | for (i = descs - 1; i >= 0; i--) { | |
6953 | struct mvpp2_tx_desc *tx_desc = txq->descs + i; | |
6954 | tx_desc_unmap_put(port, txq, tx_desc); | |
6955 | } | |
6956 | return 0; | |
6957 | } | |
6958 | ||
3f518509 MW |
6959 | /* Main tx processing */ |
6960 | static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev) | |
6961 | { | |
6962 | struct mvpp2_port *port = netdev_priv(dev); | |
6963 | struct mvpp2_tx_queue *txq, *aggr_txq; | |
6964 | struct mvpp2_txq_pcpu *txq_pcpu; | |
6965 | struct mvpp2_tx_desc *tx_desc; | |
20396136 | 6966 | dma_addr_t buf_dma_addr; |
3f518509 MW |
6967 | int frags = 0; |
6968 | u16 txq_id; | |
6969 | u32 tx_cmd; | |
6970 | ||
6971 | txq_id = skb_get_queue_mapping(skb); | |
6972 | txq = port->txqs[txq_id]; | |
6973 | txq_pcpu = this_cpu_ptr(txq->pcpu); | |
6974 | aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; | |
6975 | ||
186cd4d4 AT |
6976 | if (skb_is_gso(skb)) { |
6977 | frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); | |
6978 | goto out; | |
6979 | } | |
3f518509 MW |
6980 | frags = skb_shinfo(skb)->nr_frags + 1; |
6981 | ||
6982 | /* Check number of available descriptors */ | |
6983 | if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) || | |
6984 | mvpp2_txq_reserved_desc_num_proc(port->priv, txq, | |
6985 | txq_pcpu, frags)) { | |
6986 | frags = 0; | |
6987 | goto out; | |
6988 | } | |
6989 | ||
6990 | /* Get a descriptor for the first part of the packet */ | |
6991 | tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
ac3dd277 TP |
6992 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); |
6993 | mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); | |
3f518509 | 6994 | |
20396136 | 6995 | buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, |
ac3dd277 | 6996 | skb_headlen(skb), DMA_TO_DEVICE); |
20396136 | 6997 | if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { |
3f518509 MW |
6998 | mvpp2_txq_desc_put(txq); |
6999 | frags = 0; | |
7000 | goto out; | |
7001 | } | |
ac3dd277 | 7002 | |
6eb5d375 | 7003 | mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); |
3f518509 MW |
7004 | |
7005 | tx_cmd = mvpp2_skb_tx_csum(port, skb); | |
7006 | ||
7007 | if (frags == 1) { | |
7008 | /* First and Last descriptor */ | |
7009 | tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; | |
ac3dd277 TP |
7010 | mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); |
7011 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
3f518509 MW |
7012 | } else { |
7013 | /* First but not Last */ | |
7014 | tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; | |
ac3dd277 TP |
7015 | mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); |
7016 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
3f518509 MW |
7017 | |
7018 | /* Continue with other skb fragments */ | |
7019 | if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { | |
ac3dd277 | 7020 | tx_desc_unmap_put(port, txq, tx_desc); |
3f518509 | 7021 | frags = 0; |
3f518509 MW |
7022 | } |
7023 | } | |
7024 | ||
3f518509 MW |
7025 | out: |
7026 | if (frags > 0) { | |
7027 | struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); | |
186cd4d4 AT |
7028 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
7029 | ||
7030 | txq_pcpu->reserved_num -= frags; | |
7031 | txq_pcpu->count += frags; | |
7032 | aggr_txq->count += frags; | |
7033 | ||
7034 | /* Enable transmit */ | |
7035 | wmb(); | |
7036 | mvpp2_aggr_txq_pend_desc_add(port, frags); | |
7037 | ||
1d17db08 | 7038 | if (txq_pcpu->count >= txq_pcpu->stop_threshold) |
186cd4d4 | 7039 | netif_tx_stop_queue(nq); |
3f518509 MW |
7040 | |
7041 | u64_stats_update_begin(&stats->syncp); | |
7042 | stats->tx_packets++; | |
7043 | stats->tx_bytes += skb->len; | |
7044 | u64_stats_update_end(&stats->syncp); | |
7045 | } else { | |
7046 | dev->stats.tx_dropped++; | |
7047 | dev_kfree_skb_any(skb); | |
7048 | } | |
7049 | ||
edc660fa | 7050 | /* Finalize TX processing */ |
082297e6 | 7051 | if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) |
edc660fa MW |
7052 | mvpp2_txq_done(port, txq, txq_pcpu); |
7053 | ||
7054 | /* Set the timer in case not all frags were processed */ | |
213f428f TP |
7055 | if (!port->has_tx_irqs && txq_pcpu->count <= frags && |
7056 | txq_pcpu->count > 0) { | |
edc660fa MW |
7057 | struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); |
7058 | ||
7059 | mvpp2_timer_set(port_pcpu); | |
7060 | } | |
7061 | ||
3f518509 MW |
7062 | return NETDEV_TX_OK; |
7063 | } | |
7064 | ||
7065 | static inline void mvpp2_cause_error(struct net_device *dev, int cause) | |
7066 | { | |
7067 | if (cause & MVPP2_CAUSE_FCS_ERR_MASK) | |
7068 | netdev_err(dev, "FCS error\n"); | |
7069 | if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) | |
7070 | netdev_err(dev, "rx fifo overrun error\n"); | |
7071 | if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) | |
7072 | netdev_err(dev, "tx fifo underrun error\n"); | |
7073 | } | |
7074 | ||
edc660fa | 7075 | static int mvpp2_poll(struct napi_struct *napi, int budget) |
3f518509 | 7076 | { |
213f428f | 7077 | u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; |
edc660fa MW |
7078 | int rx_done = 0; |
7079 | struct mvpp2_port *port = netdev_priv(napi->dev); | |
591f4cfa | 7080 | struct mvpp2_queue_vector *qv; |
a786841d | 7081 | int cpu = smp_processor_id(); |
3f518509 | 7082 | |
591f4cfa TP |
7083 | qv = container_of(napi, struct mvpp2_queue_vector, napi); |
7084 | ||
3f518509 MW |
7085 | /* Rx/Tx cause register |
7086 | * | |
7087 | * Bits 0-15: each bit indicates received packets on the Rx queue | |
7088 | * (bit 0 is for Rx queue 0). | |
7089 | * | |
7090 | * Bits 16-23: each bit indicates transmitted packets on the Tx queue | |
7091 | * (bit 16 is for Tx queue 0). | |
7092 | * | |
7093 | * Each CPU has its own Rx/Tx cause register | |
7094 | */ | |
213f428f | 7095 | cause_rx_tx = mvpp2_percpu_read(port->priv, qv->sw_thread_id, |
a786841d | 7096 | MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); |
3f518509 | 7097 | |
213f428f | 7098 | cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; |
3f518509 MW |
7099 | if (cause_misc) { |
7100 | mvpp2_cause_error(port->dev, cause_misc); | |
7101 | ||
7102 | /* Clear the cause register */ | |
7103 | mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); | |
a786841d TP |
7104 | mvpp2_percpu_write(port->priv, cpu, |
7105 | MVPP2_ISR_RX_TX_CAUSE_REG(port->id), | |
7106 | cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); | |
3f518509 MW |
7107 | } |
7108 | ||
213f428f TP |
7109 | cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; |
7110 | if (cause_tx) { | |
7111 | cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; | |
7112 | mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); | |
7113 | } | |
3f518509 MW |
7114 | |
7115 | /* Process RX packets */ | |
213f428f TP |
7116 | cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; |
7117 | cause_rx <<= qv->first_rxq; | |
591f4cfa | 7118 | cause_rx |= qv->pending_cause_rx; |
3f518509 MW |
7119 | while (cause_rx && budget > 0) { |
7120 | int count; | |
7121 | struct mvpp2_rx_queue *rxq; | |
7122 | ||
7123 | rxq = mvpp2_get_rx_queue(port, cause_rx); | |
7124 | if (!rxq) | |
7125 | break; | |
7126 | ||
591f4cfa | 7127 | count = mvpp2_rx(port, napi, budget, rxq); |
3f518509 MW |
7128 | rx_done += count; |
7129 | budget -= count; | |
7130 | if (budget > 0) { | |
7131 | /* Clear the bit associated to this Rx queue | |
7132 | * so that next iteration will continue from | |
7133 | * the next Rx queue. | |
7134 | */ | |
7135 | cause_rx &= ~(1 << rxq->logic_rxq); | |
7136 | } | |
7137 | } | |
7138 | ||
7139 | if (budget > 0) { | |
7140 | cause_rx = 0; | |
6ad20165 | 7141 | napi_complete_done(napi, rx_done); |
3f518509 | 7142 | |
591f4cfa | 7143 | mvpp2_qvec_interrupt_enable(qv); |
3f518509 | 7144 | } |
591f4cfa | 7145 | qv->pending_cause_rx = cause_rx; |
3f518509 MW |
7146 | return rx_done; |
7147 | } | |
7148 | ||
7149 | /* Set hw internals when starting port */ | |
7150 | static void mvpp2_start_dev(struct mvpp2_port *port) | |
7151 | { | |
8e07269d | 7152 | struct net_device *ndev = port->dev; |
591f4cfa | 7153 | int i; |
8e07269d | 7154 | |
76eb1b1d SC |
7155 | if (port->gop_id == 0 && |
7156 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
7157 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) | |
7158 | mvpp2_xlg_max_rx_size_set(port); | |
7159 | else | |
7160 | mvpp2_gmac_max_rx_size_set(port); | |
7161 | ||
3f518509 MW |
7162 | mvpp2_txp_max_tx_size_set(port); |
7163 | ||
591f4cfa TP |
7164 | for (i = 0; i < port->nqvecs; i++) |
7165 | napi_enable(&port->qvecs[i].napi); | |
3f518509 MW |
7166 | |
7167 | /* Enable interrupts on all CPUs */ | |
7168 | mvpp2_interrupts_enable(port); | |
7169 | ||
542897d9 AT |
7170 | if (port->priv->hw_version == MVPP22) { |
7171 | mvpp22_comphy_init(port); | |
f84bf386 | 7172 | mvpp22_gop_init(port); |
542897d9 | 7173 | } |
f84bf386 | 7174 | |
2055d626 | 7175 | mvpp2_port_mii_set(port); |
3f518509 | 7176 | mvpp2_port_enable(port); |
5997c86b AT |
7177 | if (ndev->phydev) |
7178 | phy_start(ndev->phydev); | |
3f518509 MW |
7179 | netif_tx_start_all_queues(port->dev); |
7180 | } | |
7181 | ||
7182 | /* Set hw internals when stopping port */ | |
7183 | static void mvpp2_stop_dev(struct mvpp2_port *port) | |
7184 | { | |
8e07269d | 7185 | struct net_device *ndev = port->dev; |
591f4cfa | 7186 | int i; |
8e07269d | 7187 | |
3f518509 MW |
7188 | /* Stop new packets from arriving to RXQs */ |
7189 | mvpp2_ingress_disable(port); | |
7190 | ||
7191 | mdelay(10); | |
7192 | ||
7193 | /* Disable interrupts on all CPUs */ | |
7194 | mvpp2_interrupts_disable(port); | |
7195 | ||
591f4cfa TP |
7196 | for (i = 0; i < port->nqvecs; i++) |
7197 | napi_disable(&port->qvecs[i].napi); | |
3f518509 MW |
7198 | |
7199 | netif_carrier_off(port->dev); | |
7200 | netif_tx_stop_all_queues(port->dev); | |
7201 | ||
7202 | mvpp2_egress_disable(port); | |
7203 | mvpp2_port_disable(port); | |
5997c86b AT |
7204 | if (ndev->phydev) |
7205 | phy_stop(ndev->phydev); | |
542897d9 | 7206 | phy_power_off(port->comphy); |
3f518509 MW |
7207 | } |
7208 | ||
3f518509 MW |
7209 | static int mvpp2_check_ringparam_valid(struct net_device *dev, |
7210 | struct ethtool_ringparam *ring) | |
7211 | { | |
7212 | u16 new_rx_pending = ring->rx_pending; | |
7213 | u16 new_tx_pending = ring->tx_pending; | |
7214 | ||
7215 | if (ring->rx_pending == 0 || ring->tx_pending == 0) | |
7216 | return -EINVAL; | |
7217 | ||
7cf87e4a YM |
7218 | if (ring->rx_pending > MVPP2_MAX_RXD_MAX) |
7219 | new_rx_pending = MVPP2_MAX_RXD_MAX; | |
3f518509 MW |
7220 | else if (!IS_ALIGNED(ring->rx_pending, 16)) |
7221 | new_rx_pending = ALIGN(ring->rx_pending, 16); | |
7222 | ||
7cf87e4a YM |
7223 | if (ring->tx_pending > MVPP2_MAX_TXD_MAX) |
7224 | new_tx_pending = MVPP2_MAX_TXD_MAX; | |
3f518509 MW |
7225 | else if (!IS_ALIGNED(ring->tx_pending, 32)) |
7226 | new_tx_pending = ALIGN(ring->tx_pending, 32); | |
7227 | ||
76e583c5 AT |
7228 | /* The Tx ring size cannot be smaller than the minimum number of |
7229 | * descriptors needed for TSO. | |
7230 | */ | |
7231 | if (new_tx_pending < MVPP2_MAX_SKB_DESCS) | |
7232 | new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); | |
7233 | ||
3f518509 MW |
7234 | if (ring->rx_pending != new_rx_pending) { |
7235 | netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", | |
7236 | ring->rx_pending, new_rx_pending); | |
7237 | ring->rx_pending = new_rx_pending; | |
7238 | } | |
7239 | ||
7240 | if (ring->tx_pending != new_tx_pending) { | |
7241 | netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", | |
7242 | ring->tx_pending, new_tx_pending); | |
7243 | ring->tx_pending = new_tx_pending; | |
7244 | } | |
7245 | ||
7246 | return 0; | |
7247 | } | |
7248 | ||
26975821 | 7249 | static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) |
3f518509 MW |
7250 | { |
7251 | u32 mac_addr_l, mac_addr_m, mac_addr_h; | |
7252 | ||
7253 | mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); | |
7254 | mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); | |
7255 | mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); | |
7256 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
7257 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
7258 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
7259 | addr[3] = mac_addr_h & 0xFF; | |
7260 | addr[4] = mac_addr_m & 0xFF; | |
7261 | addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; | |
7262 | } | |
7263 | ||
7264 | static int mvpp2_phy_connect(struct mvpp2_port *port) | |
7265 | { | |
7266 | struct phy_device *phy_dev; | |
7267 | ||
5997c86b AT |
7268 | /* No PHY is attached */ |
7269 | if (!port->phy_node) | |
7270 | return 0; | |
7271 | ||
3f518509 MW |
7272 | phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0, |
7273 | port->phy_interface); | |
7274 | if (!phy_dev) { | |
7275 | netdev_err(port->dev, "cannot connect to phy\n"); | |
7276 | return -ENODEV; | |
7277 | } | |
7278 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
7279 | phy_dev->advertising = phy_dev->supported; | |
7280 | ||
3f518509 MW |
7281 | port->link = 0; |
7282 | port->duplex = 0; | |
7283 | port->speed = 0; | |
7284 | ||
7285 | return 0; | |
7286 | } | |
7287 | ||
7288 | static void mvpp2_phy_disconnect(struct mvpp2_port *port) | |
7289 | { | |
8e07269d PR |
7290 | struct net_device *ndev = port->dev; |
7291 | ||
5997c86b AT |
7292 | if (!ndev->phydev) |
7293 | return; | |
7294 | ||
8e07269d | 7295 | phy_disconnect(ndev->phydev); |
3f518509 MW |
7296 | } |
7297 | ||
591f4cfa TP |
7298 | static int mvpp2_irqs_init(struct mvpp2_port *port) |
7299 | { | |
7300 | int err, i; | |
7301 | ||
7302 | for (i = 0; i < port->nqvecs; i++) { | |
7303 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
7304 | ||
13c249a9 MZ |
7305 | if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) |
7306 | irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); | |
7307 | ||
591f4cfa TP |
7308 | err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); |
7309 | if (err) | |
7310 | goto err; | |
213f428f TP |
7311 | |
7312 | if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) | |
7313 | irq_set_affinity_hint(qv->irq, | |
7314 | cpumask_of(qv->sw_thread_id)); | |
591f4cfa TP |
7315 | } |
7316 | ||
7317 | return 0; | |
7318 | err: | |
7319 | for (i = 0; i < port->nqvecs; i++) { | |
7320 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
7321 | ||
213f428f | 7322 | irq_set_affinity_hint(qv->irq, NULL); |
591f4cfa TP |
7323 | free_irq(qv->irq, qv); |
7324 | } | |
7325 | ||
7326 | return err; | |
7327 | } | |
7328 | ||
7329 | static void mvpp2_irqs_deinit(struct mvpp2_port *port) | |
7330 | { | |
7331 | int i; | |
7332 | ||
7333 | for (i = 0; i < port->nqvecs; i++) { | |
7334 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
7335 | ||
213f428f | 7336 | irq_set_affinity_hint(qv->irq, NULL); |
13c249a9 | 7337 | irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); |
591f4cfa TP |
7338 | free_irq(qv->irq, qv); |
7339 | } | |
7340 | } | |
7341 | ||
1d7d15d7 AT |
7342 | static void mvpp22_init_rss(struct mvpp2_port *port) |
7343 | { | |
7344 | struct mvpp2 *priv = port->priv; | |
7345 | int i; | |
7346 | ||
7347 | /* Set the table width: replace the whole classifier Rx queue number | |
7348 | * with the ones configured in RSS table entries. | |
7349 | */ | |
7350 | mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_TABLE(0)); | |
7351 | mvpp2_write(priv, MVPP22_RSS_WIDTH, 8); | |
7352 | ||
7353 | /* Loop through the classifier Rx Queues and map them to a RSS table. | |
7354 | * Map them all to the first table (0) by default. | |
7355 | */ | |
7356 | for (i = 0; i < MVPP2_CLS_RX_QUEUES; i++) { | |
7357 | mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_QUEUE(i)); | |
7358 | mvpp2_write(priv, MVPP22_RSS_TABLE, | |
7359 | MVPP22_RSS_TABLE_POINTER(0)); | |
7360 | } | |
7361 | ||
7362 | /* Configure the first table to evenly distribute the packets across | |
7363 | * real Rx Queues. The table entries map a hash to an port Rx Queue. | |
7364 | */ | |
7365 | for (i = 0; i < MVPP22_RSS_TABLE_ENTRIES; i++) { | |
7366 | u32 sel = MVPP22_RSS_INDEX_TABLE(0) | | |
7367 | MVPP22_RSS_INDEX_TABLE_ENTRY(i); | |
7368 | mvpp2_write(priv, MVPP22_RSS_INDEX, sel); | |
7369 | ||
7370 | mvpp2_write(priv, MVPP22_RSS_TABLE_ENTRY, i % port->nrxqs); | |
7371 | } | |
7372 | ||
7373 | } | |
7374 | ||
3f518509 MW |
7375 | static int mvpp2_open(struct net_device *dev) |
7376 | { | |
7377 | struct mvpp2_port *port = netdev_priv(dev); | |
fd3651b2 | 7378 | struct mvpp2 *priv = port->priv; |
3f518509 MW |
7379 | unsigned char mac_bcast[ETH_ALEN] = { |
7380 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
7381 | int err; | |
7382 | ||
7383 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true); | |
7384 | if (err) { | |
7385 | netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); | |
7386 | return err; | |
7387 | } | |
7388 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, | |
7389 | dev->dev_addr, true); | |
7390 | if (err) { | |
7391 | netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n"); | |
7392 | return err; | |
7393 | } | |
7394 | err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); | |
7395 | if (err) { | |
7396 | netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); | |
7397 | return err; | |
7398 | } | |
7399 | err = mvpp2_prs_def_flow(port); | |
7400 | if (err) { | |
7401 | netdev_err(dev, "mvpp2_prs_def_flow failed\n"); | |
7402 | return err; | |
7403 | } | |
7404 | ||
7405 | /* Allocate the Rx/Tx queues */ | |
7406 | err = mvpp2_setup_rxqs(port); | |
7407 | if (err) { | |
7408 | netdev_err(port->dev, "cannot allocate Rx queues\n"); | |
7409 | return err; | |
7410 | } | |
7411 | ||
7412 | err = mvpp2_setup_txqs(port); | |
7413 | if (err) { | |
7414 | netdev_err(port->dev, "cannot allocate Tx queues\n"); | |
7415 | goto err_cleanup_rxqs; | |
7416 | } | |
7417 | ||
591f4cfa | 7418 | err = mvpp2_irqs_init(port); |
3f518509 | 7419 | if (err) { |
591f4cfa | 7420 | netdev_err(port->dev, "cannot init IRQs\n"); |
3f518509 MW |
7421 | goto err_cleanup_txqs; |
7422 | } | |
7423 | ||
fd3651b2 AT |
7424 | if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) { |
7425 | err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, | |
7426 | dev->name, port); | |
7427 | if (err) { | |
7428 | netdev_err(port->dev, "cannot request link IRQ %d\n", | |
7429 | port->link_irq); | |
7430 | goto err_free_irq; | |
7431 | } | |
7432 | ||
7433 | mvpp22_gop_setup_irq(port); | |
7434 | } | |
7435 | ||
3f518509 MW |
7436 | /* In default link is down */ |
7437 | netif_carrier_off(port->dev); | |
7438 | ||
7439 | err = mvpp2_phy_connect(port); | |
7440 | if (err < 0) | |
fd3651b2 | 7441 | goto err_free_link_irq; |
3f518509 MW |
7442 | |
7443 | /* Unmask interrupts on all CPUs */ | |
7444 | on_each_cpu(mvpp2_interrupts_unmask, port, 1); | |
213f428f | 7445 | mvpp2_shared_interrupt_mask_unmask(port, false); |
3f518509 MW |
7446 | |
7447 | mvpp2_start_dev(port); | |
7448 | ||
1d7d15d7 AT |
7449 | if (priv->hw_version == MVPP22) |
7450 | mvpp22_init_rss(port); | |
7451 | ||
118d6298 | 7452 | /* Start hardware statistics gathering */ |
e5c500eb | 7453 | queue_delayed_work(priv->stats_queue, &port->stats_work, |
118d6298 MR |
7454 | MVPP2_MIB_COUNTERS_STATS_DELAY); |
7455 | ||
3f518509 MW |
7456 | return 0; |
7457 | ||
fd3651b2 AT |
7458 | err_free_link_irq: |
7459 | if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) | |
7460 | free_irq(port->link_irq, port); | |
3f518509 | 7461 | err_free_irq: |
591f4cfa | 7462 | mvpp2_irqs_deinit(port); |
3f518509 MW |
7463 | err_cleanup_txqs: |
7464 | mvpp2_cleanup_txqs(port); | |
7465 | err_cleanup_rxqs: | |
7466 | mvpp2_cleanup_rxqs(port); | |
7467 | return err; | |
7468 | } | |
7469 | ||
7470 | static int mvpp2_stop(struct net_device *dev) | |
7471 | { | |
7472 | struct mvpp2_port *port = netdev_priv(dev); | |
edc660fa | 7473 | struct mvpp2_port_pcpu *port_pcpu; |
fd3651b2 | 7474 | struct mvpp2 *priv = port->priv; |
edc660fa | 7475 | int cpu; |
3f518509 MW |
7476 | |
7477 | mvpp2_stop_dev(port); | |
7478 | mvpp2_phy_disconnect(port); | |
7479 | ||
7480 | /* Mask interrupts on all CPUs */ | |
7481 | on_each_cpu(mvpp2_interrupts_mask, port, 1); | |
213f428f | 7482 | mvpp2_shared_interrupt_mask_unmask(port, true); |
3f518509 | 7483 | |
fd3651b2 AT |
7484 | if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) |
7485 | free_irq(port->link_irq, port); | |
7486 | ||
591f4cfa | 7487 | mvpp2_irqs_deinit(port); |
213f428f TP |
7488 | if (!port->has_tx_irqs) { |
7489 | for_each_present_cpu(cpu) { | |
7490 | port_pcpu = per_cpu_ptr(port->pcpu, cpu); | |
edc660fa | 7491 | |
213f428f TP |
7492 | hrtimer_cancel(&port_pcpu->tx_done_timer); |
7493 | port_pcpu->timer_scheduled = false; | |
7494 | tasklet_kill(&port_pcpu->tx_done_tasklet); | |
7495 | } | |
edc660fa | 7496 | } |
3f518509 MW |
7497 | mvpp2_cleanup_rxqs(port); |
7498 | mvpp2_cleanup_txqs(port); | |
7499 | ||
e5c500eb | 7500 | cancel_delayed_work_sync(&port->stats_work); |
118d6298 | 7501 | |
3f518509 MW |
7502 | return 0; |
7503 | } | |
7504 | ||
7505 | static void mvpp2_set_rx_mode(struct net_device *dev) | |
7506 | { | |
7507 | struct mvpp2_port *port = netdev_priv(dev); | |
7508 | struct mvpp2 *priv = port->priv; | |
7509 | struct netdev_hw_addr *ha; | |
7510 | int id = port->id; | |
7511 | bool allmulti = dev->flags & IFF_ALLMULTI; | |
7512 | ||
7ac8ff95 | 7513 | retry: |
3f518509 MW |
7514 | mvpp2_prs_mac_promisc_set(priv, id, dev->flags & IFF_PROMISC); |
7515 | mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_ALL, allmulti); | |
7516 | mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_IP6, allmulti); | |
7517 | ||
7518 | /* Remove all port->id's mcast enries */ | |
7519 | mvpp2_prs_mcast_del_all(priv, id); | |
7520 | ||
7ac8ff95 MP |
7521 | if (!allmulti) { |
7522 | netdev_for_each_mc_addr(ha, dev) { | |
7523 | if (mvpp2_prs_mac_da_accept(priv, id, ha->addr, true)) { | |
7524 | allmulti = true; | |
7525 | goto retry; | |
7526 | } | |
7527 | } | |
3f518509 | 7528 | } |
56beda3d MC |
7529 | |
7530 | /* Disable VLAN filtering in promiscuous mode */ | |
7531 | if (dev->flags & IFF_PROMISC) | |
7532 | mvpp2_prs_vid_disable_filtering(port); | |
7533 | else | |
7534 | mvpp2_prs_vid_enable_filtering(port); | |
3f518509 MW |
7535 | } |
7536 | ||
7537 | static int mvpp2_set_mac_address(struct net_device *dev, void *p) | |
7538 | { | |
7539 | struct mvpp2_port *port = netdev_priv(dev); | |
7540 | const struct sockaddr *addr = p; | |
7541 | int err; | |
7542 | ||
7543 | if (!is_valid_ether_addr(addr->sa_data)) { | |
7544 | err = -EADDRNOTAVAIL; | |
c1175547 | 7545 | goto log_error; |
3f518509 MW |
7546 | } |
7547 | ||
7548 | if (!netif_running(dev)) { | |
7549 | err = mvpp2_prs_update_mac_da(dev, addr->sa_data); | |
7550 | if (!err) | |
7551 | return 0; | |
7552 | /* Reconfigure parser to accept the original MAC address */ | |
7553 | err = mvpp2_prs_update_mac_da(dev, dev->dev_addr); | |
7554 | if (err) | |
c1175547 | 7555 | goto log_error; |
3f518509 MW |
7556 | } |
7557 | ||
7558 | mvpp2_stop_dev(port); | |
7559 | ||
7560 | err = mvpp2_prs_update_mac_da(dev, addr->sa_data); | |
7561 | if (!err) | |
7562 | goto out_start; | |
7563 | ||
7564 | /* Reconfigure parser accept the original MAC address */ | |
7565 | err = mvpp2_prs_update_mac_da(dev, dev->dev_addr); | |
7566 | if (err) | |
c1175547 | 7567 | goto log_error; |
3f518509 MW |
7568 | out_start: |
7569 | mvpp2_start_dev(port); | |
7570 | mvpp2_egress_enable(port); | |
7571 | mvpp2_ingress_enable(port); | |
7572 | return 0; | |
c1175547 | 7573 | log_error: |
dfd4240a | 7574 | netdev_err(dev, "failed to change MAC address\n"); |
3f518509 MW |
7575 | return err; |
7576 | } | |
7577 | ||
7578 | static int mvpp2_change_mtu(struct net_device *dev, int mtu) | |
7579 | { | |
7580 | struct mvpp2_port *port = netdev_priv(dev); | |
7581 | int err; | |
7582 | ||
5777987e JW |
7583 | if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { |
7584 | netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, | |
7585 | ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); | |
7586 | mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); | |
3f518509 MW |
7587 | } |
7588 | ||
7589 | if (!netif_running(dev)) { | |
7590 | err = mvpp2_bm_update_mtu(dev, mtu); | |
7591 | if (!err) { | |
7592 | port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
7593 | return 0; | |
7594 | } | |
7595 | ||
7596 | /* Reconfigure BM to the original MTU */ | |
7597 | err = mvpp2_bm_update_mtu(dev, dev->mtu); | |
7598 | if (err) | |
c1175547 | 7599 | goto log_error; |
3f518509 MW |
7600 | } |
7601 | ||
7602 | mvpp2_stop_dev(port); | |
7603 | ||
7604 | err = mvpp2_bm_update_mtu(dev, mtu); | |
7605 | if (!err) { | |
7606 | port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
7607 | goto out_start; | |
7608 | } | |
7609 | ||
7610 | /* Reconfigure BM to the original MTU */ | |
7611 | err = mvpp2_bm_update_mtu(dev, dev->mtu); | |
7612 | if (err) | |
c1175547 | 7613 | goto log_error; |
3f518509 MW |
7614 | |
7615 | out_start: | |
7616 | mvpp2_start_dev(port); | |
7617 | mvpp2_egress_enable(port); | |
7618 | mvpp2_ingress_enable(port); | |
7619 | ||
7620 | return 0; | |
c1175547 | 7621 | log_error: |
dfd4240a | 7622 | netdev_err(dev, "failed to change MTU\n"); |
3f518509 MW |
7623 | return err; |
7624 | } | |
7625 | ||
bc1f4470 | 7626 | static void |
3f518509 MW |
7627 | mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
7628 | { | |
7629 | struct mvpp2_port *port = netdev_priv(dev); | |
7630 | unsigned int start; | |
7631 | int cpu; | |
7632 | ||
7633 | for_each_possible_cpu(cpu) { | |
7634 | struct mvpp2_pcpu_stats *cpu_stats; | |
7635 | u64 rx_packets; | |
7636 | u64 rx_bytes; | |
7637 | u64 tx_packets; | |
7638 | u64 tx_bytes; | |
7639 | ||
7640 | cpu_stats = per_cpu_ptr(port->stats, cpu); | |
7641 | do { | |
7642 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); | |
7643 | rx_packets = cpu_stats->rx_packets; | |
7644 | rx_bytes = cpu_stats->rx_bytes; | |
7645 | tx_packets = cpu_stats->tx_packets; | |
7646 | tx_bytes = cpu_stats->tx_bytes; | |
7647 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); | |
7648 | ||
7649 | stats->rx_packets += rx_packets; | |
7650 | stats->rx_bytes += rx_bytes; | |
7651 | stats->tx_packets += tx_packets; | |
7652 | stats->tx_bytes += tx_bytes; | |
7653 | } | |
7654 | ||
7655 | stats->rx_errors = dev->stats.rx_errors; | |
7656 | stats->rx_dropped = dev->stats.rx_dropped; | |
7657 | stats->tx_dropped = dev->stats.tx_dropped; | |
3f518509 MW |
7658 | } |
7659 | ||
bd695a5f TP |
7660 | static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
7661 | { | |
bd695a5f TP |
7662 | int ret; |
7663 | ||
8e07269d | 7664 | if (!dev->phydev) |
bd695a5f TP |
7665 | return -ENOTSUPP; |
7666 | ||
8e07269d | 7667 | ret = phy_mii_ioctl(dev->phydev, ifr, cmd); |
bd695a5f TP |
7668 | if (!ret) |
7669 | mvpp2_link_event(dev); | |
7670 | ||
7671 | return ret; | |
7672 | } | |
7673 | ||
56beda3d MC |
7674 | static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) |
7675 | { | |
7676 | struct mvpp2_port *port = netdev_priv(dev); | |
7677 | int ret; | |
7678 | ||
7679 | ret = mvpp2_prs_vid_entry_add(port, vid); | |
7680 | if (ret) | |
7681 | netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", | |
7682 | MVPP2_PRS_VLAN_FILT_MAX - 1); | |
7683 | return ret; | |
7684 | } | |
7685 | ||
7686 | static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) | |
7687 | { | |
7688 | struct mvpp2_port *port = netdev_priv(dev); | |
7689 | ||
7690 | mvpp2_prs_vid_entry_remove(port, vid); | |
7691 | return 0; | |
7692 | } | |
7693 | ||
7694 | static int mvpp2_set_features(struct net_device *dev, | |
7695 | netdev_features_t features) | |
7696 | { | |
7697 | netdev_features_t changed = dev->features ^ features; | |
7698 | struct mvpp2_port *port = netdev_priv(dev); | |
7699 | ||
7700 | if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { | |
7701 | if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { | |
7702 | mvpp2_prs_vid_enable_filtering(port); | |
7703 | } else { | |
7704 | /* Invalidate all registered VID filters for this | |
7705 | * port | |
7706 | */ | |
7707 | mvpp2_prs_vid_remove_all(port); | |
7708 | ||
7709 | mvpp2_prs_vid_disable_filtering(port); | |
7710 | } | |
7711 | } | |
7712 | ||
7713 | return 0; | |
7714 | } | |
7715 | ||
3f518509 MW |
7716 | /* Ethtool methods */ |
7717 | ||
3f518509 MW |
7718 | /* Set interrupt coalescing for ethtools */ |
7719 | static int mvpp2_ethtool_set_coalesce(struct net_device *dev, | |
7720 | struct ethtool_coalesce *c) | |
7721 | { | |
7722 | struct mvpp2_port *port = netdev_priv(dev); | |
7723 | int queue; | |
7724 | ||
09f83975 | 7725 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
7726 | struct mvpp2_rx_queue *rxq = port->rxqs[queue]; |
7727 | ||
7728 | rxq->time_coal = c->rx_coalesce_usecs; | |
7729 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
d63f9e41 TP |
7730 | mvpp2_rx_pkts_coal_set(port, rxq); |
7731 | mvpp2_rx_time_coal_set(port, rxq); | |
3f518509 MW |
7732 | } |
7733 | ||
213f428f TP |
7734 | if (port->has_tx_irqs) { |
7735 | port->tx_time_coal = c->tx_coalesce_usecs; | |
7736 | mvpp2_tx_time_coal_set(port); | |
7737 | } | |
7738 | ||
09f83975 | 7739 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
7740 | struct mvpp2_tx_queue *txq = port->txqs[queue]; |
7741 | ||
7742 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
213f428f TP |
7743 | |
7744 | if (port->has_tx_irqs) | |
7745 | mvpp2_tx_pkts_coal_set(port, txq); | |
3f518509 MW |
7746 | } |
7747 | ||
3f518509 MW |
7748 | return 0; |
7749 | } | |
7750 | ||
7751 | /* get coalescing for ethtools */ | |
7752 | static int mvpp2_ethtool_get_coalesce(struct net_device *dev, | |
7753 | struct ethtool_coalesce *c) | |
7754 | { | |
7755 | struct mvpp2_port *port = netdev_priv(dev); | |
7756 | ||
385c284f AT |
7757 | c->rx_coalesce_usecs = port->rxqs[0]->time_coal; |
7758 | c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; | |
7759 | c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; | |
24b28ccb | 7760 | c->tx_coalesce_usecs = port->tx_time_coal; |
3f518509 MW |
7761 | return 0; |
7762 | } | |
7763 | ||
7764 | static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, | |
7765 | struct ethtool_drvinfo *drvinfo) | |
7766 | { | |
7767 | strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, | |
7768 | sizeof(drvinfo->driver)); | |
7769 | strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, | |
7770 | sizeof(drvinfo->version)); | |
7771 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
7772 | sizeof(drvinfo->bus_info)); | |
7773 | } | |
7774 | ||
7775 | static void mvpp2_ethtool_get_ringparam(struct net_device *dev, | |
7776 | struct ethtool_ringparam *ring) | |
7777 | { | |
7778 | struct mvpp2_port *port = netdev_priv(dev); | |
7779 | ||
7cf87e4a YM |
7780 | ring->rx_max_pending = MVPP2_MAX_RXD_MAX; |
7781 | ring->tx_max_pending = MVPP2_MAX_TXD_MAX; | |
3f518509 MW |
7782 | ring->rx_pending = port->rx_ring_size; |
7783 | ring->tx_pending = port->tx_ring_size; | |
7784 | } | |
7785 | ||
7786 | static int mvpp2_ethtool_set_ringparam(struct net_device *dev, | |
7787 | struct ethtool_ringparam *ring) | |
7788 | { | |
7789 | struct mvpp2_port *port = netdev_priv(dev); | |
7790 | u16 prev_rx_ring_size = port->rx_ring_size; | |
7791 | u16 prev_tx_ring_size = port->tx_ring_size; | |
7792 | int err; | |
7793 | ||
7794 | err = mvpp2_check_ringparam_valid(dev, ring); | |
7795 | if (err) | |
7796 | return err; | |
7797 | ||
7798 | if (!netif_running(dev)) { | |
7799 | port->rx_ring_size = ring->rx_pending; | |
7800 | port->tx_ring_size = ring->tx_pending; | |
7801 | return 0; | |
7802 | } | |
7803 | ||
7804 | /* The interface is running, so we have to force a | |
7805 | * reallocation of the queues | |
7806 | */ | |
7807 | mvpp2_stop_dev(port); | |
7808 | mvpp2_cleanup_rxqs(port); | |
7809 | mvpp2_cleanup_txqs(port); | |
7810 | ||
7811 | port->rx_ring_size = ring->rx_pending; | |
7812 | port->tx_ring_size = ring->tx_pending; | |
7813 | ||
7814 | err = mvpp2_setup_rxqs(port); | |
7815 | if (err) { | |
7816 | /* Reallocate Rx queues with the original ring size */ | |
7817 | port->rx_ring_size = prev_rx_ring_size; | |
7818 | ring->rx_pending = prev_rx_ring_size; | |
7819 | err = mvpp2_setup_rxqs(port); | |
7820 | if (err) | |
7821 | goto err_out; | |
7822 | } | |
7823 | err = mvpp2_setup_txqs(port); | |
7824 | if (err) { | |
7825 | /* Reallocate Tx queues with the original ring size */ | |
7826 | port->tx_ring_size = prev_tx_ring_size; | |
7827 | ring->tx_pending = prev_tx_ring_size; | |
7828 | err = mvpp2_setup_txqs(port); | |
7829 | if (err) | |
7830 | goto err_clean_rxqs; | |
7831 | } | |
7832 | ||
7833 | mvpp2_start_dev(port); | |
7834 | mvpp2_egress_enable(port); | |
7835 | mvpp2_ingress_enable(port); | |
7836 | ||
7837 | return 0; | |
7838 | ||
7839 | err_clean_rxqs: | |
7840 | mvpp2_cleanup_rxqs(port); | |
7841 | err_out: | |
dfd4240a | 7842 | netdev_err(dev, "failed to change ring parameters"); |
3f518509 MW |
7843 | return err; |
7844 | } | |
7845 | ||
7846 | /* Device ops */ | |
7847 | ||
7848 | static const struct net_device_ops mvpp2_netdev_ops = { | |
7849 | .ndo_open = mvpp2_open, | |
7850 | .ndo_stop = mvpp2_stop, | |
7851 | .ndo_start_xmit = mvpp2_tx, | |
7852 | .ndo_set_rx_mode = mvpp2_set_rx_mode, | |
7853 | .ndo_set_mac_address = mvpp2_set_mac_address, | |
7854 | .ndo_change_mtu = mvpp2_change_mtu, | |
7855 | .ndo_get_stats64 = mvpp2_get_stats64, | |
bd695a5f | 7856 | .ndo_do_ioctl = mvpp2_ioctl, |
56beda3d MC |
7857 | .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, |
7858 | .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, | |
7859 | .ndo_set_features = mvpp2_set_features, | |
3f518509 MW |
7860 | }; |
7861 | ||
7862 | static const struct ethtool_ops mvpp2_eth_tool_ops = { | |
00606c49 | 7863 | .nway_reset = phy_ethtool_nway_reset, |
3f518509 | 7864 | .get_link = ethtool_op_get_link, |
3f518509 MW |
7865 | .set_coalesce = mvpp2_ethtool_set_coalesce, |
7866 | .get_coalesce = mvpp2_ethtool_get_coalesce, | |
7867 | .get_drvinfo = mvpp2_ethtool_get_drvinfo, | |
7868 | .get_ringparam = mvpp2_ethtool_get_ringparam, | |
7869 | .set_ringparam = mvpp2_ethtool_set_ringparam, | |
118d6298 MR |
7870 | .get_strings = mvpp2_ethtool_get_strings, |
7871 | .get_ethtool_stats = mvpp2_ethtool_get_stats, | |
7872 | .get_sset_count = mvpp2_ethtool_get_sset_count, | |
fb773e97 PR |
7873 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
7874 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
3f518509 MW |
7875 | }; |
7876 | ||
213f428f TP |
7877 | /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that |
7878 | * had a single IRQ defined per-port. | |
7879 | */ | |
7880 | static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, | |
7881 | struct device_node *port_node) | |
591f4cfa TP |
7882 | { |
7883 | struct mvpp2_queue_vector *v = &port->qvecs[0]; | |
7884 | ||
7885 | v->first_rxq = 0; | |
7886 | v->nrxqs = port->nrxqs; | |
7887 | v->type = MVPP2_QUEUE_VECTOR_SHARED; | |
7888 | v->sw_thread_id = 0; | |
7889 | v->sw_thread_mask = *cpumask_bits(cpu_online_mask); | |
7890 | v->port = port; | |
7891 | v->irq = irq_of_parse_and_map(port_node, 0); | |
7892 | if (v->irq <= 0) | |
7893 | return -EINVAL; | |
7894 | netif_napi_add(port->dev, &v->napi, mvpp2_poll, | |
7895 | NAPI_POLL_WEIGHT); | |
7896 | ||
7897 | port->nqvecs = 1; | |
7898 | ||
7899 | return 0; | |
7900 | } | |
7901 | ||
213f428f TP |
7902 | static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, |
7903 | struct device_node *port_node) | |
7904 | { | |
7905 | struct mvpp2_queue_vector *v; | |
7906 | int i, ret; | |
7907 | ||
7908 | port->nqvecs = num_possible_cpus(); | |
7909 | if (queue_mode == MVPP2_QDIST_SINGLE_MODE) | |
7910 | port->nqvecs += 1; | |
7911 | ||
7912 | for (i = 0; i < port->nqvecs; i++) { | |
7913 | char irqname[16]; | |
7914 | ||
7915 | v = port->qvecs + i; | |
7916 | ||
7917 | v->port = port; | |
7918 | v->type = MVPP2_QUEUE_VECTOR_PRIVATE; | |
7919 | v->sw_thread_id = i; | |
7920 | v->sw_thread_mask = BIT(i); | |
7921 | ||
7922 | snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); | |
7923 | ||
7924 | if (queue_mode == MVPP2_QDIST_MULTI_MODE) { | |
7925 | v->first_rxq = i * MVPP2_DEFAULT_RXQ; | |
7926 | v->nrxqs = MVPP2_DEFAULT_RXQ; | |
7927 | } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && | |
7928 | i == (port->nqvecs - 1)) { | |
7929 | v->first_rxq = 0; | |
7930 | v->nrxqs = port->nrxqs; | |
7931 | v->type = MVPP2_QUEUE_VECTOR_SHARED; | |
7932 | strncpy(irqname, "rx-shared", sizeof(irqname)); | |
7933 | } | |
7934 | ||
a75edc7c MW |
7935 | if (port_node) |
7936 | v->irq = of_irq_get_byname(port_node, irqname); | |
7937 | else | |
7938 | v->irq = fwnode_irq_get(port->fwnode, i); | |
213f428f TP |
7939 | if (v->irq <= 0) { |
7940 | ret = -EINVAL; | |
7941 | goto err; | |
7942 | } | |
7943 | ||
7944 | netif_napi_add(port->dev, &v->napi, mvpp2_poll, | |
7945 | NAPI_POLL_WEIGHT); | |
7946 | } | |
7947 | ||
7948 | return 0; | |
7949 | ||
7950 | err: | |
7951 | for (i = 0; i < port->nqvecs; i++) | |
7952 | irq_dispose_mapping(port->qvecs[i].irq); | |
7953 | return ret; | |
7954 | } | |
7955 | ||
7956 | static int mvpp2_queue_vectors_init(struct mvpp2_port *port, | |
7957 | struct device_node *port_node) | |
7958 | { | |
7959 | if (port->has_tx_irqs) | |
7960 | return mvpp2_multi_queue_vectors_init(port, port_node); | |
7961 | else | |
7962 | return mvpp2_simple_queue_vectors_init(port, port_node); | |
7963 | } | |
7964 | ||
591f4cfa TP |
7965 | static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) |
7966 | { | |
7967 | int i; | |
7968 | ||
7969 | for (i = 0; i < port->nqvecs; i++) | |
7970 | irq_dispose_mapping(port->qvecs[i].irq); | |
7971 | } | |
7972 | ||
7973 | /* Configure Rx queue group interrupt for this port */ | |
7974 | static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) | |
7975 | { | |
7976 | struct mvpp2 *priv = port->priv; | |
7977 | u32 val; | |
7978 | int i; | |
7979 | ||
7980 | if (priv->hw_version == MVPP21) { | |
7981 | mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), | |
7982 | port->nrxqs); | |
7983 | return; | |
7984 | } | |
7985 | ||
7986 | /* Handle the more complicated PPv2.2 case */ | |
7987 | for (i = 0; i < port->nqvecs; i++) { | |
7988 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
7989 | ||
7990 | if (!qv->nrxqs) | |
7991 | continue; | |
7992 | ||
7993 | val = qv->sw_thread_id; | |
7994 | val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; | |
7995 | mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); | |
7996 | ||
7997 | val = qv->first_rxq; | |
7998 | val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; | |
7999 | mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); | |
8000 | } | |
8001 | } | |
8002 | ||
3f518509 MW |
8003 | /* Initialize port HW */ |
8004 | static int mvpp2_port_init(struct mvpp2_port *port) | |
8005 | { | |
8006 | struct device *dev = port->dev->dev.parent; | |
8007 | struct mvpp2 *priv = port->priv; | |
8008 | struct mvpp2_txq_pcpu *txq_pcpu; | |
8009 | int queue, cpu, err; | |
8010 | ||
09f83975 TP |
8011 | /* Checks for hardware constraints */ |
8012 | if (port->first_rxq + port->nrxqs > | |
59b9a31e | 8013 | MVPP2_MAX_PORTS * priv->max_port_rxqs) |
3f518509 MW |
8014 | return -EINVAL; |
8015 | ||
09f83975 TP |
8016 | if (port->nrxqs % 4 || (port->nrxqs > priv->max_port_rxqs) || |
8017 | (port->ntxqs > MVPP2_MAX_TXQ)) | |
8018 | return -EINVAL; | |
8019 | ||
3f518509 MW |
8020 | /* Disable port */ |
8021 | mvpp2_egress_disable(port); | |
8022 | mvpp2_port_disable(port); | |
8023 | ||
213f428f TP |
8024 | port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; |
8025 | ||
09f83975 | 8026 | port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), |
3f518509 MW |
8027 | GFP_KERNEL); |
8028 | if (!port->txqs) | |
8029 | return -ENOMEM; | |
8030 | ||
8031 | /* Associate physical Tx queues to this port and initialize. | |
8032 | * The mapping is predefined. | |
8033 | */ | |
09f83975 | 8034 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
8035 | int queue_phy_id = mvpp2_txq_phys(port->id, queue); |
8036 | struct mvpp2_tx_queue *txq; | |
8037 | ||
8038 | txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); | |
177c8d1c CJ |
8039 | if (!txq) { |
8040 | err = -ENOMEM; | |
8041 | goto err_free_percpu; | |
8042 | } | |
3f518509 MW |
8043 | |
8044 | txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); | |
8045 | if (!txq->pcpu) { | |
8046 | err = -ENOMEM; | |
8047 | goto err_free_percpu; | |
8048 | } | |
8049 | ||
8050 | txq->id = queue_phy_id; | |
8051 | txq->log_id = queue; | |
8052 | txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; | |
8053 | for_each_present_cpu(cpu) { | |
8054 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
8055 | txq_pcpu->cpu = cpu; | |
8056 | } | |
8057 | ||
8058 | port->txqs[queue] = txq; | |
8059 | } | |
8060 | ||
09f83975 | 8061 | port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), |
3f518509 MW |
8062 | GFP_KERNEL); |
8063 | if (!port->rxqs) { | |
8064 | err = -ENOMEM; | |
8065 | goto err_free_percpu; | |
8066 | } | |
8067 | ||
8068 | /* Allocate and initialize Rx queue for this port */ | |
09f83975 | 8069 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
8070 | struct mvpp2_rx_queue *rxq; |
8071 | ||
8072 | /* Map physical Rx queue to port's logical Rx queue */ | |
8073 | rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); | |
d82b0c21 JZ |
8074 | if (!rxq) { |
8075 | err = -ENOMEM; | |
3f518509 | 8076 | goto err_free_percpu; |
d82b0c21 | 8077 | } |
3f518509 MW |
8078 | /* Map this Rx queue to a physical queue */ |
8079 | rxq->id = port->first_rxq + queue; | |
8080 | rxq->port = port->id; | |
8081 | rxq->logic_rxq = queue; | |
8082 | ||
8083 | port->rxqs[queue] = rxq; | |
8084 | } | |
8085 | ||
591f4cfa | 8086 | mvpp2_rx_irqs_setup(port); |
3f518509 MW |
8087 | |
8088 | /* Create Rx descriptor rings */ | |
09f83975 | 8089 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
8090 | struct mvpp2_rx_queue *rxq = port->rxqs[queue]; |
8091 | ||
8092 | rxq->size = port->rx_ring_size; | |
8093 | rxq->pkts_coal = MVPP2_RX_COAL_PKTS; | |
8094 | rxq->time_coal = MVPP2_RX_COAL_USEC; | |
8095 | } | |
8096 | ||
8097 | mvpp2_ingress_disable(port); | |
8098 | ||
8099 | /* Port default configuration */ | |
8100 | mvpp2_defaults_set(port); | |
8101 | ||
8102 | /* Port's classifier configuration */ | |
8103 | mvpp2_cls_oversize_rxq_set(port); | |
8104 | mvpp2_cls_port_config(port); | |
8105 | ||
8106 | /* Provide an initial Rx packet size */ | |
8107 | port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); | |
8108 | ||
8109 | /* Initialize pools for swf */ | |
8110 | err = mvpp2_swf_bm_pool_init(port); | |
8111 | if (err) | |
8112 | goto err_free_percpu; | |
8113 | ||
8114 | return 0; | |
8115 | ||
8116 | err_free_percpu: | |
09f83975 | 8117 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
8118 | if (!port->txqs[queue]) |
8119 | continue; | |
8120 | free_percpu(port->txqs[queue]->pcpu); | |
8121 | } | |
8122 | return err; | |
8123 | } | |
8124 | ||
213f428f TP |
8125 | /* Checks if the port DT description has the TX interrupts |
8126 | * described. On PPv2.1, there are no such interrupts. On PPv2.2, | |
8127 | * there are available, but we need to keep support for old DTs. | |
8128 | */ | |
8129 | static bool mvpp2_port_has_tx_irqs(struct mvpp2 *priv, | |
8130 | struct device_node *port_node) | |
8131 | { | |
8132 | char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", | |
8133 | "tx-cpu2", "tx-cpu3" }; | |
8134 | int ret, i; | |
8135 | ||
8136 | if (priv->hw_version == MVPP21) | |
8137 | return false; | |
8138 | ||
8139 | for (i = 0; i < 5; i++) { | |
8140 | ret = of_property_match_string(port_node, "interrupt-names", | |
8141 | irqs[i]); | |
8142 | if (ret < 0) | |
8143 | return false; | |
8144 | } | |
8145 | ||
8146 | return true; | |
8147 | } | |
8148 | ||
3ba8c81e | 8149 | static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, |
24812221 | 8150 | struct fwnode_handle *fwnode, |
3ba8c81e AT |
8151 | char **mac_from) |
8152 | { | |
8153 | struct mvpp2_port *port = netdev_priv(dev); | |
8154 | char hw_mac_addr[ETH_ALEN] = {0}; | |
24812221 | 8155 | char fw_mac_addr[ETH_ALEN]; |
3ba8c81e | 8156 | |
24812221 MW |
8157 | if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { |
8158 | *mac_from = "firmware node"; | |
8159 | ether_addr_copy(dev->dev_addr, fw_mac_addr); | |
688cbaf2 AT |
8160 | return; |
8161 | } | |
d2a6e48e | 8162 | |
688cbaf2 AT |
8163 | if (priv->hw_version == MVPP21) { |
8164 | mvpp21_get_mac_address(port, hw_mac_addr); | |
8165 | if (is_valid_ether_addr(hw_mac_addr)) { | |
8166 | *mac_from = "hardware"; | |
8167 | ether_addr_copy(dev->dev_addr, hw_mac_addr); | |
8168 | return; | |
8169 | } | |
3ba8c81e | 8170 | } |
688cbaf2 AT |
8171 | |
8172 | *mac_from = "random"; | |
8173 | eth_hw_addr_random(dev); | |
3ba8c81e AT |
8174 | } |
8175 | ||
3f518509 MW |
8176 | /* Ports initialization */ |
8177 | static int mvpp2_port_probe(struct platform_device *pdev, | |
24812221 | 8178 | struct fwnode_handle *port_fwnode, |
bf147153 | 8179 | struct mvpp2 *priv) |
3f518509 MW |
8180 | { |
8181 | struct device_node *phy_node; | |
a75edc7c | 8182 | struct phy *comphy = NULL; |
3f518509 | 8183 | struct mvpp2_port *port; |
edc660fa | 8184 | struct mvpp2_port_pcpu *port_pcpu; |
24812221 | 8185 | struct device_node *port_node = to_of_node(port_fwnode); |
3f518509 MW |
8186 | struct net_device *dev; |
8187 | struct resource *res; | |
3ba8c81e | 8188 | char *mac_from = ""; |
09f83975 | 8189 | unsigned int ntxqs, nrxqs; |
213f428f | 8190 | bool has_tx_irqs; |
3f518509 MW |
8191 | u32 id; |
8192 | int features; | |
8193 | int phy_mode; | |
edc660fa | 8194 | int err, i, cpu; |
3f518509 | 8195 | |
a75edc7c MW |
8196 | if (port_node) { |
8197 | has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node); | |
8198 | } else { | |
8199 | has_tx_irqs = true; | |
8200 | queue_mode = MVPP2_QDIST_MULTI_MODE; | |
8201 | } | |
213f428f TP |
8202 | |
8203 | if (!has_tx_irqs) | |
8204 | queue_mode = MVPP2_QDIST_SINGLE_MODE; | |
8205 | ||
09f83975 | 8206 | ntxqs = MVPP2_MAX_TXQ; |
213f428f TP |
8207 | if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE) |
8208 | nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus(); | |
8209 | else | |
8210 | nrxqs = MVPP2_DEFAULT_RXQ; | |
09f83975 TP |
8211 | |
8212 | dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); | |
3f518509 MW |
8213 | if (!dev) |
8214 | return -ENOMEM; | |
8215 | ||
a75edc7c MW |
8216 | if (port_node) |
8217 | phy_node = of_parse_phandle(port_node, "phy", 0); | |
8218 | else | |
8219 | phy_node = NULL; | |
8220 | ||
24812221 | 8221 | phy_mode = fwnode_get_phy_mode(port_fwnode); |
3f518509 MW |
8222 | if (phy_mode < 0) { |
8223 | dev_err(&pdev->dev, "incorrect phy mode\n"); | |
8224 | err = phy_mode; | |
8225 | goto err_free_netdev; | |
8226 | } | |
8227 | ||
a75edc7c MW |
8228 | if (port_node) { |
8229 | comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); | |
8230 | if (IS_ERR(comphy)) { | |
8231 | if (PTR_ERR(comphy) == -EPROBE_DEFER) { | |
8232 | err = -EPROBE_DEFER; | |
8233 | goto err_free_netdev; | |
8234 | } | |
8235 | comphy = NULL; | |
542897d9 | 8236 | } |
542897d9 AT |
8237 | } |
8238 | ||
24812221 | 8239 | if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { |
3f518509 MW |
8240 | err = -EINVAL; |
8241 | dev_err(&pdev->dev, "missing port-id value\n"); | |
8242 | goto err_free_netdev; | |
8243 | } | |
8244 | ||
7cf87e4a | 8245 | dev->tx_queue_len = MVPP2_MAX_TXD_MAX; |
3f518509 MW |
8246 | dev->watchdog_timeo = 5 * HZ; |
8247 | dev->netdev_ops = &mvpp2_netdev_ops; | |
8248 | dev->ethtool_ops = &mvpp2_eth_tool_ops; | |
8249 | ||
8250 | port = netdev_priv(dev); | |
591f4cfa | 8251 | port->dev = dev; |
a75edc7c | 8252 | port->fwnode = port_fwnode; |
09f83975 TP |
8253 | port->ntxqs = ntxqs; |
8254 | port->nrxqs = nrxqs; | |
213f428f TP |
8255 | port->priv = priv; |
8256 | port->has_tx_irqs = has_tx_irqs; | |
3f518509 | 8257 | |
591f4cfa TP |
8258 | err = mvpp2_queue_vectors_init(port, port_node); |
8259 | if (err) | |
3f518509 | 8260 | goto err_free_netdev; |
3f518509 | 8261 | |
a75edc7c MW |
8262 | if (port_node) |
8263 | port->link_irq = of_irq_get_byname(port_node, "link"); | |
8264 | else | |
8265 | port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); | |
fd3651b2 AT |
8266 | if (port->link_irq == -EPROBE_DEFER) { |
8267 | err = -EPROBE_DEFER; | |
8268 | goto err_deinit_qvecs; | |
8269 | } | |
8270 | if (port->link_irq <= 0) | |
8271 | /* the link irq is optional */ | |
8272 | port->link_irq = 0; | |
8273 | ||
24812221 | 8274 | if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) |
3f518509 MW |
8275 | port->flags |= MVPP2_F_LOOPBACK; |
8276 | ||
3f518509 | 8277 | port->id = id; |
59b9a31e | 8278 | if (priv->hw_version == MVPP21) |
09f83975 | 8279 | port->first_rxq = port->id * port->nrxqs; |
59b9a31e TP |
8280 | else |
8281 | port->first_rxq = port->id * priv->max_port_rxqs; | |
8282 | ||
3f518509 MW |
8283 | port->phy_node = phy_node; |
8284 | port->phy_interface = phy_mode; | |
542897d9 | 8285 | port->comphy = comphy; |
3f518509 | 8286 | |
a786841d TP |
8287 | if (priv->hw_version == MVPP21) { |
8288 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id); | |
8289 | port->base = devm_ioremap_resource(&pdev->dev, res); | |
8290 | if (IS_ERR(port->base)) { | |
8291 | err = PTR_ERR(port->base); | |
fd3651b2 | 8292 | goto err_free_irq; |
a786841d | 8293 | } |
118d6298 MR |
8294 | |
8295 | port->stats_base = port->priv->lms_base + | |
8296 | MVPP21_MIB_COUNTERS_OFFSET + | |
8297 | port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; | |
a786841d | 8298 | } else { |
24812221 MW |
8299 | if (fwnode_property_read_u32(port_fwnode, "gop-port-id", |
8300 | &port->gop_id)) { | |
a786841d TP |
8301 | err = -EINVAL; |
8302 | dev_err(&pdev->dev, "missing gop-port-id value\n"); | |
591f4cfa | 8303 | goto err_deinit_qvecs; |
a786841d TP |
8304 | } |
8305 | ||
8306 | port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); | |
118d6298 MR |
8307 | port->stats_base = port->priv->iface_base + |
8308 | MVPP22_MIB_COUNTERS_OFFSET + | |
8309 | port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; | |
3f518509 MW |
8310 | } |
8311 | ||
118d6298 | 8312 | /* Alloc per-cpu and ethtool stats */ |
3f518509 MW |
8313 | port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); |
8314 | if (!port->stats) { | |
8315 | err = -ENOMEM; | |
fd3651b2 | 8316 | goto err_free_irq; |
3f518509 MW |
8317 | } |
8318 | ||
118d6298 MR |
8319 | port->ethtool_stats = devm_kcalloc(&pdev->dev, |
8320 | ARRAY_SIZE(mvpp2_ethtool_regs), | |
8321 | sizeof(u64), GFP_KERNEL); | |
8322 | if (!port->ethtool_stats) { | |
8323 | err = -ENOMEM; | |
8324 | goto err_free_stats; | |
8325 | } | |
8326 | ||
e5c500eb MR |
8327 | mutex_init(&port->gather_stats_lock); |
8328 | INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); | |
8329 | ||
24812221 | 8330 | mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); |
3f518509 | 8331 | |
7cf87e4a YM |
8332 | port->tx_ring_size = MVPP2_MAX_TXD_DFLT; |
8333 | port->rx_ring_size = MVPP2_MAX_RXD_DFLT; | |
3f518509 MW |
8334 | SET_NETDEV_DEV(dev, &pdev->dev); |
8335 | ||
8336 | err = mvpp2_port_init(port); | |
8337 | if (err < 0) { | |
8338 | dev_err(&pdev->dev, "failed to init port %d\n", id); | |
8339 | goto err_free_stats; | |
8340 | } | |
26975821 | 8341 | |
26975821 TP |
8342 | mvpp2_port_periodic_xon_disable(port); |
8343 | ||
8344 | if (priv->hw_version == MVPP21) | |
8345 | mvpp2_port_fc_adv_enable(port); | |
8346 | ||
8347 | mvpp2_port_reset(port); | |
3f518509 | 8348 | |
edc660fa MW |
8349 | port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); |
8350 | if (!port->pcpu) { | |
8351 | err = -ENOMEM; | |
8352 | goto err_free_txq_pcpu; | |
8353 | } | |
8354 | ||
213f428f TP |
8355 | if (!port->has_tx_irqs) { |
8356 | for_each_present_cpu(cpu) { | |
8357 | port_pcpu = per_cpu_ptr(port->pcpu, cpu); | |
edc660fa | 8358 | |
213f428f TP |
8359 | hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, |
8360 | HRTIMER_MODE_REL_PINNED); | |
8361 | port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; | |
8362 | port_pcpu->timer_scheduled = false; | |
edc660fa | 8363 | |
213f428f TP |
8364 | tasklet_init(&port_pcpu->tx_done_tasklet, |
8365 | mvpp2_tx_proc_cb, | |
8366 | (unsigned long)dev); | |
8367 | } | |
edc660fa MW |
8368 | } |
8369 | ||
381c5671 AT |
8370 | features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
8371 | NETIF_F_TSO; | |
3f518509 | 8372 | dev->features = features | NETIF_F_RXCSUM; |
56beda3d MC |
8373 | dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | |
8374 | NETIF_F_HW_VLAN_CTAG_FILTER; | |
576193f2 SC |
8375 | |
8376 | if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) { | |
8377 | dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); | |
8378 | dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); | |
8379 | } | |
8380 | ||
3f518509 | 8381 | dev->vlan_features |= features; |
1d17db08 | 8382 | dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; |
3f518509 | 8383 | |
576193f2 | 8384 | /* MTU range: 68 - 9704 */ |
5777987e | 8385 | dev->min_mtu = ETH_MIN_MTU; |
576193f2 SC |
8386 | /* 9704 == 9728 - 20 and rounding to 8 */ |
8387 | dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; | |
5777987e | 8388 | |
3f518509 MW |
8389 | err = register_netdev(dev); |
8390 | if (err < 0) { | |
8391 | dev_err(&pdev->dev, "failed to register netdev\n"); | |
edc660fa | 8392 | goto err_free_port_pcpu; |
3f518509 MW |
8393 | } |
8394 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); | |
8395 | ||
bf147153 MW |
8396 | priv->port_list[priv->port_count++] = port; |
8397 | ||
3f518509 MW |
8398 | return 0; |
8399 | ||
edc660fa MW |
8400 | err_free_port_pcpu: |
8401 | free_percpu(port->pcpu); | |
3f518509 | 8402 | err_free_txq_pcpu: |
09f83975 | 8403 | for (i = 0; i < port->ntxqs; i++) |
3f518509 MW |
8404 | free_percpu(port->txqs[i]->pcpu); |
8405 | err_free_stats: | |
8406 | free_percpu(port->stats); | |
fd3651b2 AT |
8407 | err_free_irq: |
8408 | if (port->link_irq) | |
8409 | irq_dispose_mapping(port->link_irq); | |
591f4cfa TP |
8410 | err_deinit_qvecs: |
8411 | mvpp2_queue_vectors_deinit(port); | |
3f518509 | 8412 | err_free_netdev: |
ccb80393 | 8413 | of_node_put(phy_node); |
3f518509 MW |
8414 | free_netdev(dev); |
8415 | return err; | |
8416 | } | |
8417 | ||
8418 | /* Ports removal routine */ | |
8419 | static void mvpp2_port_remove(struct mvpp2_port *port) | |
8420 | { | |
8421 | int i; | |
8422 | ||
8423 | unregister_netdev(port->dev); | |
ccb80393 | 8424 | of_node_put(port->phy_node); |
edc660fa | 8425 | free_percpu(port->pcpu); |
3f518509 | 8426 | free_percpu(port->stats); |
09f83975 | 8427 | for (i = 0; i < port->ntxqs; i++) |
3f518509 | 8428 | free_percpu(port->txqs[i]->pcpu); |
591f4cfa | 8429 | mvpp2_queue_vectors_deinit(port); |
fd3651b2 AT |
8430 | if (port->link_irq) |
8431 | irq_dispose_mapping(port->link_irq); | |
3f518509 MW |
8432 | free_netdev(port->dev); |
8433 | } | |
8434 | ||
8435 | /* Initialize decoding windows */ | |
8436 | static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, | |
8437 | struct mvpp2 *priv) | |
8438 | { | |
8439 | u32 win_enable; | |
8440 | int i; | |
8441 | ||
8442 | for (i = 0; i < 6; i++) { | |
8443 | mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); | |
8444 | mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); | |
8445 | ||
8446 | if (i < 4) | |
8447 | mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); | |
8448 | } | |
8449 | ||
8450 | win_enable = 0; | |
8451 | ||
8452 | for (i = 0; i < dram->num_cs; i++) { | |
8453 | const struct mbus_dram_window *cs = dram->cs + i; | |
8454 | ||
8455 | mvpp2_write(priv, MVPP2_WIN_BASE(i), | |
8456 | (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | | |
8457 | dram->mbus_dram_target_id); | |
8458 | ||
8459 | mvpp2_write(priv, MVPP2_WIN_SIZE(i), | |
8460 | (cs->size - 1) & 0xffff0000); | |
8461 | ||
8462 | win_enable |= (1 << i); | |
8463 | } | |
8464 | ||
8465 | mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); | |
8466 | } | |
8467 | ||
8468 | /* Initialize Rx FIFO's */ | |
8469 | static void mvpp2_rx_fifo_init(struct mvpp2 *priv) | |
8470 | { | |
8471 | int port; | |
8472 | ||
8473 | for (port = 0; port < MVPP2_MAX_PORTS; port++) { | |
8474 | mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), | |
2d1d7df8 | 8475 | MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); |
3f518509 | 8476 | mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), |
2d1d7df8 AT |
8477 | MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); |
8478 | } | |
8479 | ||
8480 | mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, | |
8481 | MVPP2_RX_FIFO_PORT_MIN_PKT); | |
8482 | mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); | |
8483 | } | |
8484 | ||
8485 | static void mvpp22_rx_fifo_init(struct mvpp2 *priv) | |
8486 | { | |
8487 | int port; | |
8488 | ||
8489 | /* The FIFO size parameters are set depending on the maximum speed a | |
8490 | * given port can handle: | |
8491 | * - Port 0: 10Gbps | |
8492 | * - Port 1: 2.5Gbps | |
8493 | * - Ports 2 and 3: 1Gbps | |
8494 | */ | |
8495 | ||
8496 | mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), | |
8497 | MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); | |
8498 | mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), | |
8499 | MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); | |
8500 | ||
8501 | mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), | |
8502 | MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); | |
8503 | mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), | |
8504 | MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); | |
8505 | ||
8506 | for (port = 2; port < MVPP2_MAX_PORTS; port++) { | |
8507 | mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), | |
8508 | MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); | |
8509 | mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), | |
8510 | MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); | |
3f518509 MW |
8511 | } |
8512 | ||
8513 | mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, | |
8514 | MVPP2_RX_FIFO_PORT_MIN_PKT); | |
8515 | mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); | |
8516 | } | |
8517 | ||
93ff130f YM |
8518 | /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G |
8519 | * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, | |
8520 | * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. | |
8521 | */ | |
7c10f974 AT |
8522 | static void mvpp22_tx_fifo_init(struct mvpp2 *priv) |
8523 | { | |
93ff130f | 8524 | int port, size, thrs; |
7c10f974 | 8525 | |
93ff130f YM |
8526 | for (port = 0; port < MVPP2_MAX_PORTS; port++) { |
8527 | if (port == 0) { | |
8528 | size = MVPP22_TX_FIFO_DATA_SIZE_10KB; | |
8529 | thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; | |
8530 | } else { | |
8531 | size = MVPP22_TX_FIFO_DATA_SIZE_3KB; | |
8532 | thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; | |
8533 | } | |
8534 | mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); | |
8535 | mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); | |
8536 | } | |
7c10f974 AT |
8537 | } |
8538 | ||
6763ce31 TP |
8539 | static void mvpp2_axi_init(struct mvpp2 *priv) |
8540 | { | |
8541 | u32 val, rdval, wrval; | |
8542 | ||
8543 | mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); | |
8544 | ||
8545 | /* AXI Bridge Configuration */ | |
8546 | ||
8547 | rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE | |
8548 | << MVPP22_AXI_ATTR_CACHE_OFFS; | |
8549 | rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
8550 | << MVPP22_AXI_ATTR_DOMAIN_OFFS; | |
8551 | ||
8552 | wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE | |
8553 | << MVPP22_AXI_ATTR_CACHE_OFFS; | |
8554 | wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
8555 | << MVPP22_AXI_ATTR_DOMAIN_OFFS; | |
8556 | ||
8557 | /* BM */ | |
8558 | mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); | |
8559 | mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); | |
8560 | ||
8561 | /* Descriptors */ | |
8562 | mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); | |
8563 | mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); | |
8564 | mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); | |
8565 | mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); | |
8566 | ||
8567 | /* Buffer Data */ | |
8568 | mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); | |
8569 | mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); | |
8570 | ||
8571 | val = MVPP22_AXI_CODE_CACHE_NON_CACHE | |
8572 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
8573 | val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM | |
8574 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
8575 | mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); | |
8576 | mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); | |
8577 | ||
8578 | val = MVPP22_AXI_CODE_CACHE_RD_CACHE | |
8579 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
8580 | val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
8581 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
8582 | ||
8583 | mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); | |
8584 | ||
8585 | val = MVPP22_AXI_CODE_CACHE_WR_CACHE | |
8586 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
8587 | val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
8588 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
8589 | ||
8590 | mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); | |
8591 | } | |
8592 | ||
3f518509 MW |
8593 | /* Initialize network controller common part HW */ |
8594 | static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) | |
8595 | { | |
8596 | const struct mbus_dram_target_info *dram_target_info; | |
8597 | int err, i; | |
08a23755 | 8598 | u32 val; |
3f518509 | 8599 | |
3f518509 MW |
8600 | /* MBUS windows configuration */ |
8601 | dram_target_info = mv_mbus_dram_info(); | |
8602 | if (dram_target_info) | |
8603 | mvpp2_conf_mbus_windows(dram_target_info, priv); | |
8604 | ||
6763ce31 TP |
8605 | if (priv->hw_version == MVPP22) |
8606 | mvpp2_axi_init(priv); | |
8607 | ||
08a23755 | 8608 | /* Disable HW PHY polling */ |
26975821 TP |
8609 | if (priv->hw_version == MVPP21) { |
8610 | val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); | |
8611 | val |= MVPP2_PHY_AN_STOP_SMI0_MASK; | |
8612 | writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); | |
8613 | } else { | |
8614 | val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); | |
8615 | val &= ~MVPP22_SMI_POLLING_EN; | |
8616 | writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); | |
8617 | } | |
08a23755 | 8618 | |
3f518509 MW |
8619 | /* Allocate and initialize aggregated TXQs */ |
8620 | priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(), | |
d7ce3cec | 8621 | sizeof(*priv->aggr_txqs), |
3f518509 MW |
8622 | GFP_KERNEL); |
8623 | if (!priv->aggr_txqs) | |
8624 | return -ENOMEM; | |
8625 | ||
8626 | for_each_present_cpu(i) { | |
8627 | priv->aggr_txqs[i].id = i; | |
8628 | priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; | |
85affd7e | 8629 | err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); |
3f518509 MW |
8630 | if (err < 0) |
8631 | return err; | |
8632 | } | |
8633 | ||
7c10f974 AT |
8634 | /* Fifo Init */ |
8635 | if (priv->hw_version == MVPP21) { | |
2d1d7df8 | 8636 | mvpp2_rx_fifo_init(priv); |
7c10f974 | 8637 | } else { |
2d1d7df8 | 8638 | mvpp22_rx_fifo_init(priv); |
7c10f974 AT |
8639 | mvpp22_tx_fifo_init(priv); |
8640 | } | |
3f518509 | 8641 | |
26975821 TP |
8642 | if (priv->hw_version == MVPP21) |
8643 | writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, | |
8644 | priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); | |
3f518509 MW |
8645 | |
8646 | /* Allow cache snoop when transmiting packets */ | |
8647 | mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); | |
8648 | ||
8649 | /* Buffer Manager initialization */ | |
8650 | err = mvpp2_bm_init(pdev, priv); | |
8651 | if (err < 0) | |
8652 | return err; | |
8653 | ||
8654 | /* Parser default initialization */ | |
8655 | err = mvpp2_prs_default_init(pdev, priv); | |
8656 | if (err < 0) | |
8657 | return err; | |
8658 | ||
8659 | /* Classifier default initialization */ | |
8660 | mvpp2_cls_init(priv); | |
8661 | ||
8662 | return 0; | |
8663 | } | |
8664 | ||
8665 | static int mvpp2_probe(struct platform_device *pdev) | |
8666 | { | |
a75edc7c | 8667 | const struct acpi_device_id *acpi_id; |
24812221 MW |
8668 | struct fwnode_handle *fwnode = pdev->dev.fwnode; |
8669 | struct fwnode_handle *port_fwnode; | |
3f518509 MW |
8670 | struct mvpp2 *priv; |
8671 | struct resource *res; | |
a786841d | 8672 | void __iomem *base; |
118d6298 | 8673 | int i; |
3f518509 MW |
8674 | int err; |
8675 | ||
0b92e594 | 8676 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
3f518509 MW |
8677 | if (!priv) |
8678 | return -ENOMEM; | |
8679 | ||
a75edc7c MW |
8680 | if (has_acpi_companion(&pdev->dev)) { |
8681 | acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, | |
8682 | &pdev->dev); | |
8683 | priv->hw_version = (unsigned long)acpi_id->driver_data; | |
8684 | } else { | |
8685 | priv->hw_version = | |
8686 | (unsigned long)of_device_get_match_data(&pdev->dev); | |
8687 | } | |
faca9247 | 8688 | |
3f518509 | 8689 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a786841d TP |
8690 | base = devm_ioremap_resource(&pdev->dev, res); |
8691 | if (IS_ERR(base)) | |
8692 | return PTR_ERR(base); | |
8693 | ||
8694 | if (priv->hw_version == MVPP21) { | |
8695 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
8696 | priv->lms_base = devm_ioremap_resource(&pdev->dev, res); | |
8697 | if (IS_ERR(priv->lms_base)) | |
8698 | return PTR_ERR(priv->lms_base); | |
8699 | } else { | |
8700 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
a75edc7c MW |
8701 | if (has_acpi_companion(&pdev->dev)) { |
8702 | /* In case the MDIO memory region is declared in | |
8703 | * the ACPI, it can already appear as 'in-use' | |
8704 | * in the OS. Because it is overlapped by second | |
8705 | * region of the network controller, make | |
8706 | * sure it is released, before requesting it again. | |
8707 | * The care is taken by mvpp2 driver to avoid | |
8708 | * concurrent access to this memory region. | |
8709 | */ | |
8710 | release_resource(res); | |
8711 | } | |
a786841d TP |
8712 | priv->iface_base = devm_ioremap_resource(&pdev->dev, res); |
8713 | if (IS_ERR(priv->iface_base)) | |
8714 | return PTR_ERR(priv->iface_base); | |
a75edc7c | 8715 | } |
f84bf386 | 8716 | |
a75edc7c | 8717 | if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { |
f84bf386 AT |
8718 | priv->sysctrl_base = |
8719 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
8720 | "marvell,system-controller"); | |
8721 | if (IS_ERR(priv->sysctrl_base)) | |
8722 | /* The system controller regmap is optional for dt | |
8723 | * compatibility reasons. When not provided, the | |
8724 | * configuration of the GoP relies on the | |
8725 | * firmware/bootloader. | |
8726 | */ | |
8727 | priv->sysctrl_base = NULL; | |
a786841d TP |
8728 | } |
8729 | ||
01d04936 SC |
8730 | mvpp2_setup_bm_pool(); |
8731 | ||
df089aa0 | 8732 | for (i = 0; i < MVPP2_MAX_THREADS; i++) { |
a786841d TP |
8733 | u32 addr_space_sz; |
8734 | ||
8735 | addr_space_sz = (priv->hw_version == MVPP21 ? | |
8736 | MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); | |
df089aa0 | 8737 | priv->swth_base[i] = base + i * addr_space_sz; |
a786841d | 8738 | } |
3f518509 | 8739 | |
59b9a31e TP |
8740 | if (priv->hw_version == MVPP21) |
8741 | priv->max_port_rxqs = 8; | |
8742 | else | |
8743 | priv->max_port_rxqs = 32; | |
8744 | ||
a75edc7c MW |
8745 | if (dev_of_node(&pdev->dev)) { |
8746 | priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); | |
8747 | if (IS_ERR(priv->pp_clk)) | |
8748 | return PTR_ERR(priv->pp_clk); | |
8749 | err = clk_prepare_enable(priv->pp_clk); | |
8750 | if (err < 0) | |
8751 | return err; | |
3f518509 | 8752 | |
a75edc7c MW |
8753 | priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); |
8754 | if (IS_ERR(priv->gop_clk)) { | |
8755 | err = PTR_ERR(priv->gop_clk); | |
8756 | goto err_pp_clk; | |
fceb55d4 | 8757 | } |
a75edc7c | 8758 | err = clk_prepare_enable(priv->gop_clk); |
fceb55d4 | 8759 | if (err < 0) |
a75edc7c MW |
8760 | goto err_pp_clk; |
8761 | ||
8762 | if (priv->hw_version == MVPP22) { | |
8763 | priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); | |
8764 | if (IS_ERR(priv->mg_clk)) { | |
8765 | err = PTR_ERR(priv->mg_clk); | |
8766 | goto err_gop_clk; | |
8767 | } | |
8768 | ||
8769 | err = clk_prepare_enable(priv->mg_clk); | |
8770 | if (err < 0) | |
8771 | goto err_gop_clk; | |
8772 | } | |
4792ea04 GC |
8773 | |
8774 | priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); | |
8775 | if (IS_ERR(priv->axi_clk)) { | |
8776 | err = PTR_ERR(priv->axi_clk); | |
8777 | if (err == -EPROBE_DEFER) | |
8778 | goto err_gop_clk; | |
8779 | priv->axi_clk = NULL; | |
8780 | } else { | |
8781 | err = clk_prepare_enable(priv->axi_clk); | |
8782 | if (err < 0) | |
8783 | goto err_gop_clk; | |
8784 | } | |
fceb55d4 | 8785 | |
a75edc7c MW |
8786 | /* Get system's tclk rate */ |
8787 | priv->tclk = clk_get_rate(priv->pp_clk); | |
8788 | } else if (device_property_read_u32(&pdev->dev, "clock-frequency", | |
8789 | &priv->tclk)) { | |
8790 | dev_err(&pdev->dev, "missing clock-frequency value\n"); | |
8791 | return -EINVAL; | |
8792 | } | |
3f518509 | 8793 | |
2067e0a1 TP |
8794 | if (priv->hw_version == MVPP22) { |
8795 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); | |
8796 | if (err) | |
8797 | goto err_mg_clk; | |
8798 | /* Sadly, the BM pools all share the same register to | |
8799 | * store the high 32 bits of their address. So they | |
8800 | * must all have the same high 32 bits, which forces | |
8801 | * us to restrict coherent memory to DMA_BIT_MASK(32). | |
8802 | */ | |
8803 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
8804 | if (err) | |
8805 | goto err_mg_clk; | |
8806 | } | |
8807 | ||
3f518509 MW |
8808 | /* Initialize network controller */ |
8809 | err = mvpp2_init(pdev, priv); | |
8810 | if (err < 0) { | |
8811 | dev_err(&pdev->dev, "failed to initialize controller\n"); | |
fceb55d4 | 8812 | goto err_mg_clk; |
3f518509 MW |
8813 | } |
8814 | ||
3f518509 | 8815 | /* Initialize ports */ |
24812221 MW |
8816 | fwnode_for_each_available_child_node(fwnode, port_fwnode) { |
8817 | err = mvpp2_port_probe(pdev, port_fwnode, priv); | |
3f518509 | 8818 | if (err < 0) |
26146b0e | 8819 | goto err_port_probe; |
bf147153 MW |
8820 | } |
8821 | ||
8822 | if (priv->port_count == 0) { | |
8823 | dev_err(&pdev->dev, "no ports enabled\n"); | |
8824 | err = -ENODEV; | |
8825 | goto err_mg_clk; | |
3f518509 MW |
8826 | } |
8827 | ||
118d6298 MR |
8828 | /* Statistics must be gathered regularly because some of them (like |
8829 | * packets counters) are 32-bit registers and could overflow quite | |
8830 | * quickly. For instance, a 10Gb link used at full bandwidth with the | |
8831 | * smallest packets (64B) will overflow a 32-bit counter in less than | |
8832 | * 30 seconds. Then, use a workqueue to fill 64-bit counters. | |
8833 | */ | |
118d6298 MR |
8834 | snprintf(priv->queue_name, sizeof(priv->queue_name), |
8835 | "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), | |
8836 | priv->port_count > 1 ? "+" : ""); | |
8837 | priv->stats_queue = create_singlethread_workqueue(priv->queue_name); | |
8838 | if (!priv->stats_queue) { | |
8839 | err = -ENOMEM; | |
26146b0e | 8840 | goto err_port_probe; |
118d6298 MR |
8841 | } |
8842 | ||
3f518509 MW |
8843 | platform_set_drvdata(pdev, priv); |
8844 | return 0; | |
8845 | ||
26146b0e AT |
8846 | err_port_probe: |
8847 | i = 0; | |
24812221 | 8848 | fwnode_for_each_available_child_node(fwnode, port_fwnode) { |
26146b0e AT |
8849 | if (priv->port_list[i]) |
8850 | mvpp2_port_remove(priv->port_list[i]); | |
8851 | i++; | |
8852 | } | |
fceb55d4 | 8853 | err_mg_clk: |
4792ea04 | 8854 | clk_disable_unprepare(priv->axi_clk); |
fceb55d4 TP |
8855 | if (priv->hw_version == MVPP22) |
8856 | clk_disable_unprepare(priv->mg_clk); | |
3f518509 MW |
8857 | err_gop_clk: |
8858 | clk_disable_unprepare(priv->gop_clk); | |
8859 | err_pp_clk: | |
8860 | clk_disable_unprepare(priv->pp_clk); | |
8861 | return err; | |
8862 | } | |
8863 | ||
8864 | static int mvpp2_remove(struct platform_device *pdev) | |
8865 | { | |
8866 | struct mvpp2 *priv = platform_get_drvdata(pdev); | |
24812221 MW |
8867 | struct fwnode_handle *fwnode = pdev->dev.fwnode; |
8868 | struct fwnode_handle *port_fwnode; | |
3f518509 MW |
8869 | int i = 0; |
8870 | ||
e5c500eb | 8871 | flush_workqueue(priv->stats_queue); |
118d6298 | 8872 | destroy_workqueue(priv->stats_queue); |
118d6298 | 8873 | |
24812221 | 8874 | fwnode_for_each_available_child_node(fwnode, port_fwnode) { |
e5c500eb MR |
8875 | if (priv->port_list[i]) { |
8876 | mutex_destroy(&priv->port_list[i]->gather_stats_lock); | |
3f518509 | 8877 | mvpp2_port_remove(priv->port_list[i]); |
e5c500eb | 8878 | } |
3f518509 MW |
8879 | i++; |
8880 | } | |
8881 | ||
8882 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
8883 | struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; | |
8884 | ||
8885 | mvpp2_bm_pool_destroy(pdev, priv, bm_pool); | |
8886 | } | |
8887 | ||
8888 | for_each_present_cpu(i) { | |
8889 | struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; | |
8890 | ||
8891 | dma_free_coherent(&pdev->dev, | |
8892 | MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, | |
8893 | aggr_txq->descs, | |
20396136 | 8894 | aggr_txq->descs_dma); |
3f518509 MW |
8895 | } |
8896 | ||
a75edc7c MW |
8897 | if (is_acpi_node(port_fwnode)) |
8898 | return 0; | |
8899 | ||
4792ea04 | 8900 | clk_disable_unprepare(priv->axi_clk); |
fceb55d4 | 8901 | clk_disable_unprepare(priv->mg_clk); |
3f518509 MW |
8902 | clk_disable_unprepare(priv->pp_clk); |
8903 | clk_disable_unprepare(priv->gop_clk); | |
8904 | ||
8905 | return 0; | |
8906 | } | |
8907 | ||
8908 | static const struct of_device_id mvpp2_match[] = { | |
faca9247 TP |
8909 | { |
8910 | .compatible = "marvell,armada-375-pp2", | |
8911 | .data = (void *)MVPP21, | |
8912 | }, | |
fc5e1550 TP |
8913 | { |
8914 | .compatible = "marvell,armada-7k-pp22", | |
8915 | .data = (void *)MVPP22, | |
8916 | }, | |
3f518509 MW |
8917 | { } |
8918 | }; | |
8919 | MODULE_DEVICE_TABLE(of, mvpp2_match); | |
8920 | ||
a75edc7c MW |
8921 | static const struct acpi_device_id mvpp2_acpi_match[] = { |
8922 | { "MRVL0110", MVPP22 }, | |
8923 | { }, | |
8924 | }; | |
8925 | MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); | |
8926 | ||
3f518509 MW |
8927 | static struct platform_driver mvpp2_driver = { |
8928 | .probe = mvpp2_probe, | |
8929 | .remove = mvpp2_remove, | |
8930 | .driver = { | |
8931 | .name = MVPP2_DRIVER_NAME, | |
8932 | .of_match_table = mvpp2_match, | |
a75edc7c | 8933 | .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), |
3f518509 MW |
8934 | }, |
8935 | }; | |
8936 | ||
8937 | module_platform_driver(mvpp2_driver); | |
8938 | ||
8939 | MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); | |
8940 | MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); | |
c634099d | 8941 | MODULE_LICENSE("GPL v2"); |