projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mvpp2: remove misleading comment
[linux-2.6-block.git] / drivers / net / ethernet / marvell / mvpp2 / mvpp2_main.c
CommitLineData
f1e37e31 1// SPDX-License-Identifier: GPL-2.0
3f518509
MW		 2/*
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Marcin Wojtas <mw@semihalf.com>
3f518509
MW		 8 */
9
a75edc7c 10#include <linux/acpi.h>
3f518509
MW		 11#include <linux/kernel.h>
12#include <linux/netdevice.h>
13#include <linux/etherdevice.h>
14#include <linux/platform_device.h>
15#include <linux/skbuff.h>
16#include <linux/inetdevice.h>
17#include <linux/mbus.h>
18#include <linux/module.h>
f84bf386 19#include <linux/mfd/syscon.h>
3f518509
MW		 20#include <linux/interrupt.h>
21#include <linux/cpumask.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_mdio.h>
25#include <linux/of_net.h>
26#include <linux/of_address.h>
faca9247 27#include <linux/of_device.h>
3f518509 28#include <linux/phy.h>
4bb04326 29#include <linux/phylink.h>
542897d9 30#include <linux/phy/phy.h>
3f518509 31#include <linux/clk.h>
edc660fa
MW		 32#include <linux/hrtimer.h>
33#include <linux/ktime.h>
f84bf386 34#include <linux/regmap.h>
3f518509
MW		 35#include <uapi/linux/ppp_defs.h>
36#include <net/ip.h>
37#include <net/ipv6.h>
186cd4d4 38#include <net/tso.h>
3f518509 39
db9d7d36
MC		 40#include "mvpp2.h"
41#include "mvpp2_prs.h"
42#include "mvpp2_cls.h"
a786841d 43
01d04936
SC		 44enum mvpp2_bm_pool_log_num {
45 MVPP2_BM_SHORT,
46 MVPP2_BM_LONG,
576193f2 47 MVPP2_BM_JUMBO,
01d04936 48 MVPP2_BM_POOLS_NUM
3f518509
MW		 49};
50
db9d7d36
MC		 51static struct {
52 int pkt_size;
53 int buf_num;
54} mvpp2_pools[MVPP2_BM_POOLS_NUM];
3f518509 55
db9d7d36
MC		 56/* The prototype is added here to be used in start_dev when using ACPI. This
57 * will be removed once phylink is used for all modes (dt+ACPI).
58 */
44cc27e4 59static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
db9d7d36 60 const struct phylink_link_state *state);
44cc27e4 61static void mvpp2_mac_link_up(struct phylink_config *config, unsigned int mode,
41948ccb 62 phy_interface_t interface, struct phy_device *phy);
10fea26c 63
db9d7d36
MC		 64/* Queue modes */
65#define MVPP2_QDIST_SINGLE_MODE 0
66#define MVPP2_QDIST_MULTI_MODE 1
3f518509 67
3f6aaf72 68static int queue_mode = MVPP2_QDIST_MULTI_MODE;
3f518509 69
db9d7d36
MC		 70module_param(queue_mode, int, 0444);
71MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
3f518509 72
db9d7d36 73/* Utility/helper methods */
3f518509 74
db9d7d36
MC		 75void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
76{
77 writel(data, priv->swth_base[0] + offset);
3f518509
MW		 78}
79
db9d7d36 80u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
3f518509 81{
db9d7d36 82 return readl(priv->swth_base[0] + offset);
3f518509
MW		 83}
84
16274427 85static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
3f518509 86{
db9d7d36 87 return readl_relaxed(priv->swth_base[0] + offset);
3f518509 88}
543ec376 89
e531f767 90static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
543ec376 91{
e531f767 92 return cpu % priv->nthreads;
543ec376
AT		 93}
94
db9d7d36
MC		 95/* These accessors should be used to access:
96 *
543ec376 97 * - per-thread registers, where each thread has its own copy of the
db9d7d36
MC		 98 * register.
99 *
100 * MVPP2_BM_VIRT_ALLOC_REG
101 * MVPP2_BM_ADDR_HIGH_ALLOC
102 * MVPP22_BM_ADDR_HIGH_RLS_REG
103 * MVPP2_BM_VIRT_RLS_REG
104 * MVPP2_ISR_RX_TX_CAUSE_REG
105 * MVPP2_ISR_RX_TX_MASK_REG
106 * MVPP2_TXQ_NUM_REG
107 * MVPP2_AGGR_TXQ_UPDATE_REG
108 * MVPP2_TXQ_RSVD_REQ_REG
109 * MVPP2_TXQ_RSVD_RSLT_REG
110 * MVPP2_TXQ_SENT_REG
111 * MVPP2_RXQ_NUM_REG
112 *
543ec376
AT		 113 * - global registers that must be accessed through a specific thread
114 * window, because they are related to an access to a per-thread
db9d7d36
MC		 115 * register
116 *
117 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG)
118 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG)
119 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG)
120 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG)
121 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG)
122 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG)
123 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
124 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG)
125 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG)
126 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG)
127 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
128 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
129 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
130 */
1068549c 131static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
db9d7d36
MC		 132 u32 offset, u32 data)
133{
543ec376 134 writel(data, priv->swth_base[thread] + offset);
3f518509
MW		 135}
136
1068549c 137static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
db9d7d36 138 u32 offset)
3f518509 139{
543ec376 140 return readl(priv->swth_base[thread] + offset);
db9d7d36 141}
3f518509 142
1068549c 143static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
db9d7d36
MC		 144 u32 offset, u32 data)
145{
543ec376 146 writel_relaxed(data, priv->swth_base[thread] + offset);
db9d7d36 147}
0c6d9b44 148
1068549c 149static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
db9d7d36
MC		 150 u32 offset)
151{
543ec376 152 return readl_relaxed(priv->swth_base[thread] + offset);
db9d7d36 153}
3f518509 154
db9d7d36
MC		 155static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
156 struct mvpp2_tx_desc *tx_desc)
157{
158 if (port->priv->hw_version == MVPP21)
7b9c7d7d 159 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
db9d7d36 160 else
7b9c7d7d
MC		 161 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
162 MVPP2_DESC_DMA_MASK;
db9d7d36 163}
3f518509 164
db9d7d36
MC		 165static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
166 struct mvpp2_tx_desc *tx_desc,
167 dma_addr_t dma_addr)
168{
169 dma_addr_t addr, offset;
3f518509 170
db9d7d36
MC		 171 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
172 offset = dma_addr & MVPP2_TX_DESC_ALIGN;
3f518509 173
db9d7d36 174 if (port->priv->hw_version == MVPP21) {
7b9c7d7d 175 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
db9d7d36 176 tx_desc->pp21.packet_offset = offset;
0c6d9b44 177 } else {
7b9c7d7d 178 __le64 val = cpu_to_le64(addr);
3f518509 179
7b9c7d7d 180 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
db9d7d36
MC		 181 tx_desc->pp22.buf_dma_addr_ptp |= val;
182 tx_desc->pp22.packet_offset = offset;
183 }
3f518509
MW		 184}
185
db9d7d36
MC		 186static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
187 struct mvpp2_tx_desc *tx_desc)
3f518509 188{
db9d7d36 189 if (port->priv->hw_version == MVPP21)
7b9c7d7d 190 return le16_to_cpu(tx_desc->pp21.data_size);
db9d7d36 191 else
7b9c7d7d 192 return le16_to_cpu(tx_desc->pp22.data_size);
3f518509
MW		 193}
194
db9d7d36
MC		 195static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
196 struct mvpp2_tx_desc *tx_desc,
197 size_t size)
3f518509 198{
db9d7d36 199 if (port->priv->hw_version == MVPP21)
7b9c7d7d 200 tx_desc->pp21.data_size = cpu_to_le16(size);
db9d7d36 201 else
7b9c7d7d 202 tx_desc->pp22.data_size = cpu_to_le16(size);
3f518509
MW		 203}
204
db9d7d36
MC		 205static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
206 struct mvpp2_tx_desc *tx_desc,
207 unsigned int txq)
3f518509 208{
db9d7d36
MC		 209 if (port->priv->hw_version == MVPP21)
210 tx_desc->pp21.phys_txq = txq;
211 else
212 tx_desc->pp22.phys_txq = txq;
3f518509
MW		 213}
214
db9d7d36
MC		 215static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
216 struct mvpp2_tx_desc *tx_desc,
217 unsigned int command)
3f518509 218{
db9d7d36 219 if (port->priv->hw_version == MVPP21)
7b9c7d7d 220 tx_desc->pp21.command = cpu_to_le32(command);
db9d7d36 221 else
7b9c7d7d 222 tx_desc->pp22.command = cpu_to_le32(command);
db9d7d36 223}
3f518509 224
db9d7d36
MC		 225static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
226 struct mvpp2_tx_desc *tx_desc)
227{
228 if (port->priv->hw_version == MVPP21)
229 return tx_desc->pp21.packet_offset;
230 else
231 return tx_desc->pp22.packet_offset;
232}
3f518509 233
db9d7d36
MC		 234static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
235 struct mvpp2_rx_desc *rx_desc)
236{
237 if (port->priv->hw_version == MVPP21)
7b9c7d7d 238 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
db9d7d36 239 else
7b9c7d7d
MC		 240 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
241 MVPP2_DESC_DMA_MASK;
db9d7d36 242}
3f518509 243
db9d7d36
MC		 244static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
245 struct mvpp2_rx_desc *rx_desc)
246{
247 if (port->priv->hw_version == MVPP21)
7b9c7d7d 248 return le32_to_cpu(rx_desc->pp21.buf_cookie);
db9d7d36 249 else
7b9c7d7d
MC		 250 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
251 MVPP2_DESC_DMA_MASK;
db9d7d36 252}
3f518509 253
db9d7d36
MC		 254static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
255 struct mvpp2_rx_desc *rx_desc)
256{
257 if (port->priv->hw_version == MVPP21)
7b9c7d7d 258 return le16_to_cpu(rx_desc->pp21.data_size);
db9d7d36 259 else
7b9c7d7d 260 return le16_to_cpu(rx_desc->pp22.data_size);
db9d7d36 261}
3f518509 262
db9d7d36
MC		 263static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
264 struct mvpp2_rx_desc *rx_desc)
265{
266 if (port->priv->hw_version == MVPP21)
7b9c7d7d 267 return le32_to_cpu(rx_desc->pp21.status);
db9d7d36 268 else
7b9c7d7d 269 return le32_to_cpu(rx_desc->pp22.status);
3f518509
MW		 270}
271
db9d7d36 272static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
3f518509 273{
db9d7d36
MC		 274 txq_pcpu->txq_get_index++;
275 if (txq_pcpu->txq_get_index == txq_pcpu->size)
276 txq_pcpu->txq_get_index = 0;
277}
3f518509 278
db9d7d36
MC		 279static void mvpp2_txq_inc_put(struct mvpp2_port *port,
280 struct mvpp2_txq_pcpu *txq_pcpu,
281 struct sk_buff *skb,
282 struct mvpp2_tx_desc *tx_desc)
283{
284 struct mvpp2_txq_pcpu_buf *tx_buf =
285 txq_pcpu->buffs + txq_pcpu->txq_put_index;
286 tx_buf->skb = skb;
287 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
288 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
289 mvpp2_txdesc_offset_get(port, tx_desc);
290 txq_pcpu->txq_put_index++;
291 if (txq_pcpu->txq_put_index == txq_pcpu->size)
292 txq_pcpu->txq_put_index = 0;
293}
3f518509 294
7d04b0b1
MC		 295/* Get number of maximum RXQ */
296static int mvpp2_get_nrxqs(struct mvpp2 *priv)
297{
298 unsigned int nrxqs;
299
300 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
301 return 1;
302
303 /* According to the PPv2.2 datasheet and our experiments on
304 * PPv2.1, RX queues have an allocation granularity of 4 (when
305 * more than a single one on PPv2.2).
306 * Round up to nearest multiple of 4.
307 */
308 nrxqs = (num_possible_cpus() + 3) & ~0x3;
309 if (nrxqs > MVPP2_PORT_MAX_RXQ)
310 nrxqs = MVPP2_PORT_MAX_RXQ;
311
312 return nrxqs;
313}
314
db9d7d36
MC		 315/* Get number of physical egress port */
316static inline int mvpp2_egress_port(struct mvpp2_port *port)
317{
318 return MVPP2_MAX_TCONT + port->id;
319}
3f518509 320
db9d7d36
MC		 321/* Get number of physical TXQ */
322static inline int mvpp2_txq_phys(int port, int txq)
323{
324 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
3f518509
MW		 325}
326
0e037281
TP		 327static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool)
328{
329 if (likely(pool->frag_size <= PAGE_SIZE))
330 return netdev_alloc_frag(pool->frag_size);
331 else
332 return kmalloc(pool->frag_size, GFP_ATOMIC);
333}
334
335static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data)
336{
337 if (likely(pool->frag_size <= PAGE_SIZE))
338 skb_free_frag(data);
339 else
340 kfree(data);
341}
342
3f518509
MW		 343/* Buffer Manager configuration routines */
344
345/* Create pool */
13616361 346static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
3f518509
MW		 347 struct mvpp2_bm_pool *bm_pool, int size)
348{
3f518509
MW		 349 u32 val;
350
d01524d8
TP		 351 /* Number of buffer pointers must be a multiple of 16, as per
352 * hardware constraints
353 */
354 if (!IS_ALIGNED(size, 16))
355 return -EINVAL;
356
357 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
358 * bytes per buffer pointer
359 */
360 if (priv->hw_version == MVPP21)
361 bm_pool->size_bytes = 2 * sizeof(u32) * size;
362 else
363 bm_pool->size_bytes = 2 * sizeof(u64) * size;
364
13616361 365 bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes,
20396136 366 &bm_pool->dma_addr,
3f518509
MW		 367 GFP_KERNEL);
368 if (!bm_pool->virt_addr)
369 return -ENOMEM;
370
d3158807
TP		 371 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
372 MVPP2_BM_POOL_PTR_ALIGN)) {
13616361 373 dma_free_coherent(dev, bm_pool->size_bytes,
d01524d8 374 bm_pool->virt_addr, bm_pool->dma_addr);
13616361 375 dev_err(dev, "BM pool %d is not %d bytes aligned\n",
3f518509
MW		 376 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
377 return -ENOMEM;
378 }
379
380 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
d01524d8 381 lower_32_bits(bm_pool->dma_addr));
3f518509
MW		 382 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
383
384 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
385 val |= MVPP2_BM_START_MASK;
386 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
387
3f518509
MW		 388 bm_pool->size = size;
389 bm_pool->pkt_size = 0;
390 bm_pool->buf_num = 0;
3f518509
MW		 391
392 return 0;
393}
394
395/* Set pool buffer size */
396static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
397 struct mvpp2_bm_pool *bm_pool,
398 int buf_size)
399{
400 u32 val;
401
402 bm_pool->buf_size = buf_size;
403
404 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
405 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
406}
407
d01524d8
TP		 408static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
409 struct mvpp2_bm_pool *bm_pool,
410 dma_addr_t *dma_addr,
411 phys_addr_t *phys_addr)
412{
e531f767 413 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
a786841d 414
1068549c 415 *dma_addr = mvpp2_thread_read(priv, thread,
a786841d 416 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
1068549c 417 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
d01524d8
TP		 418
419 if (priv->hw_version == MVPP22) {
420 u32 val;
421 u32 dma_addr_highbits, phys_addr_highbits;
422
1068549c 423 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
d01524d8
TP		 424 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
425 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
426 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
427
428 if (sizeof(dma_addr_t) == 8)
429 *dma_addr |= (u64)dma_addr_highbits << 32;
430
431 if (sizeof(phys_addr_t) == 8)
432 *phys_addr |= (u64)phys_addr_highbits << 32;
433 }
a704bb5c
TP		 434
435 put_cpu();
d01524d8
TP		 436}
437
7861f12b 438/* Free all buffers from the pool */
4229d502 439static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
effbf5f5 440 struct mvpp2_bm_pool *bm_pool, int buf_num)
3f518509
MW		 441{
442 int i;
443
effbf5f5
SC		 444 if (buf_num > bm_pool->buf_num) {
445 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
446 bm_pool->id, buf_num);
447 buf_num = bm_pool->buf_num;
448 }
449
450 for (i = 0; i < buf_num; i++) {
20396136 451 dma_addr_t buf_dma_addr;
4e4a105f
TP		 452 phys_addr_t buf_phys_addr;
453 void *data;
3f518509 454
d01524d8
TP		 455 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
456 &buf_dma_addr, &buf_phys_addr);
4229d502 457
20396136 458 dma_unmap_single(dev, buf_dma_addr,
4229d502
MW		 459 bm_pool->buf_size, DMA_FROM_DEVICE);
460
4e4a105f
TP		 461 data = (void *)phys_to_virt(buf_phys_addr);
462 if (!data)
3f518509 463 break;
0e037281 464
4e4a105f 465 mvpp2_frag_free(bm_pool, data);
3f518509
MW		 466 }
467
468 /* Update BM driver with number of buffers removed from pool */
469 bm_pool->buf_num -= i;
3f518509
MW		 470}
471
effbf5f5 472/* Check number of buffers in BM pool */
6e61e10a 473static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
effbf5f5
SC		 474{
475 int buf_num = 0;
476
477 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
478 MVPP22_BM_POOL_PTRS_NUM_MASK;
479 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
480 MVPP2_BM_BPPI_PTR_NUM_MASK;
481
482 /* HW has one buffer ready which is not reflected in the counters */
483 if (buf_num)
484 buf_num += 1;
485
486 return buf_num;
487}
488
3f518509 489/* Cleanup pool */
13616361 490static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv,
3f518509
MW		 491 struct mvpp2_bm_pool *bm_pool)
492{
effbf5f5 493 int buf_num;
3f518509
MW		 494 u32 val;
495
effbf5f5 496 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
13616361 497 mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num);
effbf5f5
SC		 498
499 /* Check buffer counters after free */
500 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
501 if (buf_num) {
502 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
503 bm_pool->id, bm_pool->buf_num);
3f518509
MW		 504 return 0;
505 }
506
507 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
508 val |= MVPP2_BM_STOP_MASK;
509 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
510
13616361 511 dma_free_coherent(dev, bm_pool->size_bytes,
3f518509 512 bm_pool->virt_addr,
20396136 513 bm_pool->dma_addr);
3f518509
MW		 514 return 0;
515}
516
13616361 517static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
3f518509 518{
7d04b0b1 519 int i, err, size, poolnum = MVPP2_BM_POOLS_NUM;
3f518509
MW		 520 struct mvpp2_bm_pool *bm_pool;
521
7d04b0b1
MC		 522 if (priv->percpu_pools)
523 poolnum = mvpp2_get_nrxqs(priv) * 2;
524
3f518509
MW		 525 /* Create all pools with maximum size */
526 size = MVPP2_BM_POOL_SIZE_MAX;
7d04b0b1 527 for (i = 0; i < poolnum; i++) {
3f518509
MW		 528 bm_pool = &priv->bm_pools[i];
529 bm_pool->id = i;
13616361 530 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
3f518509
MW		 531 if (err)
532 goto err_unroll_pools;
533 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
534 }
535 return 0;
536
537err_unroll_pools:
13616361 538 dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
3f518509 539 for (i = i - 1; i >= 0; i--)
13616361 540 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
3f518509
MW		 541 return err;
542}
543
13616361 544static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
3f518509 545{
7d04b0b1
MC		 546 int i, err, poolnum = MVPP2_BM_POOLS_NUM;
547
548 if (priv->percpu_pools)
549 poolnum = mvpp2_get_nrxqs(priv) * 2;
3f518509 550
7d04b0b1
MC		 551 dev_info(dev, "using %d %s buffers\n", poolnum,
552 priv->percpu_pools ? "per-cpu" : "shared");
553
554 for (i = 0; i < poolnum; i++) {
3f518509
MW		 555 /* Mask BM all interrupts */
556 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
557 /* Clear BM cause register */
558 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
559 }
560
561 /* Allocate and initialize BM pools */
7d04b0b1 562 priv->bm_pools = devm_kcalloc(dev, poolnum,
81f915eb 563 sizeof(*priv->bm_pools), GFP_KERNEL);
3f518509
MW		 564 if (!priv->bm_pools)
565 return -ENOMEM;
566
13616361 567 err = mvpp2_bm_pools_init(dev, priv);
3f518509
MW		 568 if (err < 0)
569 return err;
570 return 0;
571}
572
01d04936
SC		 573static void mvpp2_setup_bm_pool(void)
574{
575 /* Short pool */
576 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM;
577 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
578
579 /* Long pool */
580 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM;
581 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
576193f2
SC		 582
583 /* Jumbo pool */
584 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM;
585 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
01d04936
SC		 586}
587
3f518509
MW		 588/* Attach long pool to rxq */
589static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
590 int lrxq, int long_pool)
591{
5eac892a 592 u32 val, mask;
3f518509
MW		 593 int prxq;
594
595 /* Get queue physical ID */
596 prxq = port->rxqs[lrxq]->id;
597
5eac892a
TP		 598 if (port->priv->hw_version == MVPP21)
599 mask = MVPP21_RXQ_POOL_LONG_MASK;
600 else
601 mask = MVPP22_RXQ_POOL_LONG_MASK;
3f518509 602
5eac892a
TP		 603 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
604 val &= ~mask;
605 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
3f518509
MW		 606 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
607}
608
609/* Attach short pool to rxq */
610static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
611 int lrxq, int short_pool)
612{
5eac892a 613 u32 val, mask;
3f518509
MW		 614 int prxq;
615
616 /* Get queue physical ID */
617 prxq = port->rxqs[lrxq]->id;
618
5eac892a
TP		 619 if (port->priv->hw_version == MVPP21)
620 mask = MVPP21_RXQ_POOL_SHORT_MASK;
621 else
622 mask = MVPP22_RXQ_POOL_SHORT_MASK;
3f518509 623
5eac892a
TP		 624 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
625 val &= ~mask;
626 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
3f518509
MW		 627 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
628}
629
0e037281
TP		 630static void *mvpp2_buf_alloc(struct mvpp2_port *port,
631 struct mvpp2_bm_pool *bm_pool,
20396136 632 dma_addr_t *buf_dma_addr,
4e4a105f 633 phys_addr_t *buf_phys_addr,
0e037281 634 gfp_t gfp_mask)
3f518509 635{
20396136 636 dma_addr_t dma_addr;
0e037281 637 void *data;
3f518509 638
0e037281
TP		 639 data = mvpp2_frag_alloc(bm_pool);
640 if (!data)
3f518509
MW		 641 return NULL;
642
20396136
TP		 643 dma_addr = dma_map_single(port->dev->dev.parent, data,
644 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
645 DMA_FROM_DEVICE);
646 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
0e037281 647 mvpp2_frag_free(bm_pool, data);
3f518509
MW		 648 return NULL;
649 }
20396136 650 *buf_dma_addr = dma_addr;
4e4a105f 651 *buf_phys_addr = virt_to_phys(data);
3f518509 652
0e037281 653 return data;
3f518509
MW		 654}
655
3f518509
MW		 656/* Release buffer to BM */
657static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
20396136 658 dma_addr_t buf_dma_addr,
4e4a105f 659 phys_addr_t buf_phys_addr)
3f518509 660{
e531f767
AT		 661 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
662 unsigned long flags = 0;
663
664 if (test_bit(thread, &port->priv->lock_map))
665 spin_lock_irqsave(&port->bm_lock[thread], flags);
a786841d 666
d01524d8
TP		 667 if (port->priv->hw_version == MVPP22) {
668 u32 val = 0;
669
670 if (sizeof(dma_addr_t) == 8)
671 val |= upper_32_bits(buf_dma_addr) &
672 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
673
674 if (sizeof(phys_addr_t) == 8)
675 val |= (upper_32_bits(buf_phys_addr)
676 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
677 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
678
1068549c 679 mvpp2_thread_write_relaxed(port->priv, thread,
cdcfeb0f 680 MVPP22_BM_ADDR_HIGH_RLS_REG, val);
d01524d8
TP		 681 }
682
4e4a105f
TP		 683 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
684 * returned in the "cookie" field of the RX
685 * descriptor. Instead of storing the virtual address, we
686 * store the physical address
687 */
1068549c 688 mvpp2_thread_write_relaxed(port->priv, thread,
cdcfeb0f 689 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
1068549c 690 mvpp2_thread_write_relaxed(port->priv, thread,
cdcfeb0f 691 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
a704bb5c 692
e531f767
AT		 693 if (test_bit(thread, &port->priv->lock_map))
694 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
695
a704bb5c 696 put_cpu();
3f518509
MW		 697}
698
3f518509
MW		 699/* Allocate buffers for the pool */
700static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
701 struct mvpp2_bm_pool *bm_pool, int buf_num)
702{
3f518509 703 int i, buf_size, total_size;
20396136 704 dma_addr_t dma_addr;
4e4a105f 705 phys_addr_t phys_addr;
0e037281 706 void *buf;
3f518509 707
7d04b0b1
MC		 708 if (port->priv->percpu_pools &&
709 bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
710 netdev_err(port->dev,
711 "attempted to use jumbo frames with per-cpu pools");
712 return 0;
713 }
714
3f518509
MW		 715 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
716 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
717
718 if (buf_num < 0 ||
719 (buf_num + bm_pool->buf_num > bm_pool->size)) {
720 netdev_err(port->dev,
721 "cannot allocate %d buffers for pool %d\n",
722 buf_num, bm_pool->id);
723 return 0;
724 }
725
3f518509 726 for (i = 0; i < buf_num; i++) {
4e4a105f
TP		 727 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr,
728 &phys_addr, GFP_KERNEL);
0e037281 729 if (!buf)
3f518509
MW		 730 break;
731
20396136 732 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
4e4a105f 733 phys_addr);
3f518509
MW		 734 }
735
736 /* Update BM driver with number of buffers added to pool */
737 bm_pool->buf_num += i;
3f518509
MW		 738
739 netdev_dbg(port->dev,
01d04936 740 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
3f518509
MW		 741 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
742
743 netdev_dbg(port->dev,
01d04936 744 "pool %d: %d of %d buffers added\n",
3f518509
MW		 745 bm_pool->id, i, buf_num);
746 return i;
747}
748
749/* Notify the driver that BM pool is being used as specific type and return the
750 * pool pointer on success
751 */
752static struct mvpp2_bm_pool *
01d04936 753mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
3f518509 754{
3f518509
MW		 755 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
756 int num;
757
7d04b0b1
MC		 758 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) ||
759 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) {
760 netdev_err(port->dev, "Invalid pool %d\n", pool);
761 return NULL;
762 }
763
764 /* Allocate buffers in case BM pool is used as long pool, but packet
765 * size doesn't match MTU or BM pool hasn't being used yet
766 */
767 if (new_pool->pkt_size == 0) {
768 int pkts_num;
769
770 /* Set default buffer number or free all the buffers in case
771 * the pool is not empty
772 */
773 pkts_num = new_pool->buf_num;
774 if (pkts_num == 0) {
775 if (port->priv->percpu_pools) {
776 if (pool < port->nrxqs)
777 pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num;
778 else
779 pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num;
780 } else {
781 pkts_num = mvpp2_pools[pool].buf_num;
782 }
783 } else {
784 mvpp2_bm_bufs_free(port->dev->dev.parent,
785 port->priv, new_pool, pkts_num);
786 }
787
788 new_pool->pkt_size = pkt_size;
789 new_pool->frag_size =
790 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
791 MVPP2_SKB_SHINFO_SIZE;
792
793 /* Allocate buffers for this pool */
794 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
795 if (num != pkts_num) {
796 WARN(1, "pool %d: %d of %d allocated\n",
797 new_pool->id, num, pkts_num);
798 return NULL;
799 }
800 }
801
802 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
803 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
804
805 return new_pool;
806}
807
808static struct mvpp2_bm_pool *
809mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type,
810 unsigned int pool, int pkt_size)
811{
812 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
813 int num;
814
815 if (pool > port->nrxqs * 2) {
01d04936 816 netdev_err(port->dev, "Invalid pool %d\n", pool);
3f518509
MW		 817 return NULL;
818 }
819
3f518509
MW		 820 /* Allocate buffers in case BM pool is used as long pool, but packet
821 * size doesn't match MTU or BM pool hasn't being used yet
822 */
01d04936 823 if (new_pool->pkt_size == 0) {
3f518509
MW		 824 int pkts_num;
825
826 /* Set default buffer number or free all the buffers in case
827 * the pool is not empty
828 */
829 pkts_num = new_pool->buf_num;
830 if (pkts_num == 0)
7d04b0b1 831 pkts_num = mvpp2_pools[type].buf_num;
3f518509 832 else
4229d502 833 mvpp2_bm_bufs_free(port->dev->dev.parent,
effbf5f5 834 port->priv, new_pool, pkts_num);
3f518509
MW		 835
836 new_pool->pkt_size = pkt_size;
0e037281
TP		 837 new_pool->frag_size =
838 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
839 MVPP2_SKB_SHINFO_SIZE;
3f518509
MW		 840
841 /* Allocate buffers for this pool */
842 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
843 if (num != pkts_num) {
844 WARN(1, "pool %d: %d of %d allocated\n",
845 new_pool->id, num, pkts_num);
3f518509
MW		 846 return NULL;
847 }
848 }
849
850 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
851 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
852
3f518509
MW		 853 return new_pool;
854}
855
7d04b0b1
MC		 856/* Initialize pools for swf, shared buffers variant */
857static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port)
3f518509 858{
576193f2 859 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
7d04b0b1 860 int rxq;
576193f2
SC		 861
862 /* If port pkt_size is higher than 1518B:
863 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
864 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
865 */
866 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
867 long_log_pool = MVPP2_BM_JUMBO;
868 short_log_pool = MVPP2_BM_LONG;
869 } else {
870 long_log_pool = MVPP2_BM_LONG;
871 short_log_pool = MVPP2_BM_SHORT;
872 }
3f518509
MW		 873
874 if (!port->pool_long) {
875 port->pool_long =
576193f2
SC		 876 mvpp2_bm_pool_use(port, long_log_pool,
877 mvpp2_pools[long_log_pool].pkt_size);
3f518509
MW		 878 if (!port->pool_long)
879 return -ENOMEM;
880
576193f2 881 port->pool_long->port_map |= BIT(port->id);
3f518509 882
09f83975 883 for (rxq = 0; rxq < port->nrxqs; rxq++)
3f518509
MW		 884 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
885 }
886
887 if (!port->pool_short) {
888 port->pool_short =
576193f2 889 mvpp2_bm_pool_use(port, short_log_pool,
e2e03164 890 mvpp2_pools[short_log_pool].pkt_size);
3f518509
MW		 891 if (!port->pool_short)
892 return -ENOMEM;
893
576193f2 894 port->pool_short->port_map |= BIT(port->id);
3f518509 895
09f83975 896 for (rxq = 0; rxq < port->nrxqs; rxq++)
3f518509
MW		 897 mvpp2_rxq_short_pool_set(port, rxq,
898 port->pool_short->id);
899 }
900
901 return 0;
902}
903
7d04b0b1
MC		 904/* Initialize pools for swf, percpu buffers variant */
905static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port)
906{
907 struct mvpp2_bm_pool *p;
908 int i;
909
910 for (i = 0; i < port->nrxqs; i++) {
911 p = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i,
912 mvpp2_pools[MVPP2_BM_SHORT].pkt_size);
913 if (!p)
914 return -ENOMEM;
915
916 port->priv->bm_pools[i].port_map |= BIT(port->id);
917 mvpp2_rxq_short_pool_set(port, i, port->priv->bm_pools[i].id);
918 }
919
920 for (i = 0; i < port->nrxqs; i++) {
921 p = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs,
922 mvpp2_pools[MVPP2_BM_LONG].pkt_size);
923 if (!p)
924 return -ENOMEM;
925
926 port->priv->bm_pools[i + port->nrxqs].port_map |= BIT(port->id);
927 mvpp2_rxq_long_pool_set(port, i,
928 port->priv->bm_pools[i + port->nrxqs].id);
929 }
930
931 port->pool_long = NULL;
932 port->pool_short = NULL;
933
934 return 0;
935}
936
937static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
938{
939 if (port->priv->percpu_pools)
940 return mvpp2_swf_bm_pool_init_percpu(port);
941 else
942 return mvpp2_swf_bm_pool_init_shared(port);
943}
944
d66503c4
MC		 945static void mvpp2_set_hw_csum(struct mvpp2_port *port,
946 enum mvpp2_bm_pool_log_num new_long_pool)
947{
948 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
949
950 /* Update L4 checksum when jumbo enable/disable on port.
951 * Only port 0 supports hardware checksum offload due to
952 * the Tx FIFO size limitation.
953 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor
954 * has 7 bits, so the maximum L3 offset is 128.
955 */
956 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
957 port->dev->features &= ~csums;
958 port->dev->hw_features &= ~csums;
959 } else {
960 port->dev->features |= csums;
961 port->dev->hw_features |= csums;
962 }
963}
964
3f518509
MW		 965static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
966{
967 struct mvpp2_port *port = netdev_priv(dev);
576193f2
SC		 968 enum mvpp2_bm_pool_log_num new_long_pool;
969 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3f518509 970
7d04b0b1
MC		 971 if (port->priv->percpu_pools)
972 goto out_set;
973
576193f2
SC		 974 /* If port MTU is higher than 1518B:
975 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
976 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
977 */
978 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
979 new_long_pool = MVPP2_BM_JUMBO;
980 else
981 new_long_pool = MVPP2_BM_LONG;
982
983 if (new_long_pool != port->pool_long->id) {
984 /* Remove port from old short & long pool */
985 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
986 port->pool_long->pkt_size);
987 port->pool_long->port_map &= ~BIT(port->id);
988 port->pool_long = NULL;
989
990 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
991 port->pool_short->pkt_size);
992 port->pool_short->port_map &= ~BIT(port->id);
993 port->pool_short = NULL;
994
995 port->pkt_size = pkt_size;
996
997 /* Add port to new short & long pool */
998 mvpp2_swf_bm_pool_init(port);
999
d66503c4 1000 mvpp2_set_hw_csum(port, new_long_pool);
3f518509
MW		 1001 }
1002
7d04b0b1 1003out_set:
3f518509 1004 dev->mtu = mtu;
576193f2
SC		 1005 dev->wanted_features = dev->features;
1006
3f518509
MW		 1007 netdev_update_features(dev);
1008 return 0;
1009}
1010
1011static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
1012{
591f4cfa
TP		 1013 int i, sw_thread_mask = 0;
1014
1015 for (i = 0; i < port->nqvecs; i++)
1016 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
3f518509 1017
3f518509 1018 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
591f4cfa 1019 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
3f518509
MW		 1020}
1021
1022static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
1023{
591f4cfa
TP		 1024 int i, sw_thread_mask = 0;
1025
1026 for (i = 0; i < port->nqvecs; i++)
1027 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1028
1029 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1030 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
1031}
1032
1033static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
1034{
1035 struct mvpp2_port *port = qvec->port;
3f518509 1036
3f518509 1037 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
591f4cfa
TP		 1038 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
1039}
1040
1041static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
1042{
1043 struct mvpp2_port *port = qvec->port;
1044
1045 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1046 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
3f518509
MW		 1047}
1048
543ec376 1049/* Mask the current thread's Rx/Tx interrupts
e0af22d9
TP		 1050 * Called by on_each_cpu(), guaranteed to run with migration disabled,
1051 * using smp_processor_id() is OK.
1052 */
3f518509
MW		 1053static void mvpp2_interrupts_mask(void *arg)
1054{
1055 struct mvpp2_port *port = arg;
1056
e531f767
AT		 1057 /* If the thread isn't used, don't do anything */
1058 if (smp_processor_id() > port->priv->nthreads)
1059 return;
1060
1068549c 1061 mvpp2_thread_write(port->priv,
e531f767 1062 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
a786841d 1063 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
3f518509
MW		 1064}
1065
543ec376 1066/* Unmask the current thread's Rx/Tx interrupts.
e0af22d9
TP		 1067 * Called by on_each_cpu(), guaranteed to run with migration disabled,
1068 * using smp_processor_id() is OK.
1069 */
3f518509
MW		 1070static void mvpp2_interrupts_unmask(void *arg)
1071{
1072 struct mvpp2_port *port = arg;
213f428f
TP		 1073 u32 val;
1074
e531f767
AT		 1075 /* If the thread isn't used, don't do anything */
1076 if (smp_processor_id() > port->priv->nthreads)
1077 return;
1078
213f428f 1079 val = MVPP2_CAUSE_MISC_SUM_MASK |
70afb58e 1080 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
213f428f
TP		 1081 if (port->has_tx_irqs)
1082 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3f518509 1083
1068549c 1084 mvpp2_thread_write(port->priv,
e531f767 1085 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
213f428f
TP		 1086 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1087}
1088
1089static void
1090mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
1091{
1092 u32 val;
1093 int i;
1094
1095 if (port->priv->hw_version != MVPP22)
1096 return;
1097
1098 if (mask)
1099 val = 0;
1100 else
70afb58e 1101 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
213f428f
TP		 1102
1103 for (i = 0; i < port->nqvecs; i++) {
1104 struct mvpp2_queue_vector *v = port->qvecs + i;
1105
1106 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
1107 continue;
1108
1068549c 1109 mvpp2_thread_write(port->priv, v->sw_thread_id,
213f428f
TP		 1110 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1111 }
3f518509
MW		 1112}
1113
1114/* Port configuration routines */
b7d286f0
RK		 1115static bool mvpp2_is_xlg(phy_interface_t interface)
1116{
1117 return interface == PHY_INTERFACE_MODE_10GKR ||
1118 interface == PHY_INTERFACE_MODE_XAUI;
1119}
3f518509 1120
f84bf386
AT		 1121static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
1122{
1123 struct mvpp2 *priv = port->priv;
1124 u32 val;
1125
1126 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1127 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
1128 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1129
1130 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1131 if (port->gop_id == 2)
1132 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;
1133 else if (port->gop_id == 3)
1134 val |= GENCONF_CTRL0_PORT1_RGMII_MII;
1135 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1136}
1137
1138static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
1139{
1140 struct mvpp2 *priv = port->priv;
1141 u32 val;
1142
1143 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1144 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
1145 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
1146 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1147
1148 if (port->gop_id > 1) {
1149 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1150 if (port->gop_id == 2)
1151 val &= ~GENCONF_CTRL0_PORT0_RGMII;
1152 else if (port->gop_id == 3)
1153 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
1154 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1155 }
1156}
1157
1158static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1159{
1160 struct mvpp2 *priv = port->priv;
1161 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1162 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1163 u32 val;
1164
f84bf386
AT		 1165 val = readl(xpcs + MVPP22_XPCS_CFG0);
1166 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1167 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1168 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1169 writel(val, xpcs + MVPP22_XPCS_CFG0);
1170
f84bf386
AT		 1171 val = readl(mpcs + MVPP22_MPCS_CTRL);
1172 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1173 writel(val, mpcs + MVPP22_MPCS_CTRL);
1174
1175 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
7409e66e 1176 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7);
f84bf386
AT		 1177 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1178 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
f84bf386
AT		 1179}
1180
1181static int mvpp22_gop_init(struct mvpp2_port *port)
1182{
1183 struct mvpp2 *priv = port->priv;
1184 u32 val;
1185
1186 if (!priv->sysctrl_base)
1187 return 0;
1188
1189 switch (port->phy_interface) {
1190 case PHY_INTERFACE_MODE_RGMII:
1191 case PHY_INTERFACE_MODE_RGMII_ID:
1192 case PHY_INTERFACE_MODE_RGMII_RXID:
1193 case PHY_INTERFACE_MODE_RGMII_TXID:
1194 if (port->gop_id == 0)
1195 goto invalid_conf;
1196 mvpp22_gop_init_rgmii(port);
1197 break;
1198 case PHY_INTERFACE_MODE_SGMII:
d97c9f4a 1199 case PHY_INTERFACE_MODE_1000BASEX:
a6fe31de 1200 case PHY_INTERFACE_MODE_2500BASEX:
f84bf386
AT		 1201 mvpp22_gop_init_sgmii(port);
1202 break;
1203 case PHY_INTERFACE_MODE_10GKR:
1204 if (port->gop_id != 0)
1205 goto invalid_conf;
1206 mvpp22_gop_init_10gkr(port);
1207 break;
1208 default:
1209 goto unsupported_conf;
1210 }
1211
1212 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1213 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1214 GENCONF_PORT_CTRL1_EN(port->gop_id);
1215 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1216
1217 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1218 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1219 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1220
1221 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1222 val |= GENCONF_SOFT_RESET1_GOP;
1223 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1224
1225unsupported_conf:
1226 return 0;
1227
1228invalid_conf:
1229 netdev_err(port->dev, "Invalid port configuration\n");
1230 return -EINVAL;
1231}
1232
fd3651b2
AT		 1233static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1234{
1235 u32 val;
1236
1237 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
4a4cec72
RK		 1238 phy_interface_mode_is_8023z(port->phy_interface) ||
1239 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
fd3651b2
AT		 1240 /* Enable the GMAC link status irq for this port */
1241 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1242 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1243 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1244 }
1245
1246 if (port->gop_id == 0) {
1247 /* Enable the XLG/GIG irqs for this port */
1248 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1d9b041e 1249 if (mvpp2_is_xlg(port->phy_interface))
fd3651b2
AT		 1250 val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1251 else
1252 val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1253 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1254 }
1255}
1256
1257static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1258{
1259 u32 val;
1260
1261 if (port->gop_id == 0) {
1262 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1263 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
a3302baa 1264 MVPP22_XLG_EXT_INT_MASK_GIG);
fd3651b2
AT		 1265 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1266 }
1267
1268 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
4a4cec72
RK		 1269 phy_interface_mode_is_8023z(port->phy_interface) ||
1270 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
fd3651b2
AT		 1271 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1272 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1273 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1274 }
1275}
1276
1277static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1278{
1279 u32 val;
1280
bf2fa125
RK		 1281 if (port->phylink ||
1282 phy_interface_mode_is_rgmii(port->phy_interface) ||
4a4cec72
RK		 1283 phy_interface_mode_is_8023z(port->phy_interface) ||
1284 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
fd3651b2
AT		 1285 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1286 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1287 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1288 }
1289
1290 if (port->gop_id == 0) {
1291 val = readl(port->base + MVPP22_XLG_INT_MASK);
1292 val |= MVPP22_XLG_INT_MASK_LINK;
1293 writel(val, port->base + MVPP22_XLG_INT_MASK);
1294 }
1295
1296 mvpp22_gop_unmask_irq(port);
1297}
1298
a6fe31de
AT		 1299/* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1300 *
1301 * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1302 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1303 * differ.
1304 *
1305 * The COMPHY configures the serdes lanes regardless of the actual use of the
1306 * lanes by the physical layer. This is why configurations like
1307 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1308 */
542897d9
AT		 1309static int mvpp22_comphy_init(struct mvpp2_port *port)
1310{
542897d9
AT		 1311 int ret;
1312
1313 if (!port->comphy)
1314 return 0;
1315
cccc43b8
GS		 1316 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET,
1317 port->phy_interface);
542897d9
AT		 1318 if (ret)
1319 return ret;
1320
1321 return phy_power_on(port->comphy);
1322}
1323
3f518509
MW		 1324static void mvpp2_port_enable(struct mvpp2_port *port)
1325{
1326 u32 val;
1327
725757ae 1328 /* Only GOP port 0 has an XLG MAC */
b7d286f0 1329 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
725757ae 1330 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
649e51d5 1331 val |= MVPP22_XLG_CTRL0_PORT_EN;
725757ae
AT		 1332 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1333 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1334 } else {
1335 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1336 val |= MVPP2_GMAC_PORT_EN_MASK;
1337 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1338 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1339 }
3f518509
MW		 1340}
1341
1342static void mvpp2_port_disable(struct mvpp2_port *port)
1343{
1344 u32 val;
1345
725757ae 1346 /* Only GOP port 0 has an XLG MAC */
b7d286f0 1347 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
725757ae 1348 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4bb04326
AT		 1349 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1350 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
725757ae 1351 }
6b10bfc5
AT		 1352
1353 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1354 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1355 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3f518509
MW		 1356}
1357
1358/* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1359static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1360{
1361 u32 val;
1362
1363 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1364 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1365 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1366}
1367
1368/* Configure loopback port */
4bb04326
AT		 1369static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1370 const struct phylink_link_state *state)
3f518509
MW		 1371{
1372 u32 val;
1373
1374 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1375
4bb04326 1376 if (state->speed == 1000)
3f518509
MW		 1377 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1378 else
1379 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1380
4a4cec72
RK		 1381 if (phy_interface_mode_is_8023z(port->phy_interface) ||
1382 port->phy_interface == PHY_INTERFACE_MODE_SGMII)
3f518509
MW		 1383 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1384 else
1385 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1386
1387 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1388}
1389
118d6298
MR		 1390struct mvpp2_ethtool_counter {
1391 unsigned int offset;
1392 const char string[ETH_GSTRING_LEN];
1393 bool reg_is_64b;
1394};
1395
1396static u64 mvpp2_read_count(struct mvpp2_port *port,
1397 const struct mvpp2_ethtool_counter *counter)
1398{
1399 u64 val;
1400
1401 val = readl(port->stats_base + counter->offset);
1402 if (counter->reg_is_64b)
1403 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1404
1405 return val;
1406}
1407
9bea6897
MC		 1408/* Some counters are accessed indirectly by first writing an index to
1409 * MVPP2_CTRS_IDX. The index can represent various resources depending on the
1410 * register we access, it can be a hit counter for some classification tables,
1411 * a counter specific to a rxq, a txq or a buffer pool.
1412 */
1413static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg)
1414{
1415 mvpp2_write(priv, MVPP2_CTRS_IDX, index);
1416 return mvpp2_read(priv, reg);
1417}
1418
118d6298
MR		 1419/* Due to the fact that software statistics and hardware statistics are, by
1420 * design, incremented at different moments in the chain of packet processing,
1421 * it is very likely that incoming packets could have been dropped after being
1422 * counted by hardware but before reaching software statistics (most probably
1423 * multicast packets), and in the oppposite way, during transmission, FCS bytes
1424 * are added in between as well as TSO skb will be split and header bytes added.
1425 * Hence, statistics gathered from userspace with ifconfig (software) and
1426 * ethtool (hardware) cannot be compared.
1427 */
f9fa96b9 1428static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = {
118d6298
MR		 1429 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1430 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1431 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1432 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1433 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1434 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1435 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1436 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1437 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1438 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1439 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1440 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1441 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1442 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1443 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1444 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1445 { MVPP2_MIB_FC_SENT, "fc_sent" },
1446 { MVPP2_MIB_FC_RCVD, "fc_received" },
1447 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1448 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1449 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1450 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1451 { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1452 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1453 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1454 { MVPP2_MIB_COLLISION, "collision" },
1455 { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1456};
1457
9bea6897
MC		 1458static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = {
1459 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" },
1460 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" },
1461};
1462
1463static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = {
1464 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" },
1465 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" },
1466 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" },
1467 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" },
1468 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" },
1469 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" },
1470 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" },
1471 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" },
1472 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" },
1473};
1474
1475static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = {
1476 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" },
1477 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" },
1478 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" },
1479 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" },
1480};
1481
1482#define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \
1483 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \
1484 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \
1485 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)))
1486
118d6298
MR		 1487static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1488 u8 *data)
1489{
9bea6897
MC		 1490 struct mvpp2_port *port = netdev_priv(netdev);
1491 int i, q;
118d6298 1492
9bea6897
MC		 1493 if (sset != ETH_SS_STATS)
1494 return;
1495
1496 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) {
1497 strscpy(data, mvpp2_ethtool_mib_regs[i].string,
1498 ETH_GSTRING_LEN);
1499 data += ETH_GSTRING_LEN;
1500 }
1501
1502 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) {
1503 strscpy(data, mvpp2_ethtool_port_regs[i].string,
1504 ETH_GSTRING_LEN);
1505 data += ETH_GSTRING_LEN;
1506 }
1507
1508 for (q = 0; q < port->ntxqs; q++) {
1509 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) {
1510 snprintf(data, ETH_GSTRING_LEN,
1511 mvpp2_ethtool_txq_regs[i].string, q);
1512 data += ETH_GSTRING_LEN;
1513 }
1514 }
1515
1516 for (q = 0; q < port->nrxqs; q++) {
1517 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) {
1518 snprintf(data, ETH_GSTRING_LEN,
1519 mvpp2_ethtool_rxq_regs[i].string,
1520 q);
1521 data += ETH_GSTRING_LEN;
1522 }
118d6298
MR		 1523 }
1524}
1525
9bea6897
MC		 1526static void mvpp2_read_stats(struct mvpp2_port *port)
1527{
1528 u64 *pstats;
1529 int i, q;
1530
1531 pstats = port->ethtool_stats;
1532
1533 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++)
1534 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]);
1535
1536 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++)
1537 *pstats++ += mvpp2_read(port->priv,
1538 mvpp2_ethtool_port_regs[i].offset +
1539 4 * port->id);
1540
1541 for (q = 0; q < port->ntxqs; q++)
1542 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++)
1543 *pstats++ += mvpp2_read_index(port->priv,
1544 MVPP22_CTRS_TX_CTR(port->id, i),
1545 mvpp2_ethtool_txq_regs[i].offset);
1546
1547 /* Rxqs are numbered from 0 from the user standpoint, but not from the
1548 * driver's. We need to add the port->first_rxq offset.
1549 */
1550 for (q = 0; q < port->nrxqs; q++)
1551 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++)
1552 *pstats++ += mvpp2_read_index(port->priv,
1553 port->first_rxq + i,
1554 mvpp2_ethtool_rxq_regs[i].offset);
1555}
1556
118d6298
MR		 1557static void mvpp2_gather_hw_statistics(struct work_struct *work)
1558{
1559 struct delayed_work *del_work = to_delayed_work(work);
e5c500eb
MR		 1560 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
1561 stats_work);
118d6298 1562
e5c500eb 1563 mutex_lock(&port->gather_stats_lock);
118d6298 1564
9bea6897 1565 mvpp2_read_stats(port);
118d6298
MR		 1566
1567 /* No need to read again the counters right after this function if it
1568 * was called asynchronously by the user (ie. use of ethtool).
1569 */
e5c500eb
MR		 1570 cancel_delayed_work(&port->stats_work);
1571 queue_delayed_work(port->priv->stats_queue, &port->stats_work,
118d6298
MR		 1572 MVPP2_MIB_COUNTERS_STATS_DELAY);
1573
e5c500eb 1574 mutex_unlock(&port->gather_stats_lock);
118d6298
MR		 1575}
1576
1577static void mvpp2_ethtool_get_stats(struct net_device *dev,
1578 struct ethtool_stats *stats, u64 *data)
1579{
1580 struct mvpp2_port *port = netdev_priv(dev);
1581
e5c500eb
MR		 1582 /* Update statistics for the given port, then take the lock to avoid
1583 * concurrent accesses on the ethtool_stats structure during its copy.
1584 */
1585 mvpp2_gather_hw_statistics(&port->stats_work.work);
118d6298 1586
e5c500eb 1587 mutex_lock(&port->gather_stats_lock);
118d6298 1588 memcpy(data, port->ethtool_stats,
9bea6897 1589 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs));
e5c500eb 1590 mutex_unlock(&port->gather_stats_lock);
118d6298
MR		 1591}
1592
1593static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
1594{
9bea6897
MC		 1595 struct mvpp2_port *port = netdev_priv(dev);
1596
118d6298 1597 if (sset == ETH_SS_STATS)
9bea6897 1598 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs);
118d6298
MR		 1599
1600 return -EOPNOTSUPP;
1601}
1602
649e51d5 1603static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
3f518509 1604{
649e51d5 1605 u32 val;
118d6298 1606
316734fd
RK		 1607 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) |
1608 MVPP2_GMAC_PORT_RESET_MASK;
3f518509 1609 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
649e51d5
AT		 1610
1611 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
1612 val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
1613 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1614 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1615 }
3f518509
MW		 1616}
1617
7409e66e
AT		 1618static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
1619{
1620 struct mvpp2 *priv = port->priv;
1621 void __iomem *mpcs, *xpcs;
1622 u32 val;
1623
1624 if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
1625 return;
1626
1627 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1628 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1629
1630 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1631 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
1632 val |= MVPP22_MPCS_CLK_RESET_DIV_SET;
1633 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1634
1635 val = readl(xpcs + MVPP22_XPCS_CFG0);
1636 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
1637}
1638
1639static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
1640{
1641 struct mvpp2 *priv = port->priv;
1642 void __iomem *mpcs, *xpcs;
1643 u32 val;
1644
1645 if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
1646 return;
1647
1648 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1649 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1650
1651 switch (port->phy_interface) {
1652 case PHY_INTERFACE_MODE_10GKR:
1653 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1654 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
1655 MAC_CLK_RESET_SD_TX;
1656 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
1657 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1658 break;
1659 case PHY_INTERFACE_MODE_XAUI:
1660 case PHY_INTERFACE_MODE_RXAUI:
1661 val = readl(xpcs + MVPP22_XPCS_CFG0);
1662 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
1663 break;
1664 default:
1665 break;
1666 }
1667}
1668
3f518509
MW		 1669/* Change maximum receive size of the port */
1670static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
1671{
1672 u32 val;
1673
1674 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1675 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
1676 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1677 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
1678 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1679}
1680
76eb1b1d
SC		 1681/* Change maximum receive size of the port */
1682static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1683{
1684 u32 val;
1685
1686 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
1687 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
1688 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
ec15ecde 1689 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
76eb1b1d
SC		 1690 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
1691}
1692
3f518509
MW		 1693/* Set defaults to the MVPP2 port */
1694static void mvpp2_defaults_set(struct mvpp2_port *port)
1695{
21808437 1696 int tx_port_num, val, queue, lrxq;
3f518509 1697
3d9017d9 1698 if (port->priv->hw_version == MVPP21) {
3d9017d9
TP		 1699 /* Update TX FIFO MIN Threshold */
1700 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1701 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
1702 /* Min. TX threshold must be less than minimal packet length */
1703 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
1704 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1705 }
3f518509
MW		 1706
1707 /* Disable Legacy WRR, Disable EJP, Release from reset */
1708 tx_port_num = mvpp2_egress_port(port);
1709 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
1710 tx_port_num);
1711 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
1712
4251ea5b
MC		 1713 /* Set TXQ scheduling to Round-Robin */
1714 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
1715
3f518509 1716 /* Close bandwidth for all queues */
21808437 1717 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++)
3f518509 1718 mvpp2_write(port->priv,
21808437 1719 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
3f518509
MW		 1720
1721 /* Set refill period to 1 usec, refill tokens
1722 * and bucket size to maximum
1723 */
1724 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
1725 port->priv->tclk / USEC_PER_SEC);
1726 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
1727 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
1728 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
1729 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
1730 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
1731 val = MVPP2_TXP_TOKEN_SIZE_MAX;
1732 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1733
1734 /* Set MaximumLowLatencyPacketSize value to 256 */
1735 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
1736 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
1737 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
1738
1739 /* Enable Rx cache snoop */
09f83975 1740 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1741 queue = port->rxqs[lrxq]->id;
1742 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1743 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
1744 MVPP2_SNOOP_BUF_HDR_MASK;
1745 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1746 }
1747
1748 /* At default, mask all interrupts to all present cpus */
1749 mvpp2_interrupts_disable(port);
1750}
1751
1752/* Enable/disable receiving packets */
1753static void mvpp2_ingress_enable(struct mvpp2_port *port)
1754{
1755 u32 val;
1756 int lrxq, queue;
1757
09f83975 1758 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1759 queue = port->rxqs[lrxq]->id;
1760 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1761 val &= ~MVPP2_RXQ_DISABLE_MASK;
1762 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1763 }
1764}
1765
1766static void mvpp2_ingress_disable(struct mvpp2_port *port)
1767{
1768 u32 val;
1769 int lrxq, queue;
1770
09f83975 1771 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1772 queue = port->rxqs[lrxq]->id;
1773 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1774 val |= MVPP2_RXQ_DISABLE_MASK;
1775 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1776 }
1777}
1778
1779/* Enable transmit via physical egress queue
1780 * - HW starts take descriptors from DRAM
1781 */
1782static void mvpp2_egress_enable(struct mvpp2_port *port)
1783{
1784 u32 qmap;
1785 int queue;
1786 int tx_port_num = mvpp2_egress_port(port);
1787
1788 /* Enable all initialized TXs. */
1789 qmap = 0;
09f83975 1790 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 1791 struct mvpp2_tx_queue *txq = port->txqs[queue];
1792
dbbb2f03 1793 if (txq->descs)
3f518509
MW		 1794 qmap |= (1 << queue);
1795 }
1796
1797 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1798 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
1799}
1800
1801/* Disable transmit via physical egress queue
1802 * - HW doesn't take descriptors from DRAM
1803 */
1804static void mvpp2_egress_disable(struct mvpp2_port *port)
1805{
1806 u32 reg_data;
1807 int delay;
1808 int tx_port_num = mvpp2_egress_port(port);
1809
1810 /* Issue stop command for active channels only */
1811 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1812 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
1813 MVPP2_TXP_SCHED_ENQ_MASK;
1814 if (reg_data != 0)
1815 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
1816 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
1817
1818 /* Wait for all Tx activity to terminate. */
1819 delay = 0;
1820 do {
1821 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
1822 netdev_warn(port->dev,
1823 "Tx stop timed out, status=0x%08x\n",
1824 reg_data);
1825 break;
1826 }
1827 mdelay(1);
1828 delay++;
1829
1830 /* Check port TX Command register that all
1831 * Tx queues are stopped
1832 */
1833 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
1834 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
1835}
1836
1837/* Rx descriptors helper methods */
1838
1839/* Get number of Rx descriptors occupied by received packets */
1840static inline int
1841mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
1842{
1843 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
1844
1845 return val & MVPP2_RXQ_OCCUPIED_MASK;
1846}
1847
1848/* Update Rx queue status with the number of occupied and available
1849 * Rx descriptor slots.
1850 */
1851static inline void
1852mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
1853 int used_count, int free_count)
1854{
1855 /* Decrement the number of used descriptors and increment count
1856 * increment the number of free descriptors.
1857 */
1858 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
1859
1860 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
1861}
1862
1863/* Get pointer to next RX descriptor to be processed by SW */
1864static inline struct mvpp2_rx_desc *
1865mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
1866{
1867 int rx_desc = rxq->next_desc_to_proc;
1868
1869 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
1870 prefetch(rxq->descs + rxq->next_desc_to_proc);
1871 return rxq->descs + rx_desc;
1872}
1873
1874/* Set rx queue offset */
1875static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
1876 int prxq, int offset)
1877{
1878 u32 val;
1879
1880 /* Convert offset from bytes to units of 32 bytes */
1881 offset = offset >> 5;
1882
1883 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
1884 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
1885
1886 /* Offset is in */
1887 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
1888 MVPP2_RXQ_PACKET_OFFSET_MASK);
1889
1890 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
1891}
1892
3f518509
MW		 1893/* Tx descriptors helper methods */
1894
3f518509
MW		 1895/* Get pointer to next Tx descriptor to be processed (send) by HW */
1896static struct mvpp2_tx_desc *
1897mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
1898{
1899 int tx_desc = txq->next_desc_to_proc;
1900
1901 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
1902 return txq->descs + tx_desc;
1903}
1904
e0af22d9
TP		 1905/* Update HW with number of aggregated Tx descriptors to be sent
1906 *
1907 * Called only from mvpp2_tx(), so migration is disabled, using
1908 * smp_processor_id() is OK.
1909 */
3f518509
MW		 1910static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
1911{
1912 /* aggregated access - relevant TXQ number is written in TX desc */
1068549c 1913 mvpp2_thread_write(port->priv,
e531f767 1914 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
a786841d 1915 MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3f518509
MW		 1916}
1917
3f518509
MW		 1918/* Check if there are enough free descriptors in aggregated txq.
1919 * If not, update the number of occupied descriptors and repeat the check.
e0af22d9
TP		 1920 *
1921 * Called only from mvpp2_tx(), so migration is disabled, using
1922 * smp_processor_id() is OK.
3f518509 1923 */
e531f767 1924static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
3f518509
MW		 1925 struct mvpp2_tx_queue *aggr_txq, int num)
1926{
02856a3b 1927 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
3f518509 1928 /* Update number of occupied aggregated Tx descriptors */
e531f767
AT		 1929 unsigned int thread =
1930 mvpp2_cpu_to_thread(port->priv, smp_processor_id());
1931 u32 val = mvpp2_read_relaxed(port->priv,
543ec376 1932 MVPP2_AGGR_TXQ_STATUS_REG(thread));
3f518509
MW		 1933
1934 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
3f518509 1935
914365f1
YM		 1936 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
1937 return -ENOMEM;
1938 }
3f518509
MW		 1939 return 0;
1940}
1941
e0af22d9
TP		 1942/* Reserved Tx descriptors allocation request
1943 *
1944 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
1945 * only by mvpp2_tx(), so migration is disabled, using
1946 * smp_processor_id() is OK.
1947 */
e531f767 1948static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
3f518509
MW		 1949 struct mvpp2_tx_queue *txq, int num)
1950{
e531f767
AT		 1951 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
1952 struct mvpp2 *priv = port->priv;
3f518509
MW		 1953 u32 val;
1954
1955 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
1068549c 1956 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
3f518509 1957
1068549c 1958 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
3f518509
MW		 1959
1960 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
1961}
1962
1963/* Check if there are enough reserved descriptors for transmission.
1964 * If not, request chunk of reserved descriptors and check again.
1965 */
074c74df 1966static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
3f518509
MW		 1967 struct mvpp2_tx_queue *txq,
1968 struct mvpp2_txq_pcpu *txq_pcpu,
1969 int num)
1970{
850623b3 1971 int req, desc_count;
074c74df 1972 unsigned int thread;
3f518509
MW		 1973
1974 if (txq_pcpu->reserved_num >= num)
1975 return 0;
1976
1977 /* Not enough descriptors reserved! Update the reserved descriptor
1978 * count and check again.
1979 */
1980
1981 desc_count = 0;
1982 /* Compute total of used descriptors */
e531f767 1983 for (thread = 0; thread < port->priv->nthreads; thread++) {
3f518509
MW		 1984 struct mvpp2_txq_pcpu *txq_pcpu_aux;
1985
074c74df 1986 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
3f518509
MW		 1987 desc_count += txq_pcpu_aux->count;
1988 desc_count += txq_pcpu_aux->reserved_num;
1989 }
1990
1991 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
1992 desc_count += req;
1993
1994 if (desc_count >
074c74df 1995 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
3f518509
MW		 1996 return -ENOMEM;
1997
e531f767 1998 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
3f518509 1999
a3302baa 2000 /* OK, the descriptor could have been updated: check again. */
3f518509
MW		 2001 if (txq_pcpu->reserved_num < num)
2002 return -ENOMEM;
2003 return 0;
2004}
2005
2006/* Release the last allocated Tx descriptor. Useful to handle DMA
2007 * mapping failures in the Tx path.
2008 */
2009static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
2010{
2011 if (txq->next_desc_to_proc == 0)
2012 txq->next_desc_to_proc = txq->last_desc - 1;
2013 else
2014 txq->next_desc_to_proc--;
2015}
2016
2017/* Set Tx descriptors fields relevant for CSUM calculation */
35f3625c 2018static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
3f518509
MW		 2019 int ip_hdr_len, int l4_proto)
2020{
2021 u32 command;
2022
2023 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
2024 * G_L4_chk, L4_type required only for checksum calculation
2025 */
2026 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
2027 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
2028 command |= MVPP2_TXD_IP_CSUM_DISABLE;
2029
dc734dbe 2030 if (l3_proto == htons(ETH_P_IP)) {
3f518509
MW		 2031 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
2032 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
2033 } else {
2034 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
2035 }
2036
2037 if (l4_proto == IPPROTO_TCP) {
2038 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
2039 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
2040 } else if (l4_proto == IPPROTO_UDP) {
2041 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
2042 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
2043 } else {
2044 command |= MVPP2_TXD_L4_CSUM_NOT;
2045 }
2046
2047 return command;
2048}
2049
2050/* Get number of sent descriptors and decrement counter.
2051 * The number of sent descriptors is returned.
543ec376 2052 * Per-thread access
e0af22d9
TP		 2053 *
2054 * Called only from mvpp2_txq_done(), called from mvpp2_tx()
2055 * (migration disabled) and from the TX completion tasklet (migration
2056 * disabled) so using smp_processor_id() is OK.
3f518509
MW		 2057 */
2058static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
2059 struct mvpp2_tx_queue *txq)
2060{
2061 u32 val;
2062
2063 /* Reading status reg resets transmitted descriptor counter */
1068549c 2064 val = mvpp2_thread_read_relaxed(port->priv,
e531f767 2065 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
cdcfeb0f 2066 MVPP2_TXQ_SENT_REG(txq->id));
3f518509
MW		 2067
2068 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
2069 MVPP2_TRANSMITTED_COUNT_OFFSET;
2070}
2071
e0af22d9
TP		 2072/* Called through on_each_cpu(), so runs on all CPUs, with migration
2073 * disabled, therefore using smp_processor_id() is OK.
2074 */
3f518509
MW		 2075static void mvpp2_txq_sent_counter_clear(void *arg)
2076{
2077 struct mvpp2_port *port = arg;
2078 int queue;
2079
e531f767
AT		 2080 /* If the thread isn't used, don't do anything */
2081 if (smp_processor_id() > port->priv->nthreads)
2082 return;
2083
09f83975 2084 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 2085 int id = port->txqs[queue]->id;
2086
1068549c 2087 mvpp2_thread_read(port->priv,
e531f767 2088 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
a786841d 2089 MVPP2_TXQ_SENT_REG(id));
3f518509
MW		 2090 }
2091}
2092
2093/* Set max sizes for Tx queues */
2094static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
2095{
2096 u32 val, size, mtu;
2097 int txq, tx_port_num;
2098
2099 mtu = port->pkt_size * 8;
2100 if (mtu > MVPP2_TXP_MTU_MAX)
2101 mtu = MVPP2_TXP_MTU_MAX;
2102
2103 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
2104 mtu = 3 * mtu;
2105
2106 /* Indirect access to registers */
2107 tx_port_num = mvpp2_egress_port(port);
2108 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2109
2110 /* Set MTU */
2111 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
2112 val &= ~MVPP2_TXP_MTU_MAX;
2113 val |= mtu;
2114 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
2115
2116 /* TXP token size and all TXQs token size must be larger that MTU */
2117 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
2118 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
2119 if (size < mtu) {
2120 size = mtu;
2121 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
2122 val |= size;
2123 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2124 }
2125
09f83975 2126 for (txq = 0; txq < port->ntxqs; txq++) {
3f518509
MW		 2127 val = mvpp2_read(port->priv,
2128 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
2129 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
2130
2131 if (size < mtu) {
2132 size = mtu;
2133 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
2134 val |= size;
2135 mvpp2_write(port->priv,
2136 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
2137 val);
2138 }
2139 }
2140}
2141
2142/* Set the number of packets that will be received before Rx interrupt
2143 * will be generated by HW.
2144 */
2145static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
d63f9e41 2146 struct mvpp2_rx_queue *rxq)
3f518509 2147{
e531f767 2148 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
a786841d 2149
f8b0d5f8
TP		 2150 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
2151 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
3f518509 2152
1068549c
AT		 2153 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2154 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
a786841d 2155 rxq->pkts_coal);
a704bb5c
TP		 2156
2157 put_cpu();
3f518509
MW		 2158}
2159
213f428f
TP		 2160/* For some reason in the LSP this is done on each CPU. Why ? */
2161static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
2162 struct mvpp2_tx_queue *txq)
2163{
e531f767 2164 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
213f428f
TP		 2165 u32 val;
2166
2167 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
2168 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
2169
2170 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
1068549c
AT		 2171 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2172 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
213f428f
TP		 2173
2174 put_cpu();
2175}
2176
ab42676a
TP		 2177static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
2178{
2179 u64 tmp = (u64)clk_hz * usec;
2180
2181 do_div(tmp, USEC_PER_SEC);
2182
2183 return tmp > U32_MAX ? U32_MAX : tmp;
2184}
2185
2186static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
2187{
2188 u64 tmp = (u64)cycles * USEC_PER_SEC;
2189
2190 do_div(tmp, clk_hz);
2191
2192 return tmp > U32_MAX ? U32_MAX : tmp;
2193}
2194
3f518509
MW		 2195/* Set the time delay in usec before Rx interrupt */
2196static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
d63f9e41 2197 struct mvpp2_rx_queue *rxq)
3f518509 2198{
ab42676a
TP		 2199 unsigned long freq = port->priv->tclk;
2200 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2201
2202 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
2203 rxq->time_coal =
2204 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
2205
2206 /* re-evaluate to get actual register value */
2207 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2208 }
3f518509 2209
3f518509 2210 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
3f518509
MW		 2211}
2212
213f428f
TP		 2213static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
2214{
2215 unsigned long freq = port->priv->tclk;
2216 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2217
2218 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
2219 port->tx_time_coal =
2220 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
2221
2222 /* re-evaluate to get actual register value */
2223 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2224 }
2225
2226 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
2227}
2228
3f518509
MW		 2229/* Free Tx queue skbuffs */
2230static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
2231 struct mvpp2_tx_queue *txq,
2232 struct mvpp2_txq_pcpu *txq_pcpu, int num)
2233{
2234 int i;
2235
2236 for (i = 0; i < num; i++) {
8354491c
TP		 2237 struct mvpp2_txq_pcpu_buf *tx_buf =
2238 txq_pcpu->buffs + txq_pcpu->txq_get_index;
3f518509 2239
20920267
AT		 2240 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma))
2241 dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
2242 tx_buf->size, DMA_TO_DEVICE);
36fb7435
TP		 2243 if (tx_buf->skb)
2244 dev_kfree_skb_any(tx_buf->skb);
2245
2246 mvpp2_txq_inc_get(txq_pcpu);
3f518509
MW		 2247 }
2248}
2249
2250static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2251 u32 cause)
2252{
2253 int queue = fls(cause) - 1;
2254
2255 return port->rxqs[queue];
2256}
2257
2258static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2259 u32 cause)
2260{
edc660fa 2261 int queue = fls(cause) - 1;
3f518509
MW		 2262
2263 return port->txqs[queue];
2264}
2265
2266/* Handle end of transmission */
2267static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2268 struct mvpp2_txq_pcpu *txq_pcpu)
2269{
2270 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2271 int tx_done;
2272
e531f767 2273 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
3f518509
MW		 2274 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2275
2276 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2277 if (!tx_done)
2278 return;
2279 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2280
2281 txq_pcpu->count -= tx_done;
2282
2283 if (netif_tx_queue_stopped(nq))
1d17db08 2284 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
3f518509
MW		 2285 netif_tx_wake_queue(nq);
2286}
2287
213f428f 2288static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
543ec376 2289 unsigned int thread)
edc660fa
MW		 2290{
2291 struct mvpp2_tx_queue *txq;
2292 struct mvpp2_txq_pcpu *txq_pcpu;
2293 unsigned int tx_todo = 0;
2294
2295 while (cause) {
2296 txq = mvpp2_get_tx_queue(port, cause);
2297 if (!txq)
2298 break;
2299
543ec376 2300 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
edc660fa
MW		 2301
2302 if (txq_pcpu->count) {
2303 mvpp2_txq_done(port, txq, txq_pcpu);
2304 tx_todo += txq_pcpu->count;
2305 }
2306
2307 cause &= ~(1 << txq->log_id);
2308 }
2309 return tx_todo;
2310}
2311
3f518509
MW		 2312/* Rx/Tx queue initialization/cleanup methods */
2313
2314/* Allocate and initialize descriptors for aggr TXQ */
2315static int mvpp2_aggr_txq_init(struct platform_device *pdev,
850623b3 2316 struct mvpp2_tx_queue *aggr_txq,
543ec376 2317 unsigned int thread, struct mvpp2 *priv)
3f518509 2318{
b02f31fb
TP		 2319 u32 txq_dma;
2320
3f518509 2321 /* Allocate memory for TX descriptors */
750afb08
LC		 2322 aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
2323 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2324 &aggr_txq->descs_dma, GFP_KERNEL);
3f518509
MW		 2325 if (!aggr_txq->descs)
2326 return -ENOMEM;
2327
02856a3b 2328 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
3f518509
MW		 2329
2330 /* Aggr TXQ no reset WA */
2331 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
543ec376 2332 MVPP2_AGGR_TXQ_INDEX_REG(thread));
3f518509 2333
b02f31fb
TP		 2334 /* Set Tx descriptors queue starting address indirect
2335 * access
2336 */
2337 if (priv->hw_version == MVPP21)
2338 txq_dma = aggr_txq->descs_dma;
2339 else
2340 txq_dma = aggr_txq->descs_dma >>
2341 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2342
543ec376
AT		 2343 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2344 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
85affd7e 2345 MVPP2_AGGR_TXQ_SIZE);
3f518509
MW		 2346
2347 return 0;
2348}
2349
2350/* Create a specified Rx queue */
2351static int mvpp2_rxq_init(struct mvpp2_port *port,
2352 struct mvpp2_rx_queue *rxq)
2353
2354{
543ec376 2355 unsigned int thread;
b02f31fb
TP		 2356 u32 rxq_dma;
2357
3f518509
MW		 2358 rxq->size = port->rx_ring_size;
2359
2360 /* Allocate memory for RX descriptors */
2361 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2362 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2363 &rxq->descs_dma, GFP_KERNEL);
3f518509
MW		 2364 if (!rxq->descs)
2365 return -ENOMEM;
2366
3f518509
MW		 2367 rxq->last_desc = rxq->size - 1;
2368
2369 /* Zero occupied and non-occupied counters - direct access */
2370 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2371
2372 /* Set Rx descriptors queue starting address - indirect access */
e531f767 2373 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1068549c 2374 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
b02f31fb
TP		 2375 if (port->priv->hw_version == MVPP21)
2376 rxq_dma = rxq->descs_dma;
2377 else
2378 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
1068549c
AT		 2379 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2380 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2381 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
a704bb5c 2382 put_cpu();
3f518509
MW		 2383
2384 /* Set Offset */
2385 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
2386
2387 /* Set coalescing pkts and time */
d63f9e41
TP		 2388 mvpp2_rx_pkts_coal_set(port, rxq);
2389 mvpp2_rx_time_coal_set(port, rxq);
3f518509
MW		 2390
2391 /* Add number of descriptors ready for receiving packets */
2392 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2393
2394 return 0;
2395}
2396
2397/* Push packets received by the RXQ to BM pool */
2398static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
2399 struct mvpp2_rx_queue *rxq)
2400{
2401 int rx_received, i;
2402
2403 rx_received = mvpp2_rxq_received(port, rxq->id);
2404 if (!rx_received)
2405 return;
2406
2407 for (i = 0; i < rx_received; i++) {
2408 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
56b8aae9
TP		 2409 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2410 int pool;
2411
2412 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2413 MVPP2_RXD_BM_POOL_ID_OFFS;
3f518509 2414
7d7627ba 2415 mvpp2_bm_pool_put(port, pool,
ac3dd277
TP		 2416 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
2417 mvpp2_rxdesc_cookie_get(port, rx_desc));
3f518509
MW		 2418 }
2419 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
2420}
2421
2422/* Cleanup Rx queue */
2423static void mvpp2_rxq_deinit(struct mvpp2_port *port,
2424 struct mvpp2_rx_queue *rxq)
2425{
543ec376 2426 unsigned int thread;
a786841d 2427
3f518509
MW		 2428 mvpp2_rxq_drop_pkts(port, rxq);
2429
2430 if (rxq->descs)
2431 dma_free_coherent(port->dev->dev.parent,
2432 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2433 rxq->descs,
20396136 2434 rxq->descs_dma);
3f518509
MW		 2435
2436 rxq->descs = NULL;
2437 rxq->last_desc = 0;
2438 rxq->next_desc_to_proc = 0;
20396136 2439 rxq->descs_dma = 0;
3f518509
MW		 2440
2441 /* Clear Rx descriptors queue starting address and size;
2442 * free descriptor number
2443 */
2444 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
e531f767 2445 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1068549c
AT		 2446 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2447 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
2448 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
a704bb5c 2449 put_cpu();
3f518509
MW		 2450}
2451
2452/* Create and initialize a Tx queue */
2453static int mvpp2_txq_init(struct mvpp2_port *port,
2454 struct mvpp2_tx_queue *txq)
2455{
2456 u32 val;
074c74df 2457 unsigned int thread;
850623b3 2458 int desc, desc_per_txq, tx_port_num;
3f518509
MW		 2459 struct mvpp2_txq_pcpu *txq_pcpu;
2460
2461 txq->size = port->tx_ring_size;
2462
2463 /* Allocate memory for Tx descriptors */
2464 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
2465 txq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2466 &txq->descs_dma, GFP_KERNEL);
3f518509
MW		 2467 if (!txq->descs)
2468 return -ENOMEM;
2469
3f518509
MW		 2470 txq->last_desc = txq->size - 1;
2471
2472 /* Set Tx descriptors queue starting address - indirect access */
e531f767 2473 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1068549c
AT		 2474 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2475 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
a786841d 2476 txq->descs_dma);
1068549c 2477 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
a786841d 2478 txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
1068549c
AT		 2479 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
2480 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
a786841d 2481 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
1068549c 2482 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
3f518509 2483 val &= ~MVPP2_TXQ_PENDING_MASK;
1068549c 2484 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
3f518509
MW		 2485
2486 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
2487 * for each existing TXQ.
2488 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
a3302baa 2489 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
3f518509
MW		 2490 */
2491 desc_per_txq = 16;
2492 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
2493 (txq->log_id * desc_per_txq);
2494
1068549c 2495 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
a786841d
TP		 2496 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
2497 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
a704bb5c 2498 put_cpu();
3f518509
MW		 2499
2500 /* WRR / EJP configuration - indirect access */
2501 tx_port_num = mvpp2_egress_port(port);
2502 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2503
2504 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
2505 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
2506 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
2507 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
2508 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
2509
2510 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
2511 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
2512 val);
2513
e531f767 2514 for (thread = 0; thread < port->priv->nthreads; thread++) {
074c74df 2515 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3f518509 2516 txq_pcpu->size = txq->size;
02c91ece
ME		 2517 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
2518 sizeof(*txq_pcpu->buffs),
2519 GFP_KERNEL);
8354491c 2520 if (!txq_pcpu->buffs)
ba2d8d88 2521 return -ENOMEM;
3f518509
MW		 2522
2523 txq_pcpu->count = 0;
2524 txq_pcpu->reserved_num = 0;
2525 txq_pcpu->txq_put_index = 0;
2526 txq_pcpu->txq_get_index = 0;
b70d4a51 2527 txq_pcpu->tso_headers = NULL;
186cd4d4 2528
1d17db08
AT		 2529 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
2530 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
2531
186cd4d4
AT		 2532 txq_pcpu->tso_headers =
2533 dma_alloc_coherent(port->dev->dev.parent,
822eaf7c 2534 txq_pcpu->size * TSO_HEADER_SIZE,
186cd4d4
AT		 2535 &txq_pcpu->tso_headers_dma,
2536 GFP_KERNEL);
2537 if (!txq_pcpu->tso_headers)
ba2d8d88 2538 return -ENOMEM;
3f518509
MW		 2539 }
2540
2541 return 0;
2542}
2543
2544/* Free allocated TXQ resources */
2545static void mvpp2_txq_deinit(struct mvpp2_port *port,
2546 struct mvpp2_tx_queue *txq)
2547{
2548 struct mvpp2_txq_pcpu *txq_pcpu;
074c74df 2549 unsigned int thread;
3f518509 2550
e531f767 2551 for (thread = 0; thread < port->priv->nthreads; thread++) {
074c74df 2552 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
8354491c 2553 kfree(txq_pcpu->buffs);
186cd4d4 2554
b70d4a51
AT		 2555 if (txq_pcpu->tso_headers)
2556 dma_free_coherent(port->dev->dev.parent,
2557 txq_pcpu->size * TSO_HEADER_SIZE,
2558 txq_pcpu->tso_headers,
2559 txq_pcpu->tso_headers_dma);
2560
2561 txq_pcpu->tso_headers = NULL;
3f518509
MW		 2562 }
2563
2564 if (txq->descs)
2565 dma_free_coherent(port->dev->dev.parent,
2566 txq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2567 txq->descs, txq->descs_dma);
3f518509
MW		 2568
2569 txq->descs = NULL;
2570 txq->last_desc = 0;
2571 txq->next_desc_to_proc = 0;
20396136 2572 txq->descs_dma = 0;
3f518509
MW		 2573
2574 /* Set minimum bandwidth for disabled TXQs */
21808437 2575 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
3f518509
MW		 2576
2577 /* Set Tx descriptors queue starting address and size */
e531f767 2578 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1068549c
AT		 2579 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2580 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
2581 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
a704bb5c 2582 put_cpu();
3f518509
MW		 2583}
2584
2585/* Cleanup Tx ports */
2586static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
2587{
2588 struct mvpp2_txq_pcpu *txq_pcpu;
850623b3 2589 int delay, pending;
e531f767 2590 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3f518509
MW		 2591 u32 val;
2592
1068549c
AT		 2593 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2594 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
3f518509 2595 val |= MVPP2_TXQ_DRAIN_EN_MASK;
1068549c 2596 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3f518509
MW		 2597
2598 /* The napi queue has been stopped so wait for all packets
2599 * to be transmitted.
2600 */
2601 delay = 0;
2602 do {
2603 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
2604 netdev_warn(port->dev,
2605 "port %d: cleaning queue %d timed out\n",
2606 port->id, txq->log_id);
2607 break;
2608 }
2609 mdelay(1);
2610 delay++;
2611
1068549c 2612 pending = mvpp2_thread_read(port->priv, thread,
a786841d
TP		 2613 MVPP2_TXQ_PENDING_REG);
2614 pending &= MVPP2_TXQ_PENDING_MASK;
3f518509
MW		 2615 } while (pending);
2616
2617 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
1068549c 2618 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
a704bb5c 2619 put_cpu();
3f518509 2620
e531f767 2621 for (thread = 0; thread < port->priv->nthreads; thread++) {
074c74df 2622 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3f518509
MW		 2623
2624 /* Release all packets */
2625 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
2626
2627 /* Reset queue */
2628 txq_pcpu->count = 0;
2629 txq_pcpu->txq_put_index = 0;
2630 txq_pcpu->txq_get_index = 0;
2631 }
2632}
2633
2634/* Cleanup all Tx queues */
2635static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
2636{
2637 struct mvpp2_tx_queue *txq;
2638 int queue;
2639 u32 val;
2640
2641 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
2642
2643 /* Reset Tx ports and delete Tx queues */
2644 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
2645 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2646
09f83975 2647 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 2648 txq = port->txqs[queue];
2649 mvpp2_txq_clean(port, txq);
2650 mvpp2_txq_deinit(port, txq);
2651 }
2652
2653 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2654
2655 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
2656 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2657}
2658
2659/* Cleanup all Rx queues */
2660static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
2661{
2662 int queue;
2663
09f83975 2664 for (queue = 0; queue < port->nrxqs; queue++)
3f518509
MW		 2665 mvpp2_rxq_deinit(port, port->rxqs[queue]);
2666}
2667
2668/* Init all Rx queues for port */
2669static int mvpp2_setup_rxqs(struct mvpp2_port *port)
2670{
2671 int queue, err;
2672
09f83975 2673 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 2674 err = mvpp2_rxq_init(port, port->rxqs[queue]);
2675 if (err)
2676 goto err_cleanup;
2677 }
2678 return 0;
2679
2680err_cleanup:
2681 mvpp2_cleanup_rxqs(port);
2682 return err;
2683}
2684
2685/* Init all tx queues for port */
2686static int mvpp2_setup_txqs(struct mvpp2_port *port)
2687{
2688 struct mvpp2_tx_queue *txq;
0d283ab5 2689 int queue, err, cpu;
3f518509 2690
09f83975 2691 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 2692 txq = port->txqs[queue];
2693 err = mvpp2_txq_init(port, txq);
2694 if (err)
2695 goto err_cleanup;
0d283ab5
MC		 2696
2697 /* Assign this queue to a CPU */
2698 cpu = queue % num_present_cpus();
2699 netif_set_xps_queue(port->dev, cpumask_of(cpu), queue);
3f518509
MW		 2700 }
2701
213f428f
TP		 2702 if (port->has_tx_irqs) {
2703 mvpp2_tx_time_coal_set(port);
2704 for (queue = 0; queue < port->ntxqs; queue++) {
2705 txq = port->txqs[queue];
2706 mvpp2_tx_pkts_coal_set(port, txq);
2707 }
2708 }
2709
3f518509
MW		 2710 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2711 return 0;
2712
2713err_cleanup:
2714 mvpp2_cleanup_txqs(port);
2715 return err;
2716}
2717
2718/* The callback for per-port interrupt */
2719static irqreturn_t mvpp2_isr(int irq, void *dev_id)
2720{
591f4cfa 2721 struct mvpp2_queue_vector *qv = dev_id;
3f518509 2722
591f4cfa 2723 mvpp2_qvec_interrupt_disable(qv);
3f518509 2724
591f4cfa 2725 napi_schedule(&qv->napi);
3f518509
MW		 2726
2727 return IRQ_HANDLED;
2728}
2729
fd3651b2
AT		 2730/* Per-port interrupt for link status changes */
2731static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
2732{
2733 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
2734 struct net_device *dev = port->dev;
2735 bool event = false, link = false;
2736 u32 val;
2737
2738 mvpp22_gop_mask_irq(port);
2739
1d9b041e 2740 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
fd3651b2
AT		 2741 val = readl(port->base + MVPP22_XLG_INT_STAT);
2742 if (val & MVPP22_XLG_INT_STAT_LINK) {
2743 event = true;
2744 val = readl(port->base + MVPP22_XLG_STATUS);
2745 if (val & MVPP22_XLG_STATUS_LINK_UP)
2746 link = true;
2747 }
2748 } else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
4a4cec72
RK		 2749 phy_interface_mode_is_8023z(port->phy_interface) ||
2750 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
fd3651b2
AT		 2751 val = readl(port->base + MVPP22_GMAC_INT_STAT);
2752 if (val & MVPP22_GMAC_INT_STAT_LINK) {
2753 event = true;
2754 val = readl(port->base + MVPP2_GMAC_STATUS0);
2755 if (val & MVPP2_GMAC_STATUS0_LINK_UP)
2756 link = true;
2757 }
2758 }
2759
4bb04326
AT		 2760 if (port->phylink) {
2761 phylink_mac_change(port->phylink, link);
2762 goto handled;
2763 }
2764
fd3651b2
AT		 2765 if (!netif_running(dev) || !event)
2766 goto handled;
2767
2768 if (link) {
2769 mvpp2_interrupts_enable(port);
2770
2771 mvpp2_egress_enable(port);
2772 mvpp2_ingress_enable(port);
2773 netif_carrier_on(dev);
2774 netif_tx_wake_all_queues(dev);
2775 } else {
2776 netif_tx_stop_all_queues(dev);
2777 netif_carrier_off(dev);
2778 mvpp2_ingress_disable(port);
2779 mvpp2_egress_disable(port);
2780
2781 mvpp2_interrupts_disable(port);
2782 }
2783
2784handled:
2785 mvpp22_gop_unmask_irq(port);
2786 return IRQ_HANDLED;
2787}
2788
ecb9f80d 2789static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
edc660fa 2790{
ecb9f80d
TG		 2791 struct net_device *dev;
2792 struct mvpp2_port *port;
074c74df 2793 struct mvpp2_port_pcpu *port_pcpu;
edc660fa
MW		 2794 unsigned int tx_todo, cause;
2795
ecb9f80d
TG		 2796 port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer);
2797 dev = port_pcpu->dev;
074c74df 2798
edc660fa 2799 if (!netif_running(dev))
ecb9f80d
TG		 2800 return HRTIMER_NORESTART;
2801
edc660fa 2802 port_pcpu->timer_scheduled = false;
ecb9f80d 2803 port = netdev_priv(dev);
edc660fa
MW		 2804
2805 /* Process all the Tx queues */
09f83975 2806 cause = (1 << port->ntxqs) - 1;
074c74df 2807 tx_todo = mvpp2_tx_done(port, cause,
e531f767 2808 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
edc660fa
MW		 2809
2810 /* Set the timer in case not all the packets were processed */
ecb9f80d
TG		 2811 if (tx_todo && !port_pcpu->timer_scheduled) {
2812 port_pcpu->timer_scheduled = true;
2813 hrtimer_forward_now(&port_pcpu->tx_done_timer,
2814 MVPP2_TXDONE_HRTIMER_PERIOD_NS);
edc660fa 2815
ecb9f80d
TG		 2816 return HRTIMER_RESTART;
2817 }
edc660fa
MW		 2818 return HRTIMER_NORESTART;
2819}
2820
3f518509
MW		 2821/* Main RX/TX processing routines */
2822
2823/* Display more error info */
2824static void mvpp2_rx_error(struct mvpp2_port *port,
2825 struct mvpp2_rx_desc *rx_desc)
2826{
ac3dd277
TP		 2827 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2828 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
934e0f83 2829 char *err_str = NULL;
3f518509
MW		 2830
2831 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
2832 case MVPP2_RXD_ERR_CRC:
934e0f83 2833 err_str = "crc";
3f518509
MW		 2834 break;
2835 case MVPP2_RXD_ERR_OVERRUN:
934e0f83 2836 err_str = "overrun";
3f518509
MW		 2837 break;
2838 case MVPP2_RXD_ERR_RESOURCE:
934e0f83 2839 err_str = "resource";
3f518509
MW		 2840 break;
2841 }
934e0f83
YM		 2842 if (err_str && net_ratelimit())
2843 netdev_err(port->dev,
2844 "bad rx status %08x (%s error), size=%zu\n",
2845 status, err_str, sz);
3f518509
MW		 2846}
2847
2848/* Handle RX checksum offload */
2849static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
2850 struct sk_buff *skb)
2851{
2852 if (((status & MVPP2_RXD_L3_IP4) &&
2853 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
2854 (status & MVPP2_RXD_L3_IP6))
2855 if (((status & MVPP2_RXD_L4_UDP) ||
2856 (status & MVPP2_RXD_L4_TCP)) &&
2857 (status & MVPP2_RXD_L4_CSUM_OK)) {
2858 skb->csum = 0;
2859 skb->ip_summed = CHECKSUM_UNNECESSARY;
2860 return;
2861 }
2862
2863 skb->ip_summed = CHECKSUM_NONE;
2864}
2865
80f60a91 2866/* Allocate a new skb and add it to BM pool */
3f518509 2867static int mvpp2_rx_refill(struct mvpp2_port *port,
56b8aae9 2868 struct mvpp2_bm_pool *bm_pool, int pool)
3f518509 2869{
20396136 2870 dma_addr_t dma_addr;
4e4a105f 2871 phys_addr_t phys_addr;
0e037281 2872 void *buf;
3f518509 2873
4e4a105f
TP		 2874 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr,
2875 GFP_ATOMIC);
0e037281 2876 if (!buf)
3f518509
MW		 2877 return -ENOMEM;
2878
7d7627ba 2879 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
7ef7e1d9 2880
3f518509
MW		 2881 return 0;
2882}
2883
2884/* Handle tx checksum */
2885static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
2886{
2887 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2888 int ip_hdr_len = 0;
2889 u8 l4_proto;
35f3625c 2890 __be16 l3_proto = vlan_get_protocol(skb);
3f518509 2891
35f3625c 2892 if (l3_proto == htons(ETH_P_IP)) {
3f518509
MW		 2893 struct iphdr *ip4h = ip_hdr(skb);
2894
2895 /* Calculate IPv4 checksum and L4 checksum */
2896 ip_hdr_len = ip4h->ihl;
2897 l4_proto = ip4h->protocol;
35f3625c 2898 } else if (l3_proto == htons(ETH_P_IPV6)) {
3f518509
MW		 2899 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2900
2901 /* Read l4_protocol from one of IPv6 extra headers */
2902 if (skb_network_header_len(skb) > 0)
2903 ip_hdr_len = (skb_network_header_len(skb) >> 2);
2904 l4_proto = ip6h->nexthdr;
2905 } else {
2906 return MVPP2_TXD_L4_CSUM_NOT;
2907 }
2908
2909 return mvpp2_txq_desc_csum(skb_network_offset(skb),
35f3625c 2910 l3_proto, ip_hdr_len, l4_proto);
3f518509
MW		 2911 }
2912
2913 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
2914}
2915
3f518509 2916/* Main rx processing */
591f4cfa
TP		 2917static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
2918 int rx_todo, struct mvpp2_rx_queue *rxq)
3f518509
MW		 2919{
2920 struct net_device *dev = port->dev;
b5015854
MW		 2921 int rx_received;
2922 int rx_done = 0;
3f518509
MW		 2923 u32 rcvd_pkts = 0;
2924 u32 rcvd_bytes = 0;
2925
2926 /* Get number of received packets and clamp the to-do */
2927 rx_received = mvpp2_rxq_received(port, rxq->id);
2928 if (rx_todo > rx_received)
2929 rx_todo = rx_received;
2930
b5015854 2931 while (rx_done < rx_todo) {
3f518509
MW		 2932 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2933 struct mvpp2_bm_pool *bm_pool;
2934 struct sk_buff *skb;
0e037281 2935 unsigned int frag_size;
20396136 2936 dma_addr_t dma_addr;
ac3dd277 2937 phys_addr_t phys_addr;
56b8aae9 2938 u32 rx_status;
3f518509 2939 int pool, rx_bytes, err;
0e037281 2940 void *data;
3f518509 2941
b5015854 2942 rx_done++;
ac3dd277
TP		 2943 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
2944 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
2945 rx_bytes -= MVPP2_MH_SIZE;
2946 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
2947 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
2948 data = (void *)phys_to_virt(phys_addr);
2949
56b8aae9
TP		 2950 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2951 MVPP2_RXD_BM_POOL_ID_OFFS;
3f518509 2952 bm_pool = &port->priv->bm_pools[pool];
3f518509
MW		 2953
2954 /* In case of an error, release the requested buffer pointer
2955 * to the Buffer Manager. This request process is controlled
2956 * by the hardware, and the information about the buffer is
2957 * comprised by the RX descriptor.
2958 */
2959 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
8a52488b 2960err_drop_frame:
3f518509
MW		 2961 dev->stats.rx_errors++;
2962 mvpp2_rx_error(port, rx_desc);
b5015854 2963 /* Return the buffer to the pool */
7d7627ba 2964 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3f518509
MW		 2965 continue;
2966 }
2967
0e037281
TP		 2968 if (bm_pool->frag_size > PAGE_SIZE)
2969 frag_size = 0;
2970 else
2971 frag_size = bm_pool->frag_size;
2972
2973 skb = build_skb(data, frag_size);
2974 if (!skb) {
2975 netdev_warn(port->dev, "skb build failed\n");
2976 goto err_drop_frame;
2977 }
3f518509 2978
56b8aae9 2979 err = mvpp2_rx_refill(port, bm_pool, pool);
b5015854
MW		 2980 if (err) {
2981 netdev_err(port->dev, "failed to refill BM pools\n");
2982 goto err_drop_frame;
2983 }
2984
20396136 2985 dma_unmap_single(dev->dev.parent, dma_addr,
4229d502
MW		 2986 bm_pool->buf_size, DMA_FROM_DEVICE);
2987
3f518509
MW		 2988 rcvd_pkts++;
2989 rcvd_bytes += rx_bytes;
3f518509 2990
0e037281 2991 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD);
3f518509
MW		 2992 skb_put(skb, rx_bytes);
2993 skb->protocol = eth_type_trans(skb, dev);
2994 mvpp2_rx_csum(port, rx_status, skb);
2995
591f4cfa 2996 napi_gro_receive(napi, skb);
3f518509
MW		 2997 }
2998
2999 if (rcvd_pkts) {
3000 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
3001
3002 u64_stats_update_begin(&stats->syncp);
3003 stats->rx_packets += rcvd_pkts;
3004 stats->rx_bytes += rcvd_bytes;
3005 u64_stats_update_end(&stats->syncp);
3006 }
3007
3008 /* Update Rx queue management counters */
3009 wmb();
b5015854 3010 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
3f518509
MW		 3011
3012 return rx_todo;
3013}
3014
3015static inline void
ac3dd277 3016tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
3f518509
MW		 3017 struct mvpp2_tx_desc *desc)
3018{
e531f767 3019 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
074c74df 3020 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
20920267 3021
ac3dd277
TP		 3022 dma_addr_t buf_dma_addr =
3023 mvpp2_txdesc_dma_addr_get(port, desc);
3024 size_t buf_sz =
3025 mvpp2_txdesc_size_get(port, desc);
20920267
AT		 3026 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
3027 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
3028 buf_sz, DMA_TO_DEVICE);
3f518509
MW		 3029 mvpp2_txq_desc_put(txq);
3030}
3031
3032/* Handle tx fragmentation processing */
3033static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
3034 struct mvpp2_tx_queue *aggr_txq,
3035 struct mvpp2_tx_queue *txq)
3036{
e531f767 3037 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
074c74df 3038 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3f518509
MW		 3039 struct mvpp2_tx_desc *tx_desc;
3040 int i;
20396136 3041 dma_addr_t buf_dma_addr;
3f518509
MW		 3042
3043 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3044 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
d7840976 3045 void *addr = skb_frag_address(frag);
3f518509
MW		 3046
3047 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
ac3dd277 3048 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
d7840976 3049 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag));
3f518509 3050
20396136 3051 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
d7840976
MWO		 3052 skb_frag_size(frag),
3053 DMA_TO_DEVICE);
20396136 3054 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
3f518509 3055 mvpp2_txq_desc_put(txq);
32bae631 3056 goto cleanup;
3f518509
MW		 3057 }
3058
6eb5d375 3059 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3f518509
MW		 3060
3061 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
3062 /* Last descriptor */
ac3dd277
TP		 3063 mvpp2_txdesc_cmd_set(port, tx_desc,
3064 MVPP2_TXD_L_DESC);
3065 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3f518509
MW		 3066 } else {
3067 /* Descriptor in the middle: Not First, Not Last */
ac3dd277
TP		 3068 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
3069 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3f518509
MW		 3070 }
3071 }
3072
3073 return 0;
32bae631 3074cleanup:
3f518509
MW		 3075 /* Release all descriptors that were used to map fragments of
3076 * this packet, as well as the corresponding DMA mappings
3077 */
3078 for (i = i - 1; i >= 0; i--) {
3079 tx_desc = txq->descs + i;
ac3dd277 3080 tx_desc_unmap_put(port, txq, tx_desc);
3f518509
MW		 3081 }
3082
3083 return -ENOMEM;
3084}
3085
186cd4d4
AT		 3086static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
3087 struct net_device *dev,
3088 struct mvpp2_tx_queue *txq,
3089 struct mvpp2_tx_queue *aggr_txq,
3090 struct mvpp2_txq_pcpu *txq_pcpu,
3091 int hdr_sz)
3092{
3093 struct mvpp2_port *port = netdev_priv(dev);
3094 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3095 dma_addr_t addr;
3096
3097 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3098 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
3099
3100 addr = txq_pcpu->tso_headers_dma +
3101 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
6eb5d375 3102 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
186cd4d4
AT		 3103
3104 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
3105 MVPP2_TXD_F_DESC |
3106 MVPP2_TXD_PADDING_DISABLE);
3107 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3108}
3109
3110static inline int mvpp2_tso_put_data(struct sk_buff *skb,
3111 struct net_device *dev, struct tso_t *tso,
3112 struct mvpp2_tx_queue *txq,
3113 struct mvpp2_tx_queue *aggr_txq,
3114 struct mvpp2_txq_pcpu *txq_pcpu,
3115 int sz, bool left, bool last)
3116{
3117 struct mvpp2_port *port = netdev_priv(dev);
3118 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3119 dma_addr_t buf_dma_addr;
3120
3121 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3122 mvpp2_txdesc_size_set(port, tx_desc, sz);
3123
3124 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
3125 DMA_TO_DEVICE);
3126 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3127 mvpp2_txq_desc_put(txq);
3128 return -ENOMEM;
3129 }
3130
6eb5d375 3131 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
186cd4d4
AT		 3132
3133 if (!left) {
3134 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
3135 if (last) {
3136 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3137 return 0;
3138 }
3139 } else {
3140 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
3141 }
3142
3143 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3144 return 0;
3145}
3146
3147static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
3148 struct mvpp2_tx_queue *txq,
3149 struct mvpp2_tx_queue *aggr_txq,
3150 struct mvpp2_txq_pcpu *txq_pcpu)
3151{
3152 struct mvpp2_port *port = netdev_priv(dev);
3153 struct tso_t tso;
3154 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb);
3155 int i, len, descs = 0;
3156
3157 /* Check number of available descriptors */
e531f767 3158 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
074c74df 3159 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
186cd4d4
AT		 3160 tso_count_descs(skb)))
3161 return 0;
3162
3163 tso_start(skb, &tso);
3164 len = skb->len - hdr_sz;
3165 while (len > 0) {
3166 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
3167 char *hdr = txq_pcpu->tso_headers +
3168 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
3169
3170 len -= left;
3171 descs++;
3172
3173 tso_build_hdr(skb, hdr, &tso, left, len == 0);
3174 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
3175
3176 while (left > 0) {
3177 int sz = min_t(int, tso.size, left);
3178 left -= sz;
3179 descs++;
3180
3181 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
3182 txq_pcpu, sz, left, len == 0))
3183 goto release;
3184 tso_build_data(skb, &tso, sz);
3185 }
3186 }
3187
3188 return descs;
3189
3190release:
3191 for (i = descs - 1; i >= 0; i--) {
3192 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
3193 tx_desc_unmap_put(port, txq, tx_desc);
3194 }
3195 return 0;
3196}
3197
3f518509 3198/* Main tx processing */
f03508ce 3199static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
3f518509
MW		 3200{
3201 struct mvpp2_port *port = netdev_priv(dev);
3202 struct mvpp2_tx_queue *txq, *aggr_txq;
3203 struct mvpp2_txq_pcpu *txq_pcpu;
3204 struct mvpp2_tx_desc *tx_desc;
20396136 3205 dma_addr_t buf_dma_addr;
e531f767 3206 unsigned long flags = 0;
074c74df 3207 unsigned int thread;
3f518509
MW		 3208 int frags = 0;
3209 u16 txq_id;
3210 u32 tx_cmd;
3211
e531f767 3212 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
074c74df 3213
3f518509
MW		 3214 txq_id = skb_get_queue_mapping(skb);
3215 txq = port->txqs[txq_id];
074c74df
AT		 3216 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3217 aggr_txq = &port->priv->aggr_txqs[thread];
3f518509 3218
e531f767
AT		 3219 if (test_bit(thread, &port->priv->lock_map))
3220 spin_lock_irqsave(&port->tx_lock[thread], flags);
3221
186cd4d4
AT		 3222 if (skb_is_gso(skb)) {
3223 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
3224 goto out;
3225 }
3f518509
MW		 3226 frags = skb_shinfo(skb)->nr_frags + 1;
3227
3228 /* Check number of available descriptors */
e531f767 3229 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
074c74df 3230 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
3f518509
MW		 3231 frags = 0;
3232 goto out;
3233 }
3234
3235 /* Get a descriptor for the first part of the packet */
3236 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
ac3dd277
TP		 3237 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3238 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
3f518509 3239
20396136 3240 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
ac3dd277 3241 skb_headlen(skb), DMA_TO_DEVICE);
20396136 3242 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3f518509
MW		 3243 mvpp2_txq_desc_put(txq);
3244 frags = 0;
3245 goto out;
3246 }
ac3dd277 3247
6eb5d375 3248 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3f518509
MW		 3249
3250 tx_cmd = mvpp2_skb_tx_csum(port, skb);
3251
3252 if (frags == 1) {
3253 /* First and Last descriptor */
3254 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
ac3dd277
TP		 3255 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3256 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3f518509
MW		 3257 } else {
3258 /* First but not Last */
3259 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
ac3dd277
TP		 3260 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3261 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3f518509
MW		 3262
3263 /* Continue with other skb fragments */
3264 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
ac3dd277 3265 tx_desc_unmap_put(port, txq, tx_desc);
3f518509 3266 frags = 0;
3f518509
MW		 3267 }
3268 }
3269
3f518509
MW		 3270out:
3271 if (frags > 0) {
074c74df 3272 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
186cd4d4
AT		 3273 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
3274
3275 txq_pcpu->reserved_num -= frags;
3276 txq_pcpu->count += frags;
3277 aggr_txq->count += frags;
3278
3279 /* Enable transmit */
3280 wmb();
3281 mvpp2_aggr_txq_pend_desc_add(port, frags);
3282
1d17db08 3283 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
186cd4d4 3284 netif_tx_stop_queue(nq);
3f518509
MW		 3285
3286 u64_stats_update_begin(&stats->syncp);
3287 stats->tx_packets++;
3288 stats->tx_bytes += skb->len;
3289 u64_stats_update_end(&stats->syncp);
3290 } else {
3291 dev->stats.tx_dropped++;
3292 dev_kfree_skb_any(skb);
3293 }
3294
edc660fa 3295 /* Finalize TX processing */
082297e6 3296 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
edc660fa
MW		 3297 mvpp2_txq_done(port, txq, txq_pcpu);
3298
3299 /* Set the timer in case not all frags were processed */
213f428f
TP		 3300 if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
3301 txq_pcpu->count > 0) {
074c74df 3302 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
edc660fa 3303
ecb9f80d
TG		 3304 if (!port_pcpu->timer_scheduled) {
3305 port_pcpu->timer_scheduled = true;
3306 hrtimer_start(&port_pcpu->tx_done_timer,
3307 MVPP2_TXDONE_HRTIMER_PERIOD_NS,
3308 HRTIMER_MODE_REL_PINNED_SOFT);
3309 }
edc660fa
MW		 3310 }
3311
e531f767
AT		 3312 if (test_bit(thread, &port->priv->lock_map))
3313 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
3314
3f518509
MW		 3315 return NETDEV_TX_OK;
3316}
3317
3318static inline void mvpp2_cause_error(struct net_device *dev, int cause)
3319{
3320 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
3321 netdev_err(dev, "FCS error\n");
3322 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
3323 netdev_err(dev, "rx fifo overrun error\n");
3324 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
3325 netdev_err(dev, "tx fifo underrun error\n");
3326}
3327
edc660fa 3328static int mvpp2_poll(struct napi_struct *napi, int budget)
3f518509 3329{
213f428f 3330 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
edc660fa
MW		 3331 int rx_done = 0;
3332 struct mvpp2_port *port = netdev_priv(napi->dev);
591f4cfa 3333 struct mvpp2_queue_vector *qv;
e531f767 3334 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3f518509 3335
591f4cfa
TP		 3336 qv = container_of(napi, struct mvpp2_queue_vector, napi);
3337
3f518509
MW		 3338 /* Rx/Tx cause register
3339 *
3340 * Bits 0-15: each bit indicates received packets on the Rx queue
3341 * (bit 0 is for Rx queue 0).
3342 *
3343 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
3344 * (bit 16 is for Tx queue 0).
3345 *
3346 * Each CPU has its own Rx/Tx cause register
3347 */
1068549c 3348 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
cdcfeb0f 3349 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
3f518509 3350
213f428f 3351 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
3f518509
MW		 3352 if (cause_misc) {
3353 mvpp2_cause_error(port->dev, cause_misc);
3354
3355 /* Clear the cause register */
3356 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
1068549c 3357 mvpp2_thread_write(port->priv, thread,
a786841d
TP		 3358 MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
3359 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
3f518509
MW		 3360 }
3361
774268f3
AT		 3362 if (port->has_tx_irqs) {
3363 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3364 if (cause_tx) {
3365 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
3366 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
3367 }
213f428f 3368 }
3f518509
MW		 3369
3370 /* Process RX packets */
70afb58e
AT		 3371 cause_rx = cause_rx_tx &
3372 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
213f428f 3373 cause_rx <<= qv->first_rxq;
591f4cfa 3374 cause_rx |= qv->pending_cause_rx;
3f518509
MW		 3375 while (cause_rx && budget > 0) {
3376 int count;
3377 struct mvpp2_rx_queue *rxq;
3378
3379 rxq = mvpp2_get_rx_queue(port, cause_rx);
3380 if (!rxq)
3381 break;
3382
591f4cfa 3383 count = mvpp2_rx(port, napi, budget, rxq);
3f518509
MW		 3384 rx_done += count;
3385 budget -= count;
3386 if (budget > 0) {
3387 /* Clear the bit associated to this Rx queue
3388 * so that next iteration will continue from
3389 * the next Rx queue.
3390 */
3391 cause_rx &= ~(1 << rxq->logic_rxq);
3392 }
3393 }
3394
3395 if (budget > 0) {
3396 cause_rx = 0;
6ad20165 3397 napi_complete_done(napi, rx_done);
3f518509 3398
591f4cfa 3399 mvpp2_qvec_interrupt_enable(qv);
3f518509 3400 }
591f4cfa 3401 qv->pending_cause_rx = cause_rx;
3f518509
MW		 3402 return rx_done;
3403}
3404
4bb04326 3405static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
3f518509 3406{
4bb04326
AT		 3407 u32 ctrl3;
3408
5434e8fa
AT		 3409 /* Set the GMAC & XLG MAC in reset */
3410 mvpp2_mac_reset_assert(port);
3411
7409e66e
AT		 3412 /* Set the MPCS and XPCS in reset */
3413 mvpp22_pcs_reset_assert(port);
3414
4bb04326
AT		 3415 /* comphy reconfiguration */
3416 mvpp22_comphy_init(port);
3417
3418 /* gop reconfiguration */
3419 mvpp22_gop_init(port);
3420
7409e66e
AT		 3421 mvpp22_pcs_reset_deassert(port);
3422
4bb04326
AT		 3423 /* Only GOP port 0 has an XLG MAC */
3424 if (port->gop_id == 0) {
3425 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
3426 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3427
b7d286f0 3428 if (mvpp2_is_xlg(port->phy_interface))
4bb04326
AT		 3429 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
3430 else
3431 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3432
3433 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
3434 }
8e07269d 3435
b7d286f0 3436 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface))
76eb1b1d
SC		 3437 mvpp2_xlg_max_rx_size_set(port);
3438 else
3439 mvpp2_gmac_max_rx_size_set(port);
4bb04326
AT		 3440}
3441
3442/* Set hw internals when starting port */
3443static void mvpp2_start_dev(struct mvpp2_port *port)
3444{
3445 int i;
76eb1b1d 3446
3f518509
MW		 3447 mvpp2_txp_max_tx_size_set(port);
3448
591f4cfa
TP		 3449 for (i = 0; i < port->nqvecs; i++)
3450 napi_enable(&port->qvecs[i].napi);
3f518509 3451
543ec376 3452 /* Enable interrupts on all threads */
3f518509
MW		 3453 mvpp2_interrupts_enable(port);
3454
4bb04326
AT		 3455 if (port->priv->hw_version == MVPP22)
3456 mvpp22_mode_reconfigure(port);
3457
3458 if (port->phylink) {
3459 phylink_start(port->phylink);
3460 } else {
3461 /* Phylink isn't used as of now for ACPI, so the MAC has to be
3462 * configured manually when the interface is started. This will
3463 * be removed as soon as the phylink ACPI support lands in.
3464 */
3465 struct phylink_link_state state = {
3466 .interface = port->phy_interface,
4bb04326 3467 };
44cc27e4
IC		 3468 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
3469 mvpp2_mac_link_up(&port->phylink_config, MLO_AN_INBAND,
3470 port->phy_interface, NULL);
542897d9 3471 }
f84bf386 3472
3f518509
MW		 3473 netif_tx_start_all_queues(port->dev);
3474}
3475
3476/* Set hw internals when stopping port */
3477static void mvpp2_stop_dev(struct mvpp2_port *port)
3478{
591f4cfa 3479 int i;
8e07269d 3480
543ec376 3481 /* Disable interrupts on all threads */
3f518509
MW		 3482 mvpp2_interrupts_disable(port);
3483
591f4cfa
TP		 3484 for (i = 0; i < port->nqvecs; i++)
3485 napi_disable(&port->qvecs[i].napi);
3f518509 3486
4bb04326
AT		 3487 if (port->phylink)
3488 phylink_stop(port->phylink);
542897d9 3489 phy_power_off(port->comphy);
3f518509
MW		 3490}
3491
3f518509
MW		 3492static int mvpp2_check_ringparam_valid(struct net_device *dev,
3493 struct ethtool_ringparam *ring)
3494{
3495 u16 new_rx_pending = ring->rx_pending;
3496 u16 new_tx_pending = ring->tx_pending;
3497
3498 if (ring->rx_pending == 0 || ring->tx_pending == 0)
3499 return -EINVAL;
3500
7cf87e4a
YM		 3501 if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
3502 new_rx_pending = MVPP2_MAX_RXD_MAX;
3f518509
MW		 3503 else if (!IS_ALIGNED(ring->rx_pending, 16))
3504 new_rx_pending = ALIGN(ring->rx_pending, 16);
3505
7cf87e4a
YM		 3506 if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
3507 new_tx_pending = MVPP2_MAX_TXD_MAX;
3f518509
MW		 3508 else if (!IS_ALIGNED(ring->tx_pending, 32))
3509 new_tx_pending = ALIGN(ring->tx_pending, 32);
3510
76e583c5
AT		 3511 /* The Tx ring size cannot be smaller than the minimum number of
3512 * descriptors needed for TSO.
3513 */
3514 if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
3515 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
3516
3f518509
MW		 3517 if (ring->rx_pending != new_rx_pending) {
3518 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
3519 ring->rx_pending, new_rx_pending);
3520 ring->rx_pending = new_rx_pending;
3521 }
3522
3523 if (ring->tx_pending != new_tx_pending) {
3524 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
3525 ring->tx_pending, new_tx_pending);
3526 ring->tx_pending = new_tx_pending;
3527 }
3528
3529 return 0;
3530}
3531
26975821 3532static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
3f518509
MW		 3533{
3534 u32 mac_addr_l, mac_addr_m, mac_addr_h;
3535
3536 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3537 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
3538 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
3539 addr[0] = (mac_addr_h >> 24) & 0xFF;
3540 addr[1] = (mac_addr_h >> 16) & 0xFF;
3541 addr[2] = (mac_addr_h >> 8) & 0xFF;
3542 addr[3] = mac_addr_h & 0xFF;
3543 addr[4] = mac_addr_m & 0xFF;
3544 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
3545}
3546
591f4cfa
TP		 3547static int mvpp2_irqs_init(struct mvpp2_port *port)
3548{
3549 int err, i;
3550
3551 for (i = 0; i < port->nqvecs; i++) {
3552 struct mvpp2_queue_vector *qv = port->qvecs + i;
3553
a6b3a3fa
MZ		 3554 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
3555 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
3556 if (!qv->mask) {
3557 err = -ENOMEM;
3558 goto err;
3559 }
3560
13c249a9 3561 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
a6b3a3fa 3562 }
13c249a9 3563
591f4cfa
TP		 3564 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
3565 if (err)
3566 goto err;
213f428f 3567
e531f767 3568 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
e531f767
AT		 3569 unsigned int cpu;
3570
3571 for_each_present_cpu(cpu) {
3572 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
3573 qv->sw_thread_id)
a6b3a3fa 3574 cpumask_set_cpu(cpu, qv->mask);
e531f767
AT		 3575 }
3576
a6b3a3fa 3577 irq_set_affinity_hint(qv->irq, qv->mask);
e531f767 3578 }
591f4cfa
TP		 3579 }
3580
3581 return 0;
3582err:
3583 for (i = 0; i < port->nqvecs; i++) {
3584 struct mvpp2_queue_vector *qv = port->qvecs + i;
3585
213f428f 3586 irq_set_affinity_hint(qv->irq, NULL);
a6b3a3fa
MZ		 3587 kfree(qv->mask);
3588 qv->mask = NULL;
591f4cfa
TP		 3589 free_irq(qv->irq, qv);
3590 }
3591
3592 return err;
3593}
3594
3595static void mvpp2_irqs_deinit(struct mvpp2_port *port)
3596{
3597 int i;
3598
3599 for (i = 0; i < port->nqvecs; i++) {
3600 struct mvpp2_queue_vector *qv = port->qvecs + i;
3601
213f428f 3602 irq_set_affinity_hint(qv->irq, NULL);
a6b3a3fa
MZ		 3603 kfree(qv->mask);
3604 qv->mask = NULL;
13c249a9 3605 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
591f4cfa
TP		 3606 free_irq(qv->irq, qv);
3607 }
3608}
3609
4c4a5686
YM		 3610static bool mvpp22_rss_is_supported(void)
3611{
3612 return queue_mode == MVPP2_QDIST_MULTI_MODE;
3613}
3614
3f518509
MW		 3615static int mvpp2_open(struct net_device *dev)
3616{
3617 struct mvpp2_port *port = netdev_priv(dev);
fd3651b2 3618 struct mvpp2 *priv = port->priv;
3f518509
MW		 3619 unsigned char mac_bcast[ETH_ALEN] = {
3620 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4bb04326 3621 bool valid = false;
3f518509
MW		 3622 int err;
3623
ce2a27c7 3624 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
3f518509
MW		 3625 if (err) {
3626 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3627 return err;
3628 }
ce2a27c7 3629 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
3f518509 3630 if (err) {
ce2a27c7 3631 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
3f518509
MW		 3632 return err;
3633 }
3634 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
3635 if (err) {
3636 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
3637 return err;
3638 }
3639 err = mvpp2_prs_def_flow(port);
3640 if (err) {
3641 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3642 return err;
3643 }
3644
3645 /* Allocate the Rx/Tx queues */
3646 err = mvpp2_setup_rxqs(port);
3647 if (err) {
3648 netdev_err(port->dev, "cannot allocate Rx queues\n");
3649 return err;
3650 }
3651
3652 err = mvpp2_setup_txqs(port);
3653 if (err) {
3654 netdev_err(port->dev, "cannot allocate Tx queues\n");
3655 goto err_cleanup_rxqs;
3656 }
3657
591f4cfa 3658 err = mvpp2_irqs_init(port);
3f518509 3659 if (err) {
591f4cfa 3660 netdev_err(port->dev, "cannot init IRQs\n");
3f518509
MW		 3661 goto err_cleanup_txqs;
3662 }
3663
4bb04326
AT		 3664 /* Phylink isn't supported yet in ACPI mode */
3665 if (port->of_node) {
3666 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
3667 if (err) {
3668 netdev_err(port->dev, "could not attach PHY (%d)\n",
3669 err);
3670 goto err_free_irq;
3671 }
3672
3673 valid = true;
3674 }
3675
3676 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) {
fd3651b2
AT		 3677 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
3678 dev->name, port);
3679 if (err) {
3680 netdev_err(port->dev, "cannot request link IRQ %d\n",
3681 port->link_irq);
3682 goto err_free_irq;
3683 }
3684
3685 mvpp22_gop_setup_irq(port);
fd3651b2 3686
4bb04326
AT		 3687 /* In default link is down */
3688 netif_carrier_off(port->dev);
3f518509 3689
4bb04326
AT		 3690 valid = true;
3691 } else {
3692 port->link_irq = 0;
3693 }
3694
3695 if (!valid) {
3696 netdev_err(port->dev,
3697 "invalid configuration: no dt or link IRQ");
3698 goto err_free_irq;
3699 }
3f518509
MW		 3700
3701 /* Unmask interrupts on all CPUs */
3702 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
213f428f 3703 mvpp2_shared_interrupt_mask_unmask(port, false);
3f518509
MW		 3704
3705 mvpp2_start_dev(port);
3706
118d6298 3707 /* Start hardware statistics gathering */
e5c500eb 3708 queue_delayed_work(priv->stats_queue, &port->stats_work,
118d6298
MR		 3709 MVPP2_MIB_COUNTERS_STATS_DELAY);
3710
3f518509
MW		 3711 return 0;
3712
3713err_free_irq:
591f4cfa 3714 mvpp2_irqs_deinit(port);
3f518509
MW		 3715err_cleanup_txqs:
3716 mvpp2_cleanup_txqs(port);
3717err_cleanup_rxqs:
3718 mvpp2_cleanup_rxqs(port);
3719 return err;
3720}
3721
3722static int mvpp2_stop(struct net_device *dev)
3723{
3724 struct mvpp2_port *port = netdev_priv(dev);
edc660fa 3725 struct mvpp2_port_pcpu *port_pcpu;
074c74df 3726 unsigned int thread;
3f518509
MW		 3727
3728 mvpp2_stop_dev(port);
3f518509 3729
e531f767 3730 /* Mask interrupts on all threads */
3f518509 3731 on_each_cpu(mvpp2_interrupts_mask, port, 1);
213f428f 3732 mvpp2_shared_interrupt_mask_unmask(port, true);
3f518509 3733
4bb04326
AT		 3734 if (port->phylink)
3735 phylink_disconnect_phy(port->phylink);
3736 if (port->link_irq)
fd3651b2
AT		 3737 free_irq(port->link_irq, port);
3738
591f4cfa 3739 mvpp2_irqs_deinit(port);
213f428f 3740 if (!port->has_tx_irqs) {
e531f767 3741 for (thread = 0; thread < port->priv->nthreads; thread++) {
074c74df 3742 port_pcpu = per_cpu_ptr(port->pcpu, thread);
edc660fa 3743
213f428f
TP		 3744 hrtimer_cancel(&port_pcpu->tx_done_timer);
3745 port_pcpu->timer_scheduled = false;
213f428f 3746 }
edc660fa 3747 }
3f518509
MW		 3748 mvpp2_cleanup_rxqs(port);
3749 mvpp2_cleanup_txqs(port);
3750
e5c500eb 3751 cancel_delayed_work_sync(&port->stats_work);
118d6298 3752
1f69afce
AT		 3753 mvpp2_mac_reset_assert(port);
3754 mvpp22_pcs_reset_assert(port);
3755
3f518509
MW		 3756 return 0;
3757}
3758
10fea26c
MC		 3759static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
3760 struct netdev_hw_addr_list *list)
3f518509 3761{
3f518509 3762 struct netdev_hw_addr *ha;
10fea26c
MC		 3763 int ret;
3764
3765 netdev_hw_addr_list_for_each(ha, list) {
3766 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
3767 if (ret)
3768 return ret;
3f518509 3769 }
56beda3d 3770
10fea26c
MC		 3771 return 0;
3772}
3773
3774static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
3775{
3776 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
56beda3d 3777 mvpp2_prs_vid_enable_filtering(port);
10fea26c
MC		 3778 else
3779 mvpp2_prs_vid_disable_filtering(port);
3780
3781 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3782 MVPP2_PRS_L2_UNI_CAST, enable);
3783
3784 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3785 MVPP2_PRS_L2_MULTI_CAST, enable);
3786}
3787
3788static void mvpp2_set_rx_mode(struct net_device *dev)
3789{
3790 struct mvpp2_port *port = netdev_priv(dev);
3791
3792 /* Clear the whole UC and MC list */
3793 mvpp2_prs_mac_del_all(port);
3794
3795 if (dev->flags & IFF_PROMISC) {
3796 mvpp2_set_rx_promisc(port, true);
3797 return;
3798 }
3799
3800 mvpp2_set_rx_promisc(port, false);
3801
3802 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
3803 mvpp2_prs_mac_da_accept_list(port, &dev->uc))
3804 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3805 MVPP2_PRS_L2_UNI_CAST, true);
3806
3807 if (dev->flags & IFF_ALLMULTI) {
3808 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3809 MVPP2_PRS_L2_MULTI_CAST, true);
3810 return;
3811 }
3812
3813 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
3814 mvpp2_prs_mac_da_accept_list(port, &dev->mc))
3815 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3816 MVPP2_PRS_L2_MULTI_CAST, true);
3f518509
MW		 3817}
3818
3819static int mvpp2_set_mac_address(struct net_device *dev, void *p)
3820{
3f518509
MW		 3821 const struct sockaddr *addr = p;
3822 int err;
3823
5b0ab2f4
YM		 3824 if (!is_valid_ether_addr(addr->sa_data))
3825 return -EADDRNOTAVAIL;
3f518509
MW		 3826
3827 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
5b0ab2f4
YM		 3828 if (err) {
3829 /* Reconfigure parser accept the original MAC address */
3830 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
3831 netdev_err(dev, "failed to change MAC address\n");
3832 }
3f518509
MW		 3833 return err;
3834}
3835
7d04b0b1
MC		 3836/* Shut down all the ports, reconfigure the pools as percpu or shared,
3837 * then bring up again all ports.
3838 */
3839static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu)
3840{
3841 int numbufs = MVPP2_BM_POOLS_NUM, i;
3842 struct mvpp2_port *port = NULL;
3843 bool status[MVPP2_MAX_PORTS];
3844
3845 for (i = 0; i < priv->port_count; i++) {
3846 port = priv->port_list[i];
3847 status[i] = netif_running(port->dev);
3848 if (status[i])
3849 mvpp2_stop(port->dev);
3850 }
3851
3852 /* nrxqs is the same for all ports */
3853 if (priv->percpu_pools)
3854 numbufs = port->nrxqs * 2;
3855
3856 for (i = 0; i < numbufs; i++)
3857 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]);
3858
3859 devm_kfree(port->dev->dev.parent, priv->bm_pools);
3860 priv->percpu_pools = percpu;
3861 mvpp2_bm_init(port->dev->dev.parent, priv);
3862
3863 for (i = 0; i < priv->port_count; i++) {
3864 port = priv->port_list[i];
3865 mvpp2_swf_bm_pool_init(port);
3866 if (status[i])
3867 mvpp2_open(port->dev);
3868 }
3869
3870 return 0;
3871}
3872
3f518509
MW		 3873static int mvpp2_change_mtu(struct net_device *dev, int mtu)
3874{
3875 struct mvpp2_port *port = netdev_priv(dev);
230bd958 3876 bool running = netif_running(dev);
7d04b0b1 3877 struct mvpp2 *priv = port->priv;
3f518509
MW		 3878 int err;
3879
5777987e
JW		 3880 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
3881 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
3882 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
3883 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
3f518509
MW		 3884 }
3885
7d04b0b1
MC		 3886 if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) {
3887 if (priv->percpu_pools) {
3888 netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu);
3889 mvpp2_bm_switch_buffers(priv, false);
3890 }
3891 } else {
3892 bool jumbo = false;
3893 int i;
3894
3895 for (i = 0; i < priv->port_count; i++)
3896 if (priv->port_list[i] != port &&
3897 MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) >
3898 MVPP2_BM_LONG_PKT_SIZE) {
3899 jumbo = true;
3900 break;
3901 }
3902
3903 /* No port is using jumbo frames */
3904 if (!jumbo) {
3905 dev_info(port->dev->dev.parent,
3906 "all ports have a low MTU, switching to per-cpu buffers");
3907 mvpp2_bm_switch_buffers(priv, true);
3908 }
3909 }
3910
230bd958
MC		 3911 if (running)
3912 mvpp2_stop_dev(port);
3f518509
MW		 3913
3914 err = mvpp2_bm_update_mtu(dev, mtu);
230bd958
MC		 3915 if (err) {
3916 netdev_err(dev, "failed to change MTU\n");
3917 /* Reconfigure BM to the original MTU */
3918 mvpp2_bm_update_mtu(dev, dev->mtu);
3919 } else {
3f518509 3920 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3f518509
MW		 3921 }
3922
230bd958
MC		 3923 if (running) {
3924 mvpp2_start_dev(port);
3925 mvpp2_egress_enable(port);
3926 mvpp2_ingress_enable(port);
3927 }
3f518509 3928
3f518509
MW		 3929 return err;
3930}
3931
bc1f4470 3932static void
3f518509
MW		 3933mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
3934{
3935 struct mvpp2_port *port = netdev_priv(dev);
3936 unsigned int start;
850623b3 3937 unsigned int cpu;
3f518509
MW		 3938
3939 for_each_possible_cpu(cpu) {
3940 struct mvpp2_pcpu_stats *cpu_stats;
3941 u64 rx_packets;
3942 u64 rx_bytes;
3943 u64 tx_packets;
3944 u64 tx_bytes;
3945
3946 cpu_stats = per_cpu_ptr(port->stats, cpu);
3947 do {
3948 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
3949 rx_packets = cpu_stats->rx_packets;
3950 rx_bytes = cpu_stats->rx_bytes;
3951 tx_packets = cpu_stats->tx_packets;
3952 tx_bytes = cpu_stats->tx_bytes;
3953 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
3954
3955 stats->rx_packets += rx_packets;
3956 stats->rx_bytes += rx_bytes;
3957 stats->tx_packets += tx_packets;
3958 stats->tx_bytes += tx_bytes;
3959 }
3960
3961 stats->rx_errors = dev->stats.rx_errors;
3962 stats->rx_dropped = dev->stats.rx_dropped;
3963 stats->tx_dropped = dev->stats.tx_dropped;
3f518509
MW		 3964}
3965
bd695a5f
TP		 3966static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3967{
4bb04326 3968 struct mvpp2_port *port = netdev_priv(dev);
bd695a5f 3969
4bb04326 3970 if (!port->phylink)
bd695a5f
TP		 3971 return -ENOTSUPP;
3972
4bb04326 3973 return phylink_mii_ioctl(port->phylink, ifr, cmd);
bd695a5f
TP		 3974}
3975
56beda3d
MC		 3976static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
3977{
3978 struct mvpp2_port *port = netdev_priv(dev);
3979 int ret;
3980
3981 ret = mvpp2_prs_vid_entry_add(port, vid);
3982 if (ret)
3983 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
3984 MVPP2_PRS_VLAN_FILT_MAX - 1);
3985 return ret;
3986}
3987
3988static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
3989{
3990 struct mvpp2_port *port = netdev_priv(dev);
3991
3992 mvpp2_prs_vid_entry_remove(port, vid);
3993 return 0;
3994}
3995
3996static int mvpp2_set_features(struct net_device *dev,
3997 netdev_features_t features)
3998{
3999 netdev_features_t changed = dev->features ^ features;
4000 struct mvpp2_port *port = netdev_priv(dev);
4001
4002 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
4003 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
4004 mvpp2_prs_vid_enable_filtering(port);
4005 } else {
4006 /* Invalidate all registered VID filters for this
4007 * port
4008 */
4009 mvpp2_prs_vid_remove_all(port);
4010
4011 mvpp2_prs_vid_disable_filtering(port);
4012 }
4013 }
4014
d33ec452
MC		 4015 if (changed & NETIF_F_RXHASH) {
4016 if (features & NETIF_F_RXHASH)
6310f77d 4017 mvpp22_port_rss_enable(port);
d33ec452 4018 else
6310f77d 4019 mvpp22_port_rss_disable(port);
d33ec452
MC		 4020 }
4021
56beda3d
MC		 4022 return 0;
4023}
4024
3f518509
MW		 4025/* Ethtool methods */
4026
4bb04326
AT		 4027static int mvpp2_ethtool_nway_reset(struct net_device *dev)
4028{
4029 struct mvpp2_port *port = netdev_priv(dev);
4030
4031 if (!port->phylink)
4032 return -ENOTSUPP;
4033
4034 return phylink_ethtool_nway_reset(port->phylink);
4035}
4036
3f518509
MW		 4037/* Set interrupt coalescing for ethtools */
4038static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
4039 struct ethtool_coalesce *c)
4040{
4041 struct mvpp2_port *port = netdev_priv(dev);
4042 int queue;
4043
09f83975 4044 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 4045 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4046
4047 rxq->time_coal = c->rx_coalesce_usecs;
4048 rxq->pkts_coal = c->rx_max_coalesced_frames;
d63f9e41
TP		 4049 mvpp2_rx_pkts_coal_set(port, rxq);
4050 mvpp2_rx_time_coal_set(port, rxq);
3f518509
MW		 4051 }
4052
213f428f
TP		 4053 if (port->has_tx_irqs) {
4054 port->tx_time_coal = c->tx_coalesce_usecs;
4055 mvpp2_tx_time_coal_set(port);
4056 }
4057
09f83975 4058 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 4059 struct mvpp2_tx_queue *txq = port->txqs[queue];
4060
4061 txq->done_pkts_coal = c->tx_max_coalesced_frames;
213f428f
TP		 4062
4063 if (port->has_tx_irqs)
4064 mvpp2_tx_pkts_coal_set(port, txq);
3f518509
MW		 4065 }
4066
3f518509
MW		 4067 return 0;
4068}
4069
4070/* get coalescing for ethtools */
4071static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
4072 struct ethtool_coalesce *c)
4073{
4074 struct mvpp2_port *port = netdev_priv(dev);
4075
385c284f
AT		 4076 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
4077 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
4078 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
24b28ccb 4079 c->tx_coalesce_usecs = port->tx_time_coal;
3f518509
MW		 4080 return 0;
4081}
4082
4083static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
4084 struct ethtool_drvinfo *drvinfo)
4085{
4086 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
4087 sizeof(drvinfo->driver));
4088 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
4089 sizeof(drvinfo->version));
4090 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
4091 sizeof(drvinfo->bus_info));
4092}
4093
4094static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
4095 struct ethtool_ringparam *ring)
4096{
4097 struct mvpp2_port *port = netdev_priv(dev);
4098
7cf87e4a
YM		 4099 ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
4100 ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
3f518509
MW		 4101 ring->rx_pending = port->rx_ring_size;
4102 ring->tx_pending = port->tx_ring_size;
4103}
4104
4105static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
4106 struct ethtool_ringparam *ring)
4107{
4108 struct mvpp2_port *port = netdev_priv(dev);
4109 u16 prev_rx_ring_size = port->rx_ring_size;
4110 u16 prev_tx_ring_size = port->tx_ring_size;
4111 int err;
4112
4113 err = mvpp2_check_ringparam_valid(dev, ring);
4114 if (err)
4115 return err;
4116
4117 if (!netif_running(dev)) {
4118 port->rx_ring_size = ring->rx_pending;
4119 port->tx_ring_size = ring->tx_pending;
4120 return 0;
4121 }
4122
4123 /* The interface is running, so we have to force a
4124 * reallocation of the queues
4125 */
4126 mvpp2_stop_dev(port);
4127 mvpp2_cleanup_rxqs(port);
4128 mvpp2_cleanup_txqs(port);
4129
4130 port->rx_ring_size = ring->rx_pending;
4131 port->tx_ring_size = ring->tx_pending;
4132
4133 err = mvpp2_setup_rxqs(port);
4134 if (err) {
4135 /* Reallocate Rx queues with the original ring size */
4136 port->rx_ring_size = prev_rx_ring_size;
4137 ring->rx_pending = prev_rx_ring_size;
4138 err = mvpp2_setup_rxqs(port);
4139 if (err)
4140 goto err_out;
4141 }
4142 err = mvpp2_setup_txqs(port);
4143 if (err) {
4144 /* Reallocate Tx queues with the original ring size */
4145 port->tx_ring_size = prev_tx_ring_size;
4146 ring->tx_pending = prev_tx_ring_size;
4147 err = mvpp2_setup_txqs(port);
4148 if (err)
4149 goto err_clean_rxqs;
4150 }
4151
4152 mvpp2_start_dev(port);
4153 mvpp2_egress_enable(port);
4154 mvpp2_ingress_enable(port);
4155
4156 return 0;
4157
4158err_clean_rxqs:
4159 mvpp2_cleanup_rxqs(port);
4160err_out:
dfd4240a 4161 netdev_err(dev, "failed to change ring parameters");
3f518509
MW		 4162 return err;
4163}
4164
4bb04326
AT		 4165static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
4166 struct ethtool_pauseparam *pause)
4167{
4168 struct mvpp2_port *port = netdev_priv(dev);
4169
4170 if (!port->phylink)
4171 return;
4172
4173 phylink_ethtool_get_pauseparam(port->phylink, pause);
4174}
4175
4176static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
4177 struct ethtool_pauseparam *pause)
4178{
4179 struct mvpp2_port *port = netdev_priv(dev);
4180
4181 if (!port->phylink)
4182 return -ENOTSUPP;
4183
4184 return phylink_ethtool_set_pauseparam(port->phylink, pause);
4185}
4186
4187static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
4188 struct ethtool_link_ksettings *cmd)
4189{
4190 struct mvpp2_port *port = netdev_priv(dev);
4191
4192 if (!port->phylink)
4193 return -ENOTSUPP;
4194
4195 return phylink_ethtool_ksettings_get(port->phylink, cmd);
4196}
4197
4198static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
4199 const struct ethtool_link_ksettings *cmd)
4200{
4201 struct mvpp2_port *port = netdev_priv(dev);
4202
4203 if (!port->phylink)
4204 return -ENOTSUPP;
4205
4206 return phylink_ethtool_ksettings_set(port->phylink, cmd);
4207}
4208
8179642b
AT		 4209static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
4210 struct ethtool_rxnfc *info, u32 *rules)
4211{
4212 struct mvpp2_port *port = netdev_priv(dev);
90b509b3 4213 int ret = 0, i, loc = 0;
8179642b
AT		 4214
4215 if (!mvpp22_rss_is_supported())
4216 return -EOPNOTSUPP;
4217
4218 switch (info->cmd) {
436d4fdb
MC		 4219 case ETHTOOL_GRXFH:
4220 ret = mvpp2_ethtool_rxfh_get(port, info);
4221 break;
8179642b
AT		 4222 case ETHTOOL_GRXRINGS:
4223 info->data = port->nrxqs;
4224 break;
90b509b3
MC		 4225 case ETHTOOL_GRXCLSRLCNT:
4226 info->rule_cnt = port->n_rfs_rules;
4227 break;
4228 case ETHTOOL_GRXCLSRULE:
4229 ret = mvpp2_ethtool_cls_rule_get(port, info);
4230 break;
4231 case ETHTOOL_GRXCLSRLALL:
ae8e1d5e 4232 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) {
90b509b3
MC		 4233 if (port->rfs_rules[i])
4234 rules[loc++] = i;
4235 }
4236 break;
8179642b
AT		 4237 default:
4238 return -ENOTSUPP;
4239 }
4240
436d4fdb
MC		 4241 return ret;
4242}
4243
4244static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
4245 struct ethtool_rxnfc *info)
4246{
4247 struct mvpp2_port *port = netdev_priv(dev);
4248 int ret = 0;
4249
4250 if (!mvpp22_rss_is_supported())
4251 return -EOPNOTSUPP;
4252
4253 switch (info->cmd) {
4254 case ETHTOOL_SRXFH:
4255 ret = mvpp2_ethtool_rxfh_set(port, info);
4256 break;
90b509b3
MC		 4257 case ETHTOOL_SRXCLSRLINS:
4258 ret = mvpp2_ethtool_cls_rule_ins(port, info);
4259 break;
4260 case ETHTOOL_SRXCLSRLDEL:
4261 ret = mvpp2_ethtool_cls_rule_del(port, info);
4262 break;
436d4fdb
MC		 4263 default:
4264 return -EOPNOTSUPP;
4265 }
4266 return ret;
8179642b
AT		 4267}
4268
4269static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
4270{
4271 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0;
4272}
4273
4274static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
4275 u8 *hfunc)
4276{
4277 struct mvpp2_port *port = netdev_priv(dev);
895586d5 4278 int ret = 0;
8179642b
AT		 4279
4280 if (!mvpp22_rss_is_supported())
4281 return -EOPNOTSUPP;
4282
4283 if (indir)
895586d5 4284 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir);
8179642b
AT		 4285
4286 if (hfunc)
4287 *hfunc = ETH_RSS_HASH_CRC32;
4288
895586d5 4289 return ret;
8179642b
AT		 4290}
4291
4292static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
4293 const u8 *key, const u8 hfunc)
4294{
4295 struct mvpp2_port *port = netdev_priv(dev);
895586d5 4296 int ret = 0;
8179642b
AT		 4297
4298 if (!mvpp22_rss_is_supported())
4299 return -EOPNOTSUPP;
4300
4301 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
4302 return -EOPNOTSUPP;
4303
4304 if (key)
4305 return -EOPNOTSUPP;
4306
895586d5
MC		 4307 if (indir)
4308 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir);
8179642b 4309
895586d5 4310 return ret;
8179642b
AT		 4311}
4312
895586d5
MC		 4313static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,
4314 u8 *key, u8 *hfunc, u32 rss_context)
4315{
4316 struct mvpp2_port *port = netdev_priv(dev);
4317 int ret = 0;
4318
4319 if (!mvpp22_rss_is_supported())
4320 return -EOPNOTSUPP;
4321
4322 if (hfunc)
4323 *hfunc = ETH_RSS_HASH_CRC32;
4324
4325 if (indir)
4326 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir);
4327
4328 return ret;
4329}
4330
4331static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,
4332 const u32 *indir, const u8 *key,
4333 const u8 hfunc, u32 *rss_context,
4334 bool delete)
4335{
4336 struct mvpp2_port *port = netdev_priv(dev);
4337 int ret;
4338
4339 if (!mvpp22_rss_is_supported())
4340 return -EOPNOTSUPP;
4341
4342 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
4343 return -EOPNOTSUPP;
4344
4345 if (key)
4346 return -EOPNOTSUPP;
4347
4348 if (delete)
4349 return mvpp22_port_rss_ctx_delete(port, *rss_context);
4350
4351 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
4352 ret = mvpp22_port_rss_ctx_create(port, rss_context);
4353 if (ret)
4354 return ret;
4355 }
4356
4357 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir);
4358}
3f518509
MW		 4359/* Device ops */
4360
4361static const struct net_device_ops mvpp2_netdev_ops = {
4362 .ndo_open = mvpp2_open,
4363 .ndo_stop = mvpp2_stop,
4364 .ndo_start_xmit = mvpp2_tx,
4365 .ndo_set_rx_mode = mvpp2_set_rx_mode,
4366 .ndo_set_mac_address = mvpp2_set_mac_address,
4367 .ndo_change_mtu = mvpp2_change_mtu,
4368 .ndo_get_stats64 = mvpp2_get_stats64,
bd695a5f 4369 .ndo_do_ioctl = mvpp2_ioctl,
56beda3d
MC		 4370 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid,
4371 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid,
4372 .ndo_set_features = mvpp2_set_features,
3f518509
MW		 4373};
4374
4375static const struct ethtool_ops mvpp2_eth_tool_ops = {
4bb04326 4376 .nway_reset = mvpp2_ethtool_nway_reset,
dcd3e73a
AT		 4377 .get_link = ethtool_op_get_link,
4378 .set_coalesce = mvpp2_ethtool_set_coalesce,
4379 .get_coalesce = mvpp2_ethtool_get_coalesce,
4380 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
4381 .get_ringparam = mvpp2_ethtool_get_ringparam,
4382 .set_ringparam = mvpp2_ethtool_set_ringparam,
4383 .get_strings = mvpp2_ethtool_get_strings,
4384 .get_ethtool_stats = mvpp2_ethtool_get_stats,
4385 .get_sset_count = mvpp2_ethtool_get_sset_count,
4bb04326
AT		 4386 .get_pauseparam = mvpp2_ethtool_get_pause_param,
4387 .set_pauseparam = mvpp2_ethtool_set_pause_param,
4388 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings,
4389 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings,
8179642b 4390 .get_rxnfc = mvpp2_ethtool_get_rxnfc,
436d4fdb 4391 .set_rxnfc = mvpp2_ethtool_set_rxnfc,
8179642b
AT		 4392 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size,
4393 .get_rxfh = mvpp2_ethtool_get_rxfh,
4394 .set_rxfh = mvpp2_ethtool_set_rxfh,
895586d5
MC		 4395 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context,
4396 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context,
3f518509
MW		 4397};
4398
213f428f
TP		 4399/* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
4400 * had a single IRQ defined per-port.
4401 */
4402static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
4403 struct device_node *port_node)
591f4cfa
TP		 4404{
4405 struct mvpp2_queue_vector *v = &port->qvecs[0];
4406
4407 v->first_rxq = 0;
4408 v->nrxqs = port->nrxqs;
4409 v->type = MVPP2_QUEUE_VECTOR_SHARED;
4410 v->sw_thread_id = 0;
4411 v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
4412 v->port = port;
4413 v->irq = irq_of_parse_and_map(port_node, 0);
4414 if (v->irq <= 0)
4415 return -EINVAL;
4416 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4417 NAPI_POLL_WEIGHT);
4418
4419 port->nqvecs = 1;
4420
4421 return 0;
4422}
4423
213f428f
TP		 4424static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
4425 struct device_node *port_node)
4426{
e531f767 4427 struct mvpp2 *priv = port->priv;
213f428f
TP		 4428 struct mvpp2_queue_vector *v;
4429 int i, ret;
4430
e531f767
AT		 4431 switch (queue_mode) {
4432 case MVPP2_QDIST_SINGLE_MODE:
4433 port->nqvecs = priv->nthreads + 1;
4434 break;
4435 case MVPP2_QDIST_MULTI_MODE:
4436 port->nqvecs = priv->nthreads;
4437 break;
4438 }
213f428f
TP		 4439
4440 for (i = 0; i < port->nqvecs; i++) {
4441 char irqname[16];
4442
4443 v = port->qvecs + i;
4444
4445 v->port = port;
4446 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
4447 v->sw_thread_id = i;
4448 v->sw_thread_mask = BIT(i);
4449
a9aac385
AT		 4450 if (port->flags & MVPP2_F_DT_COMPAT)
4451 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
4452 else
4453 snprintf(irqname, sizeof(irqname), "hif%d", i);
213f428f
TP		 4454
4455 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
3f136849
AT		 4456 v->first_rxq = i;
4457 v->nrxqs = 1;
213f428f
TP		 4458 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
4459 i == (port->nqvecs - 1)) {
4460 v->first_rxq = 0;
4461 v->nrxqs = port->nrxqs;
4462 v->type = MVPP2_QUEUE_VECTOR_SHARED;
a9aac385
AT		 4463
4464 if (port->flags & MVPP2_F_DT_COMPAT)
4465 strncpy(irqname, "rx-shared", sizeof(irqname));
213f428f
TP		 4466 }
4467
a75edc7c
MW		 4468 if (port_node)
4469 v->irq = of_irq_get_byname(port_node, irqname);
4470 else
4471 v->irq = fwnode_irq_get(port->fwnode, i);
213f428f
TP		 4472 if (v->irq <= 0) {
4473 ret = -EINVAL;
4474 goto err;
4475 }
4476
4477 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4478 NAPI_POLL_WEIGHT);
4479 }
4480
4481 return 0;
4482
4483err:
4484 for (i = 0; i < port->nqvecs; i++)
4485 irq_dispose_mapping(port->qvecs[i].irq);
4486 return ret;
4487}
4488
4489static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
4490 struct device_node *port_node)
4491{
4492 if (port->has_tx_irqs)
4493 return mvpp2_multi_queue_vectors_init(port, port_node);
4494 else
4495 return mvpp2_simple_queue_vectors_init(port, port_node);
4496}
4497
591f4cfa
TP		 4498static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
4499{
4500 int i;
4501
4502 for (i = 0; i < port->nqvecs; i++)
4503 irq_dispose_mapping(port->qvecs[i].irq);
4504}
4505
4506/* Configure Rx queue group interrupt for this port */
4507static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
4508{
4509 struct mvpp2 *priv = port->priv;
4510 u32 val;
4511 int i;
4512
4513 if (priv->hw_version == MVPP21) {
4514 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4515 port->nrxqs);
4516 return;
4517 }
4518
4519 /* Handle the more complicated PPv2.2 case */
4520 for (i = 0; i < port->nqvecs; i++) {
4521 struct mvpp2_queue_vector *qv = port->qvecs + i;
4522
4523 if (!qv->nrxqs)
4524 continue;
4525
4526 val = qv->sw_thread_id;
4527 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
4528 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4529
4530 val = qv->first_rxq;
4531 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
4532 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4533 }
4534}
4535
3f518509
MW		 4536/* Initialize port HW */
4537static int mvpp2_port_init(struct mvpp2_port *port)
4538{
4539 struct device *dev = port->dev->dev.parent;
4540 struct mvpp2 *priv = port->priv;
4541 struct mvpp2_txq_pcpu *txq_pcpu;
074c74df 4542 unsigned int thread;
9bea6897 4543 int queue, err;
3f518509 4544
09f83975
TP		 4545 /* Checks for hardware constraints */
4546 if (port->first_rxq + port->nrxqs >
59b9a31e 4547 MVPP2_MAX_PORTS * priv->max_port_rxqs)
3f518509
MW		 4548 return -EINVAL;
4549
3f136849 4550 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
09f83975
TP		 4551 return -EINVAL;
4552
3f518509
MW		 4553 /* Disable port */
4554 mvpp2_egress_disable(port);
4555 mvpp2_port_disable(port);
4556
213f428f
TP		 4557 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
4558
09f83975 4559 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
3f518509
MW		 4560 GFP_KERNEL);
4561 if (!port->txqs)
4562 return -ENOMEM;
4563
4564 /* Associate physical Tx queues to this port and initialize.
4565 * The mapping is predefined.
4566 */
09f83975 4567 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 4568 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4569 struct mvpp2_tx_queue *txq;
4570
4571 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
177c8d1c
CJ		 4572 if (!txq) {
4573 err = -ENOMEM;
4574 goto err_free_percpu;
4575 }
3f518509
MW		 4576
4577 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
4578 if (!txq->pcpu) {
4579 err = -ENOMEM;
4580 goto err_free_percpu;
4581 }
4582
4583 txq->id = queue_phy_id;
4584 txq->log_id = queue;
4585 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
e531f767 4586 for (thread = 0; thread < priv->nthreads; thread++) {
074c74df
AT		 4587 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4588 txq_pcpu->thread = thread;
3f518509
MW		 4589 }
4590
4591 port->txqs[queue] = txq;
4592 }
4593
09f83975 4594 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
3f518509
MW		 4595 GFP_KERNEL);
4596 if (!port->rxqs) {
4597 err = -ENOMEM;
4598 goto err_free_percpu;
4599 }
4600
4601 /* Allocate and initialize Rx queue for this port */
09f83975 4602 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 4603 struct mvpp2_rx_queue *rxq;
4604
4605 /* Map physical Rx queue to port's logical Rx queue */
4606 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
d82b0c21
JZ		 4607 if (!rxq) {
4608 err = -ENOMEM;
3f518509 4609 goto err_free_percpu;
d82b0c21 4610 }
3f518509
MW		 4611 /* Map this Rx queue to a physical queue */
4612 rxq->id = port->first_rxq + queue;
4613 rxq->port = port->id;
4614 rxq->logic_rxq = queue;
4615
4616 port->rxqs[queue] = rxq;
4617 }
4618
591f4cfa 4619 mvpp2_rx_irqs_setup(port);
3f518509
MW		 4620
4621 /* Create Rx descriptor rings */
09f83975 4622 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 4623 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4624
4625 rxq->size = port->rx_ring_size;
4626 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4627 rxq->time_coal = MVPP2_RX_COAL_USEC;
4628 }
4629
4630 mvpp2_ingress_disable(port);
4631
4632 /* Port default configuration */
4633 mvpp2_defaults_set(port);
4634
4635 /* Port's classifier configuration */
4636 mvpp2_cls_oversize_rxq_set(port);
4637 mvpp2_cls_port_config(port);
4638
e6e21c02 4639 if (mvpp22_rss_is_supported())
6310f77d 4640 mvpp22_port_rss_init(port);
e6e21c02 4641
3f518509
MW		 4642 /* Provide an initial Rx packet size */
4643 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
4644
4645 /* Initialize pools for swf */
4646 err = mvpp2_swf_bm_pool_init(port);
4647 if (err)
4648 goto err_free_percpu;
4649
9bea6897
MC		 4650 /* Clear all port stats */
4651 mvpp2_read_stats(port);
4652 memset(port->ethtool_stats, 0,
4653 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64));
6410c139 4654
3f518509
MW		 4655 return 0;
4656
4657err_free_percpu:
09f83975 4658 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 4659 if (!port->txqs[queue])
4660 continue;
4661 free_percpu(port->txqs[queue]->pcpu);
4662 }
4663 return err;
4664}
4665
a9aac385
AT		 4666static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
4667 unsigned long *flags)
4668{
4669 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
4670 "tx-cpu3" };
4671 int i;
4672
4673 for (i = 0; i < 5; i++)
4674 if (of_property_match_string(port_node, "interrupt-names",
4675 irqs[i]) < 0)
4676 return false;
4677
4678 *flags |= MVPP2_F_DT_COMPAT;
4679 return true;
4680}
4681
4682/* Checks if the port dt description has the required Tx interrupts:
4683 * - PPv2.1: there are no such interrupts.
4684 * - PPv2.2:
4685 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
4686 * - The new ones have: "hifX" with X in [0..8]
4687 *
4688 * All those variants are supported to keep the backward compatibility.
213f428f 4689 */
a9aac385
AT		 4690static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
4691 struct device_node *port_node,
4692 unsigned long *flags)
213f428f 4693{
a9aac385
AT		 4694 char name[5];
4695 int i;
213f428f 4696
fd4a1056
AT		 4697 /* ACPI */
4698 if (!port_node)
4699 return true;
4700
213f428f
TP		 4701 if (priv->hw_version == MVPP21)
4702 return false;
4703
a9aac385
AT		 4704 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
4705 return true;
4706
4707 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
4708 snprintf(name, 5, "hif%d", i);
4709 if (of_property_match_string(port_node, "interrupt-names",
4710 name) < 0)
213f428f
TP		 4711 return false;
4712 }
4713
4714 return true;
4715}
4716
3ba8c81e 4717static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
24812221 4718 struct fwnode_handle *fwnode,
3ba8c81e
AT		 4719 char **mac_from)
4720{
4721 struct mvpp2_port *port = netdev_priv(dev);
4722 char hw_mac_addr[ETH_ALEN] = {0};
24812221 4723 char fw_mac_addr[ETH_ALEN];
3ba8c81e 4724
24812221
MW		 4725 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
4726 *mac_from = "firmware node";
4727 ether_addr_copy(dev->dev_addr, fw_mac_addr);
688cbaf2
AT		 4728 return;
4729 }
d2a6e48e 4730
688cbaf2
AT		 4731 if (priv->hw_version == MVPP21) {
4732 mvpp21_get_mac_address(port, hw_mac_addr);
4733 if (is_valid_ether_addr(hw_mac_addr)) {
4734 *mac_from = "hardware";
4735 ether_addr_copy(dev->dev_addr, hw_mac_addr);
4736 return;
4737 }
3ba8c81e 4738 }
688cbaf2
AT		 4739
4740 *mac_from = "random";
4741 eth_hw_addr_random(dev);
3ba8c81e
AT		 4742}
4743
44cc27e4 4744static void mvpp2_phylink_validate(struct phylink_config *config,
4bb04326
AT		 4745 unsigned long *supported,
4746 struct phylink_link_state *state)
4747{
44cc27e4
IC		 4748 struct mvpp2_port *port = container_of(config, struct mvpp2_port,
4749 phylink_config);
4bb04326
AT		 4750 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
4751
0fb628f0
BS		 4752 /* Invalid combinations */
4753 switch (state->interface) {
4754 case PHY_INTERFACE_MODE_10GKR:
4755 case PHY_INTERFACE_MODE_XAUI:
4756 if (port->gop_id != 0)
4757 goto empty_set;
4758 break;
4759 case PHY_INTERFACE_MODE_RGMII:
4760 case PHY_INTERFACE_MODE_RGMII_ID:
4761 case PHY_INTERFACE_MODE_RGMII_RXID:
4762 case PHY_INTERFACE_MODE_RGMII_TXID:
8b318f30 4763 if (port->priv->hw_version == MVPP22 && port->gop_id == 0)
0fb628f0
BS		 4764 goto empty_set;
4765 break;
4766 default:
4767 break;
4768 }
4769
4bb04326
AT		 4770 phylink_set(mask, Autoneg);
4771 phylink_set_port_modes(mask);
4772 phylink_set(mask, Pause);
4773 phylink_set(mask, Asym_Pause);
4774
d97c9f4a
AT		 4775 switch (state->interface) {
4776 case PHY_INTERFACE_MODE_10GKR:
0fb628f0 4777 case PHY_INTERFACE_MODE_XAUI:
01b3fd5a 4778 case PHY_INTERFACE_MODE_NA:
00679177 4779 if (port->gop_id == 0) {
1b451fb2 4780 phylink_set(mask, 10000baseT_Full);
00679177
AT		 4781 phylink_set(mask, 10000baseCR_Full);
4782 phylink_set(mask, 10000baseSR_Full);
4783 phylink_set(mask, 10000baseLR_Full);
4784 phylink_set(mask, 10000baseLRM_Full);
4785 phylink_set(mask, 10000baseER_Full);
4786 phylink_set(mask, 10000baseKR_Full);
4787 }
d97c9f4a 4788 /* Fall-through */
0fb628f0
BS		 4789 case PHY_INTERFACE_MODE_RGMII:
4790 case PHY_INTERFACE_MODE_RGMII_ID:
4791 case PHY_INTERFACE_MODE_RGMII_RXID:
4792 case PHY_INTERFACE_MODE_RGMII_TXID:
4793 case PHY_INTERFACE_MODE_SGMII:
d97c9f4a
AT		 4794 phylink_set(mask, 10baseT_Half);
4795 phylink_set(mask, 10baseT_Full);
4796 phylink_set(mask, 100baseT_Half);
4797 phylink_set(mask, 100baseT_Full);
d97c9f4a
AT		 4798 /* Fall-through */
4799 case PHY_INTERFACE_MODE_1000BASEX:
a6fe31de 4800 case PHY_INTERFACE_MODE_2500BASEX:
d97c9f4a
AT		 4801 phylink_set(mask, 1000baseT_Full);
4802 phylink_set(mask, 1000baseX_Full);
b38d198c 4803 phylink_set(mask, 2500baseT_Full);
a6fe31de 4804 phylink_set(mask, 2500baseX_Full);
0fb628f0
BS		 4805 break;
4806 default:
4807 goto empty_set;
4bb04326
AT		 4808 }
4809
4810 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
4811 bitmap_and(state->advertising, state->advertising, mask,
4812 __ETHTOOL_LINK_MODE_MASK_NBITS);
0fb628f0
BS		 4813 return;
4814
4815empty_set:
4816 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
4bb04326
AT		 4817}
4818
4819static void mvpp22_xlg_link_state(struct mvpp2_port *port,
4820 struct phylink_link_state *state)
4821{
4822 u32 val;
4823
4824 state->speed = SPEED_10000;
4825 state->duplex = 1;
4826 state->an_complete = 1;
4827
4828 val = readl(port->base + MVPP22_XLG_STATUS);
4829 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
4830
4831 state->pause = 0;
4832 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4833 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
4834 state->pause |= MLO_PAUSE_TX;
4835 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
4836 state->pause |= MLO_PAUSE_RX;
4837}
4838
4839static void mvpp2_gmac_link_state(struct mvpp2_port *port,
4840 struct phylink_link_state *state)
4841{
4842 u32 val;
4843
4844 val = readl(port->base + MVPP2_GMAC_STATUS0);
4845
4846 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
4847 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
4848 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
4849
d97c9f4a
AT		 4850 switch (port->phy_interface) {
4851 case PHY_INTERFACE_MODE_1000BASEX:
4bb04326 4852 state->speed = SPEED_1000;
d97c9f4a 4853 break;
a6fe31de
AT		 4854 case PHY_INTERFACE_MODE_2500BASEX:
4855 state->speed = SPEED_2500;
4856 break;
d97c9f4a
AT		 4857 default:
4858 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
4859 state->speed = SPEED_1000;
4860 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
4861 state->speed = SPEED_100;
4862 else
4863 state->speed = SPEED_10;
4864 }
4bb04326
AT		 4865
4866 state->pause = 0;
4867 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
4868 state->pause |= MLO_PAUSE_RX;
4869 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
4870 state->pause |= MLO_PAUSE_TX;
4871}
4872
44cc27e4 4873static int mvpp2_phylink_mac_link_state(struct phylink_config *config,
4bb04326
AT		 4874 struct phylink_link_state *state)
4875{
44cc27e4
IC		 4876 struct mvpp2_port *port = container_of(config, struct mvpp2_port,
4877 phylink_config);
4bb04326
AT		 4878
4879 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
4880 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
4881 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4882
4883 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
4884 mvpp22_xlg_link_state(port, state);
4885 return 1;
4886 }
4887 }
4888
4889 mvpp2_gmac_link_state(port, state);
4890 return 1;
4891}
4892
44cc27e4 4893static void mvpp2_mac_an_restart(struct phylink_config *config)
4bb04326 4894{
44cc27e4
IC		 4895 struct mvpp2_port *port = container_of(config, struct mvpp2_port,
4896 phylink_config);
a4650477 4897 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4bb04326 4898
a4650477
RK		 4899 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
4900 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4901 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
4902 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4bb04326
AT		 4903}
4904
4905static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
4906 const struct phylink_link_state *state)
4907{
f17e70d2
AT		 4908 u32 old_ctrl0, ctrl0;
4909 u32 old_ctrl4, ctrl4;
4bb04326 4910
f17e70d2
AT		 4911 old_ctrl0 = ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG);
4912 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG);
4bb04326 4913
649e51d5
AT		 4914 ctrl0 |= MVPP22_XLG_CTRL0_MAC_RESET_DIS;
4915
4bb04326
AT		 4916 if (state->pause & MLO_PAUSE_TX)
4917 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
e240b7db
RK		 4918 else
4919 ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
4920
4bb04326
AT		 4921 if (state->pause & MLO_PAUSE_RX)
4922 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
e240b7db
RK		 4923 else
4924 ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
4bb04326 4925
bba18318
MC		 4926 ctrl4 &= ~(MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
4927 MVPP22_XLG_CTRL4_EN_IDLE_CHECK);
4928 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC;
4bb04326 4929
f17e70d2
AT		 4930 if (old_ctrl0 != ctrl0)
4931 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG);
4932 if (old_ctrl4 != ctrl4)
4933 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);
649e51d5
AT		 4934
4935 if (!(old_ctrl0 & MVPP22_XLG_CTRL0_MAC_RESET_DIS)) {
4936 while (!(readl(port->base + MVPP22_XLG_CTRL0_REG) &
4937 MVPP22_XLG_CTRL0_MAC_RESET_DIS))
4938 continue;
4939 }
4bb04326
AT		 4940}
4941
4942static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
4943 const struct phylink_link_state *state)
4944{
d14e078f
RK		 4945 u32 old_an, an;
4946 u32 old_ctrl0, ctrl0;
4947 u32 old_ctrl2, ctrl2;
4948 u32 old_ctrl4, ctrl4;
4bb04326 4949
d14e078f
RK		 4950 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4951 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4952 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4953 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4bb04326
AT		 4954
4955 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED |
4956 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
4957 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
d14e078f
RK		 4958 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN |
4959 MVPP2_GMAC_IN_BAND_AUTONEG | MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS);
4bb04326 4960 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
388ca27f
RK		 4961 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PORT_RESET_MASK |
4962 MVPP2_GMAC_PCS_ENABLE_MASK);
4963 ctrl4 &= ~(MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
4bb04326 4964
388ca27f 4965 /* Configure port type */
4a4cec72 4966 if (phy_interface_mode_is_8023z(state->interface)) {
388ca27f
RK		 4967 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK;
4968 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
4969 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4970 MVPP22_CTRL4_DP_CLK_SEL |
4971 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4972 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
4973 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK;
4974 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
4975 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4976 MVPP22_CTRL4_DP_CLK_SEL |
4977 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4978 } else if (phy_interface_mode_is_rgmii(state->interface)) {
4979 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
4980 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4981 MVPP22_CTRL4_SYNC_BYPASS_DIS |
4982 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
d97c9f4a 4983 }
4bb04326 4984
388ca27f 4985 /* Configure advertisement bits */
4bb04326
AT		 4986 if (phylink_test(state->advertising, Pause))
4987 an |= MVPP2_GMAC_FC_ADV_EN;
4988 if (phylink_test(state->advertising, Asym_Pause))
4989 an |= MVPP2_GMAC_FC_ADV_ASM_EN;
4990
388ca27f
RK		 4991 /* Configure negotiation style */
4992 if (!phylink_autoneg_inband(mode)) {
4993 /* Phy or fixed speed - no in-band AN */
4994 if (state->duplex)
4995 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4bb04326 4996
388ca27f
RK		 4997 if (state->speed == SPEED_1000 || state->speed == SPEED_2500)
4998 an |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4999 else if (state->speed == SPEED_100)
5000 an |= MVPP2_GMAC_CONFIG_MII_SPEED;
4bb04326
AT		 5001
5002 if (state->pause & MLO_PAUSE_TX)
5003 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
5004 if (state->pause & MLO_PAUSE_RX)
5005 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
388ca27f
RK		 5006 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
5007 /* SGMII in-band mode receives the speed and duplex from
5008 * the PHY. Flow control information is not received. */
5009 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS);
5010 an |= MVPP2_GMAC_IN_BAND_AUTONEG |
5011 MVPP2_GMAC_AN_SPEED_EN |
5012 MVPP2_GMAC_AN_DUPLEX_EN;
4bb04326 5013
388ca27f
RK		 5014 if (state->pause & MLO_PAUSE_TX)
5015 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
5016 if (state->pause & MLO_PAUSE_RX)
5017 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
5018 } else if (phy_interface_mode_is_8023z(state->interface)) {
5019 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
5020 * they negotiate duplex: they are always operating with a fixed
5021 * speed of 1000/2500Mbps in full duplex, so force 1000/2500
5022 * speed and full duplex here.
5023 */
5024 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
5025 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS);
d14e078f
RK		 5026 an |= MVPP2_GMAC_IN_BAND_AUTONEG |
5027 MVPP2_GMAC_CONFIG_GMII_SPEED |
388ca27f 5028 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4bb04326 5029
388ca27f
RK		 5030 if (state->pause & MLO_PAUSE_AN && state->an_enabled) {
5031 an |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
5032 } else {
5033 if (state->pause & MLO_PAUSE_TX)
5034 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
5035 if (state->pause & MLO_PAUSE_RX)
5036 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
5037 }
4bb04326
AT		 5038 }
5039
9a490e34
AT		 5040/* Some fields of the auto-negotiation register require the port to be down when
5041 * their value is updated.
5042 */
5043#define MVPP2_GMAC_AN_PORT_DOWN_MASK \
5044 (MVPP2_GMAC_IN_BAND_AUTONEG | \
5045 MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | \
5046 MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | \
5047 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_CONFIG_FULL_DUPLEX | \
5048 MVPP2_GMAC_AN_DUPLEX_EN)
5049
d14e078f
RK		 5050 if ((old_ctrl0 ^ ctrl0) & MVPP2_GMAC_PORT_TYPE_MASK ||
5051 (old_ctrl2 ^ ctrl2) & MVPP2_GMAC_INBAND_AN_MASK ||
9a490e34 5052 (old_an ^ an) & MVPP2_GMAC_AN_PORT_DOWN_MASK) {
d14e078f
RK		 5053 /* Force link down */
5054 old_an &= ~MVPP2_GMAC_FORCE_LINK_PASS;
5055 old_an |= MVPP2_GMAC_FORCE_LINK_DOWN;
5056 writel(old_an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5057
5058 /* Set the GMAC in a reset state - do this in a way that
5059 * ensures we clear it below.
5060 */
5061 old_ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK;
5062 writel(old_ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
5063 }
5064
5065 if (old_ctrl0 != ctrl0)
5066 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
5067 if (old_ctrl2 != ctrl2)
5068 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
5069 if (old_ctrl4 != ctrl4)
5070 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
5071 if (old_an != an)
5072 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
316734fd
RK		 5073
5074 if (old_ctrl2 & MVPP2_GMAC_PORT_RESET_MASK) {
5075 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
5076 MVPP2_GMAC_PORT_RESET_MASK)
5077 continue;
5078 }
4bb04326
AT		 5079}
5080
44cc27e4 5081static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
4bb04326
AT		 5082 const struct phylink_link_state *state)
5083{
44cc27e4 5084 struct net_device *dev = to_net_dev(config->dev);
4bb04326 5085 struct mvpp2_port *port = netdev_priv(dev);
bf2fa125 5086 bool change_interface = port->phy_interface != state->interface;
4bb04326
AT		 5087
5088 /* Check for invalid configuration */
1d9b041e 5089 if (mvpp2_is_xlg(state->interface) && port->gop_id != 0) {
4bb04326
AT		 5090 netdev_err(dev, "Invalid mode on %s\n", dev->name);
5091 return;
5092 }
5093
4bb04326
AT		 5094 /* Make sure the port is disabled when reconfiguring the mode */
5095 mvpp2_port_disable(port);
1970ee96 5096
d78a1809 5097 if (port->priv->hw_version == MVPP22 && change_interface) {
bf2fa125 5098 mvpp22_gop_mask_irq(port);
4bb04326 5099
d78a1809 5100 port->phy_interface = state->interface;
4bb04326 5101
d78a1809
AT		 5102 /* Reconfigure the serdes lanes */
5103 phy_power_off(port->comphy);
5104 mvpp22_mode_reconfigure(port);
4bb04326
AT		 5105 }
5106
5107 /* mac (re)configuration */
1d9b041e 5108 if (mvpp2_is_xlg(state->interface))
4bb04326
AT		 5109 mvpp2_xlg_config(port, mode, state);
5110 else if (phy_interface_mode_is_rgmii(state->interface) ||
4a4cec72
RK		 5111 phy_interface_mode_is_8023z(state->interface) ||
5112 state->interface == PHY_INTERFACE_MODE_SGMII)
4bb04326
AT		 5113 mvpp2_gmac_config(port, mode, state);
5114
5115 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
5116 mvpp2_port_loopback_set(port, state);
5117
d78a1809 5118 if (port->priv->hw_version == MVPP22 && change_interface)
bf2fa125
RK		 5119 mvpp22_gop_unmask_irq(port);
5120
41948ccb 5121 mvpp2_port_enable(port);
4bb04326
AT		 5122}
5123
44cc27e4 5124static void mvpp2_mac_link_up(struct phylink_config *config, unsigned int mode,
4bb04326
AT		 5125 phy_interface_t interface, struct phy_device *phy)
5126{
44cc27e4 5127 struct net_device *dev = to_net_dev(config->dev);
4bb04326
AT		 5128 struct mvpp2_port *port = netdev_priv(dev);
5129 u32 val;
5130
1970ee96
AT		 5131 if (!phylink_autoneg_inband(mode)) {
5132 if (mvpp2_is_xlg(interface)) {
5133 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5134 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
5135 val |= MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
5136 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
5137 } else {
5138 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5139 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
5140 val |= MVPP2_GMAC_FORCE_LINK_PASS;
5141 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5142 }
4bb04326
AT		 5143 }
5144
5145 mvpp2_port_enable(port);
5146
5147 mvpp2_egress_enable(port);
5148 mvpp2_ingress_enable(port);
5149 netif_tx_wake_all_queues(dev);
5150}
5151
44cc27e4
IC		 5152static void mvpp2_mac_link_down(struct phylink_config *config,
5153 unsigned int mode, phy_interface_t interface)
4bb04326 5154{
44cc27e4 5155 struct net_device *dev = to_net_dev(config->dev);
4bb04326
AT		 5156 struct mvpp2_port *port = netdev_priv(dev);
5157 u32 val;
5158
1970ee96
AT		 5159 if (!phylink_autoneg_inband(mode)) {
5160 if (mvpp2_is_xlg(interface)) {
5161 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5162 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
5163 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
5164 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
5165 } else {
5166 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5167 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
5168 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
5169 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5170 }
4bb04326
AT		 5171 }
5172
5173 netif_tx_stop_all_queues(dev);
5174 mvpp2_egress_disable(port);
5175 mvpp2_ingress_disable(port);
5176
4bb04326
AT		 5177 mvpp2_port_disable(port);
5178}
5179
5180static const struct phylink_mac_ops mvpp2_phylink_ops = {
5181 .validate = mvpp2_phylink_validate,
5182 .mac_link_state = mvpp2_phylink_mac_link_state,
5183 .mac_an_restart = mvpp2_mac_an_restart,
5184 .mac_config = mvpp2_mac_config,
5185 .mac_link_up = mvpp2_mac_link_up,
5186 .mac_link_down = mvpp2_mac_link_down,
5187};
5188
3f518509
MW		 5189/* Ports initialization */
5190static int mvpp2_port_probe(struct platform_device *pdev,
24812221 5191 struct fwnode_handle *port_fwnode,
bf147153 5192 struct mvpp2 *priv)
3f518509 5193{
a75edc7c 5194 struct phy *comphy = NULL;
3f518509 5195 struct mvpp2_port *port;
edc660fa 5196 struct mvpp2_port_pcpu *port_pcpu;
24812221 5197 struct device_node *port_node = to_of_node(port_fwnode);
c9dbb6cf 5198 netdev_features_t features;
3f518509 5199 struct net_device *dev;
4bb04326 5200 struct phylink *phylink;
3ba8c81e 5201 char *mac_from = "";
074c74df 5202 unsigned int ntxqs, nrxqs, thread;
a9aac385 5203 unsigned long flags = 0;
213f428f 5204 bool has_tx_irqs;
3f518509 5205 u32 id;
3f518509 5206 int phy_mode;
850623b3 5207 int err, i;
3f518509 5208
fd4a1056
AT		 5209 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
5210 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
5211 dev_err(&pdev->dev,
5212 "not enough IRQs to support multi queue mode\n");
5213 return -EINVAL;
a75edc7c 5214 }
213f428f 5215
09f83975 5216 ntxqs = MVPP2_MAX_TXQ;
7d04b0b1 5217 nrxqs = mvpp2_get_nrxqs(priv);
09f83975
TP		 5218
5219 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
3f518509
MW		 5220 if (!dev)
5221 return -ENOMEM;
5222
24812221 5223 phy_mode = fwnode_get_phy_mode(port_fwnode);
3f518509
MW		 5224 if (phy_mode < 0) {
5225 dev_err(&pdev->dev, "incorrect phy mode\n");
5226 err = phy_mode;
5227 goto err_free_netdev;
5228 }
5229
a75edc7c
MW		 5230 if (port_node) {
5231 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
5232 if (IS_ERR(comphy)) {
5233 if (PTR_ERR(comphy) == -EPROBE_DEFER) {
5234 err = -EPROBE_DEFER;
5235 goto err_free_netdev;
5236 }
5237 comphy = NULL;
542897d9 5238 }
542897d9
AT		 5239 }
5240
24812221 5241 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
3f518509
MW		 5242 err = -EINVAL;
5243 dev_err(&pdev->dev, "missing port-id value\n");
5244 goto err_free_netdev;
5245 }
5246
7cf87e4a 5247 dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
3f518509
MW		 5248 dev->watchdog_timeo = 5 * HZ;
5249 dev->netdev_ops = &mvpp2_netdev_ops;
5250 dev->ethtool_ops = &mvpp2_eth_tool_ops;
5251
5252 port = netdev_priv(dev);
591f4cfa 5253 port->dev = dev;
a75edc7c 5254 port->fwnode = port_fwnode;
4bb04326 5255 port->has_phy = !!of_find_property(port_node, "phy", NULL);
09f83975
TP		 5256 port->ntxqs = ntxqs;
5257 port->nrxqs = nrxqs;
213f428f
TP		 5258 port->priv = priv;
5259 port->has_tx_irqs = has_tx_irqs;
a9aac385 5260 port->flags = flags;
3f518509 5261
591f4cfa
TP		 5262 err = mvpp2_queue_vectors_init(port, port_node);
5263 if (err)
3f518509 5264 goto err_free_netdev;
3f518509 5265
a75edc7c
MW		 5266 if (port_node)
5267 port->link_irq = of_irq_get_byname(port_node, "link");
5268 else
5269 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
fd3651b2
AT		 5270 if (port->link_irq == -EPROBE_DEFER) {
5271 err = -EPROBE_DEFER;
5272 goto err_deinit_qvecs;
5273 }
5274 if (port->link_irq <= 0)
5275 /* the link irq is optional */
5276 port->link_irq = 0;
5277
24812221 5278 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
3f518509
MW		 5279 port->flags |= MVPP2_F_LOOPBACK;
5280
3f518509 5281 port->id = id;
59b9a31e 5282 if (priv->hw_version == MVPP21)
09f83975 5283 port->first_rxq = port->id * port->nrxqs;
59b9a31e
TP		 5284 else
5285 port->first_rxq = port->id * priv->max_port_rxqs;
5286
4bb04326 5287 port->of_node = port_node;
3f518509 5288 port->phy_interface = phy_mode;
542897d9 5289 port->comphy = comphy;
3f518509 5290
a786841d 5291 if (priv->hw_version == MVPP21) {
3230a55b 5292 port->base = devm_platform_ioremap_resource(pdev, 2 + id);
a786841d
TP		 5293 if (IS_ERR(port->base)) {
5294 err = PTR_ERR(port->base);
fd3651b2 5295 goto err_free_irq;
a786841d 5296 }
118d6298
MR		 5297
5298 port->stats_base = port->priv->lms_base +
5299 MVPP21_MIB_COUNTERS_OFFSET +
5300 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
a786841d 5301 } else {
24812221
MW		 5302 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
5303 &port->gop_id)) {
a786841d
TP		 5304 err = -EINVAL;
5305 dev_err(&pdev->dev, "missing gop-port-id value\n");
591f4cfa 5306 goto err_deinit_qvecs;
a786841d
TP		 5307 }
5308
5309 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
118d6298
MR		 5310 port->stats_base = port->priv->iface_base +
5311 MVPP22_MIB_COUNTERS_OFFSET +
5312 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
3f518509
MW		 5313 }
5314
118d6298 5315 /* Alloc per-cpu and ethtool stats */
3f518509
MW		 5316 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
5317 if (!port->stats) {
5318 err = -ENOMEM;
fd3651b2 5319 goto err_free_irq;
3f518509
MW		 5320 }
5321
118d6298 5322 port->ethtool_stats = devm_kcalloc(&pdev->dev,
9bea6897 5323 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs),
118d6298
MR		 5324 sizeof(u64), GFP_KERNEL);
5325 if (!port->ethtool_stats) {
5326 err = -ENOMEM;
5327 goto err_free_stats;
5328 }
5329
e5c500eb
MR		 5330 mutex_init(&port->gather_stats_lock);
5331 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
5332
24812221 5333 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
3f518509 5334
7cf87e4a
YM		 5335 port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
5336 port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
3f518509
MW		 5337 SET_NETDEV_DEV(dev, &pdev->dev);
5338
5339 err = mvpp2_port_init(port);
5340 if (err < 0) {
5341 dev_err(&pdev->dev, "failed to init port %d\n", id);
5342 goto err_free_stats;
5343 }
26975821 5344
26975821
TP		 5345 mvpp2_port_periodic_xon_disable(port);
5346
649e51d5 5347 mvpp2_mac_reset_assert(port);
7409e66e 5348 mvpp22_pcs_reset_assert(port);
3f518509 5349
edc660fa
MW		 5350 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
5351 if (!port->pcpu) {
5352 err = -ENOMEM;
5353 goto err_free_txq_pcpu;
5354 }
5355
213f428f 5356 if (!port->has_tx_irqs) {
e531f767 5357 for (thread = 0; thread < priv->nthreads; thread++) {
074c74df 5358 port_pcpu = per_cpu_ptr(port->pcpu, thread);
edc660fa 5359
213f428f 5360 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
ecb9f80d 5361 HRTIMER_MODE_REL_PINNED_SOFT);
213f428f
TP		 5362 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
5363 port_pcpu->timer_scheduled = false;
ecb9f80d 5364 port_pcpu->dev = dev;
213f428f 5365 }
edc660fa
MW		 5366 }
5367
381c5671
AT		 5368 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5369 NETIF_F_TSO;
3f518509 5370 dev->features = features | NETIF_F_RXCSUM;
56beda3d
MC		 5371 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
5372 NETIF_F_HW_VLAN_CTAG_FILTER;
576193f2 5373
da86f59f 5374 if (mvpp22_rss_is_supported()) {
d33ec452 5375 dev->hw_features |= NETIF_F_RXHASH;
da86f59f
MC		 5376 dev->features |= NETIF_F_NTUPLE;
5377 }
d33ec452 5378
7d04b0b1
MC		 5379 if (!port->priv->percpu_pools)
5380 mvpp2_set_hw_csum(port, port->pool_long->id);
576193f2 5381
3f518509 5382 dev->vlan_features |= features;
1d17db08 5383 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
10fea26c 5384 dev->priv_flags |= IFF_UNICAST_FLT;
3f518509 5385
576193f2 5386 /* MTU range: 68 - 9704 */
5777987e 5387 dev->min_mtu = ETH_MIN_MTU;
576193f2
SC		 5388 /* 9704 == 9728 - 20 and rounding to 8 */
5389 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
c4053ef3 5390 dev->dev.of_node = port_node;
5777987e 5391
4bb04326
AT		 5392 /* Phylink isn't used w/ ACPI as of now */
5393 if (port_node) {
44cc27e4
IC		 5394 port->phylink_config.dev = &dev->dev;
5395 port->phylink_config.type = PHYLINK_NETDEV;
5396
5397 phylink = phylink_create(&port->phylink_config, port_fwnode,
5398 phy_mode, &mvpp2_phylink_ops);
4bb04326
AT		 5399 if (IS_ERR(phylink)) {
5400 err = PTR_ERR(phylink);
5401 goto err_free_port_pcpu;
5402 }
5403 port->phylink = phylink;
5404 } else {
5405 port->phylink = NULL;
5406 }
5407
3f518509
MW		 5408 err = register_netdev(dev);
5409 if (err < 0) {
5410 dev_err(&pdev->dev, "failed to register netdev\n");
4bb04326 5411 goto err_phylink;
3f518509
MW		 5412 }
5413 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
5414
bf147153
MW		 5415 priv->port_list[priv->port_count++] = port;
5416
3f518509
MW		 5417 return 0;
5418
4bb04326
AT		 5419err_phylink:
5420 if (port->phylink)
5421 phylink_destroy(port->phylink);
edc660fa
MW		 5422err_free_port_pcpu:
5423 free_percpu(port->pcpu);
3f518509 5424err_free_txq_pcpu:
09f83975 5425 for (i = 0; i < port->ntxqs; i++)
3f518509
MW		 5426 free_percpu(port->txqs[i]->pcpu);
5427err_free_stats:
5428 free_percpu(port->stats);
fd3651b2
AT		 5429err_free_irq:
5430 if (port->link_irq)
5431 irq_dispose_mapping(port->link_irq);
591f4cfa
TP		 5432err_deinit_qvecs:
5433 mvpp2_queue_vectors_deinit(port);
3f518509
MW		 5434err_free_netdev:
5435 free_netdev(dev);
5436 return err;
5437}
5438
5439/* Ports removal routine */
5440static void mvpp2_port_remove(struct mvpp2_port *port)
5441{
5442 int i;
5443
5444 unregister_netdev(port->dev);
4bb04326
AT		 5445 if (port->phylink)
5446 phylink_destroy(port->phylink);
edc660fa 5447 free_percpu(port->pcpu);
3f518509 5448 free_percpu(port->stats);
09f83975 5449 for (i = 0; i < port->ntxqs; i++)
3f518509 5450 free_percpu(port->txqs[i]->pcpu);
591f4cfa 5451 mvpp2_queue_vectors_deinit(port);
fd3651b2
AT		 5452 if (port->link_irq)
5453 irq_dispose_mapping(port->link_irq);
3f518509
MW		 5454 free_netdev(port->dev);
5455}
5456
5457/* Initialize decoding windows */
5458static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
5459 struct mvpp2 *priv)
5460{
5461 u32 win_enable;
5462 int i;
5463
5464 for (i = 0; i < 6; i++) {
5465 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
5466 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
5467
5468 if (i < 4)
5469 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
5470 }
5471
5472 win_enable = 0;
5473
5474 for (i = 0; i < dram->num_cs; i++) {
5475 const struct mbus_dram_window *cs = dram->cs + i;
5476
5477 mvpp2_write(priv, MVPP2_WIN_BASE(i),
5478 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
5479 dram->mbus_dram_target_id);
5480
5481 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
5482 (cs->size - 1) & 0xffff0000);
5483
5484 win_enable |= (1 << i);
5485 }
5486
5487 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
5488}
5489
5490/* Initialize Rx FIFO's */
5491static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
5492{
5493 int port;
5494
5495 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
5496 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
2d1d7df8 5497 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
3f518509 5498 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
2d1d7df8
AT		 5499 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
5500 }
5501
5502 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
5503 MVPP2_RX_FIFO_PORT_MIN_PKT);
5504 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
5505}
5506
5507static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
5508{
5509 int port;
5510
5511 /* The FIFO size parameters are set depending on the maximum speed a
5512 * given port can handle:
5513 * - Port 0: 10Gbps
5514 * - Port 1: 2.5Gbps
5515 * - Ports 2 and 3: 1Gbps
5516 */
5517
5518 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
5519 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
5520 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
5521 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB);
5522
5523 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
5524 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
5525 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
5526 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB);
5527
5528 for (port = 2; port < MVPP2_MAX_PORTS; port++) {
5529 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
5530 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
5531 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
5532 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
3f518509
MW		 5533 }
5534
5535 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
5536 MVPP2_RX_FIFO_PORT_MIN_PKT);
5537 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
5538}
5539
93ff130f
YM		 5540/* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G
5541 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G,
5542 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB.
5543 */
7c10f974
AT		 5544static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
5545{
93ff130f 5546 int port, size, thrs;
7c10f974 5547
93ff130f
YM		 5548 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
5549 if (port == 0) {
5550 size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
5551 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB;
5552 } else {
5553 size = MVPP22_TX_FIFO_DATA_SIZE_3KB;
5554 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB;
5555 }
5556 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
5557 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);
5558 }
7c10f974
AT		 5559}
5560
6763ce31
TP		 5561static void mvpp2_axi_init(struct mvpp2 *priv)
5562{
5563 u32 val, rdval, wrval;
5564
5565 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
5566
5567 /* AXI Bridge Configuration */
5568
5569 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
5570 << MVPP22_AXI_ATTR_CACHE_OFFS;
5571 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5572 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5573
5574 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
5575 << MVPP22_AXI_ATTR_CACHE_OFFS;
5576 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5577 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5578
5579 /* BM */
5580 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
5581 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
5582
5583 /* Descriptors */
5584 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
5585 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
5586 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
5587 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
5588
5589 /* Buffer Data */
5590 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
5591 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
5592
5593 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
5594 << MVPP22_AXI_CODE_CACHE_OFFS;
5595 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
5596 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5597 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
5598 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
5599
5600 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
5601 << MVPP22_AXI_CODE_CACHE_OFFS;
5602 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5603 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5604
5605 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
5606
5607 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
5608 << MVPP22_AXI_CODE_CACHE_OFFS;
5609 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5610 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5611
5612 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
5613}
5614
3f518509
MW		 5615/* Initialize network controller common part HW */
5616static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
5617{
5618 const struct mbus_dram_target_info *dram_target_info;
5619 int err, i;
08a23755 5620 u32 val;
3f518509 5621
3f518509
MW		 5622 /* MBUS windows configuration */
5623 dram_target_info = mv_mbus_dram_info();
5624 if (dram_target_info)
5625 mvpp2_conf_mbus_windows(dram_target_info, priv);
5626
6763ce31
TP		 5627 if (priv->hw_version == MVPP22)
5628 mvpp2_axi_init(priv);
5629
08a23755 5630 /* Disable HW PHY polling */
26975821
TP		 5631 if (priv->hw_version == MVPP21) {
5632 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5633 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5634 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5635 } else {
5636 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5637 val &= ~MVPP22_SMI_POLLING_EN;
5638 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5639 }
08a23755 5640
3f518509 5641 /* Allocate and initialize aggregated TXQs */
074c74df 5642 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
d7ce3cec 5643 sizeof(*priv->aggr_txqs),
3f518509
MW		 5644 GFP_KERNEL);
5645 if (!priv->aggr_txqs)
5646 return -ENOMEM;
5647
074c74df 5648 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
3f518509
MW		 5649 priv->aggr_txqs[i].id = i;
5650 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
85affd7e 5651 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
3f518509
MW		 5652 if (err < 0)
5653 return err;
5654 }
5655
7c10f974
AT		 5656 /* Fifo Init */
5657 if (priv->hw_version == MVPP21) {
2d1d7df8 5658 mvpp2_rx_fifo_init(priv);
7c10f974 5659 } else {
2d1d7df8 5660 mvpp22_rx_fifo_init(priv);
7c10f974
AT		 5661 mvpp22_tx_fifo_init(priv);
5662 }
3f518509 5663
26975821
TP		 5664 if (priv->hw_version == MVPP21)
5665 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5666 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
3f518509
MW		 5667
5668 /* Allow cache snoop when transmiting packets */
5669 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5670
5671 /* Buffer Manager initialization */
13616361 5672 err = mvpp2_bm_init(&pdev->dev, priv);
3f518509
MW		 5673 if (err < 0)
5674 return err;
5675
5676 /* Parser default initialization */
5677 err = mvpp2_prs_default_init(pdev, priv);
5678 if (err < 0)
5679 return err;
5680
5681 /* Classifier default initialization */
5682 mvpp2_cls_init(priv);
5683
5684 return 0;
5685}
5686
5687static int mvpp2_probe(struct platform_device *pdev)
5688{
a75edc7c 5689 const struct acpi_device_id *acpi_id;
24812221
MW		 5690 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5691 struct fwnode_handle *port_fwnode;
3f518509
MW		 5692 struct mvpp2 *priv;
5693 struct resource *res;
a786841d 5694 void __iomem *base;
e531f767 5695 int i, shared;
3f518509
MW		 5696 int err;
5697
0b92e594 5698 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
3f518509
MW		 5699 if (!priv)
5700 return -ENOMEM;
5701
a75edc7c
MW		 5702 if (has_acpi_companion(&pdev->dev)) {
5703 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
5704 &pdev->dev);
92ee77d1
KL		 5705 if (!acpi_id)
5706 return -EINVAL;
a75edc7c
MW		 5707 priv->hw_version = (unsigned long)acpi_id->driver_data;
5708 } else {
5709 priv->hw_version =
5710 (unsigned long)of_device_get_match_data(&pdev->dev);
5711 }
faca9247 5712
1e27a628
MC		 5713 /* multi queue mode isn't supported on PPV2.1, fallback to single
5714 * mode
5715 */
5716 if (priv->hw_version == MVPP21)
5717 queue_mode = MVPP2_QDIST_SINGLE_MODE;
5718
3230a55b 5719 base = devm_platform_ioremap_resource(pdev, 0);
a786841d
TP		 5720 if (IS_ERR(base))
5721 return PTR_ERR(base);
5722
5723 if (priv->hw_version == MVPP21) {
3230a55b 5724 priv->lms_base = devm_platform_ioremap_resource(pdev, 1);
a786841d
TP		 5725 if (IS_ERR(priv->lms_base))
5726 return PTR_ERR(priv->lms_base);
5727 } else {
5728 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
a75edc7c
MW		 5729 if (has_acpi_companion(&pdev->dev)) {
5730 /* In case the MDIO memory region is declared in
5731 * the ACPI, it can already appear as 'in-use'
5732 * in the OS. Because it is overlapped by second
5733 * region of the network controller, make
5734 * sure it is released, before requesting it again.
5735 * The care is taken by mvpp2 driver to avoid
5736 * concurrent access to this memory region.
5737 */
5738 release_resource(res);
5739 }
a786841d
TP		 5740 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
5741 if (IS_ERR(priv->iface_base))
5742 return PTR_ERR(priv->iface_base);
a75edc7c 5743 }
f84bf386 5744
a75edc7c 5745 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
f84bf386
AT		 5746 priv->sysctrl_base =
5747 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
5748 "marvell,system-controller");
5749 if (IS_ERR(priv->sysctrl_base))
5750 /* The system controller regmap is optional for dt
5751 * compatibility reasons. When not provided, the
5752 * configuration of the GoP relies on the
5753 * firmware/bootloader.
5754 */
5755 priv->sysctrl_base = NULL;
a786841d
TP		 5756 }
5757
7d04b0b1
MC		 5758 if (priv->hw_version == MVPP22 &&
5759 mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
5760 priv->percpu_pools = 1;
5761
01d04936
SC		 5762 mvpp2_setup_bm_pool();
5763
e531f767
AT		 5764
5765 priv->nthreads = min_t(unsigned int, num_present_cpus(),
5766 MVPP2_MAX_THREADS);
5767
5768 shared = num_present_cpus() - priv->nthreads;
5769 if (shared > 0)
5770 bitmap_fill(&priv->lock_map,
5771 min_t(int, shared, MVPP2_MAX_THREADS));
5772
df089aa0 5773 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
a786841d
TP		 5774 u32 addr_space_sz;
5775
5776 addr_space_sz = (priv->hw_version == MVPP21 ?
5777 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
df089aa0 5778 priv->swth_base[i] = base + i * addr_space_sz;
a786841d 5779 }
3f518509 5780
59b9a31e
TP		 5781 if (priv->hw_version == MVPP21)
5782 priv->max_port_rxqs = 8;
5783 else
5784 priv->max_port_rxqs = 32;
5785
a75edc7c
MW		 5786 if (dev_of_node(&pdev->dev)) {
5787 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
5788 if (IS_ERR(priv->pp_clk))
5789 return PTR_ERR(priv->pp_clk);
5790 err = clk_prepare_enable(priv->pp_clk);
5791 if (err < 0)
5792 return err;
3f518509 5793
a75edc7c
MW		 5794 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
5795 if (IS_ERR(priv->gop_clk)) {
5796 err = PTR_ERR(priv->gop_clk);
5797 goto err_pp_clk;
fceb55d4 5798 }
a75edc7c 5799 err = clk_prepare_enable(priv->gop_clk);
fceb55d4 5800 if (err < 0)
a75edc7c
MW		 5801 goto err_pp_clk;
5802
5803 if (priv->hw_version == MVPP22) {
5804 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
5805 if (IS_ERR(priv->mg_clk)) {
5806 err = PTR_ERR(priv->mg_clk);
5807 goto err_gop_clk;
5808 }
5809
5810 err = clk_prepare_enable(priv->mg_clk);
5811 if (err < 0)
5812 goto err_gop_clk;
9af771ce
MC		 5813
5814 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
5815 if (IS_ERR(priv->mg_core_clk)) {
5816 priv->mg_core_clk = NULL;
5817 } else {
5818 err = clk_prepare_enable(priv->mg_core_clk);
5819 if (err < 0)
5820 goto err_mg_clk;
5821 }
a75edc7c 5822 }
4792ea04
GC		 5823
5824 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
5825 if (IS_ERR(priv->axi_clk)) {
5826 err = PTR_ERR(priv->axi_clk);
5827 if (err == -EPROBE_DEFER)
9af771ce 5828 goto err_mg_core_clk;
4792ea04
GC		 5829 priv->axi_clk = NULL;
5830 } else {
5831 err = clk_prepare_enable(priv->axi_clk);
5832 if (err < 0)
9af771ce 5833 goto err_mg_core_clk;
4792ea04 5834 }
fceb55d4 5835
a75edc7c
MW		 5836 /* Get system's tclk rate */
5837 priv->tclk = clk_get_rate(priv->pp_clk);
5838 } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
5839 &priv->tclk)) {
5840 dev_err(&pdev->dev, "missing clock-frequency value\n");
5841 return -EINVAL;
5842 }
3f518509 5843
2067e0a1 5844 if (priv->hw_version == MVPP22) {
da42bb27 5845 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
2067e0a1 5846 if (err)
45f972ad 5847 goto err_axi_clk;
2067e0a1
TP		 5848 /* Sadly, the BM pools all share the same register to
5849 * store the high 32 bits of their address. So they
5850 * must all have the same high 32 bits, which forces
5851 * us to restrict coherent memory to DMA_BIT_MASK(32).
5852 */
5853 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5854 if (err)
45f972ad 5855 goto err_axi_clk;
2067e0a1
TP		 5856 }
5857
3f518509
MW		 5858 /* Initialize network controller */
5859 err = mvpp2_init(pdev, priv);
5860 if (err < 0) {
5861 dev_err(&pdev->dev, "failed to initialize controller\n");
45f972ad 5862 goto err_axi_clk;
3f518509
MW		 5863 }
5864
3f518509 5865 /* Initialize ports */
24812221
MW		 5866 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5867 err = mvpp2_port_probe(pdev, port_fwnode, priv);
3f518509 5868 if (err < 0)
26146b0e 5869 goto err_port_probe;
bf147153
MW		 5870 }
5871
5872 if (priv->port_count == 0) {
5873 dev_err(&pdev->dev, "no ports enabled\n");
5874 err = -ENODEV;
45f972ad 5875 goto err_axi_clk;
3f518509
MW		 5876 }
5877
118d6298
MR		 5878 /* Statistics must be gathered regularly because some of them (like
5879 * packets counters) are 32-bit registers and could overflow quite
5880 * quickly. For instance, a 10Gb link used at full bandwidth with the
5881 * smallest packets (64B) will overflow a 32-bit counter in less than
5882 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
5883 */
118d6298
MR		 5884 snprintf(priv->queue_name, sizeof(priv->queue_name),
5885 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
5886 priv->port_count > 1 ? "+" : "");
5887 priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
5888 if (!priv->stats_queue) {
5889 err = -ENOMEM;
26146b0e 5890 goto err_port_probe;
118d6298
MR		 5891 }
5892
21da57a2
MC		 5893 mvpp2_dbgfs_init(priv, pdev->name);
5894
3f518509
MW		 5895 platform_set_drvdata(pdev, priv);
5896 return 0;
5897
26146b0e
AT		 5898err_port_probe:
5899 i = 0;
24812221 5900 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
26146b0e
AT		 5901 if (priv->port_list[i])
5902 mvpp2_port_remove(priv->port_list[i]);
5903 i++;
5904 }
45f972ad 5905err_axi_clk:
4792ea04 5906 clk_disable_unprepare(priv->axi_clk);
9af771ce
MC		 5907
5908err_mg_core_clk:
5909 if (priv->hw_version == MVPP22)
5910 clk_disable_unprepare(priv->mg_core_clk);
45f972ad 5911err_mg_clk:
fceb55d4
TP		 5912 if (priv->hw_version == MVPP22)
5913 clk_disable_unprepare(priv->mg_clk);
3f518509
MW		 5914err_gop_clk:
5915 clk_disable_unprepare(priv->gop_clk);
5916err_pp_clk:
5917 clk_disable_unprepare(priv->pp_clk);
5918 return err;
5919}
5920
5921static int mvpp2_remove(struct platform_device *pdev)
5922{
5923 struct mvpp2 *priv = platform_get_drvdata(pdev);
24812221
MW		 5924 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5925 struct fwnode_handle *port_fwnode;
3f518509
MW		 5926 int i = 0;
5927
21da57a2
MC		 5928 mvpp2_dbgfs_cleanup(priv);
5929
24812221 5930 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
e5c500eb
MR		 5931 if (priv->port_list[i]) {
5932 mutex_destroy(&priv->port_list[i]->gather_stats_lock);
3f518509 5933 mvpp2_port_remove(priv->port_list[i]);
e5c500eb 5934 }
3f518509
MW		 5935 i++;
5936 }
5937
944a83a2
MC		 5938 destroy_workqueue(priv->stats_queue);
5939
3f518509
MW		 5940 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5941 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
5942
13616361 5943 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool);
3f518509
MW		 5944 }
5945
074c74df 5946 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
3f518509
MW		 5947 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
5948
5949 dma_free_coherent(&pdev->dev,
5950 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
5951 aggr_txq->descs,
20396136 5952 aggr_txq->descs_dma);
3f518509
MW		 5953 }
5954
a75edc7c
MW		 5955 if (is_acpi_node(port_fwnode))
5956 return 0;
5957
4792ea04 5958 clk_disable_unprepare(priv->axi_clk);
9af771ce 5959 clk_disable_unprepare(priv->mg_core_clk);
fceb55d4 5960 clk_disable_unprepare(priv->mg_clk);
3f518509
MW		 5961 clk_disable_unprepare(priv->pp_clk);
5962 clk_disable_unprepare(priv->gop_clk);
5963
5964 return 0;
5965}
5966
5967static const struct of_device_id mvpp2_match[] = {
faca9247
TP		 5968 {
5969 .compatible = "marvell,armada-375-pp2",
5970 .data = (void *)MVPP21,
5971 },
fc5e1550
TP		 5972 {
5973 .compatible = "marvell,armada-7k-pp22",
5974 .data = (void *)MVPP22,
5975 },
3f518509
MW		 5976 { }
5977};
5978MODULE_DEVICE_TABLE(of, mvpp2_match);
5979
a75edc7c
MW		 5980static const struct acpi_device_id mvpp2_acpi_match[] = {
5981 { "MRVL0110", MVPP22 },
5982 { },
5983};
5984MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
5985
3f518509
MW		 5986static struct platform_driver mvpp2_driver = {
5987 .probe = mvpp2_probe,
5988 .remove = mvpp2_remove,
5989 .driver = {
5990 .name = MVPP2_DRIVER_NAME,
5991 .of_match_table = mvpp2_match,
a75edc7c 5992 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
3f518509
MW		 5993 },
5994};
5995
5996module_platform_driver(mvpp2_driver);
5997
5998MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
5999MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
c634099d 6000MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)