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Merge branch 'for-5.4/apple' into for-linus
[linux-2.6-block.git] / drivers / net / ethernet / marvell / mvpp2 / mvpp2_main.c
CommitLineData
f1e37e31 1// SPDX-License-Identifier: GPL-2.0
3f518509
MW		 2/*
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Marcin Wojtas <mw@semihalf.com>
3f518509
MW		 8 */
9
a75edc7c 10#include <linux/acpi.h>
3f518509
MW		 11#include <linux/kernel.h>
12#include <linux/netdevice.h>
13#include <linux/etherdevice.h>
14#include <linux/platform_device.h>
15#include <linux/skbuff.h>
16#include <linux/inetdevice.h>
17#include <linux/mbus.h>
18#include <linux/module.h>
f84bf386 19#include <linux/mfd/syscon.h>
3f518509
MW		 20#include <linux/interrupt.h>
21#include <linux/cpumask.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_mdio.h>
25#include <linux/of_net.h>
26#include <linux/of_address.h>
faca9247 27#include <linux/of_device.h>
3f518509 28#include <linux/phy.h>
4bb04326 29#include <linux/phylink.h>
542897d9 30#include <linux/phy/phy.h>
3f518509 31#include <linux/clk.h>
edc660fa
MW		 32#include <linux/hrtimer.h>
33#include <linux/ktime.h>
f84bf386 34#include <linux/regmap.h>
3f518509
MW		 35#include <uapi/linux/ppp_defs.h>
36#include <net/ip.h>
37#include <net/ipv6.h>
186cd4d4 38#include <net/tso.h>
3f518509 39
db9d7d36
MC		 40#include "mvpp2.h"
41#include "mvpp2_prs.h"
42#include "mvpp2_cls.h"
a786841d 43
01d04936
SC		 44enum mvpp2_bm_pool_log_num {
45 MVPP2_BM_SHORT,
46 MVPP2_BM_LONG,
576193f2 47 MVPP2_BM_JUMBO,
01d04936 48 MVPP2_BM_POOLS_NUM
3f518509
MW		 49};
50
db9d7d36
MC		 51static struct {
52 int pkt_size;
53 int buf_num;
54} mvpp2_pools[MVPP2_BM_POOLS_NUM];
3f518509 55
db9d7d36
MC		 56/* The prototype is added here to be used in start_dev when using ACPI. This
57 * will be removed once phylink is used for all modes (dt+ACPI).
58 */
44cc27e4 59static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
db9d7d36 60 const struct phylink_link_state *state);
44cc27e4 61static void mvpp2_mac_link_up(struct phylink_config *config, unsigned int mode,
41948ccb 62 phy_interface_t interface, struct phy_device *phy);
10fea26c 63
db9d7d36
MC		 64/* Queue modes */
65#define MVPP2_QDIST_SINGLE_MODE 0
66#define MVPP2_QDIST_MULTI_MODE 1
3f518509 67
3f6aaf72 68static int queue_mode = MVPP2_QDIST_MULTI_MODE;
3f518509 69
db9d7d36
MC		 70module_param(queue_mode, int, 0444);
71MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
3f518509 72
db9d7d36 73/* Utility/helper methods */
3f518509 74
db9d7d36
MC		 75void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
76{
77 writel(data, priv->swth_base[0] + offset);
3f518509
MW		 78}
79
db9d7d36 80u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
3f518509 81{
db9d7d36 82 return readl(priv->swth_base[0] + offset);
3f518509
MW		 83}
84
16274427 85static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
3f518509 86{
db9d7d36 87 return readl_relaxed(priv->swth_base[0] + offset);
3f518509 88}
543ec376 89
e531f767 90static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
543ec376 91{
e531f767 92 return cpu % priv->nthreads;
543ec376
AT		 93}
94
db9d7d36
MC		 95/* These accessors should be used to access:
96 *
543ec376 97 * - per-thread registers, where each thread has its own copy of the
db9d7d36
MC		 98 * register.
99 *
100 * MVPP2_BM_VIRT_ALLOC_REG
101 * MVPP2_BM_ADDR_HIGH_ALLOC
102 * MVPP22_BM_ADDR_HIGH_RLS_REG
103 * MVPP2_BM_VIRT_RLS_REG
104 * MVPP2_ISR_RX_TX_CAUSE_REG
105 * MVPP2_ISR_RX_TX_MASK_REG
106 * MVPP2_TXQ_NUM_REG
107 * MVPP2_AGGR_TXQ_UPDATE_REG
108 * MVPP2_TXQ_RSVD_REQ_REG
109 * MVPP2_TXQ_RSVD_RSLT_REG
110 * MVPP2_TXQ_SENT_REG
111 * MVPP2_RXQ_NUM_REG
112 *
543ec376
AT		 113 * - global registers that must be accessed through a specific thread
114 * window, because they are related to an access to a per-thread
db9d7d36
MC		 115 * register
116 *
117 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG)
118 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG)
119 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG)
120 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG)
121 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG)
122 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG)
123 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
124 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG)
125 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG)
126 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG)
127 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
128 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
129 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
130 */
1068549c 131static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
db9d7d36
MC		 132 u32 offset, u32 data)
133{
543ec376 134 writel(data, priv->swth_base[thread] + offset);
3f518509
MW		 135}
136
1068549c 137static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
db9d7d36 138 u32 offset)
3f518509 139{
543ec376 140 return readl(priv->swth_base[thread] + offset);
db9d7d36 141}
3f518509 142
1068549c 143static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
db9d7d36
MC		 144 u32 offset, u32 data)
145{
543ec376 146 writel_relaxed(data, priv->swth_base[thread] + offset);
db9d7d36 147}
0c6d9b44 148
1068549c 149static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
db9d7d36
MC		 150 u32 offset)
151{
543ec376 152 return readl_relaxed(priv->swth_base[thread] + offset);
db9d7d36 153}
3f518509 154
db9d7d36
MC		 155static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
156 struct mvpp2_tx_desc *tx_desc)
157{
158 if (port->priv->hw_version == MVPP21)
7b9c7d7d 159 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
db9d7d36 160 else
7b9c7d7d
MC		 161 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
162 MVPP2_DESC_DMA_MASK;
db9d7d36 163}
3f518509 164
db9d7d36
MC		 165static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
166 struct mvpp2_tx_desc *tx_desc,
167 dma_addr_t dma_addr)
168{
169 dma_addr_t addr, offset;
3f518509 170
db9d7d36
MC		 171 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
172 offset = dma_addr & MVPP2_TX_DESC_ALIGN;
3f518509 173
db9d7d36 174 if (port->priv->hw_version == MVPP21) {
7b9c7d7d 175 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
db9d7d36 176 tx_desc->pp21.packet_offset = offset;
0c6d9b44 177 } else {
7b9c7d7d 178 __le64 val = cpu_to_le64(addr);
3f518509 179
7b9c7d7d 180 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
db9d7d36
MC		 181 tx_desc->pp22.buf_dma_addr_ptp |= val;
182 tx_desc->pp22.packet_offset = offset;
183 }
3f518509
MW		 184}
185
db9d7d36
MC		 186static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
187 struct mvpp2_tx_desc *tx_desc)
3f518509 188{
db9d7d36 189 if (port->priv->hw_version == MVPP21)
7b9c7d7d 190 return le16_to_cpu(tx_desc->pp21.data_size);
db9d7d36 191 else
7b9c7d7d 192 return le16_to_cpu(tx_desc->pp22.data_size);
3f518509
MW		 193}
194
db9d7d36
MC		 195static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
196 struct mvpp2_tx_desc *tx_desc,
197 size_t size)
3f518509 198{
db9d7d36 199 if (port->priv->hw_version == MVPP21)
7b9c7d7d 200 tx_desc->pp21.data_size = cpu_to_le16(size);
db9d7d36 201 else
7b9c7d7d 202 tx_desc->pp22.data_size = cpu_to_le16(size);
3f518509
MW		 203}
204
db9d7d36
MC		 205static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
206 struct mvpp2_tx_desc *tx_desc,
207 unsigned int txq)
3f518509 208{
db9d7d36
MC		 209 if (port->priv->hw_version == MVPP21)
210 tx_desc->pp21.phys_txq = txq;
211 else
212 tx_desc->pp22.phys_txq = txq;
3f518509
MW		 213}
214
db9d7d36
MC		 215static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
216 struct mvpp2_tx_desc *tx_desc,
217 unsigned int command)
3f518509 218{
db9d7d36 219 if (port->priv->hw_version == MVPP21)
7b9c7d7d 220 tx_desc->pp21.command = cpu_to_le32(command);
db9d7d36 221 else
7b9c7d7d 222 tx_desc->pp22.command = cpu_to_le32(command);
db9d7d36 223}
3f518509 224
db9d7d36
MC		 225static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
226 struct mvpp2_tx_desc *tx_desc)
227{
228 if (port->priv->hw_version == MVPP21)
229 return tx_desc->pp21.packet_offset;
230 else
231 return tx_desc->pp22.packet_offset;
232}
3f518509 233
db9d7d36
MC		 234static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
235 struct mvpp2_rx_desc *rx_desc)
236{
237 if (port->priv->hw_version == MVPP21)
7b9c7d7d 238 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
db9d7d36 239 else
7b9c7d7d
MC		 240 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
241 MVPP2_DESC_DMA_MASK;
db9d7d36 242}
3f518509 243
db9d7d36
MC		 244static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
245 struct mvpp2_rx_desc *rx_desc)
246{
247 if (port->priv->hw_version == MVPP21)
7b9c7d7d 248 return le32_to_cpu(rx_desc->pp21.buf_cookie);
db9d7d36 249 else
7b9c7d7d
MC		 250 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
251 MVPP2_DESC_DMA_MASK;
db9d7d36 252}
3f518509 253
db9d7d36
MC		 254static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
255 struct mvpp2_rx_desc *rx_desc)
256{
257 if (port->priv->hw_version == MVPP21)
7b9c7d7d 258 return le16_to_cpu(rx_desc->pp21.data_size);
db9d7d36 259 else
7b9c7d7d 260 return le16_to_cpu(rx_desc->pp22.data_size);
db9d7d36 261}
3f518509 262
db9d7d36
MC		 263static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
264 struct mvpp2_rx_desc *rx_desc)
265{
266 if (port->priv->hw_version == MVPP21)
7b9c7d7d 267 return le32_to_cpu(rx_desc->pp21.status);
db9d7d36 268 else
7b9c7d7d 269 return le32_to_cpu(rx_desc->pp22.status);
3f518509
MW		 270}
271
db9d7d36 272static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
3f518509 273{
db9d7d36
MC		 274 txq_pcpu->txq_get_index++;
275 if (txq_pcpu->txq_get_index == txq_pcpu->size)
276 txq_pcpu->txq_get_index = 0;
277}
3f518509 278
db9d7d36
MC		 279static void mvpp2_txq_inc_put(struct mvpp2_port *port,
280 struct mvpp2_txq_pcpu *txq_pcpu,
281 struct sk_buff *skb,
282 struct mvpp2_tx_desc *tx_desc)
283{
284 struct mvpp2_txq_pcpu_buf *tx_buf =
285 txq_pcpu->buffs + txq_pcpu->txq_put_index;
286 tx_buf->skb = skb;
287 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
288 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
289 mvpp2_txdesc_offset_get(port, tx_desc);
290 txq_pcpu->txq_put_index++;
291 if (txq_pcpu->txq_put_index == txq_pcpu->size)
292 txq_pcpu->txq_put_index = 0;
293}
3f518509 294
db9d7d36
MC		 295/* Get number of physical egress port */
296static inline int mvpp2_egress_port(struct mvpp2_port *port)
297{
298 return MVPP2_MAX_TCONT + port->id;
299}
3f518509 300
db9d7d36
MC		 301/* Get number of physical TXQ */
302static inline int mvpp2_txq_phys(int port, int txq)
303{
304 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
3f518509
MW		 305}
306
0e037281
TP		 307static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool)
308{
309 if (likely(pool->frag_size <= PAGE_SIZE))
310 return netdev_alloc_frag(pool->frag_size);
311 else
312 return kmalloc(pool->frag_size, GFP_ATOMIC);
313}
314
315static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data)
316{
317 if (likely(pool->frag_size <= PAGE_SIZE))
318 skb_free_frag(data);
319 else
320 kfree(data);
321}
322
3f518509
MW		 323/* Buffer Manager configuration routines */
324
325/* Create pool */
326static int mvpp2_bm_pool_create(struct platform_device *pdev,
327 struct mvpp2 *priv,
328 struct mvpp2_bm_pool *bm_pool, int size)
329{
3f518509
MW		 330 u32 val;
331
d01524d8
TP		 332 /* Number of buffer pointers must be a multiple of 16, as per
333 * hardware constraints
334 */
335 if (!IS_ALIGNED(size, 16))
336 return -EINVAL;
337
338 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
339 * bytes per buffer pointer
340 */
341 if (priv->hw_version == MVPP21)
342 bm_pool->size_bytes = 2 * sizeof(u32) * size;
343 else
344 bm_pool->size_bytes = 2 * sizeof(u64) * size;
345
346 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes,
20396136 347 &bm_pool->dma_addr,
3f518509
MW		 348 GFP_KERNEL);
349 if (!bm_pool->virt_addr)
350 return -ENOMEM;
351
d3158807
TP		 352 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
353 MVPP2_BM_POOL_PTR_ALIGN)) {
d01524d8
TP		 354 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
355 bm_pool->virt_addr, bm_pool->dma_addr);
3f518509
MW		 356 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
357 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
358 return -ENOMEM;
359 }
360
361 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
d01524d8 362 lower_32_bits(bm_pool->dma_addr));
3f518509
MW		 363 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
364
365 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
366 val |= MVPP2_BM_START_MASK;
367 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
368
3f518509
MW		 369 bm_pool->size = size;
370 bm_pool->pkt_size = 0;
371 bm_pool->buf_num = 0;
3f518509
MW		 372
373 return 0;
374}
375
376/* Set pool buffer size */
377static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
378 struct mvpp2_bm_pool *bm_pool,
379 int buf_size)
380{
381 u32 val;
382
383 bm_pool->buf_size = buf_size;
384
385 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
386 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
387}
388
d01524d8
TP		 389static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
390 struct mvpp2_bm_pool *bm_pool,
391 dma_addr_t *dma_addr,
392 phys_addr_t *phys_addr)
393{
e531f767 394 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
a786841d 395
1068549c 396 *dma_addr = mvpp2_thread_read(priv, thread,
a786841d 397 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
1068549c 398 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
d01524d8
TP		 399
400 if (priv->hw_version == MVPP22) {
401 u32 val;
402 u32 dma_addr_highbits, phys_addr_highbits;
403
1068549c 404 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
d01524d8
TP		 405 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
406 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
407 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
408
409 if (sizeof(dma_addr_t) == 8)
410 *dma_addr |= (u64)dma_addr_highbits << 32;
411
412 if (sizeof(phys_addr_t) == 8)
413 *phys_addr |= (u64)phys_addr_highbits << 32;
414 }
a704bb5c
TP		 415
416 put_cpu();
d01524d8
TP		 417}
418
7861f12b 419/* Free all buffers from the pool */
4229d502 420static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
effbf5f5 421 struct mvpp2_bm_pool *bm_pool, int buf_num)
3f518509
MW		 422{
423 int i;
424
effbf5f5
SC		 425 if (buf_num > bm_pool->buf_num) {
426 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
427 bm_pool->id, buf_num);
428 buf_num = bm_pool->buf_num;
429 }
430
431 for (i = 0; i < buf_num; i++) {
20396136 432 dma_addr_t buf_dma_addr;
4e4a105f
TP		 433 phys_addr_t buf_phys_addr;
434 void *data;
3f518509 435
d01524d8
TP		 436 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
437 &buf_dma_addr, &buf_phys_addr);
4229d502 438
20396136 439 dma_unmap_single(dev, buf_dma_addr,
4229d502
MW		 440 bm_pool->buf_size, DMA_FROM_DEVICE);
441
4e4a105f
TP		 442 data = (void *)phys_to_virt(buf_phys_addr);
443 if (!data)
3f518509 444 break;
0e037281 445
4e4a105f 446 mvpp2_frag_free(bm_pool, data);
3f518509
MW		 447 }
448
449 /* Update BM driver with number of buffers removed from pool */
450 bm_pool->buf_num -= i;
3f518509
MW		 451}
452
effbf5f5 453/* Check number of buffers in BM pool */
6e61e10a 454static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
effbf5f5
SC		 455{
456 int buf_num = 0;
457
458 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
459 MVPP22_BM_POOL_PTRS_NUM_MASK;
460 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
461 MVPP2_BM_BPPI_PTR_NUM_MASK;
462
463 /* HW has one buffer ready which is not reflected in the counters */
464 if (buf_num)
465 buf_num += 1;
466
467 return buf_num;
468}
469
3f518509
MW		 470/* Cleanup pool */
471static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
472 struct mvpp2 *priv,
473 struct mvpp2_bm_pool *bm_pool)
474{
effbf5f5 475 int buf_num;
3f518509
MW		 476 u32 val;
477
effbf5f5
SC		 478 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
479 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num);
480
481 /* Check buffer counters after free */
482 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
483 if (buf_num) {
484 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
485 bm_pool->id, bm_pool->buf_num);
3f518509
MW		 486 return 0;
487 }
488
489 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
490 val |= MVPP2_BM_STOP_MASK;
491 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
492
d01524d8 493 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
3f518509 494 bm_pool->virt_addr,
20396136 495 bm_pool->dma_addr);
3f518509
MW		 496 return 0;
497}
498
499static int mvpp2_bm_pools_init(struct platform_device *pdev,
500 struct mvpp2 *priv)
501{
502 int i, err, size;
503 struct mvpp2_bm_pool *bm_pool;
504
505 /* Create all pools with maximum size */
506 size = MVPP2_BM_POOL_SIZE_MAX;
507 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
508 bm_pool = &priv->bm_pools[i];
509 bm_pool->id = i;
510 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size);
511 if (err)
512 goto err_unroll_pools;
513 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
514 }
515 return 0;
516
517err_unroll_pools:
518 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
519 for (i = i - 1; i >= 0; i--)
520 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]);
521 return err;
522}
523
524static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
525{
526 int i, err;
527
528 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
529 /* Mask BM all interrupts */
530 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
531 /* Clear BM cause register */
532 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
533 }
534
535 /* Allocate and initialize BM pools */
536 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM,
81f915eb 537 sizeof(*priv->bm_pools), GFP_KERNEL);
3f518509
MW		 538 if (!priv->bm_pools)
539 return -ENOMEM;
540
541 err = mvpp2_bm_pools_init(pdev, priv);
542 if (err < 0)
543 return err;
544 return 0;
545}
546
01d04936
SC		 547static void mvpp2_setup_bm_pool(void)
548{
549 /* Short pool */
550 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM;
551 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
552
553 /* Long pool */
554 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM;
555 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
576193f2
SC		 556
557 /* Jumbo pool */
558 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM;
559 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
01d04936
SC		 560}
561
3f518509
MW		 562/* Attach long pool to rxq */
563static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
564 int lrxq, int long_pool)
565{
5eac892a 566 u32 val, mask;
3f518509
MW		 567 int prxq;
568
569 /* Get queue physical ID */
570 prxq = port->rxqs[lrxq]->id;
571
5eac892a
TP		 572 if (port->priv->hw_version == MVPP21)
573 mask = MVPP21_RXQ_POOL_LONG_MASK;
574 else
575 mask = MVPP22_RXQ_POOL_LONG_MASK;
3f518509 576
5eac892a
TP		 577 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
578 val &= ~mask;
579 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
3f518509
MW		 580 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
581}
582
583/* Attach short pool to rxq */
584static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
585 int lrxq, int short_pool)
586{
5eac892a 587 u32 val, mask;
3f518509
MW		 588 int prxq;
589
590 /* Get queue physical ID */
591 prxq = port->rxqs[lrxq]->id;
592
5eac892a
TP		 593 if (port->priv->hw_version == MVPP21)
594 mask = MVPP21_RXQ_POOL_SHORT_MASK;
595 else
596 mask = MVPP22_RXQ_POOL_SHORT_MASK;
3f518509 597
5eac892a
TP		 598 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
599 val &= ~mask;
600 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
3f518509
MW		 601 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
602}
603
0e037281
TP		 604static void *mvpp2_buf_alloc(struct mvpp2_port *port,
605 struct mvpp2_bm_pool *bm_pool,
20396136 606 dma_addr_t *buf_dma_addr,
4e4a105f 607 phys_addr_t *buf_phys_addr,
0e037281 608 gfp_t gfp_mask)
3f518509 609{
20396136 610 dma_addr_t dma_addr;
0e037281 611 void *data;
3f518509 612
0e037281
TP		 613 data = mvpp2_frag_alloc(bm_pool);
614 if (!data)
3f518509
MW		 615 return NULL;
616
20396136
TP		 617 dma_addr = dma_map_single(port->dev->dev.parent, data,
618 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
619 DMA_FROM_DEVICE);
620 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
0e037281 621 mvpp2_frag_free(bm_pool, data);
3f518509
MW		 622 return NULL;
623 }
20396136 624 *buf_dma_addr = dma_addr;
4e4a105f 625 *buf_phys_addr = virt_to_phys(data);
3f518509 626
0e037281 627 return data;
3f518509
MW		 628}
629
3f518509
MW		 630/* Release buffer to BM */
631static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
20396136 632 dma_addr_t buf_dma_addr,
4e4a105f 633 phys_addr_t buf_phys_addr)
3f518509 634{
e531f767
AT		 635 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
636 unsigned long flags = 0;
637
638 if (test_bit(thread, &port->priv->lock_map))
639 spin_lock_irqsave(&port->bm_lock[thread], flags);
a786841d 640
d01524d8
TP		 641 if (port->priv->hw_version == MVPP22) {
642 u32 val = 0;
643
644 if (sizeof(dma_addr_t) == 8)
645 val |= upper_32_bits(buf_dma_addr) &
646 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
647
648 if (sizeof(phys_addr_t) == 8)
649 val |= (upper_32_bits(buf_phys_addr)
650 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
651 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
652
1068549c 653 mvpp2_thread_write_relaxed(port->priv, thread,
cdcfeb0f 654 MVPP22_BM_ADDR_HIGH_RLS_REG, val);
d01524d8
TP		 655 }
656
4e4a105f
TP		 657 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
658 * returned in the "cookie" field of the RX
659 * descriptor. Instead of storing the virtual address, we
660 * store the physical address
661 */
1068549c 662 mvpp2_thread_write_relaxed(port->priv, thread,
cdcfeb0f 663 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
1068549c 664 mvpp2_thread_write_relaxed(port->priv, thread,
cdcfeb0f 665 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
a704bb5c 666
e531f767
AT		 667 if (test_bit(thread, &port->priv->lock_map))
668 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
669
a704bb5c 670 put_cpu();
3f518509
MW		 671}
672
3f518509
MW		 673/* Allocate buffers for the pool */
674static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
675 struct mvpp2_bm_pool *bm_pool, int buf_num)
676{
3f518509 677 int i, buf_size, total_size;
20396136 678 dma_addr_t dma_addr;
4e4a105f 679 phys_addr_t phys_addr;
0e037281 680 void *buf;
3f518509
MW		 681
682 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
683 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
684
685 if (buf_num < 0 ||
686 (buf_num + bm_pool->buf_num > bm_pool->size)) {
687 netdev_err(port->dev,
688 "cannot allocate %d buffers for pool %d\n",
689 buf_num, bm_pool->id);
690 return 0;
691 }
692
3f518509 693 for (i = 0; i < buf_num; i++) {
4e4a105f
TP		 694 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr,
695 &phys_addr, GFP_KERNEL);
0e037281 696 if (!buf)
3f518509
MW		 697 break;
698
20396136 699 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
4e4a105f 700 phys_addr);
3f518509
MW		 701 }
702
703 /* Update BM driver with number of buffers added to pool */
704 bm_pool->buf_num += i;
3f518509
MW		 705
706 netdev_dbg(port->dev,
01d04936 707 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
3f518509
MW		 708 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
709
710 netdev_dbg(port->dev,
01d04936 711 "pool %d: %d of %d buffers added\n",
3f518509
MW		 712 bm_pool->id, i, buf_num);
713 return i;
714}
715
716/* Notify the driver that BM pool is being used as specific type and return the
717 * pool pointer on success
718 */
719static struct mvpp2_bm_pool *
01d04936 720mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
3f518509 721{
3f518509
MW		 722 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
723 int num;
724
01d04936
SC		 725 if (pool >= MVPP2_BM_POOLS_NUM) {
726 netdev_err(port->dev, "Invalid pool %d\n", pool);
3f518509
MW		 727 return NULL;
728 }
729
3f518509
MW		 730 /* Allocate buffers in case BM pool is used as long pool, but packet
731 * size doesn't match MTU or BM pool hasn't being used yet
732 */
01d04936 733 if (new_pool->pkt_size == 0) {
3f518509
MW		 734 int pkts_num;
735
736 /* Set default buffer number or free all the buffers in case
737 * the pool is not empty
738 */
739 pkts_num = new_pool->buf_num;
740 if (pkts_num == 0)
01d04936 741 pkts_num = mvpp2_pools[pool].buf_num;
3f518509 742 else
4229d502 743 mvpp2_bm_bufs_free(port->dev->dev.parent,
effbf5f5 744 port->priv, new_pool, pkts_num);
3f518509
MW		 745
746 new_pool->pkt_size = pkt_size;
0e037281
TP		 747 new_pool->frag_size =
748 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
749 MVPP2_SKB_SHINFO_SIZE;
3f518509
MW		 750
751 /* Allocate buffers for this pool */
752 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
753 if (num != pkts_num) {
754 WARN(1, "pool %d: %d of %d allocated\n",
755 new_pool->id, num, pkts_num);
3f518509
MW		 756 return NULL;
757 }
758 }
759
760 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
761 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
762
3f518509
MW		 763 return new_pool;
764}
765
766/* Initialize pools for swf */
767static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
768{
3f518509 769 int rxq;
576193f2
SC		 770 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
771
772 /* If port pkt_size is higher than 1518B:
773 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
774 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
775 */
776 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
777 long_log_pool = MVPP2_BM_JUMBO;
778 short_log_pool = MVPP2_BM_LONG;
779 } else {
780 long_log_pool = MVPP2_BM_LONG;
781 short_log_pool = MVPP2_BM_SHORT;
782 }
3f518509
MW		 783
784 if (!port->pool_long) {
785 port->pool_long =
576193f2
SC		 786 mvpp2_bm_pool_use(port, long_log_pool,
787 mvpp2_pools[long_log_pool].pkt_size);
3f518509
MW		 788 if (!port->pool_long)
789 return -ENOMEM;
790
576193f2 791 port->pool_long->port_map |= BIT(port->id);
3f518509 792
09f83975 793 for (rxq = 0; rxq < port->nrxqs; rxq++)
3f518509
MW		 794 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
795 }
796
797 if (!port->pool_short) {
798 port->pool_short =
576193f2 799 mvpp2_bm_pool_use(port, short_log_pool,
e2e03164 800 mvpp2_pools[short_log_pool].pkt_size);
3f518509
MW		 801 if (!port->pool_short)
802 return -ENOMEM;
803
576193f2 804 port->pool_short->port_map |= BIT(port->id);
3f518509 805
09f83975 806 for (rxq = 0; rxq < port->nrxqs; rxq++)
3f518509
MW		 807 mvpp2_rxq_short_pool_set(port, rxq,
808 port->pool_short->id);
809 }
810
811 return 0;
812}
813
d66503c4
MC		 814static void mvpp2_set_hw_csum(struct mvpp2_port *port,
815 enum mvpp2_bm_pool_log_num new_long_pool)
816{
817 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
818
819 /* Update L4 checksum when jumbo enable/disable on port.
820 * Only port 0 supports hardware checksum offload due to
821 * the Tx FIFO size limitation.
822 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor
823 * has 7 bits, so the maximum L3 offset is 128.
824 */
825 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
826 port->dev->features &= ~csums;
827 port->dev->hw_features &= ~csums;
828 } else {
829 port->dev->features |= csums;
830 port->dev->hw_features |= csums;
831 }
832}
833
3f518509
MW		 834static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
835{
836 struct mvpp2_port *port = netdev_priv(dev);
576193f2
SC		 837 enum mvpp2_bm_pool_log_num new_long_pool;
838 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3f518509 839
576193f2
SC		 840 /* If port MTU is higher than 1518B:
841 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
842 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
843 */
844 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
845 new_long_pool = MVPP2_BM_JUMBO;
846 else
847 new_long_pool = MVPP2_BM_LONG;
848
849 if (new_long_pool != port->pool_long->id) {
850 /* Remove port from old short & long pool */
851 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
852 port->pool_long->pkt_size);
853 port->pool_long->port_map &= ~BIT(port->id);
854 port->pool_long = NULL;
855
856 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
857 port->pool_short->pkt_size);
858 port->pool_short->port_map &= ~BIT(port->id);
859 port->pool_short = NULL;
860
861 port->pkt_size = pkt_size;
862
863 /* Add port to new short & long pool */
864 mvpp2_swf_bm_pool_init(port);
865
d66503c4 866 mvpp2_set_hw_csum(port, new_long_pool);
3f518509
MW		 867 }
868
3f518509 869 dev->mtu = mtu;
576193f2
SC		 870 dev->wanted_features = dev->features;
871
3f518509
MW		 872 netdev_update_features(dev);
873 return 0;
874}
875
876static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
877{
591f4cfa
TP		 878 int i, sw_thread_mask = 0;
879
880 for (i = 0; i < port->nqvecs; i++)
881 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
3f518509 882
3f518509 883 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
591f4cfa 884 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
3f518509
MW		 885}
886
887static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
888{
591f4cfa
TP		 889 int i, sw_thread_mask = 0;
890
891 for (i = 0; i < port->nqvecs; i++)
892 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
893
894 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
895 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
896}
897
898static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
899{
900 struct mvpp2_port *port = qvec->port;
3f518509 901
3f518509 902 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
591f4cfa
TP		 903 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
904}
905
906static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
907{
908 struct mvpp2_port *port = qvec->port;
909
910 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
911 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
3f518509
MW		 912}
913
543ec376 914/* Mask the current thread's Rx/Tx interrupts
e0af22d9
TP		 915 * Called by on_each_cpu(), guaranteed to run with migration disabled,
916 * using smp_processor_id() is OK.
917 */
3f518509
MW		 918static void mvpp2_interrupts_mask(void *arg)
919{
920 struct mvpp2_port *port = arg;
921
e531f767
AT		 922 /* If the thread isn't used, don't do anything */
923 if (smp_processor_id() > port->priv->nthreads)
924 return;
925
1068549c 926 mvpp2_thread_write(port->priv,
e531f767 927 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
a786841d 928 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
3f518509
MW		 929}
930
543ec376 931/* Unmask the current thread's Rx/Tx interrupts.
e0af22d9
TP		 932 * Called by on_each_cpu(), guaranteed to run with migration disabled,
933 * using smp_processor_id() is OK.
934 */
3f518509
MW		 935static void mvpp2_interrupts_unmask(void *arg)
936{
937 struct mvpp2_port *port = arg;
213f428f
TP		 938 u32 val;
939
e531f767
AT		 940 /* If the thread isn't used, don't do anything */
941 if (smp_processor_id() > port->priv->nthreads)
942 return;
943
213f428f 944 val = MVPP2_CAUSE_MISC_SUM_MASK |
70afb58e 945 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
213f428f
TP		 946 if (port->has_tx_irqs)
947 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3f518509 948
1068549c 949 mvpp2_thread_write(port->priv,
e531f767 950 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
213f428f
TP		 951 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
952}
953
954static void
955mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
956{
957 u32 val;
958 int i;
959
960 if (port->priv->hw_version != MVPP22)
961 return;
962
963 if (mask)
964 val = 0;
965 else
70afb58e 966 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
213f428f
TP		 967
968 for (i = 0; i < port->nqvecs; i++) {
969 struct mvpp2_queue_vector *v = port->qvecs + i;
970
971 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
972 continue;
973
1068549c 974 mvpp2_thread_write(port->priv, v->sw_thread_id,
213f428f
TP		 975 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
976 }
3f518509
MW		 977}
978
979/* Port configuration routines */
b7d286f0
RK		 980static bool mvpp2_is_xlg(phy_interface_t interface)
981{
982 return interface == PHY_INTERFACE_MODE_10GKR ||
983 interface == PHY_INTERFACE_MODE_XAUI;
984}
3f518509 985
f84bf386
AT		 986static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
987{
988 struct mvpp2 *priv = port->priv;
989 u32 val;
990
991 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
992 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
993 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
994
995 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
996 if (port->gop_id == 2)
997 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;
998 else if (port->gop_id == 3)
999 val |= GENCONF_CTRL0_PORT1_RGMII_MII;
1000 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1001}
1002
1003static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
1004{
1005 struct mvpp2 *priv = port->priv;
1006 u32 val;
1007
1008 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1009 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
1010 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
1011 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1012
1013 if (port->gop_id > 1) {
1014 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1015 if (port->gop_id == 2)
1016 val &= ~GENCONF_CTRL0_PORT0_RGMII;
1017 else if (port->gop_id == 3)
1018 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
1019 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1020 }
1021}
1022
1023static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1024{
1025 struct mvpp2 *priv = port->priv;
1026 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1027 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1028 u32 val;
1029
f84bf386
AT		 1030 val = readl(xpcs + MVPP22_XPCS_CFG0);
1031 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1032 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1033 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1034 writel(val, xpcs + MVPP22_XPCS_CFG0);
1035
f84bf386
AT		 1036 val = readl(mpcs + MVPP22_MPCS_CTRL);
1037 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1038 writel(val, mpcs + MVPP22_MPCS_CTRL);
1039
1040 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
7409e66e 1041 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7);
f84bf386
AT		 1042 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1043 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
f84bf386
AT		 1044}
1045
1046static int mvpp22_gop_init(struct mvpp2_port *port)
1047{
1048 struct mvpp2 *priv = port->priv;
1049 u32 val;
1050
1051 if (!priv->sysctrl_base)
1052 return 0;
1053
1054 switch (port->phy_interface) {
1055 case PHY_INTERFACE_MODE_RGMII:
1056 case PHY_INTERFACE_MODE_RGMII_ID:
1057 case PHY_INTERFACE_MODE_RGMII_RXID:
1058 case PHY_INTERFACE_MODE_RGMII_TXID:
1059 if (port->gop_id == 0)
1060 goto invalid_conf;
1061 mvpp22_gop_init_rgmii(port);
1062 break;
1063 case PHY_INTERFACE_MODE_SGMII:
d97c9f4a 1064 case PHY_INTERFACE_MODE_1000BASEX:
a6fe31de 1065 case PHY_INTERFACE_MODE_2500BASEX:
f84bf386
AT		 1066 mvpp22_gop_init_sgmii(port);
1067 break;
1068 case PHY_INTERFACE_MODE_10GKR:
1069 if (port->gop_id != 0)
1070 goto invalid_conf;
1071 mvpp22_gop_init_10gkr(port);
1072 break;
1073 default:
1074 goto unsupported_conf;
1075 }
1076
1077 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1078 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1079 GENCONF_PORT_CTRL1_EN(port->gop_id);
1080 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1081
1082 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1083 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1084 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1085
1086 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1087 val |= GENCONF_SOFT_RESET1_GOP;
1088 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1089
1090unsupported_conf:
1091 return 0;
1092
1093invalid_conf:
1094 netdev_err(port->dev, "Invalid port configuration\n");
1095 return -EINVAL;
1096}
1097
fd3651b2
AT		 1098static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1099{
1100 u32 val;
1101
1102 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
4a4cec72
RK		 1103 phy_interface_mode_is_8023z(port->phy_interface) ||
1104 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
fd3651b2
AT		 1105 /* Enable the GMAC link status irq for this port */
1106 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1107 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1108 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1109 }
1110
1111 if (port->gop_id == 0) {
1112 /* Enable the XLG/GIG irqs for this port */
1113 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1d9b041e 1114 if (mvpp2_is_xlg(port->phy_interface))
fd3651b2
AT		 1115 val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1116 else
1117 val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1118 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1119 }
1120}
1121
1122static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1123{
1124 u32 val;
1125
1126 if (port->gop_id == 0) {
1127 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1128 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
a3302baa 1129 MVPP22_XLG_EXT_INT_MASK_GIG);
fd3651b2
AT		 1130 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1131 }
1132
1133 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
4a4cec72
RK		 1134 phy_interface_mode_is_8023z(port->phy_interface) ||
1135 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
fd3651b2
AT		 1136 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1137 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1138 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1139 }
1140}
1141
1142static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1143{
1144 u32 val;
1145
bf2fa125
RK		 1146 if (port->phylink ||
1147 phy_interface_mode_is_rgmii(port->phy_interface) ||
4a4cec72
RK		 1148 phy_interface_mode_is_8023z(port->phy_interface) ||
1149 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
fd3651b2
AT		 1150 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1151 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1152 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1153 }
1154
1155 if (port->gop_id == 0) {
1156 val = readl(port->base + MVPP22_XLG_INT_MASK);
1157 val |= MVPP22_XLG_INT_MASK_LINK;
1158 writel(val, port->base + MVPP22_XLG_INT_MASK);
1159 }
1160
1161 mvpp22_gop_unmask_irq(port);
1162}
1163
a6fe31de
AT		 1164/* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1165 *
1166 * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1167 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1168 * differ.
1169 *
1170 * The COMPHY configures the serdes lanes regardless of the actual use of the
1171 * lanes by the physical layer. This is why configurations like
1172 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1173 */
542897d9
AT		 1174static int mvpp22_comphy_init(struct mvpp2_port *port)
1175{
542897d9
AT		 1176 int ret;
1177
1178 if (!port->comphy)
1179 return 0;
1180
cccc43b8
GS		 1181 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET,
1182 port->phy_interface);
542897d9
AT		 1183 if (ret)
1184 return ret;
1185
1186 return phy_power_on(port->comphy);
1187}
1188
3f518509
MW		 1189static void mvpp2_port_enable(struct mvpp2_port *port)
1190{
1191 u32 val;
1192
725757ae 1193 /* Only GOP port 0 has an XLG MAC */
b7d286f0 1194 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
725757ae 1195 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
649e51d5 1196 val |= MVPP22_XLG_CTRL0_PORT_EN;
725757ae
AT		 1197 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1198 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1199 } else {
1200 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1201 val |= MVPP2_GMAC_PORT_EN_MASK;
1202 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1203 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1204 }
3f518509
MW		 1205}
1206
1207static void mvpp2_port_disable(struct mvpp2_port *port)
1208{
1209 u32 val;
1210
725757ae 1211 /* Only GOP port 0 has an XLG MAC */
b7d286f0 1212 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
725757ae 1213 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4bb04326
AT		 1214 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1215 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
725757ae 1216 }
6b10bfc5
AT		 1217
1218 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1219 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1220 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3f518509
MW		 1221}
1222
1223/* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1224static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1225{
1226 u32 val;
1227
1228 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1229 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1230 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1231}
1232
1233/* Configure loopback port */
4bb04326
AT		 1234static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1235 const struct phylink_link_state *state)
3f518509
MW		 1236{
1237 u32 val;
1238
1239 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1240
4bb04326 1241 if (state->speed == 1000)
3f518509
MW		 1242 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1243 else
1244 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1245
4a4cec72
RK		 1246 if (phy_interface_mode_is_8023z(port->phy_interface) ||
1247 port->phy_interface == PHY_INTERFACE_MODE_SGMII)
3f518509
MW		 1248 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1249 else
1250 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1251
1252 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1253}
1254
118d6298
MR		 1255struct mvpp2_ethtool_counter {
1256 unsigned int offset;
1257 const char string[ETH_GSTRING_LEN];
1258 bool reg_is_64b;
1259};
1260
1261static u64 mvpp2_read_count(struct mvpp2_port *port,
1262 const struct mvpp2_ethtool_counter *counter)
1263{
1264 u64 val;
1265
1266 val = readl(port->stats_base + counter->offset);
1267 if (counter->reg_is_64b)
1268 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1269
1270 return val;
1271}
1272
9bea6897
MC		 1273/* Some counters are accessed indirectly by first writing an index to
1274 * MVPP2_CTRS_IDX. The index can represent various resources depending on the
1275 * register we access, it can be a hit counter for some classification tables,
1276 * a counter specific to a rxq, a txq or a buffer pool.
1277 */
1278static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg)
1279{
1280 mvpp2_write(priv, MVPP2_CTRS_IDX, index);
1281 return mvpp2_read(priv, reg);
1282}
1283
118d6298
MR		 1284/* Due to the fact that software statistics and hardware statistics are, by
1285 * design, incremented at different moments in the chain of packet processing,
1286 * it is very likely that incoming packets could have been dropped after being
1287 * counted by hardware but before reaching software statistics (most probably
1288 * multicast packets), and in the oppposite way, during transmission, FCS bytes
1289 * are added in between as well as TSO skb will be split and header bytes added.
1290 * Hence, statistics gathered from userspace with ifconfig (software) and
1291 * ethtool (hardware) cannot be compared.
1292 */
f9fa96b9 1293static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = {
118d6298
MR		 1294 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1295 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1296 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1297 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1298 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1299 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1300 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1301 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1302 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1303 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1304 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1305 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1306 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1307 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1308 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1309 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1310 { MVPP2_MIB_FC_SENT, "fc_sent" },
1311 { MVPP2_MIB_FC_RCVD, "fc_received" },
1312 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1313 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1314 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1315 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1316 { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1317 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1318 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1319 { MVPP2_MIB_COLLISION, "collision" },
1320 { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1321};
1322
9bea6897
MC		 1323static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = {
1324 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" },
1325 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" },
1326};
1327
1328static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = {
1329 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" },
1330 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" },
1331 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" },
1332 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" },
1333 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" },
1334 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" },
1335 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" },
1336 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" },
1337 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" },
1338};
1339
1340static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = {
1341 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" },
1342 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" },
1343 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" },
1344 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" },
1345};
1346
1347#define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \
1348 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \
1349 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \
1350 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)))
1351
118d6298
MR		 1352static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1353 u8 *data)
1354{
9bea6897
MC		 1355 struct mvpp2_port *port = netdev_priv(netdev);
1356 int i, q;
118d6298 1357
9bea6897
MC		 1358 if (sset != ETH_SS_STATS)
1359 return;
1360
1361 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) {
1362 strscpy(data, mvpp2_ethtool_mib_regs[i].string,
1363 ETH_GSTRING_LEN);
1364 data += ETH_GSTRING_LEN;
1365 }
1366
1367 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) {
1368 strscpy(data, mvpp2_ethtool_port_regs[i].string,
1369 ETH_GSTRING_LEN);
1370 data += ETH_GSTRING_LEN;
1371 }
1372
1373 for (q = 0; q < port->ntxqs; q++) {
1374 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) {
1375 snprintf(data, ETH_GSTRING_LEN,
1376 mvpp2_ethtool_txq_regs[i].string, q);
1377 data += ETH_GSTRING_LEN;
1378 }
1379 }
1380
1381 for (q = 0; q < port->nrxqs; q++) {
1382 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) {
1383 snprintf(data, ETH_GSTRING_LEN,
1384 mvpp2_ethtool_rxq_regs[i].string,
1385 q);
1386 data += ETH_GSTRING_LEN;
1387 }
118d6298
MR		 1388 }
1389}
1390
9bea6897
MC		 1391static void mvpp2_read_stats(struct mvpp2_port *port)
1392{
1393 u64 *pstats;
1394 int i, q;
1395
1396 pstats = port->ethtool_stats;
1397
1398 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++)
1399 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]);
1400
1401 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++)
1402 *pstats++ += mvpp2_read(port->priv,
1403 mvpp2_ethtool_port_regs[i].offset +
1404 4 * port->id);
1405
1406 for (q = 0; q < port->ntxqs; q++)
1407 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++)
1408 *pstats++ += mvpp2_read_index(port->priv,
1409 MVPP22_CTRS_TX_CTR(port->id, i),
1410 mvpp2_ethtool_txq_regs[i].offset);
1411
1412 /* Rxqs are numbered from 0 from the user standpoint, but not from the
1413 * driver's. We need to add the port->first_rxq offset.
1414 */
1415 for (q = 0; q < port->nrxqs; q++)
1416 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++)
1417 *pstats++ += mvpp2_read_index(port->priv,
1418 port->first_rxq + i,
1419 mvpp2_ethtool_rxq_regs[i].offset);
1420}
1421
118d6298
MR		 1422static void mvpp2_gather_hw_statistics(struct work_struct *work)
1423{
1424 struct delayed_work *del_work = to_delayed_work(work);
e5c500eb
MR		 1425 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
1426 stats_work);
118d6298 1427
e5c500eb 1428 mutex_lock(&port->gather_stats_lock);
118d6298 1429
9bea6897 1430 mvpp2_read_stats(port);
118d6298
MR		 1431
1432 /* No need to read again the counters right after this function if it
1433 * was called asynchronously by the user (ie. use of ethtool).
1434 */
e5c500eb
MR		 1435 cancel_delayed_work(&port->stats_work);
1436 queue_delayed_work(port->priv->stats_queue, &port->stats_work,
118d6298
MR		 1437 MVPP2_MIB_COUNTERS_STATS_DELAY);
1438
e5c500eb 1439 mutex_unlock(&port->gather_stats_lock);
118d6298
MR		 1440}
1441
1442static void mvpp2_ethtool_get_stats(struct net_device *dev,
1443 struct ethtool_stats *stats, u64 *data)
1444{
1445 struct mvpp2_port *port = netdev_priv(dev);
1446
e5c500eb
MR		 1447 /* Update statistics for the given port, then take the lock to avoid
1448 * concurrent accesses on the ethtool_stats structure during its copy.
1449 */
1450 mvpp2_gather_hw_statistics(&port->stats_work.work);
118d6298 1451
e5c500eb 1452 mutex_lock(&port->gather_stats_lock);
118d6298 1453 memcpy(data, port->ethtool_stats,
9bea6897 1454 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs));
e5c500eb 1455 mutex_unlock(&port->gather_stats_lock);
118d6298
MR		 1456}
1457
1458static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
1459{
9bea6897
MC		 1460 struct mvpp2_port *port = netdev_priv(dev);
1461
118d6298 1462 if (sset == ETH_SS_STATS)
9bea6897 1463 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs);
118d6298
MR		 1464
1465 return -EOPNOTSUPP;
1466}
1467
649e51d5 1468static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
3f518509 1469{
649e51d5 1470 u32 val;
118d6298 1471
316734fd
RK		 1472 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) |
1473 MVPP2_GMAC_PORT_RESET_MASK;
3f518509 1474 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
649e51d5
AT		 1475
1476 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
1477 val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
1478 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1479 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1480 }
3f518509
MW		 1481}
1482
7409e66e
AT		 1483static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
1484{
1485 struct mvpp2 *priv = port->priv;
1486 void __iomem *mpcs, *xpcs;
1487 u32 val;
1488
1489 if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
1490 return;
1491
1492 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1493 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1494
1495 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1496 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
1497 val |= MVPP22_MPCS_CLK_RESET_DIV_SET;
1498 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1499
1500 val = readl(xpcs + MVPP22_XPCS_CFG0);
1501 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
1502}
1503
1504static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
1505{
1506 struct mvpp2 *priv = port->priv;
1507 void __iomem *mpcs, *xpcs;
1508 u32 val;
1509
1510 if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
1511 return;
1512
1513 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1514 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1515
1516 switch (port->phy_interface) {
1517 case PHY_INTERFACE_MODE_10GKR:
1518 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1519 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
1520 MAC_CLK_RESET_SD_TX;
1521 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
1522 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1523 break;
1524 case PHY_INTERFACE_MODE_XAUI:
1525 case PHY_INTERFACE_MODE_RXAUI:
1526 val = readl(xpcs + MVPP22_XPCS_CFG0);
1527 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
1528 break;
1529 default:
1530 break;
1531 }
1532}
1533
3f518509
MW		 1534/* Change maximum receive size of the port */
1535static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
1536{
1537 u32 val;
1538
1539 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1540 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
1541 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1542 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
1543 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1544}
1545
76eb1b1d
SC		 1546/* Change maximum receive size of the port */
1547static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1548{
1549 u32 val;
1550
1551 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
1552 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
1553 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
ec15ecde 1554 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
76eb1b1d
SC		 1555 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
1556}
1557
3f518509
MW		 1558/* Set defaults to the MVPP2 port */
1559static void mvpp2_defaults_set(struct mvpp2_port *port)
1560{
21808437 1561 int tx_port_num, val, queue, lrxq;
3f518509 1562
3d9017d9 1563 if (port->priv->hw_version == MVPP21) {
3d9017d9
TP		 1564 /* Update TX FIFO MIN Threshold */
1565 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1566 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
1567 /* Min. TX threshold must be less than minimal packet length */
1568 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
1569 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1570 }
3f518509
MW		 1571
1572 /* Disable Legacy WRR, Disable EJP, Release from reset */
1573 tx_port_num = mvpp2_egress_port(port);
1574 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
1575 tx_port_num);
1576 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
1577
4251ea5b
MC		 1578 /* Set TXQ scheduling to Round-Robin */
1579 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
1580
3f518509 1581 /* Close bandwidth for all queues */
21808437 1582 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++)
3f518509 1583 mvpp2_write(port->priv,
21808437 1584 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
3f518509
MW		 1585
1586 /* Set refill period to 1 usec, refill tokens
1587 * and bucket size to maximum
1588 */
1589 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
1590 port->priv->tclk / USEC_PER_SEC);
1591 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
1592 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
1593 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
1594 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
1595 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
1596 val = MVPP2_TXP_TOKEN_SIZE_MAX;
1597 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1598
1599 /* Set MaximumLowLatencyPacketSize value to 256 */
1600 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
1601 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
1602 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
1603
1604 /* Enable Rx cache snoop */
09f83975 1605 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1606 queue = port->rxqs[lrxq]->id;
1607 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1608 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
1609 MVPP2_SNOOP_BUF_HDR_MASK;
1610 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1611 }
1612
1613 /* At default, mask all interrupts to all present cpus */
1614 mvpp2_interrupts_disable(port);
1615}
1616
1617/* Enable/disable receiving packets */
1618static void mvpp2_ingress_enable(struct mvpp2_port *port)
1619{
1620 u32 val;
1621 int lrxq, queue;
1622
09f83975 1623 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1624 queue = port->rxqs[lrxq]->id;
1625 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1626 val &= ~MVPP2_RXQ_DISABLE_MASK;
1627 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1628 }
1629}
1630
1631static void mvpp2_ingress_disable(struct mvpp2_port *port)
1632{
1633 u32 val;
1634 int lrxq, queue;
1635
09f83975 1636 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1637 queue = port->rxqs[lrxq]->id;
1638 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1639 val |= MVPP2_RXQ_DISABLE_MASK;
1640 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1641 }
1642}
1643
1644/* Enable transmit via physical egress queue
1645 * - HW starts take descriptors from DRAM
1646 */
1647static void mvpp2_egress_enable(struct mvpp2_port *port)
1648{
1649 u32 qmap;
1650 int queue;
1651 int tx_port_num = mvpp2_egress_port(port);
1652
1653 /* Enable all initialized TXs. */
1654 qmap = 0;
09f83975 1655 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 1656 struct mvpp2_tx_queue *txq = port->txqs[queue];
1657
dbbb2f03 1658 if (txq->descs)
3f518509
MW		 1659 qmap |= (1 << queue);
1660 }
1661
1662 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1663 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
1664}
1665
1666/* Disable transmit via physical egress queue
1667 * - HW doesn't take descriptors from DRAM
1668 */
1669static void mvpp2_egress_disable(struct mvpp2_port *port)
1670{
1671 u32 reg_data;
1672 int delay;
1673 int tx_port_num = mvpp2_egress_port(port);
1674
1675 /* Issue stop command for active channels only */
1676 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1677 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
1678 MVPP2_TXP_SCHED_ENQ_MASK;
1679 if (reg_data != 0)
1680 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
1681 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
1682
1683 /* Wait for all Tx activity to terminate. */
1684 delay = 0;
1685 do {
1686 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
1687 netdev_warn(port->dev,
1688 "Tx stop timed out, status=0x%08x\n",
1689 reg_data);
1690 break;
1691 }
1692 mdelay(1);
1693 delay++;
1694
1695 /* Check port TX Command register that all
1696 * Tx queues are stopped
1697 */
1698 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
1699 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
1700}
1701
1702/* Rx descriptors helper methods */
1703
1704/* Get number of Rx descriptors occupied by received packets */
1705static inline int
1706mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
1707{
1708 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
1709
1710 return val & MVPP2_RXQ_OCCUPIED_MASK;
1711}
1712
1713/* Update Rx queue status with the number of occupied and available
1714 * Rx descriptor slots.
1715 */
1716static inline void
1717mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
1718 int used_count, int free_count)
1719{
1720 /* Decrement the number of used descriptors and increment count
1721 * increment the number of free descriptors.
1722 */
1723 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
1724
1725 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
1726}
1727
1728/* Get pointer to next RX descriptor to be processed by SW */
1729static inline struct mvpp2_rx_desc *
1730mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
1731{
1732 int rx_desc = rxq->next_desc_to_proc;
1733
1734 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
1735 prefetch(rxq->descs + rxq->next_desc_to_proc);
1736 return rxq->descs + rx_desc;
1737}
1738
1739/* Set rx queue offset */
1740static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
1741 int prxq, int offset)
1742{
1743 u32 val;
1744
1745 /* Convert offset from bytes to units of 32 bytes */
1746 offset = offset >> 5;
1747
1748 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
1749 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
1750
1751 /* Offset is in */
1752 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
1753 MVPP2_RXQ_PACKET_OFFSET_MASK);
1754
1755 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
1756}
1757
3f518509
MW		 1758/* Tx descriptors helper methods */
1759
3f518509
MW		 1760/* Get pointer to next Tx descriptor to be processed (send) by HW */
1761static struct mvpp2_tx_desc *
1762mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
1763{
1764 int tx_desc = txq->next_desc_to_proc;
1765
1766 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
1767 return txq->descs + tx_desc;
1768}
1769
e0af22d9
TP		 1770/* Update HW with number of aggregated Tx descriptors to be sent
1771 *
1772 * Called only from mvpp2_tx(), so migration is disabled, using
1773 * smp_processor_id() is OK.
1774 */
3f518509
MW		 1775static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
1776{
1777 /* aggregated access - relevant TXQ number is written in TX desc */
1068549c 1778 mvpp2_thread_write(port->priv,
e531f767 1779 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
a786841d 1780 MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3f518509
MW		 1781}
1782
3f518509
MW		 1783/* Check if there are enough free descriptors in aggregated txq.
1784 * If not, update the number of occupied descriptors and repeat the check.
e0af22d9
TP		 1785 *
1786 * Called only from mvpp2_tx(), so migration is disabled, using
1787 * smp_processor_id() is OK.
3f518509 1788 */
e531f767 1789static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
3f518509
MW		 1790 struct mvpp2_tx_queue *aggr_txq, int num)
1791{
02856a3b 1792 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
3f518509 1793 /* Update number of occupied aggregated Tx descriptors */
e531f767
AT		 1794 unsigned int thread =
1795 mvpp2_cpu_to_thread(port->priv, smp_processor_id());
1796 u32 val = mvpp2_read_relaxed(port->priv,
543ec376 1797 MVPP2_AGGR_TXQ_STATUS_REG(thread));
3f518509
MW		 1798
1799 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
3f518509 1800
914365f1
YM		 1801 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
1802 return -ENOMEM;
1803 }
3f518509
MW		 1804 return 0;
1805}
1806
e0af22d9
TP		 1807/* Reserved Tx descriptors allocation request
1808 *
1809 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
1810 * only by mvpp2_tx(), so migration is disabled, using
1811 * smp_processor_id() is OK.
1812 */
e531f767 1813static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
3f518509
MW		 1814 struct mvpp2_tx_queue *txq, int num)
1815{
e531f767
AT		 1816 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
1817 struct mvpp2 *priv = port->priv;
3f518509
MW		 1818 u32 val;
1819
1820 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
1068549c 1821 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
3f518509 1822
1068549c 1823 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
3f518509
MW		 1824
1825 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
1826}
1827
1828/* Check if there are enough reserved descriptors for transmission.
1829 * If not, request chunk of reserved descriptors and check again.
1830 */
074c74df 1831static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
3f518509
MW		 1832 struct mvpp2_tx_queue *txq,
1833 struct mvpp2_txq_pcpu *txq_pcpu,
1834 int num)
1835{
850623b3 1836 int req, desc_count;
074c74df 1837 unsigned int thread;
3f518509
MW		 1838
1839 if (txq_pcpu->reserved_num >= num)
1840 return 0;
1841
1842 /* Not enough descriptors reserved! Update the reserved descriptor
1843 * count and check again.
1844 */
1845
1846 desc_count = 0;
1847 /* Compute total of used descriptors */
e531f767 1848 for (thread = 0; thread < port->priv->nthreads; thread++) {
3f518509
MW		 1849 struct mvpp2_txq_pcpu *txq_pcpu_aux;
1850
074c74df 1851 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
3f518509
MW		 1852 desc_count += txq_pcpu_aux->count;
1853 desc_count += txq_pcpu_aux->reserved_num;
1854 }
1855
1856 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
1857 desc_count += req;
1858
1859 if (desc_count >
074c74df 1860 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
3f518509
MW		 1861 return -ENOMEM;
1862
e531f767 1863 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
3f518509 1864
a3302baa 1865 /* OK, the descriptor could have been updated: check again. */
3f518509
MW		 1866 if (txq_pcpu->reserved_num < num)
1867 return -ENOMEM;
1868 return 0;
1869}
1870
1871/* Release the last allocated Tx descriptor. Useful to handle DMA
1872 * mapping failures in the Tx path.
1873 */
1874static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
1875{
1876 if (txq->next_desc_to_proc == 0)
1877 txq->next_desc_to_proc = txq->last_desc - 1;
1878 else
1879 txq->next_desc_to_proc--;
1880}
1881
1882/* Set Tx descriptors fields relevant for CSUM calculation */
35f3625c 1883static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
3f518509
MW		 1884 int ip_hdr_len, int l4_proto)
1885{
1886 u32 command;
1887
1888 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1889 * G_L4_chk, L4_type required only for checksum calculation
1890 */
1891 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
1892 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
1893 command |= MVPP2_TXD_IP_CSUM_DISABLE;
1894
dc734dbe 1895 if (l3_proto == htons(ETH_P_IP)) {
3f518509
MW		 1896 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
1897 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
1898 } else {
1899 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
1900 }
1901
1902 if (l4_proto == IPPROTO_TCP) {
1903 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
1904 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
1905 } else if (l4_proto == IPPROTO_UDP) {
1906 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
1907 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
1908 } else {
1909 command |= MVPP2_TXD_L4_CSUM_NOT;
1910 }
1911
1912 return command;
1913}
1914
1915/* Get number of sent descriptors and decrement counter.
1916 * The number of sent descriptors is returned.
543ec376 1917 * Per-thread access
e0af22d9
TP		 1918 *
1919 * Called only from mvpp2_txq_done(), called from mvpp2_tx()
1920 * (migration disabled) and from the TX completion tasklet (migration
1921 * disabled) so using smp_processor_id() is OK.
3f518509
MW		 1922 */
1923static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
1924 struct mvpp2_tx_queue *txq)
1925{
1926 u32 val;
1927
1928 /* Reading status reg resets transmitted descriptor counter */
1068549c 1929 val = mvpp2_thread_read_relaxed(port->priv,
e531f767 1930 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
cdcfeb0f 1931 MVPP2_TXQ_SENT_REG(txq->id));
3f518509
MW		 1932
1933 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
1934 MVPP2_TRANSMITTED_COUNT_OFFSET;
1935}
1936
e0af22d9
TP		 1937/* Called through on_each_cpu(), so runs on all CPUs, with migration
1938 * disabled, therefore using smp_processor_id() is OK.
1939 */
3f518509
MW		 1940static void mvpp2_txq_sent_counter_clear(void *arg)
1941{
1942 struct mvpp2_port *port = arg;
1943 int queue;
1944
e531f767
AT		 1945 /* If the thread isn't used, don't do anything */
1946 if (smp_processor_id() > port->priv->nthreads)
1947 return;
1948
09f83975 1949 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 1950 int id = port->txqs[queue]->id;
1951
1068549c 1952 mvpp2_thread_read(port->priv,
e531f767 1953 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
a786841d 1954 MVPP2_TXQ_SENT_REG(id));
3f518509
MW		 1955 }
1956}
1957
1958/* Set max sizes for Tx queues */
1959static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
1960{
1961 u32 val, size, mtu;
1962 int txq, tx_port_num;
1963
1964 mtu = port->pkt_size * 8;
1965 if (mtu > MVPP2_TXP_MTU_MAX)
1966 mtu = MVPP2_TXP_MTU_MAX;
1967
1968 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
1969 mtu = 3 * mtu;
1970
1971 /* Indirect access to registers */
1972 tx_port_num = mvpp2_egress_port(port);
1973 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1974
1975 /* Set MTU */
1976 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
1977 val &= ~MVPP2_TXP_MTU_MAX;
1978 val |= mtu;
1979 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
1980
1981 /* TXP token size and all TXQs token size must be larger that MTU */
1982 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
1983 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
1984 if (size < mtu) {
1985 size = mtu;
1986 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
1987 val |= size;
1988 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1989 }
1990
09f83975 1991 for (txq = 0; txq < port->ntxqs; txq++) {
3f518509
MW		 1992 val = mvpp2_read(port->priv,
1993 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
1994 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
1995
1996 if (size < mtu) {
1997 size = mtu;
1998 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
1999 val |= size;
2000 mvpp2_write(port->priv,
2001 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
2002 val);
2003 }
2004 }
2005}
2006
2007/* Set the number of packets that will be received before Rx interrupt
2008 * will be generated by HW.
2009 */
2010static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
d63f9e41 2011 struct mvpp2_rx_queue *rxq)
3f518509 2012{
e531f767 2013 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
a786841d 2014
f8b0d5f8
TP		 2015 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
2016 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
3f518509 2017
1068549c
AT		 2018 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2019 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
a786841d 2020 rxq->pkts_coal);
a704bb5c
TP		 2021
2022 put_cpu();
3f518509
MW		 2023}
2024
213f428f
TP		 2025/* For some reason in the LSP this is done on each CPU. Why ? */
2026static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
2027 struct mvpp2_tx_queue *txq)
2028{
e531f767 2029 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
213f428f
TP		 2030 u32 val;
2031
2032 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
2033 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
2034
2035 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
1068549c
AT		 2036 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2037 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
213f428f
TP		 2038
2039 put_cpu();
2040}
2041
ab42676a
TP		 2042static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
2043{
2044 u64 tmp = (u64)clk_hz * usec;
2045
2046 do_div(tmp, USEC_PER_SEC);
2047
2048 return tmp > U32_MAX ? U32_MAX : tmp;
2049}
2050
2051static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
2052{
2053 u64 tmp = (u64)cycles * USEC_PER_SEC;
2054
2055 do_div(tmp, clk_hz);
2056
2057 return tmp > U32_MAX ? U32_MAX : tmp;
2058}
2059
3f518509
MW		 2060/* Set the time delay in usec before Rx interrupt */
2061static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
d63f9e41 2062 struct mvpp2_rx_queue *rxq)
3f518509 2063{
ab42676a
TP		 2064 unsigned long freq = port->priv->tclk;
2065 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2066
2067 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
2068 rxq->time_coal =
2069 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
2070
2071 /* re-evaluate to get actual register value */
2072 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2073 }
3f518509 2074
3f518509 2075 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
3f518509
MW		 2076}
2077
213f428f
TP		 2078static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
2079{
2080 unsigned long freq = port->priv->tclk;
2081 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2082
2083 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
2084 port->tx_time_coal =
2085 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
2086
2087 /* re-evaluate to get actual register value */
2088 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2089 }
2090
2091 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
2092}
2093
3f518509
MW		 2094/* Free Tx queue skbuffs */
2095static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
2096 struct mvpp2_tx_queue *txq,
2097 struct mvpp2_txq_pcpu *txq_pcpu, int num)
2098{
2099 int i;
2100
2101 for (i = 0; i < num; i++) {
8354491c
TP		 2102 struct mvpp2_txq_pcpu_buf *tx_buf =
2103 txq_pcpu->buffs + txq_pcpu->txq_get_index;
3f518509 2104
20920267
AT		 2105 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma))
2106 dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
2107 tx_buf->size, DMA_TO_DEVICE);
36fb7435
TP		 2108 if (tx_buf->skb)
2109 dev_kfree_skb_any(tx_buf->skb);
2110
2111 mvpp2_txq_inc_get(txq_pcpu);
3f518509
MW		 2112 }
2113}
2114
2115static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2116 u32 cause)
2117{
2118 int queue = fls(cause) - 1;
2119
2120 return port->rxqs[queue];
2121}
2122
2123static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2124 u32 cause)
2125{
edc660fa 2126 int queue = fls(cause) - 1;
3f518509
MW		 2127
2128 return port->txqs[queue];
2129}
2130
2131/* Handle end of transmission */
2132static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2133 struct mvpp2_txq_pcpu *txq_pcpu)
2134{
2135 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2136 int tx_done;
2137
e531f767 2138 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
3f518509
MW		 2139 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2140
2141 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2142 if (!tx_done)
2143 return;
2144 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2145
2146 txq_pcpu->count -= tx_done;
2147
2148 if (netif_tx_queue_stopped(nq))
1d17db08 2149 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
3f518509
MW		 2150 netif_tx_wake_queue(nq);
2151}
2152
213f428f 2153static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
543ec376 2154 unsigned int thread)
edc660fa
MW		 2155{
2156 struct mvpp2_tx_queue *txq;
2157 struct mvpp2_txq_pcpu *txq_pcpu;
2158 unsigned int tx_todo = 0;
2159
2160 while (cause) {
2161 txq = mvpp2_get_tx_queue(port, cause);
2162 if (!txq)
2163 break;
2164
543ec376 2165 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
edc660fa
MW		 2166
2167 if (txq_pcpu->count) {
2168 mvpp2_txq_done(port, txq, txq_pcpu);
2169 tx_todo += txq_pcpu->count;
2170 }
2171
2172 cause &= ~(1 << txq->log_id);
2173 }
2174 return tx_todo;
2175}
2176
3f518509
MW		 2177/* Rx/Tx queue initialization/cleanup methods */
2178
2179/* Allocate and initialize descriptors for aggr TXQ */
2180static int mvpp2_aggr_txq_init(struct platform_device *pdev,
850623b3 2181 struct mvpp2_tx_queue *aggr_txq,
543ec376 2182 unsigned int thread, struct mvpp2 *priv)
3f518509 2183{
b02f31fb
TP		 2184 u32 txq_dma;
2185
3f518509 2186 /* Allocate memory for TX descriptors */
750afb08
LC		 2187 aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
2188 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2189 &aggr_txq->descs_dma, GFP_KERNEL);
3f518509
MW		 2190 if (!aggr_txq->descs)
2191 return -ENOMEM;
2192
02856a3b 2193 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
3f518509
MW		 2194
2195 /* Aggr TXQ no reset WA */
2196 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
543ec376 2197 MVPP2_AGGR_TXQ_INDEX_REG(thread));
3f518509 2198
b02f31fb
TP		 2199 /* Set Tx descriptors queue starting address indirect
2200 * access
2201 */
2202 if (priv->hw_version == MVPP21)
2203 txq_dma = aggr_txq->descs_dma;
2204 else
2205 txq_dma = aggr_txq->descs_dma >>
2206 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2207
543ec376
AT		 2208 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2209 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
85affd7e 2210 MVPP2_AGGR_TXQ_SIZE);
3f518509
MW		 2211
2212 return 0;
2213}
2214
2215/* Create a specified Rx queue */
2216static int mvpp2_rxq_init(struct mvpp2_port *port,
2217 struct mvpp2_rx_queue *rxq)
2218
2219{
543ec376 2220 unsigned int thread;
b02f31fb
TP		 2221 u32 rxq_dma;
2222
3f518509
MW		 2223 rxq->size = port->rx_ring_size;
2224
2225 /* Allocate memory for RX descriptors */
2226 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2227 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2228 &rxq->descs_dma, GFP_KERNEL);
3f518509
MW		 2229 if (!rxq->descs)
2230 return -ENOMEM;
2231
3f518509
MW		 2232 rxq->last_desc = rxq->size - 1;
2233
2234 /* Zero occupied and non-occupied counters - direct access */
2235 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2236
2237 /* Set Rx descriptors queue starting address - indirect access */
e531f767 2238 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1068549c 2239 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
b02f31fb
TP		 2240 if (port->priv->hw_version == MVPP21)
2241 rxq_dma = rxq->descs_dma;
2242 else
2243 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
1068549c
AT		 2244 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2245 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2246 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
a704bb5c 2247 put_cpu();
3f518509
MW		 2248
2249 /* Set Offset */
2250 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
2251
2252 /* Set coalescing pkts and time */
d63f9e41
TP		 2253 mvpp2_rx_pkts_coal_set(port, rxq);
2254 mvpp2_rx_time_coal_set(port, rxq);
3f518509
MW		 2255
2256 /* Add number of descriptors ready for receiving packets */
2257 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2258
2259 return 0;
2260}
2261
2262/* Push packets received by the RXQ to BM pool */
2263static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
2264 struct mvpp2_rx_queue *rxq)
2265{
2266 int rx_received, i;
2267
2268 rx_received = mvpp2_rxq_received(port, rxq->id);
2269 if (!rx_received)
2270 return;
2271
2272 for (i = 0; i < rx_received; i++) {
2273 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
56b8aae9
TP		 2274 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2275 int pool;
2276
2277 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2278 MVPP2_RXD_BM_POOL_ID_OFFS;
3f518509 2279
7d7627ba 2280 mvpp2_bm_pool_put(port, pool,
ac3dd277
TP		 2281 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
2282 mvpp2_rxdesc_cookie_get(port, rx_desc));
3f518509
MW		 2283 }
2284 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
2285}
2286
2287/* Cleanup Rx queue */
2288static void mvpp2_rxq_deinit(struct mvpp2_port *port,
2289 struct mvpp2_rx_queue *rxq)
2290{
543ec376 2291 unsigned int thread;
a786841d 2292
3f518509
MW		 2293 mvpp2_rxq_drop_pkts(port, rxq);
2294
2295 if (rxq->descs)
2296 dma_free_coherent(port->dev->dev.parent,
2297 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2298 rxq->descs,
20396136 2299 rxq->descs_dma);
3f518509
MW		 2300
2301 rxq->descs = NULL;
2302 rxq->last_desc = 0;
2303 rxq->next_desc_to_proc = 0;
20396136 2304 rxq->descs_dma = 0;
3f518509
MW		 2305
2306 /* Clear Rx descriptors queue starting address and size;
2307 * free descriptor number
2308 */
2309 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
e531f767 2310 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1068549c
AT		 2311 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2312 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
2313 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
a704bb5c 2314 put_cpu();
3f518509
MW		 2315}
2316
2317/* Create and initialize a Tx queue */
2318static int mvpp2_txq_init(struct mvpp2_port *port,
2319 struct mvpp2_tx_queue *txq)
2320{
2321 u32 val;
074c74df 2322 unsigned int thread;
850623b3 2323 int desc, desc_per_txq, tx_port_num;
3f518509
MW		 2324 struct mvpp2_txq_pcpu *txq_pcpu;
2325
2326 txq->size = port->tx_ring_size;
2327
2328 /* Allocate memory for Tx descriptors */
2329 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
2330 txq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2331 &txq->descs_dma, GFP_KERNEL);
3f518509
MW		 2332 if (!txq->descs)
2333 return -ENOMEM;
2334
3f518509
MW		 2335 txq->last_desc = txq->size - 1;
2336
2337 /* Set Tx descriptors queue starting address - indirect access */
e531f767 2338 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1068549c
AT		 2339 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2340 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
a786841d 2341 txq->descs_dma);
1068549c 2342 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
a786841d 2343 txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
1068549c
AT		 2344 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
2345 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
a786841d 2346 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
1068549c 2347 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
3f518509 2348 val &= ~MVPP2_TXQ_PENDING_MASK;
1068549c 2349 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
3f518509
MW		 2350
2351 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
2352 * for each existing TXQ.
2353 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
a3302baa 2354 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
3f518509
MW		 2355 */
2356 desc_per_txq = 16;
2357 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
2358 (txq->log_id * desc_per_txq);
2359
1068549c 2360 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
a786841d
TP		 2361 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
2362 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
a704bb5c 2363 put_cpu();
3f518509
MW		 2364
2365 /* WRR / EJP configuration - indirect access */
2366 tx_port_num = mvpp2_egress_port(port);
2367 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2368
2369 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
2370 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
2371 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
2372 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
2373 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
2374
2375 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
2376 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
2377 val);
2378
e531f767 2379 for (thread = 0; thread < port->priv->nthreads; thread++) {
074c74df 2380 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3f518509 2381 txq_pcpu->size = txq->size;
02c91ece
ME		 2382 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
2383 sizeof(*txq_pcpu->buffs),
2384 GFP_KERNEL);
8354491c 2385 if (!txq_pcpu->buffs)
ba2d8d88 2386 return -ENOMEM;
3f518509
MW		 2387
2388 txq_pcpu->count = 0;
2389 txq_pcpu->reserved_num = 0;
2390 txq_pcpu->txq_put_index = 0;
2391 txq_pcpu->txq_get_index = 0;
b70d4a51 2392 txq_pcpu->tso_headers = NULL;
186cd4d4 2393
1d17db08
AT		 2394 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
2395 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
2396
186cd4d4
AT		 2397 txq_pcpu->tso_headers =
2398 dma_alloc_coherent(port->dev->dev.parent,
822eaf7c 2399 txq_pcpu->size * TSO_HEADER_SIZE,
186cd4d4
AT		 2400 &txq_pcpu->tso_headers_dma,
2401 GFP_KERNEL);
2402 if (!txq_pcpu->tso_headers)
ba2d8d88 2403 return -ENOMEM;
3f518509
MW		 2404 }
2405
2406 return 0;
2407}
2408
2409/* Free allocated TXQ resources */
2410static void mvpp2_txq_deinit(struct mvpp2_port *port,
2411 struct mvpp2_tx_queue *txq)
2412{
2413 struct mvpp2_txq_pcpu *txq_pcpu;
074c74df 2414 unsigned int thread;
3f518509 2415
e531f767 2416 for (thread = 0; thread < port->priv->nthreads; thread++) {
074c74df 2417 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
8354491c 2418 kfree(txq_pcpu->buffs);
186cd4d4 2419
b70d4a51
AT		 2420 if (txq_pcpu->tso_headers)
2421 dma_free_coherent(port->dev->dev.parent,
2422 txq_pcpu->size * TSO_HEADER_SIZE,
2423 txq_pcpu->tso_headers,
2424 txq_pcpu->tso_headers_dma);
2425
2426 txq_pcpu->tso_headers = NULL;
3f518509
MW		 2427 }
2428
2429 if (txq->descs)
2430 dma_free_coherent(port->dev->dev.parent,
2431 txq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2432 txq->descs, txq->descs_dma);
3f518509
MW		 2433
2434 txq->descs = NULL;
2435 txq->last_desc = 0;
2436 txq->next_desc_to_proc = 0;
20396136 2437 txq->descs_dma = 0;
3f518509
MW		 2438
2439 /* Set minimum bandwidth for disabled TXQs */
21808437 2440 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
3f518509
MW		 2441
2442 /* Set Tx descriptors queue starting address and size */
e531f767 2443 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1068549c
AT		 2444 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2445 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
2446 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
a704bb5c 2447 put_cpu();
3f518509
MW		 2448}
2449
2450/* Cleanup Tx ports */
2451static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
2452{
2453 struct mvpp2_txq_pcpu *txq_pcpu;
850623b3 2454 int delay, pending;
e531f767 2455 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3f518509
MW		 2456 u32 val;
2457
1068549c
AT		 2458 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2459 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
3f518509 2460 val |= MVPP2_TXQ_DRAIN_EN_MASK;
1068549c 2461 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3f518509
MW		 2462
2463 /* The napi queue has been stopped so wait for all packets
2464 * to be transmitted.
2465 */
2466 delay = 0;
2467 do {
2468 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
2469 netdev_warn(port->dev,
2470 "port %d: cleaning queue %d timed out\n",
2471 port->id, txq->log_id);
2472 break;
2473 }
2474 mdelay(1);
2475 delay++;
2476
1068549c 2477 pending = mvpp2_thread_read(port->priv, thread,
a786841d
TP		 2478 MVPP2_TXQ_PENDING_REG);
2479 pending &= MVPP2_TXQ_PENDING_MASK;
3f518509
MW		 2480 } while (pending);
2481
2482 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
1068549c 2483 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
a704bb5c 2484 put_cpu();
3f518509 2485
e531f767 2486 for (thread = 0; thread < port->priv->nthreads; thread++) {
074c74df 2487 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3f518509
MW		 2488
2489 /* Release all packets */
2490 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
2491
2492 /* Reset queue */
2493 txq_pcpu->count = 0;
2494 txq_pcpu->txq_put_index = 0;
2495 txq_pcpu->txq_get_index = 0;
2496 }
2497}
2498
2499/* Cleanup all Tx queues */
2500static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
2501{
2502 struct mvpp2_tx_queue *txq;
2503 int queue;
2504 u32 val;
2505
2506 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
2507
2508 /* Reset Tx ports and delete Tx queues */
2509 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
2510 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2511
09f83975 2512 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 2513 txq = port->txqs[queue];
2514 mvpp2_txq_clean(port, txq);
2515 mvpp2_txq_deinit(port, txq);
2516 }
2517
2518 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2519
2520 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
2521 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2522}
2523
2524/* Cleanup all Rx queues */
2525static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
2526{
2527 int queue;
2528
09f83975 2529 for (queue = 0; queue < port->nrxqs; queue++)
3f518509
MW		 2530 mvpp2_rxq_deinit(port, port->rxqs[queue]);
2531}
2532
2533/* Init all Rx queues for port */
2534static int mvpp2_setup_rxqs(struct mvpp2_port *port)
2535{
2536 int queue, err;
2537
09f83975 2538 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 2539 err = mvpp2_rxq_init(port, port->rxqs[queue]);
2540 if (err)
2541 goto err_cleanup;
2542 }
2543 return 0;
2544
2545err_cleanup:
2546 mvpp2_cleanup_rxqs(port);
2547 return err;
2548}
2549
2550/* Init all tx queues for port */
2551static int mvpp2_setup_txqs(struct mvpp2_port *port)
2552{
2553 struct mvpp2_tx_queue *txq;
0d283ab5 2554 int queue, err, cpu;
3f518509 2555
09f83975 2556 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 2557 txq = port->txqs[queue];
2558 err = mvpp2_txq_init(port, txq);
2559 if (err)
2560 goto err_cleanup;
0d283ab5
MC		 2561
2562 /* Assign this queue to a CPU */
2563 cpu = queue % num_present_cpus();
2564 netif_set_xps_queue(port->dev, cpumask_of(cpu), queue);
3f518509
MW		 2565 }
2566
213f428f
TP		 2567 if (port->has_tx_irqs) {
2568 mvpp2_tx_time_coal_set(port);
2569 for (queue = 0; queue < port->ntxqs; queue++) {
2570 txq = port->txqs[queue];
2571 mvpp2_tx_pkts_coal_set(port, txq);
2572 }
2573 }
2574
3f518509
MW		 2575 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2576 return 0;
2577
2578err_cleanup:
2579 mvpp2_cleanup_txqs(port);
2580 return err;
2581}
2582
2583/* The callback for per-port interrupt */
2584static irqreturn_t mvpp2_isr(int irq, void *dev_id)
2585{
591f4cfa 2586 struct mvpp2_queue_vector *qv = dev_id;
3f518509 2587
591f4cfa 2588 mvpp2_qvec_interrupt_disable(qv);
3f518509 2589
591f4cfa 2590 napi_schedule(&qv->napi);
3f518509
MW		 2591
2592 return IRQ_HANDLED;
2593}
2594
fd3651b2
AT		 2595/* Per-port interrupt for link status changes */
2596static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
2597{
2598 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
2599 struct net_device *dev = port->dev;
2600 bool event = false, link = false;
2601 u32 val;
2602
2603 mvpp22_gop_mask_irq(port);
2604
1d9b041e 2605 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
fd3651b2
AT		 2606 val = readl(port->base + MVPP22_XLG_INT_STAT);
2607 if (val & MVPP22_XLG_INT_STAT_LINK) {
2608 event = true;
2609 val = readl(port->base + MVPP22_XLG_STATUS);
2610 if (val & MVPP22_XLG_STATUS_LINK_UP)
2611 link = true;
2612 }
2613 } else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
4a4cec72
RK		 2614 phy_interface_mode_is_8023z(port->phy_interface) ||
2615 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
fd3651b2
AT		 2616 val = readl(port->base + MVPP22_GMAC_INT_STAT);
2617 if (val & MVPP22_GMAC_INT_STAT_LINK) {
2618 event = true;
2619 val = readl(port->base + MVPP2_GMAC_STATUS0);
2620 if (val & MVPP2_GMAC_STATUS0_LINK_UP)
2621 link = true;
2622 }
2623 }
2624
4bb04326
AT		 2625 if (port->phylink) {
2626 phylink_mac_change(port->phylink, link);
2627 goto handled;
2628 }
2629
fd3651b2
AT		 2630 if (!netif_running(dev) || !event)
2631 goto handled;
2632
2633 if (link) {
2634 mvpp2_interrupts_enable(port);
2635
2636 mvpp2_egress_enable(port);
2637 mvpp2_ingress_enable(port);
2638 netif_carrier_on(dev);
2639 netif_tx_wake_all_queues(dev);
2640 } else {
2641 netif_tx_stop_all_queues(dev);
2642 netif_carrier_off(dev);
2643 mvpp2_ingress_disable(port);
2644 mvpp2_egress_disable(port);
2645
2646 mvpp2_interrupts_disable(port);
2647 }
2648
2649handled:
2650 mvpp22_gop_unmask_irq(port);
2651 return IRQ_HANDLED;
2652}
2653
edc660fa
MW		 2654static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
2655{
2656 ktime_t interval;
2657
2658 if (!port_pcpu->timer_scheduled) {
2659 port_pcpu->timer_scheduled = true;
8b0e1953 2660 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS;
edc660fa
MW		 2661 hrtimer_start(&port_pcpu->tx_done_timer, interval,
2662 HRTIMER_MODE_REL_PINNED);
2663 }
2664}
2665
2666static void mvpp2_tx_proc_cb(unsigned long data)
2667{
2668 struct net_device *dev = (struct net_device *)data;
2669 struct mvpp2_port *port = netdev_priv(dev);
074c74df 2670 struct mvpp2_port_pcpu *port_pcpu;
edc660fa
MW		 2671 unsigned int tx_todo, cause;
2672
074c74df 2673 port_pcpu = per_cpu_ptr(port->pcpu,
e531f767 2674 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
074c74df 2675
edc660fa
MW		 2676 if (!netif_running(dev))
2677 return;
2678 port_pcpu->timer_scheduled = false;
2679
2680 /* Process all the Tx queues */
09f83975 2681 cause = (1 << port->ntxqs) - 1;
074c74df 2682 tx_todo = mvpp2_tx_done(port, cause,
e531f767 2683 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
edc660fa
MW		 2684
2685 /* Set the timer in case not all the packets were processed */
2686 if (tx_todo)
2687 mvpp2_timer_set(port_pcpu);
2688}
2689
2690static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
2691{
2692 struct mvpp2_port_pcpu *port_pcpu = container_of(timer,
2693 struct mvpp2_port_pcpu,
2694 tx_done_timer);
2695
2696 tasklet_schedule(&port_pcpu->tx_done_tasklet);
2697
2698 return HRTIMER_NORESTART;
2699}
2700
3f518509
MW		 2701/* Main RX/TX processing routines */
2702
2703/* Display more error info */
2704static void mvpp2_rx_error(struct mvpp2_port *port,
2705 struct mvpp2_rx_desc *rx_desc)
2706{
ac3dd277
TP		 2707 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2708 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
934e0f83 2709 char *err_str = NULL;
3f518509
MW		 2710
2711 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
2712 case MVPP2_RXD_ERR_CRC:
934e0f83 2713 err_str = "crc";
3f518509
MW		 2714 break;
2715 case MVPP2_RXD_ERR_OVERRUN:
934e0f83 2716 err_str = "overrun";
3f518509
MW		 2717 break;
2718 case MVPP2_RXD_ERR_RESOURCE:
934e0f83 2719 err_str = "resource";
3f518509
MW		 2720 break;
2721 }
934e0f83
YM		 2722 if (err_str && net_ratelimit())
2723 netdev_err(port->dev,
2724 "bad rx status %08x (%s error), size=%zu\n",
2725 status, err_str, sz);
3f518509
MW		 2726}
2727
2728/* Handle RX checksum offload */
2729static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
2730 struct sk_buff *skb)
2731{
2732 if (((status & MVPP2_RXD_L3_IP4) &&
2733 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
2734 (status & MVPP2_RXD_L3_IP6))
2735 if (((status & MVPP2_RXD_L4_UDP) ||
2736 (status & MVPP2_RXD_L4_TCP)) &&
2737 (status & MVPP2_RXD_L4_CSUM_OK)) {
2738 skb->csum = 0;
2739 skb->ip_summed = CHECKSUM_UNNECESSARY;
2740 return;
2741 }
2742
2743 skb->ip_summed = CHECKSUM_NONE;
2744}
2745
2746/* Reuse skb if possible, or allocate a new skb and add it to BM pool */
2747static int mvpp2_rx_refill(struct mvpp2_port *port,
56b8aae9 2748 struct mvpp2_bm_pool *bm_pool, int pool)
3f518509 2749{
20396136 2750 dma_addr_t dma_addr;
4e4a105f 2751 phys_addr_t phys_addr;
0e037281 2752 void *buf;
3f518509 2753
3f518509 2754 /* No recycle or too many buffers are in use, so allocate a new skb */
4e4a105f
TP		 2755 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr,
2756 GFP_ATOMIC);
0e037281 2757 if (!buf)
3f518509
MW		 2758 return -ENOMEM;
2759
7d7627ba 2760 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
7ef7e1d9 2761
3f518509
MW		 2762 return 0;
2763}
2764
2765/* Handle tx checksum */
2766static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
2767{
2768 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2769 int ip_hdr_len = 0;
2770 u8 l4_proto;
35f3625c 2771 __be16 l3_proto = vlan_get_protocol(skb);
3f518509 2772
35f3625c 2773 if (l3_proto == htons(ETH_P_IP)) {
3f518509
MW		 2774 struct iphdr *ip4h = ip_hdr(skb);
2775
2776 /* Calculate IPv4 checksum and L4 checksum */
2777 ip_hdr_len = ip4h->ihl;
2778 l4_proto = ip4h->protocol;
35f3625c 2779 } else if (l3_proto == htons(ETH_P_IPV6)) {
3f518509
MW		 2780 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2781
2782 /* Read l4_protocol from one of IPv6 extra headers */
2783 if (skb_network_header_len(skb) > 0)
2784 ip_hdr_len = (skb_network_header_len(skb) >> 2);
2785 l4_proto = ip6h->nexthdr;
2786 } else {
2787 return MVPP2_TXD_L4_CSUM_NOT;
2788 }
2789
2790 return mvpp2_txq_desc_csum(skb_network_offset(skb),
35f3625c 2791 l3_proto, ip_hdr_len, l4_proto);
3f518509
MW		 2792 }
2793
2794 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
2795}
2796
3f518509 2797/* Main rx processing */
591f4cfa
TP		 2798static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
2799 int rx_todo, struct mvpp2_rx_queue *rxq)
3f518509
MW		 2800{
2801 struct net_device *dev = port->dev;
b5015854
MW		 2802 int rx_received;
2803 int rx_done = 0;
3f518509
MW		 2804 u32 rcvd_pkts = 0;
2805 u32 rcvd_bytes = 0;
2806
2807 /* Get number of received packets and clamp the to-do */
2808 rx_received = mvpp2_rxq_received(port, rxq->id);
2809 if (rx_todo > rx_received)
2810 rx_todo = rx_received;
2811
b5015854 2812 while (rx_done < rx_todo) {
3f518509
MW		 2813 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2814 struct mvpp2_bm_pool *bm_pool;
2815 struct sk_buff *skb;
0e037281 2816 unsigned int frag_size;
20396136 2817 dma_addr_t dma_addr;
ac3dd277 2818 phys_addr_t phys_addr;
56b8aae9 2819 u32 rx_status;
3f518509 2820 int pool, rx_bytes, err;
0e037281 2821 void *data;
3f518509 2822
b5015854 2823 rx_done++;
ac3dd277
TP		 2824 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
2825 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
2826 rx_bytes -= MVPP2_MH_SIZE;
2827 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
2828 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
2829 data = (void *)phys_to_virt(phys_addr);
2830
56b8aae9
TP		 2831 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2832 MVPP2_RXD_BM_POOL_ID_OFFS;
3f518509 2833 bm_pool = &port->priv->bm_pools[pool];
3f518509
MW		 2834
2835 /* In case of an error, release the requested buffer pointer
2836 * to the Buffer Manager. This request process is controlled
2837 * by the hardware, and the information about the buffer is
2838 * comprised by the RX descriptor.
2839 */
2840 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
8a52488b 2841err_drop_frame:
3f518509
MW		 2842 dev->stats.rx_errors++;
2843 mvpp2_rx_error(port, rx_desc);
b5015854 2844 /* Return the buffer to the pool */
7d7627ba 2845 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3f518509
MW		 2846 continue;
2847 }
2848
0e037281
TP		 2849 if (bm_pool->frag_size > PAGE_SIZE)
2850 frag_size = 0;
2851 else
2852 frag_size = bm_pool->frag_size;
2853
2854 skb = build_skb(data, frag_size);
2855 if (!skb) {
2856 netdev_warn(port->dev, "skb build failed\n");
2857 goto err_drop_frame;
2858 }
3f518509 2859
56b8aae9 2860 err = mvpp2_rx_refill(port, bm_pool, pool);
b5015854
MW		 2861 if (err) {
2862 netdev_err(port->dev, "failed to refill BM pools\n");
2863 goto err_drop_frame;
2864 }
2865
20396136 2866 dma_unmap_single(dev->dev.parent, dma_addr,
4229d502
MW		 2867 bm_pool->buf_size, DMA_FROM_DEVICE);
2868
3f518509
MW		 2869 rcvd_pkts++;
2870 rcvd_bytes += rx_bytes;
3f518509 2871
0e037281 2872 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD);
3f518509
MW		 2873 skb_put(skb, rx_bytes);
2874 skb->protocol = eth_type_trans(skb, dev);
2875 mvpp2_rx_csum(port, rx_status, skb);
2876
591f4cfa 2877 napi_gro_receive(napi, skb);
3f518509
MW		 2878 }
2879
2880 if (rcvd_pkts) {
2881 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
2882
2883 u64_stats_update_begin(&stats->syncp);
2884 stats->rx_packets += rcvd_pkts;
2885 stats->rx_bytes += rcvd_bytes;
2886 u64_stats_update_end(&stats->syncp);
2887 }
2888
2889 /* Update Rx queue management counters */
2890 wmb();
b5015854 2891 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
3f518509
MW		 2892
2893 return rx_todo;
2894}
2895
2896static inline void
ac3dd277 2897tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
3f518509
MW		 2898 struct mvpp2_tx_desc *desc)
2899{
e531f767 2900 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
074c74df 2901 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
20920267 2902
ac3dd277
TP		 2903 dma_addr_t buf_dma_addr =
2904 mvpp2_txdesc_dma_addr_get(port, desc);
2905 size_t buf_sz =
2906 mvpp2_txdesc_size_get(port, desc);
20920267
AT		 2907 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
2908 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
2909 buf_sz, DMA_TO_DEVICE);
3f518509
MW		 2910 mvpp2_txq_desc_put(txq);
2911}
2912
2913/* Handle tx fragmentation processing */
2914static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
2915 struct mvpp2_tx_queue *aggr_txq,
2916 struct mvpp2_tx_queue *txq)
2917{
e531f767 2918 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
074c74df 2919 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3f518509
MW		 2920 struct mvpp2_tx_desc *tx_desc;
2921 int i;
20396136 2922 dma_addr_t buf_dma_addr;
3f518509
MW		 2923
2924 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2925 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2926 void *addr = page_address(frag->page.p) + frag->page_offset;
2927
2928 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
ac3dd277
TP		 2929 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2930 mvpp2_txdesc_size_set(port, tx_desc, frag->size);
3f518509 2931
20396136 2932 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
a3302baa 2933 frag->size, DMA_TO_DEVICE);
20396136 2934 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
3f518509 2935 mvpp2_txq_desc_put(txq);
32bae631 2936 goto cleanup;
3f518509
MW		 2937 }
2938
6eb5d375 2939 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3f518509
MW		 2940
2941 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
2942 /* Last descriptor */
ac3dd277
TP		 2943 mvpp2_txdesc_cmd_set(port, tx_desc,
2944 MVPP2_TXD_L_DESC);
2945 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3f518509
MW		 2946 } else {
2947 /* Descriptor in the middle: Not First, Not Last */
ac3dd277
TP		 2948 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2949 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3f518509
MW		 2950 }
2951 }
2952
2953 return 0;
32bae631 2954cleanup:
3f518509
MW		 2955 /* Release all descriptors that were used to map fragments of
2956 * this packet, as well as the corresponding DMA mappings
2957 */
2958 for (i = i - 1; i >= 0; i--) {
2959 tx_desc = txq->descs + i;
ac3dd277 2960 tx_desc_unmap_put(port, txq, tx_desc);
3f518509
MW		 2961 }
2962
2963 return -ENOMEM;
2964}
2965
186cd4d4
AT		 2966static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
2967 struct net_device *dev,
2968 struct mvpp2_tx_queue *txq,
2969 struct mvpp2_tx_queue *aggr_txq,
2970 struct mvpp2_txq_pcpu *txq_pcpu,
2971 int hdr_sz)
2972{
2973 struct mvpp2_port *port = netdev_priv(dev);
2974 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2975 dma_addr_t addr;
2976
2977 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2978 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
2979
2980 addr = txq_pcpu->tso_headers_dma +
2981 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
6eb5d375 2982 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
186cd4d4
AT		 2983
2984 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
2985 MVPP2_TXD_F_DESC |
2986 MVPP2_TXD_PADDING_DISABLE);
2987 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2988}
2989
2990static inline int mvpp2_tso_put_data(struct sk_buff *skb,
2991 struct net_device *dev, struct tso_t *tso,
2992 struct mvpp2_tx_queue *txq,
2993 struct mvpp2_tx_queue *aggr_txq,
2994 struct mvpp2_txq_pcpu *txq_pcpu,
2995 int sz, bool left, bool last)
2996{
2997 struct mvpp2_port *port = netdev_priv(dev);
2998 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2999 dma_addr_t buf_dma_addr;
3000
3001 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3002 mvpp2_txdesc_size_set(port, tx_desc, sz);
3003
3004 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
3005 DMA_TO_DEVICE);
3006 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3007 mvpp2_txq_desc_put(txq);
3008 return -ENOMEM;
3009 }
3010
6eb5d375 3011 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
186cd4d4
AT		 3012
3013 if (!left) {
3014 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
3015 if (last) {
3016 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3017 return 0;
3018 }
3019 } else {
3020 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
3021 }
3022
3023 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3024 return 0;
3025}
3026
3027static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
3028 struct mvpp2_tx_queue *txq,
3029 struct mvpp2_tx_queue *aggr_txq,
3030 struct mvpp2_txq_pcpu *txq_pcpu)
3031{
3032 struct mvpp2_port *port = netdev_priv(dev);
3033 struct tso_t tso;
3034 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb);
3035 int i, len, descs = 0;
3036
3037 /* Check number of available descriptors */
e531f767 3038 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
074c74df 3039 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
186cd4d4
AT		 3040 tso_count_descs(skb)))
3041 return 0;
3042
3043 tso_start(skb, &tso);
3044 len = skb->len - hdr_sz;
3045 while (len > 0) {
3046 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
3047 char *hdr = txq_pcpu->tso_headers +
3048 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
3049
3050 len -= left;
3051 descs++;
3052
3053 tso_build_hdr(skb, hdr, &tso, left, len == 0);
3054 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
3055
3056 while (left > 0) {
3057 int sz = min_t(int, tso.size, left);
3058 left -= sz;
3059 descs++;
3060
3061 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
3062 txq_pcpu, sz, left, len == 0))
3063 goto release;
3064 tso_build_data(skb, &tso, sz);
3065 }
3066 }
3067
3068 return descs;
3069
3070release:
3071 for (i = descs - 1; i >= 0; i--) {
3072 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
3073 tx_desc_unmap_put(port, txq, tx_desc);
3074 }
3075 return 0;
3076}
3077
3f518509 3078/* Main tx processing */
f03508ce 3079static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
3f518509
MW		 3080{
3081 struct mvpp2_port *port = netdev_priv(dev);
3082 struct mvpp2_tx_queue *txq, *aggr_txq;
3083 struct mvpp2_txq_pcpu *txq_pcpu;
3084 struct mvpp2_tx_desc *tx_desc;
20396136 3085 dma_addr_t buf_dma_addr;
e531f767 3086 unsigned long flags = 0;
074c74df 3087 unsigned int thread;
3f518509
MW		 3088 int frags = 0;
3089 u16 txq_id;
3090 u32 tx_cmd;
3091
e531f767 3092 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
074c74df 3093
3f518509
MW		 3094 txq_id = skb_get_queue_mapping(skb);
3095 txq = port->txqs[txq_id];
074c74df
AT		 3096 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3097 aggr_txq = &port->priv->aggr_txqs[thread];
3f518509 3098
e531f767
AT		 3099 if (test_bit(thread, &port->priv->lock_map))
3100 spin_lock_irqsave(&port->tx_lock[thread], flags);
3101
186cd4d4
AT		 3102 if (skb_is_gso(skb)) {
3103 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
3104 goto out;
3105 }
3f518509
MW		 3106 frags = skb_shinfo(skb)->nr_frags + 1;
3107
3108 /* Check number of available descriptors */
e531f767 3109 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
074c74df 3110 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
3f518509
MW		 3111 frags = 0;
3112 goto out;
3113 }
3114
3115 /* Get a descriptor for the first part of the packet */
3116 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
ac3dd277
TP		 3117 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3118 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
3f518509 3119
20396136 3120 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
ac3dd277 3121 skb_headlen(skb), DMA_TO_DEVICE);
20396136 3122 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3f518509
MW		 3123 mvpp2_txq_desc_put(txq);
3124 frags = 0;
3125 goto out;
3126 }
ac3dd277 3127
6eb5d375 3128 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3f518509
MW		 3129
3130 tx_cmd = mvpp2_skb_tx_csum(port, skb);
3131
3132 if (frags == 1) {
3133 /* First and Last descriptor */
3134 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
ac3dd277
TP		 3135 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3136 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3f518509
MW		 3137 } else {
3138 /* First but not Last */
3139 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
ac3dd277
TP		 3140 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3141 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3f518509
MW		 3142
3143 /* Continue with other skb fragments */
3144 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
ac3dd277 3145 tx_desc_unmap_put(port, txq, tx_desc);
3f518509 3146 frags = 0;
3f518509
MW		 3147 }
3148 }
3149
3f518509
MW		 3150out:
3151 if (frags > 0) {
074c74df 3152 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
186cd4d4
AT		 3153 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
3154
3155 txq_pcpu->reserved_num -= frags;
3156 txq_pcpu->count += frags;
3157 aggr_txq->count += frags;
3158
3159 /* Enable transmit */
3160 wmb();
3161 mvpp2_aggr_txq_pend_desc_add(port, frags);
3162
1d17db08 3163 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
186cd4d4 3164 netif_tx_stop_queue(nq);
3f518509
MW		 3165
3166 u64_stats_update_begin(&stats->syncp);
3167 stats->tx_packets++;
3168 stats->tx_bytes += skb->len;
3169 u64_stats_update_end(&stats->syncp);
3170 } else {
3171 dev->stats.tx_dropped++;
3172 dev_kfree_skb_any(skb);
3173 }
3174
edc660fa 3175 /* Finalize TX processing */
082297e6 3176 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
edc660fa
MW		 3177 mvpp2_txq_done(port, txq, txq_pcpu);
3178
3179 /* Set the timer in case not all frags were processed */
213f428f
TP		 3180 if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
3181 txq_pcpu->count > 0) {
074c74df 3182 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
edc660fa
MW		 3183
3184 mvpp2_timer_set(port_pcpu);
3185 }
3186
e531f767
AT		 3187 if (test_bit(thread, &port->priv->lock_map))
3188 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
3189
3f518509
MW		 3190 return NETDEV_TX_OK;
3191}
3192
3193static inline void mvpp2_cause_error(struct net_device *dev, int cause)
3194{
3195 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
3196 netdev_err(dev, "FCS error\n");
3197 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
3198 netdev_err(dev, "rx fifo overrun error\n");
3199 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
3200 netdev_err(dev, "tx fifo underrun error\n");
3201}
3202
edc660fa 3203static int mvpp2_poll(struct napi_struct *napi, int budget)
3f518509 3204{
213f428f 3205 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
edc660fa
MW		 3206 int rx_done = 0;
3207 struct mvpp2_port *port = netdev_priv(napi->dev);
591f4cfa 3208 struct mvpp2_queue_vector *qv;
e531f767 3209 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3f518509 3210
591f4cfa
TP		 3211 qv = container_of(napi, struct mvpp2_queue_vector, napi);
3212
3f518509
MW		 3213 /* Rx/Tx cause register
3214 *
3215 * Bits 0-15: each bit indicates received packets on the Rx queue
3216 * (bit 0 is for Rx queue 0).
3217 *
3218 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
3219 * (bit 16 is for Tx queue 0).
3220 *
3221 * Each CPU has its own Rx/Tx cause register
3222 */
1068549c 3223 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
cdcfeb0f 3224 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
3f518509 3225
213f428f 3226 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
3f518509
MW		 3227 if (cause_misc) {
3228 mvpp2_cause_error(port->dev, cause_misc);
3229
3230 /* Clear the cause register */
3231 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
1068549c 3232 mvpp2_thread_write(port->priv, thread,
a786841d
TP		 3233 MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
3234 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
3f518509
MW		 3235 }
3236
774268f3
AT		 3237 if (port->has_tx_irqs) {
3238 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3239 if (cause_tx) {
3240 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
3241 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
3242 }
213f428f 3243 }
3f518509
MW		 3244
3245 /* Process RX packets */
70afb58e
AT		 3246 cause_rx = cause_rx_tx &
3247 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
213f428f 3248 cause_rx <<= qv->first_rxq;
591f4cfa 3249 cause_rx |= qv->pending_cause_rx;
3f518509
MW		 3250 while (cause_rx && budget > 0) {
3251 int count;
3252 struct mvpp2_rx_queue *rxq;
3253
3254 rxq = mvpp2_get_rx_queue(port, cause_rx);
3255 if (!rxq)
3256 break;
3257
591f4cfa 3258 count = mvpp2_rx(port, napi, budget, rxq);
3f518509
MW		 3259 rx_done += count;
3260 budget -= count;
3261 if (budget > 0) {
3262 /* Clear the bit associated to this Rx queue
3263 * so that next iteration will continue from
3264 * the next Rx queue.
3265 */
3266 cause_rx &= ~(1 << rxq->logic_rxq);
3267 }
3268 }
3269
3270 if (budget > 0) {
3271 cause_rx = 0;
6ad20165 3272 napi_complete_done(napi, rx_done);
3f518509 3273
591f4cfa 3274 mvpp2_qvec_interrupt_enable(qv);
3f518509 3275 }
591f4cfa 3276 qv->pending_cause_rx = cause_rx;
3f518509
MW		 3277 return rx_done;
3278}
3279
4bb04326 3280static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
3f518509 3281{
4bb04326
AT		 3282 u32 ctrl3;
3283
5434e8fa
AT		 3284 /* Set the GMAC & XLG MAC in reset */
3285 mvpp2_mac_reset_assert(port);
3286
7409e66e
AT		 3287 /* Set the MPCS and XPCS in reset */
3288 mvpp22_pcs_reset_assert(port);
3289
4bb04326
AT		 3290 /* comphy reconfiguration */
3291 mvpp22_comphy_init(port);
3292
3293 /* gop reconfiguration */
3294 mvpp22_gop_init(port);
3295
7409e66e
AT		 3296 mvpp22_pcs_reset_deassert(port);
3297
4bb04326
AT		 3298 /* Only GOP port 0 has an XLG MAC */
3299 if (port->gop_id == 0) {
3300 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
3301 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3302
b7d286f0 3303 if (mvpp2_is_xlg(port->phy_interface))
4bb04326
AT		 3304 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
3305 else
3306 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3307
3308 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
3309 }
8e07269d 3310
b7d286f0 3311 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface))
76eb1b1d
SC		 3312 mvpp2_xlg_max_rx_size_set(port);
3313 else
3314 mvpp2_gmac_max_rx_size_set(port);
4bb04326
AT		 3315}
3316
3317/* Set hw internals when starting port */
3318static void mvpp2_start_dev(struct mvpp2_port *port)
3319{
3320 int i;
76eb1b1d 3321
3f518509
MW		 3322 mvpp2_txp_max_tx_size_set(port);
3323
591f4cfa
TP		 3324 for (i = 0; i < port->nqvecs; i++)
3325 napi_enable(&port->qvecs[i].napi);
3f518509 3326
543ec376 3327 /* Enable interrupts on all threads */
3f518509
MW		 3328 mvpp2_interrupts_enable(port);
3329
4bb04326
AT		 3330 if (port->priv->hw_version == MVPP22)
3331 mvpp22_mode_reconfigure(port);
3332
3333 if (port->phylink) {
3334 phylink_start(port->phylink);
3335 } else {
3336 /* Phylink isn't used as of now for ACPI, so the MAC has to be
3337 * configured manually when the interface is started. This will
3338 * be removed as soon as the phylink ACPI support lands in.
3339 */
3340 struct phylink_link_state state = {
3341 .interface = port->phy_interface,
4bb04326 3342 };
44cc27e4
IC		 3343 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
3344 mvpp2_mac_link_up(&port->phylink_config, MLO_AN_INBAND,
3345 port->phy_interface, NULL);
542897d9 3346 }
f84bf386 3347
3f518509
MW		 3348 netif_tx_start_all_queues(port->dev);
3349}
3350
3351/* Set hw internals when stopping port */
3352static void mvpp2_stop_dev(struct mvpp2_port *port)
3353{
591f4cfa 3354 int i;
8e07269d 3355
543ec376 3356 /* Disable interrupts on all threads */
3f518509
MW		 3357 mvpp2_interrupts_disable(port);
3358
591f4cfa
TP		 3359 for (i = 0; i < port->nqvecs; i++)
3360 napi_disable(&port->qvecs[i].napi);
3f518509 3361
4bb04326
AT		 3362 if (port->phylink)
3363 phylink_stop(port->phylink);
542897d9 3364 phy_power_off(port->comphy);
3f518509
MW		 3365}
3366
3f518509
MW		 3367static int mvpp2_check_ringparam_valid(struct net_device *dev,
3368 struct ethtool_ringparam *ring)
3369{
3370 u16 new_rx_pending = ring->rx_pending;
3371 u16 new_tx_pending = ring->tx_pending;
3372
3373 if (ring->rx_pending == 0 || ring->tx_pending == 0)
3374 return -EINVAL;
3375
7cf87e4a
YM		 3376 if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
3377 new_rx_pending = MVPP2_MAX_RXD_MAX;
3f518509
MW		 3378 else if (!IS_ALIGNED(ring->rx_pending, 16))
3379 new_rx_pending = ALIGN(ring->rx_pending, 16);
3380
7cf87e4a
YM		 3381 if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
3382 new_tx_pending = MVPP2_MAX_TXD_MAX;
3f518509
MW		 3383 else if (!IS_ALIGNED(ring->tx_pending, 32))
3384 new_tx_pending = ALIGN(ring->tx_pending, 32);
3385
76e583c5
AT		 3386 /* The Tx ring size cannot be smaller than the minimum number of
3387 * descriptors needed for TSO.
3388 */
3389 if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
3390 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
3391
3f518509
MW		 3392 if (ring->rx_pending != new_rx_pending) {
3393 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
3394 ring->rx_pending, new_rx_pending);
3395 ring->rx_pending = new_rx_pending;
3396 }
3397
3398 if (ring->tx_pending != new_tx_pending) {
3399 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
3400 ring->tx_pending, new_tx_pending);
3401 ring->tx_pending = new_tx_pending;
3402 }
3403
3404 return 0;
3405}
3406
26975821 3407static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
3f518509
MW		 3408{
3409 u32 mac_addr_l, mac_addr_m, mac_addr_h;
3410
3411 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3412 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
3413 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
3414 addr[0] = (mac_addr_h >> 24) & 0xFF;
3415 addr[1] = (mac_addr_h >> 16) & 0xFF;
3416 addr[2] = (mac_addr_h >> 8) & 0xFF;
3417 addr[3] = mac_addr_h & 0xFF;
3418 addr[4] = mac_addr_m & 0xFF;
3419 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
3420}
3421
591f4cfa
TP		 3422static int mvpp2_irqs_init(struct mvpp2_port *port)
3423{
3424 int err, i;
3425
3426 for (i = 0; i < port->nqvecs; i++) {
3427 struct mvpp2_queue_vector *qv = port->qvecs + i;
3428
a6b3a3fa
MZ		 3429 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
3430 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
3431 if (!qv->mask) {
3432 err = -ENOMEM;
3433 goto err;
3434 }
3435
13c249a9 3436 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
a6b3a3fa 3437 }
13c249a9 3438
591f4cfa
TP		 3439 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
3440 if (err)
3441 goto err;
213f428f 3442
e531f767 3443 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
e531f767
AT		 3444 unsigned int cpu;
3445
3446 for_each_present_cpu(cpu) {
3447 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
3448 qv->sw_thread_id)
a6b3a3fa 3449 cpumask_set_cpu(cpu, qv->mask);
e531f767
AT		 3450 }
3451
a6b3a3fa 3452 irq_set_affinity_hint(qv->irq, qv->mask);
e531f767 3453 }
591f4cfa
TP		 3454 }
3455
3456 return 0;
3457err:
3458 for (i = 0; i < port->nqvecs; i++) {
3459 struct mvpp2_queue_vector *qv = port->qvecs + i;
3460
213f428f 3461 irq_set_affinity_hint(qv->irq, NULL);
a6b3a3fa
MZ		 3462 kfree(qv->mask);
3463 qv->mask = NULL;
591f4cfa
TP		 3464 free_irq(qv->irq, qv);
3465 }
3466
3467 return err;
3468}
3469
3470static void mvpp2_irqs_deinit(struct mvpp2_port *port)
3471{
3472 int i;
3473
3474 for (i = 0; i < port->nqvecs; i++) {
3475 struct mvpp2_queue_vector *qv = port->qvecs + i;
3476
213f428f 3477 irq_set_affinity_hint(qv->irq, NULL);
a6b3a3fa
MZ		 3478 kfree(qv->mask);
3479 qv->mask = NULL;
13c249a9 3480 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
591f4cfa
TP		 3481 free_irq(qv->irq, qv);
3482 }
3483}
3484
4c4a5686
YM		 3485static bool mvpp22_rss_is_supported(void)
3486{
3487 return queue_mode == MVPP2_QDIST_MULTI_MODE;
3488}
3489
3f518509
MW		 3490static int mvpp2_open(struct net_device *dev)
3491{
3492 struct mvpp2_port *port = netdev_priv(dev);
fd3651b2 3493 struct mvpp2 *priv = port->priv;
3f518509
MW		 3494 unsigned char mac_bcast[ETH_ALEN] = {
3495 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4bb04326 3496 bool valid = false;
3f518509
MW		 3497 int err;
3498
ce2a27c7 3499 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
3f518509
MW		 3500 if (err) {
3501 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3502 return err;
3503 }
ce2a27c7 3504 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
3f518509 3505 if (err) {
ce2a27c7 3506 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
3f518509
MW		 3507 return err;
3508 }
3509 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
3510 if (err) {
3511 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
3512 return err;
3513 }
3514 err = mvpp2_prs_def_flow(port);
3515 if (err) {
3516 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3517 return err;
3518 }
3519
3520 /* Allocate the Rx/Tx queues */
3521 err = mvpp2_setup_rxqs(port);
3522 if (err) {
3523 netdev_err(port->dev, "cannot allocate Rx queues\n");
3524 return err;
3525 }
3526
3527 err = mvpp2_setup_txqs(port);
3528 if (err) {
3529 netdev_err(port->dev, "cannot allocate Tx queues\n");
3530 goto err_cleanup_rxqs;
3531 }
3532
591f4cfa 3533 err = mvpp2_irqs_init(port);
3f518509 3534 if (err) {
591f4cfa 3535 netdev_err(port->dev, "cannot init IRQs\n");
3f518509
MW		 3536 goto err_cleanup_txqs;
3537 }
3538
4bb04326
AT		 3539 /* Phylink isn't supported yet in ACPI mode */
3540 if (port->of_node) {
3541 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
3542 if (err) {
3543 netdev_err(port->dev, "could not attach PHY (%d)\n",
3544 err);
3545 goto err_free_irq;
3546 }
3547
3548 valid = true;
3549 }
3550
3551 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) {
fd3651b2
AT		 3552 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
3553 dev->name, port);
3554 if (err) {
3555 netdev_err(port->dev, "cannot request link IRQ %d\n",
3556 port->link_irq);
3557 goto err_free_irq;
3558 }
3559
3560 mvpp22_gop_setup_irq(port);
fd3651b2 3561
4bb04326
AT		 3562 /* In default link is down */
3563 netif_carrier_off(port->dev);
3f518509 3564
4bb04326
AT		 3565 valid = true;
3566 } else {
3567 port->link_irq = 0;
3568 }
3569
3570 if (!valid) {
3571 netdev_err(port->dev,
3572 "invalid configuration: no dt or link IRQ");
3573 goto err_free_irq;
3574 }
3f518509
MW		 3575
3576 /* Unmask interrupts on all CPUs */
3577 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
213f428f 3578 mvpp2_shared_interrupt_mask_unmask(port, false);
3f518509
MW		 3579
3580 mvpp2_start_dev(port);
3581
118d6298 3582 /* Start hardware statistics gathering */
e5c500eb 3583 queue_delayed_work(priv->stats_queue, &port->stats_work,
118d6298
MR		 3584 MVPP2_MIB_COUNTERS_STATS_DELAY);
3585
3f518509
MW		 3586 return 0;
3587
3588err_free_irq:
591f4cfa 3589 mvpp2_irqs_deinit(port);
3f518509
MW		 3590err_cleanup_txqs:
3591 mvpp2_cleanup_txqs(port);
3592err_cleanup_rxqs:
3593 mvpp2_cleanup_rxqs(port);
3594 return err;
3595}
3596
3597static int mvpp2_stop(struct net_device *dev)
3598{
3599 struct mvpp2_port *port = netdev_priv(dev);
edc660fa 3600 struct mvpp2_port_pcpu *port_pcpu;
074c74df 3601 unsigned int thread;
3f518509
MW		 3602
3603 mvpp2_stop_dev(port);
3f518509 3604
e531f767 3605 /* Mask interrupts on all threads */
3f518509 3606 on_each_cpu(mvpp2_interrupts_mask, port, 1);
213f428f 3607 mvpp2_shared_interrupt_mask_unmask(port, true);
3f518509 3608
4bb04326
AT		 3609 if (port->phylink)
3610 phylink_disconnect_phy(port->phylink);
3611 if (port->link_irq)
fd3651b2
AT		 3612 free_irq(port->link_irq, port);
3613
591f4cfa 3614 mvpp2_irqs_deinit(port);
213f428f 3615 if (!port->has_tx_irqs) {
e531f767 3616 for (thread = 0; thread < port->priv->nthreads; thread++) {
074c74df 3617 port_pcpu = per_cpu_ptr(port->pcpu, thread);
edc660fa 3618
213f428f
TP		 3619 hrtimer_cancel(&port_pcpu->tx_done_timer);
3620 port_pcpu->timer_scheduled = false;
3621 tasklet_kill(&port_pcpu->tx_done_tasklet);
3622 }
edc660fa 3623 }
3f518509
MW		 3624 mvpp2_cleanup_rxqs(port);
3625 mvpp2_cleanup_txqs(port);
3626
e5c500eb 3627 cancel_delayed_work_sync(&port->stats_work);
118d6298 3628
1f69afce
AT		 3629 mvpp2_mac_reset_assert(port);
3630 mvpp22_pcs_reset_assert(port);
3631
3f518509
MW		 3632 return 0;
3633}
3634
10fea26c
MC		 3635static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
3636 struct netdev_hw_addr_list *list)
3f518509 3637{
3f518509 3638 struct netdev_hw_addr *ha;
10fea26c
MC		 3639 int ret;
3640
3641 netdev_hw_addr_list_for_each(ha, list) {
3642 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
3643 if (ret)
3644 return ret;
3f518509 3645 }
56beda3d 3646
10fea26c
MC		 3647 return 0;
3648}
3649
3650static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
3651{
3652 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
56beda3d 3653 mvpp2_prs_vid_enable_filtering(port);
10fea26c
MC		 3654 else
3655 mvpp2_prs_vid_disable_filtering(port);
3656
3657 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3658 MVPP2_PRS_L2_UNI_CAST, enable);
3659
3660 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3661 MVPP2_PRS_L2_MULTI_CAST, enable);
3662}
3663
3664static void mvpp2_set_rx_mode(struct net_device *dev)
3665{
3666 struct mvpp2_port *port = netdev_priv(dev);
3667
3668 /* Clear the whole UC and MC list */
3669 mvpp2_prs_mac_del_all(port);
3670
3671 if (dev->flags & IFF_PROMISC) {
3672 mvpp2_set_rx_promisc(port, true);
3673 return;
3674 }
3675
3676 mvpp2_set_rx_promisc(port, false);
3677
3678 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
3679 mvpp2_prs_mac_da_accept_list(port, &dev->uc))
3680 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3681 MVPP2_PRS_L2_UNI_CAST, true);
3682
3683 if (dev->flags & IFF_ALLMULTI) {
3684 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3685 MVPP2_PRS_L2_MULTI_CAST, true);
3686 return;
3687 }
3688
3689 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
3690 mvpp2_prs_mac_da_accept_list(port, &dev->mc))
3691 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3692 MVPP2_PRS_L2_MULTI_CAST, true);
3f518509
MW		 3693}
3694
3695static int mvpp2_set_mac_address(struct net_device *dev, void *p)
3696{
3f518509
MW		 3697 const struct sockaddr *addr = p;
3698 int err;
3699
5b0ab2f4
YM		 3700 if (!is_valid_ether_addr(addr->sa_data))
3701 return -EADDRNOTAVAIL;
3f518509
MW		 3702
3703 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
5b0ab2f4
YM		 3704 if (err) {
3705 /* Reconfigure parser accept the original MAC address */
3706 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
3707 netdev_err(dev, "failed to change MAC address\n");
3708 }
3f518509
MW		 3709 return err;
3710}
3711
3712static int mvpp2_change_mtu(struct net_device *dev, int mtu)
3713{
3714 struct mvpp2_port *port = netdev_priv(dev);
230bd958 3715 bool running = netif_running(dev);
3f518509
MW		 3716 int err;
3717
5777987e
JW		 3718 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
3719 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
3720 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
3721 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
3f518509
MW		 3722 }
3723
230bd958
MC		 3724 if (running)
3725 mvpp2_stop_dev(port);
3f518509
MW		 3726
3727 err = mvpp2_bm_update_mtu(dev, mtu);
230bd958
MC		 3728 if (err) {
3729 netdev_err(dev, "failed to change MTU\n");
3730 /* Reconfigure BM to the original MTU */
3731 mvpp2_bm_update_mtu(dev, dev->mtu);
3732 } else {
3f518509 3733 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3f518509
MW		 3734 }
3735
230bd958
MC		 3736 if (running) {
3737 mvpp2_start_dev(port);
3738 mvpp2_egress_enable(port);
3739 mvpp2_ingress_enable(port);
3740 }
3f518509 3741
3f518509
MW		 3742 return err;
3743}
3744
bc1f4470 3745static void
3f518509
MW		 3746mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
3747{
3748 struct mvpp2_port *port = netdev_priv(dev);
3749 unsigned int start;
850623b3 3750 unsigned int cpu;
3f518509
MW		 3751
3752 for_each_possible_cpu(cpu) {
3753 struct mvpp2_pcpu_stats *cpu_stats;
3754 u64 rx_packets;
3755 u64 rx_bytes;
3756 u64 tx_packets;
3757 u64 tx_bytes;
3758
3759 cpu_stats = per_cpu_ptr(port->stats, cpu);
3760 do {
3761 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
3762 rx_packets = cpu_stats->rx_packets;
3763 rx_bytes = cpu_stats->rx_bytes;
3764 tx_packets = cpu_stats->tx_packets;
3765 tx_bytes = cpu_stats->tx_bytes;
3766 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
3767
3768 stats->rx_packets += rx_packets;
3769 stats->rx_bytes += rx_bytes;
3770 stats->tx_packets += tx_packets;
3771 stats->tx_bytes += tx_bytes;
3772 }
3773
3774 stats->rx_errors = dev->stats.rx_errors;
3775 stats->rx_dropped = dev->stats.rx_dropped;
3776 stats->tx_dropped = dev->stats.tx_dropped;
3f518509
MW		 3777}
3778
bd695a5f
TP		 3779static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3780{
4bb04326 3781 struct mvpp2_port *port = netdev_priv(dev);
bd695a5f 3782
4bb04326 3783 if (!port->phylink)
bd695a5f
TP		 3784 return -ENOTSUPP;
3785
4bb04326 3786 return phylink_mii_ioctl(port->phylink, ifr, cmd);
bd695a5f
TP		 3787}
3788
56beda3d
MC		 3789static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
3790{
3791 struct mvpp2_port *port = netdev_priv(dev);
3792 int ret;
3793
3794 ret = mvpp2_prs_vid_entry_add(port, vid);
3795 if (ret)
3796 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
3797 MVPP2_PRS_VLAN_FILT_MAX - 1);
3798 return ret;
3799}
3800
3801static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
3802{
3803 struct mvpp2_port *port = netdev_priv(dev);
3804
3805 mvpp2_prs_vid_entry_remove(port, vid);
3806 return 0;
3807}
3808
3809static int mvpp2_set_features(struct net_device *dev,
3810 netdev_features_t features)
3811{
3812 netdev_features_t changed = dev->features ^ features;
3813 struct mvpp2_port *port = netdev_priv(dev);
3814
3815 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
3816 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
3817 mvpp2_prs_vid_enable_filtering(port);
3818 } else {
3819 /* Invalidate all registered VID filters for this
3820 * port
3821 */
3822 mvpp2_prs_vid_remove_all(port);
3823
3824 mvpp2_prs_vid_disable_filtering(port);
3825 }
3826 }
3827
d33ec452
MC		 3828 if (changed & NETIF_F_RXHASH) {
3829 if (features & NETIF_F_RXHASH)
6310f77d 3830 mvpp22_port_rss_enable(port);
d33ec452 3831 else
6310f77d 3832 mvpp22_port_rss_disable(port);
d33ec452
MC		 3833 }
3834
56beda3d
MC		 3835 return 0;
3836}
3837
3f518509
MW		 3838/* Ethtool methods */
3839
4bb04326
AT		 3840static int mvpp2_ethtool_nway_reset(struct net_device *dev)
3841{
3842 struct mvpp2_port *port = netdev_priv(dev);
3843
3844 if (!port->phylink)
3845 return -ENOTSUPP;
3846
3847 return phylink_ethtool_nway_reset(port->phylink);
3848}
3849
3f518509
MW		 3850/* Set interrupt coalescing for ethtools */
3851static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
3852 struct ethtool_coalesce *c)
3853{
3854 struct mvpp2_port *port = netdev_priv(dev);
3855 int queue;
3856
09f83975 3857 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 3858 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3859
3860 rxq->time_coal = c->rx_coalesce_usecs;
3861 rxq->pkts_coal = c->rx_max_coalesced_frames;
d63f9e41
TP		 3862 mvpp2_rx_pkts_coal_set(port, rxq);
3863 mvpp2_rx_time_coal_set(port, rxq);
3f518509
MW		 3864 }
3865
213f428f
TP		 3866 if (port->has_tx_irqs) {
3867 port->tx_time_coal = c->tx_coalesce_usecs;
3868 mvpp2_tx_time_coal_set(port);
3869 }
3870
09f83975 3871 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 3872 struct mvpp2_tx_queue *txq = port->txqs[queue];
3873
3874 txq->done_pkts_coal = c->tx_max_coalesced_frames;
213f428f
TP		 3875
3876 if (port->has_tx_irqs)
3877 mvpp2_tx_pkts_coal_set(port, txq);
3f518509
MW		 3878 }
3879
3f518509
MW		 3880 return 0;
3881}
3882
3883/* get coalescing for ethtools */
3884static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
3885 struct ethtool_coalesce *c)
3886{
3887 struct mvpp2_port *port = netdev_priv(dev);
3888
385c284f
AT		 3889 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
3890 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
3891 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
24b28ccb 3892 c->tx_coalesce_usecs = port->tx_time_coal;
3f518509
MW		 3893 return 0;
3894}
3895
3896static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
3897 struct ethtool_drvinfo *drvinfo)
3898{
3899 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
3900 sizeof(drvinfo->driver));
3901 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
3902 sizeof(drvinfo->version));
3903 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3904 sizeof(drvinfo->bus_info));
3905}
3906
3907static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
3908 struct ethtool_ringparam *ring)
3909{
3910 struct mvpp2_port *port = netdev_priv(dev);
3911
7cf87e4a
YM		 3912 ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
3913 ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
3f518509
MW		 3914 ring->rx_pending = port->rx_ring_size;
3915 ring->tx_pending = port->tx_ring_size;
3916}
3917
3918static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
3919 struct ethtool_ringparam *ring)
3920{
3921 struct mvpp2_port *port = netdev_priv(dev);
3922 u16 prev_rx_ring_size = port->rx_ring_size;
3923 u16 prev_tx_ring_size = port->tx_ring_size;
3924 int err;
3925
3926 err = mvpp2_check_ringparam_valid(dev, ring);
3927 if (err)
3928 return err;
3929
3930 if (!netif_running(dev)) {
3931 port->rx_ring_size = ring->rx_pending;
3932 port->tx_ring_size = ring->tx_pending;
3933 return 0;
3934 }
3935
3936 /* The interface is running, so we have to force a
3937 * reallocation of the queues
3938 */
3939 mvpp2_stop_dev(port);
3940 mvpp2_cleanup_rxqs(port);
3941 mvpp2_cleanup_txqs(port);
3942
3943 port->rx_ring_size = ring->rx_pending;
3944 port->tx_ring_size = ring->tx_pending;
3945
3946 err = mvpp2_setup_rxqs(port);
3947 if (err) {
3948 /* Reallocate Rx queues with the original ring size */
3949 port->rx_ring_size = prev_rx_ring_size;
3950 ring->rx_pending = prev_rx_ring_size;
3951 err = mvpp2_setup_rxqs(port);
3952 if (err)
3953 goto err_out;
3954 }
3955 err = mvpp2_setup_txqs(port);
3956 if (err) {
3957 /* Reallocate Tx queues with the original ring size */
3958 port->tx_ring_size = prev_tx_ring_size;
3959 ring->tx_pending = prev_tx_ring_size;
3960 err = mvpp2_setup_txqs(port);
3961 if (err)
3962 goto err_clean_rxqs;
3963 }
3964
3965 mvpp2_start_dev(port);
3966 mvpp2_egress_enable(port);
3967 mvpp2_ingress_enable(port);
3968
3969 return 0;
3970
3971err_clean_rxqs:
3972 mvpp2_cleanup_rxqs(port);
3973err_out:
dfd4240a 3974 netdev_err(dev, "failed to change ring parameters");
3f518509
MW		 3975 return err;
3976}
3977
4bb04326
AT		 3978static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
3979 struct ethtool_pauseparam *pause)
3980{
3981 struct mvpp2_port *port = netdev_priv(dev);
3982
3983 if (!port->phylink)
3984 return;
3985
3986 phylink_ethtool_get_pauseparam(port->phylink, pause);
3987}
3988
3989static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
3990 struct ethtool_pauseparam *pause)
3991{
3992 struct mvpp2_port *port = netdev_priv(dev);
3993
3994 if (!port->phylink)
3995 return -ENOTSUPP;
3996
3997 return phylink_ethtool_set_pauseparam(port->phylink, pause);
3998}
3999
4000static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
4001 struct ethtool_link_ksettings *cmd)
4002{
4003 struct mvpp2_port *port = netdev_priv(dev);
4004
4005 if (!port->phylink)
4006 return -ENOTSUPP;
4007
4008 return phylink_ethtool_ksettings_get(port->phylink, cmd);
4009}
4010
4011static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
4012 const struct ethtool_link_ksettings *cmd)
4013{
4014 struct mvpp2_port *port = netdev_priv(dev);
4015
4016 if (!port->phylink)
4017 return -ENOTSUPP;
4018
4019 return phylink_ethtool_ksettings_set(port->phylink, cmd);
4020}
4021
8179642b
AT		 4022static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
4023 struct ethtool_rxnfc *info, u32 *rules)
4024{
4025 struct mvpp2_port *port = netdev_priv(dev);
90b509b3 4026 int ret = 0, i, loc = 0;
8179642b
AT		 4027
4028 if (!mvpp22_rss_is_supported())
4029 return -EOPNOTSUPP;
4030
4031 switch (info->cmd) {
436d4fdb
MC		 4032 case ETHTOOL_GRXFH:
4033 ret = mvpp2_ethtool_rxfh_get(port, info);
4034 break;
8179642b
AT		 4035 case ETHTOOL_GRXRINGS:
4036 info->data = port->nrxqs;
4037 break;
90b509b3
MC		 4038 case ETHTOOL_GRXCLSRLCNT:
4039 info->rule_cnt = port->n_rfs_rules;
4040 break;
4041 case ETHTOOL_GRXCLSRULE:
4042 ret = mvpp2_ethtool_cls_rule_get(port, info);
4043 break;
4044 case ETHTOOL_GRXCLSRLALL:
ae8e1d5e 4045 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) {
90b509b3
MC		 4046 if (port->rfs_rules[i])
4047 rules[loc++] = i;
4048 }
4049 break;
8179642b
AT		 4050 default:
4051 return -ENOTSUPP;
4052 }
4053
436d4fdb
MC		 4054 return ret;
4055}
4056
4057static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
4058 struct ethtool_rxnfc *info)
4059{
4060 struct mvpp2_port *port = netdev_priv(dev);
4061 int ret = 0;
4062
4063 if (!mvpp22_rss_is_supported())
4064 return -EOPNOTSUPP;
4065
4066 switch (info->cmd) {
4067 case ETHTOOL_SRXFH:
4068 ret = mvpp2_ethtool_rxfh_set(port, info);
4069 break;
90b509b3
MC		 4070 case ETHTOOL_SRXCLSRLINS:
4071 ret = mvpp2_ethtool_cls_rule_ins(port, info);
4072 break;
4073 case ETHTOOL_SRXCLSRLDEL:
4074 ret = mvpp2_ethtool_cls_rule_del(port, info);
4075 break;
436d4fdb
MC		 4076 default:
4077 return -EOPNOTSUPP;
4078 }
4079 return ret;
8179642b
AT		 4080}
4081
4082static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
4083{
4084 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0;
4085}
4086
4087static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
4088 u8 *hfunc)
4089{
4090 struct mvpp2_port *port = netdev_priv(dev);
895586d5 4091 int ret = 0;
8179642b
AT		 4092
4093 if (!mvpp22_rss_is_supported())
4094 return -EOPNOTSUPP;
4095
4096 if (indir)
895586d5 4097 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir);
8179642b
AT		 4098
4099 if (hfunc)
4100 *hfunc = ETH_RSS_HASH_CRC32;
4101
895586d5 4102 return ret;
8179642b
AT		 4103}
4104
4105static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
4106 const u8 *key, const u8 hfunc)
4107{
4108 struct mvpp2_port *port = netdev_priv(dev);
895586d5 4109 int ret = 0;
8179642b
AT		 4110
4111 if (!mvpp22_rss_is_supported())
4112 return -EOPNOTSUPP;
4113
4114 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
4115 return -EOPNOTSUPP;
4116
4117 if (key)
4118 return -EOPNOTSUPP;
4119
895586d5
MC		 4120 if (indir)
4121 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir);
8179642b 4122
895586d5 4123 return ret;
8179642b
AT		 4124}
4125
895586d5
MC		 4126static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,
4127 u8 *key, u8 *hfunc, u32 rss_context)
4128{
4129 struct mvpp2_port *port = netdev_priv(dev);
4130 int ret = 0;
4131
4132 if (!mvpp22_rss_is_supported())
4133 return -EOPNOTSUPP;
4134
4135 if (hfunc)
4136 *hfunc = ETH_RSS_HASH_CRC32;
4137
4138 if (indir)
4139 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir);
4140
4141 return ret;
4142}
4143
4144static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,
4145 const u32 *indir, const u8 *key,
4146 const u8 hfunc, u32 *rss_context,
4147 bool delete)
4148{
4149 struct mvpp2_port *port = netdev_priv(dev);
4150 int ret;
4151
4152 if (!mvpp22_rss_is_supported())
4153 return -EOPNOTSUPP;
4154
4155 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
4156 return -EOPNOTSUPP;
4157
4158 if (key)
4159 return -EOPNOTSUPP;
4160
4161 if (delete)
4162 return mvpp22_port_rss_ctx_delete(port, *rss_context);
4163
4164 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
4165 ret = mvpp22_port_rss_ctx_create(port, rss_context);
4166 if (ret)
4167 return ret;
4168 }
4169
4170 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir);
4171}
3f518509
MW		 4172/* Device ops */
4173
4174static const struct net_device_ops mvpp2_netdev_ops = {
4175 .ndo_open = mvpp2_open,
4176 .ndo_stop = mvpp2_stop,
4177 .ndo_start_xmit = mvpp2_tx,
4178 .ndo_set_rx_mode = mvpp2_set_rx_mode,
4179 .ndo_set_mac_address = mvpp2_set_mac_address,
4180 .ndo_change_mtu = mvpp2_change_mtu,
4181 .ndo_get_stats64 = mvpp2_get_stats64,
bd695a5f 4182 .ndo_do_ioctl = mvpp2_ioctl,
56beda3d
MC		 4183 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid,
4184 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid,
4185 .ndo_set_features = mvpp2_set_features,
3f518509
MW		 4186};
4187
4188static const struct ethtool_ops mvpp2_eth_tool_ops = {
4bb04326 4189 .nway_reset = mvpp2_ethtool_nway_reset,
dcd3e73a
AT		 4190 .get_link = ethtool_op_get_link,
4191 .set_coalesce = mvpp2_ethtool_set_coalesce,
4192 .get_coalesce = mvpp2_ethtool_get_coalesce,
4193 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
4194 .get_ringparam = mvpp2_ethtool_get_ringparam,
4195 .set_ringparam = mvpp2_ethtool_set_ringparam,
4196 .get_strings = mvpp2_ethtool_get_strings,
4197 .get_ethtool_stats = mvpp2_ethtool_get_stats,
4198 .get_sset_count = mvpp2_ethtool_get_sset_count,
4bb04326
AT		 4199 .get_pauseparam = mvpp2_ethtool_get_pause_param,
4200 .set_pauseparam = mvpp2_ethtool_set_pause_param,
4201 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings,
4202 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings,
8179642b 4203 .get_rxnfc = mvpp2_ethtool_get_rxnfc,
436d4fdb 4204 .set_rxnfc = mvpp2_ethtool_set_rxnfc,
8179642b
AT		 4205 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size,
4206 .get_rxfh = mvpp2_ethtool_get_rxfh,
4207 .set_rxfh = mvpp2_ethtool_set_rxfh,
895586d5
MC		 4208 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context,
4209 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context,
3f518509
MW		 4210};
4211
213f428f
TP		 4212/* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
4213 * had a single IRQ defined per-port.
4214 */
4215static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
4216 struct device_node *port_node)
591f4cfa
TP		 4217{
4218 struct mvpp2_queue_vector *v = &port->qvecs[0];
4219
4220 v->first_rxq = 0;
4221 v->nrxqs = port->nrxqs;
4222 v->type = MVPP2_QUEUE_VECTOR_SHARED;
4223 v->sw_thread_id = 0;
4224 v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
4225 v->port = port;
4226 v->irq = irq_of_parse_and_map(port_node, 0);
4227 if (v->irq <= 0)
4228 return -EINVAL;
4229 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4230 NAPI_POLL_WEIGHT);
4231
4232 port->nqvecs = 1;
4233
4234 return 0;
4235}
4236
213f428f
TP		 4237static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
4238 struct device_node *port_node)
4239{
e531f767 4240 struct mvpp2 *priv = port->priv;
213f428f
TP		 4241 struct mvpp2_queue_vector *v;
4242 int i, ret;
4243
e531f767
AT		 4244 switch (queue_mode) {
4245 case MVPP2_QDIST_SINGLE_MODE:
4246 port->nqvecs = priv->nthreads + 1;
4247 break;
4248 case MVPP2_QDIST_MULTI_MODE:
4249 port->nqvecs = priv->nthreads;
4250 break;
4251 }
213f428f
TP		 4252
4253 for (i = 0; i < port->nqvecs; i++) {
4254 char irqname[16];
4255
4256 v = port->qvecs + i;
4257
4258 v->port = port;
4259 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
4260 v->sw_thread_id = i;
4261 v->sw_thread_mask = BIT(i);
4262
a9aac385
AT		 4263 if (port->flags & MVPP2_F_DT_COMPAT)
4264 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
4265 else
4266 snprintf(irqname, sizeof(irqname), "hif%d", i);
213f428f
TP		 4267
4268 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
3f136849
AT		 4269 v->first_rxq = i;
4270 v->nrxqs = 1;
213f428f
TP		 4271 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
4272 i == (port->nqvecs - 1)) {
4273 v->first_rxq = 0;
4274 v->nrxqs = port->nrxqs;
4275 v->type = MVPP2_QUEUE_VECTOR_SHARED;
a9aac385
AT		 4276
4277 if (port->flags & MVPP2_F_DT_COMPAT)
4278 strncpy(irqname, "rx-shared", sizeof(irqname));
213f428f
TP		 4279 }
4280
a75edc7c
MW		 4281 if (port_node)
4282 v->irq = of_irq_get_byname(port_node, irqname);
4283 else
4284 v->irq = fwnode_irq_get(port->fwnode, i);
213f428f
TP		 4285 if (v->irq <= 0) {
4286 ret = -EINVAL;
4287 goto err;
4288 }
4289
4290 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4291 NAPI_POLL_WEIGHT);
4292 }
4293
4294 return 0;
4295
4296err:
4297 for (i = 0; i < port->nqvecs; i++)
4298 irq_dispose_mapping(port->qvecs[i].irq);
4299 return ret;
4300}
4301
4302static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
4303 struct device_node *port_node)
4304{
4305 if (port->has_tx_irqs)
4306 return mvpp2_multi_queue_vectors_init(port, port_node);
4307 else
4308 return mvpp2_simple_queue_vectors_init(port, port_node);
4309}
4310
591f4cfa
TP		 4311static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
4312{
4313 int i;
4314
4315 for (i = 0; i < port->nqvecs; i++)
4316 irq_dispose_mapping(port->qvecs[i].irq);
4317}
4318
4319/* Configure Rx queue group interrupt for this port */
4320static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
4321{
4322 struct mvpp2 *priv = port->priv;
4323 u32 val;
4324 int i;
4325
4326 if (priv->hw_version == MVPP21) {
4327 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4328 port->nrxqs);
4329 return;
4330 }
4331
4332 /* Handle the more complicated PPv2.2 case */
4333 for (i = 0; i < port->nqvecs; i++) {
4334 struct mvpp2_queue_vector *qv = port->qvecs + i;
4335
4336 if (!qv->nrxqs)
4337 continue;
4338
4339 val = qv->sw_thread_id;
4340 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
4341 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4342
4343 val = qv->first_rxq;
4344 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
4345 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4346 }
4347}
4348
3f518509
MW		 4349/* Initialize port HW */
4350static int mvpp2_port_init(struct mvpp2_port *port)
4351{
4352 struct device *dev = port->dev->dev.parent;
4353 struct mvpp2 *priv = port->priv;
4354 struct mvpp2_txq_pcpu *txq_pcpu;
074c74df 4355 unsigned int thread;
9bea6897 4356 int queue, err;
3f518509 4357
09f83975
TP		 4358 /* Checks for hardware constraints */
4359 if (port->first_rxq + port->nrxqs >
59b9a31e 4360 MVPP2_MAX_PORTS * priv->max_port_rxqs)
3f518509
MW		 4361 return -EINVAL;
4362
3f136849 4363 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
09f83975
TP		 4364 return -EINVAL;
4365
3f518509
MW		 4366 /* Disable port */
4367 mvpp2_egress_disable(port);
4368 mvpp2_port_disable(port);
4369
213f428f
TP		 4370 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
4371
09f83975 4372 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
3f518509
MW		 4373 GFP_KERNEL);
4374 if (!port->txqs)
4375 return -ENOMEM;
4376
4377 /* Associate physical Tx queues to this port and initialize.
4378 * The mapping is predefined.
4379 */
09f83975 4380 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 4381 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4382 struct mvpp2_tx_queue *txq;
4383
4384 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
177c8d1c
CJ		 4385 if (!txq) {
4386 err = -ENOMEM;
4387 goto err_free_percpu;
4388 }
3f518509
MW		 4389
4390 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
4391 if (!txq->pcpu) {
4392 err = -ENOMEM;
4393 goto err_free_percpu;
4394 }
4395
4396 txq->id = queue_phy_id;
4397 txq->log_id = queue;
4398 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
e531f767 4399 for (thread = 0; thread < priv->nthreads; thread++) {
074c74df
AT		 4400 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4401 txq_pcpu->thread = thread;
3f518509
MW		 4402 }
4403
4404 port->txqs[queue] = txq;
4405 }
4406
09f83975 4407 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
3f518509
MW		 4408 GFP_KERNEL);
4409 if (!port->rxqs) {
4410 err = -ENOMEM;
4411 goto err_free_percpu;
4412 }
4413
4414 /* Allocate and initialize Rx queue for this port */
09f83975 4415 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 4416 struct mvpp2_rx_queue *rxq;
4417
4418 /* Map physical Rx queue to port's logical Rx queue */
4419 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
d82b0c21
JZ		 4420 if (!rxq) {
4421 err = -ENOMEM;
3f518509 4422 goto err_free_percpu;
d82b0c21 4423 }
3f518509
MW		 4424 /* Map this Rx queue to a physical queue */
4425 rxq->id = port->first_rxq + queue;
4426 rxq->port = port->id;
4427 rxq->logic_rxq = queue;
4428
4429 port->rxqs[queue] = rxq;
4430 }
4431
591f4cfa 4432 mvpp2_rx_irqs_setup(port);
3f518509
MW		 4433
4434 /* Create Rx descriptor rings */
09f83975 4435 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 4436 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4437
4438 rxq->size = port->rx_ring_size;
4439 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4440 rxq->time_coal = MVPP2_RX_COAL_USEC;
4441 }
4442
4443 mvpp2_ingress_disable(port);
4444
4445 /* Port default configuration */
4446 mvpp2_defaults_set(port);
4447
4448 /* Port's classifier configuration */
4449 mvpp2_cls_oversize_rxq_set(port);
4450 mvpp2_cls_port_config(port);
4451
e6e21c02 4452 if (mvpp22_rss_is_supported())
6310f77d 4453 mvpp22_port_rss_init(port);
e6e21c02 4454
3f518509
MW		 4455 /* Provide an initial Rx packet size */
4456 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
4457
4458 /* Initialize pools for swf */
4459 err = mvpp2_swf_bm_pool_init(port);
4460 if (err)
4461 goto err_free_percpu;
4462
9bea6897
MC		 4463 /* Clear all port stats */
4464 mvpp2_read_stats(port);
4465 memset(port->ethtool_stats, 0,
4466 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64));
6410c139 4467
3f518509
MW		 4468 return 0;
4469
4470err_free_percpu:
09f83975 4471 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 4472 if (!port->txqs[queue])
4473 continue;
4474 free_percpu(port->txqs[queue]->pcpu);
4475 }
4476 return err;
4477}
4478
a9aac385
AT		 4479static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
4480 unsigned long *flags)
4481{
4482 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
4483 "tx-cpu3" };
4484 int i;
4485
4486 for (i = 0; i < 5; i++)
4487 if (of_property_match_string(port_node, "interrupt-names",
4488 irqs[i]) < 0)
4489 return false;
4490
4491 *flags |= MVPP2_F_DT_COMPAT;
4492 return true;
4493}
4494
4495/* Checks if the port dt description has the required Tx interrupts:
4496 * - PPv2.1: there are no such interrupts.
4497 * - PPv2.2:
4498 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
4499 * - The new ones have: "hifX" with X in [0..8]
4500 *
4501 * All those variants are supported to keep the backward compatibility.
213f428f 4502 */
a9aac385
AT		 4503static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
4504 struct device_node *port_node,
4505 unsigned long *flags)
213f428f 4506{
a9aac385
AT		 4507 char name[5];
4508 int i;
213f428f 4509
fd4a1056
AT		 4510 /* ACPI */
4511 if (!port_node)
4512 return true;
4513
213f428f
TP		 4514 if (priv->hw_version == MVPP21)
4515 return false;
4516
a9aac385
AT		 4517 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
4518 return true;
4519
4520 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
4521 snprintf(name, 5, "hif%d", i);
4522 if (of_property_match_string(port_node, "interrupt-names",
4523 name) < 0)
213f428f
TP		 4524 return false;
4525 }
4526
4527 return true;
4528}
4529
3ba8c81e 4530static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
24812221 4531 struct fwnode_handle *fwnode,
3ba8c81e
AT		 4532 char **mac_from)
4533{
4534 struct mvpp2_port *port = netdev_priv(dev);
4535 char hw_mac_addr[ETH_ALEN] = {0};
24812221 4536 char fw_mac_addr[ETH_ALEN];
3ba8c81e 4537
24812221
MW		 4538 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
4539 *mac_from = "firmware node";
4540 ether_addr_copy(dev->dev_addr, fw_mac_addr);
688cbaf2
AT		 4541 return;
4542 }
d2a6e48e 4543
688cbaf2
AT		 4544 if (priv->hw_version == MVPP21) {
4545 mvpp21_get_mac_address(port, hw_mac_addr);
4546 if (is_valid_ether_addr(hw_mac_addr)) {
4547 *mac_from = "hardware";
4548 ether_addr_copy(dev->dev_addr, hw_mac_addr);
4549 return;
4550 }
3ba8c81e 4551 }
688cbaf2
AT		 4552
4553 *mac_from = "random";
4554 eth_hw_addr_random(dev);
3ba8c81e
AT		 4555}
4556
44cc27e4 4557static void mvpp2_phylink_validate(struct phylink_config *config,
4bb04326
AT		 4558 unsigned long *supported,
4559 struct phylink_link_state *state)
4560{
44cc27e4
IC		 4561 struct mvpp2_port *port = container_of(config, struct mvpp2_port,
4562 phylink_config);
4bb04326
AT		 4563 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
4564
0fb628f0
BS		 4565 /* Invalid combinations */
4566 switch (state->interface) {
4567 case PHY_INTERFACE_MODE_10GKR:
4568 case PHY_INTERFACE_MODE_XAUI:
4569 if (port->gop_id != 0)
4570 goto empty_set;
4571 break;
4572 case PHY_INTERFACE_MODE_RGMII:
4573 case PHY_INTERFACE_MODE_RGMII_ID:
4574 case PHY_INTERFACE_MODE_RGMII_RXID:
4575 case PHY_INTERFACE_MODE_RGMII_TXID:
8b318f30 4576 if (port->priv->hw_version == MVPP22 && port->gop_id == 0)
0fb628f0
BS		 4577 goto empty_set;
4578 break;
4579 default:
4580 break;
4581 }
4582
4bb04326
AT		 4583 phylink_set(mask, Autoneg);
4584 phylink_set_port_modes(mask);
4585 phylink_set(mask, Pause);
4586 phylink_set(mask, Asym_Pause);
4587
d97c9f4a
AT		 4588 switch (state->interface) {
4589 case PHY_INTERFACE_MODE_10GKR:
0fb628f0 4590 case PHY_INTERFACE_MODE_XAUI:
01b3fd5a 4591 case PHY_INTERFACE_MODE_NA:
00679177 4592 if (port->gop_id == 0) {
1b451fb2 4593 phylink_set(mask, 10000baseT_Full);
00679177
AT		 4594 phylink_set(mask, 10000baseCR_Full);
4595 phylink_set(mask, 10000baseSR_Full);
4596 phylink_set(mask, 10000baseLR_Full);
4597 phylink_set(mask, 10000baseLRM_Full);
4598 phylink_set(mask, 10000baseER_Full);
4599 phylink_set(mask, 10000baseKR_Full);
4600 }
d97c9f4a 4601 /* Fall-through */
0fb628f0
BS		 4602 case PHY_INTERFACE_MODE_RGMII:
4603 case PHY_INTERFACE_MODE_RGMII_ID:
4604 case PHY_INTERFACE_MODE_RGMII_RXID:
4605 case PHY_INTERFACE_MODE_RGMII_TXID:
4606 case PHY_INTERFACE_MODE_SGMII:
d97c9f4a
AT		 4607 phylink_set(mask, 10baseT_Half);
4608 phylink_set(mask, 10baseT_Full);
4609 phylink_set(mask, 100baseT_Half);
4610 phylink_set(mask, 100baseT_Full);
d97c9f4a
AT		 4611 /* Fall-through */
4612 case PHY_INTERFACE_MODE_1000BASEX:
a6fe31de 4613 case PHY_INTERFACE_MODE_2500BASEX:
d97c9f4a
AT		 4614 phylink_set(mask, 1000baseT_Full);
4615 phylink_set(mask, 1000baseX_Full);
b38d198c 4616 phylink_set(mask, 2500baseT_Full);
a6fe31de 4617 phylink_set(mask, 2500baseX_Full);
0fb628f0
BS		 4618 break;
4619 default:
4620 goto empty_set;
4bb04326
AT		 4621 }
4622
4623 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
4624 bitmap_and(state->advertising, state->advertising, mask,
4625 __ETHTOOL_LINK_MODE_MASK_NBITS);
0fb628f0
BS		 4626 return;
4627
4628empty_set:
4629 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
4bb04326
AT		 4630}
4631
4632static void mvpp22_xlg_link_state(struct mvpp2_port *port,
4633 struct phylink_link_state *state)
4634{
4635 u32 val;
4636
4637 state->speed = SPEED_10000;
4638 state->duplex = 1;
4639 state->an_complete = 1;
4640
4641 val = readl(port->base + MVPP22_XLG_STATUS);
4642 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
4643
4644 state->pause = 0;
4645 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4646 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
4647 state->pause |= MLO_PAUSE_TX;
4648 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
4649 state->pause |= MLO_PAUSE_RX;
4650}
4651
4652static void mvpp2_gmac_link_state(struct mvpp2_port *port,
4653 struct phylink_link_state *state)
4654{
4655 u32 val;
4656
4657 val = readl(port->base + MVPP2_GMAC_STATUS0);
4658
4659 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
4660 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
4661 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
4662
d97c9f4a
AT		 4663 switch (port->phy_interface) {
4664 case PHY_INTERFACE_MODE_1000BASEX:
4bb04326 4665 state->speed = SPEED_1000;
d97c9f4a 4666 break;
a6fe31de
AT		 4667 case PHY_INTERFACE_MODE_2500BASEX:
4668 state->speed = SPEED_2500;
4669 break;
d97c9f4a
AT		 4670 default:
4671 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
4672 state->speed = SPEED_1000;
4673 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
4674 state->speed = SPEED_100;
4675 else
4676 state->speed = SPEED_10;
4677 }
4bb04326
AT		 4678
4679 state->pause = 0;
4680 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
4681 state->pause |= MLO_PAUSE_RX;
4682 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
4683 state->pause |= MLO_PAUSE_TX;
4684}
4685
44cc27e4 4686static int mvpp2_phylink_mac_link_state(struct phylink_config *config,
4bb04326
AT		 4687 struct phylink_link_state *state)
4688{
44cc27e4
IC		 4689 struct mvpp2_port *port = container_of(config, struct mvpp2_port,
4690 phylink_config);
4bb04326
AT		 4691
4692 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
4693 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
4694 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4695
4696 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
4697 mvpp22_xlg_link_state(port, state);
4698 return 1;
4699 }
4700 }
4701
4702 mvpp2_gmac_link_state(port, state);
4703 return 1;
4704}
4705
44cc27e4 4706static void mvpp2_mac_an_restart(struct phylink_config *config)
4bb04326 4707{
44cc27e4
IC		 4708 struct mvpp2_port *port = container_of(config, struct mvpp2_port,
4709 phylink_config);
a4650477 4710 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4bb04326 4711
a4650477
RK		 4712 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
4713 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4714 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
4715 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4bb04326
AT		 4716}
4717
4718static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
4719 const struct phylink_link_state *state)
4720{
f17e70d2
AT		 4721 u32 old_ctrl0, ctrl0;
4722 u32 old_ctrl4, ctrl4;
4bb04326 4723
f17e70d2
AT		 4724 old_ctrl0 = ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG);
4725 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG);
4bb04326 4726
649e51d5
AT		 4727 ctrl0 |= MVPP22_XLG_CTRL0_MAC_RESET_DIS;
4728
4bb04326
AT		 4729 if (state->pause & MLO_PAUSE_TX)
4730 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
e240b7db
RK		 4731 else
4732 ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
4733
4bb04326
AT		 4734 if (state->pause & MLO_PAUSE_RX)
4735 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
e240b7db
RK		 4736 else
4737 ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
4bb04326 4738
bba18318
MC		 4739 ctrl4 &= ~(MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
4740 MVPP22_XLG_CTRL4_EN_IDLE_CHECK);
4741 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC;
4bb04326 4742
f17e70d2
AT		 4743 if (old_ctrl0 != ctrl0)
4744 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG);
4745 if (old_ctrl4 != ctrl4)
4746 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);
649e51d5
AT		 4747
4748 if (!(old_ctrl0 & MVPP22_XLG_CTRL0_MAC_RESET_DIS)) {
4749 while (!(readl(port->base + MVPP22_XLG_CTRL0_REG) &
4750 MVPP22_XLG_CTRL0_MAC_RESET_DIS))
4751 continue;
4752 }
4bb04326
AT		 4753}
4754
4755static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
4756 const struct phylink_link_state *state)
4757{
d14e078f
RK		 4758 u32 old_an, an;
4759 u32 old_ctrl0, ctrl0;
4760 u32 old_ctrl2, ctrl2;
4761 u32 old_ctrl4, ctrl4;
4bb04326 4762
d14e078f
RK		 4763 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4764 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4765 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4766 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4bb04326
AT		 4767
4768 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED |
4769 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
4770 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
d14e078f
RK		 4771 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN |
4772 MVPP2_GMAC_IN_BAND_AUTONEG | MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS);
4bb04326 4773 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
388ca27f
RK		 4774 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PORT_RESET_MASK |
4775 MVPP2_GMAC_PCS_ENABLE_MASK);
4776 ctrl4 &= ~(MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
4bb04326 4777
388ca27f 4778 /* Configure port type */
4a4cec72 4779 if (phy_interface_mode_is_8023z(state->interface)) {
388ca27f
RK		 4780 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK;
4781 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
4782 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4783 MVPP22_CTRL4_DP_CLK_SEL |
4784 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4785 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
4786 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK;
4787 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
4788 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4789 MVPP22_CTRL4_DP_CLK_SEL |
4790 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4791 } else if (phy_interface_mode_is_rgmii(state->interface)) {
4792 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
4793 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4794 MVPP22_CTRL4_SYNC_BYPASS_DIS |
4795 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
d97c9f4a 4796 }
4bb04326 4797
388ca27f 4798 /* Configure advertisement bits */
4bb04326
AT		 4799 if (phylink_test(state->advertising, Pause))
4800 an |= MVPP2_GMAC_FC_ADV_EN;
4801 if (phylink_test(state->advertising, Asym_Pause))
4802 an |= MVPP2_GMAC_FC_ADV_ASM_EN;
4803
388ca27f
RK		 4804 /* Configure negotiation style */
4805 if (!phylink_autoneg_inband(mode)) {
4806 /* Phy or fixed speed - no in-band AN */
4807 if (state->duplex)
4808 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4bb04326 4809
388ca27f
RK		 4810 if (state->speed == SPEED_1000 || state->speed == SPEED_2500)
4811 an |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4812 else if (state->speed == SPEED_100)
4813 an |= MVPP2_GMAC_CONFIG_MII_SPEED;
4bb04326
AT		 4814
4815 if (state->pause & MLO_PAUSE_TX)
4816 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4817 if (state->pause & MLO_PAUSE_RX)
4818 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
388ca27f
RK		 4819 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
4820 /* SGMII in-band mode receives the speed and duplex from
4821 * the PHY. Flow control information is not received. */
4822 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS);
4823 an |= MVPP2_GMAC_IN_BAND_AUTONEG |
4824 MVPP2_GMAC_AN_SPEED_EN |
4825 MVPP2_GMAC_AN_DUPLEX_EN;
4bb04326 4826
388ca27f
RK		 4827 if (state->pause & MLO_PAUSE_TX)
4828 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4829 if (state->pause & MLO_PAUSE_RX)
4830 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
4831 } else if (phy_interface_mode_is_8023z(state->interface)) {
4832 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
4833 * they negotiate duplex: they are always operating with a fixed
4834 * speed of 1000/2500Mbps in full duplex, so force 1000/2500
4835 * speed and full duplex here.
4836 */
4837 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
4838 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS);
d14e078f
RK		 4839 an |= MVPP2_GMAC_IN_BAND_AUTONEG |
4840 MVPP2_GMAC_CONFIG_GMII_SPEED |
388ca27f 4841 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4bb04326 4842
388ca27f
RK		 4843 if (state->pause & MLO_PAUSE_AN && state->an_enabled) {
4844 an |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
4845 } else {
4846 if (state->pause & MLO_PAUSE_TX)
4847 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4848 if (state->pause & MLO_PAUSE_RX)
4849 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
4850 }
4bb04326
AT		 4851 }
4852
9a490e34
AT		 4853/* Some fields of the auto-negotiation register require the port to be down when
4854 * their value is updated.
4855 */
4856#define MVPP2_GMAC_AN_PORT_DOWN_MASK \
4857 (MVPP2_GMAC_IN_BAND_AUTONEG | \
4858 MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | \
4859 MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | \
4860 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_CONFIG_FULL_DUPLEX | \
4861 MVPP2_GMAC_AN_DUPLEX_EN)
4862
d14e078f
RK		 4863 if ((old_ctrl0 ^ ctrl0) & MVPP2_GMAC_PORT_TYPE_MASK ||
4864 (old_ctrl2 ^ ctrl2) & MVPP2_GMAC_INBAND_AN_MASK ||
9a490e34 4865 (old_an ^ an) & MVPP2_GMAC_AN_PORT_DOWN_MASK) {
d14e078f
RK		 4866 /* Force link down */
4867 old_an &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4868 old_an |= MVPP2_GMAC_FORCE_LINK_DOWN;
4869 writel(old_an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4870
4871 /* Set the GMAC in a reset state - do this in a way that
4872 * ensures we clear it below.
4873 */
4874 old_ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK;
4875 writel(old_ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4876 }
4877
4878 if (old_ctrl0 != ctrl0)
4879 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
4880 if (old_ctrl2 != ctrl2)
4881 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4882 if (old_ctrl4 != ctrl4)
4883 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
4884 if (old_an != an)
4885 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
316734fd
RK		 4886
4887 if (old_ctrl2 & MVPP2_GMAC_PORT_RESET_MASK) {
4888 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
4889 MVPP2_GMAC_PORT_RESET_MASK)
4890 continue;
4891 }
4bb04326
AT		 4892}
4893
44cc27e4 4894static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
4bb04326
AT		 4895 const struct phylink_link_state *state)
4896{
44cc27e4 4897 struct net_device *dev = to_net_dev(config->dev);
4bb04326 4898 struct mvpp2_port *port = netdev_priv(dev);
bf2fa125 4899 bool change_interface = port->phy_interface != state->interface;
4bb04326
AT		 4900
4901 /* Check for invalid configuration */
1d9b041e 4902 if (mvpp2_is_xlg(state->interface) && port->gop_id != 0) {
4bb04326
AT		 4903 netdev_err(dev, "Invalid mode on %s\n", dev->name);
4904 return;
4905 }
4906
4bb04326
AT		 4907 /* Make sure the port is disabled when reconfiguring the mode */
4908 mvpp2_port_disable(port);
1970ee96 4909
d78a1809 4910 if (port->priv->hw_version == MVPP22 && change_interface) {
bf2fa125 4911 mvpp22_gop_mask_irq(port);
4bb04326 4912
d78a1809 4913 port->phy_interface = state->interface;
4bb04326 4914
d78a1809
AT		 4915 /* Reconfigure the serdes lanes */
4916 phy_power_off(port->comphy);
4917 mvpp22_mode_reconfigure(port);
4bb04326
AT		 4918 }
4919
4920 /* mac (re)configuration */
1d9b041e 4921 if (mvpp2_is_xlg(state->interface))
4bb04326
AT		 4922 mvpp2_xlg_config(port, mode, state);
4923 else if (phy_interface_mode_is_rgmii(state->interface) ||
4a4cec72
RK		 4924 phy_interface_mode_is_8023z(state->interface) ||
4925 state->interface == PHY_INTERFACE_MODE_SGMII)
4bb04326
AT		 4926 mvpp2_gmac_config(port, mode, state);
4927
4928 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
4929 mvpp2_port_loopback_set(port, state);
4930
d78a1809 4931 if (port->priv->hw_version == MVPP22 && change_interface)
bf2fa125
RK		 4932 mvpp22_gop_unmask_irq(port);
4933
41948ccb 4934 mvpp2_port_enable(port);
4bb04326
AT		 4935}
4936
44cc27e4 4937static void mvpp2_mac_link_up(struct phylink_config *config, unsigned int mode,
4bb04326
AT		 4938 phy_interface_t interface, struct phy_device *phy)
4939{
44cc27e4 4940 struct net_device *dev = to_net_dev(config->dev);
4bb04326
AT		 4941 struct mvpp2_port *port = netdev_priv(dev);
4942 u32 val;
4943
1970ee96
AT		 4944 if (!phylink_autoneg_inband(mode)) {
4945 if (mvpp2_is_xlg(interface)) {
4946 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4947 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
4948 val |= MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
4949 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
4950 } else {
4951 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4952 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
4953 val |= MVPP2_GMAC_FORCE_LINK_PASS;
4954 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4955 }
4bb04326
AT		 4956 }
4957
4958 mvpp2_port_enable(port);
4959
4960 mvpp2_egress_enable(port);
4961 mvpp2_ingress_enable(port);
4962 netif_tx_wake_all_queues(dev);
4963}
4964
44cc27e4
IC		 4965static void mvpp2_mac_link_down(struct phylink_config *config,
4966 unsigned int mode, phy_interface_t interface)
4bb04326 4967{
44cc27e4 4968 struct net_device *dev = to_net_dev(config->dev);
4bb04326
AT		 4969 struct mvpp2_port *port = netdev_priv(dev);
4970 u32 val;
4971
1970ee96
AT		 4972 if (!phylink_autoneg_inband(mode)) {
4973 if (mvpp2_is_xlg(interface)) {
4974 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4975 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
4976 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
4977 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
4978 } else {
4979 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4980 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4981 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
4982 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4983 }
4bb04326
AT		 4984 }
4985
4986 netif_tx_stop_all_queues(dev);
4987 mvpp2_egress_disable(port);
4988 mvpp2_ingress_disable(port);
4989
4bb04326
AT		 4990 mvpp2_port_disable(port);
4991}
4992
4993static const struct phylink_mac_ops mvpp2_phylink_ops = {
4994 .validate = mvpp2_phylink_validate,
4995 .mac_link_state = mvpp2_phylink_mac_link_state,
4996 .mac_an_restart = mvpp2_mac_an_restart,
4997 .mac_config = mvpp2_mac_config,
4998 .mac_link_up = mvpp2_mac_link_up,
4999 .mac_link_down = mvpp2_mac_link_down,
5000};
5001
3f518509
MW		 5002/* Ports initialization */
5003static int mvpp2_port_probe(struct platform_device *pdev,
24812221 5004 struct fwnode_handle *port_fwnode,
bf147153 5005 struct mvpp2 *priv)
3f518509 5006{
a75edc7c 5007 struct phy *comphy = NULL;
3f518509 5008 struct mvpp2_port *port;
edc660fa 5009 struct mvpp2_port_pcpu *port_pcpu;
24812221 5010 struct device_node *port_node = to_of_node(port_fwnode);
c9dbb6cf 5011 netdev_features_t features;
3f518509
MW		 5012 struct net_device *dev;
5013 struct resource *res;
4bb04326 5014 struct phylink *phylink;
3ba8c81e 5015 char *mac_from = "";
074c74df 5016 unsigned int ntxqs, nrxqs, thread;
a9aac385 5017 unsigned long flags = 0;
213f428f 5018 bool has_tx_irqs;
3f518509 5019 u32 id;
3f518509 5020 int phy_mode;
850623b3 5021 int err, i;
3f518509 5022
fd4a1056
AT		 5023 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
5024 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
5025 dev_err(&pdev->dev,
5026 "not enough IRQs to support multi queue mode\n");
5027 return -EINVAL;
a75edc7c 5028 }
213f428f 5029
09f83975 5030 ntxqs = MVPP2_MAX_TXQ;
3f136849
AT		 5031 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE) {
5032 nrxqs = 1;
5033 } else {
5034 /* According to the PPv2.2 datasheet and our experiments on
5035 * PPv2.1, RX queues have an allocation granularity of 4 (when
5036 * more than a single one on PPv2.2).
5037 * Round up to nearest multiple of 4.
5038 */
5039 nrxqs = (num_possible_cpus() + 3) & ~0x3;
5040 if (nrxqs > MVPP2_PORT_MAX_RXQ)
5041 nrxqs = MVPP2_PORT_MAX_RXQ;
5042 }
09f83975
TP		 5043
5044 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
3f518509
MW		 5045 if (!dev)
5046 return -ENOMEM;
5047
24812221 5048 phy_mode = fwnode_get_phy_mode(port_fwnode);
3f518509
MW		 5049 if (phy_mode < 0) {
5050 dev_err(&pdev->dev, "incorrect phy mode\n");
5051 err = phy_mode;
5052 goto err_free_netdev;
5053 }
5054
a75edc7c
MW		 5055 if (port_node) {
5056 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
5057 if (IS_ERR(comphy)) {
5058 if (PTR_ERR(comphy) == -EPROBE_DEFER) {
5059 err = -EPROBE_DEFER;
5060 goto err_free_netdev;
5061 }
5062 comphy = NULL;
542897d9 5063 }
542897d9
AT		 5064 }
5065
24812221 5066 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
3f518509
MW		 5067 err = -EINVAL;
5068 dev_err(&pdev->dev, "missing port-id value\n");
5069 goto err_free_netdev;
5070 }
5071
7cf87e4a 5072 dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
3f518509
MW		 5073 dev->watchdog_timeo = 5 * HZ;
5074 dev->netdev_ops = &mvpp2_netdev_ops;
5075 dev->ethtool_ops = &mvpp2_eth_tool_ops;
5076
5077 port = netdev_priv(dev);
591f4cfa 5078 port->dev = dev;
a75edc7c 5079 port->fwnode = port_fwnode;
4bb04326 5080 port->has_phy = !!of_find_property(port_node, "phy", NULL);
09f83975
TP		 5081 port->ntxqs = ntxqs;
5082 port->nrxqs = nrxqs;
213f428f
TP		 5083 port->priv = priv;
5084 port->has_tx_irqs = has_tx_irqs;
a9aac385 5085 port->flags = flags;
3f518509 5086
591f4cfa
TP		 5087 err = mvpp2_queue_vectors_init(port, port_node);
5088 if (err)
3f518509 5089 goto err_free_netdev;
3f518509 5090
a75edc7c
MW		 5091 if (port_node)
5092 port->link_irq = of_irq_get_byname(port_node, "link");
5093 else
5094 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
fd3651b2
AT		 5095 if (port->link_irq == -EPROBE_DEFER) {
5096 err = -EPROBE_DEFER;
5097 goto err_deinit_qvecs;
5098 }
5099 if (port->link_irq <= 0)
5100 /* the link irq is optional */
5101 port->link_irq = 0;
5102
24812221 5103 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
3f518509
MW		 5104 port->flags |= MVPP2_F_LOOPBACK;
5105
3f518509 5106 port->id = id;
59b9a31e 5107 if (priv->hw_version == MVPP21)
09f83975 5108 port->first_rxq = port->id * port->nrxqs;
59b9a31e
TP		 5109 else
5110 port->first_rxq = port->id * priv->max_port_rxqs;
5111
4bb04326 5112 port->of_node = port_node;
3f518509 5113 port->phy_interface = phy_mode;
542897d9 5114 port->comphy = comphy;
3f518509 5115
a786841d
TP		 5116 if (priv->hw_version == MVPP21) {
5117 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id);
5118 port->base = devm_ioremap_resource(&pdev->dev, res);
5119 if (IS_ERR(port->base)) {
5120 err = PTR_ERR(port->base);
fd3651b2 5121 goto err_free_irq;
a786841d 5122 }
118d6298
MR		 5123
5124 port->stats_base = port->priv->lms_base +
5125 MVPP21_MIB_COUNTERS_OFFSET +
5126 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
a786841d 5127 } else {
24812221
MW		 5128 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
5129 &port->gop_id)) {
a786841d
TP		 5130 err = -EINVAL;
5131 dev_err(&pdev->dev, "missing gop-port-id value\n");
591f4cfa 5132 goto err_deinit_qvecs;
a786841d
TP		 5133 }
5134
5135 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
118d6298
MR		 5136 port->stats_base = port->priv->iface_base +
5137 MVPP22_MIB_COUNTERS_OFFSET +
5138 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
3f518509
MW		 5139 }
5140
118d6298 5141 /* Alloc per-cpu and ethtool stats */
3f518509
MW		 5142 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
5143 if (!port->stats) {
5144 err = -ENOMEM;
fd3651b2 5145 goto err_free_irq;
3f518509
MW		 5146 }
5147
118d6298 5148 port->ethtool_stats = devm_kcalloc(&pdev->dev,
9bea6897 5149 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs),
118d6298
MR		 5150 sizeof(u64), GFP_KERNEL);
5151 if (!port->ethtool_stats) {
5152 err = -ENOMEM;
5153 goto err_free_stats;
5154 }
5155
e5c500eb
MR		 5156 mutex_init(&port->gather_stats_lock);
5157 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
5158
24812221 5159 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
3f518509 5160
7cf87e4a
YM		 5161 port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
5162 port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
3f518509
MW		 5163 SET_NETDEV_DEV(dev, &pdev->dev);
5164
5165 err = mvpp2_port_init(port);
5166 if (err < 0) {
5167 dev_err(&pdev->dev, "failed to init port %d\n", id);
5168 goto err_free_stats;
5169 }
26975821 5170
26975821
TP		 5171 mvpp2_port_periodic_xon_disable(port);
5172
649e51d5 5173 mvpp2_mac_reset_assert(port);
7409e66e 5174 mvpp22_pcs_reset_assert(port);
3f518509 5175
edc660fa
MW		 5176 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
5177 if (!port->pcpu) {
5178 err = -ENOMEM;
5179 goto err_free_txq_pcpu;
5180 }
5181
213f428f 5182 if (!port->has_tx_irqs) {
e531f767 5183 for (thread = 0; thread < priv->nthreads; thread++) {
074c74df 5184 port_pcpu = per_cpu_ptr(port->pcpu, thread);
edc660fa 5185
213f428f
TP		 5186 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
5187 HRTIMER_MODE_REL_PINNED);
5188 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
5189 port_pcpu->timer_scheduled = false;
edc660fa 5190
213f428f
TP		 5191 tasklet_init(&port_pcpu->tx_done_tasklet,
5192 mvpp2_tx_proc_cb,
5193 (unsigned long)dev);
5194 }
edc660fa
MW		 5195 }
5196
381c5671
AT		 5197 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5198 NETIF_F_TSO;
3f518509 5199 dev->features = features | NETIF_F_RXCSUM;
56beda3d
MC		 5200 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
5201 NETIF_F_HW_VLAN_CTAG_FILTER;
576193f2 5202
da86f59f 5203 if (mvpp22_rss_is_supported()) {
d33ec452 5204 dev->hw_features |= NETIF_F_RXHASH;
da86f59f
MC		 5205 dev->features |= NETIF_F_NTUPLE;
5206 }
d33ec452 5207
d66503c4 5208 mvpp2_set_hw_csum(port, port->pool_long->id);
576193f2 5209
3f518509 5210 dev->vlan_features |= features;
1d17db08 5211 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
10fea26c 5212 dev->priv_flags |= IFF_UNICAST_FLT;
3f518509 5213
576193f2 5214 /* MTU range: 68 - 9704 */
5777987e 5215 dev->min_mtu = ETH_MIN_MTU;
576193f2
SC		 5216 /* 9704 == 9728 - 20 and rounding to 8 */
5217 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
c4053ef3 5218 dev->dev.of_node = port_node;
5777987e 5219
4bb04326
AT		 5220 /* Phylink isn't used w/ ACPI as of now */
5221 if (port_node) {
44cc27e4
IC		 5222 port->phylink_config.dev = &dev->dev;
5223 port->phylink_config.type = PHYLINK_NETDEV;
5224
5225 phylink = phylink_create(&port->phylink_config, port_fwnode,
5226 phy_mode, &mvpp2_phylink_ops);
4bb04326
AT		 5227 if (IS_ERR(phylink)) {
5228 err = PTR_ERR(phylink);
5229 goto err_free_port_pcpu;
5230 }
5231 port->phylink = phylink;
5232 } else {
5233 port->phylink = NULL;
5234 }
5235
3f518509
MW		 5236 err = register_netdev(dev);
5237 if (err < 0) {
5238 dev_err(&pdev->dev, "failed to register netdev\n");
4bb04326 5239 goto err_phylink;
3f518509
MW		 5240 }
5241 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
5242
bf147153
MW		 5243 priv->port_list[priv->port_count++] = port;
5244
3f518509
MW		 5245 return 0;
5246
4bb04326
AT		 5247err_phylink:
5248 if (port->phylink)
5249 phylink_destroy(port->phylink);
edc660fa
MW		 5250err_free_port_pcpu:
5251 free_percpu(port->pcpu);
3f518509 5252err_free_txq_pcpu:
09f83975 5253 for (i = 0; i < port->ntxqs; i++)
3f518509
MW		 5254 free_percpu(port->txqs[i]->pcpu);
5255err_free_stats:
5256 free_percpu(port->stats);
fd3651b2
AT		 5257err_free_irq:
5258 if (port->link_irq)
5259 irq_dispose_mapping(port->link_irq);
591f4cfa
TP		 5260err_deinit_qvecs:
5261 mvpp2_queue_vectors_deinit(port);
3f518509
MW		 5262err_free_netdev:
5263 free_netdev(dev);
5264 return err;
5265}
5266
5267/* Ports removal routine */
5268static void mvpp2_port_remove(struct mvpp2_port *port)
5269{
5270 int i;
5271
5272 unregister_netdev(port->dev);
4bb04326
AT		 5273 if (port->phylink)
5274 phylink_destroy(port->phylink);
edc660fa 5275 free_percpu(port->pcpu);
3f518509 5276 free_percpu(port->stats);
09f83975 5277 for (i = 0; i < port->ntxqs; i++)
3f518509 5278 free_percpu(port->txqs[i]->pcpu);
591f4cfa 5279 mvpp2_queue_vectors_deinit(port);
fd3651b2
AT		 5280 if (port->link_irq)
5281 irq_dispose_mapping(port->link_irq);
3f518509
MW		 5282 free_netdev(port->dev);
5283}
5284
5285/* Initialize decoding windows */
5286static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
5287 struct mvpp2 *priv)
5288{
5289 u32 win_enable;
5290 int i;
5291
5292 for (i = 0; i < 6; i++) {
5293 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
5294 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
5295
5296 if (i < 4)
5297 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
5298 }
5299
5300 win_enable = 0;
5301
5302 for (i = 0; i < dram->num_cs; i++) {
5303 const struct mbus_dram_window *cs = dram->cs + i;
5304
5305 mvpp2_write(priv, MVPP2_WIN_BASE(i),
5306 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
5307 dram->mbus_dram_target_id);
5308
5309 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
5310 (cs->size - 1) & 0xffff0000);
5311
5312 win_enable |= (1 << i);
5313 }
5314
5315 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
5316}
5317
5318/* Initialize Rx FIFO's */
5319static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
5320{
5321 int port;
5322
5323 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
5324 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
2d1d7df8 5325 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
3f518509 5326 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
2d1d7df8
AT		 5327 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
5328 }
5329
5330 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
5331 MVPP2_RX_FIFO_PORT_MIN_PKT);
5332 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
5333}
5334
5335static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
5336{
5337 int port;
5338
5339 /* The FIFO size parameters are set depending on the maximum speed a
5340 * given port can handle:
5341 * - Port 0: 10Gbps
5342 * - Port 1: 2.5Gbps
5343 * - Ports 2 and 3: 1Gbps
5344 */
5345
5346 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
5347 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
5348 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
5349 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB);
5350
5351 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
5352 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
5353 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
5354 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB);
5355
5356 for (port = 2; port < MVPP2_MAX_PORTS; port++) {
5357 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
5358 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
5359 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
5360 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
3f518509
MW		 5361 }
5362
5363 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
5364 MVPP2_RX_FIFO_PORT_MIN_PKT);
5365 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
5366}
5367
93ff130f
YM		 5368/* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G
5369 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G,
5370 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB.
5371 */
7c10f974
AT		 5372static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
5373{
93ff130f 5374 int port, size, thrs;
7c10f974 5375
93ff130f
YM		 5376 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
5377 if (port == 0) {
5378 size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
5379 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB;
5380 } else {
5381 size = MVPP22_TX_FIFO_DATA_SIZE_3KB;
5382 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB;
5383 }
5384 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
5385 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);
5386 }
7c10f974
AT		 5387}
5388
6763ce31
TP		 5389static void mvpp2_axi_init(struct mvpp2 *priv)
5390{
5391 u32 val, rdval, wrval;
5392
5393 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
5394
5395 /* AXI Bridge Configuration */
5396
5397 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
5398 << MVPP22_AXI_ATTR_CACHE_OFFS;
5399 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5400 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5401
5402 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
5403 << MVPP22_AXI_ATTR_CACHE_OFFS;
5404 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5405 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5406
5407 /* BM */
5408 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
5409 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
5410
5411 /* Descriptors */
5412 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
5413 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
5414 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
5415 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
5416
5417 /* Buffer Data */
5418 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
5419 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
5420
5421 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
5422 << MVPP22_AXI_CODE_CACHE_OFFS;
5423 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
5424 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5425 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
5426 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
5427
5428 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
5429 << MVPP22_AXI_CODE_CACHE_OFFS;
5430 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5431 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5432
5433 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
5434
5435 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
5436 << MVPP22_AXI_CODE_CACHE_OFFS;
5437 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5438 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5439
5440 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
5441}
5442
3f518509
MW		 5443/* Initialize network controller common part HW */
5444static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
5445{
5446 const struct mbus_dram_target_info *dram_target_info;
5447 int err, i;
08a23755 5448 u32 val;
3f518509 5449
3f518509
MW		 5450 /* MBUS windows configuration */
5451 dram_target_info = mv_mbus_dram_info();
5452 if (dram_target_info)
5453 mvpp2_conf_mbus_windows(dram_target_info, priv);
5454
6763ce31
TP		 5455 if (priv->hw_version == MVPP22)
5456 mvpp2_axi_init(priv);
5457
08a23755 5458 /* Disable HW PHY polling */
26975821
TP		 5459 if (priv->hw_version == MVPP21) {
5460 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5461 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5462 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5463 } else {
5464 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5465 val &= ~MVPP22_SMI_POLLING_EN;
5466 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5467 }
08a23755 5468
3f518509 5469 /* Allocate and initialize aggregated TXQs */
074c74df 5470 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
d7ce3cec 5471 sizeof(*priv->aggr_txqs),
3f518509
MW		 5472 GFP_KERNEL);
5473 if (!priv->aggr_txqs)
5474 return -ENOMEM;
5475
074c74df 5476 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
3f518509
MW		 5477 priv->aggr_txqs[i].id = i;
5478 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
85affd7e 5479 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
3f518509
MW		 5480 if (err < 0)
5481 return err;
5482 }
5483
7c10f974
AT		 5484 /* Fifo Init */
5485 if (priv->hw_version == MVPP21) {
2d1d7df8 5486 mvpp2_rx_fifo_init(priv);
7c10f974 5487 } else {
2d1d7df8 5488 mvpp22_rx_fifo_init(priv);
7c10f974
AT		 5489 mvpp22_tx_fifo_init(priv);
5490 }
3f518509 5491
26975821
TP		 5492 if (priv->hw_version == MVPP21)
5493 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5494 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
3f518509
MW		 5495
5496 /* Allow cache snoop when transmiting packets */
5497 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5498
5499 /* Buffer Manager initialization */
5500 err = mvpp2_bm_init(pdev, priv);
5501 if (err < 0)
5502 return err;
5503
5504 /* Parser default initialization */
5505 err = mvpp2_prs_default_init(pdev, priv);
5506 if (err < 0)
5507 return err;
5508
5509 /* Classifier default initialization */
5510 mvpp2_cls_init(priv);
5511
5512 return 0;
5513}
5514
5515static int mvpp2_probe(struct platform_device *pdev)
5516{
a75edc7c 5517 const struct acpi_device_id *acpi_id;
24812221
MW		 5518 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5519 struct fwnode_handle *port_fwnode;
3f518509
MW		 5520 struct mvpp2 *priv;
5521 struct resource *res;
a786841d 5522 void __iomem *base;
e531f767 5523 int i, shared;
3f518509
MW		 5524 int err;
5525
0b92e594 5526 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
3f518509
MW		 5527 if (!priv)
5528 return -ENOMEM;
5529
a75edc7c
MW		 5530 if (has_acpi_companion(&pdev->dev)) {
5531 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
5532 &pdev->dev);
92ee77d1
KL		 5533 if (!acpi_id)
5534 return -EINVAL;
a75edc7c
MW		 5535 priv->hw_version = (unsigned long)acpi_id->driver_data;
5536 } else {
5537 priv->hw_version =
5538 (unsigned long)of_device_get_match_data(&pdev->dev);
5539 }
faca9247 5540
1e27a628
MC		 5541 /* multi queue mode isn't supported on PPV2.1, fallback to single
5542 * mode
5543 */
5544 if (priv->hw_version == MVPP21)
5545 queue_mode = MVPP2_QDIST_SINGLE_MODE;
5546
3f518509 5547 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a786841d
TP		 5548 base = devm_ioremap_resource(&pdev->dev, res);
5549 if (IS_ERR(base))
5550 return PTR_ERR(base);
5551
5552 if (priv->hw_version == MVPP21) {
5553 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5554 priv->lms_base = devm_ioremap_resource(&pdev->dev, res);
5555 if (IS_ERR(priv->lms_base))
5556 return PTR_ERR(priv->lms_base);
5557 } else {
5558 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
a75edc7c
MW		 5559 if (has_acpi_companion(&pdev->dev)) {
5560 /* In case the MDIO memory region is declared in
5561 * the ACPI, it can already appear as 'in-use'
5562 * in the OS. Because it is overlapped by second
5563 * region of the network controller, make
5564 * sure it is released, before requesting it again.
5565 * The care is taken by mvpp2 driver to avoid
5566 * concurrent access to this memory region.
5567 */
5568 release_resource(res);
5569 }
a786841d
TP		 5570 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
5571 if (IS_ERR(priv->iface_base))
5572 return PTR_ERR(priv->iface_base);
a75edc7c 5573 }
f84bf386 5574
a75edc7c 5575 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
f84bf386
AT		 5576 priv->sysctrl_base =
5577 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
5578 "marvell,system-controller");
5579 if (IS_ERR(priv->sysctrl_base))
5580 /* The system controller regmap is optional for dt
5581 * compatibility reasons. When not provided, the
5582 * configuration of the GoP relies on the
5583 * firmware/bootloader.
5584 */
5585 priv->sysctrl_base = NULL;
a786841d
TP		 5586 }
5587
01d04936
SC		 5588 mvpp2_setup_bm_pool();
5589
e531f767
AT		 5590
5591 priv->nthreads = min_t(unsigned int, num_present_cpus(),
5592 MVPP2_MAX_THREADS);
5593
5594 shared = num_present_cpus() - priv->nthreads;
5595 if (shared > 0)
5596 bitmap_fill(&priv->lock_map,
5597 min_t(int, shared, MVPP2_MAX_THREADS));
5598
df089aa0 5599 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
a786841d
TP		 5600 u32 addr_space_sz;
5601
5602 addr_space_sz = (priv->hw_version == MVPP21 ?
5603 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
df089aa0 5604 priv->swth_base[i] = base + i * addr_space_sz;
a786841d 5605 }
3f518509 5606
59b9a31e
TP		 5607 if (priv->hw_version == MVPP21)
5608 priv->max_port_rxqs = 8;
5609 else
5610 priv->max_port_rxqs = 32;
5611
a75edc7c
MW		 5612 if (dev_of_node(&pdev->dev)) {
5613 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
5614 if (IS_ERR(priv->pp_clk))
5615 return PTR_ERR(priv->pp_clk);
5616 err = clk_prepare_enable(priv->pp_clk);
5617 if (err < 0)
5618 return err;
3f518509 5619
a75edc7c
MW		 5620 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
5621 if (IS_ERR(priv->gop_clk)) {
5622 err = PTR_ERR(priv->gop_clk);
5623 goto err_pp_clk;
fceb55d4 5624 }
a75edc7c 5625 err = clk_prepare_enable(priv->gop_clk);
fceb55d4 5626 if (err < 0)
a75edc7c
MW		 5627 goto err_pp_clk;
5628
5629 if (priv->hw_version == MVPP22) {
5630 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
5631 if (IS_ERR(priv->mg_clk)) {
5632 err = PTR_ERR(priv->mg_clk);
5633 goto err_gop_clk;
5634 }
5635
5636 err = clk_prepare_enable(priv->mg_clk);
5637 if (err < 0)
5638 goto err_gop_clk;
9af771ce
MC		 5639
5640 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
5641 if (IS_ERR(priv->mg_core_clk)) {
5642 priv->mg_core_clk = NULL;
5643 } else {
5644 err = clk_prepare_enable(priv->mg_core_clk);
5645 if (err < 0)
5646 goto err_mg_clk;
5647 }
a75edc7c 5648 }
4792ea04
GC		 5649
5650 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
5651 if (IS_ERR(priv->axi_clk)) {
5652 err = PTR_ERR(priv->axi_clk);
5653 if (err == -EPROBE_DEFER)
9af771ce 5654 goto err_mg_core_clk;
4792ea04
GC		 5655 priv->axi_clk = NULL;
5656 } else {
5657 err = clk_prepare_enable(priv->axi_clk);
5658 if (err < 0)
9af771ce 5659 goto err_mg_core_clk;
4792ea04 5660 }
fceb55d4 5661
a75edc7c
MW		 5662 /* Get system's tclk rate */
5663 priv->tclk = clk_get_rate(priv->pp_clk);
5664 } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
5665 &priv->tclk)) {
5666 dev_err(&pdev->dev, "missing clock-frequency value\n");
5667 return -EINVAL;
5668 }
3f518509 5669
2067e0a1 5670 if (priv->hw_version == MVPP22) {
da42bb27 5671 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
2067e0a1 5672 if (err)
45f972ad 5673 goto err_axi_clk;
2067e0a1
TP		 5674 /* Sadly, the BM pools all share the same register to
5675 * store the high 32 bits of their address. So they
5676 * must all have the same high 32 bits, which forces
5677 * us to restrict coherent memory to DMA_BIT_MASK(32).
5678 */
5679 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5680 if (err)
45f972ad 5681 goto err_axi_clk;
2067e0a1
TP		 5682 }
5683
3f518509
MW		 5684 /* Initialize network controller */
5685 err = mvpp2_init(pdev, priv);
5686 if (err < 0) {
5687 dev_err(&pdev->dev, "failed to initialize controller\n");
45f972ad 5688 goto err_axi_clk;
3f518509
MW		 5689 }
5690
3f518509 5691 /* Initialize ports */
24812221
MW		 5692 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5693 err = mvpp2_port_probe(pdev, port_fwnode, priv);
3f518509 5694 if (err < 0)
26146b0e 5695 goto err_port_probe;
bf147153
MW		 5696 }
5697
5698 if (priv->port_count == 0) {
5699 dev_err(&pdev->dev, "no ports enabled\n");
5700 err = -ENODEV;
45f972ad 5701 goto err_axi_clk;
3f518509
MW		 5702 }
5703
118d6298
MR		 5704 /* Statistics must be gathered regularly because some of them (like
5705 * packets counters) are 32-bit registers and could overflow quite
5706 * quickly. For instance, a 10Gb link used at full bandwidth with the
5707 * smallest packets (64B) will overflow a 32-bit counter in less than
5708 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
5709 */
118d6298
MR		 5710 snprintf(priv->queue_name, sizeof(priv->queue_name),
5711 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
5712 priv->port_count > 1 ? "+" : "");
5713 priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
5714 if (!priv->stats_queue) {
5715 err = -ENOMEM;
26146b0e 5716 goto err_port_probe;
118d6298
MR		 5717 }
5718
21da57a2
MC		 5719 mvpp2_dbgfs_init(priv, pdev->name);
5720
3f518509
MW		 5721 platform_set_drvdata(pdev, priv);
5722 return 0;
5723
26146b0e
AT		 5724err_port_probe:
5725 i = 0;
24812221 5726 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
26146b0e
AT		 5727 if (priv->port_list[i])
5728 mvpp2_port_remove(priv->port_list[i]);
5729 i++;
5730 }
45f972ad 5731err_axi_clk:
4792ea04 5732 clk_disable_unprepare(priv->axi_clk);
9af771ce
MC		 5733
5734err_mg_core_clk:
5735 if (priv->hw_version == MVPP22)
5736 clk_disable_unprepare(priv->mg_core_clk);
45f972ad 5737err_mg_clk:
fceb55d4
TP		 5738 if (priv->hw_version == MVPP22)
5739 clk_disable_unprepare(priv->mg_clk);
3f518509
MW		 5740err_gop_clk:
5741 clk_disable_unprepare(priv->gop_clk);
5742err_pp_clk:
5743 clk_disable_unprepare(priv->pp_clk);
5744 return err;
5745}
5746
5747static int mvpp2_remove(struct platform_device *pdev)
5748{
5749 struct mvpp2 *priv = platform_get_drvdata(pdev);
24812221
MW		 5750 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5751 struct fwnode_handle *port_fwnode;
3f518509
MW		 5752 int i = 0;
5753
21da57a2
MC		 5754 mvpp2_dbgfs_cleanup(priv);
5755
24812221 5756 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
e5c500eb
MR		 5757 if (priv->port_list[i]) {
5758 mutex_destroy(&priv->port_list[i]->gather_stats_lock);
3f518509 5759 mvpp2_port_remove(priv->port_list[i]);
e5c500eb 5760 }
3f518509
MW		 5761 i++;
5762 }
5763
944a83a2
MC		 5764 destroy_workqueue(priv->stats_queue);
5765
3f518509
MW		 5766 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5767 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
5768
5769 mvpp2_bm_pool_destroy(pdev, priv, bm_pool);
5770 }
5771
074c74df 5772 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
3f518509
MW		 5773 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
5774
5775 dma_free_coherent(&pdev->dev,
5776 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
5777 aggr_txq->descs,
20396136 5778 aggr_txq->descs_dma);
3f518509
MW		 5779 }
5780
a75edc7c
MW		 5781 if (is_acpi_node(port_fwnode))
5782 return 0;
5783
4792ea04 5784 clk_disable_unprepare(priv->axi_clk);
9af771ce 5785 clk_disable_unprepare(priv->mg_core_clk);
fceb55d4 5786 clk_disable_unprepare(priv->mg_clk);
3f518509
MW		 5787 clk_disable_unprepare(priv->pp_clk);
5788 clk_disable_unprepare(priv->gop_clk);
5789
5790 return 0;
5791}
5792
5793static const struct of_device_id mvpp2_match[] = {
faca9247
TP		 5794 {
5795 .compatible = "marvell,armada-375-pp2",
5796 .data = (void *)MVPP21,
5797 },
fc5e1550
TP		 5798 {
5799 .compatible = "marvell,armada-7k-pp22",
5800 .data = (void *)MVPP22,
5801 },
3f518509
MW		 5802 { }
5803};
5804MODULE_DEVICE_TABLE(of, mvpp2_match);
5805
a75edc7c
MW		 5806static const struct acpi_device_id mvpp2_acpi_match[] = {
5807 { "MRVL0110", MVPP22 },
5808 { },
5809};
5810MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
5811
3f518509
MW		 5812static struct platform_driver mvpp2_driver = {
5813 .probe = mvpp2_probe,
5814 .remove = mvpp2_remove,
5815 .driver = {
5816 .name = MVPP2_DRIVER_NAME,
5817 .of_match_table = mvpp2_match,
a75edc7c 5818 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
3f518509
MW		 5819 },
5820};
5821
5822module_platform_driver(mvpp2_driver);
5823
5824MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
5825MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
c634099d 5826MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)