Commit | Line | Data |
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c5aff182 TP |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Rami Rosen <rosenr@marvell.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
0e03f563 JZ |
14 | #include <linux/clk.h> |
15 | #include <linux/cpu.h> | |
c5aff182 | 16 | #include <linux/etherdevice.h> |
0e03f563 | 17 | #include <linux/if_vlan.h> |
c5aff182 | 18 | #include <linux/inetdevice.h> |
c5aff182 | 19 | #include <linux/interrupt.h> |
c3f0dd38 | 20 | #include <linux/io.h> |
0e03f563 JZ |
21 | #include <linux/kernel.h> |
22 | #include <linux/mbus.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/netdevice.h> | |
c5aff182 | 25 | #include <linux/of.h> |
0e03f563 | 26 | #include <linux/of_address.h> |
c5aff182 TP |
27 | #include <linux/of_irq.h> |
28 | #include <linux/of_mdio.h> | |
29 | #include <linux/of_net.h> | |
a10c1c81 | 30 | #include <linux/phy/phy.h> |
c5aff182 | 31 | #include <linux/phy.h> |
503f9aa9 | 32 | #include <linux/phylink.h> |
0e03f563 JZ |
33 | #include <linux/platform_device.h> |
34 | #include <linux/skbuff.h> | |
baa11ebc | 35 | #include <net/hwbm.h> |
dc35a10f | 36 | #include "mvneta_bm.h" |
0e03f563 JZ |
37 | #include <net/ip.h> |
38 | #include <net/ipv6.h> | |
39 | #include <net/tso.h> | |
568a3fa2 | 40 | #include <net/page_pool.h> |
0db51da7 | 41 | #include <linux/bpf_trace.h> |
c5aff182 TP |
42 | |
43 | /* Registers */ | |
44 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
e5bdf689 | 45 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) |
dc35a10f MW |
46 | #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 |
47 | #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 | |
48 | #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 | |
49 | #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 | |
c5aff182 TP |
50 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) |
51 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
52 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
53 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
54 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
55 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
56 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
57 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
58 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
59 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
60 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
61 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
62 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
dc35a10f MW |
63 | #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) |
64 | #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 | |
65 | #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 | |
c5aff182 TP |
66 | #define MVNETA_PORT_RX_RESET 0x1cc0 |
67 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
68 | #define MVNETA_PHY_ADDR 0x2000 | |
69 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
70 | #define MVNETA_MBUS_RETRY 0x2010 | |
71 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
72 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
73 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
74 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
75 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
76 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
77 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 | |
db6ba9a5 | 78 | #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 |
c5aff182 TP |
79 | #define MVNETA_PORT_CONFIG 0x2400 |
80 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
81 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
82 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
83 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
84 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
85 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
86 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
87 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
88 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
89 | MVNETA_DEF_RXQ_ARP(q) | \ | |
90 | MVNETA_DEF_RXQ_TCP(q) | \ | |
91 | MVNETA_DEF_RXQ_UDP(q) | \ | |
92 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
93 | MVNETA_TX_UNSET_ERR_SUM | \ | |
94 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
95 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
96 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
97 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
98 | #define MVNETA_SDMA_CONFIG 0x241c | |
99 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
c5aff182 TP |
100 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
101 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
102 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
9ad8fef6 | 103 | #define MVNETA_DESC_SWAP BIT(6) |
c5aff182 TP |
104 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
105 | #define MVNETA_PORT_STATUS 0x2444 | |
106 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
107 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
108 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
3f1dd4bc | 109 | #define MVNETA_SERDES_CFG 0x24A0 |
5445eaf3 | 110 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 |
3f1dd4bc | 111 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 |
c5aff182 TP |
112 | #define MVNETA_TYPE_PRIO 0x24bc |
113 | #define MVNETA_FORCE_UNI BIT(21) | |
114 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
115 | #define MVNETA_TXQ_CMD 0x2448 | |
116 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
117 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
e483911f AL |
118 | #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 |
119 | #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 | |
898b2970 SS |
120 | #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 |
121 | #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) | |
c5aff182 | 122 | #define MVNETA_ACC_MODE 0x2500 |
dc35a10f | 123 | #define MVNETA_BM_ADDRESS 0x2504 |
c5aff182 TP |
124 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) |
125 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
126 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
2dcf75e2 | 127 | #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) |
50bf8cb6 | 128 | #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) |
c5aff182 | 129 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) |
40ba35e7 | 130 | |
2dcf75e2 GC |
131 | /* Exception Interrupt Port/Queue Cause register |
132 | * | |
133 | * Their behavior depend of the mapping done using the PCPX2Q | |
134 | * registers. For a given CPU if the bit associated to a queue is not | |
135 | * set, then for the register a read from this CPU will always return | |
136 | * 0 and a write won't do anything | |
137 | */ | |
40ba35e7 | 138 | |
c5aff182 | 139 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
c5aff182 | 140 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
40ba35e7 | 141 | |
142 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
143 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
144 | * bits 16..23 = RXQ FREE, one bit per queue. | |
145 | * bit 29 = OLD_REG_SUM, see old reg ? | |
146 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
147 | * bit 31 = MISC_SUM, one bit for 4 ports | |
148 | */ | |
149 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
150 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
151 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
152 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
898b2970 | 153 | #define MVNETA_MISCINTR_INTR_MASK BIT(31) |
40ba35e7 | 154 | |
c5aff182 TP |
155 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
156 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
40ba35e7 | 157 | |
158 | /* Data Path Port/Queue Cause Register */ | |
c5aff182 TP |
159 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
160 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
40ba35e7 | 161 | |
162 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) | |
163 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) | |
164 | #define MVNETA_CAUSE_PTP BIT(4) | |
165 | ||
166 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) | |
167 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) | |
168 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) | |
169 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) | |
170 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) | |
171 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) | |
172 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) | |
173 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) | |
174 | ||
175 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 | |
176 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) | |
177 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) | |
178 | ||
179 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 | |
180 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) | |
181 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) | |
182 | ||
c5aff182 TP |
183 | #define MVNETA_INTR_ENABLE 0x25b8 |
184 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 | |
dc1aadf6 | 185 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff |
40ba35e7 | 186 | |
c5aff182 TP |
187 | #define MVNETA_RXQ_CMD 0x2680 |
188 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
189 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
190 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
191 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
192 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
193 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
194 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
22f4bf8a | 195 | #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) |
c5aff182 TP |
196 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) |
197 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
898b2970 | 198 | #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) |
a79121d3 | 199 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
c5aff182 TP |
200 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
201 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
202 | #define MVNETA_GMAC_STATUS 0x2c10 | |
203 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
204 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
205 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
206 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
207 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
208 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
209 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
210 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
503f9aa9 RK |
211 | #define MVNETA_GMAC_AN_COMPLETE BIT(11) |
212 | #define MVNETA_GMAC_SYNC_OK BIT(14) | |
c5aff182 TP |
213 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c |
214 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
215 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
898b2970 | 216 | #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) |
22f4bf8a RK |
217 | #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) |
218 | #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) | |
c5aff182 TP |
219 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) |
220 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
71408602 | 221 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
22f4bf8a RK |
222 | #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) |
223 | #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) | |
898b2970 | 224 | #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) |
c5aff182 | 225 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
71408602 | 226 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
da58a931 MC |
227 | #define MVNETA_GMAC_CTRL_4 0x2c90 |
228 | #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) | |
e483911f | 229 | #define MVNETA_MIB_COUNTERS_BASE 0x3000 |
c5aff182 TP |
230 | #define MVNETA_MIB_LATE_COLLISION 0x7c |
231 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
232 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
233 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
234 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
235 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
236 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
237 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
238 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
239 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
2a90f7e1 | 240 | #define MVNETA_TXQ_DEC_SENT_MASK 0xff |
c5aff182 TP |
241 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) |
242 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
243 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
244 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
245 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
246 | #define MVNETA_TX_MTU 0x3e0c | |
247 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
248 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
249 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
250 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
251 | ||
6d81f451 RK |
252 | #define MVNETA_LPI_CTRL_0 0x2cc0 |
253 | #define MVNETA_LPI_CTRL_1 0x2cc4 | |
254 | #define MVNETA_LPI_REQUEST_ENABLE BIT(0) | |
255 | #define MVNETA_LPI_CTRL_2 0x2cc8 | |
256 | #define MVNETA_LPI_STATUS 0x2ccc | |
257 | ||
c5aff182 TP |
258 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff |
259 | ||
260 | /* Descriptor ring Macros */ | |
261 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
262 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
263 | ||
264 | /* Various constants */ | |
265 | ||
266 | /* Coalescing */ | |
06708f81 | 267 | #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ |
c5aff182 TP |
268 | #define MVNETA_RX_COAL_PKTS 32 |
269 | #define MVNETA_RX_COAL_USEC 100 | |
270 | ||
6a20c175 | 271 | /* The two bytes Marvell header. Either contains a special value used |
c5aff182 TP |
272 | * by Marvell switches when a specific hardware mode is enabled (not |
273 | * supported by this driver) or is filled automatically by zeroes on | |
274 | * the RX side. Those two bytes being at the front of the Ethernet | |
275 | * header, they allow to have the IP header aligned on a 4 bytes | |
276 | * boundary automatically: the hardware skips those two bytes on its | |
277 | * own. | |
278 | */ | |
279 | #define MVNETA_MH_SIZE 2 | |
280 | ||
281 | #define MVNETA_VLAN_TAG_LEN 4 | |
282 | ||
9110ee07 | 283 | #define MVNETA_TX_CSUM_DEF_SIZE 1600 |
c5aff182 | 284 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 |
dc35a10f MW |
285 | #define MVNETA_ACC_MODE_EXT1 1 |
286 | #define MVNETA_ACC_MODE_EXT2 2 | |
287 | ||
288 | #define MVNETA_MAX_DECODE_WIN 6 | |
c5aff182 TP |
289 | |
290 | /* Timeout constants */ | |
291 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
292 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
293 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
294 | ||
295 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
296 | ||
9a401dea GC |
297 | /* The RSS lookup table actually has 256 entries but we do not use |
298 | * them yet | |
299 | */ | |
300 | #define MVNETA_RSS_LU_TABLE_SIZE 1 | |
301 | ||
c5aff182 | 302 | /* Max number of Rx descriptors */ |
c307e2a8 | 303 | #define MVNETA_MAX_RXD 512 |
c5aff182 TP |
304 | |
305 | /* Max number of Tx descriptors */ | |
c307e2a8 | 306 | #define MVNETA_MAX_TXD 1024 |
c5aff182 | 307 | |
8eef5f97 EG |
308 | /* Max number of allowed TCP segments for software TSO */ |
309 | #define MVNETA_MAX_TSO_SEGS 100 | |
310 | ||
311 | #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
312 | ||
c5aff182 TP |
313 | /* descriptor aligned size */ |
314 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
315 | ||
8d5047cf MW |
316 | /* Number of bytes to be taken into account by HW when putting incoming data |
317 | * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet | |
318 | * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. | |
319 | */ | |
320 | #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 | |
321 | ||
c5aff182 TP |
322 | #define MVNETA_RX_PKT_SIZE(mtu) \ |
323 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ | |
324 | ETH_HLEN + ETH_FCS_LEN, \ | |
c66e98c9 | 325 | cache_line_size()) |
c5aff182 | 326 | |
44efc78d | 327 | #define MVNETA_SKB_HEADROOM max(XDP_PACKET_HEADROOM, NET_SKB_PAD) |
8dc9a088 | 328 | #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ |
0db51da7 | 329 | MVNETA_SKB_HEADROOM)) |
8dc9a088 LB |
330 | #define MVNETA_SKB_SIZE(len) (SKB_DATA_ALIGN(len) + MVNETA_SKB_PAD) |
331 | #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) | |
332 | ||
2e3173a3 EG |
333 | #define IS_TSO_HEADER(txq, addr) \ |
334 | ((addr >= txq->tso_hdrs_phys) && \ | |
335 | (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) | |
336 | ||
dc35a10f MW |
337 | #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ |
338 | (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) | |
c5aff182 | 339 | |
6d81f451 RK |
340 | enum { |
341 | ETHTOOL_STAT_EEE_WAKEUP, | |
17a96da6 GC |
342 | ETHTOOL_STAT_SKB_ALLOC_ERR, |
343 | ETHTOOL_STAT_REFILL_ERR, | |
6d81f451 RK |
344 | ETHTOOL_MAX_STATS, |
345 | }; | |
346 | ||
9b0cdefa RK |
347 | struct mvneta_statistic { |
348 | unsigned short offset; | |
349 | unsigned short type; | |
350 | const char name[ETH_GSTRING_LEN]; | |
351 | }; | |
352 | ||
353 | #define T_REG_32 32 | |
354 | #define T_REG_64 64 | |
6d81f451 | 355 | #define T_SW 1 |
9b0cdefa | 356 | |
0db51da7 LB |
357 | #define MVNETA_XDP_PASS BIT(0) |
358 | #define MVNETA_XDP_DROPPED BIT(1) | |
359 | #define MVNETA_XDP_TX BIT(2) | |
360 | #define MVNETA_XDP_REDIR BIT(3) | |
361 | ||
9b0cdefa RK |
362 | static const struct mvneta_statistic mvneta_statistics[] = { |
363 | { 0x3000, T_REG_64, "good_octets_received", }, | |
364 | { 0x3010, T_REG_32, "good_frames_received", }, | |
365 | { 0x3008, T_REG_32, "bad_octets_received", }, | |
366 | { 0x3014, T_REG_32, "bad_frames_received", }, | |
367 | { 0x3018, T_REG_32, "broadcast_frames_received", }, | |
368 | { 0x301c, T_REG_32, "multicast_frames_received", }, | |
369 | { 0x3050, T_REG_32, "unrec_mac_control_received", }, | |
370 | { 0x3058, T_REG_32, "good_fc_received", }, | |
371 | { 0x305c, T_REG_32, "bad_fc_received", }, | |
372 | { 0x3060, T_REG_32, "undersize_received", }, | |
373 | { 0x3064, T_REG_32, "fragments_received", }, | |
374 | { 0x3068, T_REG_32, "oversize_received", }, | |
375 | { 0x306c, T_REG_32, "jabber_received", }, | |
376 | { 0x3070, T_REG_32, "mac_receive_error", }, | |
377 | { 0x3074, T_REG_32, "bad_crc_event", }, | |
378 | { 0x3078, T_REG_32, "collision", }, | |
379 | { 0x307c, T_REG_32, "late_collision", }, | |
380 | { 0x2484, T_REG_32, "rx_discard", }, | |
381 | { 0x2488, T_REG_32, "rx_overrun", }, | |
382 | { 0x3020, T_REG_32, "frames_64_octets", }, | |
383 | { 0x3024, T_REG_32, "frames_65_to_127_octets", }, | |
384 | { 0x3028, T_REG_32, "frames_128_to_255_octets", }, | |
385 | { 0x302c, T_REG_32, "frames_256_to_511_octets", }, | |
386 | { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, | |
387 | { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, | |
388 | { 0x3038, T_REG_64, "good_octets_sent", }, | |
389 | { 0x3040, T_REG_32, "good_frames_sent", }, | |
390 | { 0x3044, T_REG_32, "excessive_collision", }, | |
391 | { 0x3048, T_REG_32, "multicast_frames_sent", }, | |
392 | { 0x304c, T_REG_32, "broadcast_frames_sent", }, | |
393 | { 0x3054, T_REG_32, "fc_sent", }, | |
394 | { 0x300c, T_REG_32, "internal_mac_transmit_err", }, | |
6d81f451 | 395 | { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, |
17a96da6 GC |
396 | { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, |
397 | { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, | |
9b0cdefa RK |
398 | }; |
399 | ||
74c41b04 | 400 | struct mvneta_pcpu_stats { |
c5aff182 | 401 | struct u64_stats_sync syncp; |
74c41b04 | 402 | u64 rx_packets; |
403 | u64 rx_bytes; | |
c35947b8 LB |
404 | u64 rx_dropped; |
405 | u64 rx_errors; | |
74c41b04 | 406 | u64 tx_packets; |
407 | u64 tx_bytes; | |
c5aff182 TP |
408 | }; |
409 | ||
12bb03b4 MR |
410 | struct mvneta_pcpu_port { |
411 | /* Pointer to the shared port */ | |
412 | struct mvneta_port *pp; | |
413 | ||
414 | /* Pointer to the CPU-local NAPI struct */ | |
415 | struct napi_struct napi; | |
416 | ||
417 | /* Cause of the previous interrupt */ | |
418 | u32 cause_rx_tx; | |
419 | }; | |
420 | ||
c5aff182 | 421 | struct mvneta_port { |
dc35a10f | 422 | u8 id; |
12bb03b4 MR |
423 | struct mvneta_pcpu_port __percpu *ports; |
424 | struct mvneta_pcpu_stats __percpu *stats; | |
425 | ||
c5aff182 TP |
426 | int pkt_size; |
427 | void __iomem *base; | |
428 | struct mvneta_rx_queue *rxqs; | |
429 | struct mvneta_tx_queue *txqs; | |
c5aff182 | 430 | struct net_device *dev; |
84a3f4db SAS |
431 | struct hlist_node node_online; |
432 | struct hlist_node node_dead; | |
90b74c01 | 433 | int rxq_def; |
5888511e GC |
434 | /* Protect the access to the percpu interrupt registers, |
435 | * ensuring that the configuration remains coherent. | |
436 | */ | |
437 | spinlock_t lock; | |
120cfa50 | 438 | bool is_stopped; |
c5aff182 | 439 | |
2636ac3c MW |
440 | u32 cause_rx_tx; |
441 | struct napi_struct napi; | |
442 | ||
0db51da7 LB |
443 | struct bpf_prog *xdp_prog; |
444 | ||
c5aff182 | 445 | /* Core clock */ |
189dd626 | 446 | struct clk *clk; |
15cc4a4a JZ |
447 | /* AXI clock */ |
448 | struct clk *clk_bus; | |
c5aff182 TP |
449 | u8 mcast_count[256]; |
450 | u16 tx_ring_size; | |
451 | u16 rx_ring_size; | |
c5aff182 | 452 | |
c5aff182 | 453 | phy_interface_t phy_interface; |
503f9aa9 | 454 | struct device_node *dn; |
b65657fc | 455 | unsigned int tx_csum_limit; |
503f9aa9 | 456 | struct phylink *phylink; |
44cc27e4 | 457 | struct phylink_config phylink_config; |
a10c1c81 | 458 | struct phy *comphy; |
9b0cdefa | 459 | |
dc35a10f MW |
460 | struct mvneta_bm *bm_priv; |
461 | struct mvneta_bm_pool *pool_long; | |
462 | struct mvneta_bm_pool *pool_short; | |
463 | int bm_win_id; | |
464 | ||
6d81f451 RK |
465 | bool eee_enabled; |
466 | bool eee_active; | |
467 | bool tx_lpi_enabled; | |
468 | ||
9b0cdefa | 469 | u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; |
9a401dea GC |
470 | |
471 | u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; | |
2636ac3c MW |
472 | |
473 | /* Flags for special SoC configurations */ | |
474 | bool neta_armada3700; | |
8d5047cf | 475 | u16 rx_offset_correction; |
9768b45c | 476 | const struct mbus_dram_target_info *dram_target_info; |
c5aff182 TP |
477 | }; |
478 | ||
6a20c175 | 479 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
c5aff182 TP |
480 | * layout of the transmit and reception DMA descriptors, and their |
481 | * layout is therefore defined by the hardware design | |
482 | */ | |
6083ed44 | 483 | |
c5aff182 TP |
484 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
485 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
486 | #define MVNETA_TX_L4_UDP BIT(16) | |
487 | #define MVNETA_TX_L3_IP6 BIT(17) | |
488 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
489 | #define MVNETA_TXD_Z_PAD BIT(19) | |
490 | #define MVNETA_TXD_L_DESC BIT(20) | |
491 | #define MVNETA_TXD_F_DESC BIT(21) | |
492 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
493 | MVNETA_TXD_L_DESC | \ | |
494 | MVNETA_TXD_F_DESC) | |
495 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
496 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
497 | ||
c5aff182 | 498 | #define MVNETA_RXD_ERR_CRC 0x0 |
dc35a10f MW |
499 | #define MVNETA_RXD_BM_POOL_SHIFT 13 |
500 | #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) | |
c5aff182 TP |
501 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) |
502 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
503 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
504 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
505 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
506 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
562e2f46 YK |
507 | #define MVNETA_RXD_LAST_DESC BIT(26) |
508 | #define MVNETA_RXD_FIRST_DESC BIT(27) | |
509 | #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ | |
510 | MVNETA_RXD_LAST_DESC) | |
c5aff182 TP |
511 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) |
512 | ||
9ad8fef6 | 513 | #if defined(__LITTLE_ENDIAN) |
6083ed44 TP |
514 | struct mvneta_tx_desc { |
515 | u32 command; /* Options used by HW for packet transmitting.*/ | |
fbd1d524 | 516 | u16 reserved1; /* csum_l4 (for future use) */ |
6083ed44 TP |
517 | u16 data_size; /* Data size of transmitted packet in bytes */ |
518 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
519 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
520 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
521 | }; | |
522 | ||
523 | struct mvneta_rx_desc { | |
524 | u32 status; /* Info about received packet */ | |
c5aff182 TP |
525 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
526 | u16 data_size; /* Size of received packet in bytes */ | |
6083ed44 | 527 | |
c5aff182 TP |
528 | u32 buf_phys_addr; /* Physical address of the buffer */ |
529 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
6083ed44 | 530 | |
c5aff182 TP |
531 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
532 | u16 reserved3; /* prefetch_cmd, for future use */ | |
533 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
6083ed44 | 534 | |
c5aff182 TP |
535 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
536 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
537 | }; | |
9ad8fef6 TP |
538 | #else |
539 | struct mvneta_tx_desc { | |
540 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
fbd1d524 | 541 | u16 reserved1; /* csum_l4 (for future use) */ |
9ad8fef6 TP |
542 | u32 command; /* Options used by HW for packet transmitting.*/ |
543 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
544 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
545 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
546 | }; | |
547 | ||
548 | struct mvneta_rx_desc { | |
549 | u16 data_size; /* Size of received packet in bytes */ | |
550 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
551 | u32 status; /* Info about received packet */ | |
552 | ||
553 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
554 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
555 | ||
556 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
557 | u16 reserved3; /* prefetch_cmd, for future use */ | |
558 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
559 | ||
560 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
561 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
562 | }; | |
563 | #endif | |
c5aff182 | 564 | |
9e58c8b4 LB |
565 | enum mvneta_tx_buf_type { |
566 | MVNETA_TYPE_SKB, | |
567 | MVNETA_TYPE_XDP_TX, | |
568 | MVNETA_TYPE_XDP_NDO, | |
569 | }; | |
570 | ||
571 | struct mvneta_tx_buf { | |
572 | enum mvneta_tx_buf_type type; | |
573 | union { | |
574 | struct xdp_frame *xdpf; | |
575 | struct sk_buff *skb; | |
576 | }; | |
577 | }; | |
578 | ||
c5aff182 TP |
579 | struct mvneta_tx_queue { |
580 | /* Number of this TX queue, in the range 0-7 */ | |
581 | u8 id; | |
582 | ||
583 | /* Number of TX DMA descriptors in the descriptor ring */ | |
584 | int size; | |
585 | ||
586 | /* Number of currently used TX DMA descriptor in the | |
6a20c175 TP |
587 | * descriptor ring |
588 | */ | |
c5aff182 | 589 | int count; |
2a90f7e1 | 590 | int pending; |
8eef5f97 EG |
591 | int tx_stop_threshold; |
592 | int tx_wake_threshold; | |
c5aff182 | 593 | |
9e58c8b4 LB |
594 | /* Array of transmitted buffers */ |
595 | struct mvneta_tx_buf *buf; | |
c5aff182 TP |
596 | |
597 | /* Index of last TX DMA descriptor that was inserted */ | |
598 | int txq_put_index; | |
599 | ||
600 | /* Index of the TX DMA descriptor to be cleaned up */ | |
601 | int txq_get_index; | |
602 | ||
603 | u32 done_pkts_coal; | |
604 | ||
605 | /* Virtual address of the TX DMA descriptors array */ | |
606 | struct mvneta_tx_desc *descs; | |
607 | ||
608 | /* DMA address of the TX DMA descriptors array */ | |
609 | dma_addr_t descs_phys; | |
610 | ||
611 | /* Index of the last TX DMA descriptor */ | |
612 | int last_desc; | |
613 | ||
614 | /* Index of the next TX DMA descriptor to process */ | |
615 | int next_desc_to_proc; | |
2adb719d EG |
616 | |
617 | /* DMA buffers for TSO headers */ | |
618 | char *tso_hdrs; | |
619 | ||
620 | /* DMA address of TSO headers */ | |
621 | dma_addr_t tso_hdrs_phys; | |
50bf8cb6 GC |
622 | |
623 | /* Affinity mask for CPUs*/ | |
624 | cpumask_t affinity_mask; | |
c5aff182 TP |
625 | }; |
626 | ||
627 | struct mvneta_rx_queue { | |
628 | /* rx queue number, in the range 0-7 */ | |
629 | u8 id; | |
630 | ||
631 | /* num of rx descriptors in the rx descriptor ring */ | |
632 | int size; | |
633 | ||
c5aff182 TP |
634 | u32 pkts_coal; |
635 | u32 time_coal; | |
636 | ||
568a3fa2 LB |
637 | /* page_pool */ |
638 | struct page_pool *page_pool; | |
639 | struct xdp_rxq_info xdp_rxq; | |
640 | ||
f88bee1c GC |
641 | /* Virtual address of the RX buffer */ |
642 | void **buf_virt_addr; | |
643 | ||
c5aff182 TP |
644 | /* Virtual address of the RX DMA descriptors array */ |
645 | struct mvneta_rx_desc *descs; | |
646 | ||
647 | /* DMA address of the RX DMA descriptors array */ | |
648 | dma_addr_t descs_phys; | |
649 | ||
650 | /* Index of the last RX DMA descriptor */ | |
651 | int last_desc; | |
652 | ||
653 | /* Index of the next RX DMA descriptor to process */ | |
654 | int next_desc_to_proc; | |
17a96da6 | 655 | |
562e2f46 YK |
656 | /* Index of first RX DMA descriptor to refill */ |
657 | int first_to_refill; | |
658 | u32 refill_num; | |
659 | ||
660 | /* pointer to uncomplete skb buffer */ | |
661 | struct sk_buff *skb; | |
662 | int left_size; | |
663 | ||
17a96da6 GC |
664 | /* error counters */ |
665 | u32 skb_alloc_err; | |
666 | u32 refill_err; | |
c5aff182 TP |
667 | }; |
668 | ||
84a3f4db | 669 | static enum cpuhp_state online_hpstate; |
edadb7fa EG |
670 | /* The hardware supports eight (8) rx queues, but we are only allowing |
671 | * the first one to be used. Therefore, let's just allocate one queue. | |
672 | */ | |
d8936657 | 673 | static int rxq_number = 8; |
c5aff182 TP |
674 | static int txq_number = 8; |
675 | ||
676 | static int rxq_def; | |
c5aff182 | 677 | |
f19fadfc | 678 | static int rx_copybreak __read_mostly = 256; |
679 | ||
dc35a10f MW |
680 | /* HW BM need that each port be identify by a unique ID */ |
681 | static int global_port_id; | |
682 | ||
c5aff182 TP |
683 | #define MVNETA_DRIVER_NAME "mvneta" |
684 | #define MVNETA_DRIVER_VERSION "1.0" | |
685 | ||
686 | /* Utility/helper methods */ | |
687 | ||
688 | /* Write helper method */ | |
689 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
690 | { | |
691 | writel(data, pp->base + offset); | |
692 | } | |
693 | ||
694 | /* Read helper method */ | |
695 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
696 | { | |
697 | return readl(pp->base + offset); | |
698 | } | |
699 | ||
700 | /* Increment txq get counter */ | |
701 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) | |
702 | { | |
703 | txq->txq_get_index++; | |
704 | if (txq->txq_get_index == txq->size) | |
705 | txq->txq_get_index = 0; | |
706 | } | |
707 | ||
708 | /* Increment txq put counter */ | |
709 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) | |
710 | { | |
711 | txq->txq_put_index++; | |
712 | if (txq->txq_put_index == txq->size) | |
713 | txq->txq_put_index = 0; | |
714 | } | |
715 | ||
716 | ||
717 | /* Clear all MIB counters */ | |
718 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
719 | { | |
720 | int i; | |
721 | u32 dummy; | |
722 | ||
723 | /* Perform dummy reads from MIB counters */ | |
724 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
725 | dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); | |
e483911f AL |
726 | dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); |
727 | dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); | |
c5aff182 TP |
728 | } |
729 | ||
730 | /* Get System Network Statistics */ | |
bc1f4470 | 731 | static void |
2dc0d2b4 BX |
732 | mvneta_get_stats64(struct net_device *dev, |
733 | struct rtnl_link_stats64 *stats) | |
c5aff182 TP |
734 | { |
735 | struct mvneta_port *pp = netdev_priv(dev); | |
736 | unsigned int start; | |
74c41b04 | 737 | int cpu; |
c5aff182 | 738 | |
74c41b04 | 739 | for_each_possible_cpu(cpu) { |
740 | struct mvneta_pcpu_stats *cpu_stats; | |
741 | u64 rx_packets; | |
742 | u64 rx_bytes; | |
c35947b8 LB |
743 | u64 rx_dropped; |
744 | u64 rx_errors; | |
74c41b04 | 745 | u64 tx_packets; |
746 | u64 tx_bytes; | |
c5aff182 | 747 | |
74c41b04 | 748 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
749 | do { | |
57a7744e | 750 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); |
74c41b04 | 751 | rx_packets = cpu_stats->rx_packets; |
752 | rx_bytes = cpu_stats->rx_bytes; | |
c35947b8 LB |
753 | rx_dropped = cpu_stats->rx_dropped; |
754 | rx_errors = cpu_stats->rx_errors; | |
74c41b04 | 755 | tx_packets = cpu_stats->tx_packets; |
756 | tx_bytes = cpu_stats->tx_bytes; | |
57a7744e | 757 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); |
c5aff182 | 758 | |
74c41b04 | 759 | stats->rx_packets += rx_packets; |
760 | stats->rx_bytes += rx_bytes; | |
c35947b8 LB |
761 | stats->rx_dropped += rx_dropped; |
762 | stats->rx_errors += rx_errors; | |
74c41b04 | 763 | stats->tx_packets += tx_packets; |
764 | stats->tx_bytes += tx_bytes; | |
765 | } | |
c5aff182 | 766 | |
c5aff182 | 767 | stats->tx_dropped = dev->stats.tx_dropped; |
c5aff182 TP |
768 | } |
769 | ||
770 | /* Rx descriptors helper methods */ | |
771 | ||
5428213c | 772 | /* Checks whether the RX descriptor having this status is both the first |
773 | * and the last descriptor for the RX packet. Each RX packet is currently | |
c5aff182 TP |
774 | * received through a single RX descriptor, so not having each RX |
775 | * descriptor with its first and last bits set is an error | |
776 | */ | |
5428213c | 777 | static int mvneta_rxq_desc_is_first_last(u32 status) |
c5aff182 | 778 | { |
5428213c | 779 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == |
c5aff182 TP |
780 | MVNETA_RXD_FIRST_LAST_DESC; |
781 | } | |
782 | ||
783 | /* Add number of descriptors ready to receive new packets */ | |
784 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
785 | struct mvneta_rx_queue *rxq, | |
786 | int ndescs) | |
787 | { | |
788 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
6a20c175 TP |
789 | * be added at once |
790 | */ | |
c5aff182 TP |
791 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
792 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
793 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
794 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
795 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
796 | } | |
797 | ||
798 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
799 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
800 | } | |
801 | ||
802 | /* Get number of RX descriptors occupied by received packets */ | |
803 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
804 | struct mvneta_rx_queue *rxq) | |
805 | { | |
806 | u32 val; | |
807 | ||
808 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
809 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
810 | } | |
811 | ||
6a20c175 | 812 | /* Update num of rx desc called upon return from rx path or |
c5aff182 TP |
813 | * from mvneta_rxq_drop_pkts(). |
814 | */ | |
815 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
816 | struct mvneta_rx_queue *rxq, | |
817 | int rx_done, int rx_filled) | |
818 | { | |
819 | u32 val; | |
820 | ||
821 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
822 | val = rx_done | | |
823 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
824 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
825 | return; | |
826 | } | |
827 | ||
828 | /* Only 255 descriptors can be added at once */ | |
829 | while ((rx_done > 0) || (rx_filled > 0)) { | |
830 | if (rx_done <= 0xff) { | |
831 | val = rx_done; | |
832 | rx_done = 0; | |
833 | } else { | |
834 | val = 0xff; | |
835 | rx_done -= 0xff; | |
836 | } | |
837 | if (rx_filled <= 0xff) { | |
838 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
839 | rx_filled = 0; | |
840 | } else { | |
841 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
842 | rx_filled -= 0xff; | |
843 | } | |
844 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
845 | } | |
846 | } | |
847 | ||
848 | /* Get pointer to next RX descriptor to be processed by SW */ | |
849 | static struct mvneta_rx_desc * | |
850 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
851 | { | |
852 | int rx_desc = rxq->next_desc_to_proc; | |
853 | ||
854 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
34e4179d | 855 | prefetch(rxq->descs + rxq->next_desc_to_proc); |
c5aff182 TP |
856 | return rxq->descs + rx_desc; |
857 | } | |
858 | ||
859 | /* Change maximum receive size of the port. */ | |
860 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) | |
861 | { | |
862 | u32 val; | |
863 | ||
864 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
865 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; | |
866 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << | |
867 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; | |
868 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
869 | } | |
870 | ||
871 | ||
872 | /* Set rx queue offset */ | |
873 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, | |
874 | struct mvneta_rx_queue *rxq, | |
875 | int offset) | |
876 | { | |
877 | u32 val; | |
878 | ||
879 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
880 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; | |
881 | ||
882 | /* Offset is in */ | |
883 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); | |
884 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
885 | } | |
886 | ||
887 | ||
888 | /* Tx descriptors helper methods */ | |
889 | ||
890 | /* Update HW with number of TX descriptors to be sent */ | |
891 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
892 | struct mvneta_tx_queue *txq, | |
893 | int pend_desc) | |
894 | { | |
895 | u32 val; | |
896 | ||
0d63785c SG |
897 | pend_desc += txq->pending; |
898 | ||
899 | /* Only 255 Tx descriptors can be added at once */ | |
900 | do { | |
901 | val = min(pend_desc, 255); | |
902 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
903 | pend_desc -= val; | |
904 | } while (pend_desc > 0); | |
2a90f7e1 | 905 | txq->pending = 0; |
c5aff182 TP |
906 | } |
907 | ||
908 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
909 | static struct mvneta_tx_desc * | |
910 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
911 | { | |
912 | int tx_desc = txq->next_desc_to_proc; | |
913 | ||
914 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
915 | return txq->descs + tx_desc; | |
916 | } | |
917 | ||
918 | /* Release the last allocated TX descriptor. Useful to handle DMA | |
6a20c175 TP |
919 | * mapping failures in the TX path. |
920 | */ | |
c5aff182 TP |
921 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
922 | { | |
923 | if (txq->next_desc_to_proc == 0) | |
924 | txq->next_desc_to_proc = txq->last_desc - 1; | |
925 | else | |
926 | txq->next_desc_to_proc--; | |
927 | } | |
928 | ||
929 | /* Set rxq buf size */ | |
930 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
931 | struct mvneta_rx_queue *rxq, | |
932 | int buf_size) | |
933 | { | |
934 | u32 val; | |
935 | ||
936 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
937 | ||
938 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
939 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
940 | ||
941 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
942 | } | |
943 | ||
944 | /* Disable buffer management (BM) */ | |
945 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, | |
946 | struct mvneta_rx_queue *rxq) | |
947 | { | |
948 | u32 val; | |
949 | ||
950 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
951 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; | |
952 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
953 | } | |
954 | ||
dc35a10f MW |
955 | /* Enable buffer management (BM) */ |
956 | static void mvneta_rxq_bm_enable(struct mvneta_port *pp, | |
957 | struct mvneta_rx_queue *rxq) | |
958 | { | |
959 | u32 val; | |
960 | ||
961 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
962 | val |= MVNETA_RXQ_HW_BUF_ALLOC; | |
963 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
964 | } | |
965 | ||
966 | /* Notify HW about port's assignment of pool for bigger packets */ | |
967 | static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, | |
968 | struct mvneta_rx_queue *rxq) | |
969 | { | |
970 | u32 val; | |
971 | ||
972 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
973 | val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; | |
974 | val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); | |
975 | ||
976 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
977 | } | |
978 | ||
979 | /* Notify HW about port's assignment of pool for smaller packets */ | |
980 | static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, | |
981 | struct mvneta_rx_queue *rxq) | |
982 | { | |
983 | u32 val; | |
984 | ||
985 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
986 | val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; | |
987 | val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); | |
988 | ||
989 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
990 | } | |
991 | ||
992 | /* Set port's receive buffer size for assigned BM pool */ | |
993 | static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, | |
994 | int buf_size, | |
995 | u8 pool_id) | |
996 | { | |
997 | u32 val; | |
998 | ||
999 | if (!IS_ALIGNED(buf_size, 8)) { | |
1000 | dev_warn(pp->dev->dev.parent, | |
1001 | "illegal buf_size value %d, round to %d\n", | |
1002 | buf_size, ALIGN(buf_size, 8)); | |
1003 | buf_size = ALIGN(buf_size, 8); | |
1004 | } | |
1005 | ||
1006 | val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); | |
1007 | val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; | |
1008 | mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); | |
1009 | } | |
1010 | ||
1011 | /* Configure MBUS window in order to enable access BM internal SRAM */ | |
1012 | static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, | |
1013 | u8 target, u8 attr) | |
1014 | { | |
1015 | u32 win_enable, win_protect; | |
1016 | int i; | |
1017 | ||
1018 | win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); | |
1019 | ||
1020 | if (pp->bm_win_id < 0) { | |
1021 | /* Find first not occupied window */ | |
1022 | for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { | |
1023 | if (win_enable & (1 << i)) { | |
1024 | pp->bm_win_id = i; | |
1025 | break; | |
1026 | } | |
1027 | } | |
1028 | if (i == MVNETA_MAX_DECODE_WIN) | |
1029 | return -ENOMEM; | |
1030 | } else { | |
1031 | i = pp->bm_win_id; | |
1032 | } | |
1033 | ||
1034 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
1035 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
1036 | ||
1037 | if (i < 4) | |
1038 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
1039 | ||
1040 | mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | | |
1041 | (attr << 8) | target); | |
1042 | ||
1043 | mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); | |
1044 | ||
1045 | win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); | |
1046 | win_protect |= 3 << (2 * i); | |
1047 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); | |
1048 | ||
1049 | win_enable &= ~(1 << i); | |
1050 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
2636ac3c | 1055 | static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) |
dc35a10f | 1056 | { |
2636ac3c | 1057 | u32 wsize; |
dc35a10f MW |
1058 | u8 target, attr; |
1059 | int err; | |
1060 | ||
1061 | /* Get BM window information */ | |
1062 | err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, | |
1063 | &target, &attr); | |
1064 | if (err < 0) | |
1065 | return err; | |
1066 | ||
1067 | pp->bm_win_id = -1; | |
1068 | ||
1069 | /* Open NETA -> BM window */ | |
1070 | err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, | |
1071 | target, attr); | |
1072 | if (err < 0) { | |
1073 | netdev_info(pp->dev, "fail to configure mbus window to BM\n"); | |
1074 | return err; | |
1075 | } | |
2636ac3c MW |
1076 | return 0; |
1077 | } | |
1078 | ||
1079 | /* Assign and initialize pools for port. In case of fail | |
1080 | * buffer manager will remain disabled for current port. | |
1081 | */ | |
1082 | static int mvneta_bm_port_init(struct platform_device *pdev, | |
1083 | struct mvneta_port *pp) | |
1084 | { | |
1085 | struct device_node *dn = pdev->dev.of_node; | |
1086 | u32 long_pool_id, short_pool_id; | |
1087 | ||
1088 | if (!pp->neta_armada3700) { | |
1089 | int ret; | |
1090 | ||
1091 | ret = mvneta_bm_port_mbus_init(pp); | |
1092 | if (ret) | |
1093 | return ret; | |
1094 | } | |
dc35a10f MW |
1095 | |
1096 | if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { | |
1097 | netdev_info(pp->dev, "missing long pool id\n"); | |
1098 | return -EINVAL; | |
1099 | } | |
1100 | ||
1101 | /* Create port's long pool depending on mtu */ | |
1102 | pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, | |
1103 | MVNETA_BM_LONG, pp->id, | |
1104 | MVNETA_RX_PKT_SIZE(pp->dev->mtu)); | |
1105 | if (!pp->pool_long) { | |
1106 | netdev_info(pp->dev, "fail to obtain long pool for port\n"); | |
1107 | return -ENOMEM; | |
1108 | } | |
1109 | ||
1110 | pp->pool_long->port_map |= 1 << pp->id; | |
1111 | ||
1112 | mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, | |
1113 | pp->pool_long->id); | |
1114 | ||
1115 | /* If short pool id is not defined, assume using single pool */ | |
1116 | if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) | |
1117 | short_pool_id = long_pool_id; | |
1118 | ||
1119 | /* Create port's short pool */ | |
1120 | pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, | |
1121 | MVNETA_BM_SHORT, pp->id, | |
1122 | MVNETA_BM_SHORT_PKT_SIZE); | |
1123 | if (!pp->pool_short) { | |
1124 | netdev_info(pp->dev, "fail to obtain short pool for port\n"); | |
1125 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1126 | return -ENOMEM; | |
1127 | } | |
1128 | ||
1129 | if (short_pool_id != long_pool_id) { | |
1130 | pp->pool_short->port_map |= 1 << pp->id; | |
1131 | mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, | |
1132 | pp->pool_short->id); | |
1133 | } | |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | /* Update settings of a pool for bigger packets */ | |
1139 | static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) | |
1140 | { | |
1141 | struct mvneta_bm_pool *bm_pool = pp->pool_long; | |
baa11ebc | 1142 | struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; |
dc35a10f MW |
1143 | int num; |
1144 | ||
1145 | /* Release all buffers from long pool */ | |
1146 | mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); | |
baa11ebc | 1147 | if (hwbm_pool->buf_num) { |
dc35a10f MW |
1148 | WARN(1, "cannot free all buffers in pool %d\n", |
1149 | bm_pool->id); | |
1150 | goto bm_mtu_err; | |
1151 | } | |
1152 | ||
1153 | bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); | |
1154 | bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); | |
baa11ebc GC |
1155 | hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + |
1156 | SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); | |
dc35a10f MW |
1157 | |
1158 | /* Fill entire long pool */ | |
6dcdd884 | 1159 | num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); |
baa11ebc | 1160 | if (num != hwbm_pool->size) { |
dc35a10f | 1161 | WARN(1, "pool %d: %d of %d allocated\n", |
baa11ebc | 1162 | bm_pool->id, num, hwbm_pool->size); |
dc35a10f MW |
1163 | goto bm_mtu_err; |
1164 | } | |
1165 | mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); | |
1166 | ||
1167 | return; | |
1168 | ||
1169 | bm_mtu_err: | |
1170 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1171 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); | |
1172 | ||
1173 | pp->bm_priv = NULL; | |
44efc78d | 1174 | pp->rx_offset_correction = MVNETA_SKB_HEADROOM; |
dc35a10f MW |
1175 | mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); |
1176 | netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); | |
1177 | } | |
1178 | ||
c5aff182 TP |
1179 | /* Start the Ethernet port RX and TX activity */ |
1180 | static void mvneta_port_up(struct mvneta_port *pp) | |
1181 | { | |
1182 | int queue; | |
1183 | u32 q_map; | |
1184 | ||
1185 | /* Enable all initialized TXs. */ | |
c5aff182 TP |
1186 | q_map = 0; |
1187 | for (queue = 0; queue < txq_number; queue++) { | |
1188 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
f95936cc | 1189 | if (txq->descs) |
c5aff182 TP |
1190 | q_map |= (1 << queue); |
1191 | } | |
1192 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
1193 | ||
e81b5e01 | 1194 | q_map = 0; |
c5aff182 | 1195 | /* Enable all initialized RXQs. */ |
2dcf75e2 GC |
1196 | for (queue = 0; queue < rxq_number; queue++) { |
1197 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
1198 | ||
f95936cc | 1199 | if (rxq->descs) |
2dcf75e2 GC |
1200 | q_map |= (1 << queue); |
1201 | } | |
1202 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
c5aff182 TP |
1203 | } |
1204 | ||
1205 | /* Stop the Ethernet port activity */ | |
1206 | static void mvneta_port_down(struct mvneta_port *pp) | |
1207 | { | |
1208 | u32 val; | |
1209 | int count; | |
1210 | ||
1211 | /* Stop Rx port activity. Check port Rx activity. */ | |
1212 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
1213 | ||
1214 | /* Issue stop command for active channels only */ | |
1215 | if (val != 0) | |
1216 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
1217 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
1218 | ||
1219 | /* Wait for all Rx activity to terminate. */ | |
1220 | count = 0; | |
1221 | do { | |
1222 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
1223 | netdev_warn(pp->dev, | |
0838abb3 | 1224 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", |
c5aff182 TP |
1225 | val); |
1226 | break; | |
1227 | } | |
1228 | mdelay(1); | |
1229 | ||
1230 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
a3703fb3 | 1231 | } while (val & MVNETA_RXQ_ENABLE_MASK); |
c5aff182 TP |
1232 | |
1233 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
6a20c175 TP |
1234 | * command for active channels only |
1235 | */ | |
c5aff182 TP |
1236 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
1237 | ||
1238 | if (val != 0) | |
1239 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
1240 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
1241 | ||
1242 | /* Wait for all Tx activity to terminate. */ | |
1243 | count = 0; | |
1244 | do { | |
1245 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
1246 | netdev_warn(pp->dev, | |
1247 | "TIMEOUT for TX stopped status=0x%08x\n", | |
1248 | val); | |
1249 | break; | |
1250 | } | |
1251 | mdelay(1); | |
1252 | ||
1253 | /* Check TX Command reg that all Txqs are stopped */ | |
1254 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
1255 | ||
a3703fb3 | 1256 | } while (val & MVNETA_TXQ_ENABLE_MASK); |
c5aff182 TP |
1257 | |
1258 | /* Double check to verify that TX FIFO is empty */ | |
1259 | count = 0; | |
1260 | do { | |
1261 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
1262 | netdev_warn(pp->dev, | |
0838abb3 | 1263 | "TX FIFO empty timeout status=0x%08x\n", |
c5aff182 TP |
1264 | val); |
1265 | break; | |
1266 | } | |
1267 | mdelay(1); | |
1268 | ||
1269 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
1270 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
1271 | (val & MVNETA_TX_IN_PRGRS)); | |
1272 | ||
1273 | udelay(200); | |
1274 | } | |
1275 | ||
1276 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
1277 | static void mvneta_port_enable(struct mvneta_port *pp) | |
1278 | { | |
1279 | u32 val; | |
1280 | ||
1281 | /* Enable port */ | |
1282 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1283 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
1284 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1285 | } | |
1286 | ||
1287 | /* Disable the port and wait for about 200 usec before retuning */ | |
1288 | static void mvneta_port_disable(struct mvneta_port *pp) | |
1289 | { | |
1290 | u32 val; | |
1291 | ||
1292 | /* Reset the Enable bit in the Serial Control Register */ | |
1293 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1294 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
1295 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1296 | ||
1297 | udelay(200); | |
1298 | } | |
1299 | ||
1300 | /* Multicast tables methods */ | |
1301 | ||
1302 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
1303 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
1304 | { | |
1305 | int offset; | |
1306 | u32 val; | |
1307 | ||
1308 | if (queue == -1) { | |
1309 | val = 0; | |
1310 | } else { | |
1311 | val = 0x1 | (queue << 1); | |
1312 | val |= (val << 24) | (val << 16) | (val << 8); | |
1313 | } | |
1314 | ||
1315 | for (offset = 0; offset <= 0xc; offset += 4) | |
1316 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
1317 | } | |
1318 | ||
1319 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
1320 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
1321 | { | |
1322 | int offset; | |
1323 | u32 val; | |
1324 | ||
1325 | if (queue == -1) { | |
1326 | val = 0; | |
1327 | } else { | |
1328 | val = 0x1 | (queue << 1); | |
1329 | val |= (val << 24) | (val << 16) | (val << 8); | |
1330 | } | |
1331 | ||
1332 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1333 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
1334 | ||
1335 | } | |
1336 | ||
1337 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
1338 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
1339 | { | |
1340 | int offset; | |
1341 | u32 val; | |
1342 | ||
1343 | if (queue == -1) { | |
1344 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
1345 | val = 0; | |
1346 | } else { | |
1347 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
1348 | val = 0x1 | (queue << 1); | |
1349 | val |= (val << 24) | (val << 16) | (val << 8); | |
1350 | } | |
1351 | ||
1352 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1353 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
1354 | } | |
1355 | ||
db488c10 GC |
1356 | static void mvneta_percpu_unmask_interrupt(void *arg) |
1357 | { | |
1358 | struct mvneta_port *pp = arg; | |
1359 | ||
1360 | /* All the queue are unmasked, but actually only the ones | |
1361 | * mapped to this CPU will be unmasked | |
1362 | */ | |
1363 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
1364 | MVNETA_RX_INTR_MASK_ALL | | |
1365 | MVNETA_TX_INTR_MASK_ALL | | |
1366 | MVNETA_MISCINTR_INTR_MASK); | |
1367 | } | |
1368 | ||
1369 | static void mvneta_percpu_mask_interrupt(void *arg) | |
1370 | { | |
1371 | struct mvneta_port *pp = arg; | |
1372 | ||
1373 | /* All the queue are masked, but actually only the ones | |
1374 | * mapped to this CPU will be masked | |
1375 | */ | |
1376 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
1377 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
1378 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
1379 | } | |
1380 | ||
1381 | static void mvneta_percpu_clear_intr_cause(void *arg) | |
1382 | { | |
1383 | struct mvneta_port *pp = arg; | |
1384 | ||
1385 | /* All the queue are cleared, but actually only the ones | |
1386 | * mapped to this CPU will be cleared | |
1387 | */ | |
1388 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
1389 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
1390 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
1391 | } | |
1392 | ||
c5aff182 TP |
1393 | /* This method sets defaults to the NETA port: |
1394 | * Clears interrupt Cause and Mask registers. | |
1395 | * Clears all MAC tables. | |
1396 | * Sets defaults to all registers. | |
1397 | * Resets RX and TX descriptor rings. | |
1398 | * Resets PHY. | |
1399 | * This method can be called after mvneta_port_down() to return the port | |
1400 | * settings to defaults. | |
1401 | */ | |
1402 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
1403 | { | |
1404 | int cpu; | |
1405 | int queue; | |
1406 | u32 val; | |
2dcf75e2 | 1407 | int max_cpu = num_present_cpus(); |
c5aff182 TP |
1408 | |
1409 | /* Clear all Cause registers */ | |
db488c10 | 1410 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
1411 | |
1412 | /* Mask all interrupts */ | |
db488c10 | 1413 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
1414 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); |
1415 | ||
1416 | /* Enable MBUS Retry bit16 */ | |
1417 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
1418 | ||
50bf8cb6 GC |
1419 | /* Set CPU queue access map. CPUs are assigned to the RX and |
1420 | * TX queues modulo their number. If there is only one TX | |
1421 | * queue then it is assigned to the CPU associated to the | |
1422 | * default RX queue. | |
6a20c175 | 1423 | */ |
2dcf75e2 GC |
1424 | for_each_present_cpu(cpu) { |
1425 | int rxq_map = 0, txq_map = 0; | |
50bf8cb6 | 1426 | int rxq, txq; |
2636ac3c MW |
1427 | if (!pp->neta_armada3700) { |
1428 | for (rxq = 0; rxq < rxq_number; rxq++) | |
1429 | if ((rxq % max_cpu) == cpu) | |
1430 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
1431 | ||
1432 | for (txq = 0; txq < txq_number; txq++) | |
1433 | if ((txq % max_cpu) == cpu) | |
1434 | txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); | |
1435 | ||
1436 | /* With only one TX queue we configure a special case | |
1437 | * which will allow to get all the irq on a single | |
1438 | * CPU | |
1439 | */ | |
1440 | if (txq_number == 1) | |
1441 | txq_map = (cpu == pp->rxq_def) ? | |
1442 | MVNETA_CPU_TXQ_ACCESS(1) : 0; | |
2dcf75e2 | 1443 | |
2636ac3c MW |
1444 | } else { |
1445 | txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
1446 | rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; | |
1447 | } | |
2dcf75e2 GC |
1448 | |
1449 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); | |
1450 | } | |
c5aff182 TP |
1451 | |
1452 | /* Reset RX and TX DMAs */ | |
1453 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
1454 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
1455 | ||
1456 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
1457 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
1458 | for (queue = 0; queue < txq_number; queue++) { | |
1459 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
1460 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
1461 | } | |
1462 | ||
1463 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
1464 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
1465 | ||
1466 | /* Set Port Acceleration Mode */ | |
dc35a10f MW |
1467 | if (pp->bm_priv) |
1468 | /* HW buffer management + legacy parser */ | |
1469 | val = MVNETA_ACC_MODE_EXT2; | |
1470 | else | |
1471 | /* SW buffer management + legacy parser */ | |
1472 | val = MVNETA_ACC_MODE_EXT1; | |
c5aff182 TP |
1473 | mvreg_write(pp, MVNETA_ACC_MODE, val); |
1474 | ||
dc35a10f MW |
1475 | if (pp->bm_priv) |
1476 | mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); | |
1477 | ||
c5aff182 | 1478 | /* Update val of portCfg register accordingly with all RxQueue types */ |
90b74c01 | 1479 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); |
c5aff182 TP |
1480 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); |
1481 | ||
1482 | val = 0; | |
1483 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
1484 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
1485 | ||
1486 | /* Build PORT_SDMA_CONFIG_REG */ | |
1487 | val = 0; | |
1488 | ||
1489 | /* Default burst size */ | |
1490 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
1491 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
9ad8fef6 | 1492 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; |
c5aff182 | 1493 | |
9ad8fef6 TP |
1494 | #if defined(__BIG_ENDIAN) |
1495 | val |= MVNETA_DESC_SWAP; | |
1496 | #endif | |
c5aff182 TP |
1497 | |
1498 | /* Assign port SDMA configuration */ | |
1499 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
1500 | ||
71408602 TP |
1501 | /* Disable PHY polling in hardware, since we're using the |
1502 | * kernel phylib to do this. | |
1503 | */ | |
1504 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
1505 | val &= ~MVNETA_PHY_POLLING_ENABLE; | |
1506 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
1507 | ||
c5aff182 TP |
1508 | mvneta_set_ucast_table(pp, -1); |
1509 | mvneta_set_special_mcast_table(pp, -1); | |
1510 | mvneta_set_other_mcast_table(pp, -1); | |
1511 | ||
1512 | /* Set port interrupt enable register - default enable all */ | |
1513 | mvreg_write(pp, MVNETA_INTR_ENABLE, | |
1514 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK | |
1515 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); | |
e483911f AL |
1516 | |
1517 | mvneta_mib_counters_clear(pp); | |
c5aff182 TP |
1518 | } |
1519 | ||
1520 | /* Set max sizes for tx queues */ | |
1521 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) | |
1522 | ||
1523 | { | |
1524 | u32 val, size, mtu; | |
1525 | int queue; | |
1526 | ||
1527 | mtu = max_tx_size * 8; | |
1528 | if (mtu > MVNETA_TX_MTU_MAX) | |
1529 | mtu = MVNETA_TX_MTU_MAX; | |
1530 | ||
1531 | /* Set MTU */ | |
1532 | val = mvreg_read(pp, MVNETA_TX_MTU); | |
1533 | val &= ~MVNETA_TX_MTU_MAX; | |
1534 | val |= mtu; | |
1535 | mvreg_write(pp, MVNETA_TX_MTU, val); | |
1536 | ||
1537 | /* TX token size and all TXQs token size must be larger that MTU */ | |
1538 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); | |
1539 | ||
1540 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; | |
1541 | if (size < mtu) { | |
1542 | size = mtu; | |
1543 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; | |
1544 | val |= size; | |
1545 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); | |
1546 | } | |
1547 | for (queue = 0; queue < txq_number; queue++) { | |
1548 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); | |
1549 | ||
1550 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1551 | if (size < mtu) { | |
1552 | size = mtu; | |
1553 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1554 | val |= size; | |
1555 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); | |
1556 | } | |
1557 | } | |
1558 | } | |
1559 | ||
1560 | /* Set unicast address */ | |
1561 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
1562 | int queue) | |
1563 | { | |
1564 | unsigned int unicast_reg; | |
1565 | unsigned int tbl_offset; | |
1566 | unsigned int reg_offset; | |
1567 | ||
1568 | /* Locate the Unicast table entry */ | |
1569 | last_nibble = (0xf & last_nibble); | |
1570 | ||
1571 | /* offset from unicast tbl base */ | |
1572 | tbl_offset = (last_nibble / 4) * 4; | |
1573 | ||
1574 | /* offset within the above reg */ | |
1575 | reg_offset = last_nibble % 4; | |
1576 | ||
1577 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
1578 | ||
1579 | if (queue == -1) { | |
1580 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
1581 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1582 | } else { | |
1583 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1584 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1585 | } | |
1586 | ||
1587 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
1588 | } | |
1589 | ||
1590 | /* Set mac address */ | |
1591 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
1592 | int queue) | |
1593 | { | |
1594 | unsigned int mac_h; | |
1595 | unsigned int mac_l; | |
1596 | ||
1597 | if (queue != -1) { | |
1598 | mac_l = (addr[4] << 8) | (addr[5]); | |
1599 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
1600 | (addr[2] << 8) | (addr[3] << 0); | |
1601 | ||
1602 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
1603 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
1604 | } | |
1605 | ||
1606 | /* Accept frames of this address */ | |
1607 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
1608 | } | |
1609 | ||
6a20c175 TP |
1610 | /* Set the number of packets that will be received before RX interrupt |
1611 | * will be generated by HW. | |
c5aff182 TP |
1612 | */ |
1613 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, | |
1614 | struct mvneta_rx_queue *rxq, u32 value) | |
1615 | { | |
1616 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), | |
1617 | value | MVNETA_RXQ_NON_OCCUPIED(0)); | |
c5aff182 TP |
1618 | } |
1619 | ||
6a20c175 TP |
1620 | /* Set the time delay in usec before RX interrupt will be generated by |
1621 | * HW. | |
c5aff182 TP |
1622 | */ |
1623 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, | |
1624 | struct mvneta_rx_queue *rxq, u32 value) | |
1625 | { | |
189dd626 TP |
1626 | u32 val; |
1627 | unsigned long clk_rate; | |
1628 | ||
1629 | clk_rate = clk_get_rate(pp->clk); | |
1630 | val = (clk_rate / 1000000) * value; | |
c5aff182 TP |
1631 | |
1632 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); | |
c5aff182 TP |
1633 | } |
1634 | ||
1635 | /* Set threshold for TX_DONE pkts coalescing */ | |
1636 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, | |
1637 | struct mvneta_tx_queue *txq, u32 value) | |
1638 | { | |
1639 | u32 val; | |
1640 | ||
1641 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); | |
1642 | ||
1643 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; | |
1644 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); | |
1645 | ||
1646 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); | |
c5aff182 TP |
1647 | } |
1648 | ||
c5aff182 TP |
1649 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
1650 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
f88bee1c GC |
1651 | u32 phys_addr, void *virt_addr, |
1652 | struct mvneta_rx_queue *rxq) | |
c5aff182 | 1653 | { |
f88bee1c GC |
1654 | int i; |
1655 | ||
c5aff182 | 1656 | rx_desc->buf_phys_addr = phys_addr; |
f88bee1c GC |
1657 | i = rx_desc - rxq->descs; |
1658 | rxq->buf_virt_addr[i] = virt_addr; | |
c5aff182 TP |
1659 | } |
1660 | ||
1661 | /* Decrement sent descriptors counter */ | |
1662 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
1663 | struct mvneta_tx_queue *txq, | |
1664 | int sent_desc) | |
1665 | { | |
1666 | u32 val; | |
1667 | ||
1668 | /* Only 255 TX descriptors can be updated at once */ | |
1669 | while (sent_desc > 0xff) { | |
1670 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1671 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1672 | sent_desc = sent_desc - 0xff; | |
1673 | } | |
1674 | ||
1675 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1676 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1677 | } | |
1678 | ||
1679 | /* Get number of TX descriptors already sent by HW */ | |
1680 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
1681 | struct mvneta_tx_queue *txq) | |
1682 | { | |
1683 | u32 val; | |
1684 | int sent_desc; | |
1685 | ||
1686 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
1687 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
1688 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
1689 | ||
1690 | return sent_desc; | |
1691 | } | |
1692 | ||
6a20c175 | 1693 | /* Get number of sent descriptors and decrement counter. |
c5aff182 TP |
1694 | * The number of sent descriptors is returned. |
1695 | */ | |
1696 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, | |
1697 | struct mvneta_tx_queue *txq) | |
1698 | { | |
1699 | int sent_desc; | |
1700 | ||
1701 | /* Get number of sent descriptors */ | |
1702 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1703 | ||
1704 | /* Decrement sent descriptors counter */ | |
1705 | if (sent_desc) | |
1706 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
1707 | ||
1708 | return sent_desc; | |
1709 | } | |
1710 | ||
1711 | /* Set TXQ descriptors fields relevant for CSUM calculation */ | |
1712 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, | |
1713 | int ip_hdr_len, int l4_proto) | |
1714 | { | |
1715 | u32 command; | |
1716 | ||
1717 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
6a20c175 TP |
1718 | * G_L4_chk, L4_type; required only for checksum |
1719 | * calculation | |
1720 | */ | |
c5aff182 TP |
1721 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
1722 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; | |
1723 | ||
0a198587 | 1724 | if (l3_proto == htons(ETH_P_IP)) |
c5aff182 TP |
1725 | command |= MVNETA_TXD_IP_CSUM; |
1726 | else | |
1727 | command |= MVNETA_TX_L3_IP6; | |
1728 | ||
1729 | if (l4_proto == IPPROTO_TCP) | |
1730 | command |= MVNETA_TX_L4_CSUM_FULL; | |
1731 | else if (l4_proto == IPPROTO_UDP) | |
1732 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; | |
1733 | else | |
1734 | command |= MVNETA_TX_L4_CSUM_NOT; | |
1735 | ||
1736 | return command; | |
1737 | } | |
1738 | ||
1739 | ||
1740 | /* Display more error info */ | |
1741 | static void mvneta_rx_error(struct mvneta_port *pp, | |
1742 | struct mvneta_rx_desc *rx_desc) | |
1743 | { | |
c35947b8 | 1744 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
c5aff182 TP |
1745 | u32 status = rx_desc->status; |
1746 | ||
c35947b8 LB |
1747 | /* update per-cpu counter */ |
1748 | u64_stats_update_begin(&stats->syncp); | |
1749 | stats->rx_errors++; | |
1750 | u64_stats_update_end(&stats->syncp); | |
1751 | ||
c5aff182 TP |
1752 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { |
1753 | case MVNETA_RXD_ERR_CRC: | |
1754 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
1755 | status, rx_desc->data_size); | |
1756 | break; | |
1757 | case MVNETA_RXD_ERR_OVERRUN: | |
1758 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
1759 | status, rx_desc->data_size); | |
1760 | break; | |
1761 | case MVNETA_RXD_ERR_LEN: | |
1762 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
1763 | status, rx_desc->data_size); | |
1764 | break; | |
1765 | case MVNETA_RXD_ERR_RESOURCE: | |
1766 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
1767 | status, rx_desc->data_size); | |
1768 | break; | |
1769 | } | |
1770 | } | |
1771 | ||
5428213c | 1772 | /* Handle RX checksum offload based on the descriptor's status */ |
1773 | static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, | |
c5aff182 TP |
1774 | struct sk_buff *skb) |
1775 | { | |
f945cec8 YK |
1776 | if ((pp->dev->features & NETIF_F_RXCSUM) && |
1777 | (status & MVNETA_RXD_L3_IP4) && | |
5428213c | 1778 | (status & MVNETA_RXD_L4_CSUM_OK)) { |
c5aff182 TP |
1779 | skb->csum = 0; |
1780 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1781 | return; | |
1782 | } | |
1783 | ||
1784 | skb->ip_summed = CHECKSUM_NONE; | |
1785 | } | |
1786 | ||
6c498974 | 1787 | /* Return tx queue pointer (find last set bit) according to <cause> returned |
1788 | * form tx_done reg. <cause> must not be null. The return value is always a | |
1789 | * valid queue for matching the first one found in <cause>. | |
1790 | */ | |
c5aff182 TP |
1791 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
1792 | u32 cause) | |
1793 | { | |
1794 | int queue = fls(cause) - 1; | |
1795 | ||
6c498974 | 1796 | return &pp->txqs[queue]; |
c5aff182 TP |
1797 | } |
1798 | ||
1799 | /* Free tx queue skbuffs */ | |
1800 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, | |
a29b6235 MW |
1801 | struct mvneta_tx_queue *txq, int num, |
1802 | struct netdev_queue *nq) | |
c5aff182 | 1803 | { |
a29b6235 | 1804 | unsigned int bytes_compl = 0, pkts_compl = 0; |
c5aff182 TP |
1805 | int i; |
1806 | ||
1807 | for (i = 0; i < num; i++) { | |
9e58c8b4 | 1808 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; |
c5aff182 TP |
1809 | struct mvneta_tx_desc *tx_desc = txq->descs + |
1810 | txq->txq_get_index; | |
a29b6235 | 1811 | |
c5aff182 TP |
1812 | mvneta_txq_inc_get(txq); |
1813 | ||
b0a43db9 LB |
1814 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && |
1815 | buf->type != MVNETA_TYPE_XDP_TX) | |
2e3173a3 EG |
1816 | dma_unmap_single(pp->dev->dev.parent, |
1817 | tx_desc->buf_phys_addr, | |
1818 | tx_desc->data_size, DMA_TO_DEVICE); | |
b0a43db9 LB |
1819 | if (buf->type == MVNETA_TYPE_SKB && buf->skb) { |
1820 | bytes_compl += buf->skb->len; | |
1821 | pkts_compl++; | |
1822 | dev_kfree_skb_any(buf->skb); | |
1823 | } else if (buf->type == MVNETA_TYPE_XDP_TX || | |
1824 | buf->type == MVNETA_TYPE_XDP_NDO) { | |
1825 | xdp_return_frame(buf->xdpf); | |
1826 | } | |
c5aff182 | 1827 | } |
a29b6235 MW |
1828 | |
1829 | netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); | |
c5aff182 TP |
1830 | } |
1831 | ||
1832 | /* Handle end of transmission */ | |
cd713199 | 1833 | static void mvneta_txq_done(struct mvneta_port *pp, |
c5aff182 TP |
1834 | struct mvneta_tx_queue *txq) |
1835 | { | |
1836 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1837 | int tx_done; | |
1838 | ||
1839 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); | |
cd713199 AE |
1840 | if (!tx_done) |
1841 | return; | |
1842 | ||
a29b6235 | 1843 | mvneta_txq_bufs_free(pp, txq, tx_done, nq); |
c5aff182 TP |
1844 | |
1845 | txq->count -= tx_done; | |
1846 | ||
1847 | if (netif_tx_queue_stopped(nq)) { | |
8eef5f97 | 1848 | if (txq->count <= txq->tx_wake_threshold) |
c5aff182 TP |
1849 | netif_tx_wake_queue(nq); |
1850 | } | |
c5aff182 TP |
1851 | } |
1852 | ||
dc35a10f | 1853 | /* Refill processing for SW buffer management */ |
7e47fd84 | 1854 | /* Allocate page per descriptor */ |
c5aff182 | 1855 | static int mvneta_rx_refill(struct mvneta_port *pp, |
f88bee1c | 1856 | struct mvneta_rx_desc *rx_desc, |
7e47fd84 GC |
1857 | struct mvneta_rx_queue *rxq, |
1858 | gfp_t gfp_mask) | |
c5aff182 TP |
1859 | { |
1860 | dma_addr_t phys_addr; | |
7e47fd84 | 1861 | struct page *page; |
c5aff182 | 1862 | |
568a3fa2 LB |
1863 | page = page_pool_alloc_pages(rxq->page_pool, |
1864 | gfp_mask | __GFP_NOWARN); | |
7e47fd84 | 1865 | if (!page) |
c5aff182 TP |
1866 | return -ENOMEM; |
1867 | ||
568a3fa2 | 1868 | phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; |
7e47fd84 | 1869 | mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); |
568a3fa2 | 1870 | |
c5aff182 TP |
1871 | return 0; |
1872 | } | |
1873 | ||
1874 | /* Handle tx checksum */ | |
1875 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) | |
1876 | { | |
1877 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1878 | int ip_hdr_len = 0; | |
817dbfa5 | 1879 | __be16 l3_proto = vlan_get_protocol(skb); |
c5aff182 TP |
1880 | u8 l4_proto; |
1881 | ||
817dbfa5 | 1882 | if (l3_proto == htons(ETH_P_IP)) { |
c5aff182 TP |
1883 | struct iphdr *ip4h = ip_hdr(skb); |
1884 | ||
1885 | /* Calculate IPv4 checksum and L4 checksum */ | |
1886 | ip_hdr_len = ip4h->ihl; | |
1887 | l4_proto = ip4h->protocol; | |
817dbfa5 | 1888 | } else if (l3_proto == htons(ETH_P_IPV6)) { |
c5aff182 TP |
1889 | struct ipv6hdr *ip6h = ipv6_hdr(skb); |
1890 | ||
1891 | /* Read l4_protocol from one of IPv6 extra headers */ | |
1892 | if (skb_network_header_len(skb) > 0) | |
1893 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
1894 | l4_proto = ip6h->nexthdr; | |
1895 | } else | |
1896 | return MVNETA_TX_L4_CSUM_NOT; | |
1897 | ||
1898 | return mvneta_txq_desc_csum(skb_network_offset(skb), | |
817dbfa5 | 1899 | l3_proto, ip_hdr_len, l4_proto); |
c5aff182 TP |
1900 | } |
1901 | ||
1902 | return MVNETA_TX_L4_CSUM_NOT; | |
1903 | } | |
1904 | ||
c5aff182 TP |
1905 | /* Drop packets received by the RXQ and free buffers */ |
1906 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
1907 | struct mvneta_rx_queue *rxq) | |
1908 | { | |
1909 | int rx_done, i; | |
1910 | ||
1911 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
dc35a10f MW |
1912 | if (rx_done) |
1913 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
1914 | ||
1915 | if (pp->bm_priv) { | |
1916 | for (i = 0; i < rx_done; i++) { | |
1917 | struct mvneta_rx_desc *rx_desc = | |
1918 | mvneta_rxq_next_desc_get(rxq); | |
1919 | u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); | |
1920 | struct mvneta_bm_pool *bm_pool; | |
1921 | ||
1922 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
1923 | /* Return dropped buffer to the pool */ | |
1924 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
1925 | rx_desc->buf_phys_addr); | |
1926 | } | |
1927 | return; | |
1928 | } | |
1929 | ||
c5aff182 TP |
1930 | for (i = 0; i < rxq->size; i++) { |
1931 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; | |
f88bee1c | 1932 | void *data = rxq->buf_virt_addr[i]; |
562e2f46 YK |
1933 | if (!data || !(rx_desc->buf_phys_addr)) |
1934 | continue; | |
c5aff182 | 1935 | |
568a3fa2 | 1936 | page_pool_put_page(rxq->page_pool, data, false); |
c5aff182 | 1937 | } |
568a3fa2 LB |
1938 | if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) |
1939 | xdp_rxq_info_unreg(&rxq->xdp_rxq); | |
1940 | page_pool_destroy(rxq->page_pool); | |
1941 | rxq->page_pool = NULL; | |
dc35a10f | 1942 | } |
c5aff182 | 1943 | |
ff519e2a LB |
1944 | static void |
1945 | mvneta_update_stats(struct mvneta_port *pp, u32 pkts, | |
1946 | u32 len, bool tx) | |
1947 | { | |
1948 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); | |
1949 | ||
1950 | u64_stats_update_begin(&stats->syncp); | |
1951 | if (tx) { | |
1952 | stats->tx_packets += pkts; | |
1953 | stats->tx_bytes += len; | |
1954 | } else { | |
1955 | stats->rx_packets += pkts; | |
1956 | stats->rx_bytes += len; | |
1957 | } | |
1958 | u64_stats_update_end(&stats->syncp); | |
1959 | } | |
1960 | ||
562e2f46 YK |
1961 | static inline |
1962 | int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) | |
1963 | { | |
1964 | struct mvneta_rx_desc *rx_desc; | |
1965 | int curr_desc = rxq->first_to_refill; | |
1966 | int i; | |
1967 | ||
1968 | for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { | |
1969 | rx_desc = rxq->descs + curr_desc; | |
1970 | if (!(rx_desc->buf_phys_addr)) { | |
1971 | if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { | |
1972 | pr_err("Can't refill queue %d. Done %d from %d\n", | |
1973 | rxq->id, i, rxq->refill_num); | |
1974 | rxq->refill_err++; | |
1975 | break; | |
1976 | } | |
1977 | } | |
1978 | curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); | |
1979 | } | |
1980 | rxq->refill_num -= i; | |
1981 | rxq->first_to_refill = curr_desc; | |
1982 | ||
1983 | return i; | |
1984 | } | |
1985 | ||
b0a43db9 LB |
1986 | static int |
1987 | mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, | |
1988 | struct xdp_frame *xdpf, bool dma_map) | |
1989 | { | |
1990 | struct mvneta_tx_desc *tx_desc; | |
1991 | struct mvneta_tx_buf *buf; | |
1992 | dma_addr_t dma_addr; | |
1993 | ||
1994 | if (txq->count >= txq->tx_stop_threshold) | |
1995 | return MVNETA_XDP_DROPPED; | |
1996 | ||
1997 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1998 | ||
1999 | buf = &txq->buf[txq->txq_put_index]; | |
2000 | if (dma_map) { | |
2001 | /* ndo_xdp_xmit */ | |
2002 | dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, | |
2003 | xdpf->len, DMA_TO_DEVICE); | |
2004 | if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { | |
2005 | mvneta_txq_desc_put(txq); | |
2006 | return MVNETA_XDP_DROPPED; | |
2007 | } | |
2008 | buf->type = MVNETA_TYPE_XDP_NDO; | |
2009 | } else { | |
2010 | struct page *page = virt_to_page(xdpf->data); | |
2011 | ||
2012 | dma_addr = page_pool_get_dma_addr(page) + | |
2013 | sizeof(*xdpf) + xdpf->headroom; | |
2014 | dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, | |
2015 | xdpf->len, DMA_BIDIRECTIONAL); | |
2016 | buf->type = MVNETA_TYPE_XDP_TX; | |
2017 | } | |
2018 | buf->xdpf = xdpf; | |
2019 | ||
2020 | tx_desc->command = MVNETA_TXD_FLZ_DESC; | |
2021 | tx_desc->buf_phys_addr = dma_addr; | |
2022 | tx_desc->data_size = xdpf->len; | |
2023 | ||
2024 | mvneta_update_stats(pp, 1, xdpf->len, true); | |
2025 | mvneta_txq_inc_put(txq); | |
2026 | txq->pending++; | |
2027 | txq->count++; | |
2028 | ||
2029 | return MVNETA_XDP_TX; | |
2030 | } | |
2031 | ||
2032 | static int | |
2033 | mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) | |
2034 | { | |
2035 | struct mvneta_tx_queue *txq; | |
2036 | struct netdev_queue *nq; | |
2037 | struct xdp_frame *xdpf; | |
2038 | int cpu; | |
2039 | u32 ret; | |
2040 | ||
2041 | xdpf = convert_to_xdp_frame(xdp); | |
2042 | if (unlikely(!xdpf)) | |
2043 | return MVNETA_XDP_DROPPED; | |
2044 | ||
2045 | cpu = smp_processor_id(); | |
2046 | txq = &pp->txqs[cpu % txq_number]; | |
2047 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
2048 | ||
2049 | __netif_tx_lock(nq, cpu); | |
2050 | ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); | |
2051 | if (ret == MVNETA_XDP_TX) | |
2052 | mvneta_txq_pend_desc_add(pp, txq, 0); | |
2053 | __netif_tx_unlock(nq); | |
2054 | ||
2055 | return ret; | |
2056 | } | |
2057 | ||
2058 | static int | |
2059 | mvneta_xdp_xmit(struct net_device *dev, int num_frame, | |
2060 | struct xdp_frame **frames, u32 flags) | |
2061 | { | |
2062 | struct mvneta_port *pp = netdev_priv(dev); | |
2063 | int cpu = smp_processor_id(); | |
2064 | struct mvneta_tx_queue *txq; | |
2065 | struct netdev_queue *nq; | |
2066 | int i, drops = 0; | |
2067 | u32 ret; | |
2068 | ||
2069 | if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) | |
2070 | return -EINVAL; | |
2071 | ||
2072 | txq = &pp->txqs[cpu % txq_number]; | |
2073 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
2074 | ||
2075 | __netif_tx_lock(nq, cpu); | |
2076 | for (i = 0; i < num_frame; i++) { | |
2077 | ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); | |
2078 | if (ret != MVNETA_XDP_TX) { | |
2079 | xdp_return_frame_rx_napi(frames[i]); | |
2080 | drops++; | |
2081 | } | |
2082 | } | |
2083 | ||
2084 | if (unlikely(flags & XDP_XMIT_FLUSH)) | |
2085 | mvneta_txq_pend_desc_add(pp, txq, 0); | |
2086 | __netif_tx_unlock(nq); | |
2087 | ||
2088 | return num_frame - drops; | |
2089 | } | |
2090 | ||
0db51da7 LB |
2091 | static int |
2092 | mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
2093 | struct bpf_prog *prog, struct xdp_buff *xdp) | |
2094 | { | |
8c4df83f LB |
2095 | unsigned int len; |
2096 | u32 ret, act; | |
2097 | ||
2098 | len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; | |
2099 | act = bpf_prog_run_xdp(prog, xdp); | |
0db51da7 LB |
2100 | |
2101 | switch (act) { | |
2102 | case XDP_PASS: | |
2103 | ret = MVNETA_XDP_PASS; | |
2104 | break; | |
2105 | case XDP_REDIRECT: { | |
2106 | int err; | |
2107 | ||
2108 | err = xdp_do_redirect(pp->dev, xdp, prog); | |
2109 | if (err) { | |
2110 | ret = MVNETA_XDP_DROPPED; | |
07e13edb | 2111 | __page_pool_put_page(rxq->page_pool, |
8c4df83f LB |
2112 | virt_to_head_page(xdp->data), |
2113 | len, true); | |
0db51da7 LB |
2114 | } else { |
2115 | ret = MVNETA_XDP_REDIR; | |
2116 | } | |
2117 | break; | |
2118 | } | |
b0a43db9 LB |
2119 | case XDP_TX: |
2120 | ret = mvneta_xdp_xmit_back(pp, xdp); | |
2121 | if (ret != MVNETA_XDP_TX) | |
07e13edb | 2122 | __page_pool_put_page(rxq->page_pool, |
8c4df83f LB |
2123 | virt_to_head_page(xdp->data), |
2124 | len, true); | |
b0a43db9 | 2125 | break; |
0db51da7 LB |
2126 | default: |
2127 | bpf_warn_invalid_xdp_action(act); | |
2128 | /* fall through */ | |
2129 | case XDP_ABORTED: | |
2130 | trace_xdp_exception(pp->dev, prog, act); | |
2131 | /* fall through */ | |
2132 | case XDP_DROP: | |
07e13edb LB |
2133 | __page_pool_put_page(rxq->page_pool, |
2134 | virt_to_head_page(xdp->data), | |
8c4df83f | 2135 | len, true); |
0db51da7 LB |
2136 | ret = MVNETA_XDP_DROPPED; |
2137 | break; | |
2138 | } | |
2139 | ||
2140 | return ret; | |
2141 | } | |
2142 | ||
8dc9a088 LB |
2143 | static int |
2144 | mvneta_swbm_rx_frame(struct mvneta_port *pp, | |
2145 | struct mvneta_rx_desc *rx_desc, | |
2146 | struct mvneta_rx_queue *rxq, | |
0db51da7 LB |
2147 | struct xdp_buff *xdp, |
2148 | struct bpf_prog *xdp_prog, | |
2149 | struct page *page, u32 *xdp_ret) | |
8dc9a088 LB |
2150 | { |
2151 | unsigned char *data = page_address(page); | |
2152 | int data_len = -MVNETA_MH_SIZE, len; | |
2153 | struct net_device *dev = pp->dev; | |
2154 | enum dma_data_direction dma_dir; | |
2155 | ||
2156 | if (MVNETA_SKB_SIZE(rx_desc->data_size) > PAGE_SIZE) { | |
2157 | len = MVNETA_MAX_RX_BUF_SIZE; | |
2158 | data_len += len; | |
2159 | } else { | |
2160 | len = rx_desc->data_size; | |
2161 | data_len += len - ETH_FCS_LEN; | |
2162 | } | |
2163 | ||
2164 | dma_dir = page_pool_get_dma_dir(rxq->page_pool); | |
2165 | dma_sync_single_for_cpu(dev->dev.parent, | |
2166 | rx_desc->buf_phys_addr, | |
2167 | len, dma_dir); | |
2168 | ||
fa383f6b LB |
2169 | /* Prefetch header */ |
2170 | prefetch(data); | |
2171 | ||
0db51da7 | 2172 | xdp->data_hard_start = data; |
b37fa92e | 2173 | xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE; |
0db51da7 LB |
2174 | xdp->data_end = xdp->data + data_len; |
2175 | xdp_set_data_meta_invalid(xdp); | |
2176 | ||
2177 | if (xdp_prog) { | |
2178 | u32 ret; | |
2179 | ||
2180 | ret = mvneta_run_xdp(pp, rxq, xdp_prog, xdp); | |
2181 | if (ret != MVNETA_XDP_PASS) { | |
2182 | mvneta_update_stats(pp, 1, | |
2183 | xdp->data_end - xdp->data, | |
2184 | false); | |
2185 | rx_desc->buf_phys_addr = 0; | |
2186 | *xdp_ret |= ret; | |
2187 | return ret; | |
2188 | } | |
2189 | } | |
2190 | ||
2191 | rxq->skb = build_skb(xdp->data_hard_start, PAGE_SIZE); | |
8dc9a088 | 2192 | if (unlikely(!rxq->skb)) { |
c35947b8 LB |
2193 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
2194 | ||
2195 | netdev_err(dev, "Can't allocate skb on queue %d\n", rxq->id); | |
8dc9a088 | 2196 | rxq->skb_alloc_err++; |
c35947b8 LB |
2197 | |
2198 | u64_stats_update_begin(&stats->syncp); | |
2199 | stats->rx_dropped++; | |
2200 | u64_stats_update_end(&stats->syncp); | |
2201 | ||
8dc9a088 LB |
2202 | return -ENOMEM; |
2203 | } | |
2204 | page_pool_release_page(rxq->page_pool, page); | |
2205 | ||
0db51da7 LB |
2206 | skb_reserve(rxq->skb, |
2207 | xdp->data - xdp->data_hard_start); | |
2208 | skb_put(rxq->skb, xdp->data_end - xdp->data); | |
8dc9a088 LB |
2209 | mvneta_rx_csum(pp, rx_desc->status, rxq->skb); |
2210 | ||
2211 | rxq->left_size = rx_desc->data_size - len; | |
2212 | rx_desc->buf_phys_addr = 0; | |
2213 | ||
2214 | return 0; | |
2215 | } | |
2216 | ||
2217 | static void | |
2218 | mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, | |
2219 | struct mvneta_rx_desc *rx_desc, | |
2220 | struct mvneta_rx_queue *rxq, | |
2221 | struct page *page) | |
2222 | { | |
2223 | struct net_device *dev = pp->dev; | |
2224 | enum dma_data_direction dma_dir; | |
2225 | int data_len, len; | |
2226 | ||
2227 | if (rxq->left_size > MVNETA_MAX_RX_BUF_SIZE) { | |
2228 | len = MVNETA_MAX_RX_BUF_SIZE; | |
2229 | data_len = len; | |
2230 | } else { | |
2231 | len = rxq->left_size; | |
2232 | data_len = len - ETH_FCS_LEN; | |
2233 | } | |
2234 | dma_dir = page_pool_get_dma_dir(rxq->page_pool); | |
2235 | dma_sync_single_for_cpu(dev->dev.parent, | |
2236 | rx_desc->buf_phys_addr, | |
2237 | len, dma_dir); | |
2238 | if (data_len > 0) { | |
2239 | /* refill descriptor with new buffer later */ | |
2240 | skb_add_rx_frag(rxq->skb, | |
2241 | skb_shinfo(rxq->skb)->nr_frags, | |
b37fa92e | 2242 | page, pp->rx_offset_correction, data_len, |
8dc9a088 LB |
2243 | PAGE_SIZE); |
2244 | } | |
2245 | page_pool_release_page(rxq->page_pool, page); | |
2246 | rx_desc->buf_phys_addr = 0; | |
2247 | rxq->left_size -= len; | |
2248 | } | |
2249 | ||
dc35a10f | 2250 | /* Main rx processing when using software buffer management */ |
7a86f05f | 2251 | static int mvneta_rx_swbm(struct napi_struct *napi, |
562e2f46 | 2252 | struct mvneta_port *pp, int budget, |
dc35a10f MW |
2253 | struct mvneta_rx_queue *rxq) |
2254 | { | |
8dc9a088 | 2255 | int rcvd_pkts = 0, rcvd_bytes = 0, rx_proc = 0; |
dc35a10f | 2256 | struct net_device *dev = pp->dev; |
0db51da7 LB |
2257 | struct bpf_prog *xdp_prog; |
2258 | struct xdp_buff xdp_buf; | |
8dc9a088 | 2259 | int rx_todo, refill; |
0db51da7 | 2260 | u32 xdp_ret = 0; |
dc35a10f MW |
2261 | |
2262 | /* Get number of received packets */ | |
562e2f46 | 2263 | rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); |
dc35a10f | 2264 | |
0db51da7 LB |
2265 | rcu_read_lock(); |
2266 | xdp_prog = READ_ONCE(pp->xdp_prog); | |
2267 | xdp_buf.rxq = &rxq->xdp_rxq; | |
2268 | ||
dc35a10f | 2269 | /* Fairness NAPI loop */ |
8dc9a088 | 2270 | while (rx_proc < budget && rx_proc < rx_todo) { |
dc35a10f | 2271 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); |
8dc9a088 | 2272 | u32 rx_status, index; |
7e47fd84 | 2273 | struct page *page; |
dc35a10f | 2274 | |
f88bee1c | 2275 | index = rx_desc - rxq->descs; |
7e47fd84 | 2276 | page = (struct page *)rxq->buf_virt_addr[index]; |
dc35a10f | 2277 | |
562e2f46 YK |
2278 | rx_status = rx_desc->status; |
2279 | rx_proc++; | |
2280 | rxq->refill_num++; | |
2281 | ||
2282 | if (rx_status & MVNETA_RXD_FIRST_DESC) { | |
8dc9a088 LB |
2283 | int err; |
2284 | ||
562e2f46 YK |
2285 | /* Check errors only for FIRST descriptor */ |
2286 | if (rx_status & MVNETA_RXD_ERR_SUMMARY) { | |
2287 | mvneta_rx_error(pp, rx_desc); | |
562e2f46 YK |
2288 | /* leave the descriptor untouched */ |
2289 | continue; | |
2290 | } | |
dc35a10f | 2291 | |
0db51da7 LB |
2292 | err = mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, |
2293 | xdp_prog, page, &xdp_ret); | |
8dc9a088 | 2294 | if (err) |
562e2f46 | 2295 | continue; |
562e2f46 | 2296 | } else { |
562e2f46 YK |
2297 | if (unlikely(!rxq->skb)) { |
2298 | pr_debug("no skb for rx_status 0x%x\n", | |
2299 | rx_status); | |
2300 | continue; | |
2301 | } | |
8dc9a088 | 2302 | mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, page); |
562e2f46 | 2303 | } /* Middle or Last descriptor */ |
dc35a10f | 2304 | |
562e2f46 YK |
2305 | if (!(rx_status & MVNETA_RXD_LAST_DESC)) |
2306 | /* no last descriptor this time */ | |
dc35a10f | 2307 | continue; |
dc35a10f | 2308 | |
562e2f46 YK |
2309 | if (rxq->left_size) { |
2310 | pr_err("get last desc, but left_size (%d) != 0\n", | |
2311 | rxq->left_size); | |
2312 | dev_kfree_skb_any(rxq->skb); | |
2313 | rxq->left_size = 0; | |
2314 | rxq->skb = NULL; | |
2315 | continue; | |
dc35a10f | 2316 | } |
dc35a10f | 2317 | rcvd_pkts++; |
562e2f46 | 2318 | rcvd_bytes += rxq->skb->len; |
dc35a10f MW |
2319 | |
2320 | /* Linux processing */ | |
562e2f46 | 2321 | rxq->skb->protocol = eth_type_trans(rxq->skb, dev); |
dc35a10f | 2322 | |
d28118e3 | 2323 | napi_gro_receive(napi, rxq->skb); |
dc35a10f | 2324 | |
562e2f46 YK |
2325 | /* clean uncomplete skb pointer in queue */ |
2326 | rxq->skb = NULL; | |
dc35a10f | 2327 | } |
0db51da7 LB |
2328 | rcu_read_unlock(); |
2329 | ||
2330 | if (xdp_ret & MVNETA_XDP_REDIR) | |
2331 | xdp_do_flush_map(); | |
dc35a10f | 2332 | |
ff519e2a LB |
2333 | if (rcvd_pkts) |
2334 | mvneta_update_stats(pp, rcvd_pkts, rcvd_bytes, false); | |
dc35a10f | 2335 | |
562e2f46 YK |
2336 | /* return some buffers to hardware queue, one at a time is too slow */ |
2337 | refill = mvneta_rx_refill_queue(pp, rxq); | |
2338 | ||
dc35a10f | 2339 | /* Update rxq management counters */ |
562e2f46 | 2340 | mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); |
dc35a10f | 2341 | |
562e2f46 | 2342 | return rcvd_pkts; |
c5aff182 TP |
2343 | } |
2344 | ||
dc35a10f | 2345 | /* Main rx processing when using hardware buffer management */ |
7a86f05f AL |
2346 | static int mvneta_rx_hwbm(struct napi_struct *napi, |
2347 | struct mvneta_port *pp, int rx_todo, | |
dc35a10f | 2348 | struct mvneta_rx_queue *rxq) |
c5aff182 TP |
2349 | { |
2350 | struct net_device *dev = pp->dev; | |
a84e3289 | 2351 | int rx_done; |
dc4277dd | 2352 | u32 rcvd_pkts = 0; |
2353 | u32 rcvd_bytes = 0; | |
c5aff182 TP |
2354 | |
2355 | /* Get number of received packets */ | |
2356 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
2357 | ||
2358 | if (rx_todo > rx_done) | |
2359 | rx_todo = rx_done; | |
2360 | ||
2361 | rx_done = 0; | |
c5aff182 TP |
2362 | |
2363 | /* Fairness NAPI loop */ | |
2364 | while (rx_done < rx_todo) { | |
2365 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
dc35a10f | 2366 | struct mvneta_bm_pool *bm_pool = NULL; |
c5aff182 | 2367 | struct sk_buff *skb; |
8ec2cd48 | 2368 | unsigned char *data; |
daf158d0 | 2369 | dma_addr_t phys_addr; |
dc35a10f | 2370 | u32 rx_status, frag_size; |
c5aff182 | 2371 | int rx_bytes, err; |
dc35a10f | 2372 | u8 pool_id; |
c5aff182 | 2373 | |
c5aff182 | 2374 | rx_done++; |
c5aff182 | 2375 | rx_status = rx_desc->status; |
f19fadfc | 2376 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); |
f88bee1c | 2377 | data = (u8 *)(uintptr_t)rx_desc->buf_cookie; |
daf158d0 | 2378 | phys_addr = rx_desc->buf_phys_addr; |
dc35a10f MW |
2379 | pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); |
2380 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
c5aff182 | 2381 | |
5428213c | 2382 | if (!mvneta_rxq_desc_is_first_last(rx_status) || |
f19fadfc | 2383 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { |
dc35a10f MW |
2384 | err_drop_frame_ret_pool: |
2385 | /* Return the buffer to the pool */ | |
2386 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2387 | rx_desc->buf_phys_addr); | |
2388 | err_drop_frame: | |
c5aff182 | 2389 | mvneta_rx_error(pp, rx_desc); |
8ec2cd48 | 2390 | /* leave the descriptor untouched */ |
c5aff182 TP |
2391 | continue; |
2392 | } | |
2393 | ||
f19fadfc | 2394 | if (rx_bytes <= rx_copybreak) { |
2395 | /* better copy a small frame and not unmap the DMA region */ | |
2396 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
2397 | if (unlikely(!skb)) | |
dc35a10f | 2398 | goto err_drop_frame_ret_pool; |
f19fadfc | 2399 | |
a8fef9ba | 2400 | dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, |
f19fadfc | 2401 | rx_desc->buf_phys_addr, |
2402 | MVNETA_MH_SIZE + NET_SKB_PAD, | |
2403 | rx_bytes, | |
2404 | DMA_FROM_DEVICE); | |
59ae1d12 JB |
2405 | skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, |
2406 | rx_bytes); | |
f19fadfc | 2407 | |
2408 | skb->protocol = eth_type_trans(skb, dev); | |
2409 | mvneta_rx_csum(pp, rx_status, skb); | |
7a86f05f | 2410 | napi_gro_receive(napi, skb); |
f19fadfc | 2411 | |
2412 | rcvd_pkts++; | |
2413 | rcvd_bytes += rx_bytes; | |
2414 | ||
dc35a10f MW |
2415 | /* Return the buffer to the pool */ |
2416 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2417 | rx_desc->buf_phys_addr); | |
2418 | ||
f19fadfc | 2419 | /* leave the descriptor and buffer untouched */ |
2420 | continue; | |
2421 | } | |
2422 | ||
a84e3289 | 2423 | /* Refill processing */ |
baa11ebc | 2424 | err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); |
a84e3289 SG |
2425 | if (err) { |
2426 | netdev_err(dev, "Linux processing - Can't refill\n"); | |
17a96da6 | 2427 | rxq->refill_err++; |
dc35a10f | 2428 | goto err_drop_frame_ret_pool; |
a84e3289 SG |
2429 | } |
2430 | ||
baa11ebc | 2431 | frag_size = bm_pool->hwbm_pool.frag_size; |
dc35a10f MW |
2432 | |
2433 | skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); | |
f19fadfc | 2434 | |
26c17a17 MW |
2435 | /* After refill old buffer has to be unmapped regardless |
2436 | * the skb is successfully built or not. | |
2437 | */ | |
dc35a10f MW |
2438 | dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, |
2439 | bm_pool->buf_size, DMA_FROM_DEVICE); | |
26c17a17 MW |
2440 | if (!skb) |
2441 | goto err_drop_frame; | |
2442 | ||
dc4277dd | 2443 | rcvd_pkts++; |
2444 | rcvd_bytes += rx_bytes; | |
c5aff182 TP |
2445 | |
2446 | /* Linux processing */ | |
8ec2cd48 | 2447 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); |
c5aff182 TP |
2448 | skb_put(skb, rx_bytes); |
2449 | ||
2450 | skb->protocol = eth_type_trans(skb, dev); | |
2451 | ||
5428213c | 2452 | mvneta_rx_csum(pp, rx_status, skb); |
c5aff182 | 2453 | |
7a86f05f | 2454 | napi_gro_receive(napi, skb); |
c5aff182 TP |
2455 | } |
2456 | ||
ff519e2a LB |
2457 | if (rcvd_pkts) |
2458 | mvneta_update_stats(pp, rcvd_pkts, rcvd_bytes, false); | |
dc4277dd | 2459 | |
c5aff182 | 2460 | /* Update rxq management counters */ |
a84e3289 | 2461 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
c5aff182 TP |
2462 | |
2463 | return rx_done; | |
2464 | } | |
2465 | ||
2adb719d EG |
2466 | static inline void |
2467 | mvneta_tso_put_hdr(struct sk_buff *skb, | |
2468 | struct mvneta_port *pp, struct mvneta_tx_queue *txq) | |
2469 | { | |
2adb719d | 2470 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
9e58c8b4 LB |
2471 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
2472 | struct mvneta_tx_desc *tx_desc; | |
2adb719d | 2473 | |
2adb719d EG |
2474 | tx_desc = mvneta_txq_next_desc_get(txq); |
2475 | tx_desc->data_size = hdr_len; | |
2476 | tx_desc->command = mvneta_skb_tx_csum(pp, skb); | |
2477 | tx_desc->command |= MVNETA_TXD_F_DESC; | |
2478 | tx_desc->buf_phys_addr = txq->tso_hdrs_phys + | |
2479 | txq->txq_put_index * TSO_HEADER_SIZE; | |
9e58c8b4 LB |
2480 | buf->type = MVNETA_TYPE_SKB; |
2481 | buf->skb = NULL; | |
2482 | ||
2adb719d EG |
2483 | mvneta_txq_inc_put(txq); |
2484 | } | |
2485 | ||
2486 | static inline int | |
2487 | mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, | |
2488 | struct sk_buff *skb, char *data, int size, | |
2489 | bool last_tcp, bool is_last) | |
2490 | { | |
9e58c8b4 | 2491 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
2adb719d EG |
2492 | struct mvneta_tx_desc *tx_desc; |
2493 | ||
2494 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2495 | tx_desc->data_size = size; | |
2496 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, | |
2497 | size, DMA_TO_DEVICE); | |
2498 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2499 | tx_desc->buf_phys_addr))) { | |
2500 | mvneta_txq_desc_put(txq); | |
2501 | return -ENOMEM; | |
2502 | } | |
2503 | ||
2504 | tx_desc->command = 0; | |
9e58c8b4 LB |
2505 | buf->type = MVNETA_TYPE_SKB; |
2506 | buf->skb = NULL; | |
2adb719d EG |
2507 | |
2508 | if (last_tcp) { | |
2509 | /* last descriptor in the TCP packet */ | |
2510 | tx_desc->command = MVNETA_TXD_L_DESC; | |
2511 | ||
2512 | /* last descriptor in SKB */ | |
2513 | if (is_last) | |
9e58c8b4 | 2514 | buf->skb = skb; |
2adb719d EG |
2515 | } |
2516 | mvneta_txq_inc_put(txq); | |
2517 | return 0; | |
2518 | } | |
2519 | ||
2520 | static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
2521 | struct mvneta_tx_queue *txq) | |
2522 | { | |
2523 | int total_len, data_left; | |
2524 | int desc_count = 0; | |
2525 | struct mvneta_port *pp = netdev_priv(dev); | |
2526 | struct tso_t tso; | |
2527 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2528 | int i; | |
2529 | ||
2530 | /* Count needed descriptors */ | |
2531 | if ((txq->count + tso_count_descs(skb)) >= txq->size) | |
2532 | return 0; | |
2533 | ||
2534 | if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { | |
2535 | pr_info("*** Is this even possible???!?!?\n"); | |
2536 | return 0; | |
2537 | } | |
2538 | ||
2539 | /* Initialize the TSO handler, and prepare the first payload */ | |
2540 | tso_start(skb, &tso); | |
2541 | ||
2542 | total_len = skb->len - hdr_len; | |
2543 | while (total_len > 0) { | |
2544 | char *hdr; | |
2545 | ||
2546 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); | |
2547 | total_len -= data_left; | |
2548 | desc_count++; | |
2549 | ||
2550 | /* prepare packet headers: MAC + IP + TCP */ | |
2551 | hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; | |
2552 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); | |
2553 | ||
2554 | mvneta_tso_put_hdr(skb, pp, txq); | |
2555 | ||
2556 | while (data_left > 0) { | |
2557 | int size; | |
2558 | desc_count++; | |
2559 | ||
2560 | size = min_t(int, tso.size, data_left); | |
2561 | ||
2562 | if (mvneta_tso_put_data(dev, txq, skb, | |
2563 | tso.data, size, | |
2564 | size == data_left, | |
2565 | total_len == 0)) | |
2566 | goto err_release; | |
2567 | data_left -= size; | |
2568 | ||
2569 | tso_build_data(skb, &tso, size); | |
2570 | } | |
2571 | } | |
2572 | ||
2573 | return desc_count; | |
2574 | ||
2575 | err_release: | |
2576 | /* Release all used data descriptors; header descriptors must not | |
2577 | * be DMA-unmapped. | |
2578 | */ | |
2579 | for (i = desc_count - 1; i >= 0; i--) { | |
2580 | struct mvneta_tx_desc *tx_desc = txq->descs + i; | |
2e3173a3 | 2581 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
2adb719d EG |
2582 | dma_unmap_single(pp->dev->dev.parent, |
2583 | tx_desc->buf_phys_addr, | |
2584 | tx_desc->data_size, | |
2585 | DMA_TO_DEVICE); | |
2586 | mvneta_txq_desc_put(txq); | |
2587 | } | |
2588 | return 0; | |
2589 | } | |
2590 | ||
c5aff182 TP |
2591 | /* Handle tx fragmentation processing */ |
2592 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, | |
2593 | struct mvneta_tx_queue *txq) | |
2594 | { | |
2595 | struct mvneta_tx_desc *tx_desc; | |
3d4ea02f | 2596 | int i, nr_frags = skb_shinfo(skb)->nr_frags; |
c5aff182 | 2597 | |
3d4ea02f | 2598 | for (i = 0; i < nr_frags; i++) { |
9e58c8b4 | 2599 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
c5aff182 | 2600 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
d7840976 | 2601 | void *addr = skb_frag_address(frag); |
c5aff182 TP |
2602 | |
2603 | tx_desc = mvneta_txq_next_desc_get(txq); | |
d7840976 | 2604 | tx_desc->data_size = skb_frag_size(frag); |
c5aff182 TP |
2605 | |
2606 | tx_desc->buf_phys_addr = | |
2607 | dma_map_single(pp->dev->dev.parent, addr, | |
2608 | tx_desc->data_size, DMA_TO_DEVICE); | |
2609 | ||
2610 | if (dma_mapping_error(pp->dev->dev.parent, | |
2611 | tx_desc->buf_phys_addr)) { | |
2612 | mvneta_txq_desc_put(txq); | |
2613 | goto error; | |
2614 | } | |
2615 | ||
3d4ea02f | 2616 | if (i == nr_frags - 1) { |
c5aff182 TP |
2617 | /* Last descriptor */ |
2618 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; | |
9e58c8b4 | 2619 | buf->skb = skb; |
c5aff182 TP |
2620 | } else { |
2621 | /* Descriptor in the middle: Not First, Not Last */ | |
2622 | tx_desc->command = 0; | |
9e58c8b4 | 2623 | buf->skb = NULL; |
c5aff182 | 2624 | } |
9e58c8b4 | 2625 | buf->type = MVNETA_TYPE_SKB; |
3d4ea02f | 2626 | mvneta_txq_inc_put(txq); |
c5aff182 TP |
2627 | } |
2628 | ||
2629 | return 0; | |
2630 | ||
2631 | error: | |
2632 | /* Release all descriptors that were used to map fragments of | |
6a20c175 TP |
2633 | * this packet, as well as the corresponding DMA mappings |
2634 | */ | |
c5aff182 TP |
2635 | for (i = i - 1; i >= 0; i--) { |
2636 | tx_desc = txq->descs + i; | |
2637 | dma_unmap_single(pp->dev->dev.parent, | |
2638 | tx_desc->buf_phys_addr, | |
2639 | tx_desc->data_size, | |
2640 | DMA_TO_DEVICE); | |
2641 | mvneta_txq_desc_put(txq); | |
2642 | } | |
2643 | ||
2644 | return -ENOMEM; | |
2645 | } | |
2646 | ||
2647 | /* Main tx processing */ | |
f03508ce | 2648 | static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) |
c5aff182 TP |
2649 | { |
2650 | struct mvneta_port *pp = netdev_priv(dev); | |
ee40a116 WT |
2651 | u16 txq_id = skb_get_queue_mapping(skb); |
2652 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; | |
9e58c8b4 | 2653 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
c5aff182 | 2654 | struct mvneta_tx_desc *tx_desc; |
5f478b41 | 2655 | int len = skb->len; |
c5aff182 TP |
2656 | int frags = 0; |
2657 | u32 tx_cmd; | |
2658 | ||
2659 | if (!netif_running(dev)) | |
2660 | goto out; | |
2661 | ||
2adb719d EG |
2662 | if (skb_is_gso(skb)) { |
2663 | frags = mvneta_tx_tso(skb, dev, txq); | |
2664 | goto out; | |
2665 | } | |
2666 | ||
c5aff182 | 2667 | frags = skb_shinfo(skb)->nr_frags + 1; |
c5aff182 TP |
2668 | |
2669 | /* Get a descriptor for the first part of the packet */ | |
2670 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2671 | ||
2672 | tx_cmd = mvneta_skb_tx_csum(pp, skb); | |
2673 | ||
2674 | tx_desc->data_size = skb_headlen(skb); | |
2675 | ||
2676 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, | |
2677 | tx_desc->data_size, | |
2678 | DMA_TO_DEVICE); | |
2679 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2680 | tx_desc->buf_phys_addr))) { | |
2681 | mvneta_txq_desc_put(txq); | |
2682 | frags = 0; | |
2683 | goto out; | |
2684 | } | |
2685 | ||
9e58c8b4 | 2686 | buf->type = MVNETA_TYPE_SKB; |
c5aff182 TP |
2687 | if (frags == 1) { |
2688 | /* First and Last descriptor */ | |
2689 | tx_cmd |= MVNETA_TXD_FLZ_DESC; | |
2690 | tx_desc->command = tx_cmd; | |
9e58c8b4 | 2691 | buf->skb = skb; |
c5aff182 TP |
2692 | mvneta_txq_inc_put(txq); |
2693 | } else { | |
2694 | /* First but not Last */ | |
2695 | tx_cmd |= MVNETA_TXD_F_DESC; | |
9e58c8b4 | 2696 | buf->skb = NULL; |
c5aff182 TP |
2697 | mvneta_txq_inc_put(txq); |
2698 | tx_desc->command = tx_cmd; | |
2699 | /* Continue with other skb fragments */ | |
2700 | if (mvneta_tx_frag_process(pp, skb, txq)) { | |
2701 | dma_unmap_single(dev->dev.parent, | |
2702 | tx_desc->buf_phys_addr, | |
2703 | tx_desc->data_size, | |
2704 | DMA_TO_DEVICE); | |
2705 | mvneta_txq_desc_put(txq); | |
2706 | frags = 0; | |
2707 | goto out; | |
2708 | } | |
2709 | } | |
2710 | ||
c5aff182 TP |
2711 | out: |
2712 | if (frags > 0) { | |
e19d2dda EG |
2713 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
2714 | ||
a29b6235 MW |
2715 | netdev_tx_sent_queue(nq, len); |
2716 | ||
e19d2dda | 2717 | txq->count += frags; |
8eef5f97 | 2718 | if (txq->count >= txq->tx_stop_threshold) |
e19d2dda | 2719 | netif_tx_stop_queue(nq); |
c5aff182 | 2720 | |
6b16f9ee | 2721 | if (!netdev_xmit_more() || netif_xmit_stopped(nq) || |
2a90f7e1 SG |
2722 | txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) |
2723 | mvneta_txq_pend_desc_add(pp, txq, frags); | |
2724 | else | |
2725 | txq->pending += frags; | |
2726 | ||
ff519e2a | 2727 | mvneta_update_stats(pp, 1, len, true); |
c5aff182 TP |
2728 | } else { |
2729 | dev->stats.tx_dropped++; | |
2730 | dev_kfree_skb_any(skb); | |
2731 | } | |
2732 | ||
c5aff182 TP |
2733 | return NETDEV_TX_OK; |
2734 | } | |
2735 | ||
2736 | ||
2737 | /* Free tx resources, when resetting a port */ | |
2738 | static void mvneta_txq_done_force(struct mvneta_port *pp, | |
2739 | struct mvneta_tx_queue *txq) | |
2740 | ||
2741 | { | |
a29b6235 | 2742 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
c5aff182 TP |
2743 | int tx_done = txq->count; |
2744 | ||
a29b6235 | 2745 | mvneta_txq_bufs_free(pp, txq, tx_done, nq); |
c5aff182 TP |
2746 | |
2747 | /* reset txq */ | |
2748 | txq->count = 0; | |
2749 | txq->txq_put_index = 0; | |
2750 | txq->txq_get_index = 0; | |
2751 | } | |
2752 | ||
6c498974 | 2753 | /* Handle tx done - called in softirq context. The <cause_tx_done> argument |
2754 | * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. | |
2755 | */ | |
0713a86a | 2756 | static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) |
c5aff182 TP |
2757 | { |
2758 | struct mvneta_tx_queue *txq; | |
c5aff182 | 2759 | struct netdev_queue *nq; |
bd9f1ee3 | 2760 | int cpu = smp_processor_id(); |
c5aff182 | 2761 | |
6c498974 | 2762 | while (cause_tx_done) { |
c5aff182 | 2763 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
c5aff182 TP |
2764 | |
2765 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
bd9f1ee3 | 2766 | __netif_tx_lock(nq, cpu); |
c5aff182 | 2767 | |
0713a86a AE |
2768 | if (txq->count) |
2769 | mvneta_txq_done(pp, txq); | |
c5aff182 TP |
2770 | |
2771 | __netif_tx_unlock(nq); | |
2772 | cause_tx_done &= ~((1 << txq->id)); | |
2773 | } | |
c5aff182 TP |
2774 | } |
2775 | ||
6a20c175 | 2776 | /* Compute crc8 of the specified address, using a unique algorithm , |
c5aff182 TP |
2777 | * according to hw spec, different than generic crc8 algorithm |
2778 | */ | |
2779 | static int mvneta_addr_crc(unsigned char *addr) | |
2780 | { | |
2781 | int crc = 0; | |
2782 | int i; | |
2783 | ||
2784 | for (i = 0; i < ETH_ALEN; i++) { | |
2785 | int j; | |
2786 | ||
2787 | crc = (crc ^ addr[i]) << 8; | |
2788 | for (j = 7; j >= 0; j--) { | |
2789 | if (crc & (0x100 << j)) | |
2790 | crc ^= 0x107 << j; | |
2791 | } | |
2792 | } | |
2793 | ||
2794 | return crc; | |
2795 | } | |
2796 | ||
2797 | /* This method controls the net device special MAC multicast support. | |
2798 | * The Special Multicast Table for MAC addresses supports MAC of the form | |
2799 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2800 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2801 | * Table entries in the DA-Filter table. This method set the Special | |
2802 | * Multicast Table appropriate entry. | |
2803 | */ | |
2804 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, | |
2805 | unsigned char last_byte, | |
2806 | int queue) | |
2807 | { | |
2808 | unsigned int smc_table_reg; | |
2809 | unsigned int tbl_offset; | |
2810 | unsigned int reg_offset; | |
2811 | ||
2812 | /* Register offset from SMC table base */ | |
2813 | tbl_offset = (last_byte / 4); | |
2814 | /* Entry offset within the above reg */ | |
2815 | reg_offset = last_byte % 4; | |
2816 | ||
2817 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST | |
2818 | + tbl_offset * 4)); | |
2819 | ||
2820 | if (queue == -1) | |
2821 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2822 | else { | |
2823 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2824 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2825 | } | |
2826 | ||
2827 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, | |
2828 | smc_table_reg); | |
2829 | } | |
2830 | ||
2831 | /* This method controls the network device Other MAC multicast support. | |
2832 | * The Other Multicast Table is used for multicast of another type. | |
2833 | * A CRC-8 is used as an index to the Other Multicast Table entries | |
2834 | * in the DA-Filter table. | |
2835 | * The method gets the CRC-8 value from the calling routine and | |
2836 | * sets the Other Multicast Table appropriate entry according to the | |
2837 | * specified CRC-8 . | |
2838 | */ | |
2839 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, | |
2840 | unsigned char crc8, | |
2841 | int queue) | |
2842 | { | |
2843 | unsigned int omc_table_reg; | |
2844 | unsigned int tbl_offset; | |
2845 | unsigned int reg_offset; | |
2846 | ||
2847 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ | |
2848 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ | |
2849 | ||
2850 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); | |
2851 | ||
2852 | if (queue == -1) { | |
2853 | /* Clear accepts frame bit at specified Other DA table entry */ | |
2854 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2855 | } else { | |
2856 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2857 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2858 | } | |
2859 | ||
2860 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); | |
2861 | } | |
2862 | ||
2863 | /* The network device supports multicast using two tables: | |
2864 | * 1) Special Multicast Table for MAC addresses of the form | |
2865 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2866 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2867 | * Table entries in the DA-Filter table. | |
2868 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value | |
2869 | * is used as an index to the Other Multicast Table entries in the | |
2870 | * DA-Filter table. | |
2871 | */ | |
2872 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, | |
2873 | int queue) | |
2874 | { | |
2875 | unsigned char crc_result = 0; | |
2876 | ||
2877 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { | |
2878 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); | |
2879 | return 0; | |
2880 | } | |
2881 | ||
2882 | crc_result = mvneta_addr_crc(p_addr); | |
2883 | if (queue == -1) { | |
2884 | if (pp->mcast_count[crc_result] == 0) { | |
2885 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", | |
2886 | crc_result); | |
2887 | return -EINVAL; | |
2888 | } | |
2889 | ||
2890 | pp->mcast_count[crc_result]--; | |
2891 | if (pp->mcast_count[crc_result] != 0) { | |
2892 | netdev_info(pp->dev, | |
2893 | "After delete there are %d valid Mcast for crc8=0x%02x\n", | |
2894 | pp->mcast_count[crc_result], crc_result); | |
2895 | return -EINVAL; | |
2896 | } | |
2897 | } else | |
2898 | pp->mcast_count[crc_result]++; | |
2899 | ||
2900 | mvneta_set_other_mcast_addr(pp, crc_result, queue); | |
2901 | ||
2902 | return 0; | |
2903 | } | |
2904 | ||
2905 | /* Configure Fitering mode of Ethernet port */ | |
2906 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, | |
2907 | int is_promisc) | |
2908 | { | |
2909 | u32 port_cfg_reg, val; | |
2910 | ||
2911 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); | |
2912 | ||
2913 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); | |
2914 | ||
2915 | /* Set / Clear UPM bit in port configuration register */ | |
2916 | if (is_promisc) { | |
2917 | /* Accept all Unicast addresses */ | |
2918 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; | |
2919 | val |= MVNETA_FORCE_UNI; | |
2920 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); | |
2921 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); | |
2922 | } else { | |
2923 | /* Reject all Unicast addresses */ | |
2924 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; | |
2925 | val &= ~MVNETA_FORCE_UNI; | |
2926 | } | |
2927 | ||
2928 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); | |
2929 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); | |
2930 | } | |
2931 | ||
2932 | /* register unicast and multicast addresses */ | |
2933 | static void mvneta_set_rx_mode(struct net_device *dev) | |
2934 | { | |
2935 | struct mvneta_port *pp = netdev_priv(dev); | |
2936 | struct netdev_hw_addr *ha; | |
2937 | ||
2938 | if (dev->flags & IFF_PROMISC) { | |
2939 | /* Accept all: Multicast + Unicast */ | |
2940 | mvneta_rx_unicast_promisc_set(pp, 1); | |
90b74c01 GC |
2941 | mvneta_set_ucast_table(pp, pp->rxq_def); |
2942 | mvneta_set_special_mcast_table(pp, pp->rxq_def); | |
2943 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2944 | } else { |
2945 | /* Accept single Unicast */ | |
2946 | mvneta_rx_unicast_promisc_set(pp, 0); | |
2947 | mvneta_set_ucast_table(pp, -1); | |
90b74c01 | 2948 | mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); |
c5aff182 TP |
2949 | |
2950 | if (dev->flags & IFF_ALLMULTI) { | |
2951 | /* Accept all multicast */ | |
90b74c01 GC |
2952 | mvneta_set_special_mcast_table(pp, pp->rxq_def); |
2953 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2954 | } else { |
2955 | /* Accept only initialized multicast */ | |
2956 | mvneta_set_special_mcast_table(pp, -1); | |
2957 | mvneta_set_other_mcast_table(pp, -1); | |
2958 | ||
2959 | if (!netdev_mc_empty(dev)) { | |
2960 | netdev_for_each_mc_addr(ha, dev) { | |
2961 | mvneta_mcast_addr_set(pp, ha->addr, | |
90b74c01 | 2962 | pp->rxq_def); |
c5aff182 TP |
2963 | } |
2964 | } | |
2965 | } | |
2966 | } | |
2967 | } | |
2968 | ||
2969 | /* Interrupt handling - the callback for request_irq() */ | |
2970 | static irqreturn_t mvneta_isr(int irq, void *dev_id) | |
2636ac3c MW |
2971 | { |
2972 | struct mvneta_port *pp = (struct mvneta_port *)dev_id; | |
2973 | ||
2974 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
2975 | napi_schedule(&pp->napi); | |
2976 | ||
2977 | return IRQ_HANDLED; | |
2978 | } | |
2979 | ||
2980 | /* Interrupt handling - the callback for request_percpu_irq() */ | |
2981 | static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) | |
c5aff182 | 2982 | { |
12bb03b4 | 2983 | struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; |
c5aff182 | 2984 | |
12bb03b4 | 2985 | disable_percpu_irq(port->pp->dev->irq); |
12bb03b4 | 2986 | napi_schedule(&port->napi); |
c5aff182 TP |
2987 | |
2988 | return IRQ_HANDLED; | |
2989 | } | |
2990 | ||
503f9aa9 | 2991 | static void mvneta_link_change(struct mvneta_port *pp) |
898b2970 | 2992 | { |
898b2970 SS |
2993 | u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); |
2994 | ||
503f9aa9 | 2995 | phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); |
898b2970 SS |
2996 | } |
2997 | ||
c5aff182 TP |
2998 | /* NAPI handler |
2999 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted | |
3000 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). | |
3001 | * Bits 8 -15 of the cause Rx Tx register indicate that are received | |
3002 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). | |
3003 | * Each CPU has its own causeRxTx register | |
3004 | */ | |
3005 | static int mvneta_poll(struct napi_struct *napi, int budget) | |
3006 | { | |
3007 | int rx_done = 0; | |
3008 | u32 cause_rx_tx; | |
2dcf75e2 | 3009 | int rx_queue; |
c5aff182 | 3010 | struct mvneta_port *pp = netdev_priv(napi->dev); |
12bb03b4 | 3011 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 TP |
3012 | |
3013 | if (!netif_running(pp->dev)) { | |
2636ac3c | 3014 | napi_complete(napi); |
c5aff182 TP |
3015 | return rx_done; |
3016 | } | |
3017 | ||
3018 | /* Read cause register */ | |
898b2970 SS |
3019 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); |
3020 | if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { | |
3021 | u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); | |
3022 | ||
3023 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
503f9aa9 RK |
3024 | |
3025 | if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 3026 | MVNETA_CAUSE_LINK_CHANGE)) |
503f9aa9 | 3027 | mvneta_link_change(pp); |
898b2970 | 3028 | } |
71f6d1b3 | 3029 | |
3030 | /* Release Tx descriptors */ | |
3031 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { | |
0713a86a | 3032 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); |
71f6d1b3 | 3033 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; |
3034 | } | |
c5aff182 | 3035 | |
6a20c175 | 3036 | /* For the case where the last mvneta_poll did not process all |
c5aff182 TP |
3037 | * RX packets |
3038 | */ | |
2dcf75e2 GC |
3039 | rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); |
3040 | ||
2636ac3c MW |
3041 | cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : |
3042 | port->cause_rx_tx; | |
2dcf75e2 GC |
3043 | |
3044 | if (rx_queue) { | |
3045 | rx_queue = rx_queue - 1; | |
dc35a10f | 3046 | if (pp->bm_priv) |
7a86f05f AL |
3047 | rx_done = mvneta_rx_hwbm(napi, pp, budget, |
3048 | &pp->rxqs[rx_queue]); | |
dc35a10f | 3049 | else |
7a86f05f AL |
3050 | rx_done = mvneta_rx_swbm(napi, pp, budget, |
3051 | &pp->rxqs[rx_queue]); | |
2dcf75e2 GC |
3052 | } |
3053 | ||
6ad20165 | 3054 | if (rx_done < budget) { |
c5aff182 | 3055 | cause_rx_tx = 0; |
6ad20165 | 3056 | napi_complete_done(napi, rx_done); |
2636ac3c MW |
3057 | |
3058 | if (pp->neta_armada3700) { | |
3059 | unsigned long flags; | |
3060 | ||
3061 | local_irq_save(flags); | |
3062 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
3063 | MVNETA_RX_INTR_MASK(rxq_number) | | |
3064 | MVNETA_TX_INTR_MASK(txq_number) | | |
3065 | MVNETA_MISCINTR_INTR_MASK); | |
3066 | local_irq_restore(flags); | |
3067 | } else { | |
3068 | enable_percpu_irq(pp->dev->irq, 0); | |
3069 | } | |
c5aff182 TP |
3070 | } |
3071 | ||
2636ac3c MW |
3072 | if (pp->neta_armada3700) |
3073 | pp->cause_rx_tx = cause_rx_tx; | |
3074 | else | |
3075 | port->cause_rx_tx = cause_rx_tx; | |
3076 | ||
c5aff182 TP |
3077 | return rx_done; |
3078 | } | |
3079 | ||
568a3fa2 LB |
3080 | static int mvneta_create_page_pool(struct mvneta_port *pp, |
3081 | struct mvneta_rx_queue *rxq, int size) | |
3082 | { | |
0db51da7 | 3083 | struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); |
568a3fa2 LB |
3084 | struct page_pool_params pp_params = { |
3085 | .order = 0, | |
07e13edb | 3086 | .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, |
568a3fa2 | 3087 | .pool_size = size, |
1657adcc | 3088 | .nid = NUMA_NO_NODE, |
568a3fa2 | 3089 | .dev = pp->dev->dev.parent, |
0db51da7 | 3090 | .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, |
07e13edb LB |
3091 | .offset = pp->rx_offset_correction, |
3092 | .max_len = MVNETA_MAX_RX_BUF_SIZE, | |
568a3fa2 LB |
3093 | }; |
3094 | int err; | |
3095 | ||
3096 | rxq->page_pool = page_pool_create(&pp_params); | |
3097 | if (IS_ERR(rxq->page_pool)) { | |
3098 | err = PTR_ERR(rxq->page_pool); | |
3099 | rxq->page_pool = NULL; | |
3100 | return err; | |
3101 | } | |
3102 | ||
3103 | err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id); | |
3104 | if (err < 0) | |
3105 | goto err_free_pp; | |
3106 | ||
3107 | err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, | |
3108 | rxq->page_pool); | |
3109 | if (err) | |
3110 | goto err_unregister_rxq; | |
3111 | ||
3112 | return 0; | |
3113 | ||
3114 | err_unregister_rxq: | |
3115 | xdp_rxq_info_unreg(&rxq->xdp_rxq); | |
3116 | err_free_pp: | |
3117 | page_pool_destroy(rxq->page_pool); | |
3118 | rxq->page_pool = NULL; | |
3119 | return err; | |
3120 | } | |
3121 | ||
c5aff182 TP |
3122 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
3123 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
3124 | int num) | |
3125 | { | |
568a3fa2 LB |
3126 | int i, err; |
3127 | ||
3128 | err = mvneta_create_page_pool(pp, rxq, num); | |
3129 | if (err < 0) | |
3130 | return err; | |
c5aff182 TP |
3131 | |
3132 | for (i = 0; i < num; i++) { | |
a1a65ab1 | 3133 | memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); |
7e47fd84 GC |
3134 | if (mvneta_rx_refill(pp, rxq->descs + i, rxq, |
3135 | GFP_KERNEL) != 0) { | |
3136 | netdev_err(pp->dev, | |
3137 | "%s:rxq %d, %d of %d buffs filled\n", | |
3138 | __func__, rxq->id, i, num); | |
c5aff182 TP |
3139 | break; |
3140 | } | |
c5aff182 TP |
3141 | } |
3142 | ||
3143 | /* Add this number of RX descriptors as non occupied (ready to | |
6a20c175 TP |
3144 | * get packets) |
3145 | */ | |
c5aff182 TP |
3146 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
3147 | ||
3148 | return i; | |
3149 | } | |
3150 | ||
3151 | /* Free all packets pending transmit from all TXQs and reset TX port */ | |
3152 | static void mvneta_tx_reset(struct mvneta_port *pp) | |
3153 | { | |
3154 | int queue; | |
3155 | ||
9672850b | 3156 | /* free the skb's in the tx ring */ |
c5aff182 TP |
3157 | for (queue = 0; queue < txq_number; queue++) |
3158 | mvneta_txq_done_force(pp, &pp->txqs[queue]); | |
3159 | ||
3160 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
3161 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
3162 | } | |
3163 | ||
3164 | static void mvneta_rx_reset(struct mvneta_port *pp) | |
3165 | { | |
3166 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
3167 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
3168 | } | |
3169 | ||
3170 | /* Rx/Tx queue initialization/cleanup methods */ | |
3171 | ||
4a188a63 JZ |
3172 | static int mvneta_rxq_sw_init(struct mvneta_port *pp, |
3173 | struct mvneta_rx_queue *rxq) | |
c5aff182 TP |
3174 | { |
3175 | rxq->size = pp->rx_ring_size; | |
3176 | ||
3177 | /* Allocate memory for RX descriptors */ | |
3178 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
3179 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3180 | &rxq->descs_phys, GFP_KERNEL); | |
f95936cc | 3181 | if (!rxq->descs) |
c5aff182 | 3182 | return -ENOMEM; |
c5aff182 | 3183 | |
c5aff182 TP |
3184 | rxq->last_desc = rxq->size - 1; |
3185 | ||
4a188a63 JZ |
3186 | return 0; |
3187 | } | |
3188 | ||
3189 | static void mvneta_rxq_hw_init(struct mvneta_port *pp, | |
3190 | struct mvneta_rx_queue *rxq) | |
3191 | { | |
c5aff182 TP |
3192 | /* Set Rx descriptors queue starting address */ |
3193 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
3194 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
3195 | ||
c5aff182 TP |
3196 | /* Set coalescing pkts and time */ |
3197 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
3198 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
3199 | ||
dc35a10f | 3200 | if (!pp->bm_priv) { |
562e2f46 YK |
3201 | /* Set Offset */ |
3202 | mvneta_rxq_offset_set(pp, rxq, 0); | |
e735fd55 | 3203 | mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? |
8dc9a088 | 3204 | MVNETA_MAX_RX_BUF_SIZE : |
e735fd55 | 3205 | MVNETA_RX_BUF_SIZE(pp->pkt_size)); |
dc35a10f | 3206 | mvneta_rxq_bm_disable(pp, rxq); |
e9f64999 | 3207 | mvneta_rxq_fill(pp, rxq, rxq->size); |
dc35a10f | 3208 | } else { |
562e2f46 YK |
3209 | /* Set Offset */ |
3210 | mvneta_rxq_offset_set(pp, rxq, | |
3211 | NET_SKB_PAD - pp->rx_offset_correction); | |
3212 | ||
dc35a10f | 3213 | mvneta_rxq_bm_enable(pp, rxq); |
562e2f46 | 3214 | /* Fill RXQ with buffers from RX pool */ |
dc35a10f MW |
3215 | mvneta_rxq_long_pool_set(pp, rxq); |
3216 | mvneta_rxq_short_pool_set(pp, rxq); | |
e9f64999 | 3217 | mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); |
dc35a10f | 3218 | } |
4a188a63 JZ |
3219 | } |
3220 | ||
3221 | /* Create a specified RX queue */ | |
3222 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
3223 | struct mvneta_rx_queue *rxq) | |
3224 | ||
3225 | { | |
3226 | int ret; | |
3227 | ||
3228 | ret = mvneta_rxq_sw_init(pp, rxq); | |
3229 | if (ret < 0) | |
3230 | return ret; | |
3231 | ||
3232 | mvneta_rxq_hw_init(pp, rxq); | |
dc35a10f | 3233 | |
c5aff182 TP |
3234 | return 0; |
3235 | } | |
3236 | ||
3237 | /* Cleanup Rx queue */ | |
3238 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
3239 | struct mvneta_rx_queue *rxq) | |
3240 | { | |
3241 | mvneta_rxq_drop_pkts(pp, rxq); | |
3242 | ||
562e2f46 YK |
3243 | if (rxq->skb) |
3244 | dev_kfree_skb_any(rxq->skb); | |
3245 | ||
c5aff182 TP |
3246 | if (rxq->descs) |
3247 | dma_free_coherent(pp->dev->dev.parent, | |
3248 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3249 | rxq->descs, | |
3250 | rxq->descs_phys); | |
3251 | ||
3252 | rxq->descs = NULL; | |
3253 | rxq->last_desc = 0; | |
3254 | rxq->next_desc_to_proc = 0; | |
3255 | rxq->descs_phys = 0; | |
562e2f46 YK |
3256 | rxq->first_to_refill = 0; |
3257 | rxq->refill_num = 0; | |
3258 | rxq->skb = NULL; | |
3259 | rxq->left_size = 0; | |
c5aff182 TP |
3260 | } |
3261 | ||
4a188a63 JZ |
3262 | static int mvneta_txq_sw_init(struct mvneta_port *pp, |
3263 | struct mvneta_tx_queue *txq) | |
c5aff182 | 3264 | { |
50bf8cb6 GC |
3265 | int cpu; |
3266 | ||
c5aff182 TP |
3267 | txq->size = pp->tx_ring_size; |
3268 | ||
8eef5f97 EG |
3269 | /* A queue must always have room for at least one skb. |
3270 | * Therefore, stop the queue when the free entries reaches | |
3271 | * the maximum number of descriptors per skb. | |
3272 | */ | |
3273 | txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; | |
3274 | txq->tx_wake_threshold = txq->tx_stop_threshold / 2; | |
3275 | ||
c5aff182 TP |
3276 | /* Allocate memory for TX descriptors */ |
3277 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
3278 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3279 | &txq->descs_phys, GFP_KERNEL); | |
f95936cc | 3280 | if (!txq->descs) |
c5aff182 | 3281 | return -ENOMEM; |
c5aff182 | 3282 | |
c5aff182 TP |
3283 | txq->last_desc = txq->size - 1; |
3284 | ||
9e58c8b4 LB |
3285 | txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); |
3286 | if (!txq->buf) { | |
c5aff182 TP |
3287 | dma_free_coherent(pp->dev->dev.parent, |
3288 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3289 | txq->descs, txq->descs_phys); | |
3290 | return -ENOMEM; | |
3291 | } | |
2adb719d EG |
3292 | |
3293 | /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ | |
3294 | txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, | |
3295 | txq->size * TSO_HEADER_SIZE, | |
3296 | &txq->tso_hdrs_phys, GFP_KERNEL); | |
f95936cc | 3297 | if (!txq->tso_hdrs) { |
9e58c8b4 | 3298 | kfree(txq->buf); |
2adb719d EG |
3299 | dma_free_coherent(pp->dev->dev.parent, |
3300 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3301 | txq->descs, txq->descs_phys); | |
3302 | return -ENOMEM; | |
3303 | } | |
c5aff182 | 3304 | |
50bf8cb6 GC |
3305 | /* Setup XPS mapping */ |
3306 | if (txq_number > 1) | |
3307 | cpu = txq->id % num_present_cpus(); | |
3308 | else | |
3309 | cpu = pp->rxq_def % num_present_cpus(); | |
3310 | cpumask_set_cpu(cpu, &txq->affinity_mask); | |
3311 | netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); | |
3312 | ||
c5aff182 TP |
3313 | return 0; |
3314 | } | |
3315 | ||
4a188a63 JZ |
3316 | static void mvneta_txq_hw_init(struct mvneta_port *pp, |
3317 | struct mvneta_tx_queue *txq) | |
3318 | { | |
3319 | /* Set maximum bandwidth for enabled TXQs */ | |
3320 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
3321 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
3322 | ||
3323 | /* Set Tx descriptors queue starting address */ | |
3324 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
3325 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
3326 | ||
3327 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
3328 | } | |
3329 | ||
3330 | /* Create and initialize a tx queue */ | |
3331 | static int mvneta_txq_init(struct mvneta_port *pp, | |
3332 | struct mvneta_tx_queue *txq) | |
3333 | { | |
3334 | int ret; | |
3335 | ||
3336 | ret = mvneta_txq_sw_init(pp, txq); | |
3337 | if (ret < 0) | |
3338 | return ret; | |
3339 | ||
3340 | mvneta_txq_hw_init(pp, txq); | |
3341 | ||
3342 | return 0; | |
3343 | } | |
3344 | ||
c5aff182 | 3345 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ |
4a188a63 JZ |
3346 | static void mvneta_txq_sw_deinit(struct mvneta_port *pp, |
3347 | struct mvneta_tx_queue *txq) | |
c5aff182 | 3348 | { |
a29b6235 MW |
3349 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
3350 | ||
9e58c8b4 | 3351 | kfree(txq->buf); |
c5aff182 | 3352 | |
2adb719d EG |
3353 | if (txq->tso_hdrs) |
3354 | dma_free_coherent(pp->dev->dev.parent, | |
3355 | txq->size * TSO_HEADER_SIZE, | |
3356 | txq->tso_hdrs, txq->tso_hdrs_phys); | |
c5aff182 TP |
3357 | if (txq->descs) |
3358 | dma_free_coherent(pp->dev->dev.parent, | |
3359 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3360 | txq->descs, txq->descs_phys); | |
3361 | ||
a29b6235 MW |
3362 | netdev_tx_reset_queue(nq); |
3363 | ||
c5aff182 TP |
3364 | txq->descs = NULL; |
3365 | txq->last_desc = 0; | |
3366 | txq->next_desc_to_proc = 0; | |
3367 | txq->descs_phys = 0; | |
4a188a63 | 3368 | } |
c5aff182 | 3369 | |
4a188a63 JZ |
3370 | static void mvneta_txq_hw_deinit(struct mvneta_port *pp, |
3371 | struct mvneta_tx_queue *txq) | |
3372 | { | |
c5aff182 TP |
3373 | /* Set minimum bandwidth for disabled TXQs */ |
3374 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
3375 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
3376 | ||
3377 | /* Set Tx descriptors queue starting address and size */ | |
3378 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
3379 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
3380 | } | |
3381 | ||
4a188a63 JZ |
3382 | static void mvneta_txq_deinit(struct mvneta_port *pp, |
3383 | struct mvneta_tx_queue *txq) | |
3384 | { | |
3385 | mvneta_txq_sw_deinit(pp, txq); | |
3386 | mvneta_txq_hw_deinit(pp, txq); | |
3387 | } | |
3388 | ||
c5aff182 TP |
3389 | /* Cleanup all Tx queues */ |
3390 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
3391 | { | |
3392 | int queue; | |
3393 | ||
3394 | for (queue = 0; queue < txq_number; queue++) | |
3395 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
3396 | } | |
3397 | ||
3398 | /* Cleanup all Rx queues */ | |
3399 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
3400 | { | |
2dcf75e2 GC |
3401 | int queue; |
3402 | ||
ca5902a6 | 3403 | for (queue = 0; queue < rxq_number; queue++) |
2dcf75e2 | 3404 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); |
c5aff182 TP |
3405 | } |
3406 | ||
3407 | ||
3408 | /* Init all Rx queues */ | |
3409 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
3410 | { | |
2dcf75e2 GC |
3411 | int queue; |
3412 | ||
3413 | for (queue = 0; queue < rxq_number; queue++) { | |
3414 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
3415 | ||
3416 | if (err) { | |
3417 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
3418 | __func__, queue); | |
3419 | mvneta_cleanup_rxqs(pp); | |
3420 | return err; | |
3421 | } | |
c5aff182 TP |
3422 | } |
3423 | ||
3424 | return 0; | |
3425 | } | |
3426 | ||
3427 | /* Init all tx queues */ | |
3428 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
3429 | { | |
3430 | int queue; | |
3431 | ||
3432 | for (queue = 0; queue < txq_number; queue++) { | |
3433 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
3434 | if (err) { | |
3435 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
3436 | __func__, queue); | |
3437 | mvneta_cleanup_txqs(pp); | |
3438 | return err; | |
3439 | } | |
3440 | } | |
3441 | ||
3442 | return 0; | |
3443 | } | |
3444 | ||
031b922b MB |
3445 | static int mvneta_comphy_init(struct mvneta_port *pp) |
3446 | { | |
3447 | int ret; | |
3448 | ||
3449 | if (!pp->comphy) | |
3450 | return 0; | |
3451 | ||
3452 | ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, | |
3453 | pp->phy_interface); | |
3454 | if (ret) | |
3455 | return ret; | |
3456 | ||
3457 | return phy_power_on(pp->comphy); | |
3458 | } | |
3459 | ||
c5aff182 TP |
3460 | static void mvneta_start_dev(struct mvneta_port *pp) |
3461 | { | |
6b125d63 | 3462 | int cpu; |
12bb03b4 | 3463 | |
031b922b | 3464 | WARN_ON(mvneta_comphy_init(pp)); |
a10c1c81 | 3465 | |
c5aff182 TP |
3466 | mvneta_max_rx_size_set(pp, pp->pkt_size); |
3467 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); | |
3468 | ||
3469 | /* start the Rx/Tx activity */ | |
3470 | mvneta_port_enable(pp); | |
3471 | ||
2636ac3c MW |
3472 | if (!pp->neta_armada3700) { |
3473 | /* Enable polling on the port */ | |
3474 | for_each_online_cpu(cpu) { | |
3475 | struct mvneta_pcpu_port *port = | |
3476 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 3477 | |
2636ac3c MW |
3478 | napi_enable(&port->napi); |
3479 | } | |
3480 | } else { | |
3481 | napi_enable(&pp->napi); | |
12bb03b4 | 3482 | } |
c5aff182 | 3483 | |
2dcf75e2 | 3484 | /* Unmask interrupts. It has to be done from each CPU */ |
6b125d63 GC |
3485 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); |
3486 | ||
898b2970 SS |
3487 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
3488 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 3489 | MVNETA_CAUSE_LINK_CHANGE); |
c5aff182 | 3490 | |
503f9aa9 | 3491 | phylink_start(pp->phylink); |
c5aff182 TP |
3492 | netif_tx_start_all_queues(pp->dev); |
3493 | } | |
3494 | ||
3495 | static void mvneta_stop_dev(struct mvneta_port *pp) | |
3496 | { | |
12bb03b4 MR |
3497 | unsigned int cpu; |
3498 | ||
503f9aa9 | 3499 | phylink_stop(pp->phylink); |
c5aff182 | 3500 | |
2636ac3c MW |
3501 | if (!pp->neta_armada3700) { |
3502 | for_each_online_cpu(cpu) { | |
3503 | struct mvneta_pcpu_port *port = | |
3504 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 3505 | |
2636ac3c MW |
3506 | napi_disable(&port->napi); |
3507 | } | |
3508 | } else { | |
3509 | napi_disable(&pp->napi); | |
12bb03b4 | 3510 | } |
c5aff182 TP |
3511 | |
3512 | netif_carrier_off(pp->dev); | |
3513 | ||
3514 | mvneta_port_down(pp); | |
3515 | netif_tx_stop_all_queues(pp->dev); | |
3516 | ||
3517 | /* Stop the port activity */ | |
3518 | mvneta_port_disable(pp); | |
3519 | ||
3520 | /* Clear all ethernet port interrupts */ | |
db488c10 | 3521 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
3522 | |
3523 | /* Mask all ethernet port interrupts */ | |
db488c10 | 3524 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
3525 | |
3526 | mvneta_tx_reset(pp); | |
3527 | mvneta_rx_reset(pp); | |
a10c1c81 RK |
3528 | |
3529 | WARN_ON(phy_power_off(pp->comphy)); | |
c5aff182 TP |
3530 | } |
3531 | ||
db5dd0db MW |
3532 | static void mvneta_percpu_enable(void *arg) |
3533 | { | |
3534 | struct mvneta_port *pp = arg; | |
3535 | ||
3536 | enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); | |
3537 | } | |
3538 | ||
3539 | static void mvneta_percpu_disable(void *arg) | |
3540 | { | |
3541 | struct mvneta_port *pp = arg; | |
3542 | ||
3543 | disable_percpu_irq(pp->dev->irq); | |
3544 | } | |
3545 | ||
c5aff182 TP |
3546 | /* Change the device mtu */ |
3547 | static int mvneta_change_mtu(struct net_device *dev, int mtu) | |
3548 | { | |
3549 | struct mvneta_port *pp = netdev_priv(dev); | |
3550 | int ret; | |
3551 | ||
5777987e JW |
3552 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { |
3553 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", | |
3554 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); | |
3555 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); | |
3556 | } | |
c5aff182 | 3557 | |
0db51da7 LB |
3558 | if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { |
3559 | netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); | |
3560 | return -EINVAL; | |
3561 | } | |
3562 | ||
c5aff182 TP |
3563 | dev->mtu = mtu; |
3564 | ||
b65657fc | 3565 | if (!netif_running(dev)) { |
dc35a10f MW |
3566 | if (pp->bm_priv) |
3567 | mvneta_bm_update_mtu(pp, mtu); | |
3568 | ||
b65657fc | 3569 | netdev_update_features(dev); |
c5aff182 | 3570 | return 0; |
b65657fc | 3571 | } |
c5aff182 | 3572 | |
6a20c175 | 3573 | /* The interface is running, so we have to force a |
a92dbd96 | 3574 | * reallocation of the queues |
c5aff182 TP |
3575 | */ |
3576 | mvneta_stop_dev(pp); | |
db5dd0db | 3577 | on_each_cpu(mvneta_percpu_disable, pp, true); |
c5aff182 TP |
3578 | |
3579 | mvneta_cleanup_txqs(pp); | |
3580 | mvneta_cleanup_rxqs(pp); | |
3581 | ||
dc35a10f MW |
3582 | if (pp->bm_priv) |
3583 | mvneta_bm_update_mtu(pp, mtu); | |
3584 | ||
a92dbd96 | 3585 | pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); |
c5aff182 TP |
3586 | |
3587 | ret = mvneta_setup_rxqs(pp); | |
3588 | if (ret) { | |
a92dbd96 | 3589 | netdev_err(dev, "unable to setup rxqs after MTU change\n"); |
c5aff182 TP |
3590 | return ret; |
3591 | } | |
3592 | ||
a92dbd96 EG |
3593 | ret = mvneta_setup_txqs(pp); |
3594 | if (ret) { | |
3595 | netdev_err(dev, "unable to setup txqs after MTU change\n"); | |
3596 | return ret; | |
3597 | } | |
c5aff182 | 3598 | |
db5dd0db | 3599 | on_each_cpu(mvneta_percpu_enable, pp, true); |
c5aff182 | 3600 | mvneta_start_dev(pp); |
c5aff182 | 3601 | |
b65657fc SG |
3602 | netdev_update_features(dev); |
3603 | ||
c5aff182 TP |
3604 | return 0; |
3605 | } | |
3606 | ||
b65657fc SG |
3607 | static netdev_features_t mvneta_fix_features(struct net_device *dev, |
3608 | netdev_features_t features) | |
3609 | { | |
3610 | struct mvneta_port *pp = netdev_priv(dev); | |
3611 | ||
3612 | if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { | |
3613 | features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); | |
3614 | netdev_info(dev, | |
3615 | "Disable IP checksum for MTU greater than %dB\n", | |
3616 | pp->tx_csum_limit); | |
3617 | } | |
3618 | ||
3619 | return features; | |
3620 | } | |
3621 | ||
8cc3e439 TP |
3622 | /* Get mac address */ |
3623 | static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) | |
3624 | { | |
3625 | u32 mac_addr_l, mac_addr_h; | |
3626 | ||
3627 | mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); | |
3628 | mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); | |
3629 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
3630 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
3631 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
3632 | addr[3] = mac_addr_h & 0xFF; | |
3633 | addr[4] = (mac_addr_l >> 8) & 0xFF; | |
3634 | addr[5] = mac_addr_l & 0xFF; | |
3635 | } | |
3636 | ||
c5aff182 TP |
3637 | /* Handle setting mac address */ |
3638 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) | |
3639 | { | |
3640 | struct mvneta_port *pp = netdev_priv(dev); | |
e68de360 EG |
3641 | struct sockaddr *sockaddr = addr; |
3642 | int ret; | |
c5aff182 | 3643 | |
e68de360 EG |
3644 | ret = eth_prepare_mac_addr_change(dev, addr); |
3645 | if (ret < 0) | |
3646 | return ret; | |
c5aff182 TP |
3647 | /* Remove previous address table entry */ |
3648 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); | |
3649 | ||
3650 | /* Set new addr in hw */ | |
90b74c01 | 3651 | mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); |
c5aff182 | 3652 | |
e68de360 | 3653 | eth_commit_mac_addr_change(dev, addr); |
c5aff182 TP |
3654 | return 0; |
3655 | } | |
3656 | ||
44cc27e4 IC |
3657 | static void mvneta_validate(struct phylink_config *config, |
3658 | unsigned long *supported, | |
503f9aa9 RK |
3659 | struct phylink_link_state *state) |
3660 | { | |
44cc27e4 | 3661 | struct net_device *ndev = to_net_dev(config->dev); |
a10c1c81 | 3662 | struct mvneta_port *pp = netdev_priv(ndev); |
503f9aa9 RK |
3663 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; |
3664 | ||
22f4bf8a | 3665 | /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ |
503f9aa9 RK |
3666 | if (state->interface != PHY_INTERFACE_MODE_NA && |
3667 | state->interface != PHY_INTERFACE_MODE_QSGMII && | |
3668 | state->interface != PHY_INTERFACE_MODE_SGMII && | |
22f4bf8a | 3669 | !phy_interface_mode_is_8023z(state->interface) && |
503f9aa9 RK |
3670 | !phy_interface_mode_is_rgmii(state->interface)) { |
3671 | bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
3672 | return; | |
3673 | } | |
3674 | ||
3675 | /* Allow all the expected bits */ | |
3676 | phylink_set(mask, Autoneg); | |
3677 | phylink_set_port_modes(mask); | |
3678 | ||
4932a918 RK |
3679 | /* Asymmetric pause is unsupported */ |
3680 | phylink_set(mask, Pause); | |
da58a931 | 3681 | |
83e65df6 | 3682 | /* Half-duplex at speeds higher than 100Mbit is unsupported */ |
a10c1c81 RK |
3683 | if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { |
3684 | phylink_set(mask, 1000baseT_Full); | |
3685 | phylink_set(mask, 1000baseX_Full); | |
3686 | } | |
3687 | if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { | |
eda3d1b0 | 3688 | phylink_set(mask, 2500baseT_Full); |
a10c1c81 RK |
3689 | phylink_set(mask, 2500baseX_Full); |
3690 | } | |
22f4bf8a RK |
3691 | |
3692 | if (!phy_interface_mode_is_8023z(state->interface)) { | |
3693 | /* 10M and 100M are only supported in non-802.3z mode */ | |
3694 | phylink_set(mask, 10baseT_Half); | |
3695 | phylink_set(mask, 10baseT_Full); | |
3696 | phylink_set(mask, 100baseT_Half); | |
3697 | phylink_set(mask, 100baseT_Full); | |
3698 | } | |
503f9aa9 RK |
3699 | |
3700 | bitmap_and(supported, supported, mask, | |
3701 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
3702 | bitmap_and(state->advertising, state->advertising, mask, | |
3703 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
a10c1c81 RK |
3704 | |
3705 | /* We can only operate at 2500BaseX or 1000BaseX. If requested | |
3706 | * to advertise both, only report advertising at 2500BaseX. | |
3707 | */ | |
3708 | phylink_helper_basex_speed(state); | |
503f9aa9 RK |
3709 | } |
3710 | ||
d46b7e4f RK |
3711 | static void mvneta_mac_pcs_get_state(struct phylink_config *config, |
3712 | struct phylink_link_state *state) | |
c5aff182 | 3713 | { |
44cc27e4 | 3714 | struct net_device *ndev = to_net_dev(config->dev); |
c5aff182 | 3715 | struct mvneta_port *pp = netdev_priv(ndev); |
503f9aa9 | 3716 | u32 gmac_stat; |
c5aff182 | 3717 | |
503f9aa9 | 3718 | gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); |
c5aff182 | 3719 | |
503f9aa9 | 3720 | if (gmac_stat & MVNETA_GMAC_SPEED_1000) |
a10c1c81 RK |
3721 | state->speed = |
3722 | state->interface == PHY_INTERFACE_MODE_2500BASEX ? | |
3723 | SPEED_2500 : SPEED_1000; | |
503f9aa9 RK |
3724 | else if (gmac_stat & MVNETA_GMAC_SPEED_100) |
3725 | state->speed = SPEED_100; | |
3726 | else | |
3727 | state->speed = SPEED_10; | |
c5aff182 | 3728 | |
503f9aa9 RK |
3729 | state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); |
3730 | state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); | |
3731 | state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); | |
c5aff182 | 3732 | |
503f9aa9 | 3733 | state->pause = 0; |
4932a918 RK |
3734 | if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) |
3735 | state->pause |= MLO_PAUSE_RX; | |
3736 | if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) | |
3737 | state->pause |= MLO_PAUSE_TX; | |
503f9aa9 RK |
3738 | } |
3739 | ||
44cc27e4 | 3740 | static void mvneta_mac_an_restart(struct phylink_config *config) |
22f4bf8a | 3741 | { |
44cc27e4 | 3742 | struct net_device *ndev = to_net_dev(config->dev); |
22f4bf8a RK |
3743 | struct mvneta_port *pp = netdev_priv(ndev); |
3744 | u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
3745 | ||
3746 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3747 | gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); | |
3748 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3749 | gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); | |
3750 | } | |
3751 | ||
44cc27e4 IC |
3752 | static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, |
3753 | const struct phylink_link_state *state) | |
503f9aa9 | 3754 | { |
44cc27e4 | 3755 | struct net_device *ndev = to_net_dev(config->dev); |
503f9aa9 | 3756 | struct mvneta_port *pp = netdev_priv(ndev); |
22f4bf8a | 3757 | u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); |
503f9aa9 | 3758 | u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
da58a931 | 3759 | u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); |
503f9aa9 RK |
3760 | u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); |
3761 | u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
3762 | ||
22f4bf8a | 3763 | new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; |
32699954 RK |
3764 | new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | |
3765 | MVNETA_GMAC2_PORT_RESET); | |
da58a931 | 3766 | new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); |
503f9aa9 RK |
3767 | new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; |
3768 | new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | | |
3769 | MVNETA_GMAC_INBAND_RESTART_AN | | |
3770 | MVNETA_GMAC_CONFIG_MII_SPEED | | |
3771 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
3772 | MVNETA_GMAC_AN_SPEED_EN | | |
22f4bf8a RK |
3773 | MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | |
3774 | MVNETA_GMAC_CONFIG_FLOW_CTRL | | |
503f9aa9 RK |
3775 | MVNETA_GMAC_AN_FLOW_CTRL_EN | |
3776 | MVNETA_GMAC_CONFIG_FULL_DUPLEX | | |
3777 | MVNETA_GMAC_AN_DUPLEX_EN); | |
3778 | ||
32699954 RK |
3779 | /* Even though it might look weird, when we're configured in |
3780 | * SGMII or QSGMII mode, the RGMII bit needs to be set. | |
3781 | */ | |
3782 | new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; | |
3783 | ||
3784 | if (state->interface == PHY_INTERFACE_MODE_QSGMII || | |
22f4bf8a RK |
3785 | state->interface == PHY_INTERFACE_MODE_SGMII || |
3786 | phy_interface_mode_is_8023z(state->interface)) | |
32699954 RK |
3787 | new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; |
3788 | ||
4932a918 RK |
3789 | if (phylink_test(state->advertising, Pause)) |
3790 | new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; | |
3791 | if (state->pause & MLO_PAUSE_TXRX_MASK) | |
3792 | new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; | |
3793 | ||
503f9aa9 RK |
3794 | if (!phylink_autoneg_inband(mode)) { |
3795 | /* Phy or fixed speed */ | |
3796 | if (state->duplex) | |
3797 | new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
3798 | ||
da58a931 | 3799 | if (state->speed == SPEED_1000 || state->speed == SPEED_2500) |
503f9aa9 RK |
3800 | new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; |
3801 | else if (state->speed == SPEED_100) | |
3802 | new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; | |
22f4bf8a | 3803 | } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { |
503f9aa9 RK |
3804 | /* SGMII mode receives the state from the PHY */ |
3805 | new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; | |
3806 | new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
3807 | new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | | |
3808 | MVNETA_GMAC_FORCE_LINK_PASS)) | | |
3809 | MVNETA_GMAC_INBAND_AN_ENABLE | | |
3810 | MVNETA_GMAC_AN_SPEED_EN | | |
3811 | MVNETA_GMAC_AN_DUPLEX_EN; | |
22f4bf8a RK |
3812 | } else { |
3813 | /* 802.3z negotiation - only 1000base-X */ | |
3814 | new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; | |
3815 | new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
3816 | new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | | |
3817 | MVNETA_GMAC_FORCE_LINK_PASS)) | | |
3818 | MVNETA_GMAC_INBAND_AN_ENABLE | | |
3819 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
3820 | /* The MAC only supports FD mode */ | |
3821 | MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
4932a918 RK |
3822 | |
3823 | if (state->pause & MLO_PAUSE_AN && state->an_enabled) | |
3824 | new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; | |
503f9aa9 | 3825 | } |
c5aff182 | 3826 | |
503f9aa9 RK |
3827 | /* Armada 370 documentation says we can only change the port mode |
3828 | * and in-band enable when the link is down, so force it down | |
3829 | * while making these changes. We also do this for GMAC_CTRL2 */ | |
22f4bf8a RK |
3830 | if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || |
3831 | (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || | |
503f9aa9 RK |
3832 | (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { |
3833 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3834 | (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | | |
3835 | MVNETA_GMAC_FORCE_LINK_DOWN); | |
fc548b99 | 3836 | } |
503f9aa9 | 3837 | |
a10c1c81 | 3838 | |
da58a931 MC |
3839 | /* When at 2.5G, the link partner can send frames with shortened |
3840 | * preambles. | |
3841 | */ | |
3842 | if (state->speed == SPEED_2500) | |
3843 | new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; | |
3844 | ||
031b922b | 3845 | if (pp->comphy && pp->phy_interface != state->interface && |
a10c1c81 RK |
3846 | (state->interface == PHY_INTERFACE_MODE_SGMII || |
3847 | state->interface == PHY_INTERFACE_MODE_1000BASEX || | |
031b922b MB |
3848 | state->interface == PHY_INTERFACE_MODE_2500BASEX)) { |
3849 | pp->phy_interface = state->interface; | |
3850 | ||
3851 | WARN_ON(phy_power_off(pp->comphy)); | |
3852 | WARN_ON(mvneta_comphy_init(pp)); | |
3853 | } | |
a10c1c81 | 3854 | |
22f4bf8a RK |
3855 | if (new_ctrl0 != gmac_ctrl0) |
3856 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); | |
503f9aa9 RK |
3857 | if (new_ctrl2 != gmac_ctrl2) |
3858 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); | |
da58a931 MC |
3859 | if (new_ctrl4 != gmac_ctrl4) |
3860 | mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); | |
503f9aa9 RK |
3861 | if (new_clk != gmac_clk) |
3862 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); | |
3863 | if (new_an != gmac_an) | |
3864 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); | |
32699954 RK |
3865 | |
3866 | if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { | |
3867 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
3868 | MVNETA_GMAC2_PORT_RESET) != 0) | |
3869 | continue; | |
3870 | } | |
fc548b99 | 3871 | } |
c5aff182 | 3872 | |
6d81f451 RK |
3873 | static void mvneta_set_eee(struct mvneta_port *pp, bool enable) |
3874 | { | |
3875 | u32 lpi_ctl1; | |
3876 | ||
3877 | lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); | |
3878 | if (enable) | |
3879 | lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; | |
3880 | else | |
3881 | lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; | |
3882 | mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); | |
3883 | } | |
3884 | ||
44cc27e4 IC |
3885 | static void mvneta_mac_link_down(struct phylink_config *config, |
3886 | unsigned int mode, phy_interface_t interface) | |
fc548b99 | 3887 | { |
44cc27e4 | 3888 | struct net_device *ndev = to_net_dev(config->dev); |
fc548b99 RK |
3889 | struct mvneta_port *pp = netdev_priv(ndev); |
3890 | u32 val; | |
3891 | ||
503f9aa9 RK |
3892 | mvneta_port_down(pp); |
3893 | ||
3894 | if (!phylink_autoneg_inband(mode)) { | |
fc548b99 RK |
3895 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
3896 | val &= ~MVNETA_GMAC_FORCE_LINK_PASS; | |
3897 | val |= MVNETA_GMAC_FORCE_LINK_DOWN; | |
3898 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
3899 | } | |
6d81f451 RK |
3900 | |
3901 | pp->eee_active = false; | |
3902 | mvneta_set_eee(pp, false); | |
fc548b99 RK |
3903 | } |
3904 | ||
44cc27e4 | 3905 | static void mvneta_mac_link_up(struct phylink_config *config, unsigned int mode, |
c6ab3008 | 3906 | phy_interface_t interface, |
503f9aa9 | 3907 | struct phy_device *phy) |
fc548b99 | 3908 | { |
44cc27e4 | 3909 | struct net_device *ndev = to_net_dev(config->dev); |
fc548b99 RK |
3910 | struct mvneta_port *pp = netdev_priv(ndev); |
3911 | u32 val; | |
3912 | ||
503f9aa9 | 3913 | if (!phylink_autoneg_inband(mode)) { |
fc548b99 RK |
3914 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
3915 | val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; | |
3916 | val |= MVNETA_GMAC_FORCE_LINK_PASS; | |
3917 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
c5aff182 TP |
3918 | } |
3919 | ||
fc548b99 | 3920 | mvneta_port_up(pp); |
6d81f451 RK |
3921 | |
3922 | if (phy && pp->eee_enabled) { | |
3923 | pp->eee_active = phy_init_eee(phy, 0) >= 0; | |
3924 | mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); | |
3925 | } | |
fc548b99 RK |
3926 | } |
3927 | ||
503f9aa9 RK |
3928 | static const struct phylink_mac_ops mvneta_phylink_ops = { |
3929 | .validate = mvneta_validate, | |
d46b7e4f | 3930 | .mac_pcs_get_state = mvneta_mac_pcs_get_state, |
22f4bf8a | 3931 | .mac_an_restart = mvneta_mac_an_restart, |
503f9aa9 RK |
3932 | .mac_config = mvneta_mac_config, |
3933 | .mac_link_down = mvneta_mac_link_down, | |
3934 | .mac_link_up = mvneta_mac_link_up, | |
3935 | }; | |
c5aff182 TP |
3936 | |
3937 | static int mvneta_mdio_probe(struct mvneta_port *pp) | |
3938 | { | |
82960fff | 3939 | struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; |
503f9aa9 | 3940 | int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); |
c5aff182 | 3941 | |
503f9aa9 RK |
3942 | if (err) |
3943 | netdev_err(pp->dev, "could not attach PHY: %d\n", err); | |
c5aff182 | 3944 | |
503f9aa9 | 3945 | phylink_ethtool_get_wol(pp->phylink, &wol); |
82960fff JZ |
3946 | device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); |
3947 | ||
503f9aa9 | 3948 | return err; |
c5aff182 TP |
3949 | } |
3950 | ||
3951 | static void mvneta_mdio_remove(struct mvneta_port *pp) | |
3952 | { | |
503f9aa9 | 3953 | phylink_disconnect_phy(pp->phylink); |
c5aff182 TP |
3954 | } |
3955 | ||
120cfa50 GC |
3956 | /* Electing a CPU must be done in an atomic way: it should be done |
3957 | * after or before the removal/insertion of a CPU and this function is | |
3958 | * not reentrant. | |
3959 | */ | |
f8642885 MR |
3960 | static void mvneta_percpu_elect(struct mvneta_port *pp) |
3961 | { | |
cad5d847 GC |
3962 | int elected_cpu = 0, max_cpu, cpu, i = 0; |
3963 | ||
3964 | /* Use the cpu associated to the rxq when it is online, in all | |
3965 | * the other cases, use the cpu 0 which can't be offline. | |
3966 | */ | |
3967 | if (cpu_online(pp->rxq_def)) | |
3968 | elected_cpu = pp->rxq_def; | |
f8642885 | 3969 | |
2dcf75e2 | 3970 | max_cpu = num_present_cpus(); |
f8642885 MR |
3971 | |
3972 | for_each_online_cpu(cpu) { | |
2dcf75e2 GC |
3973 | int rxq_map = 0, txq_map = 0; |
3974 | int rxq; | |
3975 | ||
3976 | for (rxq = 0; rxq < rxq_number; rxq++) | |
3977 | if ((rxq % max_cpu) == cpu) | |
3978 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
3979 | ||
cad5d847 | 3980 | if (cpu == elected_cpu) |
50bf8cb6 GC |
3981 | /* Map the default receive queue queue to the |
3982 | * elected CPU | |
f8642885 | 3983 | */ |
2dcf75e2 | 3984 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); |
50bf8cb6 GC |
3985 | |
3986 | /* We update the TX queue map only if we have one | |
3987 | * queue. In this case we associate the TX queue to | |
3988 | * the CPU bound to the default RX queue | |
3989 | */ | |
3990 | if (txq_number == 1) | |
cad5d847 | 3991 | txq_map = (cpu == elected_cpu) ? |
50bf8cb6 GC |
3992 | MVNETA_CPU_TXQ_ACCESS(1) : 0; |
3993 | else | |
3994 | txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & | |
3995 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
3996 | ||
2dcf75e2 GC |
3997 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); |
3998 | ||
3999 | /* Update the interrupt mask on each CPU according the | |
4000 | * new mapping | |
4001 | */ | |
4002 | smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, | |
4003 | pp, true); | |
f8642885 | 4004 | i++; |
2dcf75e2 | 4005 | |
f8642885 MR |
4006 | } |
4007 | }; | |
4008 | ||
84a3f4db | 4009 | static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) |
f8642885 | 4010 | { |
84a3f4db SAS |
4011 | int other_cpu; |
4012 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
4013 | node_online); | |
f8642885 MR |
4014 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
4015 | ||
f8642885 | 4016 | |
84a3f4db SAS |
4017 | spin_lock(&pp->lock); |
4018 | /* | |
4019 | * Configuring the driver for a new CPU while the driver is | |
4020 | * stopping is racy, so just avoid it. | |
4021 | */ | |
4022 | if (pp->is_stopped) { | |
4023 | spin_unlock(&pp->lock); | |
4024 | return 0; | |
4025 | } | |
4026 | netif_tx_stop_all_queues(pp->dev); | |
f8642885 | 4027 | |
84a3f4db SAS |
4028 | /* |
4029 | * We have to synchronise on tha napi of each CPU except the one | |
4030 | * just being woken up | |
4031 | */ | |
4032 | for_each_online_cpu(other_cpu) { | |
4033 | if (other_cpu != cpu) { | |
4034 | struct mvneta_pcpu_port *other_port = | |
4035 | per_cpu_ptr(pp->ports, other_cpu); | |
4036 | ||
4037 | napi_synchronize(&other_port->napi); | |
f8642885 | 4038 | } |
84a3f4db | 4039 | } |
f8642885 | 4040 | |
84a3f4db SAS |
4041 | /* Mask all ethernet port interrupts */ |
4042 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); | |
4043 | napi_enable(&port->napi); | |
f8642885 | 4044 | |
84a3f4db SAS |
4045 | /* |
4046 | * Enable per-CPU interrupts on the CPU that is | |
4047 | * brought up. | |
4048 | */ | |
4049 | mvneta_percpu_enable(pp); | |
2dcf75e2 | 4050 | |
84a3f4db SAS |
4051 | /* |
4052 | * Enable per-CPU interrupt on the one CPU we care | |
4053 | * about. | |
4054 | */ | |
4055 | mvneta_percpu_elect(pp); | |
2dcf75e2 | 4056 | |
84a3f4db SAS |
4057 | /* Unmask all ethernet port interrupts */ |
4058 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
4059 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
4060 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 4061 | MVNETA_CAUSE_LINK_CHANGE); |
84a3f4db SAS |
4062 | netif_tx_start_all_queues(pp->dev); |
4063 | spin_unlock(&pp->lock); | |
4064 | return 0; | |
4065 | } | |
f8642885 | 4066 | |
84a3f4db SAS |
4067 | static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) |
4068 | { | |
4069 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
4070 | node_online); | |
4071 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
f8642885 | 4072 | |
84a3f4db SAS |
4073 | /* |
4074 | * Thanks to this lock we are sure that any pending cpu election is | |
4075 | * done. | |
4076 | */ | |
4077 | spin_lock(&pp->lock); | |
4078 | /* Mask all ethernet port interrupts */ | |
4079 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); | |
4080 | spin_unlock(&pp->lock); | |
f8642885 | 4081 | |
84a3f4db SAS |
4082 | napi_synchronize(&port->napi); |
4083 | napi_disable(&port->napi); | |
4084 | /* Disable per-CPU interrupts on the CPU that is brought down. */ | |
4085 | mvneta_percpu_disable(pp); | |
4086 | return 0; | |
4087 | } | |
4088 | ||
4089 | static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) | |
4090 | { | |
4091 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
4092 | node_dead); | |
4093 | ||
4094 | /* Check if a new CPU must be elected now this on is down */ | |
4095 | spin_lock(&pp->lock); | |
4096 | mvneta_percpu_elect(pp); | |
4097 | spin_unlock(&pp->lock); | |
4098 | /* Unmask all ethernet port interrupts */ | |
4099 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
4100 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
4101 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 4102 | MVNETA_CAUSE_LINK_CHANGE); |
84a3f4db SAS |
4103 | netif_tx_start_all_queues(pp->dev); |
4104 | return 0; | |
f8642885 MR |
4105 | } |
4106 | ||
c5aff182 TP |
4107 | static int mvneta_open(struct net_device *dev) |
4108 | { | |
4109 | struct mvneta_port *pp = netdev_priv(dev); | |
6b125d63 | 4110 | int ret; |
c5aff182 | 4111 | |
c5aff182 TP |
4112 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
4113 | ||
4114 | ret = mvneta_setup_rxqs(pp); | |
4115 | if (ret) | |
4116 | return ret; | |
4117 | ||
4118 | ret = mvneta_setup_txqs(pp); | |
4119 | if (ret) | |
4120 | goto err_cleanup_rxqs; | |
4121 | ||
4122 | /* Connect to port interrupt line */ | |
2636ac3c MW |
4123 | if (pp->neta_armada3700) |
4124 | ret = request_irq(pp->dev->irq, mvneta_isr, 0, | |
4125 | dev->name, pp); | |
4126 | else | |
4127 | ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, | |
4128 | dev->name, pp->ports); | |
c5aff182 TP |
4129 | if (ret) { |
4130 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); | |
4131 | goto err_cleanup_txqs; | |
4132 | } | |
4133 | ||
2636ac3c MW |
4134 | if (!pp->neta_armada3700) { |
4135 | /* Enable per-CPU interrupt on all the CPU to handle our RX | |
4136 | * queue interrupts | |
4137 | */ | |
4138 | on_each_cpu(mvneta_percpu_enable, pp, true); | |
2dcf75e2 | 4139 | |
2636ac3c MW |
4140 | pp->is_stopped = false; |
4141 | /* Register a CPU notifier to handle the case where our CPU | |
4142 | * might be taken offline. | |
4143 | */ | |
4144 | ret = cpuhp_state_add_instance_nocalls(online_hpstate, | |
4145 | &pp->node_online); | |
4146 | if (ret) | |
4147 | goto err_free_irq; | |
84a3f4db | 4148 | |
2636ac3c MW |
4149 | ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, |
4150 | &pp->node_dead); | |
4151 | if (ret) | |
4152 | goto err_free_online_hp; | |
4153 | } | |
f8642885 | 4154 | |
c5aff182 TP |
4155 | ret = mvneta_mdio_probe(pp); |
4156 | if (ret < 0) { | |
4157 | netdev_err(dev, "cannot probe MDIO bus\n"); | |
84a3f4db | 4158 | goto err_free_dead_hp; |
c5aff182 TP |
4159 | } |
4160 | ||
4161 | mvneta_start_dev(pp); | |
4162 | ||
4163 | return 0; | |
4164 | ||
84a3f4db | 4165 | err_free_dead_hp: |
2636ac3c MW |
4166 | if (!pp->neta_armada3700) |
4167 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
4168 | &pp->node_dead); | |
84a3f4db | 4169 | err_free_online_hp: |
2636ac3c MW |
4170 | if (!pp->neta_armada3700) |
4171 | cpuhp_state_remove_instance_nocalls(online_hpstate, | |
4172 | &pp->node_online); | |
c5aff182 | 4173 | err_free_irq: |
2636ac3c MW |
4174 | if (pp->neta_armada3700) { |
4175 | free_irq(pp->dev->irq, pp); | |
4176 | } else { | |
4177 | on_each_cpu(mvneta_percpu_disable, pp, true); | |
4178 | free_percpu_irq(pp->dev->irq, pp->ports); | |
4179 | } | |
c5aff182 TP |
4180 | err_cleanup_txqs: |
4181 | mvneta_cleanup_txqs(pp); | |
4182 | err_cleanup_rxqs: | |
4183 | mvneta_cleanup_rxqs(pp); | |
4184 | return ret; | |
4185 | } | |
4186 | ||
4187 | /* Stop the port, free port interrupt line */ | |
4188 | static int mvneta_stop(struct net_device *dev) | |
4189 | { | |
4190 | struct mvneta_port *pp = netdev_priv(dev); | |
4191 | ||
2636ac3c MW |
4192 | if (!pp->neta_armada3700) { |
4193 | /* Inform that we are stopping so we don't want to setup the | |
4194 | * driver for new CPUs in the notifiers. The code of the | |
4195 | * notifier for CPU online is protected by the same spinlock, | |
4196 | * so when we get the lock, the notifer work is done. | |
4197 | */ | |
4198 | spin_lock(&pp->lock); | |
4199 | pp->is_stopped = true; | |
4200 | spin_unlock(&pp->lock); | |
1c2722a9 | 4201 | |
2636ac3c MW |
4202 | mvneta_stop_dev(pp); |
4203 | mvneta_mdio_remove(pp); | |
84a3f4db | 4204 | |
d26aac2d DC |
4205 | cpuhp_state_remove_instance_nocalls(online_hpstate, |
4206 | &pp->node_online); | |
4207 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
4208 | &pp->node_dead); | |
2636ac3c MW |
4209 | on_each_cpu(mvneta_percpu_disable, pp, true); |
4210 | free_percpu_irq(dev->irq, pp->ports); | |
4211 | } else { | |
4212 | mvneta_stop_dev(pp); | |
4213 | mvneta_mdio_remove(pp); | |
4214 | free_irq(dev->irq, pp); | |
4215 | } | |
4216 | ||
c5aff182 TP |
4217 | mvneta_cleanup_rxqs(pp); |
4218 | mvneta_cleanup_txqs(pp); | |
c5aff182 TP |
4219 | |
4220 | return 0; | |
4221 | } | |
4222 | ||
15f59456 TP |
4223 | static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
4224 | { | |
503f9aa9 | 4225 | struct mvneta_port *pp = netdev_priv(dev); |
15f59456 | 4226 | |
503f9aa9 | 4227 | return phylink_mii_ioctl(pp->phylink, ifr, cmd); |
15f59456 TP |
4228 | } |
4229 | ||
0db51da7 LB |
4230 | static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, |
4231 | struct netlink_ext_ack *extack) | |
4232 | { | |
4233 | bool need_update, running = netif_running(dev); | |
4234 | struct mvneta_port *pp = netdev_priv(dev); | |
4235 | struct bpf_prog *old_prog; | |
4236 | ||
4237 | if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { | |
4238 | NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); | |
4239 | return -EOPNOTSUPP; | |
79572c98 SA |
4240 | } |
4241 | ||
4242 | if (pp->bm_priv) { | |
4243 | NL_SET_ERR_MSG_MOD(extack, | |
4244 | "Hardware Buffer Management not supported on XDP"); | |
4245 | return -EOPNOTSUPP; | |
0db51da7 LB |
4246 | } |
4247 | ||
4248 | need_update = !!pp->xdp_prog != !!prog; | |
4249 | if (running && need_update) | |
4250 | mvneta_stop(dev); | |
4251 | ||
4252 | old_prog = xchg(&pp->xdp_prog, prog); | |
4253 | if (old_prog) | |
4254 | bpf_prog_put(old_prog); | |
4255 | ||
4256 | if (running && need_update) | |
4257 | return mvneta_open(dev); | |
4258 | ||
4259 | return 0; | |
4260 | } | |
4261 | ||
4262 | static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) | |
4263 | { | |
4264 | struct mvneta_port *pp = netdev_priv(dev); | |
4265 | ||
4266 | switch (xdp->command) { | |
4267 | case XDP_SETUP_PROG: | |
4268 | return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); | |
4269 | case XDP_QUERY_PROG: | |
4270 | xdp->prog_id = pp->xdp_prog ? pp->xdp_prog->aux->id : 0; | |
4271 | return 0; | |
4272 | default: | |
4273 | return -EINVAL; | |
4274 | } | |
4275 | } | |
4276 | ||
c5aff182 TP |
4277 | /* Ethtool methods */ |
4278 | ||
013ad40d | 4279 | /* Set link ksettings (phy address, speed) for ethtools */ |
2dc0d2b4 BX |
4280 | static int |
4281 | mvneta_ethtool_set_link_ksettings(struct net_device *ndev, | |
4282 | const struct ethtool_link_ksettings *cmd) | |
c5aff182 | 4283 | { |
013ad40d | 4284 | struct mvneta_port *pp = netdev_priv(ndev); |
0c0744fc | 4285 | |
503f9aa9 RK |
4286 | return phylink_ethtool_ksettings_set(pp->phylink, cmd); |
4287 | } | |
0c0744fc | 4288 | |
503f9aa9 RK |
4289 | /* Get link ksettings for ethtools */ |
4290 | static int | |
4291 | mvneta_ethtool_get_link_ksettings(struct net_device *ndev, | |
4292 | struct ethtool_link_ksettings *cmd) | |
4293 | { | |
4294 | struct mvneta_port *pp = netdev_priv(ndev); | |
0c0744fc | 4295 | |
503f9aa9 RK |
4296 | return phylink_ethtool_ksettings_get(pp->phylink, cmd); |
4297 | } | |
0c0744fc | 4298 | |
503f9aa9 RK |
4299 | static int mvneta_ethtool_nway_reset(struct net_device *dev) |
4300 | { | |
4301 | struct mvneta_port *pp = netdev_priv(dev); | |
0c0744fc | 4302 | |
503f9aa9 | 4303 | return phylink_ethtool_nway_reset(pp->phylink); |
c5aff182 TP |
4304 | } |
4305 | ||
4306 | /* Set interrupt coalescing for ethtools */ | |
4307 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, | |
4308 | struct ethtool_coalesce *c) | |
4309 | { | |
4310 | struct mvneta_port *pp = netdev_priv(dev); | |
4311 | int queue; | |
4312 | ||
4313 | for (queue = 0; queue < rxq_number; queue++) { | |
4314 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
4315 | rxq->time_coal = c->rx_coalesce_usecs; | |
4316 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
4317 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
4318 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
4319 | } | |
4320 | ||
4321 | for (queue = 0; queue < txq_number; queue++) { | |
4322 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
4323 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
4324 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
4325 | } | |
4326 | ||
4327 | return 0; | |
4328 | } | |
4329 | ||
4330 | /* get coalescing for ethtools */ | |
4331 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, | |
4332 | struct ethtool_coalesce *c) | |
4333 | { | |
4334 | struct mvneta_port *pp = netdev_priv(dev); | |
4335 | ||
4336 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; | |
4337 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; | |
4338 | ||
4339 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; | |
4340 | return 0; | |
4341 | } | |
4342 | ||
4343 | ||
4344 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, | |
4345 | struct ethtool_drvinfo *drvinfo) | |
4346 | { | |
4347 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, | |
4348 | sizeof(drvinfo->driver)); | |
4349 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, | |
4350 | sizeof(drvinfo->version)); | |
4351 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
4352 | sizeof(drvinfo->bus_info)); | |
4353 | } | |
4354 | ||
4355 | ||
4356 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, | |
4357 | struct ethtool_ringparam *ring) | |
4358 | { | |
4359 | struct mvneta_port *pp = netdev_priv(netdev); | |
4360 | ||
4361 | ring->rx_max_pending = MVNETA_MAX_RXD; | |
4362 | ring->tx_max_pending = MVNETA_MAX_TXD; | |
4363 | ring->rx_pending = pp->rx_ring_size; | |
4364 | ring->tx_pending = pp->tx_ring_size; | |
4365 | } | |
4366 | ||
4367 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, | |
4368 | struct ethtool_ringparam *ring) | |
4369 | { | |
4370 | struct mvneta_port *pp = netdev_priv(dev); | |
4371 | ||
4372 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) | |
4373 | return -EINVAL; | |
4374 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? | |
4375 | ring->rx_pending : MVNETA_MAX_RXD; | |
8eef5f97 EG |
4376 | |
4377 | pp->tx_ring_size = clamp_t(u16, ring->tx_pending, | |
4378 | MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); | |
4379 | if (pp->tx_ring_size != ring->tx_pending) | |
4380 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", | |
4381 | pp->tx_ring_size, ring->tx_pending); | |
c5aff182 TP |
4382 | |
4383 | if (netif_running(dev)) { | |
4384 | mvneta_stop(dev); | |
4385 | if (mvneta_open(dev)) { | |
4386 | netdev_err(dev, | |
4387 | "error on opening device after ring param change\n"); | |
4388 | return -ENOMEM; | |
4389 | } | |
4390 | } | |
4391 | ||
4392 | return 0; | |
4393 | } | |
4394 | ||
4932a918 RK |
4395 | static void mvneta_ethtool_get_pauseparam(struct net_device *dev, |
4396 | struct ethtool_pauseparam *pause) | |
4397 | { | |
4398 | struct mvneta_port *pp = netdev_priv(dev); | |
4399 | ||
4400 | phylink_ethtool_get_pauseparam(pp->phylink, pause); | |
4401 | } | |
4402 | ||
4403 | static int mvneta_ethtool_set_pauseparam(struct net_device *dev, | |
4404 | struct ethtool_pauseparam *pause) | |
4405 | { | |
4406 | struct mvneta_port *pp = netdev_priv(dev); | |
4407 | ||
4408 | return phylink_ethtool_set_pauseparam(pp->phylink, pause); | |
4409 | } | |
4410 | ||
9b0cdefa RK |
4411 | static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, |
4412 | u8 *data) | |
4413 | { | |
4414 | if (sset == ETH_SS_STATS) { | |
4415 | int i; | |
4416 | ||
4417 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
4418 | memcpy(data + i * ETH_GSTRING_LEN, | |
4419 | mvneta_statistics[i].name, ETH_GSTRING_LEN); | |
4420 | } | |
4421 | } | |
4422 | ||
4423 | static void mvneta_ethtool_update_stats(struct mvneta_port *pp) | |
4424 | { | |
4425 | const struct mvneta_statistic *s; | |
4426 | void __iomem *base = pp->base; | |
6d81f451 RK |
4427 | u32 high, low; |
4428 | u64 val; | |
9b0cdefa RK |
4429 | int i; |
4430 | ||
4431 | for (i = 0, s = mvneta_statistics; | |
4432 | s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); | |
4433 | s++, i++) { | |
6d81f451 RK |
4434 | val = 0; |
4435 | ||
9b0cdefa RK |
4436 | switch (s->type) { |
4437 | case T_REG_32: | |
4438 | val = readl_relaxed(base + s->offset); | |
4439 | break; | |
4440 | case T_REG_64: | |
4441 | /* Docs say to read low 32-bit then high */ | |
4442 | low = readl_relaxed(base + s->offset); | |
4443 | high = readl_relaxed(base + s->offset + 4); | |
6d81f451 RK |
4444 | val = (u64)high << 32 | low; |
4445 | break; | |
4446 | case T_SW: | |
4447 | switch (s->offset) { | |
4448 | case ETHTOOL_STAT_EEE_WAKEUP: | |
4449 | val = phylink_get_eee_err(pp->phylink); | |
4450 | break; | |
17a96da6 GC |
4451 | case ETHTOOL_STAT_SKB_ALLOC_ERR: |
4452 | val = pp->rxqs[0].skb_alloc_err; | |
4453 | break; | |
4454 | case ETHTOOL_STAT_REFILL_ERR: | |
4455 | val = pp->rxqs[0].refill_err; | |
4456 | break; | |
6d81f451 | 4457 | } |
9b0cdefa RK |
4458 | break; |
4459 | } | |
6d81f451 RK |
4460 | |
4461 | pp->ethtool_stats[i] += val; | |
9b0cdefa RK |
4462 | } |
4463 | } | |
4464 | ||
4465 | static void mvneta_ethtool_get_stats(struct net_device *dev, | |
4466 | struct ethtool_stats *stats, u64 *data) | |
4467 | { | |
4468 | struct mvneta_port *pp = netdev_priv(dev); | |
4469 | int i; | |
4470 | ||
4471 | mvneta_ethtool_update_stats(pp); | |
4472 | ||
4473 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
4474 | *data++ = pp->ethtool_stats[i]; | |
4475 | } | |
4476 | ||
4477 | static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) | |
4478 | { | |
4479 | if (sset == ETH_SS_STATS) | |
4480 | return ARRAY_SIZE(mvneta_statistics); | |
4481 | return -EOPNOTSUPP; | |
4482 | } | |
4483 | ||
9a401dea GC |
4484 | static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) |
4485 | { | |
4486 | return MVNETA_RSS_LU_TABLE_SIZE; | |
4487 | } | |
4488 | ||
4489 | static int mvneta_ethtool_get_rxnfc(struct net_device *dev, | |
4490 | struct ethtool_rxnfc *info, | |
4491 | u32 *rules __always_unused) | |
4492 | { | |
4493 | switch (info->cmd) { | |
4494 | case ETHTOOL_GRXRINGS: | |
4495 | info->data = rxq_number; | |
4496 | return 0; | |
4497 | case ETHTOOL_GRXFH: | |
4498 | return -EOPNOTSUPP; | |
4499 | default: | |
4500 | return -EOPNOTSUPP; | |
4501 | } | |
4502 | } | |
4503 | ||
4504 | static int mvneta_config_rss(struct mvneta_port *pp) | |
4505 | { | |
4506 | int cpu; | |
4507 | u32 val; | |
4508 | ||
4509 | netif_tx_stop_all_queues(pp->dev); | |
4510 | ||
6b125d63 | 4511 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
9a401dea | 4512 | |
0f5c6c30 JZ |
4513 | if (!pp->neta_armada3700) { |
4514 | /* We have to synchronise on the napi of each CPU */ | |
4515 | for_each_online_cpu(cpu) { | |
4516 | struct mvneta_pcpu_port *pcpu_port = | |
4517 | per_cpu_ptr(pp->ports, cpu); | |
9a401dea | 4518 | |
0f5c6c30 JZ |
4519 | napi_synchronize(&pcpu_port->napi); |
4520 | napi_disable(&pcpu_port->napi); | |
4521 | } | |
4522 | } else { | |
4523 | napi_synchronize(&pp->napi); | |
4524 | napi_disable(&pp->napi); | |
9a401dea GC |
4525 | } |
4526 | ||
4527 | pp->rxq_def = pp->indir[0]; | |
4528 | ||
4529 | /* Update unicast mapping */ | |
4530 | mvneta_set_rx_mode(pp->dev); | |
4531 | ||
4532 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
4533 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); | |
4534 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
4535 | ||
4536 | /* Update the elected CPU matching the new rxq_def */ | |
120cfa50 | 4537 | spin_lock(&pp->lock); |
9a401dea | 4538 | mvneta_percpu_elect(pp); |
120cfa50 | 4539 | spin_unlock(&pp->lock); |
9a401dea | 4540 | |
0f5c6c30 JZ |
4541 | if (!pp->neta_armada3700) { |
4542 | /* We have to synchronise on the napi of each CPU */ | |
4543 | for_each_online_cpu(cpu) { | |
4544 | struct mvneta_pcpu_port *pcpu_port = | |
4545 | per_cpu_ptr(pp->ports, cpu); | |
9a401dea | 4546 | |
0f5c6c30 JZ |
4547 | napi_enable(&pcpu_port->napi); |
4548 | } | |
4549 | } else { | |
4550 | napi_enable(&pp->napi); | |
9a401dea GC |
4551 | } |
4552 | ||
4553 | netif_tx_start_all_queues(pp->dev); | |
4554 | ||
4555 | return 0; | |
4556 | } | |
4557 | ||
4558 | static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, | |
4559 | const u8 *key, const u8 hfunc) | |
4560 | { | |
4561 | struct mvneta_port *pp = netdev_priv(dev); | |
2636ac3c MW |
4562 | |
4563 | /* Current code for Armada 3700 doesn't support RSS features yet */ | |
4564 | if (pp->neta_armada3700) | |
4565 | return -EOPNOTSUPP; | |
4566 | ||
9a401dea GC |
4567 | /* We require at least one supported parameter to be changed |
4568 | * and no change in any of the unsupported parameters | |
4569 | */ | |
4570 | if (key || | |
4571 | (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) | |
4572 | return -EOPNOTSUPP; | |
4573 | ||
4574 | if (!indir) | |
4575 | return 0; | |
4576 | ||
4577 | memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); | |
4578 | ||
4579 | return mvneta_config_rss(pp); | |
4580 | } | |
4581 | ||
4582 | static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, | |
4583 | u8 *hfunc) | |
4584 | { | |
4585 | struct mvneta_port *pp = netdev_priv(dev); | |
4586 | ||
2636ac3c MW |
4587 | /* Current code for Armada 3700 doesn't support RSS features yet */ |
4588 | if (pp->neta_armada3700) | |
4589 | return -EOPNOTSUPP; | |
4590 | ||
9a401dea GC |
4591 | if (hfunc) |
4592 | *hfunc = ETH_RSS_HASH_TOP; | |
4593 | ||
4594 | if (!indir) | |
4595 | return 0; | |
4596 | ||
4597 | memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); | |
4598 | ||
4599 | return 0; | |
4600 | } | |
4601 | ||
b60a00f9 JH |
4602 | static void mvneta_ethtool_get_wol(struct net_device *dev, |
4603 | struct ethtool_wolinfo *wol) | |
4604 | { | |
503f9aa9 | 4605 | struct mvneta_port *pp = netdev_priv(dev); |
b60a00f9 | 4606 | |
503f9aa9 | 4607 | phylink_ethtool_get_wol(pp->phylink, wol); |
b60a00f9 JH |
4608 | } |
4609 | ||
4610 | static int mvneta_ethtool_set_wol(struct net_device *dev, | |
4611 | struct ethtool_wolinfo *wol) | |
4612 | { | |
503f9aa9 | 4613 | struct mvneta_port *pp = netdev_priv(dev); |
82960fff JZ |
4614 | int ret; |
4615 | ||
503f9aa9 | 4616 | ret = phylink_ethtool_set_wol(pp->phylink, wol); |
82960fff JZ |
4617 | if (!ret) |
4618 | device_set_wakeup_enable(&dev->dev, !!wol->wolopts); | |
4619 | ||
4620 | return ret; | |
b60a00f9 JH |
4621 | } |
4622 | ||
6d81f451 RK |
4623 | static int mvneta_ethtool_get_eee(struct net_device *dev, |
4624 | struct ethtool_eee *eee) | |
4625 | { | |
4626 | struct mvneta_port *pp = netdev_priv(dev); | |
4627 | u32 lpi_ctl0; | |
4628 | ||
4629 | lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); | |
4630 | ||
4631 | eee->eee_enabled = pp->eee_enabled; | |
4632 | eee->eee_active = pp->eee_active; | |
4633 | eee->tx_lpi_enabled = pp->tx_lpi_enabled; | |
4634 | eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; | |
4635 | ||
4636 | return phylink_ethtool_get_eee(pp->phylink, eee); | |
4637 | } | |
4638 | ||
4639 | static int mvneta_ethtool_set_eee(struct net_device *dev, | |
4640 | struct ethtool_eee *eee) | |
4641 | { | |
4642 | struct mvneta_port *pp = netdev_priv(dev); | |
4643 | u32 lpi_ctl0; | |
4644 | ||
4645 | /* The Armada 37x documents do not give limits for this other than | |
4646 | * it being an 8-bit register. */ | |
e4a3e9ff | 4647 | if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) |
6d81f451 RK |
4648 | return -EINVAL; |
4649 | ||
4650 | lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); | |
4651 | lpi_ctl0 &= ~(0xff << 8); | |
4652 | lpi_ctl0 |= eee->tx_lpi_timer << 8; | |
4653 | mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); | |
4654 | ||
4655 | pp->eee_enabled = eee->eee_enabled; | |
4656 | pp->tx_lpi_enabled = eee->tx_lpi_enabled; | |
4657 | ||
4658 | mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); | |
4659 | ||
4660 | return phylink_ethtool_set_eee(pp->phylink, eee); | |
4661 | } | |
4662 | ||
c5aff182 TP |
4663 | static const struct net_device_ops mvneta_netdev_ops = { |
4664 | .ndo_open = mvneta_open, | |
4665 | .ndo_stop = mvneta_stop, | |
4666 | .ndo_start_xmit = mvneta_tx, | |
4667 | .ndo_set_rx_mode = mvneta_set_rx_mode, | |
4668 | .ndo_set_mac_address = mvneta_set_mac_addr, | |
4669 | .ndo_change_mtu = mvneta_change_mtu, | |
b65657fc | 4670 | .ndo_fix_features = mvneta_fix_features, |
c5aff182 | 4671 | .ndo_get_stats64 = mvneta_get_stats64, |
15f59456 | 4672 | .ndo_do_ioctl = mvneta_ioctl, |
0db51da7 | 4673 | .ndo_bpf = mvneta_xdp, |
b0a43db9 | 4674 | .ndo_xdp_xmit = mvneta_xdp_xmit, |
c5aff182 TP |
4675 | }; |
4676 | ||
4581be42 | 4677 | static const struct ethtool_ops mvneta_eth_tool_ops = { |
503f9aa9 | 4678 | .nway_reset = mvneta_ethtool_nway_reset, |
c5aff182 | 4679 | .get_link = ethtool_op_get_link, |
c5aff182 TP |
4680 | .set_coalesce = mvneta_ethtool_set_coalesce, |
4681 | .get_coalesce = mvneta_ethtool_get_coalesce, | |
4682 | .get_drvinfo = mvneta_ethtool_get_drvinfo, | |
4683 | .get_ringparam = mvneta_ethtool_get_ringparam, | |
4684 | .set_ringparam = mvneta_ethtool_set_ringparam, | |
4932a918 RK |
4685 | .get_pauseparam = mvneta_ethtool_get_pauseparam, |
4686 | .set_pauseparam = mvneta_ethtool_set_pauseparam, | |
9b0cdefa RK |
4687 | .get_strings = mvneta_ethtool_get_strings, |
4688 | .get_ethtool_stats = mvneta_ethtool_get_stats, | |
4689 | .get_sset_count = mvneta_ethtool_get_sset_count, | |
9a401dea GC |
4690 | .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, |
4691 | .get_rxnfc = mvneta_ethtool_get_rxnfc, | |
4692 | .get_rxfh = mvneta_ethtool_get_rxfh, | |
4693 | .set_rxfh = mvneta_ethtool_set_rxfh, | |
503f9aa9 | 4694 | .get_link_ksettings = mvneta_ethtool_get_link_ksettings, |
013ad40d | 4695 | .set_link_ksettings = mvneta_ethtool_set_link_ksettings, |
b60a00f9 JH |
4696 | .get_wol = mvneta_ethtool_get_wol, |
4697 | .set_wol = mvneta_ethtool_set_wol, | |
6d81f451 RK |
4698 | .get_eee = mvneta_ethtool_get_eee, |
4699 | .set_eee = mvneta_ethtool_set_eee, | |
c5aff182 TP |
4700 | }; |
4701 | ||
4702 | /* Initialize hw */ | |
9672850b | 4703 | static int mvneta_init(struct device *dev, struct mvneta_port *pp) |
c5aff182 TP |
4704 | { |
4705 | int queue; | |
4706 | ||
4707 | /* Disable port */ | |
4708 | mvneta_port_disable(pp); | |
4709 | ||
4710 | /* Set port default values */ | |
4711 | mvneta_defaults_set(pp); | |
4712 | ||
5d6312ed | 4713 | pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); |
c5aff182 TP |
4714 | if (!pp->txqs) |
4715 | return -ENOMEM; | |
4716 | ||
4717 | /* Initialize TX descriptor rings */ | |
4718 | for (queue = 0; queue < txq_number; queue++) { | |
4719 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
4720 | txq->id = queue; | |
4721 | txq->size = pp->tx_ring_size; | |
4722 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; | |
4723 | } | |
4724 | ||
5d6312ed | 4725 | pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); |
9672850b | 4726 | if (!pp->rxqs) |
c5aff182 | 4727 | return -ENOMEM; |
c5aff182 TP |
4728 | |
4729 | /* Create Rx descriptor rings */ | |
4730 | for (queue = 0; queue < rxq_number; queue++) { | |
4731 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
4732 | rxq->id = queue; | |
4733 | rxq->size = pp->rx_ring_size; | |
4734 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; | |
4735 | rxq->time_coal = MVNETA_RX_COAL_USEC; | |
29110630 ME |
4736 | rxq->buf_virt_addr |
4737 | = devm_kmalloc_array(pp->dev->dev.parent, | |
4738 | rxq->size, | |
4739 | sizeof(*rxq->buf_virt_addr), | |
4740 | GFP_KERNEL); | |
f88bee1c GC |
4741 | if (!rxq->buf_virt_addr) |
4742 | return -ENOMEM; | |
c5aff182 TP |
4743 | } |
4744 | ||
4745 | return 0; | |
4746 | } | |
4747 | ||
c5aff182 | 4748 | /* platform glue : initialize decoding windows */ |
03ce758e GK |
4749 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
4750 | const struct mbus_dram_target_info *dram) | |
c5aff182 TP |
4751 | { |
4752 | u32 win_enable; | |
4753 | u32 win_protect; | |
4754 | int i; | |
4755 | ||
4756 | for (i = 0; i < 6; i++) { | |
4757 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
4758 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
4759 | ||
4760 | if (i < 4) | |
4761 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
4762 | } | |
4763 | ||
4764 | win_enable = 0x3f; | |
4765 | win_protect = 0; | |
4766 | ||
2636ac3c MW |
4767 | if (dram) { |
4768 | for (i = 0; i < dram->num_cs; i++) { | |
4769 | const struct mbus_dram_window *cs = dram->cs + i; | |
4770 | ||
4771 | mvreg_write(pp, MVNETA_WIN_BASE(i), | |
4772 | (cs->base & 0xffff0000) | | |
4773 | (cs->mbus_attr << 8) | | |
4774 | dram->mbus_dram_target_id); | |
c5aff182 | 4775 | |
2636ac3c MW |
4776 | mvreg_write(pp, MVNETA_WIN_SIZE(i), |
4777 | (cs->size - 1) & 0xffff0000); | |
c5aff182 | 4778 | |
2636ac3c MW |
4779 | win_enable &= ~(1 << i); |
4780 | win_protect |= 3 << (2 * i); | |
4781 | } | |
4782 | } else { | |
4783 | /* For Armada3700 open default 4GB Mbus window, leaving | |
4784 | * arbitration of target/attribute to a different layer | |
4785 | * of configuration. | |
4786 | */ | |
4787 | mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); | |
4788 | win_enable &= ~BIT(0); | |
4789 | win_protect = 3; | |
c5aff182 TP |
4790 | } |
4791 | ||
4792 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
db6ba9a5 | 4793 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); |
c5aff182 TP |
4794 | } |
4795 | ||
4796 | /* Power up the port */ | |
3f1dd4bc | 4797 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
c5aff182 | 4798 | { |
c5aff182 TP |
4799 | /* MAC Cause register should be cleared */ |
4800 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
4801 | ||
32699954 | 4802 | if (phy_mode == PHY_INTERFACE_MODE_QSGMII) |
3f1dd4bc | 4803 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); |
22f4bf8a | 4804 | else if (phy_mode == PHY_INTERFACE_MODE_SGMII || |
a10c1c81 | 4805 | phy_interface_mode_is_8023z(phy_mode)) |
3f1dd4bc | 4806 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); |
32699954 | 4807 | else if (!phy_interface_mode_is_rgmii(phy_mode)) |
3f1dd4bc | 4808 | return -EINVAL; |
3f1dd4bc TP |
4809 | |
4810 | return 0; | |
c5aff182 TP |
4811 | } |
4812 | ||
4813 | /* Device initialization routine */ | |
03ce758e | 4814 | static int mvneta_probe(struct platform_device *pdev) |
c5aff182 | 4815 | { |
c5aff182 | 4816 | struct device_node *dn = pdev->dev.of_node; |
dc35a10f | 4817 | struct device_node *bm_node; |
c5aff182 TP |
4818 | struct mvneta_port *pp; |
4819 | struct net_device *dev; | |
503f9aa9 | 4820 | struct phylink *phylink; |
a10c1c81 | 4821 | struct phy *comphy; |
8cc3e439 TP |
4822 | const char *dt_mac_addr; |
4823 | char hw_mac_addr[ETH_ALEN]; | |
0c65b2b9 | 4824 | phy_interface_t phy_mode; |
8cc3e439 | 4825 | const char *mac_from; |
9110ee07 | 4826 | int tx_csum_limit; |
c5aff182 | 4827 | int err; |
12bb03b4 | 4828 | int cpu; |
c5aff182 | 4829 | |
a3ddd94f RP |
4830 | dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), |
4831 | txq_number, rxq_number); | |
c5aff182 TP |
4832 | if (!dev) |
4833 | return -ENOMEM; | |
4834 | ||
4835 | dev->irq = irq_of_parse_and_map(dn, 0); | |
a3ddd94f RP |
4836 | if (dev->irq == 0) |
4837 | return -EINVAL; | |
c5aff182 | 4838 | |
0c65b2b9 AL |
4839 | err = of_get_phy_mode(dn, &phy_mode); |
4840 | if (err) { | |
c5aff182 | 4841 | dev_err(&pdev->dev, "incorrect phy-mode\n"); |
503f9aa9 RK |
4842 | goto err_free_irq; |
4843 | } | |
4844 | ||
a10c1c81 RK |
4845 | comphy = devm_of_phy_get(&pdev->dev, dn, NULL); |
4846 | if (comphy == ERR_PTR(-EPROBE_DEFER)) { | |
4847 | err = -EPROBE_DEFER; | |
4848 | goto err_free_irq; | |
4849 | } else if (IS_ERR(comphy)) { | |
4850 | comphy = NULL; | |
4851 | } | |
4852 | ||
44cc27e4 IC |
4853 | pp = netdev_priv(dev); |
4854 | spin_lock_init(&pp->lock); | |
4855 | ||
4856 | pp->phylink_config.dev = &dev->dev; | |
4857 | pp->phylink_config.type = PHYLINK_NETDEV; | |
4858 | ||
4859 | phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, | |
4860 | phy_mode, &mvneta_phylink_ops); | |
503f9aa9 RK |
4861 | if (IS_ERR(phylink)) { |
4862 | err = PTR_ERR(phylink); | |
4863 | goto err_free_irq; | |
c5aff182 TP |
4864 | } |
4865 | ||
c5aff182 TP |
4866 | dev->tx_queue_len = MVNETA_MAX_TXD; |
4867 | dev->watchdog_timeo = 5 * HZ; | |
4868 | dev->netdev_ops = &mvneta_netdev_ops; | |
4869 | ||
7ad24ea4 | 4870 | dev->ethtool_ops = &mvneta_eth_tool_ops; |
c5aff182 | 4871 | |
503f9aa9 | 4872 | pp->phylink = phylink; |
a10c1c81 | 4873 | pp->comphy = comphy; |
c5aff182 | 4874 | pp->phy_interface = phy_mode; |
503f9aa9 | 4875 | pp->dn = dn; |
c5aff182 | 4876 | |
90b74c01 | 4877 | pp->rxq_def = rxq_def; |
9a401dea GC |
4878 | pp->indir[0] = rxq_def; |
4879 | ||
2636ac3c MW |
4880 | /* Get special SoC configurations */ |
4881 | if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) | |
4882 | pp->neta_armada3700 = true; | |
4883 | ||
2804ba4e JZ |
4884 | pp->clk = devm_clk_get(&pdev->dev, "core"); |
4885 | if (IS_ERR(pp->clk)) | |
4886 | pp->clk = devm_clk_get(&pdev->dev, NULL); | |
189dd626 TP |
4887 | if (IS_ERR(pp->clk)) { |
4888 | err = PTR_ERR(pp->clk); | |
503f9aa9 | 4889 | goto err_free_phylink; |
189dd626 TP |
4890 | } |
4891 | ||
4892 | clk_prepare_enable(pp->clk); | |
4893 | ||
15cc4a4a JZ |
4894 | pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); |
4895 | if (!IS_ERR(pp->clk_bus)) | |
4896 | clk_prepare_enable(pp->clk_bus); | |
4897 | ||
00c33afb | 4898 | pp->base = devm_platform_ioremap_resource(pdev, 0); |
c3f0dd38 TP |
4899 | if (IS_ERR(pp->base)) { |
4900 | err = PTR_ERR(pp->base); | |
5445eaf3 APR |
4901 | goto err_clk; |
4902 | } | |
4903 | ||
12bb03b4 MR |
4904 | /* Alloc per-cpu port structure */ |
4905 | pp->ports = alloc_percpu(struct mvneta_pcpu_port); | |
4906 | if (!pp->ports) { | |
4907 | err = -ENOMEM; | |
4908 | goto err_clk; | |
4909 | } | |
4910 | ||
74c41b04 | 4911 | /* Alloc per-cpu stats */ |
1c213bd2 | 4912 | pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); |
74c41b04 | 4913 | if (!pp->stats) { |
4914 | err = -ENOMEM; | |
12bb03b4 | 4915 | goto err_free_ports; |
74c41b04 | 4916 | } |
4917 | ||
8cc3e439 | 4918 | dt_mac_addr = of_get_mac_address(dn); |
a51645f7 | 4919 | if (!IS_ERR(dt_mac_addr)) { |
8cc3e439 | 4920 | mac_from = "device tree"; |
2d2924af | 4921 | ether_addr_copy(dev->dev_addr, dt_mac_addr); |
8cc3e439 TP |
4922 | } else { |
4923 | mvneta_get_mac_addr(pp, hw_mac_addr); | |
4924 | if (is_valid_ether_addr(hw_mac_addr)) { | |
4925 | mac_from = "hardware"; | |
4926 | memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); | |
4927 | } else { | |
4928 | mac_from = "random"; | |
4929 | eth_hw_addr_random(dev); | |
4930 | } | |
4931 | } | |
4932 | ||
9110ee07 MW |
4933 | if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { |
4934 | if (tx_csum_limit < 0 || | |
4935 | tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { | |
4936 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
4937 | dev_info(&pdev->dev, | |
4938 | "Wrong TX csum limit in DT, set to %dB\n", | |
4939 | MVNETA_TX_CSUM_DEF_SIZE); | |
4940 | } | |
4941 | } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { | |
4942 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
4943 | } else { | |
4944 | tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; | |
4945 | } | |
4946 | ||
4947 | pp->tx_csum_limit = tx_csum_limit; | |
b65657fc | 4948 | |
9768b45c | 4949 | pp->dram_target_info = mv_mbus_dram_info(); |
2636ac3c MW |
4950 | /* Armada3700 requires setting default configuration of Mbus |
4951 | * windows, however without using filled mbus_dram_target_info | |
4952 | * structure. | |
4953 | */ | |
9768b45c JL |
4954 | if (pp->dram_target_info || pp->neta_armada3700) |
4955 | mvneta_conf_mbus_windows(pp, pp->dram_target_info); | |
dc35a10f | 4956 | |
c5aff182 TP |
4957 | pp->tx_ring_size = MVNETA_MAX_TXD; |
4958 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
4959 | ||
4960 | pp->dev = dev; | |
4961 | SET_NETDEV_DEV(dev, &pdev->dev); | |
4962 | ||
dc35a10f MW |
4963 | pp->id = global_port_id++; |
4964 | ||
4965 | /* Obtain access to BM resources if enabled and already initialized */ | |
4966 | bm_node = of_parse_phandle(dn, "buffer-manager", 0); | |
965cbbec GC |
4967 | if (bm_node) { |
4968 | pp->bm_priv = mvneta_bm_get(bm_node); | |
4969 | if (pp->bm_priv) { | |
4970 | err = mvneta_bm_port_init(pdev, pp); | |
4971 | if (err < 0) { | |
4972 | dev_info(&pdev->dev, | |
4973 | "use SW buffer management\n"); | |
4974 | mvneta_bm_put(pp->bm_priv); | |
4975 | pp->bm_priv = NULL; | |
4976 | } | |
dc35a10f | 4977 | } |
562e2f46 YK |
4978 | /* Set RX packet offset correction for platforms, whose |
4979 | * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit | |
4980 | * platforms and 0B for 32-bit ones. | |
4981 | */ | |
4982 | pp->rx_offset_correction = max(0, | |
4983 | NET_SKB_PAD - | |
4984 | MVNETA_RX_PKT_OFFSET_CORRECTION); | |
dc35a10f | 4985 | } |
d4e4da00 | 4986 | of_node_put(bm_node); |
dc35a10f | 4987 | |
44efc78d LB |
4988 | /* sw buffer management */ |
4989 | if (!pp->bm_priv) | |
4990 | pp->rx_offset_correction = MVNETA_SKB_HEADROOM; | |
4991 | ||
9672850b EG |
4992 | err = mvneta_init(&pdev->dev, pp); |
4993 | if (err < 0) | |
dc35a10f | 4994 | goto err_netdev; |
3f1dd4bc TP |
4995 | |
4996 | err = mvneta_port_power_up(pp, phy_mode); | |
4997 | if (err < 0) { | |
4998 | dev_err(&pdev->dev, "can't power up port\n"); | |
dc35a10f | 4999 | goto err_netdev; |
3f1dd4bc | 5000 | } |
c5aff182 | 5001 | |
2636ac3c MW |
5002 | /* Armada3700 network controller does not support per-cpu |
5003 | * operation, so only single NAPI should be initialized. | |
5004 | */ | |
5005 | if (pp->neta_armada3700) { | |
5006 | netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); | |
5007 | } else { | |
5008 | for_each_present_cpu(cpu) { | |
5009 | struct mvneta_pcpu_port *port = | |
5010 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 5011 | |
2636ac3c MW |
5012 | netif_napi_add(dev, &port->napi, mvneta_poll, |
5013 | NAPI_POLL_WEIGHT); | |
5014 | port->pp = pp; | |
5015 | } | |
12bb03b4 | 5016 | } |
c5aff182 | 5017 | |
7772988a JZ |
5018 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
5019 | NETIF_F_TSO | NETIF_F_RXCSUM; | |
01ef26ca EG |
5020 | dev->hw_features |= dev->features; |
5021 | dev->vlan_features |= dev->features; | |
97db8afa | 5022 | dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; |
8eef5f97 | 5023 | dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; |
b50b72de | 5024 | |
5777987e JW |
5025 | /* MTU range: 68 - 9676 */ |
5026 | dev->min_mtu = ETH_MIN_MTU; | |
5027 | /* 9676 == 9700 - 20 and rounding to 8 */ | |
5028 | dev->max_mtu = 9676; | |
5029 | ||
c5aff182 TP |
5030 | err = register_netdev(dev); |
5031 | if (err < 0) { | |
5032 | dev_err(&pdev->dev, "failed to register\n"); | |
d484e06e | 5033 | goto err_netdev; |
c5aff182 TP |
5034 | } |
5035 | ||
8cc3e439 TP |
5036 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, |
5037 | dev->dev_addr); | |
c5aff182 TP |
5038 | |
5039 | platform_set_drvdata(pdev, pp->dev); | |
5040 | ||
5041 | return 0; | |
5042 | ||
dc35a10f | 5043 | err_netdev: |
dc35a10f MW |
5044 | if (pp->bm_priv) { |
5045 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
5046 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
5047 | 1 << pp->id); | |
965cbbec | 5048 | mvneta_bm_put(pp->bm_priv); |
dc35a10f | 5049 | } |
74c41b04 | 5050 | free_percpu(pp->stats); |
12bb03b4 MR |
5051 | err_free_ports: |
5052 | free_percpu(pp->ports); | |
5445eaf3 | 5053 | err_clk: |
15cc4a4a | 5054 | clk_disable_unprepare(pp->clk_bus); |
5445eaf3 | 5055 | clk_disable_unprepare(pp->clk); |
503f9aa9 RK |
5056 | err_free_phylink: |
5057 | if (pp->phylink) | |
5058 | phylink_destroy(pp->phylink); | |
c5aff182 TP |
5059 | err_free_irq: |
5060 | irq_dispose_mapping(dev->irq); | |
c5aff182 TP |
5061 | return err; |
5062 | } | |
5063 | ||
5064 | /* Device removal routine */ | |
03ce758e | 5065 | static int mvneta_remove(struct platform_device *pdev) |
c5aff182 TP |
5066 | { |
5067 | struct net_device *dev = platform_get_drvdata(pdev); | |
5068 | struct mvneta_port *pp = netdev_priv(dev); | |
5069 | ||
5070 | unregister_netdev(dev); | |
15cc4a4a | 5071 | clk_disable_unprepare(pp->clk_bus); |
189dd626 | 5072 | clk_disable_unprepare(pp->clk); |
12bb03b4 | 5073 | free_percpu(pp->ports); |
74c41b04 | 5074 | free_percpu(pp->stats); |
c5aff182 | 5075 | irq_dispose_mapping(dev->irq); |
503f9aa9 | 5076 | phylink_destroy(pp->phylink); |
c5aff182 | 5077 | |
dc35a10f MW |
5078 | if (pp->bm_priv) { |
5079 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
5080 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
5081 | 1 << pp->id); | |
965cbbec | 5082 | mvneta_bm_put(pp->bm_priv); |
dc35a10f MW |
5083 | } |
5084 | ||
c5aff182 TP |
5085 | return 0; |
5086 | } | |
5087 | ||
9768b45c JL |
5088 | #ifdef CONFIG_PM_SLEEP |
5089 | static int mvneta_suspend(struct device *device) | |
5090 | { | |
1799cdd2 | 5091 | int queue; |
9768b45c JL |
5092 | struct net_device *dev = dev_get_drvdata(device); |
5093 | struct mvneta_port *pp = netdev_priv(dev); | |
5094 | ||
1799cdd2 JZ |
5095 | if (!netif_running(dev)) |
5096 | goto clean_exit; | |
5097 | ||
5098 | if (!pp->neta_armada3700) { | |
5099 | spin_lock(&pp->lock); | |
5100 | pp->is_stopped = true; | |
5101 | spin_unlock(&pp->lock); | |
5102 | ||
5103 | cpuhp_state_remove_instance_nocalls(online_hpstate, | |
5104 | &pp->node_online); | |
5105 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
5106 | &pp->node_dead); | |
5107 | } | |
5108 | ||
3b8bc674 | 5109 | rtnl_lock(); |
1799cdd2 | 5110 | mvneta_stop_dev(pp); |
3b8bc674 | 5111 | rtnl_unlock(); |
1799cdd2 JZ |
5112 | |
5113 | for (queue = 0; queue < rxq_number; queue++) { | |
5114 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
5115 | ||
5116 | mvneta_rxq_drop_pkts(pp, rxq); | |
5117 | } | |
5118 | ||
5119 | for (queue = 0; queue < txq_number; queue++) { | |
5120 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
5121 | ||
5122 | mvneta_txq_hw_deinit(pp, txq); | |
5123 | } | |
5124 | ||
5125 | clean_exit: | |
9768b45c JL |
5126 | netif_device_detach(dev); |
5127 | clk_disable_unprepare(pp->clk_bus); | |
5128 | clk_disable_unprepare(pp->clk); | |
1799cdd2 | 5129 | |
9768b45c JL |
5130 | return 0; |
5131 | } | |
5132 | ||
5133 | static int mvneta_resume(struct device *device) | |
5134 | { | |
5135 | struct platform_device *pdev = to_platform_device(device); | |
5136 | struct net_device *dev = dev_get_drvdata(device); | |
5137 | struct mvneta_port *pp = netdev_priv(dev); | |
1799cdd2 | 5138 | int err, queue; |
9768b45c JL |
5139 | |
5140 | clk_prepare_enable(pp->clk); | |
5141 | if (!IS_ERR(pp->clk_bus)) | |
5142 | clk_prepare_enable(pp->clk_bus); | |
5143 | if (pp->dram_target_info || pp->neta_armada3700) | |
5144 | mvneta_conf_mbus_windows(pp, pp->dram_target_info); | |
5145 | if (pp->bm_priv) { | |
5146 | err = mvneta_bm_port_init(pdev, pp); | |
5147 | if (err < 0) { | |
5148 | dev_info(&pdev->dev, "use SW buffer management\n"); | |
44efc78d | 5149 | pp->rx_offset_correction = MVNETA_SKB_HEADROOM; |
9768b45c JL |
5150 | pp->bm_priv = NULL; |
5151 | } | |
5152 | } | |
5153 | mvneta_defaults_set(pp); | |
5154 | err = mvneta_port_power_up(pp, pp->phy_interface); | |
5155 | if (err < 0) { | |
5156 | dev_err(device, "can't power up port\n"); | |
5157 | return err; | |
5158 | } | |
5159 | ||
9768b45c | 5160 | netif_device_attach(dev); |
1799cdd2 JZ |
5161 | |
5162 | if (!netif_running(dev)) | |
5163 | return 0; | |
5164 | ||
5165 | for (queue = 0; queue < rxq_number; queue++) { | |
5166 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
5167 | ||
5168 | rxq->next_desc_to_proc = 0; | |
5169 | mvneta_rxq_hw_init(pp, rxq); | |
5170 | } | |
5171 | ||
5172 | for (queue = 0; queue < txq_number; queue++) { | |
5173 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
5174 | ||
5175 | txq->next_desc_to_proc = 0; | |
5176 | mvneta_txq_hw_init(pp, txq); | |
d6956ac8 | 5177 | } |
1799cdd2 JZ |
5178 | |
5179 | if (!pp->neta_armada3700) { | |
5180 | spin_lock(&pp->lock); | |
5181 | pp->is_stopped = false; | |
5182 | spin_unlock(&pp->lock); | |
5183 | cpuhp_state_add_instance_nocalls(online_hpstate, | |
5184 | &pp->node_online); | |
5185 | cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
5186 | &pp->node_dead); | |
5187 | } | |
5188 | ||
5189 | rtnl_lock(); | |
5190 | mvneta_start_dev(pp); | |
3b8bc674 | 5191 | rtnl_unlock(); |
1799cdd2 | 5192 | mvneta_set_rx_mode(dev); |
d6956ac8 | 5193 | |
9768b45c JL |
5194 | return 0; |
5195 | } | |
5196 | #endif | |
5197 | ||
5198 | static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); | |
5199 | ||
c5aff182 TP |
5200 | static const struct of_device_id mvneta_match[] = { |
5201 | { .compatible = "marvell,armada-370-neta" }, | |
f522a975 | 5202 | { .compatible = "marvell,armada-xp-neta" }, |
2636ac3c | 5203 | { .compatible = "marvell,armada-3700-neta" }, |
c5aff182 TP |
5204 | { } |
5205 | }; | |
5206 | MODULE_DEVICE_TABLE(of, mvneta_match); | |
5207 | ||
5208 | static struct platform_driver mvneta_driver = { | |
5209 | .probe = mvneta_probe, | |
03ce758e | 5210 | .remove = mvneta_remove, |
c5aff182 TP |
5211 | .driver = { |
5212 | .name = MVNETA_DRIVER_NAME, | |
5213 | .of_match_table = mvneta_match, | |
9768b45c | 5214 | .pm = &mvneta_pm_ops, |
c5aff182 TP |
5215 | }, |
5216 | }; | |
5217 | ||
84a3f4db SAS |
5218 | static int __init mvneta_driver_init(void) |
5219 | { | |
5220 | int ret; | |
5221 | ||
5222 | ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", | |
5223 | mvneta_cpu_online, | |
5224 | mvneta_cpu_down_prepare); | |
5225 | if (ret < 0) | |
5226 | goto out; | |
5227 | online_hpstate = ret; | |
5228 | ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", | |
5229 | NULL, mvneta_cpu_dead); | |
5230 | if (ret) | |
5231 | goto err_dead; | |
5232 | ||
5233 | ret = platform_driver_register(&mvneta_driver); | |
5234 | if (ret) | |
5235 | goto err; | |
5236 | return 0; | |
5237 | ||
5238 | err: | |
5239 | cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); | |
5240 | err_dead: | |
5241 | cpuhp_remove_multi_state(online_hpstate); | |
5242 | out: | |
5243 | return ret; | |
5244 | } | |
5245 | module_init(mvneta_driver_init); | |
5246 | ||
5247 | static void __exit mvneta_driver_exit(void) | |
5248 | { | |
5249 | platform_driver_unregister(&mvneta_driver); | |
5250 | cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); | |
5251 | cpuhp_remove_multi_state(online_hpstate); | |
5252 | } | |
5253 | module_exit(mvneta_driver_exit); | |
c5aff182 TP |
5254 | |
5255 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); | |
5256 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
5257 | MODULE_LICENSE("GPL"); | |
5258 | ||
d3757ba4 JP |
5259 | module_param(rxq_number, int, 0444); |
5260 | module_param(txq_number, int, 0444); | |
c5aff182 | 5261 | |
d3757ba4 JP |
5262 | module_param(rxq_def, int, 0444); |
5263 | module_param(rx_copybreak, int, 0644); |