Commit | Line | Data |
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c5aff182 TP |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Rami Rosen <rosenr@marvell.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
0e03f563 JZ |
14 | #include <linux/clk.h> |
15 | #include <linux/cpu.h> | |
c5aff182 | 16 | #include <linux/etherdevice.h> |
0e03f563 | 17 | #include <linux/if_vlan.h> |
c5aff182 | 18 | #include <linux/inetdevice.h> |
c5aff182 | 19 | #include <linux/interrupt.h> |
c3f0dd38 | 20 | #include <linux/io.h> |
0e03f563 JZ |
21 | #include <linux/kernel.h> |
22 | #include <linux/mbus.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/netdevice.h> | |
c5aff182 | 25 | #include <linux/of.h> |
0e03f563 | 26 | #include <linux/of_address.h> |
c5aff182 TP |
27 | #include <linux/of_irq.h> |
28 | #include <linux/of_mdio.h> | |
29 | #include <linux/of_net.h> | |
a10c1c81 | 30 | #include <linux/phy/phy.h> |
c5aff182 | 31 | #include <linux/phy.h> |
503f9aa9 | 32 | #include <linux/phylink.h> |
0e03f563 JZ |
33 | #include <linux/platform_device.h> |
34 | #include <linux/skbuff.h> | |
baa11ebc | 35 | #include <net/hwbm.h> |
dc35a10f | 36 | #include "mvneta_bm.h" |
0e03f563 JZ |
37 | #include <net/ip.h> |
38 | #include <net/ipv6.h> | |
39 | #include <net/tso.h> | |
568a3fa2 | 40 | #include <net/page_pool.h> |
0db51da7 | 41 | #include <linux/bpf_trace.h> |
c5aff182 TP |
42 | |
43 | /* Registers */ | |
44 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
e5bdf689 | 45 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) |
dc35a10f MW |
46 | #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 |
47 | #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 | |
48 | #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 | |
49 | #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 | |
c5aff182 TP |
50 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) |
51 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
52 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
53 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
54 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
55 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
56 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
57 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
58 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
59 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
60 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
61 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
62 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
dc35a10f MW |
63 | #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) |
64 | #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 | |
65 | #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 | |
c5aff182 TP |
66 | #define MVNETA_PORT_RX_RESET 0x1cc0 |
67 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
68 | #define MVNETA_PHY_ADDR 0x2000 | |
69 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
70 | #define MVNETA_MBUS_RETRY 0x2010 | |
71 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
72 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
73 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
74 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
75 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
76 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
77 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 | |
db6ba9a5 | 78 | #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 |
c5aff182 TP |
79 | #define MVNETA_PORT_CONFIG 0x2400 |
80 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
81 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
82 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
83 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
84 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
85 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
86 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
87 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
88 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
89 | MVNETA_DEF_RXQ_ARP(q) | \ | |
90 | MVNETA_DEF_RXQ_TCP(q) | \ | |
91 | MVNETA_DEF_RXQ_UDP(q) | \ | |
92 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
93 | MVNETA_TX_UNSET_ERR_SUM | \ | |
94 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
95 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
96 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
97 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
98 | #define MVNETA_SDMA_CONFIG 0x241c | |
99 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
c5aff182 TP |
100 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
101 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
102 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
9ad8fef6 | 103 | #define MVNETA_DESC_SWAP BIT(6) |
c5aff182 | 104 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
4906887a MC |
105 | #define MVNETA_VLAN_PRIO_TO_RXQ 0x2440 |
106 | #define MVNETA_VLAN_PRIO_RXQ_MAP(prio, rxq) ((rxq) << ((prio) * 3)) | |
c5aff182 TP |
107 | #define MVNETA_PORT_STATUS 0x2444 |
108 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
109 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
110 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
b4748553 | 111 | /* Only exists on Armada XP and Armada 370 */ |
3f1dd4bc | 112 | #define MVNETA_SERDES_CFG 0x24A0 |
5445eaf3 | 113 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 |
3f1dd4bc | 114 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 |
1a642ca7 | 115 | #define MVNETA_HSGMII_SERDES_PROTO 0x1107 |
c5aff182 TP |
116 | #define MVNETA_TYPE_PRIO 0x24bc |
117 | #define MVNETA_FORCE_UNI BIT(21) | |
118 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
119 | #define MVNETA_TXQ_CMD 0x2448 | |
120 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
121 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
e483911f AL |
122 | #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 |
123 | #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 | |
898b2970 SS |
124 | #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 |
125 | #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) | |
c5aff182 | 126 | #define MVNETA_ACC_MODE 0x2500 |
dc35a10f | 127 | #define MVNETA_BM_ADDRESS 0x2504 |
c5aff182 TP |
128 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) |
129 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
130 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
2dcf75e2 | 131 | #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) |
50bf8cb6 | 132 | #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) |
c5aff182 | 133 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) |
40ba35e7 | 134 | |
2dcf75e2 GC |
135 | /* Exception Interrupt Port/Queue Cause register |
136 | * | |
137 | * Their behavior depend of the mapping done using the PCPX2Q | |
138 | * registers. For a given CPU if the bit associated to a queue is not | |
139 | * set, then for the register a read from this CPU will always return | |
140 | * 0 and a write won't do anything | |
141 | */ | |
40ba35e7 | 142 | |
c5aff182 | 143 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
c5aff182 | 144 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
40ba35e7 | 145 | |
146 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
147 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
148 | * bits 16..23 = RXQ FREE, one bit per queue. | |
149 | * bit 29 = OLD_REG_SUM, see old reg ? | |
150 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
151 | * bit 31 = MISC_SUM, one bit for 4 ports | |
152 | */ | |
153 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
154 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
155 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
156 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
898b2970 | 157 | #define MVNETA_MISCINTR_INTR_MASK BIT(31) |
40ba35e7 | 158 | |
c5aff182 TP |
159 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
160 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
40ba35e7 | 161 | |
162 | /* Data Path Port/Queue Cause Register */ | |
c5aff182 TP |
163 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
164 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
40ba35e7 | 165 | |
166 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) | |
167 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) | |
168 | #define MVNETA_CAUSE_PTP BIT(4) | |
169 | ||
170 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) | |
171 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) | |
172 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) | |
173 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) | |
174 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) | |
175 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) | |
176 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) | |
177 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) | |
178 | ||
179 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 | |
180 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) | |
181 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) | |
182 | ||
183 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 | |
184 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) | |
185 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) | |
186 | ||
c5aff182 TP |
187 | #define MVNETA_INTR_ENABLE 0x25b8 |
188 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 | |
dc1aadf6 | 189 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff |
40ba35e7 | 190 | |
c5aff182 TP |
191 | #define MVNETA_RXQ_CMD 0x2680 |
192 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
193 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
194 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
195 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
196 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
197 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
198 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
22f4bf8a | 199 | #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) |
c5aff182 TP |
200 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) |
201 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
898b2970 | 202 | #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) |
a79121d3 | 203 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
c5aff182 TP |
204 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
205 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
206 | #define MVNETA_GMAC_STATUS 0x2c10 | |
207 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
208 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
209 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
210 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
211 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
212 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
213 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
214 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
503f9aa9 RK |
215 | #define MVNETA_GMAC_AN_COMPLETE BIT(11) |
216 | #define MVNETA_GMAC_SYNC_OK BIT(14) | |
c5aff182 TP |
217 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c |
218 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
219 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
898b2970 | 220 | #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) |
22f4bf8a RK |
221 | #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) |
222 | #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) | |
c5aff182 TP |
223 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) |
224 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
71408602 | 225 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
22f4bf8a RK |
226 | #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) |
227 | #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) | |
898b2970 | 228 | #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) |
c5aff182 | 229 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
71408602 | 230 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
da58a931 MC |
231 | #define MVNETA_GMAC_CTRL_4 0x2c90 |
232 | #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) | |
e483911f | 233 | #define MVNETA_MIB_COUNTERS_BASE 0x3000 |
c5aff182 TP |
234 | #define MVNETA_MIB_LATE_COLLISION 0x7c |
235 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
236 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
237 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
238 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
239 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
240 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
241 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
242 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
243 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
2a90f7e1 | 244 | #define MVNETA_TXQ_DEC_SENT_MASK 0xff |
c5aff182 TP |
245 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) |
246 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
247 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
248 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
249 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
250 | #define MVNETA_TX_MTU 0x3e0c | |
251 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
252 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
253 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
254 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
255 | ||
6d81f451 RK |
256 | #define MVNETA_LPI_CTRL_0 0x2cc0 |
257 | #define MVNETA_LPI_CTRL_1 0x2cc4 | |
258 | #define MVNETA_LPI_REQUEST_ENABLE BIT(0) | |
259 | #define MVNETA_LPI_CTRL_2 0x2cc8 | |
260 | #define MVNETA_LPI_STATUS 0x2ccc | |
261 | ||
c5aff182 TP |
262 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff |
263 | ||
264 | /* Descriptor ring Macros */ | |
265 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
266 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
267 | ||
268 | /* Various constants */ | |
269 | ||
270 | /* Coalescing */ | |
06708f81 | 271 | #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ |
c5aff182 TP |
272 | #define MVNETA_RX_COAL_PKTS 32 |
273 | #define MVNETA_RX_COAL_USEC 100 | |
274 | ||
6a20c175 | 275 | /* The two bytes Marvell header. Either contains a special value used |
c5aff182 TP |
276 | * by Marvell switches when a specific hardware mode is enabled (not |
277 | * supported by this driver) or is filled automatically by zeroes on | |
278 | * the RX side. Those two bytes being at the front of the Ethernet | |
279 | * header, they allow to have the IP header aligned on a 4 bytes | |
280 | * boundary automatically: the hardware skips those two bytes on its | |
281 | * own. | |
282 | */ | |
283 | #define MVNETA_MH_SIZE 2 | |
284 | ||
285 | #define MVNETA_VLAN_TAG_LEN 4 | |
286 | ||
9110ee07 | 287 | #define MVNETA_TX_CSUM_DEF_SIZE 1600 |
c5aff182 | 288 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 |
dc35a10f MW |
289 | #define MVNETA_ACC_MODE_EXT1 1 |
290 | #define MVNETA_ACC_MODE_EXT2 2 | |
291 | ||
292 | #define MVNETA_MAX_DECODE_WIN 6 | |
c5aff182 TP |
293 | |
294 | /* Timeout constants */ | |
295 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
296 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
297 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
298 | ||
299 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
300 | ||
9a401dea GC |
301 | /* The RSS lookup table actually has 256 entries but we do not use |
302 | * them yet | |
303 | */ | |
304 | #define MVNETA_RSS_LU_TABLE_SIZE 1 | |
305 | ||
c5aff182 | 306 | /* Max number of Rx descriptors */ |
c307e2a8 | 307 | #define MVNETA_MAX_RXD 512 |
c5aff182 TP |
308 | |
309 | /* Max number of Tx descriptors */ | |
c307e2a8 | 310 | #define MVNETA_MAX_TXD 1024 |
c5aff182 | 311 | |
8eef5f97 EG |
312 | /* Max number of allowed TCP segments for software TSO */ |
313 | #define MVNETA_MAX_TSO_SEGS 100 | |
314 | ||
315 | #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
316 | ||
c5aff182 TP |
317 | /* descriptor aligned size */ |
318 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
319 | ||
8d5047cf MW |
320 | /* Number of bytes to be taken into account by HW when putting incoming data |
321 | * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet | |
322 | * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. | |
323 | */ | |
324 | #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 | |
325 | ||
c5aff182 TP |
326 | #define MVNETA_RX_PKT_SIZE(mtu) \ |
327 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ | |
328 | ETH_HLEN + ETH_FCS_LEN, \ | |
c66e98c9 | 329 | cache_line_size()) |
c5aff182 | 330 | |
ca23cb0b | 331 | /* Driver assumes that the last 3 bits are 0 */ |
e2243720 | 332 | #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) |
8dc9a088 | 333 | #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ |
0db51da7 | 334 | MVNETA_SKB_HEADROOM)) |
8dc9a088 LB |
335 | #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) |
336 | ||
2e3173a3 EG |
337 | #define IS_TSO_HEADER(txq, addr) \ |
338 | ((addr >= txq->tso_hdrs_phys) && \ | |
339 | (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) | |
340 | ||
dc35a10f MW |
341 | #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ |
342 | (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) | |
c5aff182 | 343 | |
6d81f451 RK |
344 | enum { |
345 | ETHTOOL_STAT_EEE_WAKEUP, | |
17a96da6 GC |
346 | ETHTOOL_STAT_SKB_ALLOC_ERR, |
347 | ETHTOOL_STAT_REFILL_ERR, | |
3d866523 LB |
348 | ETHTOOL_XDP_REDIRECT, |
349 | ETHTOOL_XDP_PASS, | |
350 | ETHTOOL_XDP_DROP, | |
351 | ETHTOOL_XDP_TX, | |
15070919 JDB |
352 | ETHTOOL_XDP_TX_ERR, |
353 | ETHTOOL_XDP_XMIT, | |
354 | ETHTOOL_XDP_XMIT_ERR, | |
6d81f451 RK |
355 | ETHTOOL_MAX_STATS, |
356 | }; | |
357 | ||
9b0cdefa RK |
358 | struct mvneta_statistic { |
359 | unsigned short offset; | |
360 | unsigned short type; | |
361 | const char name[ETH_GSTRING_LEN]; | |
362 | }; | |
363 | ||
364 | #define T_REG_32 32 | |
365 | #define T_REG_64 64 | |
6d81f451 | 366 | #define T_SW 1 |
9b0cdefa | 367 | |
6c8a8cfd LB |
368 | #define MVNETA_XDP_PASS 0 |
369 | #define MVNETA_XDP_DROPPED BIT(0) | |
370 | #define MVNETA_XDP_TX BIT(1) | |
371 | #define MVNETA_XDP_REDIR BIT(2) | |
0db51da7 | 372 | |
9b0cdefa RK |
373 | static const struct mvneta_statistic mvneta_statistics[] = { |
374 | { 0x3000, T_REG_64, "good_octets_received", }, | |
375 | { 0x3010, T_REG_32, "good_frames_received", }, | |
376 | { 0x3008, T_REG_32, "bad_octets_received", }, | |
377 | { 0x3014, T_REG_32, "bad_frames_received", }, | |
378 | { 0x3018, T_REG_32, "broadcast_frames_received", }, | |
379 | { 0x301c, T_REG_32, "multicast_frames_received", }, | |
380 | { 0x3050, T_REG_32, "unrec_mac_control_received", }, | |
381 | { 0x3058, T_REG_32, "good_fc_received", }, | |
382 | { 0x305c, T_REG_32, "bad_fc_received", }, | |
383 | { 0x3060, T_REG_32, "undersize_received", }, | |
384 | { 0x3064, T_REG_32, "fragments_received", }, | |
385 | { 0x3068, T_REG_32, "oversize_received", }, | |
386 | { 0x306c, T_REG_32, "jabber_received", }, | |
387 | { 0x3070, T_REG_32, "mac_receive_error", }, | |
388 | { 0x3074, T_REG_32, "bad_crc_event", }, | |
389 | { 0x3078, T_REG_32, "collision", }, | |
390 | { 0x307c, T_REG_32, "late_collision", }, | |
391 | { 0x2484, T_REG_32, "rx_discard", }, | |
392 | { 0x2488, T_REG_32, "rx_overrun", }, | |
393 | { 0x3020, T_REG_32, "frames_64_octets", }, | |
394 | { 0x3024, T_REG_32, "frames_65_to_127_octets", }, | |
395 | { 0x3028, T_REG_32, "frames_128_to_255_octets", }, | |
396 | { 0x302c, T_REG_32, "frames_256_to_511_octets", }, | |
397 | { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, | |
398 | { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, | |
399 | { 0x3038, T_REG_64, "good_octets_sent", }, | |
400 | { 0x3040, T_REG_32, "good_frames_sent", }, | |
401 | { 0x3044, T_REG_32, "excessive_collision", }, | |
402 | { 0x3048, T_REG_32, "multicast_frames_sent", }, | |
403 | { 0x304c, T_REG_32, "broadcast_frames_sent", }, | |
404 | { 0x3054, T_REG_32, "fc_sent", }, | |
405 | { 0x300c, T_REG_32, "internal_mac_transmit_err", }, | |
6d81f451 | 406 | { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, |
17a96da6 GC |
407 | { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, |
408 | { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, | |
7d51a015 LB |
409 | { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", }, |
410 | { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", }, | |
411 | { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", }, | |
412 | { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", }, | |
15070919 | 413 | { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", }, |
7d51a015 | 414 | { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", }, |
15070919 | 415 | { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", }, |
9b0cdefa RK |
416 | }; |
417 | ||
320d5441 LB |
418 | struct mvneta_stats { |
419 | u64 rx_packets; | |
420 | u64 rx_bytes; | |
421 | u64 tx_packets; | |
422 | u64 tx_bytes; | |
3d866523 LB |
423 | /* xdp */ |
424 | u64 xdp_redirect; | |
425 | u64 xdp_pass; | |
426 | u64 xdp_drop; | |
7d51a015 | 427 | u64 xdp_xmit; |
15070919 | 428 | u64 xdp_xmit_err; |
3d866523 | 429 | u64 xdp_tx; |
15070919 | 430 | u64 xdp_tx_err; |
320d5441 LB |
431 | }; |
432 | ||
9ac41f3c | 433 | struct mvneta_ethtool_stats { |
320d5441 | 434 | struct mvneta_stats ps; |
9ac41f3c LB |
435 | u64 skb_alloc_error; |
436 | u64 refill_error; | |
437 | }; | |
438 | ||
74c41b04 | 439 | struct mvneta_pcpu_stats { |
9ac41f3c LB |
440 | struct u64_stats_sync syncp; |
441 | ||
442 | struct mvneta_ethtool_stats es; | |
c35947b8 LB |
443 | u64 rx_dropped; |
444 | u64 rx_errors; | |
c5aff182 TP |
445 | }; |
446 | ||
12bb03b4 MR |
447 | struct mvneta_pcpu_port { |
448 | /* Pointer to the shared port */ | |
449 | struct mvneta_port *pp; | |
450 | ||
451 | /* Pointer to the CPU-local NAPI struct */ | |
452 | struct napi_struct napi; | |
453 | ||
454 | /* Cause of the previous interrupt */ | |
455 | u32 cause_rx_tx; | |
456 | }; | |
457 | ||
62a502cc LB |
458 | enum { |
459 | __MVNETA_DOWN, | |
460 | }; | |
461 | ||
c5aff182 | 462 | struct mvneta_port { |
dc35a10f | 463 | u8 id; |
12bb03b4 MR |
464 | struct mvneta_pcpu_port __percpu *ports; |
465 | struct mvneta_pcpu_stats __percpu *stats; | |
466 | ||
62a502cc LB |
467 | unsigned long state; |
468 | ||
c5aff182 TP |
469 | int pkt_size; |
470 | void __iomem *base; | |
471 | struct mvneta_rx_queue *rxqs; | |
472 | struct mvneta_tx_queue *txqs; | |
c5aff182 | 473 | struct net_device *dev; |
84a3f4db SAS |
474 | struct hlist_node node_online; |
475 | struct hlist_node node_dead; | |
90b74c01 | 476 | int rxq_def; |
5888511e GC |
477 | /* Protect the access to the percpu interrupt registers, |
478 | * ensuring that the configuration remains coherent. | |
479 | */ | |
480 | spinlock_t lock; | |
120cfa50 | 481 | bool is_stopped; |
c5aff182 | 482 | |
2636ac3c MW |
483 | u32 cause_rx_tx; |
484 | struct napi_struct napi; | |
485 | ||
0db51da7 LB |
486 | struct bpf_prog *xdp_prog; |
487 | ||
c5aff182 | 488 | /* Core clock */ |
189dd626 | 489 | struct clk *clk; |
15cc4a4a JZ |
490 | /* AXI clock */ |
491 | struct clk *clk_bus; | |
c5aff182 TP |
492 | u8 mcast_count[256]; |
493 | u16 tx_ring_size; | |
494 | u16 rx_ring_size; | |
4906887a | 495 | u8 prio_tc_map[8]; |
c5aff182 | 496 | |
c5aff182 | 497 | phy_interface_t phy_interface; |
503f9aa9 | 498 | struct device_node *dn; |
b65657fc | 499 | unsigned int tx_csum_limit; |
503f9aa9 | 500 | struct phylink *phylink; |
44cc27e4 | 501 | struct phylink_config phylink_config; |
a10c1c81 | 502 | struct phy *comphy; |
9b0cdefa | 503 | |
dc35a10f MW |
504 | struct mvneta_bm *bm_priv; |
505 | struct mvneta_bm_pool *pool_long; | |
506 | struct mvneta_bm_pool *pool_short; | |
507 | int bm_win_id; | |
508 | ||
6d81f451 RK |
509 | bool eee_enabled; |
510 | bool eee_active; | |
511 | bool tx_lpi_enabled; | |
512 | ||
9b0cdefa | 513 | u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; |
9a401dea GC |
514 | |
515 | u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; | |
2636ac3c MW |
516 | |
517 | /* Flags for special SoC configurations */ | |
518 | bool neta_armada3700; | |
8d5047cf | 519 | u16 rx_offset_correction; |
9768b45c | 520 | const struct mbus_dram_target_info *dram_target_info; |
c5aff182 TP |
521 | }; |
522 | ||
6a20c175 | 523 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
c5aff182 TP |
524 | * layout of the transmit and reception DMA descriptors, and their |
525 | * layout is therefore defined by the hardware design | |
526 | */ | |
6083ed44 | 527 | |
c5aff182 TP |
528 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
529 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
530 | #define MVNETA_TX_L4_UDP BIT(16) | |
531 | #define MVNETA_TX_L3_IP6 BIT(17) | |
532 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
533 | #define MVNETA_TXD_Z_PAD BIT(19) | |
534 | #define MVNETA_TXD_L_DESC BIT(20) | |
535 | #define MVNETA_TXD_F_DESC BIT(21) | |
536 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
537 | MVNETA_TXD_L_DESC | \ | |
538 | MVNETA_TXD_F_DESC) | |
539 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
540 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
541 | ||
c5aff182 | 542 | #define MVNETA_RXD_ERR_CRC 0x0 |
dc35a10f MW |
543 | #define MVNETA_RXD_BM_POOL_SHIFT 13 |
544 | #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) | |
c5aff182 TP |
545 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) |
546 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
547 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
548 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
549 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
550 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
562e2f46 YK |
551 | #define MVNETA_RXD_LAST_DESC BIT(26) |
552 | #define MVNETA_RXD_FIRST_DESC BIT(27) | |
553 | #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ | |
554 | MVNETA_RXD_LAST_DESC) | |
c5aff182 TP |
555 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) |
556 | ||
9ad8fef6 | 557 | #if defined(__LITTLE_ENDIAN) |
6083ed44 TP |
558 | struct mvneta_tx_desc { |
559 | u32 command; /* Options used by HW for packet transmitting.*/ | |
fbd1d524 | 560 | u16 reserved1; /* csum_l4 (for future use) */ |
6083ed44 TP |
561 | u16 data_size; /* Data size of transmitted packet in bytes */ |
562 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
563 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
564 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
565 | }; | |
566 | ||
567 | struct mvneta_rx_desc { | |
568 | u32 status; /* Info about received packet */ | |
c5aff182 TP |
569 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
570 | u16 data_size; /* Size of received packet in bytes */ | |
6083ed44 | 571 | |
c5aff182 TP |
572 | u32 buf_phys_addr; /* Physical address of the buffer */ |
573 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
6083ed44 | 574 | |
c5aff182 TP |
575 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
576 | u16 reserved3; /* prefetch_cmd, for future use */ | |
577 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
6083ed44 | 578 | |
c5aff182 TP |
579 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
580 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
581 | }; | |
9ad8fef6 TP |
582 | #else |
583 | struct mvneta_tx_desc { | |
584 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
fbd1d524 | 585 | u16 reserved1; /* csum_l4 (for future use) */ |
9ad8fef6 TP |
586 | u32 command; /* Options used by HW for packet transmitting.*/ |
587 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
588 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
589 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
590 | }; | |
591 | ||
592 | struct mvneta_rx_desc { | |
593 | u16 data_size; /* Size of received packet in bytes */ | |
594 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
595 | u32 status; /* Info about received packet */ | |
596 | ||
597 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
598 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
599 | ||
600 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
601 | u16 reserved3; /* prefetch_cmd, for future use */ | |
602 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
603 | ||
604 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
605 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
606 | }; | |
607 | #endif | |
c5aff182 | 608 | |
9e58c8b4 LB |
609 | enum mvneta_tx_buf_type { |
610 | MVNETA_TYPE_SKB, | |
611 | MVNETA_TYPE_XDP_TX, | |
612 | MVNETA_TYPE_XDP_NDO, | |
613 | }; | |
614 | ||
615 | struct mvneta_tx_buf { | |
616 | enum mvneta_tx_buf_type type; | |
617 | union { | |
618 | struct xdp_frame *xdpf; | |
619 | struct sk_buff *skb; | |
620 | }; | |
621 | }; | |
622 | ||
c5aff182 TP |
623 | struct mvneta_tx_queue { |
624 | /* Number of this TX queue, in the range 0-7 */ | |
625 | u8 id; | |
626 | ||
627 | /* Number of TX DMA descriptors in the descriptor ring */ | |
628 | int size; | |
629 | ||
630 | /* Number of currently used TX DMA descriptor in the | |
6a20c175 TP |
631 | * descriptor ring |
632 | */ | |
c5aff182 | 633 | int count; |
2a90f7e1 | 634 | int pending; |
8eef5f97 EG |
635 | int tx_stop_threshold; |
636 | int tx_wake_threshold; | |
c5aff182 | 637 | |
9e58c8b4 LB |
638 | /* Array of transmitted buffers */ |
639 | struct mvneta_tx_buf *buf; | |
c5aff182 TP |
640 | |
641 | /* Index of last TX DMA descriptor that was inserted */ | |
642 | int txq_put_index; | |
643 | ||
644 | /* Index of the TX DMA descriptor to be cleaned up */ | |
645 | int txq_get_index; | |
646 | ||
647 | u32 done_pkts_coal; | |
648 | ||
649 | /* Virtual address of the TX DMA descriptors array */ | |
650 | struct mvneta_tx_desc *descs; | |
651 | ||
652 | /* DMA address of the TX DMA descriptors array */ | |
653 | dma_addr_t descs_phys; | |
654 | ||
655 | /* Index of the last TX DMA descriptor */ | |
656 | int last_desc; | |
657 | ||
658 | /* Index of the next TX DMA descriptor to process */ | |
659 | int next_desc_to_proc; | |
2adb719d EG |
660 | |
661 | /* DMA buffers for TSO headers */ | |
662 | char *tso_hdrs; | |
663 | ||
664 | /* DMA address of TSO headers */ | |
665 | dma_addr_t tso_hdrs_phys; | |
50bf8cb6 GC |
666 | |
667 | /* Affinity mask for CPUs*/ | |
668 | cpumask_t affinity_mask; | |
c5aff182 TP |
669 | }; |
670 | ||
671 | struct mvneta_rx_queue { | |
672 | /* rx queue number, in the range 0-7 */ | |
673 | u8 id; | |
674 | ||
675 | /* num of rx descriptors in the rx descriptor ring */ | |
676 | int size; | |
677 | ||
c5aff182 TP |
678 | u32 pkts_coal; |
679 | u32 time_coal; | |
680 | ||
568a3fa2 LB |
681 | /* page_pool */ |
682 | struct page_pool *page_pool; | |
683 | struct xdp_rxq_info xdp_rxq; | |
684 | ||
f88bee1c GC |
685 | /* Virtual address of the RX buffer */ |
686 | void **buf_virt_addr; | |
687 | ||
c5aff182 TP |
688 | /* Virtual address of the RX DMA descriptors array */ |
689 | struct mvneta_rx_desc *descs; | |
690 | ||
691 | /* DMA address of the RX DMA descriptors array */ | |
692 | dma_addr_t descs_phys; | |
693 | ||
694 | /* Index of the last RX DMA descriptor */ | |
695 | int last_desc; | |
696 | ||
697 | /* Index of the next RX DMA descriptor to process */ | |
698 | int next_desc_to_proc; | |
17a96da6 | 699 | |
562e2f46 YK |
700 | /* Index of first RX DMA descriptor to refill */ |
701 | int first_to_refill; | |
702 | u32 refill_num; | |
c5aff182 TP |
703 | }; |
704 | ||
84a3f4db | 705 | static enum cpuhp_state online_hpstate; |
edadb7fa EG |
706 | /* The hardware supports eight (8) rx queues, but we are only allowing |
707 | * the first one to be used. Therefore, let's just allocate one queue. | |
708 | */ | |
d8936657 | 709 | static int rxq_number = 8; |
c5aff182 TP |
710 | static int txq_number = 8; |
711 | ||
712 | static int rxq_def; | |
c5aff182 | 713 | |
f19fadfc | 714 | static int rx_copybreak __read_mostly = 256; |
715 | ||
dc35a10f MW |
716 | /* HW BM need that each port be identify by a unique ID */ |
717 | static int global_port_id; | |
718 | ||
c5aff182 TP |
719 | #define MVNETA_DRIVER_NAME "mvneta" |
720 | #define MVNETA_DRIVER_VERSION "1.0" | |
721 | ||
722 | /* Utility/helper methods */ | |
723 | ||
724 | /* Write helper method */ | |
725 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
726 | { | |
727 | writel(data, pp->base + offset); | |
728 | } | |
729 | ||
730 | /* Read helper method */ | |
731 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
732 | { | |
733 | return readl(pp->base + offset); | |
734 | } | |
735 | ||
736 | /* Increment txq get counter */ | |
737 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) | |
738 | { | |
739 | txq->txq_get_index++; | |
740 | if (txq->txq_get_index == txq->size) | |
741 | txq->txq_get_index = 0; | |
742 | } | |
743 | ||
744 | /* Increment txq put counter */ | |
745 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) | |
746 | { | |
747 | txq->txq_put_index++; | |
748 | if (txq->txq_put_index == txq->size) | |
749 | txq->txq_put_index = 0; | |
750 | } | |
751 | ||
752 | ||
753 | /* Clear all MIB counters */ | |
754 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
755 | { | |
756 | int i; | |
c5aff182 TP |
757 | |
758 | /* Perform dummy reads from MIB counters */ | |
759 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
098c2fc6 ZC |
760 | mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); |
761 | mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); | |
762 | mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); | |
c5aff182 TP |
763 | } |
764 | ||
765 | /* Get System Network Statistics */ | |
bc1f4470 | 766 | static void |
2dc0d2b4 BX |
767 | mvneta_get_stats64(struct net_device *dev, |
768 | struct rtnl_link_stats64 *stats) | |
c5aff182 TP |
769 | { |
770 | struct mvneta_port *pp = netdev_priv(dev); | |
771 | unsigned int start; | |
74c41b04 | 772 | int cpu; |
c5aff182 | 773 | |
74c41b04 | 774 | for_each_possible_cpu(cpu) { |
775 | struct mvneta_pcpu_stats *cpu_stats; | |
776 | u64 rx_packets; | |
777 | u64 rx_bytes; | |
c35947b8 LB |
778 | u64 rx_dropped; |
779 | u64 rx_errors; | |
74c41b04 | 780 | u64 tx_packets; |
781 | u64 tx_bytes; | |
c5aff182 | 782 | |
74c41b04 | 783 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
784 | do { | |
57a7744e | 785 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); |
320d5441 LB |
786 | rx_packets = cpu_stats->es.ps.rx_packets; |
787 | rx_bytes = cpu_stats->es.ps.rx_bytes; | |
c35947b8 LB |
788 | rx_dropped = cpu_stats->rx_dropped; |
789 | rx_errors = cpu_stats->rx_errors; | |
320d5441 LB |
790 | tx_packets = cpu_stats->es.ps.tx_packets; |
791 | tx_bytes = cpu_stats->es.ps.tx_bytes; | |
57a7744e | 792 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); |
c5aff182 | 793 | |
74c41b04 | 794 | stats->rx_packets += rx_packets; |
795 | stats->rx_bytes += rx_bytes; | |
c35947b8 LB |
796 | stats->rx_dropped += rx_dropped; |
797 | stats->rx_errors += rx_errors; | |
74c41b04 | 798 | stats->tx_packets += tx_packets; |
799 | stats->tx_bytes += tx_bytes; | |
800 | } | |
c5aff182 | 801 | |
c5aff182 | 802 | stats->tx_dropped = dev->stats.tx_dropped; |
c5aff182 TP |
803 | } |
804 | ||
805 | /* Rx descriptors helper methods */ | |
806 | ||
5428213c | 807 | /* Checks whether the RX descriptor having this status is both the first |
808 | * and the last descriptor for the RX packet. Each RX packet is currently | |
c5aff182 TP |
809 | * received through a single RX descriptor, so not having each RX |
810 | * descriptor with its first and last bits set is an error | |
811 | */ | |
5428213c | 812 | static int mvneta_rxq_desc_is_first_last(u32 status) |
c5aff182 | 813 | { |
5428213c | 814 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == |
c5aff182 TP |
815 | MVNETA_RXD_FIRST_LAST_DESC; |
816 | } | |
817 | ||
818 | /* Add number of descriptors ready to receive new packets */ | |
819 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
820 | struct mvneta_rx_queue *rxq, | |
821 | int ndescs) | |
822 | { | |
823 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
6a20c175 TP |
824 | * be added at once |
825 | */ | |
c5aff182 TP |
826 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
827 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
828 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
829 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
830 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
831 | } | |
832 | ||
833 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
834 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
835 | } | |
836 | ||
837 | /* Get number of RX descriptors occupied by received packets */ | |
838 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
839 | struct mvneta_rx_queue *rxq) | |
840 | { | |
841 | u32 val; | |
842 | ||
843 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
844 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
845 | } | |
846 | ||
6a20c175 | 847 | /* Update num of rx desc called upon return from rx path or |
c5aff182 TP |
848 | * from mvneta_rxq_drop_pkts(). |
849 | */ | |
850 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
851 | struct mvneta_rx_queue *rxq, | |
852 | int rx_done, int rx_filled) | |
853 | { | |
854 | u32 val; | |
855 | ||
856 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
857 | val = rx_done | | |
858 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
859 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
860 | return; | |
861 | } | |
862 | ||
863 | /* Only 255 descriptors can be added at once */ | |
864 | while ((rx_done > 0) || (rx_filled > 0)) { | |
865 | if (rx_done <= 0xff) { | |
866 | val = rx_done; | |
867 | rx_done = 0; | |
868 | } else { | |
869 | val = 0xff; | |
870 | rx_done -= 0xff; | |
871 | } | |
872 | if (rx_filled <= 0xff) { | |
873 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
874 | rx_filled = 0; | |
875 | } else { | |
876 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
877 | rx_filled -= 0xff; | |
878 | } | |
879 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
880 | } | |
881 | } | |
882 | ||
883 | /* Get pointer to next RX descriptor to be processed by SW */ | |
884 | static struct mvneta_rx_desc * | |
885 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
886 | { | |
887 | int rx_desc = rxq->next_desc_to_proc; | |
888 | ||
889 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
34e4179d | 890 | prefetch(rxq->descs + rxq->next_desc_to_proc); |
c5aff182 TP |
891 | return rxq->descs + rx_desc; |
892 | } | |
893 | ||
894 | /* Change maximum receive size of the port. */ | |
895 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) | |
896 | { | |
897 | u32 val; | |
898 | ||
899 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
900 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; | |
901 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << | |
902 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; | |
903 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
904 | } | |
905 | ||
906 | ||
907 | /* Set rx queue offset */ | |
908 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, | |
909 | struct mvneta_rx_queue *rxq, | |
910 | int offset) | |
911 | { | |
912 | u32 val; | |
913 | ||
914 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
915 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; | |
916 | ||
917 | /* Offset is in */ | |
918 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); | |
919 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
920 | } | |
921 | ||
922 | ||
923 | /* Tx descriptors helper methods */ | |
924 | ||
925 | /* Update HW with number of TX descriptors to be sent */ | |
926 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
927 | struct mvneta_tx_queue *txq, | |
928 | int pend_desc) | |
929 | { | |
930 | u32 val; | |
931 | ||
0d63785c SG |
932 | pend_desc += txq->pending; |
933 | ||
934 | /* Only 255 Tx descriptors can be added at once */ | |
935 | do { | |
936 | val = min(pend_desc, 255); | |
937 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
938 | pend_desc -= val; | |
939 | } while (pend_desc > 0); | |
2a90f7e1 | 940 | txq->pending = 0; |
c5aff182 TP |
941 | } |
942 | ||
943 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
944 | static struct mvneta_tx_desc * | |
945 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
946 | { | |
947 | int tx_desc = txq->next_desc_to_proc; | |
948 | ||
949 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
950 | return txq->descs + tx_desc; | |
951 | } | |
952 | ||
953 | /* Release the last allocated TX descriptor. Useful to handle DMA | |
6a20c175 TP |
954 | * mapping failures in the TX path. |
955 | */ | |
c5aff182 TP |
956 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
957 | { | |
958 | if (txq->next_desc_to_proc == 0) | |
959 | txq->next_desc_to_proc = txq->last_desc - 1; | |
960 | else | |
961 | txq->next_desc_to_proc--; | |
962 | } | |
963 | ||
964 | /* Set rxq buf size */ | |
965 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
966 | struct mvneta_rx_queue *rxq, | |
967 | int buf_size) | |
968 | { | |
969 | u32 val; | |
970 | ||
971 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
972 | ||
973 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
974 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
975 | ||
976 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
977 | } | |
978 | ||
979 | /* Disable buffer management (BM) */ | |
980 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, | |
981 | struct mvneta_rx_queue *rxq) | |
982 | { | |
983 | u32 val; | |
984 | ||
985 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
986 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; | |
987 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
988 | } | |
989 | ||
dc35a10f MW |
990 | /* Enable buffer management (BM) */ |
991 | static void mvneta_rxq_bm_enable(struct mvneta_port *pp, | |
992 | struct mvneta_rx_queue *rxq) | |
993 | { | |
994 | u32 val; | |
995 | ||
996 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
997 | val |= MVNETA_RXQ_HW_BUF_ALLOC; | |
998 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
999 | } | |
1000 | ||
1001 | /* Notify HW about port's assignment of pool for bigger packets */ | |
1002 | static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, | |
1003 | struct mvneta_rx_queue *rxq) | |
1004 | { | |
1005 | u32 val; | |
1006 | ||
1007 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
1008 | val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; | |
1009 | val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); | |
1010 | ||
1011 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
1012 | } | |
1013 | ||
1014 | /* Notify HW about port's assignment of pool for smaller packets */ | |
1015 | static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, | |
1016 | struct mvneta_rx_queue *rxq) | |
1017 | { | |
1018 | u32 val; | |
1019 | ||
1020 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
1021 | val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; | |
1022 | val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); | |
1023 | ||
1024 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
1025 | } | |
1026 | ||
1027 | /* Set port's receive buffer size for assigned BM pool */ | |
1028 | static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, | |
1029 | int buf_size, | |
1030 | u8 pool_id) | |
1031 | { | |
1032 | u32 val; | |
1033 | ||
1034 | if (!IS_ALIGNED(buf_size, 8)) { | |
1035 | dev_warn(pp->dev->dev.parent, | |
1036 | "illegal buf_size value %d, round to %d\n", | |
1037 | buf_size, ALIGN(buf_size, 8)); | |
1038 | buf_size = ALIGN(buf_size, 8); | |
1039 | } | |
1040 | ||
1041 | val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); | |
1042 | val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; | |
1043 | mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); | |
1044 | } | |
1045 | ||
1046 | /* Configure MBUS window in order to enable access BM internal SRAM */ | |
1047 | static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, | |
1048 | u8 target, u8 attr) | |
1049 | { | |
1050 | u32 win_enable, win_protect; | |
1051 | int i; | |
1052 | ||
1053 | win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); | |
1054 | ||
1055 | if (pp->bm_win_id < 0) { | |
1056 | /* Find first not occupied window */ | |
1057 | for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { | |
1058 | if (win_enable & (1 << i)) { | |
1059 | pp->bm_win_id = i; | |
1060 | break; | |
1061 | } | |
1062 | } | |
1063 | if (i == MVNETA_MAX_DECODE_WIN) | |
1064 | return -ENOMEM; | |
1065 | } else { | |
1066 | i = pp->bm_win_id; | |
1067 | } | |
1068 | ||
1069 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
1070 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
1071 | ||
1072 | if (i < 4) | |
1073 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
1074 | ||
1075 | mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | | |
1076 | (attr << 8) | target); | |
1077 | ||
1078 | mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); | |
1079 | ||
1080 | win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); | |
1081 | win_protect |= 3 << (2 * i); | |
1082 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); | |
1083 | ||
1084 | win_enable &= ~(1 << i); | |
1085 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
9abcaa96 | 1090 | static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) |
dc35a10f | 1091 | { |
2636ac3c | 1092 | u32 wsize; |
dc35a10f MW |
1093 | u8 target, attr; |
1094 | int err; | |
1095 | ||
1096 | /* Get BM window information */ | |
1097 | err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, | |
1098 | &target, &attr); | |
1099 | if (err < 0) | |
1100 | return err; | |
1101 | ||
1102 | pp->bm_win_id = -1; | |
1103 | ||
1104 | /* Open NETA -> BM window */ | |
1105 | err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, | |
1106 | target, attr); | |
1107 | if (err < 0) { | |
1108 | netdev_info(pp->dev, "fail to configure mbus window to BM\n"); | |
1109 | return err; | |
1110 | } | |
2636ac3c MW |
1111 | return 0; |
1112 | } | |
1113 | ||
1114 | /* Assign and initialize pools for port. In case of fail | |
1115 | * buffer manager will remain disabled for current port. | |
1116 | */ | |
1117 | static int mvneta_bm_port_init(struct platform_device *pdev, | |
1118 | struct mvneta_port *pp) | |
1119 | { | |
1120 | struct device_node *dn = pdev->dev.of_node; | |
1121 | u32 long_pool_id, short_pool_id; | |
1122 | ||
1123 | if (!pp->neta_armada3700) { | |
1124 | int ret; | |
1125 | ||
1126 | ret = mvneta_bm_port_mbus_init(pp); | |
1127 | if (ret) | |
1128 | return ret; | |
1129 | } | |
dc35a10f MW |
1130 | |
1131 | if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { | |
1132 | netdev_info(pp->dev, "missing long pool id\n"); | |
1133 | return -EINVAL; | |
1134 | } | |
1135 | ||
1136 | /* Create port's long pool depending on mtu */ | |
1137 | pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, | |
1138 | MVNETA_BM_LONG, pp->id, | |
1139 | MVNETA_RX_PKT_SIZE(pp->dev->mtu)); | |
1140 | if (!pp->pool_long) { | |
1141 | netdev_info(pp->dev, "fail to obtain long pool for port\n"); | |
1142 | return -ENOMEM; | |
1143 | } | |
1144 | ||
1145 | pp->pool_long->port_map |= 1 << pp->id; | |
1146 | ||
1147 | mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, | |
1148 | pp->pool_long->id); | |
1149 | ||
1150 | /* If short pool id is not defined, assume using single pool */ | |
1151 | if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) | |
1152 | short_pool_id = long_pool_id; | |
1153 | ||
1154 | /* Create port's short pool */ | |
1155 | pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, | |
1156 | MVNETA_BM_SHORT, pp->id, | |
1157 | MVNETA_BM_SHORT_PKT_SIZE); | |
1158 | if (!pp->pool_short) { | |
1159 | netdev_info(pp->dev, "fail to obtain short pool for port\n"); | |
1160 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1161 | return -ENOMEM; | |
1162 | } | |
1163 | ||
1164 | if (short_pool_id != long_pool_id) { | |
1165 | pp->pool_short->port_map |= 1 << pp->id; | |
1166 | mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, | |
1167 | pp->pool_short->id); | |
1168 | } | |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
1173 | /* Update settings of a pool for bigger packets */ | |
1174 | static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) | |
1175 | { | |
1176 | struct mvneta_bm_pool *bm_pool = pp->pool_long; | |
baa11ebc | 1177 | struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; |
dc35a10f MW |
1178 | int num; |
1179 | ||
1180 | /* Release all buffers from long pool */ | |
1181 | mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); | |
baa11ebc | 1182 | if (hwbm_pool->buf_num) { |
dc35a10f MW |
1183 | WARN(1, "cannot free all buffers in pool %d\n", |
1184 | bm_pool->id); | |
1185 | goto bm_mtu_err; | |
1186 | } | |
1187 | ||
1188 | bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); | |
1189 | bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); | |
baa11ebc GC |
1190 | hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + |
1191 | SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); | |
dc35a10f MW |
1192 | |
1193 | /* Fill entire long pool */ | |
6dcdd884 | 1194 | num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); |
baa11ebc | 1195 | if (num != hwbm_pool->size) { |
dc35a10f | 1196 | WARN(1, "pool %d: %d of %d allocated\n", |
baa11ebc | 1197 | bm_pool->id, num, hwbm_pool->size); |
dc35a10f MW |
1198 | goto bm_mtu_err; |
1199 | } | |
1200 | mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); | |
1201 | ||
1202 | return; | |
1203 | ||
1204 | bm_mtu_err: | |
1205 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1206 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); | |
1207 | ||
1208 | pp->bm_priv = NULL; | |
44efc78d | 1209 | pp->rx_offset_correction = MVNETA_SKB_HEADROOM; |
dc35a10f MW |
1210 | mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); |
1211 | netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); | |
1212 | } | |
1213 | ||
c5aff182 TP |
1214 | /* Start the Ethernet port RX and TX activity */ |
1215 | static void mvneta_port_up(struct mvneta_port *pp) | |
1216 | { | |
1217 | int queue; | |
1218 | u32 q_map; | |
1219 | ||
1220 | /* Enable all initialized TXs. */ | |
c5aff182 TP |
1221 | q_map = 0; |
1222 | for (queue = 0; queue < txq_number; queue++) { | |
1223 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
f95936cc | 1224 | if (txq->descs) |
c5aff182 TP |
1225 | q_map |= (1 << queue); |
1226 | } | |
1227 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
1228 | ||
e81b5e01 | 1229 | q_map = 0; |
c5aff182 | 1230 | /* Enable all initialized RXQs. */ |
2dcf75e2 GC |
1231 | for (queue = 0; queue < rxq_number; queue++) { |
1232 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
1233 | ||
f95936cc | 1234 | if (rxq->descs) |
2dcf75e2 GC |
1235 | q_map |= (1 << queue); |
1236 | } | |
1237 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
c5aff182 TP |
1238 | } |
1239 | ||
1240 | /* Stop the Ethernet port activity */ | |
1241 | static void mvneta_port_down(struct mvneta_port *pp) | |
1242 | { | |
1243 | u32 val; | |
1244 | int count; | |
1245 | ||
1246 | /* Stop Rx port activity. Check port Rx activity. */ | |
1247 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
1248 | ||
1249 | /* Issue stop command for active channels only */ | |
1250 | if (val != 0) | |
1251 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
1252 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
1253 | ||
1254 | /* Wait for all Rx activity to terminate. */ | |
1255 | count = 0; | |
1256 | do { | |
1257 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
1258 | netdev_warn(pp->dev, | |
0838abb3 | 1259 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", |
c5aff182 TP |
1260 | val); |
1261 | break; | |
1262 | } | |
1263 | mdelay(1); | |
1264 | ||
1265 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
a3703fb3 | 1266 | } while (val & MVNETA_RXQ_ENABLE_MASK); |
c5aff182 TP |
1267 | |
1268 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
6a20c175 TP |
1269 | * command for active channels only |
1270 | */ | |
c5aff182 TP |
1271 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
1272 | ||
1273 | if (val != 0) | |
1274 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
1275 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
1276 | ||
1277 | /* Wait for all Tx activity to terminate. */ | |
1278 | count = 0; | |
1279 | do { | |
1280 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
1281 | netdev_warn(pp->dev, | |
1282 | "TIMEOUT for TX stopped status=0x%08x\n", | |
1283 | val); | |
1284 | break; | |
1285 | } | |
1286 | mdelay(1); | |
1287 | ||
1288 | /* Check TX Command reg that all Txqs are stopped */ | |
1289 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
1290 | ||
a3703fb3 | 1291 | } while (val & MVNETA_TXQ_ENABLE_MASK); |
c5aff182 TP |
1292 | |
1293 | /* Double check to verify that TX FIFO is empty */ | |
1294 | count = 0; | |
1295 | do { | |
1296 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
1297 | netdev_warn(pp->dev, | |
0838abb3 | 1298 | "TX FIFO empty timeout status=0x%08x\n", |
c5aff182 TP |
1299 | val); |
1300 | break; | |
1301 | } | |
1302 | mdelay(1); | |
1303 | ||
1304 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
1305 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
1306 | (val & MVNETA_TX_IN_PRGRS)); | |
1307 | ||
1308 | udelay(200); | |
1309 | } | |
1310 | ||
1311 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
1312 | static void mvneta_port_enable(struct mvneta_port *pp) | |
1313 | { | |
1314 | u32 val; | |
1315 | ||
1316 | /* Enable port */ | |
1317 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1318 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
1319 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1320 | } | |
1321 | ||
1322 | /* Disable the port and wait for about 200 usec before retuning */ | |
1323 | static void mvneta_port_disable(struct mvneta_port *pp) | |
1324 | { | |
1325 | u32 val; | |
1326 | ||
1327 | /* Reset the Enable bit in the Serial Control Register */ | |
1328 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1329 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
1330 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1331 | ||
1332 | udelay(200); | |
1333 | } | |
1334 | ||
1335 | /* Multicast tables methods */ | |
1336 | ||
1337 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
1338 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
1339 | { | |
1340 | int offset; | |
1341 | u32 val; | |
1342 | ||
1343 | if (queue == -1) { | |
1344 | val = 0; | |
1345 | } else { | |
1346 | val = 0x1 | (queue << 1); | |
1347 | val |= (val << 24) | (val << 16) | (val << 8); | |
1348 | } | |
1349 | ||
1350 | for (offset = 0; offset <= 0xc; offset += 4) | |
1351 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
1352 | } | |
1353 | ||
1354 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
1355 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
1356 | { | |
1357 | int offset; | |
1358 | u32 val; | |
1359 | ||
1360 | if (queue == -1) { | |
1361 | val = 0; | |
1362 | } else { | |
1363 | val = 0x1 | (queue << 1); | |
1364 | val |= (val << 24) | (val << 16) | (val << 8); | |
1365 | } | |
1366 | ||
1367 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1368 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
1369 | ||
1370 | } | |
1371 | ||
1372 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
1373 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
1374 | { | |
1375 | int offset; | |
1376 | u32 val; | |
1377 | ||
1378 | if (queue == -1) { | |
1379 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
1380 | val = 0; | |
1381 | } else { | |
1382 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
1383 | val = 0x1 | (queue << 1); | |
1384 | val |= (val << 24) | (val << 16) | (val << 8); | |
1385 | } | |
1386 | ||
1387 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1388 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
1389 | } | |
1390 | ||
db488c10 GC |
1391 | static void mvneta_percpu_unmask_interrupt(void *arg) |
1392 | { | |
1393 | struct mvneta_port *pp = arg; | |
1394 | ||
1395 | /* All the queue are unmasked, but actually only the ones | |
1396 | * mapped to this CPU will be unmasked | |
1397 | */ | |
1398 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
1399 | MVNETA_RX_INTR_MASK_ALL | | |
1400 | MVNETA_TX_INTR_MASK_ALL | | |
1401 | MVNETA_MISCINTR_INTR_MASK); | |
1402 | } | |
1403 | ||
1404 | static void mvneta_percpu_mask_interrupt(void *arg) | |
1405 | { | |
1406 | struct mvneta_port *pp = arg; | |
1407 | ||
1408 | /* All the queue are masked, but actually only the ones | |
1409 | * mapped to this CPU will be masked | |
1410 | */ | |
1411 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
1412 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
1413 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
1414 | } | |
1415 | ||
1416 | static void mvneta_percpu_clear_intr_cause(void *arg) | |
1417 | { | |
1418 | struct mvneta_port *pp = arg; | |
1419 | ||
1420 | /* All the queue are cleared, but actually only the ones | |
1421 | * mapped to this CPU will be cleared | |
1422 | */ | |
1423 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
1424 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
1425 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
1426 | } | |
1427 | ||
c5aff182 TP |
1428 | /* This method sets defaults to the NETA port: |
1429 | * Clears interrupt Cause and Mask registers. | |
1430 | * Clears all MAC tables. | |
1431 | * Sets defaults to all registers. | |
1432 | * Resets RX and TX descriptor rings. | |
1433 | * Resets PHY. | |
1434 | * This method can be called after mvneta_port_down() to return the port | |
1435 | * settings to defaults. | |
1436 | */ | |
1437 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
1438 | { | |
1439 | int cpu; | |
1440 | int queue; | |
1441 | u32 val; | |
2dcf75e2 | 1442 | int max_cpu = num_present_cpus(); |
c5aff182 TP |
1443 | |
1444 | /* Clear all Cause registers */ | |
db488c10 | 1445 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
1446 | |
1447 | /* Mask all interrupts */ | |
db488c10 | 1448 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
1449 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); |
1450 | ||
1451 | /* Enable MBUS Retry bit16 */ | |
1452 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
1453 | ||
50bf8cb6 GC |
1454 | /* Set CPU queue access map. CPUs are assigned to the RX and |
1455 | * TX queues modulo their number. If there is only one TX | |
1456 | * queue then it is assigned to the CPU associated to the | |
1457 | * default RX queue. | |
6a20c175 | 1458 | */ |
2dcf75e2 GC |
1459 | for_each_present_cpu(cpu) { |
1460 | int rxq_map = 0, txq_map = 0; | |
50bf8cb6 | 1461 | int rxq, txq; |
2636ac3c MW |
1462 | if (!pp->neta_armada3700) { |
1463 | for (rxq = 0; rxq < rxq_number; rxq++) | |
1464 | if ((rxq % max_cpu) == cpu) | |
1465 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
1466 | ||
1467 | for (txq = 0; txq < txq_number; txq++) | |
1468 | if ((txq % max_cpu) == cpu) | |
1469 | txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); | |
1470 | ||
1471 | /* With only one TX queue we configure a special case | |
1472 | * which will allow to get all the irq on a single | |
1473 | * CPU | |
1474 | */ | |
1475 | if (txq_number == 1) | |
1476 | txq_map = (cpu == pp->rxq_def) ? | |
1477 | MVNETA_CPU_TXQ_ACCESS(1) : 0; | |
2dcf75e2 | 1478 | |
2636ac3c MW |
1479 | } else { |
1480 | txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
1481 | rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; | |
1482 | } | |
2dcf75e2 GC |
1483 | |
1484 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); | |
1485 | } | |
c5aff182 TP |
1486 | |
1487 | /* Reset RX and TX DMAs */ | |
1488 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
1489 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
1490 | ||
1491 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
1492 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
1493 | for (queue = 0; queue < txq_number; queue++) { | |
1494 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
1495 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
1496 | } | |
1497 | ||
1498 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
1499 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
1500 | ||
1501 | /* Set Port Acceleration Mode */ | |
dc35a10f MW |
1502 | if (pp->bm_priv) |
1503 | /* HW buffer management + legacy parser */ | |
1504 | val = MVNETA_ACC_MODE_EXT2; | |
1505 | else | |
1506 | /* SW buffer management + legacy parser */ | |
1507 | val = MVNETA_ACC_MODE_EXT1; | |
c5aff182 TP |
1508 | mvreg_write(pp, MVNETA_ACC_MODE, val); |
1509 | ||
dc35a10f MW |
1510 | if (pp->bm_priv) |
1511 | mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); | |
1512 | ||
c5aff182 | 1513 | /* Update val of portCfg register accordingly with all RxQueue types */ |
90b74c01 | 1514 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); |
c5aff182 TP |
1515 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); |
1516 | ||
1517 | val = 0; | |
1518 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
1519 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
1520 | ||
1521 | /* Build PORT_SDMA_CONFIG_REG */ | |
1522 | val = 0; | |
1523 | ||
1524 | /* Default burst size */ | |
1525 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
1526 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
9ad8fef6 | 1527 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; |
c5aff182 | 1528 | |
9ad8fef6 TP |
1529 | #if defined(__BIG_ENDIAN) |
1530 | val |= MVNETA_DESC_SWAP; | |
1531 | #endif | |
c5aff182 TP |
1532 | |
1533 | /* Assign port SDMA configuration */ | |
1534 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
1535 | ||
71408602 TP |
1536 | /* Disable PHY polling in hardware, since we're using the |
1537 | * kernel phylib to do this. | |
1538 | */ | |
1539 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
1540 | val &= ~MVNETA_PHY_POLLING_ENABLE; | |
1541 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
1542 | ||
c5aff182 TP |
1543 | mvneta_set_ucast_table(pp, -1); |
1544 | mvneta_set_special_mcast_table(pp, -1); | |
1545 | mvneta_set_other_mcast_table(pp, -1); | |
1546 | ||
1547 | /* Set port interrupt enable register - default enable all */ | |
1548 | mvreg_write(pp, MVNETA_INTR_ENABLE, | |
1549 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK | |
1550 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); | |
e483911f AL |
1551 | |
1552 | mvneta_mib_counters_clear(pp); | |
c5aff182 TP |
1553 | } |
1554 | ||
1555 | /* Set max sizes for tx queues */ | |
1556 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) | |
1557 | ||
1558 | { | |
1559 | u32 val, size, mtu; | |
1560 | int queue; | |
1561 | ||
1562 | mtu = max_tx_size * 8; | |
1563 | if (mtu > MVNETA_TX_MTU_MAX) | |
1564 | mtu = MVNETA_TX_MTU_MAX; | |
1565 | ||
1566 | /* Set MTU */ | |
1567 | val = mvreg_read(pp, MVNETA_TX_MTU); | |
1568 | val &= ~MVNETA_TX_MTU_MAX; | |
1569 | val |= mtu; | |
1570 | mvreg_write(pp, MVNETA_TX_MTU, val); | |
1571 | ||
1572 | /* TX token size and all TXQs token size must be larger that MTU */ | |
1573 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); | |
1574 | ||
1575 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; | |
1576 | if (size < mtu) { | |
1577 | size = mtu; | |
1578 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; | |
1579 | val |= size; | |
1580 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); | |
1581 | } | |
1582 | for (queue = 0; queue < txq_number; queue++) { | |
1583 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); | |
1584 | ||
1585 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1586 | if (size < mtu) { | |
1587 | size = mtu; | |
1588 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1589 | val |= size; | |
1590 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); | |
1591 | } | |
1592 | } | |
1593 | } | |
1594 | ||
1595 | /* Set unicast address */ | |
1596 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
1597 | int queue) | |
1598 | { | |
1599 | unsigned int unicast_reg; | |
1600 | unsigned int tbl_offset; | |
1601 | unsigned int reg_offset; | |
1602 | ||
1603 | /* Locate the Unicast table entry */ | |
1604 | last_nibble = (0xf & last_nibble); | |
1605 | ||
1606 | /* offset from unicast tbl base */ | |
1607 | tbl_offset = (last_nibble / 4) * 4; | |
1608 | ||
1609 | /* offset within the above reg */ | |
1610 | reg_offset = last_nibble % 4; | |
1611 | ||
1612 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
1613 | ||
1614 | if (queue == -1) { | |
1615 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
1616 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1617 | } else { | |
1618 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1619 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1620 | } | |
1621 | ||
1622 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
1623 | } | |
1624 | ||
1625 | /* Set mac address */ | |
1626 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
1627 | int queue) | |
1628 | { | |
1629 | unsigned int mac_h; | |
1630 | unsigned int mac_l; | |
1631 | ||
1632 | if (queue != -1) { | |
1633 | mac_l = (addr[4] << 8) | (addr[5]); | |
1634 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
1635 | (addr[2] << 8) | (addr[3] << 0); | |
1636 | ||
1637 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
1638 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
1639 | } | |
1640 | ||
1641 | /* Accept frames of this address */ | |
1642 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
1643 | } | |
1644 | ||
6a20c175 TP |
1645 | /* Set the number of packets that will be received before RX interrupt |
1646 | * will be generated by HW. | |
c5aff182 TP |
1647 | */ |
1648 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, | |
1649 | struct mvneta_rx_queue *rxq, u32 value) | |
1650 | { | |
1651 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), | |
1652 | value | MVNETA_RXQ_NON_OCCUPIED(0)); | |
c5aff182 TP |
1653 | } |
1654 | ||
6a20c175 TP |
1655 | /* Set the time delay in usec before RX interrupt will be generated by |
1656 | * HW. | |
c5aff182 TP |
1657 | */ |
1658 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, | |
1659 | struct mvneta_rx_queue *rxq, u32 value) | |
1660 | { | |
189dd626 TP |
1661 | u32 val; |
1662 | unsigned long clk_rate; | |
1663 | ||
1664 | clk_rate = clk_get_rate(pp->clk); | |
1665 | val = (clk_rate / 1000000) * value; | |
c5aff182 TP |
1666 | |
1667 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); | |
c5aff182 TP |
1668 | } |
1669 | ||
1670 | /* Set threshold for TX_DONE pkts coalescing */ | |
1671 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, | |
1672 | struct mvneta_tx_queue *txq, u32 value) | |
1673 | { | |
1674 | u32 val; | |
1675 | ||
1676 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); | |
1677 | ||
1678 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; | |
1679 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); | |
1680 | ||
1681 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); | |
c5aff182 TP |
1682 | } |
1683 | ||
c5aff182 TP |
1684 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
1685 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
f88bee1c GC |
1686 | u32 phys_addr, void *virt_addr, |
1687 | struct mvneta_rx_queue *rxq) | |
c5aff182 | 1688 | { |
f88bee1c GC |
1689 | int i; |
1690 | ||
c5aff182 | 1691 | rx_desc->buf_phys_addr = phys_addr; |
f88bee1c GC |
1692 | i = rx_desc - rxq->descs; |
1693 | rxq->buf_virt_addr[i] = virt_addr; | |
c5aff182 TP |
1694 | } |
1695 | ||
1696 | /* Decrement sent descriptors counter */ | |
1697 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
1698 | struct mvneta_tx_queue *txq, | |
1699 | int sent_desc) | |
1700 | { | |
1701 | u32 val; | |
1702 | ||
1703 | /* Only 255 TX descriptors can be updated at once */ | |
1704 | while (sent_desc > 0xff) { | |
1705 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1706 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1707 | sent_desc = sent_desc - 0xff; | |
1708 | } | |
1709 | ||
1710 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1711 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1712 | } | |
1713 | ||
1714 | /* Get number of TX descriptors already sent by HW */ | |
1715 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
1716 | struct mvneta_tx_queue *txq) | |
1717 | { | |
1718 | u32 val; | |
1719 | int sent_desc; | |
1720 | ||
1721 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
1722 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
1723 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
1724 | ||
1725 | return sent_desc; | |
1726 | } | |
1727 | ||
6a20c175 | 1728 | /* Get number of sent descriptors and decrement counter. |
c5aff182 TP |
1729 | * The number of sent descriptors is returned. |
1730 | */ | |
1731 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, | |
1732 | struct mvneta_tx_queue *txq) | |
1733 | { | |
1734 | int sent_desc; | |
1735 | ||
1736 | /* Get number of sent descriptors */ | |
1737 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1738 | ||
1739 | /* Decrement sent descriptors counter */ | |
1740 | if (sent_desc) | |
1741 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
1742 | ||
1743 | return sent_desc; | |
1744 | } | |
1745 | ||
1746 | /* Set TXQ descriptors fields relevant for CSUM calculation */ | |
1747 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, | |
1748 | int ip_hdr_len, int l4_proto) | |
1749 | { | |
1750 | u32 command; | |
1751 | ||
1752 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
6a20c175 TP |
1753 | * G_L4_chk, L4_type; required only for checksum |
1754 | * calculation | |
1755 | */ | |
c5aff182 TP |
1756 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
1757 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; | |
1758 | ||
0a198587 | 1759 | if (l3_proto == htons(ETH_P_IP)) |
c5aff182 TP |
1760 | command |= MVNETA_TXD_IP_CSUM; |
1761 | else | |
1762 | command |= MVNETA_TX_L3_IP6; | |
1763 | ||
1764 | if (l4_proto == IPPROTO_TCP) | |
1765 | command |= MVNETA_TX_L4_CSUM_FULL; | |
1766 | else if (l4_proto == IPPROTO_UDP) | |
1767 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; | |
1768 | else | |
1769 | command |= MVNETA_TX_L4_CSUM_NOT; | |
1770 | ||
1771 | return command; | |
1772 | } | |
1773 | ||
1774 | ||
1775 | /* Display more error info */ | |
1776 | static void mvneta_rx_error(struct mvneta_port *pp, | |
1777 | struct mvneta_rx_desc *rx_desc) | |
1778 | { | |
c35947b8 | 1779 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
c5aff182 TP |
1780 | u32 status = rx_desc->status; |
1781 | ||
c35947b8 LB |
1782 | /* update per-cpu counter */ |
1783 | u64_stats_update_begin(&stats->syncp); | |
1784 | stats->rx_errors++; | |
1785 | u64_stats_update_end(&stats->syncp); | |
1786 | ||
c5aff182 TP |
1787 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { |
1788 | case MVNETA_RXD_ERR_CRC: | |
1789 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
1790 | status, rx_desc->data_size); | |
1791 | break; | |
1792 | case MVNETA_RXD_ERR_OVERRUN: | |
1793 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
1794 | status, rx_desc->data_size); | |
1795 | break; | |
1796 | case MVNETA_RXD_ERR_LEN: | |
1797 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
1798 | status, rx_desc->data_size); | |
1799 | break; | |
1800 | case MVNETA_RXD_ERR_RESOURCE: | |
1801 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
1802 | status, rx_desc->data_size); | |
1803 | break; | |
1804 | } | |
1805 | } | |
1806 | ||
5428213c | 1807 | /* Handle RX checksum offload based on the descriptor's status */ |
aff0824d | 1808 | static int mvneta_rx_csum(struct mvneta_port *pp, u32 status) |
c5aff182 | 1809 | { |
f945cec8 YK |
1810 | if ((pp->dev->features & NETIF_F_RXCSUM) && |
1811 | (status & MVNETA_RXD_L3_IP4) && | |
aff0824d LB |
1812 | (status & MVNETA_RXD_L4_CSUM_OK)) |
1813 | return CHECKSUM_UNNECESSARY; | |
c5aff182 | 1814 | |
aff0824d | 1815 | return CHECKSUM_NONE; |
c5aff182 TP |
1816 | } |
1817 | ||
6c498974 | 1818 | /* Return tx queue pointer (find last set bit) according to <cause> returned |
1819 | * form tx_done reg. <cause> must not be null. The return value is always a | |
1820 | * valid queue for matching the first one found in <cause>. | |
1821 | */ | |
c5aff182 TP |
1822 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
1823 | u32 cause) | |
1824 | { | |
1825 | int queue = fls(cause) - 1; | |
1826 | ||
6c498974 | 1827 | return &pp->txqs[queue]; |
c5aff182 TP |
1828 | } |
1829 | ||
1830 | /* Free tx queue skbuffs */ | |
1831 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, | |
a29b6235 | 1832 | struct mvneta_tx_queue *txq, int num, |
632bb64f | 1833 | struct netdev_queue *nq, bool napi) |
c5aff182 | 1834 | { |
a29b6235 | 1835 | unsigned int bytes_compl = 0, pkts_compl = 0; |
2f9d0939 | 1836 | struct xdp_frame_bulk bq; |
c5aff182 TP |
1837 | int i; |
1838 | ||
2f9d0939 LB |
1839 | xdp_frame_bulk_init(&bq); |
1840 | ||
1841 | rcu_read_lock(); /* need for xdp_return_frame_bulk */ | |
1842 | ||
c5aff182 | 1843 | for (i = 0; i < num; i++) { |
9e58c8b4 | 1844 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; |
c5aff182 TP |
1845 | struct mvneta_tx_desc *tx_desc = txq->descs + |
1846 | txq->txq_get_index; | |
a29b6235 | 1847 | |
c5aff182 TP |
1848 | mvneta_txq_inc_get(txq); |
1849 | ||
b0a43db9 LB |
1850 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && |
1851 | buf->type != MVNETA_TYPE_XDP_TX) | |
2e3173a3 EG |
1852 | dma_unmap_single(pp->dev->dev.parent, |
1853 | tx_desc->buf_phys_addr, | |
1854 | tx_desc->data_size, DMA_TO_DEVICE); | |
b0a43db9 LB |
1855 | if (buf->type == MVNETA_TYPE_SKB && buf->skb) { |
1856 | bytes_compl += buf->skb->len; | |
1857 | pkts_compl++; | |
1858 | dev_kfree_skb_any(buf->skb); | |
1859 | } else if (buf->type == MVNETA_TYPE_XDP_TX || | |
1860 | buf->type == MVNETA_TYPE_XDP_NDO) { | |
632bb64f LB |
1861 | if (napi && buf->type == MVNETA_TYPE_XDP_TX) |
1862 | xdp_return_frame_rx_napi(buf->xdpf); | |
1863 | else | |
2f9d0939 | 1864 | xdp_return_frame_bulk(buf->xdpf, &bq); |
b0a43db9 | 1865 | } |
c5aff182 | 1866 | } |
2f9d0939 LB |
1867 | xdp_flush_frame_bulk(&bq); |
1868 | ||
1869 | rcu_read_unlock(); | |
a29b6235 MW |
1870 | |
1871 | netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); | |
c5aff182 TP |
1872 | } |
1873 | ||
1874 | /* Handle end of transmission */ | |
cd713199 | 1875 | static void mvneta_txq_done(struct mvneta_port *pp, |
c5aff182 TP |
1876 | struct mvneta_tx_queue *txq) |
1877 | { | |
1878 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1879 | int tx_done; | |
1880 | ||
1881 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); | |
cd713199 AE |
1882 | if (!tx_done) |
1883 | return; | |
1884 | ||
632bb64f | 1885 | mvneta_txq_bufs_free(pp, txq, tx_done, nq, true); |
c5aff182 TP |
1886 | |
1887 | txq->count -= tx_done; | |
1888 | ||
1889 | if (netif_tx_queue_stopped(nq)) { | |
8eef5f97 | 1890 | if (txq->count <= txq->tx_wake_threshold) |
c5aff182 TP |
1891 | netif_tx_wake_queue(nq); |
1892 | } | |
c5aff182 TP |
1893 | } |
1894 | ||
dc35a10f | 1895 | /* Refill processing for SW buffer management */ |
7e47fd84 | 1896 | /* Allocate page per descriptor */ |
c5aff182 | 1897 | static int mvneta_rx_refill(struct mvneta_port *pp, |
f88bee1c | 1898 | struct mvneta_rx_desc *rx_desc, |
7e47fd84 GC |
1899 | struct mvneta_rx_queue *rxq, |
1900 | gfp_t gfp_mask) | |
c5aff182 TP |
1901 | { |
1902 | dma_addr_t phys_addr; | |
7e47fd84 | 1903 | struct page *page; |
c5aff182 | 1904 | |
568a3fa2 LB |
1905 | page = page_pool_alloc_pages(rxq->page_pool, |
1906 | gfp_mask | __GFP_NOWARN); | |
7e47fd84 | 1907 | if (!page) |
c5aff182 TP |
1908 | return -ENOMEM; |
1909 | ||
568a3fa2 | 1910 | phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; |
7e47fd84 | 1911 | mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); |
568a3fa2 | 1912 | |
c5aff182 TP |
1913 | return 0; |
1914 | } | |
1915 | ||
1916 | /* Handle tx checksum */ | |
1917 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) | |
1918 | { | |
1919 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1920 | int ip_hdr_len = 0; | |
817dbfa5 | 1921 | __be16 l3_proto = vlan_get_protocol(skb); |
c5aff182 TP |
1922 | u8 l4_proto; |
1923 | ||
817dbfa5 | 1924 | if (l3_proto == htons(ETH_P_IP)) { |
c5aff182 TP |
1925 | struct iphdr *ip4h = ip_hdr(skb); |
1926 | ||
1927 | /* Calculate IPv4 checksum and L4 checksum */ | |
1928 | ip_hdr_len = ip4h->ihl; | |
1929 | l4_proto = ip4h->protocol; | |
817dbfa5 | 1930 | } else if (l3_proto == htons(ETH_P_IPV6)) { |
c5aff182 TP |
1931 | struct ipv6hdr *ip6h = ipv6_hdr(skb); |
1932 | ||
1933 | /* Read l4_protocol from one of IPv6 extra headers */ | |
1934 | if (skb_network_header_len(skb) > 0) | |
1935 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
1936 | l4_proto = ip6h->nexthdr; | |
1937 | } else | |
1938 | return MVNETA_TX_L4_CSUM_NOT; | |
1939 | ||
1940 | return mvneta_txq_desc_csum(skb_network_offset(skb), | |
817dbfa5 | 1941 | l3_proto, ip_hdr_len, l4_proto); |
c5aff182 TP |
1942 | } |
1943 | ||
1944 | return MVNETA_TX_L4_CSUM_NOT; | |
1945 | } | |
1946 | ||
c5aff182 TP |
1947 | /* Drop packets received by the RXQ and free buffers */ |
1948 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
1949 | struct mvneta_rx_queue *rxq) | |
1950 | { | |
1951 | int rx_done, i; | |
1952 | ||
1953 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
dc35a10f MW |
1954 | if (rx_done) |
1955 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
1956 | ||
1957 | if (pp->bm_priv) { | |
1958 | for (i = 0; i < rx_done; i++) { | |
1959 | struct mvneta_rx_desc *rx_desc = | |
1960 | mvneta_rxq_next_desc_get(rxq); | |
1961 | u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); | |
1962 | struct mvneta_bm_pool *bm_pool; | |
1963 | ||
1964 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
1965 | /* Return dropped buffer to the pool */ | |
1966 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
1967 | rx_desc->buf_phys_addr); | |
1968 | } | |
1969 | return; | |
1970 | } | |
1971 | ||
c5aff182 TP |
1972 | for (i = 0; i < rxq->size; i++) { |
1973 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; | |
f88bee1c | 1974 | void *data = rxq->buf_virt_addr[i]; |
562e2f46 YK |
1975 | if (!data || !(rx_desc->buf_phys_addr)) |
1976 | continue; | |
c5aff182 | 1977 | |
458de8a9 | 1978 | page_pool_put_full_page(rxq->page_pool, data, false); |
c5aff182 | 1979 | } |
568a3fa2 LB |
1980 | if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) |
1981 | xdp_rxq_info_unreg(&rxq->xdp_rxq); | |
1982 | page_pool_destroy(rxq->page_pool); | |
1983 | rxq->page_pool = NULL; | |
dc35a10f | 1984 | } |
c5aff182 | 1985 | |
ff519e2a | 1986 | static void |
320d5441 LB |
1987 | mvneta_update_stats(struct mvneta_port *pp, |
1988 | struct mvneta_stats *ps) | |
ff519e2a LB |
1989 | { |
1990 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); | |
1991 | ||
1992 | u64_stats_update_begin(&stats->syncp); | |
320d5441 LB |
1993 | stats->es.ps.rx_packets += ps->rx_packets; |
1994 | stats->es.ps.rx_bytes += ps->rx_bytes; | |
3d866523 LB |
1995 | /* xdp */ |
1996 | stats->es.ps.xdp_redirect += ps->xdp_redirect; | |
1997 | stats->es.ps.xdp_pass += ps->xdp_pass; | |
1998 | stats->es.ps.xdp_drop += ps->xdp_drop; | |
ff519e2a LB |
1999 | u64_stats_update_end(&stats->syncp); |
2000 | } | |
2001 | ||
562e2f46 YK |
2002 | static inline |
2003 | int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) | |
2004 | { | |
2005 | struct mvneta_rx_desc *rx_desc; | |
2006 | int curr_desc = rxq->first_to_refill; | |
2007 | int i; | |
2008 | ||
2009 | for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { | |
2010 | rx_desc = rxq->descs + curr_desc; | |
2011 | if (!(rx_desc->buf_phys_addr)) { | |
2012 | if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { | |
9ac41f3c LB |
2013 | struct mvneta_pcpu_stats *stats; |
2014 | ||
562e2f46 YK |
2015 | pr_err("Can't refill queue %d. Done %d from %d\n", |
2016 | rxq->id, i, rxq->refill_num); | |
9ac41f3c LB |
2017 | |
2018 | stats = this_cpu_ptr(pp->stats); | |
2019 | u64_stats_update_begin(&stats->syncp); | |
2020 | stats->es.refill_error++; | |
2021 | u64_stats_update_end(&stats->syncp); | |
562e2f46 YK |
2022 | break; |
2023 | } | |
2024 | } | |
2025 | curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); | |
2026 | } | |
2027 | rxq->refill_num -= i; | |
2028 | rxq->first_to_refill = curr_desc; | |
2029 | ||
2030 | return i; | |
2031 | } | |
2032 | ||
ca0e0146 LB |
2033 | static void |
2034 | mvneta_xdp_put_buff(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
eb33f118 LB |
2035 | struct xdp_buff *xdp, struct skb_shared_info *sinfo, |
2036 | int sync_len) | |
ca0e0146 | 2037 | { |
ca0e0146 LB |
2038 | int i; |
2039 | ||
ca0e0146 LB |
2040 | for (i = 0; i < sinfo->nr_frags; i++) |
2041 | page_pool_put_full_page(rxq->page_pool, | |
eb33f118 | 2042 | skb_frag_page(&sinfo->frags[i]), true); |
9d3b2d3e | 2043 | page_pool_put_page(rxq->page_pool, virt_to_head_page(xdp->data), |
eb33f118 | 2044 | sync_len, true); |
ca0e0146 LB |
2045 | } |
2046 | ||
b0a43db9 LB |
2047 | static int |
2048 | mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, | |
2049 | struct xdp_frame *xdpf, bool dma_map) | |
2050 | { | |
2051 | struct mvneta_tx_desc *tx_desc; | |
2052 | struct mvneta_tx_buf *buf; | |
2053 | dma_addr_t dma_addr; | |
2054 | ||
2055 | if (txq->count >= txq->tx_stop_threshold) | |
2056 | return MVNETA_XDP_DROPPED; | |
2057 | ||
2058 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2059 | ||
2060 | buf = &txq->buf[txq->txq_put_index]; | |
2061 | if (dma_map) { | |
2062 | /* ndo_xdp_xmit */ | |
2063 | dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, | |
2064 | xdpf->len, DMA_TO_DEVICE); | |
2065 | if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { | |
2066 | mvneta_txq_desc_put(txq); | |
2067 | return MVNETA_XDP_DROPPED; | |
2068 | } | |
2069 | buf->type = MVNETA_TYPE_XDP_NDO; | |
2070 | } else { | |
2071 | struct page *page = virt_to_page(xdpf->data); | |
2072 | ||
2073 | dma_addr = page_pool_get_dma_addr(page) + | |
2074 | sizeof(*xdpf) + xdpf->headroom; | |
2075 | dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, | |
2076 | xdpf->len, DMA_BIDIRECTIONAL); | |
2077 | buf->type = MVNETA_TYPE_XDP_TX; | |
2078 | } | |
2079 | buf->xdpf = xdpf; | |
2080 | ||
2081 | tx_desc->command = MVNETA_TXD_FLZ_DESC; | |
2082 | tx_desc->buf_phys_addr = dma_addr; | |
2083 | tx_desc->data_size = xdpf->len; | |
2084 | ||
b0a43db9 LB |
2085 | mvneta_txq_inc_put(txq); |
2086 | txq->pending++; | |
2087 | txq->count++; | |
2088 | ||
2089 | return MVNETA_XDP_TX; | |
2090 | } | |
2091 | ||
2092 | static int | |
2093 | mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) | |
2094 | { | |
15070919 | 2095 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
b0a43db9 LB |
2096 | struct mvneta_tx_queue *txq; |
2097 | struct netdev_queue *nq; | |
2098 | struct xdp_frame *xdpf; | |
2099 | int cpu; | |
2100 | u32 ret; | |
2101 | ||
1b698fa5 | 2102 | xdpf = xdp_convert_buff_to_frame(xdp); |
b0a43db9 LB |
2103 | if (unlikely(!xdpf)) |
2104 | return MVNETA_XDP_DROPPED; | |
2105 | ||
2106 | cpu = smp_processor_id(); | |
2107 | txq = &pp->txqs[cpu % txq_number]; | |
2108 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
2109 | ||
2110 | __netif_tx_lock(nq, cpu); | |
2111 | ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); | |
7d51a015 | 2112 | if (ret == MVNETA_XDP_TX) { |
7d51a015 LB |
2113 | u64_stats_update_begin(&stats->syncp); |
2114 | stats->es.ps.tx_bytes += xdpf->len; | |
2115 | stats->es.ps.tx_packets++; | |
2116 | stats->es.ps.xdp_tx++; | |
2117 | u64_stats_update_end(&stats->syncp); | |
2118 | ||
b0a43db9 | 2119 | mvneta_txq_pend_desc_add(pp, txq, 0); |
15070919 JDB |
2120 | } else { |
2121 | u64_stats_update_begin(&stats->syncp); | |
2122 | stats->es.ps.xdp_tx_err++; | |
2123 | u64_stats_update_end(&stats->syncp); | |
7d51a015 | 2124 | } |
b0a43db9 LB |
2125 | __netif_tx_unlock(nq); |
2126 | ||
2127 | return ret; | |
2128 | } | |
2129 | ||
2130 | static int | |
2131 | mvneta_xdp_xmit(struct net_device *dev, int num_frame, | |
2132 | struct xdp_frame **frames, u32 flags) | |
2133 | { | |
2134 | struct mvneta_port *pp = netdev_priv(dev); | |
7d51a015 | 2135 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
fdc13979 | 2136 | int i, nxmit_byte = 0, nxmit = 0; |
b0a43db9 LB |
2137 | int cpu = smp_processor_id(); |
2138 | struct mvneta_tx_queue *txq; | |
2139 | struct netdev_queue *nq; | |
b0a43db9 LB |
2140 | u32 ret; |
2141 | ||
62a502cc LB |
2142 | if (unlikely(test_bit(__MVNETA_DOWN, &pp->state))) |
2143 | return -ENETDOWN; | |
2144 | ||
b0a43db9 LB |
2145 | if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) |
2146 | return -EINVAL; | |
2147 | ||
2148 | txq = &pp->txqs[cpu % txq_number]; | |
2149 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
2150 | ||
2151 | __netif_tx_lock(nq, cpu); | |
2152 | for (i = 0; i < num_frame; i++) { | |
2153 | ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); | |
fdc13979 LB |
2154 | if (ret != MVNETA_XDP_TX) |
2155 | break; | |
2156 | ||
2157 | nxmit_byte += frames[i]->len; | |
2158 | nxmit++; | |
b0a43db9 LB |
2159 | } |
2160 | ||
2161 | if (unlikely(flags & XDP_XMIT_FLUSH)) | |
2162 | mvneta_txq_pend_desc_add(pp, txq, 0); | |
2163 | __netif_tx_unlock(nq); | |
2164 | ||
7d51a015 LB |
2165 | u64_stats_update_begin(&stats->syncp); |
2166 | stats->es.ps.tx_bytes += nxmit_byte; | |
2167 | stats->es.ps.tx_packets += nxmit; | |
2168 | stats->es.ps.xdp_xmit += nxmit; | |
15070919 | 2169 | stats->es.ps.xdp_xmit_err += num_frame - nxmit; |
7d51a015 LB |
2170 | u64_stats_update_end(&stats->syncp); |
2171 | ||
2172 | return nxmit; | |
b0a43db9 LB |
2173 | } |
2174 | ||
0db51da7 LB |
2175 | static int |
2176 | mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
320d5441 | 2177 | struct bpf_prog *prog, struct xdp_buff *xdp, |
7d1643eb | 2178 | u32 frame_sz, struct mvneta_stats *stats) |
0db51da7 | 2179 | { |
eb33f118 | 2180 | struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); |
7d1643eb | 2181 | unsigned int len, data_len, sync; |
8c4df83f LB |
2182 | u32 ret, act; |
2183 | ||
2184 | len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; | |
7d1643eb | 2185 | data_len = xdp->data_end - xdp->data; |
8c4df83f | 2186 | act = bpf_prog_run_xdp(prog, xdp); |
0db51da7 | 2187 | |
494f44d5 JDB |
2188 | /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ |
2189 | sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; | |
2190 | sync = max(sync, len); | |
2191 | ||
0db51da7 LB |
2192 | switch (act) { |
2193 | case XDP_PASS: | |
3d866523 | 2194 | stats->xdp_pass++; |
320d5441 | 2195 | return MVNETA_XDP_PASS; |
0db51da7 LB |
2196 | case XDP_REDIRECT: { |
2197 | int err; | |
2198 | ||
2199 | err = xdp_do_redirect(pp->dev, xdp, prog); | |
15070919 | 2200 | if (unlikely(err)) { |
eb33f118 | 2201 | mvneta_xdp_put_buff(pp, rxq, xdp, sinfo, sync); |
0db51da7 | 2202 | ret = MVNETA_XDP_DROPPED; |
0db51da7 LB |
2203 | } else { |
2204 | ret = MVNETA_XDP_REDIR; | |
3d866523 | 2205 | stats->xdp_redirect++; |
0db51da7 LB |
2206 | } |
2207 | break; | |
2208 | } | |
b0a43db9 LB |
2209 | case XDP_TX: |
2210 | ret = mvneta_xdp_xmit_back(pp, xdp); | |
7d1643eb | 2211 | if (ret != MVNETA_XDP_TX) |
eb33f118 | 2212 | mvneta_xdp_put_buff(pp, rxq, xdp, sinfo, sync); |
b0a43db9 | 2213 | break; |
0db51da7 LB |
2214 | default: |
2215 | bpf_warn_invalid_xdp_action(act); | |
df561f66 | 2216 | fallthrough; |
0db51da7 LB |
2217 | case XDP_ABORTED: |
2218 | trace_xdp_exception(pp->dev, prog, act); | |
df561f66 | 2219 | fallthrough; |
0db51da7 | 2220 | case XDP_DROP: |
eb33f118 | 2221 | mvneta_xdp_put_buff(pp, rxq, xdp, sinfo, sync); |
0db51da7 | 2222 | ret = MVNETA_XDP_DROPPED; |
3d866523 | 2223 | stats->xdp_drop++; |
0db51da7 LB |
2224 | break; |
2225 | } | |
2226 | ||
7d1643eb | 2227 | stats->rx_bytes += frame_sz + xdp->data_end - xdp->data - data_len; |
320d5441 LB |
2228 | stats->rx_packets++; |
2229 | ||
0db51da7 LB |
2230 | return ret; |
2231 | } | |
2232 | ||
afda408b | 2233 | static void |
8dc9a088 LB |
2234 | mvneta_swbm_rx_frame(struct mvneta_port *pp, |
2235 | struct mvneta_rx_desc *rx_desc, | |
2236 | struct mvneta_rx_queue *rxq, | |
c7a3a8cd | 2237 | struct xdp_buff *xdp, int *size, |
3a8c4ad1 | 2238 | struct page *page) |
8dc9a088 LB |
2239 | { |
2240 | unsigned char *data = page_address(page); | |
2241 | int data_len = -MVNETA_MH_SIZE, len; | |
2242 | struct net_device *dev = pp->dev; | |
2243 | enum dma_data_direction dma_dir; | |
ca0e0146 | 2244 | struct skb_shared_info *sinfo; |
8dc9a088 | 2245 | |
879456be | 2246 | if (*size > MVNETA_MAX_RX_BUF_SIZE) { |
8dc9a088 LB |
2247 | len = MVNETA_MAX_RX_BUF_SIZE; |
2248 | data_len += len; | |
2249 | } else { | |
879456be | 2250 | len = *size; |
8dc9a088 LB |
2251 | data_len += len - ETH_FCS_LEN; |
2252 | } | |
879456be | 2253 | *size = *size - len; |
8dc9a088 LB |
2254 | |
2255 | dma_dir = page_pool_get_dma_dir(rxq->page_pool); | |
2256 | dma_sync_single_for_cpu(dev->dev.parent, | |
2257 | rx_desc->buf_phys_addr, | |
2258 | len, dma_dir); | |
2259 | ||
879456be LB |
2260 | rx_desc->buf_phys_addr = 0; |
2261 | ||
fa383f6b LB |
2262 | /* Prefetch header */ |
2263 | prefetch(data); | |
be9df4af LB |
2264 | xdp_prepare_buff(xdp, data, pp->rx_offset_correction + MVNETA_MH_SIZE, |
2265 | data_len, false); | |
0db51da7 | 2266 | |
ca0e0146 LB |
2267 | sinfo = xdp_get_shared_info_from_buff(xdp); |
2268 | sinfo->nr_frags = 0; | |
8dc9a088 LB |
2269 | } |
2270 | ||
2271 | static void | |
2272 | mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, | |
2273 | struct mvneta_rx_desc *rx_desc, | |
2274 | struct mvneta_rx_queue *rxq, | |
c7a3a8cd | 2275 | struct xdp_buff *xdp, int *size, |
039fbc47 | 2276 | struct skb_shared_info *xdp_sinfo, |
8dc9a088 LB |
2277 | struct page *page) |
2278 | { | |
2279 | struct net_device *dev = pp->dev; | |
2280 | enum dma_data_direction dma_dir; | |
2281 | int data_len, len; | |
2282 | ||
c7a3a8cd | 2283 | if (*size > MVNETA_MAX_RX_BUF_SIZE) { |
8dc9a088 LB |
2284 | len = MVNETA_MAX_RX_BUF_SIZE; |
2285 | data_len = len; | |
2286 | } else { | |
c7a3a8cd | 2287 | len = *size; |
8dc9a088 LB |
2288 | data_len = len - ETH_FCS_LEN; |
2289 | } | |
2290 | dma_dir = page_pool_get_dma_dir(rxq->page_pool); | |
2291 | dma_sync_single_for_cpu(dev->dev.parent, | |
2292 | rx_desc->buf_phys_addr, | |
2293 | len, dma_dir); | |
9c79a8ab | 2294 | rx_desc->buf_phys_addr = 0; |
ca0e0146 | 2295 | |
039fbc47 LB |
2296 | if (data_len > 0 && xdp_sinfo->nr_frags < MAX_SKB_FRAGS) { |
2297 | skb_frag_t *frag = &xdp_sinfo->frags[xdp_sinfo->nr_frags++]; | |
ca0e0146 LB |
2298 | |
2299 | skb_frag_off_set(frag, pp->rx_offset_correction); | |
2300 | skb_frag_size_set(frag, data_len); | |
2301 | __skb_frag_set_page(frag, page); | |
9c79a8ab LB |
2302 | } else { |
2303 | page_pool_put_full_page(rxq->page_pool, page, true); | |
8dc9a088 | 2304 | } |
6ff63a15 LB |
2305 | |
2306 | /* last fragment */ | |
2307 | if (len == *size) { | |
2308 | struct skb_shared_info *sinfo; | |
2309 | ||
2310 | sinfo = xdp_get_shared_info_from_buff(xdp); | |
2311 | sinfo->nr_frags = xdp_sinfo->nr_frags; | |
2312 | memcpy(sinfo->frags, xdp_sinfo->frags, | |
2313 | sinfo->nr_frags * sizeof(skb_frag_t)); | |
2314 | } | |
c7a3a8cd | 2315 | *size -= len; |
8dc9a088 LB |
2316 | } |
2317 | ||
ca0e0146 | 2318 | static struct sk_buff * |
e4017570 | 2319 | mvneta_swbm_build_skb(struct mvneta_port *pp, struct page_pool *pool, |
ca0e0146 LB |
2320 | struct xdp_buff *xdp, u32 desc_status) |
2321 | { | |
2322 | struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); | |
2323 | int i, num_frags = sinfo->nr_frags; | |
ca0e0146 LB |
2324 | struct sk_buff *skb; |
2325 | ||
ca0e0146 LB |
2326 | skb = build_skb(xdp->data_hard_start, PAGE_SIZE); |
2327 | if (!skb) | |
2328 | return ERR_PTR(-ENOMEM); | |
2329 | ||
e4017570 | 2330 | skb_mark_for_recycle(skb, virt_to_page(xdp->data), pool); |
ca0e0146 LB |
2331 | |
2332 | skb_reserve(skb, xdp->data - xdp->data_hard_start); | |
2333 | skb_put(skb, xdp->data_end - xdp->data); | |
aff0824d | 2334 | skb->ip_summed = mvneta_rx_csum(pp, desc_status); |
ca0e0146 LB |
2335 | |
2336 | for (i = 0; i < num_frags; i++) { | |
52731441 | 2337 | skb_frag_t *frag = &sinfo->frags[i]; |
ca0e0146 LB |
2338 | |
2339 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, | |
52731441 LB |
2340 | skb_frag_page(frag), skb_frag_off(frag), |
2341 | skb_frag_size(frag), PAGE_SIZE); | |
e4017570 MC |
2342 | /* We don't need to reset pp_recycle here. It's already set, so |
2343 | * just mark fragments for recycling. | |
2344 | */ | |
2345 | page_pool_store_mem_info(skb_frag_page(frag), pool); | |
ca0e0146 LB |
2346 | } |
2347 | ||
2348 | return skb; | |
2349 | } | |
2350 | ||
dc35a10f | 2351 | /* Main rx processing when using software buffer management */ |
7a86f05f | 2352 | static int mvneta_rx_swbm(struct napi_struct *napi, |
562e2f46 | 2353 | struct mvneta_port *pp, int budget, |
dc35a10f MW |
2354 | struct mvneta_rx_queue *rxq) |
2355 | { | |
c7a3a8cd | 2356 | int rx_proc = 0, rx_todo, refill, size = 0; |
dc35a10f | 2357 | struct net_device *dev = pp->dev; |
039fbc47 | 2358 | struct skb_shared_info sinfo; |
320d5441 | 2359 | struct mvneta_stats ps = {}; |
0db51da7 | 2360 | struct bpf_prog *xdp_prog; |
7d1643eb | 2361 | u32 desc_status, frame_sz; |
05c748f7 LB |
2362 | struct xdp_buff xdp_buf; |
2363 | ||
43b5169d | 2364 | xdp_init_buff(&xdp_buf, PAGE_SIZE, &rxq->xdp_rxq); |
05c748f7 | 2365 | xdp_buf.data_hard_start = NULL; |
dc35a10f | 2366 | |
039fbc47 LB |
2367 | sinfo.nr_frags = 0; |
2368 | ||
dc35a10f | 2369 | /* Get number of received packets */ |
562e2f46 | 2370 | rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); |
dc35a10f | 2371 | |
0db51da7 | 2372 | xdp_prog = READ_ONCE(pp->xdp_prog); |
0db51da7 | 2373 | |
dc35a10f | 2374 | /* Fairness NAPI loop */ |
8dc9a088 | 2375 | while (rx_proc < budget && rx_proc < rx_todo) { |
dc35a10f | 2376 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); |
8dc9a088 | 2377 | u32 rx_status, index; |
ca0e0146 | 2378 | struct sk_buff *skb; |
7e47fd84 | 2379 | struct page *page; |
dc35a10f | 2380 | |
f88bee1c | 2381 | index = rx_desc - rxq->descs; |
7e47fd84 | 2382 | page = (struct page *)rxq->buf_virt_addr[index]; |
dc35a10f | 2383 | |
562e2f46 YK |
2384 | rx_status = rx_desc->status; |
2385 | rx_proc++; | |
2386 | rxq->refill_num++; | |
2387 | ||
2388 | if (rx_status & MVNETA_RXD_FIRST_DESC) { | |
2389 | /* Check errors only for FIRST descriptor */ | |
2390 | if (rx_status & MVNETA_RXD_ERR_SUMMARY) { | |
2391 | mvneta_rx_error(pp, rx_desc); | |
ca0e0146 | 2392 | goto next; |
562e2f46 | 2393 | } |
dc35a10f | 2394 | |
c7a3a8cd LB |
2395 | size = rx_desc->data_size; |
2396 | frame_sz = size - ETH_FCS_LEN; | |
879456be | 2397 | desc_status = rx_status; |
7d1643eb | 2398 | |
c7a3a8cd | 2399 | mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, |
3a8c4ad1 | 2400 | &size, page); |
562e2f46 | 2401 | } else { |
b6e11785 LB |
2402 | if (unlikely(!xdp_buf.data_hard_start)) { |
2403 | rx_desc->buf_phys_addr = 0; | |
2404 | page_pool_put_full_page(rxq->page_pool, page, | |
2405 | true); | |
039fbc47 | 2406 | goto next; |
b6e11785 | 2407 | } |
ca0e0146 LB |
2408 | |
2409 | mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, &xdp_buf, | |
039fbc47 | 2410 | &size, &sinfo, page); |
562e2f46 | 2411 | } /* Middle or Last descriptor */ |
dc35a10f | 2412 | |
562e2f46 YK |
2413 | if (!(rx_status & MVNETA_RXD_LAST_DESC)) |
2414 | /* no last descriptor this time */ | |
dc35a10f | 2415 | continue; |
dc35a10f | 2416 | |
c7a3a8cd | 2417 | if (size) { |
039fbc47 | 2418 | mvneta_xdp_put_buff(pp, rxq, &xdp_buf, &sinfo, -1); |
ca0e0146 | 2419 | goto next; |
dc35a10f | 2420 | } |
320d5441 | 2421 | |
afda408b | 2422 | if (xdp_prog && |
7d1643eb | 2423 | mvneta_run_xdp(pp, rxq, xdp_prog, &xdp_buf, frame_sz, &ps)) |
afda408b LB |
2424 | goto next; |
2425 | ||
e4017570 | 2426 | skb = mvneta_swbm_build_skb(pp, rxq->page_pool, &xdp_buf, desc_status); |
ca0e0146 LB |
2427 | if (IS_ERR(skb)) { |
2428 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); | |
2429 | ||
039fbc47 | 2430 | mvneta_xdp_put_buff(pp, rxq, &xdp_buf, &sinfo, -1); |
ca0e0146 LB |
2431 | |
2432 | u64_stats_update_begin(&stats->syncp); | |
2433 | stats->es.skb_alloc_error++; | |
2434 | stats->rx_dropped++; | |
2435 | u64_stats_update_end(&stats->syncp); | |
dc35a10f | 2436 | |
ca0e0146 LB |
2437 | goto next; |
2438 | } | |
dc35a10f | 2439 | |
ca0e0146 LB |
2440 | ps.rx_bytes += skb->len; |
2441 | ps.rx_packets++; | |
dc35a10f | 2442 | |
ca0e0146 LB |
2443 | skb->protocol = eth_type_trans(skb, dev); |
2444 | napi_gro_receive(napi, skb); | |
2445 | next: | |
2446 | xdp_buf.data_hard_start = NULL; | |
039fbc47 | 2447 | sinfo.nr_frags = 0; |
dc35a10f | 2448 | } |
0db51da7 | 2449 | |
039fbc47 LB |
2450 | if (xdp_buf.data_hard_start) |
2451 | mvneta_xdp_put_buff(pp, rxq, &xdp_buf, &sinfo, -1); | |
ca0e0146 | 2452 | |
6c8a8cfd | 2453 | if (ps.xdp_redirect) |
0db51da7 | 2454 | xdp_do_flush_map(); |
dc35a10f | 2455 | |
320d5441 LB |
2456 | if (ps.rx_packets) |
2457 | mvneta_update_stats(pp, &ps); | |
dc35a10f | 2458 | |
562e2f46 YK |
2459 | /* return some buffers to hardware queue, one at a time is too slow */ |
2460 | refill = mvneta_rx_refill_queue(pp, rxq); | |
2461 | ||
dc35a10f | 2462 | /* Update rxq management counters */ |
562e2f46 | 2463 | mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); |
dc35a10f | 2464 | |
320d5441 | 2465 | return ps.rx_packets; |
c5aff182 TP |
2466 | } |
2467 | ||
dc35a10f | 2468 | /* Main rx processing when using hardware buffer management */ |
7a86f05f AL |
2469 | static int mvneta_rx_hwbm(struct napi_struct *napi, |
2470 | struct mvneta_port *pp, int rx_todo, | |
dc35a10f | 2471 | struct mvneta_rx_queue *rxq) |
c5aff182 TP |
2472 | { |
2473 | struct net_device *dev = pp->dev; | |
a84e3289 | 2474 | int rx_done; |
dc4277dd | 2475 | u32 rcvd_pkts = 0; |
2476 | u32 rcvd_bytes = 0; | |
c5aff182 TP |
2477 | |
2478 | /* Get number of received packets */ | |
2479 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
2480 | ||
2481 | if (rx_todo > rx_done) | |
2482 | rx_todo = rx_done; | |
2483 | ||
2484 | rx_done = 0; | |
c5aff182 TP |
2485 | |
2486 | /* Fairness NAPI loop */ | |
2487 | while (rx_done < rx_todo) { | |
2488 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
dc35a10f | 2489 | struct mvneta_bm_pool *bm_pool = NULL; |
c5aff182 | 2490 | struct sk_buff *skb; |
8ec2cd48 | 2491 | unsigned char *data; |
daf158d0 | 2492 | dma_addr_t phys_addr; |
dc35a10f | 2493 | u32 rx_status, frag_size; |
c5aff182 | 2494 | int rx_bytes, err; |
dc35a10f | 2495 | u8 pool_id; |
c5aff182 | 2496 | |
c5aff182 | 2497 | rx_done++; |
c5aff182 | 2498 | rx_status = rx_desc->status; |
f19fadfc | 2499 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); |
f88bee1c | 2500 | data = (u8 *)(uintptr_t)rx_desc->buf_cookie; |
daf158d0 | 2501 | phys_addr = rx_desc->buf_phys_addr; |
dc35a10f MW |
2502 | pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); |
2503 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
c5aff182 | 2504 | |
5428213c | 2505 | if (!mvneta_rxq_desc_is_first_last(rx_status) || |
f19fadfc | 2506 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { |
dc35a10f MW |
2507 | err_drop_frame_ret_pool: |
2508 | /* Return the buffer to the pool */ | |
2509 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2510 | rx_desc->buf_phys_addr); | |
2511 | err_drop_frame: | |
c5aff182 | 2512 | mvneta_rx_error(pp, rx_desc); |
8ec2cd48 | 2513 | /* leave the descriptor untouched */ |
c5aff182 TP |
2514 | continue; |
2515 | } | |
2516 | ||
f19fadfc | 2517 | if (rx_bytes <= rx_copybreak) { |
2518 | /* better copy a small frame and not unmap the DMA region */ | |
2519 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
2520 | if (unlikely(!skb)) | |
dc35a10f | 2521 | goto err_drop_frame_ret_pool; |
f19fadfc | 2522 | |
a8fef9ba | 2523 | dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, |
f19fadfc | 2524 | rx_desc->buf_phys_addr, |
2525 | MVNETA_MH_SIZE + NET_SKB_PAD, | |
2526 | rx_bytes, | |
2527 | DMA_FROM_DEVICE); | |
59ae1d12 JB |
2528 | skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, |
2529 | rx_bytes); | |
f19fadfc | 2530 | |
2531 | skb->protocol = eth_type_trans(skb, dev); | |
aff0824d | 2532 | skb->ip_summed = mvneta_rx_csum(pp, rx_status); |
7a86f05f | 2533 | napi_gro_receive(napi, skb); |
f19fadfc | 2534 | |
2535 | rcvd_pkts++; | |
2536 | rcvd_bytes += rx_bytes; | |
2537 | ||
dc35a10f MW |
2538 | /* Return the buffer to the pool */ |
2539 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2540 | rx_desc->buf_phys_addr); | |
2541 | ||
f19fadfc | 2542 | /* leave the descriptor and buffer untouched */ |
2543 | continue; | |
2544 | } | |
2545 | ||
a84e3289 | 2546 | /* Refill processing */ |
baa11ebc | 2547 | err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); |
a84e3289 | 2548 | if (err) { |
9ac41f3c LB |
2549 | struct mvneta_pcpu_stats *stats; |
2550 | ||
a84e3289 | 2551 | netdev_err(dev, "Linux processing - Can't refill\n"); |
9ac41f3c LB |
2552 | |
2553 | stats = this_cpu_ptr(pp->stats); | |
2554 | u64_stats_update_begin(&stats->syncp); | |
2555 | stats->es.refill_error++; | |
2556 | u64_stats_update_end(&stats->syncp); | |
2557 | ||
dc35a10f | 2558 | goto err_drop_frame_ret_pool; |
a84e3289 SG |
2559 | } |
2560 | ||
baa11ebc | 2561 | frag_size = bm_pool->hwbm_pool.frag_size; |
dc35a10f MW |
2562 | |
2563 | skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); | |
f19fadfc | 2564 | |
26c17a17 MW |
2565 | /* After refill old buffer has to be unmapped regardless |
2566 | * the skb is successfully built or not. | |
2567 | */ | |
dc35a10f MW |
2568 | dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, |
2569 | bm_pool->buf_size, DMA_FROM_DEVICE); | |
26c17a17 MW |
2570 | if (!skb) |
2571 | goto err_drop_frame; | |
2572 | ||
dc4277dd | 2573 | rcvd_pkts++; |
2574 | rcvd_bytes += rx_bytes; | |
c5aff182 TP |
2575 | |
2576 | /* Linux processing */ | |
8ec2cd48 | 2577 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); |
c5aff182 TP |
2578 | skb_put(skb, rx_bytes); |
2579 | ||
2580 | skb->protocol = eth_type_trans(skb, dev); | |
aff0824d | 2581 | skb->ip_summed = mvneta_rx_csum(pp, rx_status); |
c5aff182 | 2582 | |
7a86f05f | 2583 | napi_gro_receive(napi, skb); |
c5aff182 TP |
2584 | } |
2585 | ||
69de66fc LB |
2586 | if (rcvd_pkts) { |
2587 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); | |
2588 | ||
2589 | u64_stats_update_begin(&stats->syncp); | |
320d5441 LB |
2590 | stats->es.ps.rx_packets += rcvd_pkts; |
2591 | stats->es.ps.rx_bytes += rcvd_bytes; | |
69de66fc LB |
2592 | u64_stats_update_end(&stats->syncp); |
2593 | } | |
dc4277dd | 2594 | |
c5aff182 | 2595 | /* Update rxq management counters */ |
a84e3289 | 2596 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
c5aff182 TP |
2597 | |
2598 | return rx_done; | |
2599 | } | |
2600 | ||
2adb719d EG |
2601 | static inline void |
2602 | mvneta_tso_put_hdr(struct sk_buff *skb, | |
2603 | struct mvneta_port *pp, struct mvneta_tx_queue *txq) | |
2604 | { | |
2adb719d | 2605 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
9e58c8b4 LB |
2606 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
2607 | struct mvneta_tx_desc *tx_desc; | |
2adb719d | 2608 | |
2adb719d EG |
2609 | tx_desc = mvneta_txq_next_desc_get(txq); |
2610 | tx_desc->data_size = hdr_len; | |
2611 | tx_desc->command = mvneta_skb_tx_csum(pp, skb); | |
2612 | tx_desc->command |= MVNETA_TXD_F_DESC; | |
2613 | tx_desc->buf_phys_addr = txq->tso_hdrs_phys + | |
2614 | txq->txq_put_index * TSO_HEADER_SIZE; | |
9e58c8b4 LB |
2615 | buf->type = MVNETA_TYPE_SKB; |
2616 | buf->skb = NULL; | |
2617 | ||
2adb719d EG |
2618 | mvneta_txq_inc_put(txq); |
2619 | } | |
2620 | ||
2621 | static inline int | |
2622 | mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, | |
2623 | struct sk_buff *skb, char *data, int size, | |
2624 | bool last_tcp, bool is_last) | |
2625 | { | |
9e58c8b4 | 2626 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
2adb719d EG |
2627 | struct mvneta_tx_desc *tx_desc; |
2628 | ||
2629 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2630 | tx_desc->data_size = size; | |
2631 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, | |
2632 | size, DMA_TO_DEVICE); | |
2633 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2634 | tx_desc->buf_phys_addr))) { | |
2635 | mvneta_txq_desc_put(txq); | |
2636 | return -ENOMEM; | |
2637 | } | |
2638 | ||
2639 | tx_desc->command = 0; | |
9e58c8b4 LB |
2640 | buf->type = MVNETA_TYPE_SKB; |
2641 | buf->skb = NULL; | |
2adb719d EG |
2642 | |
2643 | if (last_tcp) { | |
2644 | /* last descriptor in the TCP packet */ | |
2645 | tx_desc->command = MVNETA_TXD_L_DESC; | |
2646 | ||
2647 | /* last descriptor in SKB */ | |
2648 | if (is_last) | |
9e58c8b4 | 2649 | buf->skb = skb; |
2adb719d EG |
2650 | } |
2651 | mvneta_txq_inc_put(txq); | |
2652 | return 0; | |
2653 | } | |
2654 | ||
2655 | static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
2656 | struct mvneta_tx_queue *txq) | |
2657 | { | |
761b331c | 2658 | int hdr_len, total_len, data_left; |
2adb719d EG |
2659 | int desc_count = 0; |
2660 | struct mvneta_port *pp = netdev_priv(dev); | |
2661 | struct tso_t tso; | |
2adb719d EG |
2662 | int i; |
2663 | ||
2664 | /* Count needed descriptors */ | |
2665 | if ((txq->count + tso_count_descs(skb)) >= txq->size) | |
2666 | return 0; | |
2667 | ||
2668 | if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { | |
fa660684 | 2669 | pr_info("*** Is this even possible?\n"); |
2adb719d EG |
2670 | return 0; |
2671 | } | |
2672 | ||
2673 | /* Initialize the TSO handler, and prepare the first payload */ | |
761b331c | 2674 | hdr_len = tso_start(skb, &tso); |
2adb719d EG |
2675 | |
2676 | total_len = skb->len - hdr_len; | |
2677 | while (total_len > 0) { | |
2678 | char *hdr; | |
2679 | ||
2680 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); | |
2681 | total_len -= data_left; | |
2682 | desc_count++; | |
2683 | ||
2684 | /* prepare packet headers: MAC + IP + TCP */ | |
2685 | hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; | |
2686 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); | |
2687 | ||
2688 | mvneta_tso_put_hdr(skb, pp, txq); | |
2689 | ||
2690 | while (data_left > 0) { | |
2691 | int size; | |
2692 | desc_count++; | |
2693 | ||
2694 | size = min_t(int, tso.size, data_left); | |
2695 | ||
2696 | if (mvneta_tso_put_data(dev, txq, skb, | |
2697 | tso.data, size, | |
2698 | size == data_left, | |
2699 | total_len == 0)) | |
2700 | goto err_release; | |
2701 | data_left -= size; | |
2702 | ||
2703 | tso_build_data(skb, &tso, size); | |
2704 | } | |
2705 | } | |
2706 | ||
2707 | return desc_count; | |
2708 | ||
2709 | err_release: | |
2710 | /* Release all used data descriptors; header descriptors must not | |
2711 | * be DMA-unmapped. | |
2712 | */ | |
2713 | for (i = desc_count - 1; i >= 0; i--) { | |
2714 | struct mvneta_tx_desc *tx_desc = txq->descs + i; | |
2e3173a3 | 2715 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
2adb719d EG |
2716 | dma_unmap_single(pp->dev->dev.parent, |
2717 | tx_desc->buf_phys_addr, | |
2718 | tx_desc->data_size, | |
2719 | DMA_TO_DEVICE); | |
2720 | mvneta_txq_desc_put(txq); | |
2721 | } | |
2722 | return 0; | |
2723 | } | |
2724 | ||
c5aff182 TP |
2725 | /* Handle tx fragmentation processing */ |
2726 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, | |
2727 | struct mvneta_tx_queue *txq) | |
2728 | { | |
2729 | struct mvneta_tx_desc *tx_desc; | |
3d4ea02f | 2730 | int i, nr_frags = skb_shinfo(skb)->nr_frags; |
c5aff182 | 2731 | |
3d4ea02f | 2732 | for (i = 0; i < nr_frags; i++) { |
9e58c8b4 | 2733 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
c5aff182 | 2734 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
d7840976 | 2735 | void *addr = skb_frag_address(frag); |
c5aff182 TP |
2736 | |
2737 | tx_desc = mvneta_txq_next_desc_get(txq); | |
d7840976 | 2738 | tx_desc->data_size = skb_frag_size(frag); |
c5aff182 TP |
2739 | |
2740 | tx_desc->buf_phys_addr = | |
2741 | dma_map_single(pp->dev->dev.parent, addr, | |
2742 | tx_desc->data_size, DMA_TO_DEVICE); | |
2743 | ||
2744 | if (dma_mapping_error(pp->dev->dev.parent, | |
2745 | tx_desc->buf_phys_addr)) { | |
2746 | mvneta_txq_desc_put(txq); | |
2747 | goto error; | |
2748 | } | |
2749 | ||
3d4ea02f | 2750 | if (i == nr_frags - 1) { |
c5aff182 TP |
2751 | /* Last descriptor */ |
2752 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; | |
9e58c8b4 | 2753 | buf->skb = skb; |
c5aff182 TP |
2754 | } else { |
2755 | /* Descriptor in the middle: Not First, Not Last */ | |
2756 | tx_desc->command = 0; | |
9e58c8b4 | 2757 | buf->skb = NULL; |
c5aff182 | 2758 | } |
9e58c8b4 | 2759 | buf->type = MVNETA_TYPE_SKB; |
3d4ea02f | 2760 | mvneta_txq_inc_put(txq); |
c5aff182 TP |
2761 | } |
2762 | ||
2763 | return 0; | |
2764 | ||
2765 | error: | |
2766 | /* Release all descriptors that were used to map fragments of | |
6a20c175 TP |
2767 | * this packet, as well as the corresponding DMA mappings |
2768 | */ | |
c5aff182 TP |
2769 | for (i = i - 1; i >= 0; i--) { |
2770 | tx_desc = txq->descs + i; | |
2771 | dma_unmap_single(pp->dev->dev.parent, | |
2772 | tx_desc->buf_phys_addr, | |
2773 | tx_desc->data_size, | |
2774 | DMA_TO_DEVICE); | |
2775 | mvneta_txq_desc_put(txq); | |
2776 | } | |
2777 | ||
2778 | return -ENOMEM; | |
2779 | } | |
2780 | ||
2781 | /* Main tx processing */ | |
f03508ce | 2782 | static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) |
c5aff182 TP |
2783 | { |
2784 | struct mvneta_port *pp = netdev_priv(dev); | |
ee40a116 WT |
2785 | u16 txq_id = skb_get_queue_mapping(skb); |
2786 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; | |
9e58c8b4 | 2787 | struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; |
c5aff182 | 2788 | struct mvneta_tx_desc *tx_desc; |
5f478b41 | 2789 | int len = skb->len; |
c5aff182 TP |
2790 | int frags = 0; |
2791 | u32 tx_cmd; | |
2792 | ||
2793 | if (!netif_running(dev)) | |
2794 | goto out; | |
2795 | ||
2adb719d EG |
2796 | if (skb_is_gso(skb)) { |
2797 | frags = mvneta_tx_tso(skb, dev, txq); | |
2798 | goto out; | |
2799 | } | |
2800 | ||
c5aff182 | 2801 | frags = skb_shinfo(skb)->nr_frags + 1; |
c5aff182 TP |
2802 | |
2803 | /* Get a descriptor for the first part of the packet */ | |
2804 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2805 | ||
2806 | tx_cmd = mvneta_skb_tx_csum(pp, skb); | |
2807 | ||
2808 | tx_desc->data_size = skb_headlen(skb); | |
2809 | ||
2810 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, | |
2811 | tx_desc->data_size, | |
2812 | DMA_TO_DEVICE); | |
2813 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2814 | tx_desc->buf_phys_addr))) { | |
2815 | mvneta_txq_desc_put(txq); | |
2816 | frags = 0; | |
2817 | goto out; | |
2818 | } | |
2819 | ||
9e58c8b4 | 2820 | buf->type = MVNETA_TYPE_SKB; |
c5aff182 TP |
2821 | if (frags == 1) { |
2822 | /* First and Last descriptor */ | |
2823 | tx_cmd |= MVNETA_TXD_FLZ_DESC; | |
2824 | tx_desc->command = tx_cmd; | |
9e58c8b4 | 2825 | buf->skb = skb; |
c5aff182 TP |
2826 | mvneta_txq_inc_put(txq); |
2827 | } else { | |
2828 | /* First but not Last */ | |
2829 | tx_cmd |= MVNETA_TXD_F_DESC; | |
9e58c8b4 | 2830 | buf->skb = NULL; |
c5aff182 TP |
2831 | mvneta_txq_inc_put(txq); |
2832 | tx_desc->command = tx_cmd; | |
2833 | /* Continue with other skb fragments */ | |
2834 | if (mvneta_tx_frag_process(pp, skb, txq)) { | |
2835 | dma_unmap_single(dev->dev.parent, | |
2836 | tx_desc->buf_phys_addr, | |
2837 | tx_desc->data_size, | |
2838 | DMA_TO_DEVICE); | |
2839 | mvneta_txq_desc_put(txq); | |
2840 | frags = 0; | |
2841 | goto out; | |
2842 | } | |
2843 | } | |
2844 | ||
c5aff182 TP |
2845 | out: |
2846 | if (frags > 0) { | |
e19d2dda | 2847 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
69de66fc | 2848 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
e19d2dda | 2849 | |
a29b6235 MW |
2850 | netdev_tx_sent_queue(nq, len); |
2851 | ||
e19d2dda | 2852 | txq->count += frags; |
8eef5f97 | 2853 | if (txq->count >= txq->tx_stop_threshold) |
e19d2dda | 2854 | netif_tx_stop_queue(nq); |
c5aff182 | 2855 | |
6b16f9ee | 2856 | if (!netdev_xmit_more() || netif_xmit_stopped(nq) || |
2a90f7e1 SG |
2857 | txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) |
2858 | mvneta_txq_pend_desc_add(pp, txq, frags); | |
2859 | else | |
2860 | txq->pending += frags; | |
2861 | ||
69de66fc | 2862 | u64_stats_update_begin(&stats->syncp); |
320d5441 LB |
2863 | stats->es.ps.tx_bytes += len; |
2864 | stats->es.ps.tx_packets++; | |
69de66fc | 2865 | u64_stats_update_end(&stats->syncp); |
c5aff182 TP |
2866 | } else { |
2867 | dev->stats.tx_dropped++; | |
2868 | dev_kfree_skb_any(skb); | |
2869 | } | |
2870 | ||
c5aff182 TP |
2871 | return NETDEV_TX_OK; |
2872 | } | |
2873 | ||
2874 | ||
2875 | /* Free tx resources, when resetting a port */ | |
2876 | static void mvneta_txq_done_force(struct mvneta_port *pp, | |
2877 | struct mvneta_tx_queue *txq) | |
2878 | ||
2879 | { | |
a29b6235 | 2880 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
c5aff182 TP |
2881 | int tx_done = txq->count; |
2882 | ||
632bb64f | 2883 | mvneta_txq_bufs_free(pp, txq, tx_done, nq, false); |
c5aff182 TP |
2884 | |
2885 | /* reset txq */ | |
2886 | txq->count = 0; | |
2887 | txq->txq_put_index = 0; | |
2888 | txq->txq_get_index = 0; | |
2889 | } | |
2890 | ||
6c498974 | 2891 | /* Handle tx done - called in softirq context. The <cause_tx_done> argument |
2892 | * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. | |
2893 | */ | |
0713a86a | 2894 | static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) |
c5aff182 TP |
2895 | { |
2896 | struct mvneta_tx_queue *txq; | |
c5aff182 | 2897 | struct netdev_queue *nq; |
bd9f1ee3 | 2898 | int cpu = smp_processor_id(); |
c5aff182 | 2899 | |
6c498974 | 2900 | while (cause_tx_done) { |
c5aff182 | 2901 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
c5aff182 TP |
2902 | |
2903 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
bd9f1ee3 | 2904 | __netif_tx_lock(nq, cpu); |
c5aff182 | 2905 | |
0713a86a AE |
2906 | if (txq->count) |
2907 | mvneta_txq_done(pp, txq); | |
c5aff182 TP |
2908 | |
2909 | __netif_tx_unlock(nq); | |
2910 | cause_tx_done &= ~((1 << txq->id)); | |
2911 | } | |
c5aff182 TP |
2912 | } |
2913 | ||
6a20c175 | 2914 | /* Compute crc8 of the specified address, using a unique algorithm , |
c5aff182 TP |
2915 | * according to hw spec, different than generic crc8 algorithm |
2916 | */ | |
2917 | static int mvneta_addr_crc(unsigned char *addr) | |
2918 | { | |
2919 | int crc = 0; | |
2920 | int i; | |
2921 | ||
2922 | for (i = 0; i < ETH_ALEN; i++) { | |
2923 | int j; | |
2924 | ||
2925 | crc = (crc ^ addr[i]) << 8; | |
2926 | for (j = 7; j >= 0; j--) { | |
2927 | if (crc & (0x100 << j)) | |
2928 | crc ^= 0x107 << j; | |
2929 | } | |
2930 | } | |
2931 | ||
2932 | return crc; | |
2933 | } | |
2934 | ||
2935 | /* This method controls the net device special MAC multicast support. | |
2936 | * The Special Multicast Table for MAC addresses supports MAC of the form | |
2937 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2938 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2939 | * Table entries in the DA-Filter table. This method set the Special | |
2940 | * Multicast Table appropriate entry. | |
2941 | */ | |
2942 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, | |
2943 | unsigned char last_byte, | |
2944 | int queue) | |
2945 | { | |
2946 | unsigned int smc_table_reg; | |
2947 | unsigned int tbl_offset; | |
2948 | unsigned int reg_offset; | |
2949 | ||
2950 | /* Register offset from SMC table base */ | |
2951 | tbl_offset = (last_byte / 4); | |
2952 | /* Entry offset within the above reg */ | |
2953 | reg_offset = last_byte % 4; | |
2954 | ||
2955 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST | |
2956 | + tbl_offset * 4)); | |
2957 | ||
2958 | if (queue == -1) | |
2959 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2960 | else { | |
2961 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2962 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2963 | } | |
2964 | ||
2965 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, | |
2966 | smc_table_reg); | |
2967 | } | |
2968 | ||
2969 | /* This method controls the network device Other MAC multicast support. | |
2970 | * The Other Multicast Table is used for multicast of another type. | |
2971 | * A CRC-8 is used as an index to the Other Multicast Table entries | |
2972 | * in the DA-Filter table. | |
2973 | * The method gets the CRC-8 value from the calling routine and | |
2974 | * sets the Other Multicast Table appropriate entry according to the | |
2975 | * specified CRC-8 . | |
2976 | */ | |
2977 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, | |
2978 | unsigned char crc8, | |
2979 | int queue) | |
2980 | { | |
2981 | unsigned int omc_table_reg; | |
2982 | unsigned int tbl_offset; | |
2983 | unsigned int reg_offset; | |
2984 | ||
2985 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ | |
2986 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ | |
2987 | ||
2988 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); | |
2989 | ||
2990 | if (queue == -1) { | |
2991 | /* Clear accepts frame bit at specified Other DA table entry */ | |
2992 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2993 | } else { | |
2994 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2995 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2996 | } | |
2997 | ||
2998 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); | |
2999 | } | |
3000 | ||
3001 | /* The network device supports multicast using two tables: | |
3002 | * 1) Special Multicast Table for MAC addresses of the form | |
3003 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
3004 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
3005 | * Table entries in the DA-Filter table. | |
3006 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value | |
3007 | * is used as an index to the Other Multicast Table entries in the | |
3008 | * DA-Filter table. | |
3009 | */ | |
3010 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, | |
3011 | int queue) | |
3012 | { | |
3013 | unsigned char crc_result = 0; | |
3014 | ||
3015 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { | |
3016 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); | |
3017 | return 0; | |
3018 | } | |
3019 | ||
3020 | crc_result = mvneta_addr_crc(p_addr); | |
3021 | if (queue == -1) { | |
3022 | if (pp->mcast_count[crc_result] == 0) { | |
3023 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", | |
3024 | crc_result); | |
3025 | return -EINVAL; | |
3026 | } | |
3027 | ||
3028 | pp->mcast_count[crc_result]--; | |
3029 | if (pp->mcast_count[crc_result] != 0) { | |
3030 | netdev_info(pp->dev, | |
3031 | "After delete there are %d valid Mcast for crc8=0x%02x\n", | |
3032 | pp->mcast_count[crc_result], crc_result); | |
3033 | return -EINVAL; | |
3034 | } | |
3035 | } else | |
3036 | pp->mcast_count[crc_result]++; | |
3037 | ||
3038 | mvneta_set_other_mcast_addr(pp, crc_result, queue); | |
3039 | ||
3040 | return 0; | |
3041 | } | |
3042 | ||
3043 | /* Configure Fitering mode of Ethernet port */ | |
3044 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, | |
3045 | int is_promisc) | |
3046 | { | |
3047 | u32 port_cfg_reg, val; | |
3048 | ||
3049 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); | |
3050 | ||
3051 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); | |
3052 | ||
3053 | /* Set / Clear UPM bit in port configuration register */ | |
3054 | if (is_promisc) { | |
3055 | /* Accept all Unicast addresses */ | |
3056 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; | |
3057 | val |= MVNETA_FORCE_UNI; | |
3058 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); | |
3059 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); | |
3060 | } else { | |
3061 | /* Reject all Unicast addresses */ | |
3062 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; | |
3063 | val &= ~MVNETA_FORCE_UNI; | |
3064 | } | |
3065 | ||
3066 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); | |
3067 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); | |
3068 | } | |
3069 | ||
3070 | /* register unicast and multicast addresses */ | |
3071 | static void mvneta_set_rx_mode(struct net_device *dev) | |
3072 | { | |
3073 | struct mvneta_port *pp = netdev_priv(dev); | |
3074 | struct netdev_hw_addr *ha; | |
3075 | ||
3076 | if (dev->flags & IFF_PROMISC) { | |
3077 | /* Accept all: Multicast + Unicast */ | |
3078 | mvneta_rx_unicast_promisc_set(pp, 1); | |
90b74c01 GC |
3079 | mvneta_set_ucast_table(pp, pp->rxq_def); |
3080 | mvneta_set_special_mcast_table(pp, pp->rxq_def); | |
3081 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
3082 | } else { |
3083 | /* Accept single Unicast */ | |
3084 | mvneta_rx_unicast_promisc_set(pp, 0); | |
3085 | mvneta_set_ucast_table(pp, -1); | |
90b74c01 | 3086 | mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); |
c5aff182 TP |
3087 | |
3088 | if (dev->flags & IFF_ALLMULTI) { | |
3089 | /* Accept all multicast */ | |
90b74c01 GC |
3090 | mvneta_set_special_mcast_table(pp, pp->rxq_def); |
3091 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
3092 | } else { |
3093 | /* Accept only initialized multicast */ | |
3094 | mvneta_set_special_mcast_table(pp, -1); | |
3095 | mvneta_set_other_mcast_table(pp, -1); | |
3096 | ||
3097 | if (!netdev_mc_empty(dev)) { | |
3098 | netdev_for_each_mc_addr(ha, dev) { | |
3099 | mvneta_mcast_addr_set(pp, ha->addr, | |
90b74c01 | 3100 | pp->rxq_def); |
c5aff182 TP |
3101 | } |
3102 | } | |
3103 | } | |
3104 | } | |
3105 | } | |
3106 | ||
3107 | /* Interrupt handling - the callback for request_irq() */ | |
3108 | static irqreturn_t mvneta_isr(int irq, void *dev_id) | |
2636ac3c MW |
3109 | { |
3110 | struct mvneta_port *pp = (struct mvneta_port *)dev_id; | |
3111 | ||
3112 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
3113 | napi_schedule(&pp->napi); | |
3114 | ||
3115 | return IRQ_HANDLED; | |
3116 | } | |
3117 | ||
3118 | /* Interrupt handling - the callback for request_percpu_irq() */ | |
3119 | static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) | |
c5aff182 | 3120 | { |
12bb03b4 | 3121 | struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; |
c5aff182 | 3122 | |
12bb03b4 | 3123 | disable_percpu_irq(port->pp->dev->irq); |
12bb03b4 | 3124 | napi_schedule(&port->napi); |
c5aff182 TP |
3125 | |
3126 | return IRQ_HANDLED; | |
3127 | } | |
3128 | ||
503f9aa9 | 3129 | static void mvneta_link_change(struct mvneta_port *pp) |
898b2970 | 3130 | { |
898b2970 SS |
3131 | u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); |
3132 | ||
503f9aa9 | 3133 | phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); |
898b2970 SS |
3134 | } |
3135 | ||
c5aff182 TP |
3136 | /* NAPI handler |
3137 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted | |
3138 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). | |
3139 | * Bits 8 -15 of the cause Rx Tx register indicate that are received | |
3140 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). | |
3141 | * Each CPU has its own causeRxTx register | |
3142 | */ | |
3143 | static int mvneta_poll(struct napi_struct *napi, int budget) | |
3144 | { | |
3145 | int rx_done = 0; | |
3146 | u32 cause_rx_tx; | |
2dcf75e2 | 3147 | int rx_queue; |
c5aff182 | 3148 | struct mvneta_port *pp = netdev_priv(napi->dev); |
12bb03b4 | 3149 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 TP |
3150 | |
3151 | if (!netif_running(pp->dev)) { | |
2636ac3c | 3152 | napi_complete(napi); |
c5aff182 TP |
3153 | return rx_done; |
3154 | } | |
3155 | ||
3156 | /* Read cause register */ | |
898b2970 SS |
3157 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); |
3158 | if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { | |
3159 | u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); | |
3160 | ||
3161 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
503f9aa9 RK |
3162 | |
3163 | if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 3164 | MVNETA_CAUSE_LINK_CHANGE)) |
503f9aa9 | 3165 | mvneta_link_change(pp); |
898b2970 | 3166 | } |
71f6d1b3 | 3167 | |
3168 | /* Release Tx descriptors */ | |
3169 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { | |
0713a86a | 3170 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); |
71f6d1b3 | 3171 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; |
3172 | } | |
c5aff182 | 3173 | |
6a20c175 | 3174 | /* For the case where the last mvneta_poll did not process all |
c5aff182 TP |
3175 | * RX packets |
3176 | */ | |
2636ac3c MW |
3177 | cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : |
3178 | port->cause_rx_tx; | |
2dcf75e2 | 3179 | |
065fd83e | 3180 | rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); |
2dcf75e2 GC |
3181 | if (rx_queue) { |
3182 | rx_queue = rx_queue - 1; | |
dc35a10f | 3183 | if (pp->bm_priv) |
7a86f05f AL |
3184 | rx_done = mvneta_rx_hwbm(napi, pp, budget, |
3185 | &pp->rxqs[rx_queue]); | |
dc35a10f | 3186 | else |
7a86f05f AL |
3187 | rx_done = mvneta_rx_swbm(napi, pp, budget, |
3188 | &pp->rxqs[rx_queue]); | |
2dcf75e2 GC |
3189 | } |
3190 | ||
6ad20165 | 3191 | if (rx_done < budget) { |
c5aff182 | 3192 | cause_rx_tx = 0; |
6ad20165 | 3193 | napi_complete_done(napi, rx_done); |
2636ac3c MW |
3194 | |
3195 | if (pp->neta_armada3700) { | |
3196 | unsigned long flags; | |
3197 | ||
3198 | local_irq_save(flags); | |
3199 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
3200 | MVNETA_RX_INTR_MASK(rxq_number) | | |
3201 | MVNETA_TX_INTR_MASK(txq_number) | | |
3202 | MVNETA_MISCINTR_INTR_MASK); | |
3203 | local_irq_restore(flags); | |
3204 | } else { | |
3205 | enable_percpu_irq(pp->dev->irq, 0); | |
3206 | } | |
c5aff182 TP |
3207 | } |
3208 | ||
2636ac3c MW |
3209 | if (pp->neta_armada3700) |
3210 | pp->cause_rx_tx = cause_rx_tx; | |
3211 | else | |
3212 | port->cause_rx_tx = cause_rx_tx; | |
3213 | ||
c5aff182 TP |
3214 | return rx_done; |
3215 | } | |
3216 | ||
568a3fa2 LB |
3217 | static int mvneta_create_page_pool(struct mvneta_port *pp, |
3218 | struct mvneta_rx_queue *rxq, int size) | |
3219 | { | |
0db51da7 | 3220 | struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); |
568a3fa2 LB |
3221 | struct page_pool_params pp_params = { |
3222 | .order = 0, | |
07e13edb | 3223 | .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, |
568a3fa2 | 3224 | .pool_size = size, |
1657adcc | 3225 | .nid = NUMA_NO_NODE, |
568a3fa2 | 3226 | .dev = pp->dev->dev.parent, |
0db51da7 | 3227 | .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, |
07e13edb LB |
3228 | .offset = pp->rx_offset_correction, |
3229 | .max_len = MVNETA_MAX_RX_BUF_SIZE, | |
568a3fa2 LB |
3230 | }; |
3231 | int err; | |
3232 | ||
3233 | rxq->page_pool = page_pool_create(&pp_params); | |
3234 | if (IS_ERR(rxq->page_pool)) { | |
3235 | err = PTR_ERR(rxq->page_pool); | |
3236 | rxq->page_pool = NULL; | |
3237 | return err; | |
3238 | } | |
3239 | ||
b02e5a0e | 3240 | err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id, 0); |
568a3fa2 LB |
3241 | if (err < 0) |
3242 | goto err_free_pp; | |
3243 | ||
3244 | err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, | |
3245 | rxq->page_pool); | |
3246 | if (err) | |
3247 | goto err_unregister_rxq; | |
3248 | ||
3249 | return 0; | |
3250 | ||
3251 | err_unregister_rxq: | |
3252 | xdp_rxq_info_unreg(&rxq->xdp_rxq); | |
3253 | err_free_pp: | |
3254 | page_pool_destroy(rxq->page_pool); | |
3255 | rxq->page_pool = NULL; | |
3256 | return err; | |
3257 | } | |
3258 | ||
c5aff182 TP |
3259 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
3260 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
3261 | int num) | |
3262 | { | |
568a3fa2 LB |
3263 | int i, err; |
3264 | ||
3265 | err = mvneta_create_page_pool(pp, rxq, num); | |
3266 | if (err < 0) | |
3267 | return err; | |
c5aff182 TP |
3268 | |
3269 | for (i = 0; i < num; i++) { | |
a1a65ab1 | 3270 | memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); |
7e47fd84 GC |
3271 | if (mvneta_rx_refill(pp, rxq->descs + i, rxq, |
3272 | GFP_KERNEL) != 0) { | |
3273 | netdev_err(pp->dev, | |
3274 | "%s:rxq %d, %d of %d buffs filled\n", | |
3275 | __func__, rxq->id, i, num); | |
c5aff182 TP |
3276 | break; |
3277 | } | |
c5aff182 TP |
3278 | } |
3279 | ||
3280 | /* Add this number of RX descriptors as non occupied (ready to | |
6a20c175 TP |
3281 | * get packets) |
3282 | */ | |
c5aff182 TP |
3283 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
3284 | ||
3285 | return i; | |
3286 | } | |
3287 | ||
3288 | /* Free all packets pending transmit from all TXQs and reset TX port */ | |
3289 | static void mvneta_tx_reset(struct mvneta_port *pp) | |
3290 | { | |
3291 | int queue; | |
3292 | ||
9672850b | 3293 | /* free the skb's in the tx ring */ |
c5aff182 TP |
3294 | for (queue = 0; queue < txq_number; queue++) |
3295 | mvneta_txq_done_force(pp, &pp->txqs[queue]); | |
3296 | ||
3297 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
3298 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
3299 | } | |
3300 | ||
3301 | static void mvneta_rx_reset(struct mvneta_port *pp) | |
3302 | { | |
3303 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
3304 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
3305 | } | |
3306 | ||
3307 | /* Rx/Tx queue initialization/cleanup methods */ | |
3308 | ||
4a188a63 JZ |
3309 | static int mvneta_rxq_sw_init(struct mvneta_port *pp, |
3310 | struct mvneta_rx_queue *rxq) | |
c5aff182 TP |
3311 | { |
3312 | rxq->size = pp->rx_ring_size; | |
3313 | ||
3314 | /* Allocate memory for RX descriptors */ | |
3315 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
3316 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3317 | &rxq->descs_phys, GFP_KERNEL); | |
f95936cc | 3318 | if (!rxq->descs) |
c5aff182 | 3319 | return -ENOMEM; |
c5aff182 | 3320 | |
c5aff182 TP |
3321 | rxq->last_desc = rxq->size - 1; |
3322 | ||
4a188a63 JZ |
3323 | return 0; |
3324 | } | |
3325 | ||
3326 | static void mvneta_rxq_hw_init(struct mvneta_port *pp, | |
3327 | struct mvneta_rx_queue *rxq) | |
3328 | { | |
c5aff182 TP |
3329 | /* Set Rx descriptors queue starting address */ |
3330 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
3331 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
3332 | ||
c5aff182 TP |
3333 | /* Set coalescing pkts and time */ |
3334 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
3335 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
3336 | ||
dc35a10f | 3337 | if (!pp->bm_priv) { |
562e2f46 YK |
3338 | /* Set Offset */ |
3339 | mvneta_rxq_offset_set(pp, rxq, 0); | |
e735fd55 | 3340 | mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? |
8dc9a088 | 3341 | MVNETA_MAX_RX_BUF_SIZE : |
e735fd55 | 3342 | MVNETA_RX_BUF_SIZE(pp->pkt_size)); |
dc35a10f | 3343 | mvneta_rxq_bm_disable(pp, rxq); |
e9f64999 | 3344 | mvneta_rxq_fill(pp, rxq, rxq->size); |
dc35a10f | 3345 | } else { |
562e2f46 YK |
3346 | /* Set Offset */ |
3347 | mvneta_rxq_offset_set(pp, rxq, | |
3348 | NET_SKB_PAD - pp->rx_offset_correction); | |
3349 | ||
dc35a10f | 3350 | mvneta_rxq_bm_enable(pp, rxq); |
562e2f46 | 3351 | /* Fill RXQ with buffers from RX pool */ |
dc35a10f MW |
3352 | mvneta_rxq_long_pool_set(pp, rxq); |
3353 | mvneta_rxq_short_pool_set(pp, rxq); | |
e9f64999 | 3354 | mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); |
dc35a10f | 3355 | } |
4a188a63 JZ |
3356 | } |
3357 | ||
3358 | /* Create a specified RX queue */ | |
3359 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
3360 | struct mvneta_rx_queue *rxq) | |
3361 | ||
3362 | { | |
3363 | int ret; | |
3364 | ||
3365 | ret = mvneta_rxq_sw_init(pp, rxq); | |
3366 | if (ret < 0) | |
3367 | return ret; | |
3368 | ||
3369 | mvneta_rxq_hw_init(pp, rxq); | |
dc35a10f | 3370 | |
c5aff182 TP |
3371 | return 0; |
3372 | } | |
3373 | ||
3374 | /* Cleanup Rx queue */ | |
3375 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
3376 | struct mvneta_rx_queue *rxq) | |
3377 | { | |
3378 | mvneta_rxq_drop_pkts(pp, rxq); | |
3379 | ||
3380 | if (rxq->descs) | |
3381 | dma_free_coherent(pp->dev->dev.parent, | |
3382 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3383 | rxq->descs, | |
3384 | rxq->descs_phys); | |
3385 | ||
3386 | rxq->descs = NULL; | |
3387 | rxq->last_desc = 0; | |
3388 | rxq->next_desc_to_proc = 0; | |
3389 | rxq->descs_phys = 0; | |
562e2f46 YK |
3390 | rxq->first_to_refill = 0; |
3391 | rxq->refill_num = 0; | |
c5aff182 TP |
3392 | } |
3393 | ||
4a188a63 JZ |
3394 | static int mvneta_txq_sw_init(struct mvneta_port *pp, |
3395 | struct mvneta_tx_queue *txq) | |
c5aff182 | 3396 | { |
50bf8cb6 GC |
3397 | int cpu; |
3398 | ||
c5aff182 TP |
3399 | txq->size = pp->tx_ring_size; |
3400 | ||
8eef5f97 EG |
3401 | /* A queue must always have room for at least one skb. |
3402 | * Therefore, stop the queue when the free entries reaches | |
3403 | * the maximum number of descriptors per skb. | |
3404 | */ | |
3405 | txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; | |
3406 | txq->tx_wake_threshold = txq->tx_stop_threshold / 2; | |
3407 | ||
c5aff182 TP |
3408 | /* Allocate memory for TX descriptors */ |
3409 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
3410 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3411 | &txq->descs_phys, GFP_KERNEL); | |
f95936cc | 3412 | if (!txq->descs) |
c5aff182 | 3413 | return -ENOMEM; |
c5aff182 | 3414 | |
c5aff182 TP |
3415 | txq->last_desc = txq->size - 1; |
3416 | ||
9e58c8b4 | 3417 | txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); |
f4544e53 | 3418 | if (!txq->buf) |
c5aff182 | 3419 | return -ENOMEM; |
2adb719d EG |
3420 | |
3421 | /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ | |
3422 | txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, | |
3423 | txq->size * TSO_HEADER_SIZE, | |
3424 | &txq->tso_hdrs_phys, GFP_KERNEL); | |
f4544e53 | 3425 | if (!txq->tso_hdrs) |
2adb719d | 3426 | return -ENOMEM; |
c5aff182 | 3427 | |
50bf8cb6 | 3428 | /* Setup XPS mapping */ |
cf9bf871 MC |
3429 | if (pp->neta_armada3700) |
3430 | cpu = 0; | |
3431 | else if (txq_number > 1) | |
50bf8cb6 GC |
3432 | cpu = txq->id % num_present_cpus(); |
3433 | else | |
3434 | cpu = pp->rxq_def % num_present_cpus(); | |
3435 | cpumask_set_cpu(cpu, &txq->affinity_mask); | |
3436 | netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); | |
3437 | ||
c5aff182 TP |
3438 | return 0; |
3439 | } | |
3440 | ||
4a188a63 JZ |
3441 | static void mvneta_txq_hw_init(struct mvneta_port *pp, |
3442 | struct mvneta_tx_queue *txq) | |
3443 | { | |
3444 | /* Set maximum bandwidth for enabled TXQs */ | |
3445 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
3446 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
3447 | ||
3448 | /* Set Tx descriptors queue starting address */ | |
3449 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
3450 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
3451 | ||
3452 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
3453 | } | |
3454 | ||
3455 | /* Create and initialize a tx queue */ | |
3456 | static int mvneta_txq_init(struct mvneta_port *pp, | |
3457 | struct mvneta_tx_queue *txq) | |
3458 | { | |
3459 | int ret; | |
3460 | ||
3461 | ret = mvneta_txq_sw_init(pp, txq); | |
3462 | if (ret < 0) | |
3463 | return ret; | |
3464 | ||
3465 | mvneta_txq_hw_init(pp, txq); | |
3466 | ||
3467 | return 0; | |
3468 | } | |
3469 | ||
c5aff182 | 3470 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ |
4a188a63 JZ |
3471 | static void mvneta_txq_sw_deinit(struct mvneta_port *pp, |
3472 | struct mvneta_tx_queue *txq) | |
c5aff182 | 3473 | { |
a29b6235 MW |
3474 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
3475 | ||
9e58c8b4 | 3476 | kfree(txq->buf); |
c5aff182 | 3477 | |
2adb719d EG |
3478 | if (txq->tso_hdrs) |
3479 | dma_free_coherent(pp->dev->dev.parent, | |
3480 | txq->size * TSO_HEADER_SIZE, | |
3481 | txq->tso_hdrs, txq->tso_hdrs_phys); | |
c5aff182 TP |
3482 | if (txq->descs) |
3483 | dma_free_coherent(pp->dev->dev.parent, | |
3484 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
3485 | txq->descs, txq->descs_phys); | |
3486 | ||
a29b6235 MW |
3487 | netdev_tx_reset_queue(nq); |
3488 | ||
c5aff182 TP |
3489 | txq->descs = NULL; |
3490 | txq->last_desc = 0; | |
3491 | txq->next_desc_to_proc = 0; | |
3492 | txq->descs_phys = 0; | |
4a188a63 | 3493 | } |
c5aff182 | 3494 | |
4a188a63 JZ |
3495 | static void mvneta_txq_hw_deinit(struct mvneta_port *pp, |
3496 | struct mvneta_tx_queue *txq) | |
3497 | { | |
c5aff182 TP |
3498 | /* Set minimum bandwidth for disabled TXQs */ |
3499 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
3500 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
3501 | ||
3502 | /* Set Tx descriptors queue starting address and size */ | |
3503 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
3504 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
3505 | } | |
3506 | ||
4a188a63 JZ |
3507 | static void mvneta_txq_deinit(struct mvneta_port *pp, |
3508 | struct mvneta_tx_queue *txq) | |
3509 | { | |
3510 | mvneta_txq_sw_deinit(pp, txq); | |
3511 | mvneta_txq_hw_deinit(pp, txq); | |
3512 | } | |
3513 | ||
c5aff182 TP |
3514 | /* Cleanup all Tx queues */ |
3515 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
3516 | { | |
3517 | int queue; | |
3518 | ||
3519 | for (queue = 0; queue < txq_number; queue++) | |
3520 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
3521 | } | |
3522 | ||
3523 | /* Cleanup all Rx queues */ | |
3524 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
3525 | { | |
2dcf75e2 GC |
3526 | int queue; |
3527 | ||
ca5902a6 | 3528 | for (queue = 0; queue < rxq_number; queue++) |
2dcf75e2 | 3529 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); |
c5aff182 TP |
3530 | } |
3531 | ||
3532 | ||
3533 | /* Init all Rx queues */ | |
3534 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
3535 | { | |
2dcf75e2 GC |
3536 | int queue; |
3537 | ||
3538 | for (queue = 0; queue < rxq_number; queue++) { | |
3539 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
3540 | ||
3541 | if (err) { | |
3542 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
3543 | __func__, queue); | |
3544 | mvneta_cleanup_rxqs(pp); | |
3545 | return err; | |
3546 | } | |
c5aff182 TP |
3547 | } |
3548 | ||
3549 | return 0; | |
3550 | } | |
3551 | ||
3552 | /* Init all tx queues */ | |
3553 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
3554 | { | |
3555 | int queue; | |
3556 | ||
3557 | for (queue = 0; queue < txq_number; queue++) { | |
3558 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
3559 | if (err) { | |
3560 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
3561 | __func__, queue); | |
3562 | mvneta_cleanup_txqs(pp); | |
3563 | return err; | |
3564 | } | |
3565 | } | |
3566 | ||
3567 | return 0; | |
3568 | } | |
3569 | ||
b4748553 | 3570 | static int mvneta_comphy_init(struct mvneta_port *pp, phy_interface_t interface) |
031b922b MB |
3571 | { |
3572 | int ret; | |
3573 | ||
b4748553 | 3574 | ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, interface); |
031b922b MB |
3575 | if (ret) |
3576 | return ret; | |
3577 | ||
3578 | return phy_power_on(pp->comphy); | |
3579 | } | |
3580 | ||
b4748553 SH |
3581 | static int mvneta_config_interface(struct mvneta_port *pp, |
3582 | phy_interface_t interface) | |
3583 | { | |
3584 | int ret = 0; | |
3585 | ||
3586 | if (pp->comphy) { | |
3587 | if (interface == PHY_INTERFACE_MODE_SGMII || | |
3588 | interface == PHY_INTERFACE_MODE_1000BASEX || | |
3589 | interface == PHY_INTERFACE_MODE_2500BASEX) { | |
3590 | ret = mvneta_comphy_init(pp, interface); | |
3591 | } | |
3592 | } else { | |
3593 | switch (interface) { | |
3594 | case PHY_INTERFACE_MODE_QSGMII: | |
3595 | mvreg_write(pp, MVNETA_SERDES_CFG, | |
3596 | MVNETA_QSGMII_SERDES_PROTO); | |
3597 | break; | |
3598 | ||
3599 | case PHY_INTERFACE_MODE_SGMII: | |
3600 | case PHY_INTERFACE_MODE_1000BASEX: | |
3601 | mvreg_write(pp, MVNETA_SERDES_CFG, | |
3602 | MVNETA_SGMII_SERDES_PROTO); | |
3603 | break; | |
1a642ca7 SH |
3604 | |
3605 | case PHY_INTERFACE_MODE_2500BASEX: | |
3606 | mvreg_write(pp, MVNETA_SERDES_CFG, | |
3607 | MVNETA_HSGMII_SERDES_PROTO); | |
3608 | break; | |
b4748553 | 3609 | default: |
d3d239dc | 3610 | break; |
b4748553 SH |
3611 | } |
3612 | } | |
3613 | ||
3614 | pp->phy_interface = interface; | |
3615 | ||
3616 | return ret; | |
3617 | } | |
3618 | ||
c5aff182 TP |
3619 | static void mvneta_start_dev(struct mvneta_port *pp) |
3620 | { | |
6b125d63 | 3621 | int cpu; |
12bb03b4 | 3622 | |
b4748553 | 3623 | WARN_ON(mvneta_config_interface(pp, pp->phy_interface)); |
a10c1c81 | 3624 | |
c5aff182 TP |
3625 | mvneta_max_rx_size_set(pp, pp->pkt_size); |
3626 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); | |
3627 | ||
3628 | /* start the Rx/Tx activity */ | |
3629 | mvneta_port_enable(pp); | |
3630 | ||
2636ac3c MW |
3631 | if (!pp->neta_armada3700) { |
3632 | /* Enable polling on the port */ | |
3633 | for_each_online_cpu(cpu) { | |
3634 | struct mvneta_pcpu_port *port = | |
3635 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 3636 | |
2636ac3c MW |
3637 | napi_enable(&port->napi); |
3638 | } | |
3639 | } else { | |
3640 | napi_enable(&pp->napi); | |
12bb03b4 | 3641 | } |
c5aff182 | 3642 | |
2dcf75e2 | 3643 | /* Unmask interrupts. It has to be done from each CPU */ |
6b125d63 GC |
3644 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); |
3645 | ||
898b2970 SS |
3646 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
3647 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 3648 | MVNETA_CAUSE_LINK_CHANGE); |
c5aff182 | 3649 | |
503f9aa9 | 3650 | phylink_start(pp->phylink); |
61b5cc20 | 3651 | |
5ba2254b | 3652 | /* We may have called phylink_speed_down before */ |
61b5cc20 DGC |
3653 | phylink_speed_up(pp->phylink); |
3654 | ||
c5aff182 | 3655 | netif_tx_start_all_queues(pp->dev); |
62a502cc LB |
3656 | |
3657 | clear_bit(__MVNETA_DOWN, &pp->state); | |
c5aff182 TP |
3658 | } |
3659 | ||
3660 | static void mvneta_stop_dev(struct mvneta_port *pp) | |
3661 | { | |
12bb03b4 MR |
3662 | unsigned int cpu; |
3663 | ||
62a502cc LB |
3664 | set_bit(__MVNETA_DOWN, &pp->state); |
3665 | ||
61b5cc20 DGC |
3666 | if (device_may_wakeup(&pp->dev->dev)) |
3667 | phylink_speed_down(pp->phylink, false); | |
3668 | ||
503f9aa9 | 3669 | phylink_stop(pp->phylink); |
c5aff182 | 3670 | |
2636ac3c MW |
3671 | if (!pp->neta_armada3700) { |
3672 | for_each_online_cpu(cpu) { | |
3673 | struct mvneta_pcpu_port *port = | |
3674 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 3675 | |
2636ac3c MW |
3676 | napi_disable(&port->napi); |
3677 | } | |
3678 | } else { | |
3679 | napi_disable(&pp->napi); | |
12bb03b4 | 3680 | } |
c5aff182 TP |
3681 | |
3682 | netif_carrier_off(pp->dev); | |
3683 | ||
3684 | mvneta_port_down(pp); | |
3685 | netif_tx_stop_all_queues(pp->dev); | |
3686 | ||
3687 | /* Stop the port activity */ | |
3688 | mvneta_port_disable(pp); | |
3689 | ||
3690 | /* Clear all ethernet port interrupts */ | |
db488c10 | 3691 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
3692 | |
3693 | /* Mask all ethernet port interrupts */ | |
db488c10 | 3694 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
3695 | |
3696 | mvneta_tx_reset(pp); | |
3697 | mvneta_rx_reset(pp); | |
a10c1c81 RK |
3698 | |
3699 | WARN_ON(phy_power_off(pp->comphy)); | |
c5aff182 TP |
3700 | } |
3701 | ||
db5dd0db MW |
3702 | static void mvneta_percpu_enable(void *arg) |
3703 | { | |
3704 | struct mvneta_port *pp = arg; | |
3705 | ||
3706 | enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); | |
3707 | } | |
3708 | ||
3709 | static void mvneta_percpu_disable(void *arg) | |
3710 | { | |
3711 | struct mvneta_port *pp = arg; | |
3712 | ||
3713 | disable_percpu_irq(pp->dev->irq); | |
3714 | } | |
3715 | ||
c5aff182 TP |
3716 | /* Change the device mtu */ |
3717 | static int mvneta_change_mtu(struct net_device *dev, int mtu) | |
3718 | { | |
3719 | struct mvneta_port *pp = netdev_priv(dev); | |
3720 | int ret; | |
3721 | ||
5777987e JW |
3722 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { |
3723 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", | |
3724 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); | |
3725 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); | |
3726 | } | |
c5aff182 | 3727 | |
0db51da7 LB |
3728 | if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { |
3729 | netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); | |
3730 | return -EINVAL; | |
3731 | } | |
3732 | ||
c5aff182 TP |
3733 | dev->mtu = mtu; |
3734 | ||
b65657fc | 3735 | if (!netif_running(dev)) { |
dc35a10f MW |
3736 | if (pp->bm_priv) |
3737 | mvneta_bm_update_mtu(pp, mtu); | |
3738 | ||
b65657fc | 3739 | netdev_update_features(dev); |
c5aff182 | 3740 | return 0; |
b65657fc | 3741 | } |
c5aff182 | 3742 | |
6a20c175 | 3743 | /* The interface is running, so we have to force a |
a92dbd96 | 3744 | * reallocation of the queues |
c5aff182 TP |
3745 | */ |
3746 | mvneta_stop_dev(pp); | |
db5dd0db | 3747 | on_each_cpu(mvneta_percpu_disable, pp, true); |
c5aff182 TP |
3748 | |
3749 | mvneta_cleanup_txqs(pp); | |
3750 | mvneta_cleanup_rxqs(pp); | |
3751 | ||
dc35a10f MW |
3752 | if (pp->bm_priv) |
3753 | mvneta_bm_update_mtu(pp, mtu); | |
3754 | ||
a92dbd96 | 3755 | pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); |
c5aff182 TP |
3756 | |
3757 | ret = mvneta_setup_rxqs(pp); | |
3758 | if (ret) { | |
a92dbd96 | 3759 | netdev_err(dev, "unable to setup rxqs after MTU change\n"); |
c5aff182 TP |
3760 | return ret; |
3761 | } | |
3762 | ||
a92dbd96 EG |
3763 | ret = mvneta_setup_txqs(pp); |
3764 | if (ret) { | |
3765 | netdev_err(dev, "unable to setup txqs after MTU change\n"); | |
3766 | return ret; | |
3767 | } | |
c5aff182 | 3768 | |
db5dd0db | 3769 | on_each_cpu(mvneta_percpu_enable, pp, true); |
c5aff182 | 3770 | mvneta_start_dev(pp); |
c5aff182 | 3771 | |
b65657fc SG |
3772 | netdev_update_features(dev); |
3773 | ||
c5aff182 TP |
3774 | return 0; |
3775 | } | |
3776 | ||
b65657fc SG |
3777 | static netdev_features_t mvneta_fix_features(struct net_device *dev, |
3778 | netdev_features_t features) | |
3779 | { | |
3780 | struct mvneta_port *pp = netdev_priv(dev); | |
3781 | ||
3782 | if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { | |
3783 | features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); | |
3784 | netdev_info(dev, | |
3785 | "Disable IP checksum for MTU greater than %dB\n", | |
3786 | pp->tx_csum_limit); | |
3787 | } | |
3788 | ||
3789 | return features; | |
3790 | } | |
3791 | ||
8cc3e439 TP |
3792 | /* Get mac address */ |
3793 | static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) | |
3794 | { | |
3795 | u32 mac_addr_l, mac_addr_h; | |
3796 | ||
3797 | mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); | |
3798 | mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); | |
3799 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
3800 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
3801 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
3802 | addr[3] = mac_addr_h & 0xFF; | |
3803 | addr[4] = (mac_addr_l >> 8) & 0xFF; | |
3804 | addr[5] = mac_addr_l & 0xFF; | |
3805 | } | |
3806 | ||
c5aff182 TP |
3807 | /* Handle setting mac address */ |
3808 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) | |
3809 | { | |
3810 | struct mvneta_port *pp = netdev_priv(dev); | |
e68de360 EG |
3811 | struct sockaddr *sockaddr = addr; |
3812 | int ret; | |
c5aff182 | 3813 | |
e68de360 EG |
3814 | ret = eth_prepare_mac_addr_change(dev, addr); |
3815 | if (ret < 0) | |
3816 | return ret; | |
c5aff182 TP |
3817 | /* Remove previous address table entry */ |
3818 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); | |
3819 | ||
3820 | /* Set new addr in hw */ | |
90b74c01 | 3821 | mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); |
c5aff182 | 3822 | |
e68de360 | 3823 | eth_commit_mac_addr_change(dev, addr); |
c5aff182 TP |
3824 | return 0; |
3825 | } | |
3826 | ||
44cc27e4 IC |
3827 | static void mvneta_validate(struct phylink_config *config, |
3828 | unsigned long *supported, | |
503f9aa9 RK |
3829 | struct phylink_link_state *state) |
3830 | { | |
44cc27e4 | 3831 | struct net_device *ndev = to_net_dev(config->dev); |
a10c1c81 | 3832 | struct mvneta_port *pp = netdev_priv(ndev); |
503f9aa9 RK |
3833 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; |
3834 | ||
c762b7fa RKO |
3835 | /* We only support QSGMII, SGMII, 802.3z and RGMII modes. |
3836 | * When in 802.3z mode, we must have AN enabled: | |
3837 | * "Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... | |
3838 | * When <PortType> = 1 (1000BASE-X) this field must be set to 1." | |
3839 | */ | |
3840 | if (phy_interface_mode_is_8023z(state->interface)) { | |
3841 | if (!phylink_test(state->advertising, Autoneg)) { | |
3842 | bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
3843 | return; | |
3844 | } | |
3845 | } else if (state->interface != PHY_INTERFACE_MODE_NA && | |
3846 | state->interface != PHY_INTERFACE_MODE_QSGMII && | |
3847 | state->interface != PHY_INTERFACE_MODE_SGMII && | |
3848 | !phy_interface_mode_is_rgmii(state->interface)) { | |
503f9aa9 RK |
3849 | bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); |
3850 | return; | |
3851 | } | |
3852 | ||
3853 | /* Allow all the expected bits */ | |
3854 | phylink_set(mask, Autoneg); | |
3855 | phylink_set_port_modes(mask); | |
3856 | ||
4932a918 RK |
3857 | /* Asymmetric pause is unsupported */ |
3858 | phylink_set(mask, Pause); | |
da58a931 | 3859 | |
83e65df6 | 3860 | /* Half-duplex at speeds higher than 100Mbit is unsupported */ |
a10c1c81 RK |
3861 | if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { |
3862 | phylink_set(mask, 1000baseT_Full); | |
3863 | phylink_set(mask, 1000baseX_Full); | |
3864 | } | |
3865 | if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { | |
eda3d1b0 | 3866 | phylink_set(mask, 2500baseT_Full); |
a10c1c81 RK |
3867 | phylink_set(mask, 2500baseX_Full); |
3868 | } | |
22f4bf8a RK |
3869 | |
3870 | if (!phy_interface_mode_is_8023z(state->interface)) { | |
3871 | /* 10M and 100M are only supported in non-802.3z mode */ | |
3872 | phylink_set(mask, 10baseT_Half); | |
3873 | phylink_set(mask, 10baseT_Full); | |
3874 | phylink_set(mask, 100baseT_Half); | |
3875 | phylink_set(mask, 100baseT_Full); | |
3876 | } | |
503f9aa9 RK |
3877 | |
3878 | bitmap_and(supported, supported, mask, | |
3879 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
3880 | bitmap_and(state->advertising, state->advertising, mask, | |
3881 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
a10c1c81 RK |
3882 | |
3883 | /* We can only operate at 2500BaseX or 1000BaseX. If requested | |
3884 | * to advertise both, only report advertising at 2500BaseX. | |
3885 | */ | |
3886 | phylink_helper_basex_speed(state); | |
503f9aa9 RK |
3887 | } |
3888 | ||
d46b7e4f RK |
3889 | static void mvneta_mac_pcs_get_state(struct phylink_config *config, |
3890 | struct phylink_link_state *state) | |
c5aff182 | 3891 | { |
44cc27e4 | 3892 | struct net_device *ndev = to_net_dev(config->dev); |
c5aff182 | 3893 | struct mvneta_port *pp = netdev_priv(ndev); |
503f9aa9 | 3894 | u32 gmac_stat; |
c5aff182 | 3895 | |
503f9aa9 | 3896 | gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); |
c5aff182 | 3897 | |
503f9aa9 | 3898 | if (gmac_stat & MVNETA_GMAC_SPEED_1000) |
a10c1c81 RK |
3899 | state->speed = |
3900 | state->interface == PHY_INTERFACE_MODE_2500BASEX ? | |
3901 | SPEED_2500 : SPEED_1000; | |
503f9aa9 RK |
3902 | else if (gmac_stat & MVNETA_GMAC_SPEED_100) |
3903 | state->speed = SPEED_100; | |
3904 | else | |
3905 | state->speed = SPEED_10; | |
c5aff182 | 3906 | |
503f9aa9 RK |
3907 | state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); |
3908 | state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); | |
3909 | state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); | |
c5aff182 | 3910 | |
503f9aa9 | 3911 | state->pause = 0; |
4932a918 RK |
3912 | if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) |
3913 | state->pause |= MLO_PAUSE_RX; | |
3914 | if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) | |
3915 | state->pause |= MLO_PAUSE_TX; | |
503f9aa9 RK |
3916 | } |
3917 | ||
44cc27e4 | 3918 | static void mvneta_mac_an_restart(struct phylink_config *config) |
22f4bf8a | 3919 | { |
44cc27e4 | 3920 | struct net_device *ndev = to_net_dev(config->dev); |
22f4bf8a RK |
3921 | struct mvneta_port *pp = netdev_priv(ndev); |
3922 | u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
3923 | ||
3924 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3925 | gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); | |
3926 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3927 | gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); | |
3928 | } | |
3929 | ||
44cc27e4 IC |
3930 | static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, |
3931 | const struct phylink_link_state *state) | |
503f9aa9 | 3932 | { |
44cc27e4 | 3933 | struct net_device *ndev = to_net_dev(config->dev); |
503f9aa9 | 3934 | struct mvneta_port *pp = netdev_priv(ndev); |
22f4bf8a | 3935 | u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); |
503f9aa9 | 3936 | u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
da58a931 | 3937 | u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); |
503f9aa9 RK |
3938 | u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); |
3939 | u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
3940 | ||
22f4bf8a | 3941 | new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; |
32699954 RK |
3942 | new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | |
3943 | MVNETA_GMAC2_PORT_RESET); | |
da58a931 | 3944 | new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); |
503f9aa9 RK |
3945 | new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; |
3946 | new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | | |
3947 | MVNETA_GMAC_INBAND_RESTART_AN | | |
503f9aa9 | 3948 | MVNETA_GMAC_AN_SPEED_EN | |
22f4bf8a | 3949 | MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | |
503f9aa9 | 3950 | MVNETA_GMAC_AN_FLOW_CTRL_EN | |
503f9aa9 RK |
3951 | MVNETA_GMAC_AN_DUPLEX_EN); |
3952 | ||
32699954 RK |
3953 | /* Even though it might look weird, when we're configured in |
3954 | * SGMII or QSGMII mode, the RGMII bit needs to be set. | |
3955 | */ | |
3956 | new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; | |
3957 | ||
3958 | if (state->interface == PHY_INTERFACE_MODE_QSGMII || | |
22f4bf8a RK |
3959 | state->interface == PHY_INTERFACE_MODE_SGMII || |
3960 | phy_interface_mode_is_8023z(state->interface)) | |
32699954 RK |
3961 | new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; |
3962 | ||
4932a918 RK |
3963 | if (phylink_test(state->advertising, Pause)) |
3964 | new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; | |
4932a918 | 3965 | |
503f9aa9 | 3966 | if (!phylink_autoneg_inband(mode)) { |
ff03f0b1 RK |
3967 | /* Phy or fixed speed - nothing to do, leave the |
3968 | * configured speed, duplex and flow control as-is. | |
3969 | */ | |
22f4bf8a | 3970 | } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { |
503f9aa9 RK |
3971 | /* SGMII mode receives the state from the PHY */ |
3972 | new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; | |
3973 | new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
3974 | new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | | |
ff03f0b1 RK |
3975 | MVNETA_GMAC_FORCE_LINK_PASS | |
3976 | MVNETA_GMAC_CONFIG_MII_SPEED | | |
3977 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
3978 | MVNETA_GMAC_CONFIG_FULL_DUPLEX)) | | |
503f9aa9 RK |
3979 | MVNETA_GMAC_INBAND_AN_ENABLE | |
3980 | MVNETA_GMAC_AN_SPEED_EN | | |
3981 | MVNETA_GMAC_AN_DUPLEX_EN; | |
22f4bf8a RK |
3982 | } else { |
3983 | /* 802.3z negotiation - only 1000base-X */ | |
3984 | new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; | |
3985 | new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
3986 | new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | | |
ff03f0b1 RK |
3987 | MVNETA_GMAC_FORCE_LINK_PASS | |
3988 | MVNETA_GMAC_CONFIG_MII_SPEED)) | | |
22f4bf8a RK |
3989 | MVNETA_GMAC_INBAND_AN_ENABLE | |
3990 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
3991 | /* The MAC only supports FD mode */ | |
3992 | MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
4932a918 RK |
3993 | |
3994 | if (state->pause & MLO_PAUSE_AN && state->an_enabled) | |
3995 | new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; | |
503f9aa9 | 3996 | } |
c5aff182 | 3997 | |
503f9aa9 RK |
3998 | /* Armada 370 documentation says we can only change the port mode |
3999 | * and in-band enable when the link is down, so force it down | |
df4a17a9 YL |
4000 | * while making these changes. We also do this for GMAC_CTRL2 |
4001 | */ | |
22f4bf8a RK |
4002 | if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || |
4003 | (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || | |
503f9aa9 RK |
4004 | (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { |
4005 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
4006 | (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | | |
4007 | MVNETA_GMAC_FORCE_LINK_DOWN); | |
fc548b99 | 4008 | } |
503f9aa9 | 4009 | |
a10c1c81 | 4010 | |
da58a931 MC |
4011 | /* When at 2.5G, the link partner can send frames with shortened |
4012 | * preambles. | |
4013 | */ | |
f2ca673d | 4014 | if (state->interface == PHY_INTERFACE_MODE_2500BASEX) |
da58a931 MC |
4015 | new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; |
4016 | ||
b4748553 SH |
4017 | if (pp->phy_interface != state->interface) { |
4018 | if (pp->comphy) | |
4019 | WARN_ON(phy_power_off(pp->comphy)); | |
4020 | WARN_ON(mvneta_config_interface(pp, state->interface)); | |
031b922b | 4021 | } |
a10c1c81 | 4022 | |
22f4bf8a RK |
4023 | if (new_ctrl0 != gmac_ctrl0) |
4024 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); | |
503f9aa9 RK |
4025 | if (new_ctrl2 != gmac_ctrl2) |
4026 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); | |
da58a931 MC |
4027 | if (new_ctrl4 != gmac_ctrl4) |
4028 | mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); | |
503f9aa9 RK |
4029 | if (new_clk != gmac_clk) |
4030 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); | |
4031 | if (new_an != gmac_an) | |
4032 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); | |
32699954 RK |
4033 | |
4034 | if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { | |
4035 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
4036 | MVNETA_GMAC2_PORT_RESET) != 0) | |
4037 | continue; | |
4038 | } | |
fc548b99 | 4039 | } |
c5aff182 | 4040 | |
6d81f451 RK |
4041 | static void mvneta_set_eee(struct mvneta_port *pp, bool enable) |
4042 | { | |
4043 | u32 lpi_ctl1; | |
4044 | ||
4045 | lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); | |
4046 | if (enable) | |
4047 | lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; | |
4048 | else | |
4049 | lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; | |
4050 | mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); | |
4051 | } | |
4052 | ||
44cc27e4 IC |
4053 | static void mvneta_mac_link_down(struct phylink_config *config, |
4054 | unsigned int mode, phy_interface_t interface) | |
fc548b99 | 4055 | { |
44cc27e4 | 4056 | struct net_device *ndev = to_net_dev(config->dev); |
fc548b99 RK |
4057 | struct mvneta_port *pp = netdev_priv(ndev); |
4058 | u32 val; | |
4059 | ||
503f9aa9 RK |
4060 | mvneta_port_down(pp); |
4061 | ||
4062 | if (!phylink_autoneg_inband(mode)) { | |
fc548b99 RK |
4063 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
4064 | val &= ~MVNETA_GMAC_FORCE_LINK_PASS; | |
4065 | val |= MVNETA_GMAC_FORCE_LINK_DOWN; | |
4066 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
4067 | } | |
6d81f451 RK |
4068 | |
4069 | pp->eee_active = false; | |
4070 | mvneta_set_eee(pp, false); | |
fc548b99 RK |
4071 | } |
4072 | ||
91a208f2 RK |
4073 | static void mvneta_mac_link_up(struct phylink_config *config, |
4074 | struct phy_device *phy, | |
4075 | unsigned int mode, phy_interface_t interface, | |
4076 | int speed, int duplex, | |
4077 | bool tx_pause, bool rx_pause) | |
fc548b99 | 4078 | { |
44cc27e4 | 4079 | struct net_device *ndev = to_net_dev(config->dev); |
fc548b99 RK |
4080 | struct mvneta_port *pp = netdev_priv(ndev); |
4081 | u32 val; | |
4082 | ||
503f9aa9 | 4083 | if (!phylink_autoneg_inband(mode)) { |
fc548b99 | 4084 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
ff03f0b1 RK |
4085 | val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN | |
4086 | MVNETA_GMAC_CONFIG_MII_SPEED | | |
4087 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
4088 | MVNETA_GMAC_CONFIG_FLOW_CTRL | | |
4089 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); | |
fc548b99 | 4090 | val |= MVNETA_GMAC_FORCE_LINK_PASS; |
ff03f0b1 RK |
4091 | |
4092 | if (speed == SPEED_1000 || speed == SPEED_2500) | |
4093 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
4094 | else if (speed == SPEED_100) | |
4095 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; | |
4096 | ||
4097 | if (duplex == DUPLEX_FULL) | |
4098 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
4099 | ||
4100 | if (tx_pause || rx_pause) | |
4101 | val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; | |
4102 | ||
4103 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
4104 | } else { | |
4105 | /* When inband doesn't cover flow control or flow control is | |
4106 | * disabled, we need to manually configure it. This bit will | |
4107 | * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset. | |
4108 | */ | |
4109 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
4110 | val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL; | |
4111 | ||
4112 | if (tx_pause || rx_pause) | |
4113 | val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; | |
4114 | ||
fc548b99 | 4115 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); |
c5aff182 TP |
4116 | } |
4117 | ||
fc548b99 | 4118 | mvneta_port_up(pp); |
6d81f451 RK |
4119 | |
4120 | if (phy && pp->eee_enabled) { | |
4121 | pp->eee_active = phy_init_eee(phy, 0) >= 0; | |
4122 | mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); | |
4123 | } | |
fc548b99 RK |
4124 | } |
4125 | ||
503f9aa9 RK |
4126 | static const struct phylink_mac_ops mvneta_phylink_ops = { |
4127 | .validate = mvneta_validate, | |
d46b7e4f | 4128 | .mac_pcs_get_state = mvneta_mac_pcs_get_state, |
22f4bf8a | 4129 | .mac_an_restart = mvneta_mac_an_restart, |
503f9aa9 RK |
4130 | .mac_config = mvneta_mac_config, |
4131 | .mac_link_down = mvneta_mac_link_down, | |
4132 | .mac_link_up = mvneta_mac_link_up, | |
4133 | }; | |
c5aff182 TP |
4134 | |
4135 | static int mvneta_mdio_probe(struct mvneta_port *pp) | |
4136 | { | |
82960fff | 4137 | struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; |
503f9aa9 | 4138 | int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); |
c5aff182 | 4139 | |
503f9aa9 RK |
4140 | if (err) |
4141 | netdev_err(pp->dev, "could not attach PHY: %d\n", err); | |
c5aff182 | 4142 | |
503f9aa9 | 4143 | phylink_ethtool_get_wol(pp->phylink, &wol); |
82960fff JZ |
4144 | device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); |
4145 | ||
61b5cc20 DGC |
4146 | /* PHY WoL may be enabled but device wakeup disabled */ |
4147 | if (wol.supported) | |
4148 | device_set_wakeup_enable(&pp->dev->dev, !!wol.wolopts); | |
4149 | ||
503f9aa9 | 4150 | return err; |
c5aff182 TP |
4151 | } |
4152 | ||
4153 | static void mvneta_mdio_remove(struct mvneta_port *pp) | |
4154 | { | |
503f9aa9 | 4155 | phylink_disconnect_phy(pp->phylink); |
c5aff182 TP |
4156 | } |
4157 | ||
120cfa50 GC |
4158 | /* Electing a CPU must be done in an atomic way: it should be done |
4159 | * after or before the removal/insertion of a CPU and this function is | |
4160 | * not reentrant. | |
4161 | */ | |
f8642885 MR |
4162 | static void mvneta_percpu_elect(struct mvneta_port *pp) |
4163 | { | |
cad5d847 GC |
4164 | int elected_cpu = 0, max_cpu, cpu, i = 0; |
4165 | ||
4166 | /* Use the cpu associated to the rxq when it is online, in all | |
4167 | * the other cases, use the cpu 0 which can't be offline. | |
4168 | */ | |
4169 | if (cpu_online(pp->rxq_def)) | |
4170 | elected_cpu = pp->rxq_def; | |
f8642885 | 4171 | |
2dcf75e2 | 4172 | max_cpu = num_present_cpus(); |
f8642885 MR |
4173 | |
4174 | for_each_online_cpu(cpu) { | |
2dcf75e2 GC |
4175 | int rxq_map = 0, txq_map = 0; |
4176 | int rxq; | |
4177 | ||
4178 | for (rxq = 0; rxq < rxq_number; rxq++) | |
4179 | if ((rxq % max_cpu) == cpu) | |
4180 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
4181 | ||
cad5d847 | 4182 | if (cpu == elected_cpu) |
b52f6425 | 4183 | /* Map the default receive queue to the elected CPU */ |
2dcf75e2 | 4184 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); |
50bf8cb6 GC |
4185 | |
4186 | /* We update the TX queue map only if we have one | |
4187 | * queue. In this case we associate the TX queue to | |
4188 | * the CPU bound to the default RX queue | |
4189 | */ | |
4190 | if (txq_number == 1) | |
cad5d847 | 4191 | txq_map = (cpu == elected_cpu) ? |
50bf8cb6 GC |
4192 | MVNETA_CPU_TXQ_ACCESS(1) : 0; |
4193 | else | |
4194 | txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & | |
4195 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
4196 | ||
2dcf75e2 GC |
4197 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); |
4198 | ||
4199 | /* Update the interrupt mask on each CPU according the | |
4200 | * new mapping | |
4201 | */ | |
4202 | smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, | |
4203 | pp, true); | |
f8642885 | 4204 | i++; |
2dcf75e2 | 4205 | |
f8642885 MR |
4206 | } |
4207 | }; | |
4208 | ||
84a3f4db | 4209 | static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) |
f8642885 | 4210 | { |
84a3f4db SAS |
4211 | int other_cpu; |
4212 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
4213 | node_online); | |
f8642885 MR |
4214 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
4215 | ||
cf9bf871 MC |
4216 | /* Armada 3700's per-cpu interrupt for mvneta is broken, all interrupts |
4217 | * are routed to CPU 0, so we don't need all the cpu-hotplug support | |
4218 | */ | |
4219 | if (pp->neta_armada3700) | |
4220 | return 0; | |
f8642885 | 4221 | |
84a3f4db SAS |
4222 | spin_lock(&pp->lock); |
4223 | /* | |
4224 | * Configuring the driver for a new CPU while the driver is | |
4225 | * stopping is racy, so just avoid it. | |
4226 | */ | |
4227 | if (pp->is_stopped) { | |
4228 | spin_unlock(&pp->lock); | |
4229 | return 0; | |
4230 | } | |
4231 | netif_tx_stop_all_queues(pp->dev); | |
f8642885 | 4232 | |
84a3f4db SAS |
4233 | /* |
4234 | * We have to synchronise on tha napi of each CPU except the one | |
4235 | * just being woken up | |
4236 | */ | |
4237 | for_each_online_cpu(other_cpu) { | |
4238 | if (other_cpu != cpu) { | |
4239 | struct mvneta_pcpu_port *other_port = | |
4240 | per_cpu_ptr(pp->ports, other_cpu); | |
4241 | ||
4242 | napi_synchronize(&other_port->napi); | |
f8642885 | 4243 | } |
84a3f4db | 4244 | } |
f8642885 | 4245 | |
84a3f4db SAS |
4246 | /* Mask all ethernet port interrupts */ |
4247 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); | |
4248 | napi_enable(&port->napi); | |
f8642885 | 4249 | |
84a3f4db SAS |
4250 | /* |
4251 | * Enable per-CPU interrupts on the CPU that is | |
4252 | * brought up. | |
4253 | */ | |
4254 | mvneta_percpu_enable(pp); | |
2dcf75e2 | 4255 | |
84a3f4db SAS |
4256 | /* |
4257 | * Enable per-CPU interrupt on the one CPU we care | |
4258 | * about. | |
4259 | */ | |
4260 | mvneta_percpu_elect(pp); | |
2dcf75e2 | 4261 | |
84a3f4db SAS |
4262 | /* Unmask all ethernet port interrupts */ |
4263 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
4264 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
4265 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 4266 | MVNETA_CAUSE_LINK_CHANGE); |
84a3f4db SAS |
4267 | netif_tx_start_all_queues(pp->dev); |
4268 | spin_unlock(&pp->lock); | |
4269 | return 0; | |
4270 | } | |
f8642885 | 4271 | |
84a3f4db SAS |
4272 | static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) |
4273 | { | |
4274 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
4275 | node_online); | |
4276 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
f8642885 | 4277 | |
84a3f4db SAS |
4278 | /* |
4279 | * Thanks to this lock we are sure that any pending cpu election is | |
4280 | * done. | |
4281 | */ | |
4282 | spin_lock(&pp->lock); | |
4283 | /* Mask all ethernet port interrupts */ | |
4284 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); | |
4285 | spin_unlock(&pp->lock); | |
f8642885 | 4286 | |
84a3f4db SAS |
4287 | napi_synchronize(&port->napi); |
4288 | napi_disable(&port->napi); | |
4289 | /* Disable per-CPU interrupts on the CPU that is brought down. */ | |
4290 | mvneta_percpu_disable(pp); | |
4291 | return 0; | |
4292 | } | |
4293 | ||
4294 | static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) | |
4295 | { | |
4296 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
4297 | node_dead); | |
4298 | ||
4299 | /* Check if a new CPU must be elected now this on is down */ | |
4300 | spin_lock(&pp->lock); | |
4301 | mvneta_percpu_elect(pp); | |
4302 | spin_unlock(&pp->lock); | |
4303 | /* Unmask all ethernet port interrupts */ | |
4304 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
4305 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
4306 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
856b2cc5 | 4307 | MVNETA_CAUSE_LINK_CHANGE); |
84a3f4db SAS |
4308 | netif_tx_start_all_queues(pp->dev); |
4309 | return 0; | |
f8642885 MR |
4310 | } |
4311 | ||
c5aff182 TP |
4312 | static int mvneta_open(struct net_device *dev) |
4313 | { | |
4314 | struct mvneta_port *pp = netdev_priv(dev); | |
6b125d63 | 4315 | int ret; |
c5aff182 | 4316 | |
c5aff182 TP |
4317 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
4318 | ||
4319 | ret = mvneta_setup_rxqs(pp); | |
4320 | if (ret) | |
4321 | return ret; | |
4322 | ||
4323 | ret = mvneta_setup_txqs(pp); | |
4324 | if (ret) | |
4325 | goto err_cleanup_rxqs; | |
4326 | ||
4327 | /* Connect to port interrupt line */ | |
2636ac3c MW |
4328 | if (pp->neta_armada3700) |
4329 | ret = request_irq(pp->dev->irq, mvneta_isr, 0, | |
4330 | dev->name, pp); | |
4331 | else | |
4332 | ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, | |
4333 | dev->name, pp->ports); | |
c5aff182 TP |
4334 | if (ret) { |
4335 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); | |
4336 | goto err_cleanup_txqs; | |
4337 | } | |
4338 | ||
2636ac3c MW |
4339 | if (!pp->neta_armada3700) { |
4340 | /* Enable per-CPU interrupt on all the CPU to handle our RX | |
4341 | * queue interrupts | |
4342 | */ | |
4343 | on_each_cpu(mvneta_percpu_enable, pp, true); | |
2dcf75e2 | 4344 | |
2636ac3c MW |
4345 | pp->is_stopped = false; |
4346 | /* Register a CPU notifier to handle the case where our CPU | |
4347 | * might be taken offline. | |
4348 | */ | |
4349 | ret = cpuhp_state_add_instance_nocalls(online_hpstate, | |
4350 | &pp->node_online); | |
4351 | if (ret) | |
4352 | goto err_free_irq; | |
84a3f4db | 4353 | |
2636ac3c MW |
4354 | ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, |
4355 | &pp->node_dead); | |
4356 | if (ret) | |
4357 | goto err_free_online_hp; | |
4358 | } | |
f8642885 | 4359 | |
c5aff182 TP |
4360 | ret = mvneta_mdio_probe(pp); |
4361 | if (ret < 0) { | |
4362 | netdev_err(dev, "cannot probe MDIO bus\n"); | |
84a3f4db | 4363 | goto err_free_dead_hp; |
c5aff182 TP |
4364 | } |
4365 | ||
4366 | mvneta_start_dev(pp); | |
4367 | ||
4368 | return 0; | |
4369 | ||
84a3f4db | 4370 | err_free_dead_hp: |
2636ac3c MW |
4371 | if (!pp->neta_armada3700) |
4372 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
4373 | &pp->node_dead); | |
84a3f4db | 4374 | err_free_online_hp: |
2636ac3c MW |
4375 | if (!pp->neta_armada3700) |
4376 | cpuhp_state_remove_instance_nocalls(online_hpstate, | |
4377 | &pp->node_online); | |
c5aff182 | 4378 | err_free_irq: |
2636ac3c MW |
4379 | if (pp->neta_armada3700) { |
4380 | free_irq(pp->dev->irq, pp); | |
4381 | } else { | |
4382 | on_each_cpu(mvneta_percpu_disable, pp, true); | |
4383 | free_percpu_irq(pp->dev->irq, pp->ports); | |
4384 | } | |
c5aff182 TP |
4385 | err_cleanup_txqs: |
4386 | mvneta_cleanup_txqs(pp); | |
4387 | err_cleanup_rxqs: | |
4388 | mvneta_cleanup_rxqs(pp); | |
4389 | return ret; | |
4390 | } | |
4391 | ||
4392 | /* Stop the port, free port interrupt line */ | |
4393 | static int mvneta_stop(struct net_device *dev) | |
4394 | { | |
4395 | struct mvneta_port *pp = netdev_priv(dev); | |
4396 | ||
2636ac3c MW |
4397 | if (!pp->neta_armada3700) { |
4398 | /* Inform that we are stopping so we don't want to setup the | |
4399 | * driver for new CPUs in the notifiers. The code of the | |
4400 | * notifier for CPU online is protected by the same spinlock, | |
4401 | * so when we get the lock, the notifer work is done. | |
4402 | */ | |
4403 | spin_lock(&pp->lock); | |
4404 | pp->is_stopped = true; | |
4405 | spin_unlock(&pp->lock); | |
1c2722a9 | 4406 | |
2636ac3c MW |
4407 | mvneta_stop_dev(pp); |
4408 | mvneta_mdio_remove(pp); | |
84a3f4db | 4409 | |
d26aac2d DC |
4410 | cpuhp_state_remove_instance_nocalls(online_hpstate, |
4411 | &pp->node_online); | |
4412 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
4413 | &pp->node_dead); | |
2636ac3c MW |
4414 | on_each_cpu(mvneta_percpu_disable, pp, true); |
4415 | free_percpu_irq(dev->irq, pp->ports); | |
4416 | } else { | |
4417 | mvneta_stop_dev(pp); | |
4418 | mvneta_mdio_remove(pp); | |
4419 | free_irq(dev->irq, pp); | |
4420 | } | |
4421 | ||
c5aff182 TP |
4422 | mvneta_cleanup_rxqs(pp); |
4423 | mvneta_cleanup_txqs(pp); | |
c5aff182 TP |
4424 | |
4425 | return 0; | |
4426 | } | |
4427 | ||
15f59456 TP |
4428 | static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
4429 | { | |
503f9aa9 | 4430 | struct mvneta_port *pp = netdev_priv(dev); |
15f59456 | 4431 | |
503f9aa9 | 4432 | return phylink_mii_ioctl(pp->phylink, ifr, cmd); |
15f59456 TP |
4433 | } |
4434 | ||
0db51da7 LB |
4435 | static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, |
4436 | struct netlink_ext_ack *extack) | |
4437 | { | |
4438 | bool need_update, running = netif_running(dev); | |
4439 | struct mvneta_port *pp = netdev_priv(dev); | |
4440 | struct bpf_prog *old_prog; | |
4441 | ||
4442 | if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { | |
0d136f5c | 4443 | NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); |
0db51da7 | 4444 | return -EOPNOTSUPP; |
79572c98 SA |
4445 | } |
4446 | ||
4447 | if (pp->bm_priv) { | |
4448 | NL_SET_ERR_MSG_MOD(extack, | |
4449 | "Hardware Buffer Management not supported on XDP"); | |
4450 | return -EOPNOTSUPP; | |
0db51da7 LB |
4451 | } |
4452 | ||
4453 | need_update = !!pp->xdp_prog != !!prog; | |
4454 | if (running && need_update) | |
4455 | mvneta_stop(dev); | |
4456 | ||
4457 | old_prog = xchg(&pp->xdp_prog, prog); | |
4458 | if (old_prog) | |
4459 | bpf_prog_put(old_prog); | |
4460 | ||
4461 | if (running && need_update) | |
4462 | return mvneta_open(dev); | |
4463 | ||
4464 | return 0; | |
4465 | } | |
4466 | ||
4467 | static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) | |
4468 | { | |
0db51da7 LB |
4469 | switch (xdp->command) { |
4470 | case XDP_SETUP_PROG: | |
4471 | return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); | |
0db51da7 LB |
4472 | default: |
4473 | return -EINVAL; | |
4474 | } | |
4475 | } | |
4476 | ||
c5aff182 TP |
4477 | /* Ethtool methods */ |
4478 | ||
013ad40d | 4479 | /* Set link ksettings (phy address, speed) for ethtools */ |
2dc0d2b4 BX |
4480 | static int |
4481 | mvneta_ethtool_set_link_ksettings(struct net_device *ndev, | |
4482 | const struct ethtool_link_ksettings *cmd) | |
c5aff182 | 4483 | { |
013ad40d | 4484 | struct mvneta_port *pp = netdev_priv(ndev); |
0c0744fc | 4485 | |
503f9aa9 RK |
4486 | return phylink_ethtool_ksettings_set(pp->phylink, cmd); |
4487 | } | |
0c0744fc | 4488 | |
503f9aa9 RK |
4489 | /* Get link ksettings for ethtools */ |
4490 | static int | |
4491 | mvneta_ethtool_get_link_ksettings(struct net_device *ndev, | |
4492 | struct ethtool_link_ksettings *cmd) | |
4493 | { | |
4494 | struct mvneta_port *pp = netdev_priv(ndev); | |
0c0744fc | 4495 | |
503f9aa9 RK |
4496 | return phylink_ethtool_ksettings_get(pp->phylink, cmd); |
4497 | } | |
0c0744fc | 4498 | |
503f9aa9 RK |
4499 | static int mvneta_ethtool_nway_reset(struct net_device *dev) |
4500 | { | |
4501 | struct mvneta_port *pp = netdev_priv(dev); | |
0c0744fc | 4502 | |
503f9aa9 | 4503 | return phylink_ethtool_nway_reset(pp->phylink); |
c5aff182 TP |
4504 | } |
4505 | ||
4506 | /* Set interrupt coalescing for ethtools */ | |
4507 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, | |
4508 | struct ethtool_coalesce *c) | |
4509 | { | |
4510 | struct mvneta_port *pp = netdev_priv(dev); | |
4511 | int queue; | |
4512 | ||
4513 | for (queue = 0; queue < rxq_number; queue++) { | |
4514 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
4515 | rxq->time_coal = c->rx_coalesce_usecs; | |
4516 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
4517 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
4518 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
4519 | } | |
4520 | ||
4521 | for (queue = 0; queue < txq_number; queue++) { | |
4522 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
4523 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
4524 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
4525 | } | |
4526 | ||
4527 | return 0; | |
4528 | } | |
4529 | ||
4530 | /* get coalescing for ethtools */ | |
4531 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, | |
4532 | struct ethtool_coalesce *c) | |
4533 | { | |
4534 | struct mvneta_port *pp = netdev_priv(dev); | |
4535 | ||
4536 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; | |
4537 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; | |
4538 | ||
4539 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; | |
4540 | return 0; | |
4541 | } | |
4542 | ||
4543 | ||
4544 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, | |
4545 | struct ethtool_drvinfo *drvinfo) | |
4546 | { | |
4547 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, | |
4548 | sizeof(drvinfo->driver)); | |
4549 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, | |
4550 | sizeof(drvinfo->version)); | |
4551 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
4552 | sizeof(drvinfo->bus_info)); | |
4553 | } | |
4554 | ||
4555 | ||
4556 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, | |
4557 | struct ethtool_ringparam *ring) | |
4558 | { | |
4559 | struct mvneta_port *pp = netdev_priv(netdev); | |
4560 | ||
4561 | ring->rx_max_pending = MVNETA_MAX_RXD; | |
4562 | ring->tx_max_pending = MVNETA_MAX_TXD; | |
4563 | ring->rx_pending = pp->rx_ring_size; | |
4564 | ring->tx_pending = pp->tx_ring_size; | |
4565 | } | |
4566 | ||
4567 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, | |
4568 | struct ethtool_ringparam *ring) | |
4569 | { | |
4570 | struct mvneta_port *pp = netdev_priv(dev); | |
4571 | ||
4572 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) | |
4573 | return -EINVAL; | |
4574 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? | |
4575 | ring->rx_pending : MVNETA_MAX_RXD; | |
8eef5f97 EG |
4576 | |
4577 | pp->tx_ring_size = clamp_t(u16, ring->tx_pending, | |
4578 | MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); | |
4579 | if (pp->tx_ring_size != ring->tx_pending) | |
4580 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", | |
4581 | pp->tx_ring_size, ring->tx_pending); | |
c5aff182 TP |
4582 | |
4583 | if (netif_running(dev)) { | |
4584 | mvneta_stop(dev); | |
4585 | if (mvneta_open(dev)) { | |
4586 | netdev_err(dev, | |
4587 | "error on opening device after ring param change\n"); | |
4588 | return -ENOMEM; | |
4589 | } | |
4590 | } | |
4591 | ||
4592 | return 0; | |
4593 | } | |
4594 | ||
4932a918 RK |
4595 | static void mvneta_ethtool_get_pauseparam(struct net_device *dev, |
4596 | struct ethtool_pauseparam *pause) | |
4597 | { | |
4598 | struct mvneta_port *pp = netdev_priv(dev); | |
4599 | ||
4600 | phylink_ethtool_get_pauseparam(pp->phylink, pause); | |
4601 | } | |
4602 | ||
4603 | static int mvneta_ethtool_set_pauseparam(struct net_device *dev, | |
4604 | struct ethtool_pauseparam *pause) | |
4605 | { | |
4606 | struct mvneta_port *pp = netdev_priv(dev); | |
4607 | ||
4608 | return phylink_ethtool_set_pauseparam(pp->phylink, pause); | |
4609 | } | |
4610 | ||
9b0cdefa RK |
4611 | static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, |
4612 | u8 *data) | |
4613 | { | |
4614 | if (sset == ETH_SS_STATS) { | |
4615 | int i; | |
4616 | ||
4617 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
4618 | memcpy(data + i * ETH_GSTRING_LEN, | |
4619 | mvneta_statistics[i].name, ETH_GSTRING_LEN); | |
4620 | } | |
4621 | } | |
4622 | ||
9ac41f3c LB |
4623 | static void |
4624 | mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp, | |
4625 | struct mvneta_ethtool_stats *es) | |
4626 | { | |
4627 | unsigned int start; | |
4628 | int cpu; | |
4629 | ||
4630 | for_each_possible_cpu(cpu) { | |
4631 | struct mvneta_pcpu_stats *stats; | |
4632 | u64 skb_alloc_error; | |
4633 | u64 refill_error; | |
3d866523 | 4634 | u64 xdp_redirect; |
15070919 JDB |
4635 | u64 xdp_xmit_err; |
4636 | u64 xdp_tx_err; | |
3d866523 LB |
4637 | u64 xdp_pass; |
4638 | u64 xdp_drop; | |
7d51a015 | 4639 | u64 xdp_xmit; |
3d866523 | 4640 | u64 xdp_tx; |
9ac41f3c LB |
4641 | |
4642 | stats = per_cpu_ptr(pp->stats, cpu); | |
4643 | do { | |
4644 | start = u64_stats_fetch_begin_irq(&stats->syncp); | |
4645 | skb_alloc_error = stats->es.skb_alloc_error; | |
4646 | refill_error = stats->es.refill_error; | |
3d866523 LB |
4647 | xdp_redirect = stats->es.ps.xdp_redirect; |
4648 | xdp_pass = stats->es.ps.xdp_pass; | |
4649 | xdp_drop = stats->es.ps.xdp_drop; | |
7d51a015 | 4650 | xdp_xmit = stats->es.ps.xdp_xmit; |
15070919 | 4651 | xdp_xmit_err = stats->es.ps.xdp_xmit_err; |
3d866523 | 4652 | xdp_tx = stats->es.ps.xdp_tx; |
15070919 | 4653 | xdp_tx_err = stats->es.ps.xdp_tx_err; |
9ac41f3c LB |
4654 | } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); |
4655 | ||
4656 | es->skb_alloc_error += skb_alloc_error; | |
4657 | es->refill_error += refill_error; | |
3d866523 LB |
4658 | es->ps.xdp_redirect += xdp_redirect; |
4659 | es->ps.xdp_pass += xdp_pass; | |
4660 | es->ps.xdp_drop += xdp_drop; | |
7d51a015 | 4661 | es->ps.xdp_xmit += xdp_xmit; |
15070919 | 4662 | es->ps.xdp_xmit_err += xdp_xmit_err; |
3d866523 | 4663 | es->ps.xdp_tx += xdp_tx; |
15070919 | 4664 | es->ps.xdp_tx_err += xdp_tx_err; |
9ac41f3c LB |
4665 | } |
4666 | } | |
4667 | ||
9b0cdefa RK |
4668 | static void mvneta_ethtool_update_stats(struct mvneta_port *pp) |
4669 | { | |
9ac41f3c | 4670 | struct mvneta_ethtool_stats stats = {}; |
9b0cdefa RK |
4671 | const struct mvneta_statistic *s; |
4672 | void __iomem *base = pp->base; | |
6d81f451 RK |
4673 | u32 high, low; |
4674 | u64 val; | |
9b0cdefa RK |
4675 | int i; |
4676 | ||
9ac41f3c | 4677 | mvneta_ethtool_update_pcpu_stats(pp, &stats); |
9b0cdefa RK |
4678 | for (i = 0, s = mvneta_statistics; |
4679 | s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); | |
4680 | s++, i++) { | |
9b0cdefa RK |
4681 | switch (s->type) { |
4682 | case T_REG_32: | |
4683 | val = readl_relaxed(base + s->offset); | |
9ac41f3c | 4684 | pp->ethtool_stats[i] += val; |
9b0cdefa RK |
4685 | break; |
4686 | case T_REG_64: | |
4687 | /* Docs say to read low 32-bit then high */ | |
4688 | low = readl_relaxed(base + s->offset); | |
4689 | high = readl_relaxed(base + s->offset + 4); | |
6d81f451 | 4690 | val = (u64)high << 32 | low; |
9ac41f3c | 4691 | pp->ethtool_stats[i] += val; |
6d81f451 RK |
4692 | break; |
4693 | case T_SW: | |
4694 | switch (s->offset) { | |
4695 | case ETHTOOL_STAT_EEE_WAKEUP: | |
4696 | val = phylink_get_eee_err(pp->phylink); | |
9ac41f3c | 4697 | pp->ethtool_stats[i] += val; |
6d81f451 | 4698 | break; |
17a96da6 | 4699 | case ETHTOOL_STAT_SKB_ALLOC_ERR: |
9ac41f3c | 4700 | pp->ethtool_stats[i] = stats.skb_alloc_error; |
17a96da6 GC |
4701 | break; |
4702 | case ETHTOOL_STAT_REFILL_ERR: | |
9ac41f3c | 4703 | pp->ethtool_stats[i] = stats.refill_error; |
17a96da6 | 4704 | break; |
3d866523 LB |
4705 | case ETHTOOL_XDP_REDIRECT: |
4706 | pp->ethtool_stats[i] = stats.ps.xdp_redirect; | |
4707 | break; | |
4708 | case ETHTOOL_XDP_PASS: | |
4709 | pp->ethtool_stats[i] = stats.ps.xdp_pass; | |
4710 | break; | |
4711 | case ETHTOOL_XDP_DROP: | |
4712 | pp->ethtool_stats[i] = stats.ps.xdp_drop; | |
4713 | break; | |
4714 | case ETHTOOL_XDP_TX: | |
4715 | pp->ethtool_stats[i] = stats.ps.xdp_tx; | |
4716 | break; | |
15070919 JDB |
4717 | case ETHTOOL_XDP_TX_ERR: |
4718 | pp->ethtool_stats[i] = stats.ps.xdp_tx_err; | |
4719 | break; | |
7d51a015 LB |
4720 | case ETHTOOL_XDP_XMIT: |
4721 | pp->ethtool_stats[i] = stats.ps.xdp_xmit; | |
4722 | break; | |
15070919 JDB |
4723 | case ETHTOOL_XDP_XMIT_ERR: |
4724 | pp->ethtool_stats[i] = stats.ps.xdp_xmit_err; | |
4725 | break; | |
6d81f451 | 4726 | } |
9b0cdefa RK |
4727 | break; |
4728 | } | |
9b0cdefa RK |
4729 | } |
4730 | } | |
4731 | ||
4732 | static void mvneta_ethtool_get_stats(struct net_device *dev, | |
4733 | struct ethtool_stats *stats, u64 *data) | |
4734 | { | |
4735 | struct mvneta_port *pp = netdev_priv(dev); | |
4736 | int i; | |
4737 | ||
4738 | mvneta_ethtool_update_stats(pp); | |
4739 | ||
4740 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
4741 | *data++ = pp->ethtool_stats[i]; | |
4742 | } | |
4743 | ||
4744 | static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) | |
4745 | { | |
4746 | if (sset == ETH_SS_STATS) | |
4747 | return ARRAY_SIZE(mvneta_statistics); | |
4748 | return -EOPNOTSUPP; | |
4749 | } | |
4750 | ||
9a401dea GC |
4751 | static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) |
4752 | { | |
4753 | return MVNETA_RSS_LU_TABLE_SIZE; | |
4754 | } | |
4755 | ||
4756 | static int mvneta_ethtool_get_rxnfc(struct net_device *dev, | |
4757 | struct ethtool_rxnfc *info, | |
4758 | u32 *rules __always_unused) | |
4759 | { | |
4760 | switch (info->cmd) { | |
4761 | case ETHTOOL_GRXRINGS: | |
4762 | info->data = rxq_number; | |
4763 | return 0; | |
4764 | case ETHTOOL_GRXFH: | |
4765 | return -EOPNOTSUPP; | |
4766 | default: | |
4767 | return -EOPNOTSUPP; | |
4768 | } | |
4769 | } | |
4770 | ||
4771 | static int mvneta_config_rss(struct mvneta_port *pp) | |
4772 | { | |
4773 | int cpu; | |
4774 | u32 val; | |
4775 | ||
4776 | netif_tx_stop_all_queues(pp->dev); | |
4777 | ||
6b125d63 | 4778 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
9a401dea | 4779 | |
0f5c6c30 JZ |
4780 | if (!pp->neta_armada3700) { |
4781 | /* We have to synchronise on the napi of each CPU */ | |
4782 | for_each_online_cpu(cpu) { | |
4783 | struct mvneta_pcpu_port *pcpu_port = | |
4784 | per_cpu_ptr(pp->ports, cpu); | |
9a401dea | 4785 | |
0f5c6c30 JZ |
4786 | napi_synchronize(&pcpu_port->napi); |
4787 | napi_disable(&pcpu_port->napi); | |
4788 | } | |
4789 | } else { | |
4790 | napi_synchronize(&pp->napi); | |
4791 | napi_disable(&pp->napi); | |
9a401dea GC |
4792 | } |
4793 | ||
4794 | pp->rxq_def = pp->indir[0]; | |
4795 | ||
4796 | /* Update unicast mapping */ | |
4797 | mvneta_set_rx_mode(pp->dev); | |
4798 | ||
4799 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
4800 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); | |
4801 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
4802 | ||
4803 | /* Update the elected CPU matching the new rxq_def */ | |
120cfa50 | 4804 | spin_lock(&pp->lock); |
9a401dea | 4805 | mvneta_percpu_elect(pp); |
120cfa50 | 4806 | spin_unlock(&pp->lock); |
9a401dea | 4807 | |
0f5c6c30 JZ |
4808 | if (!pp->neta_armada3700) { |
4809 | /* We have to synchronise on the napi of each CPU */ | |
4810 | for_each_online_cpu(cpu) { | |
4811 | struct mvneta_pcpu_port *pcpu_port = | |
4812 | per_cpu_ptr(pp->ports, cpu); | |
9a401dea | 4813 | |
0f5c6c30 JZ |
4814 | napi_enable(&pcpu_port->napi); |
4815 | } | |
4816 | } else { | |
4817 | napi_enable(&pp->napi); | |
9a401dea GC |
4818 | } |
4819 | ||
4820 | netif_tx_start_all_queues(pp->dev); | |
4821 | ||
4822 | return 0; | |
4823 | } | |
4824 | ||
4825 | static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, | |
4826 | const u8 *key, const u8 hfunc) | |
4827 | { | |
4828 | struct mvneta_port *pp = netdev_priv(dev); | |
2636ac3c MW |
4829 | |
4830 | /* Current code for Armada 3700 doesn't support RSS features yet */ | |
4831 | if (pp->neta_armada3700) | |
4832 | return -EOPNOTSUPP; | |
4833 | ||
9a401dea GC |
4834 | /* We require at least one supported parameter to be changed |
4835 | * and no change in any of the unsupported parameters | |
4836 | */ | |
4837 | if (key || | |
4838 | (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) | |
4839 | return -EOPNOTSUPP; | |
4840 | ||
4841 | if (!indir) | |
4842 | return 0; | |
4843 | ||
4844 | memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); | |
4845 | ||
4846 | return mvneta_config_rss(pp); | |
4847 | } | |
4848 | ||
4849 | static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, | |
4850 | u8 *hfunc) | |
4851 | { | |
4852 | struct mvneta_port *pp = netdev_priv(dev); | |
4853 | ||
2636ac3c MW |
4854 | /* Current code for Armada 3700 doesn't support RSS features yet */ |
4855 | if (pp->neta_armada3700) | |
4856 | return -EOPNOTSUPP; | |
4857 | ||
9a401dea GC |
4858 | if (hfunc) |
4859 | *hfunc = ETH_RSS_HASH_TOP; | |
4860 | ||
4861 | if (!indir) | |
4862 | return 0; | |
4863 | ||
4864 | memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); | |
4865 | ||
4866 | return 0; | |
4867 | } | |
4868 | ||
b60a00f9 JH |
4869 | static void mvneta_ethtool_get_wol(struct net_device *dev, |
4870 | struct ethtool_wolinfo *wol) | |
4871 | { | |
503f9aa9 | 4872 | struct mvneta_port *pp = netdev_priv(dev); |
b60a00f9 | 4873 | |
503f9aa9 | 4874 | phylink_ethtool_get_wol(pp->phylink, wol); |
b60a00f9 JH |
4875 | } |
4876 | ||
4877 | static int mvneta_ethtool_set_wol(struct net_device *dev, | |
4878 | struct ethtool_wolinfo *wol) | |
4879 | { | |
503f9aa9 | 4880 | struct mvneta_port *pp = netdev_priv(dev); |
82960fff JZ |
4881 | int ret; |
4882 | ||
503f9aa9 | 4883 | ret = phylink_ethtool_set_wol(pp->phylink, wol); |
82960fff JZ |
4884 | if (!ret) |
4885 | device_set_wakeup_enable(&dev->dev, !!wol->wolopts); | |
4886 | ||
4887 | return ret; | |
b60a00f9 JH |
4888 | } |
4889 | ||
6d81f451 RK |
4890 | static int mvneta_ethtool_get_eee(struct net_device *dev, |
4891 | struct ethtool_eee *eee) | |
4892 | { | |
4893 | struct mvneta_port *pp = netdev_priv(dev); | |
4894 | u32 lpi_ctl0; | |
4895 | ||
4896 | lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); | |
4897 | ||
4898 | eee->eee_enabled = pp->eee_enabled; | |
4899 | eee->eee_active = pp->eee_active; | |
4900 | eee->tx_lpi_enabled = pp->tx_lpi_enabled; | |
4901 | eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; | |
4902 | ||
4903 | return phylink_ethtool_get_eee(pp->phylink, eee); | |
4904 | } | |
4905 | ||
4906 | static int mvneta_ethtool_set_eee(struct net_device *dev, | |
4907 | struct ethtool_eee *eee) | |
4908 | { | |
4909 | struct mvneta_port *pp = netdev_priv(dev); | |
4910 | u32 lpi_ctl0; | |
4911 | ||
4912 | /* The Armada 37x documents do not give limits for this other than | |
df4a17a9 YL |
4913 | * it being an 8-bit register. |
4914 | */ | |
e4a3e9ff | 4915 | if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) |
6d81f451 RK |
4916 | return -EINVAL; |
4917 | ||
4918 | lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); | |
4919 | lpi_ctl0 &= ~(0xff << 8); | |
4920 | lpi_ctl0 |= eee->tx_lpi_timer << 8; | |
4921 | mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); | |
4922 | ||
4923 | pp->eee_enabled = eee->eee_enabled; | |
4924 | pp->tx_lpi_enabled = eee->tx_lpi_enabled; | |
4925 | ||
4926 | mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); | |
4927 | ||
4928 | return phylink_ethtool_set_eee(pp->phylink, eee); | |
4929 | } | |
4930 | ||
4906887a MC |
4931 | static void mvneta_clear_rx_prio_map(struct mvneta_port *pp) |
4932 | { | |
4933 | mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0); | |
4934 | } | |
4935 | ||
4936 | static void mvneta_setup_rx_prio_map(struct mvneta_port *pp) | |
4937 | { | |
4938 | u32 val = 0; | |
4939 | int i; | |
4940 | ||
4941 | for (i = 0; i < rxq_number; i++) | |
4942 | val |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]); | |
4943 | ||
4944 | mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val); | |
4945 | } | |
4946 | ||
4947 | static int mvneta_setup_mqprio(struct net_device *dev, | |
4948 | struct tc_mqprio_qopt *qopt) | |
4949 | { | |
4950 | struct mvneta_port *pp = netdev_priv(dev); | |
4951 | u8 num_tc; | |
4952 | int i; | |
4953 | ||
4954 | qopt->hw = TC_MQPRIO_HW_OFFLOAD_TCS; | |
4955 | num_tc = qopt->num_tc; | |
4956 | ||
4957 | if (num_tc > rxq_number) | |
4958 | return -EINVAL; | |
4959 | ||
4960 | if (!num_tc) { | |
4961 | mvneta_clear_rx_prio_map(pp); | |
4962 | netdev_reset_tc(dev); | |
4963 | return 0; | |
4964 | } | |
4965 | ||
4966 | memcpy(pp->prio_tc_map, qopt->prio_tc_map, sizeof(pp->prio_tc_map)); | |
4967 | ||
4968 | mvneta_setup_rx_prio_map(pp); | |
4969 | ||
4970 | netdev_set_num_tc(dev, qopt->num_tc); | |
4971 | for (i = 0; i < qopt->num_tc; i++) | |
4972 | netdev_set_tc_queue(dev, i, qopt->count[i], qopt->offset[i]); | |
4973 | ||
4974 | return 0; | |
4975 | } | |
4976 | ||
4977 | static int mvneta_setup_tc(struct net_device *dev, enum tc_setup_type type, | |
4978 | void *type_data) | |
4979 | { | |
4980 | switch (type) { | |
4981 | case TC_SETUP_QDISC_MQPRIO: | |
4982 | return mvneta_setup_mqprio(dev, type_data); | |
4983 | default: | |
4984 | return -EOPNOTSUPP; | |
4985 | } | |
4986 | } | |
4987 | ||
c5aff182 TP |
4988 | static const struct net_device_ops mvneta_netdev_ops = { |
4989 | .ndo_open = mvneta_open, | |
4990 | .ndo_stop = mvneta_stop, | |
4991 | .ndo_start_xmit = mvneta_tx, | |
4992 | .ndo_set_rx_mode = mvneta_set_rx_mode, | |
4993 | .ndo_set_mac_address = mvneta_set_mac_addr, | |
4994 | .ndo_change_mtu = mvneta_change_mtu, | |
b65657fc | 4995 | .ndo_fix_features = mvneta_fix_features, |
c5aff182 | 4996 | .ndo_get_stats64 = mvneta_get_stats64, |
a7605370 | 4997 | .ndo_eth_ioctl = mvneta_ioctl, |
0db51da7 | 4998 | .ndo_bpf = mvneta_xdp, |
b0a43db9 | 4999 | .ndo_xdp_xmit = mvneta_xdp_xmit, |
4906887a | 5000 | .ndo_setup_tc = mvneta_setup_tc, |
c5aff182 TP |
5001 | }; |
5002 | ||
4581be42 | 5003 | static const struct ethtool_ops mvneta_eth_tool_ops = { |
16e8d8b3 JK |
5004 | .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | |
5005 | ETHTOOL_COALESCE_MAX_FRAMES, | |
503f9aa9 | 5006 | .nway_reset = mvneta_ethtool_nway_reset, |
c5aff182 | 5007 | .get_link = ethtool_op_get_link, |
c5aff182 TP |
5008 | .set_coalesce = mvneta_ethtool_set_coalesce, |
5009 | .get_coalesce = mvneta_ethtool_get_coalesce, | |
5010 | .get_drvinfo = mvneta_ethtool_get_drvinfo, | |
5011 | .get_ringparam = mvneta_ethtool_get_ringparam, | |
5012 | .set_ringparam = mvneta_ethtool_set_ringparam, | |
4932a918 RK |
5013 | .get_pauseparam = mvneta_ethtool_get_pauseparam, |
5014 | .set_pauseparam = mvneta_ethtool_set_pauseparam, | |
9b0cdefa RK |
5015 | .get_strings = mvneta_ethtool_get_strings, |
5016 | .get_ethtool_stats = mvneta_ethtool_get_stats, | |
5017 | .get_sset_count = mvneta_ethtool_get_sset_count, | |
9a401dea GC |
5018 | .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, |
5019 | .get_rxnfc = mvneta_ethtool_get_rxnfc, | |
5020 | .get_rxfh = mvneta_ethtool_get_rxfh, | |
5021 | .set_rxfh = mvneta_ethtool_set_rxfh, | |
503f9aa9 | 5022 | .get_link_ksettings = mvneta_ethtool_get_link_ksettings, |
013ad40d | 5023 | .set_link_ksettings = mvneta_ethtool_set_link_ksettings, |
b60a00f9 JH |
5024 | .get_wol = mvneta_ethtool_get_wol, |
5025 | .set_wol = mvneta_ethtool_set_wol, | |
6d81f451 RK |
5026 | .get_eee = mvneta_ethtool_get_eee, |
5027 | .set_eee = mvneta_ethtool_set_eee, | |
c5aff182 TP |
5028 | }; |
5029 | ||
5030 | /* Initialize hw */ | |
9672850b | 5031 | static int mvneta_init(struct device *dev, struct mvneta_port *pp) |
c5aff182 TP |
5032 | { |
5033 | int queue; | |
5034 | ||
5035 | /* Disable port */ | |
5036 | mvneta_port_disable(pp); | |
5037 | ||
5038 | /* Set port default values */ | |
5039 | mvneta_defaults_set(pp); | |
5040 | ||
5d6312ed | 5041 | pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); |
c5aff182 TP |
5042 | if (!pp->txqs) |
5043 | return -ENOMEM; | |
5044 | ||
5045 | /* Initialize TX descriptor rings */ | |
5046 | for (queue = 0; queue < txq_number; queue++) { | |
5047 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
5048 | txq->id = queue; | |
5049 | txq->size = pp->tx_ring_size; | |
5050 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; | |
5051 | } | |
5052 | ||
5d6312ed | 5053 | pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); |
9672850b | 5054 | if (!pp->rxqs) |
c5aff182 | 5055 | return -ENOMEM; |
c5aff182 TP |
5056 | |
5057 | /* Create Rx descriptor rings */ | |
5058 | for (queue = 0; queue < rxq_number; queue++) { | |
5059 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
5060 | rxq->id = queue; | |
5061 | rxq->size = pp->rx_ring_size; | |
5062 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; | |
5063 | rxq->time_coal = MVNETA_RX_COAL_USEC; | |
29110630 ME |
5064 | rxq->buf_virt_addr |
5065 | = devm_kmalloc_array(pp->dev->dev.parent, | |
5066 | rxq->size, | |
5067 | sizeof(*rxq->buf_virt_addr), | |
5068 | GFP_KERNEL); | |
f88bee1c GC |
5069 | if (!rxq->buf_virt_addr) |
5070 | return -ENOMEM; | |
c5aff182 TP |
5071 | } |
5072 | ||
5073 | return 0; | |
5074 | } | |
5075 | ||
c5aff182 | 5076 | /* platform glue : initialize decoding windows */ |
03ce758e GK |
5077 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
5078 | const struct mbus_dram_target_info *dram) | |
c5aff182 TP |
5079 | { |
5080 | u32 win_enable; | |
5081 | u32 win_protect; | |
5082 | int i; | |
5083 | ||
5084 | for (i = 0; i < 6; i++) { | |
5085 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
5086 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
5087 | ||
5088 | if (i < 4) | |
5089 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
5090 | } | |
5091 | ||
5092 | win_enable = 0x3f; | |
5093 | win_protect = 0; | |
5094 | ||
2636ac3c MW |
5095 | if (dram) { |
5096 | for (i = 0; i < dram->num_cs; i++) { | |
5097 | const struct mbus_dram_window *cs = dram->cs + i; | |
5098 | ||
5099 | mvreg_write(pp, MVNETA_WIN_BASE(i), | |
5100 | (cs->base & 0xffff0000) | | |
5101 | (cs->mbus_attr << 8) | | |
5102 | dram->mbus_dram_target_id); | |
c5aff182 | 5103 | |
2636ac3c MW |
5104 | mvreg_write(pp, MVNETA_WIN_SIZE(i), |
5105 | (cs->size - 1) & 0xffff0000); | |
c5aff182 | 5106 | |
2636ac3c MW |
5107 | win_enable &= ~(1 << i); |
5108 | win_protect |= 3 << (2 * i); | |
5109 | } | |
5110 | } else { | |
5111 | /* For Armada3700 open default 4GB Mbus window, leaving | |
5112 | * arbitration of target/attribute to a different layer | |
5113 | * of configuration. | |
5114 | */ | |
5115 | mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); | |
5116 | win_enable &= ~BIT(0); | |
5117 | win_protect = 3; | |
c5aff182 TP |
5118 | } |
5119 | ||
5120 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
db6ba9a5 | 5121 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); |
c5aff182 TP |
5122 | } |
5123 | ||
5124 | /* Power up the port */ | |
3f1dd4bc | 5125 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
c5aff182 | 5126 | { |
c5aff182 TP |
5127 | /* MAC Cause register should be cleared */ |
5128 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
5129 | ||
41c2b6b4 SH |
5130 | if (phy_mode != PHY_INTERFACE_MODE_QSGMII && |
5131 | phy_mode != PHY_INTERFACE_MODE_SGMII && | |
5132 | !phy_interface_mode_is_8023z(phy_mode) && | |
5133 | !phy_interface_mode_is_rgmii(phy_mode)) | |
3f1dd4bc | 5134 | return -EINVAL; |
3f1dd4bc TP |
5135 | |
5136 | return 0; | |
c5aff182 TP |
5137 | } |
5138 | ||
5139 | /* Device initialization routine */ | |
03ce758e | 5140 | static int mvneta_probe(struct platform_device *pdev) |
c5aff182 | 5141 | { |
c5aff182 | 5142 | struct device_node *dn = pdev->dev.of_node; |
dc35a10f | 5143 | struct device_node *bm_node; |
c5aff182 TP |
5144 | struct mvneta_port *pp; |
5145 | struct net_device *dev; | |
503f9aa9 | 5146 | struct phylink *phylink; |
a10c1c81 | 5147 | struct phy *comphy; |
8cc3e439 | 5148 | char hw_mac_addr[ETH_ALEN]; |
0c65b2b9 | 5149 | phy_interface_t phy_mode; |
8cc3e439 | 5150 | const char *mac_from; |
9110ee07 | 5151 | int tx_csum_limit; |
c5aff182 | 5152 | int err; |
12bb03b4 | 5153 | int cpu; |
c5aff182 | 5154 | |
a3ddd94f RP |
5155 | dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), |
5156 | txq_number, rxq_number); | |
c5aff182 TP |
5157 | if (!dev) |
5158 | return -ENOMEM; | |
5159 | ||
5160 | dev->irq = irq_of_parse_and_map(dn, 0); | |
a3ddd94f RP |
5161 | if (dev->irq == 0) |
5162 | return -EINVAL; | |
c5aff182 | 5163 | |
0c65b2b9 AL |
5164 | err = of_get_phy_mode(dn, &phy_mode); |
5165 | if (err) { | |
c5aff182 | 5166 | dev_err(&pdev->dev, "incorrect phy-mode\n"); |
503f9aa9 RK |
5167 | goto err_free_irq; |
5168 | } | |
5169 | ||
a10c1c81 RK |
5170 | comphy = devm_of_phy_get(&pdev->dev, dn, NULL); |
5171 | if (comphy == ERR_PTR(-EPROBE_DEFER)) { | |
5172 | err = -EPROBE_DEFER; | |
5173 | goto err_free_irq; | |
5174 | } else if (IS_ERR(comphy)) { | |
5175 | comphy = NULL; | |
5176 | } | |
5177 | ||
44cc27e4 IC |
5178 | pp = netdev_priv(dev); |
5179 | spin_lock_init(&pp->lock); | |
5180 | ||
5181 | pp->phylink_config.dev = &dev->dev; | |
5182 | pp->phylink_config.type = PHYLINK_NETDEV; | |
5183 | ||
5184 | phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, | |
5185 | phy_mode, &mvneta_phylink_ops); | |
503f9aa9 RK |
5186 | if (IS_ERR(phylink)) { |
5187 | err = PTR_ERR(phylink); | |
5188 | goto err_free_irq; | |
c5aff182 TP |
5189 | } |
5190 | ||
c5aff182 TP |
5191 | dev->tx_queue_len = MVNETA_MAX_TXD; |
5192 | dev->watchdog_timeo = 5 * HZ; | |
5193 | dev->netdev_ops = &mvneta_netdev_ops; | |
5194 | ||
7ad24ea4 | 5195 | dev->ethtool_ops = &mvneta_eth_tool_ops; |
c5aff182 | 5196 | |
503f9aa9 | 5197 | pp->phylink = phylink; |
a10c1c81 | 5198 | pp->comphy = comphy; |
c5aff182 | 5199 | pp->phy_interface = phy_mode; |
503f9aa9 | 5200 | pp->dn = dn; |
c5aff182 | 5201 | |
90b74c01 | 5202 | pp->rxq_def = rxq_def; |
9a401dea GC |
5203 | pp->indir[0] = rxq_def; |
5204 | ||
2636ac3c MW |
5205 | /* Get special SoC configurations */ |
5206 | if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) | |
5207 | pp->neta_armada3700 = true; | |
5208 | ||
2804ba4e JZ |
5209 | pp->clk = devm_clk_get(&pdev->dev, "core"); |
5210 | if (IS_ERR(pp->clk)) | |
5211 | pp->clk = devm_clk_get(&pdev->dev, NULL); | |
189dd626 TP |
5212 | if (IS_ERR(pp->clk)) { |
5213 | err = PTR_ERR(pp->clk); | |
503f9aa9 | 5214 | goto err_free_phylink; |
189dd626 TP |
5215 | } |
5216 | ||
5217 | clk_prepare_enable(pp->clk); | |
5218 | ||
15cc4a4a JZ |
5219 | pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); |
5220 | if (!IS_ERR(pp->clk_bus)) | |
5221 | clk_prepare_enable(pp->clk_bus); | |
5222 | ||
00c33afb | 5223 | pp->base = devm_platform_ioremap_resource(pdev, 0); |
c3f0dd38 TP |
5224 | if (IS_ERR(pp->base)) { |
5225 | err = PTR_ERR(pp->base); | |
5445eaf3 APR |
5226 | goto err_clk; |
5227 | } | |
5228 | ||
12bb03b4 MR |
5229 | /* Alloc per-cpu port structure */ |
5230 | pp->ports = alloc_percpu(struct mvneta_pcpu_port); | |
5231 | if (!pp->ports) { | |
5232 | err = -ENOMEM; | |
5233 | goto err_clk; | |
5234 | } | |
5235 | ||
74c41b04 | 5236 | /* Alloc per-cpu stats */ |
1c213bd2 | 5237 | pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); |
74c41b04 | 5238 | if (!pp->stats) { |
5239 | err = -ENOMEM; | |
12bb03b4 | 5240 | goto err_free_ports; |
74c41b04 | 5241 | } |
5242 | ||
83216e39 MW |
5243 | err = of_get_mac_address(dn, dev->dev_addr); |
5244 | if (!err) { | |
8cc3e439 | 5245 | mac_from = "device tree"; |
8cc3e439 TP |
5246 | } else { |
5247 | mvneta_get_mac_addr(pp, hw_mac_addr); | |
5248 | if (is_valid_ether_addr(hw_mac_addr)) { | |
5249 | mac_from = "hardware"; | |
5250 | memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); | |
5251 | } else { | |
5252 | mac_from = "random"; | |
5253 | eth_hw_addr_random(dev); | |
5254 | } | |
5255 | } | |
5256 | ||
9110ee07 MW |
5257 | if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { |
5258 | if (tx_csum_limit < 0 || | |
5259 | tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { | |
5260 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
5261 | dev_info(&pdev->dev, | |
5262 | "Wrong TX csum limit in DT, set to %dB\n", | |
5263 | MVNETA_TX_CSUM_DEF_SIZE); | |
5264 | } | |
5265 | } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { | |
5266 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
5267 | } else { | |
5268 | tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; | |
5269 | } | |
5270 | ||
5271 | pp->tx_csum_limit = tx_csum_limit; | |
b65657fc | 5272 | |
9768b45c | 5273 | pp->dram_target_info = mv_mbus_dram_info(); |
2636ac3c MW |
5274 | /* Armada3700 requires setting default configuration of Mbus |
5275 | * windows, however without using filled mbus_dram_target_info | |
5276 | * structure. | |
5277 | */ | |
9768b45c JL |
5278 | if (pp->dram_target_info || pp->neta_armada3700) |
5279 | mvneta_conf_mbus_windows(pp, pp->dram_target_info); | |
dc35a10f | 5280 | |
c5aff182 TP |
5281 | pp->tx_ring_size = MVNETA_MAX_TXD; |
5282 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
5283 | ||
5284 | pp->dev = dev; | |
5285 | SET_NETDEV_DEV(dev, &pdev->dev); | |
5286 | ||
dc35a10f MW |
5287 | pp->id = global_port_id++; |
5288 | ||
5289 | /* Obtain access to BM resources if enabled and already initialized */ | |
5290 | bm_node = of_parse_phandle(dn, "buffer-manager", 0); | |
965cbbec GC |
5291 | if (bm_node) { |
5292 | pp->bm_priv = mvneta_bm_get(bm_node); | |
5293 | if (pp->bm_priv) { | |
5294 | err = mvneta_bm_port_init(pdev, pp); | |
5295 | if (err < 0) { | |
5296 | dev_info(&pdev->dev, | |
5297 | "use SW buffer management\n"); | |
5298 | mvneta_bm_put(pp->bm_priv); | |
5299 | pp->bm_priv = NULL; | |
5300 | } | |
dc35a10f | 5301 | } |
562e2f46 YK |
5302 | /* Set RX packet offset correction for platforms, whose |
5303 | * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit | |
5304 | * platforms and 0B for 32-bit ones. | |
5305 | */ | |
5306 | pp->rx_offset_correction = max(0, | |
5307 | NET_SKB_PAD - | |
5308 | MVNETA_RX_PKT_OFFSET_CORRECTION); | |
dc35a10f | 5309 | } |
d4e4da00 | 5310 | of_node_put(bm_node); |
dc35a10f | 5311 | |
44efc78d LB |
5312 | /* sw buffer management */ |
5313 | if (!pp->bm_priv) | |
5314 | pp->rx_offset_correction = MVNETA_SKB_HEADROOM; | |
5315 | ||
9672850b EG |
5316 | err = mvneta_init(&pdev->dev, pp); |
5317 | if (err < 0) | |
dc35a10f | 5318 | goto err_netdev; |
3f1dd4bc | 5319 | |
41c2b6b4 | 5320 | err = mvneta_port_power_up(pp, pp->phy_interface); |
3f1dd4bc TP |
5321 | if (err < 0) { |
5322 | dev_err(&pdev->dev, "can't power up port\n"); | |
58f60329 | 5323 | goto err_netdev; |
3f1dd4bc | 5324 | } |
c5aff182 | 5325 | |
2636ac3c MW |
5326 | /* Armada3700 network controller does not support per-cpu |
5327 | * operation, so only single NAPI should be initialized. | |
5328 | */ | |
5329 | if (pp->neta_armada3700) { | |
5330 | netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); | |
5331 | } else { | |
5332 | for_each_present_cpu(cpu) { | |
5333 | struct mvneta_pcpu_port *port = | |
5334 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 5335 | |
2636ac3c MW |
5336 | netif_napi_add(dev, &port->napi, mvneta_poll, |
5337 | NAPI_POLL_WEIGHT); | |
5338 | port->pp = pp; | |
5339 | } | |
12bb03b4 | 5340 | } |
c5aff182 | 5341 | |
7772988a JZ |
5342 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
5343 | NETIF_F_TSO | NETIF_F_RXCSUM; | |
01ef26ca EG |
5344 | dev->hw_features |= dev->features; |
5345 | dev->vlan_features |= dev->features; | |
97db8afa | 5346 | dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; |
8eef5f97 | 5347 | dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; |
b50b72de | 5348 | |
5777987e JW |
5349 | /* MTU range: 68 - 9676 */ |
5350 | dev->min_mtu = ETH_MIN_MTU; | |
5351 | /* 9676 == 9700 - 20 and rounding to 8 */ | |
5352 | dev->max_mtu = 9676; | |
5353 | ||
c5aff182 TP |
5354 | err = register_netdev(dev); |
5355 | if (err < 0) { | |
5356 | dev_err(&pdev->dev, "failed to register\n"); | |
d484e06e | 5357 | goto err_netdev; |
c5aff182 TP |
5358 | } |
5359 | ||
8cc3e439 TP |
5360 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, |
5361 | dev->dev_addr); | |
c5aff182 TP |
5362 | |
5363 | platform_set_drvdata(pdev, pp->dev); | |
5364 | ||
5365 | return 0; | |
5366 | ||
dc35a10f | 5367 | err_netdev: |
dc35a10f MW |
5368 | if (pp->bm_priv) { |
5369 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
5370 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
5371 | 1 << pp->id); | |
965cbbec | 5372 | mvneta_bm_put(pp->bm_priv); |
dc35a10f | 5373 | } |
74c41b04 | 5374 | free_percpu(pp->stats); |
12bb03b4 MR |
5375 | err_free_ports: |
5376 | free_percpu(pp->ports); | |
5445eaf3 | 5377 | err_clk: |
15cc4a4a | 5378 | clk_disable_unprepare(pp->clk_bus); |
5445eaf3 | 5379 | clk_disable_unprepare(pp->clk); |
503f9aa9 RK |
5380 | err_free_phylink: |
5381 | if (pp->phylink) | |
5382 | phylink_destroy(pp->phylink); | |
c5aff182 TP |
5383 | err_free_irq: |
5384 | irq_dispose_mapping(dev->irq); | |
c5aff182 TP |
5385 | return err; |
5386 | } | |
5387 | ||
5388 | /* Device removal routine */ | |
03ce758e | 5389 | static int mvneta_remove(struct platform_device *pdev) |
c5aff182 TP |
5390 | { |
5391 | struct net_device *dev = platform_get_drvdata(pdev); | |
5392 | struct mvneta_port *pp = netdev_priv(dev); | |
5393 | ||
5394 | unregister_netdev(dev); | |
15cc4a4a | 5395 | clk_disable_unprepare(pp->clk_bus); |
189dd626 | 5396 | clk_disable_unprepare(pp->clk); |
12bb03b4 | 5397 | free_percpu(pp->ports); |
74c41b04 | 5398 | free_percpu(pp->stats); |
c5aff182 | 5399 | irq_dispose_mapping(dev->irq); |
503f9aa9 | 5400 | phylink_destroy(pp->phylink); |
c5aff182 | 5401 | |
dc35a10f MW |
5402 | if (pp->bm_priv) { |
5403 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
5404 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
5405 | 1 << pp->id); | |
965cbbec | 5406 | mvneta_bm_put(pp->bm_priv); |
dc35a10f MW |
5407 | } |
5408 | ||
c5aff182 TP |
5409 | return 0; |
5410 | } | |
5411 | ||
9768b45c JL |
5412 | #ifdef CONFIG_PM_SLEEP |
5413 | static int mvneta_suspend(struct device *device) | |
5414 | { | |
1799cdd2 | 5415 | int queue; |
9768b45c JL |
5416 | struct net_device *dev = dev_get_drvdata(device); |
5417 | struct mvneta_port *pp = netdev_priv(dev); | |
5418 | ||
1799cdd2 JZ |
5419 | if (!netif_running(dev)) |
5420 | goto clean_exit; | |
5421 | ||
5422 | if (!pp->neta_armada3700) { | |
5423 | spin_lock(&pp->lock); | |
5424 | pp->is_stopped = true; | |
5425 | spin_unlock(&pp->lock); | |
5426 | ||
5427 | cpuhp_state_remove_instance_nocalls(online_hpstate, | |
5428 | &pp->node_online); | |
5429 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
5430 | &pp->node_dead); | |
5431 | } | |
5432 | ||
3b8bc674 | 5433 | rtnl_lock(); |
1799cdd2 | 5434 | mvneta_stop_dev(pp); |
3b8bc674 | 5435 | rtnl_unlock(); |
1799cdd2 JZ |
5436 | |
5437 | for (queue = 0; queue < rxq_number; queue++) { | |
5438 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
5439 | ||
5440 | mvneta_rxq_drop_pkts(pp, rxq); | |
5441 | } | |
5442 | ||
5443 | for (queue = 0; queue < txq_number; queue++) { | |
5444 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
5445 | ||
5446 | mvneta_txq_hw_deinit(pp, txq); | |
5447 | } | |
5448 | ||
5449 | clean_exit: | |
9768b45c JL |
5450 | netif_device_detach(dev); |
5451 | clk_disable_unprepare(pp->clk_bus); | |
5452 | clk_disable_unprepare(pp->clk); | |
1799cdd2 | 5453 | |
9768b45c JL |
5454 | return 0; |
5455 | } | |
5456 | ||
5457 | static int mvneta_resume(struct device *device) | |
5458 | { | |
5459 | struct platform_device *pdev = to_platform_device(device); | |
5460 | struct net_device *dev = dev_get_drvdata(device); | |
5461 | struct mvneta_port *pp = netdev_priv(dev); | |
1799cdd2 | 5462 | int err, queue; |
9768b45c JL |
5463 | |
5464 | clk_prepare_enable(pp->clk); | |
5465 | if (!IS_ERR(pp->clk_bus)) | |
5466 | clk_prepare_enable(pp->clk_bus); | |
5467 | if (pp->dram_target_info || pp->neta_armada3700) | |
5468 | mvneta_conf_mbus_windows(pp, pp->dram_target_info); | |
5469 | if (pp->bm_priv) { | |
5470 | err = mvneta_bm_port_init(pdev, pp); | |
5471 | if (err < 0) { | |
5472 | dev_info(&pdev->dev, "use SW buffer management\n"); | |
44efc78d | 5473 | pp->rx_offset_correction = MVNETA_SKB_HEADROOM; |
9768b45c JL |
5474 | pp->bm_priv = NULL; |
5475 | } | |
5476 | } | |
5477 | mvneta_defaults_set(pp); | |
5478 | err = mvneta_port_power_up(pp, pp->phy_interface); | |
5479 | if (err < 0) { | |
5480 | dev_err(device, "can't power up port\n"); | |
5481 | return err; | |
5482 | } | |
5483 | ||
9768b45c | 5484 | netif_device_attach(dev); |
1799cdd2 JZ |
5485 | |
5486 | if (!netif_running(dev)) | |
5487 | return 0; | |
5488 | ||
5489 | for (queue = 0; queue < rxq_number; queue++) { | |
5490 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
5491 | ||
5492 | rxq->next_desc_to_proc = 0; | |
5493 | mvneta_rxq_hw_init(pp, rxq); | |
5494 | } | |
5495 | ||
5496 | for (queue = 0; queue < txq_number; queue++) { | |
5497 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
5498 | ||
5499 | txq->next_desc_to_proc = 0; | |
5500 | mvneta_txq_hw_init(pp, txq); | |
d6956ac8 | 5501 | } |
1799cdd2 JZ |
5502 | |
5503 | if (!pp->neta_armada3700) { | |
5504 | spin_lock(&pp->lock); | |
5505 | pp->is_stopped = false; | |
5506 | spin_unlock(&pp->lock); | |
5507 | cpuhp_state_add_instance_nocalls(online_hpstate, | |
5508 | &pp->node_online); | |
5509 | cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
5510 | &pp->node_dead); | |
5511 | } | |
5512 | ||
5513 | rtnl_lock(); | |
5514 | mvneta_start_dev(pp); | |
3b8bc674 | 5515 | rtnl_unlock(); |
1799cdd2 | 5516 | mvneta_set_rx_mode(dev); |
d6956ac8 | 5517 | |
9768b45c JL |
5518 | return 0; |
5519 | } | |
5520 | #endif | |
5521 | ||
5522 | static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); | |
5523 | ||
c5aff182 TP |
5524 | static const struct of_device_id mvneta_match[] = { |
5525 | { .compatible = "marvell,armada-370-neta" }, | |
f522a975 | 5526 | { .compatible = "marvell,armada-xp-neta" }, |
2636ac3c | 5527 | { .compatible = "marvell,armada-3700-neta" }, |
c5aff182 TP |
5528 | { } |
5529 | }; | |
5530 | MODULE_DEVICE_TABLE(of, mvneta_match); | |
5531 | ||
5532 | static struct platform_driver mvneta_driver = { | |
5533 | .probe = mvneta_probe, | |
03ce758e | 5534 | .remove = mvneta_remove, |
c5aff182 TP |
5535 | .driver = { |
5536 | .name = MVNETA_DRIVER_NAME, | |
5537 | .of_match_table = mvneta_match, | |
9768b45c | 5538 | .pm = &mvneta_pm_ops, |
c5aff182 TP |
5539 | }, |
5540 | }; | |
5541 | ||
84a3f4db SAS |
5542 | static int __init mvneta_driver_init(void) |
5543 | { | |
5544 | int ret; | |
5545 | ||
664d035c | 5546 | ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online", |
84a3f4db SAS |
5547 | mvneta_cpu_online, |
5548 | mvneta_cpu_down_prepare); | |
5549 | if (ret < 0) | |
5550 | goto out; | |
5551 | online_hpstate = ret; | |
5552 | ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", | |
5553 | NULL, mvneta_cpu_dead); | |
5554 | if (ret) | |
5555 | goto err_dead; | |
5556 | ||
5557 | ret = platform_driver_register(&mvneta_driver); | |
5558 | if (ret) | |
5559 | goto err; | |
5560 | return 0; | |
5561 | ||
5562 | err: | |
5563 | cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); | |
5564 | err_dead: | |
5565 | cpuhp_remove_multi_state(online_hpstate); | |
5566 | out: | |
5567 | return ret; | |
5568 | } | |
5569 | module_init(mvneta_driver_init); | |
5570 | ||
5571 | static void __exit mvneta_driver_exit(void) | |
5572 | { | |
5573 | platform_driver_unregister(&mvneta_driver); | |
5574 | cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); | |
5575 | cpuhp_remove_multi_state(online_hpstate); | |
5576 | } | |
5577 | module_exit(mvneta_driver_exit); | |
c5aff182 TP |
5578 | |
5579 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); | |
5580 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
5581 | MODULE_LICENSE("GPL"); | |
5582 | ||
d3757ba4 JP |
5583 | module_param(rxq_number, int, 0444); |
5584 | module_param(txq_number, int, 0444); | |
c5aff182 | 5585 | |
d3757ba4 JP |
5586 | module_param(rxq_def, int, 0444); |
5587 | module_param(rx_copybreak, int, 0644); |