Commit | Line | Data |
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c5aff182 TP |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Rami Rosen <rosenr@marvell.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
0e03f563 JZ |
14 | #include <linux/clk.h> |
15 | #include <linux/cpu.h> | |
c5aff182 | 16 | #include <linux/etherdevice.h> |
0e03f563 | 17 | #include <linux/if_vlan.h> |
c5aff182 | 18 | #include <linux/inetdevice.h> |
c5aff182 | 19 | #include <linux/interrupt.h> |
c3f0dd38 | 20 | #include <linux/io.h> |
0e03f563 JZ |
21 | #include <linux/kernel.h> |
22 | #include <linux/mbus.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/netdevice.h> | |
c5aff182 | 25 | #include <linux/of.h> |
0e03f563 | 26 | #include <linux/of_address.h> |
c5aff182 TP |
27 | #include <linux/of_irq.h> |
28 | #include <linux/of_mdio.h> | |
29 | #include <linux/of_net.h> | |
c5aff182 | 30 | #include <linux/phy.h> |
0e03f563 JZ |
31 | #include <linux/platform_device.h> |
32 | #include <linux/skbuff.h> | |
baa11ebc | 33 | #include <net/hwbm.h> |
dc35a10f | 34 | #include "mvneta_bm.h" |
0e03f563 JZ |
35 | #include <net/ip.h> |
36 | #include <net/ipv6.h> | |
37 | #include <net/tso.h> | |
c5aff182 TP |
38 | |
39 | /* Registers */ | |
40 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
e5bdf689 | 41 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) |
dc35a10f MW |
42 | #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 |
43 | #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 | |
44 | #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 | |
45 | #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 | |
c5aff182 TP |
46 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) |
47 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
48 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
49 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
50 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
51 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
52 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
53 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
54 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
55 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
56 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
57 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
58 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
dc35a10f MW |
59 | #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) |
60 | #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 | |
61 | #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 | |
c5aff182 TP |
62 | #define MVNETA_PORT_RX_RESET 0x1cc0 |
63 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
64 | #define MVNETA_PHY_ADDR 0x2000 | |
65 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
66 | #define MVNETA_MBUS_RETRY 0x2010 | |
67 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
68 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
69 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
70 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
71 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
72 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
73 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 | |
db6ba9a5 | 74 | #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 |
c5aff182 TP |
75 | #define MVNETA_PORT_CONFIG 0x2400 |
76 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
77 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
78 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
79 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
80 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
81 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
82 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
83 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
84 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
85 | MVNETA_DEF_RXQ_ARP(q) | \ | |
86 | MVNETA_DEF_RXQ_TCP(q) | \ | |
87 | MVNETA_DEF_RXQ_UDP(q) | \ | |
88 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
89 | MVNETA_TX_UNSET_ERR_SUM | \ | |
90 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
91 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
92 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
93 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
94 | #define MVNETA_SDMA_CONFIG 0x241c | |
95 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
c5aff182 TP |
96 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
97 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
98 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
9ad8fef6 | 99 | #define MVNETA_DESC_SWAP BIT(6) |
c5aff182 TP |
100 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
101 | #define MVNETA_PORT_STATUS 0x2444 | |
102 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
103 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
104 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
3f1dd4bc | 105 | #define MVNETA_SERDES_CFG 0x24A0 |
5445eaf3 | 106 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 |
3f1dd4bc | 107 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 |
c5aff182 TP |
108 | #define MVNETA_TYPE_PRIO 0x24bc |
109 | #define MVNETA_FORCE_UNI BIT(21) | |
110 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
111 | #define MVNETA_TXQ_CMD 0x2448 | |
112 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
113 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
e483911f AL |
114 | #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 |
115 | #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 | |
898b2970 SS |
116 | #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 |
117 | #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) | |
c5aff182 | 118 | #define MVNETA_ACC_MODE 0x2500 |
dc35a10f | 119 | #define MVNETA_BM_ADDRESS 0x2504 |
c5aff182 TP |
120 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) |
121 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
122 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
2dcf75e2 | 123 | #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) |
50bf8cb6 | 124 | #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) |
c5aff182 | 125 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) |
40ba35e7 | 126 | |
2dcf75e2 GC |
127 | /* Exception Interrupt Port/Queue Cause register |
128 | * | |
129 | * Their behavior depend of the mapping done using the PCPX2Q | |
130 | * registers. For a given CPU if the bit associated to a queue is not | |
131 | * set, then for the register a read from this CPU will always return | |
132 | * 0 and a write won't do anything | |
133 | */ | |
40ba35e7 | 134 | |
c5aff182 | 135 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
c5aff182 | 136 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
40ba35e7 | 137 | |
138 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
139 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
140 | * bits 16..23 = RXQ FREE, one bit per queue. | |
141 | * bit 29 = OLD_REG_SUM, see old reg ? | |
142 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
143 | * bit 31 = MISC_SUM, one bit for 4 ports | |
144 | */ | |
145 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
146 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
147 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
148 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
898b2970 | 149 | #define MVNETA_MISCINTR_INTR_MASK BIT(31) |
40ba35e7 | 150 | |
c5aff182 TP |
151 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
152 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
40ba35e7 | 153 | |
154 | /* Data Path Port/Queue Cause Register */ | |
c5aff182 TP |
155 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
156 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
40ba35e7 | 157 | |
158 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) | |
159 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) | |
160 | #define MVNETA_CAUSE_PTP BIT(4) | |
161 | ||
162 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) | |
163 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) | |
164 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) | |
165 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) | |
166 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) | |
167 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) | |
168 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) | |
169 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) | |
170 | ||
171 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 | |
172 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) | |
173 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) | |
174 | ||
175 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 | |
176 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) | |
177 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) | |
178 | ||
c5aff182 TP |
179 | #define MVNETA_INTR_ENABLE 0x25b8 |
180 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 | |
dc1aadf6 | 181 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff |
40ba35e7 | 182 | |
c5aff182 TP |
183 | #define MVNETA_RXQ_CMD 0x2680 |
184 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
185 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
186 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
187 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
188 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
189 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
190 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
191 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) | |
192 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
898b2970 | 193 | #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) |
a79121d3 | 194 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
c5aff182 TP |
195 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
196 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
197 | #define MVNETA_GMAC_STATUS 0x2c10 | |
198 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
199 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
200 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
201 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
202 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
203 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
204 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
205 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
206 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c | |
207 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
208 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
898b2970 | 209 | #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) |
c5aff182 TP |
210 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) |
211 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
71408602 | 212 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
898b2970 | 213 | #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) |
c5aff182 | 214 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
71408602 | 215 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
e483911f | 216 | #define MVNETA_MIB_COUNTERS_BASE 0x3000 |
c5aff182 TP |
217 | #define MVNETA_MIB_LATE_COLLISION 0x7c |
218 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
219 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
220 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
221 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
222 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
223 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
224 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
225 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
226 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
2a90f7e1 | 227 | #define MVNETA_TXQ_DEC_SENT_MASK 0xff |
c5aff182 TP |
228 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) |
229 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
230 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
231 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
232 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
233 | #define MVNETA_TX_MTU 0x3e0c | |
234 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
235 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
236 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
237 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
238 | ||
239 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff | |
240 | ||
241 | /* Descriptor ring Macros */ | |
242 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
243 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
244 | ||
245 | /* Various constants */ | |
246 | ||
247 | /* Coalescing */ | |
06708f81 | 248 | #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ |
c5aff182 TP |
249 | #define MVNETA_RX_COAL_PKTS 32 |
250 | #define MVNETA_RX_COAL_USEC 100 | |
251 | ||
6a20c175 | 252 | /* The two bytes Marvell header. Either contains a special value used |
c5aff182 TP |
253 | * by Marvell switches when a specific hardware mode is enabled (not |
254 | * supported by this driver) or is filled automatically by zeroes on | |
255 | * the RX side. Those two bytes being at the front of the Ethernet | |
256 | * header, they allow to have the IP header aligned on a 4 bytes | |
257 | * boundary automatically: the hardware skips those two bytes on its | |
258 | * own. | |
259 | */ | |
260 | #define MVNETA_MH_SIZE 2 | |
261 | ||
262 | #define MVNETA_VLAN_TAG_LEN 4 | |
263 | ||
9110ee07 | 264 | #define MVNETA_TX_CSUM_DEF_SIZE 1600 |
c5aff182 | 265 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 |
dc35a10f MW |
266 | #define MVNETA_ACC_MODE_EXT1 1 |
267 | #define MVNETA_ACC_MODE_EXT2 2 | |
268 | ||
269 | #define MVNETA_MAX_DECODE_WIN 6 | |
c5aff182 TP |
270 | |
271 | /* Timeout constants */ | |
272 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
273 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
274 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
275 | ||
276 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
277 | ||
9a401dea GC |
278 | /* The RSS lookup table actually has 256 entries but we do not use |
279 | * them yet | |
280 | */ | |
281 | #define MVNETA_RSS_LU_TABLE_SIZE 1 | |
282 | ||
2adb719d EG |
283 | /* TSO header size */ |
284 | #define TSO_HEADER_SIZE 128 | |
285 | ||
c5aff182 TP |
286 | /* Max number of Rx descriptors */ |
287 | #define MVNETA_MAX_RXD 128 | |
288 | ||
289 | /* Max number of Tx descriptors */ | |
290 | #define MVNETA_MAX_TXD 532 | |
291 | ||
8eef5f97 EG |
292 | /* Max number of allowed TCP segments for software TSO */ |
293 | #define MVNETA_MAX_TSO_SEGS 100 | |
294 | ||
295 | #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
296 | ||
c5aff182 TP |
297 | /* descriptor aligned size */ |
298 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
299 | ||
8d5047cf MW |
300 | /* Number of bytes to be taken into account by HW when putting incoming data |
301 | * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet | |
302 | * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. | |
303 | */ | |
304 | #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 | |
305 | ||
c5aff182 TP |
306 | #define MVNETA_RX_PKT_SIZE(mtu) \ |
307 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ | |
308 | ETH_HLEN + ETH_FCS_LEN, \ | |
c66e98c9 | 309 | cache_line_size()) |
c5aff182 | 310 | |
2e3173a3 EG |
311 | #define IS_TSO_HEADER(txq, addr) \ |
312 | ((addr >= txq->tso_hdrs_phys) && \ | |
313 | (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) | |
314 | ||
dc35a10f MW |
315 | #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ |
316 | (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) | |
c5aff182 | 317 | |
9b0cdefa RK |
318 | struct mvneta_statistic { |
319 | unsigned short offset; | |
320 | unsigned short type; | |
321 | const char name[ETH_GSTRING_LEN]; | |
322 | }; | |
323 | ||
324 | #define T_REG_32 32 | |
325 | #define T_REG_64 64 | |
326 | ||
327 | static const struct mvneta_statistic mvneta_statistics[] = { | |
328 | { 0x3000, T_REG_64, "good_octets_received", }, | |
329 | { 0x3010, T_REG_32, "good_frames_received", }, | |
330 | { 0x3008, T_REG_32, "bad_octets_received", }, | |
331 | { 0x3014, T_REG_32, "bad_frames_received", }, | |
332 | { 0x3018, T_REG_32, "broadcast_frames_received", }, | |
333 | { 0x301c, T_REG_32, "multicast_frames_received", }, | |
334 | { 0x3050, T_REG_32, "unrec_mac_control_received", }, | |
335 | { 0x3058, T_REG_32, "good_fc_received", }, | |
336 | { 0x305c, T_REG_32, "bad_fc_received", }, | |
337 | { 0x3060, T_REG_32, "undersize_received", }, | |
338 | { 0x3064, T_REG_32, "fragments_received", }, | |
339 | { 0x3068, T_REG_32, "oversize_received", }, | |
340 | { 0x306c, T_REG_32, "jabber_received", }, | |
341 | { 0x3070, T_REG_32, "mac_receive_error", }, | |
342 | { 0x3074, T_REG_32, "bad_crc_event", }, | |
343 | { 0x3078, T_REG_32, "collision", }, | |
344 | { 0x307c, T_REG_32, "late_collision", }, | |
345 | { 0x2484, T_REG_32, "rx_discard", }, | |
346 | { 0x2488, T_REG_32, "rx_overrun", }, | |
347 | { 0x3020, T_REG_32, "frames_64_octets", }, | |
348 | { 0x3024, T_REG_32, "frames_65_to_127_octets", }, | |
349 | { 0x3028, T_REG_32, "frames_128_to_255_octets", }, | |
350 | { 0x302c, T_REG_32, "frames_256_to_511_octets", }, | |
351 | { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, | |
352 | { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, | |
353 | { 0x3038, T_REG_64, "good_octets_sent", }, | |
354 | { 0x3040, T_REG_32, "good_frames_sent", }, | |
355 | { 0x3044, T_REG_32, "excessive_collision", }, | |
356 | { 0x3048, T_REG_32, "multicast_frames_sent", }, | |
357 | { 0x304c, T_REG_32, "broadcast_frames_sent", }, | |
358 | { 0x3054, T_REG_32, "fc_sent", }, | |
359 | { 0x300c, T_REG_32, "internal_mac_transmit_err", }, | |
360 | }; | |
361 | ||
74c41b04 | 362 | struct mvneta_pcpu_stats { |
c5aff182 | 363 | struct u64_stats_sync syncp; |
74c41b04 | 364 | u64 rx_packets; |
365 | u64 rx_bytes; | |
366 | u64 tx_packets; | |
367 | u64 tx_bytes; | |
c5aff182 TP |
368 | }; |
369 | ||
12bb03b4 MR |
370 | struct mvneta_pcpu_port { |
371 | /* Pointer to the shared port */ | |
372 | struct mvneta_port *pp; | |
373 | ||
374 | /* Pointer to the CPU-local NAPI struct */ | |
375 | struct napi_struct napi; | |
376 | ||
377 | /* Cause of the previous interrupt */ | |
378 | u32 cause_rx_tx; | |
379 | }; | |
380 | ||
c5aff182 | 381 | struct mvneta_port { |
dc35a10f | 382 | u8 id; |
12bb03b4 MR |
383 | struct mvneta_pcpu_port __percpu *ports; |
384 | struct mvneta_pcpu_stats __percpu *stats; | |
385 | ||
c5aff182 | 386 | int pkt_size; |
8ec2cd48 | 387 | unsigned int frag_size; |
c5aff182 TP |
388 | void __iomem *base; |
389 | struct mvneta_rx_queue *rxqs; | |
390 | struct mvneta_tx_queue *txqs; | |
c5aff182 | 391 | struct net_device *dev; |
84a3f4db SAS |
392 | struct hlist_node node_online; |
393 | struct hlist_node node_dead; | |
90b74c01 | 394 | int rxq_def; |
5888511e GC |
395 | /* Protect the access to the percpu interrupt registers, |
396 | * ensuring that the configuration remains coherent. | |
397 | */ | |
398 | spinlock_t lock; | |
120cfa50 | 399 | bool is_stopped; |
c5aff182 | 400 | |
2636ac3c MW |
401 | u32 cause_rx_tx; |
402 | struct napi_struct napi; | |
403 | ||
c5aff182 | 404 | /* Core clock */ |
189dd626 | 405 | struct clk *clk; |
15cc4a4a JZ |
406 | /* AXI clock */ |
407 | struct clk *clk_bus; | |
c5aff182 TP |
408 | u8 mcast_count[256]; |
409 | u16 tx_ring_size; | |
410 | u16 rx_ring_size; | |
c5aff182 TP |
411 | |
412 | struct mii_bus *mii_bus; | |
c5aff182 TP |
413 | phy_interface_t phy_interface; |
414 | struct device_node *phy_node; | |
415 | unsigned int link; | |
416 | unsigned int duplex; | |
417 | unsigned int speed; | |
b65657fc | 418 | unsigned int tx_csum_limit; |
0c0744fc | 419 | unsigned int use_inband_status:1; |
9b0cdefa | 420 | |
dc35a10f MW |
421 | struct mvneta_bm *bm_priv; |
422 | struct mvneta_bm_pool *pool_long; | |
423 | struct mvneta_bm_pool *pool_short; | |
424 | int bm_win_id; | |
425 | ||
9b0cdefa | 426 | u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; |
9a401dea GC |
427 | |
428 | u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; | |
2636ac3c MW |
429 | |
430 | /* Flags for special SoC configurations */ | |
431 | bool neta_armada3700; | |
8d5047cf | 432 | u16 rx_offset_correction; |
c5aff182 TP |
433 | }; |
434 | ||
6a20c175 | 435 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
c5aff182 TP |
436 | * layout of the transmit and reception DMA descriptors, and their |
437 | * layout is therefore defined by the hardware design | |
438 | */ | |
6083ed44 | 439 | |
c5aff182 TP |
440 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
441 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
442 | #define MVNETA_TX_L4_UDP BIT(16) | |
443 | #define MVNETA_TX_L3_IP6 BIT(17) | |
444 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
445 | #define MVNETA_TXD_Z_PAD BIT(19) | |
446 | #define MVNETA_TXD_L_DESC BIT(20) | |
447 | #define MVNETA_TXD_F_DESC BIT(21) | |
448 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
449 | MVNETA_TXD_L_DESC | \ | |
450 | MVNETA_TXD_F_DESC) | |
451 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
452 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
453 | ||
c5aff182 | 454 | #define MVNETA_RXD_ERR_CRC 0x0 |
dc35a10f MW |
455 | #define MVNETA_RXD_BM_POOL_SHIFT 13 |
456 | #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) | |
c5aff182 TP |
457 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) |
458 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
459 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
460 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
461 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
462 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
463 | #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) | |
464 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) | |
465 | ||
9ad8fef6 | 466 | #if defined(__LITTLE_ENDIAN) |
6083ed44 TP |
467 | struct mvneta_tx_desc { |
468 | u32 command; /* Options used by HW for packet transmitting.*/ | |
469 | u16 reserverd1; /* csum_l4 (for future use) */ | |
470 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
471 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
472 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
473 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
474 | }; | |
475 | ||
476 | struct mvneta_rx_desc { | |
477 | u32 status; /* Info about received packet */ | |
c5aff182 TP |
478 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
479 | u16 data_size; /* Size of received packet in bytes */ | |
6083ed44 | 480 | |
c5aff182 TP |
481 | u32 buf_phys_addr; /* Physical address of the buffer */ |
482 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
6083ed44 | 483 | |
c5aff182 TP |
484 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
485 | u16 reserved3; /* prefetch_cmd, for future use */ | |
486 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
6083ed44 | 487 | |
c5aff182 TP |
488 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
489 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
490 | }; | |
9ad8fef6 TP |
491 | #else |
492 | struct mvneta_tx_desc { | |
493 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
494 | u16 reserverd1; /* csum_l4 (for future use) */ | |
495 | u32 command; /* Options used by HW for packet transmitting.*/ | |
496 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
497 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
498 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
499 | }; | |
500 | ||
501 | struct mvneta_rx_desc { | |
502 | u16 data_size; /* Size of received packet in bytes */ | |
503 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
504 | u32 status; /* Info about received packet */ | |
505 | ||
506 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
507 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
508 | ||
509 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
510 | u16 reserved3; /* prefetch_cmd, for future use */ | |
511 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
512 | ||
513 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
514 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
515 | }; | |
516 | #endif | |
c5aff182 TP |
517 | |
518 | struct mvneta_tx_queue { | |
519 | /* Number of this TX queue, in the range 0-7 */ | |
520 | u8 id; | |
521 | ||
522 | /* Number of TX DMA descriptors in the descriptor ring */ | |
523 | int size; | |
524 | ||
525 | /* Number of currently used TX DMA descriptor in the | |
6a20c175 TP |
526 | * descriptor ring |
527 | */ | |
c5aff182 | 528 | int count; |
2a90f7e1 | 529 | int pending; |
8eef5f97 EG |
530 | int tx_stop_threshold; |
531 | int tx_wake_threshold; | |
c5aff182 TP |
532 | |
533 | /* Array of transmitted skb */ | |
534 | struct sk_buff **tx_skb; | |
535 | ||
536 | /* Index of last TX DMA descriptor that was inserted */ | |
537 | int txq_put_index; | |
538 | ||
539 | /* Index of the TX DMA descriptor to be cleaned up */ | |
540 | int txq_get_index; | |
541 | ||
542 | u32 done_pkts_coal; | |
543 | ||
544 | /* Virtual address of the TX DMA descriptors array */ | |
545 | struct mvneta_tx_desc *descs; | |
546 | ||
547 | /* DMA address of the TX DMA descriptors array */ | |
548 | dma_addr_t descs_phys; | |
549 | ||
550 | /* Index of the last TX DMA descriptor */ | |
551 | int last_desc; | |
552 | ||
553 | /* Index of the next TX DMA descriptor to process */ | |
554 | int next_desc_to_proc; | |
2adb719d EG |
555 | |
556 | /* DMA buffers for TSO headers */ | |
557 | char *tso_hdrs; | |
558 | ||
559 | /* DMA address of TSO headers */ | |
560 | dma_addr_t tso_hdrs_phys; | |
50bf8cb6 GC |
561 | |
562 | /* Affinity mask for CPUs*/ | |
563 | cpumask_t affinity_mask; | |
c5aff182 TP |
564 | }; |
565 | ||
566 | struct mvneta_rx_queue { | |
567 | /* rx queue number, in the range 0-7 */ | |
568 | u8 id; | |
569 | ||
570 | /* num of rx descriptors in the rx descriptor ring */ | |
571 | int size; | |
572 | ||
573 | /* counter of times when mvneta_refill() failed */ | |
574 | int missed; | |
575 | ||
576 | u32 pkts_coal; | |
577 | u32 time_coal; | |
578 | ||
f88bee1c GC |
579 | /* Virtual address of the RX buffer */ |
580 | void **buf_virt_addr; | |
581 | ||
c5aff182 TP |
582 | /* Virtual address of the RX DMA descriptors array */ |
583 | struct mvneta_rx_desc *descs; | |
584 | ||
585 | /* DMA address of the RX DMA descriptors array */ | |
586 | dma_addr_t descs_phys; | |
587 | ||
588 | /* Index of the last RX DMA descriptor */ | |
589 | int last_desc; | |
590 | ||
591 | /* Index of the next RX DMA descriptor to process */ | |
592 | int next_desc_to_proc; | |
593 | }; | |
594 | ||
84a3f4db | 595 | static enum cpuhp_state online_hpstate; |
edadb7fa EG |
596 | /* The hardware supports eight (8) rx queues, but we are only allowing |
597 | * the first one to be used. Therefore, let's just allocate one queue. | |
598 | */ | |
d8936657 | 599 | static int rxq_number = 8; |
c5aff182 TP |
600 | static int txq_number = 8; |
601 | ||
602 | static int rxq_def; | |
c5aff182 | 603 | |
f19fadfc | 604 | static int rx_copybreak __read_mostly = 256; |
605 | ||
dc35a10f MW |
606 | /* HW BM need that each port be identify by a unique ID */ |
607 | static int global_port_id; | |
608 | ||
c5aff182 TP |
609 | #define MVNETA_DRIVER_NAME "mvneta" |
610 | #define MVNETA_DRIVER_VERSION "1.0" | |
611 | ||
612 | /* Utility/helper methods */ | |
613 | ||
614 | /* Write helper method */ | |
615 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
616 | { | |
617 | writel(data, pp->base + offset); | |
618 | } | |
619 | ||
620 | /* Read helper method */ | |
621 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
622 | { | |
623 | return readl(pp->base + offset); | |
624 | } | |
625 | ||
626 | /* Increment txq get counter */ | |
627 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) | |
628 | { | |
629 | txq->txq_get_index++; | |
630 | if (txq->txq_get_index == txq->size) | |
631 | txq->txq_get_index = 0; | |
632 | } | |
633 | ||
634 | /* Increment txq put counter */ | |
635 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) | |
636 | { | |
637 | txq->txq_put_index++; | |
638 | if (txq->txq_put_index == txq->size) | |
639 | txq->txq_put_index = 0; | |
640 | } | |
641 | ||
642 | ||
643 | /* Clear all MIB counters */ | |
644 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
645 | { | |
646 | int i; | |
647 | u32 dummy; | |
648 | ||
649 | /* Perform dummy reads from MIB counters */ | |
650 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
651 | dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); | |
e483911f AL |
652 | dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); |
653 | dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); | |
c5aff182 TP |
654 | } |
655 | ||
656 | /* Get System Network Statistics */ | |
bc1f4470 | 657 | static void |
2dc0d2b4 BX |
658 | mvneta_get_stats64(struct net_device *dev, |
659 | struct rtnl_link_stats64 *stats) | |
c5aff182 TP |
660 | { |
661 | struct mvneta_port *pp = netdev_priv(dev); | |
662 | unsigned int start; | |
74c41b04 | 663 | int cpu; |
c5aff182 | 664 | |
74c41b04 | 665 | for_each_possible_cpu(cpu) { |
666 | struct mvneta_pcpu_stats *cpu_stats; | |
667 | u64 rx_packets; | |
668 | u64 rx_bytes; | |
669 | u64 tx_packets; | |
670 | u64 tx_bytes; | |
c5aff182 | 671 | |
74c41b04 | 672 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
673 | do { | |
57a7744e | 674 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); |
74c41b04 | 675 | rx_packets = cpu_stats->rx_packets; |
676 | rx_bytes = cpu_stats->rx_bytes; | |
677 | tx_packets = cpu_stats->tx_packets; | |
678 | tx_bytes = cpu_stats->tx_bytes; | |
57a7744e | 679 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); |
c5aff182 | 680 | |
74c41b04 | 681 | stats->rx_packets += rx_packets; |
682 | stats->rx_bytes += rx_bytes; | |
683 | stats->tx_packets += tx_packets; | |
684 | stats->tx_bytes += tx_bytes; | |
685 | } | |
c5aff182 TP |
686 | |
687 | stats->rx_errors = dev->stats.rx_errors; | |
688 | stats->rx_dropped = dev->stats.rx_dropped; | |
689 | ||
690 | stats->tx_dropped = dev->stats.tx_dropped; | |
c5aff182 TP |
691 | } |
692 | ||
693 | /* Rx descriptors helper methods */ | |
694 | ||
5428213c | 695 | /* Checks whether the RX descriptor having this status is both the first |
696 | * and the last descriptor for the RX packet. Each RX packet is currently | |
c5aff182 TP |
697 | * received through a single RX descriptor, so not having each RX |
698 | * descriptor with its first and last bits set is an error | |
699 | */ | |
5428213c | 700 | static int mvneta_rxq_desc_is_first_last(u32 status) |
c5aff182 | 701 | { |
5428213c | 702 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == |
c5aff182 TP |
703 | MVNETA_RXD_FIRST_LAST_DESC; |
704 | } | |
705 | ||
706 | /* Add number of descriptors ready to receive new packets */ | |
707 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
708 | struct mvneta_rx_queue *rxq, | |
709 | int ndescs) | |
710 | { | |
711 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
6a20c175 TP |
712 | * be added at once |
713 | */ | |
c5aff182 TP |
714 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
715 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
716 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
717 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
718 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
719 | } | |
720 | ||
721 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
722 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
723 | } | |
724 | ||
725 | /* Get number of RX descriptors occupied by received packets */ | |
726 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
727 | struct mvneta_rx_queue *rxq) | |
728 | { | |
729 | u32 val; | |
730 | ||
731 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
732 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
733 | } | |
734 | ||
6a20c175 | 735 | /* Update num of rx desc called upon return from rx path or |
c5aff182 TP |
736 | * from mvneta_rxq_drop_pkts(). |
737 | */ | |
738 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
739 | struct mvneta_rx_queue *rxq, | |
740 | int rx_done, int rx_filled) | |
741 | { | |
742 | u32 val; | |
743 | ||
744 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
745 | val = rx_done | | |
746 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
747 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
748 | return; | |
749 | } | |
750 | ||
751 | /* Only 255 descriptors can be added at once */ | |
752 | while ((rx_done > 0) || (rx_filled > 0)) { | |
753 | if (rx_done <= 0xff) { | |
754 | val = rx_done; | |
755 | rx_done = 0; | |
756 | } else { | |
757 | val = 0xff; | |
758 | rx_done -= 0xff; | |
759 | } | |
760 | if (rx_filled <= 0xff) { | |
761 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
762 | rx_filled = 0; | |
763 | } else { | |
764 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
765 | rx_filled -= 0xff; | |
766 | } | |
767 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
768 | } | |
769 | } | |
770 | ||
771 | /* Get pointer to next RX descriptor to be processed by SW */ | |
772 | static struct mvneta_rx_desc * | |
773 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
774 | { | |
775 | int rx_desc = rxq->next_desc_to_proc; | |
776 | ||
777 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
34e4179d | 778 | prefetch(rxq->descs + rxq->next_desc_to_proc); |
c5aff182 TP |
779 | return rxq->descs + rx_desc; |
780 | } | |
781 | ||
782 | /* Change maximum receive size of the port. */ | |
783 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) | |
784 | { | |
785 | u32 val; | |
786 | ||
787 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
788 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; | |
789 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << | |
790 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; | |
791 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
792 | } | |
793 | ||
794 | ||
795 | /* Set rx queue offset */ | |
796 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, | |
797 | struct mvneta_rx_queue *rxq, | |
798 | int offset) | |
799 | { | |
800 | u32 val; | |
801 | ||
802 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
803 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; | |
804 | ||
805 | /* Offset is in */ | |
806 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); | |
807 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
808 | } | |
809 | ||
810 | ||
811 | /* Tx descriptors helper methods */ | |
812 | ||
813 | /* Update HW with number of TX descriptors to be sent */ | |
814 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
815 | struct mvneta_tx_queue *txq, | |
816 | int pend_desc) | |
817 | { | |
818 | u32 val; | |
819 | ||
820 | /* Only 255 descriptors can be added at once ; Assume caller | |
6a20c175 TP |
821 | * process TX desriptors in quanta less than 256 |
822 | */ | |
2a90f7e1 | 823 | val = pend_desc + txq->pending; |
c5aff182 | 824 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); |
2a90f7e1 | 825 | txq->pending = 0; |
c5aff182 TP |
826 | } |
827 | ||
828 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
829 | static struct mvneta_tx_desc * | |
830 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
831 | { | |
832 | int tx_desc = txq->next_desc_to_proc; | |
833 | ||
834 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
835 | return txq->descs + tx_desc; | |
836 | } | |
837 | ||
838 | /* Release the last allocated TX descriptor. Useful to handle DMA | |
6a20c175 TP |
839 | * mapping failures in the TX path. |
840 | */ | |
c5aff182 TP |
841 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
842 | { | |
843 | if (txq->next_desc_to_proc == 0) | |
844 | txq->next_desc_to_proc = txq->last_desc - 1; | |
845 | else | |
846 | txq->next_desc_to_proc--; | |
847 | } | |
848 | ||
849 | /* Set rxq buf size */ | |
850 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
851 | struct mvneta_rx_queue *rxq, | |
852 | int buf_size) | |
853 | { | |
854 | u32 val; | |
855 | ||
856 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
857 | ||
858 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
859 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
860 | ||
861 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
862 | } | |
863 | ||
864 | /* Disable buffer management (BM) */ | |
865 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, | |
866 | struct mvneta_rx_queue *rxq) | |
867 | { | |
868 | u32 val; | |
869 | ||
870 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
871 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; | |
872 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
873 | } | |
874 | ||
dc35a10f MW |
875 | /* Enable buffer management (BM) */ |
876 | static void mvneta_rxq_bm_enable(struct mvneta_port *pp, | |
877 | struct mvneta_rx_queue *rxq) | |
878 | { | |
879 | u32 val; | |
880 | ||
881 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
882 | val |= MVNETA_RXQ_HW_BUF_ALLOC; | |
883 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
884 | } | |
885 | ||
886 | /* Notify HW about port's assignment of pool for bigger packets */ | |
887 | static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, | |
888 | struct mvneta_rx_queue *rxq) | |
889 | { | |
890 | u32 val; | |
891 | ||
892 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
893 | val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; | |
894 | val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); | |
895 | ||
896 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
897 | } | |
898 | ||
899 | /* Notify HW about port's assignment of pool for smaller packets */ | |
900 | static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, | |
901 | struct mvneta_rx_queue *rxq) | |
902 | { | |
903 | u32 val; | |
904 | ||
905 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
906 | val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; | |
907 | val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); | |
908 | ||
909 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
910 | } | |
911 | ||
912 | /* Set port's receive buffer size for assigned BM pool */ | |
913 | static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, | |
914 | int buf_size, | |
915 | u8 pool_id) | |
916 | { | |
917 | u32 val; | |
918 | ||
919 | if (!IS_ALIGNED(buf_size, 8)) { | |
920 | dev_warn(pp->dev->dev.parent, | |
921 | "illegal buf_size value %d, round to %d\n", | |
922 | buf_size, ALIGN(buf_size, 8)); | |
923 | buf_size = ALIGN(buf_size, 8); | |
924 | } | |
925 | ||
926 | val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); | |
927 | val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; | |
928 | mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); | |
929 | } | |
930 | ||
931 | /* Configure MBUS window in order to enable access BM internal SRAM */ | |
932 | static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, | |
933 | u8 target, u8 attr) | |
934 | { | |
935 | u32 win_enable, win_protect; | |
936 | int i; | |
937 | ||
938 | win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); | |
939 | ||
940 | if (pp->bm_win_id < 0) { | |
941 | /* Find first not occupied window */ | |
942 | for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { | |
943 | if (win_enable & (1 << i)) { | |
944 | pp->bm_win_id = i; | |
945 | break; | |
946 | } | |
947 | } | |
948 | if (i == MVNETA_MAX_DECODE_WIN) | |
949 | return -ENOMEM; | |
950 | } else { | |
951 | i = pp->bm_win_id; | |
952 | } | |
953 | ||
954 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
955 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
956 | ||
957 | if (i < 4) | |
958 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
959 | ||
960 | mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | | |
961 | (attr << 8) | target); | |
962 | ||
963 | mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); | |
964 | ||
965 | win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); | |
966 | win_protect |= 3 << (2 * i); | |
967 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); | |
968 | ||
969 | win_enable &= ~(1 << i); | |
970 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
971 | ||
972 | return 0; | |
973 | } | |
974 | ||
2636ac3c | 975 | static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) |
dc35a10f | 976 | { |
2636ac3c | 977 | u32 wsize; |
dc35a10f MW |
978 | u8 target, attr; |
979 | int err; | |
980 | ||
981 | /* Get BM window information */ | |
982 | err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, | |
983 | &target, &attr); | |
984 | if (err < 0) | |
985 | return err; | |
986 | ||
987 | pp->bm_win_id = -1; | |
988 | ||
989 | /* Open NETA -> BM window */ | |
990 | err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, | |
991 | target, attr); | |
992 | if (err < 0) { | |
993 | netdev_info(pp->dev, "fail to configure mbus window to BM\n"); | |
994 | return err; | |
995 | } | |
2636ac3c MW |
996 | return 0; |
997 | } | |
998 | ||
999 | /* Assign and initialize pools for port. In case of fail | |
1000 | * buffer manager will remain disabled for current port. | |
1001 | */ | |
1002 | static int mvneta_bm_port_init(struct platform_device *pdev, | |
1003 | struct mvneta_port *pp) | |
1004 | { | |
1005 | struct device_node *dn = pdev->dev.of_node; | |
1006 | u32 long_pool_id, short_pool_id; | |
1007 | ||
1008 | if (!pp->neta_armada3700) { | |
1009 | int ret; | |
1010 | ||
1011 | ret = mvneta_bm_port_mbus_init(pp); | |
1012 | if (ret) | |
1013 | return ret; | |
1014 | } | |
dc35a10f MW |
1015 | |
1016 | if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { | |
1017 | netdev_info(pp->dev, "missing long pool id\n"); | |
1018 | return -EINVAL; | |
1019 | } | |
1020 | ||
1021 | /* Create port's long pool depending on mtu */ | |
1022 | pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, | |
1023 | MVNETA_BM_LONG, pp->id, | |
1024 | MVNETA_RX_PKT_SIZE(pp->dev->mtu)); | |
1025 | if (!pp->pool_long) { | |
1026 | netdev_info(pp->dev, "fail to obtain long pool for port\n"); | |
1027 | return -ENOMEM; | |
1028 | } | |
1029 | ||
1030 | pp->pool_long->port_map |= 1 << pp->id; | |
1031 | ||
1032 | mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, | |
1033 | pp->pool_long->id); | |
1034 | ||
1035 | /* If short pool id is not defined, assume using single pool */ | |
1036 | if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) | |
1037 | short_pool_id = long_pool_id; | |
1038 | ||
1039 | /* Create port's short pool */ | |
1040 | pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, | |
1041 | MVNETA_BM_SHORT, pp->id, | |
1042 | MVNETA_BM_SHORT_PKT_SIZE); | |
1043 | if (!pp->pool_short) { | |
1044 | netdev_info(pp->dev, "fail to obtain short pool for port\n"); | |
1045 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1046 | return -ENOMEM; | |
1047 | } | |
1048 | ||
1049 | if (short_pool_id != long_pool_id) { | |
1050 | pp->pool_short->port_map |= 1 << pp->id; | |
1051 | mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, | |
1052 | pp->pool_short->id); | |
1053 | } | |
1054 | ||
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | /* Update settings of a pool for bigger packets */ | |
1059 | static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) | |
1060 | { | |
1061 | struct mvneta_bm_pool *bm_pool = pp->pool_long; | |
baa11ebc | 1062 | struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; |
dc35a10f MW |
1063 | int num; |
1064 | ||
1065 | /* Release all buffers from long pool */ | |
1066 | mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); | |
baa11ebc | 1067 | if (hwbm_pool->buf_num) { |
dc35a10f MW |
1068 | WARN(1, "cannot free all buffers in pool %d\n", |
1069 | bm_pool->id); | |
1070 | goto bm_mtu_err; | |
1071 | } | |
1072 | ||
1073 | bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); | |
1074 | bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); | |
baa11ebc GC |
1075 | hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + |
1076 | SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); | |
dc35a10f MW |
1077 | |
1078 | /* Fill entire long pool */ | |
baa11ebc GC |
1079 | num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC); |
1080 | if (num != hwbm_pool->size) { | |
dc35a10f | 1081 | WARN(1, "pool %d: %d of %d allocated\n", |
baa11ebc | 1082 | bm_pool->id, num, hwbm_pool->size); |
dc35a10f MW |
1083 | goto bm_mtu_err; |
1084 | } | |
1085 | mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); | |
1086 | ||
1087 | return; | |
1088 | ||
1089 | bm_mtu_err: | |
1090 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1091 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); | |
1092 | ||
1093 | pp->bm_priv = NULL; | |
1094 | mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); | |
1095 | netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); | |
1096 | } | |
1097 | ||
c5aff182 TP |
1098 | /* Start the Ethernet port RX and TX activity */ |
1099 | static void mvneta_port_up(struct mvneta_port *pp) | |
1100 | { | |
1101 | int queue; | |
1102 | u32 q_map; | |
1103 | ||
1104 | /* Enable all initialized TXs. */ | |
c5aff182 TP |
1105 | q_map = 0; |
1106 | for (queue = 0; queue < txq_number; queue++) { | |
1107 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
1108 | if (txq->descs != NULL) | |
1109 | q_map |= (1 << queue); | |
1110 | } | |
1111 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
1112 | ||
1113 | /* Enable all initialized RXQs. */ | |
2dcf75e2 GC |
1114 | for (queue = 0; queue < rxq_number; queue++) { |
1115 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
1116 | ||
1117 | if (rxq->descs != NULL) | |
1118 | q_map |= (1 << queue); | |
1119 | } | |
1120 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
c5aff182 TP |
1121 | } |
1122 | ||
1123 | /* Stop the Ethernet port activity */ | |
1124 | static void mvneta_port_down(struct mvneta_port *pp) | |
1125 | { | |
1126 | u32 val; | |
1127 | int count; | |
1128 | ||
1129 | /* Stop Rx port activity. Check port Rx activity. */ | |
1130 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
1131 | ||
1132 | /* Issue stop command for active channels only */ | |
1133 | if (val != 0) | |
1134 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
1135 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
1136 | ||
1137 | /* Wait for all Rx activity to terminate. */ | |
1138 | count = 0; | |
1139 | do { | |
1140 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
1141 | netdev_warn(pp->dev, | |
0838abb3 | 1142 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", |
c5aff182 TP |
1143 | val); |
1144 | break; | |
1145 | } | |
1146 | mdelay(1); | |
1147 | ||
1148 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
a3703fb3 | 1149 | } while (val & MVNETA_RXQ_ENABLE_MASK); |
c5aff182 TP |
1150 | |
1151 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
6a20c175 TP |
1152 | * command for active channels only |
1153 | */ | |
c5aff182 TP |
1154 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
1155 | ||
1156 | if (val != 0) | |
1157 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
1158 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
1159 | ||
1160 | /* Wait for all Tx activity to terminate. */ | |
1161 | count = 0; | |
1162 | do { | |
1163 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
1164 | netdev_warn(pp->dev, | |
1165 | "TIMEOUT for TX stopped status=0x%08x\n", | |
1166 | val); | |
1167 | break; | |
1168 | } | |
1169 | mdelay(1); | |
1170 | ||
1171 | /* Check TX Command reg that all Txqs are stopped */ | |
1172 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
1173 | ||
a3703fb3 | 1174 | } while (val & MVNETA_TXQ_ENABLE_MASK); |
c5aff182 TP |
1175 | |
1176 | /* Double check to verify that TX FIFO is empty */ | |
1177 | count = 0; | |
1178 | do { | |
1179 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
1180 | netdev_warn(pp->dev, | |
0838abb3 | 1181 | "TX FIFO empty timeout status=0x%08x\n", |
c5aff182 TP |
1182 | val); |
1183 | break; | |
1184 | } | |
1185 | mdelay(1); | |
1186 | ||
1187 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
1188 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
1189 | (val & MVNETA_TX_IN_PRGRS)); | |
1190 | ||
1191 | udelay(200); | |
1192 | } | |
1193 | ||
1194 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
1195 | static void mvneta_port_enable(struct mvneta_port *pp) | |
1196 | { | |
1197 | u32 val; | |
1198 | ||
1199 | /* Enable port */ | |
1200 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1201 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
1202 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1203 | } | |
1204 | ||
1205 | /* Disable the port and wait for about 200 usec before retuning */ | |
1206 | static void mvneta_port_disable(struct mvneta_port *pp) | |
1207 | { | |
1208 | u32 val; | |
1209 | ||
1210 | /* Reset the Enable bit in the Serial Control Register */ | |
1211 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1212 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
1213 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1214 | ||
1215 | udelay(200); | |
1216 | } | |
1217 | ||
1218 | /* Multicast tables methods */ | |
1219 | ||
1220 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
1221 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
1222 | { | |
1223 | int offset; | |
1224 | u32 val; | |
1225 | ||
1226 | if (queue == -1) { | |
1227 | val = 0; | |
1228 | } else { | |
1229 | val = 0x1 | (queue << 1); | |
1230 | val |= (val << 24) | (val << 16) | (val << 8); | |
1231 | } | |
1232 | ||
1233 | for (offset = 0; offset <= 0xc; offset += 4) | |
1234 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
1235 | } | |
1236 | ||
1237 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
1238 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
1239 | { | |
1240 | int offset; | |
1241 | u32 val; | |
1242 | ||
1243 | if (queue == -1) { | |
1244 | val = 0; | |
1245 | } else { | |
1246 | val = 0x1 | (queue << 1); | |
1247 | val |= (val << 24) | (val << 16) | (val << 8); | |
1248 | } | |
1249 | ||
1250 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1251 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
1252 | ||
1253 | } | |
1254 | ||
1255 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
1256 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
1257 | { | |
1258 | int offset; | |
1259 | u32 val; | |
1260 | ||
1261 | if (queue == -1) { | |
1262 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
1263 | val = 0; | |
1264 | } else { | |
1265 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
1266 | val = 0x1 | (queue << 1); | |
1267 | val |= (val << 24) | (val << 16) | (val << 8); | |
1268 | } | |
1269 | ||
1270 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1271 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
1272 | } | |
1273 | ||
0c0744fc SS |
1274 | static void mvneta_set_autoneg(struct mvneta_port *pp, int enable) |
1275 | { | |
1276 | u32 val; | |
1277 | ||
1278 | if (enable) { | |
1279 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1280 | val &= ~(MVNETA_GMAC_FORCE_LINK_PASS | | |
1281 | MVNETA_GMAC_FORCE_LINK_DOWN | | |
1282 | MVNETA_GMAC_AN_FLOW_CTRL_EN); | |
1283 | val |= MVNETA_GMAC_INBAND_AN_ENABLE | | |
1284 | MVNETA_GMAC_AN_SPEED_EN | | |
1285 | MVNETA_GMAC_AN_DUPLEX_EN; | |
1286 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1287 | ||
1288 | val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); | |
1289 | val |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
1290 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); | |
1291 | ||
1292 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
1293 | val |= MVNETA_GMAC2_INBAND_AN_ENABLE; | |
1294 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
1295 | } else { | |
1296 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1297 | val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE | | |
1298 | MVNETA_GMAC_AN_SPEED_EN | | |
1299 | MVNETA_GMAC_AN_DUPLEX_EN); | |
1300 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1301 | ||
1302 | val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); | |
1303 | val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
1304 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); | |
1305 | ||
1306 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
1307 | val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE; | |
1308 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
1309 | } | |
1310 | } | |
1311 | ||
db488c10 GC |
1312 | static void mvneta_percpu_unmask_interrupt(void *arg) |
1313 | { | |
1314 | struct mvneta_port *pp = arg; | |
1315 | ||
1316 | /* All the queue are unmasked, but actually only the ones | |
1317 | * mapped to this CPU will be unmasked | |
1318 | */ | |
1319 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
1320 | MVNETA_RX_INTR_MASK_ALL | | |
1321 | MVNETA_TX_INTR_MASK_ALL | | |
1322 | MVNETA_MISCINTR_INTR_MASK); | |
1323 | } | |
1324 | ||
1325 | static void mvneta_percpu_mask_interrupt(void *arg) | |
1326 | { | |
1327 | struct mvneta_port *pp = arg; | |
1328 | ||
1329 | /* All the queue are masked, but actually only the ones | |
1330 | * mapped to this CPU will be masked | |
1331 | */ | |
1332 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
1333 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
1334 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
1335 | } | |
1336 | ||
1337 | static void mvneta_percpu_clear_intr_cause(void *arg) | |
1338 | { | |
1339 | struct mvneta_port *pp = arg; | |
1340 | ||
1341 | /* All the queue are cleared, but actually only the ones | |
1342 | * mapped to this CPU will be cleared | |
1343 | */ | |
1344 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
1345 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
1346 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
1347 | } | |
1348 | ||
c5aff182 TP |
1349 | /* This method sets defaults to the NETA port: |
1350 | * Clears interrupt Cause and Mask registers. | |
1351 | * Clears all MAC tables. | |
1352 | * Sets defaults to all registers. | |
1353 | * Resets RX and TX descriptor rings. | |
1354 | * Resets PHY. | |
1355 | * This method can be called after mvneta_port_down() to return the port | |
1356 | * settings to defaults. | |
1357 | */ | |
1358 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
1359 | { | |
1360 | int cpu; | |
1361 | int queue; | |
1362 | u32 val; | |
2dcf75e2 | 1363 | int max_cpu = num_present_cpus(); |
c5aff182 TP |
1364 | |
1365 | /* Clear all Cause registers */ | |
db488c10 | 1366 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
1367 | |
1368 | /* Mask all interrupts */ | |
db488c10 | 1369 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
1370 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); |
1371 | ||
1372 | /* Enable MBUS Retry bit16 */ | |
1373 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
1374 | ||
50bf8cb6 GC |
1375 | /* Set CPU queue access map. CPUs are assigned to the RX and |
1376 | * TX queues modulo their number. If there is only one TX | |
1377 | * queue then it is assigned to the CPU associated to the | |
1378 | * default RX queue. | |
6a20c175 | 1379 | */ |
2dcf75e2 GC |
1380 | for_each_present_cpu(cpu) { |
1381 | int rxq_map = 0, txq_map = 0; | |
50bf8cb6 | 1382 | int rxq, txq; |
2636ac3c MW |
1383 | if (!pp->neta_armada3700) { |
1384 | for (rxq = 0; rxq < rxq_number; rxq++) | |
1385 | if ((rxq % max_cpu) == cpu) | |
1386 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
1387 | ||
1388 | for (txq = 0; txq < txq_number; txq++) | |
1389 | if ((txq % max_cpu) == cpu) | |
1390 | txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); | |
1391 | ||
1392 | /* With only one TX queue we configure a special case | |
1393 | * which will allow to get all the irq on a single | |
1394 | * CPU | |
1395 | */ | |
1396 | if (txq_number == 1) | |
1397 | txq_map = (cpu == pp->rxq_def) ? | |
1398 | MVNETA_CPU_TXQ_ACCESS(1) : 0; | |
2dcf75e2 | 1399 | |
2636ac3c MW |
1400 | } else { |
1401 | txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
1402 | rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; | |
1403 | } | |
2dcf75e2 GC |
1404 | |
1405 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); | |
1406 | } | |
c5aff182 TP |
1407 | |
1408 | /* Reset RX and TX DMAs */ | |
1409 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
1410 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
1411 | ||
1412 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
1413 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
1414 | for (queue = 0; queue < txq_number; queue++) { | |
1415 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
1416 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
1417 | } | |
1418 | ||
1419 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
1420 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
1421 | ||
1422 | /* Set Port Acceleration Mode */ | |
dc35a10f MW |
1423 | if (pp->bm_priv) |
1424 | /* HW buffer management + legacy parser */ | |
1425 | val = MVNETA_ACC_MODE_EXT2; | |
1426 | else | |
1427 | /* SW buffer management + legacy parser */ | |
1428 | val = MVNETA_ACC_MODE_EXT1; | |
c5aff182 TP |
1429 | mvreg_write(pp, MVNETA_ACC_MODE, val); |
1430 | ||
dc35a10f MW |
1431 | if (pp->bm_priv) |
1432 | mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); | |
1433 | ||
c5aff182 | 1434 | /* Update val of portCfg register accordingly with all RxQueue types */ |
90b74c01 | 1435 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); |
c5aff182 TP |
1436 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); |
1437 | ||
1438 | val = 0; | |
1439 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
1440 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
1441 | ||
1442 | /* Build PORT_SDMA_CONFIG_REG */ | |
1443 | val = 0; | |
1444 | ||
1445 | /* Default burst size */ | |
1446 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
1447 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
9ad8fef6 | 1448 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; |
c5aff182 | 1449 | |
9ad8fef6 TP |
1450 | #if defined(__BIG_ENDIAN) |
1451 | val |= MVNETA_DESC_SWAP; | |
1452 | #endif | |
c5aff182 TP |
1453 | |
1454 | /* Assign port SDMA configuration */ | |
1455 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
1456 | ||
71408602 TP |
1457 | /* Disable PHY polling in hardware, since we're using the |
1458 | * kernel phylib to do this. | |
1459 | */ | |
1460 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
1461 | val &= ~MVNETA_PHY_POLLING_ENABLE; | |
1462 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
1463 | ||
0c0744fc | 1464 | mvneta_set_autoneg(pp, pp->use_inband_status); |
c5aff182 TP |
1465 | mvneta_set_ucast_table(pp, -1); |
1466 | mvneta_set_special_mcast_table(pp, -1); | |
1467 | mvneta_set_other_mcast_table(pp, -1); | |
1468 | ||
1469 | /* Set port interrupt enable register - default enable all */ | |
1470 | mvreg_write(pp, MVNETA_INTR_ENABLE, | |
1471 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK | |
1472 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); | |
e483911f AL |
1473 | |
1474 | mvneta_mib_counters_clear(pp); | |
c5aff182 TP |
1475 | } |
1476 | ||
1477 | /* Set max sizes for tx queues */ | |
1478 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) | |
1479 | ||
1480 | { | |
1481 | u32 val, size, mtu; | |
1482 | int queue; | |
1483 | ||
1484 | mtu = max_tx_size * 8; | |
1485 | if (mtu > MVNETA_TX_MTU_MAX) | |
1486 | mtu = MVNETA_TX_MTU_MAX; | |
1487 | ||
1488 | /* Set MTU */ | |
1489 | val = mvreg_read(pp, MVNETA_TX_MTU); | |
1490 | val &= ~MVNETA_TX_MTU_MAX; | |
1491 | val |= mtu; | |
1492 | mvreg_write(pp, MVNETA_TX_MTU, val); | |
1493 | ||
1494 | /* TX token size and all TXQs token size must be larger that MTU */ | |
1495 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); | |
1496 | ||
1497 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; | |
1498 | if (size < mtu) { | |
1499 | size = mtu; | |
1500 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; | |
1501 | val |= size; | |
1502 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); | |
1503 | } | |
1504 | for (queue = 0; queue < txq_number; queue++) { | |
1505 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); | |
1506 | ||
1507 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1508 | if (size < mtu) { | |
1509 | size = mtu; | |
1510 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1511 | val |= size; | |
1512 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); | |
1513 | } | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | /* Set unicast address */ | |
1518 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
1519 | int queue) | |
1520 | { | |
1521 | unsigned int unicast_reg; | |
1522 | unsigned int tbl_offset; | |
1523 | unsigned int reg_offset; | |
1524 | ||
1525 | /* Locate the Unicast table entry */ | |
1526 | last_nibble = (0xf & last_nibble); | |
1527 | ||
1528 | /* offset from unicast tbl base */ | |
1529 | tbl_offset = (last_nibble / 4) * 4; | |
1530 | ||
1531 | /* offset within the above reg */ | |
1532 | reg_offset = last_nibble % 4; | |
1533 | ||
1534 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
1535 | ||
1536 | if (queue == -1) { | |
1537 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
1538 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1539 | } else { | |
1540 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1541 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1542 | } | |
1543 | ||
1544 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
1545 | } | |
1546 | ||
1547 | /* Set mac address */ | |
1548 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
1549 | int queue) | |
1550 | { | |
1551 | unsigned int mac_h; | |
1552 | unsigned int mac_l; | |
1553 | ||
1554 | if (queue != -1) { | |
1555 | mac_l = (addr[4] << 8) | (addr[5]); | |
1556 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
1557 | (addr[2] << 8) | (addr[3] << 0); | |
1558 | ||
1559 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
1560 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
1561 | } | |
1562 | ||
1563 | /* Accept frames of this address */ | |
1564 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
1565 | } | |
1566 | ||
6a20c175 TP |
1567 | /* Set the number of packets that will be received before RX interrupt |
1568 | * will be generated by HW. | |
c5aff182 TP |
1569 | */ |
1570 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, | |
1571 | struct mvneta_rx_queue *rxq, u32 value) | |
1572 | { | |
1573 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), | |
1574 | value | MVNETA_RXQ_NON_OCCUPIED(0)); | |
1575 | rxq->pkts_coal = value; | |
1576 | } | |
1577 | ||
6a20c175 TP |
1578 | /* Set the time delay in usec before RX interrupt will be generated by |
1579 | * HW. | |
c5aff182 TP |
1580 | */ |
1581 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, | |
1582 | struct mvneta_rx_queue *rxq, u32 value) | |
1583 | { | |
189dd626 TP |
1584 | u32 val; |
1585 | unsigned long clk_rate; | |
1586 | ||
1587 | clk_rate = clk_get_rate(pp->clk); | |
1588 | val = (clk_rate / 1000000) * value; | |
c5aff182 TP |
1589 | |
1590 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); | |
1591 | rxq->time_coal = value; | |
1592 | } | |
1593 | ||
1594 | /* Set threshold for TX_DONE pkts coalescing */ | |
1595 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, | |
1596 | struct mvneta_tx_queue *txq, u32 value) | |
1597 | { | |
1598 | u32 val; | |
1599 | ||
1600 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); | |
1601 | ||
1602 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; | |
1603 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); | |
1604 | ||
1605 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); | |
1606 | ||
1607 | txq->done_pkts_coal = value; | |
1608 | } | |
1609 | ||
c5aff182 TP |
1610 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
1611 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
f88bee1c GC |
1612 | u32 phys_addr, void *virt_addr, |
1613 | struct mvneta_rx_queue *rxq) | |
c5aff182 | 1614 | { |
f88bee1c GC |
1615 | int i; |
1616 | ||
c5aff182 | 1617 | rx_desc->buf_phys_addr = phys_addr; |
f88bee1c GC |
1618 | i = rx_desc - rxq->descs; |
1619 | rxq->buf_virt_addr[i] = virt_addr; | |
c5aff182 TP |
1620 | } |
1621 | ||
1622 | /* Decrement sent descriptors counter */ | |
1623 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
1624 | struct mvneta_tx_queue *txq, | |
1625 | int sent_desc) | |
1626 | { | |
1627 | u32 val; | |
1628 | ||
1629 | /* Only 255 TX descriptors can be updated at once */ | |
1630 | while (sent_desc > 0xff) { | |
1631 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1632 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1633 | sent_desc = sent_desc - 0xff; | |
1634 | } | |
1635 | ||
1636 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1637 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1638 | } | |
1639 | ||
1640 | /* Get number of TX descriptors already sent by HW */ | |
1641 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
1642 | struct mvneta_tx_queue *txq) | |
1643 | { | |
1644 | u32 val; | |
1645 | int sent_desc; | |
1646 | ||
1647 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
1648 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
1649 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
1650 | ||
1651 | return sent_desc; | |
1652 | } | |
1653 | ||
6a20c175 | 1654 | /* Get number of sent descriptors and decrement counter. |
c5aff182 TP |
1655 | * The number of sent descriptors is returned. |
1656 | */ | |
1657 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, | |
1658 | struct mvneta_tx_queue *txq) | |
1659 | { | |
1660 | int sent_desc; | |
1661 | ||
1662 | /* Get number of sent descriptors */ | |
1663 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1664 | ||
1665 | /* Decrement sent descriptors counter */ | |
1666 | if (sent_desc) | |
1667 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
1668 | ||
1669 | return sent_desc; | |
1670 | } | |
1671 | ||
1672 | /* Set TXQ descriptors fields relevant for CSUM calculation */ | |
1673 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, | |
1674 | int ip_hdr_len, int l4_proto) | |
1675 | { | |
1676 | u32 command; | |
1677 | ||
1678 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
6a20c175 TP |
1679 | * G_L4_chk, L4_type; required only for checksum |
1680 | * calculation | |
1681 | */ | |
c5aff182 TP |
1682 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
1683 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; | |
1684 | ||
0a198587 | 1685 | if (l3_proto == htons(ETH_P_IP)) |
c5aff182 TP |
1686 | command |= MVNETA_TXD_IP_CSUM; |
1687 | else | |
1688 | command |= MVNETA_TX_L3_IP6; | |
1689 | ||
1690 | if (l4_proto == IPPROTO_TCP) | |
1691 | command |= MVNETA_TX_L4_CSUM_FULL; | |
1692 | else if (l4_proto == IPPROTO_UDP) | |
1693 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; | |
1694 | else | |
1695 | command |= MVNETA_TX_L4_CSUM_NOT; | |
1696 | ||
1697 | return command; | |
1698 | } | |
1699 | ||
1700 | ||
1701 | /* Display more error info */ | |
1702 | static void mvneta_rx_error(struct mvneta_port *pp, | |
1703 | struct mvneta_rx_desc *rx_desc) | |
1704 | { | |
1705 | u32 status = rx_desc->status; | |
1706 | ||
5428213c | 1707 | if (!mvneta_rxq_desc_is_first_last(status)) { |
c5aff182 TP |
1708 | netdev_err(pp->dev, |
1709 | "bad rx status %08x (buffer oversize), size=%d\n", | |
5428213c | 1710 | status, rx_desc->data_size); |
c5aff182 TP |
1711 | return; |
1712 | } | |
1713 | ||
1714 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { | |
1715 | case MVNETA_RXD_ERR_CRC: | |
1716 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
1717 | status, rx_desc->data_size); | |
1718 | break; | |
1719 | case MVNETA_RXD_ERR_OVERRUN: | |
1720 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
1721 | status, rx_desc->data_size); | |
1722 | break; | |
1723 | case MVNETA_RXD_ERR_LEN: | |
1724 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
1725 | status, rx_desc->data_size); | |
1726 | break; | |
1727 | case MVNETA_RXD_ERR_RESOURCE: | |
1728 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
1729 | status, rx_desc->data_size); | |
1730 | break; | |
1731 | } | |
1732 | } | |
1733 | ||
5428213c | 1734 | /* Handle RX checksum offload based on the descriptor's status */ |
1735 | static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, | |
c5aff182 TP |
1736 | struct sk_buff *skb) |
1737 | { | |
5428213c | 1738 | if ((status & MVNETA_RXD_L3_IP4) && |
1739 | (status & MVNETA_RXD_L4_CSUM_OK)) { | |
c5aff182 TP |
1740 | skb->csum = 0; |
1741 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1742 | return; | |
1743 | } | |
1744 | ||
1745 | skb->ip_summed = CHECKSUM_NONE; | |
1746 | } | |
1747 | ||
6c498974 | 1748 | /* Return tx queue pointer (find last set bit) according to <cause> returned |
1749 | * form tx_done reg. <cause> must not be null. The return value is always a | |
1750 | * valid queue for matching the first one found in <cause>. | |
1751 | */ | |
c5aff182 TP |
1752 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
1753 | u32 cause) | |
1754 | { | |
1755 | int queue = fls(cause) - 1; | |
1756 | ||
6c498974 | 1757 | return &pp->txqs[queue]; |
c5aff182 TP |
1758 | } |
1759 | ||
1760 | /* Free tx queue skbuffs */ | |
1761 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, | |
a29b6235 MW |
1762 | struct mvneta_tx_queue *txq, int num, |
1763 | struct netdev_queue *nq) | |
c5aff182 | 1764 | { |
a29b6235 | 1765 | unsigned int bytes_compl = 0, pkts_compl = 0; |
c5aff182 TP |
1766 | int i; |
1767 | ||
1768 | for (i = 0; i < num; i++) { | |
1769 | struct mvneta_tx_desc *tx_desc = txq->descs + | |
1770 | txq->txq_get_index; | |
1771 | struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; | |
1772 | ||
a29b6235 MW |
1773 | if (skb) { |
1774 | bytes_compl += skb->len; | |
1775 | pkts_compl++; | |
1776 | } | |
1777 | ||
c5aff182 TP |
1778 | mvneta_txq_inc_get(txq); |
1779 | ||
2e3173a3 EG |
1780 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
1781 | dma_unmap_single(pp->dev->dev.parent, | |
1782 | tx_desc->buf_phys_addr, | |
1783 | tx_desc->data_size, DMA_TO_DEVICE); | |
ba7e46ef EG |
1784 | if (!skb) |
1785 | continue; | |
c5aff182 TP |
1786 | dev_kfree_skb_any(skb); |
1787 | } | |
a29b6235 MW |
1788 | |
1789 | netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); | |
c5aff182 TP |
1790 | } |
1791 | ||
1792 | /* Handle end of transmission */ | |
cd713199 | 1793 | static void mvneta_txq_done(struct mvneta_port *pp, |
c5aff182 TP |
1794 | struct mvneta_tx_queue *txq) |
1795 | { | |
1796 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1797 | int tx_done; | |
1798 | ||
1799 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); | |
cd713199 AE |
1800 | if (!tx_done) |
1801 | return; | |
1802 | ||
a29b6235 | 1803 | mvneta_txq_bufs_free(pp, txq, tx_done, nq); |
c5aff182 TP |
1804 | |
1805 | txq->count -= tx_done; | |
1806 | ||
1807 | if (netif_tx_queue_stopped(nq)) { | |
8eef5f97 | 1808 | if (txq->count <= txq->tx_wake_threshold) |
c5aff182 TP |
1809 | netif_tx_wake_queue(nq); |
1810 | } | |
c5aff182 TP |
1811 | } |
1812 | ||
dc35a10f | 1813 | void *mvneta_frag_alloc(unsigned int frag_size) |
8ec2cd48 | 1814 | { |
dc35a10f MW |
1815 | if (likely(frag_size <= PAGE_SIZE)) |
1816 | return netdev_alloc_frag(frag_size); | |
8ec2cd48 | 1817 | else |
dc35a10f | 1818 | return kmalloc(frag_size, GFP_ATOMIC); |
8ec2cd48 | 1819 | } |
dc35a10f | 1820 | EXPORT_SYMBOL_GPL(mvneta_frag_alloc); |
8ec2cd48 | 1821 | |
dc35a10f | 1822 | void mvneta_frag_free(unsigned int frag_size, void *data) |
8ec2cd48 | 1823 | { |
dc35a10f | 1824 | if (likely(frag_size <= PAGE_SIZE)) |
13dc0d2b | 1825 | skb_free_frag(data); |
8ec2cd48 | 1826 | else |
1827 | kfree(data); | |
1828 | } | |
dc35a10f | 1829 | EXPORT_SYMBOL_GPL(mvneta_frag_free); |
8ec2cd48 | 1830 | |
dc35a10f | 1831 | /* Refill processing for SW buffer management */ |
c5aff182 | 1832 | static int mvneta_rx_refill(struct mvneta_port *pp, |
f88bee1c GC |
1833 | struct mvneta_rx_desc *rx_desc, |
1834 | struct mvneta_rx_queue *rxq) | |
c5aff182 TP |
1835 | |
1836 | { | |
1837 | dma_addr_t phys_addr; | |
8ec2cd48 | 1838 | void *data; |
c5aff182 | 1839 | |
dc35a10f | 1840 | data = mvneta_frag_alloc(pp->frag_size); |
8ec2cd48 | 1841 | if (!data) |
c5aff182 TP |
1842 | return -ENOMEM; |
1843 | ||
8ec2cd48 | 1844 | phys_addr = dma_map_single(pp->dev->dev.parent, data, |
c5aff182 TP |
1845 | MVNETA_RX_BUF_SIZE(pp->pkt_size), |
1846 | DMA_FROM_DEVICE); | |
1847 | if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { | |
dc35a10f | 1848 | mvneta_frag_free(pp->frag_size, data); |
c5aff182 TP |
1849 | return -ENOMEM; |
1850 | } | |
1851 | ||
8d5047cf | 1852 | phys_addr += pp->rx_offset_correction; |
f88bee1c | 1853 | mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq); |
c5aff182 TP |
1854 | return 0; |
1855 | } | |
1856 | ||
1857 | /* Handle tx checksum */ | |
1858 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) | |
1859 | { | |
1860 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1861 | int ip_hdr_len = 0; | |
817dbfa5 | 1862 | __be16 l3_proto = vlan_get_protocol(skb); |
c5aff182 TP |
1863 | u8 l4_proto; |
1864 | ||
817dbfa5 | 1865 | if (l3_proto == htons(ETH_P_IP)) { |
c5aff182 TP |
1866 | struct iphdr *ip4h = ip_hdr(skb); |
1867 | ||
1868 | /* Calculate IPv4 checksum and L4 checksum */ | |
1869 | ip_hdr_len = ip4h->ihl; | |
1870 | l4_proto = ip4h->protocol; | |
817dbfa5 | 1871 | } else if (l3_proto == htons(ETH_P_IPV6)) { |
c5aff182 TP |
1872 | struct ipv6hdr *ip6h = ipv6_hdr(skb); |
1873 | ||
1874 | /* Read l4_protocol from one of IPv6 extra headers */ | |
1875 | if (skb_network_header_len(skb) > 0) | |
1876 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
1877 | l4_proto = ip6h->nexthdr; | |
1878 | } else | |
1879 | return MVNETA_TX_L4_CSUM_NOT; | |
1880 | ||
1881 | return mvneta_txq_desc_csum(skb_network_offset(skb), | |
817dbfa5 | 1882 | l3_proto, ip_hdr_len, l4_proto); |
c5aff182 TP |
1883 | } |
1884 | ||
1885 | return MVNETA_TX_L4_CSUM_NOT; | |
1886 | } | |
1887 | ||
c5aff182 TP |
1888 | /* Drop packets received by the RXQ and free buffers */ |
1889 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
1890 | struct mvneta_rx_queue *rxq) | |
1891 | { | |
1892 | int rx_done, i; | |
1893 | ||
1894 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
dc35a10f MW |
1895 | if (rx_done) |
1896 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
1897 | ||
1898 | if (pp->bm_priv) { | |
1899 | for (i = 0; i < rx_done; i++) { | |
1900 | struct mvneta_rx_desc *rx_desc = | |
1901 | mvneta_rxq_next_desc_get(rxq); | |
1902 | u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); | |
1903 | struct mvneta_bm_pool *bm_pool; | |
1904 | ||
1905 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
1906 | /* Return dropped buffer to the pool */ | |
1907 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
1908 | rx_desc->buf_phys_addr); | |
1909 | } | |
1910 | return; | |
1911 | } | |
1912 | ||
c5aff182 TP |
1913 | for (i = 0; i < rxq->size; i++) { |
1914 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; | |
f88bee1c | 1915 | void *data = rxq->buf_virt_addr[i]; |
c5aff182 | 1916 | |
c5aff182 | 1917 | dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, |
a328f3a0 | 1918 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
dc35a10f | 1919 | mvneta_frag_free(pp->frag_size, data); |
c5aff182 | 1920 | } |
dc35a10f | 1921 | } |
c5aff182 | 1922 | |
dc35a10f MW |
1923 | /* Main rx processing when using software buffer management */ |
1924 | static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo, | |
1925 | struct mvneta_rx_queue *rxq) | |
1926 | { | |
1927 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); | |
1928 | struct net_device *dev = pp->dev; | |
1929 | int rx_done; | |
1930 | u32 rcvd_pkts = 0; | |
1931 | u32 rcvd_bytes = 0; | |
1932 | ||
1933 | /* Get number of received packets */ | |
1934 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
1935 | ||
1936 | if (rx_todo > rx_done) | |
1937 | rx_todo = rx_done; | |
1938 | ||
1939 | rx_done = 0; | |
1940 | ||
1941 | /* Fairness NAPI loop */ | |
1942 | while (rx_done < rx_todo) { | |
1943 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
1944 | struct sk_buff *skb; | |
1945 | unsigned char *data; | |
1946 | dma_addr_t phys_addr; | |
1947 | u32 rx_status, frag_size; | |
f88bee1c | 1948 | int rx_bytes, err, index; |
dc35a10f MW |
1949 | |
1950 | rx_done++; | |
1951 | rx_status = rx_desc->status; | |
1952 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); | |
f88bee1c GC |
1953 | index = rx_desc - rxq->descs; |
1954 | data = rxq->buf_virt_addr[index]; | |
dc35a10f MW |
1955 | phys_addr = rx_desc->buf_phys_addr; |
1956 | ||
1957 | if (!mvneta_rxq_desc_is_first_last(rx_status) || | |
1958 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { | |
1959 | err_drop_frame: | |
1960 | dev->stats.rx_errors++; | |
1961 | mvneta_rx_error(pp, rx_desc); | |
1962 | /* leave the descriptor untouched */ | |
1963 | continue; | |
1964 | } | |
1965 | ||
1966 | if (rx_bytes <= rx_copybreak) { | |
1967 | /* better copy a small frame and not unmap the DMA region */ | |
1968 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
1969 | if (unlikely(!skb)) | |
1970 | goto err_drop_frame; | |
1971 | ||
1972 | dma_sync_single_range_for_cpu(dev->dev.parent, | |
ac83b7dd | 1973 | phys_addr, |
dc35a10f MW |
1974 | MVNETA_MH_SIZE + NET_SKB_PAD, |
1975 | rx_bytes, | |
1976 | DMA_FROM_DEVICE); | |
1977 | memcpy(skb_put(skb, rx_bytes), | |
1978 | data + MVNETA_MH_SIZE + NET_SKB_PAD, | |
1979 | rx_bytes); | |
1980 | ||
1981 | skb->protocol = eth_type_trans(skb, dev); | |
1982 | mvneta_rx_csum(pp, rx_status, skb); | |
1983 | napi_gro_receive(&port->napi, skb); | |
1984 | ||
1985 | rcvd_pkts++; | |
1986 | rcvd_bytes += rx_bytes; | |
1987 | ||
1988 | /* leave the descriptor and buffer untouched */ | |
1989 | continue; | |
1990 | } | |
1991 | ||
1992 | /* Refill processing */ | |
f88bee1c | 1993 | err = mvneta_rx_refill(pp, rx_desc, rxq); |
dc35a10f MW |
1994 | if (err) { |
1995 | netdev_err(dev, "Linux processing - Can't refill\n"); | |
1996 | rxq->missed++; | |
1997 | goto err_drop_frame; | |
1998 | } | |
1999 | ||
2000 | frag_size = pp->frag_size; | |
2001 | ||
2002 | skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); | |
2003 | ||
2004 | /* After refill old buffer has to be unmapped regardless | |
2005 | * the skb is successfully built or not. | |
2006 | */ | |
2007 | dma_unmap_single(dev->dev.parent, phys_addr, | |
2008 | MVNETA_RX_BUF_SIZE(pp->pkt_size), | |
2009 | DMA_FROM_DEVICE); | |
2010 | ||
2011 | if (!skb) | |
2012 | goto err_drop_frame; | |
2013 | ||
2014 | rcvd_pkts++; | |
2015 | rcvd_bytes += rx_bytes; | |
2016 | ||
2017 | /* Linux processing */ | |
2018 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); | |
2019 | skb_put(skb, rx_bytes); | |
2020 | ||
2021 | skb->protocol = eth_type_trans(skb, dev); | |
2022 | ||
2023 | mvneta_rx_csum(pp, rx_status, skb); | |
2024 | ||
2025 | napi_gro_receive(&port->napi, skb); | |
2026 | } | |
2027 | ||
2028 | if (rcvd_pkts) { | |
2029 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); | |
2030 | ||
2031 | u64_stats_update_begin(&stats->syncp); | |
2032 | stats->rx_packets += rcvd_pkts; | |
2033 | stats->rx_bytes += rcvd_bytes; | |
2034 | u64_stats_update_end(&stats->syncp); | |
2035 | } | |
2036 | ||
2037 | /* Update rxq management counters */ | |
2038 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
2039 | ||
2040 | return rx_done; | |
c5aff182 TP |
2041 | } |
2042 | ||
dc35a10f MW |
2043 | /* Main rx processing when using hardware buffer management */ |
2044 | static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo, | |
2045 | struct mvneta_rx_queue *rxq) | |
c5aff182 | 2046 | { |
12bb03b4 | 2047 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 | 2048 | struct net_device *dev = pp->dev; |
a84e3289 | 2049 | int rx_done; |
dc4277dd | 2050 | u32 rcvd_pkts = 0; |
2051 | u32 rcvd_bytes = 0; | |
c5aff182 TP |
2052 | |
2053 | /* Get number of received packets */ | |
2054 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
2055 | ||
2056 | if (rx_todo > rx_done) | |
2057 | rx_todo = rx_done; | |
2058 | ||
2059 | rx_done = 0; | |
c5aff182 TP |
2060 | |
2061 | /* Fairness NAPI loop */ | |
2062 | while (rx_done < rx_todo) { | |
2063 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
dc35a10f | 2064 | struct mvneta_bm_pool *bm_pool = NULL; |
c5aff182 | 2065 | struct sk_buff *skb; |
8ec2cd48 | 2066 | unsigned char *data; |
daf158d0 | 2067 | dma_addr_t phys_addr; |
dc35a10f | 2068 | u32 rx_status, frag_size; |
c5aff182 | 2069 | int rx_bytes, err; |
dc35a10f | 2070 | u8 pool_id; |
c5aff182 | 2071 | |
c5aff182 | 2072 | rx_done++; |
c5aff182 | 2073 | rx_status = rx_desc->status; |
f19fadfc | 2074 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); |
f88bee1c | 2075 | data = (u8 *)(uintptr_t)rx_desc->buf_cookie; |
daf158d0 | 2076 | phys_addr = rx_desc->buf_phys_addr; |
dc35a10f MW |
2077 | pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); |
2078 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
c5aff182 | 2079 | |
5428213c | 2080 | if (!mvneta_rxq_desc_is_first_last(rx_status) || |
f19fadfc | 2081 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { |
dc35a10f MW |
2082 | err_drop_frame_ret_pool: |
2083 | /* Return the buffer to the pool */ | |
2084 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2085 | rx_desc->buf_phys_addr); | |
2086 | err_drop_frame: | |
c5aff182 TP |
2087 | dev->stats.rx_errors++; |
2088 | mvneta_rx_error(pp, rx_desc); | |
8ec2cd48 | 2089 | /* leave the descriptor untouched */ |
c5aff182 TP |
2090 | continue; |
2091 | } | |
2092 | ||
f19fadfc | 2093 | if (rx_bytes <= rx_copybreak) { |
2094 | /* better copy a small frame and not unmap the DMA region */ | |
2095 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
2096 | if (unlikely(!skb)) | |
dc35a10f | 2097 | goto err_drop_frame_ret_pool; |
f19fadfc | 2098 | |
2099 | dma_sync_single_range_for_cpu(dev->dev.parent, | |
2100 | rx_desc->buf_phys_addr, | |
2101 | MVNETA_MH_SIZE + NET_SKB_PAD, | |
2102 | rx_bytes, | |
2103 | DMA_FROM_DEVICE); | |
2104 | memcpy(skb_put(skb, rx_bytes), | |
2105 | data + MVNETA_MH_SIZE + NET_SKB_PAD, | |
2106 | rx_bytes); | |
2107 | ||
2108 | skb->protocol = eth_type_trans(skb, dev); | |
2109 | mvneta_rx_csum(pp, rx_status, skb); | |
12bb03b4 | 2110 | napi_gro_receive(&port->napi, skb); |
f19fadfc | 2111 | |
2112 | rcvd_pkts++; | |
2113 | rcvd_bytes += rx_bytes; | |
2114 | ||
dc35a10f MW |
2115 | /* Return the buffer to the pool */ |
2116 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2117 | rx_desc->buf_phys_addr); | |
2118 | ||
f19fadfc | 2119 | /* leave the descriptor and buffer untouched */ |
2120 | continue; | |
2121 | } | |
2122 | ||
a84e3289 | 2123 | /* Refill processing */ |
baa11ebc | 2124 | err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); |
a84e3289 SG |
2125 | if (err) { |
2126 | netdev_err(dev, "Linux processing - Can't refill\n"); | |
2127 | rxq->missed++; | |
dc35a10f | 2128 | goto err_drop_frame_ret_pool; |
a84e3289 SG |
2129 | } |
2130 | ||
baa11ebc | 2131 | frag_size = bm_pool->hwbm_pool.frag_size; |
dc35a10f MW |
2132 | |
2133 | skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); | |
f19fadfc | 2134 | |
26c17a17 MW |
2135 | /* After refill old buffer has to be unmapped regardless |
2136 | * the skb is successfully built or not. | |
2137 | */ | |
dc35a10f MW |
2138 | dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, |
2139 | bm_pool->buf_size, DMA_FROM_DEVICE); | |
26c17a17 MW |
2140 | if (!skb) |
2141 | goto err_drop_frame; | |
2142 | ||
dc4277dd | 2143 | rcvd_pkts++; |
2144 | rcvd_bytes += rx_bytes; | |
c5aff182 TP |
2145 | |
2146 | /* Linux processing */ | |
8ec2cd48 | 2147 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); |
c5aff182 TP |
2148 | skb_put(skb, rx_bytes); |
2149 | ||
2150 | skb->protocol = eth_type_trans(skb, dev); | |
2151 | ||
5428213c | 2152 | mvneta_rx_csum(pp, rx_status, skb); |
c5aff182 | 2153 | |
12bb03b4 | 2154 | napi_gro_receive(&port->napi, skb); |
c5aff182 TP |
2155 | } |
2156 | ||
dc4277dd | 2157 | if (rcvd_pkts) { |
74c41b04 | 2158 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
2159 | ||
2160 | u64_stats_update_begin(&stats->syncp); | |
2161 | stats->rx_packets += rcvd_pkts; | |
2162 | stats->rx_bytes += rcvd_bytes; | |
2163 | u64_stats_update_end(&stats->syncp); | |
dc4277dd | 2164 | } |
2165 | ||
c5aff182 | 2166 | /* Update rxq management counters */ |
a84e3289 | 2167 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
c5aff182 TP |
2168 | |
2169 | return rx_done; | |
2170 | } | |
2171 | ||
2adb719d EG |
2172 | static inline void |
2173 | mvneta_tso_put_hdr(struct sk_buff *skb, | |
2174 | struct mvneta_port *pp, struct mvneta_tx_queue *txq) | |
2175 | { | |
2176 | struct mvneta_tx_desc *tx_desc; | |
2177 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2178 | ||
2179 | txq->tx_skb[txq->txq_put_index] = NULL; | |
2180 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2181 | tx_desc->data_size = hdr_len; | |
2182 | tx_desc->command = mvneta_skb_tx_csum(pp, skb); | |
2183 | tx_desc->command |= MVNETA_TXD_F_DESC; | |
2184 | tx_desc->buf_phys_addr = txq->tso_hdrs_phys + | |
2185 | txq->txq_put_index * TSO_HEADER_SIZE; | |
2186 | mvneta_txq_inc_put(txq); | |
2187 | } | |
2188 | ||
2189 | static inline int | |
2190 | mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, | |
2191 | struct sk_buff *skb, char *data, int size, | |
2192 | bool last_tcp, bool is_last) | |
2193 | { | |
2194 | struct mvneta_tx_desc *tx_desc; | |
2195 | ||
2196 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2197 | tx_desc->data_size = size; | |
2198 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, | |
2199 | size, DMA_TO_DEVICE); | |
2200 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2201 | tx_desc->buf_phys_addr))) { | |
2202 | mvneta_txq_desc_put(txq); | |
2203 | return -ENOMEM; | |
2204 | } | |
2205 | ||
2206 | tx_desc->command = 0; | |
2207 | txq->tx_skb[txq->txq_put_index] = NULL; | |
2208 | ||
2209 | if (last_tcp) { | |
2210 | /* last descriptor in the TCP packet */ | |
2211 | tx_desc->command = MVNETA_TXD_L_DESC; | |
2212 | ||
2213 | /* last descriptor in SKB */ | |
2214 | if (is_last) | |
2215 | txq->tx_skb[txq->txq_put_index] = skb; | |
2216 | } | |
2217 | mvneta_txq_inc_put(txq); | |
2218 | return 0; | |
2219 | } | |
2220 | ||
2221 | static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
2222 | struct mvneta_tx_queue *txq) | |
2223 | { | |
2224 | int total_len, data_left; | |
2225 | int desc_count = 0; | |
2226 | struct mvneta_port *pp = netdev_priv(dev); | |
2227 | struct tso_t tso; | |
2228 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2229 | int i; | |
2230 | ||
2231 | /* Count needed descriptors */ | |
2232 | if ((txq->count + tso_count_descs(skb)) >= txq->size) | |
2233 | return 0; | |
2234 | ||
2235 | if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { | |
2236 | pr_info("*** Is this even possible???!?!?\n"); | |
2237 | return 0; | |
2238 | } | |
2239 | ||
2240 | /* Initialize the TSO handler, and prepare the first payload */ | |
2241 | tso_start(skb, &tso); | |
2242 | ||
2243 | total_len = skb->len - hdr_len; | |
2244 | while (total_len > 0) { | |
2245 | char *hdr; | |
2246 | ||
2247 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); | |
2248 | total_len -= data_left; | |
2249 | desc_count++; | |
2250 | ||
2251 | /* prepare packet headers: MAC + IP + TCP */ | |
2252 | hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; | |
2253 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); | |
2254 | ||
2255 | mvneta_tso_put_hdr(skb, pp, txq); | |
2256 | ||
2257 | while (data_left > 0) { | |
2258 | int size; | |
2259 | desc_count++; | |
2260 | ||
2261 | size = min_t(int, tso.size, data_left); | |
2262 | ||
2263 | if (mvneta_tso_put_data(dev, txq, skb, | |
2264 | tso.data, size, | |
2265 | size == data_left, | |
2266 | total_len == 0)) | |
2267 | goto err_release; | |
2268 | data_left -= size; | |
2269 | ||
2270 | tso_build_data(skb, &tso, size); | |
2271 | } | |
2272 | } | |
2273 | ||
2274 | return desc_count; | |
2275 | ||
2276 | err_release: | |
2277 | /* Release all used data descriptors; header descriptors must not | |
2278 | * be DMA-unmapped. | |
2279 | */ | |
2280 | for (i = desc_count - 1; i >= 0; i--) { | |
2281 | struct mvneta_tx_desc *tx_desc = txq->descs + i; | |
2e3173a3 | 2282 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
2adb719d EG |
2283 | dma_unmap_single(pp->dev->dev.parent, |
2284 | tx_desc->buf_phys_addr, | |
2285 | tx_desc->data_size, | |
2286 | DMA_TO_DEVICE); | |
2287 | mvneta_txq_desc_put(txq); | |
2288 | } | |
2289 | return 0; | |
2290 | } | |
2291 | ||
c5aff182 TP |
2292 | /* Handle tx fragmentation processing */ |
2293 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, | |
2294 | struct mvneta_tx_queue *txq) | |
2295 | { | |
2296 | struct mvneta_tx_desc *tx_desc; | |
3d4ea02f | 2297 | int i, nr_frags = skb_shinfo(skb)->nr_frags; |
c5aff182 | 2298 | |
3d4ea02f | 2299 | for (i = 0; i < nr_frags; i++) { |
c5aff182 TP |
2300 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
2301 | void *addr = page_address(frag->page.p) + frag->page_offset; | |
2302 | ||
2303 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2304 | tx_desc->data_size = frag->size; | |
2305 | ||
2306 | tx_desc->buf_phys_addr = | |
2307 | dma_map_single(pp->dev->dev.parent, addr, | |
2308 | tx_desc->data_size, DMA_TO_DEVICE); | |
2309 | ||
2310 | if (dma_mapping_error(pp->dev->dev.parent, | |
2311 | tx_desc->buf_phys_addr)) { | |
2312 | mvneta_txq_desc_put(txq); | |
2313 | goto error; | |
2314 | } | |
2315 | ||
3d4ea02f | 2316 | if (i == nr_frags - 1) { |
c5aff182 TP |
2317 | /* Last descriptor */ |
2318 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; | |
c5aff182 | 2319 | txq->tx_skb[txq->txq_put_index] = skb; |
c5aff182 TP |
2320 | } else { |
2321 | /* Descriptor in the middle: Not First, Not Last */ | |
2322 | tx_desc->command = 0; | |
c5aff182 | 2323 | txq->tx_skb[txq->txq_put_index] = NULL; |
c5aff182 | 2324 | } |
3d4ea02f | 2325 | mvneta_txq_inc_put(txq); |
c5aff182 TP |
2326 | } |
2327 | ||
2328 | return 0; | |
2329 | ||
2330 | error: | |
2331 | /* Release all descriptors that were used to map fragments of | |
6a20c175 TP |
2332 | * this packet, as well as the corresponding DMA mappings |
2333 | */ | |
c5aff182 TP |
2334 | for (i = i - 1; i >= 0; i--) { |
2335 | tx_desc = txq->descs + i; | |
2336 | dma_unmap_single(pp->dev->dev.parent, | |
2337 | tx_desc->buf_phys_addr, | |
2338 | tx_desc->data_size, | |
2339 | DMA_TO_DEVICE); | |
2340 | mvneta_txq_desc_put(txq); | |
2341 | } | |
2342 | ||
2343 | return -ENOMEM; | |
2344 | } | |
2345 | ||
2346 | /* Main tx processing */ | |
2347 | static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) | |
2348 | { | |
2349 | struct mvneta_port *pp = netdev_priv(dev); | |
ee40a116 WT |
2350 | u16 txq_id = skb_get_queue_mapping(skb); |
2351 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; | |
c5aff182 | 2352 | struct mvneta_tx_desc *tx_desc; |
5f478b41 | 2353 | int len = skb->len; |
c5aff182 TP |
2354 | int frags = 0; |
2355 | u32 tx_cmd; | |
2356 | ||
2357 | if (!netif_running(dev)) | |
2358 | goto out; | |
2359 | ||
2adb719d EG |
2360 | if (skb_is_gso(skb)) { |
2361 | frags = mvneta_tx_tso(skb, dev, txq); | |
2362 | goto out; | |
2363 | } | |
2364 | ||
c5aff182 | 2365 | frags = skb_shinfo(skb)->nr_frags + 1; |
c5aff182 TP |
2366 | |
2367 | /* Get a descriptor for the first part of the packet */ | |
2368 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2369 | ||
2370 | tx_cmd = mvneta_skb_tx_csum(pp, skb); | |
2371 | ||
2372 | tx_desc->data_size = skb_headlen(skb); | |
2373 | ||
2374 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, | |
2375 | tx_desc->data_size, | |
2376 | DMA_TO_DEVICE); | |
2377 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2378 | tx_desc->buf_phys_addr))) { | |
2379 | mvneta_txq_desc_put(txq); | |
2380 | frags = 0; | |
2381 | goto out; | |
2382 | } | |
2383 | ||
2384 | if (frags == 1) { | |
2385 | /* First and Last descriptor */ | |
2386 | tx_cmd |= MVNETA_TXD_FLZ_DESC; | |
2387 | tx_desc->command = tx_cmd; | |
2388 | txq->tx_skb[txq->txq_put_index] = skb; | |
2389 | mvneta_txq_inc_put(txq); | |
2390 | } else { | |
2391 | /* First but not Last */ | |
2392 | tx_cmd |= MVNETA_TXD_F_DESC; | |
2393 | txq->tx_skb[txq->txq_put_index] = NULL; | |
2394 | mvneta_txq_inc_put(txq); | |
2395 | tx_desc->command = tx_cmd; | |
2396 | /* Continue with other skb fragments */ | |
2397 | if (mvneta_tx_frag_process(pp, skb, txq)) { | |
2398 | dma_unmap_single(dev->dev.parent, | |
2399 | tx_desc->buf_phys_addr, | |
2400 | tx_desc->data_size, | |
2401 | DMA_TO_DEVICE); | |
2402 | mvneta_txq_desc_put(txq); | |
2403 | frags = 0; | |
2404 | goto out; | |
2405 | } | |
2406 | } | |
2407 | ||
c5aff182 TP |
2408 | out: |
2409 | if (frags > 0) { | |
74c41b04 | 2410 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
e19d2dda EG |
2411 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
2412 | ||
a29b6235 MW |
2413 | netdev_tx_sent_queue(nq, len); |
2414 | ||
e19d2dda | 2415 | txq->count += frags; |
8eef5f97 | 2416 | if (txq->count >= txq->tx_stop_threshold) |
e19d2dda | 2417 | netif_tx_stop_queue(nq); |
c5aff182 | 2418 | |
2a90f7e1 SG |
2419 | if (!skb->xmit_more || netif_xmit_stopped(nq) || |
2420 | txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) | |
2421 | mvneta_txq_pend_desc_add(pp, txq, frags); | |
2422 | else | |
2423 | txq->pending += frags; | |
2424 | ||
74c41b04 | 2425 | u64_stats_update_begin(&stats->syncp); |
2426 | stats->tx_packets++; | |
5f478b41 | 2427 | stats->tx_bytes += len; |
74c41b04 | 2428 | u64_stats_update_end(&stats->syncp); |
c5aff182 TP |
2429 | } else { |
2430 | dev->stats.tx_dropped++; | |
2431 | dev_kfree_skb_any(skb); | |
2432 | } | |
2433 | ||
c5aff182 TP |
2434 | return NETDEV_TX_OK; |
2435 | } | |
2436 | ||
2437 | ||
2438 | /* Free tx resources, when resetting a port */ | |
2439 | static void mvneta_txq_done_force(struct mvneta_port *pp, | |
2440 | struct mvneta_tx_queue *txq) | |
2441 | ||
2442 | { | |
a29b6235 | 2443 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
c5aff182 TP |
2444 | int tx_done = txq->count; |
2445 | ||
a29b6235 | 2446 | mvneta_txq_bufs_free(pp, txq, tx_done, nq); |
c5aff182 TP |
2447 | |
2448 | /* reset txq */ | |
2449 | txq->count = 0; | |
2450 | txq->txq_put_index = 0; | |
2451 | txq->txq_get_index = 0; | |
2452 | } | |
2453 | ||
6c498974 | 2454 | /* Handle tx done - called in softirq context. The <cause_tx_done> argument |
2455 | * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. | |
2456 | */ | |
0713a86a | 2457 | static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) |
c5aff182 TP |
2458 | { |
2459 | struct mvneta_tx_queue *txq; | |
c5aff182 TP |
2460 | struct netdev_queue *nq; |
2461 | ||
6c498974 | 2462 | while (cause_tx_done) { |
c5aff182 | 2463 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
c5aff182 TP |
2464 | |
2465 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
2466 | __netif_tx_lock(nq, smp_processor_id()); | |
2467 | ||
0713a86a AE |
2468 | if (txq->count) |
2469 | mvneta_txq_done(pp, txq); | |
c5aff182 TP |
2470 | |
2471 | __netif_tx_unlock(nq); | |
2472 | cause_tx_done &= ~((1 << txq->id)); | |
2473 | } | |
c5aff182 TP |
2474 | } |
2475 | ||
6a20c175 | 2476 | /* Compute crc8 of the specified address, using a unique algorithm , |
c5aff182 TP |
2477 | * according to hw spec, different than generic crc8 algorithm |
2478 | */ | |
2479 | static int mvneta_addr_crc(unsigned char *addr) | |
2480 | { | |
2481 | int crc = 0; | |
2482 | int i; | |
2483 | ||
2484 | for (i = 0; i < ETH_ALEN; i++) { | |
2485 | int j; | |
2486 | ||
2487 | crc = (crc ^ addr[i]) << 8; | |
2488 | for (j = 7; j >= 0; j--) { | |
2489 | if (crc & (0x100 << j)) | |
2490 | crc ^= 0x107 << j; | |
2491 | } | |
2492 | } | |
2493 | ||
2494 | return crc; | |
2495 | } | |
2496 | ||
2497 | /* This method controls the net device special MAC multicast support. | |
2498 | * The Special Multicast Table for MAC addresses supports MAC of the form | |
2499 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2500 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2501 | * Table entries in the DA-Filter table. This method set the Special | |
2502 | * Multicast Table appropriate entry. | |
2503 | */ | |
2504 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, | |
2505 | unsigned char last_byte, | |
2506 | int queue) | |
2507 | { | |
2508 | unsigned int smc_table_reg; | |
2509 | unsigned int tbl_offset; | |
2510 | unsigned int reg_offset; | |
2511 | ||
2512 | /* Register offset from SMC table base */ | |
2513 | tbl_offset = (last_byte / 4); | |
2514 | /* Entry offset within the above reg */ | |
2515 | reg_offset = last_byte % 4; | |
2516 | ||
2517 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST | |
2518 | + tbl_offset * 4)); | |
2519 | ||
2520 | if (queue == -1) | |
2521 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2522 | else { | |
2523 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2524 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2525 | } | |
2526 | ||
2527 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, | |
2528 | smc_table_reg); | |
2529 | } | |
2530 | ||
2531 | /* This method controls the network device Other MAC multicast support. | |
2532 | * The Other Multicast Table is used for multicast of another type. | |
2533 | * A CRC-8 is used as an index to the Other Multicast Table entries | |
2534 | * in the DA-Filter table. | |
2535 | * The method gets the CRC-8 value from the calling routine and | |
2536 | * sets the Other Multicast Table appropriate entry according to the | |
2537 | * specified CRC-8 . | |
2538 | */ | |
2539 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, | |
2540 | unsigned char crc8, | |
2541 | int queue) | |
2542 | { | |
2543 | unsigned int omc_table_reg; | |
2544 | unsigned int tbl_offset; | |
2545 | unsigned int reg_offset; | |
2546 | ||
2547 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ | |
2548 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ | |
2549 | ||
2550 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); | |
2551 | ||
2552 | if (queue == -1) { | |
2553 | /* Clear accepts frame bit at specified Other DA table entry */ | |
2554 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2555 | } else { | |
2556 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2557 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2558 | } | |
2559 | ||
2560 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); | |
2561 | } | |
2562 | ||
2563 | /* The network device supports multicast using two tables: | |
2564 | * 1) Special Multicast Table for MAC addresses of the form | |
2565 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2566 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2567 | * Table entries in the DA-Filter table. | |
2568 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value | |
2569 | * is used as an index to the Other Multicast Table entries in the | |
2570 | * DA-Filter table. | |
2571 | */ | |
2572 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, | |
2573 | int queue) | |
2574 | { | |
2575 | unsigned char crc_result = 0; | |
2576 | ||
2577 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { | |
2578 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); | |
2579 | return 0; | |
2580 | } | |
2581 | ||
2582 | crc_result = mvneta_addr_crc(p_addr); | |
2583 | if (queue == -1) { | |
2584 | if (pp->mcast_count[crc_result] == 0) { | |
2585 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", | |
2586 | crc_result); | |
2587 | return -EINVAL; | |
2588 | } | |
2589 | ||
2590 | pp->mcast_count[crc_result]--; | |
2591 | if (pp->mcast_count[crc_result] != 0) { | |
2592 | netdev_info(pp->dev, | |
2593 | "After delete there are %d valid Mcast for crc8=0x%02x\n", | |
2594 | pp->mcast_count[crc_result], crc_result); | |
2595 | return -EINVAL; | |
2596 | } | |
2597 | } else | |
2598 | pp->mcast_count[crc_result]++; | |
2599 | ||
2600 | mvneta_set_other_mcast_addr(pp, crc_result, queue); | |
2601 | ||
2602 | return 0; | |
2603 | } | |
2604 | ||
2605 | /* Configure Fitering mode of Ethernet port */ | |
2606 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, | |
2607 | int is_promisc) | |
2608 | { | |
2609 | u32 port_cfg_reg, val; | |
2610 | ||
2611 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); | |
2612 | ||
2613 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); | |
2614 | ||
2615 | /* Set / Clear UPM bit in port configuration register */ | |
2616 | if (is_promisc) { | |
2617 | /* Accept all Unicast addresses */ | |
2618 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; | |
2619 | val |= MVNETA_FORCE_UNI; | |
2620 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); | |
2621 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); | |
2622 | } else { | |
2623 | /* Reject all Unicast addresses */ | |
2624 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; | |
2625 | val &= ~MVNETA_FORCE_UNI; | |
2626 | } | |
2627 | ||
2628 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); | |
2629 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); | |
2630 | } | |
2631 | ||
2632 | /* register unicast and multicast addresses */ | |
2633 | static void mvneta_set_rx_mode(struct net_device *dev) | |
2634 | { | |
2635 | struct mvneta_port *pp = netdev_priv(dev); | |
2636 | struct netdev_hw_addr *ha; | |
2637 | ||
2638 | if (dev->flags & IFF_PROMISC) { | |
2639 | /* Accept all: Multicast + Unicast */ | |
2640 | mvneta_rx_unicast_promisc_set(pp, 1); | |
90b74c01 GC |
2641 | mvneta_set_ucast_table(pp, pp->rxq_def); |
2642 | mvneta_set_special_mcast_table(pp, pp->rxq_def); | |
2643 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2644 | } else { |
2645 | /* Accept single Unicast */ | |
2646 | mvneta_rx_unicast_promisc_set(pp, 0); | |
2647 | mvneta_set_ucast_table(pp, -1); | |
90b74c01 | 2648 | mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); |
c5aff182 TP |
2649 | |
2650 | if (dev->flags & IFF_ALLMULTI) { | |
2651 | /* Accept all multicast */ | |
90b74c01 GC |
2652 | mvneta_set_special_mcast_table(pp, pp->rxq_def); |
2653 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2654 | } else { |
2655 | /* Accept only initialized multicast */ | |
2656 | mvneta_set_special_mcast_table(pp, -1); | |
2657 | mvneta_set_other_mcast_table(pp, -1); | |
2658 | ||
2659 | if (!netdev_mc_empty(dev)) { | |
2660 | netdev_for_each_mc_addr(ha, dev) { | |
2661 | mvneta_mcast_addr_set(pp, ha->addr, | |
90b74c01 | 2662 | pp->rxq_def); |
c5aff182 TP |
2663 | } |
2664 | } | |
2665 | } | |
2666 | } | |
2667 | } | |
2668 | ||
2669 | /* Interrupt handling - the callback for request_irq() */ | |
2670 | static irqreturn_t mvneta_isr(int irq, void *dev_id) | |
2636ac3c MW |
2671 | { |
2672 | struct mvneta_port *pp = (struct mvneta_port *)dev_id; | |
2673 | ||
2674 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
2675 | napi_schedule(&pp->napi); | |
2676 | ||
2677 | return IRQ_HANDLED; | |
2678 | } | |
2679 | ||
2680 | /* Interrupt handling - the callback for request_percpu_irq() */ | |
2681 | static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) | |
c5aff182 | 2682 | { |
12bb03b4 | 2683 | struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; |
c5aff182 | 2684 | |
12bb03b4 | 2685 | disable_percpu_irq(port->pp->dev->irq); |
12bb03b4 | 2686 | napi_schedule(&port->napi); |
c5aff182 TP |
2687 | |
2688 | return IRQ_HANDLED; | |
2689 | } | |
2690 | ||
898b2970 SS |
2691 | static int mvneta_fixed_link_update(struct mvneta_port *pp, |
2692 | struct phy_device *phy) | |
2693 | { | |
2694 | struct fixed_phy_status status; | |
2695 | struct fixed_phy_status changed = {}; | |
2696 | u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); | |
2697 | ||
2698 | status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); | |
2699 | if (gmac_stat & MVNETA_GMAC_SPEED_1000) | |
2700 | status.speed = SPEED_1000; | |
2701 | else if (gmac_stat & MVNETA_GMAC_SPEED_100) | |
2702 | status.speed = SPEED_100; | |
2703 | else | |
2704 | status.speed = SPEED_10; | |
2705 | status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); | |
2706 | changed.link = 1; | |
2707 | changed.speed = 1; | |
2708 | changed.duplex = 1; | |
2709 | fixed_phy_update_state(phy, &status, &changed); | |
2710 | return 0; | |
2711 | } | |
2712 | ||
c5aff182 TP |
2713 | /* NAPI handler |
2714 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted | |
2715 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). | |
2716 | * Bits 8 -15 of the cause Rx Tx register indicate that are received | |
2717 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). | |
2718 | * Each CPU has its own causeRxTx register | |
2719 | */ | |
2720 | static int mvneta_poll(struct napi_struct *napi, int budget) | |
2721 | { | |
2722 | int rx_done = 0; | |
2723 | u32 cause_rx_tx; | |
2dcf75e2 | 2724 | int rx_queue; |
c5aff182 | 2725 | struct mvneta_port *pp = netdev_priv(napi->dev); |
c6c022e3 | 2726 | struct net_device *ndev = pp->dev; |
12bb03b4 | 2727 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 TP |
2728 | |
2729 | if (!netif_running(pp->dev)) { | |
2636ac3c | 2730 | napi_complete(napi); |
c5aff182 TP |
2731 | return rx_done; |
2732 | } | |
2733 | ||
2734 | /* Read cause register */ | |
898b2970 SS |
2735 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); |
2736 | if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { | |
2737 | u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); | |
2738 | ||
2739 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
2740 | if (pp->use_inband_status && (cause_misc & | |
2741 | (MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
2742 | MVNETA_CAUSE_LINK_CHANGE | | |
2743 | MVNETA_CAUSE_PSC_SYNC_CHANGE))) { | |
c6c022e3 | 2744 | mvneta_fixed_link_update(pp, ndev->phydev); |
898b2970 SS |
2745 | } |
2746 | } | |
71f6d1b3 | 2747 | |
2748 | /* Release Tx descriptors */ | |
2749 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { | |
0713a86a | 2750 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); |
71f6d1b3 | 2751 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; |
2752 | } | |
c5aff182 | 2753 | |
6a20c175 | 2754 | /* For the case where the last mvneta_poll did not process all |
c5aff182 TP |
2755 | * RX packets |
2756 | */ | |
2dcf75e2 GC |
2757 | rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); |
2758 | ||
2636ac3c MW |
2759 | cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : |
2760 | port->cause_rx_tx; | |
2dcf75e2 GC |
2761 | |
2762 | if (rx_queue) { | |
2763 | rx_queue = rx_queue - 1; | |
dc35a10f MW |
2764 | if (pp->bm_priv) |
2765 | rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]); | |
2766 | else | |
2767 | rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]); | |
2dcf75e2 GC |
2768 | } |
2769 | ||
d8936657 | 2770 | budget -= rx_done; |
c5aff182 TP |
2771 | |
2772 | if (budget > 0) { | |
2773 | cause_rx_tx = 0; | |
2636ac3c MW |
2774 | napi_complete(napi); |
2775 | ||
2776 | if (pp->neta_armada3700) { | |
2777 | unsigned long flags; | |
2778 | ||
2779 | local_irq_save(flags); | |
2780 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
2781 | MVNETA_RX_INTR_MASK(rxq_number) | | |
2782 | MVNETA_TX_INTR_MASK(txq_number) | | |
2783 | MVNETA_MISCINTR_INTR_MASK); | |
2784 | local_irq_restore(flags); | |
2785 | } else { | |
2786 | enable_percpu_irq(pp->dev->irq, 0); | |
2787 | } | |
c5aff182 TP |
2788 | } |
2789 | ||
2636ac3c MW |
2790 | if (pp->neta_armada3700) |
2791 | pp->cause_rx_tx = cause_rx_tx; | |
2792 | else | |
2793 | port->cause_rx_tx = cause_rx_tx; | |
2794 | ||
c5aff182 TP |
2795 | return rx_done; |
2796 | } | |
2797 | ||
c5aff182 TP |
2798 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
2799 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
2800 | int num) | |
2801 | { | |
c5aff182 TP |
2802 | int i; |
2803 | ||
2804 | for (i = 0; i < num; i++) { | |
a1a65ab1 | 2805 | memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); |
f88bee1c | 2806 | if (mvneta_rx_refill(pp, rxq->descs + i, rxq) != 0) { |
a1a65ab1 | 2807 | netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", |
c5aff182 TP |
2808 | __func__, rxq->id, i, num); |
2809 | break; | |
2810 | } | |
c5aff182 TP |
2811 | } |
2812 | ||
2813 | /* Add this number of RX descriptors as non occupied (ready to | |
6a20c175 TP |
2814 | * get packets) |
2815 | */ | |
c5aff182 TP |
2816 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
2817 | ||
2818 | return i; | |
2819 | } | |
2820 | ||
2821 | /* Free all packets pending transmit from all TXQs and reset TX port */ | |
2822 | static void mvneta_tx_reset(struct mvneta_port *pp) | |
2823 | { | |
2824 | int queue; | |
2825 | ||
9672850b | 2826 | /* free the skb's in the tx ring */ |
c5aff182 TP |
2827 | for (queue = 0; queue < txq_number; queue++) |
2828 | mvneta_txq_done_force(pp, &pp->txqs[queue]); | |
2829 | ||
2830 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
2831 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
2832 | } | |
2833 | ||
2834 | static void mvneta_rx_reset(struct mvneta_port *pp) | |
2835 | { | |
2836 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
2837 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
2838 | } | |
2839 | ||
2840 | /* Rx/Tx queue initialization/cleanup methods */ | |
2841 | ||
2842 | /* Create a specified RX queue */ | |
2843 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
2844 | struct mvneta_rx_queue *rxq) | |
2845 | ||
2846 | { | |
2847 | rxq->size = pp->rx_ring_size; | |
2848 | ||
2849 | /* Allocate memory for RX descriptors */ | |
2850 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2851 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2852 | &rxq->descs_phys, GFP_KERNEL); | |
d0320f75 | 2853 | if (rxq->descs == NULL) |
c5aff182 | 2854 | return -ENOMEM; |
c5aff182 | 2855 | |
c5aff182 TP |
2856 | rxq->last_desc = rxq->size - 1; |
2857 | ||
2858 | /* Set Rx descriptors queue starting address */ | |
2859 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
2860 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
2861 | ||
2862 | /* Set Offset */ | |
8d5047cf | 2863 | mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction); |
c5aff182 TP |
2864 | |
2865 | /* Set coalescing pkts and time */ | |
2866 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
2867 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
2868 | ||
dc35a10f MW |
2869 | if (!pp->bm_priv) { |
2870 | /* Fill RXQ with buffers from RX pool */ | |
2871 | mvneta_rxq_buf_size_set(pp, rxq, | |
2872 | MVNETA_RX_BUF_SIZE(pp->pkt_size)); | |
2873 | mvneta_rxq_bm_disable(pp, rxq); | |
e9f64999 | 2874 | mvneta_rxq_fill(pp, rxq, rxq->size); |
dc35a10f MW |
2875 | } else { |
2876 | mvneta_rxq_bm_enable(pp, rxq); | |
2877 | mvneta_rxq_long_pool_set(pp, rxq); | |
2878 | mvneta_rxq_short_pool_set(pp, rxq); | |
e9f64999 | 2879 | mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); |
dc35a10f MW |
2880 | } |
2881 | ||
c5aff182 TP |
2882 | return 0; |
2883 | } | |
2884 | ||
2885 | /* Cleanup Rx queue */ | |
2886 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
2887 | struct mvneta_rx_queue *rxq) | |
2888 | { | |
2889 | mvneta_rxq_drop_pkts(pp, rxq); | |
2890 | ||
2891 | if (rxq->descs) | |
2892 | dma_free_coherent(pp->dev->dev.parent, | |
2893 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2894 | rxq->descs, | |
2895 | rxq->descs_phys); | |
2896 | ||
2897 | rxq->descs = NULL; | |
2898 | rxq->last_desc = 0; | |
2899 | rxq->next_desc_to_proc = 0; | |
2900 | rxq->descs_phys = 0; | |
2901 | } | |
2902 | ||
2903 | /* Create and initialize a tx queue */ | |
2904 | static int mvneta_txq_init(struct mvneta_port *pp, | |
2905 | struct mvneta_tx_queue *txq) | |
2906 | { | |
50bf8cb6 GC |
2907 | int cpu; |
2908 | ||
c5aff182 TP |
2909 | txq->size = pp->tx_ring_size; |
2910 | ||
8eef5f97 EG |
2911 | /* A queue must always have room for at least one skb. |
2912 | * Therefore, stop the queue when the free entries reaches | |
2913 | * the maximum number of descriptors per skb. | |
2914 | */ | |
2915 | txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; | |
2916 | txq->tx_wake_threshold = txq->tx_stop_threshold / 2; | |
2917 | ||
2918 | ||
c5aff182 TP |
2919 | /* Allocate memory for TX descriptors */ |
2920 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2921 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2922 | &txq->descs_phys, GFP_KERNEL); | |
d0320f75 | 2923 | if (txq->descs == NULL) |
c5aff182 | 2924 | return -ENOMEM; |
c5aff182 | 2925 | |
c5aff182 TP |
2926 | txq->last_desc = txq->size - 1; |
2927 | ||
2928 | /* Set maximum bandwidth for enabled TXQs */ | |
2929 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
2930 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
2931 | ||
2932 | /* Set Tx descriptors queue starting address */ | |
2933 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
2934 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
2935 | ||
2936 | txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); | |
2937 | if (txq->tx_skb == NULL) { | |
2938 | dma_free_coherent(pp->dev->dev.parent, | |
2939 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2940 | txq->descs, txq->descs_phys); | |
2941 | return -ENOMEM; | |
2942 | } | |
2adb719d EG |
2943 | |
2944 | /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ | |
2945 | txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, | |
2946 | txq->size * TSO_HEADER_SIZE, | |
2947 | &txq->tso_hdrs_phys, GFP_KERNEL); | |
2948 | if (txq->tso_hdrs == NULL) { | |
2949 | kfree(txq->tx_skb); | |
2950 | dma_free_coherent(pp->dev->dev.parent, | |
2951 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2952 | txq->descs, txq->descs_phys); | |
2953 | return -ENOMEM; | |
2954 | } | |
c5aff182 TP |
2955 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); |
2956 | ||
50bf8cb6 GC |
2957 | /* Setup XPS mapping */ |
2958 | if (txq_number > 1) | |
2959 | cpu = txq->id % num_present_cpus(); | |
2960 | else | |
2961 | cpu = pp->rxq_def % num_present_cpus(); | |
2962 | cpumask_set_cpu(cpu, &txq->affinity_mask); | |
2963 | netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); | |
2964 | ||
c5aff182 TP |
2965 | return 0; |
2966 | } | |
2967 | ||
2968 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ | |
2969 | static void mvneta_txq_deinit(struct mvneta_port *pp, | |
2970 | struct mvneta_tx_queue *txq) | |
2971 | { | |
a29b6235 MW |
2972 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
2973 | ||
c5aff182 TP |
2974 | kfree(txq->tx_skb); |
2975 | ||
2adb719d EG |
2976 | if (txq->tso_hdrs) |
2977 | dma_free_coherent(pp->dev->dev.parent, | |
2978 | txq->size * TSO_HEADER_SIZE, | |
2979 | txq->tso_hdrs, txq->tso_hdrs_phys); | |
c5aff182 TP |
2980 | if (txq->descs) |
2981 | dma_free_coherent(pp->dev->dev.parent, | |
2982 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2983 | txq->descs, txq->descs_phys); | |
2984 | ||
a29b6235 MW |
2985 | netdev_tx_reset_queue(nq); |
2986 | ||
c5aff182 TP |
2987 | txq->descs = NULL; |
2988 | txq->last_desc = 0; | |
2989 | txq->next_desc_to_proc = 0; | |
2990 | txq->descs_phys = 0; | |
2991 | ||
2992 | /* Set minimum bandwidth for disabled TXQs */ | |
2993 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
2994 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
2995 | ||
2996 | /* Set Tx descriptors queue starting address and size */ | |
2997 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
2998 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
2999 | } | |
3000 | ||
3001 | /* Cleanup all Tx queues */ | |
3002 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
3003 | { | |
3004 | int queue; | |
3005 | ||
3006 | for (queue = 0; queue < txq_number; queue++) | |
3007 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
3008 | } | |
3009 | ||
3010 | /* Cleanup all Rx queues */ | |
3011 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
3012 | { | |
2dcf75e2 GC |
3013 | int queue; |
3014 | ||
3015 | for (queue = 0; queue < txq_number; queue++) | |
3016 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); | |
c5aff182 TP |
3017 | } |
3018 | ||
3019 | ||
3020 | /* Init all Rx queues */ | |
3021 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
3022 | { | |
2dcf75e2 GC |
3023 | int queue; |
3024 | ||
3025 | for (queue = 0; queue < rxq_number; queue++) { | |
3026 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
3027 | ||
3028 | if (err) { | |
3029 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
3030 | __func__, queue); | |
3031 | mvneta_cleanup_rxqs(pp); | |
3032 | return err; | |
3033 | } | |
c5aff182 TP |
3034 | } |
3035 | ||
3036 | return 0; | |
3037 | } | |
3038 | ||
3039 | /* Init all tx queues */ | |
3040 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
3041 | { | |
3042 | int queue; | |
3043 | ||
3044 | for (queue = 0; queue < txq_number; queue++) { | |
3045 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
3046 | if (err) { | |
3047 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
3048 | __func__, queue); | |
3049 | mvneta_cleanup_txqs(pp); | |
3050 | return err; | |
3051 | } | |
3052 | } | |
3053 | ||
3054 | return 0; | |
3055 | } | |
3056 | ||
3057 | static void mvneta_start_dev(struct mvneta_port *pp) | |
3058 | { | |
6b125d63 | 3059 | int cpu; |
c6c022e3 | 3060 | struct net_device *ndev = pp->dev; |
12bb03b4 | 3061 | |
c5aff182 TP |
3062 | mvneta_max_rx_size_set(pp, pp->pkt_size); |
3063 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); | |
3064 | ||
3065 | /* start the Rx/Tx activity */ | |
3066 | mvneta_port_enable(pp); | |
3067 | ||
2636ac3c MW |
3068 | if (!pp->neta_armada3700) { |
3069 | /* Enable polling on the port */ | |
3070 | for_each_online_cpu(cpu) { | |
3071 | struct mvneta_pcpu_port *port = | |
3072 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 3073 | |
2636ac3c MW |
3074 | napi_enable(&port->napi); |
3075 | } | |
3076 | } else { | |
3077 | napi_enable(&pp->napi); | |
12bb03b4 | 3078 | } |
c5aff182 | 3079 | |
2dcf75e2 | 3080 | /* Unmask interrupts. It has to be done from each CPU */ |
6b125d63 GC |
3081 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); |
3082 | ||
898b2970 SS |
3083 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
3084 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
3085 | MVNETA_CAUSE_LINK_CHANGE | | |
3086 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
c5aff182 | 3087 | |
c6c022e3 | 3088 | phy_start(ndev->phydev); |
c5aff182 TP |
3089 | netif_tx_start_all_queues(pp->dev); |
3090 | } | |
3091 | ||
3092 | static void mvneta_stop_dev(struct mvneta_port *pp) | |
3093 | { | |
12bb03b4 | 3094 | unsigned int cpu; |
c6c022e3 | 3095 | struct net_device *ndev = pp->dev; |
12bb03b4 | 3096 | |
c6c022e3 | 3097 | phy_stop(ndev->phydev); |
c5aff182 | 3098 | |
2636ac3c MW |
3099 | if (!pp->neta_armada3700) { |
3100 | for_each_online_cpu(cpu) { | |
3101 | struct mvneta_pcpu_port *port = | |
3102 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 3103 | |
2636ac3c MW |
3104 | napi_disable(&port->napi); |
3105 | } | |
3106 | } else { | |
3107 | napi_disable(&pp->napi); | |
12bb03b4 | 3108 | } |
c5aff182 TP |
3109 | |
3110 | netif_carrier_off(pp->dev); | |
3111 | ||
3112 | mvneta_port_down(pp); | |
3113 | netif_tx_stop_all_queues(pp->dev); | |
3114 | ||
3115 | /* Stop the port activity */ | |
3116 | mvneta_port_disable(pp); | |
3117 | ||
3118 | /* Clear all ethernet port interrupts */ | |
db488c10 | 3119 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
3120 | |
3121 | /* Mask all ethernet port interrupts */ | |
db488c10 | 3122 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
3123 | |
3124 | mvneta_tx_reset(pp); | |
3125 | mvneta_rx_reset(pp); | |
3126 | } | |
3127 | ||
db5dd0db MW |
3128 | static void mvneta_percpu_enable(void *arg) |
3129 | { | |
3130 | struct mvneta_port *pp = arg; | |
3131 | ||
3132 | enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); | |
3133 | } | |
3134 | ||
3135 | static void mvneta_percpu_disable(void *arg) | |
3136 | { | |
3137 | struct mvneta_port *pp = arg; | |
3138 | ||
3139 | disable_percpu_irq(pp->dev->irq); | |
3140 | } | |
3141 | ||
c5aff182 TP |
3142 | /* Change the device mtu */ |
3143 | static int mvneta_change_mtu(struct net_device *dev, int mtu) | |
3144 | { | |
3145 | struct mvneta_port *pp = netdev_priv(dev); | |
3146 | int ret; | |
3147 | ||
5777987e JW |
3148 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { |
3149 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", | |
3150 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); | |
3151 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); | |
3152 | } | |
c5aff182 TP |
3153 | |
3154 | dev->mtu = mtu; | |
3155 | ||
b65657fc | 3156 | if (!netif_running(dev)) { |
dc35a10f MW |
3157 | if (pp->bm_priv) |
3158 | mvneta_bm_update_mtu(pp, mtu); | |
3159 | ||
b65657fc | 3160 | netdev_update_features(dev); |
c5aff182 | 3161 | return 0; |
b65657fc | 3162 | } |
c5aff182 | 3163 | |
6a20c175 | 3164 | /* The interface is running, so we have to force a |
a92dbd96 | 3165 | * reallocation of the queues |
c5aff182 TP |
3166 | */ |
3167 | mvneta_stop_dev(pp); | |
db5dd0db | 3168 | on_each_cpu(mvneta_percpu_disable, pp, true); |
c5aff182 TP |
3169 | |
3170 | mvneta_cleanup_txqs(pp); | |
3171 | mvneta_cleanup_rxqs(pp); | |
3172 | ||
dc35a10f MW |
3173 | if (pp->bm_priv) |
3174 | mvneta_bm_update_mtu(pp, mtu); | |
3175 | ||
a92dbd96 | 3176 | pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); |
8ec2cd48 | 3177 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
3178 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
3179 | |
3180 | ret = mvneta_setup_rxqs(pp); | |
3181 | if (ret) { | |
a92dbd96 | 3182 | netdev_err(dev, "unable to setup rxqs after MTU change\n"); |
c5aff182 TP |
3183 | return ret; |
3184 | } | |
3185 | ||
a92dbd96 EG |
3186 | ret = mvneta_setup_txqs(pp); |
3187 | if (ret) { | |
3188 | netdev_err(dev, "unable to setup txqs after MTU change\n"); | |
3189 | return ret; | |
3190 | } | |
c5aff182 | 3191 | |
db5dd0db | 3192 | on_each_cpu(mvneta_percpu_enable, pp, true); |
c5aff182 TP |
3193 | mvneta_start_dev(pp); |
3194 | mvneta_port_up(pp); | |
3195 | ||
b65657fc SG |
3196 | netdev_update_features(dev); |
3197 | ||
c5aff182 TP |
3198 | return 0; |
3199 | } | |
3200 | ||
b65657fc SG |
3201 | static netdev_features_t mvneta_fix_features(struct net_device *dev, |
3202 | netdev_features_t features) | |
3203 | { | |
3204 | struct mvneta_port *pp = netdev_priv(dev); | |
3205 | ||
3206 | if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { | |
3207 | features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); | |
3208 | netdev_info(dev, | |
3209 | "Disable IP checksum for MTU greater than %dB\n", | |
3210 | pp->tx_csum_limit); | |
3211 | } | |
3212 | ||
3213 | return features; | |
3214 | } | |
3215 | ||
8cc3e439 TP |
3216 | /* Get mac address */ |
3217 | static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) | |
3218 | { | |
3219 | u32 mac_addr_l, mac_addr_h; | |
3220 | ||
3221 | mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); | |
3222 | mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); | |
3223 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
3224 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
3225 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
3226 | addr[3] = mac_addr_h & 0xFF; | |
3227 | addr[4] = (mac_addr_l >> 8) & 0xFF; | |
3228 | addr[5] = mac_addr_l & 0xFF; | |
3229 | } | |
3230 | ||
c5aff182 TP |
3231 | /* Handle setting mac address */ |
3232 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) | |
3233 | { | |
3234 | struct mvneta_port *pp = netdev_priv(dev); | |
e68de360 EG |
3235 | struct sockaddr *sockaddr = addr; |
3236 | int ret; | |
c5aff182 | 3237 | |
e68de360 EG |
3238 | ret = eth_prepare_mac_addr_change(dev, addr); |
3239 | if (ret < 0) | |
3240 | return ret; | |
c5aff182 TP |
3241 | /* Remove previous address table entry */ |
3242 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); | |
3243 | ||
3244 | /* Set new addr in hw */ | |
90b74c01 | 3245 | mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); |
c5aff182 | 3246 | |
e68de360 | 3247 | eth_commit_mac_addr_change(dev, addr); |
c5aff182 TP |
3248 | return 0; |
3249 | } | |
3250 | ||
3251 | static void mvneta_adjust_link(struct net_device *ndev) | |
3252 | { | |
3253 | struct mvneta_port *pp = netdev_priv(ndev); | |
c6c022e3 | 3254 | struct phy_device *phydev = ndev->phydev; |
c5aff182 TP |
3255 | int status_change = 0; |
3256 | ||
3257 | if (phydev->link) { | |
3258 | if ((pp->speed != phydev->speed) || | |
3259 | (pp->duplex != phydev->duplex)) { | |
3260 | u32 val; | |
3261 | ||
3262 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
3263 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
3264 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
898b2970 | 3265 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); |
c5aff182 TP |
3266 | |
3267 | if (phydev->duplex) | |
3268 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
3269 | ||
3270 | if (phydev->speed == SPEED_1000) | |
3271 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
4d12bc63 | 3272 | else if (phydev->speed == SPEED_100) |
c5aff182 TP |
3273 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; |
3274 | ||
3275 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
3276 | ||
3277 | pp->duplex = phydev->duplex; | |
3278 | pp->speed = phydev->speed; | |
3279 | } | |
3280 | } | |
3281 | ||
3282 | if (phydev->link != pp->link) { | |
3283 | if (!phydev->link) { | |
3284 | pp->duplex = -1; | |
3285 | pp->speed = 0; | |
3286 | } | |
3287 | ||
3288 | pp->link = phydev->link; | |
3289 | status_change = 1; | |
3290 | } | |
3291 | ||
3292 | if (status_change) { | |
3293 | if (phydev->link) { | |
898b2970 SS |
3294 | if (!pp->use_inband_status) { |
3295 | u32 val = mvreg_read(pp, | |
3296 | MVNETA_GMAC_AUTONEG_CONFIG); | |
3297 | val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; | |
3298 | val |= MVNETA_GMAC_FORCE_LINK_PASS; | |
3299 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3300 | val); | |
3301 | } | |
c5aff182 | 3302 | mvneta_port_up(pp); |
c5aff182 | 3303 | } else { |
898b2970 SS |
3304 | if (!pp->use_inband_status) { |
3305 | u32 val = mvreg_read(pp, | |
3306 | MVNETA_GMAC_AUTONEG_CONFIG); | |
3307 | val &= ~MVNETA_GMAC_FORCE_LINK_PASS; | |
3308 | val |= MVNETA_GMAC_FORCE_LINK_DOWN; | |
3309 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3310 | val); | |
3311 | } | |
c5aff182 | 3312 | mvneta_port_down(pp); |
c5aff182 | 3313 | } |
0089b745 | 3314 | phy_print_status(phydev); |
c5aff182 TP |
3315 | } |
3316 | } | |
3317 | ||
3318 | static int mvneta_mdio_probe(struct mvneta_port *pp) | |
3319 | { | |
3320 | struct phy_device *phy_dev; | |
3321 | ||
3322 | phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, | |
3323 | pp->phy_interface); | |
3324 | if (!phy_dev) { | |
3325 | netdev_err(pp->dev, "could not find the PHY\n"); | |
3326 | return -ENODEV; | |
3327 | } | |
3328 | ||
3329 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
3330 | phy_dev->advertising = phy_dev->supported; | |
3331 | ||
c5aff182 TP |
3332 | pp->link = 0; |
3333 | pp->duplex = 0; | |
3334 | pp->speed = 0; | |
3335 | ||
3336 | return 0; | |
3337 | } | |
3338 | ||
3339 | static void mvneta_mdio_remove(struct mvneta_port *pp) | |
3340 | { | |
c6c022e3 PR |
3341 | struct net_device *ndev = pp->dev; |
3342 | ||
3343 | phy_disconnect(ndev->phydev); | |
c5aff182 TP |
3344 | } |
3345 | ||
120cfa50 GC |
3346 | /* Electing a CPU must be done in an atomic way: it should be done |
3347 | * after or before the removal/insertion of a CPU and this function is | |
3348 | * not reentrant. | |
3349 | */ | |
f8642885 MR |
3350 | static void mvneta_percpu_elect(struct mvneta_port *pp) |
3351 | { | |
cad5d847 GC |
3352 | int elected_cpu = 0, max_cpu, cpu, i = 0; |
3353 | ||
3354 | /* Use the cpu associated to the rxq when it is online, in all | |
3355 | * the other cases, use the cpu 0 which can't be offline. | |
3356 | */ | |
3357 | if (cpu_online(pp->rxq_def)) | |
3358 | elected_cpu = pp->rxq_def; | |
f8642885 | 3359 | |
2dcf75e2 | 3360 | max_cpu = num_present_cpus(); |
f8642885 MR |
3361 | |
3362 | for_each_online_cpu(cpu) { | |
2dcf75e2 GC |
3363 | int rxq_map = 0, txq_map = 0; |
3364 | int rxq; | |
3365 | ||
3366 | for (rxq = 0; rxq < rxq_number; rxq++) | |
3367 | if ((rxq % max_cpu) == cpu) | |
3368 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
3369 | ||
cad5d847 | 3370 | if (cpu == elected_cpu) |
50bf8cb6 GC |
3371 | /* Map the default receive queue queue to the |
3372 | * elected CPU | |
f8642885 | 3373 | */ |
2dcf75e2 | 3374 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); |
50bf8cb6 GC |
3375 | |
3376 | /* We update the TX queue map only if we have one | |
3377 | * queue. In this case we associate the TX queue to | |
3378 | * the CPU bound to the default RX queue | |
3379 | */ | |
3380 | if (txq_number == 1) | |
cad5d847 | 3381 | txq_map = (cpu == elected_cpu) ? |
50bf8cb6 GC |
3382 | MVNETA_CPU_TXQ_ACCESS(1) : 0; |
3383 | else | |
3384 | txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & | |
3385 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
3386 | ||
2dcf75e2 GC |
3387 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); |
3388 | ||
3389 | /* Update the interrupt mask on each CPU according the | |
3390 | * new mapping | |
3391 | */ | |
3392 | smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, | |
3393 | pp, true); | |
f8642885 | 3394 | i++; |
2dcf75e2 | 3395 | |
f8642885 MR |
3396 | } |
3397 | }; | |
3398 | ||
84a3f4db | 3399 | static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) |
f8642885 | 3400 | { |
84a3f4db SAS |
3401 | int other_cpu; |
3402 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
3403 | node_online); | |
f8642885 MR |
3404 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
3405 | ||
f8642885 | 3406 | |
84a3f4db SAS |
3407 | spin_lock(&pp->lock); |
3408 | /* | |
3409 | * Configuring the driver for a new CPU while the driver is | |
3410 | * stopping is racy, so just avoid it. | |
3411 | */ | |
3412 | if (pp->is_stopped) { | |
3413 | spin_unlock(&pp->lock); | |
3414 | return 0; | |
3415 | } | |
3416 | netif_tx_stop_all_queues(pp->dev); | |
f8642885 | 3417 | |
84a3f4db SAS |
3418 | /* |
3419 | * We have to synchronise on tha napi of each CPU except the one | |
3420 | * just being woken up | |
3421 | */ | |
3422 | for_each_online_cpu(other_cpu) { | |
3423 | if (other_cpu != cpu) { | |
3424 | struct mvneta_pcpu_port *other_port = | |
3425 | per_cpu_ptr(pp->ports, other_cpu); | |
3426 | ||
3427 | napi_synchronize(&other_port->napi); | |
f8642885 | 3428 | } |
84a3f4db | 3429 | } |
f8642885 | 3430 | |
84a3f4db SAS |
3431 | /* Mask all ethernet port interrupts */ |
3432 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); | |
3433 | napi_enable(&port->napi); | |
f8642885 | 3434 | |
84a3f4db SAS |
3435 | /* |
3436 | * Enable per-CPU interrupts on the CPU that is | |
3437 | * brought up. | |
3438 | */ | |
3439 | mvneta_percpu_enable(pp); | |
2dcf75e2 | 3440 | |
84a3f4db SAS |
3441 | /* |
3442 | * Enable per-CPU interrupt on the one CPU we care | |
3443 | * about. | |
3444 | */ | |
3445 | mvneta_percpu_elect(pp); | |
2dcf75e2 | 3446 | |
84a3f4db SAS |
3447 | /* Unmask all ethernet port interrupts */ |
3448 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
3449 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
3450 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
3451 | MVNETA_CAUSE_LINK_CHANGE | | |
3452 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
3453 | netif_tx_start_all_queues(pp->dev); | |
3454 | spin_unlock(&pp->lock); | |
3455 | return 0; | |
3456 | } | |
f8642885 | 3457 | |
84a3f4db SAS |
3458 | static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) |
3459 | { | |
3460 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
3461 | node_online); | |
3462 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
f8642885 | 3463 | |
84a3f4db SAS |
3464 | /* |
3465 | * Thanks to this lock we are sure that any pending cpu election is | |
3466 | * done. | |
3467 | */ | |
3468 | spin_lock(&pp->lock); | |
3469 | /* Mask all ethernet port interrupts */ | |
3470 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); | |
3471 | spin_unlock(&pp->lock); | |
f8642885 | 3472 | |
84a3f4db SAS |
3473 | napi_synchronize(&port->napi); |
3474 | napi_disable(&port->napi); | |
3475 | /* Disable per-CPU interrupts on the CPU that is brought down. */ | |
3476 | mvneta_percpu_disable(pp); | |
3477 | return 0; | |
3478 | } | |
3479 | ||
3480 | static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) | |
3481 | { | |
3482 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
3483 | node_dead); | |
3484 | ||
3485 | /* Check if a new CPU must be elected now this on is down */ | |
3486 | spin_lock(&pp->lock); | |
3487 | mvneta_percpu_elect(pp); | |
3488 | spin_unlock(&pp->lock); | |
3489 | /* Unmask all ethernet port interrupts */ | |
3490 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
3491 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
3492 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
3493 | MVNETA_CAUSE_LINK_CHANGE | | |
3494 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
3495 | netif_tx_start_all_queues(pp->dev); | |
3496 | return 0; | |
f8642885 MR |
3497 | } |
3498 | ||
c5aff182 TP |
3499 | static int mvneta_open(struct net_device *dev) |
3500 | { | |
3501 | struct mvneta_port *pp = netdev_priv(dev); | |
6b125d63 | 3502 | int ret; |
c5aff182 | 3503 | |
c5aff182 | 3504 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
8ec2cd48 | 3505 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
3506 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
3507 | |
3508 | ret = mvneta_setup_rxqs(pp); | |
3509 | if (ret) | |
3510 | return ret; | |
3511 | ||
3512 | ret = mvneta_setup_txqs(pp); | |
3513 | if (ret) | |
3514 | goto err_cleanup_rxqs; | |
3515 | ||
3516 | /* Connect to port interrupt line */ | |
2636ac3c MW |
3517 | if (pp->neta_armada3700) |
3518 | ret = request_irq(pp->dev->irq, mvneta_isr, 0, | |
3519 | dev->name, pp); | |
3520 | else | |
3521 | ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, | |
3522 | dev->name, pp->ports); | |
c5aff182 TP |
3523 | if (ret) { |
3524 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); | |
3525 | goto err_cleanup_txqs; | |
3526 | } | |
3527 | ||
2636ac3c MW |
3528 | if (!pp->neta_armada3700) { |
3529 | /* Enable per-CPU interrupt on all the CPU to handle our RX | |
3530 | * queue interrupts | |
3531 | */ | |
3532 | on_each_cpu(mvneta_percpu_enable, pp, true); | |
2dcf75e2 | 3533 | |
2636ac3c MW |
3534 | pp->is_stopped = false; |
3535 | /* Register a CPU notifier to handle the case where our CPU | |
3536 | * might be taken offline. | |
3537 | */ | |
3538 | ret = cpuhp_state_add_instance_nocalls(online_hpstate, | |
3539 | &pp->node_online); | |
3540 | if (ret) | |
3541 | goto err_free_irq; | |
84a3f4db | 3542 | |
2636ac3c MW |
3543 | ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, |
3544 | &pp->node_dead); | |
3545 | if (ret) | |
3546 | goto err_free_online_hp; | |
3547 | } | |
f8642885 | 3548 | |
c5aff182 TP |
3549 | /* In default link is down */ |
3550 | netif_carrier_off(pp->dev); | |
3551 | ||
3552 | ret = mvneta_mdio_probe(pp); | |
3553 | if (ret < 0) { | |
3554 | netdev_err(dev, "cannot probe MDIO bus\n"); | |
84a3f4db | 3555 | goto err_free_dead_hp; |
c5aff182 TP |
3556 | } |
3557 | ||
3558 | mvneta_start_dev(pp); | |
3559 | ||
3560 | return 0; | |
3561 | ||
84a3f4db | 3562 | err_free_dead_hp: |
2636ac3c MW |
3563 | if (!pp->neta_armada3700) |
3564 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
3565 | &pp->node_dead); | |
84a3f4db | 3566 | err_free_online_hp: |
2636ac3c MW |
3567 | if (!pp->neta_armada3700) |
3568 | cpuhp_state_remove_instance_nocalls(online_hpstate, | |
3569 | &pp->node_online); | |
c5aff182 | 3570 | err_free_irq: |
2636ac3c MW |
3571 | if (pp->neta_armada3700) { |
3572 | free_irq(pp->dev->irq, pp); | |
3573 | } else { | |
3574 | on_each_cpu(mvneta_percpu_disable, pp, true); | |
3575 | free_percpu_irq(pp->dev->irq, pp->ports); | |
3576 | } | |
c5aff182 TP |
3577 | err_cleanup_txqs: |
3578 | mvneta_cleanup_txqs(pp); | |
3579 | err_cleanup_rxqs: | |
3580 | mvneta_cleanup_rxqs(pp); | |
3581 | return ret; | |
3582 | } | |
3583 | ||
3584 | /* Stop the port, free port interrupt line */ | |
3585 | static int mvneta_stop(struct net_device *dev) | |
3586 | { | |
3587 | struct mvneta_port *pp = netdev_priv(dev); | |
3588 | ||
2636ac3c MW |
3589 | if (!pp->neta_armada3700) { |
3590 | /* Inform that we are stopping so we don't want to setup the | |
3591 | * driver for new CPUs in the notifiers. The code of the | |
3592 | * notifier for CPU online is protected by the same spinlock, | |
3593 | * so when we get the lock, the notifer work is done. | |
3594 | */ | |
3595 | spin_lock(&pp->lock); | |
3596 | pp->is_stopped = true; | |
3597 | spin_unlock(&pp->lock); | |
1c2722a9 | 3598 | |
2636ac3c MW |
3599 | mvneta_stop_dev(pp); |
3600 | mvneta_mdio_remove(pp); | |
84a3f4db | 3601 | |
d26aac2d DC |
3602 | cpuhp_state_remove_instance_nocalls(online_hpstate, |
3603 | &pp->node_online); | |
3604 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
3605 | &pp->node_dead); | |
2636ac3c MW |
3606 | on_each_cpu(mvneta_percpu_disable, pp, true); |
3607 | free_percpu_irq(dev->irq, pp->ports); | |
3608 | } else { | |
3609 | mvneta_stop_dev(pp); | |
3610 | mvneta_mdio_remove(pp); | |
3611 | free_irq(dev->irq, pp); | |
3612 | } | |
3613 | ||
c5aff182 TP |
3614 | mvneta_cleanup_rxqs(pp); |
3615 | mvneta_cleanup_txqs(pp); | |
c5aff182 TP |
3616 | |
3617 | return 0; | |
3618 | } | |
3619 | ||
15f59456 TP |
3620 | static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3621 | { | |
c6c022e3 | 3622 | if (!dev->phydev) |
15f59456 TP |
3623 | return -ENOTSUPP; |
3624 | ||
c6c022e3 | 3625 | return phy_mii_ioctl(dev->phydev, ifr, cmd); |
15f59456 TP |
3626 | } |
3627 | ||
c5aff182 TP |
3628 | /* Ethtool methods */ |
3629 | ||
013ad40d | 3630 | /* Set link ksettings (phy address, speed) for ethtools */ |
2dc0d2b4 BX |
3631 | static int |
3632 | mvneta_ethtool_set_link_ksettings(struct net_device *ndev, | |
3633 | const struct ethtool_link_ksettings *cmd) | |
c5aff182 | 3634 | { |
013ad40d PR |
3635 | struct mvneta_port *pp = netdev_priv(ndev); |
3636 | struct phy_device *phydev = ndev->phydev; | |
c5aff182 | 3637 | |
0c0744fc | 3638 | if (!phydev) |
c5aff182 TP |
3639 | return -ENODEV; |
3640 | ||
013ad40d | 3641 | if ((cmd->base.autoneg == AUTONEG_ENABLE) != pp->use_inband_status) { |
0c0744fc SS |
3642 | u32 val; |
3643 | ||
013ad40d | 3644 | mvneta_set_autoneg(pp, cmd->base.autoneg == AUTONEG_ENABLE); |
0c0744fc | 3645 | |
013ad40d | 3646 | if (cmd->base.autoneg == AUTONEG_DISABLE) { |
0c0744fc SS |
3647 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
3648 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
3649 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
3650 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); | |
3651 | ||
3652 | if (phydev->duplex) | |
3653 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
3654 | ||
3655 | if (phydev->speed == SPEED_1000) | |
3656 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
3657 | else if (phydev->speed == SPEED_100) | |
3658 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; | |
3659 | ||
3660 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
3661 | } | |
3662 | ||
013ad40d | 3663 | pp->use_inband_status = (cmd->base.autoneg == AUTONEG_ENABLE); |
0c0744fc SS |
3664 | netdev_info(pp->dev, "autoneg status set to %i\n", |
3665 | pp->use_inband_status); | |
3666 | ||
013ad40d | 3667 | if (netif_running(ndev)) { |
0c0744fc SS |
3668 | mvneta_port_down(pp); |
3669 | mvneta_port_up(pp); | |
3670 | } | |
3671 | } | |
3672 | ||
013ad40d | 3673 | return phy_ethtool_ksettings_set(ndev->phydev, cmd); |
c5aff182 TP |
3674 | } |
3675 | ||
3676 | /* Set interrupt coalescing for ethtools */ | |
3677 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, | |
3678 | struct ethtool_coalesce *c) | |
3679 | { | |
3680 | struct mvneta_port *pp = netdev_priv(dev); | |
3681 | int queue; | |
3682 | ||
3683 | for (queue = 0; queue < rxq_number; queue++) { | |
3684 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
3685 | rxq->time_coal = c->rx_coalesce_usecs; | |
3686 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
3687 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
3688 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
3689 | } | |
3690 | ||
3691 | for (queue = 0; queue < txq_number; queue++) { | |
3692 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
3693 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
3694 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
3695 | } | |
3696 | ||
3697 | return 0; | |
3698 | } | |
3699 | ||
3700 | /* get coalescing for ethtools */ | |
3701 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, | |
3702 | struct ethtool_coalesce *c) | |
3703 | { | |
3704 | struct mvneta_port *pp = netdev_priv(dev); | |
3705 | ||
3706 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; | |
3707 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; | |
3708 | ||
3709 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; | |
3710 | return 0; | |
3711 | } | |
3712 | ||
3713 | ||
3714 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, | |
3715 | struct ethtool_drvinfo *drvinfo) | |
3716 | { | |
3717 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, | |
3718 | sizeof(drvinfo->driver)); | |
3719 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, | |
3720 | sizeof(drvinfo->version)); | |
3721 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
3722 | sizeof(drvinfo->bus_info)); | |
3723 | } | |
3724 | ||
3725 | ||
3726 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, | |
3727 | struct ethtool_ringparam *ring) | |
3728 | { | |
3729 | struct mvneta_port *pp = netdev_priv(netdev); | |
3730 | ||
3731 | ring->rx_max_pending = MVNETA_MAX_RXD; | |
3732 | ring->tx_max_pending = MVNETA_MAX_TXD; | |
3733 | ring->rx_pending = pp->rx_ring_size; | |
3734 | ring->tx_pending = pp->tx_ring_size; | |
3735 | } | |
3736 | ||
3737 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, | |
3738 | struct ethtool_ringparam *ring) | |
3739 | { | |
3740 | struct mvneta_port *pp = netdev_priv(dev); | |
3741 | ||
3742 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) | |
3743 | return -EINVAL; | |
3744 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? | |
3745 | ring->rx_pending : MVNETA_MAX_RXD; | |
8eef5f97 EG |
3746 | |
3747 | pp->tx_ring_size = clamp_t(u16, ring->tx_pending, | |
3748 | MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); | |
3749 | if (pp->tx_ring_size != ring->tx_pending) | |
3750 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", | |
3751 | pp->tx_ring_size, ring->tx_pending); | |
c5aff182 TP |
3752 | |
3753 | if (netif_running(dev)) { | |
3754 | mvneta_stop(dev); | |
3755 | if (mvneta_open(dev)) { | |
3756 | netdev_err(dev, | |
3757 | "error on opening device after ring param change\n"); | |
3758 | return -ENOMEM; | |
3759 | } | |
3760 | } | |
3761 | ||
3762 | return 0; | |
3763 | } | |
3764 | ||
9b0cdefa RK |
3765 | static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, |
3766 | u8 *data) | |
3767 | { | |
3768 | if (sset == ETH_SS_STATS) { | |
3769 | int i; | |
3770 | ||
3771 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
3772 | memcpy(data + i * ETH_GSTRING_LEN, | |
3773 | mvneta_statistics[i].name, ETH_GSTRING_LEN); | |
3774 | } | |
3775 | } | |
3776 | ||
3777 | static void mvneta_ethtool_update_stats(struct mvneta_port *pp) | |
3778 | { | |
3779 | const struct mvneta_statistic *s; | |
3780 | void __iomem *base = pp->base; | |
3781 | u32 high, low, val; | |
2c832293 | 3782 | u64 val64; |
9b0cdefa RK |
3783 | int i; |
3784 | ||
3785 | for (i = 0, s = mvneta_statistics; | |
3786 | s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); | |
3787 | s++, i++) { | |
9b0cdefa RK |
3788 | switch (s->type) { |
3789 | case T_REG_32: | |
3790 | val = readl_relaxed(base + s->offset); | |
2c832293 | 3791 | pp->ethtool_stats[i] += val; |
9b0cdefa RK |
3792 | break; |
3793 | case T_REG_64: | |
3794 | /* Docs say to read low 32-bit then high */ | |
3795 | low = readl_relaxed(base + s->offset); | |
3796 | high = readl_relaxed(base + s->offset + 4); | |
2c832293 JZ |
3797 | val64 = (u64)high << 32 | low; |
3798 | pp->ethtool_stats[i] += val64; | |
9b0cdefa RK |
3799 | break; |
3800 | } | |
9b0cdefa RK |
3801 | } |
3802 | } | |
3803 | ||
3804 | static void mvneta_ethtool_get_stats(struct net_device *dev, | |
3805 | struct ethtool_stats *stats, u64 *data) | |
3806 | { | |
3807 | struct mvneta_port *pp = netdev_priv(dev); | |
3808 | int i; | |
3809 | ||
3810 | mvneta_ethtool_update_stats(pp); | |
3811 | ||
3812 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
3813 | *data++ = pp->ethtool_stats[i]; | |
3814 | } | |
3815 | ||
3816 | static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) | |
3817 | { | |
3818 | if (sset == ETH_SS_STATS) | |
3819 | return ARRAY_SIZE(mvneta_statistics); | |
3820 | return -EOPNOTSUPP; | |
3821 | } | |
3822 | ||
9a401dea GC |
3823 | static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) |
3824 | { | |
3825 | return MVNETA_RSS_LU_TABLE_SIZE; | |
3826 | } | |
3827 | ||
3828 | static int mvneta_ethtool_get_rxnfc(struct net_device *dev, | |
3829 | struct ethtool_rxnfc *info, | |
3830 | u32 *rules __always_unused) | |
3831 | { | |
3832 | switch (info->cmd) { | |
3833 | case ETHTOOL_GRXRINGS: | |
3834 | info->data = rxq_number; | |
3835 | return 0; | |
3836 | case ETHTOOL_GRXFH: | |
3837 | return -EOPNOTSUPP; | |
3838 | default: | |
3839 | return -EOPNOTSUPP; | |
3840 | } | |
3841 | } | |
3842 | ||
3843 | static int mvneta_config_rss(struct mvneta_port *pp) | |
3844 | { | |
3845 | int cpu; | |
3846 | u32 val; | |
3847 | ||
3848 | netif_tx_stop_all_queues(pp->dev); | |
3849 | ||
6b125d63 | 3850 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
9a401dea GC |
3851 | |
3852 | /* We have to synchronise on the napi of each CPU */ | |
3853 | for_each_online_cpu(cpu) { | |
3854 | struct mvneta_pcpu_port *pcpu_port = | |
3855 | per_cpu_ptr(pp->ports, cpu); | |
3856 | ||
3857 | napi_synchronize(&pcpu_port->napi); | |
3858 | napi_disable(&pcpu_port->napi); | |
3859 | } | |
3860 | ||
3861 | pp->rxq_def = pp->indir[0]; | |
3862 | ||
3863 | /* Update unicast mapping */ | |
3864 | mvneta_set_rx_mode(pp->dev); | |
3865 | ||
3866 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
3867 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); | |
3868 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
3869 | ||
3870 | /* Update the elected CPU matching the new rxq_def */ | |
120cfa50 | 3871 | spin_lock(&pp->lock); |
9a401dea | 3872 | mvneta_percpu_elect(pp); |
120cfa50 | 3873 | spin_unlock(&pp->lock); |
9a401dea GC |
3874 | |
3875 | /* We have to synchronise on the napi of each CPU */ | |
3876 | for_each_online_cpu(cpu) { | |
3877 | struct mvneta_pcpu_port *pcpu_port = | |
3878 | per_cpu_ptr(pp->ports, cpu); | |
3879 | ||
3880 | napi_enable(&pcpu_port->napi); | |
3881 | } | |
3882 | ||
3883 | netif_tx_start_all_queues(pp->dev); | |
3884 | ||
3885 | return 0; | |
3886 | } | |
3887 | ||
3888 | static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, | |
3889 | const u8 *key, const u8 hfunc) | |
3890 | { | |
3891 | struct mvneta_port *pp = netdev_priv(dev); | |
2636ac3c MW |
3892 | |
3893 | /* Current code for Armada 3700 doesn't support RSS features yet */ | |
3894 | if (pp->neta_armada3700) | |
3895 | return -EOPNOTSUPP; | |
3896 | ||
9a401dea GC |
3897 | /* We require at least one supported parameter to be changed |
3898 | * and no change in any of the unsupported parameters | |
3899 | */ | |
3900 | if (key || | |
3901 | (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) | |
3902 | return -EOPNOTSUPP; | |
3903 | ||
3904 | if (!indir) | |
3905 | return 0; | |
3906 | ||
3907 | memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); | |
3908 | ||
3909 | return mvneta_config_rss(pp); | |
3910 | } | |
3911 | ||
3912 | static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, | |
3913 | u8 *hfunc) | |
3914 | { | |
3915 | struct mvneta_port *pp = netdev_priv(dev); | |
3916 | ||
2636ac3c MW |
3917 | /* Current code for Armada 3700 doesn't support RSS features yet */ |
3918 | if (pp->neta_armada3700) | |
3919 | return -EOPNOTSUPP; | |
3920 | ||
9a401dea GC |
3921 | if (hfunc) |
3922 | *hfunc = ETH_RSS_HASH_TOP; | |
3923 | ||
3924 | if (!indir) | |
3925 | return 0; | |
3926 | ||
3927 | memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); | |
3928 | ||
3929 | return 0; | |
3930 | } | |
3931 | ||
c5aff182 TP |
3932 | static const struct net_device_ops mvneta_netdev_ops = { |
3933 | .ndo_open = mvneta_open, | |
3934 | .ndo_stop = mvneta_stop, | |
3935 | .ndo_start_xmit = mvneta_tx, | |
3936 | .ndo_set_rx_mode = mvneta_set_rx_mode, | |
3937 | .ndo_set_mac_address = mvneta_set_mac_addr, | |
3938 | .ndo_change_mtu = mvneta_change_mtu, | |
b65657fc | 3939 | .ndo_fix_features = mvneta_fix_features, |
c5aff182 | 3940 | .ndo_get_stats64 = mvneta_get_stats64, |
15f59456 | 3941 | .ndo_do_ioctl = mvneta_ioctl, |
c5aff182 TP |
3942 | }; |
3943 | ||
3944 | const struct ethtool_ops mvneta_eth_tool_ops = { | |
5489ee89 | 3945 | .nway_reset = phy_ethtool_nway_reset, |
c5aff182 | 3946 | .get_link = ethtool_op_get_link, |
c5aff182 TP |
3947 | .set_coalesce = mvneta_ethtool_set_coalesce, |
3948 | .get_coalesce = mvneta_ethtool_get_coalesce, | |
3949 | .get_drvinfo = mvneta_ethtool_get_drvinfo, | |
3950 | .get_ringparam = mvneta_ethtool_get_ringparam, | |
3951 | .set_ringparam = mvneta_ethtool_set_ringparam, | |
9b0cdefa RK |
3952 | .get_strings = mvneta_ethtool_get_strings, |
3953 | .get_ethtool_stats = mvneta_ethtool_get_stats, | |
3954 | .get_sset_count = mvneta_ethtool_get_sset_count, | |
9a401dea GC |
3955 | .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, |
3956 | .get_rxnfc = mvneta_ethtool_get_rxnfc, | |
3957 | .get_rxfh = mvneta_ethtool_get_rxfh, | |
3958 | .set_rxfh = mvneta_ethtool_set_rxfh, | |
013ad40d PR |
3959 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
3960 | .set_link_ksettings = mvneta_ethtool_set_link_ksettings, | |
c5aff182 TP |
3961 | }; |
3962 | ||
3963 | /* Initialize hw */ | |
9672850b | 3964 | static int mvneta_init(struct device *dev, struct mvneta_port *pp) |
c5aff182 TP |
3965 | { |
3966 | int queue; | |
3967 | ||
3968 | /* Disable port */ | |
3969 | mvneta_port_disable(pp); | |
3970 | ||
3971 | /* Set port default values */ | |
3972 | mvneta_defaults_set(pp); | |
3973 | ||
9672850b EG |
3974 | pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue), |
3975 | GFP_KERNEL); | |
c5aff182 TP |
3976 | if (!pp->txqs) |
3977 | return -ENOMEM; | |
3978 | ||
3979 | /* Initialize TX descriptor rings */ | |
3980 | for (queue = 0; queue < txq_number; queue++) { | |
3981 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
3982 | txq->id = queue; | |
3983 | txq->size = pp->tx_ring_size; | |
3984 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; | |
3985 | } | |
3986 | ||
9672850b EG |
3987 | pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue), |
3988 | GFP_KERNEL); | |
3989 | if (!pp->rxqs) | |
c5aff182 | 3990 | return -ENOMEM; |
c5aff182 TP |
3991 | |
3992 | /* Create Rx descriptor rings */ | |
3993 | for (queue = 0; queue < rxq_number; queue++) { | |
3994 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
3995 | rxq->id = queue; | |
3996 | rxq->size = pp->rx_ring_size; | |
3997 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; | |
3998 | rxq->time_coal = MVNETA_RX_COAL_USEC; | |
f88bee1c GC |
3999 | rxq->buf_virt_addr = devm_kmalloc(pp->dev->dev.parent, |
4000 | rxq->size * sizeof(void *), | |
4001 | GFP_KERNEL); | |
4002 | if (!rxq->buf_virt_addr) | |
4003 | return -ENOMEM; | |
c5aff182 TP |
4004 | } |
4005 | ||
4006 | return 0; | |
4007 | } | |
4008 | ||
c5aff182 | 4009 | /* platform glue : initialize decoding windows */ |
03ce758e GK |
4010 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
4011 | const struct mbus_dram_target_info *dram) | |
c5aff182 TP |
4012 | { |
4013 | u32 win_enable; | |
4014 | u32 win_protect; | |
4015 | int i; | |
4016 | ||
4017 | for (i = 0; i < 6; i++) { | |
4018 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
4019 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
4020 | ||
4021 | if (i < 4) | |
4022 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
4023 | } | |
4024 | ||
4025 | win_enable = 0x3f; | |
4026 | win_protect = 0; | |
4027 | ||
2636ac3c MW |
4028 | if (dram) { |
4029 | for (i = 0; i < dram->num_cs; i++) { | |
4030 | const struct mbus_dram_window *cs = dram->cs + i; | |
4031 | ||
4032 | mvreg_write(pp, MVNETA_WIN_BASE(i), | |
4033 | (cs->base & 0xffff0000) | | |
4034 | (cs->mbus_attr << 8) | | |
4035 | dram->mbus_dram_target_id); | |
c5aff182 | 4036 | |
2636ac3c MW |
4037 | mvreg_write(pp, MVNETA_WIN_SIZE(i), |
4038 | (cs->size - 1) & 0xffff0000); | |
c5aff182 | 4039 | |
2636ac3c MW |
4040 | win_enable &= ~(1 << i); |
4041 | win_protect |= 3 << (2 * i); | |
4042 | } | |
4043 | } else { | |
4044 | /* For Armada3700 open default 4GB Mbus window, leaving | |
4045 | * arbitration of target/attribute to a different layer | |
4046 | * of configuration. | |
4047 | */ | |
4048 | mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); | |
4049 | win_enable &= ~BIT(0); | |
4050 | win_protect = 3; | |
c5aff182 TP |
4051 | } |
4052 | ||
4053 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
db6ba9a5 | 4054 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); |
c5aff182 TP |
4055 | } |
4056 | ||
4057 | /* Power up the port */ | |
3f1dd4bc | 4058 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
c5aff182 | 4059 | { |
3f1dd4bc | 4060 | u32 ctrl; |
c5aff182 TP |
4061 | |
4062 | /* MAC Cause register should be cleared */ | |
4063 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
4064 | ||
3f1dd4bc | 4065 | ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
c5aff182 | 4066 | |
3f1dd4bc TP |
4067 | /* Even though it might look weird, when we're configured in |
4068 | * SGMII or QSGMII mode, the RGMII bit needs to be set. | |
4069 | */ | |
4070 | switch(phy_mode) { | |
4071 | case PHY_INTERFACE_MODE_QSGMII: | |
4072 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); | |
4073 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
4074 | break; | |
4075 | case PHY_INTERFACE_MODE_SGMII: | |
4076 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); | |
4077 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
4078 | break; | |
4079 | case PHY_INTERFACE_MODE_RGMII: | |
4080 | case PHY_INTERFACE_MODE_RGMII_ID: | |
4081 | ctrl |= MVNETA_GMAC2_PORT_RGMII; | |
4082 | break; | |
4083 | default: | |
4084 | return -EINVAL; | |
4085 | } | |
c5aff182 TP |
4086 | |
4087 | /* Cancel Port Reset */ | |
3f1dd4bc TP |
4088 | ctrl &= ~MVNETA_GMAC2_PORT_RESET; |
4089 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); | |
c5aff182 TP |
4090 | |
4091 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
4092 | MVNETA_GMAC2_PORT_RESET) != 0) | |
4093 | continue; | |
3f1dd4bc TP |
4094 | |
4095 | return 0; | |
c5aff182 TP |
4096 | } |
4097 | ||
4098 | /* Device initialization routine */ | |
03ce758e | 4099 | static int mvneta_probe(struct platform_device *pdev) |
c5aff182 TP |
4100 | { |
4101 | const struct mbus_dram_target_info *dram_target_info; | |
c3f0dd38 | 4102 | struct resource *res; |
c5aff182 TP |
4103 | struct device_node *dn = pdev->dev.of_node; |
4104 | struct device_node *phy_node; | |
dc35a10f | 4105 | struct device_node *bm_node; |
c5aff182 TP |
4106 | struct mvneta_port *pp; |
4107 | struct net_device *dev; | |
8cc3e439 TP |
4108 | const char *dt_mac_addr; |
4109 | char hw_mac_addr[ETH_ALEN]; | |
4110 | const char *mac_from; | |
f8af8e6e | 4111 | const char *managed; |
9110ee07 | 4112 | int tx_csum_limit; |
c5aff182 TP |
4113 | int phy_mode; |
4114 | int err; | |
12bb03b4 | 4115 | int cpu; |
c5aff182 | 4116 | |
ee40a116 | 4117 | dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); |
c5aff182 TP |
4118 | if (!dev) |
4119 | return -ENOMEM; | |
4120 | ||
4121 | dev->irq = irq_of_parse_and_map(dn, 0); | |
4122 | if (dev->irq == 0) { | |
4123 | err = -EINVAL; | |
4124 | goto err_free_netdev; | |
4125 | } | |
4126 | ||
4127 | phy_node = of_parse_phandle(dn, "phy", 0); | |
4128 | if (!phy_node) { | |
83895bed TP |
4129 | if (!of_phy_is_fixed_link(dn)) { |
4130 | dev_err(&pdev->dev, "no PHY specified\n"); | |
4131 | err = -ENODEV; | |
4132 | goto err_free_irq; | |
4133 | } | |
4134 | ||
4135 | err = of_phy_register_fixed_link(dn); | |
4136 | if (err < 0) { | |
4137 | dev_err(&pdev->dev, "cannot register fixed PHY\n"); | |
4138 | goto err_free_irq; | |
4139 | } | |
4140 | ||
4141 | /* In the case of a fixed PHY, the DT node associated | |
4142 | * to the PHY is the Ethernet MAC DT node. | |
4143 | */ | |
c891c24c | 4144 | phy_node = of_node_get(dn); |
c5aff182 TP |
4145 | } |
4146 | ||
4147 | phy_mode = of_get_phy_mode(dn); | |
4148 | if (phy_mode < 0) { | |
4149 | dev_err(&pdev->dev, "incorrect phy-mode\n"); | |
4150 | err = -EINVAL; | |
c891c24c | 4151 | goto err_put_phy_node; |
c5aff182 TP |
4152 | } |
4153 | ||
c5aff182 TP |
4154 | dev->tx_queue_len = MVNETA_MAX_TXD; |
4155 | dev->watchdog_timeo = 5 * HZ; | |
4156 | dev->netdev_ops = &mvneta_netdev_ops; | |
4157 | ||
7ad24ea4 | 4158 | dev->ethtool_ops = &mvneta_eth_tool_ops; |
c5aff182 TP |
4159 | |
4160 | pp = netdev_priv(dev); | |
1c2722a9 | 4161 | spin_lock_init(&pp->lock); |
c5aff182 TP |
4162 | pp->phy_node = phy_node; |
4163 | pp->phy_interface = phy_mode; | |
f8af8e6e SS |
4164 | |
4165 | err = of_property_read_string(dn, "managed", &managed); | |
4166 | pp->use_inband_status = (err == 0 && | |
4167 | strcmp(managed, "in-band-status") == 0); | |
c5aff182 | 4168 | |
90b74c01 GC |
4169 | pp->rxq_def = rxq_def; |
4170 | ||
8d5047cf MW |
4171 | /* Set RX packet offset correction for platforms, whose |
4172 | * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit | |
4173 | * platforms and 0B for 32-bit ones. | |
4174 | */ | |
4175 | pp->rx_offset_correction = | |
4176 | max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION); | |
4177 | ||
9a401dea GC |
4178 | pp->indir[0] = rxq_def; |
4179 | ||
2636ac3c MW |
4180 | /* Get special SoC configurations */ |
4181 | if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) | |
4182 | pp->neta_armada3700 = true; | |
4183 | ||
2804ba4e JZ |
4184 | pp->clk = devm_clk_get(&pdev->dev, "core"); |
4185 | if (IS_ERR(pp->clk)) | |
4186 | pp->clk = devm_clk_get(&pdev->dev, NULL); | |
189dd626 TP |
4187 | if (IS_ERR(pp->clk)) { |
4188 | err = PTR_ERR(pp->clk); | |
c891c24c | 4189 | goto err_put_phy_node; |
189dd626 TP |
4190 | } |
4191 | ||
4192 | clk_prepare_enable(pp->clk); | |
4193 | ||
15cc4a4a JZ |
4194 | pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); |
4195 | if (!IS_ERR(pp->clk_bus)) | |
4196 | clk_prepare_enable(pp->clk_bus); | |
4197 | ||
c3f0dd38 TP |
4198 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
4199 | pp->base = devm_ioremap_resource(&pdev->dev, res); | |
4200 | if (IS_ERR(pp->base)) { | |
4201 | err = PTR_ERR(pp->base); | |
5445eaf3 APR |
4202 | goto err_clk; |
4203 | } | |
4204 | ||
12bb03b4 MR |
4205 | /* Alloc per-cpu port structure */ |
4206 | pp->ports = alloc_percpu(struct mvneta_pcpu_port); | |
4207 | if (!pp->ports) { | |
4208 | err = -ENOMEM; | |
4209 | goto err_clk; | |
4210 | } | |
4211 | ||
74c41b04 | 4212 | /* Alloc per-cpu stats */ |
1c213bd2 | 4213 | pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); |
74c41b04 | 4214 | if (!pp->stats) { |
4215 | err = -ENOMEM; | |
12bb03b4 | 4216 | goto err_free_ports; |
74c41b04 | 4217 | } |
4218 | ||
8cc3e439 | 4219 | dt_mac_addr = of_get_mac_address(dn); |
6c7a9a3c | 4220 | if (dt_mac_addr) { |
8cc3e439 TP |
4221 | mac_from = "device tree"; |
4222 | memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); | |
4223 | } else { | |
4224 | mvneta_get_mac_addr(pp, hw_mac_addr); | |
4225 | if (is_valid_ether_addr(hw_mac_addr)) { | |
4226 | mac_from = "hardware"; | |
4227 | memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); | |
4228 | } else { | |
4229 | mac_from = "random"; | |
4230 | eth_hw_addr_random(dev); | |
4231 | } | |
4232 | } | |
4233 | ||
9110ee07 MW |
4234 | if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { |
4235 | if (tx_csum_limit < 0 || | |
4236 | tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { | |
4237 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
4238 | dev_info(&pdev->dev, | |
4239 | "Wrong TX csum limit in DT, set to %dB\n", | |
4240 | MVNETA_TX_CSUM_DEF_SIZE); | |
4241 | } | |
4242 | } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { | |
4243 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
4244 | } else { | |
4245 | tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; | |
4246 | } | |
4247 | ||
4248 | pp->tx_csum_limit = tx_csum_limit; | |
b65657fc | 4249 | |
dc35a10f | 4250 | dram_target_info = mv_mbus_dram_info(); |
2636ac3c MW |
4251 | /* Armada3700 requires setting default configuration of Mbus |
4252 | * windows, however without using filled mbus_dram_target_info | |
4253 | * structure. | |
4254 | */ | |
4255 | if (dram_target_info || pp->neta_armada3700) | |
dc35a10f MW |
4256 | mvneta_conf_mbus_windows(pp, dram_target_info); |
4257 | ||
c5aff182 TP |
4258 | pp->tx_ring_size = MVNETA_MAX_TXD; |
4259 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
4260 | ||
4261 | pp->dev = dev; | |
4262 | SET_NETDEV_DEV(dev, &pdev->dev); | |
4263 | ||
dc35a10f MW |
4264 | pp->id = global_port_id++; |
4265 | ||
4266 | /* Obtain access to BM resources if enabled and already initialized */ | |
4267 | bm_node = of_parse_phandle(dn, "buffer-manager", 0); | |
4268 | if (bm_node && bm_node->data) { | |
4269 | pp->bm_priv = bm_node->data; | |
4270 | err = mvneta_bm_port_init(pdev, pp); | |
4271 | if (err < 0) { | |
4272 | dev_info(&pdev->dev, "use SW buffer management\n"); | |
4273 | pp->bm_priv = NULL; | |
4274 | } | |
4275 | } | |
d4e4da00 | 4276 | of_node_put(bm_node); |
dc35a10f | 4277 | |
9672850b EG |
4278 | err = mvneta_init(&pdev->dev, pp); |
4279 | if (err < 0) | |
dc35a10f | 4280 | goto err_netdev; |
3f1dd4bc TP |
4281 | |
4282 | err = mvneta_port_power_up(pp, phy_mode); | |
4283 | if (err < 0) { | |
4284 | dev_err(&pdev->dev, "can't power up port\n"); | |
dc35a10f | 4285 | goto err_netdev; |
3f1dd4bc | 4286 | } |
c5aff182 | 4287 | |
2636ac3c MW |
4288 | /* Armada3700 network controller does not support per-cpu |
4289 | * operation, so only single NAPI should be initialized. | |
4290 | */ | |
4291 | if (pp->neta_armada3700) { | |
4292 | netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); | |
4293 | } else { | |
4294 | for_each_present_cpu(cpu) { | |
4295 | struct mvneta_pcpu_port *port = | |
4296 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 4297 | |
2636ac3c MW |
4298 | netif_napi_add(dev, &port->napi, mvneta_poll, |
4299 | NAPI_POLL_WEIGHT); | |
4300 | port->pp = pp; | |
4301 | } | |
12bb03b4 | 4302 | } |
c5aff182 | 4303 | |
2adb719d | 4304 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; |
01ef26ca EG |
4305 | dev->hw_features |= dev->features; |
4306 | dev->vlan_features |= dev->features; | |
97db8afa | 4307 | dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; |
8eef5f97 | 4308 | dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; |
b50b72de | 4309 | |
5777987e JW |
4310 | /* MTU range: 68 - 9676 */ |
4311 | dev->min_mtu = ETH_MIN_MTU; | |
4312 | /* 9676 == 9700 - 20 and rounding to 8 */ | |
4313 | dev->max_mtu = 9676; | |
4314 | ||
c5aff182 TP |
4315 | err = register_netdev(dev); |
4316 | if (err < 0) { | |
4317 | dev_err(&pdev->dev, "failed to register\n"); | |
9672850b | 4318 | goto err_free_stats; |
c5aff182 TP |
4319 | } |
4320 | ||
8cc3e439 TP |
4321 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, |
4322 | dev->dev_addr); | |
c5aff182 TP |
4323 | |
4324 | platform_set_drvdata(pdev, pp->dev); | |
4325 | ||
898b2970 SS |
4326 | if (pp->use_inband_status) { |
4327 | struct phy_device *phy = of_phy_find_device(dn); | |
4328 | ||
4329 | mvneta_fixed_link_update(pp, phy); | |
04d53b20 | 4330 | |
e5a03bfd | 4331 | put_device(&phy->mdio.dev); |
898b2970 SS |
4332 | } |
4333 | ||
c5aff182 TP |
4334 | return 0; |
4335 | ||
dc35a10f MW |
4336 | err_netdev: |
4337 | unregister_netdev(dev); | |
4338 | if (pp->bm_priv) { | |
4339 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
4340 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
4341 | 1 << pp->id); | |
4342 | } | |
74c41b04 | 4343 | err_free_stats: |
4344 | free_percpu(pp->stats); | |
12bb03b4 MR |
4345 | err_free_ports: |
4346 | free_percpu(pp->ports); | |
5445eaf3 | 4347 | err_clk: |
15cc4a4a | 4348 | clk_disable_unprepare(pp->clk_bus); |
5445eaf3 | 4349 | clk_disable_unprepare(pp->clk); |
c891c24c UKK |
4350 | err_put_phy_node: |
4351 | of_node_put(phy_node); | |
5a57a304 JH |
4352 | if (of_phy_is_fixed_link(dn)) |
4353 | of_phy_deregister_fixed_link(dn); | |
c5aff182 TP |
4354 | err_free_irq: |
4355 | irq_dispose_mapping(dev->irq); | |
4356 | err_free_netdev: | |
4357 | free_netdev(dev); | |
4358 | return err; | |
4359 | } | |
4360 | ||
4361 | /* Device removal routine */ | |
03ce758e | 4362 | static int mvneta_remove(struct platform_device *pdev) |
c5aff182 TP |
4363 | { |
4364 | struct net_device *dev = platform_get_drvdata(pdev); | |
5a57a304 | 4365 | struct device_node *dn = pdev->dev.of_node; |
c5aff182 TP |
4366 | struct mvneta_port *pp = netdev_priv(dev); |
4367 | ||
4368 | unregister_netdev(dev); | |
15cc4a4a | 4369 | clk_disable_unprepare(pp->clk_bus); |
189dd626 | 4370 | clk_disable_unprepare(pp->clk); |
12bb03b4 | 4371 | free_percpu(pp->ports); |
74c41b04 | 4372 | free_percpu(pp->stats); |
5a57a304 JH |
4373 | if (of_phy_is_fixed_link(dn)) |
4374 | of_phy_deregister_fixed_link(dn); | |
c5aff182 | 4375 | irq_dispose_mapping(dev->irq); |
c891c24c | 4376 | of_node_put(pp->phy_node); |
c5aff182 TP |
4377 | free_netdev(dev); |
4378 | ||
dc35a10f MW |
4379 | if (pp->bm_priv) { |
4380 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
4381 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
4382 | 1 << pp->id); | |
4383 | } | |
4384 | ||
c5aff182 TP |
4385 | return 0; |
4386 | } | |
4387 | ||
4388 | static const struct of_device_id mvneta_match[] = { | |
4389 | { .compatible = "marvell,armada-370-neta" }, | |
f522a975 | 4390 | { .compatible = "marvell,armada-xp-neta" }, |
2636ac3c | 4391 | { .compatible = "marvell,armada-3700-neta" }, |
c5aff182 TP |
4392 | { } |
4393 | }; | |
4394 | MODULE_DEVICE_TABLE(of, mvneta_match); | |
4395 | ||
4396 | static struct platform_driver mvneta_driver = { | |
4397 | .probe = mvneta_probe, | |
03ce758e | 4398 | .remove = mvneta_remove, |
c5aff182 TP |
4399 | .driver = { |
4400 | .name = MVNETA_DRIVER_NAME, | |
4401 | .of_match_table = mvneta_match, | |
4402 | }, | |
4403 | }; | |
4404 | ||
84a3f4db SAS |
4405 | static int __init mvneta_driver_init(void) |
4406 | { | |
4407 | int ret; | |
4408 | ||
4409 | ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", | |
4410 | mvneta_cpu_online, | |
4411 | mvneta_cpu_down_prepare); | |
4412 | if (ret < 0) | |
4413 | goto out; | |
4414 | online_hpstate = ret; | |
4415 | ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", | |
4416 | NULL, mvneta_cpu_dead); | |
4417 | if (ret) | |
4418 | goto err_dead; | |
4419 | ||
4420 | ret = platform_driver_register(&mvneta_driver); | |
4421 | if (ret) | |
4422 | goto err; | |
4423 | return 0; | |
4424 | ||
4425 | err: | |
4426 | cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); | |
4427 | err_dead: | |
4428 | cpuhp_remove_multi_state(online_hpstate); | |
4429 | out: | |
4430 | return ret; | |
4431 | } | |
4432 | module_init(mvneta_driver_init); | |
4433 | ||
4434 | static void __exit mvneta_driver_exit(void) | |
4435 | { | |
4436 | platform_driver_unregister(&mvneta_driver); | |
4437 | cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); | |
4438 | cpuhp_remove_multi_state(online_hpstate); | |
4439 | } | |
4440 | module_exit(mvneta_driver_exit); | |
c5aff182 TP |
4441 | |
4442 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); | |
4443 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
4444 | MODULE_LICENSE("GPL"); | |
4445 | ||
4446 | module_param(rxq_number, int, S_IRUGO); | |
4447 | module_param(txq_number, int, S_IRUGO); | |
4448 | ||
4449 | module_param(rxq_def, int, S_IRUGO); | |
f19fadfc | 4450 | module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); |