Commit | Line | Data |
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fc8f5ade TP |
1 | /* |
2 | * Driver for the MDIO interface of Marvell network interfaces. | |
3 | * | |
4 | * Since the MDIO interface of Marvell network interfaces is shared | |
5 | * between all network interfaces, having a single driver allows to | |
6 | * handle concurrent accesses properly (you may have four Ethernet | |
7 | * ports, but they in fact share the same SMI interface to access the | |
8 | * MDIO bus). Moreover, this MDIO interface code is similar between | |
9 | * the mv643xx_eth driver and the mvneta driver. For now, it is only | |
10 | * used by the mvneta driver, but it could later be used by the | |
11 | * mv643xx_eth driver as well. | |
12 | * | |
13 | * Copyright (C) 2012 Marvell | |
14 | * | |
15 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
16 | * | |
17 | * This file is licensed under the terms of the GNU General Public | |
18 | * License version 2. This program is licensed "as is" without any | |
19 | * warranty of any kind, whether express or implied. | |
20 | */ | |
21 | ||
22 | #include <linux/init.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/mutex.h> | |
26 | #include <linux/phy.h> | |
2ec98521 | 27 | #include <linux/interrupt.h> |
fc8f5ade | 28 | #include <linux/platform_device.h> |
d98a80f5 | 29 | #include <linux/delay.h> |
7111b717 FF |
30 | #include <linux/io.h> |
31 | #include <linux/of_mdio.h> | |
2ec98521 FF |
32 | #include <linux/sched.h> |
33 | #include <linux/wait.h> | |
fc8f5ade TP |
34 | |
35 | #define MVMDIO_SMI_DATA_SHIFT 0 | |
36 | #define MVMDIO_SMI_PHY_ADDR_SHIFT 16 | |
37 | #define MVMDIO_SMI_PHY_REG_SHIFT 21 | |
38 | #define MVMDIO_SMI_READ_OPERATION BIT(26) | |
39 | #define MVMDIO_SMI_WRITE_OPERATION 0 | |
40 | #define MVMDIO_SMI_READ_VALID BIT(27) | |
41 | #define MVMDIO_SMI_BUSY BIT(28) | |
2ec98521 FF |
42 | #define MVMDIO_ERR_INT_CAUSE 0x007C |
43 | #define MVMDIO_ERR_INT_SMI_DONE 0x00000010 | |
44 | #define MVMDIO_ERR_INT_MASK 0x0080 | |
fc8f5ade TP |
45 | |
46 | struct orion_mdio_dev { | |
47 | struct mutex lock; | |
3712b717 | 48 | void __iomem *regs; |
2ec98521 FF |
49 | /* |
50 | * If we have access to the error interrupt pin (which is | |
51 | * somewhat misnamed as it not only reflects internal errors | |
52 | * but also reflects SMI completion), use that to wait for | |
53 | * SMI access completion instead of polling the SMI busy bit. | |
54 | */ | |
55 | int err_interrupt; | |
56 | wait_queue_head_t smi_busy_wait; | |
fc8f5ade TP |
57 | }; |
58 | ||
2ec98521 FF |
59 | static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev) |
60 | { | |
61 | return !(readl(dev->regs) & MVMDIO_SMI_BUSY); | |
62 | } | |
63 | ||
b07812f1 | 64 | /* Wait for the SMI unit to be ready for another operation |
fc8f5ade TP |
65 | */ |
66 | static int orion_mdio_wait_ready(struct mii_bus *bus) | |
67 | { | |
68 | struct orion_mdio_dev *dev = bus->priv; | |
69 | int count; | |
fc8f5ade | 70 | |
2ec98521 FF |
71 | if (dev->err_interrupt <= 0) { |
72 | count = 0; | |
73 | while (1) { | |
74 | if (orion_mdio_smi_is_done(dev)) | |
75 | break; | |
fc8f5ade | 76 | |
2ec98521 FF |
77 | if (count > 100) { |
78 | dev_err(bus->parent, | |
79 | "Timeout: SMI busy for too long\n"); | |
80 | return -ETIMEDOUT; | |
81 | } | |
fc8f5ade | 82 | |
2ec98521 FF |
83 | udelay(10); |
84 | count++; | |
85 | } | |
86 | } else { | |
87 | if (!orion_mdio_smi_is_done(dev)) { | |
88 | wait_event_timeout(dev->smi_busy_wait, | |
89 | orion_mdio_smi_is_done(dev), | |
90 | msecs_to_jiffies(100)); | |
91 | if (!orion_mdio_smi_is_done(dev)) | |
92 | return -ETIMEDOUT; | |
93 | } | |
fc8f5ade TP |
94 | } |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
99 | static int orion_mdio_read(struct mii_bus *bus, int mii_id, | |
100 | int regnum) | |
101 | { | |
102 | struct orion_mdio_dev *dev = bus->priv; | |
103 | int count; | |
104 | u32 val; | |
105 | int ret; | |
106 | ||
107 | mutex_lock(&dev->lock); | |
108 | ||
109 | ret = orion_mdio_wait_ready(bus); | |
110 | if (ret < 0) { | |
111 | mutex_unlock(&dev->lock); | |
112 | return ret; | |
113 | } | |
114 | ||
115 | writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) | | |
116 | (regnum << MVMDIO_SMI_PHY_REG_SHIFT) | | |
117 | MVMDIO_SMI_READ_OPERATION), | |
3712b717 | 118 | dev->regs); |
fc8f5ade TP |
119 | |
120 | /* Wait for the value to become available */ | |
121 | count = 0; | |
122 | while (1) { | |
3712b717 | 123 | val = readl(dev->regs); |
fc8f5ade TP |
124 | if (val & MVMDIO_SMI_READ_VALID) |
125 | break; | |
126 | ||
127 | if (count > 100) { | |
128 | dev_err(bus->parent, "Timeout when reading PHY\n"); | |
129 | mutex_unlock(&dev->lock); | |
130 | return -ETIMEDOUT; | |
131 | } | |
132 | ||
133 | udelay(10); | |
134 | count++; | |
135 | } | |
136 | ||
137 | mutex_unlock(&dev->lock); | |
138 | ||
139 | return val & 0xFFFF; | |
140 | } | |
141 | ||
142 | static int orion_mdio_write(struct mii_bus *bus, int mii_id, | |
143 | int regnum, u16 value) | |
144 | { | |
145 | struct orion_mdio_dev *dev = bus->priv; | |
146 | int ret; | |
147 | ||
148 | mutex_lock(&dev->lock); | |
149 | ||
150 | ret = orion_mdio_wait_ready(bus); | |
151 | if (ret < 0) { | |
152 | mutex_unlock(&dev->lock); | |
153 | return ret; | |
154 | } | |
155 | ||
156 | writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) | | |
157 | (regnum << MVMDIO_SMI_PHY_REG_SHIFT) | | |
158 | MVMDIO_SMI_WRITE_OPERATION | | |
159 | (value << MVMDIO_SMI_DATA_SHIFT)), | |
3712b717 | 160 | dev->regs); |
fc8f5ade TP |
161 | |
162 | mutex_unlock(&dev->lock); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
167 | static int orion_mdio_reset(struct mii_bus *bus) | |
168 | { | |
169 | return 0; | |
170 | } | |
171 | ||
2ec98521 FF |
172 | static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id) |
173 | { | |
174 | struct orion_mdio_dev *dev = dev_id; | |
175 | ||
176 | if (readl(dev->regs + MVMDIO_ERR_INT_CAUSE) & | |
177 | MVMDIO_ERR_INT_SMI_DONE) { | |
178 | writel(~MVMDIO_ERR_INT_SMI_DONE, | |
179 | dev->regs + MVMDIO_ERR_INT_CAUSE); | |
180 | wake_up(&dev->smi_busy_wait); | |
181 | return IRQ_HANDLED; | |
182 | } | |
183 | ||
184 | return IRQ_NONE; | |
185 | } | |
186 | ||
03ce758e | 187 | static int orion_mdio_probe(struct platform_device *pdev) |
fc8f5ade | 188 | { |
7111b717 | 189 | struct resource *r; |
fc8f5ade TP |
190 | struct mii_bus *bus; |
191 | struct orion_mdio_dev *dev; | |
192 | int i, ret; | |
193 | ||
7111b717 FF |
194 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
195 | if (!r) { | |
196 | dev_err(&pdev->dev, "No SMI register address given\n"); | |
197 | return -ENODEV; | |
198 | } | |
199 | ||
fc8f5ade TP |
200 | bus = mdiobus_alloc_size(sizeof(struct orion_mdio_dev)); |
201 | if (!bus) { | |
202 | dev_err(&pdev->dev, "Cannot allocate MDIO bus\n"); | |
203 | return -ENOMEM; | |
204 | } | |
205 | ||
206 | bus->name = "orion_mdio_bus"; | |
207 | bus->read = orion_mdio_read; | |
208 | bus->write = orion_mdio_write; | |
209 | bus->reset = orion_mdio_reset; | |
210 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", | |
211 | dev_name(&pdev->dev)); | |
212 | bus->parent = &pdev->dev; | |
213 | ||
214 | bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
215 | if (!bus->irq) { | |
fc8f5ade TP |
216 | mdiobus_free(bus); |
217 | return -ENOMEM; | |
218 | } | |
219 | ||
220 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
221 | bus->irq[i] = PHY_POLL; | |
222 | ||
223 | dev = bus->priv; | |
3712b717 FF |
224 | dev->regs = devm_ioremap(&pdev->dev, r->start, resource_size(r)); |
225 | if (!dev->regs) { | |
7111b717 | 226 | dev_err(&pdev->dev, "Unable to remap SMI register\n"); |
2ec98521 FF |
227 | ret = -ENODEV; |
228 | goto out_mdio; | |
229 | } | |
230 | ||
231 | init_waitqueue_head(&dev->smi_busy_wait); | |
232 | ||
233 | dev->err_interrupt = platform_get_irq(pdev, 0); | |
234 | if (dev->err_interrupt != -ENXIO) { | |
235 | ret = devm_request_irq(&pdev->dev, dev->err_interrupt, | |
236 | orion_mdio_err_irq, | |
237 | IRQF_SHARED, pdev->name, dev); | |
238 | if (ret) | |
239 | goto out_mdio; | |
240 | ||
241 | writel(MVMDIO_ERR_INT_SMI_DONE, | |
242 | dev->regs + MVMDIO_ERR_INT_MASK); | |
fc8f5ade TP |
243 | } |
244 | ||
245 | mutex_init(&dev->lock); | |
246 | ||
7111b717 FF |
247 | if (pdev->dev.of_node) |
248 | ret = of_mdiobus_register(bus, pdev->dev.of_node); | |
249 | else | |
250 | ret = mdiobus_register(bus); | |
fc8f5ade TP |
251 | if (ret < 0) { |
252 | dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret); | |
2ec98521 | 253 | goto out_mdio; |
fc8f5ade TP |
254 | } |
255 | ||
256 | platform_set_drvdata(pdev, bus); | |
257 | ||
258 | return 0; | |
2ec98521 FF |
259 | |
260 | out_mdio: | |
261 | kfree(bus->irq); | |
262 | mdiobus_free(bus); | |
263 | return ret; | |
fc8f5ade TP |
264 | } |
265 | ||
03ce758e | 266 | static int orion_mdio_remove(struct platform_device *pdev) |
fc8f5ade TP |
267 | { |
268 | struct mii_bus *bus = platform_get_drvdata(pdev); | |
2ec98521 FF |
269 | struct orion_mdio_dev *dev = bus->priv; |
270 | ||
271 | writel(0, dev->regs + MVMDIO_ERR_INT_MASK); | |
fc8f5ade TP |
272 | mdiobus_unregister(bus); |
273 | kfree(bus->irq); | |
274 | mdiobus_free(bus); | |
275 | return 0; | |
276 | } | |
277 | ||
278 | static const struct of_device_id orion_mdio_match[] = { | |
279 | { .compatible = "marvell,orion-mdio" }, | |
280 | { } | |
281 | }; | |
282 | MODULE_DEVICE_TABLE(of, orion_mdio_match); | |
283 | ||
284 | static struct platform_driver orion_mdio_driver = { | |
285 | .probe = orion_mdio_probe, | |
03ce758e | 286 | .remove = orion_mdio_remove, |
fc8f5ade TP |
287 | .driver = { |
288 | .name = "orion-mdio", | |
289 | .of_match_table = orion_mdio_match, | |
290 | }, | |
291 | }; | |
292 | ||
293 | module_platform_driver(orion_mdio_driver); | |
294 | ||
295 | MODULE_DESCRIPTION("Marvell MDIO interface driver"); | |
296 | MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
297 | MODULE_LICENSE("GPL"); |