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mv643xx_eth: defer probing if Marvell Orion MDIO driver not loaded
[linux-2.6-block.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
3871c387
MS		 23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
24 *
1da177e4
LT		 25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 */
a779d38c 39
7542db8b
JP		 40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
1da177e4
LT		 42#include <linux/init.h>
43#include <linux/dma-mapping.h>
b6298c22 44#include <linux/in.h>
c3efab8e 45#include <linux/ip.h>
1da177e4
LT		 46#include <linux/tcp.h>
47#include <linux/udp.h>
48#include <linux/etherdevice.h>
1da177e4
LT		 49#include <linux/delay.h>
50#include <linux/ethtool.h>
d052d1be 51#include <linux/platform_device.h>
fbd6a754
LB		 52#include <linux/module.h>
53#include <linux/kernel.h>
54#include <linux/spinlock.h>
55#include <linux/workqueue.h>
ed94493f 56#include <linux/phy.h>
fbd6a754 57#include <linux/mv643xx_eth.h>
10a9948d
LB		 58#include <linux/io.h>
59#include <linux/types.h>
eaf5d590 60#include <linux/inet_lro.h>
5a0e3ad6 61#include <linux/slab.h>
452503eb 62#include <linux/clk.h>
fbd6a754 63
e5371493 64static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 65static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 66
fbd6a754 67
fbd6a754
LB		 68/*
69 * Registers shared between all ports.
70 */
3cb4667c 71#define PHY_ADDR 0x0000
3cb4667c
LB		 72#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
73#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
74#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
75#define WINDOW_BAR_ENABLE 0x0290
76#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 77
78/*
37a6084f
LB		 79 * Main per-port registers. These live at offset 0x0400 for
80 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 81 */
37a6084f 82#define PORT_CONFIG 0x0000
d9a073ea 83#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 84#define PORT_CONFIG_EXT 0x0004
85#define MAC_ADDR_LOW 0x0014
86#define MAC_ADDR_HIGH 0x0018
87#define SDMA_CONFIG 0x001c
becfad97
LB		 88#define TX_BURST_SIZE_16_64BIT 0x01000000
89#define TX_BURST_SIZE_4_64BIT 0x00800000
90#define BLM_TX_NO_SWAP 0x00000020
91#define BLM_RX_NO_SWAP 0x00000010
92#define RX_BURST_SIZE_16_64BIT 0x00000008
93#define RX_BURST_SIZE_4_64BIT 0x00000004
37a6084f 94#define PORT_SERIAL_CONTROL 0x003c
becfad97
LB		 95#define SET_MII_SPEED_TO_100 0x01000000
96#define SET_GMII_SPEED_TO_1000 0x00800000
97#define SET_FULL_DUPLEX_MODE 0x00200000
98#define MAX_RX_PACKET_9700BYTE 0x000a0000
99#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
100#define DO_NOT_FORCE_LINK_FAIL 0x00000400
101#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
102#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
103#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
104#define FORCE_LINK_PASS 0x00000002
105#define SERIAL_PORT_ENABLE 0x00000001
37a6084f 106#define PORT_STATUS 0x0044
a2a41689 107#define TX_FIFO_EMPTY 0x00000400
ae9ae064 108#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 109#define PORT_SPEED_MASK 0x00000030
110#define PORT_SPEED_1000 0x00000010
111#define PORT_SPEED_100 0x00000020
112#define PORT_SPEED_10 0x00000000
113#define FLOW_CONTROL_ENABLED 0x00000008
114#define FULL_DUPLEX 0x00000004
81600eea 115#define LINK_UP 0x00000002
37a6084f
LB		 116#define TXQ_COMMAND 0x0048
117#define TXQ_FIX_PRIO_CONF 0x004c
118#define TX_BW_RATE 0x0050
119#define TX_BW_MTU 0x0058
120#define TX_BW_BURST 0x005c
121#define INT_CAUSE 0x0060
226bb6b7 122#define INT_TX_END 0x07f80000
e0ca8410 123#define INT_TX_END_0 0x00080000
befefe21 124#define INT_RX 0x000003fc
e0ca8410 125#define INT_RX_0 0x00000004
073a345c 126#define INT_EXT 0x00000002
37a6084f 127#define INT_CAUSE_EXT 0x0064
befefe21
LB		 128#define INT_EXT_LINK_PHY 0x00110000
129#define INT_EXT_TX 0x000000ff
37a6084f
LB		 130#define INT_MASK 0x0068
131#define INT_MASK_EXT 0x006c
132#define TX_FIFO_URGENT_THRESHOLD 0x0074
302476c9
PZ		 133#define RX_DISCARD_FRAME_CNT 0x0084
134#define RX_OVERRUN_FRAME_CNT 0x0088
37a6084f
LB		 135#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
136#define TX_BW_RATE_MOVED 0x00e0
137#define TX_BW_MTU_MOVED 0x00e8
138#define TX_BW_BURST_MOVED 0x00ec
139#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
140#define RXQ_COMMAND 0x0280
141#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
142#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
143#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
144#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
145
146/*
147 * Misc per-port registers.
148 */
3cb4667c
LB		 149#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
150#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
151#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
152#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 153
2679a550
LB		 154
155/*
becfad97 156 * SDMA configuration register default value.
2679a550 157 */
fbd6a754
LB		 158#if defined(__BIG_ENDIAN)
159#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 160 (RX_BURST_SIZE_4_64BIT | \
161 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 162#elif defined(__LITTLE_ENDIAN)
163#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 164 (RX_BURST_SIZE_4_64BIT | \
165 BLM_RX_NO_SWAP | \
166 BLM_TX_NO_SWAP | \
167 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 168#else
169#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
170#endif
171
2beff77b
LB		 172
173/*
becfad97 174 * Misc definitions.
2beff77b 175 */
becfad97
LB		 176#define DEFAULT_RX_QUEUE_SIZE 128
177#define DEFAULT_TX_QUEUE_SIZE 256
7fd96ce4 178#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
fbd6a754 179
fbd6a754 180
7ca72a3b
LB		 181/*
182 * RX/TX descriptors.
fbd6a754
LB		 183 */
184#if defined(__BIG_ENDIAN)
cc9754b3 185struct rx_desc {
fbd6a754
LB		 186 u16 byte_cnt; /* Descriptor buffer byte count */
187 u16 buf_size; /* Buffer size */
188 u32 cmd_sts; /* Descriptor command status */
189 u32 next_desc_ptr; /* Next descriptor pointer */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191};
192
cc9754b3 193struct tx_desc {
fbd6a754
LB		 194 u16 byte_cnt; /* buffer byte count */
195 u16 l4i_chk; /* CPU provided TCP checksum */
196 u32 cmd_sts; /* Command/status field */
197 u32 next_desc_ptr; /* Pointer to next descriptor */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199};
200#elif defined(__LITTLE_ENDIAN)
cc9754b3 201struct rx_desc {
fbd6a754
LB		 202 u32 cmd_sts; /* Descriptor command status */
203 u16 buf_size; /* Buffer size */
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u32 buf_ptr; /* Descriptor buffer pointer */
206 u32 next_desc_ptr; /* Next descriptor pointer */
207};
208
cc9754b3 209struct tx_desc {
fbd6a754
LB		 210 u32 cmd_sts; /* Command/status field */
211 u16 l4i_chk; /* CPU provided TCP checksum */
212 u16 byte_cnt; /* buffer byte count */
213 u32 buf_ptr; /* pointer to buffer for this descriptor*/
214 u32 next_desc_ptr; /* Pointer to next descriptor */
215};
216#else
217#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
218#endif
219
7ca72a3b 220/* RX & TX descriptor command */
cc9754b3 221#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 222
223/* RX & TX descriptor status */
cc9754b3 224#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 225
226/* RX descriptor status */
cc9754b3
LB		 227#define LAYER_4_CHECKSUM_OK 0x40000000
228#define RX_ENABLE_INTERRUPT 0x20000000
229#define RX_FIRST_DESC 0x08000000
230#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 231#define RX_IP_HDR_OK 0x02000000
232#define RX_PKT_IS_IPV4 0x01000000
233#define RX_PKT_IS_ETHERNETV2 0x00800000
234#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
235#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
236#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 237
238/* TX descriptor command */
cc9754b3
LB		 239#define TX_ENABLE_INTERRUPT 0x00800000
240#define GEN_CRC 0x00400000
241#define TX_FIRST_DESC 0x00200000
242#define TX_LAST_DESC 0x00100000
243#define ZERO_PADDING 0x00080000
244#define GEN_IP_V4_CHECKSUM 0x00040000
245#define GEN_TCP_UDP_CHECKSUM 0x00020000
246#define UDP_FRAME 0x00010000
e32b6617
LB		 247#define MAC_HDR_EXTRA_4_BYTES 0x00008000
248#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 249
cc9754b3 250#define TX_IHL_SHIFT 11
7ca72a3b
LB		 251
252
c9df406f 253/* global *******************************************************************/
e5371493 254struct mv643xx_eth_shared_private {
fc32b0e2
LB		 255 /*
256 * Ethernet controller base address.
257 */
cc9754b3 258 void __iomem *base;
c9df406f 259
fc32b0e2
LB		 260 /*
261 * Per-port MBUS window access register value.
262 */
c9df406f
LB		 263 u32 win_protect;
264
fc32b0e2
LB		 265 /*
266 * Hardware-specific parameters.
267 */
773fc3ee 268 int extended_rx_coal_limit;
457b1d5a 269 int tx_bw_control;
9b2c2ff7 270 int tx_csum_limit;
452503eb 271
c9df406f
LB		 272};
273
457b1d5a
LB		 274#define TX_BW_CONTROL_ABSENT 0
275#define TX_BW_CONTROL_OLD_LAYOUT 1
276#define TX_BW_CONTROL_NEW_LAYOUT 2
277
e7d2f4db
LB		 278static int mv643xx_eth_open(struct net_device *dev);
279static int mv643xx_eth_stop(struct net_device *dev);
280
c9df406f
LB		 281
282/* per-port *****************************************************************/
e5371493 283struct mib_counters {
fbd6a754
LB		 284 u64 good_octets_received;
285 u32 bad_octets_received;
286 u32 internal_mac_transmit_err;
287 u32 good_frames_received;
288 u32 bad_frames_received;
289 u32 broadcast_frames_received;
290 u32 multicast_frames_received;
291 u32 frames_64_octets;
292 u32 frames_65_to_127_octets;
293 u32 frames_128_to_255_octets;
294 u32 frames_256_to_511_octets;
295 u32 frames_512_to_1023_octets;
296 u32 frames_1024_to_max_octets;
297 u64 good_octets_sent;
298 u32 good_frames_sent;
299 u32 excessive_collision;
300 u32 multicast_frames_sent;
301 u32 broadcast_frames_sent;
302 u32 unrec_mac_control_received;
303 u32 fc_sent;
304 u32 good_fc_received;
305 u32 bad_fc_received;
306 u32 undersize_received;
307 u32 fragments_received;
308 u32 oversize_received;
309 u32 jabber_received;
310 u32 mac_receive_error;
311 u32 bad_crc_event;
312 u32 collision;
313 u32 late_collision;
302476c9
PZ		 314 /* Non MIB hardware counters */
315 u32 rx_discard;
316 u32 rx_overrun;
fbd6a754
LB		 317};
318
eaf5d590
LB		 319struct lro_counters {
320 u32 lro_aggregated;
321 u32 lro_flushed;
322 u32 lro_no_desc;
323};
324
8a578111 325struct rx_queue {
64da80a2
LB		 326 int index;
327
8a578111
LB		 328 int rx_ring_size;
329
330 int rx_desc_count;
331 int rx_curr_desc;
332 int rx_used_desc;
333
334 struct rx_desc *rx_desc_area;
335 dma_addr_t rx_desc_dma;
336 int rx_desc_area_size;
337 struct sk_buff **rx_skb;
eaf5d590 338
eaf5d590
LB		 339 struct net_lro_mgr lro_mgr;
340 struct net_lro_desc lro_arr[8];
8a578111
LB		 341};
342
13d64285 343struct tx_queue {
3d6b35bc
LB		 344 int index;
345
13d64285 346 int tx_ring_size;
fbd6a754 347
13d64285
LB		 348 int tx_desc_count;
349 int tx_curr_desc;
350 int tx_used_desc;
fbd6a754 351
5daffe94 352 struct tx_desc *tx_desc_area;
fbd6a754
LB		 353 dma_addr_t tx_desc_dma;
354 int tx_desc_area_size;
99ab08e0
LB		 355
356 struct sk_buff_head tx_skb;
8fd89211
LB		 357
358 unsigned long tx_packets;
359 unsigned long tx_bytes;
360 unsigned long tx_dropped;
13d64285
LB		 361};
362
363struct mv643xx_eth_private {
364 struct mv643xx_eth_shared_private *shared;
37a6084f 365 void __iomem *base;
fc32b0e2 366 int port_num;
13d64285 367
fc32b0e2 368 struct net_device *dev;
fbd6a754 369
ed94493f 370 struct phy_device *phy;
fbd6a754 371
4ff3495a
LB		 372 struct timer_list mib_counters_timer;
373 spinlock_t mib_counters_lock;
fc32b0e2 374 struct mib_counters mib_counters;
4ff3495a 375
eaf5d590
LB		 376 struct lro_counters lro_counters;
377
fc32b0e2 378 struct work_struct tx_timeout_task;
8a578111 379
1fa38c58 380 struct napi_struct napi;
e0ca8410 381 u32 int_mask;
1319ebad 382 u8 oom;
1fa38c58
LB		 383 u8 work_link;
384 u8 work_tx;
385 u8 work_tx_end;
386 u8 work_rx;
387 u8 work_rx_refill;
1fa38c58 388
2bcb4b0f 389 int skb_size;
2bcb4b0f 390
8a578111
LB		 391 /*
392 * RX state.
393 */
e7d2f4db 394 int rx_ring_size;
8a578111
LB		 395 unsigned long rx_desc_sram_addr;
396 int rx_desc_sram_size;
f7981c1c 397 int rxq_count;
2257e05c 398 struct timer_list rx_oom;
64da80a2 399 struct rx_queue rxq[8];
13d64285
LB		 400
401 /*
402 * TX state.
403 */
e7d2f4db 404 int tx_ring_size;
13d64285
LB		 405 unsigned long tx_desc_sram_addr;
406 int tx_desc_sram_size;
f7981c1c 407 int txq_count;
3d6b35bc 408 struct tx_queue txq[8];
452503eb
AL		 409
410 /*
411 * Hardware-specific parameters.
412 */
9a43a026 413#if defined(CONFIG_HAVE_CLK)
452503eb 414 struct clk *clk;
9a43a026 415#endif
452503eb 416 unsigned int t_clk;
fbd6a754 417};
1da177e4 418
fbd6a754 419
c9df406f 420/* port register accessors **************************************************/
e5371493 421static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 422{
cc9754b3 423 return readl(mp->shared->base + offset);
c9df406f 424}
fbd6a754 425
37a6084f
LB		 426static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
427{
428 return readl(mp->base + offset);
429}
430
e5371493 431static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 432{
cc9754b3 433 writel(data, mp->shared->base + offset);
c9df406f 434}
fbd6a754 435
37a6084f
LB		 436static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
437{
438 writel(data, mp->base + offset);
439}
440
fbd6a754 441
c9df406f 442/* rxq/txq helper functions *************************************************/
8a578111 443static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 444{
64da80a2 445 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 446}
fbd6a754 447
13d64285
LB		 448static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
449{
3d6b35bc 450 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 451}
452
8a578111 453static void rxq_enable(struct rx_queue *rxq)
c9df406f 454{
8a578111 455 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 456 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 457}
1da177e4 458
8a578111
LB		 459static void rxq_disable(struct rx_queue *rxq)
460{
461 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 462 u8 mask = 1 << rxq->index;
1da177e4 463
37a6084f
LB		 464 wrlp(mp, RXQ_COMMAND, mask << 8);
465 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 466 udelay(10);
c9df406f
LB		 467}
468
6b368f68
LB		 469static void txq_reset_hw_ptr(struct tx_queue *txq)
470{
471 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 472 u32 addr;
473
474 addr = (u32)txq->tx_desc_dma;
475 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 476 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 477}
478
13d64285 479static void txq_enable(struct tx_queue *txq)
1da177e4 480{
13d64285 481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 482 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 483}
484
13d64285 485static void txq_disable(struct tx_queue *txq)
1da177e4 486{
13d64285 487 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 488 u8 mask = 1 << txq->index;
c9df406f 489
37a6084f
LB		 490 wrlp(mp, TXQ_COMMAND, mask << 8);
491 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 492 udelay(10);
493}
494
1fa38c58 495static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 496{
497 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 498 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 499
8fd89211
LB		 500 if (netif_tx_queue_stopped(nq)) {
501 __netif_tx_lock(nq, smp_processor_id());
502 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
503 netif_tx_wake_queue(nq);
504 __netif_tx_unlock(nq);
505 }
1da177e4
LT		 506}
507
c9df406f 508
1fa38c58 509/* rx napi ******************************************************************/
eaf5d590
LB		 510static int
511mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
512 u64 *hdr_flags, void *priv)
513{
514 unsigned long cmd_sts = (unsigned long)priv;
515
516 /*
517 * Make sure that this packet is Ethernet II, is not VLAN
518 * tagged, is IPv4, has a valid IP header, and is TCP.
519 */
520 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
521 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
522 RX_PKT_IS_VLAN_TAGGED)) !=
523 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
524 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
525 return -1;
526
527 skb_reset_network_header(skb);
528 skb_set_transport_header(skb, ip_hdrlen(skb));
529 *iphdr = ip_hdr(skb);
530 *tcph = tcp_hdr(skb);
531 *hdr_flags = LRO_IPV4 | LRO_TCP;
532
533 return 0;
534}
eaf5d590 535
8a578111 536static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 537{
8a578111
LB		 538 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
539 struct net_device_stats *stats = &mp->dev->stats;
eaf5d590 540 int lro_flush_needed;
8a578111 541 int rx;
1da177e4 542
eaf5d590 543 lro_flush_needed = 0;
8a578111 544 rx = 0;
9e1f3772 545 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 546 struct rx_desc *rx_desc;
96587661 547 unsigned int cmd_sts;
fc32b0e2 548 struct sk_buff *skb;
6b8f90c2 549 u16 byte_cnt;
ff561eef 550
8a578111 551 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 552
96587661 553 cmd_sts = rx_desc->cmd_sts;
2257e05c 554 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 555 break;
96587661 556 rmb();
1da177e4 557
8a578111
LB		 558 skb = rxq->rx_skb[rxq->rx_curr_desc];
559 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 560
9da78745
LB		 561 rxq->rx_curr_desc++;
562 if (rxq->rx_curr_desc == rxq->rx_ring_size)
563 rxq->rx_curr_desc = 0;
ff561eef 564
eb0519b5 565 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
abe78717 566 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 567 rxq->rx_desc_count--;
568 rx++;
b1dd9ca1 569
1fa38c58
LB		 570 mp->work_rx_refill |= 1 << rxq->index;
571
6b8f90c2
LB		 572 byte_cnt = rx_desc->byte_cnt;
573
468d09f8
DF		 574 /*
575 * Update statistics.
fc32b0e2
LB		 576 *
577 * Note that the descriptor byte count includes 2 dummy
578 * bytes automatically inserted by the hardware at the
579 * start of the packet (which we don't count), and a 4
580 * byte CRC at the end of the packet (which we do count).
468d09f8 581 */
1da177e4 582 stats->rx_packets++;
6b8f90c2 583 stats->rx_bytes += byte_cnt - 2;
96587661 584
1da177e4 585 /*
fc32b0e2
LB		 586 * In case we received a packet without first / last bits
587 * on, or the error summary bit is set, the packet needs
588 * to be dropped.
1da177e4 589 */
f61e5547
LB		 590 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
591 != (RX_FIRST_DESC | RX_LAST_DESC))
592 goto err;
593
594 /*
595 * The -4 is for the CRC in the trailer of the
596 * received packet
597 */
598 skb_put(skb, byte_cnt - 2 - 4);
599
600 if (cmd_sts & LAYER_4_CHECKSUM_OK)
601 skb->ip_summed = CHECKSUM_UNNECESSARY;
602 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 603
eaf5d590
LB		 604 if (skb->dev->features & NETIF_F_LRO &&
605 skb->ip_summed == CHECKSUM_UNNECESSARY) {
606 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
607 lro_flush_needed = 1;
608 } else
eaf5d590 609 netif_receive_skb(skb);
f61e5547
LB		 610
611 continue;
612
613err:
614 stats->rx_dropped++;
615
616 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
617 (RX_FIRST_DESC | RX_LAST_DESC)) {
618 if (net_ratelimit())
7542db8b
JP		 619 netdev_err(mp->dev,
620 "received packet spanning multiple descriptors\n");
1da177e4 621 }
f61e5547
LB		 622
623 if (cmd_sts & ERROR_SUMMARY)
624 stats->rx_errors++;
625
626 dev_kfree_skb(skb);
1da177e4 627 }
fc32b0e2 628
eaf5d590
LB		 629 if (lro_flush_needed)
630 lro_flush_all(&rxq->lro_mgr);
eaf5d590 631
1fa38c58
LB		 632 if (rx < budget)
633 mp->work_rx &= ~(1 << rxq->index);
634
8a578111 635 return rx;
1da177e4
LT		 636}
637
1fa38c58 638static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 639{
1fa38c58 640 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 641 int refilled;
8a578111 642
1fa38c58
LB		 643 refilled = 0;
644 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
645 struct sk_buff *skb;
1fa38c58 646 int rx;
53771522 647 struct rx_desc *rx_desc;
530e557a 648 int size;
d0412d96 649
acb600de 650 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
2bcb4b0f 651
1fa38c58 652 if (skb == NULL) {
1319ebad 653 mp->oom = 1;
1fa38c58
LB		 654 goto oom;
655 }
d0412d96 656
7fd96ce4
LB		 657 if (SKB_DMA_REALIGN)
658 skb_reserve(skb, SKB_DMA_REALIGN);
2257e05c 659
1fa38c58
LB		 660 refilled++;
661 rxq->rx_desc_count++;
c9df406f 662
1fa38c58
LB		 663 rx = rxq->rx_used_desc++;
664 if (rxq->rx_used_desc == rxq->rx_ring_size)
665 rxq->rx_used_desc = 0;
2257e05c 666
53771522
LB		 667 rx_desc = rxq->rx_desc_area + rx;
668
530e557a 669 size = skb->end - skb->data;
eb0519b5 670 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
530e557a 671 skb->data, size,
eb0519b5 672 DMA_FROM_DEVICE);
530e557a 673 rx_desc->buf_size = size;
1fa38c58
LB		 674 rxq->rx_skb[rx] = skb;
675 wmb();
53771522 676 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 677 wmb();
2257e05c 678
1fa38c58
LB		 679 /*
680 * The hardware automatically prepends 2 bytes of
681 * dummy data to each received packet, so that the
682 * IP header ends up 16-byte aligned.
683 */
684 skb_reserve(skb, 2);
685 }
686
687 if (refilled < budget)
688 mp->work_rx_refill &= ~(1 << rxq->index);
689
690oom:
691 return refilled;
d0412d96
JC		 692}
693
c9df406f
LB		 694
695/* tx ***********************************************************************/
c9df406f 696static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 697{
13d64285 698 int frag;
1da177e4 699
c9df406f 700 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
9e903e08
ED		 701 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
702
703 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
c9df406f 704 return 1;
1da177e4 705 }
13d64285 706
c9df406f
LB		 707 return 0;
708}
7303fde8 709
13d64285 710static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 711{
eb0519b5 712 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 713 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 714 int frag;
1da177e4 715
13d64285
LB		 716 for (frag = 0; frag < nr_frags; frag++) {
717 skb_frag_t *this_frag;
718 int tx_index;
719 struct tx_desc *desc;
720
721 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 722 tx_index = txq->tx_curr_desc++;
723 if (txq->tx_curr_desc == txq->tx_ring_size)
724 txq->tx_curr_desc = 0;
13d64285
LB		 725 desc = &txq->tx_desc_area[tx_index];
726
727 /*
728 * The last fragment will generate an interrupt
729 * which will free the skb on TX completion.
730 */
731 if (frag == nr_frags - 1) {
732 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
733 ZERO_PADDING | TX_LAST_DESC |
734 TX_ENABLE_INTERRUPT;
13d64285
LB		 735 } else {
736 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 737 }
738
c9df406f 739 desc->l4i_chk = 0;
9e903e08 740 desc->byte_cnt = skb_frag_size(this_frag);
f106358b
IC		 741 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
742 this_frag, 0,
9e903e08 743 skb_frag_size(this_frag),
f106358b 744 DMA_TO_DEVICE);
c9df406f 745 }
1da177e4
LT		 746}
747
c9df406f
LB		 748static inline __be16 sum16_as_be(__sum16 sum)
749{
750 return (__force __be16)sum;
751}
1da177e4 752
4df89bd5 753static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 754{
8fa89bf5 755 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 756 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 757 int tx_index;
cc9754b3 758 struct tx_desc *desc;
c9df406f 759 u32 cmd_sts;
4df89bd5 760 u16 l4i_chk;
c9df406f 761 int length;
1da177e4 762
cc9754b3 763 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 764 l4i_chk = 0;
c9df406f
LB		 765
766 if (skb->ip_summed == CHECKSUM_PARTIAL) {
9b2c2ff7 767 int hdr_len;
4df89bd5 768 int tag_bytes;
e32b6617
LB		 769
770 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
771 skb->protocol != htons(ETH_P_8021Q));
c9df406f 772
9b2c2ff7
SB		 773 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
774 tag_bytes = hdr_len - ETH_HLEN;
775 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
776 unlikely(tag_bytes & ~12)) {
4df89bd5
LB		 777 if (skb_checksum_help(skb) == 0)
778 goto no_csum;
779 kfree_skb(skb);
780 return 1;
781 }
c9df406f 782
4df89bd5 783 if (tag_bytes & 4)
e32b6617 784 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 785 if (tag_bytes & 8)
e32b6617 786 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 787
788 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
789 GEN_IP_V4_CHECKSUM |
790 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 791
c9df406f
LB		 792 switch (ip_hdr(skb)->protocol) {
793 case IPPROTO_UDP:
cc9754b3 794 cmd_sts |= UDP_FRAME;
4df89bd5 795 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 796 break;
797 case IPPROTO_TCP:
4df89bd5 798 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 799 break;
800 default:
801 BUG();
802 }
803 } else {
4df89bd5 804no_csum:
c9df406f 805 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 806 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 807 }
808
66823b92
LB		 809 tx_index = txq->tx_curr_desc++;
810 if (txq->tx_curr_desc == txq->tx_ring_size)
811 txq->tx_curr_desc = 0;
4df89bd5
LB		 812 desc = &txq->tx_desc_area[tx_index];
813
814 if (nr_frags) {
815 txq_submit_frag_skb(txq, skb);
816 length = skb_headlen(skb);
817 } else {
818 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
819 length = skb->len;
820 }
821
822 desc->l4i_chk = l4i_chk;
823 desc->byte_cnt = length;
eb0519b5
GP		 824 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
825 length, DMA_TO_DEVICE);
4df89bd5 826
99ab08e0
LB		 827 __skb_queue_tail(&txq->tx_skb, skb);
828
3b182d7d
RC		 829 skb_tx_timestamp(skb);
830
c9df406f
LB		 831 /* ensure all other descriptors are written before first cmd_sts */
832 wmb();
833 desc->cmd_sts = cmd_sts;
834
1fa38c58
LB		 835 /* clear TX_END status */
836 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 837
c9df406f
LB		 838 /* ensure all descriptors are written before poking hardware */
839 wmb();
13d64285 840 txq_enable(txq);
c9df406f 841
13d64285 842 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 843
844 return 0;
1da177e4 845}
1da177e4 846
0ccfe64d 847static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 848{
e5371493 849 struct mv643xx_eth_private *mp = netdev_priv(dev);
73151ce3 850 int length, queue;
13d64285 851 struct tx_queue *txq;
e5ef1de1 852 struct netdev_queue *nq;
afdb57a2 853
8fd89211
LB		 854 queue = skb_get_queue_mapping(skb);
855 txq = mp->txq + queue;
856 nq = netdev_get_tx_queue(dev, queue);
857
c9df406f 858 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 859 txq->tx_dropped++;
7542db8b
JP		 860 netdev_printk(KERN_DEBUG, dev,
861 "failed to linearize skb with tiny unaligned fragment\n");
c9df406f
LB		 862 return NETDEV_TX_BUSY;
863 }
864
17cd0a59 865 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1 866 if (net_ratelimit())
7542db8b 867 netdev_err(dev, "tx queue full?!\n");
3d6b35bc
LB		 868 kfree_skb(skb);
869 return NETDEV_TX_OK;
c9df406f
LB		 870 }
871
73151ce3
RC		 872 length = skb->len;
873
4df89bd5
LB		 874 if (!txq_submit_skb(txq, skb)) {
875 int entries_left;
876
73151ce3 877 txq->tx_bytes += length;
4df89bd5 878 txq->tx_packets++;
c9df406f 879
4df89bd5
LB		 880 entries_left = txq->tx_ring_size - txq->tx_desc_count;
881 if (entries_left < MAX_SKB_FRAGS + 1)
882 netif_tx_stop_queue(nq);
883 }
c9df406f 884
c9df406f 885 return NETDEV_TX_OK;
1da177e4
LT		 886}
887
c9df406f 888
1fa38c58
LB		 889/* tx napi ******************************************************************/
890static void txq_kick(struct tx_queue *txq)
891{
892 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 893 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 894 u32 hw_desc_ptr;
895 u32 expected_ptr;
896
8fd89211 897 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 898
37a6084f 899 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 900 goto out;
901
37a6084f 902 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 903 expected_ptr = (u32)txq->tx_desc_dma +
904 txq->tx_curr_desc * sizeof(struct tx_desc);
905
906 if (hw_desc_ptr != expected_ptr)
907 txq_enable(txq);
908
909out:
8fd89211 910 __netif_tx_unlock(nq);
1fa38c58
LB		 911
912 mp->work_tx_end &= ~(1 << txq->index);
913}
914
915static int txq_reclaim(struct tx_queue *txq, int budget, int force)
916{
917 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 918 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 919 int reclaimed;
920
8fd89211 921 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 922
923 reclaimed = 0;
924 while (reclaimed < budget && txq->tx_desc_count > 0) {
925 int tx_index;
926 struct tx_desc *desc;
927 u32 cmd_sts;
928 struct sk_buff *skb;
1fa38c58
LB		 929
930 tx_index = txq->tx_used_desc;
931 desc = &txq->tx_desc_area[tx_index];
932 cmd_sts = desc->cmd_sts;
933
934 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
935 if (!force)
936 break;
937 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
938 }
939
940 txq->tx_used_desc = tx_index + 1;
941 if (txq->tx_used_desc == txq->tx_ring_size)
942 txq->tx_used_desc = 0;
943
944 reclaimed++;
945 txq->tx_desc_count--;
946
99ab08e0
LB		 947 skb = NULL;
948 if (cmd_sts & TX_LAST_DESC)
949 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 950
951 if (cmd_sts & ERROR_SUMMARY) {
7542db8b 952 netdev_info(mp->dev, "tx error\n");
1fa38c58
LB		 953 mp->dev->stats.tx_errors++;
954 }
955
a418950c 956 if (cmd_sts & TX_FIRST_DESC) {
eb0519b5 957 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 958 desc->byte_cnt, DMA_TO_DEVICE);
959 } else {
eb0519b5 960 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 961 desc->byte_cnt, DMA_TO_DEVICE);
962 }
1fa38c58 963
acb600de 964 dev_kfree_skb(skb);
1fa38c58
LB		 965 }
966
8fd89211
LB		 967 __netif_tx_unlock(nq);
968
1fa38c58
LB		 969 if (reclaimed < budget)
970 mp->work_tx &= ~(1 << txq->index);
971
1fa38c58
LB		 972 return reclaimed;
973}
974
975
89df5fdc
LB		 976/* tx rate control **********************************************************/
977/*
978 * Set total maximum TX rate (shared by all TX queues for this port)
979 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
980 */
981static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
982{
983 int token_rate;
984 int mtu;
985 int bucket_size;
986
452503eb 987 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
89df5fdc
LB		 988 if (token_rate > 1023)
989 token_rate = 1023;
990
991 mtu = (mp->dev->mtu + 255) >> 8;
992 if (mtu > 63)
993 mtu = 63;
994
995 bucket_size = (burst + 255) >> 8;
996 if (bucket_size > 65535)
997 bucket_size = 65535;
998
457b1d5a
LB		 999 switch (mp->shared->tx_bw_control) {
1000 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1001 wrlp(mp, TX_BW_RATE, token_rate);
1002 wrlp(mp, TX_BW_MTU, mtu);
1003 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1004 break;
1005 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1006 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1007 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1008 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1009 break;
1e881592 1010 }
89df5fdc
LB		 1011}
1012
1013static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1014{
1015 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1016 int token_rate;
1017 int bucket_size;
1018
452503eb 1019 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
89df5fdc
LB		 1020 if (token_rate > 1023)
1021 token_rate = 1023;
1022
1023 bucket_size = (burst + 255) >> 8;
1024 if (bucket_size > 65535)
1025 bucket_size = 65535;
1026
37a6084f
LB		 1027 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1028 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1029}
1030
1031static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1032{
1033 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1034 int off;
1035 u32 val;
1036
1037 /*
1038 * Turn on fixed priority mode.
1039 */
457b1d5a
LB		 1040 off = 0;
1041 switch (mp->shared->tx_bw_control) {
1042 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1043 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1044 break;
1045 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1046 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1047 break;
1048 }
89df5fdc 1049
457b1d5a 1050 if (off) {
37a6084f 1051 val = rdlp(mp, off);
457b1d5a 1052 val |= 1 << txq->index;
37a6084f 1053 wrlp(mp, off, val);
457b1d5a 1054 }
89df5fdc
LB		 1055}
1056
89df5fdc 1057
c9df406f 1058/* mii management interface *************************************************/
260055bb
PS		 1059static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1060{
1061 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1062 u32 autoneg_disable = FORCE_LINK_PASS |
1063 DISABLE_AUTO_NEG_SPEED_GMII |
1064 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1065 DISABLE_AUTO_NEG_FOR_DUPLEX;
1066
1067 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1068 /* enable auto negotiation */
1069 pscr &= ~autoneg_disable;
1070 goto out_write;
1071 }
1072
1073 pscr |= autoneg_disable;
1074
1075 if (mp->phy->speed == SPEED_1000) {
1076 /* force gigabit, half duplex not supported */
1077 pscr |= SET_GMII_SPEED_TO_1000;
1078 pscr |= SET_FULL_DUPLEX_MODE;
1079 goto out_write;
1080 }
1081
1082 pscr &= ~SET_GMII_SPEED_TO_1000;
1083
1084 if (mp->phy->speed == SPEED_100)
1085 pscr |= SET_MII_SPEED_TO_100;
1086 else
1087 pscr &= ~SET_MII_SPEED_TO_100;
1088
1089 if (mp->phy->duplex == DUPLEX_FULL)
1090 pscr |= SET_FULL_DUPLEX_MODE;
1091 else
1092 pscr &= ~SET_FULL_DUPLEX_MODE;
1093
1094out_write:
1095 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1096}
1097
8fd89211
LB		 1098/* statistics ***************************************************************/
1099static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1100{
1101 struct mv643xx_eth_private *mp = netdev_priv(dev);
1102 struct net_device_stats *stats = &dev->stats;
1103 unsigned long tx_packets = 0;
1104 unsigned long tx_bytes = 0;
1105 unsigned long tx_dropped = 0;
1106 int i;
1107
1108 for (i = 0; i < mp->txq_count; i++) {
1109 struct tx_queue *txq = mp->txq + i;
1110
1111 tx_packets += txq->tx_packets;
1112 tx_bytes += txq->tx_bytes;
1113 tx_dropped += txq->tx_dropped;
1114 }
1115
1116 stats->tx_packets = tx_packets;
1117 stats->tx_bytes = tx_bytes;
1118 stats->tx_dropped = tx_dropped;
1119
1120 return stats;
1121}
1122
eaf5d590
LB		 1123static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1124{
1125 u32 lro_aggregated = 0;
1126 u32 lro_flushed = 0;
1127 u32 lro_no_desc = 0;
1128 int i;
1129
eaf5d590
LB		 1130 for (i = 0; i < mp->rxq_count; i++) {
1131 struct rx_queue *rxq = mp->rxq + i;
1132
1133 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1134 lro_flushed += rxq->lro_mgr.stats.flushed;
1135 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1136 }
eaf5d590
LB		 1137
1138 mp->lro_counters.lro_aggregated = lro_aggregated;
1139 mp->lro_counters.lro_flushed = lro_flushed;
1140 mp->lro_counters.lro_no_desc = lro_no_desc;
1141}
1142
fc32b0e2 1143static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1144{
fc32b0e2 1145 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1146}
1147
fc32b0e2 1148static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1149{
fc32b0e2
LB		 1150 int i;
1151
1152 for (i = 0; i < 0x80; i += 4)
1153 mib_read(mp, i);
302476c9
PZ		 1154
1155 /* Clear non MIB hw counters also */
1156 rdlp(mp, RX_DISCARD_FRAME_CNT);
1157 rdlp(mp, RX_OVERRUN_FRAME_CNT);
c9df406f 1158}
d0412d96 1159
fc32b0e2 1160static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1161{
e5371493 1162 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1163
57e8f26a 1164 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1165 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1166 p->bad_octets_received += mib_read(mp, 0x08);
1167 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1168 p->good_frames_received += mib_read(mp, 0x10);
1169 p->bad_frames_received += mib_read(mp, 0x14);
1170 p->broadcast_frames_received += mib_read(mp, 0x18);
1171 p->multicast_frames_received += mib_read(mp, 0x1c);
1172 p->frames_64_octets += mib_read(mp, 0x20);
1173 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1174 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1175 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1176 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1177 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1178 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1179 p->good_frames_sent += mib_read(mp, 0x40);
1180 p->excessive_collision += mib_read(mp, 0x44);
1181 p->multicast_frames_sent += mib_read(mp, 0x48);
1182 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1183 p->unrec_mac_control_received += mib_read(mp, 0x50);
1184 p->fc_sent += mib_read(mp, 0x54);
1185 p->good_fc_received += mib_read(mp, 0x58);
1186 p->bad_fc_received += mib_read(mp, 0x5c);
1187 p->undersize_received += mib_read(mp, 0x60);
1188 p->fragments_received += mib_read(mp, 0x64);
1189 p->oversize_received += mib_read(mp, 0x68);
1190 p->jabber_received += mib_read(mp, 0x6c);
1191 p->mac_receive_error += mib_read(mp, 0x70);
1192 p->bad_crc_event += mib_read(mp, 0x74);
1193 p->collision += mib_read(mp, 0x78);
1194 p->late_collision += mib_read(mp, 0x7c);
302476c9
PZ		 1195 /* Non MIB hardware counters */
1196 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1197 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
57e8f26a 1198 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1199
1200 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1201}
1202
1203static void mib_counters_timer_wrapper(unsigned long _mp)
1204{
1205 struct mv643xx_eth_private *mp = (void *)_mp;
1206
1207 mib_counters_update(mp);
d0412d96
JC		 1208}
1209
c9df406f 1210
3e508034
LB		 1211/* interrupt coalescing *****************************************************/
1212/*
1213 * Hardware coalescing parameters are set in units of 64 t_clk
1214 * cycles. I.e.:
1215 *
1216 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1217 *
1218 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1219 *
1220 * In the ->set*() methods, we round the computed register value
1221 * to the nearest integer.
1222 */
1223static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1224{
1225 u32 val = rdlp(mp, SDMA_CONFIG);
1226 u64 temp;
1227
1228 if (mp->shared->extended_rx_coal_limit)
1229 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1230 else
1231 temp = (val & 0x003fff00) >> 8;
1232
1233 temp *= 64000000;
452503eb 1234 do_div(temp, mp->t_clk);
3e508034
LB		 1235
1236 return (unsigned int)temp;
1237}
1238
1239static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1240{
1241 u64 temp;
1242 u32 val;
1243
452503eb 1244 temp = (u64)usec * mp->t_clk;
3e508034
LB		 1245 temp += 31999999;
1246 do_div(temp, 64000000);
1247
1248 val = rdlp(mp, SDMA_CONFIG);
1249 if (mp->shared->extended_rx_coal_limit) {
1250 if (temp > 0xffff)
1251 temp = 0xffff;
1252 val &= ~0x023fff80;
1253 val |= (temp & 0x8000) << 10;
1254 val |= (temp & 0x7fff) << 7;
1255 } else {
1256 if (temp > 0x3fff)
1257 temp = 0x3fff;
1258 val &= ~0x003fff00;
1259 val |= (temp & 0x3fff) << 8;
1260 }
1261 wrlp(mp, SDMA_CONFIG, val);
1262}
1263
1264static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1265{
1266 u64 temp;
1267
1268 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1269 temp *= 64000000;
452503eb 1270 do_div(temp, mp->t_clk);
3e508034
LB		 1271
1272 return (unsigned int)temp;
1273}
1274
1275static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1276{
1277 u64 temp;
1278
452503eb 1279 temp = (u64)usec * mp->t_clk;
3e508034
LB		 1280 temp += 31999999;
1281 do_div(temp, 64000000);
1282
1283 if (temp > 0x3fff)
1284 temp = 0x3fff;
1285
1286 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1287}
1288
1289
c9df406f 1290/* ethtool ******************************************************************/
e5371493 1291struct mv643xx_eth_stats {
c9df406f
LB		 1292 char stat_string[ETH_GSTRING_LEN];
1293 int sizeof_stat;
16820054
LB		 1294 int netdev_off;
1295 int mp_off;
c9df406f
LB		 1296};
1297
16820054
LB		 1298#define SSTAT(m) \
1299 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1300 offsetof(struct net_device, stats.m), -1 }
1301
1302#define MIBSTAT(m) \
1303 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1304 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1305
eaf5d590
LB		 1306#define LROSTAT(m) \
1307 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1308 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1309
16820054
LB		 1310static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1311 SSTAT(rx_packets),
1312 SSTAT(tx_packets),
1313 SSTAT(rx_bytes),
1314 SSTAT(tx_bytes),
1315 SSTAT(rx_errors),
1316 SSTAT(tx_errors),
1317 SSTAT(rx_dropped),
1318 SSTAT(tx_dropped),
1319 MIBSTAT(good_octets_received),
1320 MIBSTAT(bad_octets_received),
1321 MIBSTAT(internal_mac_transmit_err),
1322 MIBSTAT(good_frames_received),
1323 MIBSTAT(bad_frames_received),
1324 MIBSTAT(broadcast_frames_received),
1325 MIBSTAT(multicast_frames_received),
1326 MIBSTAT(frames_64_octets),
1327 MIBSTAT(frames_65_to_127_octets),
1328 MIBSTAT(frames_128_to_255_octets),
1329 MIBSTAT(frames_256_to_511_octets),
1330 MIBSTAT(frames_512_to_1023_octets),
1331 MIBSTAT(frames_1024_to_max_octets),
1332 MIBSTAT(good_octets_sent),
1333 MIBSTAT(good_frames_sent),
1334 MIBSTAT(excessive_collision),
1335 MIBSTAT(multicast_frames_sent),
1336 MIBSTAT(broadcast_frames_sent),
1337 MIBSTAT(unrec_mac_control_received),
1338 MIBSTAT(fc_sent),
1339 MIBSTAT(good_fc_received),
1340 MIBSTAT(bad_fc_received),
1341 MIBSTAT(undersize_received),
1342 MIBSTAT(fragments_received),
1343 MIBSTAT(oversize_received),
1344 MIBSTAT(jabber_received),
1345 MIBSTAT(mac_receive_error),
1346 MIBSTAT(bad_crc_event),
1347 MIBSTAT(collision),
1348 MIBSTAT(late_collision),
302476c9
PZ		 1349 MIBSTAT(rx_discard),
1350 MIBSTAT(rx_overrun),
eaf5d590
LB		 1351 LROSTAT(lro_aggregated),
1352 LROSTAT(lro_flushed),
1353 LROSTAT(lro_no_desc),
c9df406f
LB		 1354};
1355
10a9948d 1356static int
6bdf576e
LB		 1357mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1358 struct ethtool_cmd *cmd)
d0412d96 1359{
d0412d96
JC		 1360 int err;
1361
ed94493f
LB		 1362 err = phy_read_status(mp->phy);
1363 if (err == 0)
1364 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1365
fc32b0e2
LB		 1366 /*
1367 * The MAC does not support 1000baseT_Half.
1368 */
d0412d96
JC		 1369 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1370 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1371
1372 return err;
1373}
1374
10a9948d 1375static int
6bdf576e 1376mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1377 struct ethtool_cmd *cmd)
bedfe324 1378{
81600eea
LB		 1379 u32 port_status;
1380
37a6084f 1381 port_status = rdlp(mp, PORT_STATUS);
81600eea 1382
bedfe324
LB		 1383 cmd->supported = SUPPORTED_MII;
1384 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1385 switch (port_status & PORT_SPEED_MASK) {
1386 case PORT_SPEED_10:
70739497 1387 ethtool_cmd_speed_set(cmd, SPEED_10);
81600eea
LB		 1388 break;
1389 case PORT_SPEED_100:
70739497 1390 ethtool_cmd_speed_set(cmd, SPEED_100);
81600eea
LB		 1391 break;
1392 case PORT_SPEED_1000:
70739497 1393 ethtool_cmd_speed_set(cmd, SPEED_1000);
81600eea
LB		 1394 break;
1395 default:
1396 cmd->speed = -1;
1397 break;
1398 }
1399 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1400 cmd->port = PORT_MII;
1401 cmd->phy_address = 0;
1402 cmd->transceiver = XCVR_INTERNAL;
1403 cmd->autoneg = AUTONEG_DISABLE;
1404 cmd->maxtxpkt = 1;
1405 cmd->maxrxpkt = 1;
1406
1407 return 0;
1408}
1409
3871c387
MS		 1410static void
1411mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1412{
1413 struct mv643xx_eth_private *mp = netdev_priv(dev);
1414 wol->supported = 0;
1415 wol->wolopts = 0;
1416 if (mp->phy)
1417 phy_ethtool_get_wol(mp->phy, wol);
1418}
1419
1420static int
1421mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1422{
1423 struct mv643xx_eth_private *mp = netdev_priv(dev);
1424 int err;
1425
1426 if (mp->phy == NULL)
1427 return -EOPNOTSUPP;
1428
1429 err = phy_ethtool_set_wol(mp->phy, wol);
1430 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1431 * this debugging hint is useful to have.
1432 */
1433 if (err == -EOPNOTSUPP)
1434 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1435 return err;
1436}
1437
6bdf576e
LB		 1438static int
1439mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1440{
1441 struct mv643xx_eth_private *mp = netdev_priv(dev);
1442
1443 if (mp->phy != NULL)
1444 return mv643xx_eth_get_settings_phy(mp, cmd);
1445 else
1446 return mv643xx_eth_get_settings_phyless(mp, cmd);
1447}
1448
10a9948d
LB		 1449static int
1450mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1451{
e5371493 1452 struct mv643xx_eth_private *mp = netdev_priv(dev);
260055bb 1453 int ret;
ab4384a6 1454
6bdf576e
LB		 1455 if (mp->phy == NULL)
1456 return -EINVAL;
1457
fc32b0e2
LB		 1458 /*
1459 * The MAC does not support 1000baseT_Half.
1460 */
1461 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1462
260055bb
PS		 1463 ret = phy_ethtool_sset(mp->phy, cmd);
1464 if (!ret)
1465 mv643xx_adjust_pscr(mp);
1466 return ret;
c9df406f 1467}
1da177e4 1468
fc32b0e2
LB		 1469static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1470 struct ethtool_drvinfo *drvinfo)
c9df406f 1471{
6f39da2c
AL		 1472 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1473 sizeof(drvinfo->driver));
68aad78c 1474 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
6f39da2c
AL		 1475 sizeof(drvinfo->version));
1476 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1477 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
16820054 1478 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1479}
1da177e4 1480
fc32b0e2 1481static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1482{
e5371493 1483 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1484
6bdf576e
LB		 1485 if (mp->phy == NULL)
1486 return -EINVAL;
1da177e4 1487
6bdf576e 1488 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1489}
1490
3e508034
LB		 1491static int
1492mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1493{
1494 struct mv643xx_eth_private *mp = netdev_priv(dev);
1495
1496 ec->rx_coalesce_usecs = get_rx_coal(mp);
1497 ec->tx_coalesce_usecs = get_tx_coal(mp);
1498
1499 return 0;
1500}
1501
1502static int
1503mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1504{
1505 struct mv643xx_eth_private *mp = netdev_priv(dev);
1506
1507 set_rx_coal(mp, ec->rx_coalesce_usecs);
1508 set_tx_coal(mp, ec->tx_coalesce_usecs);
1509
1510 return 0;
1511}
1512
e7d2f4db
LB		 1513static void
1514mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1515{
1516 struct mv643xx_eth_private *mp = netdev_priv(dev);
1517
1518 er->rx_max_pending = 4096;
1519 er->tx_max_pending = 4096;
e7d2f4db
LB		 1520
1521 er->rx_pending = mp->rx_ring_size;
1522 er->tx_pending = mp->tx_ring_size;
e7d2f4db
LB		 1523}
1524
1525static int
1526mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1527{
1528 struct mv643xx_eth_private *mp = netdev_priv(dev);
1529
1530 if (er->rx_mini_pending || er->rx_jumbo_pending)
1531 return -EINVAL;
1532
1533 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1534 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1535
1536 if (netif_running(dev)) {
1537 mv643xx_eth_stop(dev);
1538 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 1539 netdev_err(dev,
1540 "fatal error on re-opening device after ring param change\n");
e7d2f4db
LB		 1541 return -ENOMEM;
1542 }
1543 }
1544
1545 return 0;
1546}
1547
d888b373
LB		 1548
1549static int
c8f44aff 1550mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
d888b373
LB		 1551{
1552 struct mv643xx_eth_private *mp = netdev_priv(dev);
3ad9b358 1553 bool rx_csum = features & NETIF_F_RXCSUM;
d888b373
LB		 1554
1555 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1556
1557 return 0;
1558}
1559
fc32b0e2
LB		 1560static void mv643xx_eth_get_strings(struct net_device *dev,
1561 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1562{
1563 int i;
1da177e4 1564
fc32b0e2
LB		 1565 if (stringset == ETH_SS_STATS) {
1566 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1567 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1568 mv643xx_eth_stats[i].stat_string,
e5371493 1569 ETH_GSTRING_LEN);
c9df406f 1570 }
c9df406f
LB		 1571 }
1572}
1da177e4 1573
fc32b0e2
LB		 1574static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1575 struct ethtool_stats *stats,
1576 uint64_t *data)
c9df406f 1577{
b9873841 1578 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1579 int i;
1da177e4 1580
8fd89211 1581 mv643xx_eth_get_stats(dev);
fc32b0e2 1582 mib_counters_update(mp);
eaf5d590 1583 mv643xx_eth_grab_lro_stats(mp);
1da177e4 1584
16820054
LB		 1585 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1586 const struct mv643xx_eth_stats *stat;
1587 void *p;
1588
1589 stat = mv643xx_eth_stats + i;
1590
1591 if (stat->netdev_off >= 0)
1592 p = ((void *)mp->dev) + stat->netdev_off;
1593 else
1594 p = ((void *)mp) + stat->mp_off;
1595
1596 data[i] = (stat->sizeof_stat == 8) ?
1597 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1598 }
c9df406f 1599}
1da177e4 1600
fc32b0e2 1601static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1602{
fc32b0e2 1603 if (sset == ETH_SS_STATS)
16820054 1604 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1605
1606 return -EOPNOTSUPP;
c9df406f 1607}
1da177e4 1608
e5371493 1609static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1610 .get_settings = mv643xx_eth_get_settings,
1611 .set_settings = mv643xx_eth_set_settings,
1612 .get_drvinfo = mv643xx_eth_get_drvinfo,
1613 .nway_reset = mv643xx_eth_nway_reset,
ed4ba4b5 1614 .get_link = ethtool_op_get_link,
3e508034
LB		 1615 .get_coalesce = mv643xx_eth_get_coalesce,
1616 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1617 .get_ringparam = mv643xx_eth_get_ringparam,
1618 .set_ringparam = mv643xx_eth_set_ringparam,
fc32b0e2
LB		 1619 .get_strings = mv643xx_eth_get_strings,
1620 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1621 .get_sset_count = mv643xx_eth_get_sset_count,
ebad0a8d 1622 .get_ts_info = ethtool_op_get_ts_info,
3871c387
MS		 1623 .get_wol = mv643xx_eth_get_wol,
1624 .set_wol = mv643xx_eth_set_wol,
c9df406f 1625};
1da177e4 1626
bea3348e 1627
c9df406f 1628/* address handling *********************************************************/
5daffe94 1629static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1630{
66e63ffb
LB		 1631 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1632 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1633
5daffe94
LB		 1634 addr[0] = (mac_h >> 24) & 0xff;
1635 addr[1] = (mac_h >> 16) & 0xff;
1636 addr[2] = (mac_h >> 8) & 0xff;
1637 addr[3] = mac_h & 0xff;
1638 addr[4] = (mac_l >> 8) & 0xff;
1639 addr[5] = mac_l & 0xff;
c9df406f 1640}
1da177e4 1641
66e63ffb 1642static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1643{
66e63ffb
LB		 1644 wrlp(mp, MAC_ADDR_HIGH,
1645 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1646 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1647}
d0412d96 1648
66e63ffb 1649static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1650{
ccffad25 1651 struct netdev_hw_addr *ha;
66e63ffb 1652 u32 nibbles;
1da177e4 1653
66e63ffb
LB		 1654 if (dev->flags & IFF_PROMISC)
1655 return 0;
1da177e4 1656
66e63ffb 1657 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
32e7bfc4 1658 netdev_for_each_uc_addr(ha, dev) {
ccffad25 1659 if (memcmp(dev->dev_addr, ha->addr, 5))
66e63ffb 1660 return 0;
ccffad25 1661 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
66e63ffb 1662 return 0;
ff561eef 1663
ccffad25 1664 nibbles |= 1 << (ha->addr[5] & 0x0f);
66e63ffb 1665 }
1da177e4 1666
66e63ffb 1667 return nibbles;
1da177e4
LT		 1668}
1669
66e63ffb 1670static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1671{
e5371493 1672 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1673 u32 port_config;
1674 u32 nibbles;
1675 int i;
1da177e4 1676
cc9754b3 1677 uc_addr_set(mp, dev->dev_addr);
1da177e4 1678
6877f54e
PS		 1679 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1680
66e63ffb
LB		 1681 nibbles = uc_addr_filter_mask(dev);
1682 if (!nibbles) {
1683 port_config |= UNICAST_PROMISCUOUS_MODE;
6877f54e 1684 nibbles = 0xffff;
66e63ffb
LB		 1685 }
1686
1687 for (i = 0; i < 16; i += 4) {
1688 int off = UNICAST_TABLE(mp->port_num) + i;
1689 u32 v;
1690
1691 v = 0;
1692 if (nibbles & 1)
1693 v |= 0x00000001;
1694 if (nibbles & 2)
1695 v |= 0x00000100;
1696 if (nibbles & 4)
1697 v |= 0x00010000;
1698 if (nibbles & 8)
1699 v |= 0x01000000;
1700 nibbles >>= 4;
1701
1702 wrl(mp, off, v);
1703 }
1704
66e63ffb 1705 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1706}
1707
69876569
LB		 1708static int addr_crc(unsigned char *addr)
1709{
1710 int crc = 0;
1711 int i;
1712
1713 for (i = 0; i < 6; i++) {
1714 int j;
1715
1716 crc = (crc ^ addr[i]) << 8;
1717 for (j = 7; j >= 0; j--) {
1718 if (crc & (0x100 << j))
1719 crc ^= 0x107 << j;
1720 }
1721 }
1722
1723 return crc;
1724}
1725
66e63ffb 1726static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1727{
fc32b0e2 1728 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1729 u32 *mc_spec;
1730 u32 *mc_other;
22bedad3 1731 struct netdev_hw_addr *ha;
fc32b0e2 1732 int i;
c8aaea25 1733
fc32b0e2 1734 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1735 int port_num;
1736 u32 accept;
c8aaea25 1737
66e63ffb
LB		 1738oom:
1739 port_num = mp->port_num;
1740 accept = 0x01010101;
fc32b0e2
LB		 1741 for (i = 0; i < 0x100; i += 4) {
1742 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1743 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1744 }
1745 return;
1746 }
c8aaea25 1747
82a5bd6a 1748 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1749 if (mc_spec == NULL)
1750 goto oom;
1751 mc_other = mc_spec + (0x100 >> 2);
1752
1753 memset(mc_spec, 0, 0x100);
1754 memset(mc_other, 0, 0x100);
1da177e4 1755
22bedad3
JP		 1756 netdev_for_each_mc_addr(ha, dev) {
1757 u8 *a = ha->addr;
66e63ffb
LB		 1758 u32 *table;
1759 int entry;
1da177e4 1760
fc32b0e2 1761 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1762 table = mc_spec;
1763 entry = a[5];
fc32b0e2 1764 } else {
66e63ffb
LB		 1765 table = mc_other;
1766 entry = addr_crc(a);
fc32b0e2 1767 }
66e63ffb 1768
2b448334 1769 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1770 }
66e63ffb
LB		 1771
1772 for (i = 0; i < 0x100; i += 4) {
1773 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1774 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1775 }
1776
1777 kfree(mc_spec);
1778}
1779
1780static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1781{
1782 mv643xx_eth_program_unicast_filter(dev);
1783 mv643xx_eth_program_multicast_filter(dev);
1784}
1785
1786static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1787{
1788 struct sockaddr *sa = addr;
1789
a29ec08a 1790 if (!is_valid_ether_addr(sa->sa_data))
504f9b5a 1791 return -EADDRNOTAVAIL;
a29ec08a 1792
66e63ffb
LB		 1793 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1794
1795 netif_addr_lock_bh(dev);
1796 mv643xx_eth_program_unicast_filter(dev);
1797 netif_addr_unlock_bh(dev);
1798
1799 return 0;
c9df406f 1800}
c8aaea25 1801
c8aaea25 1802
c9df406f 1803/* rx/tx queue initialisation ***********************************************/
64da80a2 1804static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1805{
64da80a2 1806 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1807 struct rx_desc *rx_desc;
1808 int size;
c9df406f
LB		 1809 int i;
1810
64da80a2
LB		 1811 rxq->index = index;
1812
e7d2f4db 1813 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1814
1815 rxq->rx_desc_count = 0;
1816 rxq->rx_curr_desc = 0;
1817 rxq->rx_used_desc = 0;
1818
1819 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1820
f7981c1c 1821 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1822 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1823 mp->rx_desc_sram_size);
1824 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1825 } else {
eb0519b5
GP		 1826 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1827 size, &rxq->rx_desc_dma,
1828 GFP_KERNEL);
f7ea3337
PJ		 1829 }
1830
8a578111 1831 if (rxq->rx_desc_area == NULL) {
7542db8b 1832 netdev_err(mp->dev,
8a578111
LB		 1833 "can't allocate rx ring (%d bytes)\n", size);
1834 goto out;
1835 }
1836 memset(rxq->rx_desc_area, 0, size);
1da177e4 1837
8a578111 1838 rxq->rx_desc_area_size = size;
b2adaca9
JP		 1839 rxq->rx_skb = kmalloc_array(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1840 GFP_KERNEL);
1841 if (rxq->rx_skb == NULL)
8a578111 1842 goto out_free;
8a578111 1843
64699336 1844 rx_desc = rxq->rx_desc_area;
8a578111 1845 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1846 int nexti;
1847
1848 nexti = i + 1;
1849 if (nexti == rxq->rx_ring_size)
1850 nexti = 0;
1851
8a578111
LB		 1852 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1853 nexti * sizeof(struct rx_desc);
1854 }
1855
eaf5d590
LB		 1856 rxq->lro_mgr.dev = mp->dev;
1857 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1858 rxq->lro_mgr.features = LRO_F_NAPI;
1859 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1860 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1861 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1862 rxq->lro_mgr.max_aggr = 32;
1863 rxq->lro_mgr.frag_align_pad = 0;
1864 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1865 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1866
1867 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
eaf5d590 1868
8a578111
LB		 1869 return 0;
1870
1871
1872out_free:
f7981c1c 1873 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1874 iounmap(rxq->rx_desc_area);
1875 else
eb0519b5 1876 dma_free_coherent(mp->dev->dev.parent, size,
8a578111
LB		 1877 rxq->rx_desc_area,
1878 rxq->rx_desc_dma);
1879
1880out:
1881 return -ENOMEM;
c9df406f 1882}
c8aaea25 1883
8a578111 1884static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1885{
8a578111
LB		 1886 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1887 int i;
1888
1889 rxq_disable(rxq);
c8aaea25 1890
8a578111
LB		 1891 for (i = 0; i < rxq->rx_ring_size; i++) {
1892 if (rxq->rx_skb[i]) {
1893 dev_kfree_skb(rxq->rx_skb[i]);
1894 rxq->rx_desc_count--;
1da177e4 1895 }
c8aaea25 1896 }
1da177e4 1897
8a578111 1898 if (rxq->rx_desc_count) {
7542db8b 1899 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
8a578111
LB		 1900 rxq->rx_desc_count);
1901 }
1902
f7981c1c 1903 if (rxq->index == 0 &&
64da80a2 1904 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1905 iounmap(rxq->rx_desc_area);
c9df406f 1906 else
eb0519b5 1907 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
8a578111
LB		 1908 rxq->rx_desc_area, rxq->rx_desc_dma);
1909
1910 kfree(rxq->rx_skb);
c9df406f 1911}
1da177e4 1912
3d6b35bc 1913static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1914{
3d6b35bc 1915 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1916 struct tx_desc *tx_desc;
1917 int size;
c9df406f 1918 int i;
1da177e4 1919
3d6b35bc
LB		 1920 txq->index = index;
1921
e7d2f4db 1922 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 1923
1924 txq->tx_desc_count = 0;
1925 txq->tx_curr_desc = 0;
1926 txq->tx_used_desc = 0;
1927
1928 size = txq->tx_ring_size * sizeof(struct tx_desc);
1929
f7981c1c 1930 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1931 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1932 mp->tx_desc_sram_size);
1933 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1934 } else {
eb0519b5
GP		 1935 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1936 size, &txq->tx_desc_dma,
1937 GFP_KERNEL);
13d64285
LB		 1938 }
1939
1940 if (txq->tx_desc_area == NULL) {
7542db8b 1941 netdev_err(mp->dev,
13d64285 1942 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1943 return -ENOMEM;
c9df406f 1944 }
13d64285
LB		 1945 memset(txq->tx_desc_area, 0, size);
1946
1947 txq->tx_desc_area_size = size;
13d64285 1948
64699336 1949 tx_desc = txq->tx_desc_area;
13d64285 1950 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1951 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1952 int nexti;
1953
1954 nexti = i + 1;
1955 if (nexti == txq->tx_ring_size)
1956 nexti = 0;
6b368f68
LB		 1957
1958 txd->cmd_sts = 0;
1959 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1960 nexti * sizeof(struct tx_desc);
1961 }
1962
99ab08e0 1963 skb_queue_head_init(&txq->tx_skb);
c9df406f 1964
99ab08e0 1965 return 0;
c8aaea25 1966}
1da177e4 1967
13d64285 1968static void txq_deinit(struct tx_queue *txq)
c9df406f 1969{
13d64285 1970 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1971
13d64285 1972 txq_disable(txq);
1fa38c58 1973 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1974
13d64285 1975 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1976
f7981c1c 1977 if (txq->index == 0 &&
3d6b35bc 1978 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1979 iounmap(txq->tx_desc_area);
c9df406f 1980 else
eb0519b5 1981 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
13d64285 1982 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1983}
1da177e4 1984
1da177e4 1985
c9df406f 1986/* netdev ops and related ***************************************************/
1fa38c58
LB		 1987static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1988{
1989 u32 int_cause;
1990 u32 int_cause_ext;
1991
e0ca8410 1992 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1fa38c58
LB		 1993 if (int_cause == 0)
1994 return 0;
1995
1996 int_cause_ext = 0;
e0ca8410
SB		 1997 if (int_cause & INT_EXT) {
1998 int_cause &= ~INT_EXT;
37a6084f 1999 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
e0ca8410 2000 }
1fa38c58 2001
1fa38c58 2002 if (int_cause) {
37a6084f 2003 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2004 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2005 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2006 mp->work_rx |= (int_cause & INT_RX) >> 2;
2007 }
2008
2009 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2010 if (int_cause_ext) {
37a6084f 2011 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2012 if (int_cause_ext & INT_EXT_LINK_PHY)
2013 mp->work_link = 1;
2014 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2015 }
2016
2017 return 1;
2018}
2019
2020static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2021{
2022 struct net_device *dev = (struct net_device *)dev_id;
2023 struct mv643xx_eth_private *mp = netdev_priv(dev);
2024
2025 if (unlikely(!mv643xx_eth_collect_events(mp)))
2026 return IRQ_NONE;
2027
37a6084f 2028 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2029 napi_schedule(&mp->napi);
2030
2031 return IRQ_HANDLED;
2032}
2033
2f7eb47a
LB		 2034static void handle_link_event(struct mv643xx_eth_private *mp)
2035{
2036 struct net_device *dev = mp->dev;
2037 u32 port_status;
2038 int speed;
2039 int duplex;
2040 int fc;
2041
37a6084f 2042 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2043 if (!(port_status & LINK_UP)) {
2044 if (netif_carrier_ok(dev)) {
2045 int i;
2046
7542db8b 2047 netdev_info(dev, "link down\n");
2f7eb47a
LB		 2048
2049 netif_carrier_off(dev);
2f7eb47a 2050
f7981c1c 2051 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2052 struct tx_queue *txq = mp->txq + i;
2053
1fa38c58 2054 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2055 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2056 }
2057 }
2058 return;
2059 }
2060
2061 switch (port_status & PORT_SPEED_MASK) {
2062 case PORT_SPEED_10:
2063 speed = 10;
2064 break;
2065 case PORT_SPEED_100:
2066 speed = 100;
2067 break;
2068 case PORT_SPEED_1000:
2069 speed = 1000;
2070 break;
2071 default:
2072 speed = -1;
2073 break;
2074 }
2075 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2076 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2077
7542db8b
JP		 2078 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2079 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2f7eb47a 2080
4fdeca3f 2081 if (!netif_carrier_ok(dev))
2f7eb47a 2082 netif_carrier_on(dev);
2f7eb47a
LB		 2083}
2084
1fa38c58 2085static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2086{
1fa38c58
LB		 2087 struct mv643xx_eth_private *mp;
2088 int work_done;
ce4e2e45 2089
1fa38c58 2090 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2091
1319ebad
LB		 2092 if (unlikely(mp->oom)) {
2093 mp->oom = 0;
2094 del_timer(&mp->rx_oom);
2095 }
1da177e4 2096
1fa38c58
LB		 2097 work_done = 0;
2098 while (work_done < budget) {
2099 u8 queue_mask;
2100 int queue;
2101 int work_tbd;
2102
2103 if (mp->work_link) {
2104 mp->work_link = 0;
2105 handle_link_event(mp);
26ef1f17 2106 work_done++;
1fa38c58
LB		 2107 continue;
2108 }
1da177e4 2109
1319ebad
LB		 2110 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2111 if (likely(!mp->oom))
2112 queue_mask |= mp->work_rx_refill;
2113
1fa38c58
LB		 2114 if (!queue_mask) {
2115 if (mv643xx_eth_collect_events(mp))
2116 continue;
2117 break;
2118 }
1da177e4 2119
1fa38c58
LB		 2120 queue = fls(queue_mask) - 1;
2121 queue_mask = 1 << queue;
2122
2123 work_tbd = budget - work_done;
2124 if (work_tbd > 16)
2125 work_tbd = 16;
2126
2127 if (mp->work_tx_end & queue_mask) {
2128 txq_kick(mp->txq + queue);
2129 } else if (mp->work_tx & queue_mask) {
2130 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2131 txq_maybe_wake(mp->txq + queue);
2132 } else if (mp->work_rx & queue_mask) {
2133 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2134 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2135 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2136 } else {
2137 BUG();
2138 }
84dd619e 2139 }
fc32b0e2 2140
1fa38c58 2141 if (work_done < budget) {
1319ebad 2142 if (mp->oom)
1fa38c58
LB		 2143 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2144 napi_complete(napi);
e0ca8410 2145 wrlp(mp, INT_MASK, mp->int_mask);
226bb6b7 2146 }
3d6b35bc 2147
1fa38c58
LB		 2148 return work_done;
2149}
8fa89bf5 2150
1fa38c58
LB		 2151static inline void oom_timer_wrapper(unsigned long data)
2152{
2153 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2154
1fa38c58 2155 napi_schedule(&mp->napi);
1da177e4
LT		 2156}
2157
e5371493 2158static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2159{
45c5d3bc
LB		 2160 int data;
2161
ed94493f 2162 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2163 if (data < 0)
2164 return;
1da177e4 2165
7f106c1d 2166 data |= BMCR_RESET;
ed94493f 2167 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2168 return;
1da177e4 2169
c9df406f 2170 do {
ed94493f 2171 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2172 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2173}
2174
fc32b0e2 2175static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2176{
d0412d96 2177 u32 pscr;
8a578111 2178 int i;
1da177e4 2179
bedfe324
LB		 2180 /*
2181 * Perform PHY reset, if there is a PHY.
2182 */
ed94493f 2183 if (mp->phy != NULL) {
bedfe324
LB		 2184 struct ethtool_cmd cmd;
2185
2186 mv643xx_eth_get_settings(mp->dev, &cmd);
2187 phy_reset(mp);
2188 mv643xx_eth_set_settings(mp->dev, &cmd);
2189 }
1da177e4 2190
81600eea
LB		 2191 /*
2192 * Configure basic link parameters.
2193 */
37a6084f 2194 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2195
2196 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2197 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2198
2199 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2200 if (mp->phy == NULL)
81600eea 2201 pscr |= FORCE_LINK_PASS;
37a6084f 2202 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2203
13d64285
LB		 2204 /*
2205 * Configure TX path and queues.
2206 */
89df5fdc 2207 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2208 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2209 struct tx_queue *txq = mp->txq + i;
13d64285 2210
6b368f68 2211 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2212 txq_set_rate(txq, 1000000000, 16777216);
2213 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2214 }
2215
d9a073ea
LB		 2216 /*
2217 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2218 * frames to RX queue #0, and include the pseudo-header when
2219 * calculating receive checksums.
d9a073ea 2220 */
e138f96b 2221 mv643xx_eth_set_features(mp->dev, mp->dev->features);
01999873 2222
376489a2
LB		 2223 /*
2224 * Treat BPDUs as normal multicasts, and disable partition mode.
2225 */
37a6084f 2226 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2227
5a893922
LB		 2228 /*
2229 * Add configured unicast addresses to address filter table.
2230 */
2231 mv643xx_eth_program_unicast_filter(mp->dev);
2232
8a578111 2233 /*
64da80a2 2234 * Enable the receive queues.
8a578111 2235 */
f7981c1c 2236 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2237 struct rx_queue *rxq = mp->rxq + i;
8a578111 2238 u32 addr;
1da177e4 2239
8a578111
LB		 2240 addr = (u32)rxq->rx_desc_dma;
2241 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2242 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2243
8a578111
LB		 2244 rxq_enable(rxq);
2245 }
1da177e4
LT		 2246}
2247
2bcb4b0f
LB		 2248static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2249{
2250 int skb_size;
2251
2252 /*
2253 * Reserve 2+14 bytes for an ethernet header (the hardware
2254 * automatically prepends 2 bytes of dummy data to each
2255 * received packet), 16 bytes for up to four VLAN tags, and
2256 * 4 bytes for the trailing FCS -- 36 bytes total.
2257 */
2258 skb_size = mp->dev->mtu + 36;
2259
2260 /*
2261 * Make sure that the skb size is a multiple of 8 bytes, as
2262 * the lower three bits of the receive descriptor's buffer
2263 * size field are ignored by the hardware.
2264 */
2265 mp->skb_size = (skb_size + 7) & ~7;
7fd96ce4
LB		 2266
2267 /*
2268 * If NET_SKB_PAD is smaller than a cache line,
2269 * netdev_alloc_skb() will cause skb->data to be misaligned
2270 * to a cache line boundary. If this is the case, include
2271 * some extra space to allow re-aligning the data area.
2272 */
2273 mp->skb_size += SKB_DMA_REALIGN;
2bcb4b0f
LB		 2274}
2275
c9df406f 2276static int mv643xx_eth_open(struct net_device *dev)
16e03018 2277{
e5371493 2278 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2279 int err;
64da80a2 2280 int i;
16e03018 2281
37a6084f
LB		 2282 wrlp(mp, INT_CAUSE, 0);
2283 wrlp(mp, INT_CAUSE_EXT, 0);
2284 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2285
fc32b0e2 2286 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2287 IRQF_SHARED, dev->name, dev);
c9df406f 2288 if (err) {
7542db8b 2289 netdev_err(dev, "can't assign irq\n");
c9df406f 2290 return -EAGAIN;
16e03018
DF		 2291 }
2292
2bcb4b0f
LB		 2293 mv643xx_eth_recalc_skb_size(mp);
2294
2257e05c
LB		 2295 napi_enable(&mp->napi);
2296
e0ca8410
SB		 2297 mp->int_mask = INT_EXT;
2298
f7981c1c 2299 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2300 err = rxq_init(mp, i);
2301 if (err) {
2302 while (--i >= 0)
f7981c1c 2303 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2304 goto out;
2305 }
2306
1fa38c58 2307 rxq_refill(mp->rxq + i, INT_MAX);
e0ca8410 2308 mp->int_mask |= INT_RX_0 << i;
2257e05c
LB		 2309 }
2310
1319ebad 2311 if (mp->oom) {
2257e05c
LB		 2312 mp->rx_oom.expires = jiffies + (HZ / 10);
2313 add_timer(&mp->rx_oom);
64da80a2 2314 }
8a578111 2315
f7981c1c 2316 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2317 err = txq_init(mp, i);
2318 if (err) {
2319 while (--i >= 0)
f7981c1c 2320 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2321 goto out_free;
2322 }
e0ca8410 2323 mp->int_mask |= INT_TX_END_0 << i;
3d6b35bc 2324 }
16e03018 2325
fc32b0e2 2326 port_start(mp);
16e03018 2327
37a6084f 2328 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
e0ca8410 2329 wrlp(mp, INT_MASK, mp->int_mask);
16e03018 2330
c9df406f
LB		 2331 return 0;
2332
13d64285 2333
fc32b0e2 2334out_free:
f7981c1c
LB		 2335 for (i = 0; i < mp->rxq_count; i++)
2336 rxq_deinit(mp->rxq + i);
fc32b0e2 2337out:
c9df406f
LB		 2338 free_irq(dev->irq, dev);
2339
2340 return err;
16e03018
DF		 2341}
2342
e5371493 2343static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2344{
fc32b0e2 2345 unsigned int data;
64da80a2 2346 int i;
1da177e4 2347
f7981c1c
LB		 2348 for (i = 0; i < mp->rxq_count; i++)
2349 rxq_disable(mp->rxq + i);
2350 for (i = 0; i < mp->txq_count; i++)
2351 txq_disable(mp->txq + i);
ae9ae064
LB		 2352
2353 while (1) {
37a6084f 2354 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2355
2356 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2357 break;
13d64285 2358 udelay(10);
ae9ae064 2359 }
1da177e4 2360
c9df406f 2361 /* Reset the Enable bit in the Configuration Register */
37a6084f 2362 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2363 data &= ~(SERIAL_PORT_ENABLE |
2364 DO_NOT_FORCE_LINK_FAIL |
2365 FORCE_LINK_PASS);
37a6084f 2366 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2367}
2368
c9df406f 2369static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2370{
e5371493 2371 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2372 int i;
1da177e4 2373
fe65e704 2374 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2375 wrlp(mp, INT_MASK, 0x00000000);
2376 rdlp(mp, INT_MASK);
1da177e4 2377
c9df406f 2378 napi_disable(&mp->napi);
78fff83b 2379
2257e05c
LB		 2380 del_timer_sync(&mp->rx_oom);
2381
c9df406f 2382 netif_carrier_off(dev);
1da177e4 2383
fc32b0e2
LB		 2384 free_irq(dev->irq, dev);
2385
cc9754b3 2386 port_reset(mp);
8fd89211 2387 mv643xx_eth_get_stats(dev);
fc32b0e2 2388 mib_counters_update(mp);
57e8f26a 2389 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2390
f7981c1c
LB		 2391 for (i = 0; i < mp->rxq_count; i++)
2392 rxq_deinit(mp->rxq + i);
2393 for (i = 0; i < mp->txq_count; i++)
2394 txq_deinit(mp->txq + i);
1da177e4 2395
c9df406f 2396 return 0;
1da177e4
LT		 2397}
2398
fc32b0e2 2399static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2400{
e5371493 2401 struct mv643xx_eth_private *mp = netdev_priv(dev);
260055bb 2402 int ret;
1da177e4 2403
260055bb
PS		 2404 if (mp->phy == NULL)
2405 return -ENOTSUPP;
bedfe324 2406
260055bb
PS		 2407 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2408 if (!ret)
2409 mv643xx_adjust_pscr(mp);
2410 return ret;
1da177e4
LT		 2411}
2412
c9df406f 2413static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2414{
89df5fdc
LB		 2415 struct mv643xx_eth_private *mp = netdev_priv(dev);
2416
fc32b0e2 2417 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2418 return -EINVAL;
1da177e4 2419
c9df406f 2420 dev->mtu = new_mtu;
2bcb4b0f 2421 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2422 tx_set_rate(mp, 1000000000, 16777216);
2423
c9df406f
LB		 2424 if (!netif_running(dev))
2425 return 0;
1da177e4 2426
c9df406f
LB		 2427 /*
2428 * Stop and then re-open the interface. This will allocate RX
2429 * skbs of the new MTU.
2430 * There is a possible danger that the open will not succeed,
fc32b0e2 2431 * due to memory being full.
c9df406f
LB		 2432 */
2433 mv643xx_eth_stop(dev);
2434 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 2435 netdev_err(dev,
2436 "fatal error on re-opening device after MTU change\n");
c9df406f
LB		 2437 }
2438
2439 return 0;
1da177e4
LT		 2440}
2441
fc32b0e2 2442static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2443{
fc32b0e2 2444 struct mv643xx_eth_private *mp;
1da177e4 2445
fc32b0e2
LB		 2446 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2447 if (netif_running(mp->dev)) {
e5ef1de1 2448 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2449 port_reset(mp);
2450 port_start(mp);
e5ef1de1 2451 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2452 }
c9df406f
LB		 2453}
2454
c9df406f 2455static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2456{
e5371493 2457 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2458
7542db8b 2459 netdev_info(dev, "tx timeout\n");
d0412d96 2460
c9df406f 2461 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2462}
2463
c9df406f 2464#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2465static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2466{
fc32b0e2 2467 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2468
37a6084f
LB		 2469 wrlp(mp, INT_MASK, 0x00000000);
2470 rdlp(mp, INT_MASK);
c9df406f 2471
fc32b0e2 2472 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2473
e0ca8410 2474 wrlp(mp, INT_MASK, mp->int_mask);
9f8dd319 2475}
c9df406f 2476#endif
9f8dd319 2477
9f8dd319 2478
c9df406f 2479/* platform glue ************************************************************/
e5371493
LB		 2480static void
2481mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
63a9332b 2482 const struct mbus_dram_target_info *dram)
c9df406f 2483{
cc9754b3 2484 void __iomem *base = msp->base;
c9df406f
LB		 2485 u32 win_enable;
2486 u32 win_protect;
2487 int i;
9f8dd319 2488
c9df406f
LB		 2489 for (i = 0; i < 6; i++) {
2490 writel(0, base + WINDOW_BASE(i));
2491 writel(0, base + WINDOW_SIZE(i));
2492 if (i < 4)
2493 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2494 }
2495
c9df406f
LB		 2496 win_enable = 0x3f;
2497 win_protect = 0;
2498
2499 for (i = 0; i < dram->num_cs; i++) {
63a9332b 2500 const struct mbus_dram_window *cs = dram->cs + i;
c9df406f
LB		 2501
2502 writel((cs->base & 0xffff0000) |
2503 (cs->mbus_attr << 8) |
2504 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2505 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2506
2507 win_enable &= ~(1 << i);
2508 win_protect |= 3 << (2 * i);
2509 }
2510
2511 writel(win_enable, base + WINDOW_BAR_ENABLE);
2512 msp->win_protect = win_protect;
9f8dd319
DF		 2513}
2514
773fc3ee
LB		 2515static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2516{
2517 /*
2518 * Check whether we have a 14-bit coal limit field in bits
2519 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2520 * SDMA config register.
2521 */
37a6084f
LB		 2522 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2523 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2524 msp->extended_rx_coal_limit = 1;
2525 else
2526 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2527
2528 /*
457b1d5a
LB		 2529 * Check whether the MAC supports TX rate control, and if
2530 * yes, whether its associated registers are in the old or
2531 * the new place.
1e881592 2532 */
37a6084f
LB		 2533 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2534 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2535 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2536 } else {
37a6084f
LB		 2537 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2538 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2539 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2540 else
2541 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2542 }
773fc3ee
LB		 2543}
2544
c9df406f 2545static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2546{
10a9948d 2547 static int mv643xx_eth_version_printed;
c9df406f 2548 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2549 struct mv643xx_eth_shared_private *msp;
63a9332b 2550 const struct mbus_dram_target_info *dram;
c9df406f
LB		 2551 struct resource *res;
2552 int ret;
9f8dd319 2553
e5371493 2554 if (!mv643xx_eth_version_printed++)
7542db8b
JP		 2555 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2556 mv643xx_eth_driver_version);
9f8dd319 2557
c9df406f
LB		 2558 ret = -EINVAL;
2559 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2560 if (res == NULL)
2561 goto out;
9f8dd319 2562
c9df406f 2563 ret = -ENOMEM;
beae22e6 2564 msp = kzalloc(sizeof(*msp), GFP_KERNEL);
c9df406f
LB		 2565 if (msp == NULL)
2566 goto out;
c9df406f 2567
28f65c11 2568 msp->base = ioremap(res->start, resource_size(res));
cc9754b3 2569 if (msp->base == NULL)
c9df406f
LB		 2570 goto out_free;
2571
c9df406f
LB		 2572 /*
2573 * (Re-)program MBUS remapping windows if we are asked to.
2574 */
63a9332b
AL		 2575 dram = mv_mbus_dram_info();
2576 if (dram)
2577 mv643xx_eth_conf_mbus_windows(msp, dram);
c9df406f 2578
50a749c1
DC		 2579 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2580 pd->tx_csum_limit : 9 * 1024;
773fc3ee 2581 infer_hw_params(msp);
fc32b0e2
LB		 2582
2583 platform_set_drvdata(pdev, msp);
2584
c9df406f
LB		 2585 return 0;
2586
2587out_free:
2588 kfree(msp);
2589out:
2590 return ret;
2591}
2592
2593static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2594{
e5371493 2595 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2596
cc9754b3 2597 iounmap(msp->base);
c9df406f
LB		 2598 kfree(msp);
2599
2600 return 0;
9f8dd319
DF		 2601}
2602
c9df406f 2603static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2604 .probe = mv643xx_eth_shared_probe,
2605 .remove = mv643xx_eth_shared_remove,
c9df406f 2606 .driver = {
fc32b0e2 2607 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2608 .owner = THIS_MODULE,
2609 },
2610};
2611
e5371493 2612static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2613{
c9df406f 2614 int addr_shift = 5 * mp->port_num;
fc32b0e2 2615 u32 data;
1da177e4 2616
fc32b0e2
LB		 2617 data = rdl(mp, PHY_ADDR);
2618 data &= ~(0x1f << addr_shift);
2619 data |= (phy_addr & 0x1f) << addr_shift;
2620 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2621}
2622
e5371493 2623static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2624{
fc32b0e2
LB		 2625 unsigned int data;
2626
2627 data = rdl(mp, PHY_ADDR);
2628
2629 return (data >> (5 * mp->port_num)) & 0x1f;
2630}
2631
2632static void set_params(struct mv643xx_eth_private *mp,
2633 struct mv643xx_eth_platform_data *pd)
2634{
2635 struct net_device *dev = mp->dev;
2636
2637 if (is_valid_ether_addr(pd->mac_addr))
2638 memcpy(dev->dev_addr, pd->mac_addr, 6);
2639 else
2640 uc_addr_get(mp, dev->dev_addr);
2641
e7d2f4db 2642 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2643 if (pd->rx_queue_size)
e7d2f4db 2644 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2645 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2646 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2647
f7981c1c 2648 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2649
e7d2f4db 2650 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2651 if (pd->tx_queue_size)
e7d2f4db 2652 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2653 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2654 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2655
f7981c1c 2656 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2657}
2658
c3a07134
FF		 2659static void mv643xx_eth_adjust_link(struct net_device *dev)
2660{
2661 struct mv643xx_eth_private *mp = netdev_priv(dev);
2662
2663 mv643xx_adjust_pscr(mp);
2664}
2665
ed94493f
LB		 2666static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2667 int phy_addr)
1da177e4 2668{
ed94493f
LB		 2669 struct phy_device *phydev;
2670 int start;
2671 int num;
2672 int i;
c3a07134 2673 char phy_id[MII_BUS_ID_SIZE + 3];
45c5d3bc 2674
ed94493f
LB		 2675 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2676 start = phy_addr_get(mp) & 0x1f;
2677 num = 32;
2678 } else {
2679 start = phy_addr & 0x1f;
2680 num = 1;
2681 }
45c5d3bc 2682
c3a07134 2683 /* Attempt to connect to the PHY using orion-mdio */
976c90b9 2684 phydev = ERR_PTR(-ENODEV);
ed94493f
LB		 2685 for (i = 0; i < num; i++) {
2686 int addr = (start + i) & 0x1f;
fc32b0e2 2687
c3a07134
FF		 2688 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2689 "orion-mdio-mii", addr);
1da177e4 2690
c3a07134
FF		 2691 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2692 PHY_INTERFACE_MODE_GMII);
2693 if (!IS_ERR(phydev)) {
2694 phy_addr_set(mp, addr);
2695 break;
ed94493f
LB		 2696 }
2697 }
1da177e4 2698
ed94493f 2699 return phydev;
1da177e4
LT		 2700}
2701
ed94493f 2702static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2703{
ed94493f 2704 struct phy_device *phy = mp->phy;
c28a4f89 2705
fc32b0e2
LB		 2706 phy_reset(mp);
2707
ed94493f
LB		 2708 if (speed == 0) {
2709 phy->autoneg = AUTONEG_ENABLE;
2710 phy->speed = 0;
2711 phy->duplex = 0;
2712 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2713 } else {
ed94493f
LB		 2714 phy->autoneg = AUTONEG_DISABLE;
2715 phy->advertising = 0;
2716 phy->speed = speed;
2717 phy->duplex = duplex;
c9df406f 2718 }
ed94493f 2719 phy_start_aneg(phy);
c28a4f89
JC		 2720}
2721
81600eea
LB		 2722static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2723{
2724 u32 pscr;
2725
37a6084f 2726 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2727 if (pscr & SERIAL_PORT_ENABLE) {
2728 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2729 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2730 }
2731
2732 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2733 if (mp->phy == NULL) {
81600eea
LB		 2734 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2735 if (speed == SPEED_1000)
2736 pscr |= SET_GMII_SPEED_TO_1000;
2737 else if (speed == SPEED_100)
2738 pscr |= SET_MII_SPEED_TO_100;
2739
2740 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2741
2742 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2743 if (duplex == DUPLEX_FULL)
2744 pscr |= SET_FULL_DUPLEX_MODE;
2745 }
2746
37a6084f 2747 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2748}
2749
ea8a8642
LB		 2750static const struct net_device_ops mv643xx_eth_netdev_ops = {
2751 .ndo_open = mv643xx_eth_open,
2752 .ndo_stop = mv643xx_eth_stop,
2753 .ndo_start_xmit = mv643xx_eth_xmit,
2754 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2755 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
1d4bd947 2756 .ndo_validate_addr = eth_validate_addr,
ea8a8642
LB		 2757 .ndo_do_ioctl = mv643xx_eth_ioctl,
2758 .ndo_change_mtu = mv643xx_eth_change_mtu,
aad59c43 2759 .ndo_set_features = mv643xx_eth_set_features,
ea8a8642
LB		 2760 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2761 .ndo_get_stats = mv643xx_eth_get_stats,
2762#ifdef CONFIG_NET_POLL_CONTROLLER
2763 .ndo_poll_controller = mv643xx_eth_netpoll,
2764#endif
2765};
2766
c9df406f 2767static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2768{
c9df406f 2769 struct mv643xx_eth_platform_data *pd;
e5371493 2770 struct mv643xx_eth_private *mp;
c9df406f 2771 struct net_device *dev;
c9df406f 2772 struct resource *res;
fc32b0e2 2773 int err;
1da177e4 2774
c9df406f
LB		 2775 pd = pdev->dev.platform_data;
2776 if (pd == NULL) {
7542db8b 2777 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2778 return -ENODEV;
2779 }
1da177e4 2780
c9df406f 2781 if (pd->shared == NULL) {
7542db8b 2782 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2783 return -ENODEV;
2784 }
8f518703 2785
e5ef1de1 2786 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2787 if (!dev)
2788 return -ENOMEM;
1da177e4 2789
c9df406f 2790 mp = netdev_priv(dev);
fc32b0e2
LB		 2791 platform_set_drvdata(pdev, mp);
2792
2793 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2794 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2795 mp->port_num = pd->port_number;
2796
c9df406f 2797 mp->dev = dev;
78fff83b 2798
452503eb 2799 /*
9a43a026
AL		 2800 * Start with a default rate, and if there is a clock, allow
2801 * it to override the default.
452503eb 2802 */
9a43a026
AL		 2803 mp->t_clk = 133000000;
2804#if defined(CONFIG_HAVE_CLK)
452503eb
AL		 2805 mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0"));
2806 if (!IS_ERR(mp->clk)) {
2807 clk_prepare_enable(mp->clk);
2808 mp->t_clk = clk_get_rate(mp->clk);
452503eb 2809 }
9a43a026 2810#endif
fc32b0e2 2811 set_params(mp, pd);
206d6b32
BH		 2812 netif_set_real_num_tx_queues(dev, mp->txq_count);
2813 netif_set_real_num_rx_queues(dev, mp->rxq_count);
fc32b0e2 2814
976c90b9 2815 if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
ed94493f 2816 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2817
976c90b9
SB		 2818 if (IS_ERR(mp->phy)) {
2819 err = PTR_ERR(mp->phy);
2820 if (err == -ENODEV)
2821 err = -EPROBE_DEFER;
2822 goto out;
2823 }
ed94493f 2824 phy_init(mp, pd->speed, pd->duplex);
976c90b9 2825 }
6bdf576e
LB		 2826
2827 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2828
81600eea 2829 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2830
4ff3495a
LB		 2831
2832 mib_counters_clear(mp);
2833
2834 init_timer(&mp->mib_counters_timer);
2835 mp->mib_counters_timer.data = (unsigned long)mp;
2836 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2837 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2838 add_timer(&mp->mib_counters_timer);
2839
2840 spin_lock_init(&mp->mib_counters_lock);
2841
2842 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2843
2257e05c
LB		 2844 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2845
2846 init_timer(&mp->rx_oom);
2847 mp->rx_oom.data = (unsigned long)mp;
2848 mp->rx_oom.function = oom_timer_wrapper;
2849
fc32b0e2 2850
c9df406f
LB		 2851 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2852 BUG_ON(!res);
2853 dev->irq = res->start;
1da177e4 2854
ea8a8642
LB		 2855 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2856
c9df406f
LB		 2857 dev->watchdog_timeo = 2 * HZ;
2858 dev->base_addr = 0;
1da177e4 2859
aad59c43
MM		 2860 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
2861 NETIF_F_RXCSUM | NETIF_F_LRO;
2862 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
e32b6617 2863 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2864
01789349
JP		 2865 dev->priv_flags |= IFF_UNICAST_FLT;
2866
fc32b0e2 2867 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2868
c9df406f 2869 if (mp->shared->win_protect)
fc32b0e2 2870 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2871
a5fe3616
LB		 2872 netif_carrier_off(dev);
2873
b5e86db4
LB		 2874 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2875
4fb0a54a 2876 set_rx_coal(mp, 250);
a5fe3616
LB		 2877 set_tx_coal(mp, 0);
2878
c9df406f
LB		 2879 err = register_netdev(dev);
2880 if (err)
2881 goto out;
1da177e4 2882
7542db8b
JP		 2883 netdev_notice(dev, "port %d with MAC address %pM\n",
2884 mp->port_num, dev->dev_addr);
1da177e4 2885
13d64285 2886 if (mp->tx_desc_sram_size > 0)
7542db8b 2887 netdev_notice(dev, "configured with sram\n");
1da177e4 2888
c9df406f 2889 return 0;
1da177e4 2890
c9df406f 2891out:
baffab28
SB		 2892#if defined(CONFIG_HAVE_CLK)
2893 if (!IS_ERR(mp->clk)) {
2894 clk_disable_unprepare(mp->clk);
2895 clk_put(mp->clk);
2896 }
2897#endif
c9df406f 2898 free_netdev(dev);
1da177e4 2899
c9df406f 2900 return err;
1da177e4
LT		 2901}
2902
c9df406f 2903static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2904{
fc32b0e2 2905 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2906
fc32b0e2 2907 unregister_netdev(mp->dev);
ed94493f
LB		 2908 if (mp->phy != NULL)
2909 phy_detach(mp->phy);
23f333a2 2910 cancel_work_sync(&mp->tx_timeout_task);
452503eb 2911
9a43a026 2912#if defined(CONFIG_HAVE_CLK)
452503eb
AL		 2913 if (!IS_ERR(mp->clk)) {
2914 clk_disable_unprepare(mp->clk);
2915 clk_put(mp->clk);
2916 }
9a43a026
AL		 2917#endif
2918
fc32b0e2 2919 free_netdev(mp->dev);
c9df406f 2920
c9df406f 2921 platform_set_drvdata(pdev, NULL);
fc32b0e2 2922
c9df406f 2923 return 0;
1da177e4
LT		 2924}
2925
c9df406f 2926static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2927{
fc32b0e2 2928 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2929
c9df406f 2930 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2931 wrlp(mp, INT_MASK, 0);
2932 rdlp(mp, INT_MASK);
c9df406f 2933
fc32b0e2
LB		 2934 if (netif_running(mp->dev))
2935 port_reset(mp);
d0412d96
JC		 2936}
2937
c9df406f 2938static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2939 .probe = mv643xx_eth_probe,
2940 .remove = mv643xx_eth_remove,
2941 .shutdown = mv643xx_eth_shutdown,
c9df406f 2942 .driver = {
fc32b0e2 2943 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2944 .owner = THIS_MODULE,
2945 },
2946};
2947
e5371493 2948static int __init mv643xx_eth_init_module(void)
d0412d96 2949{
c9df406f 2950 int rc;
d0412d96 2951
c9df406f
LB		 2952 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2953 if (!rc) {
2954 rc = platform_driver_register(&mv643xx_eth_driver);
2955 if (rc)
2956 platform_driver_unregister(&mv643xx_eth_shared_driver);
2957 }
fc32b0e2 2958
c9df406f 2959 return rc;
d0412d96 2960}
fc32b0e2 2961module_init(mv643xx_eth_init_module);
d0412d96 2962
e5371493 2963static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2964{
c9df406f
LB		 2965 platform_driver_unregister(&mv643xx_eth_driver);
2966 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2967}
e5371493 2968module_exit(mv643xx_eth_cleanup_module);
1da177e4 2969
45675bc6
LB		 2970MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2971 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2972MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2973MODULE_LICENSE("GPL");
c9df406f 2974MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2975MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 6.x block layer and io_uring tree(s)