Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
3871c387 MS |
23 | * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de> |
24 | * | |
1da177e4 LT |
25 | * This program is free software; you can redistribute it and/or |
26 | * modify it under the terms of the GNU General Public License | |
27 | * as published by the Free Software Foundation; either version 2 | |
28 | * of the License, or (at your option) any later version. | |
29 | * | |
30 | * This program is distributed in the hope that it will be useful, | |
31 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
33 | * GNU General Public License for more details. | |
34 | * | |
35 | * You should have received a copy of the GNU General Public License | |
0ab75ae8 | 36 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 | 37 | */ |
a779d38c | 38 | |
7542db8b JP |
39 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
40 | ||
1da177e4 LT |
41 | #include <linux/init.h> |
42 | #include <linux/dma-mapping.h> | |
b6298c22 | 43 | #include <linux/in.h> |
c3efab8e | 44 | #include <linux/ip.h> |
3ae8f4e0 | 45 | #include <net/tso.h> |
1da177e4 LT |
46 | #include <linux/tcp.h> |
47 | #include <linux/udp.h> | |
48 | #include <linux/etherdevice.h> | |
1da177e4 LT |
49 | #include <linux/delay.h> |
50 | #include <linux/ethtool.h> | |
d052d1be | 51 | #include <linux/platform_device.h> |
fbd6a754 LB |
52 | #include <linux/module.h> |
53 | #include <linux/kernel.h> | |
54 | #include <linux/spinlock.h> | |
55 | #include <linux/workqueue.h> | |
ed94493f | 56 | #include <linux/phy.h> |
fbd6a754 | 57 | #include <linux/mv643xx_eth.h> |
10a9948d | 58 | #include <linux/io.h> |
3619eb85 | 59 | #include <linux/interrupt.h> |
10a9948d | 60 | #include <linux/types.h> |
5a0e3ad6 | 61 | #include <linux/slab.h> |
452503eb | 62 | #include <linux/clk.h> |
76723bca SH |
63 | #include <linux/of.h> |
64 | #include <linux/of_irq.h> | |
65 | #include <linux/of_net.h> | |
cc9d4598 | 66 | #include <linux/of_mdio.h> |
fbd6a754 | 67 | |
e5371493 | 68 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
042af53c | 69 | static char mv643xx_eth_driver_version[] = "1.4"; |
c9df406f | 70 | |
fbd6a754 | 71 | |
fbd6a754 LB |
72 | /* |
73 | * Registers shared between all ports. | |
74 | */ | |
3cb4667c | 75 | #define PHY_ADDR 0x0000 |
3cb4667c LB |
76 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) |
77 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
78 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
79 | #define WINDOW_BAR_ENABLE 0x0290 | |
80 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
81 | |
82 | /* | |
37a6084f LB |
83 | * Main per-port registers. These live at offset 0x0400 for |
84 | * port #0, 0x0800 for port #1, and 0x0c00 for port #2. | |
fbd6a754 | 85 | */ |
37a6084f | 86 | #define PORT_CONFIG 0x0000 |
d9a073ea | 87 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
37a6084f LB |
88 | #define PORT_CONFIG_EXT 0x0004 |
89 | #define MAC_ADDR_LOW 0x0014 | |
90 | #define MAC_ADDR_HIGH 0x0018 | |
91 | #define SDMA_CONFIG 0x001c | |
becfad97 LB |
92 | #define TX_BURST_SIZE_16_64BIT 0x01000000 |
93 | #define TX_BURST_SIZE_4_64BIT 0x00800000 | |
94 | #define BLM_TX_NO_SWAP 0x00000020 | |
95 | #define BLM_RX_NO_SWAP 0x00000010 | |
96 | #define RX_BURST_SIZE_16_64BIT 0x00000008 | |
97 | #define RX_BURST_SIZE_4_64BIT 0x00000004 | |
37a6084f | 98 | #define PORT_SERIAL_CONTROL 0x003c |
becfad97 LB |
99 | #define SET_MII_SPEED_TO_100 0x01000000 |
100 | #define SET_GMII_SPEED_TO_1000 0x00800000 | |
101 | #define SET_FULL_DUPLEX_MODE 0x00200000 | |
102 | #define MAX_RX_PACKET_9700BYTE 0x000a0000 | |
103 | #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 | |
104 | #define DO_NOT_FORCE_LINK_FAIL 0x00000400 | |
105 | #define SERIAL_PORT_CONTROL_RESERVED 0x00000200 | |
106 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 | |
107 | #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 | |
108 | #define FORCE_LINK_PASS 0x00000002 | |
109 | #define SERIAL_PORT_ENABLE 0x00000001 | |
37a6084f | 110 | #define PORT_STATUS 0x0044 |
a2a41689 | 111 | #define TX_FIFO_EMPTY 0x00000400 |
ae9ae064 | 112 | #define TX_IN_PROGRESS 0x00000080 |
2f7eb47a LB |
113 | #define PORT_SPEED_MASK 0x00000030 |
114 | #define PORT_SPEED_1000 0x00000010 | |
115 | #define PORT_SPEED_100 0x00000020 | |
116 | #define PORT_SPEED_10 0x00000000 | |
117 | #define FLOW_CONTROL_ENABLED 0x00000008 | |
118 | #define FULL_DUPLEX 0x00000004 | |
81600eea | 119 | #define LINK_UP 0x00000002 |
37a6084f LB |
120 | #define TXQ_COMMAND 0x0048 |
121 | #define TXQ_FIX_PRIO_CONF 0x004c | |
cb85215f SH |
122 | #define PORT_SERIAL_CONTROL1 0x004c |
123 | #define CLK125_BYPASS_EN 0x00000010 | |
37a6084f LB |
124 | #define TX_BW_RATE 0x0050 |
125 | #define TX_BW_MTU 0x0058 | |
126 | #define TX_BW_BURST 0x005c | |
127 | #define INT_CAUSE 0x0060 | |
226bb6b7 | 128 | #define INT_TX_END 0x07f80000 |
e0ca8410 | 129 | #define INT_TX_END_0 0x00080000 |
befefe21 | 130 | #define INT_RX 0x000003fc |
e0ca8410 | 131 | #define INT_RX_0 0x00000004 |
073a345c | 132 | #define INT_EXT 0x00000002 |
37a6084f | 133 | #define INT_CAUSE_EXT 0x0064 |
befefe21 LB |
134 | #define INT_EXT_LINK_PHY 0x00110000 |
135 | #define INT_EXT_TX 0x000000ff | |
37a6084f LB |
136 | #define INT_MASK 0x0068 |
137 | #define INT_MASK_EXT 0x006c | |
138 | #define TX_FIFO_URGENT_THRESHOLD 0x0074 | |
302476c9 PZ |
139 | #define RX_DISCARD_FRAME_CNT 0x0084 |
140 | #define RX_OVERRUN_FRAME_CNT 0x0088 | |
37a6084f LB |
141 | #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc |
142 | #define TX_BW_RATE_MOVED 0x00e0 | |
143 | #define TX_BW_MTU_MOVED 0x00e8 | |
144 | #define TX_BW_BURST_MOVED 0x00ec | |
145 | #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) | |
146 | #define RXQ_COMMAND 0x0280 | |
147 | #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) | |
148 | #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) | |
149 | #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) | |
150 | #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) | |
151 | ||
152 | /* | |
153 | * Misc per-port registers. | |
154 | */ | |
3cb4667c LB |
155 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) |
156 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
157 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
158 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 159 | |
2679a550 LB |
160 | |
161 | /* | |
becfad97 | 162 | * SDMA configuration register default value. |
2679a550 | 163 | */ |
fbd6a754 LB |
164 | #if defined(__BIG_ENDIAN) |
165 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
166 | (RX_BURST_SIZE_4_64BIT | \ |
167 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
168 | #elif defined(__LITTLE_ENDIAN) |
169 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
170 | (RX_BURST_SIZE_4_64BIT | \ |
171 | BLM_RX_NO_SWAP | \ | |
172 | BLM_TX_NO_SWAP | \ | |
173 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
174 | #else |
175 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
176 | #endif | |
177 | ||
2beff77b LB |
178 | |
179 | /* | |
becfad97 | 180 | * Misc definitions. |
2beff77b | 181 | */ |
becfad97 | 182 | #define DEFAULT_RX_QUEUE_SIZE 128 |
3ae8f4e0 | 183 | #define DEFAULT_TX_QUEUE_SIZE 512 |
7fd96ce4 | 184 | #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) |
fbd6a754 | 185 | |
3ae8f4e0 | 186 | #define TSO_HEADER_SIZE 128 |
fbd6a754 | 187 | |
ee9e4956 EG |
188 | /* Max number of allowed TCP segments for software TSO */ |
189 | #define MV643XX_MAX_TSO_SEGS 100 | |
190 | #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
191 | ||
b926260c EG |
192 | #define IS_TSO_HEADER(txq, addr) \ |
193 | ((addr >= txq->tso_hdrs_dma) && \ | |
194 | (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) | |
9e911414 EG |
195 | |
196 | #define DESC_DMA_MAP_SINGLE 0 | |
197 | #define DESC_DMA_MAP_PAGE 1 | |
198 | ||
7ca72a3b LB |
199 | /* |
200 | * RX/TX descriptors. | |
fbd6a754 LB |
201 | */ |
202 | #if defined(__BIG_ENDIAN) | |
cc9754b3 | 203 | struct rx_desc { |
fbd6a754 LB |
204 | u16 byte_cnt; /* Descriptor buffer byte count */ |
205 | u16 buf_size; /* Buffer size */ | |
206 | u32 cmd_sts; /* Descriptor command status */ | |
207 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
208 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
209 | }; | |
210 | ||
cc9754b3 | 211 | struct tx_desc { |
fbd6a754 LB |
212 | u16 byte_cnt; /* buffer byte count */ |
213 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
214 | u32 cmd_sts; /* Command/status field */ | |
215 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
216 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
217 | }; | |
218 | #elif defined(__LITTLE_ENDIAN) | |
cc9754b3 | 219 | struct rx_desc { |
fbd6a754 LB |
220 | u32 cmd_sts; /* Descriptor command status */ |
221 | u16 buf_size; /* Buffer size */ | |
222 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
223 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
224 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
225 | }; | |
226 | ||
cc9754b3 | 227 | struct tx_desc { |
fbd6a754 LB |
228 | u32 cmd_sts; /* Command/status field */ |
229 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
230 | u16 byte_cnt; /* buffer byte count */ | |
231 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
232 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
233 | }; | |
234 | #else | |
235 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
236 | #endif | |
237 | ||
7ca72a3b | 238 | /* RX & TX descriptor command */ |
cc9754b3 | 239 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
7ca72a3b LB |
240 | |
241 | /* RX & TX descriptor status */ | |
cc9754b3 | 242 | #define ERROR_SUMMARY 0x00000001 |
7ca72a3b LB |
243 | |
244 | /* RX descriptor status */ | |
cc9754b3 LB |
245 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
246 | #define RX_ENABLE_INTERRUPT 0x20000000 | |
247 | #define RX_FIRST_DESC 0x08000000 | |
248 | #define RX_LAST_DESC 0x04000000 | |
eaf5d590 LB |
249 | #define RX_IP_HDR_OK 0x02000000 |
250 | #define RX_PKT_IS_IPV4 0x01000000 | |
251 | #define RX_PKT_IS_ETHERNETV2 0x00800000 | |
252 | #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 | |
253 | #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 | |
254 | #define RX_PKT_IS_VLAN_TAGGED 0x00080000 | |
7ca72a3b LB |
255 | |
256 | /* TX descriptor command */ | |
cc9754b3 LB |
257 | #define TX_ENABLE_INTERRUPT 0x00800000 |
258 | #define GEN_CRC 0x00400000 | |
259 | #define TX_FIRST_DESC 0x00200000 | |
260 | #define TX_LAST_DESC 0x00100000 | |
261 | #define ZERO_PADDING 0x00080000 | |
262 | #define GEN_IP_V4_CHECKSUM 0x00040000 | |
263 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 | |
264 | #define UDP_FRAME 0x00010000 | |
e32b6617 | 265 | #define MAC_HDR_EXTRA_4_BYTES 0x00008000 |
84411f73 | 266 | #define GEN_TCP_UDP_CHK_FULL 0x00000400 |
e32b6617 | 267 | #define MAC_HDR_EXTRA_8_BYTES 0x00000200 |
7ca72a3b | 268 | |
cc9754b3 | 269 | #define TX_IHL_SHIFT 11 |
7ca72a3b LB |
270 | |
271 | ||
c9df406f | 272 | /* global *******************************************************************/ |
e5371493 | 273 | struct mv643xx_eth_shared_private { |
fc32b0e2 LB |
274 | /* |
275 | * Ethernet controller base address. | |
276 | */ | |
cc9754b3 | 277 | void __iomem *base; |
c9df406f | 278 | |
fc32b0e2 LB |
279 | /* |
280 | * Per-port MBUS window access register value. | |
281 | */ | |
c9df406f LB |
282 | u32 win_protect; |
283 | ||
fc32b0e2 LB |
284 | /* |
285 | * Hardware-specific parameters. | |
286 | */ | |
773fc3ee | 287 | int extended_rx_coal_limit; |
457b1d5a | 288 | int tx_bw_control; |
9b2c2ff7 | 289 | int tx_csum_limit; |
20922486 | 290 | struct clk *clk; |
c9df406f LB |
291 | }; |
292 | ||
457b1d5a LB |
293 | #define TX_BW_CONTROL_ABSENT 0 |
294 | #define TX_BW_CONTROL_OLD_LAYOUT 1 | |
295 | #define TX_BW_CONTROL_NEW_LAYOUT 2 | |
296 | ||
e7d2f4db LB |
297 | static int mv643xx_eth_open(struct net_device *dev); |
298 | static int mv643xx_eth_stop(struct net_device *dev); | |
299 | ||
c9df406f LB |
300 | |
301 | /* per-port *****************************************************************/ | |
e5371493 | 302 | struct mib_counters { |
fbd6a754 LB |
303 | u64 good_octets_received; |
304 | u32 bad_octets_received; | |
305 | u32 internal_mac_transmit_err; | |
306 | u32 good_frames_received; | |
307 | u32 bad_frames_received; | |
308 | u32 broadcast_frames_received; | |
309 | u32 multicast_frames_received; | |
310 | u32 frames_64_octets; | |
311 | u32 frames_65_to_127_octets; | |
312 | u32 frames_128_to_255_octets; | |
313 | u32 frames_256_to_511_octets; | |
314 | u32 frames_512_to_1023_octets; | |
315 | u32 frames_1024_to_max_octets; | |
316 | u64 good_octets_sent; | |
317 | u32 good_frames_sent; | |
318 | u32 excessive_collision; | |
319 | u32 multicast_frames_sent; | |
320 | u32 broadcast_frames_sent; | |
321 | u32 unrec_mac_control_received; | |
322 | u32 fc_sent; | |
323 | u32 good_fc_received; | |
324 | u32 bad_fc_received; | |
325 | u32 undersize_received; | |
326 | u32 fragments_received; | |
327 | u32 oversize_received; | |
328 | u32 jabber_received; | |
329 | u32 mac_receive_error; | |
330 | u32 bad_crc_event; | |
331 | u32 collision; | |
332 | u32 late_collision; | |
302476c9 PZ |
333 | /* Non MIB hardware counters */ |
334 | u32 rx_discard; | |
335 | u32 rx_overrun; | |
fbd6a754 LB |
336 | }; |
337 | ||
8a578111 | 338 | struct rx_queue { |
64da80a2 LB |
339 | int index; |
340 | ||
8a578111 LB |
341 | int rx_ring_size; |
342 | ||
343 | int rx_desc_count; | |
344 | int rx_curr_desc; | |
345 | int rx_used_desc; | |
346 | ||
347 | struct rx_desc *rx_desc_area; | |
348 | dma_addr_t rx_desc_dma; | |
349 | int rx_desc_area_size; | |
350 | struct sk_buff **rx_skb; | |
8a578111 LB |
351 | }; |
352 | ||
13d64285 | 353 | struct tx_queue { |
3d6b35bc LB |
354 | int index; |
355 | ||
13d64285 | 356 | int tx_ring_size; |
fbd6a754 | 357 | |
13d64285 LB |
358 | int tx_desc_count; |
359 | int tx_curr_desc; | |
360 | int tx_used_desc; | |
fbd6a754 | 361 | |
ee9e4956 EG |
362 | int tx_stop_threshold; |
363 | int tx_wake_threshold; | |
364 | ||
3ae8f4e0 EG |
365 | char *tso_hdrs; |
366 | dma_addr_t tso_hdrs_dma; | |
367 | ||
5daffe94 | 368 | struct tx_desc *tx_desc_area; |
9e911414 | 369 | char *tx_desc_mapping; /* array to track the type of the dma mapping */ |
fbd6a754 LB |
370 | dma_addr_t tx_desc_dma; |
371 | int tx_desc_area_size; | |
99ab08e0 LB |
372 | |
373 | struct sk_buff_head tx_skb; | |
8fd89211 LB |
374 | |
375 | unsigned long tx_packets; | |
376 | unsigned long tx_bytes; | |
377 | unsigned long tx_dropped; | |
13d64285 LB |
378 | }; |
379 | ||
380 | struct mv643xx_eth_private { | |
381 | struct mv643xx_eth_shared_private *shared; | |
37a6084f | 382 | void __iomem *base; |
fc32b0e2 | 383 | int port_num; |
13d64285 | 384 | |
fc32b0e2 | 385 | struct net_device *dev; |
fbd6a754 | 386 | |
ed94493f | 387 | struct phy_device *phy; |
fbd6a754 | 388 | |
4ff3495a LB |
389 | struct timer_list mib_counters_timer; |
390 | spinlock_t mib_counters_lock; | |
fc32b0e2 | 391 | struct mib_counters mib_counters; |
4ff3495a | 392 | |
fc32b0e2 | 393 | struct work_struct tx_timeout_task; |
8a578111 | 394 | |
1fa38c58 | 395 | struct napi_struct napi; |
e0ca8410 | 396 | u32 int_mask; |
1319ebad | 397 | u8 oom; |
1fa38c58 LB |
398 | u8 work_link; |
399 | u8 work_tx; | |
400 | u8 work_tx_end; | |
401 | u8 work_rx; | |
402 | u8 work_rx_refill; | |
1fa38c58 | 403 | |
2bcb4b0f | 404 | int skb_size; |
2bcb4b0f | 405 | |
8a578111 LB |
406 | /* |
407 | * RX state. | |
408 | */ | |
e7d2f4db | 409 | int rx_ring_size; |
8a578111 LB |
410 | unsigned long rx_desc_sram_addr; |
411 | int rx_desc_sram_size; | |
f7981c1c | 412 | int rxq_count; |
2257e05c | 413 | struct timer_list rx_oom; |
64da80a2 | 414 | struct rx_queue rxq[8]; |
13d64285 LB |
415 | |
416 | /* | |
417 | * TX state. | |
418 | */ | |
e7d2f4db | 419 | int tx_ring_size; |
13d64285 LB |
420 | unsigned long tx_desc_sram_addr; |
421 | int tx_desc_sram_size; | |
f7981c1c | 422 | int txq_count; |
3d6b35bc | 423 | struct tx_queue txq[8]; |
452503eb AL |
424 | |
425 | /* | |
426 | * Hardware-specific parameters. | |
427 | */ | |
428 | struct clk *clk; | |
429 | unsigned int t_clk; | |
fbd6a754 | 430 | }; |
1da177e4 | 431 | |
fbd6a754 | 432 | |
c9df406f | 433 | /* port register accessors **************************************************/ |
e5371493 | 434 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 435 | { |
cc9754b3 | 436 | return readl(mp->shared->base + offset); |
c9df406f | 437 | } |
fbd6a754 | 438 | |
37a6084f LB |
439 | static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) |
440 | { | |
441 | return readl(mp->base + offset); | |
442 | } | |
443 | ||
e5371493 | 444 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
c9df406f | 445 | { |
cc9754b3 | 446 | writel(data, mp->shared->base + offset); |
c9df406f | 447 | } |
fbd6a754 | 448 | |
37a6084f LB |
449 | static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) |
450 | { | |
451 | writel(data, mp->base + offset); | |
452 | } | |
453 | ||
fbd6a754 | 454 | |
c9df406f | 455 | /* rxq/txq helper functions *************************************************/ |
8a578111 | 456 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
c9df406f | 457 | { |
64da80a2 | 458 | return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); |
c9df406f | 459 | } |
fbd6a754 | 460 | |
13d64285 LB |
461 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
462 | { | |
3d6b35bc | 463 | return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); |
13d64285 LB |
464 | } |
465 | ||
8a578111 | 466 | static void rxq_enable(struct rx_queue *rxq) |
c9df406f | 467 | { |
8a578111 | 468 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
37a6084f | 469 | wrlp(mp, RXQ_COMMAND, 1 << rxq->index); |
8a578111 | 470 | } |
1da177e4 | 471 | |
8a578111 LB |
472 | static void rxq_disable(struct rx_queue *rxq) |
473 | { | |
474 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); | |
64da80a2 | 475 | u8 mask = 1 << rxq->index; |
1da177e4 | 476 | |
37a6084f LB |
477 | wrlp(mp, RXQ_COMMAND, mask << 8); |
478 | while (rdlp(mp, RXQ_COMMAND) & mask) | |
8a578111 | 479 | udelay(10); |
c9df406f LB |
480 | } |
481 | ||
6b368f68 LB |
482 | static void txq_reset_hw_ptr(struct tx_queue *txq) |
483 | { | |
484 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
6b368f68 LB |
485 | u32 addr; |
486 | ||
487 | addr = (u32)txq->tx_desc_dma; | |
488 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); | |
37a6084f | 489 | wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); |
6b368f68 LB |
490 | } |
491 | ||
13d64285 | 492 | static void txq_enable(struct tx_queue *txq) |
1da177e4 | 493 | { |
13d64285 | 494 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
37a6084f | 495 | wrlp(mp, TXQ_COMMAND, 1 << txq->index); |
1da177e4 LT |
496 | } |
497 | ||
13d64285 | 498 | static void txq_disable(struct tx_queue *txq) |
1da177e4 | 499 | { |
13d64285 | 500 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 501 | u8 mask = 1 << txq->index; |
c9df406f | 502 | |
37a6084f LB |
503 | wrlp(mp, TXQ_COMMAND, mask << 8); |
504 | while (rdlp(mp, TXQ_COMMAND) & mask) | |
13d64285 LB |
505 | udelay(10); |
506 | } | |
507 | ||
1fa38c58 | 508 | static void txq_maybe_wake(struct tx_queue *txq) |
13d64285 LB |
509 | { |
510 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
e5ef1de1 | 511 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
3d6b35bc | 512 | |
8fd89211 LB |
513 | if (netif_tx_queue_stopped(nq)) { |
514 | __netif_tx_lock(nq, smp_processor_id()); | |
ee9e4956 | 515 | if (txq->tx_desc_count <= txq->tx_wake_threshold) |
8fd89211 LB |
516 | netif_tx_wake_queue(nq); |
517 | __netif_tx_unlock(nq); | |
518 | } | |
1da177e4 LT |
519 | } |
520 | ||
8a578111 | 521 | static int rxq_process(struct rx_queue *rxq, int budget) |
1da177e4 | 522 | { |
8a578111 LB |
523 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
524 | struct net_device_stats *stats = &mp->dev->stats; | |
525 | int rx; | |
1da177e4 | 526 | |
8a578111 | 527 | rx = 0; |
9e1f3772 | 528 | while (rx < budget && rxq->rx_desc_count) { |
fc32b0e2 | 529 | struct rx_desc *rx_desc; |
96587661 | 530 | unsigned int cmd_sts; |
fc32b0e2 | 531 | struct sk_buff *skb; |
6b8f90c2 | 532 | u16 byte_cnt; |
ff561eef | 533 | |
8a578111 | 534 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
1da177e4 | 535 | |
96587661 | 536 | cmd_sts = rx_desc->cmd_sts; |
2257e05c | 537 | if (cmd_sts & BUFFER_OWNED_BY_DMA) |
96587661 | 538 | break; |
96587661 | 539 | rmb(); |
1da177e4 | 540 | |
8a578111 LB |
541 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
542 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; | |
ff561eef | 543 | |
9da78745 LB |
544 | rxq->rx_curr_desc++; |
545 | if (rxq->rx_curr_desc == rxq->rx_ring_size) | |
546 | rxq->rx_curr_desc = 0; | |
ff561eef | 547 | |
eb0519b5 | 548 | dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, |
abe78717 | 549 | rx_desc->buf_size, DMA_FROM_DEVICE); |
8a578111 LB |
550 | rxq->rx_desc_count--; |
551 | rx++; | |
b1dd9ca1 | 552 | |
1fa38c58 LB |
553 | mp->work_rx_refill |= 1 << rxq->index; |
554 | ||
6b8f90c2 LB |
555 | byte_cnt = rx_desc->byte_cnt; |
556 | ||
468d09f8 DF |
557 | /* |
558 | * Update statistics. | |
fc32b0e2 LB |
559 | * |
560 | * Note that the descriptor byte count includes 2 dummy | |
561 | * bytes automatically inserted by the hardware at the | |
562 | * start of the packet (which we don't count), and a 4 | |
563 | * byte CRC at the end of the packet (which we do count). | |
468d09f8 | 564 | */ |
1da177e4 | 565 | stats->rx_packets++; |
6b8f90c2 | 566 | stats->rx_bytes += byte_cnt - 2; |
96587661 | 567 | |
1da177e4 | 568 | /* |
fc32b0e2 LB |
569 | * In case we received a packet without first / last bits |
570 | * on, or the error summary bit is set, the packet needs | |
571 | * to be dropped. | |
1da177e4 | 572 | */ |
f61e5547 LB |
573 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) |
574 | != (RX_FIRST_DESC | RX_LAST_DESC)) | |
575 | goto err; | |
576 | ||
577 | /* | |
578 | * The -4 is for the CRC in the trailer of the | |
579 | * received packet | |
580 | */ | |
581 | skb_put(skb, byte_cnt - 2 - 4); | |
582 | ||
583 | if (cmd_sts & LAYER_4_CHECKSUM_OK) | |
584 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
585 | skb->protocol = eth_type_trans(skb, mp->dev); | |
eaf5d590 | 586 | |
3619eb85 | 587 | napi_gro_receive(&mp->napi, skb); |
f61e5547 LB |
588 | |
589 | continue; | |
590 | ||
591 | err: | |
592 | stats->rx_dropped++; | |
593 | ||
594 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != | |
595 | (RX_FIRST_DESC | RX_LAST_DESC)) { | |
596 | if (net_ratelimit()) | |
7542db8b JP |
597 | netdev_err(mp->dev, |
598 | "received packet spanning multiple descriptors\n"); | |
1da177e4 | 599 | } |
f61e5547 LB |
600 | |
601 | if (cmd_sts & ERROR_SUMMARY) | |
602 | stats->rx_errors++; | |
603 | ||
604 | dev_kfree_skb(skb); | |
1da177e4 | 605 | } |
fc32b0e2 | 606 | |
1fa38c58 LB |
607 | if (rx < budget) |
608 | mp->work_rx &= ~(1 << rxq->index); | |
609 | ||
8a578111 | 610 | return rx; |
1da177e4 LT |
611 | } |
612 | ||
1fa38c58 | 613 | static int rxq_refill(struct rx_queue *rxq, int budget) |
d0412d96 | 614 | { |
1fa38c58 | 615 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1fa38c58 | 616 | int refilled; |
8a578111 | 617 | |
1fa38c58 LB |
618 | refilled = 0; |
619 | while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { | |
620 | struct sk_buff *skb; | |
1fa38c58 | 621 | int rx; |
53771522 | 622 | struct rx_desc *rx_desc; |
530e557a | 623 | int size; |
d0412d96 | 624 | |
acb600de | 625 | skb = netdev_alloc_skb(mp->dev, mp->skb_size); |
2bcb4b0f | 626 | |
1fa38c58 | 627 | if (skb == NULL) { |
1319ebad | 628 | mp->oom = 1; |
1fa38c58 LB |
629 | goto oom; |
630 | } | |
d0412d96 | 631 | |
7fd96ce4 LB |
632 | if (SKB_DMA_REALIGN) |
633 | skb_reserve(skb, SKB_DMA_REALIGN); | |
2257e05c | 634 | |
1fa38c58 LB |
635 | refilled++; |
636 | rxq->rx_desc_count++; | |
c9df406f | 637 | |
1fa38c58 LB |
638 | rx = rxq->rx_used_desc++; |
639 | if (rxq->rx_used_desc == rxq->rx_ring_size) | |
640 | rxq->rx_used_desc = 0; | |
2257e05c | 641 | |
53771522 LB |
642 | rx_desc = rxq->rx_desc_area + rx; |
643 | ||
18f1d054 | 644 | size = skb_end_pointer(skb) - skb->data; |
eb0519b5 | 645 | rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, |
530e557a | 646 | skb->data, size, |
eb0519b5 | 647 | DMA_FROM_DEVICE); |
530e557a | 648 | rx_desc->buf_size = size; |
1fa38c58 LB |
649 | rxq->rx_skb[rx] = skb; |
650 | wmb(); | |
53771522 | 651 | rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; |
1fa38c58 | 652 | wmb(); |
2257e05c | 653 | |
1fa38c58 LB |
654 | /* |
655 | * The hardware automatically prepends 2 bytes of | |
656 | * dummy data to each received packet, so that the | |
657 | * IP header ends up 16-byte aligned. | |
658 | */ | |
659 | skb_reserve(skb, 2); | |
660 | } | |
661 | ||
662 | if (refilled < budget) | |
663 | mp->work_rx_refill &= ~(1 << rxq->index); | |
664 | ||
665 | oom: | |
666 | return refilled; | |
d0412d96 JC |
667 | } |
668 | ||
c9df406f LB |
669 | |
670 | /* tx ***********************************************************************/ | |
c9df406f | 671 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 672 | { |
13d64285 | 673 | int frag; |
1da177e4 | 674 | |
c9df406f | 675 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
9e903e08 ED |
676 | const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
677 | ||
678 | if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7) | |
c9df406f | 679 | return 1; |
1da177e4 | 680 | } |
13d64285 | 681 | |
c9df406f LB |
682 | return 0; |
683 | } | |
7303fde8 | 684 | |
0a8fa933 EG |
685 | static inline __be16 sum16_as_be(__sum16 sum) |
686 | { | |
687 | return (__force __be16)sum; | |
688 | } | |
689 | ||
690 | static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb, | |
691 | u16 *l4i_chk, u32 *command, int length) | |
692 | { | |
693 | int ret; | |
694 | u32 cmd = 0; | |
695 | ||
696 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
697 | int hdr_len; | |
698 | int tag_bytes; | |
699 | ||
700 | BUG_ON(skb->protocol != htons(ETH_P_IP) && | |
701 | skb->protocol != htons(ETH_P_8021Q)); | |
702 | ||
703 | hdr_len = (void *)ip_hdr(skb) - (void *)skb->data; | |
704 | tag_bytes = hdr_len - ETH_HLEN; | |
705 | ||
706 | if (length - hdr_len > mp->shared->tx_csum_limit || | |
707 | unlikely(tag_bytes & ~12)) { | |
708 | ret = skb_checksum_help(skb); | |
709 | if (!ret) | |
710 | goto no_csum; | |
711 | return ret; | |
712 | } | |
713 | ||
714 | if (tag_bytes & 4) | |
715 | cmd |= MAC_HDR_EXTRA_4_BYTES; | |
716 | if (tag_bytes & 8) | |
717 | cmd |= MAC_HDR_EXTRA_8_BYTES; | |
718 | ||
84411f73 | 719 | cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL | |
0a8fa933 EG |
720 | GEN_IP_V4_CHECKSUM | |
721 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; | |
722 | ||
84411f73 EG |
723 | /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL |
724 | * it seems we don't need to pass the initial checksum. */ | |
0a8fa933 EG |
725 | switch (ip_hdr(skb)->protocol) { |
726 | case IPPROTO_UDP: | |
727 | cmd |= UDP_FRAME; | |
84411f73 | 728 | *l4i_chk = 0; |
0a8fa933 EG |
729 | break; |
730 | case IPPROTO_TCP: | |
84411f73 | 731 | *l4i_chk = 0; |
0a8fa933 EG |
732 | break; |
733 | default: | |
734 | WARN(1, "protocol not supported"); | |
735 | } | |
736 | } else { | |
737 | no_csum: | |
738 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
739 | cmd |= 5 << TX_IHL_SHIFT; | |
740 | } | |
741 | *command = cmd; | |
742 | return 0; | |
743 | } | |
744 | ||
3ae8f4e0 EG |
745 | static inline int |
746 | txq_put_data_tso(struct net_device *dev, struct tx_queue *txq, | |
747 | struct sk_buff *skb, char *data, int length, | |
748 | bool last_tcp, bool is_last) | |
749 | { | |
750 | int tx_index; | |
751 | u32 cmd_sts; | |
752 | struct tx_desc *desc; | |
753 | ||
754 | tx_index = txq->tx_curr_desc++; | |
755 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
756 | txq->tx_curr_desc = 0; | |
757 | desc = &txq->tx_desc_area[tx_index]; | |
9e911414 | 758 | txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; |
3ae8f4e0 EG |
759 | |
760 | desc->l4i_chk = 0; | |
761 | desc->byte_cnt = length; | |
91986fd3 PK |
762 | |
763 | if (length <= 8 && (uintptr_t)data & 0x7) { | |
764 | /* Copy unaligned small data fragment to TSO header data area */ | |
3b89624a | 765 | memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE, |
91986fd3 PK |
766 | data, length); |
767 | desc->buf_ptr = txq->tso_hdrs_dma | |
3b89624a | 768 | + tx_index * TSO_HEADER_SIZE; |
91986fd3 PK |
769 | } else { |
770 | /* Alignment is okay, map buffer and hand off to hardware */ | |
771 | txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; | |
772 | desc->buf_ptr = dma_map_single(dev->dev.parent, data, | |
773 | length, DMA_TO_DEVICE); | |
774 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
775 | desc->buf_ptr))) { | |
776 | WARN(1, "dma_map_single failed!\n"); | |
777 | return -ENOMEM; | |
778 | } | |
3ae8f4e0 EG |
779 | } |
780 | ||
781 | cmd_sts = BUFFER_OWNED_BY_DMA; | |
782 | if (last_tcp) { | |
783 | /* last descriptor in the TCP packet */ | |
784 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC; | |
785 | /* last descriptor in SKB */ | |
786 | if (is_last) | |
787 | cmd_sts |= TX_ENABLE_INTERRUPT; | |
788 | } | |
789 | desc->cmd_sts = cmd_sts; | |
790 | return 0; | |
791 | } | |
792 | ||
793 | static inline void | |
968200f3 PK |
794 | txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length, |
795 | u32 *first_cmd_sts, bool first_desc) | |
3ae8f4e0 EG |
796 | { |
797 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
798 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
799 | int tx_index; | |
800 | struct tx_desc *desc; | |
801 | int ret; | |
802 | u32 cmd_csum = 0; | |
803 | u16 l4i_chk = 0; | |
968200f3 | 804 | u32 cmd_sts; |
3ae8f4e0 EG |
805 | |
806 | tx_index = txq->tx_curr_desc; | |
807 | desc = &txq->tx_desc_area[tx_index]; | |
808 | ||
809 | ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length); | |
810 | if (ret) | |
811 | WARN(1, "failed to prepare checksum!"); | |
812 | ||
813 | /* Should we set this? Can't use the value from skb_tx_csum() | |
814 | * as it's not the correct initial L4 checksum to use. */ | |
815 | desc->l4i_chk = 0; | |
816 | ||
817 | desc->byte_cnt = hdr_len; | |
818 | desc->buf_ptr = txq->tso_hdrs_dma + | |
819 | txq->tx_curr_desc * TSO_HEADER_SIZE; | |
968200f3 | 820 | cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC | |
3ae8f4e0 EG |
821 | GEN_CRC; |
822 | ||
968200f3 PK |
823 | /* Defer updating the first command descriptor until all |
824 | * following descriptors have been written. | |
825 | */ | |
826 | if (first_desc) | |
827 | *first_cmd_sts = cmd_sts; | |
828 | else | |
829 | desc->cmd_sts = cmd_sts; | |
830 | ||
3ae8f4e0 EG |
831 | txq->tx_curr_desc++; |
832 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
833 | txq->tx_curr_desc = 0; | |
834 | } | |
835 | ||
836 | static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb, | |
837 | struct net_device *dev) | |
838 | { | |
839 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
840 | int total_len, data_left, ret; | |
841 | int desc_count = 0; | |
842 | struct tso_t tso; | |
843 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
968200f3 PK |
844 | struct tx_desc *first_tx_desc; |
845 | u32 first_cmd_sts = 0; | |
3ae8f4e0 EG |
846 | |
847 | /* Count needed descriptors */ | |
848 | if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) { | |
849 | netdev_dbg(dev, "not enough descriptors for TSO!\n"); | |
850 | return -EBUSY; | |
851 | } | |
852 | ||
968200f3 PK |
853 | first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc]; |
854 | ||
3ae8f4e0 EG |
855 | /* Initialize the TSO handler, and prepare the first payload */ |
856 | tso_start(skb, &tso); | |
857 | ||
858 | total_len = skb->len - hdr_len; | |
859 | while (total_len > 0) { | |
968200f3 | 860 | bool first_desc = (desc_count == 0); |
3ae8f4e0 EG |
861 | char *hdr; |
862 | ||
863 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); | |
864 | total_len -= data_left; | |
865 | desc_count++; | |
866 | ||
867 | /* prepare packet headers: MAC + IP + TCP */ | |
868 | hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE; | |
869 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); | |
968200f3 PK |
870 | txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts, |
871 | first_desc); | |
3ae8f4e0 EG |
872 | |
873 | while (data_left > 0) { | |
874 | int size; | |
875 | desc_count++; | |
876 | ||
877 | size = min_t(int, tso.size, data_left); | |
878 | ret = txq_put_data_tso(dev, txq, skb, tso.data, size, | |
879 | size == data_left, | |
880 | total_len == 0); | |
881 | if (ret) | |
882 | goto err_release; | |
883 | data_left -= size; | |
884 | tso_build_data(skb, &tso, size); | |
885 | } | |
886 | } | |
887 | ||
888 | __skb_queue_tail(&txq->tx_skb, skb); | |
889 | skb_tx_timestamp(skb); | |
890 | ||
968200f3 PK |
891 | /* ensure all other descriptors are written before first cmd_sts */ |
892 | wmb(); | |
893 | first_tx_desc->cmd_sts = first_cmd_sts; | |
894 | ||
3ae8f4e0 EG |
895 | /* clear TX_END status */ |
896 | mp->work_tx_end &= ~(1 << txq->index); | |
897 | ||
898 | /* ensure all descriptors are written before poking hardware */ | |
899 | wmb(); | |
900 | txq_enable(txq); | |
901 | txq->tx_desc_count += desc_count; | |
902 | return 0; | |
903 | err_release: | |
904 | /* TODO: Release all used data descriptors; header descriptors must not | |
905 | * be DMA-unmapped. | |
906 | */ | |
907 | return ret; | |
908 | } | |
909 | ||
13d64285 | 910 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
c9df406f | 911 | { |
eb0519b5 | 912 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 913 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 914 | int frag; |
1da177e4 | 915 | |
13d64285 LB |
916 | for (frag = 0; frag < nr_frags; frag++) { |
917 | skb_frag_t *this_frag; | |
918 | int tx_index; | |
919 | struct tx_desc *desc; | |
920 | ||
921 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
66823b92 LB |
922 | tx_index = txq->tx_curr_desc++; |
923 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
924 | txq->tx_curr_desc = 0; | |
13d64285 | 925 | desc = &txq->tx_desc_area[tx_index]; |
9e911414 | 926 | txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE; |
13d64285 LB |
927 | |
928 | /* | |
929 | * The last fragment will generate an interrupt | |
930 | * which will free the skb on TX completion. | |
931 | */ | |
932 | if (frag == nr_frags - 1) { | |
933 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | | |
934 | ZERO_PADDING | TX_LAST_DESC | | |
935 | TX_ENABLE_INTERRUPT; | |
13d64285 LB |
936 | } else { |
937 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; | |
13d64285 LB |
938 | } |
939 | ||
c9df406f | 940 | desc->l4i_chk = 0; |
9e903e08 | 941 | desc->byte_cnt = skb_frag_size(this_frag); |
9e911414 EG |
942 | desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent, |
943 | this_frag, 0, desc->byte_cnt, | |
944 | DMA_TO_DEVICE); | |
c9df406f | 945 | } |
1da177e4 LT |
946 | } |
947 | ||
ee9e4956 EG |
948 | static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb, |
949 | struct net_device *dev) | |
1da177e4 | 950 | { |
8fa89bf5 | 951 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 952 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 953 | int tx_index; |
cc9754b3 | 954 | struct tx_desc *desc; |
c9df406f | 955 | u32 cmd_sts; |
4df89bd5 | 956 | u16 l4i_chk; |
0a8fa933 | 957 | int length, ret; |
1da177e4 | 958 | |
0a8fa933 | 959 | cmd_sts = 0; |
4df89bd5 | 960 | l4i_chk = 0; |
c9df406f | 961 | |
ee9e4956 EG |
962 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { |
963 | if (net_ratelimit()) | |
964 | netdev_err(dev, "tx queue full?!\n"); | |
965 | return -EBUSY; | |
966 | } | |
967 | ||
0a8fa933 | 968 | ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len); |
ee9e4956 | 969 | if (ret) |
0a8fa933 | 970 | return ret; |
0a8fa933 | 971 | cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
c9df406f | 972 | |
66823b92 LB |
973 | tx_index = txq->tx_curr_desc++; |
974 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
975 | txq->tx_curr_desc = 0; | |
4df89bd5 | 976 | desc = &txq->tx_desc_area[tx_index]; |
9e911414 | 977 | txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; |
4df89bd5 LB |
978 | |
979 | if (nr_frags) { | |
980 | txq_submit_frag_skb(txq, skb); | |
981 | length = skb_headlen(skb); | |
982 | } else { | |
983 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; | |
984 | length = skb->len; | |
985 | } | |
986 | ||
987 | desc->l4i_chk = l4i_chk; | |
988 | desc->byte_cnt = length; | |
eb0519b5 GP |
989 | desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, |
990 | length, DMA_TO_DEVICE); | |
4df89bd5 | 991 | |
99ab08e0 LB |
992 | __skb_queue_tail(&txq->tx_skb, skb); |
993 | ||
3b182d7d RC |
994 | skb_tx_timestamp(skb); |
995 | ||
c9df406f LB |
996 | /* ensure all other descriptors are written before first cmd_sts */ |
997 | wmb(); | |
998 | desc->cmd_sts = cmd_sts; | |
999 | ||
1fa38c58 LB |
1000 | /* clear TX_END status */ |
1001 | mp->work_tx_end &= ~(1 << txq->index); | |
8fa89bf5 | 1002 | |
c9df406f LB |
1003 | /* ensure all descriptors are written before poking hardware */ |
1004 | wmb(); | |
13d64285 | 1005 | txq_enable(txq); |
c9df406f | 1006 | |
13d64285 | 1007 | txq->tx_desc_count += nr_frags + 1; |
4df89bd5 LB |
1008 | |
1009 | return 0; | |
1da177e4 | 1010 | } |
1da177e4 | 1011 | |
0ccfe64d | 1012 | static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 1013 | { |
e5371493 | 1014 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
3ae8f4e0 | 1015 | int length, queue, ret; |
13d64285 | 1016 | struct tx_queue *txq; |
e5ef1de1 | 1017 | struct netdev_queue *nq; |
afdb57a2 | 1018 | |
8fd89211 LB |
1019 | queue = skb_get_queue_mapping(skb); |
1020 | txq = mp->txq + queue; | |
1021 | nq = netdev_get_tx_queue(dev, queue); | |
1022 | ||
c9df406f | 1023 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
7542db8b JP |
1024 | netdev_printk(KERN_DEBUG, dev, |
1025 | "failed to linearize skb with tiny unaligned fragment\n"); | |
c9df406f LB |
1026 | return NETDEV_TX_BUSY; |
1027 | } | |
1028 | ||
73151ce3 RC |
1029 | length = skb->len; |
1030 | ||
3ae8f4e0 EG |
1031 | if (skb_is_gso(skb)) |
1032 | ret = txq_submit_tso(txq, skb, dev); | |
1033 | else | |
ee9e4956 | 1034 | ret = txq_submit_skb(txq, skb, dev); |
3ae8f4e0 | 1035 | if (!ret) { |
73151ce3 | 1036 | txq->tx_bytes += length; |
4df89bd5 | 1037 | txq->tx_packets++; |
c9df406f | 1038 | |
ee9e4956 | 1039 | if (txq->tx_desc_count >= txq->tx_stop_threshold) |
4df89bd5 | 1040 | netif_tx_stop_queue(nq); |
dd11680d EG |
1041 | } else { |
1042 | txq->tx_dropped++; | |
1043 | dev_kfree_skb_any(skb); | |
4df89bd5 | 1044 | } |
c9df406f | 1045 | |
c9df406f | 1046 | return NETDEV_TX_OK; |
1da177e4 LT |
1047 | } |
1048 | ||
c9df406f | 1049 | |
1fa38c58 LB |
1050 | /* tx napi ******************************************************************/ |
1051 | static void txq_kick(struct tx_queue *txq) | |
1052 | { | |
1053 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 1054 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
1055 | u32 hw_desc_ptr; |
1056 | u32 expected_ptr; | |
1057 | ||
8fd89211 | 1058 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 | 1059 | |
37a6084f | 1060 | if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) |
1fa38c58 LB |
1061 | goto out; |
1062 | ||
37a6084f | 1063 | hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); |
1fa38c58 LB |
1064 | expected_ptr = (u32)txq->tx_desc_dma + |
1065 | txq->tx_curr_desc * sizeof(struct tx_desc); | |
1066 | ||
1067 | if (hw_desc_ptr != expected_ptr) | |
1068 | txq_enable(txq); | |
1069 | ||
1070 | out: | |
8fd89211 | 1071 | __netif_tx_unlock(nq); |
1fa38c58 LB |
1072 | |
1073 | mp->work_tx_end &= ~(1 << txq->index); | |
1074 | } | |
1075 | ||
1076 | static int txq_reclaim(struct tx_queue *txq, int budget, int force) | |
1077 | { | |
1078 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 1079 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
1080 | int reclaimed; |
1081 | ||
3aefe2b4 | 1082 | __netif_tx_lock_bh(nq); |
1fa38c58 LB |
1083 | |
1084 | reclaimed = 0; | |
1085 | while (reclaimed < budget && txq->tx_desc_count > 0) { | |
1086 | int tx_index; | |
1087 | struct tx_desc *desc; | |
1088 | u32 cmd_sts; | |
9e911414 | 1089 | char desc_dma_map; |
1fa38c58 LB |
1090 | |
1091 | tx_index = txq->tx_used_desc; | |
1092 | desc = &txq->tx_desc_area[tx_index]; | |
9e911414 EG |
1093 | desc_dma_map = txq->tx_desc_mapping[tx_index]; |
1094 | ||
1fa38c58 LB |
1095 | cmd_sts = desc->cmd_sts; |
1096 | ||
1097 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { | |
1098 | if (!force) | |
1099 | break; | |
1100 | desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; | |
1101 | } | |
1102 | ||
1103 | txq->tx_used_desc = tx_index + 1; | |
1104 | if (txq->tx_used_desc == txq->tx_ring_size) | |
1105 | txq->tx_used_desc = 0; | |
1106 | ||
1107 | reclaimed++; | |
1108 | txq->tx_desc_count--; | |
1109 | ||
9e911414 EG |
1110 | if (!IS_TSO_HEADER(txq, desc->buf_ptr)) { |
1111 | ||
1112 | if (desc_dma_map == DESC_DMA_MAP_PAGE) | |
1113 | dma_unmap_page(mp->dev->dev.parent, | |
1114 | desc->buf_ptr, | |
1115 | desc->byte_cnt, | |
1116 | DMA_TO_DEVICE); | |
1117 | else | |
1118 | dma_unmap_single(mp->dev->dev.parent, | |
1119 | desc->buf_ptr, | |
1120 | desc->byte_cnt, | |
1121 | DMA_TO_DEVICE); | |
1122 | } | |
2c2a9cbd KB |
1123 | |
1124 | if (cmd_sts & TX_ENABLE_INTERRUPT) { | |
1125 | struct sk_buff *skb = __skb_dequeue(&txq->tx_skb); | |
1126 | ||
1127 | if (!WARN_ON(!skb)) | |
1128 | dev_kfree_skb(skb); | |
1129 | } | |
1fa38c58 LB |
1130 | |
1131 | if (cmd_sts & ERROR_SUMMARY) { | |
7542db8b | 1132 | netdev_info(mp->dev, "tx error\n"); |
1fa38c58 LB |
1133 | mp->dev->stats.tx_errors++; |
1134 | } | |
1135 | ||
1fa38c58 LB |
1136 | } |
1137 | ||
3aefe2b4 | 1138 | __netif_tx_unlock_bh(nq); |
8fd89211 | 1139 | |
1fa38c58 LB |
1140 | if (reclaimed < budget) |
1141 | mp->work_tx &= ~(1 << txq->index); | |
1142 | ||
1fa38c58 LB |
1143 | return reclaimed; |
1144 | } | |
1145 | ||
1146 | ||
89df5fdc LB |
1147 | /* tx rate control **********************************************************/ |
1148 | /* | |
1149 | * Set total maximum TX rate (shared by all TX queues for this port) | |
1150 | * to 'rate' bits per second, with a maximum burst of 'burst' bytes. | |
1151 | */ | |
1152 | static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) | |
1153 | { | |
1154 | int token_rate; | |
1155 | int mtu; | |
1156 | int bucket_size; | |
1157 | ||
452503eb | 1158 | token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); |
89df5fdc LB |
1159 | if (token_rate > 1023) |
1160 | token_rate = 1023; | |
1161 | ||
1162 | mtu = (mp->dev->mtu + 255) >> 8; | |
1163 | if (mtu > 63) | |
1164 | mtu = 63; | |
1165 | ||
1166 | bucket_size = (burst + 255) >> 8; | |
1167 | if (bucket_size > 65535) | |
1168 | bucket_size = 65535; | |
1169 | ||
457b1d5a LB |
1170 | switch (mp->shared->tx_bw_control) { |
1171 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f LB |
1172 | wrlp(mp, TX_BW_RATE, token_rate); |
1173 | wrlp(mp, TX_BW_MTU, mtu); | |
1174 | wrlp(mp, TX_BW_BURST, bucket_size); | |
457b1d5a LB |
1175 | break; |
1176 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f LB |
1177 | wrlp(mp, TX_BW_RATE_MOVED, token_rate); |
1178 | wrlp(mp, TX_BW_MTU_MOVED, mtu); | |
1179 | wrlp(mp, TX_BW_BURST_MOVED, bucket_size); | |
457b1d5a | 1180 | break; |
1e881592 | 1181 | } |
89df5fdc LB |
1182 | } |
1183 | ||
1184 | static void txq_set_rate(struct tx_queue *txq, int rate, int burst) | |
1185 | { | |
1186 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1187 | int token_rate; | |
1188 | int bucket_size; | |
1189 | ||
452503eb | 1190 | token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); |
89df5fdc LB |
1191 | if (token_rate > 1023) |
1192 | token_rate = 1023; | |
1193 | ||
1194 | bucket_size = (burst + 255) >> 8; | |
1195 | if (bucket_size > 65535) | |
1196 | bucket_size = 65535; | |
1197 | ||
37a6084f LB |
1198 | wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); |
1199 | wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); | |
89df5fdc LB |
1200 | } |
1201 | ||
1202 | static void txq_set_fixed_prio_mode(struct tx_queue *txq) | |
1203 | { | |
1204 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1205 | int off; | |
1206 | u32 val; | |
1207 | ||
1208 | /* | |
1209 | * Turn on fixed priority mode. | |
1210 | */ | |
457b1d5a LB |
1211 | off = 0; |
1212 | switch (mp->shared->tx_bw_control) { | |
1213 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f | 1214 | off = TXQ_FIX_PRIO_CONF; |
457b1d5a LB |
1215 | break; |
1216 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f | 1217 | off = TXQ_FIX_PRIO_CONF_MOVED; |
457b1d5a LB |
1218 | break; |
1219 | } | |
89df5fdc | 1220 | |
457b1d5a | 1221 | if (off) { |
37a6084f | 1222 | val = rdlp(mp, off); |
457b1d5a | 1223 | val |= 1 << txq->index; |
37a6084f | 1224 | wrlp(mp, off, val); |
457b1d5a | 1225 | } |
89df5fdc LB |
1226 | } |
1227 | ||
89df5fdc | 1228 | |
c9df406f | 1229 | /* mii management interface *************************************************/ |
0a9e413b | 1230 | static void mv643xx_eth_adjust_link(struct net_device *dev) |
260055bb | 1231 | { |
0a9e413b | 1232 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
260055bb PS |
1233 | u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
1234 | u32 autoneg_disable = FORCE_LINK_PASS | | |
1235 | DISABLE_AUTO_NEG_SPEED_GMII | | |
1236 | DISABLE_AUTO_NEG_FOR_FLOW_CTRL | | |
1237 | DISABLE_AUTO_NEG_FOR_DUPLEX; | |
1238 | ||
1239 | if (mp->phy->autoneg == AUTONEG_ENABLE) { | |
1240 | /* enable auto negotiation */ | |
1241 | pscr &= ~autoneg_disable; | |
1242 | goto out_write; | |
1243 | } | |
1244 | ||
1245 | pscr |= autoneg_disable; | |
1246 | ||
1247 | if (mp->phy->speed == SPEED_1000) { | |
1248 | /* force gigabit, half duplex not supported */ | |
1249 | pscr |= SET_GMII_SPEED_TO_1000; | |
1250 | pscr |= SET_FULL_DUPLEX_MODE; | |
1251 | goto out_write; | |
1252 | } | |
1253 | ||
1254 | pscr &= ~SET_GMII_SPEED_TO_1000; | |
1255 | ||
1256 | if (mp->phy->speed == SPEED_100) | |
1257 | pscr |= SET_MII_SPEED_TO_100; | |
1258 | else | |
1259 | pscr &= ~SET_MII_SPEED_TO_100; | |
1260 | ||
1261 | if (mp->phy->duplex == DUPLEX_FULL) | |
1262 | pscr |= SET_FULL_DUPLEX_MODE; | |
1263 | else | |
1264 | pscr &= ~SET_FULL_DUPLEX_MODE; | |
1265 | ||
1266 | out_write: | |
1267 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); | |
1268 | } | |
1269 | ||
8fd89211 LB |
1270 | /* statistics ***************************************************************/ |
1271 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) | |
1272 | { | |
1273 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1274 | struct net_device_stats *stats = &dev->stats; | |
1275 | unsigned long tx_packets = 0; | |
1276 | unsigned long tx_bytes = 0; | |
1277 | unsigned long tx_dropped = 0; | |
1278 | int i; | |
1279 | ||
1280 | for (i = 0; i < mp->txq_count; i++) { | |
1281 | struct tx_queue *txq = mp->txq + i; | |
1282 | ||
1283 | tx_packets += txq->tx_packets; | |
1284 | tx_bytes += txq->tx_bytes; | |
1285 | tx_dropped += txq->tx_dropped; | |
1286 | } | |
1287 | ||
1288 | stats->tx_packets = tx_packets; | |
1289 | stats->tx_bytes = tx_bytes; | |
1290 | stats->tx_dropped = tx_dropped; | |
1291 | ||
1292 | return stats; | |
1293 | } | |
1294 | ||
fc32b0e2 | 1295 | static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 1296 | { |
fc32b0e2 | 1297 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
1da177e4 LT |
1298 | } |
1299 | ||
fc32b0e2 | 1300 | static void mib_counters_clear(struct mv643xx_eth_private *mp) |
d0412d96 | 1301 | { |
fc32b0e2 LB |
1302 | int i; |
1303 | ||
1304 | for (i = 0; i < 0x80; i += 4) | |
1305 | mib_read(mp, i); | |
302476c9 PZ |
1306 | |
1307 | /* Clear non MIB hw counters also */ | |
1308 | rdlp(mp, RX_DISCARD_FRAME_CNT); | |
1309 | rdlp(mp, RX_OVERRUN_FRAME_CNT); | |
c9df406f | 1310 | } |
d0412d96 | 1311 | |
fc32b0e2 | 1312 | static void mib_counters_update(struct mv643xx_eth_private *mp) |
c9df406f | 1313 | { |
e5371493 | 1314 | struct mib_counters *p = &mp->mib_counters; |
4b8e3655 | 1315 | |
57e8f26a | 1316 | spin_lock_bh(&mp->mib_counters_lock); |
fc32b0e2 | 1317 | p->good_octets_received += mib_read(mp, 0x00); |
fc32b0e2 LB |
1318 | p->bad_octets_received += mib_read(mp, 0x08); |
1319 | p->internal_mac_transmit_err += mib_read(mp, 0x0c); | |
1320 | p->good_frames_received += mib_read(mp, 0x10); | |
1321 | p->bad_frames_received += mib_read(mp, 0x14); | |
1322 | p->broadcast_frames_received += mib_read(mp, 0x18); | |
1323 | p->multicast_frames_received += mib_read(mp, 0x1c); | |
1324 | p->frames_64_octets += mib_read(mp, 0x20); | |
1325 | p->frames_65_to_127_octets += mib_read(mp, 0x24); | |
1326 | p->frames_128_to_255_octets += mib_read(mp, 0x28); | |
1327 | p->frames_256_to_511_octets += mib_read(mp, 0x2c); | |
1328 | p->frames_512_to_1023_octets += mib_read(mp, 0x30); | |
1329 | p->frames_1024_to_max_octets += mib_read(mp, 0x34); | |
1330 | p->good_octets_sent += mib_read(mp, 0x38); | |
fc32b0e2 LB |
1331 | p->good_frames_sent += mib_read(mp, 0x40); |
1332 | p->excessive_collision += mib_read(mp, 0x44); | |
1333 | p->multicast_frames_sent += mib_read(mp, 0x48); | |
1334 | p->broadcast_frames_sent += mib_read(mp, 0x4c); | |
1335 | p->unrec_mac_control_received += mib_read(mp, 0x50); | |
1336 | p->fc_sent += mib_read(mp, 0x54); | |
1337 | p->good_fc_received += mib_read(mp, 0x58); | |
1338 | p->bad_fc_received += mib_read(mp, 0x5c); | |
1339 | p->undersize_received += mib_read(mp, 0x60); | |
1340 | p->fragments_received += mib_read(mp, 0x64); | |
1341 | p->oversize_received += mib_read(mp, 0x68); | |
1342 | p->jabber_received += mib_read(mp, 0x6c); | |
1343 | p->mac_receive_error += mib_read(mp, 0x70); | |
1344 | p->bad_crc_event += mib_read(mp, 0x74); | |
1345 | p->collision += mib_read(mp, 0x78); | |
1346 | p->late_collision += mib_read(mp, 0x7c); | |
302476c9 PZ |
1347 | /* Non MIB hardware counters */ |
1348 | p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT); | |
1349 | p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT); | |
57e8f26a | 1350 | spin_unlock_bh(&mp->mib_counters_lock); |
4ff3495a LB |
1351 | } |
1352 | ||
1353 | static void mib_counters_timer_wrapper(unsigned long _mp) | |
1354 | { | |
1355 | struct mv643xx_eth_private *mp = (void *)_mp; | |
4ff3495a | 1356 | mib_counters_update(mp); |
041b4ddb | 1357 | mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); |
d0412d96 JC |
1358 | } |
1359 | ||
c9df406f | 1360 | |
3e508034 LB |
1361 | /* interrupt coalescing *****************************************************/ |
1362 | /* | |
1363 | * Hardware coalescing parameters are set in units of 64 t_clk | |
1364 | * cycles. I.e.: | |
1365 | * | |
1366 | * coal_delay_in_usec = 64000000 * register_value / t_clk_rate | |
1367 | * | |
1368 | * register_value = coal_delay_in_usec * t_clk_rate / 64000000 | |
1369 | * | |
1370 | * In the ->set*() methods, we round the computed register value | |
1371 | * to the nearest integer. | |
1372 | */ | |
1373 | static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) | |
1374 | { | |
1375 | u32 val = rdlp(mp, SDMA_CONFIG); | |
1376 | u64 temp; | |
1377 | ||
1378 | if (mp->shared->extended_rx_coal_limit) | |
1379 | temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); | |
1380 | else | |
1381 | temp = (val & 0x003fff00) >> 8; | |
1382 | ||
1383 | temp *= 64000000; | |
452503eb | 1384 | do_div(temp, mp->t_clk); |
3e508034 LB |
1385 | |
1386 | return (unsigned int)temp; | |
1387 | } | |
1388 | ||
1389 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1390 | { | |
1391 | u64 temp; | |
1392 | u32 val; | |
1393 | ||
452503eb | 1394 | temp = (u64)usec * mp->t_clk; |
3e508034 LB |
1395 | temp += 31999999; |
1396 | do_div(temp, 64000000); | |
1397 | ||
1398 | val = rdlp(mp, SDMA_CONFIG); | |
1399 | if (mp->shared->extended_rx_coal_limit) { | |
1400 | if (temp > 0xffff) | |
1401 | temp = 0xffff; | |
1402 | val &= ~0x023fff80; | |
1403 | val |= (temp & 0x8000) << 10; | |
1404 | val |= (temp & 0x7fff) << 7; | |
1405 | } else { | |
1406 | if (temp > 0x3fff) | |
1407 | temp = 0x3fff; | |
1408 | val &= ~0x003fff00; | |
1409 | val |= (temp & 0x3fff) << 8; | |
1410 | } | |
1411 | wrlp(mp, SDMA_CONFIG, val); | |
1412 | } | |
1413 | ||
1414 | static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) | |
1415 | { | |
1416 | u64 temp; | |
1417 | ||
1418 | temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; | |
1419 | temp *= 64000000; | |
452503eb | 1420 | do_div(temp, mp->t_clk); |
3e508034 LB |
1421 | |
1422 | return (unsigned int)temp; | |
1423 | } | |
1424 | ||
1425 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1426 | { | |
1427 | u64 temp; | |
1428 | ||
452503eb | 1429 | temp = (u64)usec * mp->t_clk; |
3e508034 LB |
1430 | temp += 31999999; |
1431 | do_div(temp, 64000000); | |
1432 | ||
1433 | if (temp > 0x3fff) | |
1434 | temp = 0x3fff; | |
1435 | ||
1436 | wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); | |
1437 | } | |
1438 | ||
1439 | ||
c9df406f | 1440 | /* ethtool ******************************************************************/ |
e5371493 | 1441 | struct mv643xx_eth_stats { |
c9df406f LB |
1442 | char stat_string[ETH_GSTRING_LEN]; |
1443 | int sizeof_stat; | |
16820054 LB |
1444 | int netdev_off; |
1445 | int mp_off; | |
c9df406f LB |
1446 | }; |
1447 | ||
16820054 LB |
1448 | #define SSTAT(m) \ |
1449 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ | |
1450 | offsetof(struct net_device, stats.m), -1 } | |
1451 | ||
1452 | #define MIBSTAT(m) \ | |
1453 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ | |
1454 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } | |
1455 | ||
1456 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { | |
1457 | SSTAT(rx_packets), | |
1458 | SSTAT(tx_packets), | |
1459 | SSTAT(rx_bytes), | |
1460 | SSTAT(tx_bytes), | |
1461 | SSTAT(rx_errors), | |
1462 | SSTAT(tx_errors), | |
1463 | SSTAT(rx_dropped), | |
1464 | SSTAT(tx_dropped), | |
1465 | MIBSTAT(good_octets_received), | |
1466 | MIBSTAT(bad_octets_received), | |
1467 | MIBSTAT(internal_mac_transmit_err), | |
1468 | MIBSTAT(good_frames_received), | |
1469 | MIBSTAT(bad_frames_received), | |
1470 | MIBSTAT(broadcast_frames_received), | |
1471 | MIBSTAT(multicast_frames_received), | |
1472 | MIBSTAT(frames_64_octets), | |
1473 | MIBSTAT(frames_65_to_127_octets), | |
1474 | MIBSTAT(frames_128_to_255_octets), | |
1475 | MIBSTAT(frames_256_to_511_octets), | |
1476 | MIBSTAT(frames_512_to_1023_octets), | |
1477 | MIBSTAT(frames_1024_to_max_octets), | |
1478 | MIBSTAT(good_octets_sent), | |
1479 | MIBSTAT(good_frames_sent), | |
1480 | MIBSTAT(excessive_collision), | |
1481 | MIBSTAT(multicast_frames_sent), | |
1482 | MIBSTAT(broadcast_frames_sent), | |
1483 | MIBSTAT(unrec_mac_control_received), | |
1484 | MIBSTAT(fc_sent), | |
1485 | MIBSTAT(good_fc_received), | |
1486 | MIBSTAT(bad_fc_received), | |
1487 | MIBSTAT(undersize_received), | |
1488 | MIBSTAT(fragments_received), | |
1489 | MIBSTAT(oversize_received), | |
1490 | MIBSTAT(jabber_received), | |
1491 | MIBSTAT(mac_receive_error), | |
1492 | MIBSTAT(bad_crc_event), | |
1493 | MIBSTAT(collision), | |
1494 | MIBSTAT(late_collision), | |
302476c9 PZ |
1495 | MIBSTAT(rx_discard), |
1496 | MIBSTAT(rx_overrun), | |
c9df406f LB |
1497 | }; |
1498 | ||
10a9948d | 1499 | static int |
6bdf576e LB |
1500 | mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, |
1501 | struct ethtool_cmd *cmd) | |
d0412d96 | 1502 | { |
d0412d96 JC |
1503 | int err; |
1504 | ||
ed94493f LB |
1505 | err = phy_read_status(mp->phy); |
1506 | if (err == 0) | |
1507 | err = phy_ethtool_gset(mp->phy, cmd); | |
d0412d96 | 1508 | |
fc32b0e2 LB |
1509 | /* |
1510 | * The MAC does not support 1000baseT_Half. | |
1511 | */ | |
d0412d96 JC |
1512 | cmd->supported &= ~SUPPORTED_1000baseT_Half; |
1513 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1514 | ||
1515 | return err; | |
1516 | } | |
1517 | ||
10a9948d | 1518 | static int |
6bdf576e | 1519 | mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, |
10a9948d | 1520 | struct ethtool_cmd *cmd) |
bedfe324 | 1521 | { |
81600eea LB |
1522 | u32 port_status; |
1523 | ||
37a6084f | 1524 | port_status = rdlp(mp, PORT_STATUS); |
81600eea | 1525 | |
bedfe324 LB |
1526 | cmd->supported = SUPPORTED_MII; |
1527 | cmd->advertising = ADVERTISED_MII; | |
81600eea LB |
1528 | switch (port_status & PORT_SPEED_MASK) { |
1529 | case PORT_SPEED_10: | |
70739497 | 1530 | ethtool_cmd_speed_set(cmd, SPEED_10); |
81600eea LB |
1531 | break; |
1532 | case PORT_SPEED_100: | |
70739497 | 1533 | ethtool_cmd_speed_set(cmd, SPEED_100); |
81600eea LB |
1534 | break; |
1535 | case PORT_SPEED_1000: | |
70739497 | 1536 | ethtool_cmd_speed_set(cmd, SPEED_1000); |
81600eea LB |
1537 | break; |
1538 | default: | |
1539 | cmd->speed = -1; | |
1540 | break; | |
1541 | } | |
1542 | cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; | |
bedfe324 LB |
1543 | cmd->port = PORT_MII; |
1544 | cmd->phy_address = 0; | |
1545 | cmd->transceiver = XCVR_INTERNAL; | |
1546 | cmd->autoneg = AUTONEG_DISABLE; | |
1547 | cmd->maxtxpkt = 1; | |
1548 | cmd->maxrxpkt = 1; | |
1549 | ||
1550 | return 0; | |
1551 | } | |
1552 | ||
3871c387 MS |
1553 | static void |
1554 | mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1555 | { | |
1556 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1557 | wol->supported = 0; | |
1558 | wol->wolopts = 0; | |
1559 | if (mp->phy) | |
1560 | phy_ethtool_get_wol(mp->phy, wol); | |
1561 | } | |
1562 | ||
1563 | static int | |
1564 | mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1565 | { | |
1566 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1567 | int err; | |
1568 | ||
1569 | if (mp->phy == NULL) | |
1570 | return -EOPNOTSUPP; | |
1571 | ||
1572 | err = phy_ethtool_set_wol(mp->phy, wol); | |
1573 | /* Given that mv643xx_eth works without the marvell-specific PHY driver, | |
1574 | * this debugging hint is useful to have. | |
1575 | */ | |
1576 | if (err == -EOPNOTSUPP) | |
1577 | netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n"); | |
1578 | return err; | |
1579 | } | |
1580 | ||
6bdf576e LB |
1581 | static int |
1582 | mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1583 | { | |
1584 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1585 | ||
1586 | if (mp->phy != NULL) | |
1587 | return mv643xx_eth_get_settings_phy(mp, cmd); | |
1588 | else | |
1589 | return mv643xx_eth_get_settings_phyless(mp, cmd); | |
1590 | } | |
1591 | ||
10a9948d LB |
1592 | static int |
1593 | mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1da177e4 | 1594 | { |
e5371493 | 1595 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
260055bb | 1596 | int ret; |
ab4384a6 | 1597 | |
6bdf576e LB |
1598 | if (mp->phy == NULL) |
1599 | return -EINVAL; | |
1600 | ||
fc32b0e2 LB |
1601 | /* |
1602 | * The MAC does not support 1000baseT_Half. | |
1603 | */ | |
1604 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1605 | ||
260055bb PS |
1606 | ret = phy_ethtool_sset(mp->phy, cmd); |
1607 | if (!ret) | |
0a9e413b | 1608 | mv643xx_eth_adjust_link(dev); |
260055bb | 1609 | return ret; |
c9df406f | 1610 | } |
1da177e4 | 1611 | |
fc32b0e2 LB |
1612 | static void mv643xx_eth_get_drvinfo(struct net_device *dev, |
1613 | struct ethtool_drvinfo *drvinfo) | |
c9df406f | 1614 | { |
6f39da2c AL |
1615 | strlcpy(drvinfo->driver, mv643xx_eth_driver_name, |
1616 | sizeof(drvinfo->driver)); | |
68aad78c | 1617 | strlcpy(drvinfo->version, mv643xx_eth_driver_version, |
6f39da2c AL |
1618 | sizeof(drvinfo->version)); |
1619 | strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); | |
1620 | strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info)); | |
c9df406f | 1621 | } |
1da177e4 | 1622 | |
fc32b0e2 | 1623 | static int mv643xx_eth_nway_reset(struct net_device *dev) |
c9df406f | 1624 | { |
e5371493 | 1625 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1626 | |
6bdf576e LB |
1627 | if (mp->phy == NULL) |
1628 | return -EINVAL; | |
1da177e4 | 1629 | |
6bdf576e | 1630 | return genphy_restart_aneg(mp->phy); |
bedfe324 LB |
1631 | } |
1632 | ||
3e508034 LB |
1633 | static int |
1634 | mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1635 | { | |
1636 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1637 | ||
1638 | ec->rx_coalesce_usecs = get_rx_coal(mp); | |
1639 | ec->tx_coalesce_usecs = get_tx_coal(mp); | |
1640 | ||
1641 | return 0; | |
1642 | } | |
1643 | ||
1644 | static int | |
1645 | mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1646 | { | |
1647 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1648 | ||
1649 | set_rx_coal(mp, ec->rx_coalesce_usecs); | |
1650 | set_tx_coal(mp, ec->tx_coalesce_usecs); | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
e7d2f4db LB |
1655 | static void |
1656 | mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1657 | { | |
1658 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1659 | ||
1660 | er->rx_max_pending = 4096; | |
1661 | er->tx_max_pending = 4096; | |
e7d2f4db LB |
1662 | |
1663 | er->rx_pending = mp->rx_ring_size; | |
1664 | er->tx_pending = mp->tx_ring_size; | |
e7d2f4db LB |
1665 | } |
1666 | ||
1667 | static int | |
1668 | mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1669 | { | |
1670 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1671 | ||
1672 | if (er->rx_mini_pending || er->rx_jumbo_pending) | |
1673 | return -EINVAL; | |
1674 | ||
1675 | mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; | |
ee9e4956 EG |
1676 | mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending, |
1677 | MV643XX_MAX_SKB_DESCS * 2, 4096); | |
1678 | if (mp->tx_ring_size != er->tx_pending) | |
1679 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", | |
1680 | mp->tx_ring_size, er->tx_pending); | |
e7d2f4db LB |
1681 | |
1682 | if (netif_running(dev)) { | |
1683 | mv643xx_eth_stop(dev); | |
1684 | if (mv643xx_eth_open(dev)) { | |
7542db8b JP |
1685 | netdev_err(dev, |
1686 | "fatal error on re-opening device after ring param change\n"); | |
e7d2f4db LB |
1687 | return -ENOMEM; |
1688 | } | |
1689 | } | |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
d888b373 LB |
1694 | |
1695 | static int | |
c8f44aff | 1696 | mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features) |
d888b373 LB |
1697 | { |
1698 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
3ad9b358 | 1699 | bool rx_csum = features & NETIF_F_RXCSUM; |
d888b373 LB |
1700 | |
1701 | wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); | |
1702 | ||
1703 | return 0; | |
1704 | } | |
1705 | ||
fc32b0e2 LB |
1706 | static void mv643xx_eth_get_strings(struct net_device *dev, |
1707 | uint32_t stringset, uint8_t *data) | |
c9df406f LB |
1708 | { |
1709 | int i; | |
1da177e4 | 1710 | |
fc32b0e2 LB |
1711 | if (stringset == ETH_SS_STATS) { |
1712 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { | |
c9df406f | 1713 | memcpy(data + i * ETH_GSTRING_LEN, |
16820054 | 1714 | mv643xx_eth_stats[i].stat_string, |
e5371493 | 1715 | ETH_GSTRING_LEN); |
c9df406f | 1716 | } |
c9df406f LB |
1717 | } |
1718 | } | |
1da177e4 | 1719 | |
fc32b0e2 LB |
1720 | static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, |
1721 | struct ethtool_stats *stats, | |
1722 | uint64_t *data) | |
c9df406f | 1723 | { |
b9873841 | 1724 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 1725 | int i; |
1da177e4 | 1726 | |
8fd89211 | 1727 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 1728 | mib_counters_update(mp); |
1da177e4 | 1729 | |
16820054 LB |
1730 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
1731 | const struct mv643xx_eth_stats *stat; | |
1732 | void *p; | |
1733 | ||
1734 | stat = mv643xx_eth_stats + i; | |
1735 | ||
1736 | if (stat->netdev_off >= 0) | |
1737 | p = ((void *)mp->dev) + stat->netdev_off; | |
1738 | else | |
1739 | p = ((void *)mp) + stat->mp_off; | |
1740 | ||
1741 | data[i] = (stat->sizeof_stat == 8) ? | |
1742 | *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1743 | } |
c9df406f | 1744 | } |
1da177e4 | 1745 | |
fc32b0e2 | 1746 | static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) |
c9df406f | 1747 | { |
fc32b0e2 | 1748 | if (sset == ETH_SS_STATS) |
16820054 | 1749 | return ARRAY_SIZE(mv643xx_eth_stats); |
fc32b0e2 LB |
1750 | |
1751 | return -EOPNOTSUPP; | |
c9df406f | 1752 | } |
1da177e4 | 1753 | |
e5371493 | 1754 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
fc32b0e2 LB |
1755 | .get_settings = mv643xx_eth_get_settings, |
1756 | .set_settings = mv643xx_eth_set_settings, | |
1757 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1758 | .nway_reset = mv643xx_eth_nway_reset, | |
ed4ba4b5 | 1759 | .get_link = ethtool_op_get_link, |
3e508034 LB |
1760 | .get_coalesce = mv643xx_eth_get_coalesce, |
1761 | .set_coalesce = mv643xx_eth_set_coalesce, | |
e7d2f4db LB |
1762 | .get_ringparam = mv643xx_eth_get_ringparam, |
1763 | .set_ringparam = mv643xx_eth_set_ringparam, | |
fc32b0e2 LB |
1764 | .get_strings = mv643xx_eth_get_strings, |
1765 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
e5371493 | 1766 | .get_sset_count = mv643xx_eth_get_sset_count, |
ebad0a8d | 1767 | .get_ts_info = ethtool_op_get_ts_info, |
3871c387 MS |
1768 | .get_wol = mv643xx_eth_get_wol, |
1769 | .set_wol = mv643xx_eth_set_wol, | |
c9df406f | 1770 | }; |
1da177e4 | 1771 | |
bea3348e | 1772 | |
c9df406f | 1773 | /* address handling *********************************************************/ |
5daffe94 | 1774 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1775 | { |
66e63ffb LB |
1776 | unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); |
1777 | unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); | |
1da177e4 | 1778 | |
5daffe94 LB |
1779 | addr[0] = (mac_h >> 24) & 0xff; |
1780 | addr[1] = (mac_h >> 16) & 0xff; | |
1781 | addr[2] = (mac_h >> 8) & 0xff; | |
1782 | addr[3] = mac_h & 0xff; | |
1783 | addr[4] = (mac_l >> 8) & 0xff; | |
1784 | addr[5] = mac_l & 0xff; | |
c9df406f | 1785 | } |
1da177e4 | 1786 | |
66e63ffb | 1787 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1788 | { |
66e63ffb LB |
1789 | wrlp(mp, MAC_ADDR_HIGH, |
1790 | (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); | |
1791 | wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); | |
c9df406f | 1792 | } |
d0412d96 | 1793 | |
66e63ffb | 1794 | static u32 uc_addr_filter_mask(struct net_device *dev) |
c9df406f | 1795 | { |
ccffad25 | 1796 | struct netdev_hw_addr *ha; |
66e63ffb | 1797 | u32 nibbles; |
1da177e4 | 1798 | |
66e63ffb LB |
1799 | if (dev->flags & IFF_PROMISC) |
1800 | return 0; | |
1da177e4 | 1801 | |
66e63ffb | 1802 | nibbles = 1 << (dev->dev_addr[5] & 0x0f); |
32e7bfc4 | 1803 | netdev_for_each_uc_addr(ha, dev) { |
ccffad25 | 1804 | if (memcmp(dev->dev_addr, ha->addr, 5)) |
66e63ffb | 1805 | return 0; |
ccffad25 | 1806 | if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0) |
66e63ffb | 1807 | return 0; |
ff561eef | 1808 | |
ccffad25 | 1809 | nibbles |= 1 << (ha->addr[5] & 0x0f); |
66e63ffb | 1810 | } |
1da177e4 | 1811 | |
66e63ffb | 1812 | return nibbles; |
1da177e4 LT |
1813 | } |
1814 | ||
66e63ffb | 1815 | static void mv643xx_eth_program_unicast_filter(struct net_device *dev) |
1da177e4 | 1816 | { |
e5371493 | 1817 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1818 | u32 port_config; |
1819 | u32 nibbles; | |
1820 | int i; | |
1da177e4 | 1821 | |
cc9754b3 | 1822 | uc_addr_set(mp, dev->dev_addr); |
1da177e4 | 1823 | |
6877f54e PS |
1824 | port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE; |
1825 | ||
66e63ffb LB |
1826 | nibbles = uc_addr_filter_mask(dev); |
1827 | if (!nibbles) { | |
1828 | port_config |= UNICAST_PROMISCUOUS_MODE; | |
6877f54e | 1829 | nibbles = 0xffff; |
66e63ffb LB |
1830 | } |
1831 | ||
1832 | for (i = 0; i < 16; i += 4) { | |
1833 | int off = UNICAST_TABLE(mp->port_num) + i; | |
1834 | u32 v; | |
1835 | ||
1836 | v = 0; | |
1837 | if (nibbles & 1) | |
1838 | v |= 0x00000001; | |
1839 | if (nibbles & 2) | |
1840 | v |= 0x00000100; | |
1841 | if (nibbles & 4) | |
1842 | v |= 0x00010000; | |
1843 | if (nibbles & 8) | |
1844 | v |= 0x01000000; | |
1845 | nibbles >>= 4; | |
1846 | ||
1847 | wrl(mp, off, v); | |
1848 | } | |
1849 | ||
66e63ffb | 1850 | wrlp(mp, PORT_CONFIG, port_config); |
1da177e4 LT |
1851 | } |
1852 | ||
69876569 LB |
1853 | static int addr_crc(unsigned char *addr) |
1854 | { | |
1855 | int crc = 0; | |
1856 | int i; | |
1857 | ||
1858 | for (i = 0; i < 6; i++) { | |
1859 | int j; | |
1860 | ||
1861 | crc = (crc ^ addr[i]) << 8; | |
1862 | for (j = 7; j >= 0; j--) { | |
1863 | if (crc & (0x100 << j)) | |
1864 | crc ^= 0x107 << j; | |
1865 | } | |
1866 | } | |
1867 | ||
1868 | return crc; | |
1869 | } | |
1870 | ||
66e63ffb | 1871 | static void mv643xx_eth_program_multicast_filter(struct net_device *dev) |
1da177e4 | 1872 | { |
fc32b0e2 | 1873 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1874 | u32 *mc_spec; |
1875 | u32 *mc_other; | |
22bedad3 | 1876 | struct netdev_hw_addr *ha; |
fc32b0e2 | 1877 | int i; |
c8aaea25 | 1878 | |
8b711d6d JP |
1879 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) |
1880 | goto promiscuous; | |
c8aaea25 | 1881 | |
8b711d6d JP |
1882 | /* Allocate both mc_spec and mc_other tables */ |
1883 | mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC); | |
1884 | if (!mc_spec) | |
1885 | goto promiscuous; | |
1886 | mc_other = &mc_spec[64]; | |
66e63ffb | 1887 | |
22bedad3 JP |
1888 | netdev_for_each_mc_addr(ha, dev) { |
1889 | u8 *a = ha->addr; | |
66e63ffb | 1890 | u32 *table; |
8b711d6d | 1891 | u8 entry; |
1da177e4 | 1892 | |
fc32b0e2 | 1893 | if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { |
66e63ffb LB |
1894 | table = mc_spec; |
1895 | entry = a[5]; | |
fc32b0e2 | 1896 | } else { |
66e63ffb LB |
1897 | table = mc_other; |
1898 | entry = addr_crc(a); | |
fc32b0e2 | 1899 | } |
66e63ffb | 1900 | |
2b448334 | 1901 | table[entry >> 2] |= 1 << (8 * (entry & 3)); |
fc32b0e2 | 1902 | } |
66e63ffb | 1903 | |
8b711d6d JP |
1904 | for (i = 0; i < 64; i++) { |
1905 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32), | |
1906 | mc_spec[i]); | |
1907 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32), | |
1908 | mc_other[i]); | |
66e63ffb LB |
1909 | } |
1910 | ||
1911 | kfree(mc_spec); | |
8b711d6d JP |
1912 | return; |
1913 | ||
1914 | promiscuous: | |
1915 | for (i = 0; i < 64; i++) { | |
1916 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32), | |
1917 | 0x01010101u); | |
1918 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32), | |
1919 | 0x01010101u); | |
1920 | } | |
66e63ffb LB |
1921 | } |
1922 | ||
1923 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
1924 | { | |
1925 | mv643xx_eth_program_unicast_filter(dev); | |
1926 | mv643xx_eth_program_multicast_filter(dev); | |
1927 | } | |
1928 | ||
1929 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
1930 | { | |
1931 | struct sockaddr *sa = addr; | |
1932 | ||
a29ec08a | 1933 | if (!is_valid_ether_addr(sa->sa_data)) |
504f9b5a | 1934 | return -EADDRNOTAVAIL; |
a29ec08a | 1935 | |
66e63ffb LB |
1936 | memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); |
1937 | ||
1938 | netif_addr_lock_bh(dev); | |
1939 | mv643xx_eth_program_unicast_filter(dev); | |
1940 | netif_addr_unlock_bh(dev); | |
1941 | ||
1942 | return 0; | |
c9df406f | 1943 | } |
c8aaea25 | 1944 | |
c8aaea25 | 1945 | |
c9df406f | 1946 | /* rx/tx queue initialisation ***********************************************/ |
64da80a2 | 1947 | static int rxq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1948 | { |
64da80a2 | 1949 | struct rx_queue *rxq = mp->rxq + index; |
8a578111 LB |
1950 | struct rx_desc *rx_desc; |
1951 | int size; | |
c9df406f LB |
1952 | int i; |
1953 | ||
64da80a2 LB |
1954 | rxq->index = index; |
1955 | ||
e7d2f4db | 1956 | rxq->rx_ring_size = mp->rx_ring_size; |
8a578111 LB |
1957 | |
1958 | rxq->rx_desc_count = 0; | |
1959 | rxq->rx_curr_desc = 0; | |
1960 | rxq->rx_used_desc = 0; | |
1961 | ||
1962 | size = rxq->rx_ring_size * sizeof(struct rx_desc); | |
1963 | ||
f7981c1c | 1964 | if (index == 0 && size <= mp->rx_desc_sram_size) { |
8a578111 LB |
1965 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, |
1966 | mp->rx_desc_sram_size); | |
1967 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; | |
1968 | } else { | |
eb0519b5 GP |
1969 | rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, |
1970 | size, &rxq->rx_desc_dma, | |
1971 | GFP_KERNEL); | |
f7ea3337 PJ |
1972 | } |
1973 | ||
8a578111 | 1974 | if (rxq->rx_desc_area == NULL) { |
7542db8b | 1975 | netdev_err(mp->dev, |
8a578111 LB |
1976 | "can't allocate rx ring (%d bytes)\n", size); |
1977 | goto out; | |
1978 | } | |
1979 | memset(rxq->rx_desc_area, 0, size); | |
1da177e4 | 1980 | |
8a578111 | 1981 | rxq->rx_desc_area_size = size; |
9fa8e980 | 1982 | rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb), |
b2adaca9 JP |
1983 | GFP_KERNEL); |
1984 | if (rxq->rx_skb == NULL) | |
8a578111 | 1985 | goto out_free; |
8a578111 | 1986 | |
64699336 | 1987 | rx_desc = rxq->rx_desc_area; |
8a578111 | 1988 | for (i = 0; i < rxq->rx_ring_size; i++) { |
9da78745 LB |
1989 | int nexti; |
1990 | ||
1991 | nexti = i + 1; | |
1992 | if (nexti == rxq->rx_ring_size) | |
1993 | nexti = 0; | |
1994 | ||
8a578111 LB |
1995 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + |
1996 | nexti * sizeof(struct rx_desc); | |
1997 | } | |
1998 | ||
8a578111 LB |
1999 | return 0; |
2000 | ||
2001 | ||
2002 | out_free: | |
f7981c1c | 2003 | if (index == 0 && size <= mp->rx_desc_sram_size) |
8a578111 LB |
2004 | iounmap(rxq->rx_desc_area); |
2005 | else | |
eb0519b5 | 2006 | dma_free_coherent(mp->dev->dev.parent, size, |
8a578111 LB |
2007 | rxq->rx_desc_area, |
2008 | rxq->rx_desc_dma); | |
2009 | ||
2010 | out: | |
2011 | return -ENOMEM; | |
c9df406f | 2012 | } |
c8aaea25 | 2013 | |
8a578111 | 2014 | static void rxq_deinit(struct rx_queue *rxq) |
c9df406f | 2015 | { |
8a578111 LB |
2016 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
2017 | int i; | |
2018 | ||
2019 | rxq_disable(rxq); | |
c8aaea25 | 2020 | |
8a578111 LB |
2021 | for (i = 0; i < rxq->rx_ring_size; i++) { |
2022 | if (rxq->rx_skb[i]) { | |
2023 | dev_kfree_skb(rxq->rx_skb[i]); | |
2024 | rxq->rx_desc_count--; | |
1da177e4 | 2025 | } |
c8aaea25 | 2026 | } |
1da177e4 | 2027 | |
8a578111 | 2028 | if (rxq->rx_desc_count) { |
7542db8b | 2029 | netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n", |
8a578111 LB |
2030 | rxq->rx_desc_count); |
2031 | } | |
2032 | ||
f7981c1c | 2033 | if (rxq->index == 0 && |
64da80a2 | 2034 | rxq->rx_desc_area_size <= mp->rx_desc_sram_size) |
8a578111 | 2035 | iounmap(rxq->rx_desc_area); |
c9df406f | 2036 | else |
eb0519b5 | 2037 | dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, |
8a578111 LB |
2038 | rxq->rx_desc_area, rxq->rx_desc_dma); |
2039 | ||
2040 | kfree(rxq->rx_skb); | |
c9df406f | 2041 | } |
1da177e4 | 2042 | |
3d6b35bc | 2043 | static int txq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 2044 | { |
3d6b35bc | 2045 | struct tx_queue *txq = mp->txq + index; |
13d64285 LB |
2046 | struct tx_desc *tx_desc; |
2047 | int size; | |
9e911414 | 2048 | int ret; |
c9df406f | 2049 | int i; |
1da177e4 | 2050 | |
3d6b35bc LB |
2051 | txq->index = index; |
2052 | ||
e7d2f4db | 2053 | txq->tx_ring_size = mp->tx_ring_size; |
13d64285 | 2054 | |
ee9e4956 EG |
2055 | /* A queue must always have room for at least one skb. |
2056 | * Therefore, stop the queue when the free entries reaches | |
2057 | * the maximum number of descriptors per skb. | |
2058 | */ | |
2059 | txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS; | |
2060 | txq->tx_wake_threshold = txq->tx_stop_threshold / 2; | |
2061 | ||
13d64285 LB |
2062 | txq->tx_desc_count = 0; |
2063 | txq->tx_curr_desc = 0; | |
2064 | txq->tx_used_desc = 0; | |
2065 | ||
2066 | size = txq->tx_ring_size * sizeof(struct tx_desc); | |
2067 | ||
f7981c1c | 2068 | if (index == 0 && size <= mp->tx_desc_sram_size) { |
13d64285 LB |
2069 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, |
2070 | mp->tx_desc_sram_size); | |
2071 | txq->tx_desc_dma = mp->tx_desc_sram_addr; | |
2072 | } else { | |
eb0519b5 GP |
2073 | txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, |
2074 | size, &txq->tx_desc_dma, | |
2075 | GFP_KERNEL); | |
13d64285 LB |
2076 | } |
2077 | ||
2078 | if (txq->tx_desc_area == NULL) { | |
7542db8b | 2079 | netdev_err(mp->dev, |
13d64285 | 2080 | "can't allocate tx ring (%d bytes)\n", size); |
99ab08e0 | 2081 | return -ENOMEM; |
c9df406f | 2082 | } |
13d64285 LB |
2083 | memset(txq->tx_desc_area, 0, size); |
2084 | ||
2085 | txq->tx_desc_area_size = size; | |
13d64285 | 2086 | |
64699336 | 2087 | tx_desc = txq->tx_desc_area; |
13d64285 | 2088 | for (i = 0; i < txq->tx_ring_size; i++) { |
6b368f68 | 2089 | struct tx_desc *txd = tx_desc + i; |
9da78745 LB |
2090 | int nexti; |
2091 | ||
2092 | nexti = i + 1; | |
2093 | if (nexti == txq->tx_ring_size) | |
2094 | nexti = 0; | |
6b368f68 LB |
2095 | |
2096 | txd->cmd_sts = 0; | |
2097 | txd->next_desc_ptr = txq->tx_desc_dma + | |
13d64285 LB |
2098 | nexti * sizeof(struct tx_desc); |
2099 | } | |
2100 | ||
9e911414 EG |
2101 | txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char), |
2102 | GFP_KERNEL); | |
2103 | if (!txq->tx_desc_mapping) { | |
2104 | ret = -ENOMEM; | |
2105 | goto err_free_desc_area; | |
2106 | } | |
2107 | ||
3ae8f4e0 EG |
2108 | /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ |
2109 | txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent, | |
2110 | txq->tx_ring_size * TSO_HEADER_SIZE, | |
2111 | &txq->tso_hdrs_dma, GFP_KERNEL); | |
2112 | if (txq->tso_hdrs == NULL) { | |
9e911414 EG |
2113 | ret = -ENOMEM; |
2114 | goto err_free_desc_mapping; | |
3ae8f4e0 | 2115 | } |
99ab08e0 | 2116 | skb_queue_head_init(&txq->tx_skb); |
c9df406f | 2117 | |
99ab08e0 | 2118 | return 0; |
9e911414 EG |
2119 | |
2120 | err_free_desc_mapping: | |
2121 | kfree(txq->tx_desc_mapping); | |
2122 | err_free_desc_area: | |
2123 | if (index == 0 && size <= mp->tx_desc_sram_size) | |
2124 | iounmap(txq->tx_desc_area); | |
2125 | else | |
2126 | dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, | |
2127 | txq->tx_desc_area, txq->tx_desc_dma); | |
2128 | return ret; | |
c8aaea25 | 2129 | } |
1da177e4 | 2130 | |
13d64285 | 2131 | static void txq_deinit(struct tx_queue *txq) |
c9df406f | 2132 | { |
13d64285 | 2133 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
fa3959f4 | 2134 | |
13d64285 | 2135 | txq_disable(txq); |
1fa38c58 | 2136 | txq_reclaim(txq, txq->tx_ring_size, 1); |
1da177e4 | 2137 | |
13d64285 | 2138 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
1da177e4 | 2139 | |
f7981c1c | 2140 | if (txq->index == 0 && |
3d6b35bc | 2141 | txq->tx_desc_area_size <= mp->tx_desc_sram_size) |
13d64285 | 2142 | iounmap(txq->tx_desc_area); |
c9df406f | 2143 | else |
eb0519b5 | 2144 | dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, |
13d64285 | 2145 | txq->tx_desc_area, txq->tx_desc_dma); |
9e911414 EG |
2146 | kfree(txq->tx_desc_mapping); |
2147 | ||
3ae8f4e0 EG |
2148 | if (txq->tso_hdrs) |
2149 | dma_free_coherent(mp->dev->dev.parent, | |
2150 | txq->tx_ring_size * TSO_HEADER_SIZE, | |
2151 | txq->tso_hdrs, txq->tso_hdrs_dma); | |
c9df406f | 2152 | } |
1da177e4 | 2153 | |
1da177e4 | 2154 | |
c9df406f | 2155 | /* netdev ops and related ***************************************************/ |
1fa38c58 LB |
2156 | static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) |
2157 | { | |
2158 | u32 int_cause; | |
2159 | u32 int_cause_ext; | |
2160 | ||
e0ca8410 | 2161 | int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask; |
1fa38c58 LB |
2162 | if (int_cause == 0) |
2163 | return 0; | |
2164 | ||
2165 | int_cause_ext = 0; | |
e0ca8410 SB |
2166 | if (int_cause & INT_EXT) { |
2167 | int_cause &= ~INT_EXT; | |
37a6084f | 2168 | int_cause_ext = rdlp(mp, INT_CAUSE_EXT); |
e0ca8410 | 2169 | } |
1fa38c58 | 2170 | |
1fa38c58 | 2171 | if (int_cause) { |
37a6084f | 2172 | wrlp(mp, INT_CAUSE, ~int_cause); |
1fa38c58 | 2173 | mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & |
37a6084f | 2174 | ~(rdlp(mp, TXQ_COMMAND) & 0xff); |
1fa38c58 LB |
2175 | mp->work_rx |= (int_cause & INT_RX) >> 2; |
2176 | } | |
2177 | ||
2178 | int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; | |
2179 | if (int_cause_ext) { | |
37a6084f | 2180 | wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); |
1fa38c58 LB |
2181 | if (int_cause_ext & INT_EXT_LINK_PHY) |
2182 | mp->work_link = 1; | |
2183 | mp->work_tx |= int_cause_ext & INT_EXT_TX; | |
2184 | } | |
2185 | ||
2186 | return 1; | |
2187 | } | |
2188 | ||
2189 | static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) | |
2190 | { | |
2191 | struct net_device *dev = (struct net_device *)dev_id; | |
2192 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
2193 | ||
2194 | if (unlikely(!mv643xx_eth_collect_events(mp))) | |
2195 | return IRQ_NONE; | |
2196 | ||
37a6084f | 2197 | wrlp(mp, INT_MASK, 0); |
1fa38c58 LB |
2198 | napi_schedule(&mp->napi); |
2199 | ||
2200 | return IRQ_HANDLED; | |
2201 | } | |
2202 | ||
2f7eb47a LB |
2203 | static void handle_link_event(struct mv643xx_eth_private *mp) |
2204 | { | |
2205 | struct net_device *dev = mp->dev; | |
2206 | u32 port_status; | |
2207 | int speed; | |
2208 | int duplex; | |
2209 | int fc; | |
2210 | ||
37a6084f | 2211 | port_status = rdlp(mp, PORT_STATUS); |
2f7eb47a LB |
2212 | if (!(port_status & LINK_UP)) { |
2213 | if (netif_carrier_ok(dev)) { | |
2214 | int i; | |
2215 | ||
7542db8b | 2216 | netdev_info(dev, "link down\n"); |
2f7eb47a LB |
2217 | |
2218 | netif_carrier_off(dev); | |
2f7eb47a | 2219 | |
f7981c1c | 2220 | for (i = 0; i < mp->txq_count; i++) { |
2f7eb47a LB |
2221 | struct tx_queue *txq = mp->txq + i; |
2222 | ||
1fa38c58 | 2223 | txq_reclaim(txq, txq->tx_ring_size, 1); |
f7981c1c | 2224 | txq_reset_hw_ptr(txq); |
2f7eb47a LB |
2225 | } |
2226 | } | |
2227 | return; | |
2228 | } | |
2229 | ||
2230 | switch (port_status & PORT_SPEED_MASK) { | |
2231 | case PORT_SPEED_10: | |
2232 | speed = 10; | |
2233 | break; | |
2234 | case PORT_SPEED_100: | |
2235 | speed = 100; | |
2236 | break; | |
2237 | case PORT_SPEED_1000: | |
2238 | speed = 1000; | |
2239 | break; | |
2240 | default: | |
2241 | speed = -1; | |
2242 | break; | |
2243 | } | |
2244 | duplex = (port_status & FULL_DUPLEX) ? 1 : 0; | |
2245 | fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; | |
2246 | ||
7542db8b JP |
2247 | netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n", |
2248 | speed, duplex ? "full" : "half", fc ? "en" : "dis"); | |
2f7eb47a | 2249 | |
4fdeca3f | 2250 | if (!netif_carrier_ok(dev)) |
2f7eb47a | 2251 | netif_carrier_on(dev); |
2f7eb47a LB |
2252 | } |
2253 | ||
1fa38c58 | 2254 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
c9df406f | 2255 | { |
1fa38c58 LB |
2256 | struct mv643xx_eth_private *mp; |
2257 | int work_done; | |
ce4e2e45 | 2258 | |
1fa38c58 | 2259 | mp = container_of(napi, struct mv643xx_eth_private, napi); |
fc32b0e2 | 2260 | |
1319ebad LB |
2261 | if (unlikely(mp->oom)) { |
2262 | mp->oom = 0; | |
2263 | del_timer(&mp->rx_oom); | |
2264 | } | |
1da177e4 | 2265 | |
1fa38c58 LB |
2266 | work_done = 0; |
2267 | while (work_done < budget) { | |
2268 | u8 queue_mask; | |
2269 | int queue; | |
2270 | int work_tbd; | |
2271 | ||
2272 | if (mp->work_link) { | |
2273 | mp->work_link = 0; | |
2274 | handle_link_event(mp); | |
26ef1f17 | 2275 | work_done++; |
1fa38c58 LB |
2276 | continue; |
2277 | } | |
1da177e4 | 2278 | |
1319ebad LB |
2279 | queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; |
2280 | if (likely(!mp->oom)) | |
2281 | queue_mask |= mp->work_rx_refill; | |
2282 | ||
1fa38c58 LB |
2283 | if (!queue_mask) { |
2284 | if (mv643xx_eth_collect_events(mp)) | |
2285 | continue; | |
2286 | break; | |
2287 | } | |
1da177e4 | 2288 | |
1fa38c58 LB |
2289 | queue = fls(queue_mask) - 1; |
2290 | queue_mask = 1 << queue; | |
2291 | ||
2292 | work_tbd = budget - work_done; | |
2293 | if (work_tbd > 16) | |
2294 | work_tbd = 16; | |
2295 | ||
2296 | if (mp->work_tx_end & queue_mask) { | |
2297 | txq_kick(mp->txq + queue); | |
2298 | } else if (mp->work_tx & queue_mask) { | |
2299 | work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); | |
2300 | txq_maybe_wake(mp->txq + queue); | |
2301 | } else if (mp->work_rx & queue_mask) { | |
2302 | work_done += rxq_process(mp->rxq + queue, work_tbd); | |
1319ebad | 2303 | } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { |
1fa38c58 LB |
2304 | work_done += rxq_refill(mp->rxq + queue, work_tbd); |
2305 | } else { | |
2306 | BUG(); | |
2307 | } | |
84dd619e | 2308 | } |
fc32b0e2 | 2309 | |
1fa38c58 | 2310 | if (work_done < budget) { |
1319ebad | 2311 | if (mp->oom) |
1fa38c58 LB |
2312 | mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); |
2313 | napi_complete(napi); | |
e0ca8410 | 2314 | wrlp(mp, INT_MASK, mp->int_mask); |
226bb6b7 | 2315 | } |
3d6b35bc | 2316 | |
1fa38c58 LB |
2317 | return work_done; |
2318 | } | |
8fa89bf5 | 2319 | |
1fa38c58 LB |
2320 | static inline void oom_timer_wrapper(unsigned long data) |
2321 | { | |
2322 | struct mv643xx_eth_private *mp = (void *)data; | |
1da177e4 | 2323 | |
1fa38c58 | 2324 | napi_schedule(&mp->napi); |
1da177e4 LT |
2325 | } |
2326 | ||
fc32b0e2 | 2327 | static void port_start(struct mv643xx_eth_private *mp) |
1da177e4 | 2328 | { |
d0412d96 | 2329 | u32 pscr; |
8a578111 | 2330 | int i; |
1da177e4 | 2331 | |
bedfe324 LB |
2332 | /* |
2333 | * Perform PHY reset, if there is a PHY. | |
2334 | */ | |
ed94493f | 2335 | if (mp->phy != NULL) { |
bedfe324 LB |
2336 | struct ethtool_cmd cmd; |
2337 | ||
2338 | mv643xx_eth_get_settings(mp->dev, &cmd); | |
7cd14636 | 2339 | phy_init_hw(mp->phy); |
bedfe324 | 2340 | mv643xx_eth_set_settings(mp->dev, &cmd); |
58911151 | 2341 | phy_start(mp->phy); |
bedfe324 | 2342 | } |
1da177e4 | 2343 | |
81600eea LB |
2344 | /* |
2345 | * Configure basic link parameters. | |
2346 | */ | |
37a6084f | 2347 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2348 | |
2349 | pscr |= SERIAL_PORT_ENABLE; | |
37a6084f | 2350 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2351 | |
2352 | pscr |= DO_NOT_FORCE_LINK_FAIL; | |
ed94493f | 2353 | if (mp->phy == NULL) |
81600eea | 2354 | pscr |= FORCE_LINK_PASS; |
37a6084f | 2355 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea | 2356 | |
13d64285 LB |
2357 | /* |
2358 | * Configure TX path and queues. | |
2359 | */ | |
89df5fdc | 2360 | tx_set_rate(mp, 1000000000, 16777216); |
f7981c1c | 2361 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc | 2362 | struct tx_queue *txq = mp->txq + i; |
13d64285 | 2363 | |
6b368f68 | 2364 | txq_reset_hw_ptr(txq); |
89df5fdc LB |
2365 | txq_set_rate(txq, 1000000000, 16777216); |
2366 | txq_set_fixed_prio_mode(txq); | |
13d64285 LB |
2367 | } |
2368 | ||
d9a073ea LB |
2369 | /* |
2370 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
170e7108 LB |
2371 | * frames to RX queue #0, and include the pseudo-header when |
2372 | * calculating receive checksums. | |
d9a073ea | 2373 | */ |
e138f96b | 2374 | mv643xx_eth_set_features(mp->dev, mp->dev->features); |
01999873 | 2375 | |
376489a2 LB |
2376 | /* |
2377 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
2378 | */ | |
37a6084f | 2379 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); |
01999873 | 2380 | |
5a893922 LB |
2381 | /* |
2382 | * Add configured unicast addresses to address filter table. | |
2383 | */ | |
2384 | mv643xx_eth_program_unicast_filter(mp->dev); | |
2385 | ||
8a578111 | 2386 | /* |
64da80a2 | 2387 | * Enable the receive queues. |
8a578111 | 2388 | */ |
f7981c1c | 2389 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 | 2390 | struct rx_queue *rxq = mp->rxq + i; |
8a578111 | 2391 | u32 addr; |
1da177e4 | 2392 | |
8a578111 LB |
2393 | addr = (u32)rxq->rx_desc_dma; |
2394 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); | |
37a6084f | 2395 | wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); |
1da177e4 | 2396 | |
8a578111 LB |
2397 | rxq_enable(rxq); |
2398 | } | |
1da177e4 LT |
2399 | } |
2400 | ||
2bcb4b0f LB |
2401 | static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) |
2402 | { | |
2403 | int skb_size; | |
2404 | ||
2405 | /* | |
2406 | * Reserve 2+14 bytes for an ethernet header (the hardware | |
2407 | * automatically prepends 2 bytes of dummy data to each | |
2408 | * received packet), 16 bytes for up to four VLAN tags, and | |
2409 | * 4 bytes for the trailing FCS -- 36 bytes total. | |
2410 | */ | |
2411 | skb_size = mp->dev->mtu + 36; | |
2412 | ||
2413 | /* | |
2414 | * Make sure that the skb size is a multiple of 8 bytes, as | |
2415 | * the lower three bits of the receive descriptor's buffer | |
2416 | * size field are ignored by the hardware. | |
2417 | */ | |
2418 | mp->skb_size = (skb_size + 7) & ~7; | |
7fd96ce4 LB |
2419 | |
2420 | /* | |
2421 | * If NET_SKB_PAD is smaller than a cache line, | |
2422 | * netdev_alloc_skb() will cause skb->data to be misaligned | |
2423 | * to a cache line boundary. If this is the case, include | |
2424 | * some extra space to allow re-aligning the data area. | |
2425 | */ | |
2426 | mp->skb_size += SKB_DMA_REALIGN; | |
2bcb4b0f LB |
2427 | } |
2428 | ||
c9df406f | 2429 | static int mv643xx_eth_open(struct net_device *dev) |
16e03018 | 2430 | { |
e5371493 | 2431 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2432 | int err; |
64da80a2 | 2433 | int i; |
16e03018 | 2434 | |
37a6084f LB |
2435 | wrlp(mp, INT_CAUSE, 0); |
2436 | wrlp(mp, INT_CAUSE_EXT, 0); | |
2437 | rdlp(mp, INT_CAUSE_EXT); | |
c9df406f | 2438 | |
fc32b0e2 | 2439 | err = request_irq(dev->irq, mv643xx_eth_irq, |
2a1867a7 | 2440 | IRQF_SHARED, dev->name, dev); |
c9df406f | 2441 | if (err) { |
7542db8b | 2442 | netdev_err(dev, "can't assign irq\n"); |
c9df406f | 2443 | return -EAGAIN; |
16e03018 DF |
2444 | } |
2445 | ||
2bcb4b0f LB |
2446 | mv643xx_eth_recalc_skb_size(mp); |
2447 | ||
2257e05c LB |
2448 | napi_enable(&mp->napi); |
2449 | ||
e0ca8410 SB |
2450 | mp->int_mask = INT_EXT; |
2451 | ||
f7981c1c | 2452 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 LB |
2453 | err = rxq_init(mp, i); |
2454 | if (err) { | |
2455 | while (--i >= 0) | |
f7981c1c | 2456 | rxq_deinit(mp->rxq + i); |
64da80a2 LB |
2457 | goto out; |
2458 | } | |
2459 | ||
1fa38c58 | 2460 | rxq_refill(mp->rxq + i, INT_MAX); |
e0ca8410 | 2461 | mp->int_mask |= INT_RX_0 << i; |
2257e05c LB |
2462 | } |
2463 | ||
1319ebad | 2464 | if (mp->oom) { |
2257e05c LB |
2465 | mp->rx_oom.expires = jiffies + (HZ / 10); |
2466 | add_timer(&mp->rx_oom); | |
64da80a2 | 2467 | } |
8a578111 | 2468 | |
f7981c1c | 2469 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc LB |
2470 | err = txq_init(mp, i); |
2471 | if (err) { | |
2472 | while (--i >= 0) | |
f7981c1c | 2473 | txq_deinit(mp->txq + i); |
3d6b35bc LB |
2474 | goto out_free; |
2475 | } | |
e0ca8410 | 2476 | mp->int_mask |= INT_TX_END_0 << i; |
3d6b35bc | 2477 | } |
16e03018 | 2478 | |
f564412c | 2479 | add_timer(&mp->mib_counters_timer); |
fc32b0e2 | 2480 | port_start(mp); |
16e03018 | 2481 | |
37a6084f | 2482 | wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); |
e0ca8410 | 2483 | wrlp(mp, INT_MASK, mp->int_mask); |
16e03018 | 2484 | |
c9df406f LB |
2485 | return 0; |
2486 | ||
13d64285 | 2487 | |
fc32b0e2 | 2488 | out_free: |
f7981c1c LB |
2489 | for (i = 0; i < mp->rxq_count; i++) |
2490 | rxq_deinit(mp->rxq + i); | |
fc32b0e2 | 2491 | out: |
c9df406f LB |
2492 | free_irq(dev->irq, dev); |
2493 | ||
2494 | return err; | |
16e03018 DF |
2495 | } |
2496 | ||
e5371493 | 2497 | static void port_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2498 | { |
fc32b0e2 | 2499 | unsigned int data; |
64da80a2 | 2500 | int i; |
1da177e4 | 2501 | |
f7981c1c LB |
2502 | for (i = 0; i < mp->rxq_count; i++) |
2503 | rxq_disable(mp->rxq + i); | |
2504 | for (i = 0; i < mp->txq_count; i++) | |
2505 | txq_disable(mp->txq + i); | |
ae9ae064 LB |
2506 | |
2507 | while (1) { | |
37a6084f | 2508 | u32 ps = rdlp(mp, PORT_STATUS); |
ae9ae064 LB |
2509 | |
2510 | if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) | |
2511 | break; | |
13d64285 | 2512 | udelay(10); |
ae9ae064 | 2513 | } |
1da177e4 | 2514 | |
c9df406f | 2515 | /* Reset the Enable bit in the Configuration Register */ |
37a6084f | 2516 | data = rdlp(mp, PORT_SERIAL_CONTROL); |
fc32b0e2 LB |
2517 | data &= ~(SERIAL_PORT_ENABLE | |
2518 | DO_NOT_FORCE_LINK_FAIL | | |
2519 | FORCE_LINK_PASS); | |
37a6084f | 2520 | wrlp(mp, PORT_SERIAL_CONTROL, data); |
1da177e4 LT |
2521 | } |
2522 | ||
c9df406f | 2523 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 | 2524 | { |
e5371493 | 2525 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
64da80a2 | 2526 | int i; |
1da177e4 | 2527 | |
fe65e704 | 2528 | wrlp(mp, INT_MASK_EXT, 0x00000000); |
37a6084f LB |
2529 | wrlp(mp, INT_MASK, 0x00000000); |
2530 | rdlp(mp, INT_MASK); | |
1da177e4 | 2531 | |
c9df406f | 2532 | napi_disable(&mp->napi); |
78fff83b | 2533 | |
2257e05c LB |
2534 | del_timer_sync(&mp->rx_oom); |
2535 | ||
c9df406f | 2536 | netif_carrier_off(dev); |
58911151 SH |
2537 | if (mp->phy) |
2538 | phy_stop(mp->phy); | |
fc32b0e2 LB |
2539 | free_irq(dev->irq, dev); |
2540 | ||
cc9754b3 | 2541 | port_reset(mp); |
8fd89211 | 2542 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 2543 | mib_counters_update(mp); |
57e8f26a | 2544 | del_timer_sync(&mp->mib_counters_timer); |
1da177e4 | 2545 | |
f7981c1c LB |
2546 | for (i = 0; i < mp->rxq_count; i++) |
2547 | rxq_deinit(mp->rxq + i); | |
2548 | for (i = 0; i < mp->txq_count; i++) | |
2549 | txq_deinit(mp->txq + i); | |
1da177e4 | 2550 | |
c9df406f | 2551 | return 0; |
1da177e4 LT |
2552 | } |
2553 | ||
fc32b0e2 | 2554 | static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2555 | { |
e5371493 | 2556 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
260055bb | 2557 | int ret; |
1da177e4 | 2558 | |
260055bb PS |
2559 | if (mp->phy == NULL) |
2560 | return -ENOTSUPP; | |
bedfe324 | 2561 | |
260055bb PS |
2562 | ret = phy_mii_ioctl(mp->phy, ifr, cmd); |
2563 | if (!ret) | |
0a9e413b | 2564 | mv643xx_eth_adjust_link(dev); |
260055bb | 2565 | return ret; |
1da177e4 LT |
2566 | } |
2567 | ||
c9df406f | 2568 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2569 | { |
89df5fdc LB |
2570 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
2571 | ||
fc32b0e2 | 2572 | if (new_mtu < 64 || new_mtu > 9500) |
c9df406f | 2573 | return -EINVAL; |
1da177e4 | 2574 | |
c9df406f | 2575 | dev->mtu = new_mtu; |
2bcb4b0f | 2576 | mv643xx_eth_recalc_skb_size(mp); |
89df5fdc LB |
2577 | tx_set_rate(mp, 1000000000, 16777216); |
2578 | ||
c9df406f LB |
2579 | if (!netif_running(dev)) |
2580 | return 0; | |
1da177e4 | 2581 | |
c9df406f LB |
2582 | /* |
2583 | * Stop and then re-open the interface. This will allocate RX | |
2584 | * skbs of the new MTU. | |
2585 | * There is a possible danger that the open will not succeed, | |
fc32b0e2 | 2586 | * due to memory being full. |
c9df406f LB |
2587 | */ |
2588 | mv643xx_eth_stop(dev); | |
2589 | if (mv643xx_eth_open(dev)) { | |
7542db8b JP |
2590 | netdev_err(dev, |
2591 | "fatal error on re-opening device after MTU change\n"); | |
c9df406f LB |
2592 | } |
2593 | ||
2594 | return 0; | |
1da177e4 LT |
2595 | } |
2596 | ||
fc32b0e2 | 2597 | static void tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2598 | { |
fc32b0e2 | 2599 | struct mv643xx_eth_private *mp; |
1da177e4 | 2600 | |
fc32b0e2 LB |
2601 | mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); |
2602 | if (netif_running(mp->dev)) { | |
e5ef1de1 | 2603 | netif_tx_stop_all_queues(mp->dev); |
fc32b0e2 LB |
2604 | port_reset(mp); |
2605 | port_start(mp); | |
e5ef1de1 | 2606 | netif_tx_wake_all_queues(mp->dev); |
fc32b0e2 | 2607 | } |
c9df406f LB |
2608 | } |
2609 | ||
c9df406f | 2610 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2611 | { |
e5371493 | 2612 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2613 | |
7542db8b | 2614 | netdev_info(dev, "tx timeout\n"); |
d0412d96 | 2615 | |
c9df406f | 2616 | schedule_work(&mp->tx_timeout_task); |
1da177e4 LT |
2617 | } |
2618 | ||
c9df406f | 2619 | #ifdef CONFIG_NET_POLL_CONTROLLER |
fc32b0e2 | 2620 | static void mv643xx_eth_netpoll(struct net_device *dev) |
9f8dd319 | 2621 | { |
fc32b0e2 | 2622 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2623 | |
37a6084f LB |
2624 | wrlp(mp, INT_MASK, 0x00000000); |
2625 | rdlp(mp, INT_MASK); | |
c9df406f | 2626 | |
fc32b0e2 | 2627 | mv643xx_eth_irq(dev->irq, dev); |
c9df406f | 2628 | |
e0ca8410 | 2629 | wrlp(mp, INT_MASK, mp->int_mask); |
9f8dd319 | 2630 | } |
c9df406f | 2631 | #endif |
9f8dd319 | 2632 | |
9f8dd319 | 2633 | |
c9df406f | 2634 | /* platform glue ************************************************************/ |
e5371493 LB |
2635 | static void |
2636 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, | |
63a9332b | 2637 | const struct mbus_dram_target_info *dram) |
c9df406f | 2638 | { |
cc9754b3 | 2639 | void __iomem *base = msp->base; |
c9df406f LB |
2640 | u32 win_enable; |
2641 | u32 win_protect; | |
2642 | int i; | |
9f8dd319 | 2643 | |
c9df406f LB |
2644 | for (i = 0; i < 6; i++) { |
2645 | writel(0, base + WINDOW_BASE(i)); | |
2646 | writel(0, base + WINDOW_SIZE(i)); | |
2647 | if (i < 4) | |
2648 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2649 | } |
2650 | ||
c9df406f LB |
2651 | win_enable = 0x3f; |
2652 | win_protect = 0; | |
2653 | ||
2654 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 2655 | const struct mbus_dram_window *cs = dram->cs + i; |
c9df406f LB |
2656 | |
2657 | writel((cs->base & 0xffff0000) | | |
2658 | (cs->mbus_attr << 8) | | |
2659 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2660 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2661 | ||
2662 | win_enable &= ~(1 << i); | |
2663 | win_protect |= 3 << (2 * i); | |
2664 | } | |
2665 | ||
2666 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2667 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2668 | } |
2669 | ||
773fc3ee LB |
2670 | static void infer_hw_params(struct mv643xx_eth_shared_private *msp) |
2671 | { | |
2672 | /* | |
2673 | * Check whether we have a 14-bit coal limit field in bits | |
2674 | * [21:8], or a 16-bit coal limit in bits [25,21:7] of the | |
2675 | * SDMA config register. | |
2676 | */ | |
37a6084f LB |
2677 | writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); |
2678 | if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) | |
773fc3ee LB |
2679 | msp->extended_rx_coal_limit = 1; |
2680 | else | |
2681 | msp->extended_rx_coal_limit = 0; | |
1e881592 LB |
2682 | |
2683 | /* | |
457b1d5a LB |
2684 | * Check whether the MAC supports TX rate control, and if |
2685 | * yes, whether its associated registers are in the old or | |
2686 | * the new place. | |
1e881592 | 2687 | */ |
37a6084f LB |
2688 | writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); |
2689 | if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { | |
457b1d5a LB |
2690 | msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; |
2691 | } else { | |
37a6084f LB |
2692 | writel(7, msp->base + 0x0400 + TX_BW_RATE); |
2693 | if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) | |
457b1d5a LB |
2694 | msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; |
2695 | else | |
2696 | msp->tx_bw_control = TX_BW_CONTROL_ABSENT; | |
2697 | } | |
773fc3ee LB |
2698 | } |
2699 | ||
76723bca SH |
2700 | #if defined(CONFIG_OF) |
2701 | static const struct of_device_id mv643xx_eth_shared_ids[] = { | |
2702 | { .compatible = "marvell,orion-eth", }, | |
2703 | { .compatible = "marvell,kirkwood-eth", }, | |
2704 | { } | |
2705 | }; | |
2706 | MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids); | |
2707 | #endif | |
2708 | ||
2709 | #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60) | |
2710 | #define mv643xx_eth_property(_np, _name, _v) \ | |
2711 | do { \ | |
2712 | u32 tmp; \ | |
2713 | if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \ | |
2714 | _v = tmp; \ | |
2715 | } while (0) | |
2716 | ||
2717 | static struct platform_device *port_platdev[3]; | |
2718 | ||
2719 | static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev, | |
2720 | struct device_node *pnp) | |
2721 | { | |
2722 | struct platform_device *ppdev; | |
2723 | struct mv643xx_eth_platform_data ppd; | |
2724 | struct resource res; | |
2725 | const char *mac_addr; | |
2726 | int ret; | |
785bf6f7 | 2727 | int dev_num = 0; |
76723bca SH |
2728 | |
2729 | memset(&ppd, 0, sizeof(ppd)); | |
2730 | ppd.shared = pdev; | |
2731 | ||
2732 | memset(&res, 0, sizeof(res)); | |
2733 | if (!of_irq_to_resource(pnp, 0, &res)) { | |
2734 | dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name); | |
2735 | return -EINVAL; | |
2736 | } | |
2737 | ||
2738 | if (of_property_read_u32(pnp, "reg", &ppd.port_number)) { | |
2739 | dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name); | |
2740 | return -EINVAL; | |
2741 | } | |
2742 | ||
2743 | if (ppd.port_number >= 3) { | |
2744 | dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name); | |
2745 | return -EINVAL; | |
2746 | } | |
2747 | ||
785bf6f7 JG |
2748 | while (dev_num < 3 && port_platdev[dev_num]) |
2749 | dev_num++; | |
2750 | ||
2751 | if (dev_num == 3) { | |
2752 | dev_err(&pdev->dev, "too many ports registered\n"); | |
2753 | return -EINVAL; | |
2754 | } | |
2755 | ||
76723bca SH |
2756 | mac_addr = of_get_mac_address(pnp); |
2757 | if (mac_addr) | |
d458cdf7 | 2758 | memcpy(ppd.mac_addr, mac_addr, ETH_ALEN); |
76723bca SH |
2759 | |
2760 | mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size); | |
2761 | mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr); | |
2762 | mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size); | |
2763 | mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size); | |
2764 | mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr); | |
2765 | mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size); | |
2766 | ||
2767 | ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0); | |
2768 | if (!ppd.phy_node) { | |
2769 | ppd.phy_addr = MV643XX_ETH_PHY_NONE; | |
2770 | of_property_read_u32(pnp, "speed", &ppd.speed); | |
2771 | of_property_read_u32(pnp, "duplex", &ppd.duplex); | |
2772 | } | |
2773 | ||
785bf6f7 | 2774 | ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num); |
76723bca SH |
2775 | if (!ppdev) |
2776 | return -ENOMEM; | |
2777 | ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
b5d82db8 | 2778 | ppdev->dev.of_node = pnp; |
76723bca SH |
2779 | |
2780 | ret = platform_device_add_resources(ppdev, &res, 1); | |
2781 | if (ret) | |
2782 | goto port_err; | |
2783 | ||
2784 | ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); | |
2785 | if (ret) | |
2786 | goto port_err; | |
2787 | ||
2788 | ret = platform_device_add(ppdev); | |
2789 | if (ret) | |
2790 | goto port_err; | |
2791 | ||
785bf6f7 | 2792 | port_platdev[dev_num] = ppdev; |
76723bca SH |
2793 | |
2794 | return 0; | |
2795 | ||
2796 | port_err: | |
2797 | platform_device_put(ppdev); | |
2798 | return ret; | |
2799 | } | |
2800 | ||
2801 | static int mv643xx_eth_shared_of_probe(struct platform_device *pdev) | |
2802 | { | |
2803 | struct mv643xx_eth_shared_platform_data *pd; | |
2804 | struct device_node *pnp, *np = pdev->dev.of_node; | |
2805 | int ret; | |
2806 | ||
2807 | /* bail out if not registered from DT */ | |
2808 | if (!np) | |
2809 | return 0; | |
2810 | ||
2811 | pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); | |
2812 | if (!pd) | |
2813 | return -ENOMEM; | |
2814 | pdev->dev.platform_data = pd; | |
2815 | ||
2816 | mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit); | |
2817 | ||
2818 | for_each_available_child_of_node(np, pnp) { | |
2819 | ret = mv643xx_eth_shared_of_add_port(pdev, pnp); | |
26b7974d JL |
2820 | if (ret) { |
2821 | of_node_put(pnp); | |
76723bca | 2822 | return ret; |
26b7974d | 2823 | } |
76723bca SH |
2824 | } |
2825 | return 0; | |
2826 | } | |
2827 | ||
2828 | static void mv643xx_eth_shared_of_remove(void) | |
2829 | { | |
2830 | int n; | |
2831 | ||
2832 | for (n = 0; n < 3; n++) { | |
2833 | platform_device_del(port_platdev[n]); | |
2834 | port_platdev[n] = NULL; | |
2835 | } | |
2836 | } | |
2837 | #else | |
ff20877a | 2838 | static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev) |
76723bca | 2839 | { |
ff20877a | 2840 | return 0; |
76723bca SH |
2841 | } |
2842 | ||
ff20877a AB |
2843 | static inline void mv643xx_eth_shared_of_remove(void) |
2844 | { | |
2845 | } | |
76723bca SH |
2846 | #endif |
2847 | ||
c9df406f | 2848 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2849 | { |
10a9948d | 2850 | static int mv643xx_eth_version_printed; |
76723bca | 2851 | struct mv643xx_eth_shared_platform_data *pd; |
e5371493 | 2852 | struct mv643xx_eth_shared_private *msp; |
63a9332b | 2853 | const struct mbus_dram_target_info *dram; |
c9df406f | 2854 | struct resource *res; |
76723bca | 2855 | int ret; |
9f8dd319 | 2856 | |
e5371493 | 2857 | if (!mv643xx_eth_version_printed++) |
7542db8b JP |
2858 | pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n", |
2859 | mv643xx_eth_driver_version); | |
9f8dd319 | 2860 | |
c9df406f LB |
2861 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2862 | if (res == NULL) | |
727f957a | 2863 | return -EINVAL; |
9f8dd319 | 2864 | |
727f957a | 2865 | msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL); |
c9df406f | 2866 | if (msp == NULL) |
727f957a | 2867 | return -ENOMEM; |
76723bca | 2868 | platform_set_drvdata(pdev, msp); |
c9df406f | 2869 | |
65a6f969 | 2870 | msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
cc9754b3 | 2871 | if (msp->base == NULL) |
727f957a | 2872 | return -ENOMEM; |
c9df406f | 2873 | |
20922486 SH |
2874 | msp->clk = devm_clk_get(&pdev->dev, NULL); |
2875 | if (!IS_ERR(msp->clk)) | |
2876 | clk_prepare_enable(msp->clk); | |
2877 | ||
c9df406f LB |
2878 | /* |
2879 | * (Re-)program MBUS remapping windows if we are asked to. | |
2880 | */ | |
63a9332b AL |
2881 | dram = mv_mbus_dram_info(); |
2882 | if (dram) | |
2883 | mv643xx_eth_conf_mbus_windows(msp, dram); | |
c9df406f | 2884 | |
76723bca SH |
2885 | ret = mv643xx_eth_shared_of_probe(pdev); |
2886 | if (ret) | |
2887 | return ret; | |
bbfa6d0a | 2888 | pd = dev_get_platdata(&pdev->dev); |
76723bca | 2889 | |
50a749c1 DC |
2890 | msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ? |
2891 | pd->tx_csum_limit : 9 * 1024; | |
773fc3ee | 2892 | infer_hw_params(msp); |
fc32b0e2 | 2893 | |
c9df406f | 2894 | return 0; |
c9df406f LB |
2895 | } |
2896 | ||
2897 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2898 | { | |
e5371493 | 2899 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
c9df406f | 2900 | |
76723bca | 2901 | mv643xx_eth_shared_of_remove(); |
20922486 SH |
2902 | if (!IS_ERR(msp->clk)) |
2903 | clk_disable_unprepare(msp->clk); | |
c9df406f | 2904 | return 0; |
9f8dd319 DF |
2905 | } |
2906 | ||
c9df406f | 2907 | static struct platform_driver mv643xx_eth_shared_driver = { |
fc32b0e2 LB |
2908 | .probe = mv643xx_eth_shared_probe, |
2909 | .remove = mv643xx_eth_shared_remove, | |
c9df406f | 2910 | .driver = { |
fc32b0e2 | 2911 | .name = MV643XX_ETH_SHARED_NAME, |
76723bca | 2912 | .of_match_table = of_match_ptr(mv643xx_eth_shared_ids), |
c9df406f LB |
2913 | }, |
2914 | }; | |
2915 | ||
e5371493 | 2916 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
1da177e4 | 2917 | { |
c9df406f | 2918 | int addr_shift = 5 * mp->port_num; |
fc32b0e2 | 2919 | u32 data; |
1da177e4 | 2920 | |
fc32b0e2 LB |
2921 | data = rdl(mp, PHY_ADDR); |
2922 | data &= ~(0x1f << addr_shift); | |
2923 | data |= (phy_addr & 0x1f) << addr_shift; | |
2924 | wrl(mp, PHY_ADDR, data); | |
1da177e4 LT |
2925 | } |
2926 | ||
e5371493 | 2927 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
1da177e4 | 2928 | { |
fc32b0e2 LB |
2929 | unsigned int data; |
2930 | ||
2931 | data = rdl(mp, PHY_ADDR); | |
2932 | ||
2933 | return (data >> (5 * mp->port_num)) & 0x1f; | |
2934 | } | |
2935 | ||
2936 | static void set_params(struct mv643xx_eth_private *mp, | |
2937 | struct mv643xx_eth_platform_data *pd) | |
2938 | { | |
2939 | struct net_device *dev = mp->dev; | |
ee9e4956 | 2940 | unsigned int tx_ring_size; |
fc32b0e2 LB |
2941 | |
2942 | if (is_valid_ether_addr(pd->mac_addr)) | |
d458cdf7 | 2943 | memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); |
fc32b0e2 LB |
2944 | else |
2945 | uc_addr_get(mp, dev->dev_addr); | |
2946 | ||
e7d2f4db | 2947 | mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
fc32b0e2 | 2948 | if (pd->rx_queue_size) |
e7d2f4db | 2949 | mp->rx_ring_size = pd->rx_queue_size; |
fc32b0e2 LB |
2950 | mp->rx_desc_sram_addr = pd->rx_sram_addr; |
2951 | mp->rx_desc_sram_size = pd->rx_sram_size; | |
1da177e4 | 2952 | |
f7981c1c | 2953 | mp->rxq_count = pd->rx_queue_count ? : 1; |
64da80a2 | 2954 | |
ee9e4956 | 2955 | tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
fc32b0e2 | 2956 | if (pd->tx_queue_size) |
ee9e4956 EG |
2957 | tx_ring_size = pd->tx_queue_size; |
2958 | ||
2959 | mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size, | |
2960 | MV643XX_MAX_SKB_DESCS * 2, 4096); | |
2961 | if (mp->tx_ring_size != tx_ring_size) | |
2962 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", | |
2963 | mp->tx_ring_size, tx_ring_size); | |
2964 | ||
fc32b0e2 LB |
2965 | mp->tx_desc_sram_addr = pd->tx_sram_addr; |
2966 | mp->tx_desc_sram_size = pd->tx_sram_size; | |
3d6b35bc | 2967 | |
f7981c1c | 2968 | mp->txq_count = pd->tx_queue_count ? : 1; |
1da177e4 LT |
2969 | } |
2970 | ||
ed94493f LB |
2971 | static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, |
2972 | int phy_addr) | |
1da177e4 | 2973 | { |
ed94493f LB |
2974 | struct phy_device *phydev; |
2975 | int start; | |
2976 | int num; | |
2977 | int i; | |
c3a07134 | 2978 | char phy_id[MII_BUS_ID_SIZE + 3]; |
45c5d3bc | 2979 | |
ed94493f LB |
2980 | if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { |
2981 | start = phy_addr_get(mp) & 0x1f; | |
2982 | num = 32; | |
2983 | } else { | |
2984 | start = phy_addr & 0x1f; | |
2985 | num = 1; | |
2986 | } | |
45c5d3bc | 2987 | |
c3a07134 | 2988 | /* Attempt to connect to the PHY using orion-mdio */ |
976c90b9 | 2989 | phydev = ERR_PTR(-ENODEV); |
ed94493f LB |
2990 | for (i = 0; i < num; i++) { |
2991 | int addr = (start + i) & 0x1f; | |
fc32b0e2 | 2992 | |
c3a07134 FF |
2993 | snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, |
2994 | "orion-mdio-mii", addr); | |
1da177e4 | 2995 | |
c3a07134 FF |
2996 | phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link, |
2997 | PHY_INTERFACE_MODE_GMII); | |
2998 | if (!IS_ERR(phydev)) { | |
2999 | phy_addr_set(mp, addr); | |
3000 | break; | |
ed94493f LB |
3001 | } |
3002 | } | |
1da177e4 | 3003 | |
ed94493f | 3004 | return phydev; |
1da177e4 LT |
3005 | } |
3006 | ||
ed94493f | 3007 | static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) |
c28a4f89 | 3008 | { |
ed94493f | 3009 | struct phy_device *phy = mp->phy; |
c28a4f89 | 3010 | |
ed94493f LB |
3011 | if (speed == 0) { |
3012 | phy->autoneg = AUTONEG_ENABLE; | |
3013 | phy->speed = 0; | |
3014 | phy->duplex = 0; | |
3015 | phy->advertising = phy->supported | ADVERTISED_Autoneg; | |
c9df406f | 3016 | } else { |
ed94493f LB |
3017 | phy->autoneg = AUTONEG_DISABLE; |
3018 | phy->advertising = 0; | |
3019 | phy->speed = speed; | |
3020 | phy->duplex = duplex; | |
c9df406f | 3021 | } |
ed94493f | 3022 | phy_start_aneg(phy); |
c28a4f89 JC |
3023 | } |
3024 | ||
81600eea LB |
3025 | static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) |
3026 | { | |
3027 | u32 pscr; | |
3028 | ||
37a6084f | 3029 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
3030 | if (pscr & SERIAL_PORT_ENABLE) { |
3031 | pscr &= ~SERIAL_PORT_ENABLE; | |
37a6084f | 3032 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
3033 | } |
3034 | ||
3035 | pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; | |
ed94493f | 3036 | if (mp->phy == NULL) { |
81600eea LB |
3037 | pscr |= DISABLE_AUTO_NEG_SPEED_GMII; |
3038 | if (speed == SPEED_1000) | |
3039 | pscr |= SET_GMII_SPEED_TO_1000; | |
3040 | else if (speed == SPEED_100) | |
3041 | pscr |= SET_MII_SPEED_TO_100; | |
3042 | ||
3043 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; | |
3044 | ||
3045 | pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; | |
3046 | if (duplex == DUPLEX_FULL) | |
3047 | pscr |= SET_FULL_DUPLEX_MODE; | |
3048 | } | |
3049 | ||
37a6084f | 3050 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
3051 | } |
3052 | ||
ea8a8642 LB |
3053 | static const struct net_device_ops mv643xx_eth_netdev_ops = { |
3054 | .ndo_open = mv643xx_eth_open, | |
3055 | .ndo_stop = mv643xx_eth_stop, | |
3056 | .ndo_start_xmit = mv643xx_eth_xmit, | |
3057 | .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, | |
3058 | .ndo_set_mac_address = mv643xx_eth_set_mac_address, | |
1d4bd947 | 3059 | .ndo_validate_addr = eth_validate_addr, |
ea8a8642 LB |
3060 | .ndo_do_ioctl = mv643xx_eth_ioctl, |
3061 | .ndo_change_mtu = mv643xx_eth_change_mtu, | |
aad59c43 | 3062 | .ndo_set_features = mv643xx_eth_set_features, |
ea8a8642 LB |
3063 | .ndo_tx_timeout = mv643xx_eth_tx_timeout, |
3064 | .ndo_get_stats = mv643xx_eth_get_stats, | |
3065 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3066 | .ndo_poll_controller = mv643xx_eth_netpoll, | |
3067 | #endif | |
3068 | }; | |
3069 | ||
c9df406f | 3070 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 3071 | { |
c9df406f | 3072 | struct mv643xx_eth_platform_data *pd; |
e5371493 | 3073 | struct mv643xx_eth_private *mp; |
c9df406f | 3074 | struct net_device *dev; |
c9df406f | 3075 | struct resource *res; |
fc32b0e2 | 3076 | int err; |
1da177e4 | 3077 | |
bbfa6d0a | 3078 | pd = dev_get_platdata(&pdev->dev); |
c9df406f | 3079 | if (pd == NULL) { |
7542db8b | 3080 | dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n"); |
c9df406f LB |
3081 | return -ENODEV; |
3082 | } | |
1da177e4 | 3083 | |
c9df406f | 3084 | if (pd->shared == NULL) { |
7542db8b | 3085 | dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n"); |
c9df406f LB |
3086 | return -ENODEV; |
3087 | } | |
8f518703 | 3088 | |
e5ef1de1 | 3089 | dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); |
c9df406f LB |
3090 | if (!dev) |
3091 | return -ENOMEM; | |
1da177e4 | 3092 | |
c9df406f | 3093 | mp = netdev_priv(dev); |
fc32b0e2 LB |
3094 | platform_set_drvdata(pdev, mp); |
3095 | ||
3096 | mp->shared = platform_get_drvdata(pd->shared); | |
37a6084f | 3097 | mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); |
fc32b0e2 LB |
3098 | mp->port_num = pd->port_number; |
3099 | ||
c9df406f | 3100 | mp->dev = dev; |
78fff83b | 3101 | |
cb85215f SH |
3102 | /* Kirkwood resets some registers on gated clocks. Especially |
3103 | * CLK125_BYPASS_EN must be cleared but is not available on | |
3104 | * all other SoCs/System Controllers using this driver. | |
3105 | */ | |
3106 | if (of_device_is_compatible(pdev->dev.of_node, | |
3107 | "marvell,kirkwood-eth-port")) | |
3108 | wrlp(mp, PORT_SERIAL_CONTROL1, | |
3109 | rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN); | |
3110 | ||
452503eb | 3111 | /* |
9a43a026 AL |
3112 | * Start with a default rate, and if there is a clock, allow |
3113 | * it to override the default. | |
452503eb | 3114 | */ |
9a43a026 | 3115 | mp->t_clk = 133000000; |
20922486 | 3116 | mp->clk = devm_clk_get(&pdev->dev, NULL); |
452503eb AL |
3117 | if (!IS_ERR(mp->clk)) { |
3118 | clk_prepare_enable(mp->clk); | |
3119 | mp->t_clk = clk_get_rate(mp->clk); | |
76723bca SH |
3120 | } else if (!IS_ERR(mp->shared->clk)) { |
3121 | mp->t_clk = clk_get_rate(mp->shared->clk); | |
452503eb | 3122 | } |
20922486 | 3123 | |
fc32b0e2 | 3124 | set_params(mp, pd); |
206d6b32 BH |
3125 | netif_set_real_num_tx_queues(dev, mp->txq_count); |
3126 | netif_set_real_num_rx_queues(dev, mp->rxq_count); | |
fc32b0e2 | 3127 | |
cc9d4598 SH |
3128 | err = 0; |
3129 | if (pd->phy_node) { | |
3130 | mp->phy = of_phy_connect(mp->dev, pd->phy_node, | |
3131 | mv643xx_eth_adjust_link, 0, | |
3132 | PHY_INTERFACE_MODE_GMII); | |
3133 | if (!mp->phy) | |
3134 | err = -ENODEV; | |
6115c11f | 3135 | else |
e5a03bfd | 3136 | phy_addr_set(mp, mp->phy->mdio.addr); |
cc9d4598 | 3137 | } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) { |
ed94493f | 3138 | mp->phy = phy_scan(mp, pd->phy_addr); |
bedfe324 | 3139 | |
cc9d4598 | 3140 | if (IS_ERR(mp->phy)) |
976c90b9 | 3141 | err = PTR_ERR(mp->phy); |
cc9d4598 SH |
3142 | else |
3143 | phy_init(mp, pd->speed, pd->duplex); | |
976c90b9 | 3144 | } |
cc9d4598 SH |
3145 | if (err == -ENODEV) { |
3146 | err = -EPROBE_DEFER; | |
3147 | goto out; | |
3148 | } | |
3149 | if (err) | |
3150 | goto out; | |
6bdf576e | 3151 | |
7ad24ea4 | 3152 | dev->ethtool_ops = &mv643xx_eth_ethtool_ops; |
ed94493f | 3153 | |
81600eea | 3154 | init_pscr(mp, pd->speed, pd->duplex); |
fc32b0e2 | 3155 | |
4ff3495a LB |
3156 | |
3157 | mib_counters_clear(mp); | |
3158 | ||
12d5e6fd VT |
3159 | setup_timer(&mp->mib_counters_timer, mib_counters_timer_wrapper, |
3160 | (unsigned long)mp); | |
4ff3495a | 3161 | mp->mib_counters_timer.expires = jiffies + 30 * HZ; |
4ff3495a LB |
3162 | |
3163 | spin_lock_init(&mp->mib_counters_lock); | |
3164 | ||
3165 | INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); | |
3166 | ||
a3659aa0 | 3167 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT); |
2257e05c | 3168 | |
12d5e6fd | 3169 | setup_timer(&mp->rx_oom, oom_timer_wrapper, (unsigned long)mp); |
2257e05c | 3170 | |
fc32b0e2 | 3171 | |
c9df406f LB |
3172 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
3173 | BUG_ON(!res); | |
3174 | dev->irq = res->start; | |
1da177e4 | 3175 | |
ea8a8642 LB |
3176 | dev->netdev_ops = &mv643xx_eth_netdev_ops; |
3177 | ||
c9df406f LB |
3178 | dev->watchdog_timeo = 2 * HZ; |
3179 | dev->base_addr = 0; | |
1da177e4 | 3180 | |
3ae8f4e0 | 3181 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; |
4d48d589 EG |
3182 | dev->vlan_features = dev->features; |
3183 | ||
3184 | dev->features |= NETIF_F_RXCSUM; | |
3185 | dev->hw_features = dev->features; | |
1da177e4 | 3186 | |
01789349 | 3187 | dev->priv_flags |= IFF_UNICAST_FLT; |
ee9e4956 | 3188 | dev->gso_max_segs = MV643XX_MAX_TSO_SEGS; |
01789349 | 3189 | |
fc32b0e2 | 3190 | SET_NETDEV_DEV(dev, &pdev->dev); |
8f518703 | 3191 | |
c9df406f | 3192 | if (mp->shared->win_protect) |
fc32b0e2 | 3193 | wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); |
1da177e4 | 3194 | |
a5fe3616 LB |
3195 | netif_carrier_off(dev); |
3196 | ||
b5e86db4 LB |
3197 | wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); |
3198 | ||
4fb0a54a | 3199 | set_rx_coal(mp, 250); |
a5fe3616 LB |
3200 | set_tx_coal(mp, 0); |
3201 | ||
c9df406f LB |
3202 | err = register_netdev(dev); |
3203 | if (err) | |
3204 | goto out; | |
1da177e4 | 3205 | |
7542db8b JP |
3206 | netdev_notice(dev, "port %d with MAC address %pM\n", |
3207 | mp->port_num, dev->dev_addr); | |
1da177e4 | 3208 | |
13d64285 | 3209 | if (mp->tx_desc_sram_size > 0) |
7542db8b | 3210 | netdev_notice(dev, "configured with sram\n"); |
1da177e4 | 3211 | |
c9df406f | 3212 | return 0; |
1da177e4 | 3213 | |
c9df406f | 3214 | out: |
20922486 | 3215 | if (!IS_ERR(mp->clk)) |
baffab28 | 3216 | clk_disable_unprepare(mp->clk); |
c9df406f | 3217 | free_netdev(dev); |
1da177e4 | 3218 | |
c9df406f | 3219 | return err; |
1da177e4 LT |
3220 | } |
3221 | ||
c9df406f | 3222 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 3223 | { |
fc32b0e2 | 3224 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
1da177e4 | 3225 | |
fc32b0e2 | 3226 | unregister_netdev(mp->dev); |
ed94493f | 3227 | if (mp->phy != NULL) |
cec753f5 | 3228 | phy_disconnect(mp->phy); |
23f333a2 | 3229 | cancel_work_sync(&mp->tx_timeout_task); |
452503eb | 3230 | |
20922486 | 3231 | if (!IS_ERR(mp->clk)) |
452503eb | 3232 | clk_disable_unprepare(mp->clk); |
9a43a026 | 3233 | |
fc32b0e2 | 3234 | free_netdev(mp->dev); |
c9df406f | 3235 | |
c9df406f | 3236 | return 0; |
1da177e4 LT |
3237 | } |
3238 | ||
c9df406f | 3239 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 3240 | { |
fc32b0e2 | 3241 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
d0412d96 | 3242 | |
c9df406f | 3243 | /* Mask all interrupts on ethernet port */ |
37a6084f LB |
3244 | wrlp(mp, INT_MASK, 0); |
3245 | rdlp(mp, INT_MASK); | |
c9df406f | 3246 | |
fc32b0e2 LB |
3247 | if (netif_running(mp->dev)) |
3248 | port_reset(mp); | |
d0412d96 JC |
3249 | } |
3250 | ||
c9df406f | 3251 | static struct platform_driver mv643xx_eth_driver = { |
fc32b0e2 LB |
3252 | .probe = mv643xx_eth_probe, |
3253 | .remove = mv643xx_eth_remove, | |
3254 | .shutdown = mv643xx_eth_shutdown, | |
c9df406f | 3255 | .driver = { |
fc32b0e2 | 3256 | .name = MV643XX_ETH_NAME, |
c9df406f LB |
3257 | }, |
3258 | }; | |
3259 | ||
3b5dde70 TR |
3260 | static struct platform_driver * const drivers[] = { |
3261 | &mv643xx_eth_shared_driver, | |
3262 | &mv643xx_eth_driver, | |
3263 | }; | |
3264 | ||
e5371493 | 3265 | static int __init mv643xx_eth_init_module(void) |
d0412d96 | 3266 | { |
3b5dde70 | 3267 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
d0412d96 | 3268 | } |
fc32b0e2 | 3269 | module_init(mv643xx_eth_init_module); |
d0412d96 | 3270 | |
e5371493 | 3271 | static void __exit mv643xx_eth_cleanup_module(void) |
d0412d96 | 3272 | { |
3b5dde70 | 3273 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
d0412d96 | 3274 | } |
e5371493 | 3275 | module_exit(mv643xx_eth_cleanup_module); |
1da177e4 | 3276 | |
45675bc6 LB |
3277 | MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " |
3278 | "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); | |
c9df406f | 3279 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
fc32b0e2 | 3280 | MODULE_LICENSE("GPL"); |
c9df406f | 3281 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |
fc32b0e2 | 3282 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |