[linux-block.git] / drivers / net / ethernet / lantiq_xrx200.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Lantiq / Intel PMAC driver for XRX200 SoCs
 *
 * Copyright (C) 2010 Lantiq Deutschland
 * Copyright (C) 2012 John Crispin <john@phrozen.org>
 * Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de>
 */

#include <linux/etherdevice.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/delay.h>

#include <linux/of_net.h>
#include <linux/of_platform.h>

#include <xway_dma.h>

/* DMA */
#define XRX200_DMA_DATA_LEN	0x600
#define XRX200_DMA_RX		0
#define XRX200_DMA_TX		1

/* cpu port mac */
#define PMAC_RX_IPG		0x0024
#define PMAC_RX_IPG_MASK	0xf

#define PMAC_HD_CTL		0x0000
/* Add Ethernet header to packets from DMA to PMAC */
#define PMAC_HD_CTL_ADD		BIT(0)
/* Add VLAN tag to Packets from DMA to PMAC */
#define PMAC_HD_CTL_TAG		BIT(1)
/* Add CRC to packets from DMA to PMAC */
#define PMAC_HD_CTL_AC		BIT(2)
/* Add status header to packets from PMAC to DMA */
#define PMAC_HD_CTL_AS		BIT(3)
/* Remove CRC from packets from PMAC to DMA */
#define PMAC_HD_CTL_RC		BIT(4)
/* Remove Layer-2 header from packets from PMAC to DMA */
#define PMAC_HD_CTL_RL2		BIT(5)
/* Status header is present from DMA to PMAC */
#define PMAC_HD_CTL_RXSH	BIT(6)
/* Add special tag from PMAC to switch */
#define PMAC_HD_CTL_AST		BIT(7)
/* Remove specail Tag from PMAC to DMA */
#define PMAC_HD_CTL_RST		BIT(8)
/* Check CRC from DMA to PMAC */
#define PMAC_HD_CTL_CCRC	BIT(9)
/* Enable reaction to Pause frames in the PMAC */
#define PMAC_HD_CTL_FC		BIT(10)

struct xrx200_chan {
	int tx_free;

	struct napi_struct napi;
	struct ltq_dma_channel dma;
	struct sk_buff *skb[LTQ_DESC_NUM];

	struct xrx200_priv *priv;
};

struct xrx200_priv {
	struct clk *clk;

	struct xrx200_chan chan_tx;
	struct xrx200_chan chan_rx;

	struct net_device *net_dev;
	struct device *dev;

	__iomem void *pmac_reg;
};

static u32 xrx200_pmac_r32(struct xrx200_priv *priv, u32 offset)
{
	return __raw_readl(priv->pmac_reg + offset);
}

static void xrx200_pmac_w32(struct xrx200_priv *priv, u32 val, u32 offset)
{
	__raw_writel(val, priv->pmac_reg + offset);
}

static void xrx200_pmac_mask(struct xrx200_priv *priv, u32 clear, u32 set,
			     u32 offset)
{
	u32 val = xrx200_pmac_r32(priv, offset);

	val &= ~(clear);
	val |= set;
	xrx200_pmac_w32(priv, val, offset);
}

/* drop all the packets from the DMA ring */
static void xrx200_flush_dma(struct xrx200_chan *ch)
{
	int i;

	for (i = 0; i < LTQ_DESC_NUM; i++) {
		struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];

		if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
			break;

		desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
			    XRX200_DMA_DATA_LEN;
		ch->dma.desc++;
		ch->dma.desc %= LTQ_DESC_NUM;
	}
}

static int xrx200_open(struct net_device *net_dev)
{
	struct xrx200_priv *priv = netdev_priv(net_dev);

	napi_enable(&priv->chan_tx.napi);
	ltq_dma_open(&priv->chan_tx.dma);
	ltq_dma_enable_irq(&priv->chan_tx.dma);

	napi_enable(&priv->chan_rx.napi);
	ltq_dma_open(&priv->chan_rx.dma);
	/* The boot loader does not always deactivate the receiving of frames
	 * on the ports and then some packets queue up in the PPE buffers.
	 * They already passed the PMAC so they do not have the tags
	 * configured here. Read the these packets here and drop them.
	 * The HW should have written them into memory after 10us
	 */
	usleep_range(20, 40);
	xrx200_flush_dma(&priv->chan_rx);
	ltq_dma_enable_irq(&priv->chan_rx.dma);

	netif_wake_queue(net_dev);

	return 0;
}

static int xrx200_close(struct net_device *net_dev)
{
	struct xrx200_priv *priv = netdev_priv(net_dev);

	netif_stop_queue(net_dev);

	napi_disable(&priv->chan_rx.napi);
	ltq_dma_close(&priv->chan_rx.dma);

	napi_disable(&priv->chan_tx.napi);
	ltq_dma_close(&priv->chan_tx.dma);

	return 0;
}

static int xrx200_alloc_skb(struct xrx200_chan *ch)
{
	int ret = 0;

	ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev,
							  XRX200_DMA_DATA_LEN);
	if (!ch->skb[ch->dma.desc]) {
		ret = -ENOMEM;
		goto skip;
	}

	ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(ch->priv->dev,
			ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
			DMA_FROM_DEVICE);
	if (unlikely(dma_mapping_error(ch->priv->dev,
				       ch->dma.desc_base[ch->dma.desc].addr))) {
		dev_kfree_skb_any(ch->skb[ch->dma.desc]);
		ret = -ENOMEM;
		goto skip;
	}

skip:
	ch->dma.desc_base[ch->dma.desc].ctl =
		LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
		XRX200_DMA_DATA_LEN;

	return ret;
}

static int xrx200_hw_receive(struct xrx200_chan *ch)
{
	struct xrx200_priv *priv = ch->priv;
	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	struct sk_buff *skb = ch->skb[ch->dma.desc];
	int len = (desc->ctl & LTQ_DMA_SIZE_MASK);
	struct net_device *net_dev = priv->net_dev;
	int ret;

	ret = xrx200_alloc_skb(ch);

	ch->dma.desc++;
	ch->dma.desc %= LTQ_DESC_NUM;

	if (ret) {
		netdev_err(net_dev, "failed to allocate new rx buffer\n");
		return ret;
	}

	skb_put(skb, len);
	skb->protocol = eth_type_trans(skb, net_dev);
	netif_receive_skb(skb);
	net_dev->stats.rx_packets++;
	net_dev->stats.rx_bytes += len - ETH_FCS_LEN;

	return 0;
}

static int xrx200_poll_rx(struct napi_struct *napi, int budget)
{
	struct xrx200_chan *ch = container_of(napi,
				struct xrx200_chan, napi);
	int rx = 0;
	int ret;

	while (rx < budget) {
		struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];

		if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
			ret = xrx200_hw_receive(ch);
			if (ret)
				return ret;
			rx++;
		} else {
			break;
		}
	}

	if (rx < budget) {
		if (napi_complete_done(&ch->napi, rx))
			ltq_dma_enable_irq(&ch->dma);
	}

	return rx;
}

static int xrx200_tx_housekeeping(struct napi_struct *napi, int budget)
{
	struct xrx200_chan *ch = container_of(napi,
				struct xrx200_chan, napi);
	struct net_device *net_dev = ch->priv->net_dev;
	int pkts = 0;
	int bytes = 0;

	netif_tx_lock(net_dev);
	while (pkts < budget) {
		struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->tx_free];

		if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
			struct sk_buff *skb = ch->skb[ch->tx_free];

			pkts++;
			bytes += skb->len;
			ch->skb[ch->tx_free] = NULL;
			consume_skb(skb);
			memset(&ch->dma.desc_base[ch->tx_free], 0,
			       sizeof(struct ltq_dma_desc));
			ch->tx_free++;
			ch->tx_free %= LTQ_DESC_NUM;
		} else {
			break;
		}
	}

	net_dev->stats.tx_packets += pkts;
	net_dev->stats.tx_bytes += bytes;
	netdev_completed_queue(ch->priv->net_dev, pkts, bytes);

	netif_tx_unlock(net_dev);
	if (netif_queue_stopped(net_dev))
		netif_wake_queue(net_dev);

	if (pkts < budget) {
		if (napi_complete_done(&ch->napi, pkts))
			ltq_dma_enable_irq(&ch->dma);
	}

	return pkts;
}

static netdev_tx_t xrx200_start_xmit(struct sk_buff *skb,
				     struct net_device *net_dev)
{
	struct xrx200_priv *priv = netdev_priv(net_dev);
	struct xrx200_chan *ch = &priv->chan_tx;
	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	u32 byte_offset;
	dma_addr_t mapping;
	int len;

	skb->dev = net_dev;
	if (skb_put_padto(skb, ETH_ZLEN)) {
		net_dev->stats.tx_dropped++;
		return NETDEV_TX_OK;
	}

	len = skb->len;

	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
		netdev_err(net_dev, "tx ring full\n");
		netif_stop_queue(net_dev);
		return NETDEV_TX_BUSY;
	}

	ch->skb[ch->dma.desc] = skb;

	mapping = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
	if (unlikely(dma_mapping_error(priv->dev, mapping)))
		goto err_drop;

	/* dma needs to start on a 16 byte aligned address */
	byte_offset = mapping % 16;

	desc->addr = mapping - byte_offset;
	/* Make sure the address is written before we give it to HW */
	wmb();
	desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
		LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
	ch->dma.desc++;
	ch->dma.desc %= LTQ_DESC_NUM;
	if (ch->dma.desc == ch->tx_free)
		netif_stop_queue(net_dev);

	netdev_sent_queue(net_dev, len);

	return NETDEV_TX_OK;

err_drop:
	dev_kfree_skb(skb);
	net_dev->stats.tx_dropped++;
	net_dev->stats.tx_errors++;
	return NETDEV_TX_OK;
}

static const struct net_device_ops xrx200_netdev_ops = {
	.ndo_open		= xrx200_open,
	.ndo_stop		= xrx200_close,
	.ndo_start_xmit		= xrx200_start_xmit,
	.ndo_set_mac_address	= eth_mac_addr,
	.ndo_validate_addr	= eth_validate_addr,
};

static irqreturn_t xrx200_dma_irq(int irq, void *ptr)
{
	struct xrx200_chan *ch = ptr;

	if (napi_schedule_prep(&ch->napi)) {
		__napi_schedule(&ch->napi);
		ltq_dma_disable_irq(&ch->dma);
	}

	ltq_dma_ack_irq(&ch->dma);

	return IRQ_HANDLED;
}

static int xrx200_dma_init(struct xrx200_priv *priv)
{
	struct xrx200_chan *ch_rx = &priv->chan_rx;
	struct xrx200_chan *ch_tx = &priv->chan_tx;
	int ret = 0;
	int i;

	ltq_dma_init_port(DMA_PORT_ETOP);

	ch_rx->dma.nr = XRX200_DMA_RX;
	ch_rx->dma.dev = priv->dev;
	ch_rx->priv = priv;

	ltq_dma_alloc_rx(&ch_rx->dma);
	for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM;
	     ch_rx->dma.desc++) {
		ret = xrx200_alloc_skb(ch_rx);
		if (ret)
			goto rx_free;
	}
	ch_rx->dma.desc = 0;
	ret = devm_request_irq(priv->dev, ch_rx->dma.irq, xrx200_dma_irq, 0,
			       "xrx200_net_rx", &priv->chan_rx);
	if (ret) {
		dev_err(priv->dev, "failed to request RX irq %d\n",
			ch_rx->dma.irq);
		goto rx_ring_free;
	}

	ch_tx->dma.nr = XRX200_DMA_TX;
	ch_tx->dma.dev = priv->dev;
	ch_tx->priv = priv;

	ltq_dma_alloc_tx(&ch_tx->dma);
	ret = devm_request_irq(priv->dev, ch_tx->dma.irq, xrx200_dma_irq, 0,
			       "xrx200_net_tx", &priv->chan_tx);
	if (ret) {
		dev_err(priv->dev, "failed to request TX irq %d\n",
			ch_tx->dma.irq);
		goto tx_free;
	}

	return ret;

tx_free:
	ltq_dma_free(&ch_tx->dma);

rx_ring_free:
	/* free the allocated RX ring */
	for (i = 0; i < LTQ_DESC_NUM; i++) {
		if (priv->chan_rx.skb[i])
			dev_kfree_skb_any(priv->chan_rx.skb[i]);
	}

rx_free:
	ltq_dma_free(&ch_rx->dma);
	return ret;
}

static void xrx200_hw_cleanup(struct xrx200_priv *priv)
{
	int i;

	ltq_dma_free(&priv->chan_tx.dma);
	ltq_dma_free(&priv->chan_rx.dma);

	/* free the allocated RX ring */
	for (i = 0; i < LTQ_DESC_NUM; i++)
		dev_kfree_skb_any(priv->chan_rx.skb[i]);
}

static int xrx200_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct resource *res;
	struct xrx200_priv *priv;
	struct net_device *net_dev;
	const u8 *mac;
	int err;

	/* alloc the network device */
	net_dev = devm_alloc_etherdev(dev, sizeof(struct xrx200_priv));
	if (!net_dev)
		return -ENOMEM;

	priv = netdev_priv(net_dev);
	priv->net_dev = net_dev;
	priv->dev = dev;

	net_dev->netdev_ops = &xrx200_netdev_ops;
	SET_NETDEV_DEV(net_dev, dev);
	net_dev->min_mtu = ETH_ZLEN;
	net_dev->max_mtu = XRX200_DMA_DATA_LEN;

	/* load the memory ranges */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(dev, "failed to get resources\n");
		return -ENOENT;
	}

	priv->pmac_reg = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->pmac_reg)) {
		dev_err(dev, "failed to request and remap io ranges\n");
		return PTR_ERR(priv->pmac_reg);
	}

	priv->chan_rx.dma.irq = platform_get_irq_byname(pdev, "rx");
	if (priv->chan_rx.dma.irq < 0)
		return -ENOENT;
	priv->chan_tx.dma.irq = platform_get_irq_byname(pdev, "tx");
	if (priv->chan_tx.dma.irq < 0)
		return -ENOENT;

	/* get the clock */
	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(dev, "failed to get clock\n");
		return PTR_ERR(priv->clk);
	}

	mac = of_get_mac_address(np);
	if (!IS_ERR(mac))
		ether_addr_copy(net_dev->dev_addr, mac);
	else
		eth_hw_addr_random(net_dev);

	/* bring up the dma engine and IP core */
	err = xrx200_dma_init(priv);
	if (err)
		return err;

	/* enable clock gate */
	err = clk_prepare_enable(priv->clk);
	if (err)
		goto err_uninit_dma;

	/* set IPG to 12 */
	xrx200_pmac_mask(priv, PMAC_RX_IPG_MASK, 0xb, PMAC_RX_IPG);

	/* enable status header, enable CRC */
	xrx200_pmac_mask(priv, 0,
			 PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH |
			 PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC,
			 PMAC_HD_CTL);

	/* setup NAPI */
	netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, 32);
	netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, 32);

	platform_set_drvdata(pdev, priv);

	err = register_netdev(net_dev);
	if (err)
		goto err_unprepare_clk;

	return 0;

err_unprepare_clk:
	clk_disable_unprepare(priv->clk);

err_uninit_dma:
	xrx200_hw_cleanup(priv);

	return err;
}

static int xrx200_remove(struct platform_device *pdev)
{
	struct xrx200_priv *priv = platform_get_drvdata(pdev);
	struct net_device *net_dev = priv->net_dev;

	/* free stack related instances */
	netif_stop_queue(net_dev);
	netif_napi_del(&priv->chan_tx.napi);
	netif_napi_del(&priv->chan_rx.napi);

	/* remove the actual device */
	unregister_netdev(net_dev);

	/* release the clock */
	clk_disable_unprepare(priv->clk);

	/* shut down hardware */
	xrx200_hw_cleanup(priv);

	return 0;
}

static const struct of_device_id xrx200_match[] = {
	{ .compatible = "lantiq,xrx200-net" },
	{},
};
MODULE_DEVICE_TABLE(of, xrx200_match);

static struct platform_driver xrx200_driver = {
	.probe = xrx200_probe,
	.remove = xrx200_remove,
	.driver = {
		.name = "lantiq,xrx200-net",
		.of_match_table = xrx200_match,
	},
};

module_platform_driver(xrx200_driver);

MODULE_AUTHOR("John Crispin <john@phrozen.org>");
MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
MODULE_LICENSE("GPL");
Commit	Line	Data
fe1a5642 HM	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Lantiq / Intel PMAC driver for XRX200 SoCs
	4	*
	5	* Copyright (C) 2010 Lantiq Deutschland
	6	* Copyright (C) 2012 John Crispin <john@phrozen.org>
	7	* Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de>
	8	*/
	9
	10	#include <linux/etherdevice.h>
	11	#include <linux/module.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/clk.h>
	15	#include <linux/delay.h>
	16
	17	#include <linux/of_net.h>
	18	#include <linux/of_platform.h>
	19
	20	#include <xway_dma.h>
	21
	22	/* DMA */
	23	#define XRX200_DMA_DATA_LEN 0x600
	24	#define XRX200_DMA_RX 0
	25	#define XRX200_DMA_TX 1
	26
	27	/* cpu port mac */
	28	#define PMAC_RX_IPG 0x0024
	29	#define PMAC_RX_IPG_MASK 0xf
	30
	31	#define PMAC_HD_CTL 0x0000
	32	/* Add Ethernet header to packets from DMA to PMAC */
	33	#define PMAC_HD_CTL_ADD BIT(0)
	34	/* Add VLAN tag to Packets from DMA to PMAC */
	35	#define PMAC_HD_CTL_TAG BIT(1)
	36	/* Add CRC to packets from DMA to PMAC */
	37	#define PMAC_HD_CTL_AC BIT(2)
	38	/* Add status header to packets from PMAC to DMA */
	39	#define PMAC_HD_CTL_AS BIT(3)
	40	/* Remove CRC from packets from PMAC to DMA */
	41	#define PMAC_HD_CTL_RC BIT(4)
	42	/* Remove Layer-2 header from packets from PMAC to DMA */
	43	#define PMAC_HD_CTL_RL2 BIT(5)
	44	/* Status header is present from DMA to PMAC */
	45	#define PMAC_HD_CTL_RXSH BIT(6)
	46	/* Add special tag from PMAC to switch */
	47	#define PMAC_HD_CTL_AST BIT(7)
	48	/* Remove specail Tag from PMAC to DMA */
	49	#define PMAC_HD_CTL_RST BIT(8)
	50	/* Check CRC from DMA to PMAC */
	51	#define PMAC_HD_CTL_CCRC BIT(9)
	52	/* Enable reaction to Pause frames in the PMAC */
	53	#define PMAC_HD_CTL_FC BIT(10)
	54
	55	struct xrx200_chan {
	56	int tx_free;
	57
	58	struct napi_struct napi;
	59	struct ltq_dma_channel dma;
	60	struct sk_buff *skb[LTQ_DESC_NUM];
	61
	62	struct xrx200_priv *priv;
	63	};
	64
65	struct xrx200_priv {
66	struct clk *clk;
67
68	struct xrx200_chan chan_tx;
69	struct xrx200_chan chan_rx;
70
71	struct net_device *net_dev;
72	struct device *dev;
73
74	__iomem void *pmac_reg;
75	};
76
77	static u32 xrx200_pmac_r32(struct xrx200_priv *priv, u32 offset)
78	{
79	return __raw_readl(priv->pmac_reg + offset);
80	}
81
82	static void xrx200_pmac_w32(struct xrx200_priv *priv, u32 val, u32 offset)
83	{
84	__raw_writel(val, priv->pmac_reg + offset);
85	}
86
87	static void xrx200_pmac_mask(struct xrx200_priv *priv, u32 clear, u32 set,
88	u32 offset)
89	{
90	u32 val = xrx200_pmac_r32(priv, offset);
91
92	val &= ~(clear);
93	val \|= set;
94	xrx200_pmac_w32(priv, val, offset);
95	}
96
97	/* drop all the packets from the DMA ring */
98	static void xrx200_flush_dma(struct xrx200_chan *ch)
99	{
100	int i;
101
102	for (i = 0; i < LTQ_DESC_NUM; i++) {
103	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
104
105	if ((desc->ctl & (LTQ_DMA_OWN \| LTQ_DMA_C)) != LTQ_DMA_C)
106	break;
107
108	desc->ctl = LTQ_DMA_OWN \| LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) \|
109	XRX200_DMA_DATA_LEN;
110	ch->dma.desc++;
111	ch->dma.desc %= LTQ_DESC_NUM;
112	}
113	}
114
115	static int xrx200_open(struct net_device *net_dev)
116	{
117	struct xrx200_priv *priv = netdev_priv(net_dev);
fe1a5642 HM	118
	119	napi_enable(&priv->chan_tx.napi);
	120	ltq_dma_open(&priv->chan_tx.dma);
	121	ltq_dma_enable_irq(&priv->chan_tx.dma);
	122
	123	napi_enable(&priv->chan_rx.napi);
	124	ltq_dma_open(&priv->chan_rx.dma);
	125	/* The boot loader does not always deactivate the receiving of frames
	126	* on the ports and then some packets queue up in the PPE buffers.
	127	* They already passed the PMAC so they do not have the tags
	128	* configured here. Read the these packets here and drop them.
	129	* The HW should have written them into memory after 10us
	130	*/
	131	usleep_range(20, 40);
	132	xrx200_flush_dma(&priv->chan_rx);
	133	ltq_dma_enable_irq(&priv->chan_rx.dma);
	134
	135	netif_wake_queue(net_dev);
	136
	137	return 0;
	138	}
	139
	140	static int xrx200_close(struct net_device *net_dev)
	141	{
	142	struct xrx200_priv *priv = netdev_priv(net_dev);
	143
	144	netif_stop_queue(net_dev);
	145
	146	napi_disable(&priv->chan_rx.napi);
	147	ltq_dma_close(&priv->chan_rx.dma);
	148
	149	napi_disable(&priv->chan_tx.napi);
	150	ltq_dma_close(&priv->chan_tx.dma);
	151
fe1a5642 HM	152	return 0;
	153	}
	154
	155	static int xrx200_alloc_skb(struct xrx200_chan *ch)
	156	{
	157	int ret = 0;
	158
	159	ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev,
	160	XRX200_DMA_DATA_LEN);
	161	if (!ch->skb[ch->dma.desc]) {
	162	ret = -ENOMEM;
	163	goto skip;
	164	}
	165
	166	ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(ch->priv->dev,
	167	ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
	168	DMA_FROM_DEVICE);
	169	if (unlikely(dma_mapping_error(ch->priv->dev,
	170	ch->dma.desc_base[ch->dma.desc].addr))) {
	171	dev_kfree_skb_any(ch->skb[ch->dma.desc]);
	172	ret = -ENOMEM;
	173	goto skip;
	174	}
	175
	176	skip:
	177	ch->dma.desc_base[ch->dma.desc].ctl =
	178	LTQ_DMA_OWN \| LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) \|
	179	XRX200_DMA_DATA_LEN;
	180
	181	return ret;
	182	}
	183
	184	static int xrx200_hw_receive(struct xrx200_chan *ch)
	185	{
	186	struct xrx200_priv *priv = ch->priv;
	187	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	188	struct sk_buff *skb = ch->skb[ch->dma.desc];
	189	int len = (desc->ctl & LTQ_DMA_SIZE_MASK);
	190	struct net_device *net_dev = priv->net_dev;
	191	int ret;
	192
	193	ret = xrx200_alloc_skb(ch);
	194
	195	ch->dma.desc++;
	196	ch->dma.desc %= LTQ_DESC_NUM;
	197
	198	if (ret) {
	199	netdev_err(net_dev, "failed to allocate new rx buffer\n");
	200	return ret;
	201	}
	202
	203	skb_put(skb, len);
	204	skb->protocol = eth_type_trans(skb, net_dev);
	205	netif_receive_skb(skb);
	206	net_dev->stats.rx_packets++;
	207	net_dev->stats.rx_bytes += len - ETH_FCS_LEN;
	208
	209	return 0;
	210	}
	211
	212	static int xrx200_poll_rx(struct napi_struct *napi, int budget)
	213	{
	214	struct xrx200_chan *ch = container_of(napi,
	215	struct xrx200_chan, napi);
216	int rx = 0;
217	int ret;
218
219	while (rx < budget) {
220	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
221
222	if ((desc->ctl & (LTQ_DMA_OWN \| LTQ_DMA_C)) == LTQ_DMA_C) {
223	ret = xrx200_hw_receive(ch);
224	if (ret)
225	return ret;
226	rx++;
227	} else {
228	break;
229	}
230	}
231
232	if (rx < budget) {
c582a7fe HM	233	if (napi_complete_done(&ch->napi, rx))
c582a7fe HM	234	ltq_dma_enable_irq(&ch->dma);
fe1a5642 HM	235	}
	236
	237	return rx;
	238	}
	239
	240	static int xrx200_tx_housekeeping(struct napi_struct *napi, int budget)
	241	{
	242	struct xrx200_chan *ch = container_of(napi,
	243	struct xrx200_chan, napi);
	244	struct net_device *net_dev = ch->priv->net_dev;
	245	int pkts = 0;
	246	int bytes = 0;
	247
f9317ae5	248	netif_tx_lock(net_dev);
fe1a5642 HM	249	while (pkts < budget) {
	250	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->tx_free];
	251
	252	if ((desc->ctl & (LTQ_DMA_OWN \| LTQ_DMA_C)) == LTQ_DMA_C) {
	253	struct sk_buff *skb = ch->skb[ch->tx_free];
	254
	255	pkts++;
	256	bytes += skb->len;
	257	ch->skb[ch->tx_free] = NULL;
	258	consume_skb(skb);
	259	memset(&ch->dma.desc_base[ch->tx_free], 0,
	260	sizeof(struct ltq_dma_desc));
	261	ch->tx_free++;
	262	ch->tx_free %= LTQ_DESC_NUM;
	263	} else {
	264	break;
	265	}
	266	}
	267
	268	net_dev->stats.tx_packets += pkts;
	269	net_dev->stats.tx_bytes += bytes;
	270	netdev_completed_queue(ch->priv->net_dev, pkts, bytes);
	271
f9317ae5	272	netif_tx_unlock(net_dev);
dea36631 HM	273	if (netif_queue_stopped(net_dev))
	274	netif_wake_queue(net_dev);
	275
fe1a5642	276	if (pkts < budget) {
c582a7fe HM	277	if (napi_complete_done(&ch->napi, pkts))
c582a7fe HM	278	ltq_dma_enable_irq(&ch->dma);
fe1a5642 HM	279	}
	280
	281	return pkts;
	282	}
	283
1cfecc23 YW	284	static netdev_tx_t xrx200_start_xmit(struct sk_buff *skb,
1cfecc23 YW	285	struct net_device *net_dev)
fe1a5642 HM	286	{
	287	struct xrx200_priv *priv = netdev_priv(net_dev);
	288	struct xrx200_chan *ch = &priv->chan_tx;
	289	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	290	u32 byte_offset;
	291	dma_addr_t mapping;
	292	int len;
	293
	294	skb->dev = net_dev;
	295	if (skb_put_padto(skb, ETH_ZLEN)) {
	296	net_dev->stats.tx_dropped++;
	297	return NETDEV_TX_OK;
	298	}
	299
	300	len = skb->len;
	301
	302	if ((desc->ctl & (LTQ_DMA_OWN \| LTQ_DMA_C)) \|\| ch->skb[ch->dma.desc]) {
	303	netdev_err(net_dev, "tx ring full\n");
	304	netif_stop_queue(net_dev);
	305	return NETDEV_TX_BUSY;
	306	}
	307
	308	ch->skb[ch->dma.desc] = skb;
	309
	310	mapping = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
	311	if (unlikely(dma_mapping_error(priv->dev, mapping)))
	312	goto err_drop;
	313
	314	/* dma needs to start on a 16 byte aligned address */
	315	byte_offset = mapping % 16;
	316
	317	desc->addr = mapping - byte_offset;
	318	/* Make sure the address is written before we give it to HW */
	319	wmb();
	320	desc->ctl = LTQ_DMA_OWN \| LTQ_DMA_SOP \| LTQ_DMA_EOP \|
	321	LTQ_DMA_TX_OFFSET(byte_offset) \| (len & LTQ_DMA_SIZE_MASK);
	322	ch->dma.desc++;
	323	ch->dma.desc %= LTQ_DESC_NUM;
	324	if (ch->dma.desc == ch->tx_free)
	325	netif_stop_queue(net_dev);
	326
	327	netdev_sent_queue(net_dev, len);
	328
	329	return NETDEV_TX_OK;
	330
	331	err_drop:
	332	dev_kfree_skb(skb);
	333	net_dev->stats.tx_dropped++;
	334	net_dev->stats.tx_errors++;
	335	return NETDEV_TX_OK;
	336	}
	337
	338	static const struct net_device_ops xrx200_netdev_ops = {
	339	.ndo_open = xrx200_open,
	340	.ndo_stop = xrx200_close,
	341	.ndo_start_xmit = xrx200_start_xmit,
	342	.ndo_set_mac_address = eth_mac_addr,
	343	.ndo_validate_addr = eth_validate_addr,
fe1a5642 HM	344	};
	345
	346	static irqreturn_t xrx200_dma_irq(int irq, void *ptr)
	347	{
	348	struct xrx200_chan *ch = ptr;
	349
9423361d HM	350	if (napi_schedule_prep(&ch->napi)) {
	351	__napi_schedule(&ch->napi);
	352	ltq_dma_disable_irq(&ch->dma);
	353	}
fe1a5642	354
9423361d	355	ltq_dma_ack_irq(&ch->dma);
fe1a5642 HM	356
	357	return IRQ_HANDLED;
	358	}
	359
	360	static int xrx200_dma_init(struct xrx200_priv *priv)
	361	{
	362	struct xrx200_chan *ch_rx = &priv->chan_rx;
	363	struct xrx200_chan *ch_tx = &priv->chan_tx;
	364	int ret = 0;
	365	int i;
	366
	367	ltq_dma_init_port(DMA_PORT_ETOP);
	368
	369	ch_rx->dma.nr = XRX200_DMA_RX;
	370	ch_rx->dma.dev = priv->dev;
	371	ch_rx->priv = priv;
	372
	373	ltq_dma_alloc_rx(&ch_rx->dma);
	374	for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM;
	375	ch_rx->dma.desc++) {
	376	ret = xrx200_alloc_skb(ch_rx);
	377	if (ret)
	378	goto rx_free;
	379	}
	380	ch_rx->dma.desc = 0;
	381	ret = devm_request_irq(priv->dev, ch_rx->dma.irq, xrx200_dma_irq, 0,
	382	"xrx200_net_rx", &priv->chan_rx);
	383	if (ret) {
	384	dev_err(priv->dev, "failed to request RX irq %d\n",
	385	ch_rx->dma.irq);
	386	goto rx_ring_free;
	387	}
	388
	389	ch_tx->dma.nr = XRX200_DMA_TX;
	390	ch_tx->dma.dev = priv->dev;
	391	ch_tx->priv = priv;
	392
	393	ltq_dma_alloc_tx(&ch_tx->dma);
	394	ret = devm_request_irq(priv->dev, ch_tx->dma.irq, xrx200_dma_irq, 0,
	395	"xrx200_net_tx", &priv->chan_tx);
	396	if (ret) {
	397	dev_err(priv->dev, "failed to request TX irq %d\n",
	398	ch_tx->dma.irq);
	399	goto tx_free;
	400	}
	401
	402	return ret;
	403
	404	tx_free:
	405	ltq_dma_free(&ch_tx->dma);
	406
	407	rx_ring_free:
	408	/* free the allocated RX ring */
	409	for (i = 0; i < LTQ_DESC_NUM; i++) {
	410	if (priv->chan_rx.skb[i])
	411	dev_kfree_skb_any(priv->chan_rx.skb[i]);
	412	}
	413
	414	rx_free:
	415	ltq_dma_free(&ch_rx->dma);
	416	return ret;
	417	}
	418
	419	static void xrx200_hw_cleanup(struct xrx200_priv *priv)
420	{
421	int i;
422
423	ltq_dma_free(&priv->chan_tx.dma);
424	ltq_dma_free(&priv->chan_rx.dma);
425
426	/* free the allocated RX ring */
427	for (i = 0; i < LTQ_DESC_NUM; i++)
428	dev_kfree_skb_any(priv->chan_rx.skb[i]);
429	}
430
431	static int xrx200_probe(struct platform_device *pdev)
432	{
433	struct device *dev = &pdev->dev;
434	struct device_node *np = dev->of_node;
435	struct resource *res;
436	struct xrx200_priv *priv;
437	struct net_device *net_dev;
438	const u8 *mac;
439	int err;
440
441	/* alloc the network device */
442	net_dev = devm_alloc_etherdev(dev, sizeof(struct xrx200_priv));
443	if (!net_dev)
444	return -ENOMEM;
445
446	priv = netdev_priv(net_dev);
447	priv->net_dev = net_dev;
448	priv->dev = dev;
449
450	net_dev->netdev_ops = &xrx200_netdev_ops;
451	SET_NETDEV_DEV(net_dev, dev);
452	net_dev->min_mtu = ETH_ZLEN;
453	net_dev->max_mtu = XRX200_DMA_DATA_LEN;
454
455	/* load the memory ranges */
456	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
457	if (!res) {
458	dev_err(dev, "failed to get resources\n");
459	return -ENOENT;
460	}
461
462	priv->pmac_reg = devm_ioremap_resource(dev, res);
b8b2de91	463	if (IS_ERR(priv->pmac_reg)) {
fe1a5642	464	dev_err(dev, "failed to request and remap io ranges\n");
b8b2de91	465	return PTR_ERR(priv->pmac_reg);
fe1a5642 HM	466	}
	467
	468	priv->chan_rx.dma.irq = platform_get_irq_byname(pdev, "rx");
d1a55841	469	if (priv->chan_rx.dma.irq < 0)
fe1a5642	470	return -ENOENT;
fe1a5642	471	priv->chan_tx.dma.irq = platform_get_irq_byname(pdev, "tx");
d1a55841	472	if (priv->chan_tx.dma.irq < 0)
fe1a5642	473	return -ENOENT;
fe1a5642 HM	474
	475	/* get the clock */
	476	priv->clk = devm_clk_get(dev, NULL);
	477	if (IS_ERR(priv->clk)) {
	478	dev_err(dev, "failed to get clock\n");
	479	return PTR_ERR(priv->clk);
	480	}
	481
	482	mac = of_get_mac_address(np);
a51645f7	483	if (!IS_ERR(mac))
fe1a5642 HM	484	ether_addr_copy(net_dev->dev_addr, mac);
	485	else
	486	eth_hw_addr_random(net_dev);
	487
	488	/* bring up the dma engine and IP core */
	489	err = xrx200_dma_init(priv);
	490	if (err)
	491	return err;
	492
a44ecfbd HM	493	/* enable clock gate */
	494	err = clk_prepare_enable(priv->clk);
	495	if (err)
	496	goto err_uninit_dma;
	497
fe1a5642 HM	498	/* set IPG to 12 */
	499	xrx200_pmac_mask(priv, PMAC_RX_IPG_MASK, 0xb, PMAC_RX_IPG);
	500
	501	/* enable status header, enable CRC */
	502	xrx200_pmac_mask(priv, 0,
	503	PMAC_HD_CTL_RST \| PMAC_HD_CTL_AST \| PMAC_HD_CTL_RXSH \|
	504	PMAC_HD_CTL_AS \| PMAC_HD_CTL_AC \| PMAC_HD_CTL_RC,
	505	PMAC_HD_CTL);
	506
	507	/* setup NAPI */
	508	netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, 32);
74c7b80e	509	netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, 32);
fe1a5642 HM	510
	511	platform_set_drvdata(pdev, priv);
	512
	513	err = register_netdev(net_dev);
	514	if (err)
a44ecfbd	515	goto err_unprepare_clk;
06bc4d00 CJ	516
06bc4d00 CJ	517	return 0;
fe1a5642	518
a44ecfbd HM	519	err_unprepare_clk:
	520	clk_disable_unprepare(priv->clk);
	521
fe1a5642 HM	522	err_uninit_dma:
	523	xrx200_hw_cleanup(priv);
	524
06bc4d00	525	return err;
fe1a5642 HM	526	}
	527
	528	static int xrx200_remove(struct platform_device *pdev)
	529	{
	530	struct xrx200_priv *priv = platform_get_drvdata(pdev);
	531	struct net_device *net_dev = priv->net_dev;
	532
	533	/* free stack related instances */
	534	netif_stop_queue(net_dev);
	535	netif_napi_del(&priv->chan_tx.napi);
	536	netif_napi_del(&priv->chan_rx.napi);
	537
	538	/* remove the actual device */
	539	unregister_netdev(net_dev);
	540
a44ecfbd HM	541	/* release the clock */
	542	clk_disable_unprepare(priv->clk);
	543
fe1a5642 HM	544	/* shut down hardware */
	545	xrx200_hw_cleanup(priv);
	546
	547	return 0;
	548	}
	549
	550	static const struct of_device_id xrx200_match[] = {
	551	{ .compatible = "lantiq,xrx200-net" },
	552	{},
	553	};
	554	MODULE_DEVICE_TABLE(of, xrx200_match);
	555
	556	static struct platform_driver xrx200_driver = {
	557	.probe = xrx200_probe,
	558	.remove = xrx200_remove,
	559	.driver = {
	560	.name = "lantiq,xrx200-net",
	561	.of_match_table = xrx200_match,
	562	},
	563	};
	564
	565	module_platform_driver(xrx200_driver);
	566
	567	MODULE_AUTHOR("John Crispin <john@phrozen.org>");
	568	MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
	569	MODULE_LICENSE("GPL");