[linux-2.6-block.git] / drivers / net / ethernet / lantiq_etop.c

/*
 *   This program is free software; you can redistribute it and/or modify it
 *   under the terms of the GNU General Public License version 2 as published
 *   by the Free Software Foundation.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 */

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/uaccess.h>
#include <linux/in.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/phy.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/mm.h>
#include <linux/platform_device.h>
#include <linux/ethtool.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>

#include <asm/checksum.h>

#include <lantiq_soc.h>
#include <xway_dma.h>
#include <lantiq_platform.h>

#define LTQ_ETOP_MDIO		0x11804
#define MDIO_REQUEST		0x80000000
#define MDIO_READ		0x40000000
#define MDIO_ADDR_MASK		0x1f
#define MDIO_ADDR_OFFSET	0x15
#define MDIO_REG_MASK		0x1f
#define MDIO_REG_OFFSET		0x10
#define MDIO_VAL_MASK		0xffff

#define PPE32_CGEN		0x800
#define LQ_PPE32_ENET_MAC_CFG	0x1840

#define LTQ_ETOP_ENETS0		0x11850
#define LTQ_ETOP_MAC_DA0	0x1186C
#define LTQ_ETOP_MAC_DA1	0x11870
#define LTQ_ETOP_CFG		0x16020
#define LTQ_ETOP_IGPLEN		0x16080

#define MAX_DMA_CHAN		0x8
#define MAX_DMA_CRC_LEN		0x4
#define MAX_DMA_DATA_LEN	0x600

#define ETOP_FTCU		BIT(28)
#define ETOP_MII_MASK		0xf
#define ETOP_MII_NORMAL		0xd
#define ETOP_MII_REVERSE	0xe
#define ETOP_PLEN_UNDER		0x40
#define ETOP_CGEN		0x800

/* use 2 static channels for TX/RX */
#define LTQ_ETOP_TX_CHANNEL	1
#define LTQ_ETOP_RX_CHANNEL	6
#define IS_TX(x)		(x == LTQ_ETOP_TX_CHANNEL)
#define IS_RX(x)		(x == LTQ_ETOP_RX_CHANNEL)

#define ltq_etop_r32(x)		ltq_r32(ltq_etop_membase + (x))
#define ltq_etop_w32(x, y)	ltq_w32(x, ltq_etop_membase + (y))
#define ltq_etop_w32_mask(x, y, z)	\
		ltq_w32_mask(x, y, ltq_etop_membase + (z))

#define DRV_VERSION	"1.0"

static void __iomem *ltq_etop_membase;

struct ltq_etop_chan {
	int idx;
	int tx_free;
	struct net_device *netdev;
	struct napi_struct napi;
	struct ltq_dma_channel dma;
	struct sk_buff *skb[LTQ_DESC_NUM];
};

struct ltq_etop_priv {
	struct net_device *netdev;
	struct platform_device *pdev;
	struct ltq_eth_data *pldata;
	struct resource *res;

	struct mii_bus *mii_bus;

	struct ltq_etop_chan ch[MAX_DMA_CHAN];
	int tx_free[MAX_DMA_CHAN >> 1];

	spinlock_t lock;
};

static int
ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
{
	ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
	if (!ch->skb[ch->dma.desc])
		return -ENOMEM;
	ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
		ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
		DMA_FROM_DEVICE);
	ch->dma.desc_base[ch->dma.desc].addr =
		CPHYSADDR(ch->skb[ch->dma.desc]->data);
	ch->dma.desc_base[ch->dma.desc].ctl =
		LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
		MAX_DMA_DATA_LEN;
	skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
	return 0;
}

static void
ltq_etop_hw_receive(struct ltq_etop_chan *ch)
{
	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	struct sk_buff *skb = ch->skb[ch->dma.desc];
	int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	if (ltq_etop_alloc_skb(ch)) {
		netdev_err(ch->netdev,
			"failed to allocate new rx buffer, stopping DMA\n");
		ltq_dma_close(&ch->dma);
	}
	ch->dma.desc++;
	ch->dma.desc %= LTQ_DESC_NUM;
	spin_unlock_irqrestore(&priv->lock, flags);

	skb_put(skb, len);
	skb->protocol = eth_type_trans(skb, ch->netdev);
	netif_receive_skb(skb);
}

static int
ltq_etop_poll_rx(struct napi_struct *napi, int budget)
{
	struct ltq_etop_chan *ch = container_of(napi,
				struct ltq_etop_chan, napi);
	int work_done = 0;

	while (work_done < budget) {
		struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];

		if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
			break;
		ltq_etop_hw_receive(ch);
		work_done++;
	}
	if (work_done < budget) {
		napi_complete_done(&ch->napi, work_done);
		ltq_dma_ack_irq(&ch->dma);
	}
	return work_done;
}

static int
ltq_etop_poll_tx(struct napi_struct *napi, int budget)
{
	struct ltq_etop_chan *ch =
		container_of(napi, struct ltq_etop_chan, napi);
	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
	struct netdev_queue *txq =
		netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	while ((ch->dma.desc_base[ch->tx_free].ctl &
			(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
		dev_kfree_skb_any(ch->skb[ch->tx_free]);
		ch->skb[ch->tx_free] = NULL;
		memset(&ch->dma.desc_base[ch->tx_free], 0,
			sizeof(struct ltq_dma_desc));
		ch->tx_free++;
		ch->tx_free %= LTQ_DESC_NUM;
	}
	spin_unlock_irqrestore(&priv->lock, flags);

	if (netif_tx_queue_stopped(txq))
		netif_tx_start_queue(txq);
	napi_complete(&ch->napi);
	ltq_dma_ack_irq(&ch->dma);
	return 1;
}

static irqreturn_t
ltq_etop_dma_irq(int irq, void *_priv)
{
	struct ltq_etop_priv *priv = _priv;
	int ch = irq - LTQ_DMA_CH0_INT;

	napi_schedule(&priv->ch[ch].napi);
	return IRQ_HANDLED;
}

static void
ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);

	ltq_dma_free(&ch->dma);
	if (ch->dma.irq)
		free_irq(ch->dma.irq, priv);
	if (IS_RX(ch->idx)) {
		int desc;
		for (desc = 0; desc < LTQ_DESC_NUM; desc++)
			dev_kfree_skb_any(ch->skb[ch->dma.desc]);
	}
}

static void
ltq_etop_hw_exit(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	int i;

	ltq_pmu_disable(PMU_PPE);
	for (i = 0; i < MAX_DMA_CHAN; i++)
		if (IS_TX(i) || IS_RX(i))
			ltq_etop_free_channel(dev, &priv->ch[i]);
}

static int
ltq_etop_hw_init(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	int i;

	ltq_pmu_enable(PMU_PPE);

	switch (priv->pldata->mii_mode) {
	case PHY_INTERFACE_MODE_RMII:
		ltq_etop_w32_mask(ETOP_MII_MASK,
			ETOP_MII_REVERSE, LTQ_ETOP_CFG);
		break;

	case PHY_INTERFACE_MODE_MII:
		ltq_etop_w32_mask(ETOP_MII_MASK,
			ETOP_MII_NORMAL, LTQ_ETOP_CFG);
		break;

	default:
		netdev_err(dev, "unknown mii mode %d\n",
			priv->pldata->mii_mode);
		return -ENOTSUPP;
	}

	/* enable crc generation */
	ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);

	ltq_dma_init_port(DMA_PORT_ETOP);

	for (i = 0; i < MAX_DMA_CHAN; i++) {
		int irq = LTQ_DMA_CH0_INT + i;
		struct ltq_etop_chan *ch = &priv->ch[i];

		ch->idx = ch->dma.nr = i;
		ch->dma.dev = &priv->pdev->dev;

		if (IS_TX(i)) {
			ltq_dma_alloc_tx(&ch->dma);
			request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
		} else if (IS_RX(i)) {
			ltq_dma_alloc_rx(&ch->dma);
			for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
					ch->dma.desc++)
				if (ltq_etop_alloc_skb(ch))
					return -ENOMEM;
			ch->dma.desc = 0;
			request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
		}
		ch->dma.irq = irq;
	}
	return 0;
}

static void
ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
	strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
	strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
}

static const struct ethtool_ops ltq_etop_ethtool_ops = {
	.get_drvinfo = ltq_etop_get_drvinfo,
	.nway_reset = phy_ethtool_nway_reset,
	.get_link_ksettings = phy_ethtool_get_link_ksettings,
	.set_link_ksettings = phy_ethtool_set_link_ksettings,
};

static int
ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
{
	u32 val = MDIO_REQUEST |
		((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
		phy_data;

	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
		;
	ltq_etop_w32(val, LTQ_ETOP_MDIO);
	return 0;
}

static int
ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
{
	u32 val = MDIO_REQUEST | MDIO_READ |
		((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);

	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
		;
	ltq_etop_w32(val, LTQ_ETOP_MDIO);
	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
		;
	val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
	return val;
}

static void
ltq_etop_mdio_link(struct net_device *dev)
{
	/* nothing to do  */
}

static int
ltq_etop_mdio_probe(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	struct phy_device *phydev;

	phydev = phy_find_first(priv->mii_bus);

	if (!phydev) {
		netdev_err(dev, "no PHY found\n");
		return -ENODEV;
	}

	phydev = phy_connect(dev, phydev_name(phydev),
			     &ltq_etop_mdio_link, priv->pldata->mii_mode);

	if (IS_ERR(phydev)) {
		netdev_err(dev, "Could not attach to PHY\n");
		return PTR_ERR(phydev);
	}

	phy_set_max_speed(phydev, SPEED_100);

	phy_attached_info(phydev);

	return 0;
}

static int
ltq_etop_mdio_init(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	int err;

	priv->mii_bus = mdiobus_alloc();
	if (!priv->mii_bus) {
		netdev_err(dev, "failed to allocate mii bus\n");
		err = -ENOMEM;
		goto err_out;
	}

	priv->mii_bus->priv = dev;
	priv->mii_bus->read = ltq_etop_mdio_rd;
	priv->mii_bus->write = ltq_etop_mdio_wr;
	priv->mii_bus->name = "ltq_mii";
	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
		priv->pdev->name, priv->pdev->id);
	if (mdiobus_register(priv->mii_bus)) {
		err = -ENXIO;
		goto err_out_free_mdiobus;
	}

	if (ltq_etop_mdio_probe(dev)) {
		err = -ENXIO;
		goto err_out_unregister_bus;
	}
	return 0;

err_out_unregister_bus:
	mdiobus_unregister(priv->mii_bus);
err_out_free_mdiobus:
	mdiobus_free(priv->mii_bus);
err_out:
	return err;
}

static void
ltq_etop_mdio_cleanup(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);

	phy_disconnect(dev->phydev);
	mdiobus_unregister(priv->mii_bus);
	mdiobus_free(priv->mii_bus);
}

static int
ltq_etop_open(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	int i;

	for (i = 0; i < MAX_DMA_CHAN; i++) {
		struct ltq_etop_chan *ch = &priv->ch[i];

		if (!IS_TX(i) && (!IS_RX(i)))
			continue;
		ltq_dma_open(&ch->dma);
		napi_enable(&ch->napi);
	}
	phy_start(dev->phydev);
	netif_tx_start_all_queues(dev);
	return 0;
}

static int
ltq_etop_stop(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	int i;

	netif_tx_stop_all_queues(dev);
	phy_stop(dev->phydev);
	for (i = 0; i < MAX_DMA_CHAN; i++) {
		struct ltq_etop_chan *ch = &priv->ch[i];

		if (!IS_RX(i) && !IS_TX(i))
			continue;
		napi_disable(&ch->napi);
		ltq_dma_close(&ch->dma);
	}
	return 0;
}

static int
ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
{
	int queue = skb_get_queue_mapping(skb);
	struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
	struct ltq_etop_priv *priv = netdev_priv(dev);
	struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	int len;
	unsigned long flags;
	u32 byte_offset;

	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;

	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
		dev_kfree_skb_any(skb);
		netdev_err(dev, "tx ring full\n");
		netif_tx_stop_queue(txq);
		return NETDEV_TX_BUSY;
	}

	/* dma needs to start on a 16 byte aligned address */
	byte_offset = CPHYSADDR(skb->data) % 16;
	ch->skb[ch->dma.desc] = skb;

	netif_trans_update(dev);

	spin_lock_irqsave(&priv->lock, flags);
	desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
						DMA_TO_DEVICE)) - byte_offset;
	wmb();
	desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
		LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
	ch->dma.desc++;
	ch->dma.desc %= LTQ_DESC_NUM;
	spin_unlock_irqrestore(&priv->lock, flags);

	if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
		netif_tx_stop_queue(txq);

	return NETDEV_TX_OK;
}

static int
ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	unsigned long flags;

	dev->mtu = new_mtu;

	spin_lock_irqsave(&priv->lock, flags);
	ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
	spin_unlock_irqrestore(&priv->lock, flags);

	return 0;
}

static int
ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
	/* TODO: mii-toll reports "No MII transceiver present!." ?!*/
	return phy_mii_ioctl(dev->phydev, rq, cmd);
}

static int
ltq_etop_set_mac_address(struct net_device *dev, void *p)
{
	int ret = eth_mac_addr(dev, p);

	if (!ret) {
		struct ltq_etop_priv *priv = netdev_priv(dev);
		unsigned long flags;

		/* store the mac for the unicast filter */
		spin_lock_irqsave(&priv->lock, flags);
		ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
		ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
			LTQ_ETOP_MAC_DA1);
		spin_unlock_irqrestore(&priv->lock, flags);
	}
	return ret;
}

static void
ltq_etop_set_multicast_list(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	unsigned long flags;

	/* ensure that the unicast filter is not enabled in promiscious mode */
	spin_lock_irqsave(&priv->lock, flags);
	if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
		ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
	else
		ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static int
ltq_etop_init(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	struct sockaddr mac;
	int err;
	bool random_mac = false;

	dev->watchdog_timeo = 10 * HZ;
	err = ltq_etop_hw_init(dev);
	if (err)
		goto err_hw;
	ltq_etop_change_mtu(dev, 1500);

	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
	if (!is_valid_ether_addr(mac.sa_data)) {
		pr_warn("etop: invalid MAC, using random\n");
		eth_random_addr(mac.sa_data);
		random_mac = true;
	}

	err = ltq_etop_set_mac_address(dev, &mac);
	if (err)
		goto err_netdev;

	/* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
	if (random_mac)
		dev->addr_assign_type = NET_ADDR_RANDOM;

	ltq_etop_set_multicast_list(dev);
	err = ltq_etop_mdio_init(dev);
	if (err)
		goto err_netdev;
	return 0;

err_netdev:
	unregister_netdev(dev);
	free_netdev(dev);
err_hw:
	ltq_etop_hw_exit(dev);
	return err;
}

static void
ltq_etop_tx_timeout(struct net_device *dev)
{
	int err;

	ltq_etop_hw_exit(dev);
	err = ltq_etop_hw_init(dev);
	if (err)
		goto err_hw;
	netif_trans_update(dev);
	netif_wake_queue(dev);
	return;

err_hw:
	ltq_etop_hw_exit(dev);
	netdev_err(dev, "failed to restart etop after TX timeout\n");
}

static const struct net_device_ops ltq_eth_netdev_ops = {
	.ndo_open = ltq_etop_open,
	.ndo_stop = ltq_etop_stop,
	.ndo_start_xmit = ltq_etop_tx,
	.ndo_change_mtu = ltq_etop_change_mtu,
	.ndo_do_ioctl = ltq_etop_ioctl,
	.ndo_set_mac_address = ltq_etop_set_mac_address,
	.ndo_validate_addr = eth_validate_addr,
	.ndo_set_rx_mode = ltq_etop_set_multicast_list,
	.ndo_select_queue = dev_pick_tx_zero,
	.ndo_init = ltq_etop_init,
	.ndo_tx_timeout = ltq_etop_tx_timeout,
};

static int __init
ltq_etop_probe(struct platform_device *pdev)
{
	struct net_device *dev;
	struct ltq_etop_priv *priv;
	struct resource *res;
	int err;
	int i;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "failed to get etop resource\n");
		err = -ENOENT;
		goto err_out;
	}

	res = devm_request_mem_region(&pdev->dev, res->start,
		resource_size(res), dev_name(&pdev->dev));
	if (!res) {
		dev_err(&pdev->dev, "failed to request etop resource\n");
		err = -EBUSY;
		goto err_out;
	}

	ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
		res->start, resource_size(res));
	if (!ltq_etop_membase) {
		dev_err(&pdev->dev, "failed to remap etop engine %d\n",
			pdev->id);
		err = -ENOMEM;
		goto err_out;
	}

	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
	if (!dev) {
		err = -ENOMEM;
		goto err_out;
	}
	strcpy(dev->name, "eth%d");
	dev->netdev_ops = &ltq_eth_netdev_ops;
	dev->ethtool_ops = &ltq_etop_ethtool_ops;
	priv = netdev_priv(dev);
	priv->res = res;
	priv->pdev = pdev;
	priv->pldata = dev_get_platdata(&pdev->dev);
	priv->netdev = dev;
	spin_lock_init(&priv->lock);
	SET_NETDEV_DEV(dev, &pdev->dev);

	for (i = 0; i < MAX_DMA_CHAN; i++) {
		if (IS_TX(i))
			netif_napi_add(dev, &priv->ch[i].napi,
				ltq_etop_poll_tx, 8);
		else if (IS_RX(i))
			netif_napi_add(dev, &priv->ch[i].napi,
				ltq_etop_poll_rx, 32);
		priv->ch[i].netdev = dev;
	}

	err = register_netdev(dev);
	if (err)
		goto err_free;

	platform_set_drvdata(pdev, dev);
	return 0;

err_free:
	free_netdev(dev);
err_out:
	return err;
}

static int
ltq_etop_remove(struct platform_device *pdev)
{
	struct net_device *dev = platform_get_drvdata(pdev);

	if (dev) {
		netif_tx_stop_all_queues(dev);
		ltq_etop_hw_exit(dev);
		ltq_etop_mdio_cleanup(dev);
		unregister_netdev(dev);
	}
	return 0;
}

static struct platform_driver ltq_mii_driver = {
	.remove = ltq_etop_remove,
	.driver = {
		.name = "ltq_etop",
	},
};

int __init
init_ltq_etop(void)
{
	int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);

	if (ret)
		pr_err("ltq_etop: Error registering platform driver!");
	return ret;
}

static void __exit
exit_ltq_etop(void)
{
	platform_driver_unregister(&ltq_mii_driver);
}

module_init(init_ltq_etop);
module_exit(exit_ltq_etop);

MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("Lantiq SoC ETOP");
MODULE_LICENSE("GPL");
Commit	Line	Data
504d4721 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
0ab75ae8	12	* along with this program; if not, see <http://www.gnu.org/licenses/>.
504d4721 JC	13	*
	14	* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
	15	*/
	16
	17	#include <linux/kernel.h>
	18	#include <linux/slab.h>
	19	#include <linux/errno.h>
	20	#include <linux/types.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/uaccess.h>
	23	#include <linux/in.h>
	24	#include <linux/netdevice.h>
	25	#include <linux/etherdevice.h>
	26	#include <linux/phy.h>
	27	#include <linux/ip.h>
	28	#include <linux/tcp.h>
	29	#include <linux/skbuff.h>
	30	#include <linux/mm.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/ethtool.h>
	33	#include <linux/init.h>
	34	#include <linux/delay.h>
	35	#include <linux/io.h>
a32fd63d JC	36	#include <linux/dma-mapping.h>
a32fd63d JC	37	#include <linux/module.h>
504d4721 JC	38
	39	#include <asm/checksum.h>
	40
	41	#include <lantiq_soc.h>
	42	#include <xway_dma.h>
	43	#include <lantiq_platform.h>
	44
	45	#define LTQ_ETOP_MDIO 0x11804
	46	#define MDIO_REQUEST 0x80000000
	47	#define MDIO_READ 0x40000000
	48	#define MDIO_ADDR_MASK 0x1f
	49	#define MDIO_ADDR_OFFSET 0x15
	50	#define MDIO_REG_MASK 0x1f
	51	#define MDIO_REG_OFFSET 0x10
	52	#define MDIO_VAL_MASK 0xffff
	53
	54	#define PPE32_CGEN 0x800
	55	#define LQ_PPE32_ENET_MAC_CFG 0x1840
	56
	57	#define LTQ_ETOP_ENETS0 0x11850
	58	#define LTQ_ETOP_MAC_DA0 0x1186C
	59	#define LTQ_ETOP_MAC_DA1 0x11870
	60	#define LTQ_ETOP_CFG 0x16020
	61	#define LTQ_ETOP_IGPLEN 0x16080
	62
	63	#define MAX_DMA_CHAN 0x8
	64	#define MAX_DMA_CRC_LEN 0x4
	65	#define MAX_DMA_DATA_LEN 0x600
	66
	67	#define ETOP_FTCU BIT(28)
	68	#define ETOP_MII_MASK 0xf
	69	#define ETOP_MII_NORMAL 0xd
	70	#define ETOP_MII_REVERSE 0xe
	71	#define ETOP_PLEN_UNDER 0x40
	72	#define ETOP_CGEN 0x800
	73
	74	/* use 2 static channels for TX/RX */
	75	#define LTQ_ETOP_TX_CHANNEL 1
	76	#define LTQ_ETOP_RX_CHANNEL 6
	77	#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
	78	#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
	79
	80	#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
	81	#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
	82	#define ltq_etop_w32_mask(x, y, z) \
	83	ltq_w32_mask(x, y, ltq_etop_membase + (z))
	84
	85	#define DRV_VERSION "1.0"
	86
	87	static void __iomem *ltq_etop_membase;
	88
	89	struct ltq_etop_chan {
	90	int idx;
	91	int tx_free;
	92	struct net_device *netdev;
	93	struct napi_struct napi;
	94	struct ltq_dma_channel dma;
	95	struct sk_buff *skb[LTQ_DESC_NUM];
	96	};
	97
	98	struct ltq_etop_priv {
	99	struct net_device *netdev;
d1b86507	100	struct platform_device *pdev;
504d4721 JC	101	struct ltq_eth_data *pldata;
	102	struct resource *res;
	103
	104	struct mii_bus *mii_bus;
504d4721 JC	105
	106	struct ltq_etop_chan ch[MAX_DMA_CHAN];
	107	int tx_free[MAX_DMA_CHAN >> 1];
	108
	109	spinlock_t lock;
	110	};
	111
	112	static int
	113	ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
	114	{
c056b734	115	ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
504d4721 JC	116	if (!ch->skb[ch->dma.desc])
	117	return -ENOMEM;
	118	ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
	119	ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
	120	DMA_FROM_DEVICE);
	121	ch->dma.desc_base[ch->dma.desc].addr =
	122	CPHYSADDR(ch->skb[ch->dma.desc]->data);
	123	ch->dma.desc_base[ch->dma.desc].ctl =
	124	LTQ_DMA_OWN \| LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) \|
	125	MAX_DMA_DATA_LEN;
	126	skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
	127	return 0;
	128	}
	129
	130	static void
	131	ltq_etop_hw_receive(struct ltq_etop_chan *ch)
	132	{
	133	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
	134	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	135	struct sk_buff *skb = ch->skb[ch->dma.desc];
	136	int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
	137	unsigned long flags;
	138
	139	spin_lock_irqsave(&priv->lock, flags);
	140	if (ltq_etop_alloc_skb(ch)) {
	141	netdev_err(ch->netdev,
	142	"failed to allocate new rx buffer, stopping DMA\n");
	143	ltq_dma_close(&ch->dma);
	144	}
	145	ch->dma.desc++;
	146	ch->dma.desc %= LTQ_DESC_NUM;
	147	spin_unlock_irqrestore(&priv->lock, flags);
	148
	149	skb_put(skb, len);
504d4721 JC	150	skb->protocol = eth_type_trans(skb, ch->netdev);
	151	netif_receive_skb(skb);
	152	}
	153
	154	static int
	155	ltq_etop_poll_rx(struct napi_struct *napi, int budget)
	156	{
	157	struct ltq_etop_chan *ch = container_of(napi,
	158	struct ltq_etop_chan, napi);
6ad20165	159	int work_done = 0;
504d4721	160
6ad20165	161	while (work_done < budget) {
504d4721 JC	162	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
504d4721 JC	163
6ad20165 ED	164	if ((desc->ctl & (LTQ_DMA_OWN \| LTQ_DMA_C)) != LTQ_DMA_C)
	165	break;
	166	ltq_etop_hw_receive(ch);
	167	work_done++;
504d4721	168	}
6ad20165 ED	169	if (work_done < budget) {
6ad20165 ED	170	napi_complete_done(&ch->napi, work_done);
504d4721 JC	171	ltq_dma_ack_irq(&ch->dma);
504d4721 JC	172	}
6ad20165	173	return work_done;
504d4721 JC	174	}
	175
	176	static int
	177	ltq_etop_poll_tx(struct napi_struct *napi, int budget)
	178	{
	179	struct ltq_etop_chan *ch =
	180	container_of(napi, struct ltq_etop_chan, napi);
	181	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
	182	struct netdev_queue *txq =
	183	netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
	184	unsigned long flags;
	185
	186	spin_lock_irqsave(&priv->lock, flags);
	187	while ((ch->dma.desc_base[ch->tx_free].ctl &
	188	(LTQ_DMA_OWN \| LTQ_DMA_C)) == LTQ_DMA_C) {
	189	dev_kfree_skb_any(ch->skb[ch->tx_free]);
	190	ch->skb[ch->tx_free] = NULL;
	191	memset(&ch->dma.desc_base[ch->tx_free], 0,
	192	sizeof(struct ltq_dma_desc));
	193	ch->tx_free++;
	194	ch->tx_free %= LTQ_DESC_NUM;
	195	}
	196	spin_unlock_irqrestore(&priv->lock, flags);
	197
	198	if (netif_tx_queue_stopped(txq))
	199	netif_tx_start_queue(txq);
	200	napi_complete(&ch->napi);
	201	ltq_dma_ack_irq(&ch->dma);
	202	return 1;
	203	}
	204
	205	static irqreturn_t
	206	ltq_etop_dma_irq(int irq, void *_priv)
	207	{
	208	struct ltq_etop_priv *priv = _priv;
	209	int ch = irq - LTQ_DMA_CH0_INT;
	210
	211	napi_schedule(&priv->ch[ch].napi);
	212	return IRQ_HANDLED;
	213	}
	214
	215	static void
	216	ltq_etop_free_channel(struct net_device dev, struct ltq_etop_chan ch)
	217	{
	218	struct ltq_etop_priv *priv = netdev_priv(dev);
	219
	220	ltq_dma_free(&ch->dma);
	221	if (ch->dma.irq)
	222	free_irq(ch->dma.irq, priv);
	223	if (IS_RX(ch->idx)) {
	224	int desc;
	225	for (desc = 0; desc < LTQ_DESC_NUM; desc++)
	226	dev_kfree_skb_any(ch->skb[ch->dma.desc]);
	227	}
	228	}
	229
	230	static void
	231	ltq_etop_hw_exit(struct net_device *dev)
	232	{
	233	struct ltq_etop_priv *priv = netdev_priv(dev);
	234	int i;
	235
	236	ltq_pmu_disable(PMU_PPE);
	237	for (i = 0; i < MAX_DMA_CHAN; i++)
238	if (IS_TX(i) \|\| IS_RX(i))
239	ltq_etop_free_channel(dev, &priv->ch[i]);
240	}
241
242	static int
243	ltq_etop_hw_init(struct net_device *dev)
244	{
245	struct ltq_etop_priv *priv = netdev_priv(dev);
246	int i;
247
248	ltq_pmu_enable(PMU_PPE);
249
250	switch (priv->pldata->mii_mode) {
251	case PHY_INTERFACE_MODE_RMII:
252	ltq_etop_w32_mask(ETOP_MII_MASK,
253	ETOP_MII_REVERSE, LTQ_ETOP_CFG);
254	break;
255
256	case PHY_INTERFACE_MODE_MII:
257	ltq_etop_w32_mask(ETOP_MII_MASK,
258	ETOP_MII_NORMAL, LTQ_ETOP_CFG);
259	break;
260
261	default:
262	netdev_err(dev, "unknown mii mode %d\n",
263	priv->pldata->mii_mode);
264	return -ENOTSUPP;
265	}
266
267	/* enable crc generation */
268	ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
269
270	ltq_dma_init_port(DMA_PORT_ETOP);
271
272	for (i = 0; i < MAX_DMA_CHAN; i++) {
273	int irq = LTQ_DMA_CH0_INT + i;
274	struct ltq_etop_chan *ch = &priv->ch[i];
275
276	ch->idx = ch->dma.nr = i;
2d946e5b	277	ch->dma.dev = &priv->pdev->dev;
504d4721 JC	278
	279	if (IS_TX(i)) {
	280	ltq_dma_alloc_tx(&ch->dma);
dddb29e4	281	request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
504d4721 JC	282	} else if (IS_RX(i)) {
	283	ltq_dma_alloc_rx(&ch->dma);
	284	for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
	285	ch->dma.desc++)
	286	if (ltq_etop_alloc_skb(ch))
	287	return -ENOMEM;
	288	ch->dma.desc = 0;
dddb29e4	289	request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
504d4721 JC	290	}
	291	ch->dma.irq = irq;
	292	}
	293	return 0;
	294	}
	295
	296	static void
	297	ltq_etop_get_drvinfo(struct net_device dev, struct ethtool_drvinfo info)
	298	{
7826d43f JP	299	strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
	300	strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
	301	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
504d4721 JC	302	}
504d4721 JC	303
504d4721 JC	304	static const struct ethtool_ops ltq_etop_ethtool_ops = {
504d4721 JC	305	.get_drvinfo = ltq_etop_get_drvinfo,
e3979ce9	306	.nway_reset = phy_ethtool_nway_reset,
5376d95f PR	307	.get_link_ksettings = phy_ethtool_get_link_ksettings,
5376d95f PR	308	.set_link_ksettings = phy_ethtool_set_link_ksettings,
504d4721 JC	309	};
	310
	311	static int
	312	ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
	313	{
	314	u32 val = MDIO_REQUEST \|
	315	((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) \|
	316	((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) \|
	317	phy_data;
	318
	319	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
	320	;
	321	ltq_etop_w32(val, LTQ_ETOP_MDIO);
	322	return 0;
	323	}
	324
	325	static int
	326	ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
	327	{
	328	u32 val = MDIO_REQUEST \| MDIO_READ \|
	329	((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) \|
	330	((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
	331
	332	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
	333	;
	334	ltq_etop_w32(val, LTQ_ETOP_MDIO);
	335	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
	336	;
	337	val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
	338	return val;
	339	}
	340
	341	static void
	342	ltq_etop_mdio_link(struct net_device *dev)
	343	{
	344	/* nothing to do */
	345	}
	346
	347	static int
	348	ltq_etop_mdio_probe(struct net_device *dev)
	349	{
	350	struct ltq_etop_priv *priv = netdev_priv(dev);
2a4fc4ea	351	struct phy_device *phydev;
504d4721	352
2a4fc4ea	353	phydev = phy_find_first(priv->mii_bus);
504d4721 JC	354
	355	if (!phydev) {
	356	netdev_err(dev, "no PHY found\n");
	357	return -ENODEV;
	358	}
	359
84eff6d1	360	phydev = phy_connect(dev, phydev_name(phydev),
f9a8f83b	361	&ltq_etop_mdio_link, priv->pldata->mii_mode);
504d4721 JC	362
	363	if (IS_ERR(phydev)) {
	364	netdev_err(dev, "Could not attach to PHY\n");
	365	return PTR_ERR(phydev);
	366	}
	367
58056c1e AL	368	phy_set_max_speed(phydev, SPEED_100);
58056c1e AL	369
2220943a	370	phy_attached_info(phydev);
504d4721 JC	371
	372	return 0;
	373	}
	374
	375	static int
	376	ltq_etop_mdio_init(struct net_device *dev)
	377	{
	378	struct ltq_etop_priv *priv = netdev_priv(dev);
504d4721 JC	379	int err;
	380
	381	priv->mii_bus = mdiobus_alloc();
	382	if (!priv->mii_bus) {
	383	netdev_err(dev, "failed to allocate mii bus\n");
	384	err = -ENOMEM;
	385	goto err_out;
	386	}
	387
	388	priv->mii_bus->priv = dev;
	389	priv->mii_bus->read = ltq_etop_mdio_rd;
	390	priv->mii_bus->write = ltq_etop_mdio_wr;
	391	priv->mii_bus->name = "ltq_mii";
d1b86507 FF	392	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
d1b86507 FF	393	priv->pdev->name, priv->pdev->id);
504d4721 JC	394	if (mdiobus_register(priv->mii_bus)) {
504d4721 JC	395	err = -ENXIO;
e7f4dc35	396	goto err_out_free_mdiobus;
504d4721 JC	397	}
	398
	399	if (ltq_etop_mdio_probe(dev)) {
	400	err = -ENXIO;
	401	goto err_out_unregister_bus;
	402	}
	403	return 0;
	404
	405	err_out_unregister_bus:
	406	mdiobus_unregister(priv->mii_bus);
504d4721 JC	407	err_out_free_mdiobus:
	408	mdiobus_free(priv->mii_bus);
	409	err_out:
	410	return err;
	411	}
	412
	413	static void
	414	ltq_etop_mdio_cleanup(struct net_device *dev)
	415	{
	416	struct ltq_etop_priv *priv = netdev_priv(dev);
	417
d1e3a356	418	phy_disconnect(dev->phydev);
504d4721	419	mdiobus_unregister(priv->mii_bus);
504d4721 JC	420	mdiobus_free(priv->mii_bus);
	421	}
	422
	423	static int
	424	ltq_etop_open(struct net_device *dev)
	425	{
	426	struct ltq_etop_priv *priv = netdev_priv(dev);
	427	int i;
	428
	429	for (i = 0; i < MAX_DMA_CHAN; i++) {
	430	struct ltq_etop_chan *ch = &priv->ch[i];
	431
	432	if (!IS_TX(i) && (!IS_RX(i)))
	433	continue;
	434	ltq_dma_open(&ch->dma);
	435	napi_enable(&ch->napi);
	436	}
d1e3a356	437	phy_start(dev->phydev);
504d4721 JC	438	netif_tx_start_all_queues(dev);
	439	return 0;
	440	}
	441
	442	static int
	443	ltq_etop_stop(struct net_device *dev)
	444	{
	445	struct ltq_etop_priv *priv = netdev_priv(dev);
	446	int i;
	447
	448	netif_tx_stop_all_queues(dev);
d1e3a356	449	phy_stop(dev->phydev);
504d4721 JC	450	for (i = 0; i < MAX_DMA_CHAN; i++) {
	451	struct ltq_etop_chan *ch = &priv->ch[i];
	452
	453	if (!IS_RX(i) && !IS_TX(i))
	454	continue;
	455	napi_disable(&ch->napi);
	456	ltq_dma_close(&ch->dma);
	457	}
	458	return 0;
	459	}
	460
	461	static int
	462	ltq_etop_tx(struct sk_buff skb, struct net_device dev)
	463	{
	464	int queue = skb_get_queue_mapping(skb);
	465	struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
	466	struct ltq_etop_priv *priv = netdev_priv(dev);
	467	struct ltq_etop_chan *ch = &priv->ch[(queue << 1) \| 1];
	468	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	469	int len;
	470	unsigned long flags;
	471	u32 byte_offset;
	472
	473	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
	474
	475	if ((desc->ctl & (LTQ_DMA_OWN \| LTQ_DMA_C)) \|\| ch->skb[ch->dma.desc]) {
	476	dev_kfree_skb_any(skb);
	477	netdev_err(dev, "tx ring full\n");
	478	netif_tx_stop_queue(txq);
	479	return NETDEV_TX_BUSY;
	480	}
	481
	482	/* dma needs to start on a 16 byte aligned address */
	483	byte_offset = CPHYSADDR(skb->data) % 16;
	484	ch->skb[ch->dma.desc] = skb;
	485
860e9538	486	netif_trans_update(dev);
504d4721 JC	487
	488	spin_lock_irqsave(&priv->lock, flags);
	489	desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
	490	DMA_TO_DEVICE)) - byte_offset;
	491	wmb();
	492	desc->ctl = LTQ_DMA_OWN \| LTQ_DMA_SOP \| LTQ_DMA_EOP \|
	493	LTQ_DMA_TX_OFFSET(byte_offset) \| (len & LTQ_DMA_SIZE_MASK);
	494	ch->dma.desc++;
	495	ch->dma.desc %= LTQ_DESC_NUM;
	496	spin_unlock_irqrestore(&priv->lock, flags);
	497
	498	if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
	499	netif_tx_stop_queue(txq);
	500
	501	return NETDEV_TX_OK;
	502	}
	503
	504	static int
	505	ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
	506	{
a52ad514 JW	507	struct ltq_etop_priv *priv = netdev_priv(dev);
a52ad514 JW	508	unsigned long flags;
504d4721	509
a52ad514	510	dev->mtu = new_mtu;
504d4721	511
a52ad514 JW	512	spin_lock_irqsave(&priv->lock, flags);
	513	ltq_etop_w32((ETOP_PLEN_UNDER << 16) \| new_mtu, LTQ_ETOP_IGPLEN);
	514	spin_unlock_irqrestore(&priv->lock, flags);
	515
	516	return 0;
504d4721 JC	517	}
	518
	519	static int
	520	ltq_etop_ioctl(struct net_device dev, struct ifreq rq, int cmd)
	521	{
504d4721	522	/* TODO: mii-toll reports "No MII transceiver present!." ?!*/
d1e3a356	523	return phy_mii_ioctl(dev->phydev, rq, cmd);
504d4721 JC	524	}
	525
	526	static int
	527	ltq_etop_set_mac_address(struct net_device dev, void p)
	528	{
	529	int ret = eth_mac_addr(dev, p);
	530
	531	if (!ret) {
	532	struct ltq_etop_priv *priv = netdev_priv(dev);
	533	unsigned long flags;
	534
	535	/* store the mac for the unicast filter */
	536	spin_lock_irqsave(&priv->lock, flags);
	537	ltq_etop_w32(((u32 )dev->dev_addr), LTQ_ETOP_MAC_DA0);
	538	ltq_etop_w32(((u16 )&dev->dev_addr[4]) << 16,
	539	LTQ_ETOP_MAC_DA1);
	540	spin_unlock_irqrestore(&priv->lock, flags);
	541	}
	542	return ret;
	543	}
	544
	545	static void
	546	ltq_etop_set_multicast_list(struct net_device *dev)
	547	{
	548	struct ltq_etop_priv *priv = netdev_priv(dev);
	549	unsigned long flags;
	550
	551	/* ensure that the unicast filter is not enabled in promiscious mode */
	552	spin_lock_irqsave(&priv->lock, flags);
	553	if ((dev->flags & IFF_PROMISC) \|\| (dev->flags & IFF_ALLMULTI))
	554	ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
	555	else
	556	ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
	557	spin_unlock_irqrestore(&priv->lock, flags);
	558	}
	559
504d4721 JC	560	static int
	561	ltq_etop_init(struct net_device *dev)
	562	{
	563	struct ltq_etop_priv *priv = netdev_priv(dev);
	564	struct sockaddr mac;
	565	int err;
43aabec5	566	bool random_mac = false;
504d4721	567
504d4721 JC	568	dev->watchdog_timeo = 10 * HZ;
	569	err = ltq_etop_hw_init(dev);
	570	if (err)
	571	goto err_hw;
	572	ltq_etop_change_mtu(dev, 1500);
	573
	574	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
	575	if (!is_valid_ether_addr(mac.sa_data)) {
	576	pr_warn("etop: invalid MAC, using random\n");
7efd26d0	577	eth_random_addr(mac.sa_data);
43aabec5	578	random_mac = true;
504d4721 JC	579	}
	580
	581	err = ltq_etop_set_mac_address(dev, &mac);
	582	if (err)
	583	goto err_netdev;
43aabec5 DK	584
	585	/* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
	586	if (random_mac)
e41b2d7f	587	dev->addr_assign_type = NET_ADDR_RANDOM;
43aabec5	588
504d4721 JC	589	ltq_etop_set_multicast_list(dev);
	590	err = ltq_etop_mdio_init(dev);
	591	if (err)
	592	goto err_netdev;
	593	return 0;
	594
	595	err_netdev:
	596	unregister_netdev(dev);
	597	free_netdev(dev);
	598	err_hw:
	599	ltq_etop_hw_exit(dev);
	600	return err;
	601	}
	602
	603	static void
	604	ltq_etop_tx_timeout(struct net_device *dev)
	605	{
	606	int err;
	607
	608	ltq_etop_hw_exit(dev);
	609	err = ltq_etop_hw_init(dev);
	610	if (err)
	611	goto err_hw;
860e9538	612	netif_trans_update(dev);
504d4721 JC	613	netif_wake_queue(dev);
	614	return;
	615
	616	err_hw:
	617	ltq_etop_hw_exit(dev);
	618	netdev_err(dev, "failed to restart etop after TX timeout\n");
	619	}
	620
	621	static const struct net_device_ops ltq_eth_netdev_ops = {
	622	.ndo_open = ltq_etop_open,
	623	.ndo_stop = ltq_etop_stop,
	624	.ndo_start_xmit = ltq_etop_tx,
	625	.ndo_change_mtu = ltq_etop_change_mtu,
	626	.ndo_do_ioctl = ltq_etop_ioctl,
	627	.ndo_set_mac_address = ltq_etop_set_mac_address,
	628	.ndo_validate_addr = eth_validate_addr,
afc4b13d	629	.ndo_set_rx_mode = ltq_etop_set_multicast_list,
a4ea8a3d	630	.ndo_select_queue = dev_pick_tx_zero,
504d4721 JC	631	.ndo_init = ltq_etop_init,
	632	.ndo_tx_timeout = ltq_etop_tx_timeout,
	633	};
	634
	635	static int __init
	636	ltq_etop_probe(struct platform_device *pdev)
	637	{
	638	struct net_device *dev;
	639	struct ltq_etop_priv *priv;
	640	struct resource *res;
	641	int err;
	642	int i;
	643
	644	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	645	if (!res) {
	646	dev_err(&pdev->dev, "failed to get etop resource\n");
	647	err = -ENOENT;
	648	goto err_out;
	649	}
	650
	651	res = devm_request_mem_region(&pdev->dev, res->start,
	652	resource_size(res), dev_name(&pdev->dev));
	653	if (!res) {
	654	dev_err(&pdev->dev, "failed to request etop resource\n");
	655	err = -EBUSY;
	656	goto err_out;
	657	}
	658
	659	ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
	660	res->start, resource_size(res));
	661	if (!ltq_etop_membase) {
	662	dev_err(&pdev->dev, "failed to remap etop engine %d\n",
	663	pdev->id);
	664	err = -ENOMEM;
	665	goto err_out;
	666	}
	667
	668	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
41de8d4c JP	669	if (!dev) {
	670	err = -ENOMEM;
	671	goto err_out;
	672	}
504d4721 JC	673	strcpy(dev->name, "eth%d");
	674	dev->netdev_ops = &ltq_eth_netdev_ops;
	675	dev->ethtool_ops = &ltq_etop_ethtool_ops;
	676	priv = netdev_priv(dev);
	677	priv->res = res;
d1b86507	678	priv->pdev = pdev;
504d4721 JC	679	priv->pldata = dev_get_platdata(&pdev->dev);
	680	priv->netdev = dev;
	681	spin_lock_init(&priv->lock);
9cecb138	682	SET_NETDEV_DEV(dev, &pdev->dev);
504d4721 JC	683
	684	for (i = 0; i < MAX_DMA_CHAN; i++) {
	685	if (IS_TX(i))
	686	netif_napi_add(dev, &priv->ch[i].napi,
	687	ltq_etop_poll_tx, 8);
	688	else if (IS_RX(i))
	689	netif_napi_add(dev, &priv->ch[i].napi,
	690	ltq_etop_poll_rx, 32);
	691	priv->ch[i].netdev = dev;
	692	}
	693
	694	err = register_netdev(dev);
	695	if (err)
	696	goto err_free;
	697
	698	platform_set_drvdata(pdev, dev);
	699	return 0;
	700
	701	err_free:
cb0e51d8	702	free_netdev(dev);
504d4721 JC	703	err_out:
	704	return err;
	705	}
	706
a0a4efed	707	static int
504d4721 JC	708	ltq_etop_remove(struct platform_device *pdev)
	709	{
	710	struct net_device *dev = platform_get_drvdata(pdev);
	711
	712	if (dev) {
	713	netif_tx_stop_all_queues(dev);
	714	ltq_etop_hw_exit(dev);
	715	ltq_etop_mdio_cleanup(dev);
	716	unregister_netdev(dev);
	717	}
	718	return 0;
	719	}
	720
	721	static struct platform_driver ltq_mii_driver = {
a0a4efed	722	.remove = ltq_etop_remove,
504d4721 JC	723	.driver = {
504d4721 JC	724	.name = "ltq_etop",
504d4721 JC	725	},
	726	};
	727
	728	int __init
	729	init_ltq_etop(void)
	730	{
	731	int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
	732
	733	if (ret)
772301b6	734	pr_err("ltq_etop: Error registering platform driver!");
504d4721 JC	735	return ret;
	736	}
	737
	738	static void __exit
	739	exit_ltq_etop(void)
	740	{
	741	platform_driver_unregister(&ltq_mii_driver);
	742	}
	743
	744	module_init(init_ltq_etop);
	745	module_exit(exit_ltq_etop);
	746
	747	MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
	748	MODULE_DESCRIPTION("Lantiq SoC ETOP");
	749	MODULE_LICENSE("GPL");