[linux-2.6-block.git] / drivers / net / ethernet / lantiq_etop.c

/*
 *   This program is free software; you can redistribute it and/or modify it
 *   under the terms of the GNU General Public License version 2 as published
 *   by the Free Software Foundation.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 */

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/uaccess.h>
#include <linux/in.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/phy.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/mm.h>
#include <linux/platform_device.h>
#include <linux/ethtool.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>

#include <asm/checksum.h>

#include <lantiq_soc.h>
#include <xway_dma.h>
#include <lantiq_platform.h>

#define LTQ_ETOP_MDIO		0x11804
#define MDIO_REQUEST		0x80000000
#define MDIO_READ		0x40000000
#define MDIO_ADDR_MASK		0x1f
#define MDIO_ADDR_OFFSET	0x15
#define MDIO_REG_MASK		0x1f
#define MDIO_REG_OFFSET		0x10
#define MDIO_VAL_MASK		0xffff

#define PPE32_CGEN		0x800
#define LQ_PPE32_ENET_MAC_CFG	0x1840

#define LTQ_ETOP_ENETS0		0x11850
#define LTQ_ETOP_MAC_DA0	0x1186C
#define LTQ_ETOP_MAC_DA1	0x11870
#define LTQ_ETOP_CFG		0x16020
#define LTQ_ETOP_IGPLEN		0x16080

#define MAX_DMA_CHAN		0x8
#define MAX_DMA_CRC_LEN		0x4
#define MAX_DMA_DATA_LEN	0x600

#define ETOP_FTCU		BIT(28)
#define ETOP_MII_MASK		0xf
#define ETOP_MII_NORMAL		0xd
#define ETOP_MII_REVERSE	0xe
#define ETOP_PLEN_UNDER		0x40
#define ETOP_CGEN		0x800

/* use 2 static channels for TX/RX */
#define LTQ_ETOP_TX_CHANNEL	1
#define LTQ_ETOP_RX_CHANNEL	6
#define IS_TX(x)		(x == LTQ_ETOP_TX_CHANNEL)
#define IS_RX(x)		(x == LTQ_ETOP_RX_CHANNEL)

#define ltq_etop_r32(x)		ltq_r32(ltq_etop_membase + (x))
#define ltq_etop_w32(x, y)	ltq_w32(x, ltq_etop_membase + (y))
#define ltq_etop_w32_mask(x, y, z)	\
		ltq_w32_mask(x, y, ltq_etop_membase + (z))

#define DRV_VERSION	"1.0"

static void __iomem *ltq_etop_membase;

struct ltq_etop_chan {
	int idx;
	int tx_free;
	struct net_device *netdev;
	struct napi_struct napi;
	struct ltq_dma_channel dma;
	struct sk_buff *skb[LTQ_DESC_NUM];
};

struct ltq_etop_priv {
	struct net_device *netdev;
	struct platform_device *pdev;
	struct ltq_eth_data *pldata;
	struct resource *res;

	struct mii_bus *mii_bus;

	struct ltq_etop_chan ch[MAX_DMA_CHAN];
	int tx_free[MAX_DMA_CHAN >> 1];

	spinlock_t lock;
};

static int
ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
{
	ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
	if (!ch->skb[ch->dma.desc])
		return -ENOMEM;
	ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
		ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
		DMA_FROM_DEVICE);
	ch->dma.desc_base[ch->dma.desc].addr =
		CPHYSADDR(ch->skb[ch->dma.desc]->data);
	ch->dma.desc_base[ch->dma.desc].ctl =
		LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
		MAX_DMA_DATA_LEN;
	skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
	return 0;
}

static void
ltq_etop_hw_receive(struct ltq_etop_chan *ch)
{
	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	struct sk_buff *skb = ch->skb[ch->dma.desc];
	int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	if (ltq_etop_alloc_skb(ch)) {
		netdev_err(ch->netdev,
			"failed to allocate new rx buffer, stopping DMA\n");
		ltq_dma_close(&ch->dma);
	}
	ch->dma.desc++;
	ch->dma.desc %= LTQ_DESC_NUM;
	spin_unlock_irqrestore(&priv->lock, flags);

	skb_put(skb, len);
	skb->protocol = eth_type_trans(skb, ch->netdev);
	netif_receive_skb(skb);
}

static int
ltq_etop_poll_rx(struct napi_struct *napi, int budget)
{
	struct ltq_etop_chan *ch = container_of(napi,
				struct ltq_etop_chan, napi);
	int rx = 0;
	int complete = 0;

	while ((rx < budget) && !complete) {
		struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];

		if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
			ltq_etop_hw_receive(ch);
			rx++;
		} else {
			complete = 1;
		}
	}
	if (complete || !rx) {
		napi_complete(&ch->napi);
		ltq_dma_ack_irq(&ch->dma);
	}
	return rx;
}

static int
ltq_etop_poll_tx(struct napi_struct *napi, int budget)
{
	struct ltq_etop_chan *ch =
		container_of(napi, struct ltq_etop_chan, napi);
	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
	struct netdev_queue *txq =
		netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	while ((ch->dma.desc_base[ch->tx_free].ctl &
			(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
		dev_kfree_skb_any(ch->skb[ch->tx_free]);
		ch->skb[ch->tx_free] = NULL;
		memset(&ch->dma.desc_base[ch->tx_free], 0,
			sizeof(struct ltq_dma_desc));
		ch->tx_free++;
		ch->tx_free %= LTQ_DESC_NUM;
	}
	spin_unlock_irqrestore(&priv->lock, flags);

	if (netif_tx_queue_stopped(txq))
		netif_tx_start_queue(txq);
	napi_complete(&ch->napi);
	ltq_dma_ack_irq(&ch->dma);
	return 1;
}

static irqreturn_t
ltq_etop_dma_irq(int irq, void *_priv)
{
	struct ltq_etop_priv *priv = _priv;
	int ch = irq - LTQ_DMA_CH0_INT;

	napi_schedule(&priv->ch[ch].napi);
	return IRQ_HANDLED;
}

static void
ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);

	ltq_dma_free(&ch->dma);
	if (ch->dma.irq)
		free_irq(ch->dma.irq, priv);
	if (IS_RX(ch->idx)) {
		int desc;
		for (desc = 0; desc < LTQ_DESC_NUM; desc++)
			dev_kfree_skb_any(ch->skb[ch->dma.desc]);
	}
}

static void
ltq_etop_hw_exit(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	int i;

	ltq_pmu_disable(PMU_PPE);
	for (i = 0; i < MAX_DMA_CHAN; i++)
		if (IS_TX(i) || IS_RX(i))
			ltq_etop_free_channel(dev, &priv->ch[i]);
}

static int
ltq_etop_hw_init(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	int i;

	ltq_pmu_enable(PMU_PPE);

	switch (priv->pldata->mii_mode) {
	case PHY_INTERFACE_MODE_RMII:
		ltq_etop_w32_mask(ETOP_MII_MASK,
			ETOP_MII_REVERSE, LTQ_ETOP_CFG);
		break;

	case PHY_INTERFACE_MODE_MII:
		ltq_etop_w32_mask(ETOP_MII_MASK,
			ETOP_MII_NORMAL, LTQ_ETOP_CFG);
		break;

	default:
		netdev_err(dev, "unknown mii mode %d\n",
			priv->pldata->mii_mode);
		return -ENOTSUPP;
	}

	/* enable crc generation */
	ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);

	ltq_dma_init_port(DMA_PORT_ETOP);

	for (i = 0; i < MAX_DMA_CHAN; i++) {
		int irq = LTQ_DMA_CH0_INT + i;
		struct ltq_etop_chan *ch = &priv->ch[i];

		ch->idx = ch->dma.nr = i;

		if (IS_TX(i)) {
			ltq_dma_alloc_tx(&ch->dma);
			request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
		} else if (IS_RX(i)) {
			ltq_dma_alloc_rx(&ch->dma);
			for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
					ch->dma.desc++)
				if (ltq_etop_alloc_skb(ch))
					return -ENOMEM;
			ch->dma.desc = 0;
			request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
		}
		ch->dma.irq = irq;
	}
	return 0;
}

static void
ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
	strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
	strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
}

static const struct ethtool_ops ltq_etop_ethtool_ops = {
	.get_drvinfo = ltq_etop_get_drvinfo,
	.nway_reset = phy_ethtool_nway_reset,
	.get_link_ksettings = phy_ethtool_get_link_ksettings,
	.set_link_ksettings = phy_ethtool_set_link_ksettings,
};

static int
ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
{
	u32 val = MDIO_REQUEST |
		((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
		phy_data;

	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
		;
	ltq_etop_w32(val, LTQ_ETOP_MDIO);
	return 0;
}

static int
ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
{
	u32 val = MDIO_REQUEST | MDIO_READ |
		((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);

	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
		;
	ltq_etop_w32(val, LTQ_ETOP_MDIO);
	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
		;
	val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
	return val;
}

static void
ltq_etop_mdio_link(struct net_device *dev)
{
	/* nothing to do  */
}

static int
ltq_etop_mdio_probe(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	struct phy_device *phydev;

	phydev = phy_find_first(priv->mii_bus);

	if (!phydev) {
		netdev_err(dev, "no PHY found\n");
		return -ENODEV;
	}

	phydev = phy_connect(dev, phydev_name(phydev),
			     &ltq_etop_mdio_link, priv->pldata->mii_mode);

	if (IS_ERR(phydev)) {
		netdev_err(dev, "Could not attach to PHY\n");
		return PTR_ERR(phydev);
	}

	phydev->supported &= (SUPPORTED_10baseT_Half
			      | SUPPORTED_10baseT_Full
			      | SUPPORTED_100baseT_Half
			      | SUPPORTED_100baseT_Full
			      | SUPPORTED_Autoneg
			      | SUPPORTED_MII
			      | SUPPORTED_TP);

	phydev->advertising = phydev->supported;
	phy_attached_info(phydev);

	return 0;
}

static int
ltq_etop_mdio_init(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	int err;

	priv->mii_bus = mdiobus_alloc();
	if (!priv->mii_bus) {
		netdev_err(dev, "failed to allocate mii bus\n");
		err = -ENOMEM;
		goto err_out;
	}

	priv->mii_bus->priv = dev;
	priv->mii_bus->read = ltq_etop_mdio_rd;
	priv->mii_bus->write = ltq_etop_mdio_wr;
	priv->mii_bus->name = "ltq_mii";
	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
		priv->pdev->name, priv->pdev->id);
	if (mdiobus_register(priv->mii_bus)) {
		err = -ENXIO;
		goto err_out_free_mdiobus;
	}

	if (ltq_etop_mdio_probe(dev)) {
		err = -ENXIO;
		goto err_out_unregister_bus;
	}
	return 0;

err_out_unregister_bus:
	mdiobus_unregister(priv->mii_bus);
err_out_free_mdiobus:
	mdiobus_free(priv->mii_bus);
err_out:
	return err;
}

static void
ltq_etop_mdio_cleanup(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);

	phy_disconnect(dev->phydev);
	mdiobus_unregister(priv->mii_bus);
	mdiobus_free(priv->mii_bus);
}

static int
ltq_etop_open(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	int i;

	for (i = 0; i < MAX_DMA_CHAN; i++) {
		struct ltq_etop_chan *ch = &priv->ch[i];

		if (!IS_TX(i) && (!IS_RX(i)))
			continue;
		ltq_dma_open(&ch->dma);
		napi_enable(&ch->napi);
	}
	phy_start(dev->phydev);
	netif_tx_start_all_queues(dev);
	return 0;
}

static int
ltq_etop_stop(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	int i;

	netif_tx_stop_all_queues(dev);
	phy_stop(dev->phydev);
	for (i = 0; i < MAX_DMA_CHAN; i++) {
		struct ltq_etop_chan *ch = &priv->ch[i];

		if (!IS_RX(i) && !IS_TX(i))
			continue;
		napi_disable(&ch->napi);
		ltq_dma_close(&ch->dma);
	}
	return 0;
}

static int
ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
{
	int queue = skb_get_queue_mapping(skb);
	struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
	struct ltq_etop_priv *priv = netdev_priv(dev);
	struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	int len;
	unsigned long flags;
	u32 byte_offset;

	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;

	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
		dev_kfree_skb_any(skb);
		netdev_err(dev, "tx ring full\n");
		netif_tx_stop_queue(txq);
		return NETDEV_TX_BUSY;
	}

	/* dma needs to start on a 16 byte aligned address */
	byte_offset = CPHYSADDR(skb->data) % 16;
	ch->skb[ch->dma.desc] = skb;

	netif_trans_update(dev);

	spin_lock_irqsave(&priv->lock, flags);
	desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
						DMA_TO_DEVICE)) - byte_offset;
	wmb();
	desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
		LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
	ch->dma.desc++;
	ch->dma.desc %= LTQ_DESC_NUM;
	spin_unlock_irqrestore(&priv->lock, flags);

	if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
		netif_tx_stop_queue(txq);

	return NETDEV_TX_OK;
}

static int
ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	unsigned long flags;

	dev->mtu = new_mtu;

	spin_lock_irqsave(&priv->lock, flags);
	ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
	spin_unlock_irqrestore(&priv->lock, flags);

	return 0;
}

static int
ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
	/* TODO: mii-toll reports "No MII transceiver present!." ?!*/
	return phy_mii_ioctl(dev->phydev, rq, cmd);
}

static int
ltq_etop_set_mac_address(struct net_device *dev, void *p)
{
	int ret = eth_mac_addr(dev, p);

	if (!ret) {
		struct ltq_etop_priv *priv = netdev_priv(dev);
		unsigned long flags;

		/* store the mac for the unicast filter */
		spin_lock_irqsave(&priv->lock, flags);
		ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
		ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
			LTQ_ETOP_MAC_DA1);
		spin_unlock_irqrestore(&priv->lock, flags);
	}
	return ret;
}

static void
ltq_etop_set_multicast_list(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	unsigned long flags;

	/* ensure that the unicast filter is not enabled in promiscious mode */
	spin_lock_irqsave(&priv->lock, flags);
	if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
		ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
	else
		ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static u16
ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb,
		      void *accel_priv, select_queue_fallback_t fallback)
{
	/* we are currently only using the first queue */
	return 0;
}

static int
ltq_etop_init(struct net_device *dev)
{
	struct ltq_etop_priv *priv = netdev_priv(dev);
	struct sockaddr mac;
	int err;
	bool random_mac = false;

	dev->watchdog_timeo = 10 * HZ;
	err = ltq_etop_hw_init(dev);
	if (err)
		goto err_hw;
	ltq_etop_change_mtu(dev, 1500);

	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
	if (!is_valid_ether_addr(mac.sa_data)) {
		pr_warn("etop: invalid MAC, using random\n");
		eth_random_addr(mac.sa_data);
		random_mac = true;
	}

	err = ltq_etop_set_mac_address(dev, &mac);
	if (err)
		goto err_netdev;

	/* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
	if (random_mac)
		dev->addr_assign_type = NET_ADDR_RANDOM;

	ltq_etop_set_multicast_list(dev);
	err = ltq_etop_mdio_init(dev);
	if (err)
		goto err_netdev;
	return 0;

err_netdev:
	unregister_netdev(dev);
	free_netdev(dev);
err_hw:
	ltq_etop_hw_exit(dev);
	return err;
}

static void
ltq_etop_tx_timeout(struct net_device *dev)
{
	int err;

	ltq_etop_hw_exit(dev);
	err = ltq_etop_hw_init(dev);
	if (err)
		goto err_hw;
	netif_trans_update(dev);
	netif_wake_queue(dev);
	return;

err_hw:
	ltq_etop_hw_exit(dev);
	netdev_err(dev, "failed to restart etop after TX timeout\n");
}

static const struct net_device_ops ltq_eth_netdev_ops = {
	.ndo_open = ltq_etop_open,
	.ndo_stop = ltq_etop_stop,
	.ndo_start_xmit = ltq_etop_tx,
	.ndo_change_mtu = ltq_etop_change_mtu,
	.ndo_do_ioctl = ltq_etop_ioctl,
	.ndo_set_mac_address = ltq_etop_set_mac_address,
	.ndo_validate_addr = eth_validate_addr,
	.ndo_set_rx_mode = ltq_etop_set_multicast_list,
	.ndo_select_queue = ltq_etop_select_queue,
	.ndo_init = ltq_etop_init,
	.ndo_tx_timeout = ltq_etop_tx_timeout,
};

static int __init
ltq_etop_probe(struct platform_device *pdev)
{
	struct net_device *dev;
	struct ltq_etop_priv *priv;
	struct resource *res;
	int err;
	int i;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "failed to get etop resource\n");
		err = -ENOENT;
		goto err_out;
	}

	res = devm_request_mem_region(&pdev->dev, res->start,
		resource_size(res), dev_name(&pdev->dev));
	if (!res) {
		dev_err(&pdev->dev, "failed to request etop resource\n");
		err = -EBUSY;
		goto err_out;
	}

	ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
		res->start, resource_size(res));
	if (!ltq_etop_membase) {
		dev_err(&pdev->dev, "failed to remap etop engine %d\n",
			pdev->id);
		err = -ENOMEM;
		goto err_out;
	}

	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
	if (!dev) {
		err = -ENOMEM;
		goto err_out;
	}
	strcpy(dev->name, "eth%d");
	dev->netdev_ops = &ltq_eth_netdev_ops;
	dev->ethtool_ops = &ltq_etop_ethtool_ops;
	priv = netdev_priv(dev);
	priv->res = res;
	priv->pdev = pdev;
	priv->pldata = dev_get_platdata(&pdev->dev);
	priv->netdev = dev;
	spin_lock_init(&priv->lock);
	SET_NETDEV_DEV(dev, &pdev->dev);

	for (i = 0; i < MAX_DMA_CHAN; i++) {
		if (IS_TX(i))
			netif_napi_add(dev, &priv->ch[i].napi,
				ltq_etop_poll_tx, 8);
		else if (IS_RX(i))
			netif_napi_add(dev, &priv->ch[i].napi,
				ltq_etop_poll_rx, 32);
		priv->ch[i].netdev = dev;
	}

	err = register_netdev(dev);
	if (err)
		goto err_free;

	platform_set_drvdata(pdev, dev);
	return 0;

err_free:
	free_netdev(dev);
err_out:
	return err;
}

static int
ltq_etop_remove(struct platform_device *pdev)
{
	struct net_device *dev = platform_get_drvdata(pdev);

	if (dev) {
		netif_tx_stop_all_queues(dev);
		ltq_etop_hw_exit(dev);
		ltq_etop_mdio_cleanup(dev);
		unregister_netdev(dev);
	}
	return 0;
}

static struct platform_driver ltq_mii_driver = {
	.remove = ltq_etop_remove,
	.driver = {
		.name = "ltq_etop",
	},
};

int __init
init_ltq_etop(void)
{
	int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);

	if (ret)
		pr_err("ltq_etop: Error registering platform driver!");
	return ret;
}

static void __exit
exit_ltq_etop(void)
{
	platform_driver_unregister(&ltq_mii_driver);
}

module_init(init_ltq_etop);
module_exit(exit_ltq_etop);

MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("Lantiq SoC ETOP");
MODULE_LICENSE("GPL");
Commit	Line	Data
504d4721 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
0ab75ae8	12	* along with this program; if not, see <http://www.gnu.org/licenses/>.
504d4721 JC	13	*
	14	* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
	15	*/
	16
	17	#include <linux/kernel.h>
	18	#include <linux/slab.h>
	19	#include <linux/errno.h>
	20	#include <linux/types.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/uaccess.h>
	23	#include <linux/in.h>
	24	#include <linux/netdevice.h>
	25	#include <linux/etherdevice.h>
	26	#include <linux/phy.h>
	27	#include <linux/ip.h>
	28	#include <linux/tcp.h>
	29	#include <linux/skbuff.h>
	30	#include <linux/mm.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/ethtool.h>
	33	#include <linux/init.h>
	34	#include <linux/delay.h>
	35	#include <linux/io.h>
a32fd63d JC	36	#include <linux/dma-mapping.h>
a32fd63d JC	37	#include <linux/module.h>
504d4721 JC	38
	39	#include <asm/checksum.h>
	40
	41	#include <lantiq_soc.h>
	42	#include <xway_dma.h>
	43	#include <lantiq_platform.h>
	44
	45	#define LTQ_ETOP_MDIO 0x11804
	46	#define MDIO_REQUEST 0x80000000
	47	#define MDIO_READ 0x40000000
	48	#define MDIO_ADDR_MASK 0x1f
	49	#define MDIO_ADDR_OFFSET 0x15
	50	#define MDIO_REG_MASK 0x1f
	51	#define MDIO_REG_OFFSET 0x10
	52	#define MDIO_VAL_MASK 0xffff
	53
	54	#define PPE32_CGEN 0x800
	55	#define LQ_PPE32_ENET_MAC_CFG 0x1840
	56
	57	#define LTQ_ETOP_ENETS0 0x11850
	58	#define LTQ_ETOP_MAC_DA0 0x1186C
	59	#define LTQ_ETOP_MAC_DA1 0x11870
	60	#define LTQ_ETOP_CFG 0x16020
	61	#define LTQ_ETOP_IGPLEN 0x16080
	62
	63	#define MAX_DMA_CHAN 0x8
	64	#define MAX_DMA_CRC_LEN 0x4
	65	#define MAX_DMA_DATA_LEN 0x600
	66
	67	#define ETOP_FTCU BIT(28)
	68	#define ETOP_MII_MASK 0xf
	69	#define ETOP_MII_NORMAL 0xd
	70	#define ETOP_MII_REVERSE 0xe
	71	#define ETOP_PLEN_UNDER 0x40
	72	#define ETOP_CGEN 0x800
	73
	74	/* use 2 static channels for TX/RX */
	75	#define LTQ_ETOP_TX_CHANNEL 1
	76	#define LTQ_ETOP_RX_CHANNEL 6
	77	#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
	78	#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
	79
	80	#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
	81	#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
	82	#define ltq_etop_w32_mask(x, y, z) \
	83	ltq_w32_mask(x, y, ltq_etop_membase + (z))
	84
	85	#define DRV_VERSION "1.0"
	86
	87	static void __iomem *ltq_etop_membase;
	88
	89	struct ltq_etop_chan {
	90	int idx;
	91	int tx_free;
	92	struct net_device *netdev;
	93	struct napi_struct napi;
	94	struct ltq_dma_channel dma;
	95	struct sk_buff *skb[LTQ_DESC_NUM];
	96	};
	97
	98	struct ltq_etop_priv {
	99	struct net_device *netdev;
d1b86507	100	struct platform_device *pdev;
504d4721 JC	101	struct ltq_eth_data *pldata;
	102	struct resource *res;
	103
	104	struct mii_bus *mii_bus;
504d4721 JC	105
	106	struct ltq_etop_chan ch[MAX_DMA_CHAN];
	107	int tx_free[MAX_DMA_CHAN >> 1];
	108
	109	spinlock_t lock;
	110	};
	111
	112	static int
	113	ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
	114	{
c056b734	115	ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
504d4721 JC	116	if (!ch->skb[ch->dma.desc])
	117	return -ENOMEM;
	118	ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
	119	ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
	120	DMA_FROM_DEVICE);
	121	ch->dma.desc_base[ch->dma.desc].addr =
	122	CPHYSADDR(ch->skb[ch->dma.desc]->data);
	123	ch->dma.desc_base[ch->dma.desc].ctl =
	124	LTQ_DMA_OWN \| LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) \|
	125	MAX_DMA_DATA_LEN;
	126	skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
	127	return 0;
	128	}
	129
	130	static void
	131	ltq_etop_hw_receive(struct ltq_etop_chan *ch)
	132	{
	133	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
	134	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	135	struct sk_buff *skb = ch->skb[ch->dma.desc];
	136	int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
	137	unsigned long flags;
	138
	139	spin_lock_irqsave(&priv->lock, flags);
	140	if (ltq_etop_alloc_skb(ch)) {
	141	netdev_err(ch->netdev,
	142	"failed to allocate new rx buffer, stopping DMA\n");
	143	ltq_dma_close(&ch->dma);
	144	}
	145	ch->dma.desc++;
	146	ch->dma.desc %= LTQ_DESC_NUM;
	147	spin_unlock_irqrestore(&priv->lock, flags);
	148
	149	skb_put(skb, len);
504d4721 JC	150	skb->protocol = eth_type_trans(skb, ch->netdev);
	151	netif_receive_skb(skb);
	152	}
	153
	154	static int
	155	ltq_etop_poll_rx(struct napi_struct *napi, int budget)
	156	{
	157	struct ltq_etop_chan *ch = container_of(napi,
	158	struct ltq_etop_chan, napi);
	159	int rx = 0;
	160	int complete = 0;
	161
	162	while ((rx < budget) && !complete) {
	163	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	164
	165	if ((desc->ctl & (LTQ_DMA_OWN \| LTQ_DMA_C)) == LTQ_DMA_C) {
	166	ltq_etop_hw_receive(ch);
	167	rx++;
	168	} else {
	169	complete = 1;
	170	}
	171	}
	172	if (complete \|\| !rx) {
	173	napi_complete(&ch->napi);
	174	ltq_dma_ack_irq(&ch->dma);
	175	}
	176	return rx;
	177	}
	178
	179	static int
	180	ltq_etop_poll_tx(struct napi_struct *napi, int budget)
	181	{
	182	struct ltq_etop_chan *ch =
	183	container_of(napi, struct ltq_etop_chan, napi);
	184	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
	185	struct netdev_queue *txq =
	186	netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
	187	unsigned long flags;
	188
	189	spin_lock_irqsave(&priv->lock, flags);
	190	while ((ch->dma.desc_base[ch->tx_free].ctl &
	191	(LTQ_DMA_OWN \| LTQ_DMA_C)) == LTQ_DMA_C) {
	192	dev_kfree_skb_any(ch->skb[ch->tx_free]);
	193	ch->skb[ch->tx_free] = NULL;
	194	memset(&ch->dma.desc_base[ch->tx_free], 0,
	195	sizeof(struct ltq_dma_desc));
	196	ch->tx_free++;
	197	ch->tx_free %= LTQ_DESC_NUM;
	198	}
	199	spin_unlock_irqrestore(&priv->lock, flags);
	200
	201	if (netif_tx_queue_stopped(txq))
	202	netif_tx_start_queue(txq);
	203	napi_complete(&ch->napi);
	204	ltq_dma_ack_irq(&ch->dma);
	205	return 1;
	206	}
	207
	208	static irqreturn_t
	209	ltq_etop_dma_irq(int irq, void *_priv)
	210	{
	211	struct ltq_etop_priv *priv = _priv;
	212	int ch = irq - LTQ_DMA_CH0_INT;
	213
214	napi_schedule(&priv->ch[ch].napi);
215	return IRQ_HANDLED;
216	}
217
218	static void
219	ltq_etop_free_channel(struct net_device dev, struct ltq_etop_chan ch)
220	{
221	struct ltq_etop_priv *priv = netdev_priv(dev);
222
223	ltq_dma_free(&ch->dma);
224	if (ch->dma.irq)
225	free_irq(ch->dma.irq, priv);
226	if (IS_RX(ch->idx)) {
227	int desc;
228	for (desc = 0; desc < LTQ_DESC_NUM; desc++)
229	dev_kfree_skb_any(ch->skb[ch->dma.desc]);
230	}
231	}
232
233	static void
234	ltq_etop_hw_exit(struct net_device *dev)
235	{
236	struct ltq_etop_priv *priv = netdev_priv(dev);
237	int i;
238
239	ltq_pmu_disable(PMU_PPE);
240	for (i = 0; i < MAX_DMA_CHAN; i++)
241	if (IS_TX(i) \|\| IS_RX(i))
242	ltq_etop_free_channel(dev, &priv->ch[i]);
243	}
244
245	static int
246	ltq_etop_hw_init(struct net_device *dev)
247	{
248	struct ltq_etop_priv *priv = netdev_priv(dev);
249	int i;
250
251	ltq_pmu_enable(PMU_PPE);
252
253	switch (priv->pldata->mii_mode) {
254	case PHY_INTERFACE_MODE_RMII:
255	ltq_etop_w32_mask(ETOP_MII_MASK,
256	ETOP_MII_REVERSE, LTQ_ETOP_CFG);
257	break;
258
259	case PHY_INTERFACE_MODE_MII:
260	ltq_etop_w32_mask(ETOP_MII_MASK,
261	ETOP_MII_NORMAL, LTQ_ETOP_CFG);
262	break;
263
264	default:
265	netdev_err(dev, "unknown mii mode %d\n",
266	priv->pldata->mii_mode);
267	return -ENOTSUPP;
268	}
269
270	/* enable crc generation */
271	ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
272
273	ltq_dma_init_port(DMA_PORT_ETOP);
274
275	for (i = 0; i < MAX_DMA_CHAN; i++) {
276	int irq = LTQ_DMA_CH0_INT + i;
277	struct ltq_etop_chan *ch = &priv->ch[i];
278
279	ch->idx = ch->dma.nr = i;
280
281	if (IS_TX(i)) {
282	ltq_dma_alloc_tx(&ch->dma);
dddb29e4	283	request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
504d4721 JC	284	} else if (IS_RX(i)) {
	285	ltq_dma_alloc_rx(&ch->dma);
	286	for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
	287	ch->dma.desc++)
	288	if (ltq_etop_alloc_skb(ch))
	289	return -ENOMEM;
	290	ch->dma.desc = 0;
dddb29e4	291	request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
504d4721 JC	292	}
	293	ch->dma.irq = irq;
	294	}
	295	return 0;
	296	}
	297
	298	static void
	299	ltq_etop_get_drvinfo(struct net_device dev, struct ethtool_drvinfo info)
	300	{
7826d43f JP	301	strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
	302	strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
	303	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
504d4721 JC	304	}
504d4721 JC	305
504d4721 JC	306	static const struct ethtool_ops ltq_etop_ethtool_ops = {
504d4721 JC	307	.get_drvinfo = ltq_etop_get_drvinfo,
e3979ce9	308	.nway_reset = phy_ethtool_nway_reset,
5376d95f PR	309	.get_link_ksettings = phy_ethtool_get_link_ksettings,
5376d95f PR	310	.set_link_ksettings = phy_ethtool_set_link_ksettings,
504d4721 JC	311	};
	312
	313	static int
	314	ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
	315	{
	316	u32 val = MDIO_REQUEST \|
	317	((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) \|
	318	((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) \|
	319	phy_data;
	320
	321	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
	322	;
	323	ltq_etop_w32(val, LTQ_ETOP_MDIO);
	324	return 0;
	325	}
	326
	327	static int
	328	ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
	329	{
	330	u32 val = MDIO_REQUEST \| MDIO_READ \|
	331	((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) \|
	332	((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
	333
	334	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
	335	;
	336	ltq_etop_w32(val, LTQ_ETOP_MDIO);
	337	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
	338	;
	339	val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
	340	return val;
	341	}
	342
	343	static void
	344	ltq_etop_mdio_link(struct net_device *dev)
	345	{
	346	/* nothing to do */
	347	}
	348
	349	static int
	350	ltq_etop_mdio_probe(struct net_device *dev)
	351	{
	352	struct ltq_etop_priv *priv = netdev_priv(dev);
2a4fc4ea	353	struct phy_device *phydev;
504d4721	354
2a4fc4ea	355	phydev = phy_find_first(priv->mii_bus);
504d4721 JC	356
	357	if (!phydev) {
	358	netdev_err(dev, "no PHY found\n");
	359	return -ENODEV;
	360	}
	361
84eff6d1	362	phydev = phy_connect(dev, phydev_name(phydev),
f9a8f83b	363	&ltq_etop_mdio_link, priv->pldata->mii_mode);
504d4721 JC	364
	365	if (IS_ERR(phydev)) {
	366	netdev_err(dev, "Could not attach to PHY\n");
	367	return PTR_ERR(phydev);
	368	}
	369
	370	phydev->supported &= (SUPPORTED_10baseT_Half
	371	\| SUPPORTED_10baseT_Full
	372	\| SUPPORTED_100baseT_Half
	373	\| SUPPORTED_100baseT_Full
	374	\| SUPPORTED_Autoneg
	375	\| SUPPORTED_MII
	376	\| SUPPORTED_TP);
	377
	378	phydev->advertising = phydev->supported;
2220943a	379	phy_attached_info(phydev);
504d4721 JC	380
	381	return 0;
	382	}
	383
	384	static int
	385	ltq_etop_mdio_init(struct net_device *dev)
	386	{
	387	struct ltq_etop_priv *priv = netdev_priv(dev);
504d4721 JC	388	int err;
	389
	390	priv->mii_bus = mdiobus_alloc();
	391	if (!priv->mii_bus) {
	392	netdev_err(dev, "failed to allocate mii bus\n");
	393	err = -ENOMEM;
	394	goto err_out;
	395	}
	396
	397	priv->mii_bus->priv = dev;
	398	priv->mii_bus->read = ltq_etop_mdio_rd;
	399	priv->mii_bus->write = ltq_etop_mdio_wr;
	400	priv->mii_bus->name = "ltq_mii";
d1b86507 FF	401	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
d1b86507 FF	402	priv->pdev->name, priv->pdev->id);
504d4721 JC	403	if (mdiobus_register(priv->mii_bus)) {
504d4721 JC	404	err = -ENXIO;
e7f4dc35	405	goto err_out_free_mdiobus;
504d4721 JC	406	}
	407
	408	if (ltq_etop_mdio_probe(dev)) {
	409	err = -ENXIO;
	410	goto err_out_unregister_bus;
	411	}
	412	return 0;
	413
	414	err_out_unregister_bus:
	415	mdiobus_unregister(priv->mii_bus);
504d4721 JC	416	err_out_free_mdiobus:
	417	mdiobus_free(priv->mii_bus);
	418	err_out:
	419	return err;
	420	}
	421
	422	static void
	423	ltq_etop_mdio_cleanup(struct net_device *dev)
	424	{
	425	struct ltq_etop_priv *priv = netdev_priv(dev);
	426
d1e3a356	427	phy_disconnect(dev->phydev);
504d4721	428	mdiobus_unregister(priv->mii_bus);
504d4721 JC	429	mdiobus_free(priv->mii_bus);
	430	}
	431
	432	static int
	433	ltq_etop_open(struct net_device *dev)
	434	{
	435	struct ltq_etop_priv *priv = netdev_priv(dev);
	436	int i;
	437
	438	for (i = 0; i < MAX_DMA_CHAN; i++) {
	439	struct ltq_etop_chan *ch = &priv->ch[i];
	440
	441	if (!IS_TX(i) && (!IS_RX(i)))
	442	continue;
	443	ltq_dma_open(&ch->dma);
	444	napi_enable(&ch->napi);
	445	}
d1e3a356	446	phy_start(dev->phydev);
504d4721 JC	447	netif_tx_start_all_queues(dev);
	448	return 0;
	449	}
	450
	451	static int
	452	ltq_etop_stop(struct net_device *dev)
	453	{
	454	struct ltq_etop_priv *priv = netdev_priv(dev);
	455	int i;
	456
	457	netif_tx_stop_all_queues(dev);
d1e3a356	458	phy_stop(dev->phydev);
504d4721 JC	459	for (i = 0; i < MAX_DMA_CHAN; i++) {
	460	struct ltq_etop_chan *ch = &priv->ch[i];
	461
	462	if (!IS_RX(i) && !IS_TX(i))
	463	continue;
	464	napi_disable(&ch->napi);
	465	ltq_dma_close(&ch->dma);
	466	}
	467	return 0;
	468	}
	469
	470	static int
	471	ltq_etop_tx(struct sk_buff skb, struct net_device dev)
	472	{
	473	int queue = skb_get_queue_mapping(skb);
	474	struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
	475	struct ltq_etop_priv *priv = netdev_priv(dev);
	476	struct ltq_etop_chan *ch = &priv->ch[(queue << 1) \| 1];
	477	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
	478	int len;
	479	unsigned long flags;
	480	u32 byte_offset;
	481
	482	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
	483
	484	if ((desc->ctl & (LTQ_DMA_OWN \| LTQ_DMA_C)) \|\| ch->skb[ch->dma.desc]) {
	485	dev_kfree_skb_any(skb);
	486	netdev_err(dev, "tx ring full\n");
	487	netif_tx_stop_queue(txq);
	488	return NETDEV_TX_BUSY;
	489	}
	490
	491	/* dma needs to start on a 16 byte aligned address */
	492	byte_offset = CPHYSADDR(skb->data) % 16;
	493	ch->skb[ch->dma.desc] = skb;
	494
860e9538	495	netif_trans_update(dev);
504d4721 JC	496
	497	spin_lock_irqsave(&priv->lock, flags);
	498	desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
	499	DMA_TO_DEVICE)) - byte_offset;
	500	wmb();
	501	desc->ctl = LTQ_DMA_OWN \| LTQ_DMA_SOP \| LTQ_DMA_EOP \|
	502	LTQ_DMA_TX_OFFSET(byte_offset) \| (len & LTQ_DMA_SIZE_MASK);
	503	ch->dma.desc++;
	504	ch->dma.desc %= LTQ_DESC_NUM;
	505	spin_unlock_irqrestore(&priv->lock, flags);
	506
	507	if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
	508	netif_tx_stop_queue(txq);
	509
	510	return NETDEV_TX_OK;
	511	}
	512
	513	static int
	514	ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
	515	{
a52ad514 JW	516	struct ltq_etop_priv *priv = netdev_priv(dev);
a52ad514 JW	517	unsigned long flags;
504d4721	518
a52ad514	519	dev->mtu = new_mtu;
504d4721	520
a52ad514 JW	521	spin_lock_irqsave(&priv->lock, flags);
	522	ltq_etop_w32((ETOP_PLEN_UNDER << 16) \| new_mtu, LTQ_ETOP_IGPLEN);
	523	spin_unlock_irqrestore(&priv->lock, flags);
	524
	525	return 0;
504d4721 JC	526	}
	527
	528	static int
	529	ltq_etop_ioctl(struct net_device dev, struct ifreq rq, int cmd)
	530	{
504d4721	531	/* TODO: mii-toll reports "No MII transceiver present!." ?!*/
d1e3a356	532	return phy_mii_ioctl(dev->phydev, rq, cmd);
504d4721 JC	533	}
	534
	535	static int
	536	ltq_etop_set_mac_address(struct net_device dev, void p)
	537	{
	538	int ret = eth_mac_addr(dev, p);
	539
	540	if (!ret) {
	541	struct ltq_etop_priv *priv = netdev_priv(dev);
	542	unsigned long flags;
	543
	544	/* store the mac for the unicast filter */
	545	spin_lock_irqsave(&priv->lock, flags);
	546	ltq_etop_w32(((u32 )dev->dev_addr), LTQ_ETOP_MAC_DA0);
	547	ltq_etop_w32(((u16 )&dev->dev_addr[4]) << 16,
	548	LTQ_ETOP_MAC_DA1);
	549	spin_unlock_irqrestore(&priv->lock, flags);
	550	}
	551	return ret;
	552	}
	553
	554	static void
	555	ltq_etop_set_multicast_list(struct net_device *dev)
	556	{
	557	struct ltq_etop_priv *priv = netdev_priv(dev);
	558	unsigned long flags;
	559
	560	/* ensure that the unicast filter is not enabled in promiscious mode */
	561	spin_lock_irqsave(&priv->lock, flags);
	562	if ((dev->flags & IFF_PROMISC) \|\| (dev->flags & IFF_ALLMULTI))
	563	ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
	564	else
	565	ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
	566	spin_unlock_irqrestore(&priv->lock, flags);
	567	}
	568
	569	static u16
f663dd9a	570	ltq_etop_select_queue(struct net_device dev, struct sk_buff skb,
99932d4f	571	void *accel_priv, select_queue_fallback_t fallback)
504d4721 JC	572	{
	573	/* we are currently only using the first queue */
	574	return 0;
	575	}
	576
	577	static int
	578	ltq_etop_init(struct net_device *dev)
	579	{
	580	struct ltq_etop_priv *priv = netdev_priv(dev);
	581	struct sockaddr mac;
	582	int err;
43aabec5	583	bool random_mac = false;
504d4721	584
504d4721 JC	585	dev->watchdog_timeo = 10 * HZ;
	586	err = ltq_etop_hw_init(dev);
	587	if (err)
	588	goto err_hw;
	589	ltq_etop_change_mtu(dev, 1500);
	590
	591	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
	592	if (!is_valid_ether_addr(mac.sa_data)) {
	593	pr_warn("etop: invalid MAC, using random\n");
7efd26d0	594	eth_random_addr(mac.sa_data);
43aabec5	595	random_mac = true;
504d4721 JC	596	}
	597
	598	err = ltq_etop_set_mac_address(dev, &mac);
	599	if (err)
	600	goto err_netdev;
43aabec5 DK	601
	602	/* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
	603	if (random_mac)
e41b2d7f	604	dev->addr_assign_type = NET_ADDR_RANDOM;
43aabec5	605
504d4721 JC	606	ltq_etop_set_multicast_list(dev);
	607	err = ltq_etop_mdio_init(dev);
	608	if (err)
	609	goto err_netdev;
	610	return 0;
	611
	612	err_netdev:
	613	unregister_netdev(dev);
	614	free_netdev(dev);
	615	err_hw:
	616	ltq_etop_hw_exit(dev);
	617	return err;
	618	}
	619
	620	static void
	621	ltq_etop_tx_timeout(struct net_device *dev)
	622	{
	623	int err;
	624
	625	ltq_etop_hw_exit(dev);
	626	err = ltq_etop_hw_init(dev);
	627	if (err)
	628	goto err_hw;
860e9538	629	netif_trans_update(dev);
504d4721 JC	630	netif_wake_queue(dev);
	631	return;
	632
	633	err_hw:
	634	ltq_etop_hw_exit(dev);
	635	netdev_err(dev, "failed to restart etop after TX timeout\n");
	636	}
	637
	638	static const struct net_device_ops ltq_eth_netdev_ops = {
	639	.ndo_open = ltq_etop_open,
	640	.ndo_stop = ltq_etop_stop,
	641	.ndo_start_xmit = ltq_etop_tx,
	642	.ndo_change_mtu = ltq_etop_change_mtu,
	643	.ndo_do_ioctl = ltq_etop_ioctl,
	644	.ndo_set_mac_address = ltq_etop_set_mac_address,
	645	.ndo_validate_addr = eth_validate_addr,
afc4b13d	646	.ndo_set_rx_mode = ltq_etop_set_multicast_list,
504d4721 JC	647	.ndo_select_queue = ltq_etop_select_queue,
	648	.ndo_init = ltq_etop_init,
	649	.ndo_tx_timeout = ltq_etop_tx_timeout,
	650	};
	651
	652	static int __init
	653	ltq_etop_probe(struct platform_device *pdev)
	654	{
	655	struct net_device *dev;
	656	struct ltq_etop_priv *priv;
	657	struct resource *res;
	658	int err;
	659	int i;
	660
	661	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	662	if (!res) {
	663	dev_err(&pdev->dev, "failed to get etop resource\n");
	664	err = -ENOENT;
	665	goto err_out;
	666	}
	667
	668	res = devm_request_mem_region(&pdev->dev, res->start,
	669	resource_size(res), dev_name(&pdev->dev));
	670	if (!res) {
	671	dev_err(&pdev->dev, "failed to request etop resource\n");
	672	err = -EBUSY;
	673	goto err_out;
	674	}
	675
	676	ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
	677	res->start, resource_size(res));
	678	if (!ltq_etop_membase) {
	679	dev_err(&pdev->dev, "failed to remap etop engine %d\n",
	680	pdev->id);
	681	err = -ENOMEM;
	682	goto err_out;
	683	}
	684
	685	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
41de8d4c JP	686	if (!dev) {
	687	err = -ENOMEM;
	688	goto err_out;
	689	}
504d4721 JC	690	strcpy(dev->name, "eth%d");
	691	dev->netdev_ops = &ltq_eth_netdev_ops;
	692	dev->ethtool_ops = &ltq_etop_ethtool_ops;
	693	priv = netdev_priv(dev);
	694	priv->res = res;
d1b86507	695	priv->pdev = pdev;
504d4721 JC	696	priv->pldata = dev_get_platdata(&pdev->dev);
	697	priv->netdev = dev;
	698	spin_lock_init(&priv->lock);
9cecb138	699	SET_NETDEV_DEV(dev, &pdev->dev);
504d4721 JC	700
	701	for (i = 0; i < MAX_DMA_CHAN; i++) {
	702	if (IS_TX(i))
	703	netif_napi_add(dev, &priv->ch[i].napi,
	704	ltq_etop_poll_tx, 8);
	705	else if (IS_RX(i))
	706	netif_napi_add(dev, &priv->ch[i].napi,
	707	ltq_etop_poll_rx, 32);
	708	priv->ch[i].netdev = dev;
	709	}
	710
	711	err = register_netdev(dev);
	712	if (err)
	713	goto err_free;
	714
	715	platform_set_drvdata(pdev, dev);
	716	return 0;
	717
	718	err_free:
cb0e51d8	719	free_netdev(dev);
504d4721 JC	720	err_out:
	721	return err;
	722	}
	723
a0a4efed	724	static int
504d4721 JC	725	ltq_etop_remove(struct platform_device *pdev)
	726	{
	727	struct net_device *dev = platform_get_drvdata(pdev);
	728
	729	if (dev) {
	730	netif_tx_stop_all_queues(dev);
	731	ltq_etop_hw_exit(dev);
	732	ltq_etop_mdio_cleanup(dev);
	733	unregister_netdev(dev);
	734	}
	735	return 0;
	736	}
	737
	738	static struct platform_driver ltq_mii_driver = {
a0a4efed	739	.remove = ltq_etop_remove,
504d4721 JC	740	.driver = {
504d4721 JC	741	.name = "ltq_etop",
504d4721 JC	742	},
	743	};
	744
	745	int __init
	746	init_ltq_etop(void)
	747	{
	748	int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
	749
	750	if (ret)
772301b6	751	pr_err("ltq_etop: Error registering platform driver!");
504d4721 JC	752	return ret;
	753	}
	754
	755	static void __exit
	756	exit_ltq_etop(void)
	757	{
	758	platform_driver_unregister(&ltq_mii_driver);
	759	}
	760
	761	module_init(init_ltq_etop);
	762	module_exit(exit_ltq_etop);
	763
	764	MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
	765	MODULE_DESCRIPTION("Lantiq SoC ETOP");
	766	MODULE_LICENSE("GPL");