Commit | Line | Data |
---|---|---|
3047f90b GR |
1 | /******************************************************************************* |
2 | ||
3 | Intel 82599 Virtual Function driver | |
dec0d8e4 | 4 | Copyright(c) 1999 - 2015 Intel Corporation. |
3047f90b GR |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
dec0d8e4 | 16 | this program; if not, see <http://www.gnu.org/licenses/>. |
3047f90b GR |
17 | |
18 | The full GNU General Public License is included in this distribution in | |
19 | the file called "COPYING". | |
20 | ||
21 | Contact Information: | |
22 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | ||
25 | *******************************************************************************/ | |
26 | ||
27 | #ifndef __IXGBE_VF_H__ | |
28 | #define __IXGBE_VF_H__ | |
29 | ||
30 | #include <linux/pci.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/if_ether.h> | |
5c58c47a | 34 | #include <linux/netdevice.h> |
3047f90b GR |
35 | |
36 | #include "defines.h" | |
37 | #include "regs.h" | |
38 | #include "mbx.h" | |
39 | ||
40 | struct ixgbe_hw; | |
41 | ||
42 | /* iterator type for walking multicast address lists */ | |
43 | typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, | |
44 | u32 *vmdq); | |
45 | struct ixgbe_mac_operations { | |
46 | s32 (*init_hw)(struct ixgbe_hw *); | |
47 | s32 (*reset_hw)(struct ixgbe_hw *); | |
48 | s32 (*start_hw)(struct ixgbe_hw *); | |
49 | s32 (*clear_hw_cntrs)(struct ixgbe_hw *); | |
50 | enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); | |
3047f90b GR |
51 | s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); |
52 | s32 (*stop_adapter)(struct ixgbe_hw *); | |
53 | s32 (*get_bus_info)(struct ixgbe_hw *); | |
7921f4dc | 54 | s32 (*negotiate_api_version)(struct ixgbe_hw *hw, int api); |
3047f90b GR |
55 | |
56 | /* Link */ | |
57 | s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool); | |
58 | s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); | |
59 | s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, | |
60 | bool *); | |
61 | ||
62 | /* RAR, Multicast, VLAN */ | |
63 | s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32); | |
46ec20ff | 64 | s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *); |
3047f90b | 65 | s32 (*init_rx_addrs)(struct ixgbe_hw *); |
5c58c47a | 66 | s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *); |
8b44a8a0 | 67 | s32 (*update_xcast_mode)(struct ixgbe_hw *, int); |
3047f90b GR |
68 | s32 (*enable_mc)(struct ixgbe_hw *); |
69 | s32 (*disable_mc)(struct ixgbe_hw *); | |
70 | s32 (*clear_vfta)(struct ixgbe_hw *); | |
71 | s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); | |
6a11e52b | 72 | s32 (*set_rlpml)(struct ixgbe_hw *, u16); |
3047f90b GR |
73 | }; |
74 | ||
75 | enum ixgbe_mac_type { | |
76 | ixgbe_mac_unknown = 0, | |
77 | ixgbe_mac_82599_vf, | |
2316aa2a | 78 | ixgbe_mac_X540_vf, |
47068b0d ET |
79 | ixgbe_mac_X550_vf, |
80 | ixgbe_mac_X550EM_x_vf, | |
1d94f987 | 81 | ixgbe_mac_x550em_a_vf, |
3047f90b GR |
82 | ixgbe_num_macs |
83 | }; | |
84 | ||
85 | struct ixgbe_mac_info { | |
86 | struct ixgbe_mac_operations ops; | |
87 | u8 addr[6]; | |
88 | u8 perm_addr[6]; | |
89 | ||
90 | enum ixgbe_mac_type type; | |
91 | ||
92 | s32 mc_filter_type; | |
93 | ||
94 | bool get_link_status; | |
95 | u32 max_tx_queues; | |
96 | u32 max_rx_queues; | |
97 | u32 max_msix_vectors; | |
98 | }; | |
99 | ||
100 | struct ixgbe_mbx_operations { | |
101 | s32 (*init_params)(struct ixgbe_hw *hw); | |
102 | s32 (*read)(struct ixgbe_hw *, u32 *, u16); | |
103 | s32 (*write)(struct ixgbe_hw *, u32 *, u16); | |
104 | s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16); | |
105 | s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16); | |
106 | s32 (*check_for_msg)(struct ixgbe_hw *); | |
107 | s32 (*check_for_ack)(struct ixgbe_hw *); | |
108 | s32 (*check_for_rst)(struct ixgbe_hw *); | |
109 | }; | |
110 | ||
111 | struct ixgbe_mbx_stats { | |
112 | u32 msgs_tx; | |
113 | u32 msgs_rx; | |
114 | ||
115 | u32 acks; | |
116 | u32 reqs; | |
117 | u32 rsts; | |
118 | }; | |
119 | ||
120 | struct ixgbe_mbx_info { | |
121 | struct ixgbe_mbx_operations ops; | |
122 | struct ixgbe_mbx_stats stats; | |
123 | u32 timeout; | |
124 | u32 udelay; | |
125 | u32 v2p_mailbox; | |
126 | u16 size; | |
127 | }; | |
128 | ||
129 | struct ixgbe_hw { | |
130 | void *back; | |
131 | ||
132 | u8 __iomem *hw_addr; | |
3047f90b GR |
133 | |
134 | struct ixgbe_mac_info mac; | |
135 | struct ixgbe_mbx_info mbx; | |
136 | ||
137 | u16 device_id; | |
138 | u16 subsystem_vendor_id; | |
139 | u16 subsystem_device_id; | |
140 | u16 vendor_id; | |
141 | ||
142 | u8 revision_id; | |
143 | bool adapter_stopped; | |
31186785 AD |
144 | |
145 | int api_version; | |
3047f90b GR |
146 | }; |
147 | ||
148 | struct ixgbevf_hw_stats { | |
149 | u64 base_vfgprc; | |
150 | u64 base_vfgptc; | |
151 | u64 base_vfgorc; | |
152 | u64 base_vfgotc; | |
153 | u64 base_vfmprc; | |
154 | ||
155 | u64 last_vfgprc; | |
156 | u64 last_vfgptc; | |
157 | u64 last_vfgorc; | |
158 | u64 last_vfgotc; | |
159 | u64 last_vfmprc; | |
160 | ||
161 | u64 vfgprc; | |
162 | u64 vfgptc; | |
163 | u64 vfgorc; | |
164 | u64 vfgotc; | |
165 | u64 vfmprc; | |
33bd9f60 GR |
166 | |
167 | u64 saved_reset_vfgprc; | |
168 | u64 saved_reset_vfgptc; | |
169 | u64 saved_reset_vfgorc; | |
170 | u64 saved_reset_vfgotc; | |
171 | u64 saved_reset_vfmprc; | |
3047f90b GR |
172 | }; |
173 | ||
174 | struct ixgbevf_info { | |
dec0d8e4 | 175 | enum ixgbe_mac_type mac; |
3d8fe98f | 176 | const struct ixgbe_mac_operations *mac_ops; |
3047f90b GR |
177 | }; |
178 | ||
dbf8b0d8 MR |
179 | #define IXGBE_FAILED_READ_REG 0xffffffffU |
180 | ||
181 | #define IXGBE_REMOVED(a) unlikely(!(a)) | |
182 | ||
06380db6 MR |
183 | static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value) |
184 | { | |
6aa7de05 | 185 | u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); |
984b0ee3 MR |
186 | |
187 | if (IXGBE_REMOVED(reg_addr)) | |
188 | return; | |
189 | writel(value, reg_addr + reg); | |
06380db6 | 190 | } |
dec0d8e4 | 191 | |
06380db6 MR |
192 | #define IXGBE_WRITE_REG(h, r, v) ixgbe_write_reg(h, r, v) |
193 | ||
32c74949 MR |
194 | u32 ixgbevf_read_reg(struct ixgbe_hw *hw, u32 reg); |
195 | #define IXGBE_READ_REG(h, r) ixgbevf_read_reg(h, r) | |
06380db6 MR |
196 | |
197 | static inline void ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, | |
dec0d8e4 | 198 | u32 offset, u32 value) |
06380db6 MR |
199 | { |
200 | ixgbe_write_reg(hw, reg + (offset << 2), value); | |
201 | } | |
dec0d8e4 | 202 | |
06380db6 MR |
203 | #define IXGBE_WRITE_REG_ARRAY(h, r, o, v) ixgbe_write_reg_array(h, r, o, v) |
204 | ||
205 | static inline u32 ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, | |
dec0d8e4 | 206 | u32 offset) |
06380db6 | 207 | { |
32c74949 | 208 | return ixgbevf_read_reg(hw, reg + (offset << 2)); |
06380db6 | 209 | } |
dec0d8e4 | 210 | |
06380db6 MR |
211 | #define IXGBE_READ_REG_ARRAY(h, r, o) ixgbe_read_reg_array(h, r, o) |
212 | ||
56e94095 AD |
213 | int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs, |
214 | unsigned int *default_tc); | |
94cf66f8 | 215 | int ixgbevf_get_reta_locked(struct ixgbe_hw *hw, u32 *reta, int num_rx_queues); |
ad1431e2 | 216 | int ixgbevf_get_rss_key_locked(struct ixgbe_hw *hw, u8 *rss_key); |
3047f90b | 217 | #endif /* __IXGBE_VF_H__ */ |