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51dce24b | 1 | // SPDX-License-Identifier: GPL-2.0 |
4c44b450 | 2 | /* Copyright(c) 1999 - 2024 Intel Corporation. */ |
92915f71 | 3 | |
92915f71 GR |
4 | /****************************************************************************** |
5 | Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code | |
6 | ******************************************************************************/ | |
dbd9636e JK |
7 | |
8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9 | ||
92915f71 | 10 | #include <linux/types.h> |
dadcd65f | 11 | #include <linux/bitops.h> |
92915f71 GR |
12 | #include <linux/module.h> |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/vmalloc.h> | |
16 | #include <linux/string.h> | |
17 | #include <linux/in.h> | |
18 | #include <linux/ip.h> | |
19 | #include <linux/tcp.h> | |
70a10e25 | 20 | #include <linux/sctp.h> |
92915f71 | 21 | #include <linux/ipv6.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
92915f71 GR |
23 | #include <net/checksum.h> |
24 | #include <net/ip6_checksum.h> | |
25 | #include <linux/ethtool.h> | |
01789349 | 26 | #include <linux/if.h> |
92915f71 | 27 | #include <linux/if_vlan.h> |
70c71606 | 28 | #include <linux/prefetch.h> |
2a20525b | 29 | #include <net/mpls.h> |
c7aec596 TN |
30 | #include <linux/bpf.h> |
31 | #include <linux/bpf_trace.h> | |
32 | #include <linux/atomic.h> | |
8f6617ba | 33 | #include <net/xfrm.h> |
92915f71 GR |
34 | |
35 | #include "ixgbevf.h" | |
36 | ||
3d8fe98f | 37 | const char ixgbevf_driver_name[] = "ixgbevf"; |
92915f71 | 38 | static const char ixgbevf_driver_string[] = |
422e05d1 | 39 | "Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver"; |
92915f71 | 40 | |
66c87bd5 | 41 | static char ixgbevf_copyright[] = |
4c44b450 | 42 | "Copyright (c) 2009 - 2024 Intel Corporation."; |
92915f71 GR |
43 | |
44 | static const struct ixgbevf_info *ixgbevf_info_tbl[] = { | |
c6d45171 KS |
45 | [board_82599_vf] = &ixgbevf_82599_vf_info, |
46 | [board_82599_vf_hv] = &ixgbevf_82599_vf_hv_info, | |
47 | [board_X540_vf] = &ixgbevf_X540_vf_info, | |
48 | [board_X540_vf_hv] = &ixgbevf_X540_vf_hv_info, | |
49 | [board_X550_vf] = &ixgbevf_X550_vf_info, | |
50 | [board_X550_vf_hv] = &ixgbevf_X550_vf_hv_info, | |
51 | [board_X550EM_x_vf] = &ixgbevf_X550EM_x_vf_info, | |
52 | [board_X550EM_x_vf_hv] = &ixgbevf_X550EM_x_vf_hv_info, | |
1d94f987 | 53 | [board_x550em_a_vf] = &ixgbevf_x550em_a_vf_info, |
4c44b450 PK |
54 | [board_e610_vf] = &ixgbevf_e610_vf_info, |
55 | [board_e610_vf_hv] = &ixgbevf_e610_vf_hv_info, | |
92915f71 GR |
56 | }; |
57 | ||
58 | /* ixgbevf_pci_tbl - PCI Device ID Table | |
59 | * | |
60 | * Wildcard entries (PCI_ANY_ID) should come last | |
61 | * Last entry must be all 0s | |
62 | * | |
63 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
64 | * Class, Class Mask, private data (not used) } | |
65 | */ | |
9baa3c34 | 66 | static const struct pci_device_id ixgbevf_pci_tbl[] = { |
39ba22b4 | 67 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_VF), board_82599_vf }, |
c6d45171 | 68 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_VF_HV), board_82599_vf_hv }, |
39ba22b4 | 69 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540_VF), board_X540_vf }, |
c6d45171 | 70 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540_VF_HV), board_X540_vf_hv }, |
47068b0d | 71 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550_VF), board_X550_vf }, |
c6d45171 | 72 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550_VF_HV), board_X550_vf_hv }, |
47068b0d | 73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_VF), board_X550EM_x_vf }, |
c6d45171 | 74 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_VF_HV), board_X550EM_x_vf_hv}, |
1d94f987 | 75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_VF), board_x550em_a_vf }, |
4c44b450 PK |
76 | {PCI_VDEVICE_SUB(INTEL, IXGBE_DEV_ID_E610_VF, PCI_ANY_ID, |
77 | IXGBE_SUBDEV_ID_E610_VF_HV), board_e610_vf_hv}, | |
78 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_VF), board_e610_vf}, | |
92915f71 GR |
79 | /* required last entry */ |
80 | {0, } | |
81 | }; | |
82 | MODULE_DEVICE_TABLE(pci, ixgbevf_pci_tbl); | |
83 | ||
b8ce18cd | 84 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit Virtual Function Network Driver"); |
98674ebe | 85 | MODULE_LICENSE("GPL v2"); |
92915f71 | 86 | |
b3f4d599 | 87 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
88 | static int debug = -1; | |
89 | module_param(debug, int, 0); | |
90 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
92915f71 | 91 | |
40a13e24 MR |
92 | static struct workqueue_struct *ixgbevf_wq; |
93 | ||
9ac5c5cc ET |
94 | static void ixgbevf_service_event_schedule(struct ixgbevf_adapter *adapter) |
95 | { | |
96 | if (!test_bit(__IXGBEVF_DOWN, &adapter->state) && | |
97 | !test_bit(__IXGBEVF_REMOVING, &adapter->state) && | |
98 | !test_and_set_bit(__IXGBEVF_SERVICE_SCHED, &adapter->state)) | |
40a13e24 | 99 | queue_work(ixgbevf_wq, &adapter->service_task); |
9ac5c5cc ET |
100 | } |
101 | ||
102 | static void ixgbevf_service_event_complete(struct ixgbevf_adapter *adapter) | |
103 | { | |
104 | BUG_ON(!test_bit(__IXGBEVF_SERVICE_SCHED, &adapter->state)); | |
105 | ||
106 | /* flush memory to make sure state is correct before next watchdog */ | |
107 | smp_mb__before_atomic(); | |
108 | clear_bit(__IXGBEVF_SERVICE_SCHED, &adapter->state); | |
109 | } | |
110 | ||
92915f71 | 111 | /* forward decls */ |
220fe050 | 112 | static void ixgbevf_queue_reset_subtask(struct ixgbevf_adapter *adapter); |
fa71ae27 | 113 | static void ixgbevf_set_itr(struct ixgbevf_q_vector *q_vector); |
56e94095 | 114 | static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter); |
925f5690 ET |
115 | static bool ixgbevf_can_reuse_rx_page(struct ixgbevf_rx_buffer *rx_buffer); |
116 | static void ixgbevf_reuse_rx_page(struct ixgbevf_ring *rx_ring, | |
117 | struct ixgbevf_rx_buffer *old_buff); | |
92915f71 | 118 | |
dbf8b0d8 MR |
119 | static void ixgbevf_remove_adapter(struct ixgbe_hw *hw) |
120 | { | |
121 | struct ixgbevf_adapter *adapter = hw->back; | |
122 | ||
123 | if (!hw->hw_addr) | |
124 | return; | |
125 | hw->hw_addr = NULL; | |
126 | dev_err(&adapter->pdev->dev, "Adapter removed\n"); | |
9ac5c5cc ET |
127 | if (test_bit(__IXGBEVF_SERVICE_INITED, &adapter->state)) |
128 | ixgbevf_service_event_schedule(adapter); | |
dbf8b0d8 MR |
129 | } |
130 | ||
131 | static void ixgbevf_check_remove(struct ixgbe_hw *hw, u32 reg) | |
132 | { | |
133 | u32 value; | |
134 | ||
135 | /* The following check not only optimizes a bit by not | |
136 | * performing a read on the status register when the | |
137 | * register just read was a status register read that | |
138 | * returned IXGBE_FAILED_READ_REG. It also blocks any | |
139 | * potential recursion. | |
140 | */ | |
141 | if (reg == IXGBE_VFSTATUS) { | |
142 | ixgbevf_remove_adapter(hw); | |
143 | return; | |
144 | } | |
32c74949 | 145 | value = ixgbevf_read_reg(hw, IXGBE_VFSTATUS); |
dbf8b0d8 MR |
146 | if (value == IXGBE_FAILED_READ_REG) |
147 | ixgbevf_remove_adapter(hw); | |
148 | } | |
149 | ||
32c74949 | 150 | u32 ixgbevf_read_reg(struct ixgbe_hw *hw, u32 reg) |
dbf8b0d8 | 151 | { |
6aa7de05 | 152 | u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); |
dbf8b0d8 MR |
153 | u32 value; |
154 | ||
155 | if (IXGBE_REMOVED(reg_addr)) | |
156 | return IXGBE_FAILED_READ_REG; | |
157 | value = readl(reg_addr + reg); | |
158 | if (unlikely(value == IXGBE_FAILED_READ_REG)) | |
159 | ixgbevf_check_remove(hw, reg); | |
160 | return value; | |
161 | } | |
162 | ||
49ce9c2c | 163 | /** |
65d676c8 | 164 | * ixgbevf_set_ivar - set IVAR registers - maps interrupt causes to vectors |
92915f71 GR |
165 | * @adapter: pointer to adapter struct |
166 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
167 | * @queue: queue to map the corresponding interrupt to | |
168 | * @msix_vector: the vector to map to the corresponding queue | |
dec0d8e4 | 169 | **/ |
92915f71 GR |
170 | static void ixgbevf_set_ivar(struct ixgbevf_adapter *adapter, s8 direction, |
171 | u8 queue, u8 msix_vector) | |
172 | { | |
173 | u32 ivar, index; | |
174 | struct ixgbe_hw *hw = &adapter->hw; | |
dec0d8e4 | 175 | |
92915f71 GR |
176 | if (direction == -1) { |
177 | /* other causes */ | |
178 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
179 | ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); | |
180 | ivar &= ~0xFF; | |
181 | ivar |= msix_vector; | |
182 | IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, ivar); | |
183 | } else { | |
dec0d8e4 | 184 | /* Tx or Rx causes */ |
92915f71 GR |
185 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; |
186 | index = ((16 * (queue & 1)) + (8 * direction)); | |
187 | ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); | |
188 | ivar &= ~(0xFF << index); | |
189 | ivar |= (msix_vector << index); | |
190 | IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), ivar); | |
191 | } | |
192 | } | |
193 | ||
e08400b7 ET |
194 | static u64 ixgbevf_get_tx_completed(struct ixgbevf_ring *ring) |
195 | { | |
196 | return ring->stats.packets; | |
197 | } | |
92915f71 | 198 | |
e08400b7 ET |
199 | static u32 ixgbevf_get_tx_pending(struct ixgbevf_ring *ring) |
200 | { | |
201 | struct ixgbevf_adapter *adapter = netdev_priv(ring->netdev); | |
202 | struct ixgbe_hw *hw = &adapter->hw; | |
92915f71 | 203 | |
e08400b7 ET |
204 | u32 head = IXGBE_READ_REG(hw, IXGBE_VFTDH(ring->reg_idx)); |
205 | u32 tail = IXGBE_READ_REG(hw, IXGBE_VFTDT(ring->reg_idx)); | |
206 | ||
207 | if (head != tail) | |
208 | return (head < tail) ? | |
209 | tail - head : (tail + ring->count - head); | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | static inline bool ixgbevf_check_tx_hang(struct ixgbevf_ring *tx_ring) | |
215 | { | |
216 | u32 tx_done = ixgbevf_get_tx_completed(tx_ring); | |
217 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
218 | u32 tx_pending = ixgbevf_get_tx_pending(tx_ring); | |
219 | ||
220 | clear_check_for_tx_hang(tx_ring); | |
221 | ||
222 | /* Check for a hung queue, but be thorough. This verifies | |
223 | * that a transmit has been completed since the previous | |
224 | * check AND there is at least one packet pending. The | |
225 | * ARMED bit is set to indicate a potential hang. | |
226 | */ | |
227 | if ((tx_done_old == tx_done) && tx_pending) { | |
228 | /* make sure it is true for two checks in a row */ | |
229 | return test_and_set_bit(__IXGBEVF_HANG_CHECK_ARMED, | |
230 | &tx_ring->state); | |
231 | } | |
232 | /* reset the countdown */ | |
233 | clear_bit(__IXGBEVF_HANG_CHECK_ARMED, &tx_ring->state); | |
234 | ||
235 | /* update completed stats and continue */ | |
236 | tx_ring->tx_stats.tx_done_old = tx_done; | |
237 | ||
238 | return false; | |
239 | } | |
240 | ||
9ac5c5cc ET |
241 | static void ixgbevf_tx_timeout_reset(struct ixgbevf_adapter *adapter) |
242 | { | |
243 | /* Do the reset outside of interrupt context */ | |
244 | if (!test_bit(__IXGBEVF_DOWN, &adapter->state)) { | |
d5dd7c3f | 245 | set_bit(__IXGBEVF_RESET_REQUESTED, &adapter->state); |
9ac5c5cc ET |
246 | ixgbevf_service_event_schedule(adapter); |
247 | } | |
248 | } | |
249 | ||
e08400b7 ET |
250 | /** |
251 | * ixgbevf_tx_timeout - Respond to a Tx Hang | |
252 | * @netdev: network interface device structure | |
b50f7bca | 253 | * @txqueue: transmit queue hanging (unused) |
e08400b7 | 254 | **/ |
b50f7bca | 255 | static void ixgbevf_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) |
e08400b7 ET |
256 | { |
257 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
258 | ||
9ac5c5cc | 259 | ixgbevf_tx_timeout_reset(adapter); |
e08400b7 | 260 | } |
92915f71 GR |
261 | |
262 | /** | |
263 | * ixgbevf_clean_tx_irq - Reclaim resources after transmit completes | |
fa71ae27 | 264 | * @q_vector: board private structure |
92915f71 | 265 | * @tx_ring: tx ring to clean |
8220bbc1 | 266 | * @napi_budget: Used to determine if we are in netpoll |
92915f71 | 267 | **/ |
fa71ae27 | 268 | static bool ixgbevf_clean_tx_irq(struct ixgbevf_q_vector *q_vector, |
8220bbc1 | 269 | struct ixgbevf_ring *tx_ring, int napi_budget) |
92915f71 | 270 | { |
fa71ae27 | 271 | struct ixgbevf_adapter *adapter = q_vector->adapter; |
7ad1a093 ET |
272 | struct ixgbevf_tx_buffer *tx_buffer; |
273 | union ixgbe_adv_tx_desc *tx_desc; | |
7f68d430 | 274 | unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; |
7ad1a093 ET |
275 | unsigned int budget = tx_ring->count / 2; |
276 | unsigned int i = tx_ring->next_to_clean; | |
92915f71 | 277 | |
10cc1bdd AD |
278 | if (test_bit(__IXGBEVF_DOWN, &adapter->state)) |
279 | return true; | |
280 | ||
7ad1a093 ET |
281 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
282 | tx_desc = IXGBEVF_TX_DESC(tx_ring, i); | |
283 | i -= tx_ring->count; | |
92915f71 | 284 | |
e757e3e1 | 285 | do { |
7ad1a093 | 286 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
e757e3e1 AD |
287 | |
288 | /* if next_to_watch is not set then there is no work pending */ | |
289 | if (!eop_desc) | |
290 | break; | |
291 | ||
292 | /* prevent any other reads prior to eop_desc */ | |
ae0c585d | 293 | smp_rmb(); |
e757e3e1 AD |
294 | |
295 | /* if DD is not set pending work has not been completed */ | |
296 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
297 | break; | |
298 | ||
299 | /* clear next_to_watch to prevent false hangs */ | |
7ad1a093 | 300 | tx_buffer->next_to_watch = NULL; |
e757e3e1 | 301 | |
7ad1a093 ET |
302 | /* update the statistics for this packet */ |
303 | total_bytes += tx_buffer->bytecount; | |
304 | total_packets += tx_buffer->gso_segs; | |
7f68d430 SN |
305 | if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) |
306 | total_ipsec++; | |
92915f71 | 307 | |
9bdfefd2 | 308 | /* free the skb */ |
21092e9c TN |
309 | if (ring_is_xdp(tx_ring)) |
310 | page_frag_free(tx_buffer->data); | |
311 | else | |
312 | napi_consume_skb(tx_buffer->skb, napi_budget); | |
9bdfefd2 ET |
313 | |
314 | /* unmap skb header data */ | |
315 | dma_unmap_single(tx_ring->dev, | |
316 | dma_unmap_addr(tx_buffer, dma), | |
317 | dma_unmap_len(tx_buffer, len), | |
318 | DMA_TO_DEVICE); | |
319 | ||
7ad1a093 | 320 | /* clear tx_buffer data */ |
9bdfefd2 | 321 | dma_unmap_len_set(tx_buffer, len, 0); |
92915f71 | 322 | |
7ad1a093 ET |
323 | /* unmap remaining buffers */ |
324 | while (tx_desc != eop_desc) { | |
7ad1a093 ET |
325 | tx_buffer++; |
326 | tx_desc++; | |
92915f71 | 327 | i++; |
7ad1a093 ET |
328 | if (unlikely(!i)) { |
329 | i -= tx_ring->count; | |
330 | tx_buffer = tx_ring->tx_buffer_info; | |
331 | tx_desc = IXGBEVF_TX_DESC(tx_ring, 0); | |
332 | } | |
e757e3e1 | 333 | |
9bdfefd2 ET |
334 | /* unmap any remaining paged data */ |
335 | if (dma_unmap_len(tx_buffer, len)) { | |
336 | dma_unmap_page(tx_ring->dev, | |
337 | dma_unmap_addr(tx_buffer, dma), | |
338 | dma_unmap_len(tx_buffer, len), | |
339 | DMA_TO_DEVICE); | |
340 | dma_unmap_len_set(tx_buffer, len, 0); | |
341 | } | |
92915f71 GR |
342 | } |
343 | ||
7ad1a093 ET |
344 | /* move us one more past the eop_desc for start of next pkt */ |
345 | tx_buffer++; | |
346 | tx_desc++; | |
347 | i++; | |
348 | if (unlikely(!i)) { | |
349 | i -= tx_ring->count; | |
350 | tx_buffer = tx_ring->tx_buffer_info; | |
351 | tx_desc = IXGBEVF_TX_DESC(tx_ring, 0); | |
352 | } | |
353 | ||
354 | /* issue prefetch for next Tx descriptor */ | |
355 | prefetch(tx_desc); | |
356 | ||
357 | /* update budget accounting */ | |
358 | budget--; | |
359 | } while (likely(budget)); | |
360 | ||
361 | i += tx_ring->count; | |
92915f71 | 362 | tx_ring->next_to_clean = i; |
7ad1a093 ET |
363 | u64_stats_update_begin(&tx_ring->syncp); |
364 | tx_ring->stats.bytes += total_bytes; | |
365 | tx_ring->stats.packets += total_packets; | |
366 | u64_stats_update_end(&tx_ring->syncp); | |
367 | q_vector->tx.total_bytes += total_bytes; | |
368 | q_vector->tx.total_packets += total_packets; | |
7f68d430 | 369 | adapter->tx_ipsec += total_ipsec; |
92915f71 | 370 | |
e08400b7 ET |
371 | if (check_for_tx_hang(tx_ring) && ixgbevf_check_tx_hang(tx_ring)) { |
372 | struct ixgbe_hw *hw = &adapter->hw; | |
373 | union ixgbe_adv_tx_desc *eop_desc; | |
374 | ||
375 | eop_desc = tx_ring->tx_buffer_info[i].next_to_watch; | |
376 | ||
21092e9c | 377 | pr_err("Detected Tx Unit Hang%s\n" |
e08400b7 ET |
378 | " Tx Queue <%d>\n" |
379 | " TDH, TDT <%x>, <%x>\n" | |
380 | " next_to_use <%x>\n" | |
381 | " next_to_clean <%x>\n" | |
382 | "tx_buffer_info[next_to_clean]\n" | |
383 | " next_to_watch <%p>\n" | |
384 | " eop_desc->wb.status <%x>\n" | |
385 | " time_stamp <%lx>\n" | |
386 | " jiffies <%lx>\n", | |
21092e9c | 387 | ring_is_xdp(tx_ring) ? " XDP" : "", |
e08400b7 ET |
388 | tx_ring->queue_index, |
389 | IXGBE_READ_REG(hw, IXGBE_VFTDH(tx_ring->reg_idx)), | |
390 | IXGBE_READ_REG(hw, IXGBE_VFTDT(tx_ring->reg_idx)), | |
391 | tx_ring->next_to_use, i, | |
392 | eop_desc, (eop_desc ? eop_desc->wb.status : 0), | |
393 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
394 | ||
21092e9c TN |
395 | if (!ring_is_xdp(tx_ring)) |
396 | netif_stop_subqueue(tx_ring->netdev, | |
397 | tx_ring->queue_index); | |
e08400b7 ET |
398 | |
399 | /* schedule immediate reset if we believe we hung */ | |
9ac5c5cc | 400 | ixgbevf_tx_timeout_reset(adapter); |
e08400b7 ET |
401 | |
402 | return true; | |
403 | } | |
404 | ||
21092e9c TN |
405 | if (ring_is_xdp(tx_ring)) |
406 | return !!budget; | |
407 | ||
92915f71 | 408 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
7ad1a093 | 409 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
f880d07b | 410 | (ixgbevf_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
92915f71 GR |
411 | /* Make sure that anybody stopping the queue after this |
412 | * sees the new next_to_clean. | |
413 | */ | |
414 | smp_mb(); | |
7ad1a093 | 415 | |
fb40195c AD |
416 | if (__netif_subqueue_stopped(tx_ring->netdev, |
417 | tx_ring->queue_index) && | |
92915f71 | 418 | !test_bit(__IXGBEVF_DOWN, &adapter->state)) { |
fb40195c AD |
419 | netif_wake_subqueue(tx_ring->netdev, |
420 | tx_ring->queue_index); | |
7ad1a093 | 421 | ++tx_ring->tx_stats.restart_queue; |
92915f71 | 422 | } |
92915f71 GR |
423 | } |
424 | ||
7ad1a093 | 425 | return !!budget; |
92915f71 GR |
426 | } |
427 | ||
08681618 JK |
428 | /** |
429 | * ixgbevf_rx_skb - Helper function to determine proper Rx method | |
430 | * @q_vector: structure containing interrupt and ring information | |
431 | * @skb: packet to send up | |
08681618 JK |
432 | **/ |
433 | static void ixgbevf_rx_skb(struct ixgbevf_q_vector *q_vector, | |
dff80520 | 434 | struct sk_buff *skb) |
08681618 | 435 | { |
688ff32d | 436 | napi_gro_receive(&q_vector->napi, skb); |
08681618 JK |
437 | } |
438 | ||
1e1429d6 FD |
439 | #define IXGBE_RSS_L4_TYPES_MASK \ |
440 | ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ | |
441 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ | |
442 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ | |
443 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) | |
444 | ||
445 | static inline void ixgbevf_rx_hash(struct ixgbevf_ring *ring, | |
446 | union ixgbe_adv_rx_desc *rx_desc, | |
447 | struct sk_buff *skb) | |
448 | { | |
449 | u16 rss_type; | |
450 | ||
451 | if (!(ring->netdev->features & NETIF_F_RXHASH)) | |
452 | return; | |
453 | ||
454 | rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & | |
455 | IXGBE_RXDADV_RSSTYPE_MASK; | |
456 | ||
457 | if (!rss_type) | |
458 | return; | |
459 | ||
460 | skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), | |
461 | (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? | |
462 | PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); | |
463 | } | |
464 | ||
dec0d8e4 JK |
465 | /** |
466 | * ixgbevf_rx_checksum - indicate in skb if hw indicated a good cksum | |
ec62fe26 ET |
467 | * @ring: structure containig ring specific data |
468 | * @rx_desc: current Rx descriptor being processed | |
92915f71 | 469 | * @skb: skb currently being received and modified |
dec0d8e4 | 470 | **/ |
55fb277c | 471 | static inline void ixgbevf_rx_checksum(struct ixgbevf_ring *ring, |
ec62fe26 ET |
472 | union ixgbe_adv_rx_desc *rx_desc, |
473 | struct sk_buff *skb) | |
92915f71 | 474 | { |
bc8acf2c | 475 | skb_checksum_none_assert(skb); |
92915f71 GR |
476 | |
477 | /* Rx csum disabled */ | |
fb40195c | 478 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
92915f71 GR |
479 | return; |
480 | ||
481 | /* if IP and error */ | |
ec62fe26 ET |
482 | if (ixgbevf_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
483 | ixgbevf_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
095e2617 | 484 | ring->rx_stats.csum_err++; |
92915f71 GR |
485 | return; |
486 | } | |
487 | ||
ec62fe26 | 488 | if (!ixgbevf_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
92915f71 GR |
489 | return; |
490 | ||
ec62fe26 | 491 | if (ixgbevf_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
095e2617 | 492 | ring->rx_stats.csum_err++; |
92915f71 GR |
493 | return; |
494 | } | |
495 | ||
496 | /* It must be a TCP or UDP packet with a valid checksum */ | |
497 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
92915f71 GR |
498 | } |
499 | ||
dec0d8e4 JK |
500 | /** |
501 | * ixgbevf_process_skb_fields - Populate skb header fields from Rx descriptor | |
dff80520 ET |
502 | * @rx_ring: rx descriptor ring packet is being transacted on |
503 | * @rx_desc: pointer to the EOP Rx descriptor | |
504 | * @skb: pointer to current skb being populated | |
505 | * | |
506 | * This function checks the ring, descriptor, and packet information in | |
507 | * order to populate the checksum, VLAN, protocol, and other fields within | |
508 | * the skb. | |
dec0d8e4 | 509 | **/ |
dff80520 ET |
510 | static void ixgbevf_process_skb_fields(struct ixgbevf_ring *rx_ring, |
511 | union ixgbe_adv_rx_desc *rx_desc, | |
512 | struct sk_buff *skb) | |
513 | { | |
1e1429d6 | 514 | ixgbevf_rx_hash(rx_ring, rx_desc, skb); |
dff80520 ET |
515 | ixgbevf_rx_checksum(rx_ring, rx_desc, skb); |
516 | ||
517 | if (ixgbevf_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { | |
518 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); | |
519 | unsigned long *active_vlans = netdev_priv(rx_ring->netdev); | |
520 | ||
521 | if (test_bit(vid & VLAN_VID_MASK, active_vlans)) | |
522 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); | |
523 | } | |
524 | ||
7f68d430 SN |
525 | if (ixgbevf_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) |
526 | ixgbevf_ipsec_rx(rx_ring, rx_desc, skb); | |
527 | ||
dff80520 ET |
528 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
529 | } | |
530 | ||
925f5690 ET |
531 | static |
532 | struct ixgbevf_rx_buffer *ixgbevf_get_rx_buffer(struct ixgbevf_ring *rx_ring, | |
533 | const unsigned int size) | |
534 | { | |
535 | struct ixgbevf_rx_buffer *rx_buffer; | |
536 | ||
537 | rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; | |
538 | prefetchw(rx_buffer->page); | |
539 | ||
540 | /* we are reusing so sync this buffer for CPU use */ | |
541 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
542 | rx_buffer->dma, | |
543 | rx_buffer->page_offset, | |
544 | size, | |
545 | DMA_FROM_DEVICE); | |
546 | ||
547 | rx_buffer->pagecnt_bias--; | |
548 | ||
549 | return rx_buffer; | |
550 | } | |
551 | ||
552 | static void ixgbevf_put_rx_buffer(struct ixgbevf_ring *rx_ring, | |
c7aec596 TN |
553 | struct ixgbevf_rx_buffer *rx_buffer, |
554 | struct sk_buff *skb) | |
925f5690 ET |
555 | { |
556 | if (ixgbevf_can_reuse_rx_page(rx_buffer)) { | |
557 | /* hand second half of page back to the ring */ | |
558 | ixgbevf_reuse_rx_page(rx_ring, rx_buffer); | |
559 | } else { | |
c7aec596 TN |
560 | if (IS_ERR(skb)) |
561 | /* We are not reusing the buffer so unmap it and free | |
562 | * any references we are holding to it | |
563 | */ | |
564 | dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, | |
565 | ixgbevf_rx_pg_size(rx_ring), | |
566 | DMA_FROM_DEVICE, | |
567 | IXGBEVF_RX_DMA_ATTR); | |
925f5690 ET |
568 | __page_frag_cache_drain(rx_buffer->page, |
569 | rx_buffer->pagecnt_bias); | |
570 | } | |
571 | ||
572 | /* clear contents of rx_buffer */ | |
573 | rx_buffer->page = NULL; | |
574 | } | |
575 | ||
4b95fe3d ET |
576 | /** |
577 | * ixgbevf_is_non_eop - process handling of non-EOP buffers | |
578 | * @rx_ring: Rx ring being processed | |
579 | * @rx_desc: Rx descriptor for current buffer | |
4b95fe3d ET |
580 | * |
581 | * This function updates next to clean. If the buffer is an EOP buffer | |
582 | * this function exits returning false, otherwise it will place the | |
583 | * sk_buff in the next buffer to be chained and return true indicating | |
584 | * that this is in fact a non-EOP buffer. | |
585 | **/ | |
586 | static bool ixgbevf_is_non_eop(struct ixgbevf_ring *rx_ring, | |
bad17234 | 587 | union ixgbe_adv_rx_desc *rx_desc) |
4b95fe3d ET |
588 | { |
589 | u32 ntc = rx_ring->next_to_clean + 1; | |
590 | ||
591 | /* fetch, update, and store next to clean */ | |
592 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
593 | rx_ring->next_to_clean = ntc; | |
594 | ||
595 | prefetch(IXGBEVF_RX_DESC(rx_ring, ntc)); | |
596 | ||
597 | if (likely(ixgbevf_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
598 | return false; | |
599 | ||
600 | return true; | |
601 | } | |
602 | ||
1ab37e12 ET |
603 | static inline unsigned int ixgbevf_rx_offset(struct ixgbevf_ring *rx_ring) |
604 | { | |
605 | return ring_uses_build_skb(rx_ring) ? IXGBEVF_SKB_PAD : 0; | |
606 | } | |
607 | ||
bad17234 ET |
608 | static bool ixgbevf_alloc_mapped_page(struct ixgbevf_ring *rx_ring, |
609 | struct ixgbevf_rx_buffer *bi) | |
bafa578f | 610 | { |
bad17234 | 611 | struct page *page = bi->page; |
93a6a37c | 612 | dma_addr_t dma; |
bafa578f | 613 | |
bad17234 ET |
614 | /* since we are recycling buffers we should seldom need to alloc */ |
615 | if (likely(page)) | |
bafa578f ET |
616 | return true; |
617 | ||
bad17234 | 618 | /* alloc new page for storage */ |
f15c5ba5 | 619 | page = dev_alloc_pages(ixgbevf_rx_pg_order(rx_ring)); |
bad17234 ET |
620 | if (unlikely(!page)) { |
621 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
bafa578f ET |
622 | return false; |
623 | } | |
624 | ||
bad17234 | 625 | /* map page for use */ |
f15c5ba5 ET |
626 | dma = dma_map_page_attrs(rx_ring->dev, page, 0, |
627 | ixgbevf_rx_pg_size(rx_ring), | |
16b35949 | 628 | DMA_FROM_DEVICE, IXGBEVF_RX_DMA_ATTR); |
bafa578f ET |
629 | |
630 | /* if mapping failed free memory back to system since | |
631 | * there isn't much point in holding memory we can't use | |
632 | */ | |
633 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
f15c5ba5 | 634 | __free_pages(page, ixgbevf_rx_pg_order(rx_ring)); |
bafa578f | 635 | |
2a35efe5 | 636 | rx_ring->rx_stats.alloc_rx_page_failed++; |
bafa578f ET |
637 | return false; |
638 | } | |
639 | ||
bafa578f | 640 | bi->dma = dma; |
bad17234 | 641 | bi->page = page; |
1ab37e12 | 642 | bi->page_offset = ixgbevf_rx_offset(rx_ring); |
35074d69 | 643 | bi->pagecnt_bias = 1; |
2a35efe5 | 644 | rx_ring->rx_stats.alloc_rx_page++; |
bafa578f ET |
645 | |
646 | return true; | |
647 | } | |
648 | ||
92915f71 GR |
649 | /** |
650 | * ixgbevf_alloc_rx_buffers - Replace used receive buffers; packet split | |
095e2617 | 651 | * @rx_ring: rx descriptor ring (for a specific queue) to setup buffers on |
bafa578f | 652 | * @cleaned_count: number of buffers to replace |
92915f71 | 653 | **/ |
095e2617 | 654 | static void ixgbevf_alloc_rx_buffers(struct ixgbevf_ring *rx_ring, |
bafa578f | 655 | u16 cleaned_count) |
92915f71 | 656 | { |
92915f71 GR |
657 | union ixgbe_adv_rx_desc *rx_desc; |
658 | struct ixgbevf_rx_buffer *bi; | |
fb40195c | 659 | unsigned int i = rx_ring->next_to_use; |
92915f71 | 660 | |
bafa578f ET |
661 | /* nothing to do or no valid netdev defined */ |
662 | if (!cleaned_count || !rx_ring->netdev) | |
663 | return; | |
b9dd245b | 664 | |
bafa578f ET |
665 | rx_desc = IXGBEVF_RX_DESC(rx_ring, i); |
666 | bi = &rx_ring->rx_buffer_info[i]; | |
667 | i -= rx_ring->count; | |
05d063aa | 668 | |
bafa578f | 669 | do { |
bad17234 | 670 | if (!ixgbevf_alloc_mapped_page(rx_ring, bi)) |
bafa578f | 671 | break; |
b9dd245b | 672 | |
16b35949 ET |
673 | /* sync the buffer for use by the device */ |
674 | dma_sync_single_range_for_device(rx_ring->dev, bi->dma, | |
675 | bi->page_offset, | |
f15c5ba5 | 676 | ixgbevf_rx_bufsz(rx_ring), |
16b35949 ET |
677 | DMA_FROM_DEVICE); |
678 | ||
bafa578f ET |
679 | /* Refresh the desc even if pkt_addr didn't change |
680 | * because each write-back erases this info. | |
681 | */ | |
bad17234 | 682 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); |
92915f71 | 683 | |
bafa578f ET |
684 | rx_desc++; |
685 | bi++; | |
92915f71 | 686 | i++; |
bafa578f ET |
687 | if (unlikely(!i)) { |
688 | rx_desc = IXGBEVF_RX_DESC(rx_ring, 0); | |
689 | bi = rx_ring->rx_buffer_info; | |
690 | i -= rx_ring->count; | |
691 | } | |
692 | ||
24bff091 ET |
693 | /* clear the length for the next_to_use descriptor */ |
694 | rx_desc->wb.upper.length = 0; | |
bafa578f ET |
695 | |
696 | cleaned_count--; | |
697 | } while (cleaned_count); | |
698 | ||
699 | i += rx_ring->count; | |
92915f71 | 700 | |
bafa578f ET |
701 | if (rx_ring->next_to_use != i) { |
702 | /* record the next descriptor to use */ | |
703 | rx_ring->next_to_use = i; | |
704 | ||
bad17234 ET |
705 | /* update next to alloc since we have filled the ring */ |
706 | rx_ring->next_to_alloc = i; | |
707 | ||
bafa578f ET |
708 | /* Force memory writes to complete before letting h/w |
709 | * know there are new descriptors to fetch. (Only | |
710 | * applicable for weak-ordered memory model archs, | |
711 | * such as IA-64). | |
712 | */ | |
713 | wmb(); | |
714 | ixgbevf_write_tail(rx_ring, i); | |
715 | } | |
92915f71 GR |
716 | } |
717 | ||
dec0d8e4 JK |
718 | /** |
719 | * ixgbevf_cleanup_headers - Correct corrupted or empty headers | |
bad17234 ET |
720 | * @rx_ring: rx descriptor ring packet is being transacted on |
721 | * @rx_desc: pointer to the EOP Rx descriptor | |
722 | * @skb: pointer to current skb being fixed | |
723 | * | |
724 | * Check for corrupted packet headers caused by senders on the local L2 | |
725 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
726 | * should be very rare. | |
727 | * | |
728 | * Also address the case where we are pulling data in on pages only | |
729 | * and as such no data is present in the skb header. | |
730 | * | |
731 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
732 | * it is large enough to qualify as a valid Ethernet frame. | |
733 | * | |
734 | * Returns true if an error was encountered and skb was freed. | |
dec0d8e4 | 735 | **/ |
bad17234 ET |
736 | static bool ixgbevf_cleanup_headers(struct ixgbevf_ring *rx_ring, |
737 | union ixgbe_adv_rx_desc *rx_desc, | |
738 | struct sk_buff *skb) | |
739 | { | |
740 | /* verify that the packet does not have any known errors */ | |
741 | if (unlikely(ixgbevf_test_staterr(rx_desc, | |
742 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK))) { | |
743 | struct net_device *netdev = rx_ring->netdev; | |
744 | ||
745 | if (!(netdev->features & NETIF_F_RXALL)) { | |
746 | dev_kfree_skb_any(skb); | |
747 | return true; | |
748 | } | |
749 | } | |
750 | ||
a94d9e22 AD |
751 | /* if eth_skb_pad returns an error the skb was freed */ |
752 | if (eth_skb_pad(skb)) | |
753 | return true; | |
bad17234 ET |
754 | |
755 | return false; | |
756 | } | |
757 | ||
dec0d8e4 JK |
758 | /** |
759 | * ixgbevf_reuse_rx_page - page flip buffer and store it back on the ring | |
bad17234 ET |
760 | * @rx_ring: rx descriptor ring to store buffers on |
761 | * @old_buff: donor buffer to have page reused | |
762 | * | |
763 | * Synchronizes page for reuse by the adapter | |
dec0d8e4 | 764 | **/ |
bad17234 ET |
765 | static void ixgbevf_reuse_rx_page(struct ixgbevf_ring *rx_ring, |
766 | struct ixgbevf_rx_buffer *old_buff) | |
767 | { | |
768 | struct ixgbevf_rx_buffer *new_buff; | |
769 | u16 nta = rx_ring->next_to_alloc; | |
770 | ||
771 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
772 | ||
773 | /* update, and store next to alloc */ | |
774 | nta++; | |
775 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
776 | ||
777 | /* transfer page from old buffer to new buffer */ | |
778 | new_buff->page = old_buff->page; | |
779 | new_buff->dma = old_buff->dma; | |
780 | new_buff->page_offset = old_buff->page_offset; | |
35074d69 | 781 | new_buff->pagecnt_bias = old_buff->pagecnt_bias; |
bad17234 ET |
782 | } |
783 | ||
925f5690 | 784 | static bool ixgbevf_can_reuse_rx_page(struct ixgbevf_rx_buffer *rx_buffer) |
a355fd9a | 785 | { |
925f5690 ET |
786 | unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; |
787 | struct page *page = rx_buffer->page; | |
35074d69 | 788 | |
a79afa78 AL |
789 | /* avoid re-using remote and pfmemalloc pages */ |
790 | if (!dev_page_is_reusable(page)) | |
a355fd9a ET |
791 | return false; |
792 | ||
793 | #if (PAGE_SIZE < 8192) | |
794 | /* if we are only owner of page we can reuse it */ | |
925f5690 | 795 | if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) |
a355fd9a | 796 | return false; |
a355fd9a | 797 | #else |
f15c5ba5 ET |
798 | #define IXGBEVF_LAST_OFFSET \ |
799 | (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBEVF_RXBUFFER_2048) | |
800 | ||
801 | if (rx_buffer->page_offset > IXGBEVF_LAST_OFFSET) | |
a355fd9a ET |
802 | return false; |
803 | ||
804 | #endif | |
35074d69 ET |
805 | |
806 | /* If we have drained the page fragment pool we need to update | |
807 | * the pagecnt_bias and page count so that we fully restock the | |
808 | * number of references the driver holds. | |
a355fd9a | 809 | */ |
925f5690 | 810 | if (unlikely(!pagecnt_bias)) { |
35074d69 ET |
811 | page_ref_add(page, USHRT_MAX); |
812 | rx_buffer->pagecnt_bias = USHRT_MAX; | |
813 | } | |
a355fd9a ET |
814 | |
815 | return true; | |
816 | } | |
817 | ||
dec0d8e4 JK |
818 | /** |
819 | * ixgbevf_add_rx_frag - Add contents of Rx buffer to sk_buff | |
bad17234 ET |
820 | * @rx_ring: rx descriptor ring to transact packets on |
821 | * @rx_buffer: buffer containing page to add | |
bad17234 | 822 | * @skb: sk_buff to place the data into |
925f5690 | 823 | * @size: size of buffer to be added |
bad17234 ET |
824 | * |
825 | * This function will add the data contained in rx_buffer->page to the skb. | |
dec0d8e4 | 826 | **/ |
925f5690 | 827 | static void ixgbevf_add_rx_frag(struct ixgbevf_ring *rx_ring, |
bad17234 | 828 | struct ixgbevf_rx_buffer *rx_buffer, |
925f5690 ET |
829 | struct sk_buff *skb, |
830 | unsigned int size) | |
bad17234 | 831 | { |
bad17234 | 832 | #if (PAGE_SIZE < 8192) |
f15c5ba5 | 833 | unsigned int truesize = ixgbevf_rx_pg_size(rx_ring) / 2; |
bad17234 | 834 | #else |
1ab37e12 ET |
835 | unsigned int truesize = ring_uses_build_skb(rx_ring) ? |
836 | SKB_DATA_ALIGN(IXGBEVF_SKB_PAD + size) : | |
837 | SKB_DATA_ALIGN(size); | |
bad17234 | 838 | #endif |
925f5690 ET |
839 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, |
840 | rx_buffer->page_offset, size, truesize); | |
841 | #if (PAGE_SIZE < 8192) | |
842 | rx_buffer->page_offset ^= truesize; | |
843 | #else | |
844 | rx_buffer->page_offset += truesize; | |
845 | #endif | |
bad17234 ET |
846 | } |
847 | ||
925f5690 ET |
848 | static |
849 | struct sk_buff *ixgbevf_construct_skb(struct ixgbevf_ring *rx_ring, | |
850 | struct ixgbevf_rx_buffer *rx_buffer, | |
c7aec596 TN |
851 | struct xdp_buff *xdp, |
852 | union ixgbe_adv_rx_desc *rx_desc) | |
bad17234 | 853 | { |
c7aec596 | 854 | unsigned int size = xdp->data_end - xdp->data; |
925f5690 ET |
855 | #if (PAGE_SIZE < 8192) |
856 | unsigned int truesize = ixgbevf_rx_pg_size(rx_ring) / 2; | |
857 | #else | |
c7aec596 TN |
858 | unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - |
859 | xdp->data_hard_start); | |
925f5690 ET |
860 | #endif |
861 | unsigned int headlen; | |
862 | struct sk_buff *skb; | |
bad17234 | 863 | |
925f5690 | 864 | /* prefetch first cache line of first page */ |
f468f21b TT |
865 | net_prefetch(xdp->data); |
866 | ||
be833332 TN |
867 | /* Note, we get here by enabling legacy-rx via: |
868 | * | |
869 | * ethtool --set-priv-flags <dev> legacy-rx on | |
870 | * | |
871 | * In this mode, we currently get 0 extra XDP headroom as | |
872 | * opposed to having legacy-rx off, where we process XDP | |
873 | * packets going to stack via ixgbevf_build_skb(). | |
874 | * | |
875 | * For ixgbevf_construct_skb() mode it means that the | |
876 | * xdp->data_meta will always point to xdp->data, since | |
877 | * the helper cannot expand the head. Should this ever | |
878 | * changed in future for legacy-rx mode on, then lets also | |
879 | * add xdp->data_meta handling here. | |
880 | */ | |
bad17234 | 881 | |
925f5690 ET |
882 | /* allocate a skb to store the frags */ |
883 | skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBEVF_RX_HDR_SIZE); | |
884 | if (unlikely(!skb)) | |
885 | return NULL; | |
bad17234 | 886 | |
925f5690 ET |
887 | /* Determine available headroom for copy */ |
888 | headlen = size; | |
889 | if (headlen > IXGBEVF_RX_HDR_SIZE) | |
c43f1255 SF |
890 | headlen = eth_get_headlen(skb->dev, xdp->data, |
891 | IXGBEVF_RX_HDR_SIZE); | |
bad17234 | 892 | |
925f5690 | 893 | /* align pull length to size of long to optimize memcpy performance */ |
c7aec596 TN |
894 | memcpy(__skb_put(skb, headlen), xdp->data, |
895 | ALIGN(headlen, sizeof(long))); | |
925f5690 ET |
896 | |
897 | /* update all of the pointers */ | |
898 | size -= headlen; | |
899 | if (size) { | |
900 | skb_add_rx_frag(skb, 0, rx_buffer->page, | |
c7aec596 TN |
901 | (xdp->data + headlen) - |
902 | page_address(rx_buffer->page), | |
925f5690 ET |
903 | size, truesize); |
904 | #if (PAGE_SIZE < 8192) | |
905 | rx_buffer->page_offset ^= truesize; | |
906 | #else | |
907 | rx_buffer->page_offset += truesize; | |
908 | #endif | |
bad17234 | 909 | } else { |
925f5690 | 910 | rx_buffer->pagecnt_bias++; |
bad17234 ET |
911 | } |
912 | ||
bad17234 ET |
913 | return skb; |
914 | } | |
915 | ||
92915f71 | 916 | static inline void ixgbevf_irq_enable_queues(struct ixgbevf_adapter *adapter, |
5f3600eb | 917 | u32 qmask) |
92915f71 | 918 | { |
92915f71 GR |
919 | struct ixgbe_hw *hw = &adapter->hw; |
920 | ||
5f3600eb | 921 | IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, qmask); |
92915f71 GR |
922 | } |
923 | ||
6d9c0217 ET |
924 | static struct sk_buff *ixgbevf_build_skb(struct ixgbevf_ring *rx_ring, |
925 | struct ixgbevf_rx_buffer *rx_buffer, | |
c7aec596 TN |
926 | struct xdp_buff *xdp, |
927 | union ixgbe_adv_rx_desc *rx_desc) | |
6d9c0217 | 928 | { |
be833332 | 929 | unsigned int metasize = xdp->data - xdp->data_meta; |
6d9c0217 ET |
930 | #if (PAGE_SIZE < 8192) |
931 | unsigned int truesize = ixgbevf_rx_pg_size(rx_ring) / 2; | |
932 | #else | |
933 | unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + | |
c7aec596 TN |
934 | SKB_DATA_ALIGN(xdp->data_end - |
935 | xdp->data_hard_start); | |
6d9c0217 ET |
936 | #endif |
937 | struct sk_buff *skb; | |
938 | ||
be833332 TN |
939 | /* Prefetch first cache line of first page. If xdp->data_meta |
940 | * is unused, this points to xdp->data, otherwise, we likely | |
941 | * have a consumer accessing first few bytes of meta data, | |
942 | * and then actual data. | |
943 | */ | |
f468f21b | 944 | net_prefetch(xdp->data_meta); |
6d9c0217 | 945 | |
c7aec596 | 946 | /* build an skb around the page buffer */ |
c1550019 | 947 | skb = napi_build_skb(xdp->data_hard_start, truesize); |
6d9c0217 ET |
948 | if (unlikely(!skb)) |
949 | return NULL; | |
950 | ||
951 | /* update pointers within the skb to store the data */ | |
c7aec596 TN |
952 | skb_reserve(skb, xdp->data - xdp->data_hard_start); |
953 | __skb_put(skb, xdp->data_end - xdp->data); | |
be833332 TN |
954 | if (metasize) |
955 | skb_metadata_set(skb, metasize); | |
6d9c0217 ET |
956 | |
957 | /* update buffer offset */ | |
958 | #if (PAGE_SIZE < 8192) | |
959 | rx_buffer->page_offset ^= truesize; | |
960 | #else | |
961 | rx_buffer->page_offset += truesize; | |
962 | #endif | |
963 | ||
964 | return skb; | |
965 | } | |
c7aec596 TN |
966 | |
967 | #define IXGBEVF_XDP_PASS 0 | |
968 | #define IXGBEVF_XDP_CONSUMED 1 | |
21092e9c TN |
969 | #define IXGBEVF_XDP_TX 2 |
970 | ||
971 | static int ixgbevf_xmit_xdp_ring(struct ixgbevf_ring *ring, | |
972 | struct xdp_buff *xdp) | |
973 | { | |
974 | struct ixgbevf_tx_buffer *tx_buffer; | |
975 | union ixgbe_adv_tx_desc *tx_desc; | |
976 | u32 len, cmd_type; | |
977 | dma_addr_t dma; | |
978 | u16 i; | |
979 | ||
980 | len = xdp->data_end - xdp->data; | |
c7aec596 | 981 | |
21092e9c TN |
982 | if (unlikely(!ixgbevf_desc_unused(ring))) |
983 | return IXGBEVF_XDP_CONSUMED; | |
984 | ||
985 | dma = dma_map_single(ring->dev, xdp->data, len, DMA_TO_DEVICE); | |
986 | if (dma_mapping_error(ring->dev, dma)) | |
987 | return IXGBEVF_XDP_CONSUMED; | |
988 | ||
989 | /* record the location of the first descriptor for this packet */ | |
21092e9c | 990 | i = ring->next_to_use; |
4be87727 | 991 | tx_buffer = &ring->tx_buffer_info[i]; |
21092e9c TN |
992 | |
993 | dma_unmap_len_set(tx_buffer, len, len); | |
994 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
995 | tx_buffer->data = xdp->data; | |
4be87727 AD |
996 | tx_buffer->bytecount = len; |
997 | tx_buffer->gso_segs = 1; | |
998 | tx_buffer->protocol = 0; | |
999 | ||
1000 | /* Populate minimal context descriptor that will provide for the | |
1001 | * fact that we are expected to process Ethernet frames. | |
1002 | */ | |
1003 | if (!test_bit(__IXGBEVF_TX_XDP_RING_PRIMED, &ring->state)) { | |
1004 | struct ixgbe_adv_tx_context_desc *context_desc; | |
1005 | ||
1006 | set_bit(__IXGBEVF_TX_XDP_RING_PRIMED, &ring->state); | |
1007 | ||
1008 | context_desc = IXGBEVF_TX_CTXTDESC(ring, 0); | |
1009 | context_desc->vlan_macip_lens = | |
1010 | cpu_to_le32(ETH_HLEN << IXGBE_ADVTXD_MACLEN_SHIFT); | |
7f68d430 | 1011 | context_desc->fceof_saidx = 0; |
4be87727 AD |
1012 | context_desc->type_tucmd_mlhl = |
1013 | cpu_to_le32(IXGBE_TXD_CMD_DEXT | | |
1014 | IXGBE_ADVTXD_DTYP_CTXT); | |
1015 | context_desc->mss_l4len_idx = 0; | |
1016 | ||
1017 | i = 1; | |
1018 | } | |
21092e9c TN |
1019 | |
1020 | /* put descriptor type bits */ | |
1021 | cmd_type = IXGBE_ADVTXD_DTYP_DATA | | |
1022 | IXGBE_ADVTXD_DCMD_DEXT | | |
1023 | IXGBE_ADVTXD_DCMD_IFCS; | |
1024 | cmd_type |= len | IXGBE_TXD_CMD; | |
4be87727 AD |
1025 | |
1026 | tx_desc = IXGBEVF_TX_DESC(ring, i); | |
1027 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
1028 | ||
21092e9c TN |
1029 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); |
1030 | tx_desc->read.olinfo_status = | |
1031 | cpu_to_le32((len << IXGBE_ADVTXD_PAYLEN_SHIFT) | | |
1032 | IXGBE_ADVTXD_CC); | |
1033 | ||
efecfd5f TN |
1034 | /* Avoid any potential race with cleanup */ |
1035 | smp_wmb(); | |
21092e9c TN |
1036 | |
1037 | /* set next_to_watch value indicating a packet is present */ | |
1038 | i++; | |
1039 | if (i == ring->count) | |
1040 | i = 0; | |
1041 | ||
1042 | tx_buffer->next_to_watch = tx_desc; | |
1043 | ring->next_to_use = i; | |
1044 | ||
21092e9c TN |
1045 | return IXGBEVF_XDP_TX; |
1046 | } | |
1047 | ||
35f715cb YH |
1048 | static int ixgbevf_run_xdp(struct ixgbevf_adapter *adapter, |
1049 | struct ixgbevf_ring *rx_ring, | |
1050 | struct xdp_buff *xdp) | |
c7aec596 TN |
1051 | { |
1052 | int result = IXGBEVF_XDP_PASS; | |
21092e9c | 1053 | struct ixgbevf_ring *xdp_ring; |
c7aec596 TN |
1054 | struct bpf_prog *xdp_prog; |
1055 | u32 act; | |
1056 | ||
c7aec596 TN |
1057 | xdp_prog = READ_ONCE(rx_ring->xdp_prog); |
1058 | ||
1059 | if (!xdp_prog) | |
1060 | goto xdp_out; | |
1061 | ||
1062 | act = bpf_prog_run_xdp(xdp_prog, xdp); | |
1063 | switch (act) { | |
1064 | case XDP_PASS: | |
1065 | break; | |
21092e9c TN |
1066 | case XDP_TX: |
1067 | xdp_ring = adapter->xdp_ring[rx_ring->queue_index]; | |
1068 | result = ixgbevf_xmit_xdp_ring(xdp_ring, xdp); | |
faae8142 MK |
1069 | if (result == IXGBEVF_XDP_CONSUMED) |
1070 | goto out_failure; | |
21092e9c | 1071 | break; |
c7aec596 | 1072 | default: |
c8064e5b | 1073 | bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act); |
5463fce6 | 1074 | fallthrough; |
c7aec596 | 1075 | case XDP_ABORTED: |
faae8142 | 1076 | out_failure: |
c7aec596 | 1077 | trace_xdp_exception(rx_ring->netdev, xdp_prog, act); |
5463fce6 | 1078 | fallthrough; /* handle aborts by dropping packet */ |
c7aec596 TN |
1079 | case XDP_DROP: |
1080 | result = IXGBEVF_XDP_CONSUMED; | |
1081 | break; | |
1082 | } | |
1083 | xdp_out: | |
35f715cb | 1084 | return result; |
c7aec596 TN |
1085 | } |
1086 | ||
81f3c628 JDB |
1087 | static unsigned int ixgbevf_rx_frame_truesize(struct ixgbevf_ring *rx_ring, |
1088 | unsigned int size) | |
1089 | { | |
1090 | unsigned int truesize; | |
1091 | ||
1092 | #if (PAGE_SIZE < 8192) | |
1093 | truesize = ixgbevf_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ | |
1094 | #else | |
1095 | truesize = ring_uses_build_skb(rx_ring) ? | |
1096 | SKB_DATA_ALIGN(IXGBEVF_SKB_PAD + size) + | |
1097 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : | |
1098 | SKB_DATA_ALIGN(size); | |
1099 | #endif | |
1100 | return truesize; | |
1101 | } | |
1102 | ||
21092e9c TN |
1103 | static void ixgbevf_rx_buffer_flip(struct ixgbevf_ring *rx_ring, |
1104 | struct ixgbevf_rx_buffer *rx_buffer, | |
1105 | unsigned int size) | |
1106 | { | |
81f3c628 | 1107 | unsigned int truesize = ixgbevf_rx_frame_truesize(rx_ring, size); |
21092e9c | 1108 | |
81f3c628 | 1109 | #if (PAGE_SIZE < 8192) |
21092e9c TN |
1110 | rx_buffer->page_offset ^= truesize; |
1111 | #else | |
21092e9c TN |
1112 | rx_buffer->page_offset += truesize; |
1113 | #endif | |
1114 | } | |
1115 | ||
08e50a20 JK |
1116 | static int ixgbevf_clean_rx_irq(struct ixgbevf_q_vector *q_vector, |
1117 | struct ixgbevf_ring *rx_ring, | |
1118 | int budget) | |
92915f71 | 1119 | { |
43b5169d | 1120 | unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0; |
21092e9c | 1121 | struct ixgbevf_adapter *adapter = q_vector->adapter; |
bafa578f | 1122 | u16 cleaned_count = ixgbevf_desc_unused(rx_ring); |
bad17234 | 1123 | struct sk_buff *skb = rx_ring->skb; |
efecfd5f | 1124 | bool xdp_xmit = false; |
c7aec596 | 1125 | struct xdp_buff xdp; |
35f715cb | 1126 | int xdp_res = 0; |
c7aec596 | 1127 | |
81f3c628 JDB |
1128 | /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ |
1129 | #if (PAGE_SIZE < 8192) | |
43b5169d | 1130 | frame_sz = ixgbevf_rx_frame_truesize(rx_ring, 0); |
81f3c628 | 1131 | #endif |
43b5169d | 1132 | xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); |
81f3c628 | 1133 | |
6622402a | 1134 | while (likely(total_rx_packets < budget)) { |
925f5690 | 1135 | struct ixgbevf_rx_buffer *rx_buffer; |
c7aec596 | 1136 | union ixgbe_adv_rx_desc *rx_desc; |
925f5690 | 1137 | unsigned int size; |
b97fe3b1 | 1138 | |
0579eefc ET |
1139 | /* return some buffers to hardware, one at a time is too slow */ |
1140 | if (cleaned_count >= IXGBEVF_RX_BUFFER_WRITE) { | |
1141 | ixgbevf_alloc_rx_buffers(rx_ring, cleaned_count); | |
1142 | cleaned_count = 0; | |
1143 | } | |
1144 | ||
bad17234 | 1145 | rx_desc = IXGBEVF_RX_DESC(rx_ring, rx_ring->next_to_clean); |
925f5690 ET |
1146 | size = le16_to_cpu(rx_desc->wb.upper.length); |
1147 | if (!size) | |
92915f71 | 1148 | break; |
92915f71 | 1149 | |
0579eefc ET |
1150 | /* This memory barrier is needed to keep us from reading |
1151 | * any other fields out of the rx_desc until we know the | |
1152 | * RXD_STAT_DD bit is set | |
1153 | */ | |
1154 | rmb(); | |
ec62fe26 | 1155 | |
925f5690 ET |
1156 | rx_buffer = ixgbevf_get_rx_buffer(rx_ring, size); |
1157 | ||
bad17234 | 1158 | /* retrieve a buffer from the ring */ |
c7aec596 | 1159 | if (!skb) { |
be9df4af LB |
1160 | unsigned int offset = ixgbevf_rx_offset(rx_ring); |
1161 | unsigned char *hard_start; | |
1162 | ||
1163 | hard_start = page_address(rx_buffer->page) + | |
1164 | rx_buffer->page_offset - offset; | |
1165 | xdp_prepare_buff(&xdp, hard_start, offset, size, true); | |
81f3c628 JDB |
1166 | #if (PAGE_SIZE > 4096) |
1167 | /* At larger PAGE_SIZE, frame_sz depend on len size */ | |
1168 | xdp.frame_sz = ixgbevf_rx_frame_truesize(rx_ring, size); | |
1169 | #endif | |
35f715cb | 1170 | xdp_res = ixgbevf_run_xdp(adapter, rx_ring, &xdp); |
c7aec596 TN |
1171 | } |
1172 | ||
35f715cb YH |
1173 | if (xdp_res) { |
1174 | if (xdp_res == IXGBEVF_XDP_TX) { | |
efecfd5f | 1175 | xdp_xmit = true; |
21092e9c TN |
1176 | ixgbevf_rx_buffer_flip(rx_ring, rx_buffer, |
1177 | size); | |
efecfd5f | 1178 | } else { |
21092e9c | 1179 | rx_buffer->pagecnt_bias++; |
efecfd5f | 1180 | } |
c7aec596 TN |
1181 | total_rx_packets++; |
1182 | total_rx_bytes += size; | |
c7aec596 | 1183 | } else if (skb) { |
925f5690 | 1184 | ixgbevf_add_rx_frag(rx_ring, rx_buffer, skb, size); |
c7aec596 | 1185 | } else if (ring_uses_build_skb(rx_ring)) { |
6d9c0217 | 1186 | skb = ixgbevf_build_skb(rx_ring, rx_buffer, |
c7aec596 TN |
1187 | &xdp, rx_desc); |
1188 | } else { | |
925f5690 | 1189 | skb = ixgbevf_construct_skb(rx_ring, rx_buffer, |
c7aec596 TN |
1190 | &xdp, rx_desc); |
1191 | } | |
0579eefc | 1192 | |
bad17234 | 1193 | /* exit if we failed to retrieve a buffer */ |
35f715cb | 1194 | if (!xdp_res && !skb) { |
2a35efe5 | 1195 | rx_ring->rx_stats.alloc_rx_buff_failed++; |
925f5690 | 1196 | rx_buffer->pagecnt_bias++; |
bad17234 | 1197 | break; |
2a35efe5 | 1198 | } |
92915f71 | 1199 | |
c7aec596 | 1200 | ixgbevf_put_rx_buffer(rx_ring, rx_buffer, skb); |
b97fe3b1 ET |
1201 | cleaned_count++; |
1202 | ||
bad17234 ET |
1203 | /* fetch next buffer in frame if non-eop */ |
1204 | if (ixgbevf_is_non_eop(rx_ring, rx_desc)) | |
0579eefc | 1205 | continue; |
5c60f81a | 1206 | |
bad17234 | 1207 | /* verify the packet layout is correct */ |
35f715cb | 1208 | if (xdp_res || ixgbevf_cleanup_headers(rx_ring, rx_desc, skb)) { |
bad17234 | 1209 | skb = NULL; |
0579eefc | 1210 | continue; |
92915f71 GR |
1211 | } |
1212 | ||
92915f71 GR |
1213 | /* probably a little skewed due to removing CRC */ |
1214 | total_rx_bytes += skb->len; | |
92915f71 | 1215 | |
815cccbf JF |
1216 | /* Workaround hardware that can't do proper VEPA multicast |
1217 | * source pruning. | |
1218 | */ | |
bd9d5592 | 1219 | if ((skb->pkt_type == PACKET_BROADCAST || |
dec0d8e4 | 1220 | skb->pkt_type == PACKET_MULTICAST) && |
095e2617 | 1221 | ether_addr_equal(rx_ring->netdev->dev_addr, |
7367d0b5 | 1222 | eth_hdr(skb)->h_source)) { |
815cccbf | 1223 | dev_kfree_skb_irq(skb); |
0579eefc | 1224 | continue; |
815cccbf JF |
1225 | } |
1226 | ||
dff80520 ET |
1227 | /* populate checksum, VLAN, and protocol */ |
1228 | ixgbevf_process_skb_fields(rx_ring, rx_desc, skb); | |
1229 | ||
1230 | ixgbevf_rx_skb(q_vector, skb); | |
92915f71 | 1231 | |
bad17234 ET |
1232 | /* reset skb pointer */ |
1233 | skb = NULL; | |
1234 | ||
0579eefc | 1235 | /* update budget accounting */ |
6622402a ET |
1236 | total_rx_packets++; |
1237 | } | |
92915f71 | 1238 | |
bad17234 ET |
1239 | /* place incomplete frames back on ring for completion */ |
1240 | rx_ring->skb = skb; | |
1241 | ||
efecfd5f TN |
1242 | if (xdp_xmit) { |
1243 | struct ixgbevf_ring *xdp_ring = | |
1244 | adapter->xdp_ring[rx_ring->queue_index]; | |
1245 | ||
1246 | /* Force memory writes to complete before letting h/w | |
1247 | * know there are new descriptors to fetch. | |
1248 | */ | |
1249 | wmb(); | |
1250 | ixgbevf_write_tail(xdp_ring, xdp_ring->next_to_use); | |
1251 | } | |
1252 | ||
4197aa7b | 1253 | u64_stats_update_begin(&rx_ring->syncp); |
095e2617 ET |
1254 | rx_ring->stats.packets += total_rx_packets; |
1255 | rx_ring->stats.bytes += total_rx_bytes; | |
4197aa7b | 1256 | u64_stats_update_end(&rx_ring->syncp); |
ac6ed8f0 GR |
1257 | q_vector->rx.total_packets += total_rx_packets; |
1258 | q_vector->rx.total_bytes += total_rx_bytes; | |
92915f71 | 1259 | |
08e50a20 | 1260 | return total_rx_packets; |
92915f71 GR |
1261 | } |
1262 | ||
1263 | /** | |
fa71ae27 | 1264 | * ixgbevf_poll - NAPI polling calback |
92915f71 GR |
1265 | * @napi: napi struct with our devices info in it |
1266 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1267 | * | |
fa71ae27 | 1268 | * This function will clean more than one or more rings associated with a |
92915f71 GR |
1269 | * q_vector. |
1270 | **/ | |
fa71ae27 | 1271 | static int ixgbevf_poll(struct napi_struct *napi, int budget) |
92915f71 GR |
1272 | { |
1273 | struct ixgbevf_q_vector *q_vector = | |
1274 | container_of(napi, struct ixgbevf_q_vector, napi); | |
1275 | struct ixgbevf_adapter *adapter = q_vector->adapter; | |
fa71ae27 | 1276 | struct ixgbevf_ring *ring; |
32b3e08f | 1277 | int per_ring_budget, work_done = 0; |
fa71ae27 AD |
1278 | bool clean_complete = true; |
1279 | ||
8220bbc1 AD |
1280 | ixgbevf_for_each_ring(ring, q_vector->tx) { |
1281 | if (!ixgbevf_clean_tx_irq(q_vector, ring, budget)) | |
1282 | clean_complete = false; | |
1283 | } | |
92915f71 | 1284 | |
d0f71aff WD |
1285 | if (budget <= 0) |
1286 | return budget; | |
c777cdfa | 1287 | |
92915f71 | 1288 | /* attempt to distribute budget to each queue fairly, but don't allow |
dec0d8e4 JK |
1289 | * the budget to go below 1 because we'll exit polling |
1290 | */ | |
fa71ae27 AD |
1291 | if (q_vector->rx.count > 1) |
1292 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
1293 | else | |
1294 | per_ring_budget = budget; | |
1295 | ||
32b3e08f JB |
1296 | ixgbevf_for_each_ring(ring, q_vector->rx) { |
1297 | int cleaned = ixgbevf_clean_rx_irq(q_vector, ring, | |
1298 | per_ring_budget); | |
1299 | work_done += cleaned; | |
8220bbc1 AD |
1300 | if (cleaned >= per_ring_budget) |
1301 | clean_complete = false; | |
32b3e08f | 1302 | } |
fa71ae27 AD |
1303 | |
1304 | /* If all work not completed, return budget and keep polling */ | |
1305 | if (!clean_complete) | |
1306 | return budget; | |
92915f71 | 1307 | |
0bcd952f JB |
1308 | /* Exit the polling mode, but don't re-enable interrupts if stack might |
1309 | * poll us due to busy-polling | |
1310 | */ | |
1311 | if (likely(napi_complete_done(napi, work_done))) { | |
1312 | if (adapter->rx_itr_setting == 1) | |
1313 | ixgbevf_set_itr(q_vector); | |
1314 | if (!test_bit(__IXGBEVF_DOWN, &adapter->state) && | |
1315 | !test_bit(__IXGBEVF_REMOVING, &adapter->state)) | |
1316 | ixgbevf_irq_enable_queues(adapter, | |
1317 | BIT(q_vector->v_idx)); | |
1318 | } | |
1319 | ||
1320 | return min(work_done, budget - 1); | |
92915f71 GR |
1321 | } |
1322 | ||
ce422606 GR |
1323 | /** |
1324 | * ixgbevf_write_eitr - write VTEITR register in hardware specific way | |
1325 | * @q_vector: structure containing interrupt and ring information | |
dec0d8e4 | 1326 | **/ |
3849623e | 1327 | void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector) |
ce422606 GR |
1328 | { |
1329 | struct ixgbevf_adapter *adapter = q_vector->adapter; | |
1330 | struct ixgbe_hw *hw = &adapter->hw; | |
1331 | int v_idx = q_vector->v_idx; | |
1332 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; | |
1333 | ||
dec0d8e4 | 1334 | /* set the WDIS bit to not clear the timer bits and cause an |
ce422606 GR |
1335 | * immediate assertion of the interrupt |
1336 | */ | |
1337 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
1338 | ||
1339 | IXGBE_WRITE_REG(hw, IXGBE_VTEITR(v_idx), itr_reg); | |
1340 | } | |
92915f71 GR |
1341 | |
1342 | /** | |
1343 | * ixgbevf_configure_msix - Configure MSI-X hardware | |
1344 | * @adapter: board private structure | |
1345 | * | |
1346 | * ixgbevf_configure_msix sets up the hardware to properly generate MSI-X | |
1347 | * interrupts. | |
1348 | **/ | |
1349 | static void ixgbevf_configure_msix(struct ixgbevf_adapter *adapter) | |
1350 | { | |
1351 | struct ixgbevf_q_vector *q_vector; | |
6b43c446 | 1352 | int q_vectors, v_idx; |
92915f71 GR |
1353 | |
1354 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
5f3600eb | 1355 | adapter->eims_enable_mask = 0; |
92915f71 | 1356 | |
dec0d8e4 | 1357 | /* Populate the IVAR table and set the ITR values to the |
92915f71 GR |
1358 | * corresponding register. |
1359 | */ | |
1360 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
6b43c446 | 1361 | struct ixgbevf_ring *ring; |
dec0d8e4 | 1362 | |
92915f71 | 1363 | q_vector = adapter->q_vector[v_idx]; |
6b43c446 AD |
1364 | |
1365 | ixgbevf_for_each_ring(ring, q_vector->rx) | |
1366 | ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx); | |
1367 | ||
1368 | ixgbevf_for_each_ring(ring, q_vector->tx) | |
1369 | ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx); | |
92915f71 | 1370 | |
5f3600eb | 1371 | if (q_vector->tx.ring && !q_vector->rx.ring) { |
dec0d8e4 | 1372 | /* Tx only vector */ |
5f3600eb | 1373 | if (adapter->tx_itr_setting == 1) |
8a9ca110 | 1374 | q_vector->itr = IXGBE_12K_ITR; |
5f3600eb AD |
1375 | else |
1376 | q_vector->itr = adapter->tx_itr_setting; | |
1377 | } else { | |
dec0d8e4 | 1378 | /* Rx or Rx/Tx vector */ |
5f3600eb AD |
1379 | if (adapter->rx_itr_setting == 1) |
1380 | q_vector->itr = IXGBE_20K_ITR; | |
1381 | else | |
1382 | q_vector->itr = adapter->rx_itr_setting; | |
1383 | } | |
1384 | ||
1385 | /* add q_vector eims value to global eims_enable_mask */ | |
8d055cc0 | 1386 | adapter->eims_enable_mask |= BIT(v_idx); |
92915f71 | 1387 | |
5f3600eb | 1388 | ixgbevf_write_eitr(q_vector); |
92915f71 GR |
1389 | } |
1390 | ||
1391 | ixgbevf_set_ivar(adapter, -1, 1, v_idx); | |
5f3600eb | 1392 | /* setup eims_other and add value to global eims_enable_mask */ |
8d055cc0 | 1393 | adapter->eims_other = BIT(v_idx); |
5f3600eb | 1394 | adapter->eims_enable_mask |= adapter->eims_other; |
92915f71 GR |
1395 | } |
1396 | ||
1397 | enum latency_range { | |
1398 | lowest_latency = 0, | |
1399 | low_latency = 1, | |
1400 | bulk_latency = 2, | |
1401 | latency_invalid = 255 | |
1402 | }; | |
1403 | ||
1404 | /** | |
1405 | * ixgbevf_update_itr - update the dynamic ITR value based on statistics | |
5f3600eb AD |
1406 | * @q_vector: structure containing interrupt and ring information |
1407 | * @ring_container: structure containing ring performance data | |
92915f71 | 1408 | * |
dec0d8e4 JK |
1409 | * Stores a new ITR value based on packets and byte |
1410 | * counts during the last interrupt. The advantage of per interrupt | |
1411 | * computation is faster updates and more accurate ITR for the current | |
1412 | * traffic pattern. Constants in this function were computed | |
1413 | * based on theoretical maximum wire speed and thresholds were set based | |
1414 | * on testing data as well as attempting to minimize response time | |
1415 | * while increasing bulk throughput. | |
92915f71 | 1416 | **/ |
5f3600eb AD |
1417 | static void ixgbevf_update_itr(struct ixgbevf_q_vector *q_vector, |
1418 | struct ixgbevf_ring_container *ring_container) | |
92915f71 | 1419 | { |
5f3600eb AD |
1420 | int bytes = ring_container->total_bytes; |
1421 | int packets = ring_container->total_packets; | |
92915f71 GR |
1422 | u32 timepassed_us; |
1423 | u64 bytes_perint; | |
5f3600eb | 1424 | u8 itr_setting = ring_container->itr; |
92915f71 GR |
1425 | |
1426 | if (packets == 0) | |
5f3600eb | 1427 | return; |
92915f71 | 1428 | |
dec0d8e4 | 1429 | /* simple throttle rate management |
92915f71 GR |
1430 | * 0-20MB/s lowest (100000 ints/s) |
1431 | * 20-100MB/s low (20000 ints/s) | |
8a9ca110 | 1432 | * 100-1249MB/s bulk (12000 ints/s) |
92915f71 GR |
1433 | */ |
1434 | /* what was last interrupt timeslice? */ | |
5f3600eb | 1435 | timepassed_us = q_vector->itr >> 2; |
e0f0be7d YX |
1436 | if (timepassed_us == 0) |
1437 | return; | |
1438 | ||
92915f71 GR |
1439 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
1440 | ||
1441 | switch (itr_setting) { | |
1442 | case lowest_latency: | |
e2c28ce7 | 1443 | if (bytes_perint > 10) |
5f3600eb | 1444 | itr_setting = low_latency; |
92915f71 GR |
1445 | break; |
1446 | case low_latency: | |
e2c28ce7 | 1447 | if (bytes_perint > 20) |
5f3600eb | 1448 | itr_setting = bulk_latency; |
e2c28ce7 | 1449 | else if (bytes_perint <= 10) |
5f3600eb | 1450 | itr_setting = lowest_latency; |
92915f71 GR |
1451 | break; |
1452 | case bulk_latency: | |
e2c28ce7 | 1453 | if (bytes_perint <= 20) |
5f3600eb | 1454 | itr_setting = low_latency; |
92915f71 GR |
1455 | break; |
1456 | } | |
1457 | ||
5f3600eb AD |
1458 | /* clear work counters since we have the values we need */ |
1459 | ring_container->total_bytes = 0; | |
1460 | ring_container->total_packets = 0; | |
1461 | ||
1462 | /* write updated itr to ring container */ | |
1463 | ring_container->itr = itr_setting; | |
92915f71 GR |
1464 | } |
1465 | ||
fa71ae27 | 1466 | static void ixgbevf_set_itr(struct ixgbevf_q_vector *q_vector) |
92915f71 | 1467 | { |
5f3600eb AD |
1468 | u32 new_itr = q_vector->itr; |
1469 | u8 current_itr; | |
92915f71 | 1470 | |
5f3600eb AD |
1471 | ixgbevf_update_itr(q_vector, &q_vector->tx); |
1472 | ixgbevf_update_itr(q_vector, &q_vector->rx); | |
92915f71 | 1473 | |
6b43c446 | 1474 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
92915f71 GR |
1475 | |
1476 | switch (current_itr) { | |
1477 | /* counts and packets in update_itr are dependent on these numbers */ | |
1478 | case lowest_latency: | |
5f3600eb | 1479 | new_itr = IXGBE_100K_ITR; |
92915f71 GR |
1480 | break; |
1481 | case low_latency: | |
5f3600eb | 1482 | new_itr = IXGBE_20K_ITR; |
92915f71 GR |
1483 | break; |
1484 | case bulk_latency: | |
8a9ca110 | 1485 | new_itr = IXGBE_12K_ITR; |
92915f71 | 1486 | break; |
9ad3d6f7 ET |
1487 | default: |
1488 | break; | |
92915f71 GR |
1489 | } |
1490 | ||
5f3600eb | 1491 | if (new_itr != q_vector->itr) { |
92915f71 | 1492 | /* do an exponential smoothing */ |
5f3600eb AD |
1493 | new_itr = (10 * new_itr * q_vector->itr) / |
1494 | ((9 * new_itr) + q_vector->itr); | |
1495 | ||
1496 | /* save the algorithm value here */ | |
1497 | q_vector->itr = new_itr; | |
1498 | ||
1499 | ixgbevf_write_eitr(q_vector); | |
92915f71 | 1500 | } |
92915f71 GR |
1501 | } |
1502 | ||
4b2cd27f | 1503 | static irqreturn_t ixgbevf_msix_other(int irq, void *data) |
92915f71 | 1504 | { |
fa71ae27 | 1505 | struct ixgbevf_adapter *adapter = data; |
92915f71 | 1506 | struct ixgbe_hw *hw = &adapter->hw; |
08259594 | 1507 | |
4b2cd27f | 1508 | hw->mac.get_link_status = 1; |
1e72bfc3 | 1509 | |
9ac5c5cc | 1510 | ixgbevf_service_event_schedule(adapter); |
3a2c4033 | 1511 | |
5f3600eb AD |
1512 | IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, adapter->eims_other); |
1513 | ||
92915f71 GR |
1514 | return IRQ_HANDLED; |
1515 | } | |
1516 | ||
92915f71 | 1517 | /** |
fa71ae27 | 1518 | * ixgbevf_msix_clean_rings - single unshared vector rx clean (all queues) |
92915f71 GR |
1519 | * @irq: unused |
1520 | * @data: pointer to our q_vector struct for this interrupt vector | |
1521 | **/ | |
fa71ae27 | 1522 | static irqreturn_t ixgbevf_msix_clean_rings(int irq, void *data) |
92915f71 GR |
1523 | { |
1524 | struct ixgbevf_q_vector *q_vector = data; | |
92915f71 | 1525 | |
5f3600eb | 1526 | /* EIAM disabled interrupts (on this vector) for us */ |
fa71ae27 | 1527 | if (q_vector->rx.ring || q_vector->tx.ring) |
ef2662b2 | 1528 | napi_schedule_irqoff(&q_vector->napi); |
92915f71 GR |
1529 | |
1530 | return IRQ_HANDLED; | |
1531 | } | |
1532 | ||
92915f71 GR |
1533 | /** |
1534 | * ixgbevf_request_msix_irqs - Initialize MSI-X interrupts | |
1535 | * @adapter: board private structure | |
1536 | * | |
1537 | * ixgbevf_request_msix_irqs allocates MSI-X vectors and requests | |
1538 | * interrupts from the kernel. | |
1539 | **/ | |
1540 | static int ixgbevf_request_msix_irqs(struct ixgbevf_adapter *adapter) | |
1541 | { | |
1542 | struct net_device *netdev = adapter->netdev; | |
fa71ae27 | 1543 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
31f5d9b1 | 1544 | unsigned int ri = 0, ti = 0; |
fa71ae27 | 1545 | int vector, err; |
92915f71 | 1546 | |
92915f71 | 1547 | for (vector = 0; vector < q_vectors; vector++) { |
fa71ae27 AD |
1548 | struct ixgbevf_q_vector *q_vector = adapter->q_vector[vector]; |
1549 | struct msix_entry *entry = &adapter->msix_entries[vector]; | |
1550 | ||
1551 | if (q_vector->tx.ring && q_vector->rx.ring) { | |
31f5d9b1 TN |
1552 | snprintf(q_vector->name, sizeof(q_vector->name), |
1553 | "%s-TxRx-%u", netdev->name, ri++); | |
fa71ae27 AD |
1554 | ti++; |
1555 | } else if (q_vector->rx.ring) { | |
31f5d9b1 TN |
1556 | snprintf(q_vector->name, sizeof(q_vector->name), |
1557 | "%s-rx-%u", netdev->name, ri++); | |
fa71ae27 | 1558 | } else if (q_vector->tx.ring) { |
31f5d9b1 TN |
1559 | snprintf(q_vector->name, sizeof(q_vector->name), |
1560 | "%s-tx-%u", netdev->name, ti++); | |
92915f71 GR |
1561 | } else { |
1562 | /* skip this unused q_vector */ | |
1563 | continue; | |
1564 | } | |
fa71ae27 AD |
1565 | err = request_irq(entry->vector, &ixgbevf_msix_clean_rings, 0, |
1566 | q_vector->name, q_vector); | |
92915f71 GR |
1567 | if (err) { |
1568 | hw_dbg(&adapter->hw, | |
dec0d8e4 JK |
1569 | "request_irq failed for MSIX interrupt Error: %d\n", |
1570 | err); | |
92915f71 GR |
1571 | goto free_queue_irqs; |
1572 | } | |
1573 | } | |
1574 | ||
92915f71 | 1575 | err = request_irq(adapter->msix_entries[vector].vector, |
4b2cd27f | 1576 | &ixgbevf_msix_other, 0, netdev->name, adapter); |
92915f71 | 1577 | if (err) { |
dec0d8e4 JK |
1578 | hw_dbg(&adapter->hw, "request_irq for msix_other failed: %d\n", |
1579 | err); | |
92915f71 GR |
1580 | goto free_queue_irqs; |
1581 | } | |
1582 | ||
1583 | return 0; | |
1584 | ||
1585 | free_queue_irqs: | |
fa71ae27 AD |
1586 | while (vector) { |
1587 | vector--; | |
1588 | free_irq(adapter->msix_entries[vector].vector, | |
1589 | adapter->q_vector[vector]); | |
1590 | } | |
a1f6c6b1 | 1591 | /* This failure is non-recoverable - it indicates the system is |
1592 | * out of MSIX vector resources and the VF driver cannot run | |
1593 | * without them. Set the number of msix vectors to zero | |
1594 | * indicating that not enough can be allocated. The error | |
1595 | * will be returned to the user indicating device open failed. | |
1596 | * Any further attempts to force the driver to open will also | |
1597 | * fail. The only way to recover is to unload the driver and | |
1598 | * reload it again. If the system has recovered some MSIX | |
1599 | * vectors then it may succeed. | |
1600 | */ | |
1601 | adapter->num_msix_vectors = 0; | |
92915f71 GR |
1602 | return err; |
1603 | } | |
1604 | ||
92915f71 GR |
1605 | /** |
1606 | * ixgbevf_request_irq - initialize interrupts | |
1607 | * @adapter: board private structure | |
1608 | * | |
1609 | * Attempts to configure interrupts using the best available | |
1610 | * capabilities of the hardware and kernel. | |
1611 | **/ | |
1612 | static int ixgbevf_request_irq(struct ixgbevf_adapter *adapter) | |
1613 | { | |
50985b5f | 1614 | int err = ixgbevf_request_msix_irqs(adapter); |
92915f71 GR |
1615 | |
1616 | if (err) | |
dec0d8e4 | 1617 | hw_dbg(&adapter->hw, "request_irq failed, Error %d\n", err); |
92915f71 GR |
1618 | |
1619 | return err; | |
1620 | } | |
1621 | ||
1622 | static void ixgbevf_free_irq(struct ixgbevf_adapter *adapter) | |
1623 | { | |
92915f71 GR |
1624 | int i, q_vectors; |
1625 | ||
eeffceee MR |
1626 | if (!adapter->msix_entries) |
1627 | return; | |
1628 | ||
92915f71 | 1629 | q_vectors = adapter->num_msix_vectors; |
92915f71 GR |
1630 | i = q_vectors - 1; |
1631 | ||
fa71ae27 | 1632 | free_irq(adapter->msix_entries[i].vector, adapter); |
92915f71 GR |
1633 | i--; |
1634 | ||
1635 | for (; i >= 0; i--) { | |
fa71ae27 AD |
1636 | /* free only the irqs that were actually requested */ |
1637 | if (!adapter->q_vector[i]->rx.ring && | |
1638 | !adapter->q_vector[i]->tx.ring) | |
1639 | continue; | |
1640 | ||
92915f71 GR |
1641 | free_irq(adapter->msix_entries[i].vector, |
1642 | adapter->q_vector[i]); | |
1643 | } | |
92915f71 GR |
1644 | } |
1645 | ||
1646 | /** | |
1647 | * ixgbevf_irq_disable - Mask off interrupt generation on the NIC | |
1648 | * @adapter: board private structure | |
1649 | **/ | |
1650 | static inline void ixgbevf_irq_disable(struct ixgbevf_adapter *adapter) | |
1651 | { | |
92915f71 | 1652 | struct ixgbe_hw *hw = &adapter->hw; |
5f3600eb | 1653 | int i; |
92915f71 | 1654 | |
5f3600eb | 1655 | IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, 0); |
92915f71 | 1656 | IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, ~0); |
5f3600eb | 1657 | IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, 0); |
92915f71 GR |
1658 | |
1659 | IXGBE_WRITE_FLUSH(hw); | |
1660 | ||
1661 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1662 | synchronize_irq(adapter->msix_entries[i].vector); | |
1663 | } | |
1664 | ||
1665 | /** | |
1666 | * ixgbevf_irq_enable - Enable default interrupt generation settings | |
1667 | * @adapter: board private structure | |
1668 | **/ | |
5f3600eb | 1669 | static inline void ixgbevf_irq_enable(struct ixgbevf_adapter *adapter) |
92915f71 GR |
1670 | { |
1671 | struct ixgbe_hw *hw = &adapter->hw; | |
92915f71 | 1672 | |
5f3600eb AD |
1673 | IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, adapter->eims_enable_mask); |
1674 | IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, adapter->eims_enable_mask); | |
1675 | IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, adapter->eims_enable_mask); | |
92915f71 GR |
1676 | } |
1677 | ||
de02decb DS |
1678 | /** |
1679 | * ixgbevf_configure_tx_ring - Configure 82599 VF Tx ring after Reset | |
1680 | * @adapter: board private structure | |
1681 | * @ring: structure containing ring specific data | |
1682 | * | |
1683 | * Configure the Tx descriptor ring after a reset. | |
1684 | **/ | |
1685 | static void ixgbevf_configure_tx_ring(struct ixgbevf_adapter *adapter, | |
1686 | struct ixgbevf_ring *ring) | |
1687 | { | |
1688 | struct ixgbe_hw *hw = &adapter->hw; | |
1689 | u64 tdba = ring->dma; | |
1690 | int wait_loop = 10; | |
1691 | u32 txdctl = IXGBE_TXDCTL_ENABLE; | |
1692 | u8 reg_idx = ring->reg_idx; | |
1693 | ||
1694 | /* disable queue to avoid issues while updating state */ | |
1695 | IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); | |
1696 | IXGBE_WRITE_FLUSH(hw); | |
1697 | ||
1698 | IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); | |
1699 | IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(reg_idx), tdba >> 32); | |
1700 | IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(reg_idx), | |
1701 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
1702 | ||
1703 | /* disable head writeback */ | |
1704 | IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(reg_idx), 0); | |
1705 | IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(reg_idx), 0); | |
1706 | ||
1707 | /* enable relaxed ordering */ | |
1708 | IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(reg_idx), | |
1709 | (IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
1710 | IXGBE_DCA_TXCTRL_DATA_RRO_EN)); | |
1711 | ||
1712 | /* reset head and tail pointers */ | |
1713 | IXGBE_WRITE_REG(hw, IXGBE_VFTDH(reg_idx), 0); | |
1714 | IXGBE_WRITE_REG(hw, IXGBE_VFTDT(reg_idx), 0); | |
dbf8b0d8 | 1715 | ring->tail = adapter->io_addr + IXGBE_VFTDT(reg_idx); |
de02decb DS |
1716 | |
1717 | /* reset ntu and ntc to place SW in sync with hardwdare */ | |
1718 | ring->next_to_clean = 0; | |
1719 | ring->next_to_use = 0; | |
1720 | ||
1721 | /* In order to avoid issues WTHRESH + PTHRESH should always be equal | |
1722 | * to or less than the number of on chip descriptors, which is | |
1723 | * currently 40. | |
1724 | */ | |
1725 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
1726 | ||
1727 | /* Setting PTHRESH to 32 both improves performance */ | |
8d055cc0 JK |
1728 | txdctl |= (1u << 8) | /* HTHRESH = 1 */ |
1729 | 32; /* PTHRESH = 32 */ | |
de02decb | 1730 | |
865a4d98 ET |
1731 | /* reinitialize tx_buffer_info */ |
1732 | memset(ring->tx_buffer_info, 0, | |
1733 | sizeof(struct ixgbevf_tx_buffer) * ring->count); | |
1734 | ||
e08400b7 | 1735 | clear_bit(__IXGBEVF_HANG_CHECK_ARMED, &ring->state); |
4be87727 | 1736 | clear_bit(__IXGBEVF_TX_XDP_RING_PRIMED, &ring->state); |
e08400b7 | 1737 | |
de02decb DS |
1738 | IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), txdctl); |
1739 | ||
1740 | /* poll to verify queue is enabled */ | |
1741 | do { | |
1742 | usleep_range(1000, 2000); | |
1743 | txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(reg_idx)); | |
1744 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
1745 | if (!wait_loop) | |
ee95053f | 1746 | hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); |
de02decb DS |
1747 | } |
1748 | ||
92915f71 GR |
1749 | /** |
1750 | * ixgbevf_configure_tx - Configure 82599 VF Transmit Unit after Reset | |
1751 | * @adapter: board private structure | |
1752 | * | |
1753 | * Configure the Tx unit of the MAC after a reset. | |
1754 | **/ | |
1755 | static void ixgbevf_configure_tx(struct ixgbevf_adapter *adapter) | |
1756 | { | |
de02decb | 1757 | u32 i; |
92915f71 GR |
1758 | |
1759 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
de02decb DS |
1760 | for (i = 0; i < adapter->num_tx_queues; i++) |
1761 | ixgbevf_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
21092e9c TN |
1762 | for (i = 0; i < adapter->num_xdp_queues; i++) |
1763 | ixgbevf_configure_tx_ring(adapter, adapter->xdp_ring[i]); | |
92915f71 GR |
1764 | } |
1765 | ||
1766 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 | |
1767 | ||
f15c5ba5 ET |
1768 | static void ixgbevf_configure_srrctl(struct ixgbevf_adapter *adapter, |
1769 | struct ixgbevf_ring *ring, int index) | |
92915f71 | 1770 | { |
92915f71 GR |
1771 | struct ixgbe_hw *hw = &adapter->hw; |
1772 | u32 srrctl; | |
1773 | ||
92915f71 GR |
1774 | srrctl = IXGBE_SRRCTL_DROP_EN; |
1775 | ||
bad17234 | 1776 | srrctl |= IXGBEVF_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; |
f15c5ba5 ET |
1777 | if (ring_uses_large_buffer(ring)) |
1778 | srrctl |= IXGBEVF_RXBUFFER_3072 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1779 | else | |
1780 | srrctl |= IXGBEVF_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
77d5dfca | 1781 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
92915f71 | 1782 | |
92915f71 GR |
1783 | IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(index), srrctl); |
1784 | } | |
1785 | ||
1bb9c639 DS |
1786 | static void ixgbevf_setup_psrtype(struct ixgbevf_adapter *adapter) |
1787 | { | |
1788 | struct ixgbe_hw *hw = &adapter->hw; | |
1789 | ||
1790 | /* PSRTYPE must be initialized in 82599 */ | |
1791 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | IXGBE_PSRTYPE_UDPHDR | | |
1792 | IXGBE_PSRTYPE_IPV4HDR | IXGBE_PSRTYPE_IPV6HDR | | |
1793 | IXGBE_PSRTYPE_L2HDR; | |
1794 | ||
1795 | if (adapter->num_rx_queues > 1) | |
8d055cc0 | 1796 | psrtype |= BIT(29); |
1bb9c639 DS |
1797 | |
1798 | IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype); | |
1799 | } | |
1800 | ||
de02decb DS |
1801 | #define IXGBEVF_MAX_RX_DESC_POLL 10 |
1802 | static void ixgbevf_disable_rx_queue(struct ixgbevf_adapter *adapter, | |
1803 | struct ixgbevf_ring *ring) | |
1804 | { | |
1805 | struct ixgbe_hw *hw = &adapter->hw; | |
1806 | int wait_loop = IXGBEVF_MAX_RX_DESC_POLL; | |
1807 | u32 rxdctl; | |
1808 | u8 reg_idx = ring->reg_idx; | |
1809 | ||
26597802 MR |
1810 | if (IXGBE_REMOVED(hw->hw_addr)) |
1811 | return; | |
de02decb DS |
1812 | rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); |
1813 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
1814 | ||
1815 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
1816 | IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl); | |
1817 | ||
dec0d8e4 | 1818 | /* the hardware may take up to 100us to really disable the Rx queue */ |
de02decb DS |
1819 | do { |
1820 | udelay(10); | |
1821 | rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); | |
1822 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
1823 | ||
1824 | if (!wait_loop) | |
1825 | pr_err("RXDCTL.ENABLE queue %d not cleared while polling\n", | |
1826 | reg_idx); | |
1827 | } | |
1828 | ||
1829 | static void ixgbevf_rx_desc_queue_enable(struct ixgbevf_adapter *adapter, | |
1830 | struct ixgbevf_ring *ring) | |
1831 | { | |
1832 | struct ixgbe_hw *hw = &adapter->hw; | |
1833 | int wait_loop = IXGBEVF_MAX_RX_DESC_POLL; | |
1834 | u32 rxdctl; | |
1835 | u8 reg_idx = ring->reg_idx; | |
1836 | ||
26597802 MR |
1837 | if (IXGBE_REMOVED(hw->hw_addr)) |
1838 | return; | |
de02decb DS |
1839 | do { |
1840 | usleep_range(1000, 2000); | |
1841 | rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); | |
1842 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
1843 | ||
1844 | if (!wait_loop) | |
1845 | pr_err("RXDCTL.ENABLE queue %d not set while polling\n", | |
1846 | reg_idx); | |
1847 | } | |
1848 | ||
e60ae003 TN |
1849 | /** |
1850 | * ixgbevf_init_rss_key - Initialize adapter RSS key | |
1851 | * @adapter: device handle | |
1852 | * | |
1853 | * Allocates and initializes the RSS key if it is not allocated. | |
1854 | **/ | |
1855 | static inline int ixgbevf_init_rss_key(struct ixgbevf_adapter *adapter) | |
1856 | { | |
1857 | u32 *rss_key; | |
1858 | ||
1859 | if (!adapter->rss_key) { | |
1860 | rss_key = kzalloc(IXGBEVF_RSS_HASH_KEY_SIZE, GFP_KERNEL); | |
1861 | if (unlikely(!rss_key)) | |
1862 | return -ENOMEM; | |
1863 | ||
1864 | netdev_rss_key_fill(rss_key, IXGBEVF_RSS_HASH_KEY_SIZE); | |
1865 | adapter->rss_key = rss_key; | |
1866 | } | |
1867 | ||
1868 | return 0; | |
1869 | } | |
1870 | ||
9295edb4 ET |
1871 | static void ixgbevf_setup_vfmrqc(struct ixgbevf_adapter *adapter) |
1872 | { | |
1873 | struct ixgbe_hw *hw = &adapter->hw; | |
1874 | u32 vfmrqc = 0, vfreta = 0; | |
9295edb4 | 1875 | u16 rss_i = adapter->num_rx_queues; |
9cba434f | 1876 | u8 i, j; |
9295edb4 ET |
1877 | |
1878 | /* Fill out hash function seeds */ | |
9cba434f | 1879 | for (i = 0; i < IXGBEVF_VFRSSRK_REGS; i++) |
e60ae003 | 1880 | IXGBE_WRITE_REG(hw, IXGBE_VFRSSRK(i), *(adapter->rss_key + i)); |
9295edb4 | 1881 | |
9cba434f | 1882 | for (i = 0, j = 0; i < IXGBEVF_X550_VFRETA_SIZE; i++, j++) { |
9295edb4 ET |
1883 | if (j == rss_i) |
1884 | j = 0; | |
9cba434f ET |
1885 | |
1886 | adapter->rss_indir_tbl[i] = j; | |
1887 | ||
1888 | vfreta |= j << (i & 0x3) * 8; | |
1889 | if ((i & 3) == 3) { | |
9295edb4 | 1890 | IXGBE_WRITE_REG(hw, IXGBE_VFRETA(i >> 2), vfreta); |
9cba434f ET |
1891 | vfreta = 0; |
1892 | } | |
9295edb4 ET |
1893 | } |
1894 | ||
1895 | /* Perform hash on these packet types */ | |
1896 | vfmrqc |= IXGBE_VFMRQC_RSS_FIELD_IPV4 | | |
1897 | IXGBE_VFMRQC_RSS_FIELD_IPV4_TCP | | |
1898 | IXGBE_VFMRQC_RSS_FIELD_IPV6 | | |
1899 | IXGBE_VFMRQC_RSS_FIELD_IPV6_TCP; | |
1900 | ||
1901 | vfmrqc |= IXGBE_VFMRQC_RSSEN; | |
1902 | ||
1903 | IXGBE_WRITE_REG(hw, IXGBE_VFMRQC, vfmrqc); | |
1904 | } | |
1905 | ||
de02decb DS |
1906 | static void ixgbevf_configure_rx_ring(struct ixgbevf_adapter *adapter, |
1907 | struct ixgbevf_ring *ring) | |
1908 | { | |
1909 | struct ixgbe_hw *hw = &adapter->hw; | |
24bff091 | 1910 | union ixgbe_adv_rx_desc *rx_desc; |
de02decb DS |
1911 | u64 rdba = ring->dma; |
1912 | u32 rxdctl; | |
1913 | u8 reg_idx = ring->reg_idx; | |
1914 | ||
1915 | /* disable queue to avoid issues while updating state */ | |
1916 | rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); | |
1917 | ixgbevf_disable_rx_queue(adapter, ring); | |
1918 | ||
1919 | IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(reg_idx), rdba & DMA_BIT_MASK(32)); | |
1920 | IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(reg_idx), rdba >> 32); | |
1921 | IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(reg_idx), | |
1922 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
1923 | ||
33b0eb15 | 1924 | #ifndef CONFIG_SPARC |
de02decb DS |
1925 | /* enable relaxed ordering */ |
1926 | IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(reg_idx), | |
1927 | IXGBE_DCA_RXCTRL_DESC_RRO_EN); | |
33b0eb15 BM |
1928 | #else |
1929 | IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(reg_idx), | |
1930 | IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
1931 | IXGBE_DCA_RXCTRL_DATA_WRO_EN); | |
1932 | #endif | |
de02decb DS |
1933 | |
1934 | /* reset head and tail pointers */ | |
1935 | IXGBE_WRITE_REG(hw, IXGBE_VFRDH(reg_idx), 0); | |
1936 | IXGBE_WRITE_REG(hw, IXGBE_VFRDT(reg_idx), 0); | |
dbf8b0d8 | 1937 | ring->tail = adapter->io_addr + IXGBE_VFRDT(reg_idx); |
de02decb | 1938 | |
40b8178b ET |
1939 | /* initialize rx_buffer_info */ |
1940 | memset(ring->rx_buffer_info, 0, | |
1941 | sizeof(struct ixgbevf_rx_buffer) * ring->count); | |
1942 | ||
24bff091 ET |
1943 | /* initialize Rx descriptor 0 */ |
1944 | rx_desc = IXGBEVF_RX_DESC(ring, 0); | |
1945 | rx_desc->wb.upper.length = 0; | |
1946 | ||
de02decb DS |
1947 | /* reset ntu and ntc to place SW in sync with hardwdare */ |
1948 | ring->next_to_clean = 0; | |
1949 | ring->next_to_use = 0; | |
bad17234 | 1950 | ring->next_to_alloc = 0; |
de02decb | 1951 | |
f15c5ba5 | 1952 | ixgbevf_configure_srrctl(adapter, ring, reg_idx); |
de02decb | 1953 | |
1ab37e12 ET |
1954 | /* RXDCTL.RLPML does not work on 82599 */ |
1955 | if (adapter->hw.mac.type != ixgbe_mac_82599_vf) { | |
1956 | rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | | |
1957 | IXGBE_RXDCTL_RLPML_EN); | |
1958 | ||
1959 | #if (PAGE_SIZE < 8192) | |
1960 | /* Limit the maximum frame size so we don't overrun the skb */ | |
1961 | if (ring_uses_build_skb(ring) && | |
1962 | !ring_uses_large_buffer(ring)) | |
1963 | rxdctl |= IXGBEVF_MAX_FRAME_BUILD_SKB | | |
1964 | IXGBE_RXDCTL_RLPML_EN; | |
1965 | #endif | |
1966 | } | |
bad17234 | 1967 | |
de02decb DS |
1968 | rxdctl |= IXGBE_RXDCTL_ENABLE | IXGBE_RXDCTL_VME; |
1969 | IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl); | |
1970 | ||
1971 | ixgbevf_rx_desc_queue_enable(adapter, ring); | |
095e2617 | 1972 | ixgbevf_alloc_rx_buffers(ring, ixgbevf_desc_unused(ring)); |
de02decb DS |
1973 | } |
1974 | ||
f15c5ba5 ET |
1975 | static void ixgbevf_set_rx_buffer_len(struct ixgbevf_adapter *adapter, |
1976 | struct ixgbevf_ring *rx_ring) | |
1977 | { | |
1978 | struct net_device *netdev = adapter->netdev; | |
1979 | unsigned int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
1980 | ||
1981 | /* set build_skb and buffer size flags */ | |
1ab37e12 | 1982 | clear_ring_build_skb_enabled(rx_ring); |
f15c5ba5 ET |
1983 | clear_ring_uses_large_buffer(rx_ring); |
1984 | ||
1985 | if (adapter->flags & IXGBEVF_FLAGS_LEGACY_RX) | |
1986 | return; | |
1987 | ||
fe68195d SMJ |
1988 | if (PAGE_SIZE < 8192) |
1989 | if (max_frame > IXGBEVF_MAX_FRAME_BUILD_SKB) | |
1990 | set_ring_uses_large_buffer(rx_ring); | |
1ab37e12 | 1991 | |
fe68195d SMJ |
1992 | /* 82599 can't rely on RXDCTL.RLPML to restrict the size of the frame */ |
1993 | if (adapter->hw.mac.type == ixgbe_mac_82599_vf && !ring_uses_large_buffer(rx_ring)) | |
1994 | return; | |
f15c5ba5 | 1995 | |
fe68195d | 1996 | set_ring_build_skb_enabled(rx_ring); |
f15c5ba5 ET |
1997 | } |
1998 | ||
92915f71 GR |
1999 | /** |
2000 | * ixgbevf_configure_rx - Configure 82599 VF Receive Unit after Reset | |
2001 | * @adapter: board private structure | |
2002 | * | |
2003 | * Configure the Rx unit of the MAC after a reset. | |
2004 | **/ | |
2005 | static void ixgbevf_configure_rx(struct ixgbevf_adapter *adapter) | |
2006 | { | |
bad17234 ET |
2007 | struct ixgbe_hw *hw = &adapter->hw; |
2008 | struct net_device *netdev = adapter->netdev; | |
6a11e52b | 2009 | int i, ret; |
92915f71 | 2010 | |
1bb9c639 | 2011 | ixgbevf_setup_psrtype(adapter); |
9295edb4 ET |
2012 | if (hw->mac.type >= ixgbe_mac_X550_vf) |
2013 | ixgbevf_setup_vfmrqc(adapter); | |
dd1fe113 | 2014 | |
14b22cd9 | 2015 | spin_lock_bh(&adapter->mbx_lock); |
bad17234 | 2016 | /* notify the PF of our intent to use this size of frame */ |
6a11e52b | 2017 | ret = hw->mac.ops.set_rlpml(hw, netdev->mtu + ETH_HLEN + ETH_FCS_LEN); |
14b22cd9 | 2018 | spin_unlock_bh(&adapter->mbx_lock); |
6a11e52b TN |
2019 | if (ret) |
2020 | dev_err(&adapter->pdev->dev, | |
2021 | "Failed to set MTU at %d\n", netdev->mtu); | |
92915f71 | 2022 | |
92915f71 | 2023 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
dec0d8e4 JK |
2024 | * the Base and Length of the Rx Descriptor Ring |
2025 | */ | |
f15c5ba5 ET |
2026 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2027 | struct ixgbevf_ring *rx_ring = adapter->rx_ring[i]; | |
2028 | ||
2029 | ixgbevf_set_rx_buffer_len(adapter, rx_ring); | |
2030 | ixgbevf_configure_rx_ring(adapter, rx_ring); | |
2031 | } | |
92915f71 GR |
2032 | } |
2033 | ||
80d5c368 PM |
2034 | static int ixgbevf_vlan_rx_add_vid(struct net_device *netdev, |
2035 | __be16 proto, u16 vid) | |
92915f71 GR |
2036 | { |
2037 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
2038 | struct ixgbe_hw *hw = &adapter->hw; | |
2ddc7fe1 AD |
2039 | int err; |
2040 | ||
55fdd45b | 2041 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 2042 | |
92915f71 | 2043 | /* add VID to filter table */ |
2ddc7fe1 | 2044 | err = hw->mac.ops.set_vfta(hw, vid, 0, true); |
1c55ed76 | 2045 | |
55fdd45b | 2046 | spin_unlock_bh(&adapter->mbx_lock); |
1c55ed76 | 2047 | |
eac0b680 JS |
2048 | if (err) { |
2049 | netdev_err(netdev, "VF could not set VLAN %d\n", vid); | |
2050 | ||
2051 | /* translate error return types so error makes sense */ | |
2052 | if (err == IXGBE_ERR_MBX) | |
2053 | return -EIO; | |
2ddc7fe1 | 2054 | |
eac0b680 JS |
2055 | if (err == IXGBE_ERR_INVALID_ARGUMENT) |
2056 | return -EACCES; | |
2057 | } | |
2ddc7fe1 | 2058 | |
dadcd65f | 2059 | set_bit(vid, adapter->active_vlans); |
8e586137 | 2060 | |
2ddc7fe1 | 2061 | return err; |
92915f71 GR |
2062 | } |
2063 | ||
80d5c368 PM |
2064 | static int ixgbevf_vlan_rx_kill_vid(struct net_device *netdev, |
2065 | __be16 proto, u16 vid) | |
92915f71 GR |
2066 | { |
2067 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
2068 | struct ixgbe_hw *hw = &adapter->hw; | |
50985b5f | 2069 | int err; |
92915f71 | 2070 | |
55fdd45b | 2071 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 2072 | |
92915f71 | 2073 | /* remove VID from filter table */ |
92fe0bf7 | 2074 | err = hw->mac.ops.set_vfta(hw, vid, 0, false); |
1c55ed76 | 2075 | |
55fdd45b | 2076 | spin_unlock_bh(&adapter->mbx_lock); |
1c55ed76 | 2077 | |
eac0b680 JS |
2078 | if (err) |
2079 | netdev_err(netdev, "Could not remove VLAN %d\n", vid); | |
2080 | ||
dadcd65f | 2081 | clear_bit(vid, adapter->active_vlans); |
8e586137 | 2082 | |
2ddc7fe1 | 2083 | return err; |
92915f71 GR |
2084 | } |
2085 | ||
2086 | static void ixgbevf_restore_vlan(struct ixgbevf_adapter *adapter) | |
2087 | { | |
dadcd65f | 2088 | u16 vid; |
92915f71 | 2089 | |
dadcd65f | 2090 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) |
80d5c368 PM |
2091 | ixgbevf_vlan_rx_add_vid(adapter->netdev, |
2092 | htons(ETH_P_8021Q), vid); | |
92915f71 GR |
2093 | } |
2094 | ||
46ec20ff GR |
2095 | static int ixgbevf_write_uc_addr_list(struct net_device *netdev) |
2096 | { | |
2097 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
2098 | struct ixgbe_hw *hw = &adapter->hw; | |
2099 | int count = 0; | |
2100 | ||
46ec20ff GR |
2101 | if (!netdev_uc_empty(netdev)) { |
2102 | struct netdev_hw_addr *ha; | |
dec0d8e4 | 2103 | |
46ec20ff GR |
2104 | netdev_for_each_uc_addr(ha, netdev) { |
2105 | hw->mac.ops.set_uc_addr(hw, ++count, ha->addr); | |
2106 | udelay(200); | |
2107 | } | |
2108 | } else { | |
dec0d8e4 JK |
2109 | /* If the list is empty then send message to PF driver to |
2110 | * clear all MAC VLANs on this VF. | |
46ec20ff GR |
2111 | */ |
2112 | hw->mac.ops.set_uc_addr(hw, 0, NULL); | |
2113 | } | |
2114 | ||
2115 | return count; | |
2116 | } | |
2117 | ||
92915f71 | 2118 | /** |
dee847f5 | 2119 | * ixgbevf_set_rx_mode - Multicast and unicast set |
92915f71 GR |
2120 | * @netdev: network interface device structure |
2121 | * | |
2122 | * The set_rx_method entry point is called whenever the multicast address | |
dee847f5 GR |
2123 | * list, unicast address list or the network interface flags are updated. |
2124 | * This routine is responsible for configuring the hardware for proper | |
2125 | * multicast mode and configuring requested unicast filters. | |
92915f71 GR |
2126 | **/ |
2127 | static void ixgbevf_set_rx_mode(struct net_device *netdev) | |
2128 | { | |
2129 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
2130 | struct ixgbe_hw *hw = &adapter->hw; | |
8443c1a4 HS |
2131 | unsigned int flags = netdev->flags; |
2132 | int xcast_mode; | |
2133 | ||
41e544cd DS |
2134 | /* request the most inclusive mode we need */ |
2135 | if (flags & IFF_PROMISC) | |
2136 | xcast_mode = IXGBEVF_XCAST_MODE_PROMISC; | |
2137 | else if (flags & IFF_ALLMULTI) | |
2138 | xcast_mode = IXGBEVF_XCAST_MODE_ALLMULTI; | |
2139 | else if (flags & (IFF_BROADCAST | IFF_MULTICAST)) | |
2140 | xcast_mode = IXGBEVF_XCAST_MODE_MULTI; | |
2141 | else | |
2142 | xcast_mode = IXGBEVF_XCAST_MODE_NONE; | |
2143 | ||
55fdd45b | 2144 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 2145 | |
8b44a8a0 | 2146 | hw->mac.ops.update_xcast_mode(hw, xcast_mode); |
8443c1a4 | 2147 | |
92915f71 | 2148 | /* reprogram multicast list */ |
92fe0bf7 | 2149 | hw->mac.ops.update_mc_addr_list(hw, netdev); |
46ec20ff GR |
2150 | |
2151 | ixgbevf_write_uc_addr_list(netdev); | |
1c55ed76 | 2152 | |
55fdd45b | 2153 | spin_unlock_bh(&adapter->mbx_lock); |
92915f71 GR |
2154 | } |
2155 | ||
2156 | static void ixgbevf_napi_enable_all(struct ixgbevf_adapter *adapter) | |
2157 | { | |
2158 | int q_idx; | |
2159 | struct ixgbevf_q_vector *q_vector; | |
2160 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2161 | ||
2162 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
92915f71 | 2163 | q_vector = adapter->q_vector[q_idx]; |
fa71ae27 | 2164 | napi_enable(&q_vector->napi); |
92915f71 GR |
2165 | } |
2166 | } | |
2167 | ||
2168 | static void ixgbevf_napi_disable_all(struct ixgbevf_adapter *adapter) | |
2169 | { | |
2170 | int q_idx; | |
2171 | struct ixgbevf_q_vector *q_vector; | |
2172 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2173 | ||
2174 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
2175 | q_vector = adapter->q_vector[q_idx]; | |
92915f71 GR |
2176 | napi_disable(&q_vector->napi); |
2177 | } | |
2178 | } | |
2179 | ||
220fe050 DS |
2180 | static int ixgbevf_configure_dcb(struct ixgbevf_adapter *adapter) |
2181 | { | |
2182 | struct ixgbe_hw *hw = &adapter->hw; | |
2183 | unsigned int def_q = 0; | |
2184 | unsigned int num_tcs = 0; | |
2dc571aa ET |
2185 | unsigned int num_rx_queues = adapter->num_rx_queues; |
2186 | unsigned int num_tx_queues = adapter->num_tx_queues; | |
220fe050 DS |
2187 | int err; |
2188 | ||
2189 | spin_lock_bh(&adapter->mbx_lock); | |
2190 | ||
2191 | /* fetch queue configuration from the PF */ | |
2192 | err = ixgbevf_get_queues(hw, &num_tcs, &def_q); | |
2193 | ||
2194 | spin_unlock_bh(&adapter->mbx_lock); | |
2195 | ||
2196 | if (err) | |
2197 | return err; | |
2198 | ||
2199 | if (num_tcs > 1) { | |
2dc571aa ET |
2200 | /* we need only one Tx queue */ |
2201 | num_tx_queues = 1; | |
2202 | ||
220fe050 | 2203 | /* update default Tx ring register index */ |
87e70ab9 | 2204 | adapter->tx_ring[0]->reg_idx = def_q; |
220fe050 DS |
2205 | |
2206 | /* we need as many queues as traffic classes */ | |
2207 | num_rx_queues = num_tcs; | |
2208 | } | |
2209 | ||
2210 | /* if we have a bad config abort request queue reset */ | |
2dc571aa ET |
2211 | if ((adapter->num_rx_queues != num_rx_queues) || |
2212 | (adapter->num_tx_queues != num_tx_queues)) { | |
220fe050 DS |
2213 | /* force mailbox timeout to prevent further messages */ |
2214 | hw->mbx.timeout = 0; | |
2215 | ||
2216 | /* wait for watchdog to come around and bail us out */ | |
d5dd7c3f | 2217 | set_bit(__IXGBEVF_QUEUE_RESET_REQUESTED, &adapter->state); |
220fe050 DS |
2218 | } |
2219 | ||
2220 | return 0; | |
2221 | } | |
2222 | ||
92915f71 GR |
2223 | static void ixgbevf_configure(struct ixgbevf_adapter *adapter) |
2224 | { | |
220fe050 DS |
2225 | ixgbevf_configure_dcb(adapter); |
2226 | ||
de02decb | 2227 | ixgbevf_set_rx_mode(adapter->netdev); |
92915f71 GR |
2228 | |
2229 | ixgbevf_restore_vlan(adapter); | |
7f68d430 | 2230 | ixgbevf_ipsec_restore(adapter); |
92915f71 GR |
2231 | |
2232 | ixgbevf_configure_tx(adapter); | |
2233 | ixgbevf_configure_rx(adapter); | |
92915f71 GR |
2234 | } |
2235 | ||
33bd9f60 GR |
2236 | static void ixgbevf_save_reset_stats(struct ixgbevf_adapter *adapter) |
2237 | { | |
2238 | /* Only save pre-reset stats if there are some */ | |
2239 | if (adapter->stats.vfgprc || adapter->stats.vfgptc) { | |
2240 | adapter->stats.saved_reset_vfgprc += adapter->stats.vfgprc - | |
2241 | adapter->stats.base_vfgprc; | |
2242 | adapter->stats.saved_reset_vfgptc += adapter->stats.vfgptc - | |
2243 | adapter->stats.base_vfgptc; | |
2244 | adapter->stats.saved_reset_vfgorc += adapter->stats.vfgorc - | |
2245 | adapter->stats.base_vfgorc; | |
2246 | adapter->stats.saved_reset_vfgotc += adapter->stats.vfgotc - | |
2247 | adapter->stats.base_vfgotc; | |
2248 | adapter->stats.saved_reset_vfmprc += adapter->stats.vfmprc - | |
2249 | adapter->stats.base_vfmprc; | |
2250 | } | |
2251 | } | |
2252 | ||
2253 | static void ixgbevf_init_last_counter_stats(struct ixgbevf_adapter *adapter) | |
2254 | { | |
2255 | struct ixgbe_hw *hw = &adapter->hw; | |
2256 | ||
2257 | adapter->stats.last_vfgprc = IXGBE_READ_REG(hw, IXGBE_VFGPRC); | |
2258 | adapter->stats.last_vfgorc = IXGBE_READ_REG(hw, IXGBE_VFGORC_LSB); | |
2259 | adapter->stats.last_vfgorc |= | |
2260 | (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGORC_MSB))) << 32); | |
2261 | adapter->stats.last_vfgptc = IXGBE_READ_REG(hw, IXGBE_VFGPTC); | |
2262 | adapter->stats.last_vfgotc = IXGBE_READ_REG(hw, IXGBE_VFGOTC_LSB); | |
2263 | adapter->stats.last_vfgotc |= | |
2264 | (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGOTC_MSB))) << 32); | |
2265 | adapter->stats.last_vfmprc = IXGBE_READ_REG(hw, IXGBE_VFMPRC); | |
2266 | ||
2267 | adapter->stats.base_vfgprc = adapter->stats.last_vfgprc; | |
2268 | adapter->stats.base_vfgorc = adapter->stats.last_vfgorc; | |
2269 | adapter->stats.base_vfgptc = adapter->stats.last_vfgptc; | |
2270 | adapter->stats.base_vfgotc = adapter->stats.last_vfgotc; | |
2271 | adapter->stats.base_vfmprc = adapter->stats.last_vfmprc; | |
2272 | } | |
2273 | ||
31186785 AD |
2274 | static void ixgbevf_negotiate_api(struct ixgbevf_adapter *adapter) |
2275 | { | |
2276 | struct ixgbe_hw *hw = &adapter->hw; | |
64d8db7d | 2277 | static const int api[] = { |
339f2896 | 2278 | ixgbe_mbox_api_15, |
64d8db7d CIK |
2279 | ixgbe_mbox_api_14, |
2280 | ixgbe_mbox_api_13, | |
2281 | ixgbe_mbox_api_12, | |
2282 | ixgbe_mbox_api_11, | |
2283 | ixgbe_mbox_api_10, | |
2284 | ixgbe_mbox_api_unknown | |
2285 | }; | |
50985b5f | 2286 | int err, idx = 0; |
31186785 | 2287 | |
55fdd45b | 2288 | spin_lock_bh(&adapter->mbx_lock); |
31186785 AD |
2289 | |
2290 | while (api[idx] != ixgbe_mbox_api_unknown) { | |
2f8214fe | 2291 | err = hw->mac.ops.negotiate_api_version(hw, api[idx]); |
31186785 AD |
2292 | if (!err) |
2293 | break; | |
2294 | idx++; | |
2295 | } | |
2296 | ||
339f2896 RT |
2297 | if (hw->api_version >= ixgbe_mbox_api_15) { |
2298 | hw->mbx.ops.init_params(hw); | |
2299 | memcpy(&hw->mbx.ops, &ixgbevf_mbx_ops, | |
2300 | sizeof(struct ixgbe_mbx_operations)); | |
2301 | } | |
2302 | ||
55fdd45b | 2303 | spin_unlock_bh(&adapter->mbx_lock); |
31186785 AD |
2304 | } |
2305 | ||
795180d8 | 2306 | static void ixgbevf_up_complete(struct ixgbevf_adapter *adapter) |
92915f71 GR |
2307 | { |
2308 | struct net_device *netdev = adapter->netdev; | |
443ebdd6 | 2309 | struct pci_dev *pdev = adapter->pdev; |
92915f71 | 2310 | struct ixgbe_hw *hw = &adapter->hw; |
443ebdd6 | 2311 | bool state; |
92915f71 GR |
2312 | |
2313 | ixgbevf_configure_msix(adapter); | |
2314 | ||
55fdd45b | 2315 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 2316 | |
92fe0bf7 GR |
2317 | if (is_valid_ether_addr(hw->mac.addr)) |
2318 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0); | |
2319 | else | |
2320 | hw->mac.ops.set_rar(hw, 0, hw->mac.perm_addr, 0); | |
92915f71 | 2321 | |
55fdd45b | 2322 | spin_unlock_bh(&adapter->mbx_lock); |
1c55ed76 | 2323 | |
443ebdd6 SM |
2324 | state = adapter->link_state; |
2325 | hw->mac.ops.get_link_state(hw, &adapter->link_state); | |
2326 | if (state && state != adapter->link_state) | |
2327 | dev_info(&pdev->dev, "VF is administratively disabled\n"); | |
2328 | ||
4e857c58 | 2329 | smp_mb__before_atomic(); |
92915f71 GR |
2330 | clear_bit(__IXGBEVF_DOWN, &adapter->state); |
2331 | ixgbevf_napi_enable_all(adapter); | |
2332 | ||
d9bdb57f ET |
2333 | /* clear any pending interrupts, may auto mask */ |
2334 | IXGBE_READ_REG(hw, IXGBE_VTEICR); | |
2335 | ixgbevf_irq_enable(adapter); | |
2336 | ||
92915f71 GR |
2337 | /* enable transmits */ |
2338 | netif_tx_start_all_queues(netdev); | |
2339 | ||
33bd9f60 GR |
2340 | ixgbevf_save_reset_stats(adapter); |
2341 | ixgbevf_init_last_counter_stats(adapter); | |
2342 | ||
4b2cd27f | 2343 | hw->mac.get_link_status = 1; |
9ac5c5cc | 2344 | mod_timer(&adapter->service_timer, jiffies); |
92915f71 GR |
2345 | } |
2346 | ||
795180d8 | 2347 | void ixgbevf_up(struct ixgbevf_adapter *adapter) |
92915f71 | 2348 | { |
92915f71 GR |
2349 | ixgbevf_configure(adapter); |
2350 | ||
795180d8 | 2351 | ixgbevf_up_complete(adapter); |
92915f71 GR |
2352 | } |
2353 | ||
2354 | /** | |
2355 | * ixgbevf_clean_rx_ring - Free Rx Buffers per Queue | |
92915f71 GR |
2356 | * @rx_ring: ring to free buffers from |
2357 | **/ | |
05d063aa | 2358 | static void ixgbevf_clean_rx_ring(struct ixgbevf_ring *rx_ring) |
92915f71 | 2359 | { |
40b8178b | 2360 | u16 i = rx_ring->next_to_clean; |
92915f71 | 2361 | |
bad17234 ET |
2362 | /* Free Rx ring sk_buff */ |
2363 | if (rx_ring->skb) { | |
2364 | dev_kfree_skb(rx_ring->skb); | |
2365 | rx_ring->skb = NULL; | |
2366 | } | |
2367 | ||
bad17234 | 2368 | /* Free all the Rx ring pages */ |
40b8178b | 2369 | while (i != rx_ring->next_to_alloc) { |
bad17234 | 2370 | struct ixgbevf_rx_buffer *rx_buffer; |
92915f71 | 2371 | |
bad17234 | 2372 | rx_buffer = &rx_ring->rx_buffer_info[i]; |
16b35949 ET |
2373 | |
2374 | /* Invalidate cache lines that may have been written to by | |
2375 | * device so that we avoid corrupting memory. | |
2376 | */ | |
2377 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
2378 | rx_buffer->dma, | |
2379 | rx_buffer->page_offset, | |
f15c5ba5 | 2380 | ixgbevf_rx_bufsz(rx_ring), |
16b35949 ET |
2381 | DMA_FROM_DEVICE); |
2382 | ||
2383 | /* free resources associated with mapping */ | |
2384 | dma_unmap_page_attrs(rx_ring->dev, | |
2385 | rx_buffer->dma, | |
f15c5ba5 | 2386 | ixgbevf_rx_pg_size(rx_ring), |
16b35949 ET |
2387 | DMA_FROM_DEVICE, |
2388 | IXGBEVF_RX_DMA_ATTR); | |
2389 | ||
35074d69 ET |
2390 | __page_frag_cache_drain(rx_buffer->page, |
2391 | rx_buffer->pagecnt_bias); | |
2392 | ||
40b8178b ET |
2393 | i++; |
2394 | if (i == rx_ring->count) | |
2395 | i = 0; | |
92915f71 GR |
2396 | } |
2397 | ||
40b8178b ET |
2398 | rx_ring->next_to_alloc = 0; |
2399 | rx_ring->next_to_clean = 0; | |
2400 | rx_ring->next_to_use = 0; | |
92915f71 GR |
2401 | } |
2402 | ||
2403 | /** | |
2404 | * ixgbevf_clean_tx_ring - Free Tx Buffers | |
92915f71 GR |
2405 | * @tx_ring: ring to be cleaned |
2406 | **/ | |
05d063aa | 2407 | static void ixgbevf_clean_tx_ring(struct ixgbevf_ring *tx_ring) |
92915f71 | 2408 | { |
865a4d98 ET |
2409 | u16 i = tx_ring->next_to_clean; |
2410 | struct ixgbevf_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; | |
92915f71 | 2411 | |
865a4d98 ET |
2412 | while (i != tx_ring->next_to_use) { |
2413 | union ixgbe_adv_tx_desc *eop_desc, *tx_desc; | |
2414 | ||
2415 | /* Free all the Tx ring sk_buffs */ | |
21092e9c TN |
2416 | if (ring_is_xdp(tx_ring)) |
2417 | page_frag_free(tx_buffer->data); | |
2418 | else | |
2419 | dev_kfree_skb_any(tx_buffer->skb); | |
865a4d98 ET |
2420 | |
2421 | /* unmap skb header data */ | |
2422 | dma_unmap_single(tx_ring->dev, | |
2423 | dma_unmap_addr(tx_buffer, dma), | |
2424 | dma_unmap_len(tx_buffer, len), | |
2425 | DMA_TO_DEVICE); | |
2426 | ||
2427 | /* check for eop_desc to determine the end of the packet */ | |
2428 | eop_desc = tx_buffer->next_to_watch; | |
2429 | tx_desc = IXGBEVF_TX_DESC(tx_ring, i); | |
2430 | ||
2431 | /* unmap remaining buffers */ | |
2432 | while (tx_desc != eop_desc) { | |
2433 | tx_buffer++; | |
2434 | tx_desc++; | |
2435 | i++; | |
2436 | if (unlikely(i == tx_ring->count)) { | |
2437 | i = 0; | |
2438 | tx_buffer = tx_ring->tx_buffer_info; | |
2439 | tx_desc = IXGBEVF_TX_DESC(tx_ring, 0); | |
2440 | } | |
c0456c23 | 2441 | |
865a4d98 ET |
2442 | /* unmap any remaining paged data */ |
2443 | if (dma_unmap_len(tx_buffer, len)) | |
2444 | dma_unmap_page(tx_ring->dev, | |
2445 | dma_unmap_addr(tx_buffer, dma), | |
2446 | dma_unmap_len(tx_buffer, len), | |
2447 | DMA_TO_DEVICE); | |
2448 | } | |
2449 | ||
2450 | /* move us one more past the eop_desc for start of next pkt */ | |
2451 | tx_buffer++; | |
2452 | i++; | |
2453 | if (unlikely(i == tx_ring->count)) { | |
2454 | i = 0; | |
2455 | tx_buffer = tx_ring->tx_buffer_info; | |
2456 | } | |
92915f71 GR |
2457 | } |
2458 | ||
865a4d98 ET |
2459 | /* reset next_to_use and next_to_clean */ |
2460 | tx_ring->next_to_use = 0; | |
2461 | tx_ring->next_to_clean = 0; | |
92915f71 | 2462 | |
92915f71 GR |
2463 | } |
2464 | ||
2465 | /** | |
2466 | * ixgbevf_clean_all_rx_rings - Free Rx Buffers for all queues | |
2467 | * @adapter: board private structure | |
2468 | **/ | |
2469 | static void ixgbevf_clean_all_rx_rings(struct ixgbevf_adapter *adapter) | |
2470 | { | |
2471 | int i; | |
2472 | ||
2473 | for (i = 0; i < adapter->num_rx_queues; i++) | |
05d063aa | 2474 | ixgbevf_clean_rx_ring(adapter->rx_ring[i]); |
92915f71 GR |
2475 | } |
2476 | ||
2477 | /** | |
2478 | * ixgbevf_clean_all_tx_rings - Free Tx Buffers for all queues | |
2479 | * @adapter: board private structure | |
2480 | **/ | |
2481 | static void ixgbevf_clean_all_tx_rings(struct ixgbevf_adapter *adapter) | |
2482 | { | |
2483 | int i; | |
2484 | ||
2485 | for (i = 0; i < adapter->num_tx_queues; i++) | |
05d063aa | 2486 | ixgbevf_clean_tx_ring(adapter->tx_ring[i]); |
21092e9c TN |
2487 | for (i = 0; i < adapter->num_xdp_queues; i++) |
2488 | ixgbevf_clean_tx_ring(adapter->xdp_ring[i]); | |
92915f71 GR |
2489 | } |
2490 | ||
2491 | void ixgbevf_down(struct ixgbevf_adapter *adapter) | |
2492 | { | |
2493 | struct net_device *netdev = adapter->netdev; | |
2494 | struct ixgbe_hw *hw = &adapter->hw; | |
de02decb | 2495 | int i; |
92915f71 GR |
2496 | |
2497 | /* signal that we are down to the interrupt handler */ | |
5b346dc9 MR |
2498 | if (test_and_set_bit(__IXGBEVF_DOWN, &adapter->state)) |
2499 | return; /* do nothing if already down */ | |
858c3dda | 2500 | |
dec0d8e4 | 2501 | /* disable all enabled Rx queues */ |
858c3dda | 2502 | for (i = 0; i < adapter->num_rx_queues; i++) |
87e70ab9 | 2503 | ixgbevf_disable_rx_queue(adapter, adapter->rx_ring[i]); |
92915f71 | 2504 | |
d9bdb57f | 2505 | usleep_range(10000, 20000); |
92915f71 GR |
2506 | |
2507 | netif_tx_stop_all_queues(netdev); | |
2508 | ||
d9bdb57f ET |
2509 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
2510 | netif_carrier_off(netdev); | |
2511 | netif_tx_disable(netdev); | |
2512 | ||
92915f71 GR |
2513 | ixgbevf_irq_disable(adapter); |
2514 | ||
2515 | ixgbevf_napi_disable_all(adapter); | |
2516 | ||
8fa7292f | 2517 | timer_delete_sync(&adapter->service_timer); |
92915f71 GR |
2518 | |
2519 | /* disable transmits in the hardware now that interrupts are off */ | |
2520 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
de02decb DS |
2521 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
2522 | ||
2523 | IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), | |
2524 | IXGBE_TXDCTL_SWFLSH); | |
92915f71 GR |
2525 | } |
2526 | ||
21092e9c TN |
2527 | for (i = 0; i < adapter->num_xdp_queues; i++) { |
2528 | u8 reg_idx = adapter->xdp_ring[i]->reg_idx; | |
2529 | ||
2530 | IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), | |
2531 | IXGBE_TXDCTL_SWFLSH); | |
2532 | } | |
2533 | ||
92915f71 GR |
2534 | if (!pci_channel_offline(adapter->pdev)) |
2535 | ixgbevf_reset(adapter); | |
2536 | ||
2537 | ixgbevf_clean_all_tx_rings(adapter); | |
2538 | ixgbevf_clean_all_rx_rings(adapter); | |
2539 | } | |
2540 | ||
2541 | void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter) | |
2542 | { | |
92915f71 GR |
2543 | while (test_and_set_bit(__IXGBEVF_RESETTING, &adapter->state)) |
2544 | msleep(1); | |
2545 | ||
4b2cd27f | 2546 | ixgbevf_down(adapter); |
d7cb9da1 | 2547 | pci_set_master(adapter->pdev); |
4b2cd27f | 2548 | ixgbevf_up(adapter); |
92915f71 GR |
2549 | |
2550 | clear_bit(__IXGBEVF_RESETTING, &adapter->state); | |
2551 | } | |
2552 | ||
2553 | void ixgbevf_reset(struct ixgbevf_adapter *adapter) | |
2554 | { | |
2555 | struct ixgbe_hw *hw = &adapter->hw; | |
2556 | struct net_device *netdev = adapter->netdev; | |
2557 | ||
798e381a | 2558 | if (hw->mac.ops.reset_hw(hw)) { |
92915f71 | 2559 | hw_dbg(hw, "PF still resetting\n"); |
798e381a | 2560 | } else { |
92915f71 | 2561 | hw->mac.ops.init_hw(hw); |
798e381a DS |
2562 | ixgbevf_negotiate_api(adapter); |
2563 | } | |
92915f71 GR |
2564 | |
2565 | if (is_valid_ether_addr(adapter->hw.mac.addr)) { | |
f3956ebb | 2566 | eth_hw_addr_set(netdev, adapter->hw.mac.addr); |
91a76baa | 2567 | ether_addr_copy(netdev->perm_addr, adapter->hw.mac.addr); |
92915f71 | 2568 | } |
e66c92ad ET |
2569 | |
2570 | adapter->last_reset = jiffies; | |
92915f71 GR |
2571 | } |
2572 | ||
e45dd5fe JK |
2573 | static int ixgbevf_acquire_msix_vectors(struct ixgbevf_adapter *adapter, |
2574 | int vectors) | |
92915f71 | 2575 | { |
a5f9337b | 2576 | int vector_threshold; |
92915f71 | 2577 | |
fa71ae27 AD |
2578 | /* We'll want at least 2 (vector_threshold): |
2579 | * 1) TxQ[0] + RxQ[0] handler | |
2580 | * 2) Other (Link Status Change, etc.) | |
92915f71 GR |
2581 | */ |
2582 | vector_threshold = MIN_MSIX_COUNT; | |
2583 | ||
2584 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
2585 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
2586 | * Right now, we simply care about how many we'll get; we'll | |
2587 | * set them up later while requesting irq's. | |
2588 | */ | |
5c1e3588 AG |
2589 | vectors = pci_enable_msix_range(adapter->pdev, adapter->msix_entries, |
2590 | vector_threshold, vectors); | |
92915f71 | 2591 | |
5c1e3588 | 2592 | if (vectors < 0) { |
e45dd5fe JK |
2593 | dev_err(&adapter->pdev->dev, |
2594 | "Unable to allocate MSI-X interrupts\n"); | |
92915f71 GR |
2595 | kfree(adapter->msix_entries); |
2596 | adapter->msix_entries = NULL; | |
5c1e3588 | 2597 | return vectors; |
92915f71 | 2598 | } |
dee847f5 | 2599 | |
5c1e3588 AG |
2600 | /* Adjust for only the vectors we'll use, which is minimum |
2601 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
2602 | * vectors we were allocated. | |
2603 | */ | |
2604 | adapter->num_msix_vectors = vectors; | |
2605 | ||
2606 | return 0; | |
92915f71 GR |
2607 | } |
2608 | ||
49ce9c2c BH |
2609 | /** |
2610 | * ixgbevf_set_num_queues - Allocate queues for device, feature dependent | |
92915f71 GR |
2611 | * @adapter: board private structure to initialize |
2612 | * | |
2613 | * This is the top level queue allocation routine. The order here is very | |
2614 | * important, starting with the "most" number of features turned on at once, | |
2615 | * and ending with the smallest set of features. This way large combinations | |
2616 | * can be allocated if they're turned on, and smaller combinations are the | |
5463fce6 | 2617 | * fall through conditions. |
92915f71 GR |
2618 | * |
2619 | **/ | |
2620 | static void ixgbevf_set_num_queues(struct ixgbevf_adapter *adapter) | |
2621 | { | |
220fe050 DS |
2622 | struct ixgbe_hw *hw = &adapter->hw; |
2623 | unsigned int def_q = 0; | |
2624 | unsigned int num_tcs = 0; | |
2625 | int err; | |
2626 | ||
92915f71 GR |
2627 | /* Start with base case */ |
2628 | adapter->num_rx_queues = 1; | |
2629 | adapter->num_tx_queues = 1; | |
21092e9c | 2630 | adapter->num_xdp_queues = 0; |
220fe050 DS |
2631 | |
2632 | spin_lock_bh(&adapter->mbx_lock); | |
2633 | ||
2634 | /* fetch queue configuration from the PF */ | |
2635 | err = ixgbevf_get_queues(hw, &num_tcs, &def_q); | |
2636 | ||
2637 | spin_unlock_bh(&adapter->mbx_lock); | |
2638 | ||
2639 | if (err) | |
2640 | return; | |
2641 | ||
2642 | /* we need as many queues as traffic classes */ | |
2dc571aa | 2643 | if (num_tcs > 1) { |
220fe050 | 2644 | adapter->num_rx_queues = num_tcs; |
2dc571aa ET |
2645 | } else { |
2646 | u16 rss = min_t(u16, num_online_cpus(), IXGBEVF_MAX_RSS_QUEUES); | |
2647 | ||
2648 | switch (hw->api_version) { | |
2649 | case ixgbe_mbox_api_11: | |
94cf66f8 | 2650 | case ixgbe_mbox_api_12: |
41e544cd | 2651 | case ixgbe_mbox_api_13: |
7f68d430 | 2652 | case ixgbe_mbox_api_14: |
339f2896 | 2653 | case ixgbe_mbox_api_15: |
21092e9c TN |
2654 | if (adapter->xdp_prog && |
2655 | hw->mac.max_tx_queues == rss) | |
2656 | rss = rss > 3 ? 2 : 1; | |
2657 | ||
2dc571aa ET |
2658 | adapter->num_rx_queues = rss; |
2659 | adapter->num_tx_queues = rss; | |
21092e9c | 2660 | adapter->num_xdp_queues = adapter->xdp_prog ? rss : 0; |
d8f0c306 | 2661 | break; |
2dc571aa ET |
2662 | default: |
2663 | break; | |
2664 | } | |
2665 | } | |
92915f71 GR |
2666 | } |
2667 | ||
2668 | /** | |
21c046e4 ET |
2669 | * ixgbevf_set_interrupt_capability - set MSI-X or FAIL if not supported |
2670 | * @adapter: board private structure to initialize | |
2671 | * | |
2672 | * Attempt to configure the interrupts using the best available | |
2673 | * capabilities of the hardware and the kernel. | |
2674 | **/ | |
2675 | static int ixgbevf_set_interrupt_capability(struct ixgbevf_adapter *adapter) | |
2676 | { | |
2677 | int vector, v_budget; | |
2678 | ||
2679 | /* It's easy to be greedy for MSI-X vectors, but it really | |
2680 | * doesn't do us much good if we have a lot more vectors | |
2681 | * than CPU's. So let's be conservative and only ask for | |
2682 | * (roughly) the same number of vectors as there are CPU's. | |
2683 | * The default is to use pairs of vectors. | |
2684 | */ | |
2685 | v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues); | |
2686 | v_budget = min_t(int, v_budget, num_online_cpus()); | |
2687 | v_budget += NON_Q_VECTORS; | |
2688 | ||
2689 | adapter->msix_entries = kcalloc(v_budget, | |
2690 | sizeof(struct msix_entry), GFP_KERNEL); | |
2691 | if (!adapter->msix_entries) | |
2692 | return -ENOMEM; | |
2693 | ||
2694 | for (vector = 0; vector < v_budget; vector++) | |
2695 | adapter->msix_entries[vector].entry = vector; | |
2696 | ||
2697 | /* A failure in MSI-X entry allocation isn't fatal, but the VF driver | |
2698 | * does not support any other modes, so we will simply fail here. Note | |
2699 | * that we clean up the msix_entries pointer else-where. | |
2700 | */ | |
2701 | return ixgbevf_acquire_msix_vectors(adapter, v_budget); | |
2702 | } | |
2703 | ||
2704 | static void ixgbevf_add_ring(struct ixgbevf_ring *ring, | |
2705 | struct ixgbevf_ring_container *head) | |
2706 | { | |
2707 | ring->next = head->ring; | |
2708 | head->ring = ring; | |
2709 | head->count++; | |
2710 | } | |
2711 | ||
2712 | /** | |
2713 | * ixgbevf_alloc_q_vector - Allocate memory for a single interrupt vector | |
92915f71 | 2714 | * @adapter: board private structure to initialize |
21c046e4 ET |
2715 | * @v_idx: index of vector in adapter struct |
2716 | * @txr_count: number of Tx rings for q vector | |
2717 | * @txr_idx: index of first Tx ring to assign | |
21092e9c TN |
2718 | * @xdp_count: total number of XDP rings to allocate |
2719 | * @xdp_idx: index of first XDP ring to allocate | |
21c046e4 ET |
2720 | * @rxr_count: number of Rx rings for q vector |
2721 | * @rxr_idx: index of first Rx ring to assign | |
92915f71 | 2722 | * |
21c046e4 | 2723 | * We allocate one q_vector. If allocation fails we return -ENOMEM. |
92915f71 | 2724 | **/ |
21c046e4 ET |
2725 | static int ixgbevf_alloc_q_vector(struct ixgbevf_adapter *adapter, int v_idx, |
2726 | int txr_count, int txr_idx, | |
21092e9c | 2727 | int xdp_count, int xdp_idx, |
21c046e4 | 2728 | int rxr_count, int rxr_idx) |
92915f71 | 2729 | { |
21c046e4 | 2730 | struct ixgbevf_q_vector *q_vector; |
21092e9c | 2731 | int reg_idx = txr_idx + xdp_idx; |
87e70ab9 | 2732 | struct ixgbevf_ring *ring; |
21c046e4 ET |
2733 | int ring_count, size; |
2734 | ||
21092e9c | 2735 | ring_count = txr_count + xdp_count + rxr_count; |
21c046e4 ET |
2736 | size = sizeof(*q_vector) + (sizeof(*ring) * ring_count); |
2737 | ||
2738 | /* allocate q_vector and rings */ | |
2739 | q_vector = kzalloc(size, GFP_KERNEL); | |
2740 | if (!q_vector) | |
2741 | return -ENOMEM; | |
2742 | ||
2743 | /* initialize NAPI */ | |
b48b89f9 | 2744 | netif_napi_add(adapter->netdev, &q_vector->napi, ixgbevf_poll); |
21c046e4 ET |
2745 | |
2746 | /* tie q_vector and adapter together */ | |
2747 | adapter->q_vector[v_idx] = q_vector; | |
2748 | q_vector->adapter = adapter; | |
2749 | q_vector->v_idx = v_idx; | |
92915f71 | 2750 | |
21c046e4 ET |
2751 | /* initialize pointer to rings */ |
2752 | ring = q_vector->ring; | |
92915f71 | 2753 | |
21c046e4 ET |
2754 | while (txr_count) { |
2755 | /* assign generic ring traits */ | |
87e70ab9 DS |
2756 | ring->dev = &adapter->pdev->dev; |
2757 | ring->netdev = adapter->netdev; | |
21c046e4 ET |
2758 | |
2759 | /* configure backlink on ring */ | |
2760 | ring->q_vector = q_vector; | |
2761 | ||
2762 | /* update q_vector Tx values */ | |
2763 | ixgbevf_add_ring(ring, &q_vector->tx); | |
2764 | ||
2765 | /* apply Tx specific ring traits */ | |
87e70ab9 | 2766 | ring->count = adapter->tx_ring_count; |
21c046e4 | 2767 | ring->queue_index = txr_idx; |
21092e9c | 2768 | ring->reg_idx = reg_idx; |
92915f71 | 2769 | |
21c046e4 | 2770 | /* assign ring to adapter */ |
c6fbfdcb | 2771 | adapter->tx_ring[txr_idx] = ring; |
21c046e4 ET |
2772 | |
2773 | /* update count and index */ | |
2774 | txr_count--; | |
2775 | txr_idx++; | |
21092e9c TN |
2776 | reg_idx++; |
2777 | ||
2778 | /* push pointer to next ring */ | |
2779 | ring++; | |
2780 | } | |
2781 | ||
2782 | while (xdp_count) { | |
2783 | /* assign generic ring traits */ | |
2784 | ring->dev = &adapter->pdev->dev; | |
2785 | ring->netdev = adapter->netdev; | |
2786 | ||
2787 | /* configure backlink on ring */ | |
2788 | ring->q_vector = q_vector; | |
2789 | ||
2790 | /* update q_vector Tx values */ | |
2791 | ixgbevf_add_ring(ring, &q_vector->tx); | |
2792 | ||
2793 | /* apply Tx specific ring traits */ | |
2794 | ring->count = adapter->tx_ring_count; | |
2795 | ring->queue_index = xdp_idx; | |
2796 | ring->reg_idx = reg_idx; | |
2797 | set_ring_xdp(ring); | |
2798 | ||
2799 | /* assign ring to adapter */ | |
2800 | adapter->xdp_ring[xdp_idx] = ring; | |
2801 | ||
2802 | /* update count and index */ | |
2803 | xdp_count--; | |
2804 | xdp_idx++; | |
2805 | reg_idx++; | |
92915f71 | 2806 | |
21c046e4 ET |
2807 | /* push pointer to next ring */ |
2808 | ring++; | |
2809 | } | |
87e70ab9 | 2810 | |
21c046e4 ET |
2811 | while (rxr_count) { |
2812 | /* assign generic ring traits */ | |
87e70ab9 DS |
2813 | ring->dev = &adapter->pdev->dev; |
2814 | ring->netdev = adapter->netdev; | |
2815 | ||
21c046e4 ET |
2816 | /* configure backlink on ring */ |
2817 | ring->q_vector = q_vector; | |
2818 | ||
2819 | /* update q_vector Rx values */ | |
2820 | ixgbevf_add_ring(ring, &q_vector->rx); | |
2821 | ||
2822 | /* apply Rx specific ring traits */ | |
87e70ab9 | 2823 | ring->count = adapter->rx_ring_count; |
21c046e4 ET |
2824 | ring->queue_index = rxr_idx; |
2825 | ring->reg_idx = rxr_idx; | |
87e70ab9 | 2826 | |
21c046e4 ET |
2827 | /* assign ring to adapter */ |
2828 | adapter->rx_ring[rxr_idx] = ring; | |
92915f71 | 2829 | |
21c046e4 ET |
2830 | /* update count and index */ |
2831 | rxr_count--; | |
2832 | rxr_idx++; | |
92915f71 | 2833 | |
21c046e4 ET |
2834 | /* push pointer to next ring */ |
2835 | ring++; | |
87e70ab9 DS |
2836 | } |
2837 | ||
21c046e4 | 2838 | return 0; |
92915f71 GR |
2839 | } |
2840 | ||
2841 | /** | |
21c046e4 | 2842 | * ixgbevf_free_q_vector - Free memory allocated for specific interrupt vector |
92915f71 | 2843 | * @adapter: board private structure to initialize |
21c046e4 | 2844 | * @v_idx: index of vector in adapter struct |
92915f71 | 2845 | * |
21c046e4 ET |
2846 | * This function frees the memory allocated to the q_vector. In addition if |
2847 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
2848 | * to freeing the q_vector. | |
92915f71 | 2849 | **/ |
21c046e4 | 2850 | static void ixgbevf_free_q_vector(struct ixgbevf_adapter *adapter, int v_idx) |
92915f71 | 2851 | { |
21c046e4 ET |
2852 | struct ixgbevf_q_vector *q_vector = adapter->q_vector[v_idx]; |
2853 | struct ixgbevf_ring *ring; | |
92915f71 | 2854 | |
21092e9c TN |
2855 | ixgbevf_for_each_ring(ring, q_vector->tx) { |
2856 | if (ring_is_xdp(ring)) | |
2857 | adapter->xdp_ring[ring->queue_index] = NULL; | |
2858 | else | |
2859 | adapter->tx_ring[ring->queue_index] = NULL; | |
2860 | } | |
92915f71 | 2861 | |
21c046e4 ET |
2862 | ixgbevf_for_each_ring(ring, q_vector->rx) |
2863 | adapter->rx_ring[ring->queue_index] = NULL; | |
92915f71 | 2864 | |
21c046e4 ET |
2865 | adapter->q_vector[v_idx] = NULL; |
2866 | netif_napi_del(&q_vector->napi); | |
92915f71 | 2867 | |
21c046e4 ET |
2868 | /* ixgbevf_get_stats() might access the rings on this vector, |
2869 | * we must wait a grace period before freeing it. | |
2870 | */ | |
2871 | kfree_rcu(q_vector, rcu); | |
92915f71 GR |
2872 | } |
2873 | ||
2874 | /** | |
2875 | * ixgbevf_alloc_q_vectors - Allocate memory for interrupt vectors | |
2876 | * @adapter: board private structure to initialize | |
2877 | * | |
2878 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
2879 | * return -ENOMEM. | |
2880 | **/ | |
2881 | static int ixgbevf_alloc_q_vectors(struct ixgbevf_adapter *adapter) | |
2882 | { | |
21c046e4 ET |
2883 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2884 | int rxr_remaining = adapter->num_rx_queues; | |
2885 | int txr_remaining = adapter->num_tx_queues; | |
21092e9c TN |
2886 | int xdp_remaining = adapter->num_xdp_queues; |
2887 | int rxr_idx = 0, txr_idx = 0, xdp_idx = 0, v_idx = 0; | |
21c046e4 ET |
2888 | int err; |
2889 | ||
21092e9c | 2890 | if (q_vectors >= (rxr_remaining + txr_remaining + xdp_remaining)) { |
21c046e4 ET |
2891 | for (; rxr_remaining; v_idx++, q_vectors--) { |
2892 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors); | |
2893 | ||
2894 | err = ixgbevf_alloc_q_vector(adapter, v_idx, | |
21092e9c | 2895 | 0, 0, 0, 0, rqpv, rxr_idx); |
21c046e4 ET |
2896 | if (err) |
2897 | goto err_out; | |
2898 | ||
2899 | /* update counts and index */ | |
2900 | rxr_remaining -= rqpv; | |
2901 | rxr_idx += rqpv; | |
2902 | } | |
2903 | } | |
2904 | ||
2905 | for (; q_vectors; v_idx++, q_vectors--) { | |
2906 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors); | |
2907 | int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors); | |
21092e9c | 2908 | int xqpv = DIV_ROUND_UP(xdp_remaining, q_vectors); |
92915f71 | 2909 | |
21c046e4 ET |
2910 | err = ixgbevf_alloc_q_vector(adapter, v_idx, |
2911 | tqpv, txr_idx, | |
21092e9c | 2912 | xqpv, xdp_idx, |
21c046e4 | 2913 | rqpv, rxr_idx); |
92915f71 | 2914 | |
21c046e4 | 2915 | if (err) |
92915f71 | 2916 | goto err_out; |
21c046e4 ET |
2917 | |
2918 | /* update counts and index */ | |
2919 | rxr_remaining -= rqpv; | |
2920 | rxr_idx += rqpv; | |
2921 | txr_remaining -= tqpv; | |
2922 | txr_idx += tqpv; | |
21092e9c TN |
2923 | xdp_remaining -= xqpv; |
2924 | xdp_idx += xqpv; | |
92915f71 GR |
2925 | } |
2926 | ||
2927 | return 0; | |
2928 | ||
2929 | err_out: | |
21c046e4 ET |
2930 | while (v_idx) { |
2931 | v_idx--; | |
2932 | ixgbevf_free_q_vector(adapter, v_idx); | |
92915f71 | 2933 | } |
21c046e4 | 2934 | |
92915f71 GR |
2935 | return -ENOMEM; |
2936 | } | |
2937 | ||
2938 | /** | |
2939 | * ixgbevf_free_q_vectors - Free memory allocated for interrupt vectors | |
2940 | * @adapter: board private structure to initialize | |
2941 | * | |
2942 | * This function frees the memory allocated to the q_vectors. In addition if | |
2943 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
2944 | * to freeing the q_vector. | |
2945 | **/ | |
2946 | static void ixgbevf_free_q_vectors(struct ixgbevf_adapter *adapter) | |
2947 | { | |
21c046e4 | 2948 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
92915f71 | 2949 | |
21c046e4 ET |
2950 | while (q_vectors) { |
2951 | q_vectors--; | |
2952 | ixgbevf_free_q_vector(adapter, q_vectors); | |
92915f71 GR |
2953 | } |
2954 | } | |
2955 | ||
2956 | /** | |
2957 | * ixgbevf_reset_interrupt_capability - Reset MSIX setup | |
2958 | * @adapter: board private structure | |
2959 | * | |
2960 | **/ | |
2961 | static void ixgbevf_reset_interrupt_capability(struct ixgbevf_adapter *adapter) | |
2962 | { | |
eeffceee MR |
2963 | if (!adapter->msix_entries) |
2964 | return; | |
2965 | ||
92915f71 GR |
2966 | pci_disable_msix(adapter->pdev); |
2967 | kfree(adapter->msix_entries); | |
2968 | adapter->msix_entries = NULL; | |
92915f71 GR |
2969 | } |
2970 | ||
2971 | /** | |
2972 | * ixgbevf_init_interrupt_scheme - Determine if MSIX is supported and init | |
2973 | * @adapter: board private structure to initialize | |
2974 | * | |
2975 | **/ | |
2976 | static int ixgbevf_init_interrupt_scheme(struct ixgbevf_adapter *adapter) | |
2977 | { | |
2978 | int err; | |
2979 | ||
2980 | /* Number of supported queues */ | |
2981 | ixgbevf_set_num_queues(adapter); | |
2982 | ||
2983 | err = ixgbevf_set_interrupt_capability(adapter); | |
2984 | if (err) { | |
2985 | hw_dbg(&adapter->hw, | |
2986 | "Unable to setup interrupt capabilities\n"); | |
2987 | goto err_set_interrupt; | |
2988 | } | |
2989 | ||
2990 | err = ixgbevf_alloc_q_vectors(adapter); | |
2991 | if (err) { | |
dec0d8e4 | 2992 | hw_dbg(&adapter->hw, "Unable to allocate memory for queue vectors\n"); |
92915f71 GR |
2993 | goto err_alloc_q_vectors; |
2994 | } | |
2995 | ||
21092e9c TN |
2996 | hw_dbg(&adapter->hw, "Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u XDP Queue count %u\n", |
2997 | (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", | |
2998 | adapter->num_rx_queues, adapter->num_tx_queues, | |
2999 | adapter->num_xdp_queues); | |
92915f71 GR |
3000 | |
3001 | set_bit(__IXGBEVF_DOWN, &adapter->state); | |
3002 | ||
3003 | return 0; | |
92915f71 GR |
3004 | err_alloc_q_vectors: |
3005 | ixgbevf_reset_interrupt_capability(adapter); | |
3006 | err_set_interrupt: | |
3007 | return err; | |
3008 | } | |
3009 | ||
0ac1e8ce AD |
3010 | /** |
3011 | * ixgbevf_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
3012 | * @adapter: board private structure to clear interrupt scheme on | |
3013 | * | |
3014 | * We go through and clear interrupt specific resources and reset the structure | |
3015 | * to pre-load conditions | |
3016 | **/ | |
3017 | static void ixgbevf_clear_interrupt_scheme(struct ixgbevf_adapter *adapter) | |
3018 | { | |
3019 | adapter->num_tx_queues = 0; | |
21092e9c | 3020 | adapter->num_xdp_queues = 0; |
0ac1e8ce AD |
3021 | adapter->num_rx_queues = 0; |
3022 | ||
3023 | ixgbevf_free_q_vectors(adapter); | |
3024 | ixgbevf_reset_interrupt_capability(adapter); | |
3025 | } | |
3026 | ||
92915f71 GR |
3027 | /** |
3028 | * ixgbevf_sw_init - Initialize general software structures | |
92915f71 GR |
3029 | * @adapter: board private structure to initialize |
3030 | * | |
3031 | * ixgbevf_sw_init initializes the Adapter private data structure. | |
3032 | * Fields are initialized based on PCI device information and | |
3033 | * OS network device settings (MTU size). | |
3034 | **/ | |
9f9a12f8 | 3035 | static int ixgbevf_sw_init(struct ixgbevf_adapter *adapter) |
92915f71 GR |
3036 | { |
3037 | struct ixgbe_hw *hw = &adapter->hw; | |
3038 | struct pci_dev *pdev = adapter->pdev; | |
e1941a74 | 3039 | struct net_device *netdev = adapter->netdev; |
92915f71 GR |
3040 | int err; |
3041 | ||
3042 | /* PCI config space info */ | |
92915f71 GR |
3043 | hw->vendor_id = pdev->vendor; |
3044 | hw->device_id = pdev->device; | |
ff938e43 | 3045 | hw->revision_id = pdev->revision; |
92915f71 GR |
3046 | hw->subsystem_vendor_id = pdev->subsystem_vendor; |
3047 | hw->subsystem_device_id = pdev->subsystem_device; | |
3048 | ||
3049 | hw->mbx.ops.init_params(hw); | |
56e94095 | 3050 | |
e60ae003 TN |
3051 | if (hw->mac.type >= ixgbe_mac_X550_vf) { |
3052 | err = ixgbevf_init_rss_key(adapter); | |
3053 | if (err) | |
3054 | goto out; | |
3055 | } | |
3056 | ||
56e94095 AD |
3057 | /* assume legacy case in which PF would only give VF 2 queues */ |
3058 | hw->mac.max_tx_queues = 2; | |
3059 | hw->mac.max_rx_queues = 2; | |
3060 | ||
798e381a DS |
3061 | /* lock to protect mailbox accesses */ |
3062 | spin_lock_init(&adapter->mbx_lock); | |
3063 | ||
92915f71 GR |
3064 | err = hw->mac.ops.reset_hw(hw); |
3065 | if (err) { | |
3066 | dev_info(&pdev->dev, | |
e1941a74 | 3067 | "PF still in reset state. Is the PF interface up?\n"); |
92915f71 GR |
3068 | } else { |
3069 | err = hw->mac.ops.init_hw(hw); | |
3070 | if (err) { | |
dbd9636e | 3071 | pr_err("init_shared_code failed: %d\n", err); |
92915f71 GR |
3072 | goto out; |
3073 | } | |
798e381a | 3074 | ixgbevf_negotiate_api(adapter); |
e1941a74 GR |
3075 | err = hw->mac.ops.get_mac_addr(hw, hw->mac.addr); |
3076 | if (err) | |
3077 | dev_info(&pdev->dev, "Error reading MAC address\n"); | |
3078 | else if (is_zero_ether_addr(adapter->hw.mac.addr)) | |
3079 | dev_info(&pdev->dev, | |
3080 | "MAC address not assigned by administrator.\n"); | |
f3956ebb | 3081 | eth_hw_addr_set(netdev, hw->mac.addr); |
e1941a74 GR |
3082 | } |
3083 | ||
3084 | if (!is_valid_ether_addr(netdev->dev_addr)) { | |
3085 | dev_info(&pdev->dev, "Assigning random MAC address\n"); | |
3086 | eth_hw_addr_random(netdev); | |
91a76baa | 3087 | ether_addr_copy(hw->mac.addr, netdev->dev_addr); |
465fc643 | 3088 | ether_addr_copy(hw->mac.perm_addr, netdev->dev_addr); |
92915f71 GR |
3089 | } |
3090 | ||
3091 | /* Enable dynamic interrupt throttling rates */ | |
5f3600eb AD |
3092 | adapter->rx_itr_setting = 1; |
3093 | adapter->tx_itr_setting = 1; | |
92915f71 | 3094 | |
92915f71 GR |
3095 | /* set default ring sizes */ |
3096 | adapter->tx_ring_count = IXGBEVF_DEFAULT_TXD; | |
3097 | adapter->rx_ring_count = IXGBEVF_DEFAULT_RXD; | |
3098 | ||
443ebdd6 SM |
3099 | adapter->link_state = true; |
3100 | ||
92915f71 | 3101 | set_bit(__IXGBEVF_DOWN, &adapter->state); |
1a0d6ae5 | 3102 | return 0; |
92915f71 GR |
3103 | |
3104 | out: | |
3105 | return err; | |
3106 | } | |
3107 | ||
92915f71 GR |
3108 | #define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \ |
3109 | { \ | |
3110 | u32 current_counter = IXGBE_READ_REG(hw, reg); \ | |
3111 | if (current_counter < last_counter) \ | |
3112 | counter += 0x100000000LL; \ | |
3113 | last_counter = current_counter; \ | |
3114 | counter &= 0xFFFFFFFF00000000LL; \ | |
3115 | counter |= current_counter; \ | |
3116 | } | |
3117 | ||
3118 | #define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ | |
3119 | { \ | |
3120 | u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \ | |
3121 | u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \ | |
dec0d8e4 JK |
3122 | u64 current_counter = (current_counter_msb << 32) | \ |
3123 | current_counter_lsb; \ | |
92915f71 GR |
3124 | if (current_counter < last_counter) \ |
3125 | counter += 0x1000000000LL; \ | |
3126 | last_counter = current_counter; \ | |
3127 | counter &= 0xFFFFFFF000000000LL; \ | |
3128 | counter |= current_counter; \ | |
3129 | } | |
3130 | /** | |
3131 | * ixgbevf_update_stats - Update the board statistics counters. | |
3132 | * @adapter: board private structure | |
3133 | **/ | |
3134 | void ixgbevf_update_stats(struct ixgbevf_adapter *adapter) | |
3135 | { | |
3136 | struct ixgbe_hw *hw = &adapter->hw; | |
2a35efe5 ET |
3137 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; |
3138 | u64 alloc_rx_page = 0, hw_csum_rx_error = 0; | |
55fb277c | 3139 | int i; |
92915f71 | 3140 | |
e66c92ad ET |
3141 | if (test_bit(__IXGBEVF_DOWN, &adapter->state) || |
3142 | test_bit(__IXGBEVF_RESETTING, &adapter->state)) | |
088245a3 GR |
3143 | return; |
3144 | ||
92915f71 GR |
3145 | UPDATE_VF_COUNTER_32bit(IXGBE_VFGPRC, adapter->stats.last_vfgprc, |
3146 | adapter->stats.vfgprc); | |
3147 | UPDATE_VF_COUNTER_32bit(IXGBE_VFGPTC, adapter->stats.last_vfgptc, | |
3148 | adapter->stats.vfgptc); | |
3149 | UPDATE_VF_COUNTER_36bit(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, | |
3150 | adapter->stats.last_vfgorc, | |
3151 | adapter->stats.vfgorc); | |
3152 | UPDATE_VF_COUNTER_36bit(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, | |
3153 | adapter->stats.last_vfgotc, | |
3154 | adapter->stats.vfgotc); | |
3155 | UPDATE_VF_COUNTER_32bit(IXGBE_VFMPRC, adapter->stats.last_vfmprc, | |
3156 | adapter->stats.vfmprc); | |
55fb277c GR |
3157 | |
3158 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2a35efe5 ET |
3159 | struct ixgbevf_ring *rx_ring = adapter->rx_ring[i]; |
3160 | ||
3161 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; | |
3162 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
3163 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
3164 | alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; | |
55fb277c | 3165 | } |
2a35efe5 ET |
3166 | |
3167 | adapter->hw_csum_rx_error = hw_csum_rx_error; | |
3168 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
3169 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
3170 | adapter->alloc_rx_page = alloc_rx_page; | |
92915f71 GR |
3171 | } |
3172 | ||
3173 | /** | |
9ac5c5cc | 3174 | * ixgbevf_service_timer - Timer Call-back |
e23cf38f | 3175 | * @t: pointer to timer_list struct |
92915f71 | 3176 | **/ |
26566eae | 3177 | static void ixgbevf_service_timer(struct timer_list *t) |
92915f71 | 3178 | { |
41cb0855 IM |
3179 | struct ixgbevf_adapter *adapter = timer_container_of(adapter, t, |
3180 | service_timer); | |
e66c92ad | 3181 | |
9ac5c5cc ET |
3182 | /* Reset the timer */ |
3183 | mod_timer(&adapter->service_timer, (HZ * 2) + jiffies); | |
3184 | ||
3185 | ixgbevf_service_event_schedule(adapter); | |
e66c92ad ET |
3186 | } |
3187 | ||
9ac5c5cc | 3188 | static void ixgbevf_reset_subtask(struct ixgbevf_adapter *adapter) |
e66c92ad | 3189 | { |
d5dd7c3f | 3190 | if (!test_and_clear_bit(__IXGBEVF_RESET_REQUESTED, &adapter->state)) |
9ac5c5cc | 3191 | return; |
e66c92ad | 3192 | |
7d6446db | 3193 | rtnl_lock(); |
e66c92ad ET |
3194 | /* If we're already down or resetting, just bail */ |
3195 | if (test_bit(__IXGBEVF_DOWN, &adapter->state) || | |
6e469ed0 | 3196 | test_bit(__IXGBEVF_REMOVING, &adapter->state) || |
7d6446db ET |
3197 | test_bit(__IXGBEVF_RESETTING, &adapter->state)) { |
3198 | rtnl_unlock(); | |
e66c92ad | 3199 | return; |
7d6446db | 3200 | } |
e66c92ad ET |
3201 | |
3202 | adapter->tx_timeout_count++; | |
3203 | ||
3204 | ixgbevf_reinit_locked(adapter); | |
8e8247ab | 3205 | rtnl_unlock(); |
e66c92ad ET |
3206 | } |
3207 | ||
dec0d8e4 JK |
3208 | /** |
3209 | * ixgbevf_check_hang_subtask - check for hung queues and dropped interrupts | |
3210 | * @adapter: pointer to the device adapter structure | |
e66c92ad ET |
3211 | * |
3212 | * This function serves two purposes. First it strobes the interrupt lines | |
3213 | * in order to make certain interrupts are occurring. Secondly it sets the | |
3214 | * bits needed to check for TX hangs. As a result we should immediately | |
3215 | * determine if a hang has occurred. | |
dec0d8e4 | 3216 | **/ |
e66c92ad ET |
3217 | static void ixgbevf_check_hang_subtask(struct ixgbevf_adapter *adapter) |
3218 | { | |
92915f71 | 3219 | struct ixgbe_hw *hw = &adapter->hw; |
5f3600eb | 3220 | u32 eics = 0; |
92915f71 GR |
3221 | int i; |
3222 | ||
e66c92ad ET |
3223 | /* If we're down or resetting, just bail */ |
3224 | if (test_bit(__IXGBEVF_DOWN, &adapter->state) || | |
3225 | test_bit(__IXGBEVF_RESETTING, &adapter->state)) | |
3226 | return; | |
92915f71 | 3227 | |
e08400b7 ET |
3228 | /* Force detection of hung controller */ |
3229 | if (netif_carrier_ok(adapter->netdev)) { | |
3230 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3231 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
21092e9c TN |
3232 | for (i = 0; i < adapter->num_xdp_queues; i++) |
3233 | set_check_for_tx_hang(adapter->xdp_ring[i]); | |
e08400b7 ET |
3234 | } |
3235 | ||
dec0d8e4 | 3236 | /* get one bit for every active Tx/Rx interrupt vector */ |
92915f71 GR |
3237 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { |
3238 | struct ixgbevf_q_vector *qv = adapter->q_vector[i]; | |
9ac5c5cc | 3239 | |
6b43c446 | 3240 | if (qv->rx.ring || qv->tx.ring) |
8d055cc0 | 3241 | eics |= BIT(i); |
92915f71 GR |
3242 | } |
3243 | ||
e66c92ad | 3244 | /* Cause software interrupt to ensure rings are cleaned */ |
5f3600eb | 3245 | IXGBE_WRITE_REG(hw, IXGBE_VTEICS, eics); |
e66c92ad | 3246 | } |
92915f71 | 3247 | |
e66c92ad ET |
3248 | /** |
3249 | * ixgbevf_watchdog_update_link - update the link status | |
dec0d8e4 | 3250 | * @adapter: pointer to the device adapter structure |
e66c92ad ET |
3251 | **/ |
3252 | static void ixgbevf_watchdog_update_link(struct ixgbevf_adapter *adapter) | |
3253 | { | |
3254 | struct ixgbe_hw *hw = &adapter->hw; | |
3255 | u32 link_speed = adapter->link_speed; | |
3256 | bool link_up = adapter->link_up; | |
3257 | s32 err; | |
3258 | ||
3259 | spin_lock_bh(&adapter->mbx_lock); | |
3260 | ||
3261 | err = hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
3262 | ||
3263 | spin_unlock_bh(&adapter->mbx_lock); | |
3264 | ||
3265 | /* if check for link returns error we will need to reset */ | |
3266 | if (err && time_after(jiffies, adapter->last_reset + (10 * HZ))) { | |
d5dd7c3f | 3267 | set_bit(__IXGBEVF_RESET_REQUESTED, &adapter->state); |
e66c92ad ET |
3268 | link_up = false; |
3269 | } | |
3270 | ||
3271 | adapter->link_up = link_up; | |
3272 | adapter->link_speed = link_speed; | |
92915f71 GR |
3273 | } |
3274 | ||
e66c92ad ET |
3275 | /** |
3276 | * ixgbevf_watchdog_link_is_up - update netif_carrier status and | |
3277 | * print link up message | |
dec0d8e4 | 3278 | * @adapter: pointer to the device adapter structure |
e66c92ad ET |
3279 | **/ |
3280 | static void ixgbevf_watchdog_link_is_up(struct ixgbevf_adapter *adapter) | |
92915f71 | 3281 | { |
e66c92ad | 3282 | struct net_device *netdev = adapter->netdev; |
92915f71 | 3283 | |
e66c92ad ET |
3284 | /* only continue if link was previously down */ |
3285 | if (netif_carrier_ok(netdev)) | |
92915f71 GR |
3286 | return; |
3287 | ||
e66c92ad ET |
3288 | dev_info(&adapter->pdev->dev, "NIC Link is Up %s\n", |
3289 | (adapter->link_speed == IXGBE_LINK_SPEED_10GB_FULL) ? | |
3290 | "10 Gbps" : | |
3291 | (adapter->link_speed == IXGBE_LINK_SPEED_1GB_FULL) ? | |
3292 | "1 Gbps" : | |
3293 | (adapter->link_speed == IXGBE_LINK_SPEED_100_FULL) ? | |
3294 | "100 Mbps" : | |
3295 | "unknown speed"); | |
92915f71 | 3296 | |
e66c92ad ET |
3297 | netif_carrier_on(netdev); |
3298 | } | |
3299 | ||
3300 | /** | |
3301 | * ixgbevf_watchdog_link_is_down - update netif_carrier status and | |
3302 | * print link down message | |
dec0d8e4 | 3303 | * @adapter: pointer to the adapter structure |
e66c92ad ET |
3304 | **/ |
3305 | static void ixgbevf_watchdog_link_is_down(struct ixgbevf_adapter *adapter) | |
3306 | { | |
3307 | struct net_device *netdev = adapter->netdev; | |
3308 | ||
3309 | adapter->link_speed = 0; | |
3310 | ||
3311 | /* only continue if link was up previously */ | |
3312 | if (!netif_carrier_ok(netdev)) | |
3313 | return; | |
3314 | ||
3315 | dev_info(&adapter->pdev->dev, "NIC Link is Down\n"); | |
3316 | ||
3317 | netif_carrier_off(netdev); | |
92915f71 GR |
3318 | } |
3319 | ||
3320 | /** | |
9ac5c5cc | 3321 | * ixgbevf_watchdog_subtask - worker thread to bring link up |
e23cf38f | 3322 | * @adapter: board private structure |
9ac5c5cc ET |
3323 | **/ |
3324 | static void ixgbevf_watchdog_subtask(struct ixgbevf_adapter *adapter) | |
3325 | { | |
3326 | /* if interface is down do nothing */ | |
3327 | if (test_bit(__IXGBEVF_DOWN, &adapter->state) || | |
3328 | test_bit(__IXGBEVF_RESETTING, &adapter->state)) | |
3329 | return; | |
3330 | ||
3331 | ixgbevf_watchdog_update_link(adapter); | |
3332 | ||
443ebdd6 | 3333 | if (adapter->link_up && adapter->link_state) |
9ac5c5cc ET |
3334 | ixgbevf_watchdog_link_is_up(adapter); |
3335 | else | |
3336 | ixgbevf_watchdog_link_is_down(adapter); | |
3337 | ||
3338 | ixgbevf_update_stats(adapter); | |
3339 | } | |
3340 | ||
3341 | /** | |
3342 | * ixgbevf_service_task - manages and runs subtasks | |
92915f71 GR |
3343 | * @work: pointer to work_struct containing our data |
3344 | **/ | |
9ac5c5cc | 3345 | static void ixgbevf_service_task(struct work_struct *work) |
92915f71 GR |
3346 | { |
3347 | struct ixgbevf_adapter *adapter = container_of(work, | |
3348 | struct ixgbevf_adapter, | |
9ac5c5cc | 3349 | service_task); |
92915f71 | 3350 | struct ixgbe_hw *hw = &adapter->hw; |
92915f71 | 3351 | |
26597802 MR |
3352 | if (IXGBE_REMOVED(hw->hw_addr)) { |
3353 | if (!test_bit(__IXGBEVF_DOWN, &adapter->state)) { | |
3354 | rtnl_lock(); | |
3355 | ixgbevf_down(adapter); | |
3356 | rtnl_unlock(); | |
3357 | } | |
3358 | return; | |
3359 | } | |
e66c92ad | 3360 | |
220fe050 | 3361 | ixgbevf_queue_reset_subtask(adapter); |
9ac5c5cc ET |
3362 | ixgbevf_reset_subtask(adapter); |
3363 | ixgbevf_watchdog_subtask(adapter); | |
e66c92ad ET |
3364 | ixgbevf_check_hang_subtask(adapter); |
3365 | ||
9ac5c5cc | 3366 | ixgbevf_service_event_complete(adapter); |
92915f71 GR |
3367 | } |
3368 | ||
3369 | /** | |
3370 | * ixgbevf_free_tx_resources - Free Tx Resources per Queue | |
92915f71 GR |
3371 | * @tx_ring: Tx descriptor ring for a specific queue |
3372 | * | |
3373 | * Free all transmit software resources | |
3374 | **/ | |
05d063aa | 3375 | void ixgbevf_free_tx_resources(struct ixgbevf_ring *tx_ring) |
92915f71 | 3376 | { |
05d063aa | 3377 | ixgbevf_clean_tx_ring(tx_ring); |
92915f71 GR |
3378 | |
3379 | vfree(tx_ring->tx_buffer_info); | |
3380 | tx_ring->tx_buffer_info = NULL; | |
3381 | ||
de02decb DS |
3382 | /* if not set, then don't free */ |
3383 | if (!tx_ring->desc) | |
3384 | return; | |
3385 | ||
05d063aa | 3386 | dma_free_coherent(tx_ring->dev, tx_ring->size, tx_ring->desc, |
2a1f8794 | 3387 | tx_ring->dma); |
92915f71 GR |
3388 | |
3389 | tx_ring->desc = NULL; | |
3390 | } | |
3391 | ||
3392 | /** | |
3393 | * ixgbevf_free_all_tx_resources - Free Tx Resources for All Queues | |
3394 | * @adapter: board private structure | |
3395 | * | |
3396 | * Free all transmit software resources | |
3397 | **/ | |
3398 | static void ixgbevf_free_all_tx_resources(struct ixgbevf_adapter *adapter) | |
3399 | { | |
3400 | int i; | |
3401 | ||
3402 | for (i = 0; i < adapter->num_tx_queues; i++) | |
87e70ab9 | 3403 | if (adapter->tx_ring[i]->desc) |
05d063aa | 3404 | ixgbevf_free_tx_resources(adapter->tx_ring[i]); |
21092e9c TN |
3405 | for (i = 0; i < adapter->num_xdp_queues; i++) |
3406 | if (adapter->xdp_ring[i]->desc) | |
3407 | ixgbevf_free_tx_resources(adapter->xdp_ring[i]); | |
92915f71 GR |
3408 | } |
3409 | ||
3410 | /** | |
3411 | * ixgbevf_setup_tx_resources - allocate Tx resources (Descriptors) | |
dec0d8e4 | 3412 | * @tx_ring: Tx descriptor ring (for a specific queue) to setup |
92915f71 GR |
3413 | * |
3414 | * Return 0 on success, negative on failure | |
3415 | **/ | |
05d063aa | 3416 | int ixgbevf_setup_tx_resources(struct ixgbevf_ring *tx_ring) |
92915f71 | 3417 | { |
4ad6af02 | 3418 | struct ixgbevf_adapter *adapter = netdev_priv(tx_ring->netdev); |
92915f71 GR |
3419 | int size; |
3420 | ||
3421 | size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count; | |
865a4d98 | 3422 | tx_ring->tx_buffer_info = vmalloc(size); |
92915f71 GR |
3423 | if (!tx_ring->tx_buffer_info) |
3424 | goto err; | |
92915f71 | 3425 | |
7c3a4626 FF |
3426 | u64_stats_init(&tx_ring->syncp); |
3427 | ||
92915f71 GR |
3428 | /* round up to nearest 4K */ |
3429 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); | |
3430 | tx_ring->size = ALIGN(tx_ring->size, 4096); | |
3431 | ||
05d063aa | 3432 | tx_ring->desc = dma_alloc_coherent(tx_ring->dev, tx_ring->size, |
2a1f8794 | 3433 | &tx_ring->dma, GFP_KERNEL); |
92915f71 GR |
3434 | if (!tx_ring->desc) |
3435 | goto err; | |
3436 | ||
92915f71 GR |
3437 | return 0; |
3438 | ||
3439 | err: | |
3440 | vfree(tx_ring->tx_buffer_info); | |
3441 | tx_ring->tx_buffer_info = NULL; | |
dec0d8e4 | 3442 | hw_dbg(&adapter->hw, "Unable to allocate memory for the transmit descriptor ring\n"); |
92915f71 GR |
3443 | return -ENOMEM; |
3444 | } | |
3445 | ||
3446 | /** | |
3447 | * ixgbevf_setup_all_tx_resources - allocate all queues Tx resources | |
3448 | * @adapter: board private structure | |
3449 | * | |
3450 | * If this function returns with an error, then it's possible one or | |
3451 | * more of the rings is populated (while the rest are not). It is the | |
3452 | * callers duty to clean those orphaned rings. | |
3453 | * | |
3454 | * Return 0 on success, negative on failure | |
3455 | **/ | |
3456 | static int ixgbevf_setup_all_tx_resources(struct ixgbevf_adapter *adapter) | |
3457 | { | |
21092e9c | 3458 | int i, j = 0, err = 0; |
92915f71 GR |
3459 | |
3460 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
05d063aa | 3461 | err = ixgbevf_setup_tx_resources(adapter->tx_ring[i]); |
92915f71 GR |
3462 | if (!err) |
3463 | continue; | |
dec0d8e4 | 3464 | hw_dbg(&adapter->hw, "Allocation for Tx Queue %u failed\n", i); |
f2d00eca | 3465 | goto err_setup_tx; |
92915f71 GR |
3466 | } |
3467 | ||
21092e9c TN |
3468 | for (j = 0; j < adapter->num_xdp_queues; j++) { |
3469 | err = ixgbevf_setup_tx_resources(adapter->xdp_ring[j]); | |
3470 | if (!err) | |
3471 | continue; | |
3472 | hw_dbg(&adapter->hw, "Allocation for XDP Queue %u failed\n", j); | |
39035bfd | 3473 | goto err_setup_tx; |
21092e9c TN |
3474 | } |
3475 | ||
f2d00eca ET |
3476 | return 0; |
3477 | err_setup_tx: | |
3478 | /* rewind the index freeing the rings as we go */ | |
21092e9c TN |
3479 | while (j--) |
3480 | ixgbevf_free_tx_resources(adapter->xdp_ring[j]); | |
f2d00eca ET |
3481 | while (i--) |
3482 | ixgbevf_free_tx_resources(adapter->tx_ring[i]); | |
21092e9c | 3483 | |
92915f71 GR |
3484 | return err; |
3485 | } | |
3486 | ||
3487 | /** | |
3488 | * ixgbevf_setup_rx_resources - allocate Rx resources (Descriptors) | |
c7aec596 | 3489 | * @adapter: board private structure |
dec0d8e4 | 3490 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup |
92915f71 GR |
3491 | * |
3492 | * Returns 0 on success, negative on failure | |
3493 | **/ | |
c7aec596 TN |
3494 | int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter, |
3495 | struct ixgbevf_ring *rx_ring) | |
92915f71 | 3496 | { |
92915f71 GR |
3497 | int size; |
3498 | ||
3499 | size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count; | |
40b8178b | 3500 | rx_ring->rx_buffer_info = vmalloc(size); |
e404decb | 3501 | if (!rx_ring->rx_buffer_info) |
05d063aa | 3502 | goto err; |
92915f71 | 3503 | |
7c3a4626 FF |
3504 | u64_stats_init(&rx_ring->syncp); |
3505 | ||
92915f71 GR |
3506 | /* Round up to nearest 4K */ |
3507 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); | |
3508 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
3509 | ||
05d063aa | 3510 | rx_ring->desc = dma_alloc_coherent(rx_ring->dev, rx_ring->size, |
2a1f8794 | 3511 | &rx_ring->dma, GFP_KERNEL); |
92915f71 | 3512 | |
05d063aa ET |
3513 | if (!rx_ring->desc) |
3514 | goto err; | |
92915f71 | 3515 | |
c7aec596 TN |
3516 | /* XDP RX-queue info */ |
3517 | if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, | |
b02e5a0e | 3518 | rx_ring->queue_index, 0) < 0) |
c7aec596 TN |
3519 | goto err; |
3520 | ||
3521 | rx_ring->xdp_prog = adapter->xdp_prog; | |
3522 | ||
92915f71 | 3523 | return 0; |
05d063aa ET |
3524 | err: |
3525 | vfree(rx_ring->rx_buffer_info); | |
3526 | rx_ring->rx_buffer_info = NULL; | |
3527 | dev_err(rx_ring->dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
92915f71 GR |
3528 | return -ENOMEM; |
3529 | } | |
3530 | ||
3531 | /** | |
3532 | * ixgbevf_setup_all_rx_resources - allocate all queues Rx resources | |
3533 | * @adapter: board private structure | |
3534 | * | |
3535 | * If this function returns with an error, then it's possible one or | |
3536 | * more of the rings is populated (while the rest are not). It is the | |
3537 | * callers duty to clean those orphaned rings. | |
3538 | * | |
3539 | * Return 0 on success, negative on failure | |
3540 | **/ | |
3541 | static int ixgbevf_setup_all_rx_resources(struct ixgbevf_adapter *adapter) | |
3542 | { | |
3543 | int i, err = 0; | |
3544 | ||
3545 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
c7aec596 | 3546 | err = ixgbevf_setup_rx_resources(adapter, adapter->rx_ring[i]); |
92915f71 GR |
3547 | if (!err) |
3548 | continue; | |
dec0d8e4 | 3549 | hw_dbg(&adapter->hw, "Allocation for Rx Queue %u failed\n", i); |
f2d00eca | 3550 | goto err_setup_rx; |
92915f71 | 3551 | } |
f2d00eca ET |
3552 | |
3553 | return 0; | |
3554 | err_setup_rx: | |
3555 | /* rewind the index freeing the rings as we go */ | |
3556 | while (i--) | |
3557 | ixgbevf_free_rx_resources(adapter->rx_ring[i]); | |
92915f71 GR |
3558 | return err; |
3559 | } | |
3560 | ||
3561 | /** | |
3562 | * ixgbevf_free_rx_resources - Free Rx Resources | |
92915f71 GR |
3563 | * @rx_ring: ring to clean the resources from |
3564 | * | |
3565 | * Free all receive software resources | |
3566 | **/ | |
05d063aa | 3567 | void ixgbevf_free_rx_resources(struct ixgbevf_ring *rx_ring) |
92915f71 | 3568 | { |
05d063aa | 3569 | ixgbevf_clean_rx_ring(rx_ring); |
92915f71 | 3570 | |
c7aec596 TN |
3571 | rx_ring->xdp_prog = NULL; |
3572 | xdp_rxq_info_unreg(&rx_ring->xdp_rxq); | |
92915f71 GR |
3573 | vfree(rx_ring->rx_buffer_info); |
3574 | rx_ring->rx_buffer_info = NULL; | |
3575 | ||
05d063aa | 3576 | dma_free_coherent(rx_ring->dev, rx_ring->size, rx_ring->desc, |
2a1f8794 | 3577 | rx_ring->dma); |
92915f71 GR |
3578 | |
3579 | rx_ring->desc = NULL; | |
3580 | } | |
3581 | ||
3582 | /** | |
3583 | * ixgbevf_free_all_rx_resources - Free Rx Resources for All Queues | |
3584 | * @adapter: board private structure | |
3585 | * | |
3586 | * Free all receive software resources | |
3587 | **/ | |
3588 | static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter) | |
3589 | { | |
3590 | int i; | |
3591 | ||
3592 | for (i = 0; i < adapter->num_rx_queues; i++) | |
87e70ab9 | 3593 | if (adapter->rx_ring[i]->desc) |
05d063aa | 3594 | ixgbevf_free_rx_resources(adapter->rx_ring[i]); |
92915f71 GR |
3595 | } |
3596 | ||
3597 | /** | |
3598 | * ixgbevf_open - Called when a network interface is made active | |
3599 | * @netdev: network interface device structure | |
3600 | * | |
3601 | * Returns 0 on success, negative value on failure | |
3602 | * | |
3603 | * The open entry point is called when a network interface is made | |
3604 | * active by the system (IFF_UP). At this point all resources needed | |
3605 | * for transmit and receive operations are allocated, the interrupt | |
3606 | * handler is registered with the OS, the watchdog timer is started, | |
3607 | * and the stack is notified that the interface is ready. | |
3608 | **/ | |
324d0867 | 3609 | int ixgbevf_open(struct net_device *netdev) |
92915f71 GR |
3610 | { |
3611 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
3612 | struct ixgbe_hw *hw = &adapter->hw; | |
3613 | int err; | |
3614 | ||
a1f6c6b1 | 3615 | /* A previous failure to open the device because of a lack of |
3616 | * available MSIX vector resources may have reset the number | |
3617 | * of msix vectors variable to zero. The only way to recover | |
3618 | * is to unload/reload the driver and hope that the system has | |
3619 | * been able to recover some MSIX vector resources. | |
3620 | */ | |
3621 | if (!adapter->num_msix_vectors) | |
3622 | return -ENOMEM; | |
3623 | ||
92915f71 GR |
3624 | if (hw->adapter_stopped) { |
3625 | ixgbevf_reset(adapter); | |
3626 | /* if adapter is still stopped then PF isn't up and | |
dec0d8e4 JK |
3627 | * the VF can't start. |
3628 | */ | |
92915f71 GR |
3629 | if (hw->adapter_stopped) { |
3630 | err = IXGBE_ERR_MBX; | |
dec0d8e4 | 3631 | pr_err("Unable to start - perhaps the PF Driver isn't up yet\n"); |
92915f71 GR |
3632 | goto err_setup_reset; |
3633 | } | |
3634 | } | |
3635 | ||
d9bdb57f ET |
3636 | /* disallow open during test */ |
3637 | if (test_bit(__IXGBEVF_TESTING, &adapter->state)) | |
3638 | return -EBUSY; | |
3639 | ||
3640 | netif_carrier_off(netdev); | |
3641 | ||
92915f71 GR |
3642 | /* allocate transmit descriptors */ |
3643 | err = ixgbevf_setup_all_tx_resources(adapter); | |
3644 | if (err) | |
3645 | goto err_setup_tx; | |
3646 | ||
3647 | /* allocate receive descriptors */ | |
3648 | err = ixgbevf_setup_all_rx_resources(adapter); | |
3649 | if (err) | |
3650 | goto err_setup_rx; | |
3651 | ||
3652 | ixgbevf_configure(adapter); | |
3653 | ||
92915f71 GR |
3654 | err = ixgbevf_request_irq(adapter); |
3655 | if (err) | |
3656 | goto err_req_irq; | |
3657 | ||
f2d00eca ET |
3658 | /* Notify the stack of the actual queue counts. */ |
3659 | err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues); | |
3660 | if (err) | |
3661 | goto err_set_queues; | |
3662 | ||
3663 | err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues); | |
3664 | if (err) | |
3665 | goto err_set_queues; | |
3666 | ||
d9bdb57f | 3667 | ixgbevf_up_complete(adapter); |
92915f71 GR |
3668 | |
3669 | return 0; | |
3670 | ||
f2d00eca ET |
3671 | err_set_queues: |
3672 | ixgbevf_free_irq(adapter); | |
92915f71 | 3673 | err_req_irq: |
92915f71 | 3674 | ixgbevf_free_all_rx_resources(adapter); |
f2d00eca | 3675 | err_setup_rx: |
92915f71 | 3676 | ixgbevf_free_all_tx_resources(adapter); |
f2d00eca | 3677 | err_setup_tx: |
92915f71 | 3678 | ixgbevf_reset(adapter); |
92915f71 GR |
3679 | err_setup_reset: |
3680 | ||
3681 | return err; | |
3682 | } | |
3683 | ||
b19cf6ee ET |
3684 | /** |
3685 | * ixgbevf_close_suspend - actions necessary to both suspend and close flows | |
3686 | * @adapter: the private adapter struct | |
3687 | * | |
3688 | * This function should contain the necessary work common to both suspending | |
3689 | * and closing of the device. | |
3690 | */ | |
3691 | static void ixgbevf_close_suspend(struct ixgbevf_adapter *adapter) | |
3692 | { | |
3693 | ixgbevf_down(adapter); | |
3694 | ixgbevf_free_irq(adapter); | |
3695 | ixgbevf_free_all_tx_resources(adapter); | |
3696 | ixgbevf_free_all_rx_resources(adapter); | |
3697 | } | |
3698 | ||
92915f71 GR |
3699 | /** |
3700 | * ixgbevf_close - Disables a network interface | |
3701 | * @netdev: network interface device structure | |
3702 | * | |
3703 | * Returns 0, this is not allowed to fail | |
3704 | * | |
3705 | * The close entry point is called when an interface is de-activated | |
3706 | * by the OS. The hardware is still under the drivers control, but | |
3707 | * needs to be disabled. A global MAC reset is issued to stop the | |
3708 | * hardware, and all transmit and receive resources are freed. | |
3709 | **/ | |
324d0867 | 3710 | int ixgbevf_close(struct net_device *netdev) |
92915f71 GR |
3711 | { |
3712 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
3713 | ||
b19cf6ee ET |
3714 | if (netif_device_present(netdev)) |
3715 | ixgbevf_close_suspend(adapter); | |
92915f71 GR |
3716 | |
3717 | return 0; | |
3718 | } | |
3719 | ||
220fe050 DS |
3720 | static void ixgbevf_queue_reset_subtask(struct ixgbevf_adapter *adapter) |
3721 | { | |
3722 | struct net_device *dev = adapter->netdev; | |
3723 | ||
d5dd7c3f ET |
3724 | if (!test_and_clear_bit(__IXGBEVF_QUEUE_RESET_REQUESTED, |
3725 | &adapter->state)) | |
220fe050 DS |
3726 | return; |
3727 | ||
220fe050 DS |
3728 | /* if interface is down do nothing */ |
3729 | if (test_bit(__IXGBEVF_DOWN, &adapter->state) || | |
3730 | test_bit(__IXGBEVF_RESETTING, &adapter->state)) | |
3731 | return; | |
3732 | ||
3733 | /* Hardware has to reinitialize queues and interrupts to | |
3734 | * match packet buffer alignment. Unfortunately, the | |
3735 | * hardware is not flexible enough to do this dynamically. | |
3736 | */ | |
2dad7b27 ET |
3737 | rtnl_lock(); |
3738 | ||
220fe050 DS |
3739 | if (netif_running(dev)) |
3740 | ixgbevf_close(dev); | |
3741 | ||
3742 | ixgbevf_clear_interrupt_scheme(adapter); | |
3743 | ixgbevf_init_interrupt_scheme(adapter); | |
3744 | ||
3745 | if (netif_running(dev)) | |
3746 | ixgbevf_open(dev); | |
2dad7b27 ET |
3747 | |
3748 | rtnl_unlock(); | |
220fe050 DS |
3749 | } |
3750 | ||
70a10e25 | 3751 | static void ixgbevf_tx_ctxtdesc(struct ixgbevf_ring *tx_ring, |
7f68d430 SN |
3752 | u32 vlan_macip_lens, u32 fceof_saidx, |
3753 | u32 type_tucmd, u32 mss_l4len_idx) | |
92915f71 GR |
3754 | { |
3755 | struct ixgbe_adv_tx_context_desc *context_desc; | |
70a10e25 | 3756 | u16 i = tx_ring->next_to_use; |
92915f71 | 3757 | |
70a10e25 | 3758 | context_desc = IXGBEVF_TX_CTXTDESC(tx_ring, i); |
92915f71 | 3759 | |
70a10e25 AD |
3760 | i++; |
3761 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
92915f71 | 3762 | |
70a10e25 AD |
3763 | /* set bits to identify this as an advanced context descriptor */ |
3764 | type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; | |
92915f71 | 3765 | |
70a10e25 | 3766 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); |
7f68d430 | 3767 | context_desc->fceof_saidx = cpu_to_le32(fceof_saidx); |
70a10e25 AD |
3768 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); |
3769 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
3770 | } | |
3771 | ||
3772 | static int ixgbevf_tso(struct ixgbevf_ring *tx_ring, | |
7ad1a093 | 3773 | struct ixgbevf_tx_buffer *first, |
7f68d430 SN |
3774 | u8 *hdr_len, |
3775 | struct ixgbevf_ipsec_tx_data *itd) | |
70a10e25 | 3776 | { |
b83e3010 | 3777 | u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; |
7ad1a093 | 3778 | struct sk_buff *skb = first->skb; |
b83e3010 AD |
3779 | union { |
3780 | struct iphdr *v4; | |
3781 | struct ipv6hdr *v6; | |
3782 | unsigned char *hdr; | |
3783 | } ip; | |
3784 | union { | |
3785 | struct tcphdr *tcp; | |
3786 | unsigned char *hdr; | |
3787 | } l4; | |
3788 | u32 paylen, l4_offset; | |
7f68d430 | 3789 | u32 fceof_saidx = 0; |
8f12c034 | 3790 | int err; |
70a10e25 | 3791 | |
01a545cf ET |
3792 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
3793 | return 0; | |
3794 | ||
70a10e25 AD |
3795 | if (!skb_is_gso(skb)) |
3796 | return 0; | |
92915f71 | 3797 | |
8f12c034 FR |
3798 | err = skb_cow_head(skb, 0); |
3799 | if (err < 0) | |
3800 | return err; | |
92915f71 | 3801 | |
2a20525b SP |
3802 | if (eth_p_mpls(first->protocol)) |
3803 | ip.hdr = skb_inner_network_header(skb); | |
3804 | else | |
3805 | ip.hdr = skb_network_header(skb); | |
b83e3010 AD |
3806 | l4.hdr = skb_checksum_start(skb); |
3807 | ||
70a10e25 AD |
3808 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
3809 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
3810 | ||
b83e3010 AD |
3811 | /* initialize outer IP header fields */ |
3812 | if (ip.v4->version == 4) { | |
c54cdc31 AD |
3813 | unsigned char *csum_start = skb_checksum_start(skb); |
3814 | unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); | |
7f68d430 | 3815 | int len = csum_start - trans_start; |
c54cdc31 | 3816 | |
b83e3010 | 3817 | /* IP header will have to cancel out any data that |
7f68d430 SN |
3818 | * is not a part of the outer IP header, so set to |
3819 | * a reverse csum if needed, else init check to 0. | |
b83e3010 | 3820 | */ |
7f68d430 SN |
3821 | ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? |
3822 | csum_fold(csum_partial(trans_start, | |
3823 | len, 0)) : 0; | |
70a10e25 | 3824 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; |
b83e3010 AD |
3825 | |
3826 | ip.v4->tot_len = 0; | |
7ad1a093 ET |
3827 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
3828 | IXGBE_TX_FLAGS_CSUM | | |
3829 | IXGBE_TX_FLAGS_IPV4; | |
b83e3010 AD |
3830 | } else { |
3831 | ip.v6->payload_len = 0; | |
7ad1a093 ET |
3832 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
3833 | IXGBE_TX_FLAGS_CSUM; | |
70a10e25 AD |
3834 | } |
3835 | ||
b83e3010 AD |
3836 | /* determine offset of inner transport header */ |
3837 | l4_offset = l4.hdr - skb->data; | |
3838 | ||
3839 | /* compute length of segmentation header */ | |
3840 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
70a10e25 | 3841 | |
b83e3010 AD |
3842 | /* remove payload length from inner checksum */ |
3843 | paylen = skb->len - l4_offset; | |
de844713 | 3844 | csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); |
b83e3010 AD |
3845 | |
3846 | /* update gso size and bytecount with header size */ | |
7ad1a093 ET |
3847 | first->gso_segs = skb_shinfo(skb)->gso_segs; |
3848 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
3849 | ||
70a10e25 | 3850 | /* mss_l4len_id: use 1 as index for TSO */ |
b83e3010 | 3851 | mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; |
70a10e25 | 3852 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; |
8d055cc0 | 3853 | mss_l4len_idx |= (1u << IXGBE_ADVTXD_IDX_SHIFT); |
70a10e25 | 3854 | |
7f68d430 SN |
3855 | fceof_saidx |= itd->pfsa; |
3856 | type_tucmd |= itd->flags | itd->trailer_len; | |
3857 | ||
70a10e25 | 3858 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ |
b83e3010 AD |
3859 | vlan_macip_lens = l4.hdr - ip.hdr; |
3860 | vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
7ad1a093 | 3861 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
70a10e25 | 3862 | |
7f68d430 SN |
3863 | ixgbevf_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, |
3864 | mss_l4len_idx); | |
70a10e25 AD |
3865 | |
3866 | return 1; | |
92915f71 GR |
3867 | } |
3868 | ||
7ad1a093 | 3869 | static void ixgbevf_tx_csum(struct ixgbevf_ring *tx_ring, |
7f68d430 SN |
3870 | struct ixgbevf_tx_buffer *first, |
3871 | struct ixgbevf_ipsec_tx_data *itd) | |
92915f71 | 3872 | { |
7ad1a093 | 3873 | struct sk_buff *skb = first->skb; |
70a10e25 | 3874 | u32 vlan_macip_lens = 0; |
7f68d430 | 3875 | u32 fceof_saidx = 0; |
70a10e25 | 3876 | u32 type_tucmd = 0; |
92915f71 | 3877 | |
cb2b3edb AD |
3878 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
3879 | goto no_csum; | |
92915f71 | 3880 | |
cb2b3edb AD |
3881 | switch (skb->csum_offset) { |
3882 | case offsetof(struct tcphdr, check): | |
3883 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5463fce6 | 3884 | fallthrough; |
cb2b3edb AD |
3885 | case offsetof(struct udphdr, check): |
3886 | break; | |
3887 | case offsetof(struct sctphdr, checksum): | |
3888 | /* validate that this is actually an SCTP request */ | |
fc186d0a | 3889 | if (skb_csum_is_sctp(skb)) { |
cb2b3edb | 3890 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
70a10e25 | 3891 | break; |
70a10e25 | 3892 | } |
5463fce6 | 3893 | fallthrough; |
cb2b3edb AD |
3894 | default: |
3895 | skb_checksum_help(skb); | |
3896 | goto no_csum; | |
92915f71 | 3897 | } |
7fb94bd5 SB |
3898 | |
3899 | if (first->protocol == htons(ETH_P_IP)) | |
3900 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
3901 | ||
cb2b3edb AD |
3902 | /* update TX checksum flag */ |
3903 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
3904 | vlan_macip_lens = skb_checksum_start_offset(skb) - | |
3905 | skb_network_offset(skb); | |
d34a614a | 3906 | no_csum: |
70a10e25 AD |
3907 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
3908 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
7ad1a093 | 3909 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
70a10e25 | 3910 | |
7f68d430 SN |
3911 | fceof_saidx |= itd->pfsa; |
3912 | type_tucmd |= itd->flags | itd->trailer_len; | |
3913 | ||
3914 | ixgbevf_tx_ctxtdesc(tx_ring, vlan_macip_lens, | |
3915 | fceof_saidx, type_tucmd, 0); | |
92915f71 GR |
3916 | } |
3917 | ||
29d37fa1 | 3918 | static __le32 ixgbevf_tx_cmd_type(u32 tx_flags) |
92915f71 | 3919 | { |
29d37fa1 ET |
3920 | /* set type for advanced descriptor with frame checksum insertion */ |
3921 | __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | | |
3922 | IXGBE_ADVTXD_DCMD_IFCS | | |
3923 | IXGBE_ADVTXD_DCMD_DEXT); | |
92915f71 | 3924 | |
dec0d8e4 | 3925 | /* set HW VLAN bit if VLAN is present */ |
29d37fa1 ET |
3926 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) |
3927 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); | |
92915f71 | 3928 | |
29d37fa1 ET |
3929 | /* set segmentation enable bits for TSO/FSO */ |
3930 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
3931 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); | |
92915f71 | 3932 | |
29d37fa1 ET |
3933 | return cmd_type; |
3934 | } | |
92915f71 | 3935 | |
29d37fa1 ET |
3936 | static void ixgbevf_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
3937 | u32 tx_flags, unsigned int paylen) | |
3938 | { | |
3939 | __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); | |
9bdfefd2 | 3940 | |
29d37fa1 ET |
3941 | /* enable L4 checksum for TSO and TX checksum offload */ |
3942 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
3943 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); | |
92915f71 | 3944 | |
29d37fa1 ET |
3945 | /* enble IPv4 checksum for TSO */ |
3946 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
3947 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); | |
92915f71 | 3948 | |
7f68d430 SN |
3949 | /* enable IPsec */ |
3950 | if (tx_flags & IXGBE_TX_FLAGS_IPSEC) | |
3951 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IPSEC); | |
3952 | ||
3953 | /* use index 1 context for TSO/FSO/FCOE/IPSEC */ | |
3954 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_IPSEC)) | |
8d055cc0 | 3955 | olinfo_status |= cpu_to_le32(1u << IXGBE_ADVTXD_IDX_SHIFT); |
92915f71 | 3956 | |
29d37fa1 ET |
3957 | /* Check Context must be set if Tx switch is enabled, which it |
3958 | * always is for case where virtual functions are running | |
3959 | */ | |
3960 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); | |
92915f71 | 3961 | |
29d37fa1 ET |
3962 | tx_desc->read.olinfo_status = olinfo_status; |
3963 | } | |
92915f71 | 3964 | |
29d37fa1 ET |
3965 | static void ixgbevf_tx_map(struct ixgbevf_ring *tx_ring, |
3966 | struct ixgbevf_tx_buffer *first, | |
3967 | const u8 hdr_len) | |
3968 | { | |
29d37fa1 ET |
3969 | struct sk_buff *skb = first->skb; |
3970 | struct ixgbevf_tx_buffer *tx_buffer; | |
3971 | union ixgbe_adv_tx_desc *tx_desc; | |
d7840976 | 3972 | skb_frag_t *frag; |
6f355454 ET |
3973 | dma_addr_t dma; |
3974 | unsigned int data_len, size; | |
29d37fa1 | 3975 | u32 tx_flags = first->tx_flags; |
6f355454 | 3976 | __le32 cmd_type = ixgbevf_tx_cmd_type(tx_flags); |
29d37fa1 | 3977 | u16 i = tx_ring->next_to_use; |
9bdfefd2 | 3978 | |
29d37fa1 | 3979 | tx_desc = IXGBEVF_TX_DESC(tx_ring, i); |
92915f71 | 3980 | |
6f355454 ET |
3981 | ixgbevf_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); |
3982 | ||
3983 | size = skb_headlen(skb); | |
3984 | data_len = skb->data_len; | |
7ad1a093 | 3985 | |
29d37fa1 | 3986 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
92915f71 | 3987 | |
6f355454 | 3988 | tx_buffer = first; |
92915f71 | 3989 | |
6f355454 ET |
3990 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { |
3991 | if (dma_mapping_error(tx_ring->dev, dma)) | |
3992 | goto dma_error; | |
3993 | ||
3994 | /* record length, and DMA address */ | |
3995 | dma_unmap_len_set(tx_buffer, len, size); | |
3996 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
3997 | ||
3998 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
92915f71 | 3999 | |
29d37fa1 ET |
4000 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
4001 | tx_desc->read.cmd_type_len = | |
4002 | cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); | |
92915f71 | 4003 | |
29d37fa1 ET |
4004 | i++; |
4005 | tx_desc++; | |
4006 | if (i == tx_ring->count) { | |
4007 | tx_desc = IXGBEVF_TX_DESC(tx_ring, 0); | |
4008 | i = 0; | |
4009 | } | |
6f355454 | 4010 | tx_desc->read.olinfo_status = 0; |
92915f71 | 4011 | |
29d37fa1 ET |
4012 | dma += IXGBE_MAX_DATA_PER_TXD; |
4013 | size -= IXGBE_MAX_DATA_PER_TXD; | |
92915f71 | 4014 | |
29d37fa1 | 4015 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
29d37fa1 | 4016 | } |
92915f71 | 4017 | |
29d37fa1 ET |
4018 | if (likely(!data_len)) |
4019 | break; | |
92915f71 | 4020 | |
29d37fa1 | 4021 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
92915f71 | 4022 | |
29d37fa1 ET |
4023 | i++; |
4024 | tx_desc++; | |
4025 | if (i == tx_ring->count) { | |
4026 | tx_desc = IXGBEVF_TX_DESC(tx_ring, 0); | |
4027 | i = 0; | |
4028 | } | |
6f355454 | 4029 | tx_desc->read.olinfo_status = 0; |
92915f71 | 4030 | |
29d37fa1 ET |
4031 | size = skb_frag_size(frag); |
4032 | data_len -= size; | |
92915f71 | 4033 | |
29d37fa1 ET |
4034 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
4035 | DMA_TO_DEVICE); | |
70a10e25 | 4036 | |
29d37fa1 | 4037 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
70a10e25 | 4038 | } |
92915f71 | 4039 | |
29d37fa1 ET |
4040 | /* write last descriptor with RS and EOP bits */ |
4041 | cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD); | |
4042 | tx_desc->read.cmd_type_len = cmd_type; | |
4043 | ||
4044 | /* set the timestamp */ | |
4045 | first->time_stamp = jiffies; | |
4046 | ||
9fc145fc JK |
4047 | skb_tx_timestamp(skb); |
4048 | ||
29d37fa1 ET |
4049 | /* Force memory writes to complete before letting h/w know there |
4050 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
4051 | * memory model archs, such as IA-64). | |
4052 | * | |
4053 | * We also need this memory barrier (wmb) to make certain all of the | |
4054 | * status bits have been updated before next_to_watch is written. | |
70a10e25 | 4055 | */ |
29d37fa1 | 4056 | wmb(); |
92915f71 | 4057 | |
29d37fa1 ET |
4058 | /* set next_to_watch value indicating a packet is present */ |
4059 | first->next_to_watch = tx_desc; | |
92915f71 | 4060 | |
29d37fa1 ET |
4061 | i++; |
4062 | if (i == tx_ring->count) | |
4063 | i = 0; | |
9bdfefd2 | 4064 | |
29d37fa1 | 4065 | tx_ring->next_to_use = i; |
92915f71 | 4066 | |
29d37fa1 | 4067 | /* notify HW of packet */ |
06380db6 | 4068 | ixgbevf_write_tail(tx_ring, i); |
29d37fa1 ET |
4069 | |
4070 | return; | |
4071 | dma_error: | |
4072 | dev_err(tx_ring->dev, "TX DMA map failed\n"); | |
865a4d98 | 4073 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
29d37fa1 ET |
4074 | |
4075 | /* clear dma mappings for failed tx_buffer_info map */ | |
865a4d98 ET |
4076 | while (tx_buffer != first) { |
4077 | if (dma_unmap_len(tx_buffer, len)) | |
4078 | dma_unmap_page(tx_ring->dev, | |
4079 | dma_unmap_addr(tx_buffer, dma), | |
4080 | dma_unmap_len(tx_buffer, len), | |
4081 | DMA_TO_DEVICE); | |
4082 | dma_unmap_len_set(tx_buffer, len, 0); | |
4083 | ||
4084 | if (i-- == 0) | |
4085 | i += tx_ring->count; | |
29d37fa1 | 4086 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
29d37fa1 | 4087 | } |
92915f71 | 4088 | |
865a4d98 ET |
4089 | if (dma_unmap_len(tx_buffer, len)) |
4090 | dma_unmap_single(tx_ring->dev, | |
4091 | dma_unmap_addr(tx_buffer, dma), | |
4092 | dma_unmap_len(tx_buffer, len), | |
4093 | DMA_TO_DEVICE); | |
4094 | dma_unmap_len_set(tx_buffer, len, 0); | |
4095 | ||
4096 | dev_kfree_skb_any(tx_buffer->skb); | |
4097 | tx_buffer->skb = NULL; | |
4098 | ||
92915f71 | 4099 | tx_ring->next_to_use = i; |
92915f71 GR |
4100 | } |
4101 | ||
fb40195c | 4102 | static int __ixgbevf_maybe_stop_tx(struct ixgbevf_ring *tx_ring, int size) |
92915f71 | 4103 | { |
fb40195c | 4104 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
92915f71 GR |
4105 | /* Herbert's original patch had: |
4106 | * smp_mb__after_netif_stop_queue(); | |
dec0d8e4 JK |
4107 | * but since that doesn't exist yet, just open code it. |
4108 | */ | |
92915f71 GR |
4109 | smp_mb(); |
4110 | ||
4111 | /* We need to check again in a case another CPU has just | |
dec0d8e4 JK |
4112 | * made room available. |
4113 | */ | |
f880d07b | 4114 | if (likely(ixgbevf_desc_unused(tx_ring) < size)) |
92915f71 GR |
4115 | return -EBUSY; |
4116 | ||
4117 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fb40195c | 4118 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
095e2617 ET |
4119 | ++tx_ring->tx_stats.restart_queue; |
4120 | ||
92915f71 GR |
4121 | return 0; |
4122 | } | |
4123 | ||
fb40195c | 4124 | static int ixgbevf_maybe_stop_tx(struct ixgbevf_ring *tx_ring, int size) |
92915f71 | 4125 | { |
f880d07b | 4126 | if (likely(ixgbevf_desc_unused(tx_ring) >= size)) |
92915f71 | 4127 | return 0; |
fb40195c | 4128 | return __ixgbevf_maybe_stop_tx(tx_ring, size); |
92915f71 GR |
4129 | } |
4130 | ||
5cc0f1c0 ET |
4131 | static int ixgbevf_xmit_frame_ring(struct sk_buff *skb, |
4132 | struct ixgbevf_ring *tx_ring) | |
92915f71 | 4133 | { |
7ad1a093 | 4134 | struct ixgbevf_tx_buffer *first; |
7ad1a093 ET |
4135 | int tso; |
4136 | u32 tx_flags = 0; | |
3595990a | 4137 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
7f68d430 | 4138 | struct ixgbevf_ipsec_tx_data ipsec_tx = { 0 }; |
3595990a AD |
4139 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD |
4140 | unsigned short f; | |
4141 | #endif | |
7ad1a093 | 4142 | u8 hdr_len = 0; |
f9d08f16 | 4143 | u8 *dst_mac = skb_header_pointer(skb, 0, 0, NULL); |
7ad1a093 | 4144 | |
46acc460 | 4145 | if (!dst_mac || is_link_local_ether_addr(dst_mac)) { |
e7fcd543 | 4146 | dev_kfree_skb_any(skb); |
f9d08f16 GR |
4147 | return NETDEV_TX_OK; |
4148 | } | |
92915f71 | 4149 | |
dec0d8e4 | 4150 | /* need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, |
3595990a AD |
4151 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
4152 | * + 2 desc gap to keep tail from touching head, | |
4153 | * + 1 desc for context descriptor, | |
4154 | * otherwise try next time | |
4155 | */ | |
4156 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
d601be97 QC |
4157 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { |
4158 | skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; | |
4159 | ||
4160 | count += TXD_USE_COUNT(skb_frag_size(frag)); | |
4161 | } | |
3595990a AD |
4162 | #else |
4163 | count += skb_shinfo(skb)->nr_frags; | |
4164 | #endif | |
fb40195c | 4165 | if (ixgbevf_maybe_stop_tx(tx_ring, count + 3)) { |
095e2617 | 4166 | tx_ring->tx_stats.tx_busy++; |
3595990a AD |
4167 | return NETDEV_TX_BUSY; |
4168 | } | |
4169 | ||
7ad1a093 ET |
4170 | /* record the location of the first descriptor for this packet */ |
4171 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
4172 | first->skb = skb; | |
4173 | first->bytecount = skb->len; | |
4174 | first->gso_segs = 1; | |
4175 | ||
df8a39de JP |
4176 | if (skb_vlan_tag_present(skb)) { |
4177 | tx_flags |= skb_vlan_tag_get(skb); | |
92915f71 GR |
4178 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
4179 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
4180 | } | |
4181 | ||
7ad1a093 ET |
4182 | /* record initial flags and protocol */ |
4183 | first->tx_flags = tx_flags; | |
4184 | first->protocol = vlan_get_protocol(skb); | |
92915f71 | 4185 | |
48e01e00 | 4186 | #ifdef CONFIG_IXGBEVF_IPSEC |
8f6617ba | 4187 | if (xfrm_offload(skb) && !ixgbevf_ipsec_tx(tx_ring, first, &ipsec_tx)) |
7f68d430 SN |
4188 | goto out_drop; |
4189 | #endif | |
4190 | tso = ixgbevf_tso(tx_ring, first, &hdr_len, &ipsec_tx); | |
7ad1a093 ET |
4191 | if (tso < 0) |
4192 | goto out_drop; | |
b5d217f3 | 4193 | else if (!tso) |
7f68d430 | 4194 | ixgbevf_tx_csum(tx_ring, first, &ipsec_tx); |
92915f71 | 4195 | |
29d37fa1 | 4196 | ixgbevf_tx_map(tx_ring, first, hdr_len); |
70a10e25 | 4197 | |
fb40195c | 4198 | ixgbevf_maybe_stop_tx(tx_ring, DESC_NEEDED); |
92915f71 | 4199 | |
7ad1a093 ET |
4200 | return NETDEV_TX_OK; |
4201 | ||
4202 | out_drop: | |
4203 | dev_kfree_skb_any(first->skb); | |
4204 | first->skb = NULL; | |
4205 | ||
92915f71 GR |
4206 | return NETDEV_TX_OK; |
4207 | } | |
4208 | ||
cf12aab6 | 4209 | static netdev_tx_t ixgbevf_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
5cc0f1c0 ET |
4210 | { |
4211 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
4212 | struct ixgbevf_ring *tx_ring; | |
4213 | ||
4214 | if (skb->len <= 0) { | |
4215 | dev_kfree_skb_any(skb); | |
4216 | return NETDEV_TX_OK; | |
4217 | } | |
4218 | ||
4219 | /* The minimum packet size for olinfo paylen is 17 so pad the skb | |
4220 | * in order to meet this minimum size requirement. | |
4221 | */ | |
4222 | if (skb->len < 17) { | |
4223 | if (skb_padto(skb, 17)) | |
4224 | return NETDEV_TX_OK; | |
4225 | skb->len = 17; | |
4226 | } | |
4227 | ||
4228 | tx_ring = adapter->tx_ring[skb->queue_mapping]; | |
4229 | return ixgbevf_xmit_frame_ring(skb, tx_ring); | |
4230 | } | |
4231 | ||
92915f71 GR |
4232 | /** |
4233 | * ixgbevf_set_mac - Change the Ethernet Address of the NIC | |
4234 | * @netdev: network interface device structure | |
4235 | * @p: pointer to an address structure | |
4236 | * | |
4237 | * Returns 0 on success, negative on failure | |
4238 | **/ | |
4239 | static int ixgbevf_set_mac(struct net_device *netdev, void *p) | |
4240 | { | |
4241 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
4242 | struct ixgbe_hw *hw = &adapter->hw; | |
4243 | struct sockaddr *addr = p; | |
32ca6868 | 4244 | int err; |
92915f71 GR |
4245 | |
4246 | if (!is_valid_ether_addr(addr->sa_data)) | |
4247 | return -EADDRNOTAVAIL; | |
4248 | ||
55fdd45b | 4249 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 4250 | |
32ca6868 | 4251 | err = hw->mac.ops.set_rar(hw, 0, addr->sa_data, 0); |
92915f71 | 4252 | |
55fdd45b | 4253 | spin_unlock_bh(&adapter->mbx_lock); |
1c55ed76 | 4254 | |
32ca6868 ET |
4255 | if (err) |
4256 | return -EPERM; | |
4257 | ||
4258 | ether_addr_copy(hw->mac.addr, addr->sa_data); | |
6e7d0ba1 | 4259 | ether_addr_copy(hw->mac.perm_addr, addr->sa_data); |
f3956ebb | 4260 | eth_hw_addr_set(netdev, addr->sa_data); |
32ca6868 | 4261 | |
92915f71 GR |
4262 | return 0; |
4263 | } | |
4264 | ||
4265 | /** | |
4266 | * ixgbevf_change_mtu - Change the Maximum Transfer Unit | |
4267 | * @netdev: network interface device structure | |
4268 | * @new_mtu: new value for maximum frame size | |
4269 | * | |
4270 | * Returns 0 on success, negative on failure | |
4271 | **/ | |
4272 | static int ixgbevf_change_mtu(struct net_device *netdev, int new_mtu) | |
4273 | { | |
4274 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
bad17234 | 4275 | struct ixgbe_hw *hw = &adapter->hw; |
92915f71 | 4276 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
6a11e52b | 4277 | int ret; |
69bfbec4 | 4278 | |
c7aec596 TN |
4279 | /* prevent MTU being changed to a size unsupported by XDP */ |
4280 | if (adapter->xdp_prog) { | |
4281 | dev_warn(&adapter->pdev->dev, "MTU cannot be changed while XDP program is loaded\n"); | |
4282 | return -EPERM; | |
4283 | } | |
4284 | ||
14b22cd9 | 4285 | spin_lock_bh(&adapter->mbx_lock); |
6a11e52b TN |
4286 | /* notify the PF of our intent to use this size of frame */ |
4287 | ret = hw->mac.ops.set_rlpml(hw, max_frame); | |
14b22cd9 | 4288 | spin_unlock_bh(&adapter->mbx_lock); |
6a11e52b TN |
4289 | if (ret) |
4290 | return -EINVAL; | |
4291 | ||
bad17234 | 4292 | hw_dbg(hw, "changing MTU from %d to %d\n", |
92915f71 | 4293 | netdev->mtu, new_mtu); |
6a11e52b | 4294 | |
92915f71 | 4295 | /* must set new MTU before calling down or up */ |
1eb2cded | 4296 | WRITE_ONCE(netdev->mtu, new_mtu); |
92915f71 | 4297 | |
1ab37e12 ET |
4298 | if (netif_running(netdev)) |
4299 | ixgbevf_reinit_locked(adapter); | |
4300 | ||
92915f71 GR |
4301 | return 0; |
4302 | } | |
4303 | ||
75a3f93b | 4304 | static int ixgbevf_suspend(struct device *dev_d) |
92915f71 | 4305 | { |
bac66317 | 4306 | struct net_device *netdev = dev_get_drvdata(dev_d); |
92915f71 GR |
4307 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); |
4308 | ||
2dad7b27 | 4309 | rtnl_lock(); |
92915f71 GR |
4310 | netif_device_detach(netdev); |
4311 | ||
b19cf6ee ET |
4312 | if (netif_running(netdev)) |
4313 | ixgbevf_close_suspend(adapter); | |
4314 | ||
4315 | ixgbevf_clear_interrupt_scheme(adapter); | |
2dad7b27 | 4316 | rtnl_unlock(); |
92915f71 | 4317 | |
0ac1e8ce AD |
4318 | return 0; |
4319 | } | |
4320 | ||
75a3f93b | 4321 | static int ixgbevf_resume(struct device *dev_d) |
0ac1e8ce | 4322 | { |
bac66317 | 4323 | struct pci_dev *pdev = to_pci_dev(dev_d); |
27ae2967 WY |
4324 | struct net_device *netdev = pci_get_drvdata(pdev); |
4325 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
0ac1e8ce AD |
4326 | u32 err; |
4327 | ||
26403b7f | 4328 | adapter->hw.hw_addr = adapter->io_addr; |
4e857c58 | 4329 | smp_mb__before_atomic(); |
bc0c7151 | 4330 | clear_bit(__IXGBEVF_DISABLED, &adapter->state); |
0ac1e8ce AD |
4331 | pci_set_master(pdev); |
4332 | ||
798e381a DS |
4333 | ixgbevf_reset(adapter); |
4334 | ||
0ac1e8ce AD |
4335 | rtnl_lock(); |
4336 | err = ixgbevf_init_interrupt_scheme(adapter); | |
f2d00eca ET |
4337 | if (!err && netif_running(netdev)) |
4338 | err = ixgbevf_open(netdev); | |
0ac1e8ce | 4339 | rtnl_unlock(); |
f2d00eca | 4340 | if (err) |
0ac1e8ce | 4341 | return err; |
0ac1e8ce AD |
4342 | |
4343 | netif_device_attach(netdev); | |
4344 | ||
4345 | return err; | |
4346 | } | |
4347 | ||
0ac1e8ce AD |
4348 | static void ixgbevf_shutdown(struct pci_dev *pdev) |
4349 | { | |
bac66317 | 4350 | ixgbevf_suspend(&pdev->dev); |
92915f71 GR |
4351 | } |
4352 | ||
21092e9c TN |
4353 | static void ixgbevf_get_tx_ring_stats(struct rtnl_link_stats64 *stats, |
4354 | const struct ixgbevf_ring *ring) | |
4355 | { | |
4356 | u64 bytes, packets; | |
4357 | unsigned int start; | |
4358 | ||
4359 | if (ring) { | |
4360 | do { | |
068c38ad | 4361 | start = u64_stats_fetch_begin(&ring->syncp); |
21092e9c TN |
4362 | bytes = ring->stats.bytes; |
4363 | packets = ring->stats.packets; | |
068c38ad | 4364 | } while (u64_stats_fetch_retry(&ring->syncp, start)); |
21092e9c TN |
4365 | stats->tx_bytes += bytes; |
4366 | stats->tx_packets += packets; | |
4367 | } | |
4368 | } | |
4369 | ||
bc1f4470 | 4370 | static void ixgbevf_get_stats(struct net_device *netdev, |
4371 | struct rtnl_link_stats64 *stats) | |
4197aa7b ED |
4372 | { |
4373 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
4374 | unsigned int start; | |
4375 | u64 bytes, packets; | |
4376 | const struct ixgbevf_ring *ring; | |
4377 | int i; | |
4378 | ||
4379 | ixgbevf_update_stats(adapter); | |
4380 | ||
4381 | stats->multicast = adapter->stats.vfmprc - adapter->stats.base_vfmprc; | |
4382 | ||
21c046e4 | 4383 | rcu_read_lock(); |
4197aa7b | 4384 | for (i = 0; i < adapter->num_rx_queues; i++) { |
87e70ab9 | 4385 | ring = adapter->rx_ring[i]; |
4197aa7b | 4386 | do { |
068c38ad | 4387 | start = u64_stats_fetch_begin(&ring->syncp); |
095e2617 ET |
4388 | bytes = ring->stats.bytes; |
4389 | packets = ring->stats.packets; | |
068c38ad | 4390 | } while (u64_stats_fetch_retry(&ring->syncp, start)); |
4197aa7b ED |
4391 | stats->rx_bytes += bytes; |
4392 | stats->rx_packets += packets; | |
4393 | } | |
4394 | ||
4395 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
87e70ab9 | 4396 | ring = adapter->tx_ring[i]; |
21092e9c TN |
4397 | ixgbevf_get_tx_ring_stats(stats, ring); |
4398 | } | |
4399 | ||
4400 | for (i = 0; i < adapter->num_xdp_queues; i++) { | |
4401 | ring = adapter->xdp_ring[i]; | |
4402 | ixgbevf_get_tx_ring_stats(stats, ring); | |
4197aa7b | 4403 | } |
21c046e4 | 4404 | rcu_read_unlock(); |
4197aa7b ED |
4405 | } |
4406 | ||
b83e3010 AD |
4407 | #define IXGBEVF_MAX_MAC_HDR_LEN 127 |
4408 | #define IXGBEVF_MAX_NETWORK_HDR_LEN 511 | |
4409 | ||
4410 | static netdev_features_t | |
4411 | ixgbevf_features_check(struct sk_buff *skb, struct net_device *dev, | |
4412 | netdev_features_t features) | |
4413 | { | |
4414 | unsigned int network_hdr_len, mac_hdr_len; | |
4415 | ||
4416 | /* Make certain the headers can be described by a context descriptor */ | |
80bfab79 | 4417 | mac_hdr_len = skb_network_offset(skb); |
b83e3010 AD |
4418 | if (unlikely(mac_hdr_len > IXGBEVF_MAX_MAC_HDR_LEN)) |
4419 | return features & ~(NETIF_F_HW_CSUM | | |
4420 | NETIF_F_SCTP_CRC | | |
4421 | NETIF_F_HW_VLAN_CTAG_TX | | |
4422 | NETIF_F_TSO | | |
4423 | NETIF_F_TSO6); | |
4424 | ||
4425 | network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); | |
4426 | if (unlikely(network_hdr_len > IXGBEVF_MAX_NETWORK_HDR_LEN)) | |
4427 | return features & ~(NETIF_F_HW_CSUM | | |
4428 | NETIF_F_SCTP_CRC | | |
4429 | NETIF_F_TSO | | |
4430 | NETIF_F_TSO6); | |
4431 | ||
4432 | /* We can only support IPV4 TSO in tunnels if we can mangle the | |
4433 | * inner IP ID field, so strip TSO if MANGLEID is not supported. | |
4434 | */ | |
4435 | if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) | |
4436 | features &= ~NETIF_F_TSO; | |
4437 | ||
4438 | return features; | |
4439 | } | |
4440 | ||
c7aec596 TN |
4441 | static int ixgbevf_xdp_setup(struct net_device *dev, struct bpf_prog *prog) |
4442 | { | |
4443 | int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
4444 | struct ixgbevf_adapter *adapter = netdev_priv(dev); | |
4445 | struct bpf_prog *old_prog; | |
4446 | ||
4447 | /* verify ixgbevf ring attributes are sufficient for XDP */ | |
4448 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4449 | struct ixgbevf_ring *ring = adapter->rx_ring[i]; | |
4450 | ||
4451 | if (frame_size > ixgbevf_rx_bufsz(ring)) | |
4452 | return -EINVAL; | |
4453 | } | |
4454 | ||
4455 | old_prog = xchg(&adapter->xdp_prog, prog); | |
21092e9c TN |
4456 | |
4457 | /* If transitioning XDP modes reconfigure rings */ | |
4458 | if (!!prog != !!old_prog) { | |
4459 | /* Hardware has to reinitialize queues and interrupts to | |
4460 | * match packet buffer alignment. Unfortunately, the | |
4461 | * hardware is not flexible enough to do this dynamically. | |
4462 | */ | |
4463 | if (netif_running(dev)) | |
4464 | ixgbevf_close(dev); | |
4465 | ||
4466 | ixgbevf_clear_interrupt_scheme(adapter); | |
4467 | ixgbevf_init_interrupt_scheme(adapter); | |
4468 | ||
4469 | if (netif_running(dev)) | |
4470 | ixgbevf_open(dev); | |
4471 | } else { | |
4472 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4473 | xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog); | |
4474 | } | |
c7aec596 TN |
4475 | |
4476 | if (old_prog) | |
4477 | bpf_prog_put(old_prog); | |
4478 | ||
4479 | return 0; | |
4480 | } | |
4481 | ||
4482 | static int ixgbevf_xdp(struct net_device *dev, struct netdev_bpf *xdp) | |
4483 | { | |
c7aec596 TN |
4484 | switch (xdp->command) { |
4485 | case XDP_SETUP_PROG: | |
4486 | return ixgbevf_xdp_setup(dev, xdp->prog); | |
c7aec596 TN |
4487 | default: |
4488 | return -EINVAL; | |
4489 | } | |
4490 | } | |
4491 | ||
0ac1e8ce | 4492 | static const struct net_device_ops ixgbevf_netdev_ops = { |
c12db769 SH |
4493 | .ndo_open = ixgbevf_open, |
4494 | .ndo_stop = ixgbevf_close, | |
4495 | .ndo_start_xmit = ixgbevf_xmit_frame, | |
4496 | .ndo_set_rx_mode = ixgbevf_set_rx_mode, | |
4197aa7b | 4497 | .ndo_get_stats64 = ixgbevf_get_stats, |
92915f71 | 4498 | .ndo_validate_addr = eth_validate_addr, |
c12db769 SH |
4499 | .ndo_set_mac_address = ixgbevf_set_mac, |
4500 | .ndo_change_mtu = ixgbevf_change_mtu, | |
4501 | .ndo_tx_timeout = ixgbevf_tx_timeout, | |
c12db769 SH |
4502 | .ndo_vlan_rx_add_vid = ixgbevf_vlan_rx_add_vid, |
4503 | .ndo_vlan_rx_kill_vid = ixgbevf_vlan_rx_kill_vid, | |
b83e3010 | 4504 | .ndo_features_check = ixgbevf_features_check, |
c7aec596 | 4505 | .ndo_bpf = ixgbevf_xdp, |
92915f71 | 4506 | }; |
92915f71 GR |
4507 | |
4508 | static void ixgbevf_assign_netdev_ops(struct net_device *dev) | |
4509 | { | |
0ac1e8ce | 4510 | dev->netdev_ops = &ixgbevf_netdev_ops; |
92915f71 GR |
4511 | ixgbevf_set_ethtool_ops(dev); |
4512 | dev->watchdog_timeo = 5 * HZ; | |
4513 | } | |
4514 | ||
4515 | /** | |
4516 | * ixgbevf_probe - Device Initialization Routine | |
4517 | * @pdev: PCI device information struct | |
4518 | * @ent: entry in ixgbevf_pci_tbl | |
4519 | * | |
4520 | * Returns 0 on success, negative on failure | |
4521 | * | |
4522 | * ixgbevf_probe initializes an adapter identified by a pci_dev structure. | |
4523 | * The OS initialization, configuring of the adapter private structure, | |
4524 | * and a hardware reset occur. | |
4525 | **/ | |
1dd06ae8 | 4526 | static int ixgbevf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
92915f71 GR |
4527 | { |
4528 | struct net_device *netdev; | |
4529 | struct ixgbevf_adapter *adapter = NULL; | |
4530 | struct ixgbe_hw *hw = NULL; | |
4531 | const struct ixgbevf_info *ii = ixgbevf_info_tbl[ent->driver_data]; | |
0333464f | 4532 | bool disable_dev = false; |
90b83d01 | 4533 | int err; |
92915f71 GR |
4534 | |
4535 | err = pci_enable_device(pdev); | |
4536 | if (err) | |
4537 | return err; | |
4538 | ||
90b83d01 CJ |
4539 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
4540 | if (err) { | |
4541 | dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); | |
4542 | goto err_dma; | |
92915f71 GR |
4543 | } |
4544 | ||
4545 | err = pci_request_regions(pdev, ixgbevf_driver_name); | |
4546 | if (err) { | |
4547 | dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err); | |
4548 | goto err_pci_reg; | |
4549 | } | |
4550 | ||
4551 | pci_set_master(pdev); | |
4552 | ||
92915f71 GR |
4553 | netdev = alloc_etherdev_mq(sizeof(struct ixgbevf_adapter), |
4554 | MAX_TX_QUEUES); | |
92915f71 GR |
4555 | if (!netdev) { |
4556 | err = -ENOMEM; | |
4557 | goto err_alloc_etherdev; | |
4558 | } | |
4559 | ||
4560 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
4561 | ||
92915f71 GR |
4562 | adapter = netdev_priv(netdev); |
4563 | ||
4564 | adapter->netdev = netdev; | |
4565 | adapter->pdev = pdev; | |
4566 | hw = &adapter->hw; | |
4567 | hw->back = adapter; | |
b3f4d599 | 4568 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
92915f71 | 4569 | |
dec0d8e4 | 4570 | /* call save state here in standalone driver because it relies on |
92915f71 GR |
4571 | * adapter struct to exist, and needs to call netdev_priv |
4572 | */ | |
4573 | pci_save_state(pdev); | |
4574 | ||
4575 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), | |
4576 | pci_resource_len(pdev, 0)); | |
dbf8b0d8 | 4577 | adapter->io_addr = hw->hw_addr; |
92915f71 GR |
4578 | if (!hw->hw_addr) { |
4579 | err = -EIO; | |
4580 | goto err_ioremap; | |
4581 | } | |
4582 | ||
4583 | ixgbevf_assign_netdev_ops(netdev); | |
4584 | ||
dec0d8e4 | 4585 | /* Setup HW API */ |
92915f71 GR |
4586 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); |
4587 | hw->mac.type = ii->mac; | |
4588 | ||
9c9463c2 | 4589 | memcpy(&hw->mbx.ops, &ixgbevf_mbx_ops_legacy, |
f416dfc0 | 4590 | sizeof(struct ixgbe_mbx_operations)); |
92915f71 | 4591 | |
92915f71 GR |
4592 | /* setup the private structure */ |
4593 | err = ixgbevf_sw_init(adapter); | |
1a0d6ae5 DK |
4594 | if (err) |
4595 | goto err_sw_init; | |
4596 | ||
4597 | /* The HW MAC address was set and/or determined in sw_init */ | |
1a0d6ae5 DK |
4598 | if (!is_valid_ether_addr(netdev->dev_addr)) { |
4599 | pr_err("invalid MAC address\n"); | |
4600 | err = -EIO; | |
4601 | goto err_sw_init; | |
4602 | } | |
92915f71 | 4603 | |
471a76de | 4604 | netdev->hw_features = NETIF_F_SG | |
dec0d8e4 JK |
4605 | NETIF_F_TSO | |
4606 | NETIF_F_TSO6 | | |
cb2b3edb AD |
4607 | NETIF_F_RXCSUM | |
4608 | NETIF_F_HW_CSUM | | |
4609 | NETIF_F_SCTP_CRC; | |
471a76de | 4610 | |
b83e3010 AD |
4611 | #define IXGBEVF_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ |
4612 | NETIF_F_GSO_GRE_CSUM | \ | |
7e13318d | 4613 | NETIF_F_GSO_IPXIP4 | \ |
bf2d1df3 | 4614 | NETIF_F_GSO_IPXIP6 | \ |
b83e3010 AD |
4615 | NETIF_F_GSO_UDP_TUNNEL | \ |
4616 | NETIF_F_GSO_UDP_TUNNEL_CSUM) | |
92915f71 | 4617 | |
b83e3010 AD |
4618 | netdev->gso_partial_features = IXGBEVF_GSO_PARTIAL_FEATURES; |
4619 | netdev->hw_features |= NETIF_F_GSO_PARTIAL | | |
4620 | IXGBEVF_GSO_PARTIAL_FEATURES; | |
cb2b3edb | 4621 | |
90b83d01 | 4622 | netdev->features = netdev->hw_features | NETIF_F_HIGHDMA; |
92915f71 | 4623 | |
b83e3010 | 4624 | netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; |
2a20525b SP |
4625 | netdev->mpls_features |= NETIF_F_SG | |
4626 | NETIF_F_TSO | | |
4627 | NETIF_F_TSO6 | | |
4628 | NETIF_F_HW_CSUM; | |
4629 | netdev->mpls_features |= IXGBEVF_GSO_PARTIAL_FEATURES; | |
b83e3010 AD |
4630 | netdev->hw_enc_features |= netdev->vlan_features; |
4631 | ||
4632 | /* set this bit last since it cannot be part of vlan_features */ | |
4633 | netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | | |
4634 | NETIF_F_HW_VLAN_CTAG_RX | | |
4635 | NETIF_F_HW_VLAN_CTAG_TX; | |
4636 | ||
01789349 | 4637 | netdev->priv_flags |= IFF_UNICAST_FLT; |
66c0e13a | 4638 | netdev->xdp_features = NETDEV_XDP_ACT_BASIC; |
01789349 | 4639 | |
91c527a5 JW |
4640 | /* MTU range: 68 - 1504 or 9710 */ |
4641 | netdev->min_mtu = ETH_MIN_MTU; | |
4642 | switch (adapter->hw.api_version) { | |
4643 | case ixgbe_mbox_api_11: | |
4644 | case ixgbe_mbox_api_12: | |
41e544cd | 4645 | case ixgbe_mbox_api_13: |
7f68d430 | 4646 | case ixgbe_mbox_api_14: |
339f2896 | 4647 | case ixgbe_mbox_api_15: |
91c527a5 JW |
4648 | netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - |
4649 | (ETH_HLEN + ETH_FCS_LEN); | |
4650 | break; | |
4651 | default: | |
4652 | if (adapter->hw.mac.type != ixgbe_mac_82599_vf) | |
4653 | netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - | |
4654 | (ETH_HLEN + ETH_FCS_LEN); | |
4655 | else | |
4656 | netdev->max_mtu = ETH_DATA_LEN + ETH_FCS_LEN; | |
4657 | break; | |
4658 | } | |
4659 | ||
ea699569 MR |
4660 | if (IXGBE_REMOVED(hw->hw_addr)) { |
4661 | err = -EIO; | |
4662 | goto err_sw_init; | |
4663 | } | |
9ac5c5cc | 4664 | |
26566eae | 4665 | timer_setup(&adapter->service_timer, ixgbevf_service_timer, 0); |
9ac5c5cc ET |
4666 | |
4667 | INIT_WORK(&adapter->service_task, ixgbevf_service_task); | |
4668 | set_bit(__IXGBEVF_SERVICE_INITED, &adapter->state); | |
4669 | clear_bit(__IXGBEVF_SERVICE_SCHED, &adapter->state); | |
92915f71 GR |
4670 | |
4671 | err = ixgbevf_init_interrupt_scheme(adapter); | |
4672 | if (err) | |
4673 | goto err_sw_init; | |
4674 | ||
92915f71 GR |
4675 | strcpy(netdev->name, "eth%d"); |
4676 | ||
4677 | err = register_netdev(netdev); | |
4678 | if (err) | |
4679 | goto err_register; | |
4680 | ||
0333464f | 4681 | pci_set_drvdata(pdev, netdev); |
5d426ad1 | 4682 | netif_carrier_off(netdev); |
7f68d430 | 4683 | ixgbevf_init_ipsec_offload(adapter); |
5d426ad1 | 4684 | |
33bd9f60 GR |
4685 | ixgbevf_init_last_counter_stats(adapter); |
4686 | ||
47068b0d ET |
4687 | /* print the VF info */ |
4688 | dev_info(&pdev->dev, "%pM\n", netdev->dev_addr); | |
4689 | dev_info(&pdev->dev, "MAC: %d\n", hw->mac.type); | |
92915f71 | 4690 | |
47068b0d ET |
4691 | switch (hw->mac.type) { |
4692 | case ixgbe_mac_X550_vf: | |
4693 | dev_info(&pdev->dev, "Intel(R) X550 Virtual Function\n"); | |
4694 | break; | |
4695 | case ixgbe_mac_X540_vf: | |
4696 | dev_info(&pdev->dev, "Intel(R) X540 Virtual Function\n"); | |
4697 | break; | |
4c44b450 PK |
4698 | case ixgbe_mac_e610_vf: |
4699 | dev_info(&pdev->dev, "Intel(R) E610 Virtual Function\n"); | |
4700 | break; | |
47068b0d ET |
4701 | case ixgbe_mac_82599_vf: |
4702 | default: | |
4703 | dev_info(&pdev->dev, "Intel(R) 82599 Virtual Function\n"); | |
4704 | break; | |
4705 | } | |
92915f71 | 4706 | |
92915f71 GR |
4707 | return 0; |
4708 | ||
4709 | err_register: | |
0ac1e8ce | 4710 | ixgbevf_clear_interrupt_scheme(adapter); |
92915f71 GR |
4711 | err_sw_init: |
4712 | ixgbevf_reset_interrupt_capability(adapter); | |
dbf8b0d8 | 4713 | iounmap(adapter->io_addr); |
e60ae003 | 4714 | kfree(adapter->rss_key); |
92915f71 | 4715 | err_ioremap: |
0333464f | 4716 | disable_dev = !test_and_set_bit(__IXGBEVF_DISABLED, &adapter->state); |
92915f71 GR |
4717 | free_netdev(netdev); |
4718 | err_alloc_etherdev: | |
4719 | pci_release_regions(pdev); | |
4720 | err_pci_reg: | |
4721 | err_dma: | |
0333464f | 4722 | if (!adapter || disable_dev) |
bc0c7151 | 4723 | pci_disable_device(pdev); |
92915f71 GR |
4724 | return err; |
4725 | } | |
4726 | ||
4727 | /** | |
4728 | * ixgbevf_remove - Device Removal Routine | |
4729 | * @pdev: PCI device information struct | |
4730 | * | |
4731 | * ixgbevf_remove is called by the PCI subsystem to alert the driver | |
4732 | * that it should release a PCI device. The could be caused by a | |
4733 | * Hot-Plug event, or because the driver is going to be removed from | |
4734 | * memory. | |
4735 | **/ | |
9f9a12f8 | 4736 | static void ixgbevf_remove(struct pci_dev *pdev) |
92915f71 GR |
4737 | { |
4738 | struct net_device *netdev = pci_get_drvdata(pdev); | |
0333464f ET |
4739 | struct ixgbevf_adapter *adapter; |
4740 | bool disable_dev; | |
4741 | ||
4742 | if (!netdev) | |
4743 | return; | |
4744 | ||
4745 | adapter = netdev_priv(netdev); | |
92915f71 | 4746 | |
2e7cfbdd | 4747 | set_bit(__IXGBEVF_REMOVING, &adapter->state); |
9ac5c5cc | 4748 | cancel_work_sync(&adapter->service_task); |
92915f71 | 4749 | |
fd13a9ab | 4750 | if (netdev->reg_state == NETREG_REGISTERED) |
92915f71 | 4751 | unregister_netdev(netdev); |
92915f71 | 4752 | |
7f68d430 | 4753 | ixgbevf_stop_ipsec_offload(adapter); |
0ac1e8ce | 4754 | ixgbevf_clear_interrupt_scheme(adapter); |
92915f71 GR |
4755 | ixgbevf_reset_interrupt_capability(adapter); |
4756 | ||
dbf8b0d8 | 4757 | iounmap(adapter->io_addr); |
92915f71 GR |
4758 | pci_release_regions(pdev); |
4759 | ||
4760 | hw_dbg(&adapter->hw, "Remove complete\n"); | |
4761 | ||
e60ae003 | 4762 | kfree(adapter->rss_key); |
0333464f | 4763 | disable_dev = !test_and_set_bit(__IXGBEVF_DISABLED, &adapter->state); |
92915f71 GR |
4764 | free_netdev(netdev); |
4765 | ||
0333464f | 4766 | if (disable_dev) |
bc0c7151 | 4767 | pci_disable_device(pdev); |
92915f71 GR |
4768 | } |
4769 | ||
9f19f31d AD |
4770 | /** |
4771 | * ixgbevf_io_error_detected - called when PCI error is detected | |
4772 | * @pdev: Pointer to PCI device | |
4773 | * @state: The current pci connection state | |
4774 | * | |
4775 | * This function is called after a PCI bus error affecting | |
4776 | * this device has been detected. | |
dec0d8e4 | 4777 | **/ |
9f19f31d AD |
4778 | static pci_ers_result_t ixgbevf_io_error_detected(struct pci_dev *pdev, |
4779 | pci_channel_state_t state) | |
4780 | { | |
4781 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4782 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
4783 | ||
9ac5c5cc | 4784 | if (!test_bit(__IXGBEVF_SERVICE_INITED, &adapter->state)) |
ea699569 MR |
4785 | return PCI_ERS_RESULT_DISCONNECT; |
4786 | ||
bc0c7151 | 4787 | rtnl_lock(); |
9f19f31d AD |
4788 | netif_device_detach(netdev); |
4789 | ||
b212d815 MR |
4790 | if (netif_running(netdev)) |
4791 | ixgbevf_close_suspend(adapter); | |
4792 | ||
bc0c7151 MR |
4793 | if (state == pci_channel_io_perm_failure) { |
4794 | rtnl_unlock(); | |
9f19f31d | 4795 | return PCI_ERS_RESULT_DISCONNECT; |
bc0c7151 | 4796 | } |
9f19f31d | 4797 | |
bc0c7151 MR |
4798 | if (!test_and_set_bit(__IXGBEVF_DISABLED, &adapter->state)) |
4799 | pci_disable_device(pdev); | |
4800 | rtnl_unlock(); | |
9f19f31d | 4801 | |
8bfb7869 | 4802 | /* Request a slot reset. */ |
9f19f31d AD |
4803 | return PCI_ERS_RESULT_NEED_RESET; |
4804 | } | |
4805 | ||
4806 | /** | |
4807 | * ixgbevf_io_slot_reset - called after the pci bus has been reset. | |
4808 | * @pdev: Pointer to PCI device | |
4809 | * | |
4810 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
4811 | * resembles the first-half of the ixgbevf_resume routine. | |
dec0d8e4 | 4812 | **/ |
9f19f31d AD |
4813 | static pci_ers_result_t ixgbevf_io_slot_reset(struct pci_dev *pdev) |
4814 | { | |
4815 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4816 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
4817 | ||
4818 | if (pci_enable_device_mem(pdev)) { | |
4819 | dev_err(&pdev->dev, | |
4820 | "Cannot re-enable PCI device after reset.\n"); | |
4821 | return PCI_ERS_RESULT_DISCONNECT; | |
4822 | } | |
4823 | ||
26403b7f | 4824 | adapter->hw.hw_addr = adapter->io_addr; |
4e857c58 | 4825 | smp_mb__before_atomic(); |
bc0c7151 | 4826 | clear_bit(__IXGBEVF_DISABLED, &adapter->state); |
9f19f31d AD |
4827 | pci_set_master(pdev); |
4828 | ||
4829 | ixgbevf_reset(adapter); | |
4830 | ||
4831 | return PCI_ERS_RESULT_RECOVERED; | |
4832 | } | |
4833 | ||
4834 | /** | |
4835 | * ixgbevf_io_resume - called when traffic can start flowing again. | |
4836 | * @pdev: Pointer to PCI device | |
4837 | * | |
4838 | * This callback is called when the error recovery driver tells us that | |
4839 | * its OK to resume normal operation. Implementation resembles the | |
4840 | * second-half of the ixgbevf_resume routine. | |
dec0d8e4 | 4841 | **/ |
9f19f31d AD |
4842 | static void ixgbevf_io_resume(struct pci_dev *pdev) |
4843 | { | |
4844 | struct net_device *netdev = pci_get_drvdata(pdev); | |
9f19f31d | 4845 | |
b19cf6ee | 4846 | rtnl_lock(); |
9f19f31d | 4847 | if (netif_running(netdev)) |
b19cf6ee | 4848 | ixgbevf_open(netdev); |
9f19f31d AD |
4849 | |
4850 | netif_device_attach(netdev); | |
b19cf6ee | 4851 | rtnl_unlock(); |
9f19f31d AD |
4852 | } |
4853 | ||
4854 | /* PCI Error Recovery (ERS) */ | |
3646f0e5 | 4855 | static const struct pci_error_handlers ixgbevf_err_handler = { |
9f19f31d AD |
4856 | .error_detected = ixgbevf_io_error_detected, |
4857 | .slot_reset = ixgbevf_io_slot_reset, | |
4858 | .resume = ixgbevf_io_resume, | |
4859 | }; | |
4860 | ||
75a3f93b | 4861 | static DEFINE_SIMPLE_DEV_PM_OPS(ixgbevf_pm_ops, ixgbevf_suspend, ixgbevf_resume); |
bac66317 | 4862 | |
92915f71 | 4863 | static struct pci_driver ixgbevf_driver = { |
dec0d8e4 JK |
4864 | .name = ixgbevf_driver_name, |
4865 | .id_table = ixgbevf_pci_tbl, | |
4866 | .probe = ixgbevf_probe, | |
4867 | .remove = ixgbevf_remove, | |
bac66317 | 4868 | |
0ac1e8ce | 4869 | /* Power Management Hooks */ |
75a3f93b | 4870 | .driver.pm = pm_sleep_ptr(&ixgbevf_pm_ops), |
bac66317 | 4871 | |
dec0d8e4 JK |
4872 | .shutdown = ixgbevf_shutdown, |
4873 | .err_handler = &ixgbevf_err_handler | |
92915f71 GR |
4874 | }; |
4875 | ||
4876 | /** | |
65d676c8 | 4877 | * ixgbevf_init_module - Driver Registration Routine |
92915f71 | 4878 | * |
65d676c8 | 4879 | * ixgbevf_init_module is the first routine called when the driver is |
92915f71 GR |
4880 | * loaded. All it does is register with the PCI subsystem. |
4881 | **/ | |
4882 | static int __init ixgbevf_init_module(void) | |
4883 | { | |
8cfa238a SX |
4884 | int err; |
4885 | ||
34a2a3b8 | 4886 | pr_info("%s\n", ixgbevf_driver_string); |
dbd9636e | 4887 | pr_info("%s\n", ixgbevf_copyright); |
40a13e24 MR |
4888 | ixgbevf_wq = create_singlethread_workqueue(ixgbevf_driver_name); |
4889 | if (!ixgbevf_wq) { | |
4890 | pr_err("%s: Failed to create workqueue\n", ixgbevf_driver_name); | |
4891 | return -ENOMEM; | |
4892 | } | |
92915f71 | 4893 | |
8cfa238a SX |
4894 | err = pci_register_driver(&ixgbevf_driver); |
4895 | if (err) { | |
4896 | destroy_workqueue(ixgbevf_wq); | |
4897 | return err; | |
4898 | } | |
4899 | ||
4900 | return 0; | |
92915f71 GR |
4901 | } |
4902 | ||
4903 | module_init(ixgbevf_init_module); | |
4904 | ||
4905 | /** | |
65d676c8 | 4906 | * ixgbevf_exit_module - Driver Exit Cleanup Routine |
92915f71 | 4907 | * |
65d676c8 | 4908 | * ixgbevf_exit_module is called just before the driver is removed |
92915f71 GR |
4909 | * from memory. |
4910 | **/ | |
4911 | static void __exit ixgbevf_exit_module(void) | |
4912 | { | |
4913 | pci_unregister_driver(&ixgbevf_driver); | |
40a13e24 MR |
4914 | if (ixgbevf_wq) { |
4915 | destroy_workqueue(ixgbevf_wq); | |
4916 | ixgbevf_wq = NULL; | |
4917 | } | |
92915f71 GR |
4918 | } |
4919 | ||
4920 | #ifdef DEBUG | |
4921 | /** | |
65d676c8 | 4922 | * ixgbevf_get_hw_dev_name - return device name string |
92915f71 | 4923 | * used by hardware layer to print debugging information |
e23cf38f | 4924 | * @hw: pointer to private hardware struct |
92915f71 GR |
4925 | **/ |
4926 | char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw) | |
4927 | { | |
4928 | struct ixgbevf_adapter *adapter = hw->back; | |
dec0d8e4 | 4929 | |
92915f71 GR |
4930 | return adapter->netdev->name; |
4931 | } | |
4932 | ||
4933 | #endif | |
4934 | module_exit(ixgbevf_exit_module); | |
4935 | ||
4936 | /* ixgbevf_main.c */ |