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ixgbe: Make return values more direct
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_x540.c
CommitLineData
fe15e8e1
DS		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
e4856696 4 Copyright(c) 1999 - 2014 Intel Corporation.
fe15e8e1
DS		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
fe15e8e1
DS		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
33#include "ixgbe.h"
34#include "ixgbe_phy.h"
fe15e8e1 35
b0007484
JK		 36#define IXGBE_X540_MAX_TX_QUEUES 128
37#define IXGBE_X540_MAX_RX_QUEUES 128
38#define IXGBE_X540_RAR_ENTRIES 128
39#define IXGBE_X540_MC_TBL_SIZE 128
40#define IXGBE_X540_VFT_TBL_SIZE 128
41#define IXGBE_X540_RX_PB_SIZE 384
fe15e8e1
DS		 42
43static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
44static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
45static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
46static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
47static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
48static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
49
b93a2226 50static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
fe15e8e1
DS		 51{
52 return ixgbe_media_type_copper;
53}
54
55static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
56{
57 struct ixgbe_mac_info *mac = &hw->mac;
58
59 /* Call PHY identify routine to get the phy type */
60 ixgbe_identify_phy_generic(hw);
61
62 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
63 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
64 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
6997d4d1 65 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
fe15e8e1
DS		 66 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
67 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
68 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
69
70 return 0;
71}
72
73/**
74 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
75 * @hw: pointer to hardware structure
76 * @speed: new link speed
fe15e8e1
DS		 77 * @autoneg_wait_to_complete: true when waiting for completion is needed
78 **/
b93a2226 79static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
fd0326f2
JH		 80 ixgbe_link_speed speed,
81 bool autoneg_wait_to_complete)
fe15e8e1 82{
99b76642 83 return hw->phy.ops.setup_link_speed(hw, speed,
e7cf745b 84 autoneg_wait_to_complete);
fe15e8e1
DS		 85}
86
87/**
88 * ixgbe_reset_hw_X540 - Perform hardware reset
89 * @hw: pointer to hardware structure
90 *
91 * Resets the hardware by resetting the transmit and receive units, masks
92 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
93 * reset.
94 **/
b93a2226 95static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
fe15e8e1 96{
8132b54e
AD		 97 s32 status;
98 u32 ctrl, i;
fe15e8e1
DS		 99
100 /* Call adapter stop to disable tx/rx and clear interrupts */
ff9d1a5a 101 status = hw->mac.ops.stop_adapter(hw);
e90dd264
MR		 102 if (status)
103 return status;
fe15e8e1 104
ff9d1a5a
ET		 105 /* flush pending Tx transactions */
106 ixgbe_clear_tx_pending(hw);
fe15e8e1 107
a4297dc2 108mac_reset_top:
8c838d73 109 ctrl = IXGBE_CTRL_RST;
8132b54e
AD		 110 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
111 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
fe15e8e1
DS		 112 IXGBE_WRITE_FLUSH(hw);
113
114 /* Poll for reset bit to self-clear indicating reset is complete */
115 for (i = 0; i < 10; i++) {
116 udelay(1);
117 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
8132b54e 118 if (!(ctrl & IXGBE_CTRL_RST_MASK))
fe15e8e1
DS		 119 break;
120 }
8132b54e
AD		 121
122 if (ctrl & IXGBE_CTRL_RST_MASK) {
fe15e8e1
DS		 123 status = IXGBE_ERR_RESET_FAILED;
124 hw_dbg(hw, "Reset polling failed to complete.\n");
125 }
8c838d73 126 msleep(100);
8132b54e 127
a4297dc2
ET		 128 /*
129 * Double resets are required for recovery from certain error
130 * conditions. Between resets, it is necessary to stall to allow time
8132b54e 131 * for any pending HW events to complete.
a4297dc2
ET		 132 */
133 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
134 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 135 goto mac_reset_top;
136 }
137
fe15e8e1
DS		 138 /* Set the Rx packet buffer size. */
139 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
140
141 /* Store the permanent mac address */
142 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
143
fe15e8e1
DS		 144 /*
145 * Store MAC address from RAR0, clear receive address registers, and
146 * clear the multicast table. Also reset num_rar_entries to 128,
147 * since we modify this value when programming the SAN MAC address.
148 */
93cb38dc 149 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
fe15e8e1
DS		 150 hw->mac.ops.init_rx_addrs(hw);
151
fe15e8e1
DS		 152 /* Store the permanent SAN mac address */
153 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
154
155 /* Add the SAN MAC address to the RAR only if it's a valid address */
f8ebc683 156 if (is_valid_ether_addr(hw->mac.san_addr)) {
fe15e8e1 157 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
e7cf745b 158 hw->mac.san_addr, 0, IXGBE_RAH_AV);
fe15e8e1 159
7fa7c9dc
AD		 160 /* Save the SAN MAC RAR index */
161 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
162
fe15e8e1
DS		 163 /* Reserve the last RAR for the SAN MAC address */
164 hw->mac.num_rar_entries--;
165 }
166
167 /* Store the alternative WWNN/WWPN prefix */
168 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
e7cf745b 169 &hw->mac.wwpn_prefix);
fe15e8e1
DS		 170
171 return status;
172}
173
7184b7cf
ET		 174/**
175 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
176 * @hw: pointer to hardware structure
177 *
178 * Starts the hardware using the generic start_hw function
179 * and the generation start_hw function.
180 * Then performs revision-specific operations, if any.
181 **/
182static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
183{
e90dd264 184 s32 ret_val;
7184b7cf
ET		 185
186 ret_val = ixgbe_start_hw_generic(hw);
e90dd264
MR		 187 if (ret_val)
188 return ret_val;
7184b7cf 189
e90dd264 190 return ixgbe_start_hw_gen2(hw);
7184b7cf
ET		 191}
192
fe15e8e1 193/**
77ed18f3
ET		 194 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
195 * @hw: pointer to hardware structure
196 *
197 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
198 * ixgbe_hw struct in order to set up EEPROM access.
fe15e8e1 199 **/
b93a2226 200static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
fe15e8e1
DS		 201{
202 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
203 u32 eec;
204 u16 eeprom_size;
205
206 if (eeprom->type == ixgbe_eeprom_uninitialized) {
207 eeprom->semaphore_delay = 10;
208 eeprom->type = ixgbe_flash;
209
210 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
211 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
e7cf745b 212 IXGBE_EEC_SIZE_SHIFT);
fe15e8e1 213 eeprom->word_size = 1 << (eeprom_size +
e7cf745b 214 IXGBE_EEPROM_WORD_SIZE_SHIFT);
fe15e8e1
DS		 215
216 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
77ed18f3 217 eeprom->type, eeprom->word_size);
fe15e8e1
DS		 218 }
219
220 return 0;
221}
222
223/**
68c7005d
ET		 224 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
225 * @hw: pointer to hardware structure
226 * @offset: offset of word in the EEPROM to read
227 * @data: word read from the EEPROM
228 *
229 * Reads a 16 bit word from the EEPROM using the EERD register.
fe15e8e1 230 **/
b93a2226 231static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
fe15e8e1 232{
e4856696
MR		 233 s32 status;
234
235 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
236 return IXGBE_ERR_SWFW_SYNC;
fe15e8e1 237
e4856696 238 status = ixgbe_read_eerd_generic(hw, offset, data);
fe15e8e1 239
6d980c3e 240 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
fe15e8e1
DS		 241 return status;
242}
243
68c7005d
ET		 244/**
245 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
246 * @hw: pointer to hardware structure
247 * @offset: offset of word in the EEPROM to read
248 * @words: number of words
249 * @data: word(s) read from the EEPROM
250 *
251 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
252 **/
253static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
254 u16 offset, u16 words, u16 *data)
255{
e4856696
MR		 256 s32 status;
257
258 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
259 return IXGBE_ERR_SWFW_SYNC;
68c7005d 260
e4856696 261 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
68c7005d
ET		 262
263 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
264 return status;
265}
266
fe15e8e1 267/**
eb9c3e3e
ET		 268 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
269 * @hw: pointer to hardware structure
270 * @offset: offset of word in the EEPROM to write
271 * @data: word write to the EEPROM
fe15e8e1 272 *
eb9c3e3e 273 * Write a 16 bit word to the EEPROM using the EEWR register.
fe15e8e1 274 **/
b93a2226 275static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
fe15e8e1 276{
e4856696
MR		 277 s32 status;
278
279 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
280 return IXGBE_ERR_SWFW_SYNC;
fe15e8e1 281
e4856696 282 status = ixgbe_write_eewr_generic(hw, offset, data);
fe15e8e1 283
eb9c3e3e 284 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
fe15e8e1
DS		 285 return status;
286}
287
68c7005d
ET		 288/**
289 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
290 * @hw: pointer to hardware structure
291 * @offset: offset of word in the EEPROM to write
292 * @words: number of words
293 * @data: word(s) write to the EEPROM
294 *
295 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
296 **/
297static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
298 u16 offset, u16 words, u16 *data)
299{
e4856696 300 s32 status;
68c7005d 301
e4856696
MR		 302 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
303 return IXGBE_ERR_SWFW_SYNC;
304
305 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
68c7005d
ET		 306
307 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
308 return status;
309}
310
fe15e8e1 311/**
eb9c3e3e
ET		 312 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
313 *
314 * This function does not use synchronization for EERD and EEWR. It can
315 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
316 *
317 * @hw: pointer to hardware structure
fe15e8e1
DS		 318 **/
319static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
320{
321 u16 i;
322 u16 j;
323 u16 checksum = 0;
324 u16 length = 0;
325 u16 pointer = 0;
326 u16 word = 0;
327
eb9c3e3e
ET		 328 /*
329 * Do not use hw->eeprom.ops.read because we do not want to take
330 * the synchronization semaphores here. Instead use
331 * ixgbe_read_eerd_generic
332 */
333
fe15e8e1
DS		 334 /* Include 0x0-0x3F in the checksum */
335 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
eb9c3e3e 336 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) {
fe15e8e1
DS		 337 hw_dbg(hw, "EEPROM read failed\n");
338 break;
339 }
340 checksum += word;
341 }
342
343 /*
344 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
345 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
346 */
347 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
348 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
349 continue;
350
eb9c3e3e 351 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) {
fe15e8e1
DS		 352 hw_dbg(hw, "EEPROM read failed\n");
353 break;
354 }
355
356 /* Skip pointer section if the pointer is invalid. */
357 if (pointer == 0xFFFF || pointer == 0 ||
358 pointer >= hw->eeprom.word_size)
359 continue;
360
eb9c3e3e 361 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) {
fe15e8e1
DS		 362 hw_dbg(hw, "EEPROM read failed\n");
363 break;
364 }
365
366 /* Skip pointer section if length is invalid. */
367 if (length == 0xFFFF || length == 0 ||
368 (pointer + length) >= hw->eeprom.word_size)
369 continue;
370
371 for (j = pointer+1; j <= pointer+length; j++) {
eb9c3e3e 372 if (ixgbe_read_eerd_generic(hw, j, &word) != 0) {
fe15e8e1
DS		 373 hw_dbg(hw, "EEPROM read failed\n");
374 break;
375 }
376 checksum += word;
377 }
378 }
379
380 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
381
382 return checksum;
383}
384
eb9c3e3e
ET		 385/**
386 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
387 * @hw: pointer to hardware structure
388 * @checksum_val: calculated checksum
389 *
390 * Performs checksum calculation and validates the EEPROM checksum. If the
391 * caller does not need checksum_val, the value can be NULL.
392 **/
393static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
394 u16 *checksum_val)
395{
396 s32 status;
397 u16 checksum;
398 u16 read_checksum = 0;
399
e4856696 400 /* Read the first word from the EEPROM. If this times out or fails, do
eb9c3e3e
ET		 401 * not continue or we could be in for a very long wait while every
402 * EEPROM read fails
403 */
404 status = hw->eeprom.ops.read(hw, 0, &checksum);
e4856696 405 if (status) {
eb9c3e3e 406 hw_dbg(hw, "EEPROM read failed\n");
e4856696 407 return status;
eb9c3e3e
ET		 408 }
409
e4856696
MR		 410 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
411 return IXGBE_ERR_SWFW_SYNC;
412
413 checksum = hw->eeprom.ops.calc_checksum(hw);
414
415 /* Do not use hw->eeprom.ops.read because we do not want to take
416 * the synchronization semaphores twice here.
417 */
418 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
419 &read_checksum);
eb9c3e3e
ET		 420
421 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
e4856696
MR		 422
423 /* If the user cares, return the calculated checksum */
424 if (checksum_val)
425 *checksum_val = checksum;
426
427 /* Verify read and calculated checksums are the same */
428 if (read_checksum != checksum)
429 return IXGBE_ERR_EEPROM_CHECKSUM;
430
eb9c3e3e
ET		 431 return status;
432}
433
fe15e8e1
DS		 434/**
435 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
436 * @hw: pointer to hardware structure
437 *
438 * After writing EEPROM to shadow RAM using EEWR register, software calculates
439 * checksum and updates the EEPROM and instructs the hardware to update
440 * the flash.
441 **/
b93a2226 442static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
fe15e8e1
DS		 443{
444 s32 status;
eb9c3e3e 445 u16 checksum;
fe15e8e1 446
e4856696 447 /* Read the first word from the EEPROM. If this times out or fails, do
eb9c3e3e
ET		 448 * not continue or we could be in for a very long wait while every
449 * EEPROM read fails
450 */
451 status = hw->eeprom.ops.read(hw, 0, &checksum);
e4856696 452 if (status) {
eb9c3e3e 453 hw_dbg(hw, "EEPROM read failed\n");
e4856696
MR		 454 return status;
455 }
eb9c3e3e 456
e4856696
MR		 457 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
458 return IXGBE_ERR_SWFW_SYNC;
fe15e8e1 459
e4856696 460 checksum = hw->eeprom.ops.calc_checksum(hw);
eb9c3e3e 461
e4856696
MR		 462 /* Do not use hw->eeprom.ops.write because we do not want to
463 * take the synchronization semaphores twice here.
464 */
465 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
466 if (!status)
fe15e8e1 467 status = ixgbe_update_flash_X540(hw);
eb9c3e3e
ET		 468
469 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
fe15e8e1
DS		 470 return status;
471}
472
473/**
474 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
475 * @hw: pointer to hardware structure
476 *
477 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
478 * EEPROM from shadow RAM to the flash device.
479 **/
480static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
481{
482 u32 flup;
e90dd264 483 s32 status;
fe15e8e1
DS		 484
485 status = ixgbe_poll_flash_update_done_X540(hw);
486 if (status == IXGBE_ERR_EEPROM) {
487 hw_dbg(hw, "Flash update time out\n");
e90dd264 488 return status;
fe15e8e1
DS		 489 }
490
491 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
492 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
493
494 status = ixgbe_poll_flash_update_done_X540(hw);
2ea5ea5f 495 if (status == 0)
fe15e8e1
DS		 496 hw_dbg(hw, "Flash update complete\n");
497 else
498 hw_dbg(hw, "Flash update time out\n");
499
500 if (hw->revision_id == 0) {
501 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
502
503 if (flup & IXGBE_EEC_SEC1VAL) {
504 flup |= IXGBE_EEC_FLUP;
505 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
506 }
507
508 status = ixgbe_poll_flash_update_done_X540(hw);
2ea5ea5f 509 if (status == 0)
fe15e8e1
DS		 510 hw_dbg(hw, "Flash update complete\n");
511 else
512 hw_dbg(hw, "Flash update time out\n");
fe15e8e1 513 }
e90dd264 514
fe15e8e1
DS		 515 return status;
516}
517
518/**
519 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
520 * @hw: pointer to hardware structure
521 *
522 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
523 * flash update is done.
524 **/
525static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
526{
527 u32 i;
528 u32 reg;
fe15e8e1
DS		 529
530 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
531 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
e90dd264
MR		 532 if (reg & IXGBE_EEC_FLUDONE)
533 return 0;
fe15e8e1
DS		 534 udelay(5);
535 }
e90dd264 536 return IXGBE_ERR_EEPROM;
fe15e8e1
DS		 537}
538
539/**
540 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
541 * @hw: pointer to hardware structure
542 * @mask: Mask to specify which semaphore to acquire
543 *
544 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
545 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
546 **/
547static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
548{
549 u32 swfw_sync;
550 u32 swmask = mask;
551 u32 fwmask = mask << 5;
552 u32 hwmask = 0;
553 u32 timeout = 200;
554 u32 i;
555
556 if (swmask == IXGBE_GSSR_EEP_SM)
557 hwmask = IXGBE_GSSR_FLASH_SM;
558
559 for (i = 0; i < timeout; i++) {
560 /*
561 * SW NVM semaphore bit is used for access to all
562 * SW_FW_SYNC bits (not just NVM)
563 */
564 if (ixgbe_get_swfw_sync_semaphore(hw))
565 return IXGBE_ERR_SWFW_SYNC;
566
567 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
568 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
569 swfw_sync |= swmask;
570 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
571 ixgbe_release_swfw_sync_semaphore(hw);
572 break;
573 } else {
574 /*
575 * Firmware currently using resource (fwmask),
576 * hardware currently using resource (hwmask),
577 * or other software thread currently using
578 * resource (swmask)
579 */
580 ixgbe_release_swfw_sync_semaphore(hw);
032b4325 581 usleep_range(5000, 10000);
fe15e8e1
DS		 582 }
583 }
584
585 /*
586 * If the resource is not released by the FW/HW the SW can assume that
587 * the FW/HW malfunctions. In that case the SW should sets the
588 * SW bit(s) of the requested resource(s) while ignoring the
589 * corresponding FW/HW bits in the SW_FW_SYNC register.
590 */
591 if (i >= timeout) {
592 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
593 if (swfw_sync & (fwmask | hwmask)) {
594 if (ixgbe_get_swfw_sync_semaphore(hw))
595 return IXGBE_ERR_SWFW_SYNC;
596
597 swfw_sync |= swmask;
598 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
599 ixgbe_release_swfw_sync_semaphore(hw);
600 }
601 }
602
032b4325 603 usleep_range(5000, 10000);
fe15e8e1
DS		 604 return 0;
605}
606
607/**
608 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
609 * @hw: pointer to hardware structure
610 * @mask: Mask to specify which semaphore to release
611 *
25985edc 612 * Releases the SWFW semaphore through the SW_FW_SYNC register
fe15e8e1
DS		 613 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
614 **/
615static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
616{
617 u32 swfw_sync;
618 u32 swmask = mask;
619
620 ixgbe_get_swfw_sync_semaphore(hw);
621
622 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
623 swfw_sync &= ~swmask;
624 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
625
626 ixgbe_release_swfw_sync_semaphore(hw);
032b4325 627 usleep_range(5000, 10000);
fe15e8e1
DS		 628}
629
630/**
acb1ce22 631 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
fe15e8e1
DS		 632 * @hw: pointer to hardware structure
633 *
634 * Sets the hardware semaphores so SW/FW can gain control of shared resources
acb1ce22 635 */
fe15e8e1
DS		 636static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
637{
fe15e8e1
DS		 638 u32 timeout = 2000;
639 u32 i;
640 u32 swsm;
641
642 /* Get SMBI software semaphore between device drivers first */
643 for (i = 0; i < timeout; i++) {
acb1ce22 644 /* If the SMBI bit is 0 when we read it, then the bit will be
fe15e8e1
DS		 645 * set and we have the semaphore
646 */
647 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
acb1ce22 648 if (!(swsm & IXGBE_SWSM_SMBI))
fe15e8e1 649 break;
d819fc52 650 usleep_range(50, 100);
fe15e8e1
DS		 651 }
652
acb1ce22
MR		 653 if (i == timeout) {
654 hw_dbg(hw,
655 "Software semaphore SMBI between device drivers not granted.\n");
656 return IXGBE_ERR_EEPROM;
657 }
658
fe15e8e1 659 /* Now get the semaphore between SW/FW through the REGSMP bit */
acb1ce22
MR		 660 for (i = 0; i < timeout; i++) {
661 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
662 if (!(swsm & IXGBE_SWFW_REGSMP))
663 return 0;
fe15e8e1 664
acb1ce22 665 usleep_range(50, 100);
fe15e8e1
DS		 666 }
667
acb1ce22 668 return IXGBE_ERR_EEPROM;
fe15e8e1
DS		 669}
670
671/**
672 * ixgbe_release_nvm_semaphore - Release hardware semaphore
673 * @hw: pointer to hardware structure
674 *
675 * This function clears hardware semaphore bits.
676 **/
677static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
678{
679 u32 swsm;
680
681 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
682
683 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
684 swsm &= ~IXGBE_SWSM_SMBI;
685 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
686
687 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
688 swsm &= ~IXGBE_SWFW_REGSMP;
689 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
690
691 IXGBE_WRITE_FLUSH(hw);
692}
693
98508c93
ET		 694/**
695 * ixgbe_blink_led_start_X540 - Blink LED based on index.
696 * @hw: pointer to hardware structure
697 * @index: led number to blink
698 *
699 * Devices that implement the version 2 interface:
700 * X540
701 **/
702static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
703{
704 u32 macc_reg;
705 u32 ledctl_reg;
8d233633
ET		 706 ixgbe_link_speed speed;
707 bool link_up;
98508c93
ET		 708
709 /*
8d233633
ET		 710 * Link should be up in order for the blink bit in the LED control
711 * register to work. Force link and speed in the MAC if link is down.
712 * This will be reversed when we stop the blinking.
98508c93 713 */
8d233633 714 hw->mac.ops.check_link(hw, &speed, &link_up, false);
23677ce3 715 if (!link_up) {
8d233633
ET		 716 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
717 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
718 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
719 }
98508c93
ET		 720 /* Set the LED to LINK_UP + BLINK. */
721 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
722 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
723 ledctl_reg |= IXGBE_LED_BLINK(index);
724 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
725 IXGBE_WRITE_FLUSH(hw);
726
727 return 0;
728}
729
730/**
731 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
732 * @hw: pointer to hardware structure
733 * @index: led number to stop blinking
734 *
735 * Devices that implement the version 2 interface:
736 * X540
737 **/
738static s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
739{
740 u32 macc_reg;
741 u32 ledctl_reg;
742
743 /* Restore the LED to its default value. */
744 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
745 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
746 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
747 ledctl_reg &= ~IXGBE_LED_BLINK(index);
748 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
749
750 /* Unforce link and speed in the MAC. */
751 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
752 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
753 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
754 IXGBE_WRITE_FLUSH(hw);
755
756 return 0;
757}
fe15e8e1
DS		 758static struct ixgbe_mac_operations mac_ops_X540 = {
759 .init_hw = &ixgbe_init_hw_generic,
760 .reset_hw = &ixgbe_reset_hw_X540,
7184b7cf 761 .start_hw = &ixgbe_start_hw_X540,
fe15e8e1
DS		 762 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
763 .get_media_type = &ixgbe_get_media_type_X540,
fe15e8e1
DS		 764 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
765 .get_mac_addr = &ixgbe_get_mac_addr_generic,
766 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
b776d104 767 .get_device_caps = &ixgbe_get_device_caps_generic,
fe15e8e1
DS		 768 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
769 .stop_adapter = &ixgbe_stop_adapter_generic,
770 .get_bus_info = &ixgbe_get_bus_info_generic,
771 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
772 .read_analog_reg8 = NULL,
773 .write_analog_reg8 = NULL,
774 .setup_link = &ixgbe_setup_mac_link_X540,
80605c65 775 .set_rxpba = &ixgbe_set_rxpba_generic,
fe15e8e1
DS		 776 .check_link = &ixgbe_check_mac_link_generic,
777 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
778 .led_on = &ixgbe_led_on_generic,
779 .led_off = &ixgbe_led_off_generic,
98508c93
ET		 780 .blink_led_start = &ixgbe_blink_led_start_X540,
781 .blink_led_stop = &ixgbe_blink_led_stop_X540,
fe15e8e1
DS		 782 .set_rar = &ixgbe_set_rar_generic,
783 .clear_rar = &ixgbe_clear_rar_generic,
784 .set_vmdq = &ixgbe_set_vmdq_generic,
7fa7c9dc 785 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
fe15e8e1
DS		 786 .clear_vmdq = &ixgbe_clear_vmdq_generic,
787 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
fe15e8e1
DS		 788 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
789 .enable_mc = &ixgbe_enable_mc_generic,
790 .disable_mc = &ixgbe_disable_mc_generic,
791 .clear_vfta = &ixgbe_clear_vfta_generic,
792 .set_vfta = &ixgbe_set_vfta_generic,
793 .fc_enable = &ixgbe_fc_enable_generic,
9612de92 794 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
fe15e8e1
DS		 795 .init_uta_tables = &ixgbe_init_uta_tables_generic,
796 .setup_sfp = NULL,
3377eba7
GR		 797 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
798 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
5e655105
DS		 799 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
800 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
d2f5e7f3
AS		 801 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
802 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
3ca8bc6d
DS		 803 .get_thermal_sensor_data = NULL,
804 .init_thermal_sensor_thresh = NULL,
429d6a3b
DS		 805 .prot_autoc_read = &prot_autoc_read_generic,
806 .prot_autoc_write = &prot_autoc_write_generic,
fe15e8e1
DS		 807};
808
809static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
810 .init_params = &ixgbe_init_eeprom_params_X540,
811 .read = &ixgbe_read_eerd_X540,
68c7005d 812 .read_buffer = &ixgbe_read_eerd_buffer_X540,
fe15e8e1 813 .write = &ixgbe_write_eewr_X540,
68c7005d 814 .write_buffer = &ixgbe_write_eewr_buffer_X540,
fe15e8e1 815 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
eb9c3e3e 816 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
fe15e8e1
DS		 817 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
818};
819
820static struct ixgbe_phy_operations phy_ops_X540 = {
821 .identify = &ixgbe_identify_phy_generic,
822 .identify_sfp = &ixgbe_identify_sfp_module_generic,
823 .init = NULL,
b60c5dd3 824 .reset = NULL,
fe15e8e1
DS		 825 .read_reg = &ixgbe_read_phy_reg_generic,
826 .write_reg = &ixgbe_write_phy_reg_generic,
827 .setup_link = &ixgbe_setup_phy_link_generic,
828 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
829 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
830 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
07ce870b 831 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
fe15e8e1
DS		 832 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
833 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
834 .check_overtemp = &ixgbe_tn_check_overtemp,
3e7307fc 835 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
fe15e8e1
DS		 836};
837
838struct ixgbe_info ixgbe_X540_info = {
839 .mac = ixgbe_mac_X540,
840 .get_invariants = &ixgbe_get_invariants_X540,
841 .mac_ops = &mac_ops_X540,
842 .eeprom_ops = &eeprom_ops_X540,
843 .phy_ops = &phy_ops_X540,
844 .mbx_ops = &mbx_ops_generic,
845};
Linux 6.x block layer and io_uring tree(s)