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fe15e8e1 DS |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
e4856696 | 4 | Copyright(c) 1999 - 2014 Intel Corporation. |
fe15e8e1 DS |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
fe15e8e1 DS |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/pci.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/sched.h> | |
32 | ||
33 | #include "ixgbe.h" | |
34 | #include "ixgbe_phy.h" | |
6a14ee0c | 35 | #include "ixgbe_x540.h" |
fe15e8e1 | 36 | |
b0007484 JK |
37 | #define IXGBE_X540_MAX_TX_QUEUES 128 |
38 | #define IXGBE_X540_MAX_RX_QUEUES 128 | |
39 | #define IXGBE_X540_RAR_ENTRIES 128 | |
40 | #define IXGBE_X540_MC_TBL_SIZE 128 | |
41 | #define IXGBE_X540_VFT_TBL_SIZE 128 | |
42 | #define IXGBE_X540_RX_PB_SIZE 384 | |
fe15e8e1 DS |
43 | |
44 | static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); | |
45 | static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); | |
fe15e8e1 DS |
46 | static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); |
47 | static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); | |
48 | ||
6a14ee0c | 49 | enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
50 | { |
51 | return ixgbe_media_type_copper; | |
52 | } | |
53 | ||
6a14ee0c | 54 | s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
55 | { |
56 | struct ixgbe_mac_info *mac = &hw->mac; | |
b5529ef5 DS |
57 | struct ixgbe_phy_info *phy = &hw->phy; |
58 | ||
59 | /* set_phy_power was set by default to NULL */ | |
3c2f2b77 | 60 | phy->ops.set_phy_power = ixgbe_set_copper_phy_power; |
fe15e8e1 | 61 | |
fe15e8e1 DS |
62 | mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; |
63 | mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; | |
64 | mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; | |
6997d4d1 | 65 | mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; |
fe15e8e1 DS |
66 | mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; |
67 | mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; | |
68 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); | |
69 | ||
70 | return 0; | |
71 | } | |
72 | ||
73 | /** | |
74 | * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires | |
75 | * @hw: pointer to hardware structure | |
76 | * @speed: new link speed | |
fe15e8e1 DS |
77 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
78 | **/ | |
6a14ee0c DS |
79 | s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed, |
80 | bool autoneg_wait_to_complete) | |
fe15e8e1 | 81 | { |
99b76642 | 82 | return hw->phy.ops.setup_link_speed(hw, speed, |
e7cf745b | 83 | autoneg_wait_to_complete); |
fe15e8e1 DS |
84 | } |
85 | ||
86 | /** | |
87 | * ixgbe_reset_hw_X540 - Perform hardware reset | |
88 | * @hw: pointer to hardware structure | |
89 | * | |
90 | * Resets the hardware by resetting the transmit and receive units, masks | |
91 | * and clears all interrupts, perform a PHY reset, and perform a link (MAC) | |
92 | * reset. | |
93 | **/ | |
6a14ee0c | 94 | s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) |
fe15e8e1 | 95 | { |
8132b54e AD |
96 | s32 status; |
97 | u32 ctrl, i; | |
fe15e8e1 DS |
98 | |
99 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
ff9d1a5a | 100 | status = hw->mac.ops.stop_adapter(hw); |
e90dd264 MR |
101 | if (status) |
102 | return status; | |
fe15e8e1 | 103 | |
ff9d1a5a ET |
104 | /* flush pending Tx transactions */ |
105 | ixgbe_clear_tx_pending(hw); | |
fe15e8e1 | 106 | |
a4297dc2 | 107 | mac_reset_top: |
8c838d73 | 108 | ctrl = IXGBE_CTRL_RST; |
8132b54e AD |
109 | ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); |
110 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
fe15e8e1 | 111 | IXGBE_WRITE_FLUSH(hw); |
efff2e02 | 112 | usleep_range(1000, 1200); |
fe15e8e1 DS |
113 | |
114 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
115 | for (i = 0; i < 10; i++) { | |
fe15e8e1 | 116 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
8132b54e | 117 | if (!(ctrl & IXGBE_CTRL_RST_MASK)) |
fe15e8e1 | 118 | break; |
efff2e02 | 119 | udelay(1); |
fe15e8e1 | 120 | } |
8132b54e AD |
121 | |
122 | if (ctrl & IXGBE_CTRL_RST_MASK) { | |
fe15e8e1 DS |
123 | status = IXGBE_ERR_RESET_FAILED; |
124 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
125 | } | |
8c838d73 | 126 | msleep(100); |
8132b54e | 127 | |
a4297dc2 ET |
128 | /* |
129 | * Double resets are required for recovery from certain error | |
130 | * conditions. Between resets, it is necessary to stall to allow time | |
8132b54e | 131 | * for any pending HW events to complete. |
a4297dc2 ET |
132 | */ |
133 | if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { | |
134 | hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; | |
a4297dc2 ET |
135 | goto mac_reset_top; |
136 | } | |
137 | ||
fe15e8e1 DS |
138 | /* Set the Rx packet buffer size. */ |
139 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); | |
140 | ||
141 | /* Store the permanent mac address */ | |
142 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); | |
143 | ||
fe15e8e1 DS |
144 | /* |
145 | * Store MAC address from RAR0, clear receive address registers, and | |
146 | * clear the multicast table. Also reset num_rar_entries to 128, | |
147 | * since we modify this value when programming the SAN MAC address. | |
148 | */ | |
93cb38dc | 149 | hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES; |
fe15e8e1 DS |
150 | hw->mac.ops.init_rx_addrs(hw); |
151 | ||
fe15e8e1 DS |
152 | /* Store the permanent SAN mac address */ |
153 | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); | |
154 | ||
155 | /* Add the SAN MAC address to the RAR only if it's a valid address */ | |
f8ebc683 | 156 | if (is_valid_ether_addr(hw->mac.san_addr)) { |
7fa7c9dc AD |
157 | /* Save the SAN MAC RAR index */ |
158 | hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; | |
159 | ||
6e982aea AD |
160 | hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, |
161 | hw->mac.san_addr, 0, IXGBE_RAH_AV); | |
162 | ||
163 | /* clear VMDq pool/queue selection for this RAR */ | |
164 | hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, | |
165 | IXGBE_CLEAR_VMDQ_ALL); | |
166 | ||
fe15e8e1 DS |
167 | /* Reserve the last RAR for the SAN MAC address */ |
168 | hw->mac.num_rar_entries--; | |
169 | } | |
170 | ||
171 | /* Store the alternative WWNN/WWPN prefix */ | |
172 | hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, | |
e7cf745b | 173 | &hw->mac.wwpn_prefix); |
fe15e8e1 DS |
174 | |
175 | return status; | |
176 | } | |
177 | ||
7184b7cf ET |
178 | /** |
179 | * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx | |
180 | * @hw: pointer to hardware structure | |
181 | * | |
182 | * Starts the hardware using the generic start_hw function | |
183 | * and the generation start_hw function. | |
184 | * Then performs revision-specific operations, if any. | |
185 | **/ | |
6a14ee0c | 186 | s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) |
7184b7cf | 187 | { |
e90dd264 | 188 | s32 ret_val; |
7184b7cf ET |
189 | |
190 | ret_val = ixgbe_start_hw_generic(hw); | |
e90dd264 MR |
191 | if (ret_val) |
192 | return ret_val; | |
7184b7cf | 193 | |
e90dd264 | 194 | return ixgbe_start_hw_gen2(hw); |
7184b7cf ET |
195 | } |
196 | ||
fe15e8e1 | 197 | /** |
77ed18f3 ET |
198 | * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params |
199 | * @hw: pointer to hardware structure | |
200 | * | |
201 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the | |
202 | * ixgbe_hw struct in order to set up EEPROM access. | |
fe15e8e1 | 203 | **/ |
6a14ee0c | 204 | s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
205 | { |
206 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | |
207 | u32 eec; | |
208 | u16 eeprom_size; | |
209 | ||
210 | if (eeprom->type == ixgbe_eeprom_uninitialized) { | |
211 | eeprom->semaphore_delay = 10; | |
212 | eeprom->type = ixgbe_flash; | |
213 | ||
9a900eca | 214 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
fe15e8e1 | 215 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> |
e7cf745b | 216 | IXGBE_EEC_SIZE_SHIFT); |
fe15e8e1 | 217 | eeprom->word_size = 1 << (eeprom_size + |
e7cf745b | 218 | IXGBE_EEPROM_WORD_SIZE_SHIFT); |
fe15e8e1 DS |
219 | |
220 | hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", | |
77ed18f3 | 221 | eeprom->type, eeprom->word_size); |
fe15e8e1 DS |
222 | } |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | /** | |
68c7005d ET |
228 | * ixgbe_read_eerd_X540- Read EEPROM word using EERD |
229 | * @hw: pointer to hardware structure | |
230 | * @offset: offset of word in the EEPROM to read | |
231 | * @data: word read from the EEPROM | |
232 | * | |
233 | * Reads a 16 bit word from the EEPROM using the EERD register. | |
fe15e8e1 | 234 | **/ |
b93a2226 | 235 | static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) |
fe15e8e1 | 236 | { |
e4856696 MR |
237 | s32 status; |
238 | ||
239 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) | |
240 | return IXGBE_ERR_SWFW_SYNC; | |
fe15e8e1 | 241 | |
e4856696 | 242 | status = ixgbe_read_eerd_generic(hw, offset, data); |
fe15e8e1 | 243 | |
6d980c3e | 244 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
fe15e8e1 DS |
245 | return status; |
246 | } | |
247 | ||
68c7005d ET |
248 | /** |
249 | * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD | |
250 | * @hw: pointer to hardware structure | |
251 | * @offset: offset of word in the EEPROM to read | |
252 | * @words: number of words | |
253 | * @data: word(s) read from the EEPROM | |
254 | * | |
255 | * Reads a 16 bit word(s) from the EEPROM using the EERD register. | |
256 | **/ | |
257 | static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, | |
258 | u16 offset, u16 words, u16 *data) | |
259 | { | |
e4856696 MR |
260 | s32 status; |
261 | ||
262 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) | |
263 | return IXGBE_ERR_SWFW_SYNC; | |
68c7005d | 264 | |
e4856696 | 265 | status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data); |
68c7005d ET |
266 | |
267 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
268 | return status; | |
269 | } | |
270 | ||
fe15e8e1 | 271 | /** |
eb9c3e3e ET |
272 | * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR |
273 | * @hw: pointer to hardware structure | |
274 | * @offset: offset of word in the EEPROM to write | |
275 | * @data: word write to the EEPROM | |
fe15e8e1 | 276 | * |
eb9c3e3e | 277 | * Write a 16 bit word to the EEPROM using the EEWR register. |
fe15e8e1 | 278 | **/ |
b93a2226 | 279 | static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) |
fe15e8e1 | 280 | { |
e4856696 MR |
281 | s32 status; |
282 | ||
283 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) | |
284 | return IXGBE_ERR_SWFW_SYNC; | |
fe15e8e1 | 285 | |
e4856696 | 286 | status = ixgbe_write_eewr_generic(hw, offset, data); |
fe15e8e1 | 287 | |
eb9c3e3e | 288 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
fe15e8e1 DS |
289 | return status; |
290 | } | |
291 | ||
68c7005d ET |
292 | /** |
293 | * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR | |
294 | * @hw: pointer to hardware structure | |
295 | * @offset: offset of word in the EEPROM to write | |
296 | * @words: number of words | |
297 | * @data: word(s) write to the EEPROM | |
298 | * | |
299 | * Write a 16 bit word(s) to the EEPROM using the EEWR register. | |
300 | **/ | |
301 | static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, | |
302 | u16 offset, u16 words, u16 *data) | |
303 | { | |
e4856696 | 304 | s32 status; |
68c7005d | 305 | |
e4856696 MR |
306 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) |
307 | return IXGBE_ERR_SWFW_SYNC; | |
308 | ||
309 | status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data); | |
68c7005d ET |
310 | |
311 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
312 | return status; | |
313 | } | |
314 | ||
fe15e8e1 | 315 | /** |
eb9c3e3e ET |
316 | * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum |
317 | * | |
318 | * This function does not use synchronization for EERD and EEWR. It can | |
319 | * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. | |
320 | * | |
321 | * @hw: pointer to hardware structure | |
fe15e8e1 | 322 | **/ |
735c35af | 323 | static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
324 | { |
325 | u16 i; | |
326 | u16 j; | |
327 | u16 checksum = 0; | |
328 | u16 length = 0; | |
329 | u16 pointer = 0; | |
330 | u16 word = 0; | |
735c35af DS |
331 | u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM; |
332 | u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; | |
fe15e8e1 | 333 | |
eb9c3e3e ET |
334 | /* |
335 | * Do not use hw->eeprom.ops.read because we do not want to take | |
336 | * the synchronization semaphores here. Instead use | |
337 | * ixgbe_read_eerd_generic | |
338 | */ | |
339 | ||
fe15e8e1 | 340 | /* Include 0x0-0x3F in the checksum */ |
735c35af DS |
341 | for (i = 0; i < checksum_last_word; i++) { |
342 | if (ixgbe_read_eerd_generic(hw, i, &word)) { | |
fe15e8e1 | 343 | hw_dbg(hw, "EEPROM read failed\n"); |
735c35af | 344 | return IXGBE_ERR_EEPROM; |
fe15e8e1 DS |
345 | } |
346 | checksum += word; | |
347 | } | |
348 | ||
349 | /* | |
350 | * Include all data from pointers 0x3, 0x6-0xE. This excludes the | |
351 | * FW, PHY module, and PCIe Expansion/Option ROM pointers. | |
352 | */ | |
735c35af | 353 | for (i = ptr_start; i < IXGBE_FW_PTR; i++) { |
fe15e8e1 DS |
354 | if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) |
355 | continue; | |
356 | ||
735c35af | 357 | if (ixgbe_read_eerd_generic(hw, i, &pointer)) { |
fe15e8e1 DS |
358 | hw_dbg(hw, "EEPROM read failed\n"); |
359 | break; | |
360 | } | |
361 | ||
362 | /* Skip pointer section if the pointer is invalid. */ | |
363 | if (pointer == 0xFFFF || pointer == 0 || | |
364 | pointer >= hw->eeprom.word_size) | |
365 | continue; | |
366 | ||
735c35af | 367 | if (ixgbe_read_eerd_generic(hw, pointer, &length)) { |
fe15e8e1 | 368 | hw_dbg(hw, "EEPROM read failed\n"); |
735c35af | 369 | return IXGBE_ERR_EEPROM; |
fe15e8e1 DS |
370 | break; |
371 | } | |
372 | ||
373 | /* Skip pointer section if length is invalid. */ | |
374 | if (length == 0xFFFF || length == 0 || | |
375 | (pointer + length) >= hw->eeprom.word_size) | |
376 | continue; | |
377 | ||
735c35af DS |
378 | for (j = pointer + 1; j <= pointer + length; j++) { |
379 | if (ixgbe_read_eerd_generic(hw, j, &word)) { | |
fe15e8e1 | 380 | hw_dbg(hw, "EEPROM read failed\n"); |
735c35af | 381 | return IXGBE_ERR_EEPROM; |
fe15e8e1 DS |
382 | } |
383 | checksum += word; | |
384 | } | |
385 | } | |
386 | ||
387 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; | |
388 | ||
735c35af | 389 | return (s32)checksum; |
fe15e8e1 DS |
390 | } |
391 | ||
eb9c3e3e ET |
392 | /** |
393 | * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum | |
394 | * @hw: pointer to hardware structure | |
395 | * @checksum_val: calculated checksum | |
396 | * | |
397 | * Performs checksum calculation and validates the EEPROM checksum. If the | |
398 | * caller does not need checksum_val, the value can be NULL. | |
399 | **/ | |
400 | static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, | |
401 | u16 *checksum_val) | |
402 | { | |
403 | s32 status; | |
404 | u16 checksum; | |
405 | u16 read_checksum = 0; | |
406 | ||
e4856696 | 407 | /* Read the first word from the EEPROM. If this times out or fails, do |
eb9c3e3e ET |
408 | * not continue or we could be in for a very long wait while every |
409 | * EEPROM read fails | |
410 | */ | |
411 | status = hw->eeprom.ops.read(hw, 0, &checksum); | |
e4856696 | 412 | if (status) { |
eb9c3e3e | 413 | hw_dbg(hw, "EEPROM read failed\n"); |
e4856696 | 414 | return status; |
eb9c3e3e ET |
415 | } |
416 | ||
e4856696 MR |
417 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) |
418 | return IXGBE_ERR_SWFW_SYNC; | |
419 | ||
735c35af DS |
420 | status = hw->eeprom.ops.calc_checksum(hw); |
421 | if (status < 0) | |
422 | goto out; | |
423 | ||
424 | checksum = (u16)(status & 0xffff); | |
e4856696 MR |
425 | |
426 | /* Do not use hw->eeprom.ops.read because we do not want to take | |
427 | * the synchronization semaphores twice here. | |
428 | */ | |
429 | status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, | |
430 | &read_checksum); | |
735c35af DS |
431 | if (status) |
432 | goto out; | |
eb9c3e3e | 433 | |
735c35af DS |
434 | /* Verify read checksum from EEPROM is the same as |
435 | * calculated checksum | |
436 | */ | |
437 | if (read_checksum != checksum) { | |
438 | hw_dbg(hw, "Invalid EEPROM checksum"); | |
439 | status = IXGBE_ERR_EEPROM_CHECKSUM; | |
440 | } | |
e4856696 MR |
441 | |
442 | /* If the user cares, return the calculated checksum */ | |
443 | if (checksum_val) | |
444 | *checksum_val = checksum; | |
445 | ||
735c35af DS |
446 | out: |
447 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
e4856696 | 448 | |
eb9c3e3e ET |
449 | return status; |
450 | } | |
451 | ||
fe15e8e1 DS |
452 | /** |
453 | * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash | |
454 | * @hw: pointer to hardware structure | |
455 | * | |
456 | * After writing EEPROM to shadow RAM using EEWR register, software calculates | |
457 | * checksum and updates the EEPROM and instructs the hardware to update | |
458 | * the flash. | |
459 | **/ | |
b93a2226 | 460 | static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
461 | { |
462 | s32 status; | |
eb9c3e3e | 463 | u16 checksum; |
fe15e8e1 | 464 | |
e4856696 | 465 | /* Read the first word from the EEPROM. If this times out or fails, do |
eb9c3e3e ET |
466 | * not continue or we could be in for a very long wait while every |
467 | * EEPROM read fails | |
468 | */ | |
469 | status = hw->eeprom.ops.read(hw, 0, &checksum); | |
e4856696 | 470 | if (status) { |
eb9c3e3e | 471 | hw_dbg(hw, "EEPROM read failed\n"); |
e4856696 MR |
472 | return status; |
473 | } | |
eb9c3e3e | 474 | |
e4856696 MR |
475 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) |
476 | return IXGBE_ERR_SWFW_SYNC; | |
fe15e8e1 | 477 | |
735c35af DS |
478 | status = hw->eeprom.ops.calc_checksum(hw); |
479 | if (status < 0) | |
480 | goto out; | |
481 | ||
482 | checksum = (u16)(status & 0xffff); | |
eb9c3e3e | 483 | |
e4856696 MR |
484 | /* Do not use hw->eeprom.ops.write because we do not want to |
485 | * take the synchronization semaphores twice here. | |
486 | */ | |
487 | status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); | |
735c35af DS |
488 | if (status) |
489 | goto out; | |
490 | ||
491 | status = ixgbe_update_flash_X540(hw); | |
eb9c3e3e | 492 | |
735c35af | 493 | out: |
eb9c3e3e | 494 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
fe15e8e1 DS |
495 | return status; |
496 | } | |
497 | ||
498 | /** | |
499 | * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device | |
500 | * @hw: pointer to hardware structure | |
501 | * | |
502 | * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy | |
503 | * EEPROM from shadow RAM to the flash device. | |
504 | **/ | |
505 | static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) | |
506 | { | |
507 | u32 flup; | |
e90dd264 | 508 | s32 status; |
fe15e8e1 DS |
509 | |
510 | status = ixgbe_poll_flash_update_done_X540(hw); | |
511 | if (status == IXGBE_ERR_EEPROM) { | |
512 | hw_dbg(hw, "Flash update time out\n"); | |
e90dd264 | 513 | return status; |
fe15e8e1 DS |
514 | } |
515 | ||
9a900eca DS |
516 | flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP; |
517 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup); | |
fe15e8e1 DS |
518 | |
519 | status = ixgbe_poll_flash_update_done_X540(hw); | |
2ea5ea5f | 520 | if (status == 0) |
fe15e8e1 DS |
521 | hw_dbg(hw, "Flash update complete\n"); |
522 | else | |
523 | hw_dbg(hw, "Flash update time out\n"); | |
524 | ||
525 | if (hw->revision_id == 0) { | |
9a900eca | 526 | flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
fe15e8e1 DS |
527 | |
528 | if (flup & IXGBE_EEC_SEC1VAL) { | |
529 | flup |= IXGBE_EEC_FLUP; | |
9a900eca | 530 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup); |
fe15e8e1 DS |
531 | } |
532 | ||
533 | status = ixgbe_poll_flash_update_done_X540(hw); | |
2ea5ea5f | 534 | if (status == 0) |
fe15e8e1 DS |
535 | hw_dbg(hw, "Flash update complete\n"); |
536 | else | |
537 | hw_dbg(hw, "Flash update time out\n"); | |
fe15e8e1 | 538 | } |
e90dd264 | 539 | |
fe15e8e1 DS |
540 | return status; |
541 | } | |
542 | ||
543 | /** | |
544 | * ixgbe_poll_flash_update_done_X540 - Poll flash update status | |
545 | * @hw: pointer to hardware structure | |
546 | * | |
547 | * Polls the FLUDONE (bit 26) of the EEC Register to determine when the | |
548 | * flash update is done. | |
549 | **/ | |
550 | static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) | |
551 | { | |
552 | u32 i; | |
553 | u32 reg; | |
fe15e8e1 DS |
554 | |
555 | for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { | |
9a900eca | 556 | reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
e90dd264 MR |
557 | if (reg & IXGBE_EEC_FLUDONE) |
558 | return 0; | |
fe15e8e1 DS |
559 | udelay(5); |
560 | } | |
e90dd264 | 561 | return IXGBE_ERR_EEPROM; |
fe15e8e1 DS |
562 | } |
563 | ||
564 | /** | |
565 | * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore | |
566 | * @hw: pointer to hardware structure | |
567 | * @mask: Mask to specify which semaphore to acquire | |
568 | * | |
569 | * Acquires the SWFW semaphore thought the SW_FW_SYNC register for | |
570 | * the specified function (CSR, PHY0, PHY1, NVM, Flash) | |
571 | **/ | |
6a14ee0c | 572 | s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) |
fe15e8e1 | 573 | { |
449e21a9 MR |
574 | u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; |
575 | u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; | |
576 | u32 fwmask = swmask << 5; | |
fe15e8e1 | 577 | u32 timeout = 200; |
449e21a9 MR |
578 | u32 hwmask = 0; |
579 | u32 swfw_sync; | |
fe15e8e1 DS |
580 | u32 i; |
581 | ||
449e21a9 | 582 | if (swmask & IXGBE_GSSR_EEP_SM) |
fe15e8e1 DS |
583 | hwmask = IXGBE_GSSR_FLASH_SM; |
584 | ||
449e21a9 MR |
585 | /* SW only mask does not have FW bit pair */ |
586 | if (mask & IXGBE_GSSR_SW_MNG_SM) | |
587 | swmask |= IXGBE_GSSR_SW_MNG_SM; | |
588 | ||
589 | swmask |= swi2c_mask; | |
590 | fwmask |= swi2c_mask << 2; | |
fe15e8e1 | 591 | for (i = 0; i < timeout; i++) { |
449e21a9 | 592 | /* SW NVM semaphore bit is used for access to all |
fe15e8e1 DS |
593 | * SW_FW_SYNC bits (not just NVM) |
594 | */ | |
595 | if (ixgbe_get_swfw_sync_semaphore(hw)) | |
596 | return IXGBE_ERR_SWFW_SYNC; | |
597 | ||
9a900eca | 598 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); |
fe15e8e1 DS |
599 | if (!(swfw_sync & (fwmask | swmask | hwmask))) { |
600 | swfw_sync |= swmask; | |
9a900eca | 601 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); |
fe15e8e1 | 602 | ixgbe_release_swfw_sync_semaphore(hw); |
449e21a9 MR |
603 | usleep_range(5000, 6000); |
604 | return 0; | |
fe15e8e1 | 605 | } |
449e21a9 MR |
606 | /* Firmware currently using resource (fwmask), hardware |
607 | * currently using resource (hwmask), or other software | |
608 | * thread currently using resource (swmask) | |
609 | */ | |
610 | ixgbe_release_swfw_sync_semaphore(hw); | |
611 | usleep_range(5000, 10000); | |
fe15e8e1 DS |
612 | } |
613 | ||
449e21a9 MR |
614 | /* Failed to get SW only semaphore */ |
615 | if (swmask == IXGBE_GSSR_SW_MNG_SM) { | |
616 | hw_dbg(hw, "Failed to get SW only semaphore\n"); | |
617 | return IXGBE_ERR_SWFW_SYNC; | |
618 | } | |
fe15e8e1 | 619 | |
449e21a9 MR |
620 | /* If the resource is not released by the FW/HW the SW can assume that |
621 | * the FW/HW malfunctions. In that case the SW should set the SW bit(s) | |
622 | * of the requested resource(s) while ignoring the corresponding FW/HW | |
623 | * bits in the SW_FW_SYNC register. | |
624 | */ | |
625 | if (ixgbe_get_swfw_sync_semaphore(hw)) | |
626 | return IXGBE_ERR_SWFW_SYNC; | |
627 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); | |
628 | if (swfw_sync & (fwmask | hwmask)) { | |
629 | swfw_sync |= swmask; | |
630 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); | |
631 | ixgbe_release_swfw_sync_semaphore(hw); | |
632 | usleep_range(5000, 6000); | |
633 | return 0; | |
634 | } | |
635 | /* If the resource is not released by other SW the SW can assume that | |
636 | * the other SW malfunctions. In that case the SW should clear all SW | |
637 | * flags that it does not own and then repeat the whole process once | |
638 | * again. | |
639 | */ | |
640 | if (swfw_sync & swmask) { | |
641 | u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | | |
642 | IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM; | |
643 | ||
644 | if (swi2c_mask) | |
645 | rmask |= IXGBE_GSSR_I2C_MASK; | |
646 | ixgbe_release_swfw_sync_X540(hw, rmask); | |
647 | ixgbe_release_swfw_sync_semaphore(hw); | |
648 | return IXGBE_ERR_SWFW_SYNC; | |
fe15e8e1 | 649 | } |
449e21a9 | 650 | ixgbe_release_swfw_sync_semaphore(hw); |
fe15e8e1 | 651 | |
449e21a9 | 652 | return IXGBE_ERR_SWFW_SYNC; |
fe15e8e1 DS |
653 | } |
654 | ||
655 | /** | |
656 | * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore | |
657 | * @hw: pointer to hardware structure | |
658 | * @mask: Mask to specify which semaphore to release | |
659 | * | |
25985edc | 660 | * Releases the SWFW semaphore through the SW_FW_SYNC register |
fe15e8e1 DS |
661 | * for the specified function (CSR, PHY0, PHY1, EVM, Flash) |
662 | **/ | |
6a14ee0c | 663 | void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) |
fe15e8e1 | 664 | { |
449e21a9 | 665 | u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); |
fe15e8e1 | 666 | u32 swfw_sync; |
fe15e8e1 | 667 | |
449e21a9 MR |
668 | if (mask & IXGBE_GSSR_I2C_MASK) |
669 | swmask |= mask & IXGBE_GSSR_I2C_MASK; | |
fe15e8e1 DS |
670 | ixgbe_get_swfw_sync_semaphore(hw); |
671 | ||
9a900eca | 672 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); |
fe15e8e1 | 673 | swfw_sync &= ~swmask; |
9a900eca | 674 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); |
fe15e8e1 DS |
675 | |
676 | ixgbe_release_swfw_sync_semaphore(hw); | |
449e21a9 | 677 | usleep_range(5000, 6000); |
fe15e8e1 DS |
678 | } |
679 | ||
680 | /** | |
acb1ce22 | 681 | * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore |
fe15e8e1 DS |
682 | * @hw: pointer to hardware structure |
683 | * | |
684 | * Sets the hardware semaphores so SW/FW can gain control of shared resources | |
acb1ce22 | 685 | */ |
fe15e8e1 DS |
686 | static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) |
687 | { | |
fe15e8e1 DS |
688 | u32 timeout = 2000; |
689 | u32 i; | |
690 | u32 swsm; | |
691 | ||
692 | /* Get SMBI software semaphore between device drivers first */ | |
693 | for (i = 0; i < timeout; i++) { | |
acb1ce22 | 694 | /* If the SMBI bit is 0 when we read it, then the bit will be |
fe15e8e1 DS |
695 | * set and we have the semaphore |
696 | */ | |
9a900eca | 697 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); |
acb1ce22 | 698 | if (!(swsm & IXGBE_SWSM_SMBI)) |
fe15e8e1 | 699 | break; |
d819fc52 | 700 | usleep_range(50, 100); |
fe15e8e1 DS |
701 | } |
702 | ||
acb1ce22 MR |
703 | if (i == timeout) { |
704 | hw_dbg(hw, | |
705 | "Software semaphore SMBI between device drivers not granted.\n"); | |
706 | return IXGBE_ERR_EEPROM; | |
707 | } | |
708 | ||
fe15e8e1 | 709 | /* Now get the semaphore between SW/FW through the REGSMP bit */ |
acb1ce22 | 710 | for (i = 0; i < timeout; i++) { |
9a900eca | 711 | swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); |
acb1ce22 MR |
712 | if (!(swsm & IXGBE_SWFW_REGSMP)) |
713 | return 0; | |
fe15e8e1 | 714 | |
acb1ce22 | 715 | usleep_range(50, 100); |
fe15e8e1 DS |
716 | } |
717 | ||
5967fe22 MR |
718 | /* Release semaphores and return error if SW NVM semaphore |
719 | * was not granted because we do not have access to the EEPROM | |
720 | */ | |
721 | hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n"); | |
722 | ixgbe_release_swfw_sync_semaphore(hw); | |
acb1ce22 | 723 | return IXGBE_ERR_EEPROM; |
fe15e8e1 DS |
724 | } |
725 | ||
726 | /** | |
727 | * ixgbe_release_nvm_semaphore - Release hardware semaphore | |
728 | * @hw: pointer to hardware structure | |
729 | * | |
730 | * This function clears hardware semaphore bits. | |
731 | **/ | |
732 | static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) | |
733 | { | |
734 | u32 swsm; | |
735 | ||
736 | /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ | |
737 | ||
9a900eca | 738 | swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); |
fe15e8e1 | 739 | swsm &= ~IXGBE_SWFW_REGSMP; |
9a900eca | 740 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm); |
fe15e8e1 | 741 | |
9a900eca | 742 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); |
cb2effe5 | 743 | swsm &= ~IXGBE_SWSM_SMBI; |
9a900eca | 744 | IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); |
cb2effe5 | 745 | |
fe15e8e1 DS |
746 | IXGBE_WRITE_FLUSH(hw); |
747 | } | |
748 | ||
98508c93 ET |
749 | /** |
750 | * ixgbe_blink_led_start_X540 - Blink LED based on index. | |
751 | * @hw: pointer to hardware structure | |
752 | * @index: led number to blink | |
753 | * | |
754 | * Devices that implement the version 2 interface: | |
755 | * X540 | |
756 | **/ | |
6a14ee0c | 757 | s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) |
98508c93 ET |
758 | { |
759 | u32 macc_reg; | |
760 | u32 ledctl_reg; | |
8d233633 ET |
761 | ixgbe_link_speed speed; |
762 | bool link_up; | |
98508c93 ET |
763 | |
764 | /* | |
8d233633 ET |
765 | * Link should be up in order for the blink bit in the LED control |
766 | * register to work. Force link and speed in the MAC if link is down. | |
767 | * This will be reversed when we stop the blinking. | |
98508c93 | 768 | */ |
8d233633 | 769 | hw->mac.ops.check_link(hw, &speed, &link_up, false); |
23677ce3 | 770 | if (!link_up) { |
8d233633 ET |
771 | macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); |
772 | macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; | |
773 | IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); | |
774 | } | |
98508c93 ET |
775 | /* Set the LED to LINK_UP + BLINK. */ |
776 | ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
777 | ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); | |
778 | ledctl_reg |= IXGBE_LED_BLINK(index); | |
779 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); | |
780 | IXGBE_WRITE_FLUSH(hw); | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
785 | /** | |
786 | * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. | |
787 | * @hw: pointer to hardware structure | |
788 | * @index: led number to stop blinking | |
789 | * | |
790 | * Devices that implement the version 2 interface: | |
791 | * X540 | |
792 | **/ | |
6a14ee0c | 793 | s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) |
98508c93 ET |
794 | { |
795 | u32 macc_reg; | |
796 | u32 ledctl_reg; | |
797 | ||
798 | /* Restore the LED to its default value. */ | |
799 | ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
800 | ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); | |
801 | ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); | |
802 | ledctl_reg &= ~IXGBE_LED_BLINK(index); | |
803 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); | |
804 | ||
805 | /* Unforce link and speed in the MAC. */ | |
806 | macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); | |
807 | macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); | |
808 | IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); | |
809 | IXGBE_WRITE_FLUSH(hw); | |
810 | ||
811 | return 0; | |
812 | } | |
fe15e8e1 DS |
813 | static struct ixgbe_mac_operations mac_ops_X540 = { |
814 | .init_hw = &ixgbe_init_hw_generic, | |
815 | .reset_hw = &ixgbe_reset_hw_X540, | |
7184b7cf | 816 | .start_hw = &ixgbe_start_hw_X540, |
fe15e8e1 DS |
817 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
818 | .get_media_type = &ixgbe_get_media_type_X540, | |
fe15e8e1 DS |
819 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, |
820 | .get_mac_addr = &ixgbe_get_mac_addr_generic, | |
821 | .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, | |
b776d104 | 822 | .get_device_caps = &ixgbe_get_device_caps_generic, |
fe15e8e1 DS |
823 | .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, |
824 | .stop_adapter = &ixgbe_stop_adapter_generic, | |
825 | .get_bus_info = &ixgbe_get_bus_info_generic, | |
826 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, | |
827 | .read_analog_reg8 = NULL, | |
828 | .write_analog_reg8 = NULL, | |
829 | .setup_link = &ixgbe_setup_mac_link_X540, | |
80605c65 | 830 | .set_rxpba = &ixgbe_set_rxpba_generic, |
fe15e8e1 DS |
831 | .check_link = &ixgbe_check_mac_link_generic, |
832 | .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, | |
833 | .led_on = &ixgbe_led_on_generic, | |
834 | .led_off = &ixgbe_led_off_generic, | |
98508c93 ET |
835 | .blink_led_start = &ixgbe_blink_led_start_X540, |
836 | .blink_led_stop = &ixgbe_blink_led_stop_X540, | |
fe15e8e1 DS |
837 | .set_rar = &ixgbe_set_rar_generic, |
838 | .clear_rar = &ixgbe_clear_rar_generic, | |
839 | .set_vmdq = &ixgbe_set_vmdq_generic, | |
7fa7c9dc | 840 | .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, |
fe15e8e1 DS |
841 | .clear_vmdq = &ixgbe_clear_vmdq_generic, |
842 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, | |
fe15e8e1 DS |
843 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, |
844 | .enable_mc = &ixgbe_enable_mc_generic, | |
845 | .disable_mc = &ixgbe_disable_mc_generic, | |
846 | .clear_vfta = &ixgbe_clear_vfta_generic, | |
847 | .set_vfta = &ixgbe_set_vfta_generic, | |
848 | .fc_enable = &ixgbe_fc_enable_generic, | |
9612de92 | 849 | .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, |
fe15e8e1 DS |
850 | .init_uta_tables = &ixgbe_init_uta_tables_generic, |
851 | .setup_sfp = NULL, | |
3377eba7 GR |
852 | .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, |
853 | .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, | |
5e655105 DS |
854 | .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, |
855 | .release_swfw_sync = &ixgbe_release_swfw_sync_X540, | |
d2f5e7f3 AS |
856 | .disable_rx_buff = &ixgbe_disable_rx_buff_generic, |
857 | .enable_rx_buff = &ixgbe_enable_rx_buff_generic, | |
3ca8bc6d DS |
858 | .get_thermal_sensor_data = NULL, |
859 | .init_thermal_sensor_thresh = NULL, | |
429d6a3b DS |
860 | .prot_autoc_read = &prot_autoc_read_generic, |
861 | .prot_autoc_write = &prot_autoc_write_generic, | |
1f9ac57c DS |
862 | .enable_rx = &ixgbe_enable_rx_generic, |
863 | .disable_rx = &ixgbe_disable_rx_generic, | |
fe15e8e1 DS |
864 | }; |
865 | ||
866 | static struct ixgbe_eeprom_operations eeprom_ops_X540 = { | |
867 | .init_params = &ixgbe_init_eeprom_params_X540, | |
868 | .read = &ixgbe_read_eerd_X540, | |
68c7005d | 869 | .read_buffer = &ixgbe_read_eerd_buffer_X540, |
fe15e8e1 | 870 | .write = &ixgbe_write_eewr_X540, |
68c7005d | 871 | .write_buffer = &ixgbe_write_eewr_buffer_X540, |
fe15e8e1 | 872 | .calc_checksum = &ixgbe_calc_eeprom_checksum_X540, |
eb9c3e3e | 873 | .validate_checksum = &ixgbe_validate_eeprom_checksum_X540, |
fe15e8e1 DS |
874 | .update_checksum = &ixgbe_update_eeprom_checksum_X540, |
875 | }; | |
876 | ||
877 | static struct ixgbe_phy_operations phy_ops_X540 = { | |
878 | .identify = &ixgbe_identify_phy_generic, | |
879 | .identify_sfp = &ixgbe_identify_sfp_module_generic, | |
880 | .init = NULL, | |
b60c5dd3 | 881 | .reset = NULL, |
fe15e8e1 DS |
882 | .read_reg = &ixgbe_read_phy_reg_generic, |
883 | .write_reg = &ixgbe_write_phy_reg_generic, | |
884 | .setup_link = &ixgbe_setup_phy_link_generic, | |
885 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
886 | .read_i2c_byte = &ixgbe_read_i2c_byte_generic, | |
887 | .write_i2c_byte = &ixgbe_write_i2c_byte_generic, | |
07ce870b | 888 | .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, |
fe15e8e1 DS |
889 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, |
890 | .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, | |
891 | .check_overtemp = &ixgbe_tn_check_overtemp, | |
961fac88 | 892 | .set_phy_power = &ixgbe_set_copper_phy_power, |
3e7307fc | 893 | .get_firmware_version = &ixgbe_get_phy_firmware_version_generic, |
fe15e8e1 DS |
894 | }; |
895 | ||
9a900eca DS |
896 | static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { |
897 | IXGBE_MVALS_INIT(X540) | |
898 | }; | |
899 | ||
fe15e8e1 DS |
900 | struct ixgbe_info ixgbe_X540_info = { |
901 | .mac = ixgbe_mac_X540, | |
902 | .get_invariants = &ixgbe_get_invariants_X540, | |
903 | .mac_ops = &mac_ops_X540, | |
904 | .eeprom_ops = &eeprom_ops_X540, | |
905 | .phy_ops = &phy_ops_X540, | |
906 | .mbx_ops = &mbx_ops_generic, | |
9a900eca | 907 | .mvals = ixgbe_mvals_X540, |
fe15e8e1 | 908 | }; |