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3a6a4eda JK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
a9763f3c | 4 | Copyright(c) 1999 - 2015 Intel Corporation. |
3a6a4eda JK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
3a6a4eda JK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | #include "ixgbe.h" | |
1d1a79b5 | 29 | #include <linux/ptp_classify.h> |
a9763f3c | 30 | #include <linux/clocksource.h> |
3a6a4eda JK |
31 | |
32 | /* | |
33 | * The 82599 and the X540 do not have true 64bit nanosecond scale | |
34 | * counter registers. Instead, SYSTIME is defined by a fixed point | |
35 | * system which allows the user to define the scale counter increment | |
36 | * value at every level change of the oscillator driving the SYSTIME | |
37 | * value. For both devices the TIMINCA:IV field defines this | |
38 | * increment. On the X540 device, 31 bits are provided. However on the | |
39 | * 82599 only provides 24 bits. The time unit is determined by the | |
40 | * clock frequency of the oscillator in combination with the TIMINCA | |
41 | * register. When these devices link at 10Gb the oscillator has a | |
42 | * period of 6.4ns. In order to convert the scale counter into | |
43 | * nanoseconds the cyclecounter and timecounter structures are | |
44 | * used. The SYSTIME registers need to be converted to ns values by use | |
45 | * of only a right shift (division by power of 2). The following math | |
46 | * determines the largest incvalue that will fit into the available | |
47 | * bits in the TIMINCA register. | |
48 | * | |
49 | * PeriodWidth: Number of bits to store the clock period | |
50 | * MaxWidth: The maximum width value of the TIMINCA register | |
51 | * Period: The clock period for the oscillator | |
52 | * round(): discard the fractional portion of the calculation | |
53 | * | |
54 | * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ] | |
55 | * | |
56 | * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns | |
57 | * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns | |
58 | * | |
59 | * The period also changes based on the link speed: | |
60 | * At 10Gb link or no link, the period remains the same. | |
61 | * At 1Gb link, the period is multiplied by 10. (64ns) | |
62 | * At 100Mb link, the period is multiplied by 100. (640ns) | |
63 | * | |
64 | * The calculated value allows us to right shift the SYSTIME register | |
65 | * value in order to quickly convert it into a nanosecond clock, | |
66 | * while allowing for the maximum possible adjustment value. | |
67 | * | |
68 | * These diagrams are only for the 10Gb link period | |
69 | * | |
70 | * SYSTIMEH SYSTIMEL | |
71 | * +--------------+ +--------------+ | |
72 | * X540 | 32 | | 1 | 3 | 28 | | |
73 | * *--------------+ +--------------+ | |
74 | * \________ 36 bits ______/ fract | |
75 | * | |
76 | * +--------------+ +--------------+ | |
77 | * 82599 | 32 | | 8 | 3 | 21 | | |
78 | * *--------------+ +--------------+ | |
79 | * \________ 43 bits ______/ fract | |
80 | * | |
81 | * The 36 bit X540 SYSTIME overflows every | |
82 | * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds | |
83 | * | |
84 | * The 43 bit 82599 SYSTIME overflows every | |
85 | * 2^43 * 10^-9 / 3600 = 2.4 hours | |
86 | */ | |
87 | #define IXGBE_INCVAL_10GB 0x66666666 | |
88 | #define IXGBE_INCVAL_1GB 0x40000000 | |
89 | #define IXGBE_INCVAL_100 0x50000000 | |
90 | ||
91 | #define IXGBE_INCVAL_SHIFT_10GB 28 | |
92 | #define IXGBE_INCVAL_SHIFT_1GB 24 | |
93 | #define IXGBE_INCVAL_SHIFT_100 21 | |
94 | ||
95 | #define IXGBE_INCVAL_SHIFT_82599 7 | |
96 | #define IXGBE_INCPER_SHIFT_82599 24 | |
3a6a4eda JK |
97 | |
98 | #define IXGBE_OVERFLOW_PERIOD (HZ * 30) | |
891dc082 | 99 | #define IXGBE_PTP_TX_TIMEOUT (HZ * 15) |
3a6a4eda | 100 | |
a5a0fc04 JK |
101 | /* half of a one second clock period, for use with PPS signal. We have to use |
102 | * this instead of something pre-defined like IXGBE_PTP_PPS_HALF_SECOND, in | |
103 | * order to force at least 64bits of precision for shifting | |
104 | */ | |
105 | #define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL | |
681ae1ad | 106 | |
a9763f3c MR |
107 | /* In contrast, the X550 controller has two registers, SYSTIMEH and SYSTIMEL |
108 | * which contain measurements of seconds and nanoseconds respectively. This | |
109 | * matches the standard linux representation of time in the kernel. In addition, | |
110 | * the X550 also has a SYSTIMER register which represents residue, or | |
111 | * subnanosecond overflow adjustments. To control clock adjustment, the TIMINCA | |
112 | * register is used, but it is unlike the X540 and 82599 devices. TIMINCA | |
113 | * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the | |
114 | * high bit representing whether the adjustent is positive or negative. Every | |
115 | * clock cycle, the X550 will add 12.5 ns + TIMINCA which can result in a range | |
116 | * of 12 to 13 nanoseconds adjustment. Unlike the 82599 and X540 devices, the | |
117 | * X550's clock for purposes of SYSTIME generation is constant and not dependent | |
118 | * on the link speed. | |
119 | * | |
120 | * SYSTIMEH SYSTIMEL SYSTIMER | |
121 | * +--------------+ +--------------+ +-------------+ | |
122 | * X550 | 32 | | 32 | | 32 | | |
123 | * *--------------+ +--------------+ +-------------+ | |
124 | * \____seconds___/ \_nanoseconds_/ \__2^-32 ns__/ | |
125 | * | |
126 | * This results in a full 96 bits to represent the clock, with 32 bits for | |
127 | * seconds, 32 bits for nanoseconds (largest value is 0d999999999 or just under | |
128 | * 1 second) and an additional 32 bits to measure sub nanosecond adjustments for | |
129 | * underflow of adjustments. | |
130 | * | |
131 | * The 32 bits of seconds for the X550 overflows every | |
132 | * 2^32 / ( 365.25 * 24 * 60 * 60 ) = ~136 years. | |
133 | * | |
134 | * In order to adjust the clock frequency for the X550, the TIMINCA register is | |
135 | * provided. This register represents a + or minus nearly 0.5 ns adjustment to | |
136 | * the base frequency. It is measured in 2^-32 ns units, with the high bit being | |
137 | * the sign bit. This register enables software to calculate frequency | |
138 | * adjustments and apply them directly to the clock rate. | |
139 | * | |
140 | * The math for converting ppb into TIMINCA values is fairly straightforward. | |
141 | * TIMINCA value = ( Base_Frequency * ppb ) / 1000000000ULL | |
142 | * | |
143 | * This assumes that ppb is never high enough to create a value bigger than | |
144 | * TIMINCA's 31 bits can store. This is ensured by the stack. Calculating this | |
145 | * value is also simple. | |
146 | * Max ppb = ( Max Adjustment / Base Frequency ) / 1000000000ULL | |
147 | * | |
148 | * For the X550, the Max adjustment is +/- 0.5 ns, and the base frequency is | |
149 | * 12.5 nanoseconds. This means that the Max ppb is 39999999 | |
150 | * Note: We subtract one in order to ensure no overflow, because the TIMINCA | |
151 | * register can only hold slightly under 0.5 nanoseconds. | |
152 | * | |
153 | * Because TIMINCA is measured in 2^-32 ns units, we have to convert 12.5 ns | |
154 | * into 2^-32 units, which is | |
155 | * | |
156 | * 12.5 * 2^32 = C80000000 | |
157 | * | |
158 | * Some revisions of hardware have a faster base frequency than the registers | |
159 | * were defined for. To fix this, we use a timecounter structure with the | |
160 | * proper mult and shift to convert the cycles into nanoseconds of time. | |
161 | */ | |
162 | #define IXGBE_X550_BASE_PERIOD 0xC80000000ULL | |
163 | #define INCVALUE_MASK 0x7FFFFFFF | |
164 | #define ISGN 0x80000000 | |
165 | #define MAX_TIMADJ 0x7FFFFFFF | |
166 | ||
82083673 | 167 | /** |
a9763f3c | 168 | * ixgbe_ptp_setup_sdp_x540 |
82083673 | 169 | * @hw: the hardware private structure |
82083673 | 170 | * |
db0677fa JK |
171 | * this function enables or disables the clock out feature on SDP0 for |
172 | * the X540 device. It will create a 1second periodic output that can | |
173 | * be used as the PPS (via an interrupt). | |
82083673 JK |
174 | * |
175 | * It calculates when the systime will be on an exact second, and then | |
176 | * aligns the start of the PPS signal to that value. The shift is | |
177 | * necessary because it can change based on the link speed. | |
178 | */ | |
a9763f3c | 179 | static void ixgbe_ptp_setup_sdp_x540(struct ixgbe_adapter *adapter) |
82083673 JK |
180 | { |
181 | struct ixgbe_hw *hw = &adapter->hw; | |
a9763f3c | 182 | int shift = adapter->hw_cc.shift; |
82083673 JK |
183 | u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem; |
184 | u64 ns = 0, clock_edge = 0; | |
185 | ||
a9763f3c MR |
186 | /* disable the pin first */ |
187 | IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0); | |
188 | IXGBE_WRITE_FLUSH(hw); | |
db0677fa | 189 | |
a9763f3c MR |
190 | if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED)) |
191 | return; | |
db0677fa | 192 | |
a9763f3c | 193 | esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); |
82083673 | 194 | |
a9763f3c MR |
195 | /* enable the SDP0 pin as output, and connected to the |
196 | * native function for Timesync (ClockOut) | |
197 | */ | |
198 | esdp |= IXGBE_ESDP_SDP0_DIR | | |
199 | IXGBE_ESDP_SDP0_NATIVE; | |
82083673 | 200 | |
a9763f3c MR |
201 | /* enable the Clock Out feature on SDP0, and allow |
202 | * interrupts to occur when the pin changes | |
203 | */ | |
204 | tsauxc = IXGBE_TSAUXC_EN_CLK | | |
205 | IXGBE_TSAUXC_SYNCLK | | |
206 | IXGBE_TSAUXC_SDP0_INT; | |
82083673 | 207 | |
a9763f3c MR |
208 | /* clock period (or pulse length) */ |
209 | clktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift); | |
210 | clktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32); | |
82083673 | 211 | |
a9763f3c MR |
212 | /* Account for the cyclecounter wrap-around value by |
213 | * using the converted ns value of the current time to | |
214 | * check for when the next aligned second would occur. | |
215 | */ | |
216 | clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML); | |
217 | clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32; | |
218 | ns = timecounter_cyc2time(&adapter->hw_tc, clock_edge); | |
82083673 | 219 | |
a9763f3c MR |
220 | div_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem); |
221 | clock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift); | |
82083673 | 222 | |
a9763f3c MR |
223 | /* specify the initial clock start time */ |
224 | trgttiml = (u32)clock_edge; | |
225 | trgttimh = (u32)(clock_edge >> 32); | |
82083673 | 226 | |
a9763f3c MR |
227 | IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml); |
228 | IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh); | |
229 | IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml); | |
230 | IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh); | |
82083673 | 231 | |
a9763f3c MR |
232 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); |
233 | IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); | |
82083673 | 234 | |
82083673 JK |
235 | IXGBE_WRITE_FLUSH(hw); |
236 | } | |
237 | ||
3a6a4eda | 238 | /** |
a9763f3c MR |
239 | * ixgbe_ptp_read_X550 - read cycle counter value |
240 | * @hw_cc: cyclecounter structure | |
241 | * | |
242 | * This function reads SYSTIME registers. It is called by the cyclecounter | |
243 | * structure to convert from internal representation into nanoseconds. We need | |
244 | * this for X550 since some skews do not have expected clock frequency and | |
245 | * result of SYSTIME is 32bits of "billions of cycles" and 32 bits of | |
246 | * "cycles", rather than seconds and nanoseconds. | |
247 | */ | |
248 | static cycle_t ixgbe_ptp_read_X550(const struct cyclecounter *hw_cc) | |
249 | { | |
250 | struct ixgbe_adapter *adapter = | |
251 | container_of(hw_cc, struct ixgbe_adapter, hw_cc); | |
252 | struct ixgbe_hw *hw = &adapter->hw; | |
253 | struct timespec64 ts; | |
254 | ||
255 | /* storage is 32 bits of 'billions of cycles' and 32 bits of 'cycles'. | |
256 | * Some revisions of hardware run at a higher frequency and so the | |
257 | * cycles are not guaranteed to be nanoseconds. The timespec64 created | |
258 | * here is used for its math/conversions but does not necessarily | |
259 | * represent nominal time. | |
260 | * | |
261 | * It should be noted that this cyclecounter will overflow at a | |
262 | * non-bitmask field since we have to convert our billions of cycles | |
263 | * into an actual cycles count. This results in some possible weird | |
264 | * situations at high cycle counter stamps. However given that 32 bits | |
265 | * of "seconds" is ~138 years this isn't a problem. Even at the | |
266 | * increased frequency of some revisions, this is still ~103 years. | |
267 | * Since the SYSTIME values start at 0 and we never write them, it is | |
268 | * highly unlikely for the cyclecounter to overflow in practice. | |
269 | */ | |
270 | IXGBE_READ_REG(hw, IXGBE_SYSTIMR); | |
271 | ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML); | |
272 | ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH); | |
273 | ||
274 | return (u64)timespec64_to_ns(&ts); | |
275 | } | |
276 | ||
277 | /** | |
278 | * ixgbe_ptp_read_82599 - read raw cycle counter (to be used by time counter) | |
49ce9c2c | 279 | * @cc: the cyclecounter structure |
3a6a4eda JK |
280 | * |
281 | * this function reads the cyclecounter registers and is called by the | |
282 | * cyclecounter structure used to construct a ns counter from the | |
283 | * arbitrary fixed point registers | |
284 | */ | |
a9763f3c | 285 | static cycle_t ixgbe_ptp_read_82599(const struct cyclecounter *cc) |
3a6a4eda JK |
286 | { |
287 | struct ixgbe_adapter *adapter = | |
a9763f3c | 288 | container_of(cc, struct ixgbe_adapter, hw_cc); |
3a6a4eda JK |
289 | struct ixgbe_hw *hw = &adapter->hw; |
290 | u64 stamp = 0; | |
291 | ||
292 | stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML); | |
293 | stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32; | |
294 | ||
295 | return stamp; | |
296 | } | |
297 | ||
298 | /** | |
a9763f3c MR |
299 | * ixgbe_ptp_convert_to_hwtstamp - convert register value to hw timestamp |
300 | * @adapter: private adapter structure | |
301 | * @hwtstamp: stack timestamp structure | |
302 | * @systim: unsigned 64bit system time value | |
303 | * | |
304 | * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value | |
305 | * which can be used by the stack's ptp functions. | |
306 | * | |
307 | * The lock is used to protect consistency of the cyclecounter and the SYSTIME | |
308 | * registers. However, it does not need to protect against the Rx or Tx | |
309 | * timestamp registers, as there can't be a new timestamp until the old one is | |
310 | * unlatched by reading. | |
311 | * | |
312 | * In addition to the timestamp in hardware, some controllers need a software | |
313 | * overflow cyclecounter, and this function takes this into account as well. | |
314 | **/ | |
315 | static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter, | |
316 | struct skb_shared_hwtstamps *hwtstamp, | |
317 | u64 timestamp) | |
318 | { | |
319 | unsigned long flags; | |
320 | struct timespec64 systime; | |
321 | u64 ns; | |
322 | ||
323 | memset(hwtstamp, 0, sizeof(*hwtstamp)); | |
324 | ||
325 | switch (adapter->hw.mac.type) { | |
326 | /* X550 and later hardware supposedly represent time using a seconds | |
327 | * and nanoseconds counter, instead of raw 64bits nanoseconds. We need | |
328 | * to convert the timestamp into cycles before it can be fed to the | |
329 | * cyclecounter. We need an actual cyclecounter because some revisions | |
330 | * of hardware run at a higher frequency and thus the counter does | |
331 | * not represent seconds/nanoseconds. Instead it can be thought of as | |
332 | * cycles and billions of cycles. | |
333 | */ | |
334 | case ixgbe_mac_X550: | |
335 | case ixgbe_mac_X550EM_x: | |
336 | /* Upper 32 bits represent billions of cycles, lower 32 bits | |
337 | * represent cycles. However, we use timespec64_to_ns for the | |
338 | * correct math even though the units haven't been corrected | |
339 | * yet. | |
340 | */ | |
341 | systime.tv_sec = timestamp >> 32; | |
342 | systime.tv_nsec = timestamp & 0xFFFFFFFF; | |
343 | ||
344 | timestamp = timespec64_to_ns(&systime); | |
345 | break; | |
346 | default: | |
347 | break; | |
348 | } | |
349 | ||
350 | spin_lock_irqsave(&adapter->tmreg_lock, flags); | |
351 | ns = timecounter_cyc2time(&adapter->hw_tc, timestamp); | |
352 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); | |
353 | ||
354 | hwtstamp->hwtstamp = ns_to_ktime(ns); | |
355 | } | |
356 | ||
357 | /** | |
358 | * ixgbe_ptp_adjfreq_82599 | |
49ce9c2c BH |
359 | * @ptp: the ptp clock structure |
360 | * @ppb: parts per billion adjustment from base | |
3a6a4eda JK |
361 | * |
362 | * adjust the frequency of the ptp cycle counter by the | |
363 | * indicated ppb from the base frequency. | |
364 | */ | |
a9763f3c | 365 | static int ixgbe_ptp_adjfreq_82599(struct ptp_clock_info *ptp, s32 ppb) |
3a6a4eda JK |
366 | { |
367 | struct ixgbe_adapter *adapter = | |
368 | container_of(ptp, struct ixgbe_adapter, ptp_caps); | |
369 | struct ixgbe_hw *hw = &adapter->hw; | |
a9763f3c MR |
370 | u64 freq, incval; |
371 | u32 diff; | |
3a6a4eda JK |
372 | int neg_adj = 0; |
373 | ||
374 | if (ppb < 0) { | |
375 | neg_adj = 1; | |
376 | ppb = -ppb; | |
377 | } | |
378 | ||
379 | smp_mb(); | |
380 | incval = ACCESS_ONCE(adapter->base_incval); | |
381 | ||
382 | freq = incval; | |
383 | freq *= ppb; | |
384 | diff = div_u64(freq, 1000000000ULL); | |
385 | ||
386 | incval = neg_adj ? (incval - diff) : (incval + diff); | |
387 | ||
388 | switch (hw->mac.type) { | |
389 | case ixgbe_mac_X540: | |
a9763f3c MR |
390 | if (incval > 0xFFFFFFFFULL) |
391 | e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n"); | |
392 | IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, (u32)incval); | |
3a6a4eda JK |
393 | break; |
394 | case ixgbe_mac_82599EB: | |
a9763f3c MR |
395 | if (incval > 0x00FFFFFFULL) |
396 | e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n"); | |
3a6a4eda JK |
397 | IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, |
398 | (1 << IXGBE_INCPER_SHIFT_82599) | | |
a9763f3c | 399 | ((u32)incval & 0x00FFFFFFUL)); |
3a6a4eda JK |
400 | break; |
401 | default: | |
402 | break; | |
403 | } | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
a9763f3c MR |
408 | /** |
409 | * ixgbe_ptp_adjfreq_X550 | |
410 | * @ptp: the ptp clock structure | |
411 | * @ppb: parts per billion adjustment from base | |
412 | * | |
413 | * adjust the frequency of the SYSTIME registers by the indicated ppb from base | |
414 | * frequency | |
415 | */ | |
416 | static int ixgbe_ptp_adjfreq_X550(struct ptp_clock_info *ptp, s32 ppb) | |
417 | { | |
418 | struct ixgbe_adapter *adapter = | |
419 | container_of(ptp, struct ixgbe_adapter, ptp_caps); | |
420 | struct ixgbe_hw *hw = &adapter->hw; | |
421 | int neg_adj = 0; | |
422 | u64 rate = IXGBE_X550_BASE_PERIOD; | |
423 | u32 inca; | |
424 | ||
425 | if (ppb < 0) { | |
426 | neg_adj = 1; | |
427 | ppb = -ppb; | |
428 | } | |
429 | rate *= ppb; | |
430 | rate = div_u64(rate, 1000000000ULL); | |
431 | ||
432 | /* warn if rate is too large */ | |
433 | if (rate >= INCVALUE_MASK) | |
434 | e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n"); | |
435 | ||
436 | inca = rate & INCVALUE_MASK; | |
437 | if (neg_adj) | |
438 | inca |= ISGN; | |
439 | ||
440 | IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, inca); | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
3a6a4eda JK |
445 | /** |
446 | * ixgbe_ptp_adjtime | |
49ce9c2c BH |
447 | * @ptp: the ptp clock structure |
448 | * @delta: offset to adjust the cycle counter by | |
3a6a4eda JK |
449 | * |
450 | * adjust the timer by resetting the timecounter structure. | |
451 | */ | |
452 | static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
453 | { | |
454 | struct ixgbe_adapter *adapter = | |
455 | container_of(ptp, struct ixgbe_adapter, ptp_caps); | |
456 | unsigned long flags; | |
3a6a4eda JK |
457 | |
458 | spin_lock_irqsave(&adapter->tmreg_lock, flags); | |
a9763f3c | 459 | timecounter_adjtime(&adapter->hw_tc, delta); |
3a6a4eda | 460 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); |
db0677fa | 461 | |
a9763f3c MR |
462 | if (adapter->ptp_setup_sdp) |
463 | adapter->ptp_setup_sdp(adapter); | |
82083673 | 464 | |
3a6a4eda JK |
465 | return 0; |
466 | } | |
467 | ||
468 | /** | |
469 | * ixgbe_ptp_gettime | |
49ce9c2c BH |
470 | * @ptp: the ptp clock structure |
471 | * @ts: timespec structure to hold the current time value | |
3a6a4eda JK |
472 | * |
473 | * read the timecounter and return the correct value on ns, | |
474 | * after converting it into a struct timespec. | |
475 | */ | |
91432d18 | 476 | static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) |
3a6a4eda JK |
477 | { |
478 | struct ixgbe_adapter *adapter = | |
479 | container_of(ptp, struct ixgbe_adapter, ptp_caps); | |
3a6a4eda | 480 | unsigned long flags; |
a9763f3c | 481 | u64 ns; |
3a6a4eda JK |
482 | |
483 | spin_lock_irqsave(&adapter->tmreg_lock, flags); | |
a9763f3c | 484 | ns = timecounter_read(&adapter->hw_tc); |
3a6a4eda JK |
485 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); |
486 | ||
0704fae3 | 487 | *ts = ns_to_timespec64(ns); |
3a6a4eda JK |
488 | |
489 | return 0; | |
490 | } | |
491 | ||
492 | /** | |
493 | * ixgbe_ptp_settime | |
49ce9c2c BH |
494 | * @ptp: the ptp clock structure |
495 | * @ts: the timespec containing the new time for the cycle counter | |
3a6a4eda JK |
496 | * |
497 | * reset the timecounter to use a new base value instead of the kernel | |
498 | * wall timer value. | |
499 | */ | |
500 | static int ixgbe_ptp_settime(struct ptp_clock_info *ptp, | |
91432d18 | 501 | const struct timespec64 *ts) |
3a6a4eda JK |
502 | { |
503 | struct ixgbe_adapter *adapter = | |
504 | container_of(ptp, struct ixgbe_adapter, ptp_caps); | |
3a6a4eda | 505 | unsigned long flags; |
a9763f3c | 506 | u64 ns = timespec64_to_ns(ts); |
3a6a4eda JK |
507 | |
508 | /* reset the timecounter */ | |
509 | spin_lock_irqsave(&adapter->tmreg_lock, flags); | |
a9763f3c | 510 | timecounter_init(&adapter->hw_tc, &adapter->hw_cc, ns); |
3a6a4eda JK |
511 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); |
512 | ||
a9763f3c MR |
513 | if (adapter->ptp_setup_sdp) |
514 | adapter->ptp_setup_sdp(adapter); | |
3a6a4eda JK |
515 | return 0; |
516 | } | |
517 | ||
518 | /** | |
04c8de8e | 519 | * ixgbe_ptp_feature_enable |
49ce9c2c BH |
520 | * @ptp: the ptp clock structure |
521 | * @rq: the requested feature to change | |
522 | * @on: whether to enable or disable the feature | |
3a6a4eda JK |
523 | * |
524 | * enable (or disable) ancillary features of the phc subsystem. | |
681ae1ad | 525 | * our driver only supports the PPS feature on the X540 |
3a6a4eda | 526 | */ |
04c8de8e JK |
527 | static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp, |
528 | struct ptp_clock_request *rq, int on) | |
3a6a4eda | 529 | { |
681ae1ad JK |
530 | struct ixgbe_adapter *adapter = |
531 | container_of(ptp, struct ixgbe_adapter, ptp_caps); | |
532 | ||
533 | /** | |
534 | * When PPS is enabled, unmask the interrupt for the ClockOut | |
535 | * feature, so that the interrupt handler can send the PPS | |
536 | * event when the clock SDP triggers. Clear mask when PPS is | |
537 | * disabled | |
538 | */ | |
a9763f3c MR |
539 | if (rq->type != PTP_CLK_REQ_PPS || !adapter->ptp_setup_sdp) |
540 | return -ENOTSUPP; | |
541 | ||
542 | if (on) | |
543 | adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED; | |
544 | else | |
545 | adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED; | |
681ae1ad | 546 | |
a9763f3c MR |
547 | adapter->ptp_setup_sdp(adapter); |
548 | return 0; | |
3a6a4eda JK |
549 | } |
550 | ||
681ae1ad JK |
551 | /** |
552 | * ixgbe_ptp_check_pps_event | |
49ce9c2c | 553 | * @adapter: the private adapter structure |
681ae1ad JK |
554 | * |
555 | * This function is called by the interrupt routine when checking for | |
556 | * interrupts. It will check and handle a pps event. | |
557 | */ | |
a9763f3c | 558 | void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter) |
681ae1ad JK |
559 | { |
560 | struct ixgbe_hw *hw = &adapter->hw; | |
561 | struct ptp_clock_event event; | |
562 | ||
3645adbb JK |
563 | event.type = PTP_CLOCK_PPS; |
564 | ||
565 | /* this check is necessary in case the interrupt was enabled via some | |
566 | * alternative means (ex. debug_fs). Better to check here than | |
567 | * everywhere that calls this function. | |
568 | */ | |
569 | if (!adapter->ptp_clock) | |
570 | return; | |
571 | ||
db0677fa JK |
572 | switch (hw->mac.type) { |
573 | case ixgbe_mac_X540: | |
574 | ptp_clock_event(adapter->ptp_clock, &event); | |
575 | break; | |
576 | default: | |
577 | break; | |
681ae1ad JK |
578 | } |
579 | } | |
580 | ||
3a6a4eda | 581 | /** |
f2f33387 JK |
582 | * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow |
583 | * @adapter: private adapter struct | |
3a6a4eda | 584 | * |
f2f33387 | 585 | * this watchdog task periodically reads the timecounter |
3a6a4eda | 586 | * in order to prevent missing when the system time registers wrap |
f2f33387 | 587 | * around. This needs to be run approximately twice a minute. |
3a6a4eda JK |
588 | */ |
589 | void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter) | |
590 | { | |
f2f33387 JK |
591 | bool timeout = time_is_before_jiffies(adapter->last_overflow_check + |
592 | IXGBE_OVERFLOW_PERIOD); | |
91432d18 | 593 | struct timespec64 ts; |
3a6a4eda | 594 | |
891dc082 | 595 | if (timeout) { |
3a6a4eda JK |
596 | ixgbe_ptp_gettime(&adapter->ptp_caps, &ts); |
597 | adapter->last_overflow_check = jiffies; | |
598 | } | |
599 | } | |
600 | ||
1d1a79b5 | 601 | /** |
6cb562d6 JK |
602 | * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched |
603 | * @adapter: private network adapter structure | |
1d1a79b5 | 604 | * |
6cb562d6 JK |
605 | * this watchdog task is scheduled to detect error case where hardware has |
606 | * dropped an Rx packet that was timestamped when the ring is full. The | |
607 | * particular error is rare but leaves the device in a state unable to timestamp | |
608 | * any future packets. | |
1d1a79b5 | 609 | */ |
6cb562d6 | 610 | void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter) |
1d1a79b5 | 611 | { |
6cb562d6 | 612 | struct ixgbe_hw *hw = &adapter->hw; |
6cb562d6 | 613 | u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); |
a9763f3c | 614 | struct ixgbe_ring *rx_ring; |
6cb562d6 | 615 | unsigned long rx_event; |
a9763f3c | 616 | int n; |
1d1a79b5 | 617 | |
6cb562d6 JK |
618 | /* if we don't have a valid timestamp in the registers, just update the |
619 | * timeout counter and exit | |
620 | */ | |
621 | if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) { | |
622 | adapter->last_rx_ptp_check = jiffies; | |
623 | return; | |
1d1a79b5 JK |
624 | } |
625 | ||
6cb562d6 JK |
626 | /* determine the most recent watchdog or rx_timestamp event */ |
627 | rx_event = adapter->last_rx_ptp_check; | |
a9763f3c MR |
628 | for (n = 0; n < adapter->num_rx_queues; n++) { |
629 | rx_ring = adapter->rx_ring[n]; | |
630 | if (time_after(rx_ring->last_rx_timestamp, rx_event)) | |
631 | rx_event = rx_ring->last_rx_timestamp; | |
632 | } | |
1d1a79b5 | 633 | |
6cb562d6 | 634 | /* only need to read the high RXSTMP register to clear the lock */ |
a9763f3c | 635 | if (time_is_before_jiffies(rx_event + 5 * HZ)) { |
6cb562d6 JK |
636 | IXGBE_READ_REG(hw, IXGBE_RXSTMPH); |
637 | adapter->last_rx_ptp_check = jiffies; | |
1d1a79b5 | 638 | |
a9763f3c | 639 | adapter->rx_hwtstamp_cleared++; |
c5ffe7e1 | 640 | e_warn(drv, "clearing RX Timestamp hang\n"); |
1d1a79b5 JK |
641 | } |
642 | } | |
643 | ||
a9763f3c MR |
644 | /** |
645 | * ixgbe_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state | |
646 | * @adapter: the private adapter structure | |
647 | * | |
648 | * This function should be called whenever the state related to a Tx timestamp | |
649 | * needs to be cleared. This helps ensure that all related bits are reset for | |
650 | * the next Tx timestamp event. | |
651 | */ | |
652 | static void ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter *adapter) | |
653 | { | |
654 | struct ixgbe_hw *hw = &adapter->hw; | |
655 | ||
656 | IXGBE_READ_REG(hw, IXGBE_TXSTMPH); | |
657 | if (adapter->ptp_tx_skb) { | |
658 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
659 | adapter->ptp_tx_skb = NULL; | |
660 | } | |
661 | clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); | |
662 | } | |
663 | ||
3a6a4eda JK |
664 | /** |
665 | * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp | |
891dc082 | 666 | * @adapter: the private adapter struct |
3a6a4eda JK |
667 | * |
668 | * if the timestamp is valid, we convert it into the timecounter ns | |
669 | * value, then store that result into the shhwtstamps structure which | |
670 | * is passed up the network stack | |
671 | */ | |
891dc082 | 672 | static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter) |
3a6a4eda | 673 | { |
891dc082 | 674 | struct ixgbe_hw *hw = &adapter->hw; |
3a6a4eda | 675 | struct skb_shared_hwtstamps shhwtstamps; |
a9763f3c | 676 | u64 regval = 0; |
3a6a4eda | 677 | |
3a6a4eda JK |
678 | regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); |
679 | regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32; | |
680 | ||
a9763f3c | 681 | ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval); |
891dc082 JK |
682 | skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); |
683 | ||
a9763f3c | 684 | ixgbe_ptp_clear_tx_timestamp(adapter); |
891dc082 JK |
685 | } |
686 | ||
687 | /** | |
688 | * ixgbe_ptp_tx_hwtstamp_work | |
689 | * @work: pointer to the work struct | |
690 | * | |
691 | * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware | |
dbedd44e | 692 | * timestamp has been taken for the current skb. It is necessary, because the |
891dc082 JK |
693 | * descriptor's "done" bit does not correlate with the timestamp event. |
694 | */ | |
695 | static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work) | |
696 | { | |
697 | struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter, | |
698 | ptp_tx_work); | |
699 | struct ixgbe_hw *hw = &adapter->hw; | |
700 | bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + | |
701 | IXGBE_PTP_TX_TIMEOUT); | |
702 | u32 tsynctxctl; | |
703 | ||
a9763f3c MR |
704 | /* we have to have a valid skb to poll for a timestamp */ |
705 | if (!adapter->ptp_tx_skb) { | |
706 | ixgbe_ptp_clear_tx_timestamp(adapter); | |
891dc082 JK |
707 | return; |
708 | } | |
709 | ||
a9763f3c | 710 | /* stop polling once we have a valid timestamp */ |
891dc082 | 711 | tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); |
a9763f3c | 712 | if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) { |
891dc082 | 713 | ixgbe_ptp_tx_hwtstamp(adapter); |
a9763f3c MR |
714 | return; |
715 | } | |
716 | ||
717 | if (timeout) { | |
718 | ixgbe_ptp_clear_tx_timestamp(adapter); | |
719 | adapter->tx_hwtstamp_timeouts++; | |
720 | e_warn(drv, "clearing Tx Timestamp hang\n"); | |
721 | } else { | |
891dc082 JK |
722 | /* reschedule to keep checking if it's not available yet */ |
723 | schedule_work(&adapter->ptp_tx_work); | |
a9763f3c | 724 | } |
3a6a4eda JK |
725 | } |
726 | ||
727 | /** | |
a9763f3c MR |
728 | * ixgbe_ptp_rx_pktstamp - utility function to get RX time stamp from buffer |
729 | * @q_vector: structure containing interrupt and ring information | |
730 | * @skb: the packet | |
731 | * | |
732 | * This function will be called by the Rx routine of the timestamp for this | |
733 | * packet is stored in the buffer. The value is stored in little endian format | |
734 | * starting at the end of the packet data. | |
735 | */ | |
736 | void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *q_vector, | |
737 | struct sk_buff *skb) | |
738 | { | |
739 | __le64 regval; | |
740 | ||
741 | /* copy the bits out of the skb, and then trim the skb length */ | |
742 | skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, ®val, | |
743 | IXGBE_TS_HDR_LEN); | |
744 | __pskb_trim(skb, skb->len - IXGBE_TS_HDR_LEN); | |
745 | ||
746 | /* The timestamp is recorded in little endian format, and is stored at | |
747 | * the end of the packet. | |
748 | * | |
749 | * DWORD: N N + 1 N + 2 | |
750 | * Field: End of Packet SYSTIMH SYSTIML | |
751 | */ | |
752 | ixgbe_ptp_convert_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb), | |
753 | le64_to_cpu(regval)); | |
754 | } | |
755 | ||
756 | /** | |
757 | * ixgbe_ptp_rx_rgtstamp - utility function which checks for RX time stamp | |
758 | * @q_vector: structure containing interrupt and ring information | |
3a6a4eda JK |
759 | * @skb: particular skb to send timestamp with |
760 | * | |
761 | * if the timestamp is valid, we convert it into the timecounter ns | |
762 | * value, then store that result into the shhwtstamps structure which | |
763 | * is passed up the network stack | |
764 | */ | |
a9763f3c MR |
765 | void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *q_vector, |
766 | struct sk_buff *skb) | |
3a6a4eda | 767 | { |
a9763f3c MR |
768 | struct ixgbe_adapter *adapter; |
769 | struct ixgbe_hw *hw; | |
770 | u64 regval = 0; | |
3a6a4eda | 771 | u32 tsyncrxctl; |
a9763f3c MR |
772 | |
773 | /* we cannot process timestamps on a ring without a q_vector */ | |
774 | if (!q_vector || !q_vector->adapter) | |
775 | return; | |
776 | ||
777 | adapter = q_vector->adapter; | |
778 | hw = &adapter->hw; | |
779 | ||
780 | /* Read the tsyncrxctl register afterwards in order to prevent taking an | |
781 | * I/O hit on every packet. | |
782 | */ | |
3a6a4eda | 783 | |
3a6a4eda | 784 | tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); |
f42df167 | 785 | if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) |
1d1a79b5 JK |
786 | return; |
787 | ||
3a6a4eda JK |
788 | regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); |
789 | regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32; | |
790 | ||
a9763f3c | 791 | ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); |
3a6a4eda JK |
792 | } |
793 | ||
93501d48 JK |
794 | int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr) |
795 | { | |
796 | struct hwtstamp_config *config = &adapter->tstamp_config; | |
797 | ||
798 | return copy_to_user(ifr->ifr_data, config, | |
799 | sizeof(*config)) ? -EFAULT : 0; | |
800 | } | |
801 | ||
3a6a4eda | 802 | /** |
a7ef4286 JK |
803 | * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode |
804 | * @adapter: the private ixgbe adapter structure | |
805 | * @config: the hwtstamp configuration requested | |
3a6a4eda JK |
806 | * |
807 | * Outgoing time stamping can be enabled and disabled. Play nice and | |
93501d48 | 808 | * disable it when requested, although it shouldn't cause any overhead |
3a6a4eda JK |
809 | * when no packet needs it. At most one packet in the queue may be |
810 | * marked for time stamping, otherwise it would be impossible to tell | |
811 | * for sure to which packet the hardware time stamp belongs. | |
812 | * | |
813 | * Incoming time stamping has to be configured via the hardware | |
814 | * filters. Not all combinations are supported, in particular event | |
815 | * type has to be specified. Matching the kind of event packet is | |
816 | * not supported, with the exception of "all V2 events regardless of | |
817 | * level 2 or 4". | |
c19197a7 JK |
818 | * |
819 | * Since hardware always timestamps Path delay packets when timestamping V2 | |
820 | * packets, regardless of the type specified in the register, only use V2 | |
821 | * Event mode. This more accurately tells the user what the hardware is going | |
822 | * to do anyways. | |
a7ef4286 JK |
823 | * |
824 | * Note: this may modify the hwtstamp configuration towards a more general | |
825 | * mode, if required to support the specifically requested mode. | |
3a6a4eda | 826 | */ |
a7ef4286 JK |
827 | static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, |
828 | struct hwtstamp_config *config) | |
3a6a4eda JK |
829 | { |
830 | struct ixgbe_hw *hw = &adapter->hw; | |
3a6a4eda JK |
831 | u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED; |
832 | u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED; | |
f3444d8b | 833 | u32 tsync_rx_mtrl = PTP_EV_PORT << 16; |
3a6a4eda JK |
834 | bool is_l2 = false; |
835 | u32 regval; | |
836 | ||
3a6a4eda | 837 | /* reserved for future extensions */ |
a7ef4286 | 838 | if (config->flags) |
3a6a4eda JK |
839 | return -EINVAL; |
840 | ||
a7ef4286 | 841 | switch (config->tx_type) { |
3a6a4eda JK |
842 | case HWTSTAMP_TX_OFF: |
843 | tsync_tx_ctl = 0; | |
844 | case HWTSTAMP_TX_ON: | |
845 | break; | |
846 | default: | |
847 | return -ERANGE; | |
848 | } | |
849 | ||
a7ef4286 | 850 | switch (config->rx_filter) { |
3a6a4eda JK |
851 | case HWTSTAMP_FILTER_NONE: |
852 | tsync_rx_ctl = 0; | |
f3444d8b | 853 | tsync_rx_mtrl = 0; |
a9763f3c MR |
854 | adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | |
855 | IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); | |
3a6a4eda JK |
856 | break; |
857 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
858 | tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; | |
b1e50f7a | 859 | tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG; |
a9763f3c MR |
860 | adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | |
861 | IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); | |
3a6a4eda JK |
862 | break; |
863 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
864 | tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; | |
b1e50f7a | 865 | tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG; |
a9763f3c MR |
866 | adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | |
867 | IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); | |
3a6a4eda | 868 | break; |
c19197a7 JK |
869 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
870 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
871 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
3a6a4eda JK |
872 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
873 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
874 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3a6a4eda JK |
875 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
876 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
877 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
3a6a4eda | 878 | tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2; |
3a6a4eda | 879 | is_l2 = true; |
a7ef4286 | 880 | config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
a9763f3c MR |
881 | adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | |
882 | IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); | |
3a6a4eda JK |
883 | break; |
884 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
885 | case HWTSTAMP_FILTER_ALL: | |
a9763f3c MR |
886 | /* The X550 controller is capable of timestamping all packets, |
887 | * which allows it to accept any filter. | |
888 | */ | |
889 | if (hw->mac.type >= ixgbe_mac_X550) { | |
890 | tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL; | |
891 | config->rx_filter = HWTSTAMP_FILTER_ALL; | |
892 | adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; | |
893 | break; | |
894 | } | |
895 | /* fall through */ | |
3a6a4eda JK |
896 | default: |
897 | /* | |
1d1a79b5 JK |
898 | * register RXMTRL must be set in order to do V1 packets, |
899 | * therefore it is not possible to time stamp both V1 Sync and | |
900 | * Delay_Req messages and hardware does not support | |
901 | * timestamping all packets => return error | |
3a6a4eda | 902 | */ |
a9763f3c MR |
903 | adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | |
904 | IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); | |
a7ef4286 | 905 | config->rx_filter = HWTSTAMP_FILTER_NONE; |
3a6a4eda JK |
906 | return -ERANGE; |
907 | } | |
908 | ||
909 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
a9763f3c MR |
910 | adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | |
911 | IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); | |
3a6a4eda JK |
912 | if (tsync_rx_ctl | tsync_tx_ctl) |
913 | return -ERANGE; | |
914 | return 0; | |
915 | } | |
916 | ||
a9763f3c MR |
917 | /* Per-packet timestamping only works if the filter is set to all |
918 | * packets. Since this is desired, always timestamp all packets as long | |
919 | * as any Rx filter was configured. | |
920 | */ | |
921 | switch (hw->mac.type) { | |
922 | case ixgbe_mac_X550: | |
923 | case ixgbe_mac_X550EM_x: | |
924 | /* enable timestamping all packets only if at least some | |
925 | * packets were requested. Otherwise, play nice and disable | |
926 | * timestamping | |
927 | */ | |
928 | if (config->rx_filter == HWTSTAMP_FILTER_NONE) | |
929 | break; | |
930 | ||
931 | tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED | | |
932 | IXGBE_TSYNCRXCTL_TYPE_ALL | | |
933 | IXGBE_TSYNCRXCTL_TSIP_UT_EN; | |
934 | config->rx_filter = HWTSTAMP_FILTER_ALL; | |
935 | adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; | |
936 | adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER; | |
937 | is_l2 = true; | |
938 | break; | |
939 | default: | |
940 | break; | |
941 | } | |
942 | ||
6ccf7a57 | 943 | /* define ethertype filter for timestamping L2 packets */ |
3a6a4eda | 944 | if (is_l2) |
6ccf7a57 | 945 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), |
3a6a4eda JK |
946 | (IXGBE_ETQF_FILTER_EN | /* enable filter */ |
947 | IXGBE_ETQF_1588 | /* enable timestamping */ | |
948 | ETH_P_1588)); /* 1588 eth protocol type */ | |
949 | else | |
6ccf7a57 | 950 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); |
3a6a4eda | 951 | |
3a6a4eda JK |
952 | /* enable/disable TX */ |
953 | regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); | |
954 | regval &= ~IXGBE_TSYNCTXCTL_ENABLED; | |
955 | regval |= tsync_tx_ctl; | |
956 | IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval); | |
957 | ||
958 | /* enable/disable RX */ | |
959 | regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); | |
960 | regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK); | |
961 | regval |= tsync_rx_ctl; | |
962 | IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval); | |
963 | ||
964 | /* define which PTP packets are time stamped */ | |
965 | IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl); | |
966 | ||
967 | IXGBE_WRITE_FLUSH(hw); | |
968 | ||
969 | /* clear TX/RX time stamp registers, just to be sure */ | |
a9763f3c MR |
970 | ixgbe_ptp_clear_tx_timestamp(adapter); |
971 | IXGBE_READ_REG(hw, IXGBE_RXSTMPH); | |
3a6a4eda | 972 | |
a7ef4286 JK |
973 | return 0; |
974 | } | |
975 | ||
976 | /** | |
977 | * ixgbe_ptp_set_ts_config - user entry point for timestamp mode | |
978 | * @adapter: pointer to adapter struct | |
979 | * @ifreq: ioctl data | |
980 | * | |
981 | * Set hardware to requested mode. If unsupported, return an error with no | |
982 | * changes. Otherwise, store the mode for future reference. | |
983 | */ | |
984 | int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr) | |
985 | { | |
986 | struct hwtstamp_config config; | |
987 | int err; | |
988 | ||
989 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
990 | return -EFAULT; | |
991 | ||
992 | err = ixgbe_ptp_set_timestamp_mode(adapter, &config); | |
993 | if (err) | |
994 | return err; | |
995 | ||
93501d48 JK |
996 | /* save these settings for future reference */ |
997 | memcpy(&adapter->tstamp_config, &config, | |
998 | sizeof(adapter->tstamp_config)); | |
999 | ||
3a6a4eda JK |
1000 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
1001 | -EFAULT : 0; | |
1002 | } | |
1003 | ||
a9763f3c MR |
1004 | static void ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter *adapter, |
1005 | u32 *shift, u32 *incval) | |
3a6a4eda | 1006 | { |
3a6a4eda JK |
1007 | /** |
1008 | * Scale the NIC cycle counter by a large factor so that | |
1009 | * relatively small corrections to the frequency can be added | |
1010 | * or subtracted. The drawbacks of a large factor include | |
1011 | * (a) the clock register overflows more quickly, (b) the cycle | |
1012 | * counter structure must be able to convert the systime value | |
1013 | * to nanoseconds using only a multiplier and a right-shift, | |
1014 | * and (c) the value must fit within the timinca register space | |
1015 | * => math based on internal DMA clock rate and available bits | |
1a71ab24 JK |
1016 | * |
1017 | * Note that when there is no link, internal DMA clock is same as when | |
1018 | * link speed is 10Gb. Set the registers correctly even when link is | |
1019 | * down to preserve the clock setting | |
3a6a4eda | 1020 | */ |
1a71ab24 | 1021 | switch (adapter->link_speed) { |
3a6a4eda | 1022 | case IXGBE_LINK_SPEED_100_FULL: |
a9763f3c MR |
1023 | *shift = IXGBE_INCVAL_SHIFT_100; |
1024 | *incval = IXGBE_INCVAL_100; | |
3a6a4eda JK |
1025 | break; |
1026 | case IXGBE_LINK_SPEED_1GB_FULL: | |
a9763f3c MR |
1027 | *shift = IXGBE_INCVAL_SHIFT_1GB; |
1028 | *incval = IXGBE_INCVAL_1GB; | |
3a6a4eda JK |
1029 | break; |
1030 | case IXGBE_LINK_SPEED_10GB_FULL: | |
1a71ab24 | 1031 | default: |
a9763f3c MR |
1032 | *shift = IXGBE_INCVAL_SHIFT_10GB; |
1033 | *incval = IXGBE_INCVAL_10GB; | |
3a6a4eda JK |
1034 | break; |
1035 | } | |
a9763f3c | 1036 | } |
3a6a4eda | 1037 | |
a9763f3c MR |
1038 | /** |
1039 | * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw | |
1040 | * @adapter: pointer to the adapter structure | |
1041 | * | |
1042 | * This function should be called to set the proper values for the TIMINCA | |
1043 | * register and tell the cyclecounter structure what the tick rate of SYSTIME | |
1044 | * is. It does not directly modify SYSTIME registers or the timecounter | |
1045 | * structure. It should be called whenever a new TIMINCA value is necessary, | |
1046 | * such as during initialization or when the link speed changes. | |
1047 | */ | |
1048 | void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter) | |
1049 | { | |
1050 | struct ixgbe_hw *hw = &adapter->hw; | |
1051 | struct cyclecounter cc; | |
1052 | unsigned long flags; | |
1053 | u32 incval = 0; | |
1054 | u32 tsauxc = 0; | |
1055 | u32 fuse0 = 0; | |
1056 | ||
1057 | /* For some of the boards below this mask is technically incorrect. | |
1058 | * The timestamp mask overflows at approximately 61bits. However the | |
1059 | * particular hardware does not overflow on an even bitmask value. | |
1060 | * Instead, it overflows due to conversion of upper 32bits billions of | |
1061 | * cycles. Timecounters are not really intended for this purpose so | |
1062 | * they do not properly function if the overflow point isn't 2^N-1. | |
1063 | * However, the actual SYSTIME values in question take ~138 years to | |
1064 | * overflow. In practice this means they won't actually overflow. A | |
1065 | * proper fix to this problem would require modification of the | |
1066 | * timecounter delta calculations. | |
3a6a4eda | 1067 | */ |
a9763f3c MR |
1068 | cc.mask = CLOCKSOURCE_MASK(64); |
1069 | cc.mult = 1; | |
1070 | cc.shift = 0; | |
1071 | ||
3a6a4eda | 1072 | switch (hw->mac.type) { |
a9763f3c MR |
1073 | case ixgbe_mac_X550EM_x: |
1074 | /* SYSTIME assumes X550EM_x board frequency is 300Mhz, and is | |
1075 | * designed to represent seconds and nanoseconds when this is | |
1076 | * the case. However, some revisions of hardware have a 400Mhz | |
1077 | * clock and we have to compensate for this frequency | |
1078 | * variation using corrected mult and shift values. | |
1079 | */ | |
1080 | fuse0 = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)); | |
1081 | if (!(fuse0 & IXGBE_FUSES0_300MHZ)) { | |
1082 | cc.mult = 3; | |
1083 | cc.shift = 2; | |
1084 | } | |
1085 | /* fallthrough */ | |
1086 | case ixgbe_mac_X550: | |
1087 | cc.read = ixgbe_ptp_read_X550; | |
1088 | ||
1089 | /* enable SYSTIME counter */ | |
1090 | IXGBE_WRITE_REG(hw, IXGBE_SYSTIMR, 0); | |
1091 | IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0); | |
1092 | IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0); | |
1093 | tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); | |
1094 | IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, | |
1095 | tsauxc & ~IXGBE_TSAUXC_DISABLE_SYSTIME); | |
1096 | IXGBE_WRITE_REG(hw, IXGBE_TSIM, IXGBE_TSIM_TXTS); | |
1097 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_TIMESYNC); | |
1098 | ||
1099 | IXGBE_WRITE_FLUSH(hw); | |
1100 | break; | |
3a6a4eda | 1101 | case ixgbe_mac_X540: |
a9763f3c MR |
1102 | cc.read = ixgbe_ptp_read_82599; |
1103 | ||
1104 | ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval); | |
3a6a4eda JK |
1105 | IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); |
1106 | break; | |
1107 | case ixgbe_mac_82599EB: | |
a9763f3c MR |
1108 | cc.read = ixgbe_ptp_read_82599; |
1109 | ||
1110 | ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval); | |
3a6a4eda | 1111 | incval >>= IXGBE_INCVAL_SHIFT_82599; |
a9763f3c | 1112 | cc.shift -= IXGBE_INCVAL_SHIFT_82599; |
3a6a4eda | 1113 | IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, |
a9763f3c | 1114 | (1 << IXGBE_INCPER_SHIFT_82599) | incval); |
3a6a4eda JK |
1115 | break; |
1116 | default: | |
1117 | /* other devices aren't supported */ | |
1118 | return; | |
1119 | } | |
1120 | ||
1a71ab24 | 1121 | /* update the base incval used to calculate frequency adjustment */ |
3a6a4eda JK |
1122 | ACCESS_ONCE(adapter->base_incval) = incval; |
1123 | smp_mb(); | |
1124 | ||
1a71ab24 | 1125 | /* need lock to prevent incorrect read while modifying cyclecounter */ |
3a6a4eda | 1126 | spin_lock_irqsave(&adapter->tmreg_lock, flags); |
a9763f3c | 1127 | memcpy(&adapter->hw_cc, &cc, sizeof(adapter->hw_cc)); |
1a71ab24 JK |
1128 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); |
1129 | } | |
1130 | ||
1131 | /** | |
1132 | * ixgbe_ptp_reset | |
1133 | * @adapter: the ixgbe private board structure | |
1134 | * | |
d6321407 JK |
1135 | * When the MAC resets, all the hardware bits for timesync are reset. This |
1136 | * function is used to re-enable the device for PTP based on current settings. | |
1137 | * We do lose the current clock time, so just reset the cyclecounter to the | |
1138 | * system real clock time. | |
1139 | * | |
1140 | * This function will maintain hwtstamp_config settings, and resets the SDP | |
1141 | * output if it was enabled. | |
1a71ab24 JK |
1142 | */ |
1143 | void ixgbe_ptp_reset(struct ixgbe_adapter *adapter) | |
1144 | { | |
1145 | struct ixgbe_hw *hw = &adapter->hw; | |
1146 | unsigned long flags; | |
1147 | ||
d6321407 JK |
1148 | /* reset the hardware timestamping mode */ |
1149 | ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); | |
93501d48 | 1150 | |
a9763f3c MR |
1151 | /* 82598 does not support PTP */ |
1152 | if (hw->mac.type == ixgbe_mac_82598EB) | |
1153 | return; | |
1154 | ||
1a71ab24 JK |
1155 | ixgbe_ptp_start_cyclecounter(adapter); |
1156 | ||
1157 | spin_lock_irqsave(&adapter->tmreg_lock, flags); | |
a9763f3c | 1158 | timecounter_init(&adapter->hw_tc, &adapter->hw_cc, |
3a6a4eda | 1159 | ktime_to_ns(ktime_get_real())); |
3a6a4eda | 1160 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); |
82083673 | 1161 | |
a9763f3c MR |
1162 | adapter->last_overflow_check = jiffies; |
1163 | ||
1164 | /* Now that the shift has been calculated and the systime | |
82083673 JK |
1165 | * registers reset, (re-)enable the Clock out feature |
1166 | */ | |
a9763f3c MR |
1167 | if (adapter->ptp_setup_sdp) |
1168 | adapter->ptp_setup_sdp(adapter); | |
3a6a4eda JK |
1169 | } |
1170 | ||
1171 | /** | |
63328ada | 1172 | * ixgbe_ptp_create_clock |
49ce9c2c | 1173 | * @adapter: the ixgbe private adapter structure |
3a6a4eda | 1174 | * |
63328ada JK |
1175 | * This function performs setup of the user entry point function table and |
1176 | * initializes the PTP clock device, which is used to access the clock-like | |
a9763f3c MR |
1177 | * features of the PTP core. It will be called by ixgbe_ptp_init, and may |
1178 | * reuse a previously initialized clock (such as during a suspend/resume | |
1179 | * cycle). | |
3a6a4eda | 1180 | */ |
a9763f3c | 1181 | static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter) |
3a6a4eda JK |
1182 | { |
1183 | struct net_device *netdev = adapter->netdev; | |
63328ada JK |
1184 | long err; |
1185 | ||
1186 | /* do nothing if we already have a clock device */ | |
1187 | if (!IS_ERR_OR_NULL(adapter->ptp_clock)) | |
1188 | return 0; | |
3a6a4eda JK |
1189 | |
1190 | switch (adapter->hw.mac.type) { | |
1191 | case ixgbe_mac_X540: | |
ca324099 JK |
1192 | snprintf(adapter->ptp_caps.name, |
1193 | sizeof(adapter->ptp_caps.name), | |
1194 | "%s", netdev->name); | |
681ae1ad JK |
1195 | adapter->ptp_caps.owner = THIS_MODULE; |
1196 | adapter->ptp_caps.max_adj = 250000000; | |
1197 | adapter->ptp_caps.n_alarm = 0; | |
1198 | adapter->ptp_caps.n_ext_ts = 0; | |
1199 | adapter->ptp_caps.n_per_out = 0; | |
1200 | adapter->ptp_caps.pps = 1; | |
a9763f3c | 1201 | adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599; |
681ae1ad | 1202 | adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime; |
91432d18 RC |
1203 | adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime; |
1204 | adapter->ptp_caps.settime64 = ixgbe_ptp_settime; | |
04c8de8e | 1205 | adapter->ptp_caps.enable = ixgbe_ptp_feature_enable; |
a9763f3c | 1206 | adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_x540; |
681ae1ad | 1207 | break; |
3a6a4eda | 1208 | case ixgbe_mac_82599EB: |
ca324099 JK |
1209 | snprintf(adapter->ptp_caps.name, |
1210 | sizeof(adapter->ptp_caps.name), | |
1211 | "%s", netdev->name); | |
3a6a4eda JK |
1212 | adapter->ptp_caps.owner = THIS_MODULE; |
1213 | adapter->ptp_caps.max_adj = 250000000; | |
1214 | adapter->ptp_caps.n_alarm = 0; | |
1215 | adapter->ptp_caps.n_ext_ts = 0; | |
1216 | adapter->ptp_caps.n_per_out = 0; | |
1217 | adapter->ptp_caps.pps = 0; | |
a9763f3c MR |
1218 | adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599; |
1219 | adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime; | |
1220 | adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime; | |
1221 | adapter->ptp_caps.settime64 = ixgbe_ptp_settime; | |
1222 | adapter->ptp_caps.enable = ixgbe_ptp_feature_enable; | |
1223 | break; | |
1224 | case ixgbe_mac_X550: | |
1225 | case ixgbe_mac_X550EM_x: | |
1226 | snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name); | |
1227 | adapter->ptp_caps.owner = THIS_MODULE; | |
1228 | adapter->ptp_caps.max_adj = 30000000; | |
1229 | adapter->ptp_caps.n_alarm = 0; | |
1230 | adapter->ptp_caps.n_ext_ts = 0; | |
1231 | adapter->ptp_caps.n_per_out = 0; | |
1232 | adapter->ptp_caps.pps = 0; | |
1233 | adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_X550; | |
3a6a4eda | 1234 | adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime; |
91432d18 RC |
1235 | adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime; |
1236 | adapter->ptp_caps.settime64 = ixgbe_ptp_settime; | |
04c8de8e | 1237 | adapter->ptp_caps.enable = ixgbe_ptp_feature_enable; |
a9763f3c | 1238 | adapter->ptp_setup_sdp = NULL; |
3a6a4eda JK |
1239 | break; |
1240 | default: | |
1241 | adapter->ptp_clock = NULL; | |
a9763f3c | 1242 | adapter->ptp_setup_sdp = NULL; |
63328ada | 1243 | return -EOPNOTSUPP; |
3a6a4eda JK |
1244 | } |
1245 | ||
1ef76158 RC |
1246 | adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, |
1247 | &adapter->pdev->dev); | |
3a6a4eda | 1248 | if (IS_ERR(adapter->ptp_clock)) { |
63328ada | 1249 | err = PTR_ERR(adapter->ptp_clock); |
3a6a4eda JK |
1250 | adapter->ptp_clock = NULL; |
1251 | e_dev_err("ptp_clock_register failed\n"); | |
63328ada | 1252 | return err; |
3a6a4eda JK |
1253 | } else |
1254 | e_dev_info("registered PHC device on %s\n", netdev->name); | |
1255 | ||
63328ada JK |
1256 | /* set default timestamp mode to disabled here. We do this in |
1257 | * create_clock instead of init, because we don't want to override the | |
1258 | * previous settings during a resume cycle. | |
1259 | */ | |
d6321407 JK |
1260 | adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; |
1261 | adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; | |
63328ada JK |
1262 | |
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | /** | |
1267 | * ixgbe_ptp_init | |
1268 | * @adapter: the ixgbe private adapter structure | |
1269 | * | |
1270 | * This function performs the required steps for enabling PTP | |
1271 | * support. If PTP support has already been loaded it simply calls the | |
1272 | * cyclecounter init routine and exits. | |
1273 | */ | |
1274 | void ixgbe_ptp_init(struct ixgbe_adapter *adapter) | |
1275 | { | |
1276 | /* initialize the spin lock first since we can't control when a user | |
1277 | * will call the entry functions once we have initialized the clock | |
1278 | * device | |
1279 | */ | |
1280 | spin_lock_init(&adapter->tmreg_lock); | |
1281 | ||
1282 | /* obtain a PTP device, or re-use an existing device */ | |
1283 | if (ixgbe_ptp_create_clock(adapter)) | |
1284 | return; | |
1285 | ||
1286 | /* we have a clock so we can initialize work now */ | |
1287 | INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work); | |
1288 | ||
1289 | /* reset the PTP related hardware bits */ | |
1a71ab24 JK |
1290 | ixgbe_ptp_reset(adapter); |
1291 | ||
8fecf67c JK |
1292 | /* enter the IXGBE_PTP_RUNNING state */ |
1293 | set_bit(__IXGBE_PTP_RUNNING, &adapter->state); | |
1a71ab24 | 1294 | |
3a6a4eda JK |
1295 | return; |
1296 | } | |
1297 | ||
1298 | /** | |
9966d1ee JK |
1299 | * ixgbe_ptp_suspend - stop PTP work items |
1300 | * @ adapter: pointer to adapter struct | |
3a6a4eda | 1301 | * |
9966d1ee JK |
1302 | * this function suspends PTP activity, and prevents more PTP work from being |
1303 | * generated, but does not destroy the PTP clock device. | |
3a6a4eda | 1304 | */ |
9966d1ee | 1305 | void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter) |
3a6a4eda | 1306 | { |
8fecf67c JK |
1307 | /* Leave the IXGBE_PTP_RUNNING state. */ |
1308 | if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state)) | |
1309 | return; | |
db0677fa | 1310 | |
a9763f3c MR |
1311 | adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED; |
1312 | if (adapter->ptp_setup_sdp) | |
1313 | adapter->ptp_setup_sdp(adapter); | |
3a6a4eda | 1314 | |
9966d1ee | 1315 | /* ensure that we cancel any pending PTP Tx work item in progress */ |
891dc082 | 1316 | cancel_work_sync(&adapter->ptp_tx_work); |
a9763f3c | 1317 | ixgbe_ptp_clear_tx_timestamp(adapter); |
9966d1ee JK |
1318 | } |
1319 | ||
1320 | /** | |
1321 | * ixgbe_ptp_stop - close the PTP device | |
1322 | * @adapter: pointer to adapter struct | |
1323 | * | |
1324 | * completely destroy the PTP device, should only be called when the device is | |
1325 | * being fully closed. | |
1326 | */ | |
1327 | void ixgbe_ptp_stop(struct ixgbe_adapter *adapter) | |
1328 | { | |
1329 | /* first, suspend PTP activity */ | |
1330 | ixgbe_ptp_suspend(adapter); | |
891dc082 | 1331 | |
9966d1ee | 1332 | /* disable the PTP clock device */ |
3a6a4eda JK |
1333 | if (adapter->ptp_clock) { |
1334 | ptp_clock_unregister(adapter->ptp_clock); | |
1335 | adapter->ptp_clock = NULL; | |
1336 | e_dev_info("removed PHC on %s\n", | |
1337 | adapter->netdev->name); | |
1338 | } | |
1339 | } |