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ixgbe: Make return values more direct
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_phy.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
c97506ab 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
b12babd4 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_phy.h"
35
11afc1b1
PW		 36static void ixgbe_i2c_start(struct ixgbe_hw *hw);
37static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
38static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
39static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
40static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
41static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
42static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
e1befd77 43static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
11afc1b1
PW		 44static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
45static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
46static bool ixgbe_get_i2c_data(u32 *i2cctl);
47static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
9a799d71
AK		 48static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
49static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
88217547 50static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
9a799d71
AK		 51
52/**
c44ade9e 53 * ixgbe_identify_phy_generic - Get physical layer module
9a799d71
AK		 54 * @hw: pointer to hardware structure
55 *
56 * Determines the physical layer module found on the current adapter.
57 **/
c44ade9e 58s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71 59{
9a799d71 60 u32 phy_addr;
037c6d0a 61 u16 ext_ability = 0;
9a799d71 62
c44ade9e
JB		 63 if (hw->phy.type == ixgbe_phy_unknown) {
64 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63d6e1d8 65 hw->phy.mdio.prtad = phy_addr;
6b73e10d 66 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
c44ade9e
JB		 67 ixgbe_get_phy_id(hw);
68 hw->phy.type =
e7cf745b 69 ixgbe_get_phy_type_from_id(hw->phy.id);
037c6d0a
ET		 70
71 if (hw->phy.type == ixgbe_phy_unknown) {
72 hw->phy.ops.read_reg(hw,
73 MDIO_PMA_EXTABLE,
74 MDIO_MMD_PMAPMD,
75 &ext_ability);
76 if (ext_ability &
77 (MDIO_PMA_EXTABLE_10GBT |
78 MDIO_PMA_EXTABLE_1000BT))
79 hw->phy.type =
80 ixgbe_phy_cu_unknown;
81 else
82 hw->phy.type =
83 ixgbe_phy_generic;
84 }
85
e90dd264 86 return 0;
c44ade9e 87 }
9a799d71 88 }
63d6e1d8 89 /* clear value if nothing found */
e90dd264
MR		 90 hw->phy.mdio.prtad = 0;
91 return IXGBE_ERR_PHY_ADDR_INVALID;
9a799d71 92 }
e90dd264 93 return 0;
9a799d71
AK		 94}
95
c97506ab
DS		 96/**
97 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
98 * @hw: pointer to the hardware structure
99 *
100 * This function checks the MMNGC.MNG_VETO bit to see if there are
101 * any constraints on link from manageability. For MAC's that don't
102 * have this bit just return false since the link can not be blocked
103 * via this method.
104 **/
6425f0f3 105bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
c97506ab
DS		 106{
107 u32 mmngc;
108
109 /* If we don't have this bit, it can't be blocking */
110 if (hw->mac.type == ixgbe_mac_82598EB)
111 return false;
112
113 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
114 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
115 hw_dbg(hw, "MNG_VETO bit detected.\n");
116 return true;
117 }
118
119 return false;
120}
121
9a799d71
AK		 122/**
123 * ixgbe_get_phy_id - Get the phy type
124 * @hw: pointer to hardware structure
125 *
126 **/
127static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
128{
129 u32 status;
130 u16 phy_id_high = 0;
131 u16 phy_id_low = 0;
132
6b73e10d 133 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
e7cf745b 134 &phy_id_high);
9a799d71
AK		 135
136 if (status == 0) {
137 hw->phy.id = (u32)(phy_id_high << 16);
6b73e10d 138 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
e7cf745b 139 &phy_id_low);
9a799d71
AK		 140 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
141 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
142 }
9a799d71
AK		 143 return status;
144}
145
146/**
147 * ixgbe_get_phy_type_from_id - Get the phy type
148 * @hw: pointer to hardware structure
149 *
150 **/
151static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
152{
153 enum ixgbe_phy_type phy_type;
154
155 switch (phy_id) {
0befdb3e
JB		 156 case TN1010_PHY_ID:
157 phy_type = ixgbe_phy_tn;
158 break;
2b264909 159 case X540_PHY_ID:
fe15e8e1
DS		 160 phy_type = ixgbe_phy_aq;
161 break;
9a799d71
AK		 162 case QT2022_PHY_ID:
163 phy_type = ixgbe_phy_qt;
164 break;
c4900be0
DS		 165 case ATH_PHY_ID:
166 phy_type = ixgbe_phy_nl;
167 break;
9a799d71
AK		 168 default:
169 phy_type = ixgbe_phy_unknown;
170 break;
171 }
172
173 return phy_type;
174}
175
176/**
c44ade9e 177 * ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71
AK		 178 * @hw: pointer to hardware structure
179 **/
c44ade9e 180s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71 181{
1783575c
ET		 182 u32 i;
183 u16 ctrl = 0;
184 s32 status = 0;
185
186 if (hw->phy.type == ixgbe_phy_unknown)
187 status = ixgbe_identify_phy_generic(hw);
188
189 if (status != 0 || hw->phy.type == ixgbe_phy_none)
e90dd264 190 return status;
1783575c 191
119fc60a
MC		 192 /* Don't reset PHY if it's shut down due to overtemp. */
193 if (!hw->phy.reset_if_overtemp &&
194 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
e90dd264 195 return 0;
119fc60a 196
c97506ab
DS		 197 /* Blocked by MNG FW so bail */
198 if (ixgbe_check_reset_blocked(hw))
e90dd264 199 return 0;
c97506ab 200
9a799d71
AK		 201 /*
202 * Perform soft PHY reset to the PHY_XS.
203 * This will cause a soft reset to the PHY
204 */
1783575c
ET		 205 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
206 MDIO_MMD_PHYXS,
207 MDIO_CTRL1_RESET);
208
209 /*
210 * Poll for reset bit to self-clear indicating reset is complete.
211 * Some PHYs could take up to 3 seconds to complete and need about
212 * 1.7 usec delay after the reset is complete.
213 */
214 for (i = 0; i < 30; i++) {
215 msleep(100);
216 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
217 MDIO_MMD_PHYXS, &ctrl);
218 if (!(ctrl & MDIO_CTRL1_RESET)) {
219 udelay(2);
220 break;
221 }
222 }
223
224 if (ctrl & MDIO_CTRL1_RESET) {
1783575c 225 hw_dbg(hw, "PHY reset polling failed to complete.\n");
e90dd264 226 return IXGBE_ERR_RESET_FAILED;
1783575c
ET		 227 }
228
e90dd264 229 return 0;
9a799d71
AK		 230}
231
3dcc2f41
ET		 232/**
233 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
234 * the SWFW lock
235 * @hw: pointer to hardware structure
236 * @reg_addr: 32 bit address of PHY register to read
237 * @phy_data: Pointer to read data from PHY register
238 **/
239s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
240 u16 *phy_data)
241{
242 u32 i, data, command;
243
244 /* Setup and write the address cycle command */
245 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
246 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
247 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
248 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
249
250 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
251
252 /* Check every 10 usec to see if the address cycle completed.
253 * The MDI Command bit will clear when the operation is
254 * complete
255 */
256 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
257 udelay(10);
258
259 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
260 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
261 break;
262 }
263
264
265 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
266 hw_dbg(hw, "PHY address command did not complete.\n");
267 return IXGBE_ERR_PHY;
268 }
269
270 /* Address cycle complete, setup and write the read
271 * command
272 */
273 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
274 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
275 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
276 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
277
278 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
279
280 /* Check every 10 usec to see if the address cycle
281 * completed. The MDI Command bit will clear when the
282 * operation is complete
283 */
284 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
285 udelay(10);
286
287 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
288 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
289 break;
290 }
291
292 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
293 hw_dbg(hw, "PHY read command didn't complete\n");
294 return IXGBE_ERR_PHY;
295 }
296
297 /* Read operation is complete. Get the data
298 * from MSRWD
299 */
300 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
301 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
302 *phy_data = (u16)(data);
303
304 return 0;
305}
306
9a799d71 307/**
c44ade9e 308 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
3dcc2f41 309 * using the SWFW lock - this function is needed in most cases
9a799d71
AK		 310 * @hw: pointer to hardware structure
311 * @reg_addr: 32 bit address of PHY register to read
312 * @phy_data: Pointer to read data from PHY register
313 **/
c44ade9e 314s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
e7cf745b 315 u32 device_type, u16 *phy_data)
9a799d71 316{
3dcc2f41 317 s32 status;
9a799d71
AK		 318 u16 gssr;
319
320 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
321 gssr = IXGBE_GSSR_PHY1_SM;
322 else
323 gssr = IXGBE_GSSR_PHY0_SM;
324
3dcc2f41
ET		 325 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
326 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
327 phy_data);
328 hw->mac.ops.release_swfw_sync(hw, gssr);
329 } else {
e90dd264 330 return IXGBE_ERR_SWFW_SYNC;
3dcc2f41 331 }
9a799d71 332
3dcc2f41
ET		 333 return status;
334}
335
336/**
337 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
338 * without SWFW lock
339 * @hw: pointer to hardware structure
340 * @reg_addr: 32 bit PHY register to write
341 * @device_type: 5 bit device type
342 * @phy_data: Data to write to the PHY register
343 **/
344s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
345 u32 device_type, u16 phy_data)
346{
347 u32 i, command;
9a799d71 348
3dcc2f41
ET		 349 /* Put the data in the MDI single read and write data register*/
350 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
9a799d71 351
3dcc2f41
ET		 352 /* Setup and write the address cycle command */
353 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
354 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
355 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
356 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71 357
3dcc2f41 358 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
9a799d71 359
3dcc2f41
ET		 360 /*
361 * Check every 10 usec to see if the address cycle completed.
362 * The MDI Command bit will clear when the operation is
363 * complete
364 */
365 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
366 udelay(10);
9a799d71 367
3dcc2f41
ET		 368 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
369 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
370 break;
371 }
9a799d71 372
3dcc2f41
ET		 373 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
374 hw_dbg(hw, "PHY address cmd didn't complete\n");
375 return IXGBE_ERR_PHY;
376 }
9a799d71 377
3dcc2f41
ET		 378 /*
379 * Address cycle complete, setup and write the write
380 * command
381 */
382 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
383 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
384 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
385 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
9a799d71 386
3dcc2f41
ET		 387 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
388
389 /* Check every 10 usec to see if the address cycle
390 * completed. The MDI Command bit will clear when the
391 * operation is complete
392 */
393 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
394 udelay(10);
395
396 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
397 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
398 break;
9a799d71 399 }
c44ade9e 400
3dcc2f41
ET		 401 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
402 hw_dbg(hw, "PHY write cmd didn't complete\n");
403 return IXGBE_ERR_PHY;
404 }
405
406 return 0;
9a799d71
AK		 407}
408
409/**
c44ade9e 410 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
3dcc2f41 411 * using SWFW lock- this function is needed in most cases
9a799d71
AK		 412 * @hw: pointer to hardware structure
413 * @reg_addr: 32 bit PHY register to write
414 * @device_type: 5 bit device type
415 * @phy_data: Data to write to the PHY register
416 **/
c44ade9e 417s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
e7cf745b 418 u32 device_type, u16 phy_data)
9a799d71 419{
3dcc2f41 420 s32 status;
9a799d71
AK		 421 u16 gssr;
422
423 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
424 gssr = IXGBE_GSSR_PHY1_SM;
425 else
426 gssr = IXGBE_GSSR_PHY0_SM;
427
3dcc2f41
ET		 428 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
429 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
430 phy_data);
5e655105 431 hw->mac.ops.release_swfw_sync(hw, gssr);
3dcc2f41 432 } else {
e90dd264 433 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 434 }
435
436 return status;
437}
438
439/**
c44ade9e 440 * ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71
AK		 441 * @hw: pointer to hardware structure
442 *
443 * Restart autonegotiation and PHY and waits for completion.
444 **/
c44ade9e 445s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71 446{
9dda1736 447 s32 status = 0;
9a799d71
AK		 448 u32 time_out;
449 u32 max_time_out = 10;
9dda1736
ET		 450 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
451 bool autoneg = false;
452 ixgbe_link_speed speed;
9a799d71 453
9dda1736
ET		 454 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
455
456 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
457 /* Set or unset auto-negotiation 10G advertisement */
458 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
459 MDIO_MMD_AN,
460 &autoneg_reg);
9a799d71 461
6b73e10d 462 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
9dda1736
ET		 463 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
464 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 465
9dda1736
ET		 466 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
467 MDIO_MMD_AN,
468 autoneg_reg);
469 }
470
471 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
472 /* Set or unset auto-negotiation 1G advertisement */
473 hw->phy.ops.read_reg(hw,
474 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
475 MDIO_MMD_AN,
476 &autoneg_reg);
477
478 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
479 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
480 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
481
482 hw->phy.ops.write_reg(hw,
483 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
484 MDIO_MMD_AN,
485 autoneg_reg);
486 }
487
488 if (speed & IXGBE_LINK_SPEED_100_FULL) {
489 /* Set or unset auto-negotiation 100M advertisement */
490 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
491 MDIO_MMD_AN,
492 &autoneg_reg);
493
a59e8a1a
ET		 494 autoneg_reg &= ~(ADVERTISE_100FULL |
495 ADVERTISE_100HALF);
9dda1736
ET		 496 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
497 autoneg_reg |= ADVERTISE_100FULL;
498
499 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
500 MDIO_MMD_AN,
501 autoneg_reg);
502 }
9a799d71 503
c97506ab
DS		 504 /* Blocked by MNG FW so don't reset PHY */
505 if (ixgbe_check_reset_blocked(hw))
e90dd264 506 return 0;
c97506ab 507
9a799d71 508 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 509 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
510 MDIO_MMD_AN, &autoneg_reg);
9a799d71 511
6b73e10d 512 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
9a799d71 513
9dda1736
ET		 514 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
515 MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 516
517 /* Wait for autonegotiation to finish */
518 for (time_out = 0; time_out < max_time_out; time_out++) {
519 udelay(10);
520 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 521 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
522 MDIO_MMD_AN,
523 &autoneg_reg);
9a799d71 524
6b73e10d
BH		 525 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
526 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
9a799d71
AK		 527 break;
528 }
529 }
530
9dda1736 531 if (time_out == max_time_out) {
c5ffe7e1 532 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out\n");
e90dd264 533 return IXGBE_ERR_LINK_SETUP;
9dda1736 534 }
9a799d71
AK		 535
536 return status;
537}
538
539/**
c44ade9e 540 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71
AK		 541 * @hw: pointer to hardware structure
542 * @speed: new link speed
9a799d71 543 **/
c44ade9e 544s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
e7cf745b
JK		 545 ixgbe_link_speed speed,
546 bool autoneg_wait_to_complete)
9a799d71 547{
c44ade9e 548
9a799d71
AK		 549 /*
550 * Clear autoneg_advertised and set new values based on input link
551 * speed.
552 */
553 hw->phy.autoneg_advertised = 0;
554
555 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
556 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e 557
9a799d71
AK		 558 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
559 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
560
9dda1736
ET		 561 if (speed & IXGBE_LINK_SPEED_100_FULL)
562 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
563
9a799d71 564 /* Setup link based on the new speed settings */
c44ade9e 565 hw->phy.ops.setup_link(hw);
9a799d71
AK		 566
567 return 0;
568}
c44ade9e 569
a391f1d5
DS		 570/**
571 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
572 * @hw: pointer to hardware structure
573 * @speed: pointer to link speed
574 * @autoneg: boolean auto-negotiation value
575 *
576 * Determines the link capabilities by reading the AUTOC register.
577 */
578s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
e7cf745b
JK		 579 ixgbe_link_speed *speed,
580 bool *autoneg)
a391f1d5 581{
e90dd264 582 s32 status;
a391f1d5
DS		 583 u16 speed_ability;
584
585 *speed = 0;
586 *autoneg = true;
587
588 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
e7cf745b 589 &speed_ability);
a391f1d5
DS		 590
591 if (status == 0) {
592 if (speed_ability & MDIO_SPEED_10G)
593 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
594 if (speed_ability & MDIO_PMA_SPEED_1000)
595 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
596 if (speed_ability & MDIO_PMA_SPEED_100)
597 *speed |= IXGBE_LINK_SPEED_100_FULL;
598 }
599
600 return status;
601}
602
9dda1736
ET		 603/**
604 * ixgbe_check_phy_link_tnx - Determine link and speed status
605 * @hw: pointer to hardware structure
606 *
607 * Reads the VS1 register to determine if link is up and the current speed for
608 * the PHY.
609 **/
610s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
611 bool *link_up)
612{
e90dd264 613 s32 status;
9dda1736
ET		 614 u32 time_out;
615 u32 max_time_out = 10;
616 u16 phy_link = 0;
617 u16 phy_speed = 0;
618 u16 phy_data = 0;
619
620 /* Initialize speed and link to default case */
621 *link_up = false;
622 *speed = IXGBE_LINK_SPEED_10GB_FULL;
623
624 /*
625 * Check current speed and link status of the PHY register.
626 * This is a vendor specific register and may have to
627 * be changed for other copper PHYs.
628 */
629 for (time_out = 0; time_out < max_time_out; time_out++) {
630 udelay(10);
631 status = hw->phy.ops.read_reg(hw,
632 MDIO_STAT1,
633 MDIO_MMD_VEND1,
634 &phy_data);
635 phy_link = phy_data &
636 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
637 phy_speed = phy_data &
638 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
639 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
640 *link_up = true;
641 if (phy_speed ==
642 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
643 *speed = IXGBE_LINK_SPEED_1GB_FULL;
644 break;
645 }
646 }
647
648 return status;
649}
650
651/**
652 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
653 * @hw: pointer to hardware structure
654 *
655 * Restart autonegotiation and PHY and waits for completion.
656 **/
657s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
658{
e90dd264 659 s32 status;
9dda1736
ET		 660 u32 time_out;
661 u32 max_time_out = 10;
662 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
663 bool autoneg = false;
664 ixgbe_link_speed speed;
665
666 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
667
668 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
669 /* Set or unset auto-negotiation 10G advertisement */
670 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
671 MDIO_MMD_AN,
672 &autoneg_reg);
673
674 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
675 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
676 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
677
678 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
679 MDIO_MMD_AN,
680 autoneg_reg);
681 }
682
683 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
684 /* Set or unset auto-negotiation 1G advertisement */
685 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
686 MDIO_MMD_AN,
687 &autoneg_reg);
688
689 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
690 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
691 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
692
693 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
694 MDIO_MMD_AN,
695 autoneg_reg);
696 }
697
698 if (speed & IXGBE_LINK_SPEED_100_FULL) {
699 /* Set or unset auto-negotiation 100M advertisement */
700 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
701 MDIO_MMD_AN,
702 &autoneg_reg);
703
50c022e7
ET		 704 autoneg_reg &= ~(ADVERTISE_100FULL |
705 ADVERTISE_100HALF);
9dda1736
ET		 706 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
707 autoneg_reg |= ADVERTISE_100FULL;
708
709 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
710 MDIO_MMD_AN,
711 autoneg_reg);
712 }
713
c97506ab
DS		 714 /* Blocked by MNG FW so don't reset PHY */
715 if (ixgbe_check_reset_blocked(hw))
e90dd264 716 return 0;
c97506ab 717
9dda1736
ET		 718 /* Restart PHY autonegotiation and wait for completion */
719 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
720 MDIO_MMD_AN, &autoneg_reg);
721
722 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
723
724 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
725 MDIO_MMD_AN, autoneg_reg);
726
727 /* Wait for autonegotiation to finish */
728 for (time_out = 0; time_out < max_time_out; time_out++) {
729 udelay(10);
730 /* Restart PHY autonegotiation and wait for completion */
731 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
732 MDIO_MMD_AN,
733 &autoneg_reg);
734
735 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
736 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
737 break;
738 }
739
740 if (time_out == max_time_out) {
c5ffe7e1 741 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out\n");
e90dd264 742 return IXGBE_ERR_LINK_SETUP;
9dda1736
ET		 743 }
744
745 return status;
746}
747
748/**
749 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
750 * @hw: pointer to hardware structure
751 * @firmware_version: pointer to the PHY Firmware Version
752 **/
753s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
754 u16 *firmware_version)
755{
e90dd264 756 s32 status;
9dda1736
ET		 757
758 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
759 MDIO_MMD_VEND1,
760 firmware_version);
761
762 return status;
763}
764
765/**
766 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
767 * @hw: pointer to hardware structure
768 * @firmware_version: pointer to the PHY Firmware Version
769 **/
770s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
771 u16 *firmware_version)
772{
e90dd264 773 s32 status;
9dda1736
ET		 774
775 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
776 MDIO_MMD_VEND1,
777 firmware_version);
778
779 return status;
780}
781
c4900be0
DS		 782/**
783 * ixgbe_reset_phy_nl - Performs a PHY reset
784 * @hw: pointer to hardware structure
785 **/
786s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
787{
788 u16 phy_offset, control, eword, edata, block_crc;
789 bool end_data = false;
790 u16 list_offset, data_offset;
791 u16 phy_data = 0;
e90dd264 792 s32 ret_val;
c4900be0
DS		 793 u32 i;
794
c97506ab
DS		 795 /* Blocked by MNG FW so bail */
796 if (ixgbe_check_reset_blocked(hw))
e90dd264 797 return 0;
c97506ab 798
6b73e10d 799 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
c4900be0
DS		 800
801 /* reset the PHY and poll for completion */
6b73e10d 802 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
e7cf745b 803 (phy_data | MDIO_CTRL1_RESET));
c4900be0
DS		 804
805 for (i = 0; i < 100; i++) {
6b73e10d 806 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
e7cf745b 807 &phy_data);
6b73e10d 808 if ((phy_data & MDIO_CTRL1_RESET) == 0)
c4900be0 809 break;
032b4325 810 usleep_range(10000, 20000);
c4900be0
DS		 811 }
812
6b73e10d 813 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
c4900be0 814 hw_dbg(hw, "PHY reset did not complete.\n");
e90dd264 815 return IXGBE_ERR_PHY;
c4900be0
DS		 816 }
817
818 /* Get init offsets */
819 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
e7cf745b 820 &data_offset);
e90dd264
MR		 821 if (ret_val)
822 return ret_val;
c4900be0
DS		 823
824 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
825 data_offset++;
826 while (!end_data) {
827 /*
828 * Read control word from PHY init contents offset
829 */
830 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
be0c27b4
MR		 831 if (ret_val)
832 goto err_eeprom;
c4900be0 833 control = (eword & IXGBE_CONTROL_MASK_NL) >>
e7cf745b 834 IXGBE_CONTROL_SHIFT_NL;
c4900be0
DS		 835 edata = eword & IXGBE_DATA_MASK_NL;
836 switch (control) {
837 case IXGBE_DELAY_NL:
838 data_offset++;
839 hw_dbg(hw, "DELAY: %d MS\n", edata);
032b4325 840 usleep_range(edata * 1000, edata * 2000);
c4900be0
DS		 841 break;
842 case IXGBE_DATA_NL:
d6dbee86 843 hw_dbg(hw, "DATA:\n");
c4900be0 844 data_offset++;
be0c27b4
MR		 845 ret_val = hw->eeprom.ops.read(hw, data_offset++,
846 &phy_offset);
847 if (ret_val)
848 goto err_eeprom;
c4900be0 849 for (i = 0; i < edata; i++) {
be0c27b4
MR		 850 ret_val = hw->eeprom.ops.read(hw, data_offset,
851 &eword);
852 if (ret_val)
853 goto err_eeprom;
c4900be0 854 hw->phy.ops.write_reg(hw, phy_offset,
e7cf745b 855 MDIO_MMD_PMAPMD, eword);
c4900be0
DS		 856 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
857 phy_offset);
858 data_offset++;
859 phy_offset++;
860 }
861 break;
862 case IXGBE_CONTROL_NL:
863 data_offset++;
d6dbee86 864 hw_dbg(hw, "CONTROL:\n");
c4900be0
DS		 865 if (edata == IXGBE_CONTROL_EOL_NL) {
866 hw_dbg(hw, "EOL\n");
867 end_data = true;
868 } else if (edata == IXGBE_CONTROL_SOL_NL) {
869 hw_dbg(hw, "SOL\n");
870 } else {
871 hw_dbg(hw, "Bad control value\n");
e90dd264 872 return IXGBE_ERR_PHY;
c4900be0
DS		 873 }
874 break;
875 default:
876 hw_dbg(hw, "Bad control type\n");
e90dd264 877 return IXGBE_ERR_PHY;
c4900be0
DS		 878 }
879 }
880
c4900be0 881 return ret_val;
be0c27b4
MR		 882
883err_eeprom:
884 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
885 return IXGBE_ERR_PHY;
c4900be0
DS		 886}
887
888/**
8f58332b 889 * ixgbe_identify_module_generic - Identifies module type
c4900be0
DS		 890 * @hw: pointer to hardware structure
891 *
8f58332b
DS		 892 * Determines HW type and calls appropriate function.
893 **/
894s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
895{
8f58332b
DS		 896 switch (hw->mac.ops.get_media_type(hw)) {
897 case ixgbe_media_type_fiber:
e90dd264 898 return ixgbe_identify_sfp_module_generic(hw);
8f58332b 899 case ixgbe_media_type_fiber_qsfp:
e90dd264 900 return ixgbe_identify_qsfp_module_generic(hw);
8f58332b
DS		 901 default:
902 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
e90dd264 903 return IXGBE_ERR_SFP_NOT_PRESENT;
8f58332b
DS		 904 }
905
e90dd264 906 return IXGBE_ERR_SFP_NOT_PRESENT;
8f58332b
DS		 907}
908
909/**
910 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
911 * @hw: pointer to hardware structure
e90dd264 912 *
76d97dd4 913 * Searches for and identifies the SFP module and assigns appropriate PHY type.
c4900be0
DS		 914 **/
915s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
916{
8ef78adc 917 struct ixgbe_adapter *adapter = hw->back;
e90dd264 918 s32 status;
c4900be0 919 u32 vendor_oui = 0;
553b4497 920 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
c4900be0
DS		 921 u8 identifier = 0;
922 u8 comp_codes_1g = 0;
923 u8 comp_codes_10g = 0;
11afc1b1 924 u8 oui_bytes[3] = {0, 0, 0};
537d58a0 925 u8 cable_tech = 0;
ea0a04df 926 u8 cable_spec = 0;
11afc1b1 927 u16 enforce_sfp = 0;
c4900be0 928
8ca783ab
DS		 929 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
930 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
e90dd264 931 return IXGBE_ERR_SFP_NOT_PRESENT;
8ca783ab
DS		 932 }
933
76d97dd4
ET		 934 status = hw->phy.ops.read_i2c_eeprom(hw,
935 IXGBE_SFF_IDENTIFIER,
51d0420b 936 &identifier);
c4900be0 937
e90dd264 938 if (status)
76d97dd4 939 goto err_read_i2c_eeprom;
c4900be0 940
76d97dd4
ET		 941 /* LAN ID is needed for sfp_type determination */
942 hw->mac.ops.set_lan_id(hw);
943
944 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
945 hw->phy.type = ixgbe_phy_sfp_unsupported;
e90dd264
MR		 946 return IXGBE_ERR_SFP_NOT_SUPPORTED;
947 }
948 status = hw->phy.ops.read_i2c_eeprom(hw,
949 IXGBE_SFF_1GBE_COMP_CODES,
950 &comp_codes_1g);
76d97dd4 951
e90dd264
MR		 952 if (status)
953 goto err_read_i2c_eeprom;
76d97dd4 954
e90dd264
MR		 955 status = hw->phy.ops.read_i2c_eeprom(hw,
956 IXGBE_SFF_10GBE_COMP_CODES,
957 &comp_codes_10g);
76d97dd4 958
e90dd264
MR		 959 if (status)
960 goto err_read_i2c_eeprom;
961 status = hw->phy.ops.read_i2c_eeprom(hw,
962 IXGBE_SFF_CABLE_TECHNOLOGY,
963 &cable_tech);
76d97dd4 964
e90dd264
MR		 965 if (status)
966 goto err_read_i2c_eeprom;
76d97dd4 967
e90dd264
MR		 968 /* ID Module
969 * =========
970 * 0 SFP_DA_CU
971 * 1 SFP_SR
972 * 2 SFP_LR
973 * 3 SFP_DA_CORE0 - 82599-specific
974 * 4 SFP_DA_CORE1 - 82599-specific
975 * 5 SFP_SR/LR_CORE0 - 82599-specific
976 * 6 SFP_SR/LR_CORE1 - 82599-specific
977 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
978 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
979 * 9 SFP_1g_cu_CORE0 - 82599-specific
980 * 10 SFP_1g_cu_CORE1 - 82599-specific
981 * 11 SFP_1g_sx_CORE0 - 82599-specific
982 * 12 SFP_1g_sx_CORE1 - 82599-specific
983 */
984 if (hw->mac.type == ixgbe_mac_82598EB) {
985 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
986 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
987 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
988 hw->phy.sfp_type = ixgbe_sfp_type_sr;
989 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
990 hw->phy.sfp_type = ixgbe_sfp_type_lr;
991 else
992 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
993 } else if (hw->mac.type == ixgbe_mac_82599EB) {
994 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
995 if (hw->bus.lan_id == 0)
996 hw->phy.sfp_type =
997 ixgbe_sfp_type_da_cu_core0;
11afc1b1 998 else
e90dd264
MR		 999 hw->phy.sfp_type =
1000 ixgbe_sfp_type_da_cu_core1;
1001 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1002 hw->phy.ops.read_i2c_eeprom(
1003 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1004 &cable_spec);
1005 if (cable_spec &
1006 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
345be204
DS		 1007 if (hw->bus.lan_id == 0)
1008 hw->phy.sfp_type =
e90dd264 1009 ixgbe_sfp_type_da_act_lmt_core0;
345be204
DS		 1010 else
1011 hw->phy.sfp_type =
e90dd264 1012 ixgbe_sfp_type_da_act_lmt_core1;
76d97dd4 1013 } else {
e90dd264
MR		 1014 hw->phy.sfp_type =
1015 ixgbe_sfp_type_unknown;
76d97dd4 1016 }
e90dd264
MR		 1017 } else if (comp_codes_10g &
1018 (IXGBE_SFF_10GBASESR_CAPABLE |
1019 IXGBE_SFF_10GBASELR_CAPABLE)) {
1020 if (hw->bus.lan_id == 0)
1021 hw->phy.sfp_type =
1022 ixgbe_sfp_type_srlr_core0;
1023 else
1024 hw->phy.sfp_type =
1025 ixgbe_sfp_type_srlr_core1;
1026 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1027 if (hw->bus.lan_id == 0)
1028 hw->phy.sfp_type =
1029 ixgbe_sfp_type_1g_cu_core0;
1030 else
1031 hw->phy.sfp_type =
1032 ixgbe_sfp_type_1g_cu_core1;
1033 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1034 if (hw->bus.lan_id == 0)
1035 hw->phy.sfp_type =
1036 ixgbe_sfp_type_1g_sx_core0;
1037 else
1038 hw->phy.sfp_type =
1039 ixgbe_sfp_type_1g_sx_core1;
1040 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1041 if (hw->bus.lan_id == 0)
1042 hw->phy.sfp_type =
1043 ixgbe_sfp_type_1g_lx_core0;
1044 else
1045 hw->phy.sfp_type =
1046 ixgbe_sfp_type_1g_lx_core1;
1047 } else {
1048 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
11afc1b1 1049 }
e90dd264 1050 }
c4900be0 1051
e90dd264
MR		 1052 if (hw->phy.sfp_type != stored_sfp_type)
1053 hw->phy.sfp_setup_needed = true;
fa466e91 1054
e90dd264
MR		 1055 /* Determine if the SFP+ PHY is dual speed or not. */
1056 hw->phy.multispeed_fiber = false;
1057 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1058 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1059 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1060 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1061 hw->phy.multispeed_fiber = true;
fa466e91 1062
e90dd264
MR		 1063 /* Determine PHY vendor */
1064 if (hw->phy.type != ixgbe_phy_nl) {
1065 hw->phy.id = identifier;
1066 status = hw->phy.ops.read_i2c_eeprom(hw,
1067 IXGBE_SFF_VENDOR_OUI_BYTE0,
1068 &oui_bytes[0]);
fa466e91 1069
e90dd264
MR		 1070 if (status != 0)
1071 goto err_read_i2c_eeprom;
11afc1b1 1072
e90dd264
MR		 1073 status = hw->phy.ops.read_i2c_eeprom(hw,
1074 IXGBE_SFF_VENDOR_OUI_BYTE1,
1075 &oui_bytes[1]);
1076
1077 if (status != 0)
1078 goto err_read_i2c_eeprom;
1079
1080 status = hw->phy.ops.read_i2c_eeprom(hw,
1081 IXGBE_SFF_VENDOR_OUI_BYTE2,
1082 &oui_bytes[2]);
1083
1084 if (status != 0)
1085 goto err_read_i2c_eeprom;
1086
1087 vendor_oui =
1088 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1089 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1090 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1091
1092 switch (vendor_oui) {
1093 case IXGBE_SFF_VENDOR_OUI_TYCO:
1094 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1095 hw->phy.type =
1096 ixgbe_phy_sfp_passive_tyco;
1097 break;
1098 case IXGBE_SFF_VENDOR_OUI_FTL:
1099 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1100 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1101 else
1102 hw->phy.type = ixgbe_phy_sfp_ftl;
1103 break;
1104 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1105 hw->phy.type = ixgbe_phy_sfp_avago;
1106 break;
1107 case IXGBE_SFF_VENDOR_OUI_INTEL:
1108 hw->phy.type = ixgbe_phy_sfp_intel;
1109 break;
1110 default:
1111 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1112 hw->phy.type =
1113 ixgbe_phy_sfp_passive_unknown;
1114 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1115 hw->phy.type =
1116 ixgbe_phy_sfp_active_unknown;
1117 else
1118 hw->phy.type = ixgbe_phy_sfp_unknown;
1119 break;
11afc1b1 1120 }
c4900be0
DS		 1121 }
1122
e90dd264
MR		 1123 /* Allow any DA cable vendor */
1124 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1125 IXGBE_SFF_DA_ACTIVE_CABLE))
1126 return 0;
1127
1128 /* Verify supported 1G SFP modules */
1129 if (comp_codes_10g == 0 &&
1130 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1131 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1132 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1133 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1134 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1135 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1136 hw->phy.type = ixgbe_phy_sfp_unsupported;
1137 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1138 }
1139
1140 /* Anything else 82598-based is supported */
1141 if (hw->mac.type == ixgbe_mac_82598EB)
1142 return 0;
1143
1144 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1145 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1146 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1147 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1148 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1149 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1150 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1151 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1152 /* Make sure we're a supported PHY type */
1153 if (hw->phy.type == ixgbe_phy_sfp_intel)
1154 return 0;
1155 if (hw->allow_unsupported_sfp) {
1156 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1157 return 0;
1158 }
1159 hw_dbg(hw, "SFP+ module not supported\n");
1160 hw->phy.type = ixgbe_phy_sfp_unsupported;
1161 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1162 }
1163 return 0;
76d97dd4
ET		 1164
1165err_read_i2c_eeprom:
1166 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1167 if (hw->phy.type != ixgbe_phy_nl) {
1168 hw->phy.id = 0;
1169 hw->phy.type = ixgbe_phy_unknown;
1170 }
1171 return IXGBE_ERR_SFP_NOT_PRESENT;
c4900be0
DS		 1172}
1173
8f58332b
DS		 1174/**
1175 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1176 * @hw: pointer to hardware structure
1177 *
1178 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1179 **/
88217547 1180static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
8f58332b
DS		 1181{
1182 struct ixgbe_adapter *adapter = hw->back;
e90dd264 1183 s32 status;
8f58332b
DS		 1184 u32 vendor_oui = 0;
1185 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1186 u8 identifier = 0;
1187 u8 comp_codes_1g = 0;
1188 u8 comp_codes_10g = 0;
1189 u8 oui_bytes[3] = {0, 0, 0};
1190 u16 enforce_sfp = 0;
9a84fea2
ET		 1191 u8 connector = 0;
1192 u8 cable_length = 0;
1193 u8 device_tech = 0;
1194 bool active_cable = false;
8f58332b
DS		 1195
1196 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1197 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
e90dd264 1198 return IXGBE_ERR_SFP_NOT_PRESENT;
8f58332b
DS		 1199 }
1200
1201 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1202 &identifier);
1203
1204 if (status != 0)
1205 goto err_read_i2c_eeprom;
1206
1207 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1208 hw->phy.type = ixgbe_phy_sfp_unsupported;
e90dd264 1209 return IXGBE_ERR_SFP_NOT_SUPPORTED;
8f58332b
DS		 1210 }
1211
1212 hw->phy.id = identifier;
1213
1214 /* LAN ID is needed for sfp_type determination */
1215 hw->mac.ops.set_lan_id(hw);
1216
1217 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1218 &comp_codes_10g);
1219
1220 if (status != 0)
1221 goto err_read_i2c_eeprom;
1222
61aaf9e8
ET		 1223 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1224 &comp_codes_1g);
1225
1226 if (status != 0)
1227 goto err_read_i2c_eeprom;
1228
8f58332b
DS		 1229 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1230 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1231 if (hw->bus.lan_id == 0)
1232 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1233 else
1234 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
8f58332b
DS		 1235 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1236 IXGBE_SFF_10GBASELR_CAPABLE)) {
1237 if (hw->bus.lan_id == 0)
1238 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1239 else
1240 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1241 } else {
9a84fea2
ET		 1242 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1243 active_cable = true;
1244
1245 if (!active_cable) {
1246 /* check for active DA cables that pre-date
1247 * SFF-8436 v3.6
1248 */
1249 hw->phy.ops.read_i2c_eeprom(hw,
1250 IXGBE_SFF_QSFP_CONNECTOR,
1251 &connector);
1252
1253 hw->phy.ops.read_i2c_eeprom(hw,
1254 IXGBE_SFF_QSFP_CABLE_LENGTH,
1255 &cable_length);
1256
1257 hw->phy.ops.read_i2c_eeprom(hw,
1258 IXGBE_SFF_QSFP_DEVICE_TECH,
1259 &device_tech);
1260
1261 if ((connector ==
1262 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1263 (cable_length > 0) &&
1264 ((device_tech >> 4) ==
1265 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1266 active_cable = true;
1267 }
1268
1269 if (active_cable) {
1270 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1271 if (hw->bus.lan_id == 0)
1272 hw->phy.sfp_type =
1273 ixgbe_sfp_type_da_act_lmt_core0;
1274 else
1275 hw->phy.sfp_type =
1276 ixgbe_sfp_type_da_act_lmt_core1;
1277 } else {
1278 /* unsupported module type */
1279 hw->phy.type = ixgbe_phy_sfp_unsupported;
e90dd264 1280 return IXGBE_ERR_SFP_NOT_SUPPORTED;
9a84fea2 1281 }
8f58332b
DS		 1282 }
1283
1284 if (hw->phy.sfp_type != stored_sfp_type)
1285 hw->phy.sfp_setup_needed = true;
1286
1287 /* Determine if the QSFP+ PHY is dual speed or not. */
1288 hw->phy.multispeed_fiber = false;
1289 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1290 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1291 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1292 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1293 hw->phy.multispeed_fiber = true;
1294
1295 /* Determine PHY vendor for optical modules */
1296 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1297 IXGBE_SFF_10GBASELR_CAPABLE)) {
1298 status = hw->phy.ops.read_i2c_eeprom(hw,
1299 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1300 &oui_bytes[0]);
1301
1302 if (status != 0)
1303 goto err_read_i2c_eeprom;
1304
1305 status = hw->phy.ops.read_i2c_eeprom(hw,
1306 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1307 &oui_bytes[1]);
1308
1309 if (status != 0)
1310 goto err_read_i2c_eeprom;
1311
1312 status = hw->phy.ops.read_i2c_eeprom(hw,
1313 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1314 &oui_bytes[2]);
1315
1316 if (status != 0)
1317 goto err_read_i2c_eeprom;
1318
1319 vendor_oui =
1320 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1321 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1322 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1323
1324 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1325 hw->phy.type = ixgbe_phy_qsfp_intel;
1326 else
1327 hw->phy.type = ixgbe_phy_qsfp_unknown;
1328
1329 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1330 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1331 /* Make sure we're a supported PHY type */
e90dd264
MR		 1332 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1333 return 0;
1334 if (hw->allow_unsupported_sfp) {
1335 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1336 return 0;
8f58332b 1337 }
e90dd264
MR		 1338 hw_dbg(hw, "QSFP module not supported\n");
1339 hw->phy.type = ixgbe_phy_sfp_unsupported;
1340 return IXGBE_ERR_SFP_NOT_SUPPORTED;
8f58332b 1341 }
e90dd264 1342 return 0;
8f58332b 1343 }
e90dd264 1344 return 0;
8f58332b
DS		 1345
1346err_read_i2c_eeprom:
1347 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1348 hw->phy.id = 0;
1349 hw->phy.type = ixgbe_phy_unknown;
1350
1351 return IXGBE_ERR_SFP_NOT_PRESENT;
1352}
1353
c4900be0 1354/**
76d97dd4 1355 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
c4900be0
DS		 1356 * @hw: pointer to hardware structure
1357 * @list_offset: offset to the SFP ID list
1358 * @data_offset: offset to the SFP data block
75f19c3c
ET		 1359 *
1360 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1361 * so it returns the offsets to the phy init sequence block.
c4900be0
DS		 1362 **/
1363s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
e7cf745b
JK		 1364 u16 *list_offset,
1365 u16 *data_offset)
c4900be0
DS		 1366{
1367 u16 sfp_id;
cb836a97 1368 u16 sfp_type = hw->phy.sfp_type;
c4900be0
DS		 1369
1370 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1371 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1372
1373 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1374 return IXGBE_ERR_SFP_NOT_PRESENT;
1375
1376 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1377 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1378 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1379
cb836a97
DS		 1380 /*
1381 * Limiting active cables and 1G Phys must be initialized as
1382 * SR modules
1383 */
1384 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
345be204 1385 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
a49fda3e
JK		 1386 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1387 sfp_type == ixgbe_sfp_type_1g_sx_core0)
cb836a97
DS		 1388 sfp_type = ixgbe_sfp_type_srlr_core0;
1389 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
345be204 1390 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
a49fda3e
JK		 1391 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1392 sfp_type == ixgbe_sfp_type_1g_sx_core1)
cb836a97
DS		 1393 sfp_type = ixgbe_sfp_type_srlr_core1;
1394
c4900be0 1395 /* Read offset to PHY init contents */
be0c27b4
MR		 1396 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1397 hw_err(hw, "eeprom read at %d failed\n",
1398 IXGBE_PHY_INIT_OFFSET_NL);
1399 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1400 }
c4900be0
DS		 1401
1402 if ((!*list_offset) || (*list_offset == 0xFFFF))
11afc1b1 1403 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
c4900be0
DS		 1404
1405 /* Shift offset to first ID word */
1406 (*list_offset)++;
1407
1408 /*
1409 * Find the matching SFP ID in the EEPROM
1410 * and program the init sequence
1411 */
be0c27b4
MR		 1412 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1413 goto err_phy;
c4900be0
DS		 1414
1415 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
cb836a97 1416 if (sfp_id == sfp_type) {
c4900be0 1417 (*list_offset)++;
be0c27b4
MR		 1418 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1419 goto err_phy;
c4900be0
DS		 1420 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1421 hw_dbg(hw, "SFP+ module not supported\n");
1422 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1423 } else {
1424 break;
1425 }
1426 } else {
1427 (*list_offset) += 2;
1428 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
be0c27b4 1429 goto err_phy;
c4900be0
DS		 1430 }
1431 }
1432
1433 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1434 hw_dbg(hw, "No matching SFP+ module found\n");
1435 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1436 }
1437
1438 return 0;
be0c27b4
MR		 1439
1440err_phy:
1441 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1442 return IXGBE_ERR_PHY;
c4900be0
DS		 1443}
1444
11afc1b1
PW		 1445/**
1446 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1447 * @hw: pointer to hardware structure
1448 * @byte_offset: EEPROM byte offset to read
1449 * @eeprom_data: value read
1450 *
1451 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1452 **/
1453s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
e7cf745b 1454 u8 *eeprom_data)
11afc1b1
PW		 1455{
1456 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
e7cf745b
JK		 1457 IXGBE_I2C_EEPROM_DEV_ADDR,
1458 eeprom_data);
11afc1b1
PW		 1459}
1460
07ce870b
ET		 1461/**
1462 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1463 * @hw: pointer to hardware structure
1464 * @byte_offset: byte offset at address 0xA2
1465 * @eeprom_data: value read
1466 *
1467 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1468 **/
1469s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1470 u8 *sff8472_data)
1471{
1472 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1473 IXGBE_I2C_EEPROM_DEV_ADDR2,
1474 sff8472_data);
1475}
1476
11afc1b1
PW		 1477/**
1478 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1479 * @hw: pointer to hardware structure
1480 * @byte_offset: EEPROM byte offset to write
1481 * @eeprom_data: value to write
1482 *
1483 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1484 **/
1485s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
e7cf745b 1486 u8 eeprom_data)
11afc1b1
PW		 1487{
1488 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
e7cf745b
JK		 1489 IXGBE_I2C_EEPROM_DEV_ADDR,
1490 eeprom_data);
11afc1b1
PW		 1491}
1492
1493/**
1494 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1495 * @hw: pointer to hardware structure
1496 * @byte_offset: byte offset to read
1497 * @data: value read
1498 *
1499 * Performs byte read operation to SFP module's EEPROM over I2C interface at
3fbaa3ac 1500 * a specified device address.
11afc1b1
PW		 1501 **/
1502s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
e7cf745b 1503 u8 dev_addr, u8 *data)
11afc1b1 1504{
e90dd264 1505 s32 status;
75f19c3c 1506 u32 max_retry = 10;
11afc1b1 1507 u32 retry = 0;
75f19c3c 1508 u16 swfw_mask = 0;
3db1cd5c 1509 bool nack = true;
3fbaa3ac 1510 *data = 0;
11afc1b1 1511
75f19c3c
ET		 1512 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1513 swfw_mask = IXGBE_GSSR_PHY1_SM;
1514 else
1515 swfw_mask = IXGBE_GSSR_PHY0_SM;
1516
11afc1b1 1517 do {
e90dd264
MR		 1518 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1519 return IXGBE_ERR_SWFW_SYNC;
75f19c3c 1520
11afc1b1
PW		 1521 ixgbe_i2c_start(hw);
1522
1523 /* Device Address and write indication */
1524 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1525 if (status != 0)
1526 goto fail;
1527
1528 status = ixgbe_get_i2c_ack(hw);
1529 if (status != 0)
1530 goto fail;
1531
1532 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1533 if (status != 0)
1534 goto fail;
1535
1536 status = ixgbe_get_i2c_ack(hw);
1537 if (status != 0)
1538 goto fail;
1539
1540 ixgbe_i2c_start(hw);
1541
1542 /* Device Address and read indication */
1543 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1544 if (status != 0)
1545 goto fail;
1546
1547 status = ixgbe_get_i2c_ack(hw);
1548 if (status != 0)
1549 goto fail;
1550
1551 status = ixgbe_clock_in_i2c_byte(hw, data);
1552 if (status != 0)
1553 goto fail;
1554
1555 status = ixgbe_clock_out_i2c_bit(hw, nack);
1556 if (status != 0)
1557 goto fail;
1558
1559 ixgbe_i2c_stop(hw);
1560 break;
1561
1562fail:
d0310dc4 1563 ixgbe_i2c_bus_clear(hw);
6d980c3e 1564 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c 1565 msleep(100);
11afc1b1
PW		 1566 retry++;
1567 if (retry < max_retry)
1568 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1569 else
1570 hw_dbg(hw, "I2C byte read error.\n");
1571
1572 } while (retry < max_retry);
1573
6d980c3e 1574 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c 1575
11afc1b1
PW		 1576 return status;
1577}
1578
1579/**
1580 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1581 * @hw: pointer to hardware structure
1582 * @byte_offset: byte offset to write
1583 * @data: value to write
1584 *
1585 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1586 * a specified device address.
1587 **/
1588s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
e7cf745b 1589 u8 dev_addr, u8 data)
11afc1b1 1590{
e90dd264 1591 s32 status;
11afc1b1
PW		 1592 u32 max_retry = 1;
1593 u32 retry = 0;
75f19c3c
ET		 1594 u16 swfw_mask = 0;
1595
1596 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1597 swfw_mask = IXGBE_GSSR_PHY1_SM;
1598 else
1599 swfw_mask = IXGBE_GSSR_PHY0_SM;
1600
e90dd264
MR		 1601 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1602 return IXGBE_ERR_SWFW_SYNC;
11afc1b1
PW		 1603
1604 do {
1605 ixgbe_i2c_start(hw);
1606
1607 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1608 if (status != 0)
1609 goto fail;
1610
1611 status = ixgbe_get_i2c_ack(hw);
1612 if (status != 0)
1613 goto fail;
1614
1615 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1616 if (status != 0)
1617 goto fail;
1618
1619 status = ixgbe_get_i2c_ack(hw);
1620 if (status != 0)
1621 goto fail;
1622
1623 status = ixgbe_clock_out_i2c_byte(hw, data);
1624 if (status != 0)
1625 goto fail;
1626
1627 status = ixgbe_get_i2c_ack(hw);
1628 if (status != 0)
1629 goto fail;
1630
1631 ixgbe_i2c_stop(hw);
1632 break;
1633
1634fail:
1635 ixgbe_i2c_bus_clear(hw);
1636 retry++;
1637 if (retry < max_retry)
1638 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1639 else
1640 hw_dbg(hw, "I2C byte write error.\n");
1641 } while (retry < max_retry);
1642
6d980c3e 1643 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c 1644
11afc1b1
PW		 1645 return status;
1646}
1647
1648/**
1649 * ixgbe_i2c_start - Sets I2C start condition
1650 * @hw: pointer to hardware structure
1651 *
1652 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1653 **/
1654static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1655{
1656 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1657
1658 /* Start condition must begin with data and clock high */
1659 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1660 ixgbe_raise_i2c_clk(hw, &i2cctl);
1661
1662 /* Setup time for start condition (4.7us) */
1663 udelay(IXGBE_I2C_T_SU_STA);
1664
1665 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1666
1667 /* Hold time for start condition (4us) */
1668 udelay(IXGBE_I2C_T_HD_STA);
1669
1670 ixgbe_lower_i2c_clk(hw, &i2cctl);
1671
1672 /* Minimum low period of clock is 4.7 us */
1673 udelay(IXGBE_I2C_T_LOW);
1674
1675}
1676
1677/**
1678 * ixgbe_i2c_stop - Sets I2C stop condition
1679 * @hw: pointer to hardware structure
1680 *
1681 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1682 **/
1683static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1684{
1685 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1686
1687 /* Stop condition must begin with data low and clock high */
1688 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1689 ixgbe_raise_i2c_clk(hw, &i2cctl);
1690
1691 /* Setup time for stop condition (4us) */
1692 udelay(IXGBE_I2C_T_SU_STO);
1693
1694 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1695
1696 /* bus free time between stop and start (4.7us)*/
1697 udelay(IXGBE_I2C_T_BUF);
1698}
1699
1700/**
1701 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1702 * @hw: pointer to hardware structure
1703 * @data: data byte to clock in
1704 *
1705 * Clocks in one byte data via I2C data/clock
1706 **/
1707static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1708{
11afc1b1 1709 s32 i;
3db1cd5c 1710 bool bit = false;
11afc1b1
PW		 1711
1712 for (i = 7; i >= 0; i--) {
e1befd77 1713 ixgbe_clock_in_i2c_bit(hw, &bit);
11afc1b1 1714 *data |= bit << i;
11afc1b1
PW		 1715 }
1716
e1befd77 1717 return 0;
11afc1b1
PW		 1718}
1719
1720/**
1721 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1722 * @hw: pointer to hardware structure
1723 * @data: data byte clocked out
1724 *
1725 * Clocks out one byte data via I2C data/clock
1726 **/
1727static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1728{
e90dd264 1729 s32 status;
11afc1b1
PW		 1730 s32 i;
1731 u32 i2cctl;
3db1cd5c 1732 bool bit = false;
11afc1b1
PW		 1733
1734 for (i = 7; i >= 0; i--) {
1735 bit = (data >> i) & 0x1;
1736 status = ixgbe_clock_out_i2c_bit(hw, bit);
1737
1738 if (status != 0)
1739 break;
1740 }
1741
1742 /* Release SDA line (set high) */
1743 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1744 i2cctl |= IXGBE_I2C_DATA_OUT;
1745 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
176f950d 1746 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1747
1748 return status;
1749}
1750
1751/**
1752 * ixgbe_get_i2c_ack - Polls for I2C ACK
1753 * @hw: pointer to hardware structure
1754 *
1755 * Clocks in/out one bit via I2C data/clock
1756 **/
1757static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1758{
e1befd77 1759 s32 status = 0;
11afc1b1
PW		 1760 u32 i = 0;
1761 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1762 u32 timeout = 10;
3db1cd5c 1763 bool ack = true;
11afc1b1 1764
e1befd77 1765 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1 1766
11afc1b1
PW		 1767
1768 /* Minimum high period of clock is 4us */
1769 udelay(IXGBE_I2C_T_HIGH);
1770
1771 /* Poll for ACK. Note that ACK in I2C spec is
1772 * transition from 1 to 0 */
1773 for (i = 0; i < timeout; i++) {
1774 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1775 ack = ixgbe_get_i2c_data(&i2cctl);
1776
1777 udelay(1);
1778 if (ack == 0)
1779 break;
1780 }
1781
1782 if (ack == 1) {
1783 hw_dbg(hw, "I2C ack was not received.\n");
1784 status = IXGBE_ERR_I2C;
1785 }
1786
1787 ixgbe_lower_i2c_clk(hw, &i2cctl);
1788
1789 /* Minimum low period of clock is 4.7 us */
1790 udelay(IXGBE_I2C_T_LOW);
1791
11afc1b1
PW		 1792 return status;
1793}
1794
1795/**
1796 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1797 * @hw: pointer to hardware structure
1798 * @data: read data value
1799 *
1800 * Clocks in one bit via I2C data/clock
1801 **/
1802static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1803{
11afc1b1
PW		 1804 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1805
e1befd77 1806 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1
PW		 1807
1808 /* Minimum high period of clock is 4us */
1809 udelay(IXGBE_I2C_T_HIGH);
1810
1811 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1812 *data = ixgbe_get_i2c_data(&i2cctl);
1813
1814 ixgbe_lower_i2c_clk(hw, &i2cctl);
1815
1816 /* Minimum low period of clock is 4.7 us */
1817 udelay(IXGBE_I2C_T_LOW);
1818
e1befd77 1819 return 0;
11afc1b1
PW		 1820}
1821
1822/**
1823 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1824 * @hw: pointer to hardware structure
1825 * @data: data value to write
1826 *
1827 * Clocks out one bit via I2C data/clock
1828 **/
1829static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1830{
1831 s32 status;
1832 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1833
1834 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1835 if (status == 0) {
e1befd77 1836 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1
PW		 1837
1838 /* Minimum high period of clock is 4us */
1839 udelay(IXGBE_I2C_T_HIGH);
1840
1841 ixgbe_lower_i2c_clk(hw, &i2cctl);
1842
1843 /* Minimum low period of clock is 4.7 us.
1844 * This also takes care of the data hold time.
1845 */
1846 udelay(IXGBE_I2C_T_LOW);
1847 } else {
11afc1b1 1848 hw_dbg(hw, "I2C data was not set to %X\n", data);
e90dd264 1849 return IXGBE_ERR_I2C;
11afc1b1
PW		 1850 }
1851
e90dd264 1852 return 0;
11afc1b1
PW		 1853}
1854/**
1855 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1856 * @hw: pointer to hardware structure
1857 * @i2cctl: Current value of I2CCTL register
1858 *
1859 * Raises the I2C clock line '0'->'1'
1860 **/
e1befd77 1861static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
11afc1b1 1862{
8f56e4b9
DS		 1863 u32 i = 0;
1864 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1865 u32 i2cctl_r = 0;
11afc1b1 1866
8f56e4b9
DS		 1867 for (i = 0; i < timeout; i++) {
1868 *i2cctl |= IXGBE_I2C_CLK_OUT;
1869 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1870 IXGBE_WRITE_FLUSH(hw);
1871 /* SCL rise time (1000ns) */
1872 udelay(IXGBE_I2C_T_RISE);
1873
1874 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1875 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1876 break;
1877 }
11afc1b1
PW		 1878}
1879
1880/**
1881 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1882 * @hw: pointer to hardware structure
1883 * @i2cctl: Current value of I2CCTL register
1884 *
1885 * Lowers the I2C clock line '1'->'0'
1886 **/
1887static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1888{
1889
1890 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1891
1892 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
945a5151 1893 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1894
1895 /* SCL fall time (300ns) */
1896 udelay(IXGBE_I2C_T_FALL);
1897}
1898
1899/**
1900 * ixgbe_set_i2c_data - Sets the I2C data bit
1901 * @hw: pointer to hardware structure
1902 * @i2cctl: Current value of I2CCTL register
1903 * @data: I2C data value (0 or 1) to set
1904 *
1905 * Sets the I2C data bit
1906 **/
1907static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1908{
11afc1b1
PW		 1909 if (data)
1910 *i2cctl |= IXGBE_I2C_DATA_OUT;
1911 else
1912 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1913
1914 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
945a5151 1915 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1916
1917 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1918 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1919
1920 /* Verify data was set correctly */
1921 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1922 if (data != ixgbe_get_i2c_data(i2cctl)) {
11afc1b1 1923 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
e90dd264 1924 return IXGBE_ERR_I2C;
11afc1b1
PW		 1925 }
1926
e90dd264 1927 return 0;
11afc1b1
PW		 1928}
1929
1930/**
1931 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1932 * @hw: pointer to hardware structure
1933 * @i2cctl: Current value of I2CCTL register
1934 *
1935 * Returns the I2C data bit value
1936 **/
1937static bool ixgbe_get_i2c_data(u32 *i2cctl)
1938{
11afc1b1 1939 if (*i2cctl & IXGBE_I2C_DATA_IN)
e90dd264
MR		 1940 return true;
1941 return false;
11afc1b1
PW		 1942}
1943
1944/**
1945 * ixgbe_i2c_bus_clear - Clears the I2C bus
1946 * @hw: pointer to hardware structure
1947 *
1948 * Clears the I2C bus by sending nine clock pulses.
1949 * Used when data line is stuck low.
1950 **/
1951static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1952{
1953 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1954 u32 i;
1955
75f19c3c
ET		 1956 ixgbe_i2c_start(hw);
1957
11afc1b1
PW		 1958 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1959
1960 for (i = 0; i < 9; i++) {
1961 ixgbe_raise_i2c_clk(hw, &i2cctl);
1962
1963 /* Min high period of clock is 4us */
1964 udelay(IXGBE_I2C_T_HIGH);
1965
1966 ixgbe_lower_i2c_clk(hw, &i2cctl);
1967
1968 /* Min low period of clock is 4.7us*/
1969 udelay(IXGBE_I2C_T_LOW);
1970 }
1971
75f19c3c
ET		 1972 ixgbe_i2c_start(hw);
1973
11afc1b1
PW		 1974 /* Put the i2c bus back to default state */
1975 ixgbe_i2c_stop(hw);
1976}
1977
119fc60a 1978/**
25985edc 1979 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
119fc60a
MC		 1980 * @hw: pointer to hardware structure
1981 *
1982 * Checks if the LASI temp alarm status was triggered due to overtemp
1983 **/
1984s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1985{
119fc60a
MC		 1986 u16 phy_data = 0;
1987
1988 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
e90dd264 1989 return 0;
119fc60a
MC		 1990
1991 /* Check that the LASI temp alarm status was triggered */
1992 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
e7cf745b 1993 MDIO_MMD_PMAPMD, &phy_data);
119fc60a
MC		 1994
1995 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
e90dd264 1996 return 0;
119fc60a 1997
e90dd264 1998 return IXGBE_ERR_OVERTEMP;
119fc60a 1999}
Linux 6.x block layer and io_uring tree(s)