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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
94971820 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
9a799d71 AK |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
897ab156 | 38 | #include <linux/sctp.h> |
60127865 | 39 | #include <linux/pkt_sched.h> |
9a799d71 | 40 | #include <linux/ipv6.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
9a799d71 AK |
42 | #include <net/checksum.h> |
43 | #include <net/ip6_checksum.h> | |
44 | #include <linux/ethtool.h> | |
01789349 | 45 | #include <linux/if.h> |
9a799d71 | 46 | #include <linux/if_vlan.h> |
815cccbf | 47 | #include <linux/if_bridge.h> |
70c71606 | 48 | #include <linux/prefetch.h> |
eacd73f7 | 49 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
50 | |
51 | #include "ixgbe.h" | |
52 | #include "ixgbe_common.h" | |
ee5f784a | 53 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 54 | #include "ixgbe_sriov.h" |
9a799d71 AK |
55 | |
56 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 57 | static const char ixgbe_driver_string[] = |
e8e9f696 | 58 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
8af3c33f | 59 | #ifdef IXGBE_FCOE |
ea81875a NP |
60 | char ixgbe_default_device_descr[] = |
61 | "Intel(R) 10 Gigabit Network Connection"; | |
8af3c33f JK |
62 | #else |
63 | static char ixgbe_default_device_descr[] = | |
64 | "Intel(R) 10 Gigabit Network Connection"; | |
65 | #endif | |
14a8d4bb | 66 | #define DRV_VERSION "3.11.33-k" |
9c8eb720 | 67 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 68 | static const char ixgbe_copyright[] = |
94971820 | 69 | "Copyright (c) 1999-2012 Intel Corporation."; |
9a799d71 AK |
70 | |
71 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 72 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 73 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 74 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
75 | }; |
76 | ||
77 | /* ixgbe_pci_tbl - PCI Device ID Table | |
78 | * | |
79 | * Wildcard entries (PCI_ANY_ID) should come last | |
80 | * Last entry must be all 0s | |
81 | * | |
82 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
83 | * Class, Class Mask, private data (not used) } | |
84 | */ | |
a3aa1884 | 85 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
54239c67 AD |
86 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
88 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
7d145282 | 112 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
df376f0d | 114 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, |
9a799d71 AK |
115 | /* required last entry */ |
116 | {0, } | |
117 | }; | |
118 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
119 | ||
5dd2d332 | 120 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 121 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 122 | void *p); |
bd0362dd JC |
123 | static struct notifier_block dca_notifier = { |
124 | .notifier_call = ixgbe_notify_dca, | |
125 | .next = NULL, | |
126 | .priority = 0 | |
127 | }; | |
128 | #endif | |
129 | ||
1cdd1ec8 GR |
130 | #ifdef CONFIG_PCI_IOV |
131 | static unsigned int max_vfs; | |
132 | module_param(max_vfs, uint, 0); | |
e8e9f696 | 133 | MODULE_PARM_DESC(max_vfs, |
6b42a9c5 | 134 | "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63"); |
1cdd1ec8 GR |
135 | #endif /* CONFIG_PCI_IOV */ |
136 | ||
8ef78adc PWJ |
137 | static unsigned int allow_unsupported_sfp; |
138 | module_param(allow_unsupported_sfp, uint, 0); | |
139 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
140 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
141 | ||
b3f4d599 | 142 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
143 | static int debug = -1; | |
144 | module_param(debug, int, 0); | |
145 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
146 | ||
9a799d71 AK |
147 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
148 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
149 | MODULE_LICENSE("GPL"); | |
150 | MODULE_VERSION(DRV_VERSION); | |
151 | ||
7086400d AD |
152 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
153 | { | |
154 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
155 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) | |
156 | schedule_work(&adapter->service_task); | |
157 | } | |
158 | ||
159 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) | |
160 | { | |
161 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
162 | ||
52f33af8 | 163 | /* flush memory to make sure state is correct before next watchdog */ |
7086400d AD |
164 | smp_mb__before_clear_bit(); |
165 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
166 | } | |
167 | ||
dcd79aeb TI |
168 | struct ixgbe_reg_info { |
169 | u32 ofs; | |
170 | char *name; | |
171 | }; | |
172 | ||
173 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
174 | ||
175 | /* General Registers */ | |
176 | {IXGBE_CTRL, "CTRL"}, | |
177 | {IXGBE_STATUS, "STATUS"}, | |
178 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
179 | ||
180 | /* Interrupt Registers */ | |
181 | {IXGBE_EICR, "EICR"}, | |
182 | ||
183 | /* RX Registers */ | |
184 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
185 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
186 | {IXGBE_RDLEN(0), "RDLEN"}, | |
187 | {IXGBE_RDH(0), "RDH"}, | |
188 | {IXGBE_RDT(0), "RDT"}, | |
189 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
190 | {IXGBE_RDBAL(0), "RDBAL"}, | |
191 | {IXGBE_RDBAH(0), "RDBAH"}, | |
192 | ||
193 | /* TX Registers */ | |
194 | {IXGBE_TDBAL(0), "TDBAL"}, | |
195 | {IXGBE_TDBAH(0), "TDBAH"}, | |
196 | {IXGBE_TDLEN(0), "TDLEN"}, | |
197 | {IXGBE_TDH(0), "TDH"}, | |
198 | {IXGBE_TDT(0), "TDT"}, | |
199 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
200 | ||
201 | /* List Terminator */ | |
202 | {} | |
203 | }; | |
204 | ||
205 | ||
206 | /* | |
207 | * ixgbe_regdump - register printout routine | |
208 | */ | |
209 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
210 | { | |
211 | int i = 0, j = 0; | |
212 | char rname[16]; | |
213 | u32 regs[64]; | |
214 | ||
215 | switch (reginfo->ofs) { | |
216 | case IXGBE_SRRCTL(0): | |
217 | for (i = 0; i < 64; i++) | |
218 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
219 | break; | |
220 | case IXGBE_DCA_RXCTRL(0): | |
221 | for (i = 0; i < 64; i++) | |
222 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
223 | break; | |
224 | case IXGBE_RDLEN(0): | |
225 | for (i = 0; i < 64; i++) | |
226 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
227 | break; | |
228 | case IXGBE_RDH(0): | |
229 | for (i = 0; i < 64; i++) | |
230 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
231 | break; | |
232 | case IXGBE_RDT(0): | |
233 | for (i = 0; i < 64; i++) | |
234 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
235 | break; | |
236 | case IXGBE_RXDCTL(0): | |
237 | for (i = 0; i < 64; i++) | |
238 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
239 | break; | |
240 | case IXGBE_RDBAL(0): | |
241 | for (i = 0; i < 64; i++) | |
242 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
243 | break; | |
244 | case IXGBE_RDBAH(0): | |
245 | for (i = 0; i < 64; i++) | |
246 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
247 | break; | |
248 | case IXGBE_TDBAL(0): | |
249 | for (i = 0; i < 64; i++) | |
250 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
251 | break; | |
252 | case IXGBE_TDBAH(0): | |
253 | for (i = 0; i < 64; i++) | |
254 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
255 | break; | |
256 | case IXGBE_TDLEN(0): | |
257 | for (i = 0; i < 64; i++) | |
258 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
259 | break; | |
260 | case IXGBE_TDH(0): | |
261 | for (i = 0; i < 64; i++) | |
262 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
263 | break; | |
264 | case IXGBE_TDT(0): | |
265 | for (i = 0; i < 64; i++) | |
266 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
267 | break; | |
268 | case IXGBE_TXDCTL(0): | |
269 | for (i = 0; i < 64; i++) | |
270 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
271 | break; | |
272 | default: | |
c7689578 | 273 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
274 | IXGBE_READ_REG(hw, reginfo->ofs)); |
275 | return; | |
276 | } | |
277 | ||
278 | for (i = 0; i < 8; i++) { | |
279 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 280 | pr_err("%-15s", rname); |
dcd79aeb | 281 | for (j = 0; j < 8; j++) |
c7689578 JP |
282 | pr_cont(" %08x", regs[i*8+j]); |
283 | pr_cont("\n"); | |
dcd79aeb TI |
284 | } |
285 | ||
286 | } | |
287 | ||
288 | /* | |
289 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
290 | */ | |
291 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
292 | { | |
293 | struct net_device *netdev = adapter->netdev; | |
294 | struct ixgbe_hw *hw = &adapter->hw; | |
295 | struct ixgbe_reg_info *reginfo; | |
296 | int n = 0; | |
297 | struct ixgbe_ring *tx_ring; | |
729739b7 | 298 | struct ixgbe_tx_buffer *tx_buffer; |
dcd79aeb TI |
299 | union ixgbe_adv_tx_desc *tx_desc; |
300 | struct my_u0 { u64 a; u64 b; } *u0; | |
301 | struct ixgbe_ring *rx_ring; | |
302 | union ixgbe_adv_rx_desc *rx_desc; | |
303 | struct ixgbe_rx_buffer *rx_buffer_info; | |
304 | u32 staterr; | |
305 | int i = 0; | |
306 | ||
307 | if (!netif_msg_hw(adapter)) | |
308 | return; | |
309 | ||
310 | /* Print netdevice Info */ | |
311 | if (netdev) { | |
312 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 313 | pr_info("Device Name state " |
dcd79aeb | 314 | "trans_start last_rx\n"); |
c7689578 JP |
315 | pr_info("%-15s %016lX %016lX %016lX\n", |
316 | netdev->name, | |
317 | netdev->state, | |
318 | netdev->trans_start, | |
319 | netdev->last_rx); | |
dcd79aeb TI |
320 | } |
321 | ||
322 | /* Print Registers */ | |
323 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 324 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
325 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
326 | reginfo->name; reginfo++) { | |
327 | ixgbe_regdump(hw, reginfo); | |
328 | } | |
329 | ||
330 | /* Print TX Ring Summary */ | |
331 | if (!netdev || !netif_running(netdev)) | |
332 | goto exit; | |
333 | ||
334 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
8ad88e37 JH |
335 | pr_info(" %s %s %s %s\n", |
336 | "Queue [NTU] [NTC] [bi(ntc)->dma ]", | |
337 | "leng", "ntw", "timestamp"); | |
dcd79aeb TI |
338 | for (n = 0; n < adapter->num_tx_queues; n++) { |
339 | tx_ring = adapter->tx_ring[n]; | |
729739b7 | 340 | tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
8ad88e37 | 341 | pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", |
dcd79aeb | 342 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
729739b7 AD |
343 | (u64)dma_unmap_addr(tx_buffer, dma), |
344 | dma_unmap_len(tx_buffer, len), | |
345 | tx_buffer->next_to_watch, | |
346 | (u64)tx_buffer->time_stamp); | |
dcd79aeb TI |
347 | } |
348 | ||
349 | /* Print TX Rings */ | |
350 | if (!netif_msg_tx_done(adapter)) | |
351 | goto rx_ring_summary; | |
352 | ||
353 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
354 | ||
355 | /* Transmit Descriptor Formats | |
356 | * | |
39ac868a | 357 | * 82598 Advanced Transmit Descriptor |
dcd79aeb TI |
358 | * +--------------------------------------------------------------+ |
359 | * 0 | Buffer Address [63:0] | | |
360 | * +--------------------------------------------------------------+ | |
39ac868a | 361 | * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | |
dcd79aeb TI |
362 | * +--------------------------------------------------------------+ |
363 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
39ac868a JH |
364 | * |
365 | * 82598 Advanced Transmit Descriptor (Write-Back Format) | |
366 | * +--------------------------------------------------------------+ | |
367 | * 0 | RSV [63:0] | | |
368 | * +--------------------------------------------------------------+ | |
369 | * 8 | RSV | STA | NXTSEQ | | |
370 | * +--------------------------------------------------------------+ | |
371 | * 63 36 35 32 31 0 | |
372 | * | |
373 | * 82599+ Advanced Transmit Descriptor | |
374 | * +--------------------------------------------------------------+ | |
375 | * 0 | Buffer Address [63:0] | | |
376 | * +--------------------------------------------------------------+ | |
377 | * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | | |
378 | * +--------------------------------------------------------------+ | |
379 | * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 | |
380 | * | |
381 | * 82599+ Advanced Transmit Descriptor (Write-Back Format) | |
382 | * +--------------------------------------------------------------+ | |
383 | * 0 | RSV [63:0] | | |
384 | * +--------------------------------------------------------------+ | |
385 | * 8 | RSV | STA | RSV | | |
386 | * +--------------------------------------------------------------+ | |
387 | * 63 36 35 32 31 0 | |
dcd79aeb TI |
388 | */ |
389 | ||
390 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
391 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
392 | pr_info("------------------------------------\n"); |
393 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
394 | pr_info("------------------------------------\n"); | |
8ad88e37 JH |
395 | pr_info("%s%s %s %s %s %s\n", |
396 | "T [desc] [address 63:0 ] ", | |
397 | "[PlPOIdStDDt Ln] [bi->dma ] ", | |
398 | "leng", "ntw", "timestamp", "bi->skb"); | |
dcd79aeb TI |
399 | |
400 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
e4f74028 | 401 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 402 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
dcd79aeb | 403 | u0 = (struct my_u0 *)tx_desc; |
8ad88e37 JH |
404 | if (dma_unmap_len(tx_buffer, len) > 0) { |
405 | pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", | |
406 | i, | |
407 | le64_to_cpu(u0->a), | |
408 | le64_to_cpu(u0->b), | |
409 | (u64)dma_unmap_addr(tx_buffer, dma), | |
729739b7 | 410 | dma_unmap_len(tx_buffer, len), |
8ad88e37 JH |
411 | tx_buffer->next_to_watch, |
412 | (u64)tx_buffer->time_stamp, | |
413 | tx_buffer->skb); | |
414 | if (i == tx_ring->next_to_use && | |
415 | i == tx_ring->next_to_clean) | |
416 | pr_cont(" NTC/U\n"); | |
417 | else if (i == tx_ring->next_to_use) | |
418 | pr_cont(" NTU\n"); | |
419 | else if (i == tx_ring->next_to_clean) | |
420 | pr_cont(" NTC\n"); | |
421 | else | |
422 | pr_cont("\n"); | |
423 | ||
424 | if (netif_msg_pktdata(adapter) && | |
425 | tx_buffer->skb) | |
426 | print_hex_dump(KERN_INFO, "", | |
427 | DUMP_PREFIX_ADDRESS, 16, 1, | |
428 | tx_buffer->skb->data, | |
429 | dma_unmap_len(tx_buffer, len), | |
430 | true); | |
431 | } | |
dcd79aeb TI |
432 | } |
433 | } | |
434 | ||
435 | /* Print RX Rings Summary */ | |
436 | rx_ring_summary: | |
437 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 438 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
439 | for (n = 0; n < adapter->num_rx_queues; n++) { |
440 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
441 | pr_info("%5d %5X %5X\n", |
442 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
443 | } |
444 | ||
445 | /* Print RX Rings */ | |
446 | if (!netif_msg_rx_status(adapter)) | |
447 | goto exit; | |
448 | ||
449 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
450 | ||
39ac868a JH |
451 | /* Receive Descriptor Formats |
452 | * | |
453 | * 82598 Advanced Receive Descriptor (Read) Format | |
dcd79aeb TI |
454 | * 63 1 0 |
455 | * +-----------------------------------------------------+ | |
456 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
457 | * +----------------------------------------------+------+ | |
458 | * 8 | Header Buffer Address [63:1] | DD | | |
459 | * +-----------------------------------------------------+ | |
460 | * | |
461 | * | |
39ac868a | 462 | * 82598 Advanced Receive Descriptor (Write-Back) Format |
dcd79aeb TI |
463 | * |
464 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
465 | * +------------------------------------------------------+ | |
39ac868a JH |
466 | * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | |
467 | * | Packet | IP | | | | Type | Type | | |
468 | * | Checksum | Ident | | | | | | | |
dcd79aeb TI |
469 | * +------------------------------------------------------+ |
470 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
471 | * +------------------------------------------------------+ | |
472 | * 63 48 47 32 31 20 19 0 | |
39ac868a JH |
473 | * |
474 | * 82599+ Advanced Receive Descriptor (Read) Format | |
475 | * 63 1 0 | |
476 | * +-----------------------------------------------------+ | |
477 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
478 | * +----------------------------------------------+------+ | |
479 | * 8 | Header Buffer Address [63:1] | DD | | |
480 | * +-----------------------------------------------------+ | |
481 | * | |
482 | * | |
483 | * 82599+ Advanced Receive Descriptor (Write-Back) Format | |
484 | * | |
485 | * 63 48 47 32 31 30 21 20 17 16 4 3 0 | |
486 | * +------------------------------------------------------+ | |
487 | * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | | |
488 | * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | | |
489 | * |/ Flow Dir Flt ID | | | | | | | |
490 | * +------------------------------------------------------+ | |
491 | * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | | |
492 | * +------------------------------------------------------+ | |
493 | * 63 48 47 32 31 20 19 0 | |
dcd79aeb | 494 | */ |
39ac868a | 495 | |
dcd79aeb TI |
496 | for (n = 0; n < adapter->num_rx_queues; n++) { |
497 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
498 | pr_info("------------------------------------\n"); |
499 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
500 | pr_info("------------------------------------\n"); | |
8ad88e37 JH |
501 | pr_info("%s%s%s", |
502 | "R [desc] [ PktBuf A0] ", | |
503 | "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", | |
dcd79aeb | 504 | "<-- Adv Rx Read format\n"); |
8ad88e37 JH |
505 | pr_info("%s%s%s", |
506 | "RWB[desc] [PcsmIpSHl PtRs] ", | |
507 | "[vl er S cks ln] ---------------- [bi->skb ] ", | |
dcd79aeb TI |
508 | "<-- Adv Rx Write-Back format\n"); |
509 | ||
510 | for (i = 0; i < rx_ring->count; i++) { | |
511 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
e4f74028 | 512 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb TI |
513 | u0 = (struct my_u0 *)rx_desc; |
514 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
515 | if (staterr & IXGBE_RXD_STAT_DD) { | |
516 | /* Descriptor Done */ | |
c7689578 | 517 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
518 | "%016llX ---------------- %p", i, |
519 | le64_to_cpu(u0->a), | |
520 | le64_to_cpu(u0->b), | |
521 | rx_buffer_info->skb); | |
522 | } else { | |
c7689578 | 523 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
524 | "%016llX %016llX %p", i, |
525 | le64_to_cpu(u0->a), | |
526 | le64_to_cpu(u0->b), | |
527 | (u64)rx_buffer_info->dma, | |
528 | rx_buffer_info->skb); | |
529 | ||
9c50c035 ET |
530 | if (netif_msg_pktdata(adapter) && |
531 | rx_buffer_info->dma) { | |
dcd79aeb TI |
532 | print_hex_dump(KERN_INFO, "", |
533 | DUMP_PREFIX_ADDRESS, 16, 1, | |
9c50c035 ET |
534 | page_address(rx_buffer_info->page) + |
535 | rx_buffer_info->page_offset, | |
f800326d | 536 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
537 | } |
538 | } | |
539 | ||
540 | if (i == rx_ring->next_to_use) | |
c7689578 | 541 | pr_cont(" NTU\n"); |
dcd79aeb | 542 | else if (i == rx_ring->next_to_clean) |
c7689578 | 543 | pr_cont(" NTC\n"); |
dcd79aeb | 544 | else |
c7689578 | 545 | pr_cont("\n"); |
dcd79aeb TI |
546 | |
547 | } | |
548 | } | |
549 | ||
550 | exit: | |
551 | return; | |
552 | } | |
553 | ||
5eba3699 AV |
554 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
555 | { | |
556 | u32 ctrl_ext; | |
557 | ||
558 | /* Let firmware take over control of h/w */ | |
559 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
560 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 561 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
562 | } |
563 | ||
564 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
565 | { | |
566 | u32 ctrl_ext; | |
567 | ||
568 | /* Let firmware know the driver has taken over */ | |
569 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
570 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 571 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 572 | } |
9a799d71 | 573 | |
49ce9c2c | 574 | /** |
e8e26350 PW |
575 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors |
576 | * @adapter: pointer to adapter struct | |
577 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
578 | * @queue: queue to map the corresponding interrupt to | |
579 | * @msix_vector: the vector to map to the corresponding queue | |
580 | * | |
581 | */ | |
582 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 583 | u8 queue, u8 msix_vector) |
9a799d71 AK |
584 | { |
585 | u32 ivar, index; | |
e8e26350 PW |
586 | struct ixgbe_hw *hw = &adapter->hw; |
587 | switch (hw->mac.type) { | |
588 | case ixgbe_mac_82598EB: | |
589 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
590 | if (direction == -1) | |
591 | direction = 0; | |
592 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
593 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
594 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
595 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
596 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
597 | break; | |
598 | case ixgbe_mac_82599EB: | |
b93a2226 | 599 | case ixgbe_mac_X540: |
e8e26350 PW |
600 | if (direction == -1) { |
601 | /* other causes */ | |
602 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
603 | index = ((queue & 1) * 8); | |
604 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
605 | ivar &= ~(0xFF << index); | |
606 | ivar |= (msix_vector << index); | |
607 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
608 | break; | |
609 | } else { | |
610 | /* tx or rx causes */ | |
611 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
612 | index = ((16 * (queue & 1)) + (8 * direction)); | |
613 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
614 | ivar &= ~(0xFF << index); | |
615 | ivar |= (msix_vector << index); | |
616 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
617 | break; | |
618 | } | |
619 | default: | |
620 | break; | |
621 | } | |
9a799d71 AK |
622 | } |
623 | ||
fe49f04a | 624 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 625 | u64 qmask) |
fe49f04a AD |
626 | { |
627 | u32 mask; | |
628 | ||
bd508178 AD |
629 | switch (adapter->hw.mac.type) { |
630 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
631 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
632 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
633 | break; |
634 | case ixgbe_mac_82599EB: | |
b93a2226 | 635 | case ixgbe_mac_X540: |
fe49f04a AD |
636 | mask = (qmask & 0xFFFFFFFF); |
637 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
638 | mask = (qmask >> 32); | |
639 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
640 | break; |
641 | default: | |
642 | break; | |
fe49f04a AD |
643 | } |
644 | } | |
645 | ||
729739b7 AD |
646 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, |
647 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 648 | { |
729739b7 AD |
649 | if (tx_buffer->skb) { |
650 | dev_kfree_skb_any(tx_buffer->skb); | |
651 | if (dma_unmap_len(tx_buffer, len)) | |
d3d00239 | 652 | dma_unmap_single(ring->dev, |
729739b7 AD |
653 | dma_unmap_addr(tx_buffer, dma), |
654 | dma_unmap_len(tx_buffer, len), | |
655 | DMA_TO_DEVICE); | |
656 | } else if (dma_unmap_len(tx_buffer, len)) { | |
657 | dma_unmap_page(ring->dev, | |
658 | dma_unmap_addr(tx_buffer, dma), | |
659 | dma_unmap_len(tx_buffer, len), | |
660 | DMA_TO_DEVICE); | |
e5a43549 | 661 | } |
729739b7 AD |
662 | tx_buffer->next_to_watch = NULL; |
663 | tx_buffer->skb = NULL; | |
664 | dma_unmap_len_set(tx_buffer, len, 0); | |
665 | /* tx_buffer must be completely set up in the transmit path */ | |
9a799d71 AK |
666 | } |
667 | ||
943561d3 | 668 | static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) |
c84d324c JF |
669 | { |
670 | struct ixgbe_hw *hw = &adapter->hw; | |
671 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
c84d324c | 672 | int i; |
943561d3 | 673 | u32 data; |
c84d324c | 674 | |
943561d3 AD |
675 | if ((hw->fc.current_mode != ixgbe_fc_full) && |
676 | (hw->fc.current_mode != ixgbe_fc_rx_pause)) | |
677 | return; | |
c84d324c | 678 | |
943561d3 AD |
679 | switch (hw->mac.type) { |
680 | case ixgbe_mac_82598EB: | |
681 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
682 | break; | |
683 | default: | |
684 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
685 | } | |
686 | hwstats->lxoffrxc += data; | |
c84d324c | 687 | |
943561d3 AD |
688 | /* refill credits (no tx hang) if we received xoff */ |
689 | if (!data) | |
c84d324c | 690 | return; |
943561d3 AD |
691 | |
692 | for (i = 0; i < adapter->num_tx_queues; i++) | |
693 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
694 | &adapter->tx_ring[i]->state); | |
695 | } | |
696 | ||
697 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
698 | { | |
699 | struct ixgbe_hw *hw = &adapter->hw; | |
700 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
701 | u32 xoff[8] = {0}; | |
2afaa00d | 702 | u8 tc; |
943561d3 AD |
703 | int i; |
704 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
705 | ||
706 | if (adapter->ixgbe_ieee_pfc) | |
707 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
708 | ||
709 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { | |
710 | ixgbe_update_xoff_rx_lfc(adapter); | |
c84d324c | 711 | return; |
943561d3 | 712 | } |
c84d324c JF |
713 | |
714 | /* update stats for each tc, only valid with PFC enabled */ | |
715 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
2afaa00d PN |
716 | u32 pxoffrxc; |
717 | ||
c84d324c JF |
718 | switch (hw->mac.type) { |
719 | case ixgbe_mac_82598EB: | |
2afaa00d | 720 | pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); |
bd508178 | 721 | break; |
c84d324c | 722 | default: |
2afaa00d | 723 | pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); |
26f23d82 | 724 | } |
2afaa00d PN |
725 | hwstats->pxoffrxc[i] += pxoffrxc; |
726 | /* Get the TC for given UP */ | |
727 | tc = netdev_get_prio_tc_map(adapter->netdev, i); | |
728 | xoff[tc] += pxoffrxc; | |
c84d324c JF |
729 | } |
730 | ||
731 | /* disarm tx queues that have received xoff frames */ | |
732 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
733 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
c84d324c | 734 | |
2afaa00d | 735 | tc = tx_ring->dcb_tc; |
c84d324c JF |
736 | if (xoff[tc]) |
737 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 738 | } |
26f23d82 YZ |
739 | } |
740 | ||
c84d324c | 741 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 742 | { |
7d7ce682 | 743 | return ring->stats.packets; |
c84d324c JF |
744 | } |
745 | ||
746 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
747 | { | |
748 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 749 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 750 | |
c84d324c JF |
751 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
752 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
753 | ||
754 | if (head != tail) | |
755 | return (head < tail) ? | |
756 | tail - head : (tail + ring->count - head); | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
762 | { | |
763 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
764 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
765 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
766 | bool ret = false; | |
767 | ||
7d637bcc | 768 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
769 | |
770 | /* | |
771 | * Check for a hung queue, but be thorough. This verifies | |
772 | * that a transmit has been completed since the previous | |
773 | * check AND there is at least one packet pending. The | |
774 | * ARMED bit is set to indicate a potential hang. The | |
775 | * bit is cleared if a pause frame is received to remove | |
776 | * false hang detection due to PFC or 802.3x frames. By | |
777 | * requiring this to fail twice we avoid races with | |
778 | * pfc clearing the ARMED bit and conditions where we | |
779 | * run the check_tx_hang logic with a transmit completion | |
780 | * pending but without time to complete it yet. | |
781 | */ | |
782 | if ((tx_done_old == tx_done) && tx_pending) { | |
783 | /* make sure it is true for two checks in a row */ | |
784 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
785 | &tx_ring->state); | |
786 | } else { | |
787 | /* update completed stats and continue */ | |
788 | tx_ring->tx_stats.tx_done_old = tx_done; | |
789 | /* reset the countdown */ | |
790 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
791 | } |
792 | ||
c84d324c | 793 | return ret; |
9a799d71 AK |
794 | } |
795 | ||
c83c6cbd AD |
796 | /** |
797 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
798 | * @adapter: driver private struct | |
799 | **/ | |
800 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
801 | { | |
802 | ||
803 | /* Do the reset outside of interrupt context */ | |
804 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
805 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
806 | ixgbe_service_event_schedule(adapter); | |
807 | } | |
808 | } | |
e01c31a5 | 809 | |
9a799d71 AK |
810 | /** |
811 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 812 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 813 | * @tx_ring: tx ring to clean |
9a799d71 | 814 | **/ |
fe49f04a | 815 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 816 | struct ixgbe_ring *tx_ring) |
9a799d71 | 817 | { |
fe49f04a | 818 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
819 | struct ixgbe_tx_buffer *tx_buffer; |
820 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 821 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 822 | unsigned int budget = q_vector->tx.work_limit; |
729739b7 AD |
823 | unsigned int i = tx_ring->next_to_clean; |
824 | ||
825 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
826 | return true; | |
9a799d71 | 827 | |
d3d00239 | 828 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 829 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 830 | i -= tx_ring->count; |
12207e49 | 831 | |
729739b7 | 832 | do { |
d3d00239 AD |
833 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
834 | ||
835 | /* if next_to_watch is not set then there is no work pending */ | |
836 | if (!eop_desc) | |
837 | break; | |
838 | ||
7f83a9e6 AD |
839 | /* prevent any other reads prior to eop_desc */ |
840 | rmb(); | |
841 | ||
d3d00239 AD |
842 | /* if DD is not set pending work has not been completed */ |
843 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
844 | break; | |
8ad494b0 | 845 | |
d3d00239 AD |
846 | /* clear next_to_watch to prevent false hangs */ |
847 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 848 | |
091a6246 AD |
849 | /* update the statistics for this packet */ |
850 | total_bytes += tx_buffer->bytecount; | |
851 | total_packets += tx_buffer->gso_segs; | |
852 | ||
0ede4a60 JK |
853 | if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP)) |
854 | ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb); | |
0ede4a60 | 855 | |
fd0db0ed AD |
856 | /* free the skb */ |
857 | dev_kfree_skb_any(tx_buffer->skb); | |
858 | ||
729739b7 AD |
859 | /* unmap skb header data */ |
860 | dma_unmap_single(tx_ring->dev, | |
861 | dma_unmap_addr(tx_buffer, dma), | |
862 | dma_unmap_len(tx_buffer, len), | |
863 | DMA_TO_DEVICE); | |
864 | ||
fd0db0ed AD |
865 | /* clear tx_buffer data */ |
866 | tx_buffer->skb = NULL; | |
729739b7 | 867 | dma_unmap_len_set(tx_buffer, len, 0); |
fd0db0ed | 868 | |
729739b7 AD |
869 | /* unmap remaining buffers */ |
870 | while (tx_desc != eop_desc) { | |
d3d00239 AD |
871 | tx_buffer++; |
872 | tx_desc++; | |
8ad494b0 | 873 | i++; |
729739b7 AD |
874 | if (unlikely(!i)) { |
875 | i -= tx_ring->count; | |
d3d00239 | 876 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 877 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 878 | } |
e01c31a5 | 879 | |
729739b7 AD |
880 | /* unmap any remaining paged data */ |
881 | if (dma_unmap_len(tx_buffer, len)) { | |
882 | dma_unmap_page(tx_ring->dev, | |
883 | dma_unmap_addr(tx_buffer, dma), | |
884 | dma_unmap_len(tx_buffer, len), | |
885 | DMA_TO_DEVICE); | |
886 | dma_unmap_len_set(tx_buffer, len, 0); | |
887 | } | |
888 | } | |
889 | ||
890 | /* move us one more past the eop_desc for start of next pkt */ | |
891 | tx_buffer++; | |
892 | tx_desc++; | |
893 | i++; | |
894 | if (unlikely(!i)) { | |
895 | i -= tx_ring->count; | |
896 | tx_buffer = tx_ring->tx_buffer_info; | |
897 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
898 | } | |
899 | ||
900 | /* issue prefetch for next Tx descriptor */ | |
901 | prefetch(tx_desc); | |
12207e49 | 902 | |
729739b7 AD |
903 | /* update budget accounting */ |
904 | budget--; | |
905 | } while (likely(budget)); | |
906 | ||
907 | i += tx_ring->count; | |
9a799d71 | 908 | tx_ring->next_to_clean = i; |
d3d00239 | 909 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 910 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 911 | tx_ring->stats.packets += total_packets; |
d3d00239 | 912 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
913 | q_vector->tx.total_bytes += total_bytes; |
914 | q_vector->tx.total_packets += total_packets; | |
b953799e | 915 | |
c84d324c JF |
916 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
917 | /* schedule immediate reset if we believe we hung */ | |
918 | struct ixgbe_hw *hw = &adapter->hw; | |
c84d324c JF |
919 | e_err(drv, "Detected Tx Unit Hang\n" |
920 | " Tx Queue <%d>\n" | |
921 | " TDH, TDT <%x>, <%x>\n" | |
922 | " next_to_use <%x>\n" | |
923 | " next_to_clean <%x>\n" | |
924 | "tx_buffer_info[next_to_clean]\n" | |
925 | " time_stamp <%lx>\n" | |
926 | " jiffies <%lx>\n", | |
927 | tx_ring->queue_index, | |
928 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
929 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
930 | tx_ring->next_to_use, i, |
931 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
932 | |
933 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
934 | ||
935 | e_info(probe, | |
936 | "tx hang %d detected on queue %d, resetting adapter\n", | |
937 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
938 | ||
b953799e | 939 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 940 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
941 | |
942 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 943 | return true; |
b953799e | 944 | } |
9a799d71 | 945 | |
b2d96e0a AD |
946 | netdev_tx_completed_queue(txring_txq(tx_ring), |
947 | total_packets, total_bytes); | |
948 | ||
e092be60 | 949 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 950 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 951 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
952 | /* Make sure that anybody stopping the queue after this |
953 | * sees the new next_to_clean. | |
954 | */ | |
955 | smp_mb(); | |
729739b7 AD |
956 | if (__netif_subqueue_stopped(tx_ring->netdev, |
957 | tx_ring->queue_index) | |
958 | && !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
959 | netif_wake_subqueue(tx_ring->netdev, | |
960 | tx_ring->queue_index); | |
5b7da515 | 961 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 962 | } |
e092be60 | 963 | } |
9a799d71 | 964 | |
59224555 | 965 | return !!budget; |
9a799d71 AK |
966 | } |
967 | ||
5dd2d332 | 968 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
969 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
970 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 971 | int cpu) |
bd0362dd | 972 | { |
33cf09c9 | 973 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
974 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); |
975 | u16 reg_offset; | |
33cf09c9 | 976 | |
33cf09c9 AD |
977 | switch (hw->mac.type) { |
978 | case ixgbe_mac_82598EB: | |
bdda1a61 | 979 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
980 | break; |
981 | case ixgbe_mac_82599EB: | |
b93a2226 | 982 | case ixgbe_mac_X540: |
bdda1a61 AD |
983 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
984 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
985 | break; |
986 | default: | |
bdda1a61 AD |
987 | /* for unknown hardware do not write register */ |
988 | return; | |
bd0362dd | 989 | } |
bdda1a61 AD |
990 | |
991 | /* | |
992 | * We can enable relaxed ordering for reads, but not writes when | |
993 | * DCA is enabled. This is due to a known issue in some chipsets | |
994 | * which will cause the DCA tag to be cleared. | |
995 | */ | |
996 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
997 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
998 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
999 | ||
1000 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
1001 | } |
1002 | ||
bdda1a61 AD |
1003 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
1004 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 1005 | int cpu) |
bd0362dd | 1006 | { |
33cf09c9 | 1007 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
1008 | u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); |
1009 | u8 reg_idx = rx_ring->reg_idx; | |
1010 | ||
33cf09c9 AD |
1011 | |
1012 | switch (hw->mac.type) { | |
33cf09c9 | 1013 | case ixgbe_mac_82599EB: |
b93a2226 | 1014 | case ixgbe_mac_X540: |
bdda1a61 | 1015 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
1016 | break; |
1017 | default: | |
1018 | break; | |
1019 | } | |
bdda1a61 AD |
1020 | |
1021 | /* | |
1022 | * We can enable relaxed ordering for reads, but not writes when | |
1023 | * DCA is enabled. This is due to a known issue in some chipsets | |
1024 | * which will cause the DCA tag to be cleared. | |
1025 | */ | |
1026 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
bdda1a61 AD |
1027 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
1028 | ||
1029 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
1030 | } |
1031 | ||
1032 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
1033 | { | |
1034 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 1035 | struct ixgbe_ring *ring; |
bd0362dd | 1036 | int cpu = get_cpu(); |
bd0362dd | 1037 | |
33cf09c9 AD |
1038 | if (q_vector->cpu == cpu) |
1039 | goto out_no_update; | |
1040 | ||
a557928e | 1041 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 1042 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 1043 | |
a557928e | 1044 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 1045 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
1046 | |
1047 | q_vector->cpu = cpu; | |
1048 | out_no_update: | |
bd0362dd JC |
1049 | put_cpu(); |
1050 | } | |
1051 | ||
1052 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
1053 | { | |
1054 | int i; | |
1055 | ||
1056 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
1057 | return; | |
1058 | ||
e35ec126 AD |
1059 | /* always use CB2 mode, difference is masked in the CB driver */ |
1060 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
1061 | ||
49c7ffbe | 1062 | for (i = 0; i < adapter->num_q_vectors; i++) { |
33cf09c9 AD |
1063 | adapter->q_vector[i]->cpu = -1; |
1064 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1065 | } |
1066 | } | |
1067 | ||
1068 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1069 | { | |
c60fbb00 | 1070 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1071 | unsigned long event = *(unsigned long *)data; |
1072 | ||
2a72c31e | 1073 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
1074 | return 0; |
1075 | ||
bd0362dd JC |
1076 | switch (event) { |
1077 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1078 | /* if we're already enabled, don't do it again */ |
1079 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1080 | break; | |
652f093f | 1081 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1082 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1083 | ixgbe_setup_dca(adapter); |
1084 | break; | |
1085 | } | |
1086 | /* Fall Through since DCA is disabled. */ | |
1087 | case DCA_PROVIDER_REMOVE: | |
1088 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1089 | dca_remove_requester(dev); | |
1090 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1091 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1092 | } | |
1093 | break; | |
1094 | } | |
1095 | ||
652f093f | 1096 | return 0; |
bd0362dd | 1097 | } |
67a74ee2 | 1098 | |
bdda1a61 | 1099 | #endif /* CONFIG_IXGBE_DCA */ |
8a0da21b AD |
1100 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
1101 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
1102 | struct sk_buff *skb) |
1103 | { | |
8a0da21b AD |
1104 | if (ring->netdev->features & NETIF_F_RXHASH) |
1105 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
67a74ee2 ET |
1106 | } |
1107 | ||
f800326d | 1108 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1109 | /** |
1110 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
57efd44c | 1111 | * @ring: structure containing ring specific data |
ff886dfc AD |
1112 | * @rx_desc: advanced rx descriptor |
1113 | * | |
1114 | * Returns : true if it is FCoE pkt | |
1115 | */ | |
57efd44c | 1116 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, |
ff886dfc AD |
1117 | union ixgbe_adv_rx_desc *rx_desc) |
1118 | { | |
1119 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1120 | ||
57efd44c | 1121 | return test_bit(__IXGBE_RX_FCOE, &ring->state) && |
ff886dfc AD |
1122 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == |
1123 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1124 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1125 | } | |
1126 | ||
f800326d | 1127 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1128 | /** |
1129 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1130 | * @ring: structure containing ring specific data |
1131 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1132 | * @skb: skb currently being received and modified |
1133 | **/ | |
8a0da21b | 1134 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1135 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1136 | struct sk_buff *skb) |
9a799d71 | 1137 | { |
8a0da21b | 1138 | skb_checksum_none_assert(skb); |
9a799d71 | 1139 | |
712744be | 1140 | /* Rx csum disabled */ |
8a0da21b | 1141 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1142 | return; |
e59bd25d AV |
1143 | |
1144 | /* if IP and error */ | |
f56e0cb1 AD |
1145 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1146 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1147 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1148 | return; |
1149 | } | |
e59bd25d | 1150 | |
f56e0cb1 | 1151 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1152 | return; |
1153 | ||
f56e0cb1 | 1154 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
f800326d | 1155 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
8bae1b2b DS |
1156 | |
1157 | /* | |
1158 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1159 | * checksum errors. | |
1160 | */ | |
8a0da21b AD |
1161 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1162 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1163 | return; |
1164 | ||
8a0da21b | 1165 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1166 | return; |
1167 | } | |
1168 | ||
9a799d71 | 1169 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1170 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1171 | } |
1172 | ||
84ea2591 | 1173 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 | 1174 | { |
f56e0cb1 | 1175 | rx_ring->next_to_use = val; |
f800326d AD |
1176 | |
1177 | /* update next to alloc since we have filled the ring */ | |
1178 | rx_ring->next_to_alloc = val; | |
e8e26350 PW |
1179 | /* |
1180 | * Force memory writes to complete before letting h/w | |
1181 | * know there are new descriptors to fetch. (Only | |
1182 | * applicable for weak-ordered memory model archs, | |
1183 | * such as IA-64). | |
1184 | */ | |
1185 | wmb(); | |
84ea2591 | 1186 | writel(val, rx_ring->tail); |
e8e26350 PW |
1187 | } |
1188 | ||
f990b79b AD |
1189 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1190 | struct ixgbe_rx_buffer *bi) | |
1191 | { | |
1192 | struct page *page = bi->page; | |
f800326d | 1193 | dma_addr_t dma = bi->dma; |
f990b79b | 1194 | |
f800326d AD |
1195 | /* since we are recycling buffers we should seldom need to alloc */ |
1196 | if (likely(dma)) | |
f990b79b AD |
1197 | return true; |
1198 | ||
f800326d AD |
1199 | /* alloc new page for storage */ |
1200 | if (likely(!page)) { | |
0614002b MG |
1201 | page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP, |
1202 | bi->skb, ixgbe_rx_pg_order(rx_ring)); | |
f990b79b AD |
1203 | if (unlikely(!page)) { |
1204 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1205 | return false; | |
1206 | } | |
f800326d | 1207 | bi->page = page; |
f990b79b AD |
1208 | } |
1209 | ||
f800326d AD |
1210 | /* map page for use */ |
1211 | dma = dma_map_page(rx_ring->dev, page, 0, | |
1212 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1213 | ||
1214 | /* | |
1215 | * if mapping failed free memory back to system since | |
1216 | * there isn't much point in holding memory we can't use | |
1217 | */ | |
1218 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
dd411ec4 | 1219 | __free_pages(page, ixgbe_rx_pg_order(rx_ring)); |
f800326d | 1220 | bi->page = NULL; |
f990b79b | 1221 | |
f990b79b AD |
1222 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1223 | return false; | |
1224 | } | |
1225 | ||
f800326d | 1226 | bi->dma = dma; |
afaa9459 | 1227 | bi->page_offset = 0; |
f800326d | 1228 | |
f990b79b AD |
1229 | return true; |
1230 | } | |
1231 | ||
9a799d71 | 1232 | /** |
f990b79b | 1233 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1234 | * @rx_ring: ring to place buffers on |
1235 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1236 | **/ |
fc77dc3c | 1237 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1238 | { |
9a799d71 | 1239 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1240 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1241 | u16 i = rx_ring->next_to_use; |
9a799d71 | 1242 | |
f800326d AD |
1243 | /* nothing to do */ |
1244 | if (!cleaned_count) | |
fc77dc3c AD |
1245 | return; |
1246 | ||
e4f74028 | 1247 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1248 | bi = &rx_ring->rx_buffer_info[i]; |
1249 | i -= rx_ring->count; | |
9a799d71 | 1250 | |
f800326d AD |
1251 | do { |
1252 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1253 | break; |
d5f398ed | 1254 | |
f800326d AD |
1255 | /* |
1256 | * Refresh the desc even if buffer_addrs didn't change | |
1257 | * because each write-back erases this info. | |
1258 | */ | |
1259 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1260 | |
f990b79b AD |
1261 | rx_desc++; |
1262 | bi++; | |
9a799d71 | 1263 | i++; |
f990b79b | 1264 | if (unlikely(!i)) { |
e4f74028 | 1265 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1266 | bi = rx_ring->rx_buffer_info; |
1267 | i -= rx_ring->count; | |
1268 | } | |
1269 | ||
1270 | /* clear the hdr_addr for the next_to_use descriptor */ | |
1271 | rx_desc->read.hdr_addr = 0; | |
f800326d AD |
1272 | |
1273 | cleaned_count--; | |
1274 | } while (cleaned_count); | |
7c6e0a43 | 1275 | |
f990b79b AD |
1276 | i += rx_ring->count; |
1277 | ||
f56e0cb1 | 1278 | if (rx_ring->next_to_use != i) |
84ea2591 | 1279 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1280 | } |
1281 | ||
1d2024f6 AD |
1282 | /** |
1283 | * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE | |
1284 | * @data: pointer to the start of the headers | |
1285 | * @max_len: total length of section to find headers in | |
1286 | * | |
1287 | * This function is meant to determine the length of headers that will | |
1288 | * be recognized by hardware for LRO, GRO, and RSC offloads. The main | |
1289 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
1290 | * packets so that we can do basic things like calculating the gso_size | |
1291 | * based on the average data per packet. | |
1292 | **/ | |
1293 | static unsigned int ixgbe_get_headlen(unsigned char *data, | |
1294 | unsigned int max_len) | |
1295 | { | |
1296 | union { | |
1297 | unsigned char *network; | |
1298 | /* l2 headers */ | |
1299 | struct ethhdr *eth; | |
1300 | struct vlan_hdr *vlan; | |
1301 | /* l3 headers */ | |
1302 | struct iphdr *ipv4; | |
a048b40e | 1303 | struct ipv6hdr *ipv6; |
1d2024f6 AD |
1304 | } hdr; |
1305 | __be16 protocol; | |
1306 | u8 nexthdr = 0; /* default to not TCP */ | |
1307 | u8 hlen; | |
1308 | ||
1309 | /* this should never happen, but better safe than sorry */ | |
1310 | if (max_len < ETH_HLEN) | |
1311 | return max_len; | |
1312 | ||
1313 | /* initialize network frame pointer */ | |
1314 | hdr.network = data; | |
1315 | ||
1316 | /* set first protocol and move network header forward */ | |
1317 | protocol = hdr.eth->h_proto; | |
1318 | hdr.network += ETH_HLEN; | |
1319 | ||
1320 | /* handle any vlan tag if present */ | |
1321 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
1322 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
1323 | return max_len; | |
1324 | ||
1325 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
1326 | hdr.network += VLAN_HLEN; | |
1327 | } | |
1328 | ||
1329 | /* handle L3 protocols */ | |
1330 | if (protocol == __constant_htons(ETH_P_IP)) { | |
1331 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
1332 | return max_len; | |
1333 | ||
1334 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
1335 | hlen = (hdr.network[0] & 0x0F) << 2; | |
1336 | ||
1337 | /* verify hlen meets minimum size requirements */ | |
1338 | if (hlen < sizeof(struct iphdr)) | |
1339 | return hdr.network - data; | |
1340 | ||
1341 | /* record next protocol */ | |
1342 | nexthdr = hdr.ipv4->protocol; | |
1343 | hdr.network += hlen; | |
a048b40e AD |
1344 | } else if (protocol == __constant_htons(ETH_P_IPV6)) { |
1345 | if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) | |
1346 | return max_len; | |
1347 | ||
1348 | /* record next protocol */ | |
1349 | nexthdr = hdr.ipv6->nexthdr; | |
1350 | hdr.network += sizeof(struct ipv6hdr); | |
f800326d | 1351 | #ifdef IXGBE_FCOE |
1d2024f6 AD |
1352 | } else if (protocol == __constant_htons(ETH_P_FCOE)) { |
1353 | if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN)) | |
1354 | return max_len; | |
1355 | hdr.network += FCOE_HEADER_LEN; | |
1356 | #endif | |
1357 | } else { | |
1358 | return hdr.network - data; | |
1359 | } | |
1360 | ||
a048b40e | 1361 | /* finally sort out TCP/UDP */ |
1d2024f6 AD |
1362 | if (nexthdr == IPPROTO_TCP) { |
1363 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
1364 | return max_len; | |
1365 | ||
1366 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
1367 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
1368 | ||
1369 | /* verify hlen meets minimum size requirements */ | |
1370 | if (hlen < sizeof(struct tcphdr)) | |
1371 | return hdr.network - data; | |
1372 | ||
1373 | hdr.network += hlen; | |
a048b40e AD |
1374 | } else if (nexthdr == IPPROTO_UDP) { |
1375 | if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) | |
1376 | return max_len; | |
1377 | ||
1378 | hdr.network += sizeof(struct udphdr); | |
1d2024f6 AD |
1379 | } |
1380 | ||
1381 | /* | |
1382 | * If everything has gone correctly hdr.network should be the | |
1383 | * data section of the packet and will be the end of the header. | |
1384 | * If not then it probably represents the end of the last recognized | |
1385 | * header. | |
1386 | */ | |
1387 | if ((hdr.network - data) < max_len) | |
1388 | return hdr.network - data; | |
1389 | else | |
1390 | return max_len; | |
1391 | } | |
1392 | ||
1d2024f6 AD |
1393 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1394 | struct sk_buff *skb) | |
1395 | { | |
f800326d | 1396 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1397 | |
1398 | /* set gso_size to avoid messing up TCP MSS */ | |
1399 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1400 | IXGBE_CB(skb)->append_cnt); | |
1401 | } | |
1402 | ||
1403 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1404 | struct sk_buff *skb) | |
1405 | { | |
1406 | /* if append_cnt is 0 then frame is not RSC */ | |
1407 | if (!IXGBE_CB(skb)->append_cnt) | |
1408 | return; | |
1409 | ||
1410 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1411 | rx_ring->rx_stats.rsc_flush++; | |
1412 | ||
1413 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1414 | ||
1415 | /* gso_size is computed using append_cnt so always clear it last */ | |
1416 | IXGBE_CB(skb)->append_cnt = 0; | |
1417 | } | |
1418 | ||
8a0da21b AD |
1419 | /** |
1420 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1421 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1422 | * @rx_desc: pointer to the EOP Rx descriptor | |
1423 | * @skb: pointer to current skb being populated | |
f8212f97 | 1424 | * |
8a0da21b AD |
1425 | * This function checks the ring, descriptor, and packet information in |
1426 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1427 | * other fields within the skb. | |
f8212f97 | 1428 | **/ |
8a0da21b AD |
1429 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1430 | union ixgbe_adv_rx_desc *rx_desc, | |
1431 | struct sk_buff *skb) | |
f8212f97 | 1432 | { |
43e95f11 JF |
1433 | struct net_device *dev = rx_ring->netdev; |
1434 | ||
8a0da21b AD |
1435 | ixgbe_update_rsc_stats(rx_ring, skb); |
1436 | ||
1437 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1438 | |
8a0da21b AD |
1439 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1440 | ||
1d1a79b5 | 1441 | ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); |
3a6a4eda | 1442 | |
43e95f11 JF |
1443 | if ((dev->features & NETIF_F_HW_VLAN_RX) && |
1444 | ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { | |
8a0da21b AD |
1445 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); |
1446 | __vlan_hwaccel_put_tag(skb, vid); | |
f8212f97 AD |
1447 | } |
1448 | ||
8a0da21b | 1449 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1450 | |
43e95f11 | 1451 | skb->protocol = eth_type_trans(skb, dev); |
f8212f97 AD |
1452 | } |
1453 | ||
8a0da21b AD |
1454 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1455 | struct sk_buff *skb) | |
aa80175a | 1456 | { |
8a0da21b AD |
1457 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1458 | ||
1459 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1460 | napi_gro_receive(&q_vector->napi, skb); | |
1461 | else | |
1462 | netif_rx(skb); | |
aa80175a | 1463 | } |
43634e82 | 1464 | |
f800326d AD |
1465 | /** |
1466 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1467 | * @rx_ring: Rx ring being processed | |
1468 | * @rx_desc: Rx descriptor for current buffer | |
1469 | * @skb: Current socket buffer containing buffer in progress | |
1470 | * | |
1471 | * This function updates next to clean. If the buffer is an EOP buffer | |
1472 | * this function exits returning false, otherwise it will place the | |
1473 | * sk_buff in the next buffer to be chained and return true indicating | |
1474 | * that this is in fact a non-EOP buffer. | |
1475 | **/ | |
1476 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1477 | union ixgbe_adv_rx_desc *rx_desc, | |
1478 | struct sk_buff *skb) | |
1479 | { | |
1480 | u32 ntc = rx_ring->next_to_clean + 1; | |
1481 | ||
1482 | /* fetch, update, and store next to clean */ | |
1483 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1484 | rx_ring->next_to_clean = ntc; | |
1485 | ||
1486 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1487 | ||
5a02cbd1 AD |
1488 | /* update RSC append count if present */ |
1489 | if (ring_is_rsc_enabled(rx_ring)) { | |
1490 | __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1491 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1492 | ||
1493 | if (unlikely(rsc_enabled)) { | |
1494 | u32 rsc_cnt = le32_to_cpu(rsc_enabled); | |
1495 | ||
1496 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1497 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
f800326d | 1498 | |
5a02cbd1 AD |
1499 | /* update ntc based on RSC value */ |
1500 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1501 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1502 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1503 | } | |
f800326d AD |
1504 | } |
1505 | ||
5a02cbd1 AD |
1506 | /* if we are the last buffer then there is nothing else to do */ |
1507 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1508 | return false; | |
1509 | ||
f800326d AD |
1510 | /* place skb in next buffer to be received */ |
1511 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1512 | rx_ring->rx_stats.non_eop_descs++; | |
1513 | ||
1514 | return true; | |
1515 | } | |
1516 | ||
19861ce2 AD |
1517 | /** |
1518 | * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail | |
1519 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1520 | * @skb: pointer to current skb being adjusted | |
1521 | * | |
1522 | * This function is an ixgbe specific version of __pskb_pull_tail. The | |
1523 | * main difference between this version and the original function is that | |
1524 | * this function can make several assumptions about the state of things | |
1525 | * that allow for significant optimizations versus the standard function. | |
1526 | * As a result we can do things like drop a frag and maintain an accurate | |
1527 | * truesize for the skb. | |
1528 | */ | |
1529 | static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, | |
1530 | struct sk_buff *skb) | |
1531 | { | |
1532 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1533 | unsigned char *va; | |
1534 | unsigned int pull_len; | |
1535 | ||
1536 | /* | |
1537 | * it is valid to use page_address instead of kmap since we are | |
1538 | * working with pages allocated out of the lomem pool per | |
1539 | * alloc_page(GFP_ATOMIC) | |
1540 | */ | |
1541 | va = skb_frag_address(frag); | |
1542 | ||
1543 | /* | |
1544 | * we need the header to contain the greater of either ETH_HLEN or | |
1545 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1546 | */ | |
cf3fe7ac | 1547 | pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE); |
19861ce2 AD |
1548 | |
1549 | /* align pull length to size of long to optimize memcpy performance */ | |
1550 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1551 | ||
1552 | /* update all of the pointers */ | |
1553 | skb_frag_size_sub(frag, pull_len); | |
1554 | frag->page_offset += pull_len; | |
1555 | skb->data_len -= pull_len; | |
1556 | skb->tail += pull_len; | |
19861ce2 AD |
1557 | } |
1558 | ||
42073d91 AD |
1559 | /** |
1560 | * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB | |
1561 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1562 | * @skb: pointer to current skb being updated | |
1563 | * | |
1564 | * This function provides a basic DMA sync up for the first fragment of an | |
1565 | * skb. The reason for doing this is that the first fragment cannot be | |
1566 | * unmapped until we have reached the end of packet descriptor for a buffer | |
1567 | * chain. | |
1568 | */ | |
1569 | static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, | |
1570 | struct sk_buff *skb) | |
1571 | { | |
1572 | /* if the page was released unmap it, else just sync our portion */ | |
1573 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
1574 | dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, | |
1575 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1576 | IXGBE_CB(skb)->page_released = false; | |
1577 | } else { | |
1578 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1579 | ||
1580 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1581 | IXGBE_CB(skb)->dma, | |
1582 | frag->page_offset, | |
1583 | ixgbe_rx_bufsz(rx_ring), | |
1584 | DMA_FROM_DEVICE); | |
1585 | } | |
1586 | IXGBE_CB(skb)->dma = 0; | |
1587 | } | |
1588 | ||
f800326d AD |
1589 | /** |
1590 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1591 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1592 | * @rx_desc: pointer to the EOP Rx descriptor | |
1593 | * @skb: pointer to current skb being fixed | |
1594 | * | |
1595 | * Check for corrupted packet headers caused by senders on the local L2 | |
1596 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1597 | * should be very rare. | |
1598 | * | |
1599 | * Also address the case where we are pulling data in on pages only | |
1600 | * and as such no data is present in the skb header. | |
1601 | * | |
1602 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1603 | * it is large enough to qualify as a valid Ethernet frame. | |
1604 | * | |
1605 | * Returns true if an error was encountered and skb was freed. | |
1606 | **/ | |
1607 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1608 | union ixgbe_adv_rx_desc *rx_desc, | |
1609 | struct sk_buff *skb) | |
1610 | { | |
f800326d | 1611 | struct net_device *netdev = rx_ring->netdev; |
f800326d AD |
1612 | |
1613 | /* verify that the packet does not have any known errors */ | |
1614 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1615 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1616 | !(netdev->features & NETIF_F_RXALL))) { | |
1617 | dev_kfree_skb_any(skb); | |
1618 | return true; | |
1619 | } | |
1620 | ||
19861ce2 | 1621 | /* place header in linear portion of buffer */ |
cf3fe7ac AD |
1622 | if (skb_is_nonlinear(skb)) |
1623 | ixgbe_pull_tail(rx_ring, skb); | |
f800326d | 1624 | |
57efd44c AD |
1625 | #ifdef IXGBE_FCOE |
1626 | /* do not attempt to pad FCoE Frames as this will disrupt DDP */ | |
1627 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) | |
1628 | return false; | |
1629 | ||
1630 | #endif | |
f800326d AD |
1631 | /* if skb_pad returns an error the skb was freed */ |
1632 | if (unlikely(skb->len < 60)) { | |
1633 | int pad_len = 60 - skb->len; | |
1634 | ||
1635 | if (skb_pad(skb, pad_len)) | |
1636 | return true; | |
1637 | __skb_put(skb, pad_len); | |
1638 | } | |
1639 | ||
1640 | return false; | |
1641 | } | |
1642 | ||
f800326d AD |
1643 | /** |
1644 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1645 | * @rx_ring: rx descriptor ring to store buffers on | |
1646 | * @old_buff: donor buffer to have page reused | |
1647 | * | |
0549ae20 | 1648 | * Synchronizes page for reuse by the adapter |
f800326d AD |
1649 | **/ |
1650 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1651 | struct ixgbe_rx_buffer *old_buff) | |
1652 | { | |
1653 | struct ixgbe_rx_buffer *new_buff; | |
1654 | u16 nta = rx_ring->next_to_alloc; | |
f800326d AD |
1655 | |
1656 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1657 | ||
1658 | /* update, and store next to alloc */ | |
1659 | nta++; | |
1660 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1661 | ||
1662 | /* transfer page from old buffer to new buffer */ | |
1663 | new_buff->page = old_buff->page; | |
1664 | new_buff->dma = old_buff->dma; | |
0549ae20 | 1665 | new_buff->page_offset = old_buff->page_offset; |
f800326d AD |
1666 | |
1667 | /* sync the buffer for use by the device */ | |
1668 | dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, | |
0549ae20 AD |
1669 | new_buff->page_offset, |
1670 | ixgbe_rx_bufsz(rx_ring), | |
f800326d | 1671 | DMA_FROM_DEVICE); |
f800326d AD |
1672 | } |
1673 | ||
1674 | /** | |
1675 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1676 | * @rx_ring: rx descriptor ring to transact packets on | |
1677 | * @rx_buffer: buffer containing page to add | |
1678 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1679 | * @skb: sk_buff to place the data into | |
1680 | * | |
0549ae20 AD |
1681 | * This function will add the data contained in rx_buffer->page to the skb. |
1682 | * This is done either through a direct copy if the data in the buffer is | |
1683 | * less than the skb header size, otherwise it will just attach the page as | |
1684 | * a frag to the skb. | |
1685 | * | |
1686 | * The function will then update the page offset if necessary and return | |
1687 | * true if the buffer can be reused by the adapter. | |
f800326d | 1688 | **/ |
0549ae20 | 1689 | static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, |
f800326d | 1690 | struct ixgbe_rx_buffer *rx_buffer, |
0549ae20 AD |
1691 | union ixgbe_adv_rx_desc *rx_desc, |
1692 | struct sk_buff *skb) | |
f800326d | 1693 | { |
0549ae20 AD |
1694 | struct page *page = rx_buffer->page; |
1695 | unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); | |
09816fbe | 1696 | #if (PAGE_SIZE < 8192) |
0549ae20 | 1697 | unsigned int truesize = ixgbe_rx_bufsz(rx_ring); |
09816fbe AD |
1698 | #else |
1699 | unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); | |
1700 | unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - | |
1701 | ixgbe_rx_bufsz(rx_ring); | |
1702 | #endif | |
0549ae20 | 1703 | |
cf3fe7ac AD |
1704 | if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { |
1705 | unsigned char *va = page_address(page) + rx_buffer->page_offset; | |
1706 | ||
1707 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); | |
1708 | ||
1709 | /* we can reuse buffer as-is, just make sure it is local */ | |
1710 | if (likely(page_to_nid(page) == numa_node_id())) | |
1711 | return true; | |
1712 | ||
1713 | /* this page cannot be reused so discard it */ | |
1714 | put_page(page); | |
1715 | return false; | |
1716 | } | |
1717 | ||
0549ae20 AD |
1718 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, |
1719 | rx_buffer->page_offset, size, truesize); | |
1720 | ||
09816fbe AD |
1721 | /* avoid re-using remote pages */ |
1722 | if (unlikely(page_to_nid(page) != numa_node_id())) | |
1723 | return false; | |
1724 | ||
1725 | #if (PAGE_SIZE < 8192) | |
1726 | /* if we are only owner of page we can reuse it */ | |
1727 | if (unlikely(page_count(page) != 1)) | |
0549ae20 AD |
1728 | return false; |
1729 | ||
1730 | /* flip page offset to other buffer */ | |
1731 | rx_buffer->page_offset ^= truesize; | |
1732 | ||
09816fbe AD |
1733 | /* |
1734 | * since we are the only owner of the page and we need to | |
1735 | * increment it, just set the value to 2 in order to avoid | |
1736 | * an unecessary locked operation | |
1737 | */ | |
1738 | atomic_set(&page->_count, 2); | |
1739 | #else | |
1740 | /* move offset up to the next cache line */ | |
1741 | rx_buffer->page_offset += truesize; | |
1742 | ||
1743 | if (rx_buffer->page_offset > last_offset) | |
1744 | return false; | |
1745 | ||
0549ae20 AD |
1746 | /* bump ref count on page before it is given to the stack */ |
1747 | get_page(page); | |
09816fbe | 1748 | #endif |
0549ae20 AD |
1749 | |
1750 | return true; | |
f800326d AD |
1751 | } |
1752 | ||
18806c9e AD |
1753 | static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, |
1754 | union ixgbe_adv_rx_desc *rx_desc) | |
1755 | { | |
1756 | struct ixgbe_rx_buffer *rx_buffer; | |
1757 | struct sk_buff *skb; | |
1758 | struct page *page; | |
1759 | ||
1760 | rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; | |
1761 | page = rx_buffer->page; | |
1762 | prefetchw(page); | |
1763 | ||
1764 | skb = rx_buffer->skb; | |
1765 | ||
1766 | if (likely(!skb)) { | |
1767 | void *page_addr = page_address(page) + | |
1768 | rx_buffer->page_offset; | |
1769 | ||
1770 | /* prefetch first cache line of first page */ | |
1771 | prefetch(page_addr); | |
1772 | #if L1_CACHE_BYTES < 128 | |
1773 | prefetch(page_addr + L1_CACHE_BYTES); | |
1774 | #endif | |
1775 | ||
1776 | /* allocate a skb to store the frags */ | |
1777 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
1778 | IXGBE_RX_HDR_SIZE); | |
1779 | if (unlikely(!skb)) { | |
1780 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
1781 | return NULL; | |
1782 | } | |
1783 | ||
1784 | /* | |
1785 | * we will be copying header into skb->data in | |
1786 | * pskb_may_pull so it is in our interest to prefetch | |
1787 | * it now to avoid a possible cache miss | |
1788 | */ | |
1789 | prefetchw(skb->data); | |
1790 | ||
1791 | /* | |
1792 | * Delay unmapping of the first packet. It carries the | |
1793 | * header information, HW may still access the header | |
1794 | * after the writeback. Only unmap it when EOP is | |
1795 | * reached | |
1796 | */ | |
1797 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1798 | goto dma_sync; | |
1799 | ||
1800 | IXGBE_CB(skb)->dma = rx_buffer->dma; | |
1801 | } else { | |
1802 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) | |
1803 | ixgbe_dma_sync_frag(rx_ring, skb); | |
1804 | ||
1805 | dma_sync: | |
1806 | /* we are reusing so sync this buffer for CPU use */ | |
1807 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1808 | rx_buffer->dma, | |
1809 | rx_buffer->page_offset, | |
1810 | ixgbe_rx_bufsz(rx_ring), | |
1811 | DMA_FROM_DEVICE); | |
1812 | } | |
1813 | ||
1814 | /* pull page into skb */ | |
1815 | if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { | |
1816 | /* hand second half of page back to the ring */ | |
1817 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
1818 | } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { | |
1819 | /* the page has been released from the ring */ | |
1820 | IXGBE_CB(skb)->page_released = true; | |
1821 | } else { | |
1822 | /* we are not reusing the buffer so unmap it */ | |
1823 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
1824 | ixgbe_rx_pg_size(rx_ring), | |
1825 | DMA_FROM_DEVICE); | |
1826 | } | |
1827 | ||
1828 | /* clear contents of buffer_info */ | |
1829 | rx_buffer->skb = NULL; | |
1830 | rx_buffer->dma = 0; | |
1831 | rx_buffer->page = NULL; | |
1832 | ||
1833 | return skb; | |
f800326d AD |
1834 | } |
1835 | ||
1836 | /** | |
1837 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1838 | * @q_vector: structure containing interrupt and ring information | |
1839 | * @rx_ring: rx descriptor ring to transact packets on | |
1840 | * @budget: Total limit on number of packets to process | |
1841 | * | |
1842 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1843 | * processing. The advantage to this is that on systems that have | |
1844 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1845 | * it by maintaining the mapping of the page to the syste. | |
1846 | * | |
1847 | * Returns true if all work is completed without reaching budget | |
1848 | **/ | |
4ff7fb12 | 1849 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 1850 | struct ixgbe_ring *rx_ring, |
f4de00ed | 1851 | const int budget) |
9a799d71 | 1852 | { |
d2f4fbe2 | 1853 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3f2d1c0f | 1854 | #ifdef IXGBE_FCOE |
f800326d | 1855 | struct ixgbe_adapter *adapter = q_vector->adapter; |
4ffdf91a MR |
1856 | int ddp_bytes; |
1857 | unsigned int mss = 0; | |
3d8fd385 | 1858 | #endif /* IXGBE_FCOE */ |
f800326d | 1859 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 | 1860 | |
f800326d | 1861 | do { |
f800326d AD |
1862 | union ixgbe_adv_rx_desc *rx_desc; |
1863 | struct sk_buff *skb; | |
f800326d AD |
1864 | |
1865 | /* return some buffers to hardware, one at a time is too slow */ | |
1866 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
1867 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1868 | cleaned_count = 0; | |
1869 | } | |
1870 | ||
18806c9e | 1871 | rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); |
f800326d AD |
1872 | |
1873 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) | |
1874 | break; | |
9a799d71 | 1875 | |
f800326d AD |
1876 | /* |
1877 | * This memory barrier is needed to keep us from reading | |
1878 | * any other fields out of the rx_desc until we know the | |
1879 | * RXD_STAT_DD bit is set | |
1880 | */ | |
1881 | rmb(); | |
9a799d71 | 1882 | |
18806c9e AD |
1883 | /* retrieve a buffer from the ring */ |
1884 | skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); | |
f800326d | 1885 | |
18806c9e AD |
1886 | /* exit if we failed to retrieve a buffer */ |
1887 | if (!skb) | |
1888 | break; | |
9a799d71 | 1889 | |
9a799d71 | 1890 | cleaned_count++; |
f8212f97 | 1891 | |
f800326d AD |
1892 | /* place incomplete frames back on ring for completion */ |
1893 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
1894 | continue; | |
c267fc16 | 1895 | |
f800326d AD |
1896 | /* verify the packet layout is correct */ |
1897 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
1898 | continue; | |
9a799d71 | 1899 | |
d2f4fbe2 AV |
1900 | /* probably a little skewed due to removing CRC */ |
1901 | total_rx_bytes += skb->len; | |
d2f4fbe2 | 1902 | |
8a0da21b AD |
1903 | /* populate checksum, timestamp, VLAN, and protocol */ |
1904 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
1905 | ||
332d4a7d YZ |
1906 | #ifdef IXGBE_FCOE |
1907 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
57efd44c | 1908 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { |
f56e0cb1 | 1909 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
4ffdf91a MR |
1910 | /* include DDPed FCoE data */ |
1911 | if (ddp_bytes > 0) { | |
1912 | if (!mss) { | |
1913 | mss = rx_ring->netdev->mtu - | |
1914 | sizeof(struct fcoe_hdr) - | |
1915 | sizeof(struct fc_frame_header) - | |
1916 | sizeof(struct fcoe_crc_eof); | |
1917 | if (mss > 512) | |
1918 | mss &= ~511; | |
1919 | } | |
1920 | total_rx_bytes += ddp_bytes; | |
1921 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, | |
1922 | mss); | |
1923 | } | |
63d635b2 AD |
1924 | if (!ddp_bytes) { |
1925 | dev_kfree_skb_any(skb); | |
f800326d | 1926 | continue; |
63d635b2 | 1927 | } |
3d8fd385 | 1928 | } |
f800326d | 1929 | |
332d4a7d | 1930 | #endif /* IXGBE_FCOE */ |
8a0da21b | 1931 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 1932 | |
f800326d | 1933 | /* update budget accounting */ |
f4de00ed AD |
1934 | total_rx_packets++; |
1935 | } while (likely(total_rx_packets < budget)); | |
9a799d71 | 1936 | |
c267fc16 AD |
1937 | u64_stats_update_begin(&rx_ring->syncp); |
1938 | rx_ring->stats.packets += total_rx_packets; | |
1939 | rx_ring->stats.bytes += total_rx_bytes; | |
1940 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
1941 | q_vector->rx.total_packets += total_rx_packets; |
1942 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 1943 | |
f800326d AD |
1944 | if (cleaned_count) |
1945 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1946 | ||
f4de00ed | 1947 | return (total_rx_packets < budget); |
9a799d71 AK |
1948 | } |
1949 | ||
9a799d71 AK |
1950 | /** |
1951 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1952 | * @adapter: board private structure | |
1953 | * | |
1954 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1955 | * interrupts. | |
1956 | **/ | |
1957 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1958 | { | |
021230d4 | 1959 | struct ixgbe_q_vector *q_vector; |
49c7ffbe | 1960 | int v_idx; |
021230d4 | 1961 | u32 mask; |
9a799d71 | 1962 | |
8e34d1aa AD |
1963 | /* Populate MSIX to EITR Select */ |
1964 | if (adapter->num_vfs > 32) { | |
1965 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1966 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1967 | } | |
1968 | ||
4df10466 JB |
1969 | /* |
1970 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1971 | * corresponding register. |
1972 | */ | |
49c7ffbe | 1973 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { |
efe3d3c8 | 1974 | struct ixgbe_ring *ring; |
7a921c93 | 1975 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 1976 | |
a557928e | 1977 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
1978 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
1979 | ||
a557928e | 1980 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
1981 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
1982 | ||
fe49f04a | 1983 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1984 | } |
1985 | ||
bd508178 AD |
1986 | switch (adapter->hw.mac.type) { |
1987 | case ixgbe_mac_82598EB: | |
e8e26350 | 1988 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1989 | v_idx); |
bd508178 AD |
1990 | break; |
1991 | case ixgbe_mac_82599EB: | |
b93a2226 | 1992 | case ixgbe_mac_X540: |
e8e26350 | 1993 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 1994 | break; |
bd508178 AD |
1995 | default: |
1996 | break; | |
1997 | } | |
021230d4 AV |
1998 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1999 | ||
41fb9248 | 2000 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 2001 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
2002 | mask &= ~(IXGBE_EIMS_OTHER | |
2003 | IXGBE_EIMS_MAILBOX | | |
2004 | IXGBE_EIMS_LSC); | |
2005 | ||
021230d4 | 2006 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
2007 | } |
2008 | ||
f494e8fa AV |
2009 | enum latency_range { |
2010 | lowest_latency = 0, | |
2011 | low_latency = 1, | |
2012 | bulk_latency = 2, | |
2013 | latency_invalid = 255 | |
2014 | }; | |
2015 | ||
2016 | /** | |
2017 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
2018 | * @q_vector: structure containing interrupt and ring information |
2019 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
2020 | * |
2021 | * Stores a new ITR value based on packets and byte | |
2022 | * counts during the last interrupt. The advantage of per interrupt | |
2023 | * computation is faster updates and more accurate ITR for the current | |
2024 | * traffic pattern. Constants in this function were computed | |
2025 | * based on theoretical maximum wire speed and thresholds were set based | |
2026 | * on testing data as well as attempting to minimize response time | |
2027 | * while increasing bulk throughput. | |
2028 | * this functionality is controlled by the InterruptThrottleRate module | |
2029 | * parameter (see ixgbe_param.c) | |
2030 | **/ | |
bd198058 AD |
2031 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
2032 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 2033 | { |
bd198058 AD |
2034 | int bytes = ring_container->total_bytes; |
2035 | int packets = ring_container->total_packets; | |
2036 | u32 timepassed_us; | |
621bd70e | 2037 | u64 bytes_perint; |
bd198058 | 2038 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
2039 | |
2040 | if (packets == 0) | |
bd198058 | 2041 | return; |
f494e8fa AV |
2042 | |
2043 | /* simple throttlerate management | |
621bd70e AD |
2044 | * 0-10MB/s lowest (100000 ints/s) |
2045 | * 10-20MB/s low (20000 ints/s) | |
2046 | * 20-1249MB/s bulk (8000 ints/s) | |
f494e8fa AV |
2047 | */ |
2048 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 2049 | timepassed_us = q_vector->itr >> 2; |
f494e8fa AV |
2050 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
2051 | ||
2052 | switch (itr_setting) { | |
2053 | case lowest_latency: | |
621bd70e | 2054 | if (bytes_perint > 10) |
bd198058 | 2055 | itr_setting = low_latency; |
f494e8fa AV |
2056 | break; |
2057 | case low_latency: | |
621bd70e | 2058 | if (bytes_perint > 20) |
bd198058 | 2059 | itr_setting = bulk_latency; |
621bd70e | 2060 | else if (bytes_perint <= 10) |
bd198058 | 2061 | itr_setting = lowest_latency; |
f494e8fa AV |
2062 | break; |
2063 | case bulk_latency: | |
621bd70e | 2064 | if (bytes_perint <= 20) |
bd198058 | 2065 | itr_setting = low_latency; |
f494e8fa AV |
2066 | break; |
2067 | } | |
2068 | ||
bd198058 AD |
2069 | /* clear work counters since we have the values we need */ |
2070 | ring_container->total_bytes = 0; | |
2071 | ring_container->total_packets = 0; | |
2072 | ||
2073 | /* write updated itr to ring container */ | |
2074 | ring_container->itr = itr_setting; | |
f494e8fa AV |
2075 | } |
2076 | ||
509ee935 JB |
2077 | /** |
2078 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 2079 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
2080 | * |
2081 | * This function is made to be called by ethtool and by the driver | |
2082 | * when it needs to update EITR registers at runtime. Hardware | |
2083 | * specific quirks/differences are taken care of here. | |
2084 | */ | |
fe49f04a | 2085 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 2086 | { |
fe49f04a | 2087 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 2088 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2089 | int v_idx = q_vector->v_idx; |
5d967eb7 | 2090 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 2091 | |
bd508178 AD |
2092 | switch (adapter->hw.mac.type) { |
2093 | case ixgbe_mac_82598EB: | |
509ee935 JB |
2094 | /* must write high and low 16 bits to reset counter */ |
2095 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
2096 | break; |
2097 | case ixgbe_mac_82599EB: | |
b93a2226 | 2098 | case ixgbe_mac_X540: |
509ee935 JB |
2099 | /* |
2100 | * set the WDIS bit to not clear the timer bits and cause an | |
2101 | * immediate assertion of the interrupt | |
2102 | */ | |
2103 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
2104 | break; |
2105 | default: | |
2106 | break; | |
509ee935 JB |
2107 | } |
2108 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
2109 | } | |
2110 | ||
bd198058 | 2111 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 2112 | { |
d5bf4f67 | 2113 | u32 new_itr = q_vector->itr; |
bd198058 | 2114 | u8 current_itr; |
f494e8fa | 2115 | |
bd198058 AD |
2116 | ixgbe_update_itr(q_vector, &q_vector->tx); |
2117 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 2118 | |
08c8833b | 2119 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
2120 | |
2121 | switch (current_itr) { | |
2122 | /* counts and packets in update_itr are dependent on these numbers */ | |
2123 | case lowest_latency: | |
d5bf4f67 | 2124 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
2125 | break; |
2126 | case low_latency: | |
d5bf4f67 | 2127 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
2128 | break; |
2129 | case bulk_latency: | |
d5bf4f67 | 2130 | new_itr = IXGBE_8K_ITR; |
f494e8fa | 2131 | break; |
bd198058 AD |
2132 | default: |
2133 | break; | |
f494e8fa AV |
2134 | } |
2135 | ||
d5bf4f67 | 2136 | if (new_itr != q_vector->itr) { |
fe49f04a | 2137 | /* do an exponential smoothing */ |
d5bf4f67 ET |
2138 | new_itr = (10 * new_itr * q_vector->itr) / |
2139 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 2140 | |
bd198058 | 2141 | /* save the algorithm value here */ |
5d967eb7 | 2142 | q_vector->itr = new_itr; |
fe49f04a AD |
2143 | |
2144 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2145 | } |
f494e8fa AV |
2146 | } |
2147 | ||
119fc60a | 2148 | /** |
de88eeeb | 2149 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 2150 | * @adapter: pointer to adapter |
119fc60a | 2151 | **/ |
f0f9778d | 2152 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 2153 | { |
119fc60a MC |
2154 | struct ixgbe_hw *hw = &adapter->hw; |
2155 | u32 eicr = adapter->interrupt_event; | |
2156 | ||
f0f9778d | 2157 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
2158 | return; |
2159 | ||
f0f9778d AD |
2160 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2161 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
2162 | return; | |
2163 | ||
2164 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2165 | ||
7ca647bd | 2166 | switch (hw->device_id) { |
f0f9778d AD |
2167 | case IXGBE_DEV_ID_82599_T3_LOM: |
2168 | /* | |
2169 | * Since the warning interrupt is for both ports | |
2170 | * we don't have to check if: | |
2171 | * - This interrupt wasn't for our port. | |
2172 | * - We may have missed the interrupt so always have to | |
2173 | * check if we got a LSC | |
2174 | */ | |
2175 | if (!(eicr & IXGBE_EICR_GPI_SDP0) && | |
2176 | !(eicr & IXGBE_EICR_LSC)) | |
2177 | return; | |
2178 | ||
2179 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
2180 | u32 autoneg; | |
2181 | bool link_up = false; | |
7ca647bd | 2182 | |
7ca647bd JP |
2183 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); |
2184 | ||
f0f9778d AD |
2185 | if (link_up) |
2186 | return; | |
2187 | } | |
2188 | ||
2189 | /* Check if this is not due to overtemp */ | |
2190 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2191 | return; | |
2192 | ||
2193 | break; | |
7ca647bd JP |
2194 | default: |
2195 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 2196 | return; |
7ca647bd | 2197 | break; |
119fc60a | 2198 | } |
7ca647bd JP |
2199 | e_crit(drv, |
2200 | "Network adapter has been stopped because it has over heated. " | |
2201 | "Restart the computer. If the problem persists, " | |
2202 | "power off the system and replace the adapter\n"); | |
f0f9778d AD |
2203 | |
2204 | adapter->interrupt_event = 0; | |
119fc60a MC |
2205 | } |
2206 | ||
0befdb3e JB |
2207 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2208 | { | |
2209 | struct ixgbe_hw *hw = &adapter->hw; | |
2210 | ||
2211 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
2212 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 2213 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
2214 | /* write to clear the interrupt */ |
2215 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
2216 | } | |
2217 | } | |
cf8280ee | 2218 | |
4f51bf70 JK |
2219 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2220 | { | |
2221 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) | |
2222 | return; | |
2223 | ||
2224 | switch (adapter->hw.mac.type) { | |
2225 | case ixgbe_mac_82599EB: | |
2226 | /* | |
2227 | * Need to check link state so complete overtemp check | |
2228 | * on service task | |
2229 | */ | |
2230 | if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && | |
2231 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { | |
2232 | adapter->interrupt_event = eicr; | |
2233 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2234 | ixgbe_service_event_schedule(adapter); | |
2235 | return; | |
2236 | } | |
2237 | return; | |
2238 | case ixgbe_mac_X540: | |
2239 | if (!(eicr & IXGBE_EICR_TS)) | |
2240 | return; | |
2241 | break; | |
2242 | default: | |
2243 | return; | |
2244 | } | |
2245 | ||
2246 | e_crit(drv, | |
2247 | "Network adapter has been stopped because it has over heated. " | |
2248 | "Restart the computer. If the problem persists, " | |
2249 | "power off the system and replace the adapter\n"); | |
2250 | } | |
2251 | ||
e8e26350 PW |
2252 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2253 | { | |
2254 | struct ixgbe_hw *hw = &adapter->hw; | |
2255 | ||
73c4b7cd AD |
2256 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
2257 | /* Clear the interrupt */ | |
2258 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
7086400d AD |
2259 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2260 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
2261 | ixgbe_service_event_schedule(adapter); | |
2262 | } | |
73c4b7cd AD |
2263 | } |
2264 | ||
e8e26350 PW |
2265 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
2266 | /* Clear the interrupt */ | |
2267 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
7086400d AD |
2268 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2269 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2270 | ixgbe_service_event_schedule(adapter); | |
2271 | } | |
e8e26350 PW |
2272 | } |
2273 | } | |
2274 | ||
cf8280ee JB |
2275 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2276 | { | |
2277 | struct ixgbe_hw *hw = &adapter->hw; | |
2278 | ||
2279 | adapter->lsc_int++; | |
2280 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2281 | adapter->link_check_timeout = jiffies; | |
2282 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2283 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2284 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2285 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2286 | } |
2287 | } | |
2288 | ||
fe49f04a AD |
2289 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2290 | u64 qmask) | |
2291 | { | |
2292 | u32 mask; | |
bd508178 | 2293 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2294 | |
bd508178 AD |
2295 | switch (hw->mac.type) { |
2296 | case ixgbe_mac_82598EB: | |
fe49f04a | 2297 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2298 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2299 | break; | |
2300 | case ixgbe_mac_82599EB: | |
b93a2226 | 2301 | case ixgbe_mac_X540: |
fe49f04a | 2302 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2303 | if (mask) |
2304 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2305 | mask = (qmask >> 32); |
bd508178 AD |
2306 | if (mask) |
2307 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2308 | break; | |
2309 | default: | |
2310 | break; | |
fe49f04a AD |
2311 | } |
2312 | /* skip the flush */ | |
2313 | } | |
2314 | ||
2315 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2316 | u64 qmask) |
fe49f04a AD |
2317 | { |
2318 | u32 mask; | |
bd508178 | 2319 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2320 | |
bd508178 AD |
2321 | switch (hw->mac.type) { |
2322 | case ixgbe_mac_82598EB: | |
fe49f04a | 2323 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2324 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2325 | break; | |
2326 | case ixgbe_mac_82599EB: | |
b93a2226 | 2327 | case ixgbe_mac_X540: |
fe49f04a | 2328 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2329 | if (mask) |
2330 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2331 | mask = (qmask >> 32); |
bd508178 AD |
2332 | if (mask) |
2333 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2334 | break; | |
2335 | default: | |
2336 | break; | |
fe49f04a AD |
2337 | } |
2338 | /* skip the flush */ | |
2339 | } | |
2340 | ||
021230d4 | 2341 | /** |
2c4af694 AD |
2342 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2343 | * @adapter: board private structure | |
021230d4 | 2344 | **/ |
2c4af694 AD |
2345 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2346 | bool flush) | |
9a799d71 | 2347 | { |
2c4af694 | 2348 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2349 | |
2c4af694 AD |
2350 | /* don't reenable LSC while waiting for link */ |
2351 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2352 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2353 | |
2c4af694 | 2354 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2355 | switch (adapter->hw.mac.type) { |
2356 | case ixgbe_mac_82599EB: | |
2357 | mask |= IXGBE_EIMS_GPI_SDP0; | |
2358 | break; | |
2359 | case ixgbe_mac_X540: | |
2360 | mask |= IXGBE_EIMS_TS; | |
2361 | break; | |
2362 | default: | |
2363 | break; | |
2364 | } | |
2c4af694 AD |
2365 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2366 | mask |= IXGBE_EIMS_GPI_SDP1; | |
2367 | switch (adapter->hw.mac.type) { | |
2368 | case ixgbe_mac_82599EB: | |
2c4af694 AD |
2369 | mask |= IXGBE_EIMS_GPI_SDP1; |
2370 | mask |= IXGBE_EIMS_GPI_SDP2; | |
858bc081 DS |
2371 | case ixgbe_mac_X540: |
2372 | mask |= IXGBE_EIMS_ECC; | |
2c4af694 AD |
2373 | mask |= IXGBE_EIMS_MAILBOX; |
2374 | break; | |
2375 | default: | |
2376 | break; | |
9a799d71 | 2377 | } |
db0677fa | 2378 | |
db0677fa JK |
2379 | if (adapter->hw.mac.type == ixgbe_mac_X540) |
2380 | mask |= IXGBE_EIMS_TIMESYNC; | |
db0677fa | 2381 | |
2c4af694 AD |
2382 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2383 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2384 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2385 | |
2c4af694 AD |
2386 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2387 | if (queues) | |
2388 | ixgbe_irq_enable_queues(adapter, ~0); | |
2389 | if (flush) | |
2390 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2391 | } |
2392 | ||
2c4af694 | 2393 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2394 | { |
a65151ba | 2395 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2396 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2397 | u32 eicr; |
91281fd3 | 2398 | |
54037505 DS |
2399 | /* |
2400 | * Workaround for Silicon errata. Use clear-by-write instead | |
2401 | * of clear-by-read. Reading with EICS will return the | |
2402 | * interrupt causes without clearing, which later be done | |
2403 | * with the write to EICR. | |
2404 | */ | |
2405 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
2406 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
33cf09c9 | 2407 | |
cf8280ee JB |
2408 | if (eicr & IXGBE_EICR_LSC) |
2409 | ixgbe_check_lsc(adapter); | |
f0848276 | 2410 | |
1cdd1ec8 GR |
2411 | if (eicr & IXGBE_EICR_MAILBOX) |
2412 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2413 | |
bd508178 AD |
2414 | switch (hw->mac.type) { |
2415 | case ixgbe_mac_82599EB: | |
b93a2226 | 2416 | case ixgbe_mac_X540: |
2c4af694 AD |
2417 | if (eicr & IXGBE_EICR_ECC) |
2418 | e_info(link, "Received unrecoverable ECC Err, please " | |
2419 | "reboot\n"); | |
c4cf55e5 PWJ |
2420 | /* Handle Flow Director Full threshold interrupt */ |
2421 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2422 | int reinit_count = 0; |
c4cf55e5 | 2423 | int i; |
c4cf55e5 | 2424 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2425 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2426 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2427 | &ring->state)) |
2428 | reinit_count++; | |
2429 | } | |
2430 | if (reinit_count) { | |
2431 | /* no more flow director interrupts until after init */ | |
2432 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
2433 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
2434 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
2435 | } |
2436 | } | |
f0f9778d | 2437 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 2438 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2439 | break; |
2440 | default: | |
2441 | break; | |
c4cf55e5 | 2442 | } |
f0848276 | 2443 | |
bd508178 | 2444 | ixgbe_check_fan_failure(adapter, eicr); |
db0677fa | 2445 | |
db0677fa JK |
2446 | if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) |
2447 | ixgbe_ptp_check_pps_event(adapter, eicr); | |
efe3d3c8 | 2448 | |
7086400d | 2449 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 2450 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 2451 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 2452 | |
9a799d71 | 2453 | return IRQ_HANDLED; |
f0848276 | 2454 | } |
91281fd3 | 2455 | |
4ff7fb12 | 2456 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 2457 | { |
021230d4 | 2458 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 2459 | |
9b471446 | 2460 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2461 | |
4ff7fb12 AD |
2462 | if (q_vector->rx.ring || q_vector->tx.ring) |
2463 | napi_schedule(&q_vector->napi); | |
91281fd3 | 2464 | |
9a799d71 | 2465 | return IRQ_HANDLED; |
91281fd3 AD |
2466 | } |
2467 | ||
eb01b975 AD |
2468 | /** |
2469 | * ixgbe_poll - NAPI Rx polling callback | |
2470 | * @napi: structure for representing this polling device | |
2471 | * @budget: how many packets driver is allowed to clean | |
2472 | * | |
2473 | * This function is used for legacy and MSI, NAPI mode | |
2474 | **/ | |
8af3c33f | 2475 | int ixgbe_poll(struct napi_struct *napi, int budget) |
eb01b975 AD |
2476 | { |
2477 | struct ixgbe_q_vector *q_vector = | |
2478 | container_of(napi, struct ixgbe_q_vector, napi); | |
2479 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2480 | struct ixgbe_ring *ring; | |
2481 | int per_ring_budget; | |
2482 | bool clean_complete = true; | |
2483 | ||
2484 | #ifdef CONFIG_IXGBE_DCA | |
2485 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2486 | ixgbe_update_dca(q_vector); | |
2487 | #endif | |
2488 | ||
2489 | ixgbe_for_each_ring(ring, q_vector->tx) | |
2490 | clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); | |
2491 | ||
2492 | /* attempt to distribute budget to each queue fairly, but don't allow | |
2493 | * the budget to go below 1 because we'll exit polling */ | |
2494 | if (q_vector->rx.count > 1) | |
2495 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
2496 | else | |
2497 | per_ring_budget = budget; | |
2498 | ||
2499 | ixgbe_for_each_ring(ring, q_vector->rx) | |
2500 | clean_complete &= ixgbe_clean_rx_irq(q_vector, ring, | |
2501 | per_ring_budget); | |
2502 | ||
2503 | /* If all work not completed, return budget and keep polling */ | |
2504 | if (!clean_complete) | |
2505 | return budget; | |
2506 | ||
2507 | /* all work done, exit the polling mode */ | |
2508 | napi_complete(napi); | |
2509 | if (adapter->rx_itr_setting & 1) | |
2510 | ixgbe_set_itr(q_vector); | |
2511 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2512 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
2513 | ||
2514 | return 0; | |
2515 | } | |
2516 | ||
021230d4 AV |
2517 | /** |
2518 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2519 | * @adapter: board private structure | |
2520 | * | |
2521 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2522 | * interrupts from the kernel. | |
2523 | **/ | |
2524 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2525 | { | |
2526 | struct net_device *netdev = adapter->netdev; | |
207867f5 | 2527 | int vector, err; |
e8e9f696 | 2528 | int ri = 0, ti = 0; |
021230d4 | 2529 | |
49c7ffbe | 2530 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
d0759ebb | 2531 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2532 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2533 | |
4ff7fb12 | 2534 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2535 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2536 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2537 | ti++; | |
2538 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2539 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2540 | "%s-%s-%d", netdev->name, "rx", ri++); |
2541 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2542 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2543 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2544 | } else { |
2545 | /* skip this unused q_vector */ | |
2546 | continue; | |
32aa77a4 | 2547 | } |
207867f5 AD |
2548 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2549 | q_vector->name, q_vector); | |
9a799d71 | 2550 | if (err) { |
396e799c | 2551 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2552 | "Error: %d\n", err); |
021230d4 | 2553 | goto free_queue_irqs; |
9a799d71 | 2554 | } |
207867f5 AD |
2555 | /* If Flow Director is enabled, set interrupt affinity */ |
2556 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2557 | /* assign the mask for this irq */ | |
2558 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 2559 | &q_vector->affinity_mask); |
207867f5 | 2560 | } |
9a799d71 AK |
2561 | } |
2562 | ||
021230d4 | 2563 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2564 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2565 | if (err) { |
de88eeeb | 2566 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 2567 | goto free_queue_irqs; |
9a799d71 AK |
2568 | } |
2569 | ||
9a799d71 AK |
2570 | return 0; |
2571 | ||
021230d4 | 2572 | free_queue_irqs: |
207867f5 AD |
2573 | while (vector) { |
2574 | vector--; | |
2575 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2576 | NULL); | |
2577 | free_irq(adapter->msix_entries[vector].vector, | |
2578 | adapter->q_vector[vector]); | |
2579 | } | |
021230d4 AV |
2580 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2581 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2582 | kfree(adapter->msix_entries); |
2583 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2584 | return err; |
2585 | } | |
2586 | ||
2587 | /** | |
021230d4 | 2588 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2589 | * @irq: interrupt number |
2590 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2591 | **/ |
2592 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2593 | { | |
a65151ba | 2594 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2595 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2596 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2597 | u32 eicr; |
2598 | ||
54037505 | 2599 | /* |
24ddd967 | 2600 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
2601 | * before the read of EICR. |
2602 | */ | |
2603 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2604 | ||
021230d4 | 2605 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 2606 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 2607 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 2608 | if (!eicr) { |
6af3b9eb ET |
2609 | /* |
2610 | * shared interrupt alert! | |
f47cf66e | 2611 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2612 | * have disabled interrupts due to EIAM |
2613 | * finish the workaround of silicon errata on 82598. Unmask | |
2614 | * the interrupt that we masked before the EICR read. | |
2615 | */ | |
2616 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2617 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2618 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2619 | } |
9a799d71 | 2620 | |
cf8280ee JB |
2621 | if (eicr & IXGBE_EICR_LSC) |
2622 | ixgbe_check_lsc(adapter); | |
021230d4 | 2623 | |
bd508178 AD |
2624 | switch (hw->mac.type) { |
2625 | case ixgbe_mac_82599EB: | |
e8e26350 | 2626 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
2627 | /* Fall through */ |
2628 | case ixgbe_mac_X540: | |
2629 | if (eicr & IXGBE_EICR_ECC) | |
2630 | e_info(link, "Received unrecoverable ECC err, please " | |
2631 | "reboot\n"); | |
4f51bf70 | 2632 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2633 | break; |
2634 | default: | |
2635 | break; | |
2636 | } | |
e8e26350 | 2637 | |
0befdb3e | 2638 | ixgbe_check_fan_failure(adapter, eicr); |
db0677fa JK |
2639 | if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) |
2640 | ixgbe_ptp_check_pps_event(adapter, eicr); | |
0befdb3e | 2641 | |
b9f6ed2b AD |
2642 | /* would disable interrupts here but EIAM disabled it */ |
2643 | napi_schedule(&q_vector->napi); | |
9a799d71 | 2644 | |
6af3b9eb ET |
2645 | /* |
2646 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2647 | * ixgbe_poll will re-enable the queue interrupts | |
2648 | */ | |
6af3b9eb ET |
2649 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2650 | ixgbe_irq_enable(adapter, false, false); | |
2651 | ||
9a799d71 AK |
2652 | return IRQ_HANDLED; |
2653 | } | |
2654 | ||
2655 | /** | |
2656 | * ixgbe_request_irq - initialize interrupts | |
2657 | * @adapter: board private structure | |
2658 | * | |
2659 | * Attempts to configure interrupts using the best available | |
2660 | * capabilities of the hardware and kernel. | |
2661 | **/ | |
021230d4 | 2662 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2663 | { |
2664 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2665 | int err; |
9a799d71 | 2666 | |
4cc6df29 | 2667 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 2668 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 2669 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 2670 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 2671 | netdev->name, adapter); |
4cc6df29 | 2672 | else |
a0607fd3 | 2673 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 2674 | netdev->name, adapter); |
9a799d71 | 2675 | |
de88eeeb | 2676 | if (err) |
396e799c | 2677 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2678 | |
9a799d71 AK |
2679 | return err; |
2680 | } | |
2681 | ||
2682 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2683 | { | |
49c7ffbe | 2684 | int vector; |
9a799d71 | 2685 | |
49c7ffbe AD |
2686 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2687 | free_irq(adapter->pdev->irq, adapter); | |
2688 | return; | |
2689 | } | |
4cc6df29 | 2690 | |
49c7ffbe AD |
2691 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
2692 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; | |
2693 | struct msix_entry *entry = &adapter->msix_entries[vector]; | |
894ff7cf | 2694 | |
49c7ffbe AD |
2695 | /* free only the irqs that were actually requested */ |
2696 | if (!q_vector->rx.ring && !q_vector->tx.ring) | |
2697 | continue; | |
207867f5 | 2698 | |
49c7ffbe AD |
2699 | /* clear the affinity_mask in the IRQ descriptor */ |
2700 | irq_set_affinity_hint(entry->vector, NULL); | |
2701 | ||
2702 | free_irq(entry->vector, q_vector); | |
9a799d71 | 2703 | } |
49c7ffbe AD |
2704 | |
2705 | free_irq(adapter->msix_entries[vector++].vector, adapter); | |
9a799d71 AK |
2706 | } |
2707 | ||
22d5a71b JB |
2708 | /** |
2709 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2710 | * @adapter: board private structure | |
2711 | **/ | |
2712 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2713 | { | |
bd508178 AD |
2714 | switch (adapter->hw.mac.type) { |
2715 | case ixgbe_mac_82598EB: | |
835462fc | 2716 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2717 | break; |
2718 | case ixgbe_mac_82599EB: | |
b93a2226 | 2719 | case ixgbe_mac_X540: |
835462fc NS |
2720 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2721 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2722 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
2723 | break; |
2724 | default: | |
2725 | break; | |
22d5a71b JB |
2726 | } |
2727 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2728 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
49c7ffbe AD |
2729 | int vector; |
2730 | ||
2731 | for (vector = 0; vector < adapter->num_q_vectors; vector++) | |
2732 | synchronize_irq(adapter->msix_entries[vector].vector); | |
2733 | ||
2734 | synchronize_irq(adapter->msix_entries[vector++].vector); | |
22d5a71b JB |
2735 | } else { |
2736 | synchronize_irq(adapter->pdev->irq); | |
2737 | } | |
2738 | } | |
2739 | ||
9a799d71 AK |
2740 | /** |
2741 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2742 | * | |
2743 | **/ | |
2744 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2745 | { | |
d5bf4f67 | 2746 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 2747 | |
d5bf4f67 | 2748 | ixgbe_write_eitr(q_vector); |
9a799d71 | 2749 | |
e8e26350 PW |
2750 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2751 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 2752 | |
396e799c | 2753 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2754 | } |
2755 | ||
43e69bf0 AD |
2756 | /** |
2757 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2758 | * @adapter: board private structure | |
2759 | * @ring: structure containing ring specific data | |
2760 | * | |
2761 | * Configure the Tx descriptor ring after a reset. | |
2762 | **/ | |
84418e3b AD |
2763 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2764 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2765 | { |
2766 | struct ixgbe_hw *hw = &adapter->hw; | |
2767 | u64 tdba = ring->dma; | |
2f1860b8 | 2768 | int wait_loop = 10; |
b88c6de2 | 2769 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 2770 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2771 | |
2f1860b8 | 2772 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 2773 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
2774 | IXGBE_WRITE_FLUSH(hw); |
2775 | ||
43e69bf0 | 2776 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2777 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2778 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2779 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2780 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2781 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2782 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2783 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2784 | |
b88c6de2 AD |
2785 | /* |
2786 | * set WTHRESH to encourage burst writeback, it should not be set | |
2787 | * higher than 1 when ITR is 0 as it could cause false TX hangs | |
2788 | * | |
2789 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
2790 | * to or less than the number of on chip descriptors, which is | |
2791 | * currently 40. | |
2792 | */ | |
e954b374 | 2793 | if (!ring->q_vector || (ring->q_vector->itr < 8)) |
b88c6de2 AD |
2794 | txdctl |= (1 << 16); /* WTHRESH = 1 */ |
2795 | else | |
2796 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
2797 | ||
e954b374 AD |
2798 | /* |
2799 | * Setting PTHRESH to 32 both improves performance | |
2800 | * and avoids a TX hang with DFP enabled | |
2801 | */ | |
b88c6de2 AD |
2802 | txdctl |= (1 << 8) | /* HTHRESH = 1 */ |
2803 | 32; /* PTHRESH = 32 */ | |
2f1860b8 AD |
2804 | |
2805 | /* reinitialize flowdirector state */ | |
39cb681b | 2806 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
ee9e0f0b AD |
2807 | ring->atr_sample_rate = adapter->atr_sample_rate; |
2808 | ring->atr_count = 0; | |
2809 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2810 | } else { | |
2811 | ring->atr_sample_rate = 0; | |
2812 | } | |
2f1860b8 | 2813 | |
c84d324c JF |
2814 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2815 | ||
2f1860b8 | 2816 | /* enable queue */ |
2f1860b8 AD |
2817 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
2818 | ||
2819 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2820 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2821 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2822 | return; | |
2823 | ||
2824 | /* poll to verify queue is enabled */ | |
2825 | do { | |
032b4325 | 2826 | usleep_range(1000, 2000); |
2f1860b8 AD |
2827 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2828 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2829 | if (!wait_loop) | |
2830 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2831 | } |
2832 | ||
120ff942 AD |
2833 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2834 | { | |
2835 | struct ixgbe_hw *hw = &adapter->hw; | |
671c0adb | 2836 | u32 rttdcs, mtqc; |
8b1c0b24 | 2837 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
2838 | |
2839 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2840 | return; | |
2841 | ||
2842 | /* disable the arbiter while setting MTQC */ | |
2843 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2844 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2845 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2846 | ||
2847 | /* set transmit pool layout */ | |
671c0adb AD |
2848 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
2849 | mtqc = IXGBE_MTQC_VT_ENA; | |
2850 | if (tcs > 4) | |
2851 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
2852 | else if (tcs > 1) | |
2853 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
2854 | else if (adapter->ring_feature[RING_F_RSS].indices == 4) | |
2855 | mtqc |= IXGBE_MTQC_32VF; | |
2856 | else | |
2857 | mtqc |= IXGBE_MTQC_64VF; | |
2858 | } else { | |
2859 | if (tcs > 4) | |
2860 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
2861 | else if (tcs > 1) | |
2862 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
8b1c0b24 | 2863 | else |
671c0adb AD |
2864 | mtqc = IXGBE_MTQC_64Q_1PB; |
2865 | } | |
120ff942 | 2866 | |
671c0adb | 2867 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); |
120ff942 | 2868 | |
671c0adb AD |
2869 | /* Enable Security TX Buffer IFG for multiple pb */ |
2870 | if (tcs) { | |
2871 | u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
2872 | sectx |= IXGBE_SECTX_DCB; | |
2873 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); | |
120ff942 AD |
2874 | } |
2875 | ||
2876 | /* re-enable the arbiter */ | |
2877 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2878 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2879 | } | |
2880 | ||
9a799d71 | 2881 | /** |
3a581073 | 2882 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2883 | * @adapter: board private structure |
2884 | * | |
2885 | * Configure the Tx unit of the MAC after a reset. | |
2886 | **/ | |
2887 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2888 | { | |
2f1860b8 AD |
2889 | struct ixgbe_hw *hw = &adapter->hw; |
2890 | u32 dmatxctl; | |
43e69bf0 | 2891 | u32 i; |
9a799d71 | 2892 | |
2f1860b8 AD |
2893 | ixgbe_setup_mtqc(adapter); |
2894 | ||
2895 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2896 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2897 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2898 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2899 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2900 | } | |
2901 | ||
9a799d71 | 2902 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2903 | for (i = 0; i < adapter->num_tx_queues; i++) |
2904 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2905 | } |
2906 | ||
3ebe8fde AD |
2907 | static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, |
2908 | struct ixgbe_ring *ring) | |
2909 | { | |
2910 | struct ixgbe_hw *hw = &adapter->hw; | |
2911 | u8 reg_idx = ring->reg_idx; | |
2912 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
2913 | ||
2914 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
2915 | ||
2916 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
2917 | } | |
2918 | ||
2919 | static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, | |
2920 | struct ixgbe_ring *ring) | |
2921 | { | |
2922 | struct ixgbe_hw *hw = &adapter->hw; | |
2923 | u8 reg_idx = ring->reg_idx; | |
2924 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
2925 | ||
2926 | srrctl &= ~IXGBE_SRRCTL_DROP_EN; | |
2927 | ||
2928 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
2929 | } | |
2930 | ||
2931 | #ifdef CONFIG_IXGBE_DCB | |
2932 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
2933 | #else | |
2934 | static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
2935 | #endif | |
2936 | { | |
2937 | int i; | |
2938 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
2939 | ||
2940 | if (adapter->ixgbe_ieee_pfc) | |
2941 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
2942 | ||
2943 | /* | |
2944 | * We should set the drop enable bit if: | |
2945 | * SR-IOV is enabled | |
2946 | * or | |
2947 | * Number of Rx queues > 1 and flow control is disabled | |
2948 | * | |
2949 | * This allows us to avoid head of line blocking for security | |
2950 | * and performance reasons. | |
2951 | */ | |
2952 | if (adapter->num_vfs || (adapter->num_rx_queues > 1 && | |
2953 | !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { | |
2954 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2955 | ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); | |
2956 | } else { | |
2957 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2958 | ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); | |
2959 | } | |
2960 | } | |
2961 | ||
e8e26350 | 2962 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2963 | |
a6616b42 | 2964 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2965 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2966 | { |
45e9baa5 | 2967 | struct ixgbe_hw *hw = &adapter->hw; |
cc41ac7c | 2968 | u32 srrctl; |
bf29ee6c | 2969 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2970 | |
45e9baa5 AD |
2971 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2972 | u16 mask = adapter->ring_feature[RING_F_RSS].mask; | |
cc41ac7c | 2973 | |
45e9baa5 AD |
2974 | /* |
2975 | * if VMDq is not active we must program one srrctl register | |
2976 | * per RSS queue since we have enabled RDRXCTL.MVMEN | |
2977 | */ | |
2978 | reg_idx &= mask; | |
2979 | } | |
cc41ac7c | 2980 | |
45e9baa5 AD |
2981 | /* configure header buffer length, needed for RSC */ |
2982 | srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; | |
afafd5b0 | 2983 | |
45e9baa5 | 2984 | /* configure the packet buffer length */ |
f800326d | 2985 | srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; |
45e9baa5 AD |
2986 | |
2987 | /* configure descriptor type */ | |
f800326d | 2988 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 2989 | |
45e9baa5 | 2990 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2991 | } |
9a799d71 | 2992 | |
05abb126 | 2993 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2994 | { |
05abb126 AD |
2995 | struct ixgbe_hw *hw = &adapter->hw; |
2996 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2997 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2998 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2999 | u32 mrqc = 0, reta = 0; |
3000 | u32 rxcsum; | |
3001 | int i, j; | |
671c0adb AD |
3002 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; |
3003 | ||
671c0adb AD |
3004 | /* |
3005 | * Program table for at least 2 queues w/ SR-IOV so that VFs can | |
3006 | * make full use of any rings they may have. We will use the | |
3007 | * PSRTYPE register to control how many rings we use within the PF. | |
3008 | */ | |
3009 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) | |
3010 | rss_i = 2; | |
0cefafad | 3011 | |
05abb126 AD |
3012 | /* Fill out hash function seeds */ |
3013 | for (i = 0; i < 10; i++) | |
3014 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
3015 | ||
3016 | /* Fill out redirection table */ | |
3017 | for (i = 0, j = 0; i < 128; i++, j++) { | |
671c0adb | 3018 | if (j == rss_i) |
05abb126 AD |
3019 | j = 0; |
3020 | /* reta = 4-byte sliding window of | |
3021 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
3022 | reta = (reta << 8) | (j * 0x11); | |
3023 | if ((i & 3) == 3) | |
3024 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
3025 | } | |
0cefafad | 3026 | |
05abb126 AD |
3027 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
3028 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
3029 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
3030 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
3031 | ||
671c0adb | 3032 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
fbe7ca7f | 3033 | if (adapter->ring_feature[RING_F_RSS].mask) |
671c0adb | 3034 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 | 3035 | } else { |
671c0adb AD |
3036 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
3037 | ||
3038 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3039 | if (tcs > 4) | |
3040 | mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ | |
3041 | else if (tcs > 1) | |
3042 | mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ | |
3043 | else if (adapter->ring_feature[RING_F_RSS].indices == 4) | |
3044 | mrqc = IXGBE_MRQC_VMDQRSS32EN; | |
8b1c0b24 | 3045 | else |
671c0adb AD |
3046 | mrqc = IXGBE_MRQC_VMDQRSS64EN; |
3047 | } else { | |
3048 | if (tcs > 4) | |
8b1c0b24 | 3049 | mrqc = IXGBE_MRQC_RTRSS8TCEN; |
671c0adb AD |
3050 | else if (tcs > 1) |
3051 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
3052 | else | |
3053 | mrqc = IXGBE_MRQC_RSSEN; | |
8b1c0b24 | 3054 | } |
0cefafad JB |
3055 | } |
3056 | ||
05abb126 | 3057 | /* Perform hash on these packet types */ |
671c0adb AD |
3058 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
3059 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | | |
3060 | IXGBE_MRQC_RSS_FIELD_IPV6 | | |
3061 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
05abb126 | 3062 | |
ef6afc0c AD |
3063 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) |
3064 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; | |
3065 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) | |
3066 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
3067 | ||
05abb126 | 3068 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
0cefafad JB |
3069 | } |
3070 | ||
bb5a9ad2 NS |
3071 | /** |
3072 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
3073 | * @adapter: address of board private structure | |
3074 | * @index: index of ring to set | |
bb5a9ad2 | 3075 | **/ |
082757af | 3076 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 3077 | struct ixgbe_ring *ring) |
bb5a9ad2 | 3078 | { |
bb5a9ad2 | 3079 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 3080 | u32 rscctrl; |
bf29ee6c | 3081 | u8 reg_idx = ring->reg_idx; |
7367096a | 3082 | |
7d637bcc | 3083 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 3084 | return; |
bb5a9ad2 | 3085 | |
7367096a | 3086 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
3087 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
3088 | /* | |
3089 | * we must limit the number of descriptors so that the | |
3090 | * total size of max desc * buf_len is not greater | |
642c680e | 3091 | * than 65536 |
bb5a9ad2 | 3092 | */ |
f800326d | 3093 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; |
7367096a | 3094 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
3095 | } |
3096 | ||
9e10e045 AD |
3097 | #define IXGBE_MAX_RX_DESC_POLL 10 |
3098 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
3099 | struct ixgbe_ring *ring) | |
3100 | { | |
3101 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
3102 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
3103 | u32 rxdctl; | |
bf29ee6c | 3104 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
3105 | |
3106 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
3107 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3108 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3109 | return; | |
3110 | ||
3111 | do { | |
032b4325 | 3112 | usleep_range(1000, 2000); |
9e10e045 AD |
3113 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3114 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3115 | ||
3116 | if (!wait_loop) { | |
3117 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
3118 | "the polling period\n", reg_idx); | |
3119 | } | |
3120 | } | |
3121 | ||
2d39d576 YZ |
3122 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
3123 | struct ixgbe_ring *ring) | |
3124 | { | |
3125 | struct ixgbe_hw *hw = &adapter->hw; | |
3126 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
3127 | u32 rxdctl; | |
3128 | u8 reg_idx = ring->reg_idx; | |
3129 | ||
3130 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3131 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
3132 | ||
3133 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
3134 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3135 | ||
3136 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3137 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3138 | return; | |
3139 | ||
3140 | /* the hardware may take up to 100us to really disable the rx queue */ | |
3141 | do { | |
3142 | udelay(10); | |
3143 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3144 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3145 | ||
3146 | if (!wait_loop) { | |
3147 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
3148 | "the polling period\n", reg_idx); | |
3149 | } | |
3150 | } | |
3151 | ||
84418e3b AD |
3152 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
3153 | struct ixgbe_ring *ring) | |
acd37177 AD |
3154 | { |
3155 | struct ixgbe_hw *hw = &adapter->hw; | |
3156 | u64 rdba = ring->dma; | |
9e10e045 | 3157 | u32 rxdctl; |
bf29ee6c | 3158 | u8 reg_idx = ring->reg_idx; |
acd37177 | 3159 | |
9e10e045 AD |
3160 | /* disable queue to avoid issues while updating state */ |
3161 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 3162 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3163 | |
acd37177 AD |
3164 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3165 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3166 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3167 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
3168 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
3169 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 3170 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3171 | |
3172 | ixgbe_configure_srrctl(adapter, ring); | |
3173 | ixgbe_configure_rscctl(adapter, ring); | |
3174 | ||
3175 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
3176 | /* | |
3177 | * enable cache line friendly hardware writes: | |
3178 | * PTHRESH=32 descriptors (half the internal cache), | |
3179 | * this also removes ugly rx_no_buffer_count increment | |
3180 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3181 | * WTHRESH=8 burst writeback up to two cache lines | |
3182 | */ | |
3183 | rxdctl &= ~0x3FFFFF; | |
3184 | rxdctl |= 0x080420; | |
3185 | } | |
3186 | ||
3187 | /* enable receive descriptor ring */ | |
3188 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3189 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3190 | ||
3191 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 3192 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
3193 | } |
3194 | ||
48654521 AD |
3195 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3196 | { | |
3197 | struct ixgbe_hw *hw = &adapter->hw; | |
fbe7ca7f | 3198 | int rss_i = adapter->ring_feature[RING_F_RSS].indices; |
48654521 AD |
3199 | int p; |
3200 | ||
3201 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3202 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3203 | IXGBE_PSRTYPE_UDPHDR | |
3204 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3205 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3206 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3207 | |
3208 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3209 | return; | |
3210 | ||
fbe7ca7f AD |
3211 | if (rss_i > 3) |
3212 | psrtype |= 2 << 29; | |
3213 | else if (rss_i > 1) | |
3214 | psrtype |= 1 << 29; | |
48654521 AD |
3215 | |
3216 | for (p = 0; p < adapter->num_rx_pools; p++) | |
1d9c0bfd | 3217 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)), |
48654521 AD |
3218 | psrtype); |
3219 | } | |
3220 | ||
f5b4a52e AD |
3221 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3222 | { | |
3223 | struct ixgbe_hw *hw = &adapter->hw; | |
f5b4a52e | 3224 | u32 reg_offset, vf_shift; |
435b19f6 | 3225 | u32 gcr_ext, vmdctl; |
de4c7f65 | 3226 | int i; |
f5b4a52e AD |
3227 | |
3228 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3229 | return; | |
3230 | ||
3231 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
435b19f6 AD |
3232 | vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; |
3233 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
1d9c0bfd | 3234 | vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; |
435b19f6 AD |
3235 | vmdctl |= IXGBE_VT_CTL_REPLEN; |
3236 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
f5b4a52e | 3237 | |
1d9c0bfd AD |
3238 | vf_shift = VMDQ_P(0) % 32; |
3239 | reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; | |
f5b4a52e AD |
3240 | |
3241 | /* Enable only the PF's pool for Tx/Rx */ | |
435b19f6 AD |
3242 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); |
3243 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); | |
3244 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); | |
3245 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); | |
9b735984 GR |
3246 | if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) |
3247 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
f5b4a52e AD |
3248 | |
3249 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
1d9c0bfd | 3250 | hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); |
f5b4a52e AD |
3251 | |
3252 | /* | |
3253 | * Set up VF register offsets for selected VT Mode, | |
3254 | * i.e. 32 or 64 VFs for SR-IOV | |
3255 | */ | |
73079ea0 AD |
3256 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { |
3257 | case IXGBE_82599_VMDQ_8Q_MASK: | |
3258 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; | |
3259 | break; | |
3260 | case IXGBE_82599_VMDQ_4Q_MASK: | |
3261 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; | |
3262 | break; | |
3263 | default: | |
3264 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; | |
3265 | break; | |
3266 | } | |
3267 | ||
f5b4a52e AD |
3268 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); |
3269 | ||
435b19f6 | 3270 | |
a985b6c3 | 3271 | /* Enable MAC Anti-Spoofing */ |
435b19f6 | 3272 | hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), |
a985b6c3 | 3273 | adapter->num_vfs); |
de4c7f65 GR |
3274 | /* For VFs that have spoof checking turned off */ |
3275 | for (i = 0; i < adapter->num_vfs; i++) { | |
3276 | if (!adapter->vfinfo[i].spoofchk_enabled) | |
3277 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); | |
3278 | } | |
f5b4a52e AD |
3279 | } |
3280 | ||
477de6ed | 3281 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3282 | { |
9a799d71 AK |
3283 | struct ixgbe_hw *hw = &adapter->hw; |
3284 | struct net_device *netdev = adapter->netdev; | |
3285 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
3286 | struct ixgbe_ring *rx_ring; |
3287 | int i; | |
3288 | u32 mhadd, hlreg0; | |
48654521 | 3289 | |
63f39bd1 | 3290 | #ifdef IXGBE_FCOE |
477de6ed AD |
3291 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3292 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3293 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3294 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3295 | |
477de6ed | 3296 | #endif /* IXGBE_FCOE */ |
872844dd AD |
3297 | |
3298 | /* adjust max frame to be at least the size of a standard frame */ | |
3299 | if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) | |
3300 | max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); | |
3301 | ||
477de6ed AD |
3302 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
3303 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3304 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3305 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3306 | ||
3307 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3308 | } | |
3309 | ||
3310 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
3311 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3312 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3313 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3314 | |
0cefafad JB |
3315 | /* |
3316 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3317 | * the Base and Length of the Rx Descriptor Ring | |
3318 | */ | |
9a799d71 | 3319 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3320 | rx_ring = adapter->rx_ring[i]; |
7d637bcc AD |
3321 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
3322 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3323 | else |
7d637bcc | 3324 | clear_ring_rsc_enabled(rx_ring); |
477de6ed | 3325 | } |
477de6ed AD |
3326 | } |
3327 | ||
7367096a AD |
3328 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3329 | { | |
3330 | struct ixgbe_hw *hw = &adapter->hw; | |
3331 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3332 | ||
3333 | switch (hw->mac.type) { | |
3334 | case ixgbe_mac_82598EB: | |
3335 | /* | |
3336 | * For VMDq support of different descriptor types or | |
3337 | * buffer sizes through the use of multiple SRRCTL | |
3338 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3339 | * | |
3340 | * also, the manual doesn't mention it clearly but DCA hints | |
3341 | * will only use queue 0's tags unless this bit is set. Side | |
3342 | * effects of setting this bit are only that SRRCTL must be | |
3343 | * fully programmed [0..15] | |
3344 | */ | |
3345 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3346 | break; | |
3347 | case ixgbe_mac_82599EB: | |
b93a2226 | 3348 | case ixgbe_mac_X540: |
7367096a AD |
3349 | /* Disable RSC for ACK packets */ |
3350 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3351 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3352 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3353 | /* hardware requires some bits to be set by default */ | |
3354 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3355 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3356 | break; | |
3357 | default: | |
3358 | /* We should do nothing since we don't know this hardware */ | |
3359 | return; | |
3360 | } | |
3361 | ||
3362 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3363 | } | |
3364 | ||
477de6ed AD |
3365 | /** |
3366 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3367 | * @adapter: board private structure | |
3368 | * | |
3369 | * Configure the Rx unit of the MAC after a reset. | |
3370 | **/ | |
3371 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3372 | { | |
3373 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3374 | int i; |
3375 | u32 rxctrl; | |
477de6ed AD |
3376 | |
3377 | /* disable receives while setting up the descriptors */ | |
3378 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3379 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3380 | ||
3381 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3382 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3383 | |
9e10e045 | 3384 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3385 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3386 | |
477de6ed AD |
3387 | /* set_rx_buffer_len must be called before ring initialization */ |
3388 | ixgbe_set_rx_buffer_len(adapter); | |
3389 | ||
3390 | /* | |
3391 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3392 | * the Base and Length of the Rx Descriptor Ring | |
3393 | */ | |
9e10e045 AD |
3394 | for (i = 0; i < adapter->num_rx_queues; i++) |
3395 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3396 | |
9e10e045 AD |
3397 | /* disable drop enable for 82598 parts */ |
3398 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3399 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3400 | ||
3401 | /* enable all receives */ | |
3402 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3403 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3404 | } |
3405 | ||
8e586137 | 3406 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3407 | { |
3408 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3409 | struct ixgbe_hw *hw = &adapter->hw; | |
3410 | ||
3411 | /* add VID to filter table */ | |
1d9c0bfd | 3412 | hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true); |
f62bbb5e | 3413 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
3414 | |
3415 | return 0; | |
068c89b0 DS |
3416 | } |
3417 | ||
8e586137 | 3418 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3419 | { |
3420 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3421 | struct ixgbe_hw *hw = &adapter->hw; | |
3422 | ||
068c89b0 | 3423 | /* remove VID from filter table */ |
1d9c0bfd | 3424 | hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false); |
f62bbb5e | 3425 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
3426 | |
3427 | return 0; | |
068c89b0 DS |
3428 | } |
3429 | ||
5f6c0181 JB |
3430 | /** |
3431 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3432 | * @adapter: driver data | |
3433 | */ | |
3434 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3435 | { | |
3436 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3437 | u32 vlnctrl; |
3438 | ||
3439 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3440 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3441 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3442 | } | |
3443 | ||
3444 | /** | |
3445 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3446 | * @adapter: driver data | |
3447 | */ | |
3448 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3449 | { | |
3450 | struct ixgbe_hw *hw = &adapter->hw; | |
3451 | u32 vlnctrl; | |
3452 | ||
3453 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3454 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3455 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3456 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3457 | } | |
3458 | ||
3459 | /** | |
3460 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3461 | * @adapter: driver data | |
3462 | */ | |
3463 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3464 | { | |
3465 | struct ixgbe_hw *hw = &adapter->hw; | |
3466 | u32 vlnctrl; | |
5f6c0181 JB |
3467 | int i, j; |
3468 | ||
3469 | switch (hw->mac.type) { | |
3470 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3471 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3472 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3473 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3474 | break; | |
3475 | case ixgbe_mac_82599EB: | |
b93a2226 | 3476 | case ixgbe_mac_X540: |
5f6c0181 JB |
3477 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3478 | j = adapter->rx_ring[i]->reg_idx; | |
3479 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3480 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3481 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3482 | } | |
3483 | break; | |
3484 | default: | |
3485 | break; | |
3486 | } | |
3487 | } | |
3488 | ||
3489 | /** | |
f62bbb5e | 3490 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3491 | * @adapter: driver data |
3492 | */ | |
f62bbb5e | 3493 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3494 | { |
3495 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3496 | u32 vlnctrl; |
5f6c0181 JB |
3497 | int i, j; |
3498 | ||
3499 | switch (hw->mac.type) { | |
3500 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3501 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3502 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3503 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3504 | break; | |
3505 | case ixgbe_mac_82599EB: | |
b93a2226 | 3506 | case ixgbe_mac_X540: |
5f6c0181 JB |
3507 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3508 | j = adapter->rx_ring[i]->reg_idx; | |
3509 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3510 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3511 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3512 | } | |
3513 | break; | |
3514 | default: | |
3515 | break; | |
3516 | } | |
3517 | } | |
3518 | ||
9a799d71 AK |
3519 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3520 | { | |
f62bbb5e | 3521 | u16 vid; |
9a799d71 | 3522 | |
f62bbb5e JG |
3523 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3524 | ||
3525 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3526 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3527 | } |
3528 | ||
2850062a AD |
3529 | /** |
3530 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3531 | * @netdev: network interface device structure | |
3532 | * | |
3533 | * Writes unicast address list to the RAR table. | |
3534 | * Returns: -ENOMEM on failure/insufficient address space | |
3535 | * 0 on no addresses written | |
3536 | * X on writing X addresses to the RAR table | |
3537 | **/ | |
3538 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3539 | { | |
3540 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3541 | struct ixgbe_hw *hw = &adapter->hw; | |
95447461 | 3542 | unsigned int rar_entries = hw->mac.num_rar_entries - 1; |
2850062a AD |
3543 | int count = 0; |
3544 | ||
95447461 JF |
3545 | /* In SR-IOV mode significantly less RAR entries are available */ |
3546 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3547 | rar_entries = IXGBE_MAX_PF_MACVLANS - 1; | |
3548 | ||
2850062a AD |
3549 | /* return ENOMEM indicating insufficient memory for addresses */ |
3550 | if (netdev_uc_count(netdev) > rar_entries) | |
3551 | return -ENOMEM; | |
3552 | ||
95447461 | 3553 | if (!netdev_uc_empty(netdev)) { |
2850062a AD |
3554 | struct netdev_hw_addr *ha; |
3555 | /* return error if we do not support writing to RAR table */ | |
3556 | if (!hw->mac.ops.set_rar) | |
3557 | return -ENOMEM; | |
3558 | ||
3559 | netdev_for_each_uc_addr(ha, netdev) { | |
3560 | if (!rar_entries) | |
3561 | break; | |
3562 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
1d9c0bfd | 3563 | VMDQ_P(0), IXGBE_RAH_AV); |
2850062a AD |
3564 | count++; |
3565 | } | |
3566 | } | |
3567 | /* write the addresses in reverse order to avoid write combining */ | |
3568 | for (; rar_entries > 0 ; rar_entries--) | |
3569 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3570 | ||
3571 | return count; | |
3572 | } | |
3573 | ||
9a799d71 | 3574 | /** |
2c5645cf | 3575 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3576 | * @netdev: network interface device structure |
3577 | * | |
2c5645cf CL |
3578 | * The set_rx_method entry point is called whenever the unicast/multicast |
3579 | * address list or the network interface flags are updated. This routine is | |
3580 | * responsible for configuring the hardware for proper unicast, multicast and | |
3581 | * promiscuous mode. | |
9a799d71 | 3582 | **/ |
7f870475 | 3583 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3584 | { |
3585 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3586 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3587 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3588 | int count; | |
9a799d71 AK |
3589 | |
3590 | /* Check for Promiscuous and All Multicast modes */ | |
3591 | ||
3592 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3593 | ||
f5dc442b | 3594 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 3595 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
3596 | fctrl |= IXGBE_FCTRL_BAM; |
3597 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3598 | fctrl |= IXGBE_FCTRL_PMCF; | |
3599 | ||
2850062a AD |
3600 | /* clear the bits we are changing the status of */ |
3601 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3602 | ||
9a799d71 | 3603 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3604 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3605 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3606 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3607 | /* don't hardware filter vlans in promisc mode */ |
3608 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3609 | } else { |
746b9f02 PM |
3610 | if (netdev->flags & IFF_ALLMULTI) { |
3611 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3612 | vmolr |= IXGBE_VMOLR_MPE; |
3613 | } else { | |
3614 | /* | |
3615 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3616 | * then we should just turn on promiscuous mode so |
2850062a AD |
3617 | * that we can at least receive multicast traffic |
3618 | */ | |
3619 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3620 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3621 | } |
5f6c0181 | 3622 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3623 | hw->addr_ctrl.user_set_promisc = false; |
9dcb373c JF |
3624 | } |
3625 | ||
3626 | /* | |
3627 | * Write addresses to available RAR registers, if there is not | |
3628 | * sufficient space to store all the addresses then enable | |
3629 | * unicast promiscuous mode | |
3630 | */ | |
3631 | count = ixgbe_write_uc_addr_list(netdev); | |
3632 | if (count < 0) { | |
3633 | fctrl |= IXGBE_FCTRL_UPE; | |
3634 | vmolr |= IXGBE_VMOLR_ROPE; | |
9a799d71 AK |
3635 | } |
3636 | ||
1d9c0bfd | 3637 | if (adapter->num_vfs) |
1cdd1ec8 | 3638 | ixgbe_restore_vf_multicasts(adapter); |
1d9c0bfd AD |
3639 | |
3640 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3641 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & | |
2850062a AD |
3642 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | |
3643 | IXGBE_VMOLR_ROPE); | |
1d9c0bfd | 3644 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); |
2850062a AD |
3645 | } |
3646 | ||
3f2d1c0f BG |
3647 | /* This is useful for sniffing bad packets. */ |
3648 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3649 | /* UPE and MPE will be handled by normal PROMISC logic | |
3650 | * in e1000e_set_rx_mode */ | |
3651 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
3652 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
3653 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3654 | ||
3655 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
3656 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
3657 | } | |
3658 | ||
2850062a | 3659 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e JG |
3660 | |
3661 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3662 | ixgbe_vlan_strip_enable(adapter); | |
3663 | else | |
3664 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3665 | } |
3666 | ||
021230d4 AV |
3667 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3668 | { | |
3669 | int q_idx; | |
021230d4 | 3670 | |
49c7ffbe AD |
3671 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) |
3672 | napi_enable(&adapter->q_vector[q_idx]->napi); | |
021230d4 AV |
3673 | } |
3674 | ||
3675 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3676 | { | |
3677 | int q_idx; | |
021230d4 | 3678 | |
49c7ffbe AD |
3679 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) |
3680 | napi_disable(&adapter->q_vector[q_idx]->napi); | |
021230d4 AV |
3681 | } |
3682 | ||
7a6b6f51 | 3683 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c | 3684 | /** |
2f90b865 AD |
3685 | * ixgbe_configure_dcb - Configure DCB hardware |
3686 | * @adapter: ixgbe adapter struct | |
3687 | * | |
3688 | * This is called by the driver on open to configure the DCB hardware. | |
3689 | * This is also called by the gennetlink interface when reconfiguring | |
3690 | * the DCB state. | |
3691 | */ | |
3692 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3693 | { | |
3694 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3695 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3696 | |
67ebd791 AD |
3697 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3698 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3699 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3700 | return; | |
3701 | } | |
3702 | ||
3703 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3704 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3705 | ||
971060b1 | 3706 | #ifdef IXGBE_FCOE |
b120818e JF |
3707 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
3708 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 3709 | #endif |
b120818e JF |
3710 | |
3711 | /* reconfigure the hardware */ | |
3712 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
3713 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
3714 | DCB_TX_CONFIG); | |
3715 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3716 | DCB_RX_CONFIG); | |
3717 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
3718 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
3719 | ixgbe_dcb_hw_ets(&adapter->hw, | |
3720 | adapter->ixgbe_ieee_ets, | |
3721 | max_frame); | |
3722 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
3723 | adapter->ixgbe_ieee_pfc->pfc_en, | |
3724 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 3725 | } |
8187cd48 JF |
3726 | |
3727 | /* Enable RSS Hash per TC */ | |
3728 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
4ae63730 AD |
3729 | u32 msb = 0; |
3730 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; | |
8187cd48 | 3731 | |
d411a936 AD |
3732 | while (rss_i) { |
3733 | msb++; | |
3734 | rss_i >>= 1; | |
3735 | } | |
8187cd48 | 3736 | |
4ae63730 AD |
3737 | /* write msb to all 8 TCs in one write */ |
3738 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); | |
8187cd48 | 3739 | } |
2f90b865 | 3740 | } |
9da712d2 JF |
3741 | #endif |
3742 | ||
3743 | /* Additional bittime to account for IXGBE framing */ | |
3744 | #define IXGBE_ETH_FRAMING 20 | |
3745 | ||
49ce9c2c | 3746 | /** |
9da712d2 JF |
3747 | * ixgbe_hpbthresh - calculate high water mark for flow control |
3748 | * | |
3749 | * @adapter: board private structure to calculate for | |
49ce9c2c | 3750 | * @pb: packet buffer to calculate |
9da712d2 JF |
3751 | */ |
3752 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
3753 | { | |
3754 | struct ixgbe_hw *hw = &adapter->hw; | |
3755 | struct net_device *dev = adapter->netdev; | |
3756 | int link, tc, kb, marker; | |
3757 | u32 dv_id, rx_pba; | |
3758 | ||
3759 | /* Calculate max LAN frame size */ | |
3760 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
3761 | ||
3762 | #ifdef IXGBE_FCOE | |
3763 | /* FCoE traffic class uses FCOE jumbo frames */ | |
800bd607 AD |
3764 | if ((dev->features & NETIF_F_FCOE_MTU) && |
3765 | (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
3766 | (pb == ixgbe_fcoe_get_tc(adapter))) | |
3767 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9da712d2 JF |
3768 | |
3769 | #endif | |
9da712d2 JF |
3770 | /* Calculate delay value for device */ |
3771 | switch (hw->mac.type) { | |
3772 | case ixgbe_mac_X540: | |
3773 | dv_id = IXGBE_DV_X540(link, tc); | |
3774 | break; | |
3775 | default: | |
3776 | dv_id = IXGBE_DV(link, tc); | |
3777 | break; | |
3778 | } | |
3779 | ||
3780 | /* Loopback switch introduces additional latency */ | |
3781 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3782 | dv_id += IXGBE_B2BT(tc); | |
3783 | ||
3784 | /* Delay value is calculated in bit times convert to KB */ | |
3785 | kb = IXGBE_BT2KB(dv_id); | |
3786 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
3787 | ||
3788 | marker = rx_pba - kb; | |
3789 | ||
3790 | /* It is possible that the packet buffer is not large enough | |
3791 | * to provide required headroom. In this case throw an error | |
3792 | * to user and a do the best we can. | |
3793 | */ | |
3794 | if (marker < 0) { | |
3795 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
3796 | "headroom to support flow control." | |
3797 | "Decrease MTU or number of traffic classes\n", pb); | |
3798 | marker = tc + 1; | |
3799 | } | |
3800 | ||
3801 | return marker; | |
3802 | } | |
3803 | ||
49ce9c2c | 3804 | /** |
9da712d2 JF |
3805 | * ixgbe_lpbthresh - calculate low water mark for for flow control |
3806 | * | |
3807 | * @adapter: board private structure to calculate for | |
49ce9c2c | 3808 | * @pb: packet buffer to calculate |
9da712d2 JF |
3809 | */ |
3810 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter) | |
3811 | { | |
3812 | struct ixgbe_hw *hw = &adapter->hw; | |
3813 | struct net_device *dev = adapter->netdev; | |
3814 | int tc; | |
3815 | u32 dv_id; | |
3816 | ||
3817 | /* Calculate max LAN frame size */ | |
3818 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
3819 | ||
3820 | /* Calculate delay value for device */ | |
3821 | switch (hw->mac.type) { | |
3822 | case ixgbe_mac_X540: | |
3823 | dv_id = IXGBE_LOW_DV_X540(tc); | |
3824 | break; | |
3825 | default: | |
3826 | dv_id = IXGBE_LOW_DV(tc); | |
3827 | break; | |
3828 | } | |
3829 | ||
3830 | /* Delay value is calculated in bit times convert to KB */ | |
3831 | return IXGBE_BT2KB(dv_id); | |
3832 | } | |
3833 | ||
3834 | /* | |
3835 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
3836 | */ | |
3837 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
3838 | { | |
3839 | struct ixgbe_hw *hw = &adapter->hw; | |
3840 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
3841 | int i; | |
3842 | ||
3843 | if (!num_tc) | |
3844 | num_tc = 1; | |
3845 | ||
3846 | hw->fc.low_water = ixgbe_lpbthresh(adapter); | |
3847 | ||
3848 | for (i = 0; i < num_tc; i++) { | |
3849 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
3850 | ||
3851 | /* Low water marks must not be larger than high water marks */ | |
3852 | if (hw->fc.low_water > hw->fc.high_water[i]) | |
3853 | hw->fc.low_water = 0; | |
3854 | } | |
3855 | } | |
3856 | ||
80605c65 JF |
3857 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
3858 | { | |
80605c65 | 3859 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
3860 | int hdrm; |
3861 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
3862 | |
3863 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3864 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
3865 | hdrm = 32 << adapter->fdir_pballoc; |
3866 | else | |
3867 | hdrm = 0; | |
80605c65 | 3868 | |
f7e1027f | 3869 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 3870 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
3871 | } |
3872 | ||
e4911d57 AD |
3873 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
3874 | { | |
3875 | struct ixgbe_hw *hw = &adapter->hw; | |
3876 | struct hlist_node *node, *node2; | |
3877 | struct ixgbe_fdir_filter *filter; | |
3878 | ||
3879 | spin_lock(&adapter->fdir_perfect_lock); | |
3880 | ||
3881 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
3882 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
3883 | ||
3884 | hlist_for_each_entry_safe(filter, node, node2, | |
3885 | &adapter->fdir_filter_list, fdir_node) { | |
3886 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
3887 | &filter->filter, |
3888 | filter->sw_idx, | |
3889 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
3890 | IXGBE_FDIR_DROP_QUEUE : | |
3891 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
3892 | } |
3893 | ||
3894 | spin_unlock(&adapter->fdir_perfect_lock); | |
3895 | } | |
3896 | ||
9a799d71 AK |
3897 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3898 | { | |
d2f5e7f3 AS |
3899 | struct ixgbe_hw *hw = &adapter->hw; |
3900 | ||
80605c65 | 3901 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 3902 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3903 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3904 | #endif |
b35d4d42 AD |
3905 | /* |
3906 | * We must restore virtualization before VLANs or else | |
3907 | * the VLVF registers will not be populated | |
3908 | */ | |
3909 | ixgbe_configure_virtualization(adapter); | |
9a799d71 | 3910 | |
4c1d7b4b | 3911 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
3912 | ixgbe_restore_vlan(adapter); |
3913 | ||
d2f5e7f3 AS |
3914 | switch (hw->mac.type) { |
3915 | case ixgbe_mac_82599EB: | |
3916 | case ixgbe_mac_X540: | |
3917 | hw->mac.ops.disable_rx_buff(hw); | |
3918 | break; | |
3919 | default: | |
3920 | break; | |
3921 | } | |
3922 | ||
c4cf55e5 | 3923 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
3924 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
3925 | adapter->fdir_pballoc); | |
e4911d57 AD |
3926 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
3927 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
3928 | adapter->fdir_pballoc); | |
3929 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 3930 | } |
4c1d7b4b | 3931 | |
d2f5e7f3 AS |
3932 | switch (hw->mac.type) { |
3933 | case ixgbe_mac_82599EB: | |
3934 | case ixgbe_mac_X540: | |
3935 | hw->mac.ops.enable_rx_buff(hw); | |
3936 | break; | |
3937 | default: | |
3938 | break; | |
3939 | } | |
3940 | ||
7c8ae65a AD |
3941 | #ifdef IXGBE_FCOE |
3942 | /* configure FCoE L2 filters, redirection table, and Rx control */ | |
3943 | ixgbe_configure_fcoe(adapter); | |
3944 | ||
3945 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
3946 | ixgbe_configure_tx(adapter); |
3947 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3948 | } |
3949 | ||
e8e26350 PW |
3950 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3951 | { | |
3952 | switch (hw->phy.type) { | |
3953 | case ixgbe_phy_sfp_avago: | |
3954 | case ixgbe_phy_sfp_ftl: | |
3955 | case ixgbe_phy_sfp_intel: | |
3956 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3957 | case ixgbe_phy_sfp_passive_tyco: |
3958 | case ixgbe_phy_sfp_passive_unknown: | |
3959 | case ixgbe_phy_sfp_active_unknown: | |
3960 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 | 3961 | return true; |
8917b447 AD |
3962 | case ixgbe_phy_nl: |
3963 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3964 | return true; | |
e8e26350 PW |
3965 | default: |
3966 | return false; | |
3967 | } | |
3968 | } | |
3969 | ||
0ecc061d | 3970 | /** |
e8e26350 PW |
3971 | * ixgbe_sfp_link_config - set up SFP+ link |
3972 | * @adapter: pointer to private adapter struct | |
3973 | **/ | |
3974 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3975 | { | |
7086400d | 3976 | /* |
52f33af8 | 3977 | * We are assuming the worst case scenario here, and that |
7086400d AD |
3978 | * is that an SFP was inserted/removed after the reset |
3979 | * but before SFP detection was enabled. As such the best | |
3980 | * solution is to just start searching as soon as we start | |
3981 | */ | |
3982 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3983 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 3984 | |
7086400d | 3985 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
e8e26350 PW |
3986 | } |
3987 | ||
3988 | /** | |
3989 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3990 | * @hw: pointer to private hardware struct |
3991 | * | |
3992 | * Returns 0 on success, negative on failure | |
3993 | **/ | |
e8e26350 | 3994 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3995 | { |
3996 | u32 autoneg; | |
8620a103 | 3997 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3998 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3999 | ||
4000 | if (hw->mac.ops.check_link) | |
4001 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
4002 | ||
4003 | if (ret) | |
4004 | goto link_cfg_out; | |
4005 | ||
0b0c2b31 ET |
4006 | autoneg = hw->phy.autoneg_advertised; |
4007 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
4008 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
4009 | &negotiation); | |
0ecc061d PWJ |
4010 | if (ret) |
4011 | goto link_cfg_out; | |
4012 | ||
8620a103 MC |
4013 | if (hw->mac.ops.setup_link) |
4014 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
4015 | link_cfg_out: |
4016 | return ret; | |
4017 | } | |
4018 | ||
a34bcfff | 4019 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 4020 | { |
9a799d71 | 4021 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 4022 | u32 gpie = 0; |
9a799d71 | 4023 | |
9b471446 | 4024 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
4025 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
4026 | IXGBE_GPIE_OCD; | |
4027 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
4028 | /* |
4029 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
4030 | * this saves a register write for every interrupt | |
4031 | */ | |
4032 | switch (hw->mac.type) { | |
4033 | case ixgbe_mac_82598EB: | |
4034 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
4035 | break; | |
9b471446 | 4036 | case ixgbe_mac_82599EB: |
b93a2226 DS |
4037 | case ixgbe_mac_X540: |
4038 | default: | |
9b471446 JB |
4039 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
4040 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
4041 | break; | |
4042 | } | |
4043 | } else { | |
021230d4 AV |
4044 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
4045 | * specifically only auto mask tx and rx interrupts */ | |
4046 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
4047 | } | |
9a799d71 | 4048 | |
a34bcfff AD |
4049 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
4050 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
4051 | ||
4052 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
4053 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
73079ea0 AD |
4054 | |
4055 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { | |
4056 | case IXGBE_82599_VMDQ_8Q_MASK: | |
4057 | gpie |= IXGBE_GPIE_VTMODE_16; | |
4058 | break; | |
4059 | case IXGBE_82599_VMDQ_4Q_MASK: | |
4060 | gpie |= IXGBE_GPIE_VTMODE_32; | |
4061 | break; | |
4062 | default: | |
4063 | gpie |= IXGBE_GPIE_VTMODE_64; | |
4064 | break; | |
4065 | } | |
119fc60a MC |
4066 | } |
4067 | ||
5fdd31f9 | 4068 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
4069 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
4070 | switch (adapter->hw.mac.type) { | |
4071 | case ixgbe_mac_82599EB: | |
4072 | gpie |= IXGBE_SDP0_GPIEN; | |
4073 | break; | |
4074 | case ixgbe_mac_X540: | |
4075 | gpie |= IXGBE_EIMS_TS; | |
4076 | break; | |
4077 | default: | |
4078 | break; | |
4079 | } | |
4080 | } | |
5fdd31f9 | 4081 | |
a34bcfff AD |
4082 | /* Enable fan failure interrupt */ |
4083 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 4084 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 4085 | |
2698b208 | 4086 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
4087 | gpie |= IXGBE_SDP1_GPIEN; |
4088 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 4089 | } |
a34bcfff AD |
4090 | |
4091 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
4092 | } | |
4093 | ||
c7ccde0f | 4094 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
4095 | { |
4096 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 4097 | int err; |
a34bcfff AD |
4098 | u32 ctrl_ext; |
4099 | ||
4100 | ixgbe_get_hw_control(adapter); | |
4101 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 4102 | |
9a799d71 AK |
4103 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4104 | ixgbe_configure_msix(adapter); | |
4105 | else | |
4106 | ixgbe_configure_msi_and_legacy(adapter); | |
4107 | ||
ec74a471 ET |
4108 | /* enable the optics for 82599 SFP+ fiber */ |
4109 | if (hw->mac.ops.enable_tx_laser) | |
61fac744 PW |
4110 | hw->mac.ops.enable_tx_laser(hw); |
4111 | ||
9a799d71 | 4112 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
4113 | ixgbe_napi_enable_all(adapter); |
4114 | ||
73c4b7cd AD |
4115 | if (ixgbe_is_sfp(hw)) { |
4116 | ixgbe_sfp_link_config(adapter); | |
4117 | } else { | |
4118 | err = ixgbe_non_sfp_link_config(hw); | |
4119 | if (err) | |
4120 | e_err(probe, "link_config FAILED %d\n", err); | |
4121 | } | |
4122 | ||
021230d4 AV |
4123 | /* clear any pending interrupts, may auto mask */ |
4124 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 4125 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 4126 | |
bf069c97 DS |
4127 | /* |
4128 | * If this adapter has a fan, check to see if we had a failure | |
4129 | * before we enabled the interrupt. | |
4130 | */ | |
4131 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
4132 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
4133 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 4134 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
4135 | } |
4136 | ||
1da100bb | 4137 | /* enable transmits */ |
477de6ed | 4138 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 4139 | |
9a799d71 AK |
4140 | /* bring the link up in the watchdog, this could race with our first |
4141 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
4142 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
4143 | adapter->link_check_timeout = jiffies; | |
7086400d | 4144 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
4145 | |
4146 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
4147 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
4148 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
4149 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
4150 | } |
4151 | ||
d4f80882 AV |
4152 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
4153 | { | |
4154 | WARN_ON(in_interrupt()); | |
7086400d AD |
4155 | /* put off any impending NetWatchDogTimeout */ |
4156 | adapter->netdev->trans_start = jiffies; | |
4157 | ||
d4f80882 | 4158 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 4159 | usleep_range(1000, 2000); |
d4f80882 | 4160 | ixgbe_down(adapter); |
5809a1ae GR |
4161 | /* |
4162 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
4163 | * back up to give the VFs time to respond to the reset. The | |
4164 | * two second wait is based upon the watchdog timer cycle in | |
4165 | * the VF driver. | |
4166 | */ | |
4167 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4168 | msleep(2000); | |
d4f80882 AV |
4169 | ixgbe_up(adapter); |
4170 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
4171 | } | |
4172 | ||
c7ccde0f | 4173 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4174 | { |
4175 | /* hardware has been reset, we need to reload some things */ | |
4176 | ixgbe_configure(adapter); | |
4177 | ||
c7ccde0f | 4178 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4179 | } |
4180 | ||
4181 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
4182 | { | |
c44ade9e | 4183 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
4184 | int err; |
4185 | ||
7086400d AD |
4186 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
4187 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
4188 | usleep_range(1000, 2000); | |
4189 | ||
4190 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
4191 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
4192 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
4193 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
4194 | ||
8ca783ab | 4195 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
4196 | switch (err) { |
4197 | case 0: | |
4198 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 4199 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
4200 | break; |
4201 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 4202 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 4203 | break; |
794caeb2 PWJ |
4204 | case IXGBE_ERR_EEPROM_VERSION: |
4205 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 4206 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 4207 | "Please be aware there may be issues associated with " |
849c4542 ET |
4208 | "your hardware. If you are experiencing problems " |
4209 | "please contact your Intel or hardware " | |
4210 | "representative who provided you with this " | |
4211 | "hardware.\n"); | |
794caeb2 | 4212 | break; |
da4dd0f7 | 4213 | default: |
849c4542 | 4214 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 4215 | } |
9a799d71 | 4216 | |
7086400d AD |
4217 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
4218 | ||
9a799d71 | 4219 | /* reprogram the RAR[0] in case user changed it. */ |
1d9c0bfd | 4220 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV); |
7fa7c9dc AD |
4221 | |
4222 | /* update SAN MAC vmdq pool selection */ | |
4223 | if (hw->mac.san_mac_rar_index) | |
4224 | hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); | |
1a71ab24 | 4225 | |
1a71ab24 JK |
4226 | if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) |
4227 | ixgbe_ptp_reset(adapter); | |
9a799d71 AK |
4228 | } |
4229 | ||
9a799d71 AK |
4230 | /** |
4231 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
4232 | * @rx_ring: ring to free buffers from |
4233 | **/ | |
b6ec895e | 4234 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 4235 | { |
b6ec895e | 4236 | struct device *dev = rx_ring->dev; |
9a799d71 | 4237 | unsigned long size; |
b6ec895e | 4238 | u16 i; |
9a799d71 | 4239 | |
84418e3b AD |
4240 | /* ring already cleared, nothing to do */ |
4241 | if (!rx_ring->rx_buffer_info) | |
4242 | return; | |
9a799d71 | 4243 | |
84418e3b | 4244 | /* Free all the Rx ring sk_buffs */ |
9a799d71 | 4245 | for (i = 0; i < rx_ring->count; i++) { |
f800326d AD |
4246 | struct ixgbe_rx_buffer *rx_buffer; |
4247 | ||
4248 | rx_buffer = &rx_ring->rx_buffer_info[i]; | |
4249 | if (rx_buffer->skb) { | |
4250 | struct sk_buff *skb = rx_buffer->skb; | |
4251 | if (IXGBE_CB(skb)->page_released) { | |
4252 | dma_unmap_page(dev, | |
4253 | IXGBE_CB(skb)->dma, | |
4254 | ixgbe_rx_bufsz(rx_ring), | |
4255 | DMA_FROM_DEVICE); | |
4256 | IXGBE_CB(skb)->page_released = false; | |
4c1975d7 AD |
4257 | } |
4258 | dev_kfree_skb(skb); | |
9a799d71 | 4259 | } |
f800326d AD |
4260 | rx_buffer->skb = NULL; |
4261 | if (rx_buffer->dma) | |
4262 | dma_unmap_page(dev, rx_buffer->dma, | |
4263 | ixgbe_rx_pg_size(rx_ring), | |
4264 | DMA_FROM_DEVICE); | |
4265 | rx_buffer->dma = 0; | |
4266 | if (rx_buffer->page) | |
dd411ec4 AD |
4267 | __free_pages(rx_buffer->page, |
4268 | ixgbe_rx_pg_order(rx_ring)); | |
f800326d | 4269 | rx_buffer->page = NULL; |
9a799d71 AK |
4270 | } |
4271 | ||
4272 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4273 | memset(rx_ring->rx_buffer_info, 0, size); | |
4274 | ||
4275 | /* Zero out the descriptor ring */ | |
4276 | memset(rx_ring->desc, 0, rx_ring->size); | |
4277 | ||
f800326d | 4278 | rx_ring->next_to_alloc = 0; |
9a799d71 AK |
4279 | rx_ring->next_to_clean = 0; |
4280 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4281 | } |
4282 | ||
4283 | /** | |
4284 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4285 | * @tx_ring: ring to be cleaned |
4286 | **/ | |
b6ec895e | 4287 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4288 | { |
4289 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4290 | unsigned long size; | |
b6ec895e | 4291 | u16 i; |
9a799d71 | 4292 | |
84418e3b AD |
4293 | /* ring already cleared, nothing to do */ |
4294 | if (!tx_ring->tx_buffer_info) | |
4295 | return; | |
9a799d71 | 4296 | |
84418e3b | 4297 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4298 | for (i = 0; i < tx_ring->count; i++) { |
4299 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4300 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4301 | } |
4302 | ||
dad8a3b3 JF |
4303 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
4304 | ||
9a799d71 AK |
4305 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
4306 | memset(tx_ring->tx_buffer_info, 0, size); | |
4307 | ||
4308 | /* Zero out the descriptor ring */ | |
4309 | memset(tx_ring->desc, 0, tx_ring->size); | |
4310 | ||
4311 | tx_ring->next_to_use = 0; | |
4312 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4313 | } |
4314 | ||
4315 | /** | |
021230d4 | 4316 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4317 | * @adapter: board private structure |
4318 | **/ | |
021230d4 | 4319 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4320 | { |
4321 | int i; | |
4322 | ||
021230d4 | 4323 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4324 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4325 | } |
4326 | ||
4327 | /** | |
021230d4 | 4328 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4329 | * @adapter: board private structure |
4330 | **/ | |
021230d4 | 4331 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4332 | { |
4333 | int i; | |
4334 | ||
021230d4 | 4335 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4336 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4337 | } |
4338 | ||
e4911d57 AD |
4339 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
4340 | { | |
4341 | struct hlist_node *node, *node2; | |
4342 | struct ixgbe_fdir_filter *filter; | |
4343 | ||
4344 | spin_lock(&adapter->fdir_perfect_lock); | |
4345 | ||
4346 | hlist_for_each_entry_safe(filter, node, node2, | |
4347 | &adapter->fdir_filter_list, fdir_node) { | |
4348 | hlist_del(&filter->fdir_node); | |
4349 | kfree(filter); | |
4350 | } | |
4351 | adapter->fdir_filter_count = 0; | |
4352 | ||
4353 | spin_unlock(&adapter->fdir_perfect_lock); | |
4354 | } | |
4355 | ||
9a799d71 AK |
4356 | void ixgbe_down(struct ixgbe_adapter *adapter) |
4357 | { | |
4358 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4359 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4360 | u32 rxctrl; |
bf29ee6c | 4361 | int i; |
9a799d71 AK |
4362 | |
4363 | /* signal that we are down to the interrupt handler */ | |
4364 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4365 | ||
4366 | /* disable receives */ | |
7f821875 JB |
4367 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4368 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4369 | |
2d39d576 YZ |
4370 | /* disable all enabled rx queues */ |
4371 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4372 | /* this call also flushes the previous write */ | |
4373 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4374 | ||
032b4325 | 4375 | usleep_range(10000, 20000); |
9a799d71 | 4376 | |
7f821875 JB |
4377 | netif_tx_stop_all_queues(netdev); |
4378 | ||
7086400d | 4379 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
4380 | netif_carrier_off(netdev); |
4381 | netif_tx_disable(netdev); | |
4382 | ||
4383 | ixgbe_irq_disable(adapter); | |
4384 | ||
4385 | ixgbe_napi_disable_all(adapter); | |
4386 | ||
d034acf1 AD |
4387 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
4388 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
4389 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
4390 | ||
4391 | del_timer_sync(&adapter->service_timer); | |
4392 | ||
34cecbbf | 4393 | if (adapter->num_vfs) { |
8e34d1aa AD |
4394 | /* Clear EITR Select mapping */ |
4395 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
4396 | |
4397 | /* Mark all the VFs as inactive */ | |
4398 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 4399 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 4400 | |
34cecbbf AD |
4401 | /* ping all the active vfs to let them know we are going down */ |
4402 | ixgbe_ping_all_vfs(adapter); | |
4403 | ||
4404 | /* Disable all VFTE/VFRE TX/RX */ | |
4405 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
4406 | } |
4407 | ||
7f821875 JB |
4408 | /* disable transmits in the hardware now that interrupts are off */ |
4409 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 4410 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 4411 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 4412 | } |
34cecbbf AD |
4413 | |
4414 | /* Disable the Tx DMA engine on 82599 and X540 */ | |
bd508178 AD |
4415 | switch (hw->mac.type) { |
4416 | case ixgbe_mac_82599EB: | |
b93a2226 | 4417 | case ixgbe_mac_X540: |
88512539 | 4418 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4419 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4420 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4421 | break; |
4422 | default: | |
4423 | break; | |
4424 | } | |
7f821875 | 4425 | |
6f4a0e45 PL |
4426 | if (!pci_channel_offline(adapter->pdev)) |
4427 | ixgbe_reset(adapter); | |
c6ecf39a | 4428 | |
ec74a471 ET |
4429 | /* power down the optics for 82599 SFP+ fiber */ |
4430 | if (hw->mac.ops.disable_tx_laser) | |
c6ecf39a DS |
4431 | hw->mac.ops.disable_tx_laser(hw); |
4432 | ||
9a799d71 AK |
4433 | ixgbe_clean_all_tx_rings(adapter); |
4434 | ixgbe_clean_all_rx_rings(adapter); | |
4435 | ||
5dd2d332 | 4436 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4437 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4438 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4439 | #endif |
9a799d71 AK |
4440 | } |
4441 | ||
9a799d71 AK |
4442 | /** |
4443 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4444 | * @netdev: network interface device structure | |
4445 | **/ | |
4446 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4447 | { | |
4448 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4449 | ||
4450 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 4451 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
4452 | } |
4453 | ||
9a799d71 AK |
4454 | /** |
4455 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4456 | * @adapter: board private structure to initialize | |
4457 | * | |
4458 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4459 | * Fields are initialized based on PCI device information and | |
4460 | * OS network device settings (MTU size). | |
4461 | **/ | |
4462 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4463 | { | |
4464 | struct ixgbe_hw *hw = &adapter->hw; | |
4465 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 4466 | unsigned int rss; |
7a6b6f51 | 4467 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4468 | int j; |
4469 | struct tc_configuration *tc; | |
4470 | #endif | |
021230d4 | 4471 | |
c44ade9e JB |
4472 | /* PCI config space info */ |
4473 | ||
4474 | hw->vendor_id = pdev->vendor; | |
4475 | hw->device_id = pdev->device; | |
4476 | hw->revision_id = pdev->revision; | |
4477 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4478 | hw->subsystem_device_id = pdev->subsystem_device; | |
4479 | ||
021230d4 | 4480 | /* Set capability flags */ |
3ed69d7e | 4481 | rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus()); |
c087663e | 4482 | adapter->ring_feature[RING_F_RSS].limit = rss; |
bd508178 AD |
4483 | switch (hw->mac.type) { |
4484 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
4485 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
4486 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
49c7ffbe | 4487 | adapter->max_q_vectors = MAX_Q_VECTORS_82598; |
bd508178 | 4488 | break; |
b93a2226 | 4489 | case ixgbe_mac_X540: |
4f51bf70 JK |
4490 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; |
4491 | case ixgbe_mac_82599EB: | |
49c7ffbe | 4492 | adapter->max_q_vectors = MAX_Q_VECTORS_82599; |
0c19d6af PWJ |
4493 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4494 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
4495 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
4496 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 | 4497 | /* Flow Director hash filters enabled */ |
45b9f509 | 4498 | adapter->atr_sample_rate = 20; |
c087663e | 4499 | adapter->ring_feature[RING_F_FDIR].limit = |
e8e9f696 | 4500 | IXGBE_MAX_FDIR_INDICES; |
c04f6ca8 | 4501 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
eacd73f7 | 4502 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4503 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4504 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
61a0f421 | 4505 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 | 4506 | /* Default traffic class to use for FCoE */ |
56075a98 | 4507 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 4508 | #endif |
eacd73f7 | 4509 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
4510 | break; |
4511 | default: | |
4512 | break; | |
f8212f97 | 4513 | } |
2f90b865 | 4514 | |
7c8ae65a AD |
4515 | #ifdef IXGBE_FCOE |
4516 | /* FCoE support exists, always init the FCoE lock */ | |
4517 | spin_lock_init(&adapter->fcoe.lock); | |
4518 | ||
4519 | #endif | |
1fc5f038 AD |
4520 | /* n-tuple support exists, always init our spinlock */ |
4521 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4522 | ||
7a6b6f51 | 4523 | #ifdef CONFIG_IXGBE_DCB |
4de2a022 JF |
4524 | switch (hw->mac.type) { |
4525 | case ixgbe_mac_X540: | |
4526 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; | |
4527 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
4528 | break; | |
4529 | default: | |
4530 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
4531 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
4532 | break; | |
4533 | } | |
4534 | ||
2f90b865 AD |
4535 | /* Configure DCB traffic classes */ |
4536 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4537 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4538 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4539 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4540 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4541 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4542 | tc->dcb_pfc = pfc_disabled; | |
4543 | } | |
4de2a022 JF |
4544 | |
4545 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
4546 | tc = &adapter->dcb_cfg.tc_config[0]; | |
4547 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4548 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4549 | ||
2f90b865 AD |
4550 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; |
4551 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 4552 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 4553 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 4554 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
f525c6d2 JF |
4555 | memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, |
4556 | sizeof(adapter->temp_dcb_cfg)); | |
2f90b865 AD |
4557 | |
4558 | #endif | |
9a799d71 AK |
4559 | |
4560 | /* default flow control settings */ | |
cd7664f6 | 4561 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4562 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
9da712d2 | 4563 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
4564 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
4565 | hw->fc.send_xon = true; | |
db2adc2d JK |
4566 | hw->fc.disable_fc_autoneg = |
4567 | (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true; | |
9a799d71 | 4568 | |
99d74487 AD |
4569 | #ifdef CONFIG_PCI_IOV |
4570 | /* assign number of SR-IOV VFs */ | |
4571 | if (hw->mac.type != ixgbe_mac_82598EB) | |
4572 | adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs; | |
4573 | ||
4574 | #endif | |
30efa5a3 | 4575 | /* enable itr by default in dynamic mode */ |
f7554a2b | 4576 | adapter->rx_itr_setting = 1; |
f7554a2b | 4577 | adapter->tx_itr_setting = 1; |
30efa5a3 | 4578 | |
30efa5a3 JB |
4579 | /* set default ring sizes */ |
4580 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4581 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4582 | ||
bd198058 | 4583 | /* set default work limits */ |
59224555 | 4584 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 4585 | |
9a799d71 | 4586 | /* initialize eeprom parameters */ |
c44ade9e | 4587 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 4588 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
4589 | return -EIO; |
4590 | } | |
4591 | ||
9a799d71 AK |
4592 | set_bit(__IXGBE_DOWN, &adapter->state); |
4593 | ||
4594 | return 0; | |
4595 | } | |
4596 | ||
4597 | /** | |
4598 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 4599 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4600 | * |
4601 | * Return 0 on success, negative on failure | |
4602 | **/ | |
b6ec895e | 4603 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4604 | { |
b6ec895e | 4605 | struct device *dev = tx_ring->dev; |
de88eeeb AD |
4606 | int orig_node = dev_to_node(dev); |
4607 | int numa_node = -1; | |
9a799d71 AK |
4608 | int size; |
4609 | ||
3a581073 | 4610 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
4611 | |
4612 | if (tx_ring->q_vector) | |
4613 | numa_node = tx_ring->q_vector->numa_node; | |
4614 | ||
4615 | tx_ring->tx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4616 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 4617 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
4618 | if (!tx_ring->tx_buffer_info) |
4619 | goto err; | |
9a799d71 AK |
4620 | |
4621 | /* round up to nearest 4K */ | |
12207e49 | 4622 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4623 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4624 | |
de88eeeb AD |
4625 | set_dev_node(dev, numa_node); |
4626 | tx_ring->desc = dma_alloc_coherent(dev, | |
4627 | tx_ring->size, | |
4628 | &tx_ring->dma, | |
4629 | GFP_KERNEL); | |
4630 | set_dev_node(dev, orig_node); | |
4631 | if (!tx_ring->desc) | |
4632 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
4633 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
4634 | if (!tx_ring->desc) |
4635 | goto err; | |
9a799d71 | 4636 | |
3a581073 JB |
4637 | tx_ring->next_to_use = 0; |
4638 | tx_ring->next_to_clean = 0; | |
9a799d71 | 4639 | return 0; |
e01c31a5 JB |
4640 | |
4641 | err: | |
4642 | vfree(tx_ring->tx_buffer_info); | |
4643 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 4644 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 4645 | return -ENOMEM; |
9a799d71 AK |
4646 | } |
4647 | ||
69888674 AD |
4648 | /** |
4649 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4650 | * @adapter: board private structure | |
4651 | * | |
4652 | * If this function returns with an error, then it's possible one or | |
4653 | * more of the rings is populated (while the rest are not). It is the | |
4654 | * callers duty to clean those orphaned rings. | |
4655 | * | |
4656 | * Return 0 on success, negative on failure | |
4657 | **/ | |
4658 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4659 | { | |
4660 | int i, err = 0; | |
4661 | ||
4662 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 4663 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
4664 | if (!err) |
4665 | continue; | |
de3d5b94 | 4666 | |
396e799c | 4667 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
de3d5b94 | 4668 | goto err_setup_tx; |
69888674 AD |
4669 | } |
4670 | ||
de3d5b94 AD |
4671 | return 0; |
4672 | err_setup_tx: | |
4673 | /* rewind the index freeing the rings as we go */ | |
4674 | while (i--) | |
4675 | ixgbe_free_tx_resources(adapter->tx_ring[i]); | |
69888674 AD |
4676 | return err; |
4677 | } | |
4678 | ||
9a799d71 AK |
4679 | /** |
4680 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 4681 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4682 | * |
4683 | * Returns 0 on success, negative on failure | |
4684 | **/ | |
b6ec895e | 4685 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4686 | { |
b6ec895e | 4687 | struct device *dev = rx_ring->dev; |
de88eeeb AD |
4688 | int orig_node = dev_to_node(dev); |
4689 | int numa_node = -1; | |
021230d4 | 4690 | int size; |
9a799d71 | 4691 | |
3a581073 | 4692 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
4693 | |
4694 | if (rx_ring->q_vector) | |
4695 | numa_node = rx_ring->q_vector->numa_node; | |
4696 | ||
4697 | rx_ring->rx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4698 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 4699 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
4700 | if (!rx_ring->rx_buffer_info) |
4701 | goto err; | |
9a799d71 | 4702 | |
9a799d71 | 4703 | /* Round up to nearest 4K */ |
3a581073 JB |
4704 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
4705 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 4706 | |
de88eeeb AD |
4707 | set_dev_node(dev, numa_node); |
4708 | rx_ring->desc = dma_alloc_coherent(dev, | |
4709 | rx_ring->size, | |
4710 | &rx_ring->dma, | |
4711 | GFP_KERNEL); | |
4712 | set_dev_node(dev, orig_node); | |
4713 | if (!rx_ring->desc) | |
4714 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
4715 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
4716 | if (!rx_ring->desc) |
4717 | goto err; | |
9a799d71 | 4718 | |
3a581073 JB |
4719 | rx_ring->next_to_clean = 0; |
4720 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4721 | |
4722 | return 0; | |
b6ec895e AD |
4723 | err: |
4724 | vfree(rx_ring->rx_buffer_info); | |
4725 | rx_ring->rx_buffer_info = NULL; | |
4726 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 4727 | return -ENOMEM; |
9a799d71 AK |
4728 | } |
4729 | ||
69888674 AD |
4730 | /** |
4731 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
4732 | * @adapter: board private structure | |
4733 | * | |
4734 | * If this function returns with an error, then it's possible one or | |
4735 | * more of the rings is populated (while the rest are not). It is the | |
4736 | * callers duty to clean those orphaned rings. | |
4737 | * | |
4738 | * Return 0 on success, negative on failure | |
4739 | **/ | |
69888674 AD |
4740 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
4741 | { | |
4742 | int i, err = 0; | |
4743 | ||
4744 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 4745 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
4746 | if (!err) |
4747 | continue; | |
de3d5b94 | 4748 | |
396e799c | 4749 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
de3d5b94 | 4750 | goto err_setup_rx; |
69888674 AD |
4751 | } |
4752 | ||
7c8ae65a AD |
4753 | #ifdef IXGBE_FCOE |
4754 | err = ixgbe_setup_fcoe_ddp_resources(adapter); | |
4755 | if (!err) | |
4756 | #endif | |
4757 | return 0; | |
de3d5b94 AD |
4758 | err_setup_rx: |
4759 | /* rewind the index freeing the rings as we go */ | |
4760 | while (i--) | |
4761 | ixgbe_free_rx_resources(adapter->rx_ring[i]); | |
69888674 AD |
4762 | return err; |
4763 | } | |
4764 | ||
9a799d71 AK |
4765 | /** |
4766 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
4767 | * @tx_ring: Tx descriptor ring for a specific queue |
4768 | * | |
4769 | * Free all transmit software resources | |
4770 | **/ | |
b6ec895e | 4771 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4772 | { |
b6ec895e | 4773 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
4774 | |
4775 | vfree(tx_ring->tx_buffer_info); | |
4776 | tx_ring->tx_buffer_info = NULL; | |
4777 | ||
b6ec895e AD |
4778 | /* if not set, then don't free */ |
4779 | if (!tx_ring->desc) | |
4780 | return; | |
4781 | ||
4782 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
4783 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
4784 | |
4785 | tx_ring->desc = NULL; | |
4786 | } | |
4787 | ||
4788 | /** | |
4789 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4790 | * @adapter: board private structure | |
4791 | * | |
4792 | * Free all transmit software resources | |
4793 | **/ | |
4794 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4795 | { | |
4796 | int i; | |
4797 | ||
4798 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 4799 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 4800 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
4801 | } |
4802 | ||
4803 | /** | |
b4617240 | 4804 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4805 | * @rx_ring: ring to clean the resources from |
4806 | * | |
4807 | * Free all receive software resources | |
4808 | **/ | |
b6ec895e | 4809 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4810 | { |
b6ec895e | 4811 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
4812 | |
4813 | vfree(rx_ring->rx_buffer_info); | |
4814 | rx_ring->rx_buffer_info = NULL; | |
4815 | ||
b6ec895e AD |
4816 | /* if not set, then don't free */ |
4817 | if (!rx_ring->desc) | |
4818 | return; | |
4819 | ||
4820 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
4821 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
4822 | |
4823 | rx_ring->desc = NULL; | |
4824 | } | |
4825 | ||
4826 | /** | |
4827 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4828 | * @adapter: board private structure | |
4829 | * | |
4830 | * Free all receive software resources | |
4831 | **/ | |
4832 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4833 | { | |
4834 | int i; | |
4835 | ||
7c8ae65a AD |
4836 | #ifdef IXGBE_FCOE |
4837 | ixgbe_free_fcoe_ddp_resources(adapter); | |
4838 | ||
4839 | #endif | |
9a799d71 | 4840 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 4841 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 4842 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
4843 | } |
4844 | ||
9a799d71 AK |
4845 | /** |
4846 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4847 | * @netdev: network interface device structure | |
4848 | * @new_mtu: new value for maximum frame size | |
4849 | * | |
4850 | * Returns 0 on success, negative on failure | |
4851 | **/ | |
4852 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4853 | { | |
4854 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4855 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4856 | ||
42c783c5 | 4857 | /* MTU < 68 is an error and causes problems on some kernels */ |
655309e9 AD |
4858 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) |
4859 | return -EINVAL; | |
4860 | ||
4861 | /* | |
872844dd AD |
4862 | * For 82599EB we cannot allow legacy VFs to enable their receive |
4863 | * paths when MTU greater than 1500 is configured. So display a | |
4864 | * warning that legacy VFs will be disabled. | |
655309e9 AD |
4865 | */ |
4866 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
4867 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
4868 | (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
872844dd | 4869 | e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); |
9a799d71 | 4870 | |
396e799c | 4871 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 4872 | |
021230d4 | 4873 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4874 | netdev->mtu = new_mtu; |
4875 | ||
d4f80882 AV |
4876 | if (netif_running(netdev)) |
4877 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4878 | |
4879 | return 0; | |
4880 | } | |
4881 | ||
4882 | /** | |
4883 | * ixgbe_open - Called when a network interface is made active | |
4884 | * @netdev: network interface device structure | |
4885 | * | |
4886 | * Returns 0 on success, negative value on failure | |
4887 | * | |
4888 | * The open entry point is called when a network interface is made | |
4889 | * active by the system (IFF_UP). At this point all resources needed | |
4890 | * for transmit and receive operations are allocated, the interrupt | |
4891 | * handler is registered with the OS, the watchdog timer is started, | |
4892 | * and the stack is notified that the interface is ready. | |
4893 | **/ | |
4894 | static int ixgbe_open(struct net_device *netdev) | |
4895 | { | |
4896 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4897 | int err; | |
4bebfaa5 AK |
4898 | |
4899 | /* disallow open during test */ | |
4900 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4901 | return -EBUSY; | |
9a799d71 | 4902 | |
54386467 JB |
4903 | netif_carrier_off(netdev); |
4904 | ||
9a799d71 AK |
4905 | /* allocate transmit descriptors */ |
4906 | err = ixgbe_setup_all_tx_resources(adapter); | |
4907 | if (err) | |
4908 | goto err_setup_tx; | |
4909 | ||
9a799d71 AK |
4910 | /* allocate receive descriptors */ |
4911 | err = ixgbe_setup_all_rx_resources(adapter); | |
4912 | if (err) | |
4913 | goto err_setup_rx; | |
4914 | ||
4915 | ixgbe_configure(adapter); | |
4916 | ||
021230d4 | 4917 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4918 | if (err) |
4919 | goto err_req_irq; | |
4920 | ||
ac802f5d AD |
4921 | /* Notify the stack of the actual queue counts. */ |
4922 | err = netif_set_real_num_tx_queues(netdev, | |
4923 | adapter->num_rx_pools > 1 ? 1 : | |
4924 | adapter->num_tx_queues); | |
4925 | if (err) | |
4926 | goto err_set_queues; | |
4927 | ||
4928 | ||
4929 | err = netif_set_real_num_rx_queues(netdev, | |
4930 | adapter->num_rx_pools > 1 ? 1 : | |
4931 | adapter->num_rx_queues); | |
4932 | if (err) | |
4933 | goto err_set_queues; | |
4934 | ||
1a71ab24 | 4935 | ixgbe_ptp_init(adapter); |
1a71ab24 | 4936 | |
c7ccde0f | 4937 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4938 | |
4939 | return 0; | |
4940 | ||
ac802f5d AD |
4941 | err_set_queues: |
4942 | ixgbe_free_irq(adapter); | |
9a799d71 | 4943 | err_req_irq: |
a20a1199 | 4944 | ixgbe_free_all_rx_resources(adapter); |
de3d5b94 | 4945 | err_setup_rx: |
a20a1199 | 4946 | ixgbe_free_all_tx_resources(adapter); |
de3d5b94 | 4947 | err_setup_tx: |
9a799d71 AK |
4948 | ixgbe_reset(adapter); |
4949 | ||
4950 | return err; | |
4951 | } | |
4952 | ||
4953 | /** | |
4954 | * ixgbe_close - Disables a network interface | |
4955 | * @netdev: network interface device structure | |
4956 | * | |
4957 | * Returns 0, this is not allowed to fail | |
4958 | * | |
4959 | * The close entry point is called when an interface is de-activated | |
4960 | * by the OS. The hardware is still under the drivers control, but | |
4961 | * needs to be disabled. A global MAC reset is issued to stop the | |
4962 | * hardware, and all transmit and receive resources are freed. | |
4963 | **/ | |
4964 | static int ixgbe_close(struct net_device *netdev) | |
4965 | { | |
4966 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 | 4967 | |
1a71ab24 | 4968 | ixgbe_ptp_stop(adapter); |
1a71ab24 | 4969 | |
9a799d71 AK |
4970 | ixgbe_down(adapter); |
4971 | ixgbe_free_irq(adapter); | |
4972 | ||
e4911d57 AD |
4973 | ixgbe_fdir_filter_exit(adapter); |
4974 | ||
9a799d71 AK |
4975 | ixgbe_free_all_tx_resources(adapter); |
4976 | ixgbe_free_all_rx_resources(adapter); | |
4977 | ||
5eba3699 | 4978 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4979 | |
4980 | return 0; | |
4981 | } | |
4982 | ||
b3c8b4ba AD |
4983 | #ifdef CONFIG_PM |
4984 | static int ixgbe_resume(struct pci_dev *pdev) | |
4985 | { | |
c60fbb00 AD |
4986 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4987 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
4988 | u32 err; |
4989 | ||
4990 | pci_set_power_state(pdev, PCI_D0); | |
4991 | pci_restore_state(pdev); | |
656ab817 DS |
4992 | /* |
4993 | * pci_restore_state clears dev->state_saved so call | |
4994 | * pci_save_state to restore it. | |
4995 | */ | |
4996 | pci_save_state(pdev); | |
9ce77666 | 4997 | |
4998 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4999 | if (err) { |
849c4542 | 5000 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
5001 | return err; |
5002 | } | |
5003 | pci_set_master(pdev); | |
5004 | ||
dd4d8ca6 | 5005 | pci_wake_from_d3(pdev, false); |
b3c8b4ba | 5006 | |
b3c8b4ba AD |
5007 | ixgbe_reset(adapter); |
5008 | ||
495dce12 WJP |
5009 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
5010 | ||
ac802f5d AD |
5011 | rtnl_lock(); |
5012 | err = ixgbe_init_interrupt_scheme(adapter); | |
5013 | if (!err && netif_running(netdev)) | |
c60fbb00 | 5014 | err = ixgbe_open(netdev); |
ac802f5d AD |
5015 | |
5016 | rtnl_unlock(); | |
5017 | ||
5018 | if (err) | |
5019 | return err; | |
b3c8b4ba AD |
5020 | |
5021 | netif_device_attach(netdev); | |
5022 | ||
5023 | return 0; | |
5024 | } | |
b3c8b4ba | 5025 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
5026 | |
5027 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 5028 | { |
c60fbb00 AD |
5029 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5030 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
5031 | struct ixgbe_hw *hw = &adapter->hw; |
5032 | u32 ctrl, fctrl; | |
5033 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
5034 | #ifdef CONFIG_PM |
5035 | int retval = 0; | |
5036 | #endif | |
5037 | ||
5038 | netif_device_detach(netdev); | |
5039 | ||
5040 | if (netif_running(netdev)) { | |
ab6039a7 | 5041 | rtnl_lock(); |
b3c8b4ba AD |
5042 | ixgbe_down(adapter); |
5043 | ixgbe_free_irq(adapter); | |
5044 | ixgbe_free_all_tx_resources(adapter); | |
5045 | ixgbe_free_all_rx_resources(adapter); | |
ab6039a7 | 5046 | rtnl_unlock(); |
b3c8b4ba | 5047 | } |
b3c8b4ba | 5048 | |
5f5ae6fc AD |
5049 | ixgbe_clear_interrupt_scheme(adapter); |
5050 | ||
b3c8b4ba AD |
5051 | #ifdef CONFIG_PM |
5052 | retval = pci_save_state(pdev); | |
5053 | if (retval) | |
5054 | return retval; | |
4df10466 | 5055 | |
b3c8b4ba | 5056 | #endif |
e8e26350 PW |
5057 | if (wufc) { |
5058 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 5059 | |
ec74a471 ET |
5060 | /* enable the optics for 82599 SFP+ fiber as we can WoL */ |
5061 | if (hw->mac.ops.enable_tx_laser) | |
c509e754 DS |
5062 | hw->mac.ops.enable_tx_laser(hw); |
5063 | ||
e8e26350 PW |
5064 | /* turn on all-multi mode if wake on multicast is enabled */ |
5065 | if (wufc & IXGBE_WUFC_MC) { | |
5066 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5067 | fctrl |= IXGBE_FCTRL_MPE; | |
5068 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
5069 | } | |
5070 | ||
5071 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
5072 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
5073 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
5074 | ||
5075 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
5076 | } else { | |
5077 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
5078 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
5079 | } | |
5080 | ||
bd508178 AD |
5081 | switch (hw->mac.type) { |
5082 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 5083 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
5084 | break; |
5085 | case ixgbe_mac_82599EB: | |
b93a2226 | 5086 | case ixgbe_mac_X540: |
bd508178 AD |
5087 | pci_wake_from_d3(pdev, !!wufc); |
5088 | break; | |
5089 | default: | |
5090 | break; | |
5091 | } | |
b3c8b4ba | 5092 | |
9d8d05ae RW |
5093 | *enable_wake = !!wufc; |
5094 | ||
b3c8b4ba AD |
5095 | ixgbe_release_hw_control(adapter); |
5096 | ||
5097 | pci_disable_device(pdev); | |
5098 | ||
9d8d05ae RW |
5099 | return 0; |
5100 | } | |
5101 | ||
5102 | #ifdef CONFIG_PM | |
5103 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5104 | { | |
5105 | int retval; | |
5106 | bool wake; | |
5107 | ||
5108 | retval = __ixgbe_shutdown(pdev, &wake); | |
5109 | if (retval) | |
5110 | return retval; | |
5111 | ||
5112 | if (wake) { | |
5113 | pci_prepare_to_sleep(pdev); | |
5114 | } else { | |
5115 | pci_wake_from_d3(pdev, false); | |
5116 | pci_set_power_state(pdev, PCI_D3hot); | |
5117 | } | |
b3c8b4ba AD |
5118 | |
5119 | return 0; | |
5120 | } | |
9d8d05ae | 5121 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5122 | |
5123 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5124 | { | |
9d8d05ae RW |
5125 | bool wake; |
5126 | ||
5127 | __ixgbe_shutdown(pdev, &wake); | |
5128 | ||
5129 | if (system_state == SYSTEM_POWER_OFF) { | |
5130 | pci_wake_from_d3(pdev, wake); | |
5131 | pci_set_power_state(pdev, PCI_D3hot); | |
5132 | } | |
b3c8b4ba AD |
5133 | } |
5134 | ||
9a799d71 AK |
5135 | /** |
5136 | * ixgbe_update_stats - Update the board statistics counters. | |
5137 | * @adapter: board private structure | |
5138 | **/ | |
5139 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5140 | { | |
2d86f139 | 5141 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5142 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 5143 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
5144 | u64 total_mpc = 0; |
5145 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
5146 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
5147 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 5148 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
9a799d71 | 5149 | |
d08935c2 DS |
5150 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5151 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5152 | return; | |
5153 | ||
94b982b2 | 5154 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5155 | u64 rsc_count = 0; |
94b982b2 | 5156 | u64 rsc_flush = 0; |
94b982b2 | 5157 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
5158 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
5159 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5160 | } |
5161 | adapter->rsc_total_count = rsc_count; | |
5162 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5163 | } |
5164 | ||
5b7da515 AD |
5165 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5166 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5167 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5168 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5169 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 5170 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
5171 | bytes += rx_ring->stats.bytes; |
5172 | packets += rx_ring->stats.packets; | |
5173 | } | |
5174 | adapter->non_eop_descs = non_eop_descs; | |
5175 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5176 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 5177 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
5178 | netdev->stats.rx_bytes = bytes; |
5179 | netdev->stats.rx_packets = packets; | |
5180 | ||
5181 | bytes = 0; | |
5182 | packets = 0; | |
7ca3bc58 | 5183 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5184 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5185 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5186 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5187 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5188 | bytes += tx_ring->stats.bytes; | |
5189 | packets += tx_ring->stats.packets; | |
5190 | } | |
eb985f09 | 5191 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5192 | adapter->tx_busy = tx_busy; |
5193 | netdev->stats.tx_bytes = bytes; | |
5194 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5195 | |
7ca647bd | 5196 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
5197 | |
5198 | /* 8 register reads */ | |
6f11eef7 AV |
5199 | for (i = 0; i < 8; i++) { |
5200 | /* for packet buffers not used, the register should read 0 */ | |
5201 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5202 | missed_rx += mpc; | |
7ca647bd JP |
5203 | hwstats->mpc[i] += mpc; |
5204 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
5205 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5206 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
5207 | switch (hw->mac.type) { |
5208 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
5209 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5210 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5211 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
5212 | hwstats->pxonrxc[i] += |
5213 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5214 | break; |
5215 | case ixgbe_mac_82599EB: | |
b93a2226 | 5216 | case ixgbe_mac_X540: |
bd508178 AD |
5217 | hwstats->pxonrxc[i] += |
5218 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5219 | break; |
5220 | default: | |
5221 | break; | |
e8e26350 | 5222 | } |
6f11eef7 | 5223 | } |
1a70db4b ET |
5224 | |
5225 | /*16 register reads */ | |
5226 | for (i = 0; i < 16; i++) { | |
5227 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5228 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5229 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
5230 | (hw->mac.type == ixgbe_mac_X540)) { | |
5231 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); | |
5232 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
5233 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
5234 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
5235 | } | |
5236 | } | |
5237 | ||
7ca647bd | 5238 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5239 | /* work around hardware counting issue */ |
7ca647bd | 5240 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5241 | |
c84d324c JF |
5242 | ixgbe_update_xoff_received(adapter); |
5243 | ||
6f11eef7 | 5244 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5245 | switch (hw->mac.type) { |
5246 | case ixgbe_mac_82598EB: | |
5247 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5248 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5249 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5250 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5251 | break; | |
b93a2226 | 5252 | case ixgbe_mac_X540: |
58f6bcf9 ET |
5253 | /* OS2BMC stats are X540 only*/ |
5254 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); | |
5255 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
5256 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
5257 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
5258 | case ixgbe_mac_82599EB: | |
a4d4f629 AD |
5259 | for (i = 0; i < 16; i++) |
5260 | adapter->hw_rx_no_dma_resources += | |
5261 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
7ca647bd | 5262 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5263 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5264 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5265 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5266 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5267 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5268 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5269 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5270 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5271 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5272 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5273 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5274 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5275 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5276 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5277 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc | 5278 | /* Add up per cpu counters for total ddp aloc fail */ |
5a1ee270 AD |
5279 | if (adapter->fcoe.ddp_pool) { |
5280 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
5281 | struct ixgbe_fcoe_ddp_pool *ddp_pool; | |
5282 | unsigned int cpu; | |
5283 | u64 noddp = 0, noddp_ext_buff = 0; | |
7b859ebc | 5284 | for_each_possible_cpu(cpu) { |
5a1ee270 AD |
5285 | ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); |
5286 | noddp += ddp_pool->noddp; | |
5287 | noddp_ext_buff += ddp_pool->noddp_ext_buff; | |
7b859ebc | 5288 | } |
5a1ee270 AD |
5289 | hwstats->fcoe_noddp = noddp; |
5290 | hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; | |
7b859ebc | 5291 | } |
6d45522c | 5292 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5293 | break; |
5294 | default: | |
5295 | break; | |
e8e26350 | 5296 | } |
9a799d71 | 5297 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5298 | hwstats->bprc += bprc; |
5299 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5300 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5301 | hwstats->mprc -= bprc; |
5302 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5303 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5304 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5305 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5306 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5307 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5308 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5309 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5310 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5311 | hwstats->lxontxc += lxon; |
6f11eef7 | 5312 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 5313 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
5314 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
5315 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5316 | /* |
5317 | * 82598 errata - tx of flow control packets is included in tx counters | |
5318 | */ | |
5319 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5320 | hwstats->gptc -= xon_off_tot; |
5321 | hwstats->mptc -= xon_off_tot; | |
5322 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5323 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5324 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5325 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5326 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5327 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5328 | hwstats->ptc64 -= xon_off_tot; | |
5329 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5330 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5331 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5332 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5333 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5334 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5335 | |
5336 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5337 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5338 | |
5339 | /* Rx Errors */ | |
7ca647bd | 5340 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5341 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5342 | netdev->stats.rx_length_errors = hwstats->rlec; |
5343 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5344 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5345 | } |
5346 | ||
5347 | /** | |
d034acf1 | 5348 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
49ce9c2c | 5349 | * @adapter: pointer to the device adapter structure |
9a799d71 | 5350 | **/ |
d034acf1 | 5351 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 5352 | { |
cf8280ee | 5353 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 5354 | int i; |
cf8280ee | 5355 | |
d034acf1 AD |
5356 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
5357 | return; | |
5358 | ||
5359 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 5360 | |
d034acf1 | 5361 | /* if interface is down do nothing */ |
fe49f04a | 5362 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
5363 | return; |
5364 | ||
5365 | /* do nothing if we are not using signature filters */ | |
5366 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
5367 | return; | |
5368 | ||
5369 | adapter->fdir_overflow++; | |
5370 | ||
93c52dd0 AD |
5371 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
5372 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5373 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
f0f9778d | 5374 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
5375 | /* re-enable flow director interrupts */ |
5376 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
5377 | } else { |
5378 | e_err(probe, "failed to finish FDIR re-initialization, " | |
5379 | "ignored adding FDIR ATR filters\n"); | |
5380 | } | |
93c52dd0 AD |
5381 | } |
5382 | ||
5383 | /** | |
5384 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
49ce9c2c | 5385 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5386 | * |
5387 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 5388 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 5389 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 5390 | * determine if a hang has occurred. |
93c52dd0 AD |
5391 | */ |
5392 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 5393 | { |
cf8280ee | 5394 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5395 | u64 eics = 0; |
5396 | int i; | |
cf8280ee | 5397 | |
93c52dd0 AD |
5398 | /* If we're down or resetting, just bail */ |
5399 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5400 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5401 | return; | |
22d5a71b | 5402 | |
93c52dd0 AD |
5403 | /* Force detection of hung controller */ |
5404 | if (netif_carrier_ok(adapter->netdev)) { | |
5405 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5406 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
5407 | } | |
22d5a71b | 5408 | |
fe49f04a AD |
5409 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
5410 | /* | |
5411 | * for legacy and MSI interrupts don't set any bits | |
5412 | * that are enabled for EIAM, because this operation | |
5413 | * would set *both* EIMS and EICS for any bit in EIAM | |
5414 | */ | |
5415 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
5416 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
5417 | } else { |
5418 | /* get one bit for every active tx/rx interrupt vector */ | |
49c7ffbe | 5419 | for (i = 0; i < adapter->num_q_vectors; i++) { |
93c52dd0 | 5420 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; |
efe3d3c8 | 5421 | if (qv->rx.ring || qv->tx.ring) |
93c52dd0 AD |
5422 | eics |= ((u64)1 << i); |
5423 | } | |
cf8280ee | 5424 | } |
9a799d71 | 5425 | |
93c52dd0 | 5426 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a AD |
5427 | ixgbe_irq_rearm_queues(adapter, eics); |
5428 | ||
cf8280ee JB |
5429 | } |
5430 | ||
e8e26350 | 5431 | /** |
93c52dd0 | 5432 | * ixgbe_watchdog_update_link - update the link status |
49ce9c2c BH |
5433 | * @adapter: pointer to the device adapter structure |
5434 | * @link_speed: pointer to a u32 to store the link_speed | |
e8e26350 | 5435 | **/ |
93c52dd0 | 5436 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 5437 | { |
e8e26350 | 5438 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5439 | u32 link_speed = adapter->link_speed; |
5440 | bool link_up = adapter->link_up; | |
041441d0 | 5441 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; |
e8e26350 | 5442 | |
93c52dd0 AD |
5443 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
5444 | return; | |
5445 | ||
5446 | if (hw->mac.ops.check_link) { | |
5447 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 5448 | } else { |
93c52dd0 AD |
5449 | /* always assume link is up, if no check link function */ |
5450 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
5451 | link_up = true; | |
c4cf55e5 | 5452 | } |
041441d0 AD |
5453 | |
5454 | if (adapter->ixgbe_ieee_pfc) | |
5455 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
5456 | ||
3ebe8fde | 5457 | if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { |
041441d0 | 5458 | hw->mac.ops.fc_enable(hw); |
3ebe8fde AD |
5459 | ixgbe_set_rx_drop_en(adapter); |
5460 | } | |
93c52dd0 AD |
5461 | |
5462 | if (link_up || | |
5463 | time_after(jiffies, (adapter->link_check_timeout + | |
5464 | IXGBE_TRY_LINK_TIMEOUT))) { | |
5465 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
5466 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
5467 | IXGBE_WRITE_FLUSH(hw); | |
5468 | } | |
5469 | ||
5470 | adapter->link_up = link_up; | |
5471 | adapter->link_speed = link_speed; | |
e8e26350 PW |
5472 | } |
5473 | ||
107d3018 AD |
5474 | static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) |
5475 | { | |
5476 | #ifdef CONFIG_IXGBE_DCB | |
5477 | struct net_device *netdev = adapter->netdev; | |
5478 | struct dcb_app app = { | |
5479 | .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, | |
5480 | .protocol = 0, | |
5481 | }; | |
5482 | u8 up = 0; | |
5483 | ||
5484 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) | |
5485 | up = dcb_ieee_getapp_mask(netdev, &app); | |
5486 | ||
5487 | adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; | |
5488 | #endif | |
5489 | } | |
5490 | ||
e8e26350 | 5491 | /** |
93c52dd0 AD |
5492 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
5493 | * print link up message | |
49ce9c2c | 5494 | * @adapter: pointer to the device adapter structure |
e8e26350 | 5495 | **/ |
93c52dd0 | 5496 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 5497 | { |
93c52dd0 | 5498 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 5499 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5500 | u32 link_speed = adapter->link_speed; |
5501 | bool flow_rx, flow_tx; | |
e8e26350 | 5502 | |
93c52dd0 AD |
5503 | /* only continue if link was previously down */ |
5504 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 5505 | return; |
63d6e1d8 | 5506 | |
93c52dd0 | 5507 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 5508 | |
93c52dd0 AD |
5509 | switch (hw->mac.type) { |
5510 | case ixgbe_mac_82598EB: { | |
5511 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5512 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
5513 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
5514 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
5515 | } | |
5516 | break; | |
5517 | case ixgbe_mac_X540: | |
5518 | case ixgbe_mac_82599EB: { | |
5519 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5520 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
5521 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
5522 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
5523 | } | |
5524 | break; | |
5525 | default: | |
5526 | flow_tx = false; | |
5527 | flow_rx = false; | |
5528 | break; | |
e8e26350 | 5529 | } |
3a6a4eda | 5530 | |
1a71ab24 JK |
5531 | if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) |
5532 | ixgbe_ptp_start_cyclecounter(adapter); | |
3a6a4eda | 5533 | |
93c52dd0 AD |
5534 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
5535 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
5536 | "10 Gbps" : | |
5537 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5538 | "1 Gbps" : | |
5539 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
5540 | "100 Mbps" : | |
5541 | "unknown speed"))), | |
5542 | ((flow_rx && flow_tx) ? "RX/TX" : | |
5543 | (flow_rx ? "RX" : | |
5544 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 5545 | |
93c52dd0 | 5546 | netif_carrier_on(netdev); |
93c52dd0 | 5547 | ixgbe_check_vf_rate_limit(adapter); |
befa2af7 | 5548 | |
107d3018 AD |
5549 | /* update the default user priority for VFs */ |
5550 | ixgbe_update_default_up(adapter); | |
5551 | ||
befa2af7 AD |
5552 | /* ping all the active vfs to let them know link has changed */ |
5553 | ixgbe_ping_all_vfs(adapter); | |
e8e26350 PW |
5554 | } |
5555 | ||
c4cf55e5 | 5556 | /** |
93c52dd0 AD |
5557 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
5558 | * print link down message | |
49ce9c2c | 5559 | * @adapter: pointer to the adapter structure |
c4cf55e5 | 5560 | **/ |
581330ba | 5561 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) |
c4cf55e5 | 5562 | { |
cf8280ee | 5563 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 5564 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 5565 | |
93c52dd0 AD |
5566 | adapter->link_up = false; |
5567 | adapter->link_speed = 0; | |
cf8280ee | 5568 | |
93c52dd0 AD |
5569 | /* only continue if link was up previously */ |
5570 | if (!netif_carrier_ok(netdev)) | |
5571 | return; | |
264857b8 | 5572 | |
93c52dd0 AD |
5573 | /* poll for SFP+ cable when link is down */ |
5574 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
5575 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 5576 | |
1a71ab24 JK |
5577 | if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) |
5578 | ixgbe_ptp_start_cyclecounter(adapter); | |
3a6a4eda | 5579 | |
93c52dd0 AD |
5580 | e_info(drv, "NIC Link is Down\n"); |
5581 | netif_carrier_off(netdev); | |
befa2af7 AD |
5582 | |
5583 | /* ping all the active vfs to let them know link has changed */ | |
5584 | ixgbe_ping_all_vfs(adapter); | |
93c52dd0 | 5585 | } |
e8e26350 | 5586 | |
93c52dd0 AD |
5587 | /** |
5588 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
49ce9c2c | 5589 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5590 | **/ |
5591 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
5592 | { | |
c4cf55e5 | 5593 | int i; |
93c52dd0 | 5594 | int some_tx_pending = 0; |
c4cf55e5 | 5595 | |
93c52dd0 | 5596 | if (!netif_carrier_ok(adapter->netdev)) { |
bc59fcda | 5597 | for (i = 0; i < adapter->num_tx_queues; i++) { |
93c52dd0 | 5598 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5599 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5600 | some_tx_pending = 1; | |
5601 | break; | |
5602 | } | |
5603 | } | |
5604 | ||
5605 | if (some_tx_pending) { | |
5606 | /* We've lost link, so the controller stops DMA, | |
5607 | * but we've got queued Tx work that's never going | |
5608 | * to get done, so reset controller to flush Tx. | |
5609 | * (Do the reset outside of interrupt context). | |
5610 | */ | |
c83c6cbd | 5611 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 5612 | } |
c4cf55e5 | 5613 | } |
c4cf55e5 PWJ |
5614 | } |
5615 | ||
a985b6c3 GR |
5616 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
5617 | { | |
5618 | u32 ssvpc; | |
5619 | ||
0584d999 GR |
5620 | /* Do not perform spoof check for 82598 or if not in IOV mode */ |
5621 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
5622 | adapter->num_vfs == 0) | |
a985b6c3 GR |
5623 | return; |
5624 | ||
5625 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
5626 | ||
5627 | /* | |
5628 | * ssvpc register is cleared on read, if zero then no | |
5629 | * spoofed packets in the last interval. | |
5630 | */ | |
5631 | if (!ssvpc) | |
5632 | return; | |
5633 | ||
d6ea0754 | 5634 | e_warn(drv, "%u Spoofed packets detected\n", ssvpc); |
a985b6c3 GR |
5635 | } |
5636 | ||
93c52dd0 AD |
5637 | /** |
5638 | * ixgbe_watchdog_subtask - check and bring link up | |
49ce9c2c | 5639 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5640 | **/ |
5641 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
5642 | { | |
5643 | /* if interface is down do nothing */ | |
7edebf9a ET |
5644 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5645 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
93c52dd0 AD |
5646 | return; |
5647 | ||
5648 | ixgbe_watchdog_update_link(adapter); | |
5649 | ||
5650 | if (adapter->link_up) | |
5651 | ixgbe_watchdog_link_is_up(adapter); | |
5652 | else | |
5653 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 5654 | |
a985b6c3 | 5655 | ixgbe_spoof_check(adapter); |
9a799d71 | 5656 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
5657 | |
5658 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 5659 | } |
10eec955 | 5660 | |
cf8280ee | 5661 | /** |
7086400d | 5662 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
49ce9c2c | 5663 | * @adapter: the ixgbe adapter structure |
cf8280ee | 5664 | **/ |
7086400d | 5665 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 5666 | { |
cf8280ee | 5667 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 5668 | s32 err; |
cf8280ee | 5669 | |
7086400d AD |
5670 | /* not searching for SFP so there is nothing to do here */ |
5671 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
5672 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5673 | return; | |
10eec955 | 5674 | |
7086400d AD |
5675 | /* someone else is in init, wait until next service event */ |
5676 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5677 | return; | |
cf8280ee | 5678 | |
7086400d AD |
5679 | err = hw->phy.ops.identify_sfp(hw); |
5680 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5681 | goto sfp_out; | |
264857b8 | 5682 | |
7086400d AD |
5683 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
5684 | /* If no cable is present, then we need to reset | |
5685 | * the next time we find a good cable. */ | |
5686 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 5687 | } |
9a799d71 | 5688 | |
7086400d AD |
5689 | /* exit on error */ |
5690 | if (err) | |
5691 | goto sfp_out; | |
e8e26350 | 5692 | |
7086400d AD |
5693 | /* exit if reset not needed */ |
5694 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5695 | goto sfp_out; | |
9a799d71 | 5696 | |
7086400d | 5697 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 5698 | |
7086400d AD |
5699 | /* |
5700 | * A module may be identified correctly, but the EEPROM may not have | |
5701 | * support for that module. setup_sfp() will fail in that case, so | |
5702 | * we should not allow that module to load. | |
5703 | */ | |
5704 | if (hw->mac.type == ixgbe_mac_82598EB) | |
5705 | err = hw->phy.ops.reset(hw); | |
5706 | else | |
5707 | err = hw->mac.ops.setup_sfp(hw); | |
5708 | ||
5709 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5710 | goto sfp_out; | |
5711 | ||
5712 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
5713 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
5714 | ||
5715 | sfp_out: | |
5716 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5717 | ||
5718 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
5719 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
5720 | e_dev_err("failed to initialize because an unsupported " | |
5721 | "SFP+ module type was detected.\n"); | |
5722 | e_dev_err("Reload the driver after installing a " | |
5723 | "supported module.\n"); | |
5724 | unregister_netdev(adapter->netdev); | |
bc59fcda | 5725 | } |
7086400d | 5726 | } |
bc59fcda | 5727 | |
7086400d AD |
5728 | /** |
5729 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
49ce9c2c | 5730 | * @adapter: the ixgbe adapter structure |
7086400d AD |
5731 | **/ |
5732 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
5733 | { | |
5734 | struct ixgbe_hw *hw = &adapter->hw; | |
5735 | u32 autoneg; | |
5736 | bool negotiation; | |
5737 | ||
5738 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
5739 | return; | |
5740 | ||
5741 | /* someone else is in init, wait until next service event */ | |
5742 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5743 | return; | |
5744 | ||
5745 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
5746 | ||
5747 | autoneg = hw->phy.autoneg_advertised; | |
5748 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
5749 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); | |
7086400d AD |
5750 | if (hw->mac.ops.setup_link) |
5751 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
5752 | ||
5753 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
5754 | adapter->link_check_timeout = jiffies; | |
5755 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5756 | } | |
5757 | ||
83c61fa9 GR |
5758 | #ifdef CONFIG_PCI_IOV |
5759 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) | |
5760 | { | |
5761 | int vf; | |
5762 | struct ixgbe_hw *hw = &adapter->hw; | |
5763 | struct net_device *netdev = adapter->netdev; | |
5764 | u32 gpc; | |
5765 | u32 ciaa, ciad; | |
5766 | ||
5767 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
5768 | if (gpc) /* If incrementing then no need for the check below */ | |
5769 | return; | |
5770 | /* | |
5771 | * Check to see if a bad DMA write target from an errant or | |
5772 | * malicious VF has caused a PCIe error. If so then we can | |
5773 | * issue a VFLR to the offending VF(s) and then resume without | |
5774 | * requesting a full slot reset. | |
5775 | */ | |
5776 | ||
5777 | for (vf = 0; vf < adapter->num_vfs; vf++) { | |
5778 | ciaa = (vf << 16) | 0x80000000; | |
5779 | /* 32 bit read so align, we really want status at offset 6 */ | |
5780 | ciaa |= PCI_COMMAND; | |
5781 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5782 | ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599); | |
5783 | ciaa &= 0x7FFFFFFF; | |
5784 | /* disable debug mode asap after reading data */ | |
5785 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5786 | /* Get the upper 16 bits which will be the PCI status reg */ | |
5787 | ciad >>= 16; | |
5788 | if (ciad & PCI_STATUS_REC_MASTER_ABORT) { | |
5789 | netdev_err(netdev, "VF %d Hung DMA\n", vf); | |
5790 | /* Issue VFLR */ | |
5791 | ciaa = (vf << 16) | 0x80000000; | |
5792 | ciaa |= 0xA8; | |
5793 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5794 | ciad = 0x00008000; /* VFLR */ | |
5795 | IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad); | |
5796 | ciaa &= 0x7FFFFFFF; | |
5797 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5798 | } | |
5799 | } | |
5800 | } | |
5801 | ||
5802 | #endif | |
7086400d AD |
5803 | /** |
5804 | * ixgbe_service_timer - Timer Call-back | |
5805 | * @data: pointer to adapter cast into an unsigned long | |
5806 | **/ | |
5807 | static void ixgbe_service_timer(unsigned long data) | |
5808 | { | |
5809 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
5810 | unsigned long next_event_offset; | |
83c61fa9 | 5811 | bool ready = true; |
7086400d | 5812 | |
6bb78cfb AD |
5813 | /* poll faster when waiting for link */ |
5814 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
5815 | next_event_offset = HZ / 10; | |
5816 | else | |
5817 | next_event_offset = HZ * 2; | |
83c61fa9 | 5818 | |
6bb78cfb | 5819 | #ifdef CONFIG_PCI_IOV |
83c61fa9 GR |
5820 | /* |
5821 | * don't bother with SR-IOV VF DMA hang check if there are | |
5822 | * no VFs or the link is down | |
5823 | */ | |
5824 | if (!adapter->num_vfs || | |
6bb78cfb | 5825 | (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
83c61fa9 | 5826 | goto normal_timer_service; |
83c61fa9 GR |
5827 | |
5828 | /* If we have VFs allocated then we must check for DMA hangs */ | |
5829 | ixgbe_check_for_bad_vf(adapter); | |
5830 | next_event_offset = HZ / 50; | |
5831 | adapter->timer_event_accumulator++; | |
5832 | ||
6bb78cfb | 5833 | if (adapter->timer_event_accumulator >= 100) |
83c61fa9 | 5834 | adapter->timer_event_accumulator = 0; |
7086400d | 5835 | else |
6bb78cfb | 5836 | ready = false; |
7086400d | 5837 | |
6bb78cfb | 5838 | normal_timer_service: |
83c61fa9 | 5839 | #endif |
7086400d AD |
5840 | /* Reset the timer */ |
5841 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
5842 | ||
83c61fa9 GR |
5843 | if (ready) |
5844 | ixgbe_service_event_schedule(adapter); | |
7086400d AD |
5845 | } |
5846 | ||
c83c6cbd AD |
5847 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
5848 | { | |
5849 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
5850 | return; | |
5851 | ||
5852 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
5853 | ||
5854 | /* If we're already down or resetting, just bail */ | |
5855 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5856 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5857 | return; | |
5858 | ||
5859 | ixgbe_dump(adapter); | |
5860 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
5861 | adapter->tx_timeout_count++; | |
5862 | ||
5863 | ixgbe_reinit_locked(adapter); | |
5864 | } | |
5865 | ||
7086400d AD |
5866 | /** |
5867 | * ixgbe_service_task - manages and runs subtasks | |
5868 | * @work: pointer to work_struct containing our data | |
5869 | **/ | |
5870 | static void ixgbe_service_task(struct work_struct *work) | |
5871 | { | |
5872 | struct ixgbe_adapter *adapter = container_of(work, | |
5873 | struct ixgbe_adapter, | |
5874 | service_task); | |
5875 | ||
c83c6cbd | 5876 | ixgbe_reset_subtask(adapter); |
7086400d AD |
5877 | ixgbe_sfp_detection_subtask(adapter); |
5878 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 5879 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 5880 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 5881 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 5882 | ixgbe_check_hang_subtask(adapter); |
3a6a4eda | 5883 | ixgbe_ptp_overflow_check(adapter); |
7086400d AD |
5884 | |
5885 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
5886 | } |
5887 | ||
fd0db0ed AD |
5888 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
5889 | struct ixgbe_tx_buffer *first, | |
244e27ad | 5890 | u8 *hdr_len) |
897ab156 | 5891 | { |
fd0db0ed | 5892 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5893 | u32 vlan_macip_lens, type_tucmd; |
5894 | u32 mss_l4len_idx, l4len; | |
9a799d71 | 5895 | |
897ab156 AD |
5896 | if (!skb_is_gso(skb)) |
5897 | return 0; | |
9a799d71 | 5898 | |
897ab156 | 5899 | if (skb_header_cloned(skb)) { |
244e27ad | 5900 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
897ab156 AD |
5901 | if (err) |
5902 | return err; | |
9a799d71 | 5903 | } |
9a799d71 | 5904 | |
897ab156 AD |
5905 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
5906 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5907 | ||
244e27ad | 5908 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
897ab156 AD |
5909 | struct iphdr *iph = ip_hdr(skb); |
5910 | iph->tot_len = 0; | |
5911 | iph->check = 0; | |
5912 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5913 | iph->daddr, 0, | |
5914 | IPPROTO_TCP, | |
5915 | 0); | |
5916 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
244e27ad AD |
5917 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5918 | IXGBE_TX_FLAGS_CSUM | | |
5919 | IXGBE_TX_FLAGS_IPV4; | |
897ab156 AD |
5920 | } else if (skb_is_gso_v6(skb)) { |
5921 | ipv6_hdr(skb)->payload_len = 0; | |
5922 | tcp_hdr(skb)->check = | |
5923 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
5924 | &ipv6_hdr(skb)->daddr, | |
5925 | 0, IPPROTO_TCP, 0); | |
244e27ad AD |
5926 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5927 | IXGBE_TX_FLAGS_CSUM; | |
897ab156 AD |
5928 | } |
5929 | ||
091a6246 | 5930 | /* compute header lengths */ |
897ab156 AD |
5931 | l4len = tcp_hdrlen(skb); |
5932 | *hdr_len = skb_transport_offset(skb) + l4len; | |
5933 | ||
091a6246 AD |
5934 | /* update gso size and bytecount with header size */ |
5935 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
5936 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
5937 | ||
897ab156 AD |
5938 | /* mss_l4len_id: use 1 as index for TSO */ |
5939 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; | |
5940 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
5941 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
5942 | ||
5943 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
5944 | vlan_macip_lens = skb_network_header_len(skb); | |
5945 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
244e27ad | 5946 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
897ab156 AD |
5947 | |
5948 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
244e27ad | 5949 | mss_l4len_idx); |
897ab156 AD |
5950 | |
5951 | return 1; | |
5952 | } | |
5953 | ||
244e27ad AD |
5954 | static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, |
5955 | struct ixgbe_tx_buffer *first) | |
7ca647bd | 5956 | { |
fd0db0ed | 5957 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5958 | u32 vlan_macip_lens = 0; |
5959 | u32 mss_l4len_idx = 0; | |
5960 | u32 type_tucmd = 0; | |
7ca647bd | 5961 | |
897ab156 | 5962 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
62748b7b AD |
5963 | if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) { |
5964 | if (unlikely(skb->no_fcs)) | |
5965 | first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS; | |
5966 | if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW)) | |
5967 | return; | |
5968 | } | |
897ab156 AD |
5969 | } else { |
5970 | u8 l4_hdr = 0; | |
244e27ad | 5971 | switch (first->protocol) { |
897ab156 AD |
5972 | case __constant_htons(ETH_P_IP): |
5973 | vlan_macip_lens |= skb_network_header_len(skb); | |
5974 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
5975 | l4_hdr = ip_hdr(skb)->protocol; | |
7ca647bd | 5976 | break; |
897ab156 AD |
5977 | case __constant_htons(ETH_P_IPV6): |
5978 | vlan_macip_lens |= skb_network_header_len(skb); | |
5979 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
5980 | break; | |
5981 | default: | |
5982 | if (unlikely(net_ratelimit())) { | |
5983 | dev_warn(tx_ring->dev, | |
5984 | "partial checksum but proto=%x!\n", | |
244e27ad | 5985 | first->protocol); |
897ab156 | 5986 | } |
7ca647bd JP |
5987 | break; |
5988 | } | |
897ab156 AD |
5989 | |
5990 | switch (l4_hdr) { | |
7ca647bd | 5991 | case IPPROTO_TCP: |
897ab156 AD |
5992 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; |
5993 | mss_l4len_idx = tcp_hdrlen(skb) << | |
5994 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7ca647bd JP |
5995 | break; |
5996 | case IPPROTO_SCTP: | |
897ab156 AD |
5997 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
5998 | mss_l4len_idx = sizeof(struct sctphdr) << | |
5999 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
6000 | break; | |
6001 | case IPPROTO_UDP: | |
6002 | mss_l4len_idx = sizeof(struct udphdr) << | |
6003 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
6004 | break; | |
6005 | default: | |
6006 | if (unlikely(net_ratelimit())) { | |
6007 | dev_warn(tx_ring->dev, | |
6008 | "partial checksum but l4 proto=%x!\n", | |
244e27ad | 6009 | l4_hdr); |
897ab156 | 6010 | } |
7ca647bd JP |
6011 | break; |
6012 | } | |
244e27ad AD |
6013 | |
6014 | /* update TX checksum flag */ | |
6015 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7ca647bd JP |
6016 | } |
6017 | ||
244e27ad | 6018 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
897ab156 | 6019 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
244e27ad | 6020 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
9a799d71 | 6021 | |
897ab156 AD |
6022 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, |
6023 | type_tucmd, mss_l4len_idx); | |
9a799d71 AK |
6024 | } |
6025 | ||
d3d00239 | 6026 | static __le32 ixgbe_tx_cmd_type(u32 tx_flags) |
9a799d71 | 6027 | { |
d3d00239 AD |
6028 | /* set type for advanced descriptor with frame checksum insertion */ |
6029 | __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | | |
d3d00239 | 6030 | IXGBE_ADVTXD_DCMD_DEXT); |
9a799d71 | 6031 | |
d3d00239 | 6032 | /* set HW vlan bit if vlan is present */ |
66f32a8b | 6033 | if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN) |
d3d00239 | 6034 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); |
9a799d71 | 6035 | |
3a6a4eda JK |
6036 | if (tx_flags & IXGBE_TX_FLAGS_TSTAMP) |
6037 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP); | |
3a6a4eda | 6038 | |
d3d00239 AD |
6039 | /* set segmentation enable bits for TSO/FSO */ |
6040 | #ifdef IXGBE_FCOE | |
93f5b3c1 | 6041 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO)) |
d3d00239 AD |
6042 | #else |
6043 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
6044 | #endif | |
6045 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); | |
eacd73f7 | 6046 | |
62748b7b AD |
6047 | /* insert frame checksum */ |
6048 | if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS)) | |
6049 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS); | |
6050 | ||
d3d00239 AD |
6051 | return cmd_type; |
6052 | } | |
9a799d71 | 6053 | |
729739b7 AD |
6054 | static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
6055 | u32 tx_flags, unsigned int paylen) | |
d3d00239 | 6056 | { |
93f5b3c1 | 6057 | __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); |
9a799d71 | 6058 | |
d3d00239 AD |
6059 | /* enable L4 checksum for TSO and TX checksum offload */ |
6060 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
6061 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 6062 | |
93f5b3c1 AD |
6063 | /* enble IPv4 checksum for TSO */ |
6064 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
6065 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 6066 | |
93f5b3c1 AD |
6067 | /* use index 1 context for TSO/FSO/FCOE */ |
6068 | #ifdef IXGBE_FCOE | |
6069 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE)) | |
6070 | #else | |
6071 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
d3d00239 | 6072 | #endif |
93f5b3c1 AD |
6073 | olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT); |
6074 | ||
7f9643fd AD |
6075 | /* |
6076 | * Check Context must be set if Tx switch is enabled, which it | |
6077 | * always is for case where virtual functions are running | |
6078 | */ | |
93f5b3c1 AD |
6079 | #ifdef IXGBE_FCOE |
6080 | if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE)) | |
6081 | #else | |
7f9643fd | 6082 | if (tx_flags & IXGBE_TX_FLAGS_TXSW) |
93f5b3c1 | 6083 | #endif |
7f9643fd AD |
6084 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); |
6085 | ||
729739b7 | 6086 | tx_desc->read.olinfo_status = olinfo_status; |
d3d00239 | 6087 | } |
44df32c5 | 6088 | |
d3d00239 AD |
6089 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
6090 | IXGBE_TXD_CMD_RS) | |
6091 | ||
6092 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 | 6093 | struct ixgbe_tx_buffer *first, |
d3d00239 AD |
6094 | const u8 hdr_len) |
6095 | { | |
729739b7 | 6096 | dma_addr_t dma; |
fd0db0ed | 6097 | struct sk_buff *skb = first->skb; |
729739b7 | 6098 | struct ixgbe_tx_buffer *tx_buffer; |
d3d00239 | 6099 | union ixgbe_adv_tx_desc *tx_desc; |
729739b7 | 6100 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
d3d00239 AD |
6101 | unsigned int data_len = skb->data_len; |
6102 | unsigned int size = skb_headlen(skb); | |
729739b7 | 6103 | unsigned int paylen = skb->len - hdr_len; |
244e27ad | 6104 | u32 tx_flags = first->tx_flags; |
729739b7 | 6105 | __le32 cmd_type; |
d3d00239 | 6106 | u16 i = tx_ring->next_to_use; |
d3d00239 | 6107 | |
729739b7 AD |
6108 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
6109 | ||
6110 | ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen); | |
6111 | cmd_type = ixgbe_tx_cmd_type(tx_flags); | |
6112 | ||
d3d00239 AD |
6113 | #ifdef IXGBE_FCOE |
6114 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
729739b7 | 6115 | if (data_len < sizeof(struct fcoe_crc_eof)) { |
d3d00239 AD |
6116 | size -= sizeof(struct fcoe_crc_eof) - data_len; |
6117 | data_len = 0; | |
729739b7 AD |
6118 | } else { |
6119 | data_len -= sizeof(struct fcoe_crc_eof); | |
9a799d71 AK |
6120 | } |
6121 | } | |
44df32c5 | 6122 | |
d3d00239 | 6123 | #endif |
729739b7 AD |
6124 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
6125 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 6126 | goto dma_error; |
8ad494b0 | 6127 | |
729739b7 AD |
6128 | /* record length, and DMA address */ |
6129 | dma_unmap_len_set(first, len, size); | |
6130 | dma_unmap_addr_set(first, dma, dma); | |
9a799d71 | 6131 | |
729739b7 | 6132 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
e5a43549 | 6133 | |
d3d00239 | 6134 | for (;;) { |
729739b7 | 6135 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
d3d00239 AD |
6136 | tx_desc->read.cmd_type_len = |
6137 | cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); | |
e5a43549 | 6138 | |
d3d00239 | 6139 | i++; |
729739b7 | 6140 | tx_desc++; |
d3d00239 | 6141 | if (i == tx_ring->count) { |
e4f74028 | 6142 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
6143 | i = 0; |
6144 | } | |
729739b7 AD |
6145 | |
6146 | dma += IXGBE_MAX_DATA_PER_TXD; | |
6147 | size -= IXGBE_MAX_DATA_PER_TXD; | |
6148 | ||
6149 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
6150 | tx_desc->read.olinfo_status = 0; | |
d3d00239 | 6151 | } |
e5a43549 | 6152 | |
729739b7 AD |
6153 | if (likely(!data_len)) |
6154 | break; | |
9a799d71 | 6155 | |
d3d00239 | 6156 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
9a799d71 | 6157 | |
729739b7 AD |
6158 | i++; |
6159 | tx_desc++; | |
6160 | if (i == tx_ring->count) { | |
6161 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
6162 | i = 0; | |
6163 | } | |
9a799d71 | 6164 | |
d3d00239 | 6165 | #ifdef IXGBE_FCOE |
9e903e08 | 6166 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 6167 | #else |
9e903e08 | 6168 | size = skb_frag_size(frag); |
d3d00239 AD |
6169 | #endif |
6170 | data_len -= size; | |
9a799d71 | 6171 | |
729739b7 AD |
6172 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
6173 | DMA_TO_DEVICE); | |
6174 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 6175 | goto dma_error; |
9a799d71 | 6176 | |
729739b7 AD |
6177 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6178 | dma_unmap_len_set(tx_buffer, len, size); | |
6179 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
9a799d71 | 6180 | |
729739b7 AD |
6181 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
6182 | tx_desc->read.olinfo_status = 0; | |
9a799d71 | 6183 | |
729739b7 AD |
6184 | frag++; |
6185 | } | |
9a799d71 | 6186 | |
729739b7 AD |
6187 | /* write last descriptor with RS and EOP bits */ |
6188 | cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD); | |
6189 | tx_desc->read.cmd_type_len = cmd_type; | |
eacd73f7 | 6190 | |
091a6246 | 6191 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
b2d96e0a | 6192 | |
d3d00239 AD |
6193 | /* set the timestamp */ |
6194 | first->time_stamp = jiffies; | |
9a799d71 AK |
6195 | |
6196 | /* | |
729739b7 AD |
6197 | * Force memory writes to complete before letting h/w know there |
6198 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
6199 | * memory model archs, such as IA-64). | |
6200 | * | |
6201 | * We also need this memory barrier to make certain all of the | |
6202 | * status bits have been updated before next_to_watch is written. | |
9a799d71 AK |
6203 | */ |
6204 | wmb(); | |
6205 | ||
d3d00239 AD |
6206 | /* set next_to_watch value indicating a packet is present */ |
6207 | first->next_to_watch = tx_desc; | |
6208 | ||
729739b7 AD |
6209 | i++; |
6210 | if (i == tx_ring->count) | |
6211 | i = 0; | |
6212 | ||
6213 | tx_ring->next_to_use = i; | |
6214 | ||
d3d00239 | 6215 | /* notify HW of packet */ |
84ea2591 | 6216 | writel(i, tx_ring->tail); |
d3d00239 AD |
6217 | |
6218 | return; | |
6219 | dma_error: | |
729739b7 | 6220 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
d3d00239 AD |
6221 | |
6222 | /* clear dma mappings for failed tx_buffer_info map */ | |
6223 | for (;;) { | |
729739b7 AD |
6224 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6225 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
6226 | if (tx_buffer == first) | |
d3d00239 AD |
6227 | break; |
6228 | if (i == 0) | |
6229 | i = tx_ring->count; | |
6230 | i--; | |
6231 | } | |
6232 | ||
d3d00239 | 6233 | tx_ring->next_to_use = i; |
9a799d71 AK |
6234 | } |
6235 | ||
fd0db0ed | 6236 | static void ixgbe_atr(struct ixgbe_ring *ring, |
244e27ad | 6237 | struct ixgbe_tx_buffer *first) |
69830529 AD |
6238 | { |
6239 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6240 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6241 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6242 | union { | |
6243 | unsigned char *network; | |
6244 | struct iphdr *ipv4; | |
6245 | struct ipv6hdr *ipv6; | |
6246 | } hdr; | |
ee9e0f0b | 6247 | struct tcphdr *th; |
905e4a41 | 6248 | __be16 vlan_id; |
c4cf55e5 | 6249 | |
69830529 AD |
6250 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6251 | if (!q_vector) | |
6252 | return; | |
6253 | ||
6254 | /* do nothing if sampling is disabled */ | |
6255 | if (!ring->atr_sample_rate) | |
d3ead241 | 6256 | return; |
c4cf55e5 | 6257 | |
69830529 | 6258 | ring->atr_count++; |
c4cf55e5 | 6259 | |
69830529 | 6260 | /* snag network header to get L4 type and address */ |
fd0db0ed | 6261 | hdr.network = skb_network_header(first->skb); |
69830529 AD |
6262 | |
6263 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
244e27ad | 6264 | if ((first->protocol != __constant_htons(ETH_P_IPV6) || |
69830529 | 6265 | hdr.ipv6->nexthdr != IPPROTO_TCP) && |
244e27ad | 6266 | (first->protocol != __constant_htons(ETH_P_IP) || |
69830529 AD |
6267 | hdr.ipv4->protocol != IPPROTO_TCP)) |
6268 | return; | |
ee9e0f0b | 6269 | |
fd0db0ed | 6270 | th = tcp_hdr(first->skb); |
c4cf55e5 | 6271 | |
66f32a8b AD |
6272 | /* skip this packet since it is invalid or the socket is closing */ |
6273 | if (!th || th->fin) | |
69830529 AD |
6274 | return; |
6275 | ||
6276 | /* sample on all syn packets or once every atr sample count */ | |
6277 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6278 | return; | |
6279 | ||
6280 | /* reset sample count */ | |
6281 | ring->atr_count = 0; | |
6282 | ||
244e27ad | 6283 | vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); |
69830529 AD |
6284 | |
6285 | /* | |
6286 | * src and dst are inverted, think how the receiver sees them | |
6287 | * | |
6288 | * The input is broken into two sections, a non-compressed section | |
6289 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6290 | * is XORed together and stored in the compressed dword. | |
6291 | */ | |
6292 | input.formatted.vlan_id = vlan_id; | |
6293 | ||
6294 | /* | |
6295 | * since src port and flex bytes occupy the same word XOR them together | |
6296 | * and write the value to source port portion of compressed dword | |
6297 | */ | |
244e27ad | 6298 | if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
69830529 AD |
6299 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); |
6300 | else | |
244e27ad | 6301 | common.port.src ^= th->dest ^ first->protocol; |
69830529 AD |
6302 | common.port.dst ^= th->source; |
6303 | ||
244e27ad | 6304 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
69830529 AD |
6305 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; |
6306 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6307 | } else { | |
6308 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6309 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6310 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6311 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6312 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6313 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6314 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6315 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6316 | hdr.ipv6->daddr.s6_addr32[3]; | |
6317 | } | |
c4cf55e5 PWJ |
6318 | |
6319 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6320 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6321 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6322 | } |
6323 | ||
63544e9c | 6324 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6325 | { |
fc77dc3c | 6326 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6327 | /* Herbert's original patch had: |
6328 | * smp_mb__after_netif_stop_queue(); | |
6329 | * but since that doesn't exist yet, just open code it. */ | |
6330 | smp_mb(); | |
6331 | ||
6332 | /* We need to check again in a case another CPU has just | |
6333 | * made room available. */ | |
7d4987de | 6334 | if (likely(ixgbe_desc_unused(tx_ring) < size)) |
e092be60 AV |
6335 | return -EBUSY; |
6336 | ||
6337 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 6338 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 6339 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
6340 | return 0; |
6341 | } | |
6342 | ||
82d4e46e | 6343 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6344 | { |
7d4987de | 6345 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) |
e092be60 | 6346 | return 0; |
fc77dc3c | 6347 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
6348 | } |
6349 | ||
09a3b1f8 SH |
6350 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6351 | { | |
6352 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6440752c AD |
6353 | int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
6354 | smp_processor_id(); | |
56075a98 | 6355 | #ifdef IXGBE_FCOE |
6440752c | 6356 | __be16 protocol = vlan_get_protocol(skb); |
5e09a105 | 6357 | |
e5b64635 JF |
6358 | if (((protocol == htons(ETH_P_FCOE)) || |
6359 | (protocol == htons(ETH_P_FIP))) && | |
6360 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
c087663e AD |
6361 | struct ixgbe_ring_feature *f; |
6362 | ||
6363 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6364 | ||
6365 | while (txq >= f->indices) | |
6366 | txq -= f->indices; | |
e4b317e9 | 6367 | txq += adapter->ring_feature[RING_F_FCOE].offset; |
c087663e | 6368 | |
e5b64635 | 6369 | return txq; |
56075a98 JF |
6370 | } |
6371 | #endif | |
6372 | ||
fdd3d631 KK |
6373 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6374 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6375 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6376 | return txq; |
fdd3d631 | 6377 | } |
c4cf55e5 | 6378 | |
09a3b1f8 SH |
6379 | return skb_tx_hash(dev, skb); |
6380 | } | |
6381 | ||
fc77dc3c | 6382 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
6383 | struct ixgbe_adapter *adapter, |
6384 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6385 | { |
d3d00239 | 6386 | struct ixgbe_tx_buffer *first; |
5f715823 | 6387 | int tso; |
d3d00239 | 6388 | u32 tx_flags = 0; |
a535c30e AD |
6389 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD |
6390 | unsigned short f; | |
6391 | #endif | |
a535c30e | 6392 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 6393 | __be16 protocol = skb->protocol; |
63544e9c | 6394 | u8 hdr_len = 0; |
5e09a105 | 6395 | |
a535c30e AD |
6396 | /* |
6397 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 6398 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
6399 | * + 2 desc gap to keep tail from touching head, |
6400 | * + 1 desc for context descriptor, | |
6401 | * otherwise try next time | |
6402 | */ | |
6403 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
6404 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
6405 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
6406 | #else | |
6407 | count += skb_shinfo(skb)->nr_frags; | |
6408 | #endif | |
6409 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { | |
6410 | tx_ring->tx_stats.tx_busy++; | |
6411 | return NETDEV_TX_BUSY; | |
6412 | } | |
6413 | ||
fd0db0ed AD |
6414 | /* record the location of the first descriptor for this packet */ |
6415 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
6416 | first->skb = skb; | |
091a6246 AD |
6417 | first->bytecount = skb->len; |
6418 | first->gso_segs = 1; | |
fd0db0ed | 6419 | |
66f32a8b | 6420 | /* if we have a HW VLAN tag being added default to the HW one */ |
eab6d18d | 6421 | if (vlan_tx_tag_present(skb)) { |
66f32a8b AD |
6422 | tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; |
6423 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
6424 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
6425 | } else if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6426 | struct vlan_hdr *vhdr, _vhdr; | |
6427 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
6428 | if (!vhdr) | |
6429 | goto out_drop; | |
6430 | ||
6431 | protocol = vhdr->h_vlan_encapsulated_proto; | |
9e0c5648 AD |
6432 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
6433 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
6434 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
6435 | } | |
6436 | ||
aa7bd467 JK |
6437 | skb_tx_timestamp(skb); |
6438 | ||
3a6a4eda JK |
6439 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { |
6440 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
6441 | tx_flags |= IXGBE_TX_FLAGS_TSTAMP; | |
6442 | } | |
3a6a4eda | 6443 | |
9e0c5648 AD |
6444 | #ifdef CONFIG_PCI_IOV |
6445 | /* | |
6446 | * Use the l2switch_enable flag - would be false if the DMA | |
6447 | * Tx switch had been disabled. | |
6448 | */ | |
6449 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6450 | tx_flags |= IXGBE_TX_FLAGS_TXSW; | |
6451 | ||
6452 | #endif | |
32701dc2 | 6453 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 6454 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
6455 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
6456 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 6457 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
6458 | tx_flags |= (skb->priority & 0x7) << |
6459 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
6460 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
6461 | struct vlan_ethhdr *vhdr; | |
6462 | if (skb_header_cloned(skb) && | |
6463 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) | |
6464 | goto out_drop; | |
6465 | vhdr = (struct vlan_ethhdr *)skb->data; | |
6466 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
6467 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6468 | } else { | |
6469 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 6470 | } |
9a799d71 | 6471 | } |
eacd73f7 | 6472 | |
244e27ad AD |
6473 | /* record initial flags and protocol */ |
6474 | first->tx_flags = tx_flags; | |
6475 | first->protocol = protocol; | |
6476 | ||
eacd73f7 | 6477 | #ifdef IXGBE_FCOE |
66f32a8b AD |
6478 | /* setup tx offload for FCoE */ |
6479 | if ((protocol == __constant_htons(ETH_P_FCOE)) && | |
a58915c7 | 6480 | (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { |
244e27ad | 6481 | tso = ixgbe_fso(tx_ring, first, &hdr_len); |
897ab156 AD |
6482 | if (tso < 0) |
6483 | goto out_drop; | |
9a799d71 | 6484 | |
66f32a8b | 6485 | goto xmit_fcoe; |
eacd73f7 | 6486 | } |
9a799d71 | 6487 | |
66f32a8b | 6488 | #endif /* IXGBE_FCOE */ |
244e27ad | 6489 | tso = ixgbe_tso(tx_ring, first, &hdr_len); |
66f32a8b | 6490 | if (tso < 0) |
897ab156 | 6491 | goto out_drop; |
244e27ad AD |
6492 | else if (!tso) |
6493 | ixgbe_tx_csum(tx_ring, first); | |
66f32a8b AD |
6494 | |
6495 | /* add the ATR filter if ATR is on */ | |
6496 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
244e27ad | 6497 | ixgbe_atr(tx_ring, first); |
66f32a8b AD |
6498 | |
6499 | #ifdef IXGBE_FCOE | |
6500 | xmit_fcoe: | |
6501 | #endif /* IXGBE_FCOE */ | |
244e27ad | 6502 | ixgbe_tx_map(tx_ring, first, hdr_len); |
d3d00239 AD |
6503 | |
6504 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
9a799d71 AK |
6505 | |
6506 | return NETDEV_TX_OK; | |
897ab156 AD |
6507 | |
6508 | out_drop: | |
fd0db0ed AD |
6509 | dev_kfree_skb_any(first->skb); |
6510 | first->skb = NULL; | |
6511 | ||
897ab156 | 6512 | return NETDEV_TX_OK; |
9a799d71 AK |
6513 | } |
6514 | ||
a50c29dd AD |
6515 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
6516 | struct net_device *netdev) | |
84418e3b AD |
6517 | { |
6518 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6519 | struct ixgbe_ring *tx_ring; | |
6520 | ||
a50c29dd AD |
6521 | /* |
6522 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
6523 | * in order to meet this minimum size requirement. | |
6524 | */ | |
f73332fc SH |
6525 | if (unlikely(skb->len < 17)) { |
6526 | if (skb_pad(skb, 17 - skb->len)) | |
a50c29dd AD |
6527 | return NETDEV_TX_OK; |
6528 | skb->len = 17; | |
71a49f77 | 6529 | skb_set_tail_pointer(skb, 17); |
a50c29dd AD |
6530 | } |
6531 | ||
84418e3b | 6532 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
fc77dc3c | 6533 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
6534 | } |
6535 | ||
9a799d71 AK |
6536 | /** |
6537 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6538 | * @netdev: network interface device structure | |
6539 | * @p: pointer to an address structure | |
6540 | * | |
6541 | * Returns 0 on success, negative on failure | |
6542 | **/ | |
6543 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6544 | { | |
6545 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6546 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6547 | struct sockaddr *addr = p; |
6548 | ||
6549 | if (!is_valid_ether_addr(addr->sa_data)) | |
6550 | return -EADDRNOTAVAIL; | |
6551 | ||
6552 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6553 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6554 | |
1d9c0bfd | 6555 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV); |
9a799d71 AK |
6556 | |
6557 | return 0; | |
6558 | } | |
6559 | ||
6b73e10d BH |
6560 | static int |
6561 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6562 | { | |
6563 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6564 | struct ixgbe_hw *hw = &adapter->hw; | |
6565 | u16 value; | |
6566 | int rc; | |
6567 | ||
6568 | if (prtad != hw->phy.mdio.prtad) | |
6569 | return -EINVAL; | |
6570 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6571 | if (!rc) | |
6572 | rc = value; | |
6573 | return rc; | |
6574 | } | |
6575 | ||
6576 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6577 | u16 addr, u16 value) | |
6578 | { | |
6579 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6580 | struct ixgbe_hw *hw = &adapter->hw; | |
6581 | ||
6582 | if (prtad != hw->phy.mdio.prtad) | |
6583 | return -EINVAL; | |
6584 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6585 | } | |
6586 | ||
6587 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6588 | { | |
6589 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6590 | ||
3a6a4eda | 6591 | switch (cmd) { |
3a6a4eda JK |
6592 | case SIOCSHWTSTAMP: |
6593 | return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd); | |
3a6a4eda JK |
6594 | default: |
6595 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6596 | } | |
6b73e10d BH |
6597 | } |
6598 | ||
0365e6e4 PW |
6599 | /** |
6600 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6601 | * netdev->dev_addrs |
0365e6e4 PW |
6602 | * @netdev: network interface device structure |
6603 | * | |
6604 | * Returns non-zero on failure | |
6605 | **/ | |
6606 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6607 | { | |
6608 | int err = 0; | |
6609 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7fa7c9dc | 6610 | struct ixgbe_hw *hw = &adapter->hw; |
0365e6e4 | 6611 | |
7fa7c9dc | 6612 | if (is_valid_ether_addr(hw->mac.san_addr)) { |
0365e6e4 | 6613 | rtnl_lock(); |
7fa7c9dc | 6614 | err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); |
0365e6e4 | 6615 | rtnl_unlock(); |
7fa7c9dc AD |
6616 | |
6617 | /* update SAN MAC vmdq pool selection */ | |
6618 | hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); | |
0365e6e4 PW |
6619 | } |
6620 | return err; | |
6621 | } | |
6622 | ||
6623 | /** | |
6624 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6625 | * netdev->dev_addrs |
0365e6e4 PW |
6626 | * @netdev: network interface device structure |
6627 | * | |
6628 | * Returns non-zero on failure | |
6629 | **/ | |
6630 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6631 | { | |
6632 | int err = 0; | |
6633 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6634 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6635 | ||
6636 | if (is_valid_ether_addr(mac->san_addr)) { | |
6637 | rtnl_lock(); | |
6638 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6639 | rtnl_unlock(); | |
6640 | } | |
6641 | return err; | |
6642 | } | |
6643 | ||
9a799d71 AK |
6644 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6645 | /* | |
6646 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6647 | * without having to re-enable interrupts. It's not called while | |
6648 | * the interrupt routine is executing. | |
6649 | */ | |
6650 | static void ixgbe_netpoll(struct net_device *netdev) | |
6651 | { | |
6652 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6653 | int i; |
9a799d71 | 6654 | |
1a647bd2 AD |
6655 | /* if interface is down do nothing */ |
6656 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6657 | return; | |
6658 | ||
9a799d71 | 6659 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 | 6660 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
49c7ffbe AD |
6661 | for (i = 0; i < adapter->num_q_vectors; i++) |
6662 | ixgbe_msix_clean_rings(0, adapter->q_vector[i]); | |
8f9a7167 PWJ |
6663 | } else { |
6664 | ixgbe_intr(adapter->pdev->irq, netdev); | |
6665 | } | |
9a799d71 | 6666 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 | 6667 | } |
9a799d71 | 6668 | |
581330ba | 6669 | #endif |
de1036b1 ED |
6670 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
6671 | struct rtnl_link_stats64 *stats) | |
6672 | { | |
6673 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6674 | int i; | |
6675 | ||
1a51502b | 6676 | rcu_read_lock(); |
de1036b1 | 6677 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 6678 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
6679 | u64 bytes, packets; |
6680 | unsigned int start; | |
6681 | ||
1a51502b ED |
6682 | if (ring) { |
6683 | do { | |
6684 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6685 | packets = ring->stats.packets; | |
6686 | bytes = ring->stats.bytes; | |
6687 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6688 | stats->rx_packets += packets; | |
6689 | stats->rx_bytes += bytes; | |
6690 | } | |
de1036b1 | 6691 | } |
1ac9ad13 ED |
6692 | |
6693 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
6694 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
6695 | u64 bytes, packets; | |
6696 | unsigned int start; | |
6697 | ||
6698 | if (ring) { | |
6699 | do { | |
6700 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6701 | packets = ring->stats.packets; | |
6702 | bytes = ring->stats.bytes; | |
6703 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6704 | stats->tx_packets += packets; | |
6705 | stats->tx_bytes += bytes; | |
6706 | } | |
6707 | } | |
1a51502b | 6708 | rcu_read_unlock(); |
de1036b1 ED |
6709 | /* following stats updated by ixgbe_watchdog_task() */ |
6710 | stats->multicast = netdev->stats.multicast; | |
6711 | stats->rx_errors = netdev->stats.rx_errors; | |
6712 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
6713 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
6714 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
6715 | return stats; | |
6716 | } | |
6717 | ||
8af3c33f | 6718 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c BH |
6719 | /** |
6720 | * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. | |
6721 | * @adapter: pointer to ixgbe_adapter | |
8b1c0b24 JF |
6722 | * @tc: number of traffic classes currently enabled |
6723 | * | |
6724 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
6725 | * 802.1Q priority maps to a packet buffer that exists. | |
6726 | */ | |
6727 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
6728 | { | |
6729 | struct ixgbe_hw *hw = &adapter->hw; | |
6730 | u32 reg, rsave; | |
6731 | int i; | |
6732 | ||
6733 | /* 82598 have a static priority to TC mapping that can not | |
6734 | * be changed so no validation is needed. | |
6735 | */ | |
6736 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6737 | return; | |
6738 | ||
6739 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
6740 | rsave = reg; | |
6741 | ||
6742 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
6743 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
6744 | ||
6745 | /* If up2tc is out of bounds default to zero */ | |
6746 | if (up2tc > tc) | |
6747 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
6748 | } | |
6749 | ||
6750 | if (reg != rsave) | |
6751 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
6752 | ||
6753 | return; | |
6754 | } | |
6755 | ||
02debdc9 AD |
6756 | /** |
6757 | * ixgbe_set_prio_tc_map - Configure netdev prio tc map | |
6758 | * @adapter: Pointer to adapter struct | |
6759 | * | |
6760 | * Populate the netdev user priority to tc map | |
6761 | */ | |
6762 | static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) | |
6763 | { | |
6764 | struct net_device *dev = adapter->netdev; | |
6765 | struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; | |
6766 | struct ieee_ets *ets = adapter->ixgbe_ieee_ets; | |
6767 | u8 prio; | |
6768 | ||
6769 | for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { | |
6770 | u8 tc = 0; | |
6771 | ||
6772 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) | |
6773 | tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); | |
6774 | else if (ets) | |
6775 | tc = ets->prio_tc[prio]; | |
6776 | ||
6777 | netdev_set_prio_tc_map(dev, prio, tc); | |
6778 | } | |
6779 | } | |
6780 | ||
49ce9c2c BH |
6781 | /** |
6782 | * ixgbe_setup_tc - configure net_device for multiple traffic classes | |
8b1c0b24 JF |
6783 | * |
6784 | * @netdev: net device to configure | |
6785 | * @tc: number of traffic classes to enable | |
6786 | */ | |
6787 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
6788 | { | |
8b1c0b24 JF |
6789 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
6790 | struct ixgbe_hw *hw = &adapter->hw; | |
8b1c0b24 | 6791 | |
8b1c0b24 | 6792 | /* Hardware supports up to 8 traffic classes */ |
4de2a022 | 6793 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || |
581330ba AD |
6794 | (hw->mac.type == ixgbe_mac_82598EB && |
6795 | tc < MAX_TRAFFIC_CLASS)) | |
8b1c0b24 JF |
6796 | return -EINVAL; |
6797 | ||
6798 | /* Hardware has to reinitialize queues and interrupts to | |
52f33af8 | 6799 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
6800 | * hardware is not flexible enough to do this dynamically. |
6801 | */ | |
6802 | if (netif_running(dev)) | |
6803 | ixgbe_close(dev); | |
6804 | ixgbe_clear_interrupt_scheme(adapter); | |
6805 | ||
e7589eab | 6806 | if (tc) { |
8b1c0b24 | 6807 | netdev_set_num_tc(dev, tc); |
02debdc9 AD |
6808 | ixgbe_set_prio_tc_map(adapter); |
6809 | ||
e7589eab | 6810 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
e7589eab | 6811 | |
943561d3 AD |
6812 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
6813 | adapter->last_lfc_mode = adapter->hw.fc.requested_mode; | |
e7589eab | 6814 | adapter->hw.fc.requested_mode = ixgbe_fc_none; |
943561d3 | 6815 | } |
e7589eab | 6816 | } else { |
8b1c0b24 | 6817 | netdev_reset_tc(dev); |
02debdc9 | 6818 | |
943561d3 AD |
6819 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
6820 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; | |
e7589eab JF |
6821 | |
6822 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
e7589eab JF |
6823 | |
6824 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
6825 | adapter->dcb_cfg.pfc_mode_enable = false; | |
6826 | } | |
6827 | ||
8b1c0b24 JF |
6828 | ixgbe_init_interrupt_scheme(adapter); |
6829 | ixgbe_validate_rtr(adapter, tc); | |
6830 | if (netif_running(dev)) | |
6831 | ixgbe_open(dev); | |
6832 | ||
6833 | return 0; | |
6834 | } | |
de1036b1 | 6835 | |
8af3c33f | 6836 | #endif /* CONFIG_IXGBE_DCB */ |
082757af DS |
6837 | void ixgbe_do_reset(struct net_device *netdev) |
6838 | { | |
6839 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6840 | ||
6841 | if (netif_running(netdev)) | |
6842 | ixgbe_reinit_locked(adapter); | |
6843 | else | |
6844 | ixgbe_reset(adapter); | |
6845 | } | |
6846 | ||
c8f44aff | 6847 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
567d2de2 | 6848 | netdev_features_t features) |
082757af DS |
6849 | { |
6850 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6851 | ||
082757af | 6852 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ |
567d2de2 AD |
6853 | if (!(features & NETIF_F_RXCSUM)) |
6854 | features &= ~NETIF_F_LRO; | |
082757af | 6855 | |
567d2de2 AD |
6856 | /* Turn off LRO if not RSC capable */ |
6857 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) | |
6858 | features &= ~NETIF_F_LRO; | |
8e2813f5 | 6859 | |
567d2de2 | 6860 | return features; |
082757af DS |
6861 | } |
6862 | ||
c8f44aff | 6863 | static int ixgbe_set_features(struct net_device *netdev, |
567d2de2 | 6864 | netdev_features_t features) |
082757af DS |
6865 | { |
6866 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
567d2de2 | 6867 | netdev_features_t changed = netdev->features ^ features; |
082757af DS |
6868 | bool need_reset = false; |
6869 | ||
082757af | 6870 | /* Make sure RSC matches LRO, reset if change */ |
567d2de2 AD |
6871 | if (!(features & NETIF_F_LRO)) { |
6872 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
082757af | 6873 | need_reset = true; |
567d2de2 AD |
6874 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; |
6875 | } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && | |
6876 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
6877 | if (adapter->rx_itr_setting == 1 || | |
6878 | adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { | |
6879 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
6880 | need_reset = true; | |
6881 | } else if ((changed ^ features) & NETIF_F_LRO) { | |
6882 | e_info(probe, "rx-usecs set too low, " | |
6883 | "disabling RSC\n"); | |
082757af DS |
6884 | } |
6885 | } | |
6886 | ||
6887 | /* | |
6888 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
6889 | * the state changed, we need to reset. | |
6890 | */ | |
39cb681b AD |
6891 | switch (features & NETIF_F_NTUPLE) { |
6892 | case NETIF_F_NTUPLE: | |
567d2de2 | 6893 | /* turn off ATR, enable perfect filters and reset */ |
39cb681b AD |
6894 | if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) |
6895 | need_reset = true; | |
6896 | ||
567d2de2 AD |
6897 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
6898 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
39cb681b AD |
6899 | break; |
6900 | default: | |
6901 | /* turn off perfect filters, enable ATR and reset */ | |
6902 | if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
6903 | need_reset = true; | |
6904 | ||
6905 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
6906 | ||
6907 | /* We cannot enable ATR if SR-IOV is enabled */ | |
6908 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6909 | break; | |
6910 | ||
6911 | /* We cannot enable ATR if we have 2 or more traffic classes */ | |
6912 | if (netdev_get_num_tc(netdev) > 1) | |
6913 | break; | |
6914 | ||
6915 | /* We cannot enable ATR if RSS is disabled */ | |
6916 | if (adapter->ring_feature[RING_F_RSS].limit <= 1) | |
6917 | break; | |
6918 | ||
6919 | /* A sample rate of 0 indicates ATR disabled */ | |
6920 | if (!adapter->atr_sample_rate) | |
6921 | break; | |
6922 | ||
6923 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6924 | break; | |
082757af DS |
6925 | } |
6926 | ||
146d4cc9 JF |
6927 | if (features & NETIF_F_HW_VLAN_RX) |
6928 | ixgbe_vlan_strip_enable(adapter); | |
6929 | else | |
6930 | ixgbe_vlan_strip_disable(adapter); | |
6931 | ||
3f2d1c0f BG |
6932 | if (changed & NETIF_F_RXALL) |
6933 | need_reset = true; | |
6934 | ||
567d2de2 | 6935 | netdev->features = features; |
082757af DS |
6936 | if (need_reset) |
6937 | ixgbe_do_reset(netdev); | |
6938 | ||
6939 | return 0; | |
082757af DS |
6940 | } |
6941 | ||
edc7d573 | 6942 | static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], |
0f4b0add | 6943 | struct net_device *dev, |
6b6e2725 | 6944 | const unsigned char *addr, |
0f4b0add JF |
6945 | u16 flags) |
6946 | { | |
6947 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
95447461 JF |
6948 | int err; |
6949 | ||
6950 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
6951 | return -EOPNOTSUPP; | |
0f4b0add | 6952 | |
b1ac1ef7 JF |
6953 | /* Hardware does not support aging addresses so if a |
6954 | * ndm_state is given only allow permanent addresses | |
6955 | */ | |
6956 | if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) { | |
0f4b0add JF |
6957 | pr_info("%s: FDB only supports static addresses\n", |
6958 | ixgbe_driver_name); | |
6959 | return -EINVAL; | |
6960 | } | |
6961 | ||
46acc460 | 6962 | if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { |
95447461 JF |
6963 | u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS; |
6964 | ||
6965 | if (netdev_uc_count(dev) < rar_uc_entries) | |
0f4b0add | 6966 | err = dev_uc_add_excl(dev, addr); |
0f4b0add | 6967 | else |
95447461 JF |
6968 | err = -ENOMEM; |
6969 | } else if (is_multicast_ether_addr(addr)) { | |
6970 | err = dev_mc_add_excl(dev, addr); | |
6971 | } else { | |
6972 | err = -EINVAL; | |
0f4b0add JF |
6973 | } |
6974 | ||
6975 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
6976 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
6977 | err = 0; | |
6978 | ||
6979 | return err; | |
6980 | } | |
6981 | ||
6982 | static int ixgbe_ndo_fdb_del(struct ndmsg *ndm, | |
6983 | struct net_device *dev, | |
6b6e2725 | 6984 | const unsigned char *addr) |
0f4b0add JF |
6985 | { |
6986 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6987 | int err = -EOPNOTSUPP; | |
6988 | ||
6989 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6990 | pr_info("%s: FDB only supports static addresses\n", | |
6991 | ixgbe_driver_name); | |
6992 | return -EINVAL; | |
6993 | } | |
6994 | ||
6995 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
6996 | if (is_unicast_ether_addr(addr)) | |
6997 | err = dev_uc_del(dev, addr); | |
6998 | else if (is_multicast_ether_addr(addr)) | |
6999 | err = dev_mc_del(dev, addr); | |
7000 | else | |
7001 | err = -EINVAL; | |
7002 | } | |
7003 | ||
7004 | return err; | |
7005 | } | |
7006 | ||
7007 | static int ixgbe_ndo_fdb_dump(struct sk_buff *skb, | |
7008 | struct netlink_callback *cb, | |
7009 | struct net_device *dev, | |
7010 | int idx) | |
7011 | { | |
7012 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7013 | ||
7014 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
7015 | idx = ndo_dflt_fdb_dump(skb, cb, dev, idx); | |
7016 | ||
7017 | return idx; | |
7018 | } | |
7019 | ||
815cccbf JF |
7020 | static int ixgbe_ndo_bridge_setlink(struct net_device *dev, |
7021 | struct nlmsghdr *nlh) | |
7022 | { | |
7023 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7024 | struct nlattr *attr, *br_spec; | |
7025 | int rem; | |
7026 | ||
7027 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
7028 | return -EOPNOTSUPP; | |
7029 | ||
7030 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
7031 | ||
7032 | nla_for_each_nested(attr, br_spec, rem) { | |
7033 | __u16 mode; | |
7034 | u32 reg = 0; | |
7035 | ||
7036 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
7037 | continue; | |
7038 | ||
7039 | mode = nla_get_u16(attr); | |
9b735984 | 7040 | if (mode == BRIDGE_MODE_VEPA) { |
815cccbf | 7041 | reg = 0; |
9b735984 GR |
7042 | adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB; |
7043 | } else if (mode == BRIDGE_MODE_VEB) { | |
815cccbf | 7044 | reg = IXGBE_PFDTXGSWC_VT_LBEN; |
9b735984 GR |
7045 | adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB; |
7046 | } else | |
815cccbf JF |
7047 | return -EINVAL; |
7048 | ||
7049 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg); | |
7050 | ||
7051 | e_info(drv, "enabling bridge mode: %s\n", | |
7052 | mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); | |
7053 | } | |
7054 | ||
7055 | return 0; | |
7056 | } | |
7057 | ||
7058 | static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, | |
7059 | struct net_device *dev) | |
7060 | { | |
7061 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7062 | u16 mode; | |
7063 | ||
7064 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
7065 | return 0; | |
7066 | ||
9b735984 | 7067 | if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) |
815cccbf JF |
7068 | mode = BRIDGE_MODE_VEB; |
7069 | else | |
7070 | mode = BRIDGE_MODE_VEPA; | |
7071 | ||
7072 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode); | |
7073 | } | |
7074 | ||
0edc3527 | 7075 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 7076 | .ndo_open = ixgbe_open, |
0edc3527 | 7077 | .ndo_stop = ixgbe_close, |
00829823 | 7078 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 7079 | .ndo_select_queue = ixgbe_select_queue, |
581330ba | 7080 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
7081 | .ndo_validate_addr = eth_validate_addr, |
7082 | .ndo_set_mac_address = ixgbe_set_mac, | |
7083 | .ndo_change_mtu = ixgbe_change_mtu, | |
7084 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
7085 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
7086 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 7087 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
7088 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
7089 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
7090 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
581330ba | 7091 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
7f01648a | 7092 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 7093 | .ndo_get_stats64 = ixgbe_get_stats64, |
8af3c33f | 7094 | #ifdef CONFIG_IXGBE_DCB |
24095aa3 | 7095 | .ndo_setup_tc = ixgbe_setup_tc, |
8af3c33f | 7096 | #endif |
0edc3527 SH |
7097 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7098 | .ndo_poll_controller = ixgbe_netpoll, | |
7099 | #endif | |
332d4a7d YZ |
7100 | #ifdef IXGBE_FCOE |
7101 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 7102 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 7103 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
7104 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
7105 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 7106 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 7107 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 7108 | #endif /* IXGBE_FCOE */ |
082757af DS |
7109 | .ndo_set_features = ixgbe_set_features, |
7110 | .ndo_fix_features = ixgbe_fix_features, | |
0f4b0add JF |
7111 | .ndo_fdb_add = ixgbe_ndo_fdb_add, |
7112 | .ndo_fdb_del = ixgbe_ndo_fdb_del, | |
7113 | .ndo_fdb_dump = ixgbe_ndo_fdb_dump, | |
815cccbf JF |
7114 | .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, |
7115 | .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, | |
0edc3527 SH |
7116 | }; |
7117 | ||
8e2813f5 JK |
7118 | /** |
7119 | * ixgbe_wol_supported - Check whether device supports WoL | |
7120 | * @hw: hw specific details | |
7121 | * @device_id: the device ID | |
7122 | * @subdev_id: the subsystem device ID | |
7123 | * | |
7124 | * This function is used by probe and ethtool to determine | |
7125 | * which devices have WoL support | |
7126 | * | |
7127 | **/ | |
7128 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
7129 | u16 subdevice_id) | |
7130 | { | |
7131 | struct ixgbe_hw *hw = &adapter->hw; | |
7132 | u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
7133 | int is_wol_supported = 0; | |
7134 | ||
7135 | switch (device_id) { | |
7136 | case IXGBE_DEV_ID_82599_SFP: | |
7137 | /* Only these subdevices could supports WOL */ | |
7138 | switch (subdevice_id) { | |
7139 | case IXGBE_SUBDEV_ID_82599_560FLR: | |
7140 | /* only support first port */ | |
7141 | if (hw->bus.func != 0) | |
7142 | break; | |
7143 | case IXGBE_SUBDEV_ID_82599_SFP: | |
b6dfd939 | 7144 | case IXGBE_SUBDEV_ID_82599_RNDC: |
f8a06c2c | 7145 | case IXGBE_SUBDEV_ID_82599_ECNA_DP: |
8e2813f5 JK |
7146 | is_wol_supported = 1; |
7147 | break; | |
7148 | } | |
7149 | break; | |
7150 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: | |
7151 | /* All except this subdevice support WOL */ | |
7152 | if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) | |
7153 | is_wol_supported = 1; | |
7154 | break; | |
7155 | case IXGBE_DEV_ID_82599_KX4: | |
7156 | is_wol_supported = 1; | |
7157 | break; | |
7158 | case IXGBE_DEV_ID_X540T: | |
df376f0d | 7159 | case IXGBE_DEV_ID_X540T1: |
8e2813f5 JK |
7160 | /* check eeprom to see if enabled wol */ |
7161 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
7162 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
7163 | (hw->bus.func == 0))) { | |
7164 | is_wol_supported = 1; | |
7165 | } | |
7166 | break; | |
7167 | } | |
7168 | ||
7169 | return is_wol_supported; | |
7170 | } | |
7171 | ||
9a799d71 AK |
7172 | /** |
7173 | * ixgbe_probe - Device Initialization Routine | |
7174 | * @pdev: PCI device information struct | |
7175 | * @ent: entry in ixgbe_pci_tbl | |
7176 | * | |
7177 | * Returns 0 on success, negative on failure | |
7178 | * | |
7179 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
7180 | * The OS initialization, configuring of the adapter private structure, | |
7181 | * and a hardware reset occur. | |
7182 | **/ | |
7183 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 7184 | const struct pci_device_id *ent) |
9a799d71 AK |
7185 | { |
7186 | struct net_device *netdev; | |
7187 | struct ixgbe_adapter *adapter = NULL; | |
7188 | struct ixgbe_hw *hw; | |
7189 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
7190 | static int cards_found; |
7191 | int i, err, pci_using_dac; | |
289700db | 7192 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 7193 | unsigned int indices = num_possible_cpus(); |
3f4a6f00 | 7194 | unsigned int dcb_max = 0; |
eacd73f7 YZ |
7195 | #ifdef IXGBE_FCOE |
7196 | u16 device_caps; | |
7197 | #endif | |
289700db | 7198 | u32 eec; |
9a799d71 | 7199 | |
bded64a7 AG |
7200 | /* Catch broken hardware that put the wrong VF device ID in |
7201 | * the PCIe SR-IOV capability. | |
7202 | */ | |
7203 | if (pdev->is_virtfn) { | |
7204 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
7205 | pci_name(pdev), pdev->vendor, pdev->device); | |
7206 | return -EINVAL; | |
7207 | } | |
7208 | ||
9ce77666 | 7209 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
7210 | if (err) |
7211 | return err; | |
7212 | ||
1b507730 NN |
7213 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
7214 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
7215 | pci_using_dac = 1; |
7216 | } else { | |
1b507730 | 7217 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 7218 | if (err) { |
1b507730 NN |
7219 | err = dma_set_coherent_mask(&pdev->dev, |
7220 | DMA_BIT_MASK(32)); | |
9a799d71 | 7221 | if (err) { |
b8bc0421 DC |
7222 | dev_err(&pdev->dev, |
7223 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
7224 | goto err_dma; |
7225 | } | |
7226 | } | |
7227 | pci_using_dac = 0; | |
7228 | } | |
7229 | ||
9ce77666 | 7230 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7231 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 7232 | if (err) { |
b8bc0421 DC |
7233 | dev_err(&pdev->dev, |
7234 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
7235 | goto err_pci_reg; |
7236 | } | |
7237 | ||
19d5afd4 | 7238 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 7239 | |
9a799d71 | 7240 | pci_set_master(pdev); |
fb3b27bc | 7241 | pci_save_state(pdev); |
9a799d71 | 7242 | |
e901acd6 | 7243 | #ifdef CONFIG_IXGBE_DCB |
3f4a6f00 JF |
7244 | if (ii->mac == ixgbe_mac_82598EB) |
7245 | dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS, | |
7246 | IXGBE_MAX_RSS_INDICES); | |
7247 | else | |
7248 | dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS, | |
7249 | IXGBE_MAX_FDIR_INDICES); | |
e901acd6 JF |
7250 | #endif |
7251 | ||
c85a2618 JF |
7252 | if (ii->mac == ixgbe_mac_82598EB) |
7253 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
7254 | else | |
7255 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
7256 | ||
e901acd6 | 7257 | #ifdef IXGBE_FCOE |
c85a2618 JF |
7258 | indices += min_t(unsigned int, num_possible_cpus(), |
7259 | IXGBE_MAX_FCOE_INDICES); | |
7260 | #endif | |
3f4a6f00 | 7261 | indices = max_t(unsigned int, dcb_max, indices); |
c85a2618 | 7262 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
7263 | if (!netdev) { |
7264 | err = -ENOMEM; | |
7265 | goto err_alloc_etherdev; | |
7266 | } | |
7267 | ||
9a799d71 AK |
7268 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7269 | ||
9a799d71 | 7270 | adapter = netdev_priv(netdev); |
c60fbb00 | 7271 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
7272 | |
7273 | adapter->netdev = netdev; | |
7274 | adapter->pdev = pdev; | |
7275 | hw = &adapter->hw; | |
7276 | hw->back = adapter; | |
b3f4d599 | 7277 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9a799d71 | 7278 | |
05857980 | 7279 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 7280 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
7281 | if (!hw->hw_addr) { |
7282 | err = -EIO; | |
7283 | goto err_ioremap; | |
7284 | } | |
7285 | ||
0edc3527 | 7286 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 7287 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 7288 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 7289 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 7290 | |
9a799d71 AK |
7291 | adapter->bd_number = cards_found; |
7292 | ||
9a799d71 AK |
7293 | /* Setup hw api */ |
7294 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 7295 | hw->mac.type = ii->mac; |
9a799d71 | 7296 | |
c44ade9e JB |
7297 | /* EEPROM */ |
7298 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
7299 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
7300 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
7301 | if (!(eec & (1 << 8))) | |
7302 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
7303 | ||
7304 | /* PHY */ | |
7305 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 7306 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
7307 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
7308 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
7309 | hw->phy.mdio.mmds = 0; | |
7310 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
7311 | hw->phy.mdio.dev = netdev; | |
7312 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
7313 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 7314 | |
8ca783ab | 7315 | ii->get_invariants(hw); |
9a799d71 AK |
7316 | |
7317 | /* setup the private structure */ | |
7318 | err = ixgbe_sw_init(adapter); | |
7319 | if (err) | |
7320 | goto err_sw_init; | |
7321 | ||
e86bff0e | 7322 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7323 | switch (adapter->hw.mac.type) { |
7324 | case ixgbe_mac_82599EB: | |
7325 | case ixgbe_mac_X540: | |
e86bff0e | 7326 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7327 | break; |
7328 | default: | |
7329 | break; | |
7330 | } | |
e86bff0e | 7331 | |
bf069c97 DS |
7332 | /* |
7333 | * If there is a fan on this device and it has failed log the | |
7334 | * failure. | |
7335 | */ | |
7336 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7337 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7338 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7339 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7340 | } |
7341 | ||
8ef78adc PWJ |
7342 | if (allow_unsupported_sfp) |
7343 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
7344 | ||
c44ade9e | 7345 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7346 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7347 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7348 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7349 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7350 | hw->mac.type == ixgbe_mac_82598EB) { | |
8ca783ab DS |
7351 | err = 0; |
7352 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
7086400d | 7353 | e_dev_err("failed to load because an unsupported SFP+ " |
849c4542 ET |
7354 | "module type was detected.\n"); |
7355 | e_dev_err("Reload the driver after installing a supported " | |
7356 | "module.\n"); | |
04f165ef PW |
7357 | goto err_sw_init; |
7358 | } else if (err) { | |
849c4542 | 7359 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7360 | goto err_sw_init; |
7361 | } | |
7362 | ||
99d74487 AD |
7363 | #ifdef CONFIG_PCI_IOV |
7364 | ixgbe_enable_sriov(adapter, ii); | |
1cdd1ec8 | 7365 | |
99d74487 | 7366 | #endif |
396e799c | 7367 | netdev->features = NETIF_F_SG | |
e8e9f696 | 7368 | NETIF_F_IP_CSUM | |
082757af | 7369 | NETIF_F_IPV6_CSUM | |
e8e9f696 JP |
7370 | NETIF_F_HW_VLAN_TX | |
7371 | NETIF_F_HW_VLAN_RX | | |
082757af DS |
7372 | NETIF_F_HW_VLAN_FILTER | |
7373 | NETIF_F_TSO | | |
7374 | NETIF_F_TSO6 | | |
082757af DS |
7375 | NETIF_F_RXHASH | |
7376 | NETIF_F_RXCSUM; | |
9a799d71 | 7377 | |
082757af | 7378 | netdev->hw_features = netdev->features; |
ad31c402 | 7379 | |
58be7666 DS |
7380 | switch (adapter->hw.mac.type) { |
7381 | case ixgbe_mac_82599EB: | |
7382 | case ixgbe_mac_X540: | |
45a5ead0 | 7383 | netdev->features |= NETIF_F_SCTP_CSUM; |
082757af DS |
7384 | netdev->hw_features |= NETIF_F_SCTP_CSUM | |
7385 | NETIF_F_NTUPLE; | |
58be7666 DS |
7386 | break; |
7387 | default: | |
7388 | break; | |
7389 | } | |
45a5ead0 | 7390 | |
3f2d1c0f BG |
7391 | netdev->hw_features |= NETIF_F_RXALL; |
7392 | ||
ad31c402 JK |
7393 | netdev->vlan_features |= NETIF_F_TSO; |
7394 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7395 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7396 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7397 | netdev->vlan_features |= NETIF_F_SG; |
7398 | ||
01789349 | 7399 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 7400 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 7401 | |
7a6b6f51 | 7402 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7403 | netdev->dcbnl_ops = &dcbnl_ops; |
7404 | #endif | |
7405 | ||
eacd73f7 | 7406 | #ifdef IXGBE_FCOE |
0d551589 | 7407 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7408 | if (hw->mac.ops.get_device_caps) { |
7409 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7410 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7411 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 | 7412 | } |
7c8ae65a AD |
7413 | |
7414 | adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE; | |
7415 | ||
a58915c7 AD |
7416 | netdev->features |= NETIF_F_FSO | |
7417 | NETIF_F_FCOE_CRC; | |
7418 | ||
7c8ae65a AD |
7419 | netdev->vlan_features |= NETIF_F_FSO | |
7420 | NETIF_F_FCOE_CRC | | |
7421 | NETIF_F_FCOE_MTU; | |
5e09d7f6 | 7422 | } |
eacd73f7 | 7423 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7424 | if (pci_using_dac) { |
9a799d71 | 7425 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7426 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7427 | } | |
9a799d71 | 7428 | |
082757af DS |
7429 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
7430 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 7431 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7432 | netdev->features |= NETIF_F_LRO; |
7433 | ||
9a799d71 | 7434 | /* make sure the EEPROM is good */ |
c44ade9e | 7435 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7436 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 | 7437 | err = -EIO; |
35937c05 | 7438 | goto err_sw_init; |
9a799d71 AK |
7439 | } |
7440 | ||
7441 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7442 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7443 | ||
c44ade9e | 7444 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7445 | e_dev_err("invalid MAC address\n"); |
9a799d71 | 7446 | err = -EIO; |
35937c05 | 7447 | goto err_sw_init; |
9a799d71 AK |
7448 | } |
7449 | ||
7086400d | 7450 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
581330ba | 7451 | (unsigned long) adapter); |
9a799d71 | 7452 | |
7086400d AD |
7453 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
7454 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
9a799d71 | 7455 | |
021230d4 AV |
7456 | err = ixgbe_init_interrupt_scheme(adapter); |
7457 | if (err) | |
7458 | goto err_sw_init; | |
9a799d71 | 7459 | |
8e2813f5 | 7460 | /* WOL not supported for all devices */ |
c23f5b6b | 7461 | adapter->wol = 0; |
8e2813f5 JK |
7462 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); |
7463 | if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device)) | |
9417c464 | 7464 | adapter->wol = IXGBE_WUFC_MAG; |
c23f5b6b | 7465 | |
e8e26350 PW |
7466 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7467 | ||
15e5209f ET |
7468 | /* save off EEPROM version number */ |
7469 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
7470 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
7471 | ||
04f165ef PW |
7472 | /* pick up the PCI bus settings for reporting later */ |
7473 | hw->mac.ops.get_bus_info(hw); | |
7474 | ||
9a799d71 | 7475 | /* print bus type/speed/width info */ |
849c4542 | 7476 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
6716344c DS |
7477 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : |
7478 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : | |
e8e9f696 JP |
7479 | "Unknown"), |
7480 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7481 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7482 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7483 | "Unknown"), | |
7484 | netdev->dev_addr); | |
289700db DS |
7485 | |
7486 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7487 | if (err) | |
9fe93afd | 7488 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7489 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7490 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7491 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7492 | part_str); |
e8e26350 | 7493 | else |
289700db DS |
7494 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7495 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7496 | |
e8e26350 | 7497 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7498 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7499 | "not sufficient for optimal performance.\n"); | |
7500 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7501 | "is required.\n"); | |
0c254d86 AK |
7502 | } |
7503 | ||
9a799d71 | 7504 | /* reset the hardware with the new settings */ |
794caeb2 | 7505 | err = hw->mac.ops.start_hw(hw); |
794caeb2 PWJ |
7506 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7507 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7508 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7509 | "Please be aware there may be issues associated " | |
7510 | "with your hardware. If you are experiencing " | |
7511 | "problems please contact your Intel or hardware " | |
7512 | "representative who provided you with this " | |
7513 | "hardware.\n"); | |
794caeb2 | 7514 | } |
9a799d71 AK |
7515 | strcpy(netdev->name, "eth%d"); |
7516 | err = register_netdev(netdev); | |
7517 | if (err) | |
7518 | goto err_register; | |
7519 | ||
ec74a471 ET |
7520 | /* power down the optics for 82599 SFP+ fiber */ |
7521 | if (hw->mac.ops.disable_tx_laser) | |
93d3ce8f ET |
7522 | hw->mac.ops.disable_tx_laser(hw); |
7523 | ||
54386467 JB |
7524 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7525 | netif_carrier_off(netdev); | |
7526 | ||
5dd2d332 | 7527 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7528 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7529 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7530 | ixgbe_setup_dca(adapter); |
7531 | } | |
7532 | #endif | |
1cdd1ec8 | 7533 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7534 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7535 | for (i = 0; i < adapter->num_vfs; i++) |
7536 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7537 | } | |
7538 | ||
2466dd9c JK |
7539 | /* firmware requires driver version to be 0xFFFFFFFF |
7540 | * since os does not support feature | |
7541 | */ | |
9612de92 | 7542 | if (hw->mac.ops.set_fw_drv_ver) |
2466dd9c JK |
7543 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, |
7544 | 0xFF); | |
9612de92 | 7545 | |
0365e6e4 PW |
7546 | /* add san mac addr to netdev */ |
7547 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7548 | |
ea81875a | 7549 | e_dev_info("%s\n", ixgbe_default_device_descr); |
9a799d71 | 7550 | cards_found++; |
3ca8bc6d | 7551 | |
1210982b | 7552 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d DS |
7553 | if (ixgbe_sysfs_init(adapter)) |
7554 | e_err(probe, "failed to allocate sysfs resources\n"); | |
1210982b | 7555 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 7556 | |
00949167 CS |
7557 | #ifdef CONFIG_DEBUG_FS |
7558 | ixgbe_dbg_adapter_init(adapter); | |
7559 | #endif /* CONFIG_DEBUG_FS */ | |
7560 | ||
9a799d71 AK |
7561 | return 0; |
7562 | ||
7563 | err_register: | |
5eba3699 | 7564 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7565 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 | 7566 | err_sw_init: |
99d74487 | 7567 | ixgbe_disable_sriov(adapter); |
7086400d | 7568 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
9a799d71 AK |
7569 | iounmap(hw->hw_addr); |
7570 | err_ioremap: | |
7571 | free_netdev(netdev); | |
7572 | err_alloc_etherdev: | |
e8e9f696 JP |
7573 | pci_release_selected_regions(pdev, |
7574 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7575 | err_pci_reg: |
7576 | err_dma: | |
7577 | pci_disable_device(pdev); | |
7578 | return err; | |
7579 | } | |
7580 | ||
7581 | /** | |
7582 | * ixgbe_remove - Device Removal Routine | |
7583 | * @pdev: PCI device information struct | |
7584 | * | |
7585 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7586 | * that it should release a PCI device. The could be caused by a | |
7587 | * Hot-Plug event, or because the driver is going to be removed from | |
7588 | * memory. | |
7589 | **/ | |
7590 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7591 | { | |
c60fbb00 AD |
7592 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7593 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7594 | |
00949167 CS |
7595 | #ifdef CONFIG_DEBUG_FS |
7596 | ixgbe_dbg_adapter_exit(adapter); | |
7597 | #endif /*CONFIG_DEBUG_FS */ | |
7598 | ||
9a799d71 | 7599 | set_bit(__IXGBE_DOWN, &adapter->state); |
7086400d | 7600 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 7601 | |
3a6a4eda | 7602 | |
5dd2d332 | 7603 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7604 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7605 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7606 | dca_remove_requester(&pdev->dev); | |
7607 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7608 | } | |
7609 | ||
7610 | #endif | |
1210982b | 7611 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d | 7612 | ixgbe_sysfs_exit(adapter); |
1210982b | 7613 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 7614 | |
0365e6e4 PW |
7615 | /* remove the added san mac */ |
7616 | ixgbe_del_sanmac_netdev(netdev); | |
7617 | ||
c4900be0 DS |
7618 | if (netdev->reg_state == NETREG_REGISTERED) |
7619 | unregister_netdev(netdev); | |
9a799d71 | 7620 | |
9297127b | 7621 | ixgbe_disable_sriov(adapter); |
1cdd1ec8 | 7622 | |
7a921c93 | 7623 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7624 | |
021230d4 | 7625 | ixgbe_release_hw_control(adapter); |
9a799d71 | 7626 | |
2b1588c3 AD |
7627 | #ifdef CONFIG_DCB |
7628 | kfree(adapter->ixgbe_ieee_pfc); | |
7629 | kfree(adapter->ixgbe_ieee_ets); | |
7630 | ||
7631 | #endif | |
9a799d71 | 7632 | iounmap(adapter->hw.hw_addr); |
9ce77666 | 7633 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7634 | IORESOURCE_MEM)); |
9a799d71 | 7635 | |
849c4542 | 7636 | e_dev_info("complete\n"); |
021230d4 | 7637 | |
9a799d71 AK |
7638 | free_netdev(netdev); |
7639 | ||
19d5afd4 | 7640 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7641 | |
9a799d71 AK |
7642 | pci_disable_device(pdev); |
7643 | } | |
7644 | ||
7645 | /** | |
7646 | * ixgbe_io_error_detected - called when PCI error is detected | |
7647 | * @pdev: Pointer to PCI device | |
7648 | * @state: The current pci connection state | |
7649 | * | |
7650 | * This function is called after a PCI bus error affecting | |
7651 | * this device has been detected. | |
7652 | */ | |
7653 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7654 | pci_channel_state_t state) |
9a799d71 | 7655 | { |
c60fbb00 AD |
7656 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7657 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7658 | |
83c61fa9 GR |
7659 | #ifdef CONFIG_PCI_IOV |
7660 | struct pci_dev *bdev, *vfdev; | |
7661 | u32 dw0, dw1, dw2, dw3; | |
7662 | int vf, pos; | |
7663 | u16 req_id, pf_func; | |
7664 | ||
7665 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
7666 | adapter->num_vfs == 0) | |
7667 | goto skip_bad_vf_detection; | |
7668 | ||
7669 | bdev = pdev->bus->self; | |
62f87c0e | 7670 | while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) |
83c61fa9 GR |
7671 | bdev = bdev->bus->self; |
7672 | ||
7673 | if (!bdev) | |
7674 | goto skip_bad_vf_detection; | |
7675 | ||
7676 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
7677 | if (!pos) | |
7678 | goto skip_bad_vf_detection; | |
7679 | ||
7680 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0); | |
7681 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1); | |
7682 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2); | |
7683 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3); | |
7684 | ||
7685 | req_id = dw1 >> 16; | |
7686 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
7687 | if (!(req_id & 0x0080)) | |
7688 | goto skip_bad_vf_detection; | |
7689 | ||
7690 | pf_func = req_id & 0x01; | |
7691 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
7692 | unsigned int device_id; | |
7693 | ||
7694 | vf = (req_id & 0x7F) >> 1; | |
7695 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
7696 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
7697 | "%8.8x\tdw3: %8.8x\n", | |
7698 | dw0, dw1, dw2, dw3); | |
7699 | switch (adapter->hw.mac.type) { | |
7700 | case ixgbe_mac_82599EB: | |
7701 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
7702 | break; | |
7703 | case ixgbe_mac_X540: | |
7704 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
7705 | break; | |
7706 | default: | |
7707 | device_id = 0; | |
7708 | break; | |
7709 | } | |
7710 | ||
7711 | /* Find the pci device of the offending VF */ | |
36e90319 | 7712 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); |
83c61fa9 GR |
7713 | while (vfdev) { |
7714 | if (vfdev->devfn == (req_id & 0xFF)) | |
7715 | break; | |
36e90319 | 7716 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
83c61fa9 GR |
7717 | device_id, vfdev); |
7718 | } | |
7719 | /* | |
7720 | * There's a slim chance the VF could have been hot plugged, | |
7721 | * so if it is no longer present we don't need to issue the | |
7722 | * VFLR. Just clean up the AER in that case. | |
7723 | */ | |
7724 | if (vfdev) { | |
7725 | e_dev_err("Issuing VFLR to VF %d\n", vf); | |
7726 | pci_write_config_dword(vfdev, 0xA8, 0x00008000); | |
7727 | } | |
7728 | ||
7729 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
7730 | } | |
7731 | ||
7732 | /* | |
7733 | * Even though the error may have occurred on the other port | |
7734 | * we still need to increment the vf error reference count for | |
7735 | * both ports because the I/O resume function will be called | |
7736 | * for both of them. | |
7737 | */ | |
7738 | adapter->vferr_refcount++; | |
7739 | ||
7740 | return PCI_ERS_RESULT_RECOVERED; | |
7741 | ||
7742 | skip_bad_vf_detection: | |
7743 | #endif /* CONFIG_PCI_IOV */ | |
9a799d71 AK |
7744 | netif_device_detach(netdev); |
7745 | ||
3044b8d1 BL |
7746 | if (state == pci_channel_io_perm_failure) |
7747 | return PCI_ERS_RESULT_DISCONNECT; | |
7748 | ||
9a799d71 AK |
7749 | if (netif_running(netdev)) |
7750 | ixgbe_down(adapter); | |
7751 | pci_disable_device(pdev); | |
7752 | ||
b4617240 | 7753 | /* Request a slot reset. */ |
9a799d71 AK |
7754 | return PCI_ERS_RESULT_NEED_RESET; |
7755 | } | |
7756 | ||
7757 | /** | |
7758 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7759 | * @pdev: Pointer to PCI device | |
7760 | * | |
7761 | * Restart the card from scratch, as if from a cold-boot. | |
7762 | */ | |
7763 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7764 | { | |
c60fbb00 | 7765 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
7766 | pci_ers_result_t result; |
7767 | int err; | |
9a799d71 | 7768 | |
9ce77666 | 7769 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7770 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7771 | result = PCI_ERS_RESULT_DISCONNECT; |
7772 | } else { | |
7773 | pci_set_master(pdev); | |
7774 | pci_restore_state(pdev); | |
c0e1f68b | 7775 | pci_save_state(pdev); |
9a799d71 | 7776 | |
dd4d8ca6 | 7777 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7778 | |
6fabd715 | 7779 | ixgbe_reset(adapter); |
88512539 | 7780 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7781 | result = PCI_ERS_RESULT_RECOVERED; |
7782 | } | |
7783 | ||
7784 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7785 | if (err) { | |
849c4542 ET |
7786 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7787 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7788 | /* non-fatal, continue */ |
7789 | } | |
9a799d71 | 7790 | |
6fabd715 | 7791 | return result; |
9a799d71 AK |
7792 | } |
7793 | ||
7794 | /** | |
7795 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7796 | * @pdev: Pointer to PCI device | |
7797 | * | |
7798 | * This callback is called when the error recovery driver tells us that | |
7799 | * its OK to resume normal operation. | |
7800 | */ | |
7801 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7802 | { | |
c60fbb00 AD |
7803 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7804 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7805 | |
83c61fa9 GR |
7806 | #ifdef CONFIG_PCI_IOV |
7807 | if (adapter->vferr_refcount) { | |
7808 | e_info(drv, "Resuming after VF err\n"); | |
7809 | adapter->vferr_refcount--; | |
7810 | return; | |
7811 | } | |
7812 | ||
7813 | #endif | |
c7ccde0f AD |
7814 | if (netif_running(netdev)) |
7815 | ixgbe_up(adapter); | |
9a799d71 AK |
7816 | |
7817 | netif_device_attach(netdev); | |
9a799d71 AK |
7818 | } |
7819 | ||
3646f0e5 | 7820 | static const struct pci_error_handlers ixgbe_err_handler = { |
9a799d71 AK |
7821 | .error_detected = ixgbe_io_error_detected, |
7822 | .slot_reset = ixgbe_io_slot_reset, | |
7823 | .resume = ixgbe_io_resume, | |
7824 | }; | |
7825 | ||
7826 | static struct pci_driver ixgbe_driver = { | |
7827 | .name = ixgbe_driver_name, | |
7828 | .id_table = ixgbe_pci_tbl, | |
7829 | .probe = ixgbe_probe, | |
7830 | .remove = __devexit_p(ixgbe_remove), | |
7831 | #ifdef CONFIG_PM | |
7832 | .suspend = ixgbe_suspend, | |
7833 | .resume = ixgbe_resume, | |
7834 | #endif | |
7835 | .shutdown = ixgbe_shutdown, | |
7836 | .err_handler = &ixgbe_err_handler | |
7837 | }; | |
7838 | ||
7839 | /** | |
7840 | * ixgbe_init_module - Driver Registration Routine | |
7841 | * | |
7842 | * ixgbe_init_module is the first routine called when the driver is | |
7843 | * loaded. All it does is register with the PCI subsystem. | |
7844 | **/ | |
7845 | static int __init ixgbe_init_module(void) | |
7846 | { | |
7847 | int ret; | |
c7689578 | 7848 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7849 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7850 | |
00949167 CS |
7851 | #ifdef CONFIG_DEBUG_FS |
7852 | ixgbe_dbg_init(); | |
7853 | #endif /* CONFIG_DEBUG_FS */ | |
7854 | ||
5dd2d332 | 7855 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7856 | dca_register_notify(&dca_notifier); |
bd0362dd | 7857 | #endif |
5dd2d332 | 7858 | |
9a799d71 AK |
7859 | ret = pci_register_driver(&ixgbe_driver); |
7860 | return ret; | |
7861 | } | |
b4617240 | 7862 | |
9a799d71 AK |
7863 | module_init(ixgbe_init_module); |
7864 | ||
7865 | /** | |
7866 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7867 | * | |
7868 | * ixgbe_exit_module is called just before the driver is removed | |
7869 | * from memory. | |
7870 | **/ | |
7871 | static void __exit ixgbe_exit_module(void) | |
7872 | { | |
5dd2d332 | 7873 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7874 | dca_unregister_notify(&dca_notifier); |
7875 | #endif | |
9a799d71 | 7876 | pci_unregister_driver(&ixgbe_driver); |
00949167 CS |
7877 | |
7878 | #ifdef CONFIG_DEBUG_FS | |
7879 | ixgbe_dbg_exit(); | |
7880 | #endif /* CONFIG_DEBUG_FS */ | |
7881 | ||
1a51502b | 7882 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7883 | } |
bd0362dd | 7884 | |
5dd2d332 | 7885 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7886 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7887 | void *p) |
bd0362dd JC |
7888 | { |
7889 | int ret_val; | |
7890 | ||
7891 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7892 | __ixgbe_notify_dca); |
bd0362dd JC |
7893 | |
7894 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7895 | } | |
b453368d | 7896 | |
5dd2d332 | 7897 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7898 | |
9a799d71 AK |
7899 | module_exit(ixgbe_exit_module); |
7900 | ||
7901 | /* ixgbe_main.c */ |