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Merge tag 'pci-v4.2-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
9a799d71 54
c762dff2
MP		 55#ifdef CONFIG_OF
56#include <linux/of_net.h>
57#endif
58
59#ifdef CONFIG_SPARC
60#include <asm/idprom.h>
61#include <asm/prom.h>
62#endif
63
9a799d71
AK		 64#include "ixgbe.h"
65#include "ixgbe_common.h"
ee5f784a 66#include "ixgbe_dcb_82599.h"
1cdd1ec8 67#include "ixgbe_sriov.h"
9a799d71
AK		 68
69char ixgbe_driver_name[] = "ixgbe";
9c8eb720 70static const char ixgbe_driver_string[] =
e8e9f696 71 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 72#ifdef IXGBE_FCOE
ea81875a
NP		 73char ixgbe_default_device_descr[] =
74 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 75#else
76static char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78#endif
9be4a9bb 79#define DRV_VERSION "4.0.1-k"
9c8eb720 80const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 81static const char ixgbe_copyright[] =
0391bbe3 82 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71 83
f44e751b
DS		 84static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
85
9a799d71 86static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 87 [board_82598] = &ixgbe_82598_info,
88 [board_82599] = &ixgbe_82599_info,
89 [board_X540] = &ixgbe_X540_info,
90 [board_X550] = &ixgbe_X550_info,
91 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 92};
93
94/* ixgbe_pci_tbl - PCI Device ID Table
95 *
96 * Wildcard entries (PCI_ANY_ID) should come last
97 * Last entry must be all 0s
98 *
99 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
100 * Class, Class Mask, private data (not used) }
101 */
9baa3c34 102static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
9a799d71
AK		 137 /* required last entry */
138 {0, }
139};
140MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
141
5dd2d332 142#ifdef CONFIG_IXGBE_DCA
bd0362dd 143static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 144 void *p);
bd0362dd
JC		 145static struct notifier_block dca_notifier = {
146 .notifier_call = ixgbe_notify_dca,
147 .next = NULL,
148 .priority = 0
149};
150#endif
151
1cdd1ec8
GR		 152#ifdef CONFIG_PCI_IOV
153static unsigned int max_vfs;
154module_param(max_vfs, uint, 0);
e8e9f696 155MODULE_PARM_DESC(max_vfs,
170e8543 156 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 157#endif /* CONFIG_PCI_IOV */
158
8ef78adc
PWJ		 159static unsigned int allow_unsupported_sfp;
160module_param(allow_unsupported_sfp, uint, 0);
161MODULE_PARM_DESC(allow_unsupported_sfp,
162 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
163
b3f4d599 164#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
165static int debug = -1;
166module_param(debug, int, 0);
167MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
168
9a799d71
AK		 169MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
170MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
171MODULE_LICENSE("GPL");
172MODULE_VERSION(DRV_VERSION);
173
14438464
MR		 174static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
175
b8e82001
JK		 176static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
177 u32 reg, u16 *value)
178{
b8e82001
JK		 179 struct pci_dev *parent_dev;
180 struct pci_bus *parent_bus;
181
182 parent_bus = adapter->pdev->bus->parent;
183 if (!parent_bus)
184 return -1;
185
186 parent_dev = parent_bus->self;
187 if (!parent_dev)
188 return -1;
189
c0798edf 190 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 191 return -1;
192
c0798edf 193 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 194 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
195 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
196 return -1;
b8e82001
JK		 197 return 0;
198}
199
200static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
201{
202 struct ixgbe_hw *hw = &adapter->hw;
203 u16 link_status = 0;
204 int err;
205
206 hw->bus.type = ixgbe_bus_type_pci_express;
207
208 /* Get the negotiated link width and speed from PCI config space of the
209 * parent, as this device is behind a switch
210 */
211 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
212
213 /* assume caller will handle error case */
214 if (err)
215 return err;
216
217 hw->bus.width = ixgbe_convert_bus_width(link_status);
218 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
219
220 return 0;
221}
222
e027d1ae
JK		 223/**
224 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
225 * @hw: hw specific details
226 *
227 * This function is used by probe to determine whether a device's PCI-Express
228 * bandwidth details should be gathered from the parent bus instead of from the
229 * device. Used to ensure that various locations all have the correct device ID
230 * checks.
231 */
232static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
233{
234 switch (hw->device_id) {
235 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 236 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 237 return true;
238 default:
239 return false;
240 }
241}
242
243static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
244 int expected_gts)
245{
246 int max_gts = 0;
247 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
248 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
249 struct pci_dev *pdev;
250
251 /* determine whether to use the the parent device
252 */
253 if (ixgbe_pcie_from_parent(&adapter->hw))
254 pdev = adapter->pdev->bus->parent->self;
255 else
256 pdev = adapter->pdev;
257
258 if (pcie_get_minimum_link(pdev, &speed, &width) ||
259 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
260 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
261 return;
262 }
263
264 switch (speed) {
265 case PCIE_SPEED_2_5GT:
266 /* 8b/10b encoding reduces max throughput by 20% */
267 max_gts = 2 * width;
268 break;
269 case PCIE_SPEED_5_0GT:
270 /* 8b/10b encoding reduces max throughput by 20% */
271 max_gts = 4 * width;
272 break;
273 case PCIE_SPEED_8_0GT:
9f0a433c 274 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 275 max_gts = 8 * width;
276 break;
277 default:
278 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
279 return;
280 }
281
282 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
283 max_gts);
284 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
285 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
286 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
287 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
288 "Unknown"),
289 width,
290 (speed == PCIE_SPEED_2_5GT ? "20%" :
291 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 292 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 293 "Unknown"));
294
295 if (max_gts < expected_gts) {
296 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
297 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
298 expected_gts);
299 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
300 }
301}
302
7086400d
AD		 303static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
304{
305 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 306 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 307 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
308 schedule_work(&adapter->service_task);
309}
310
2a1a091c
MR		 311static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
312{
313 struct ixgbe_adapter *adapter = hw->back;
314
315 if (!hw->hw_addr)
316 return;
317 hw->hw_addr = NULL;
318 e_dev_err("Adapter removed\n");
58cf663f
MR		 319 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
320 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 321}
322
f8e2472f 323static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 324{
325 u32 value;
326
327 /* The following check not only optimizes a bit by not
328 * performing a read on the status register when the
329 * register just read was a status register read that
330 * returned IXGBE_FAILED_READ_REG. It also blocks any
331 * potential recursion.
332 */
333 if (reg == IXGBE_STATUS) {
334 ixgbe_remove_adapter(hw);
335 return;
336 }
337 value = ixgbe_read_reg(hw, IXGBE_STATUS);
338 if (value == IXGBE_FAILED_READ_REG)
339 ixgbe_remove_adapter(hw);
340}
341
f8e2472f
MR		 342/**
343 * ixgbe_read_reg - Read from device register
344 * @hw: hw specific details
345 * @reg: offset of register to read
346 *
347 * Returns : value read or IXGBE_FAILED_READ_REG if removed
348 *
349 * This function is used to read device registers. It checks for device
350 * removal by confirming any read that returns all ones by checking the
351 * status register value for all ones. This function avoids reading from
352 * the hardware if a removal was previously detected in which case it
353 * returns IXGBE_FAILED_READ_REG (all ones).
354 */
355u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
356{
357 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
358 u32 value;
359
360 if (ixgbe_removed(reg_addr))
361 return IXGBE_FAILED_READ_REG;
362 value = readl(reg_addr + reg);
363 if (unlikely(value == IXGBE_FAILED_READ_REG))
364 ixgbe_check_remove(hw, reg);
365 return value;
366}
367
14438464
MR		 368static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
369{
370 u16 value;
371
372 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
373 if (value == IXGBE_FAILED_READ_CFG_WORD) {
374 ixgbe_remove_adapter(hw);
375 return true;
376 }
377 return false;
378}
379
380u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
381{
382 struct ixgbe_adapter *adapter = hw->back;
383 u16 value;
384
385 if (ixgbe_removed(hw->hw_addr))
386 return IXGBE_FAILED_READ_CFG_WORD;
387 pci_read_config_word(adapter->pdev, reg, &value);
388 if (value == IXGBE_FAILED_READ_CFG_WORD &&
389 ixgbe_check_cfg_remove(hw, adapter->pdev))
390 return IXGBE_FAILED_READ_CFG_WORD;
391 return value;
392}
393
394#ifdef CONFIG_PCI_IOV
395static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
396{
397 struct ixgbe_adapter *adapter = hw->back;
398 u32 value;
399
400 if (ixgbe_removed(hw->hw_addr))
401 return IXGBE_FAILED_READ_CFG_DWORD;
402 pci_read_config_dword(adapter->pdev, reg, &value);
403 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
404 ixgbe_check_cfg_remove(hw, adapter->pdev))
405 return IXGBE_FAILED_READ_CFG_DWORD;
406 return value;
407}
408#endif /* CONFIG_PCI_IOV */
409
ed19231c
JK		 410void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
411{
412 struct ixgbe_adapter *adapter = hw->back;
413
414 if (ixgbe_removed(hw->hw_addr))
415 return;
416 pci_write_config_word(adapter->pdev, reg, value);
417}
418
7086400d
AD		 419static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
420{
421 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
422
52f33af8 423 /* flush memory to make sure state is correct before next watchdog */
4e857c58 424 smp_mb__before_atomic();
7086400d
AD		 425 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
426}
427
dcd79aeb
TI		 428struct ixgbe_reg_info {
429 u32 ofs;
430 char *name;
431};
432
433static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
434
435 /* General Registers */
436 {IXGBE_CTRL, "CTRL"},
437 {IXGBE_STATUS, "STATUS"},
438 {IXGBE_CTRL_EXT, "CTRL_EXT"},
439
440 /* Interrupt Registers */
441 {IXGBE_EICR, "EICR"},
442
443 /* RX Registers */
444 {IXGBE_SRRCTL(0), "SRRCTL"},
445 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
446 {IXGBE_RDLEN(0), "RDLEN"},
447 {IXGBE_RDH(0), "RDH"},
448 {IXGBE_RDT(0), "RDT"},
449 {IXGBE_RXDCTL(0), "RXDCTL"},
450 {IXGBE_RDBAL(0), "RDBAL"},
451 {IXGBE_RDBAH(0), "RDBAH"},
452
453 /* TX Registers */
454 {IXGBE_TDBAL(0), "TDBAL"},
455 {IXGBE_TDBAH(0), "TDBAH"},
456 {IXGBE_TDLEN(0), "TDLEN"},
457 {IXGBE_TDH(0), "TDH"},
458 {IXGBE_TDT(0), "TDT"},
459 {IXGBE_TXDCTL(0), "TXDCTL"},
460
461 /* List Terminator */
ca8dfe25 462 { .name = NULL }
dcd79aeb
TI		 463};
464
465
466/*
467 * ixgbe_regdump - register printout routine
468 */
469static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
470{
471 int i = 0, j = 0;
472 char rname[16];
473 u32 regs[64];
474
475 switch (reginfo->ofs) {
476 case IXGBE_SRRCTL(0):
477 for (i = 0; i < 64; i++)
478 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
479 break;
480 case IXGBE_DCA_RXCTRL(0):
481 for (i = 0; i < 64; i++)
482 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
483 break;
484 case IXGBE_RDLEN(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
487 break;
488 case IXGBE_RDH(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
491 break;
492 case IXGBE_RDT(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
495 break;
496 case IXGBE_RXDCTL(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
499 break;
500 case IXGBE_RDBAL(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
503 break;
504 case IXGBE_RDBAH(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
507 break;
508 case IXGBE_TDBAL(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
511 break;
512 case IXGBE_TDBAH(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
515 break;
516 case IXGBE_TDLEN(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
519 break;
520 case IXGBE_TDH(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
523 break;
524 case IXGBE_TDT(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
527 break;
528 case IXGBE_TXDCTL(0):
529 for (i = 0; i < 64; i++)
530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
531 break;
532 default:
c7689578 533 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 534 IXGBE_READ_REG(hw, reginfo->ofs));
535 return;
536 }
537
538 for (i = 0; i < 8; i++) {
539 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 540 pr_err("%-15s", rname);
dcd79aeb 541 for (j = 0; j < 8; j++)
c7689578
JP		 542 pr_cont(" %08x", regs[i*8+j]);
543 pr_cont("\n");
dcd79aeb
TI		 544 }
545
546}
547
548/*
549 * ixgbe_dump - Print registers, tx-rings and rx-rings
550 */
551static void ixgbe_dump(struct ixgbe_adapter *adapter)
552{
553 struct net_device *netdev = adapter->netdev;
554 struct ixgbe_hw *hw = &adapter->hw;
555 struct ixgbe_reg_info *reginfo;
556 int n = 0;
557 struct ixgbe_ring *tx_ring;
729739b7 558 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 559 union ixgbe_adv_tx_desc *tx_desc;
560 struct my_u0 { u64 a; u64 b; } *u0;
561 struct ixgbe_ring *rx_ring;
562 union ixgbe_adv_rx_desc *rx_desc;
563 struct ixgbe_rx_buffer *rx_buffer_info;
564 u32 staterr;
565 int i = 0;
566
567 if (!netif_msg_hw(adapter))
568 return;
569
570 /* Print netdevice Info */
571 if (netdev) {
572 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 573 pr_info("Device Name state "
dcd79aeb 574 "trans_start last_rx\n");
c7689578
JP		 575 pr_info("%-15s %016lX %016lX %016lX\n",
576 netdev->name,
577 netdev->state,
578 netdev->trans_start,
579 netdev->last_rx);
dcd79aeb
TI		 580 }
581
582 /* Print Registers */
583 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 584 pr_info(" Register Name Value\n");
dcd79aeb
TI		 585 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
586 reginfo->name; reginfo++) {
587 ixgbe_regdump(hw, reginfo);
588 }
589
590 /* Print TX Ring Summary */
591 if (!netdev || !netif_running(netdev))
e90dd264 592 return;
dcd79aeb
TI		 593
594 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 595 pr_info(" %s %s %s %s\n",
596 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
597 "leng", "ntw", "timestamp");
dcd79aeb
TI		 598 for (n = 0; n < adapter->num_tx_queues; n++) {
599 tx_ring = adapter->tx_ring[n];
729739b7 600 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 601 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 602 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 603 (u64)dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 tx_buffer->next_to_watch,
606 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 607 }
608
609 /* Print TX Rings */
610 if (!netif_msg_tx_done(adapter))
611 goto rx_ring_summary;
612
613 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
614
615 /* Transmit Descriptor Formats
616 *
39ac868a 617 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 618 * +--------------------------------------------------------------+
619 * 0 | Buffer Address [63:0] |
620 * +--------------------------------------------------------------+
39ac868a 621 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 622 * +--------------------------------------------------------------+
623 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 624 *
625 * 82598 Advanced Transmit Descriptor (Write-Back Format)
626 * +--------------------------------------------------------------+
627 * 0 | RSV [63:0] |
628 * +--------------------------------------------------------------+
629 * 8 | RSV | STA | NXTSEQ |
630 * +--------------------------------------------------------------+
631 * 63 36 35 32 31 0
632 *
633 * 82599+ Advanced Transmit Descriptor
634 * +--------------------------------------------------------------+
635 * 0 | Buffer Address [63:0] |
636 * +--------------------------------------------------------------+
637 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
638 * +--------------------------------------------------------------+
639 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
640 *
641 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
642 * +--------------------------------------------------------------+
643 * 0 | RSV [63:0] |
644 * +--------------------------------------------------------------+
645 * 8 | RSV | STA | RSV |
646 * +--------------------------------------------------------------+
647 * 63 36 35 32 31 0
dcd79aeb
TI		 648 */
649
650 for (n = 0; n < adapter->num_tx_queues; n++) {
651 tx_ring = adapter->tx_ring[n];
c7689578
JP		 652 pr_info("------------------------------------\n");
653 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
654 pr_info("------------------------------------\n");
8ad88e37
JH		 655 pr_info("%s%s %s %s %s %s\n",
656 "T [desc] [address 63:0 ] ",
657 "[PlPOIdStDDt Ln] [bi->dma ] ",
658 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 659
660 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 661 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 662 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 663 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 664 if (dma_unmap_len(tx_buffer, len) > 0) {
665 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
666 i,
667 le64_to_cpu(u0->a),
668 le64_to_cpu(u0->b),
669 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 670 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 671 tx_buffer->next_to_watch,
672 (u64)tx_buffer->time_stamp,
673 tx_buffer->skb);
674 if (i == tx_ring->next_to_use &&
675 i == tx_ring->next_to_clean)
676 pr_cont(" NTC/U\n");
677 else if (i == tx_ring->next_to_use)
678 pr_cont(" NTU\n");
679 else if (i == tx_ring->next_to_clean)
680 pr_cont(" NTC\n");
681 else
682 pr_cont("\n");
683
684 if (netif_msg_pktdata(adapter) &&
685 tx_buffer->skb)
686 print_hex_dump(KERN_INFO, "",
687 DUMP_PREFIX_ADDRESS, 16, 1,
688 tx_buffer->skb->data,
689 dma_unmap_len(tx_buffer, len),
690 true);
691 }
dcd79aeb
TI		 692 }
693 }
694
695 /* Print RX Rings Summary */
696rx_ring_summary:
697 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 698 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 699 for (n = 0; n < adapter->num_rx_queues; n++) {
700 rx_ring = adapter->rx_ring[n];
c7689578
JP		 701 pr_info("%5d %5X %5X\n",
702 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 703 }
704
705 /* Print RX Rings */
706 if (!netif_msg_rx_status(adapter))
e90dd264 707 return;
dcd79aeb
TI		 708
709 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
710
39ac868a
JH		 711 /* Receive Descriptor Formats
712 *
713 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 714 * 63 1 0
715 * +-----------------------------------------------------+
716 * 0 | Packet Buffer Address [63:1] |A0/NSE|
717 * +----------------------------------------------+------+
718 * 8 | Header Buffer Address [63:1] | DD |
719 * +-----------------------------------------------------+
720 *
721 *
39ac868a 722 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 723 *
724 * 63 48 47 32 31 30 21 20 16 15 4 3 0
725 * +------------------------------------------------------+
39ac868a
JH		 726 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
727 * | Packet | IP | | | | Type | Type |
728 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 729 * +------------------------------------------------------+
730 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
731 * +------------------------------------------------------+
732 * 63 48 47 32 31 20 19 0
39ac868a
JH		 733 *
734 * 82599+ Advanced Receive Descriptor (Read) Format
735 * 63 1 0
736 * +-----------------------------------------------------+
737 * 0 | Packet Buffer Address [63:1] |A0/NSE|
738 * +----------------------------------------------+------+
739 * 8 | Header Buffer Address [63:1] | DD |
740 * +-----------------------------------------------------+
741 *
742 *
743 * 82599+ Advanced Receive Descriptor (Write-Back) Format
744 *
745 * 63 48 47 32 31 30 21 20 17 16 4 3 0
746 * +------------------------------------------------------+
747 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
748 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
749 * |/ Flow Dir Flt ID | | | | | |
750 * +------------------------------------------------------+
751 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
752 * +------------------------------------------------------+
753 * 63 48 47 32 31 20 19 0
dcd79aeb 754 */
39ac868a 755
dcd79aeb
TI		 756 for (n = 0; n < adapter->num_rx_queues; n++) {
757 rx_ring = adapter->rx_ring[n];
c7689578
JP		 758 pr_info("------------------------------------\n");
759 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
760 pr_info("------------------------------------\n");
8ad88e37
JH		 761 pr_info("%s%s%s",
762 "R [desc] [ PktBuf A0] ",
763 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 764 "<-- Adv Rx Read format\n");
8ad88e37
JH		 765 pr_info("%s%s%s",
766 "RWB[desc] [PcsmIpSHl PtRs] ",
767 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 768 "<-- Adv Rx Write-Back format\n");
769
770 for (i = 0; i < rx_ring->count; i++) {
771 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 772 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 773 u0 = (struct my_u0 *)rx_desc;
774 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
775 if (staterr & IXGBE_RXD_STAT_DD) {
776 /* Descriptor Done */
c7689578 777 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 778 "%016llX ---------------- %p", i,
779 le64_to_cpu(u0->a),
780 le64_to_cpu(u0->b),
781 rx_buffer_info->skb);
782 } else {
c7689578 783 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 784 "%016llX %016llX %p", i,
785 le64_to_cpu(u0->a),
786 le64_to_cpu(u0->b),
787 (u64)rx_buffer_info->dma,
788 rx_buffer_info->skb);
789
9c50c035
ET		 790 if (netif_msg_pktdata(adapter) &&
791 rx_buffer_info->dma) {
dcd79aeb
TI		 792 print_hex_dump(KERN_INFO, "",
793 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 794 page_address(rx_buffer_info->page) +
795 rx_buffer_info->page_offset,
f800326d 796 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 797 }
798 }
799
800 if (i == rx_ring->next_to_use)
c7689578 801 pr_cont(" NTU\n");
dcd79aeb 802 else if (i == rx_ring->next_to_clean)
c7689578 803 pr_cont(" NTC\n");
dcd79aeb 804 else
c7689578 805 pr_cont("\n");
dcd79aeb
TI		 806
807 }
808 }
dcd79aeb
TI		 809}
810
5eba3699
AV		 811static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
812{
813 u32 ctrl_ext;
814
815 /* Let firmware take over control of h/w */
816 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
817 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 818 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 819}
820
821static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
822{
823 u32 ctrl_ext;
824
825 /* Let firmware know the driver has taken over */
826 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 828 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 829}
9a799d71 830
49ce9c2c 831/**
e8e26350
PW		 832 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
833 * @adapter: pointer to adapter struct
834 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
835 * @queue: queue to map the corresponding interrupt to
836 * @msix_vector: the vector to map to the corresponding queue
837 *
838 */
839static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 840 u8 queue, u8 msix_vector)
9a799d71
AK		 841{
842 u32 ivar, index;
e8e26350
PW		 843 struct ixgbe_hw *hw = &adapter->hw;
844 switch (hw->mac.type) {
845 case ixgbe_mac_82598EB:
846 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
847 if (direction == -1)
848 direction = 0;
849 index = (((direction * 64) + queue) >> 2) & 0x1F;
850 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
851 ivar &= ~(0xFF << (8 * (queue & 0x3)));
852 ivar |= (msix_vector << (8 * (queue & 0x3)));
853 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
854 break;
855 case ixgbe_mac_82599EB:
b93a2226 856 case ixgbe_mac_X540:
9a75a1ac
DS		 857 case ixgbe_mac_X550:
858 case ixgbe_mac_X550EM_x:
e8e26350
PW		 859 if (direction == -1) {
860 /* other causes */
861 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
862 index = ((queue & 1) * 8);
863 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
864 ivar &= ~(0xFF << index);
865 ivar |= (msix_vector << index);
866 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
867 break;
868 } else {
869 /* tx or rx causes */
870 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
871 index = ((16 * (queue & 1)) + (8 * direction));
872 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
873 ivar &= ~(0xFF << index);
874 ivar |= (msix_vector << index);
875 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
876 break;
877 }
878 default:
879 break;
880 }
9a799d71
AK		 881}
882
fe49f04a 883static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 884 u64 qmask)
fe49f04a
AD		 885{
886 u32 mask;
887
bd508178
AD		 888 switch (adapter->hw.mac.type) {
889 case ixgbe_mac_82598EB:
fe49f04a
AD		 890 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
891 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 892 break;
893 case ixgbe_mac_82599EB:
b93a2226 894 case ixgbe_mac_X540:
9a75a1ac
DS		 895 case ixgbe_mac_X550:
896 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 897 mask = (qmask & 0xFFFFFFFF);
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
899 mask = (qmask >> 32);
900 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 901 break;
902 default:
903 break;
fe49f04a
AD		 904 }
905}
906
729739b7
AD		 907void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
908 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 909{
729739b7
AD		 910 if (tx_buffer->skb) {
911 dev_kfree_skb_any(tx_buffer->skb);
912 if (dma_unmap_len(tx_buffer, len))
d3d00239 913 dma_unmap_single(ring->dev,
729739b7
AD		 914 dma_unmap_addr(tx_buffer, dma),
915 dma_unmap_len(tx_buffer, len),
916 DMA_TO_DEVICE);
917 } else if (dma_unmap_len(tx_buffer, len)) {
918 dma_unmap_page(ring->dev,
919 dma_unmap_addr(tx_buffer, dma),
920 dma_unmap_len(tx_buffer, len),
921 DMA_TO_DEVICE);
e5a43549 922 }
729739b7
AD		 923 tx_buffer->next_to_watch = NULL;
924 tx_buffer->skb = NULL;
925 dma_unmap_len_set(tx_buffer, len, 0);
926 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 927}
928
943561d3 929static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 930{
931 struct ixgbe_hw *hw = &adapter->hw;
932 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 933 int i;
943561d3 934 u32 data;
c84d324c 935
943561d3
AD		 936 if ((hw->fc.current_mode != ixgbe_fc_full) &&
937 (hw->fc.current_mode != ixgbe_fc_rx_pause))
938 return;
c84d324c 939
943561d3
AD		 940 switch (hw->mac.type) {
941 case ixgbe_mac_82598EB:
942 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
943 break;
944 default:
945 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
946 }
947 hwstats->lxoffrxc += data;
c84d324c 948
943561d3
AD		 949 /* refill credits (no tx hang) if we received xoff */
950 if (!data)
c84d324c 951 return;
943561d3
AD		 952
953 for (i = 0; i < adapter->num_tx_queues; i++)
954 clear_bit(__IXGBE_HANG_CHECK_ARMED,
955 &adapter->tx_ring[i]->state);
956}
957
958static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
959{
960 struct ixgbe_hw *hw = &adapter->hw;
961 struct ixgbe_hw_stats *hwstats = &adapter->stats;
962 u32 xoff[8] = {0};
2afaa00d 963 u8 tc;
943561d3
AD		 964 int i;
965 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
966
967 if (adapter->ixgbe_ieee_pfc)
968 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
969
970 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
971 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 972 return;
943561d3 973 }
c84d324c
JF		 974
975 /* update stats for each tc, only valid with PFC enabled */
976 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 977 u32 pxoffrxc;
978
c84d324c
JF		 979 switch (hw->mac.type) {
980 case ixgbe_mac_82598EB:
2afaa00d 981 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 982 break;
c84d324c 983 default:
2afaa00d 984 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 985 }
2afaa00d
PN		 986 hwstats->pxoffrxc[i] += pxoffrxc;
987 /* Get the TC for given UP */
988 tc = netdev_get_prio_tc_map(adapter->netdev, i);
989 xoff[tc] += pxoffrxc;
c84d324c
JF		 990 }
991
992 /* disarm tx queues that have received xoff frames */
993 for (i = 0; i < adapter->num_tx_queues; i++) {
994 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 995
2afaa00d 996 tc = tx_ring->dcb_tc;
c84d324c
JF		 997 if (xoff[tc])
998 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 999 }
26f23d82
YZ		 1000}
1001
c84d324c 1002static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1003{
7d7ce682 1004 return ring->stats.packets;
c84d324c
JF		 1005}
1006
1007static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1008{
2a47fa45
JF		 1009 struct ixgbe_adapter *adapter;
1010 struct ixgbe_hw *hw;
1011 u32 head, tail;
1012
1013 if (ring->l2_accel_priv)
1014 adapter = ring->l2_accel_priv->real_adapter;
1015 else
1016 adapter = netdev_priv(ring->netdev);
e01c31a5 1017
2a47fa45
JF		 1018 hw = &adapter->hw;
1019 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1020 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1021
1022 if (head != tail)
1023 return (head < tail) ?
1024 tail - head : (tail + ring->count - head);
1025
1026 return 0;
1027}
1028
1029static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1030{
1031 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1032 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1033 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1034
7d637bcc 1035 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1036
1037 /*
1038 * Check for a hung queue, but be thorough. This verifies
1039 * that a transmit has been completed since the previous
1040 * check AND there is at least one packet pending. The
1041 * ARMED bit is set to indicate a potential hang. The
1042 * bit is cleared if a pause frame is received to remove
1043 * false hang detection due to PFC or 802.3x frames. By
1044 * requiring this to fail twice we avoid races with
1045 * pfc clearing the ARMED bit and conditions where we
1046 * run the check_tx_hang logic with a transmit completion
1047 * pending but without time to complete it yet.
1048 */
e90dd264 1049 if (tx_done_old == tx_done && tx_pending)
c84d324c 1050 /* make sure it is true for two checks in a row */
e90dd264
MR		 1051 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1052 &tx_ring->state);
1053 /* update completed stats and continue */
1054 tx_ring->tx_stats.tx_done_old = tx_done;
1055 /* reset the countdown */
1056 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1057
e90dd264 1058 return false;
9a799d71
AK		 1059}
1060
c83c6cbd
AD		 1061/**
1062 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1063 * @adapter: driver private struct
1064 **/
1065static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1066{
1067
1068 /* Do the reset outside of interrupt context */
1069 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1070 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1071 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1072 ixgbe_service_event_schedule(adapter);
1073 }
1074}
e01c31a5 1075
9a799d71
AK		 1076/**
1077 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1078 * @q_vector: structure containing interrupt and ring information
e01c31a5 1079 * @tx_ring: tx ring to clean
9a799d71 1080 **/
fe49f04a 1081static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1082 struct ixgbe_ring *tx_ring)
9a799d71 1083{
fe49f04a 1084 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1085 struct ixgbe_tx_buffer *tx_buffer;
1086 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1087 unsigned int total_bytes = 0, total_packets = 0;
59224555 1088 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1089 unsigned int i = tx_ring->next_to_clean;
1090
1091 if (test_bit(__IXGBE_DOWN, &adapter->state))
1092 return true;
9a799d71 1093
d3d00239 1094 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1095 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1096 i -= tx_ring->count;
12207e49 1097
729739b7 1098 do {
d3d00239
AD		 1099 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1100
1101 /* if next_to_watch is not set then there is no work pending */
1102 if (!eop_desc)
1103 break;
1104
7f83a9e6 1105 /* prevent any other reads prior to eop_desc */
7e63bf49 1106 read_barrier_depends();
7f83a9e6 1107
d3d00239
AD		 1108 /* if DD is not set pending work has not been completed */
1109 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1110 break;
8ad494b0 1111
d3d00239
AD		 1112 /* clear next_to_watch to prevent false hangs */
1113 tx_buffer->next_to_watch = NULL;
8ad494b0 1114
091a6246
AD		 1115 /* update the statistics for this packet */
1116 total_bytes += tx_buffer->bytecount;
1117 total_packets += tx_buffer->gso_segs;
1118
fd0db0ed 1119 /* free the skb */
fe1f2a97 1120 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1121
729739b7
AD		 1122 /* unmap skb header data */
1123 dma_unmap_single(tx_ring->dev,
1124 dma_unmap_addr(tx_buffer, dma),
1125 dma_unmap_len(tx_buffer, len),
1126 DMA_TO_DEVICE);
1127
fd0db0ed
AD		 1128 /* clear tx_buffer data */
1129 tx_buffer->skb = NULL;
729739b7 1130 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1131
729739b7
AD		 1132 /* unmap remaining buffers */
1133 while (tx_desc != eop_desc) {
d3d00239
AD		 1134 tx_buffer++;
1135 tx_desc++;
8ad494b0 1136 i++;
729739b7
AD		 1137 if (unlikely(!i)) {
1138 i -= tx_ring->count;
d3d00239 1139 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1140 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1141 }
e01c31a5 1142
729739b7
AD		 1143 /* unmap any remaining paged data */
1144 if (dma_unmap_len(tx_buffer, len)) {
1145 dma_unmap_page(tx_ring->dev,
1146 dma_unmap_addr(tx_buffer, dma),
1147 dma_unmap_len(tx_buffer, len),
1148 DMA_TO_DEVICE);
1149 dma_unmap_len_set(tx_buffer, len, 0);
1150 }
1151 }
1152
1153 /* move us one more past the eop_desc for start of next pkt */
1154 tx_buffer++;
1155 tx_desc++;
1156 i++;
1157 if (unlikely(!i)) {
1158 i -= tx_ring->count;
1159 tx_buffer = tx_ring->tx_buffer_info;
1160 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1161 }
1162
1163 /* issue prefetch for next Tx descriptor */
1164 prefetch(tx_desc);
12207e49 1165
729739b7
AD		 1166 /* update budget accounting */
1167 budget--;
1168 } while (likely(budget));
1169
1170 i += tx_ring->count;
9a799d71 1171 tx_ring->next_to_clean = i;
d3d00239 1172 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1173 tx_ring->stats.bytes += total_bytes;
bd198058 1174 tx_ring->stats.packets += total_packets;
d3d00239 1175 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1176 q_vector->tx.total_bytes += total_bytes;
1177 q_vector->tx.total_packets += total_packets;
b953799e 1178
c84d324c
JF		 1179 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1180 /* schedule immediate reset if we believe we hung */
1181 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1182 e_err(drv, "Detected Tx Unit Hang\n"
1183 " Tx Queue <%d>\n"
1184 " TDH, TDT <%x>, <%x>\n"
1185 " next_to_use <%x>\n"
1186 " next_to_clean <%x>\n"
1187 "tx_buffer_info[next_to_clean]\n"
1188 " time_stamp <%lx>\n"
1189 " jiffies <%lx>\n",
1190 tx_ring->queue_index,
1191 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1192 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1193 tx_ring->next_to_use, i,
1194 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1195
1196 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1197
1198 e_info(probe,
1199 "tx hang %d detected on queue %d, resetting adapter\n",
1200 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1201
b953799e 1202 /* schedule immediate reset if we believe we hung */
c83c6cbd 1203 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1204
1205 /* the adapter is about to reset, no point in enabling stuff */
59224555 1206 return true;
b953799e 1207 }
9a799d71 1208
b2d96e0a
AD		 1209 netdev_tx_completed_queue(txring_txq(tx_ring),
1210 total_packets, total_bytes);
1211
e092be60 1212#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1213 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1214 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1215 /* Make sure that anybody stopping the queue after this
1216 * sees the new next_to_clean.
1217 */
1218 smp_mb();
729739b7
AD		 1219 if (__netif_subqueue_stopped(tx_ring->netdev,
1220 tx_ring->queue_index)
1221 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1222 netif_wake_subqueue(tx_ring->netdev,
1223 tx_ring->queue_index);
5b7da515 1224 ++tx_ring->tx_stats.restart_queue;
30eba97a 1225 }
e092be60 1226 }
9a799d71 1227
59224555 1228 return !!budget;
9a799d71
AK		 1229}
1230
5dd2d332 1231#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1232static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1233 struct ixgbe_ring *tx_ring,
33cf09c9 1234 int cpu)
bd0362dd 1235{
33cf09c9 1236 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1237 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1238 u16 reg_offset;
33cf09c9 1239
33cf09c9
AD		 1240 switch (hw->mac.type) {
1241 case ixgbe_mac_82598EB:
bdda1a61 1242 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1243 break;
1244 case ixgbe_mac_82599EB:
b93a2226 1245 case ixgbe_mac_X540:
bdda1a61
AD		 1246 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1247 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1248 break;
1249 default:
bdda1a61
AD		 1250 /* for unknown hardware do not write register */
1251 return;
bd0362dd 1252 }
bdda1a61
AD		 1253
1254 /*
1255 * We can enable relaxed ordering for reads, but not writes when
1256 * DCA is enabled. This is due to a known issue in some chipsets
1257 * which will cause the DCA tag to be cleared.
1258 */
1259 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1260 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1261 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1262
1263 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1264}
1265
bdda1a61
AD		 1266static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1267 struct ixgbe_ring *rx_ring,
33cf09c9 1268 int cpu)
bd0362dd 1269{
33cf09c9 1270 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1271 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1272 u8 reg_idx = rx_ring->reg_idx;
1273
33cf09c9
AD		 1274
1275 switch (hw->mac.type) {
33cf09c9 1276 case ixgbe_mac_82599EB:
b93a2226 1277 case ixgbe_mac_X540:
bdda1a61 1278 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1279 break;
1280 default:
1281 break;
1282 }
bdda1a61
AD		 1283
1284 /*
1285 * We can enable relaxed ordering for reads, but not writes when
1286 * DCA is enabled. This is due to a known issue in some chipsets
1287 * which will cause the DCA tag to be cleared.
1288 */
1289 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1290 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1291
1292 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1293}
1294
1295static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1296{
1297 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1298 struct ixgbe_ring *ring;
bd0362dd 1299 int cpu = get_cpu();
bd0362dd 1300
33cf09c9
AD		 1301 if (q_vector->cpu == cpu)
1302 goto out_no_update;
1303
a557928e 1304 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1305 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1306
a557928e 1307 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1308 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1309
1310 q_vector->cpu = cpu;
1311out_no_update:
bd0362dd
JC		 1312 put_cpu();
1313}
1314
1315static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1316{
1317 int i;
1318
1319 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1320 return;
1321
e35ec126
AD		 1322 /* always use CB2 mode, difference is masked in the CB driver */
1323 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1324
49c7ffbe 1325 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1326 adapter->q_vector[i]->cpu = -1;
1327 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1328 }
1329}
1330
1331static int __ixgbe_notify_dca(struct device *dev, void *data)
1332{
c60fbb00 1333 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1334 unsigned long event = *(unsigned long *)data;
1335
2a72c31e 1336 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1337 return 0;
1338
bd0362dd
JC		 1339 switch (event) {
1340 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1341 /* if we're already enabled, don't do it again */
1342 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1343 break;
652f093f 1344 if (dca_add_requester(dev) == 0) {
96b0e0f6 1345 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1346 ixgbe_setup_dca(adapter);
1347 break;
1348 }
1349 /* Fall Through since DCA is disabled. */
1350 case DCA_PROVIDER_REMOVE:
1351 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1352 dca_remove_requester(dev);
1353 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1354 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1355 }
1356 break;
1357 }
1358
652f093f 1359 return 0;
bd0362dd 1360}
67a74ee2 1361
bdda1a61 1362#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1363static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1364 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1365 struct sk_buff *skb)
1366{
8a0da21b 1367 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1368 skb_set_hash(skb,
1369 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1370 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1371}
1372
f800326d 1373#ifdef IXGBE_FCOE
ff886dfc
AD		 1374/**
1375 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1376 * @ring: structure containing ring specific data
ff886dfc
AD		 1377 * @rx_desc: advanced rx descriptor
1378 *
1379 * Returns : true if it is FCoE pkt
1380 */
57efd44c 1381static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1382 union ixgbe_adv_rx_desc *rx_desc)
1383{
1384 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1385
57efd44c 1386 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1387 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1388 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1389 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1390}
1391
f800326d 1392#endif /* IXGBE_FCOE */
e59bd25d
AV		 1393/**
1394 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1395 * @ring: structure containing ring specific data
1396 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1397 * @skb: skb currently being received and modified
1398 **/
8a0da21b 1399static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1400 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1401 struct sk_buff *skb)
9a799d71 1402{
3f207800
DS		 1403 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1404 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1405 bool encap_pkt = false;
1406
8a0da21b 1407 skb_checksum_none_assert(skb);
9a799d71 1408
712744be 1409 /* Rx csum disabled */
8a0da21b 1410 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1411 return;
e59bd25d 1412
3f207800
DS		 1413 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1414 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1415 encap_pkt = true;
1416 skb->encapsulation = 1;
1417 skb->ip_summed = CHECKSUM_NONE;
1418 }
1419
e59bd25d 1420 /* if IP and error */
f56e0cb1
AD		 1421 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1422 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1423 ring->rx_stats.csum_err++;
9a799d71
AK		 1424 return;
1425 }
e59bd25d 1426
f56e0cb1 1427 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1428 return;
1429
f56e0cb1 1430 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1431 /*
1432 * 82599 errata, UDP frames with a 0 checksum can be marked as
1433 * checksum errors.
1434 */
8a0da21b
AD		 1435 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1436 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1437 return;
1438
8a0da21b 1439 ring->rx_stats.csum_err++;
e59bd25d
AV		 1440 return;
1441 }
1442
9a799d71 1443 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1444 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1445 if (encap_pkt) {
1446 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1447 return;
1448
1449 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1450 ring->rx_stats.csum_err++;
1451 return;
1452 }
1453 /* If we checked the outer header let the stack know */
1454 skb->csum_level = 1;
1455 }
9a799d71
AK		 1456}
1457
f990b79b
AD		 1458static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1459 struct ixgbe_rx_buffer *bi)
1460{
1461 struct page *page = bi->page;
18cb652a 1462 dma_addr_t dma;
f990b79b 1463
f800326d 1464 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1465 if (likely(page))
f990b79b
AD		 1466 return true;
1467
f800326d 1468 /* alloc new page for storage */
18cb652a
AD		 1469 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1470 if (unlikely(!page)) {
1471 rx_ring->rx_stats.alloc_rx_page_failed++;
1472 return false;
f990b79b
AD		 1473 }
1474
f800326d
AD		 1475 /* map page for use */
1476 dma = dma_map_page(rx_ring->dev, page, 0,
1477 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1478
1479 /*
1480 * if mapping failed free memory back to system since
1481 * there isn't much point in holding memory we can't use
1482 */
1483 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1484 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1485
f990b79b
AD		 1486 rx_ring->rx_stats.alloc_rx_page_failed++;
1487 return false;
1488 }
1489
f800326d 1490 bi->dma = dma;
18cb652a 1491 bi->page = page;
afaa9459 1492 bi->page_offset = 0;
f800326d 1493
f990b79b
AD		 1494 return true;
1495}
1496
9a799d71 1497/**
f990b79b 1498 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1499 * @rx_ring: ring to place buffers on
1500 * @cleaned_count: number of buffers to replace
9a799d71 1501 **/
fc77dc3c 1502void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1503{
9a799d71 1504 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1505 struct ixgbe_rx_buffer *bi;
d5f398ed 1506 u16 i = rx_ring->next_to_use;
9a799d71 1507
f800326d
AD		 1508 /* nothing to do */
1509 if (!cleaned_count)
fc77dc3c
AD		 1510 return;
1511
e4f74028 1512 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1513 bi = &rx_ring->rx_buffer_info[i];
1514 i -= rx_ring->count;
9a799d71 1515
f800326d
AD		 1516 do {
1517 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1518 break;
d5f398ed 1519
f800326d
AD		 1520 /*
1521 * Refresh the desc even if buffer_addrs didn't change
1522 * because each write-back erases this info.
1523 */
1524 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1525
f990b79b
AD		 1526 rx_desc++;
1527 bi++;
9a799d71 1528 i++;
f990b79b 1529 if (unlikely(!i)) {
e4f74028 1530 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1531 bi = rx_ring->rx_buffer_info;
1532 i -= rx_ring->count;
1533 }
1534
18cb652a
AD		 1535 /* clear the status bits for the next_to_use descriptor */
1536 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1537
1538 cleaned_count--;
1539 } while (cleaned_count);
7c6e0a43 1540
f990b79b
AD		 1541 i += rx_ring->count;
1542
ad435ec6
AD		 1543 if (rx_ring->next_to_use != i) {
1544 rx_ring->next_to_use = i;
1545
1546 /* update next to alloc since we have filled the ring */
1547 rx_ring->next_to_alloc = i;
1548
1549 /* Force memory writes to complete before letting h/w
1550 * know there are new descriptors to fetch. (Only
1551 * applicable for weak-ordered memory model archs,
1552 * such as IA-64).
1553 */
1554 wmb();
1555 writel(i, rx_ring->tail);
1556 }
9a799d71
AK		 1557}
1558
1d2024f6
AD		 1559static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1560 struct sk_buff *skb)
1561{
f800326d 1562 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1563
1564 /* set gso_size to avoid messing up TCP MSS */
1565 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1566 IXGBE_CB(skb)->append_cnt);
96be80ab 1567 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1568}
1569
1570static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1571 struct sk_buff *skb)
1572{
1573 /* if append_cnt is 0 then frame is not RSC */
1574 if (!IXGBE_CB(skb)->append_cnt)
1575 return;
1576
1577 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1578 rx_ring->rx_stats.rsc_flush++;
1579
1580 ixgbe_set_rsc_gso_size(rx_ring, skb);
1581
1582 /* gso_size is computed using append_cnt so always clear it last */
1583 IXGBE_CB(skb)->append_cnt = 0;
1584}
1585
8a0da21b
AD		 1586/**
1587 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1588 * @rx_ring: rx descriptor ring packet is being transacted on
1589 * @rx_desc: pointer to the EOP Rx descriptor
1590 * @skb: pointer to current skb being populated
f8212f97 1591 *
8a0da21b
AD		 1592 * This function checks the ring, descriptor, and packet information in
1593 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1594 * other fields within the skb.
f8212f97 1595 **/
8a0da21b
AD		 1596static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1597 union ixgbe_adv_rx_desc *rx_desc,
1598 struct sk_buff *skb)
f8212f97 1599{
43e95f11
JF		 1600 struct net_device *dev = rx_ring->netdev;
1601
8a0da21b
AD		 1602 ixgbe_update_rsc_stats(rx_ring, skb);
1603
1604 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1605
8a0da21b
AD		 1606 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1607
eda183c2
JK		 1608 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1609 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1610
f646968f 1611 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1612 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1613 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1614 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1615 }
1616
8a0da21b 1617 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1618
43e95f11 1619 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1620}
1621
8a0da21b
AD		 1622static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1623 struct sk_buff *skb)
aa80175a 1624{
b4640030 1625 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1626 netif_receive_skb(skb);
8a0da21b 1627 else
856f606e 1628 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1629}
43634e82 1630
f800326d
AD		 1631/**
1632 * ixgbe_is_non_eop - process handling of non-EOP buffers
1633 * @rx_ring: Rx ring being processed
1634 * @rx_desc: Rx descriptor for current buffer
1635 * @skb: Current socket buffer containing buffer in progress
1636 *
1637 * This function updates next to clean. If the buffer is an EOP buffer
1638 * this function exits returning false, otherwise it will place the
1639 * sk_buff in the next buffer to be chained and return true indicating
1640 * that this is in fact a non-EOP buffer.
1641 **/
1642static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1643 union ixgbe_adv_rx_desc *rx_desc,
1644 struct sk_buff *skb)
1645{
1646 u32 ntc = rx_ring->next_to_clean + 1;
1647
1648 /* fetch, update, and store next to clean */
1649 ntc = (ntc < rx_ring->count) ? ntc : 0;
1650 rx_ring->next_to_clean = ntc;
1651
1652 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1653
5a02cbd1
AD		 1654 /* update RSC append count if present */
1655 if (ring_is_rsc_enabled(rx_ring)) {
1656 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1657 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1658
1659 if (unlikely(rsc_enabled)) {
1660 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1661
1662 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1663 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1664
5a02cbd1
AD		 1665 /* update ntc based on RSC value */
1666 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1667 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1668 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1669 }
f800326d
AD		 1670 }
1671
5a02cbd1
AD		 1672 /* if we are the last buffer then there is nothing else to do */
1673 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1674 return false;
1675
f800326d
AD		 1676 /* place skb in next buffer to be received */
1677 rx_ring->rx_buffer_info[ntc].skb = skb;
1678 rx_ring->rx_stats.non_eop_descs++;
1679
1680 return true;
1681}
1682
19861ce2
AD		 1683/**
1684 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1685 * @rx_ring: rx descriptor ring packet is being transacted on
1686 * @skb: pointer to current skb being adjusted
1687 *
1688 * This function is an ixgbe specific version of __pskb_pull_tail. The
1689 * main difference between this version and the original function is that
1690 * this function can make several assumptions about the state of things
1691 * that allow for significant optimizations versus the standard function.
1692 * As a result we can do things like drop a frag and maintain an accurate
1693 * truesize for the skb.
1694 */
1695static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1696 struct sk_buff *skb)
1697{
1698 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1699 unsigned char *va;
1700 unsigned int pull_len;
1701
1702 /*
1703 * it is valid to use page_address instead of kmap since we are
1704 * working with pages allocated out of the lomem pool per
1705 * alloc_page(GFP_ATOMIC)
1706 */
1707 va = skb_frag_address(frag);
1708
1709 /*
1710 * we need the header to contain the greater of either ETH_HLEN or
1711 * 60 bytes if the skb->len is less than 60 for skb_pad.
1712 */
8496e338 1713 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1714
1715 /* align pull length to size of long to optimize memcpy performance */
1716 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1717
1718 /* update all of the pointers */
1719 skb_frag_size_sub(frag, pull_len);
1720 frag->page_offset += pull_len;
1721 skb->data_len -= pull_len;
1722 skb->tail += pull_len;
19861ce2
AD		 1723}
1724
42073d91
AD		 1725/**
1726 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1727 * @rx_ring: rx descriptor ring packet is being transacted on
1728 * @skb: pointer to current skb being updated
1729 *
1730 * This function provides a basic DMA sync up for the first fragment of an
1731 * skb. The reason for doing this is that the first fragment cannot be
1732 * unmapped until we have reached the end of packet descriptor for a buffer
1733 * chain.
1734 */
1735static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1736 struct sk_buff *skb)
1737{
1738 /* if the page was released unmap it, else just sync our portion */
1739 if (unlikely(IXGBE_CB(skb)->page_released)) {
1740 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1741 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1742 IXGBE_CB(skb)->page_released = false;
1743 } else {
1744 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1745
1746 dma_sync_single_range_for_cpu(rx_ring->dev,
1747 IXGBE_CB(skb)->dma,
1748 frag->page_offset,
1749 ixgbe_rx_bufsz(rx_ring),
1750 DMA_FROM_DEVICE);
1751 }
1752 IXGBE_CB(skb)->dma = 0;
1753}
1754
f800326d
AD		 1755/**
1756 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1757 * @rx_ring: rx descriptor ring packet is being transacted on
1758 * @rx_desc: pointer to the EOP Rx descriptor
1759 * @skb: pointer to current skb being fixed
1760 *
1761 * Check for corrupted packet headers caused by senders on the local L2
1762 * embedded NIC switch not setting up their Tx Descriptors right. These
1763 * should be very rare.
1764 *
1765 * Also address the case where we are pulling data in on pages only
1766 * and as such no data is present in the skb header.
1767 *
1768 * In addition if skb is not at least 60 bytes we need to pad it so that
1769 * it is large enough to qualify as a valid Ethernet frame.
1770 *
1771 * Returns true if an error was encountered and skb was freed.
1772 **/
1773static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1774 union ixgbe_adv_rx_desc *rx_desc,
1775 struct sk_buff *skb)
1776{
f800326d 1777 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1778
1779 /* verify that the packet does not have any known errors */
1780 if (unlikely(ixgbe_test_staterr(rx_desc,
1781 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1782 !(netdev->features & NETIF_F_RXALL))) {
1783 dev_kfree_skb_any(skb);
1784 return true;
1785 }
1786
19861ce2 1787 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1788 if (skb_is_nonlinear(skb))
1789 ixgbe_pull_tail(rx_ring, skb);
f800326d 1790
57efd44c
AD		 1791#ifdef IXGBE_FCOE
1792 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1793 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1794 return false;
1795
1796#endif
a94d9e22
AD		 1797 /* if eth_skb_pad returns an error the skb was freed */
1798 if (eth_skb_pad(skb))
1799 return true;
f800326d
AD		 1800
1801 return false;
1802}
1803
f800326d
AD		 1804/**
1805 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1806 * @rx_ring: rx descriptor ring to store buffers on
1807 * @old_buff: donor buffer to have page reused
1808 *
0549ae20 1809 * Synchronizes page for reuse by the adapter
f800326d
AD		 1810 **/
1811static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1812 struct ixgbe_rx_buffer *old_buff)
1813{
1814 struct ixgbe_rx_buffer *new_buff;
1815 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1816
1817 new_buff = &rx_ring->rx_buffer_info[nta];
1818
1819 /* update, and store next to alloc */
1820 nta++;
1821 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1822
1823 /* transfer page from old buffer to new buffer */
18cb652a 1824 *new_buff = *old_buff;
f800326d
AD		 1825
1826 /* sync the buffer for use by the device */
1827 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1828 new_buff->page_offset,
1829 ixgbe_rx_bufsz(rx_ring),
f800326d 1830 DMA_FROM_DEVICE);
f800326d
AD		 1831}
1832
18cb652a
AD		 1833static inline bool ixgbe_page_is_reserved(struct page *page)
1834{
1835 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc;
1836}
1837
f800326d
AD		 1838/**
1839 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1840 * @rx_ring: rx descriptor ring to transact packets on
1841 * @rx_buffer: buffer containing page to add
1842 * @rx_desc: descriptor containing length of buffer written by hardware
1843 * @skb: sk_buff to place the data into
1844 *
0549ae20
AD		 1845 * This function will add the data contained in rx_buffer->page to the skb.
1846 * This is done either through a direct copy if the data in the buffer is
1847 * less than the skb header size, otherwise it will just attach the page as
1848 * a frag to the skb.
1849 *
1850 * The function will then update the page offset if necessary and return
1851 * true if the buffer can be reused by the adapter.
f800326d 1852 **/
0549ae20 1853static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1854 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1855 union ixgbe_adv_rx_desc *rx_desc,
1856 struct sk_buff *skb)
f800326d 1857{
0549ae20
AD		 1858 struct page *page = rx_buffer->page;
1859 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1860#if (PAGE_SIZE < 8192)
0549ae20 1861 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1862#else
1863 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1864 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1865 ixgbe_rx_bufsz(rx_ring);
1866#endif
0549ae20 1867
cf3fe7ac
AD		 1868 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1869 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1870
1871 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1872
18cb652a
AD		 1873 /* page is not reserved, we can reuse buffer as-is */
1874 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1875 return true;
1876
1877 /* this page cannot be reused so discard it */
18cb652a 1878 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1879 return false;
1880 }
1881
0549ae20
AD		 1882 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1883 rx_buffer->page_offset, size, truesize);
1884
09816fbe 1885 /* avoid re-using remote pages */
18cb652a 1886 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1887 return false;
1888
1889#if (PAGE_SIZE < 8192)
1890 /* if we are only owner of page we can reuse it */
1891 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1892 return false;
1893
1894 /* flip page offset to other buffer */
1895 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1896#else
1897 /* move offset up to the next cache line */
1898 rx_buffer->page_offset += truesize;
1899
1900 if (rx_buffer->page_offset > last_offset)
1901 return false;
09816fbe 1902#endif
0549ae20 1903
18cb652a
AD		 1904 /* Even if we own the page, we are not allowed to use atomic_set()
1905 * This would break get_page_unless_zero() users.
1906 */
1907 atomic_inc(&page->_count);
1908
0549ae20 1909 return true;
f800326d
AD		 1910}
1911
18806c9e
AD		 1912static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1913 union ixgbe_adv_rx_desc *rx_desc)
1914{
1915 struct ixgbe_rx_buffer *rx_buffer;
1916 struct sk_buff *skb;
1917 struct page *page;
1918
1919 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1920 page = rx_buffer->page;
1921 prefetchw(page);
1922
1923 skb = rx_buffer->skb;
1924
1925 if (likely(!skb)) {
1926 void *page_addr = page_address(page) +
1927 rx_buffer->page_offset;
1928
1929 /* prefetch first cache line of first page */
1930 prefetch(page_addr);
1931#if L1_CACHE_BYTES < 128
1932 prefetch(page_addr + L1_CACHE_BYTES);
1933#endif
1934
1935 /* allocate a skb to store the frags */
67fd893e
AD		 1936 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1937 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1938 if (unlikely(!skb)) {
1939 rx_ring->rx_stats.alloc_rx_buff_failed++;
1940 return NULL;
1941 }
1942
1943 /*
1944 * we will be copying header into skb->data in
1945 * pskb_may_pull so it is in our interest to prefetch
1946 * it now to avoid a possible cache miss
1947 */
1948 prefetchw(skb->data);
1949
1950 /*
1951 * Delay unmapping of the first packet. It carries the
1952 * header information, HW may still access the header
1953 * after the writeback. Only unmap it when EOP is
1954 * reached
1955 */
1956 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1957 goto dma_sync;
1958
1959 IXGBE_CB(skb)->dma = rx_buffer->dma;
1960 } else {
1961 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1962 ixgbe_dma_sync_frag(rx_ring, skb);
1963
1964dma_sync:
1965 /* we are reusing so sync this buffer for CPU use */
1966 dma_sync_single_range_for_cpu(rx_ring->dev,
1967 rx_buffer->dma,
1968 rx_buffer->page_offset,
1969 ixgbe_rx_bufsz(rx_ring),
1970 DMA_FROM_DEVICE);
18cb652a
AD		 1971
1972 rx_buffer->skb = NULL;
18806c9e
AD		 1973 }
1974
1975 /* pull page into skb */
1976 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1977 /* hand second half of page back to the ring */
1978 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1979 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1980 /* the page has been released from the ring */
1981 IXGBE_CB(skb)->page_released = true;
1982 } else {
1983 /* we are not reusing the buffer so unmap it */
1984 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1985 ixgbe_rx_pg_size(rx_ring),
1986 DMA_FROM_DEVICE);
1987 }
1988
1989 /* clear contents of buffer_info */
18806c9e
AD		 1990 rx_buffer->page = NULL;
1991
1992 return skb;
f800326d
AD		 1993}
1994
1995/**
1996 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1997 * @q_vector: structure containing interrupt and ring information
1998 * @rx_ring: rx descriptor ring to transact packets on
1999 * @budget: Total limit on number of packets to process
2000 *
2001 * This function provides a "bounce buffer" approach to Rx interrupt
2002 * processing. The advantage to this is that on systems that have
2003 * expensive overhead for IOMMU access this provides a means of avoiding
2004 * it by maintaining the mapping of the page to the syste.
2005 *
5a85e737 2006 * Returns amount of work completed
f800326d 2007 **/
5a85e737 2008static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2009 struct ixgbe_ring *rx_ring,
f4de00ed 2010 const int budget)
9a799d71 2011{
d2f4fbe2 2012 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2013#ifdef IXGBE_FCOE
f800326d 2014 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2015 int ddp_bytes;
2016 unsigned int mss = 0;
3d8fd385 2017#endif /* IXGBE_FCOE */
f800326d 2018 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2019
fdabfc8a 2020 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2021 union ixgbe_adv_rx_desc *rx_desc;
2022 struct sk_buff *skb;
f800326d
AD		 2023
2024 /* return some buffers to hardware, one at a time is too slow */
2025 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2026 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2027 cleaned_count = 0;
2028 }
2029
18806c9e 2030 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2031
124b74c1 2032 if (!rx_desc->wb.upper.status_error)
f800326d 2033 break;
9a799d71 2034
124b74c1 2035 /* This memory barrier is needed to keep us from reading
f800326d 2036 * any other fields out of the rx_desc until we know the
124b74c1 2037 * descriptor has been written back
f800326d 2038 */
124b74c1 2039 dma_rmb();
9a799d71 2040
18806c9e
AD		 2041 /* retrieve a buffer from the ring */
2042 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2043
18806c9e
AD		 2044 /* exit if we failed to retrieve a buffer */
2045 if (!skb)
2046 break;
9a799d71 2047
9a799d71 2048 cleaned_count++;
f8212f97 2049
f800326d
AD		 2050 /* place incomplete frames back on ring for completion */
2051 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2052 continue;
c267fc16 2053
f800326d
AD		 2054 /* verify the packet layout is correct */
2055 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2056 continue;
9a799d71 2057
d2f4fbe2
AV		 2058 /* probably a little skewed due to removing CRC */
2059 total_rx_bytes += skb->len;
d2f4fbe2 2060
8a0da21b
AD		 2061 /* populate checksum, timestamp, VLAN, and protocol */
2062 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2063
332d4a7d
YZ		 2064#ifdef IXGBE_FCOE
2065 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2066 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2067 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2068 /* include DDPed FCoE data */
2069 if (ddp_bytes > 0) {
2070 if (!mss) {
2071 mss = rx_ring->netdev->mtu -
2072 sizeof(struct fcoe_hdr) -
2073 sizeof(struct fc_frame_header) -
2074 sizeof(struct fcoe_crc_eof);
2075 if (mss > 512)
2076 mss &= ~511;
2077 }
2078 total_rx_bytes += ddp_bytes;
2079 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2080 mss);
2081 }
63d635b2
AD		 2082 if (!ddp_bytes) {
2083 dev_kfree_skb_any(skb);
f800326d 2084 continue;
63d635b2 2085 }
3d8fd385 2086 }
f800326d 2087
332d4a7d 2088#endif /* IXGBE_FCOE */
8b80cda5 2089 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2090 ixgbe_rx_skb(q_vector, skb);
9a799d71 2091
f800326d 2092 /* update budget accounting */
f4de00ed 2093 total_rx_packets++;
fdabfc8a 2094 }
9a799d71 2095
c267fc16
AD		 2096 u64_stats_update_begin(&rx_ring->syncp);
2097 rx_ring->stats.packets += total_rx_packets;
2098 rx_ring->stats.bytes += total_rx_bytes;
2099 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2100 q_vector->rx.total_packets += total_rx_packets;
2101 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2102
5a85e737 2103 return total_rx_packets;
9a799d71
AK		 2104}
2105
e0d1095a 2106#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2107/* must be called with local_bh_disable()d */
2108static int ixgbe_low_latency_recv(struct napi_struct *napi)
2109{
2110 struct ixgbe_q_vector *q_vector =
2111 container_of(napi, struct ixgbe_q_vector, napi);
2112 struct ixgbe_adapter *adapter = q_vector->adapter;
2113 struct ixgbe_ring *ring;
2114 int found = 0;
2115
2116 if (test_bit(__IXGBE_DOWN, &adapter->state))
2117 return LL_FLUSH_FAILED;
2118
2119 if (!ixgbe_qv_lock_poll(q_vector))
2120 return LL_FLUSH_BUSY;
2121
2122 ixgbe_for_each_ring(ring, q_vector->rx) {
2123 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2124#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2125 if (found)
2126 ring->stats.cleaned += found;
2127 else
2128 ring->stats.misses++;
2129#endif
5a85e737
ET		 2130 if (found)
2131 break;
2132 }
2133
2134 ixgbe_qv_unlock_poll(q_vector);
2135
2136 return found;
2137}
e0d1095a 2138#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2139
9a799d71
AK		 2140/**
2141 * ixgbe_configure_msix - Configure MSI-X hardware
2142 * @adapter: board private structure
2143 *
2144 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2145 * interrupts.
2146 **/
2147static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2148{
021230d4 2149 struct ixgbe_q_vector *q_vector;
49c7ffbe 2150 int v_idx;
021230d4 2151 u32 mask;
9a799d71 2152
8e34d1aa
AD		 2153 /* Populate MSIX to EITR Select */
2154 if (adapter->num_vfs > 32) {
2155 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2156 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2157 }
2158
4df10466
JB		 2159 /*
2160 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2161 * corresponding register.
2162 */
49c7ffbe 2163 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2164 struct ixgbe_ring *ring;
7a921c93 2165 q_vector = adapter->q_vector[v_idx];
021230d4 2166
a557928e 2167 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2168 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2169
a557928e 2170 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2171 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2172
fe49f04a 2173 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2174 }
2175
bd508178
AD		 2176 switch (adapter->hw.mac.type) {
2177 case ixgbe_mac_82598EB:
e8e26350 2178 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2179 v_idx);
bd508178
AD		 2180 break;
2181 case ixgbe_mac_82599EB:
b93a2226 2182 case ixgbe_mac_X540:
9a75a1ac
DS		 2183 case ixgbe_mac_X550:
2184 case ixgbe_mac_X550EM_x:
e8e26350 2185 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2186 break;
bd508178
AD		 2187 default:
2188 break;
2189 }
021230d4
AV		 2190 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2191
41fb9248 2192 /* set up to autoclear timer, and the vectors */
021230d4 2193 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2194 mask &= ~(IXGBE_EIMS_OTHER |
2195 IXGBE_EIMS_MAILBOX |
2196 IXGBE_EIMS_LSC);
2197
021230d4 2198 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2199}
2200
f494e8fa
AV		 2201enum latency_range {
2202 lowest_latency = 0,
2203 low_latency = 1,
2204 bulk_latency = 2,
2205 latency_invalid = 255
2206};
2207
2208/**
2209 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2210 * @q_vector: structure containing interrupt and ring information
2211 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2212 *
2213 * Stores a new ITR value based on packets and byte
2214 * counts during the last interrupt. The advantage of per interrupt
2215 * computation is faster updates and more accurate ITR for the current
2216 * traffic pattern. Constants in this function were computed
2217 * based on theoretical maximum wire speed and thresholds were set based
2218 * on testing data as well as attempting to minimize response time
2219 * while increasing bulk throughput.
2220 * this functionality is controlled by the InterruptThrottleRate module
2221 * parameter (see ixgbe_param.c)
2222 **/
bd198058
AD		 2223static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2224 struct ixgbe_ring_container *ring_container)
f494e8fa 2225{
bd198058
AD		 2226 int bytes = ring_container->total_bytes;
2227 int packets = ring_container->total_packets;
2228 u32 timepassed_us;
621bd70e 2229 u64 bytes_perint;
bd198058 2230 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2231
2232 if (packets == 0)
bd198058 2233 return;
f494e8fa
AV		 2234
2235 /* simple throttlerate management
621bd70e
AD		 2236 * 0-10MB/s lowest (100000 ints/s)
2237 * 10-20MB/s low (20000 ints/s)
2238 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2239 */
2240 /* what was last interrupt timeslice? */
d5bf4f67 2241 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2242 if (timepassed_us == 0)
2243 return;
2244
f494e8fa
AV		 2245 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2246
2247 switch (itr_setting) {
2248 case lowest_latency:
621bd70e 2249 if (bytes_perint > 10)
bd198058 2250 itr_setting = low_latency;
f494e8fa
AV		 2251 break;
2252 case low_latency:
621bd70e 2253 if (bytes_perint > 20)
bd198058 2254 itr_setting = bulk_latency;
621bd70e 2255 else if (bytes_perint <= 10)
bd198058 2256 itr_setting = lowest_latency;
f494e8fa
AV		 2257 break;
2258 case bulk_latency:
621bd70e 2259 if (bytes_perint <= 20)
bd198058 2260 itr_setting = low_latency;
f494e8fa
AV		 2261 break;
2262 }
2263
bd198058
AD		 2264 /* clear work counters since we have the values we need */
2265 ring_container->total_bytes = 0;
2266 ring_container->total_packets = 0;
2267
2268 /* write updated itr to ring container */
2269 ring_container->itr = itr_setting;
f494e8fa
AV		 2270}
2271
509ee935
JB		 2272/**
2273 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2274 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2275 *
2276 * This function is made to be called by ethtool and by the driver
2277 * when it needs to update EITR registers at runtime. Hardware
2278 * specific quirks/differences are taken care of here.
2279 */
fe49f04a 2280void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2281{
fe49f04a 2282 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2283 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2284 int v_idx = q_vector->v_idx;
5d967eb7 2285 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2286
bd508178
AD		 2287 switch (adapter->hw.mac.type) {
2288 case ixgbe_mac_82598EB:
509ee935
JB		 2289 /* must write high and low 16 bits to reset counter */
2290 itr_reg |= (itr_reg << 16);
bd508178
AD		 2291 break;
2292 case ixgbe_mac_82599EB:
b93a2226 2293 case ixgbe_mac_X540:
9a75a1ac
DS		 2294 case ixgbe_mac_X550:
2295 case ixgbe_mac_X550EM_x:
509ee935
JB		 2296 /*
2297 * set the WDIS bit to not clear the timer bits and cause an
2298 * immediate assertion of the interrupt
2299 */
2300 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2301 break;
2302 default:
2303 break;
509ee935
JB		 2304 }
2305 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2306}
2307
bd198058 2308static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2309{
d5bf4f67 2310 u32 new_itr = q_vector->itr;
bd198058 2311 u8 current_itr;
f494e8fa 2312
bd198058
AD		 2313 ixgbe_update_itr(q_vector, &q_vector->tx);
2314 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2315
08c8833b 2316 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2317
2318 switch (current_itr) {
2319 /* counts and packets in update_itr are dependent on these numbers */
2320 case lowest_latency:
d5bf4f67 2321 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2322 break;
2323 case low_latency:
d5bf4f67 2324 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2325 break;
2326 case bulk_latency:
d5bf4f67 2327 new_itr = IXGBE_8K_ITR;
f494e8fa 2328 break;
bd198058
AD		 2329 default:
2330 break;
f494e8fa
AV		 2331 }
2332
d5bf4f67 2333 if (new_itr != q_vector->itr) {
fe49f04a 2334 /* do an exponential smoothing */
d5bf4f67
ET		 2335 new_itr = (10 * new_itr * q_vector->itr) /
2336 ((9 * new_itr) + q_vector->itr);
509ee935 2337
bd198058 2338 /* save the algorithm value here */
5d967eb7 2339 q_vector->itr = new_itr;
fe49f04a
AD		 2340
2341 ixgbe_write_eitr(q_vector);
f494e8fa 2342 }
f494e8fa
AV		 2343}
2344
119fc60a 2345/**
de88eeeb 2346 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2347 * @adapter: pointer to adapter
119fc60a 2348 **/
f0f9778d 2349static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2350{
119fc60a
MC		 2351 struct ixgbe_hw *hw = &adapter->hw;
2352 u32 eicr = adapter->interrupt_event;
2353
f0f9778d 2354 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2355 return;
2356
f0f9778d
AD		 2357 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2358 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2359 return;
2360
2361 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2362
7ca647bd 2363 switch (hw->device_id) {
f0f9778d
AD		 2364 case IXGBE_DEV_ID_82599_T3_LOM:
2365 /*
2366 * Since the warning interrupt is for both ports
2367 * we don't have to check if:
2368 * - This interrupt wasn't for our port.
2369 * - We may have missed the interrupt so always have to
2370 * check if we got a LSC
2371 */
9a900eca 2372 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2373 !(eicr & IXGBE_EICR_LSC))
2374 return;
2375
2376 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2377 u32 speed;
f0f9778d 2378 bool link_up = false;
7ca647bd 2379
3d292265 2380 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2381
f0f9778d
AD		 2382 if (link_up)
2383 return;
2384 }
2385
2386 /* Check if this is not due to overtemp */
2387 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2388 return;
2389
2390 break;
7ca647bd 2391 default:
597f22d6
DS		 2392 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2393 return;
9a900eca 2394 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2395 return;
7ca647bd 2396 break;
119fc60a 2397 }
f44e751b 2398 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2399
2400 adapter->interrupt_event = 0;
119fc60a
MC		 2401}
2402
0befdb3e
JB		 2403static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2404{
2405 struct ixgbe_hw *hw = &adapter->hw;
2406
2407 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2408 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2409 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2410 /* write to clear the interrupt */
9a900eca 2411 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2412 }
2413}
cf8280ee 2414
4f51bf70
JK		 2415static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2416{
9a900eca
DS		 2417 struct ixgbe_hw *hw = &adapter->hw;
2418
4f51bf70
JK		 2419 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2420 return;
2421
2422 switch (adapter->hw.mac.type) {
2423 case ixgbe_mac_82599EB:
2424 /*
2425 * Need to check link state so complete overtemp check
2426 * on service task
2427 */
9a900eca
DS		 2428 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2429 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2430 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2431 adapter->interrupt_event = eicr;
2432 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2433 ixgbe_service_event_schedule(adapter);
2434 return;
2435 }
2436 return;
2437 case ixgbe_mac_X540:
2438 if (!(eicr & IXGBE_EICR_TS))
2439 return;
2440 break;
2441 default:
2442 return;
2443 }
2444
f44e751b 2445 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2446}
2447
45788d2a
DS		 2448static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2449{
2450 switch (hw->mac.type) {
2451 case ixgbe_mac_82598EB:
2452 if (hw->phy.type == ixgbe_phy_nl)
2453 return true;
2454 return false;
2455 case ixgbe_mac_82599EB:
2456 case ixgbe_mac_X550EM_x:
2457 switch (hw->mac.ops.get_media_type(hw)) {
2458 case ixgbe_media_type_fiber:
2459 case ixgbe_media_type_fiber_qsfp:
2460 return true;
2461 default:
2462 return false;
2463 }
2464 default:
2465 return false;
2466 }
2467}
2468
e8e26350
PW		 2469static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2470{
2471 struct ixgbe_hw *hw = &adapter->hw;
2472
9a900eca 2473 if (eicr & IXGBE_EICR_GPI_SDP2(hw)) {
73c4b7cd 2474 /* Clear the interrupt */
9a900eca 2475 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2(hw));
7086400d
AD		 2476 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2477 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2478 ixgbe_service_event_schedule(adapter);
2479 }
73c4b7cd
AD		 2480 }
2481
9a900eca 2482 if (eicr & IXGBE_EICR_GPI_SDP1(hw)) {
e8e26350 2483 /* Clear the interrupt */
9a900eca 2484 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2485 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2486 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2487 ixgbe_service_event_schedule(adapter);
2488 }
e8e26350
PW		 2489 }
2490}
2491
cf8280ee
JB		 2492static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2493{
2494 struct ixgbe_hw *hw = &adapter->hw;
2495
2496 adapter->lsc_int++;
2497 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2498 adapter->link_check_timeout = jiffies;
2499 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2500 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2501 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2502 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2503 }
2504}
2505
fe49f04a
AD		 2506static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2507 u64 qmask)
2508{
2509 u32 mask;
bd508178 2510 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2511
bd508178
AD		 2512 switch (hw->mac.type) {
2513 case ixgbe_mac_82598EB:
fe49f04a 2514 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2515 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2516 break;
2517 case ixgbe_mac_82599EB:
b93a2226 2518 case ixgbe_mac_X540:
9a75a1ac
DS		 2519 case ixgbe_mac_X550:
2520 case ixgbe_mac_X550EM_x:
fe49f04a 2521 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2522 if (mask)
2523 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2524 mask = (qmask >> 32);
bd508178
AD		 2525 if (mask)
2526 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2527 break;
2528 default:
2529 break;
fe49f04a
AD		 2530 }
2531 /* skip the flush */
2532}
2533
2534static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2535 u64 qmask)
fe49f04a
AD		 2536{
2537 u32 mask;
bd508178 2538 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2539
bd508178
AD		 2540 switch (hw->mac.type) {
2541 case ixgbe_mac_82598EB:
fe49f04a 2542 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2543 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2544 break;
2545 case ixgbe_mac_82599EB:
b93a2226 2546 case ixgbe_mac_X540:
9a75a1ac
DS		 2547 case ixgbe_mac_X550:
2548 case ixgbe_mac_X550EM_x:
fe49f04a 2549 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2550 if (mask)
2551 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2552 mask = (qmask >> 32);
bd508178
AD		 2553 if (mask)
2554 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2555 break;
2556 default:
2557 break;
fe49f04a
AD		 2558 }
2559 /* skip the flush */
2560}
2561
021230d4 2562/**
2c4af694
AD		 2563 * ixgbe_irq_enable - Enable default interrupt generation settings
2564 * @adapter: board private structure
021230d4 2565 **/
2c4af694
AD		 2566static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2567 bool flush)
9a799d71 2568{
9a900eca 2569 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2570 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2571
2c4af694
AD		 2572 /* don't reenable LSC while waiting for link */
2573 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2574 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2575
2c4af694 2576 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2577 switch (adapter->hw.mac.type) {
2578 case ixgbe_mac_82599EB:
9a900eca 2579 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2580 break;
2581 case ixgbe_mac_X540:
9a75a1ac
DS		 2582 case ixgbe_mac_X550:
2583 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2584 mask |= IXGBE_EIMS_TS;
2585 break;
2586 default:
2587 break;
2588 }
2c4af694 2589 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2590 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2591 switch (adapter->hw.mac.type) {
2592 case ixgbe_mac_82599EB:
9a900eca
DS		 2593 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2594 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2595 /* fall through */
858bc081 2596 case ixgbe_mac_X540:
9a75a1ac
DS		 2597 case ixgbe_mac_X550:
2598 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2599 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2600 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2601 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2602 mask |= IXGBE_EIMS_MAILBOX;
2603 break;
2604 default:
2605 break;
9a799d71 2606 }
db0677fa 2607
2c4af694
AD		 2608 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2609 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2610 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2611
2c4af694
AD		 2612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2613 if (queues)
2614 ixgbe_irq_enable_queues(adapter, ~0);
2615 if (flush)
2616 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2617}
2618
2c4af694 2619static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2620{
a65151ba 2621 struct ixgbe_adapter *adapter = data;
9a799d71 2622 struct ixgbe_hw *hw = &adapter->hw;
54037505 2623 u32 eicr;
91281fd3 2624
54037505
DS		 2625 /*
2626 * Workaround for Silicon errata. Use clear-by-write instead
2627 * of clear-by-read. Reading with EICS will return the
2628 * interrupt causes without clearing, which later be done
2629 * with the write to EICR.
2630 */
2631 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2632
2633 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2634 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2635 * the bits are high when ixgbe_msix_other is called. There is a race
2636 * condition otherwise which results in possible performance loss
2637 * especially if the ixgbe_msix_other interrupt is triggering
2638 * consistently (as it would when PPS is turned on for the X540 device)
2639 */
2640 eicr &= 0xFFFF0000;
2641
54037505 2642 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2643
cf8280ee
JB		 2644 if (eicr & IXGBE_EICR_LSC)
2645 ixgbe_check_lsc(adapter);
f0848276 2646
1cdd1ec8
GR		 2647 if (eicr & IXGBE_EICR_MAILBOX)
2648 ixgbe_msg_task(adapter);
efe3d3c8 2649
bd508178
AD		 2650 switch (hw->mac.type) {
2651 case ixgbe_mac_82599EB:
b93a2226 2652 case ixgbe_mac_X540:
9a75a1ac
DS		 2653 case ixgbe_mac_X550:
2654 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2655 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2656 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2657 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2658 ixgbe_service_event_schedule(adapter);
2659 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2660 IXGBE_EICR_GPI_SDP0_X540);
2661 }
d773ce2d
DS		 2662 if (eicr & IXGBE_EICR_ECC) {
2663 e_info(link, "Received ECC Err, initiating reset\n");
2664 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2665 ixgbe_service_event_schedule(adapter);
2666 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2667 }
c4cf55e5
PWJ		 2668 /* Handle Flow Director Full threshold interrupt */
2669 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2670 int reinit_count = 0;
c4cf55e5 2671 int i;
c4cf55e5 2672 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2673 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2674 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2675 &ring->state))
2676 reinit_count++;
2677 }
2678 if (reinit_count) {
2679 /* no more flow director interrupts until after init */
2680 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2681 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2682 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2683 }
2684 }
f0f9778d 2685 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2686 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2687 break;
2688 default:
2689 break;
c4cf55e5 2690 }
f0848276 2691
bd508178 2692 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2693
db0677fa
JK		 2694 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2695 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2696
7086400d 2697 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2698 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2699 ixgbe_irq_enable(adapter, false, false);
f0848276 2700
9a799d71 2701 return IRQ_HANDLED;
f0848276 2702}
91281fd3 2703
4ff7fb12 2704static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2705{
021230d4 2706 struct ixgbe_q_vector *q_vector = data;
91281fd3 2707
9b471446 2708 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2709
4ff7fb12
AD		 2710 if (q_vector->rx.ring || q_vector->tx.ring)
2711 napi_schedule(&q_vector->napi);
91281fd3 2712
9a799d71 2713 return IRQ_HANDLED;
91281fd3
AD		 2714}
2715
eb01b975
AD		 2716/**
2717 * ixgbe_poll - NAPI Rx polling callback
2718 * @napi: structure for representing this polling device
2719 * @budget: how many packets driver is allowed to clean
2720 *
2721 * This function is used for legacy and MSI, NAPI mode
2722 **/
8af3c33f 2723int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2724{
2725 struct ixgbe_q_vector *q_vector =
2726 container_of(napi, struct ixgbe_q_vector, napi);
2727 struct ixgbe_adapter *adapter = q_vector->adapter;
2728 struct ixgbe_ring *ring;
2729 int per_ring_budget;
2730 bool clean_complete = true;
2731
2732#ifdef CONFIG_IXGBE_DCA
2733 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2734 ixgbe_update_dca(q_vector);
2735#endif
2736
2737 ixgbe_for_each_ring(ring, q_vector->tx)
2738 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2739
5a85e737
ET		 2740 if (!ixgbe_qv_lock_napi(q_vector))
2741 return budget;
2742
eb01b975
AD		 2743 /* attempt to distribute budget to each queue fairly, but don't allow
2744 * the budget to go below 1 because we'll exit polling */
2745 if (q_vector->rx.count > 1)
2746 per_ring_budget = max(budget/q_vector->rx.count, 1);
2747 else
2748 per_ring_budget = budget;
2749
2750 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2751 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2752 per_ring_budget) < per_ring_budget);
eb01b975 2753
5a85e737 2754 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2755 /* If all work not completed, return budget and keep polling */
2756 if (!clean_complete)
2757 return budget;
2758
2759 /* all work done, exit the polling mode */
2760 napi_complete(napi);
2761 if (adapter->rx_itr_setting & 1)
2762 ixgbe_set_itr(q_vector);
2763 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2764 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2765
2766 return 0;
2767}
2768
021230d4
AV		 2769/**
2770 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2771 * @adapter: board private structure
2772 *
2773 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2774 * interrupts from the kernel.
2775 **/
2776static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2777{
2778 struct net_device *netdev = adapter->netdev;
207867f5 2779 int vector, err;
e8e9f696 2780 int ri = 0, ti = 0;
021230d4 2781
49c7ffbe 2782 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2783 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2784 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2785
4ff7fb12 2786 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2787 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2788 "%s-%s-%d", netdev->name, "TxRx", ri++);
2789 ti++;
2790 } else if (q_vector->rx.ring) {
9fe93afd 2791 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2792 "%s-%s-%d", netdev->name, "rx", ri++);
2793 } else if (q_vector->tx.ring) {
9fe93afd 2794 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2795 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2796 } else {
2797 /* skip this unused q_vector */
2798 continue;
32aa77a4 2799 }
207867f5
AD		 2800 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2801 q_vector->name, q_vector);
9a799d71 2802 if (err) {
396e799c 2803 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2804 "Error: %d\n", err);
021230d4 2805 goto free_queue_irqs;
9a799d71 2806 }
207867f5
AD		 2807 /* If Flow Director is enabled, set interrupt affinity */
2808 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2809 /* assign the mask for this irq */
2810 irq_set_affinity_hint(entry->vector,
de88eeeb 2811 &q_vector->affinity_mask);
207867f5 2812 }
9a799d71
AK		 2813 }
2814
021230d4 2815 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2816 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2817 if (err) {
de88eeeb 2818 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2819 goto free_queue_irqs;
9a799d71
AK		 2820 }
2821
9a799d71
AK		 2822 return 0;
2823
021230d4 2824free_queue_irqs:
207867f5
AD		 2825 while (vector) {
2826 vector--;
2827 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2828 NULL);
2829 free_irq(adapter->msix_entries[vector].vector,
2830 adapter->q_vector[vector]);
2831 }
021230d4
AV		 2832 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2833 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2834 kfree(adapter->msix_entries);
2835 adapter->msix_entries = NULL;
9a799d71
AK		 2836 return err;
2837}
2838
2839/**
021230d4 2840 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2841 * @irq: interrupt number
2842 * @data: pointer to a network interface device structure
9a799d71
AK		 2843 **/
2844static irqreturn_t ixgbe_intr(int irq, void *data)
2845{
a65151ba 2846 struct ixgbe_adapter *adapter = data;
9a799d71 2847 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2848 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2849 u32 eicr;
2850
54037505 2851 /*
24ddd967 2852 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2853 * before the read of EICR.
2854 */
2855 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2856
021230d4 2857 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2858 * therefore no explicit interrupt disable is necessary */
021230d4 2859 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2860 if (!eicr) {
6af3b9eb
ET		 2861 /*
2862 * shared interrupt alert!
f47cf66e 2863 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2864 * have disabled interrupts due to EIAM
2865 * finish the workaround of silicon errata on 82598. Unmask
2866 * the interrupt that we masked before the EICR read.
2867 */
2868 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2869 ixgbe_irq_enable(adapter, true, true);
9a799d71 2870 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2871 }
9a799d71 2872
cf8280ee
JB		 2873 if (eicr & IXGBE_EICR_LSC)
2874 ixgbe_check_lsc(adapter);
021230d4 2875
bd508178
AD		 2876 switch (hw->mac.type) {
2877 case ixgbe_mac_82599EB:
e8e26350 2878 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2879 /* Fall through */
2880 case ixgbe_mac_X540:
9a75a1ac
DS		 2881 case ixgbe_mac_X550:
2882 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2883 if (eicr & IXGBE_EICR_ECC) {
2884 e_info(link, "Received ECC Err, initiating reset\n");
2885 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2886 ixgbe_service_event_schedule(adapter);
2887 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2888 }
4f51bf70 2889 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2890 break;
2891 default:
2892 break;
2893 }
e8e26350 2894
0befdb3e 2895 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2896 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2897 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2898
b9f6ed2b
AD		 2899 /* would disable interrupts here but EIAM disabled it */
2900 napi_schedule(&q_vector->napi);
9a799d71 2901
6af3b9eb
ET		 2902 /*
2903 * re-enable link(maybe) and non-queue interrupts, no flush.
2904 * ixgbe_poll will re-enable the queue interrupts
2905 */
6af3b9eb
ET		 2906 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2907 ixgbe_irq_enable(adapter, false, false);
2908
9a799d71
AK		 2909 return IRQ_HANDLED;
2910}
2911
2912/**
2913 * ixgbe_request_irq - initialize interrupts
2914 * @adapter: board private structure
2915 *
2916 * Attempts to configure interrupts using the best available
2917 * capabilities of the hardware and kernel.
2918 **/
021230d4 2919static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2920{
2921 struct net_device *netdev = adapter->netdev;
021230d4 2922 int err;
9a799d71 2923
4cc6df29 2924 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2925 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2926 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2927 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2928 netdev->name, adapter);
4cc6df29 2929 else
a0607fd3 2930 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2931 netdev->name, adapter);
9a799d71 2932
de88eeeb 2933 if (err)
396e799c 2934 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2935
9a799d71
AK		 2936 return err;
2937}
2938
2939static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2940{
49c7ffbe 2941 int vector;
9a799d71 2942
49c7ffbe
AD		 2943 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2944 free_irq(adapter->pdev->irq, adapter);
2945 return;
2946 }
4cc6df29 2947
49c7ffbe
AD		 2948 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2949 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2950 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2951
49c7ffbe
AD		 2952 /* free only the irqs that were actually requested */
2953 if (!q_vector->rx.ring && !q_vector->tx.ring)
2954 continue;
207867f5 2955
49c7ffbe
AD		 2956 /* clear the affinity_mask in the IRQ descriptor */
2957 irq_set_affinity_hint(entry->vector, NULL);
2958
2959 free_irq(entry->vector, q_vector);
9a799d71 2960 }
49c7ffbe
AD		 2961
2962 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2963}
2964
22d5a71b
JB		 2965/**
2966 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2967 * @adapter: board private structure
2968 **/
2969static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2970{
bd508178
AD		 2971 switch (adapter->hw.mac.type) {
2972 case ixgbe_mac_82598EB:
835462fc 2973 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2974 break;
2975 case ixgbe_mac_82599EB:
b93a2226 2976 case ixgbe_mac_X540:
9a75a1ac
DS		 2977 case ixgbe_mac_X550:
2978 case ixgbe_mac_X550EM_x:
835462fc
NS		 2979 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2980 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2981 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2982 break;
2983 default:
2984 break;
22d5a71b
JB		 2985 }
2986 IXGBE_WRITE_FLUSH(&adapter->hw);
2987 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2988 int vector;
2989
2990 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2991 synchronize_irq(adapter->msix_entries[vector].vector);
2992
2993 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2994 } else {
2995 synchronize_irq(adapter->pdev->irq);
2996 }
2997}
2998
9a799d71
AK		 2999/**
3000 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3001 *
3002 **/
3003static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3004{
d5bf4f67 3005 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3006
d5bf4f67 3007 ixgbe_write_eitr(q_vector);
9a799d71 3008
e8e26350
PW		 3009 ixgbe_set_ivar(adapter, 0, 0, 0);
3010 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3011
396e799c 3012 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3013}
3014
43e69bf0
AD		 3015/**
3016 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3017 * @adapter: board private structure
3018 * @ring: structure containing ring specific data
3019 *
3020 * Configure the Tx descriptor ring after a reset.
3021 **/
84418e3b
AD		 3022void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3023 struct ixgbe_ring *ring)
43e69bf0
AD		 3024{
3025 struct ixgbe_hw *hw = &adapter->hw;
3026 u64 tdba = ring->dma;
2f1860b8 3027 int wait_loop = 10;
b88c6de2 3028 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3029 u8 reg_idx = ring->reg_idx;
43e69bf0 3030
2f1860b8 3031 /* disable queue to avoid issues while updating state */
b88c6de2 3032 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3033 IXGBE_WRITE_FLUSH(hw);
3034
43e69bf0 3035 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3036 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3037 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3038 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3039 ring->count * sizeof(union ixgbe_adv_tx_desc));
3040 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3041 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3042 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3043
b88c6de2
AD		 3044 /*
3045 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3046 * higher than 1 when:
3047 * - ITR is 0 as it could cause false TX hangs
3048 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3049 *
3050 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3051 * to or less than the number of on chip descriptors, which is
3052 * currently 40.
3053 */
67da097e 3054 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3055 txdctl |= (1 << 16); /* WTHRESH = 1 */
3056 else
3057 txdctl |= (8 << 16); /* WTHRESH = 8 */
3058
e954b374
AD		 3059 /*
3060 * Setting PTHRESH to 32 both improves performance
3061 * and avoids a TX hang with DFP enabled
3062 */
b88c6de2
AD		 3063 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3064 32; /* PTHRESH = 32 */
2f1860b8
AD		 3065
3066 /* reinitialize flowdirector state */
39cb681b 3067 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3068 ring->atr_sample_rate = adapter->atr_sample_rate;
3069 ring->atr_count = 0;
3070 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3071 } else {
3072 ring->atr_sample_rate = 0;
3073 }
2f1860b8 3074
fd786b7b
AD		 3075 /* initialize XPS */
3076 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3077 struct ixgbe_q_vector *q_vector = ring->q_vector;
3078
3079 if (q_vector)
2a47fa45 3080 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3081 &q_vector->affinity_mask,
3082 ring->queue_index);
3083 }
3084
c84d324c
JF		 3085 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3086
2f1860b8 3087 /* enable queue */
2f1860b8
AD		 3088 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3089
3090 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3091 if (hw->mac.type == ixgbe_mac_82598EB &&
3092 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3093 return;
3094
3095 /* poll to verify queue is enabled */
3096 do {
032b4325 3097 usleep_range(1000, 2000);
2f1860b8
AD		 3098 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3099 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3100 if (!wait_loop)
3101 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3102}
3103
120ff942
AD		 3104static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3105{
3106 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3107 u32 rttdcs, mtqc;
8b1c0b24 3108 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3109
3110 if (hw->mac.type == ixgbe_mac_82598EB)
3111 return;
3112
3113 /* disable the arbiter while setting MTQC */
3114 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3115 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3116 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3117
3118 /* set transmit pool layout */
671c0adb
AD		 3119 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3120 mtqc = IXGBE_MTQC_VT_ENA;
3121 if (tcs > 4)
3122 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3123 else if (tcs > 1)
3124 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3125 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3126 mtqc |= IXGBE_MTQC_32VF;
3127 else
3128 mtqc |= IXGBE_MTQC_64VF;
3129 } else {
3130 if (tcs > 4)
3131 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3132 else if (tcs > 1)
3133 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3134 else
671c0adb
AD		 3135 mtqc = IXGBE_MTQC_64Q_1PB;
3136 }
120ff942 3137
671c0adb 3138 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3139
671c0adb
AD		 3140 /* Enable Security TX Buffer IFG for multiple pb */
3141 if (tcs) {
3142 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3143 sectx |= IXGBE_SECTX_DCB;
3144 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3145 }
3146
3147 /* re-enable the arbiter */
3148 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3149 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3150}
3151
9a799d71 3152/**
3a581073 3153 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3154 * @adapter: board private structure
3155 *
3156 * Configure the Tx unit of the MAC after a reset.
3157 **/
3158static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3159{
2f1860b8
AD		 3160 struct ixgbe_hw *hw = &adapter->hw;
3161 u32 dmatxctl;
43e69bf0 3162 u32 i;
9a799d71 3163
2f1860b8
AD		 3164 ixgbe_setup_mtqc(adapter);
3165
3166 if (hw->mac.type != ixgbe_mac_82598EB) {
3167 /* DMATXCTL.EN must be before Tx queues are enabled */
3168 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3169 dmatxctl |= IXGBE_DMATXCTL_TE;
3170 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3171 }
3172
9a799d71 3173 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3174 for (i = 0; i < adapter->num_tx_queues; i++)
3175 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3176}
3177
3ebe8fde
AD		 3178static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3179 struct ixgbe_ring *ring)
3180{
3181 struct ixgbe_hw *hw = &adapter->hw;
3182 u8 reg_idx = ring->reg_idx;
3183 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3184
3185 srrctl |= IXGBE_SRRCTL_DROP_EN;
3186
3187 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3188}
3189
3190static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3191 struct ixgbe_ring *ring)
3192{
3193 struct ixgbe_hw *hw = &adapter->hw;
3194 u8 reg_idx = ring->reg_idx;
3195 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3196
3197 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3198
3199 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3200}
3201
3202#ifdef CONFIG_IXGBE_DCB
3203void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3204#else
3205static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3206#endif
3207{
3208 int i;
3209 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3210
3211 if (adapter->ixgbe_ieee_pfc)
3212 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3213
3214 /*
3215 * We should set the drop enable bit if:
3216 * SR-IOV is enabled
3217 * or
3218 * Number of Rx queues > 1 and flow control is disabled
3219 *
3220 * This allows us to avoid head of line blocking for security
3221 * and performance reasons.
3222 */
3223 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3224 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3225 for (i = 0; i < adapter->num_rx_queues; i++)
3226 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3227 } else {
3228 for (i = 0; i < adapter->num_rx_queues; i++)
3229 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3230 }
3231}
3232
e8e26350 3233#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3234
a6616b42 3235static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3236 struct ixgbe_ring *rx_ring)
cc41ac7c 3237{
45e9baa5 3238 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3239 u32 srrctl;
bf29ee6c 3240 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3241
45e9baa5
AD		 3242 if (hw->mac.type == ixgbe_mac_82598EB) {
3243 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3244
45e9baa5
AD		 3245 /*
3246 * if VMDq is not active we must program one srrctl register
3247 * per RSS queue since we have enabled RDRXCTL.MVMEN
3248 */
3249 reg_idx &= mask;
3250 }
cc41ac7c 3251
45e9baa5
AD		 3252 /* configure header buffer length, needed for RSC */
3253 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3254
45e9baa5 3255 /* configure the packet buffer length */
f800326d 3256 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3257
3258 /* configure descriptor type */
f800326d 3259 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3260
45e9baa5 3261 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3262}
9a799d71 3263
dfaf891d
VZ		 3264/**
3265 * Return a number of entries in the RSS indirection table
3266 *
3267 * @adapter: device handle
3268 *
3269 * - 82598/82599/X540: 128
3270 * - X550(non-SRIOV mode): 512
3271 * - X550(SRIOV mode): 64
3272 */
7f276efb 3273u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3274{
3275 if (adapter->hw.mac.type < ixgbe_mac_X550)
3276 return 128;
3277 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3278 return 64;
3279 else
3280 return 512;
3281}
3282
3283/**
3284 * Write the RETA table to HW
3285 *
3286 * @adapter: device handle
3287 *
3288 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3289 */
3290static void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3291{
dfaf891d 3292 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3293 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3294 u32 reta = 0;
dfaf891d
VZ		 3295 u32 indices_multi;
3296 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3297
0f9b232b 3298 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3299 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3300 * indices.
3301 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3302 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3303 */
3304 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3305 indices_multi = 0x11;
3306 else
3307 indices_multi = 0x1;
3308
dfaf891d
VZ		 3309 /* Write redirection table to HW */
3310 for (i = 0; i < reta_entries; i++) {
3311 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3312 if ((i & 3) == 3) {
3313 if (i < 128)
3314 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3315 else
3316 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3317 reta);
dfaf891d 3318 reta = 0;
0f9b232b
DS		 3319 }
3320 }
3321}
3322
dfaf891d
VZ		 3323/**
3324 * Write the RETA table to HW (for x550 devices in SRIOV mode)
3325 *
3326 * @adapter: device handle
3327 *
3328 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3329 */
3330static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3331{
dfaf891d 3332 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3333 struct ixgbe_hw *hw = &adapter->hw;
3334 u32 vfreta = 0;
dfaf891d
VZ		 3335 unsigned int pf_pool = adapter->num_vfs;
3336
3337 /* Write redirection table to HW */
3338 for (i = 0; i < reta_entries; i++) {
3339 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3340 if ((i & 3) == 3) {
3341 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3342 vfreta);
3343 vfreta = 0;
3344 }
3345 }
3346}
3347
3348static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3349{
3350 struct ixgbe_hw *hw = &adapter->hw;
3351 u32 i, j;
3352 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3353 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3354
3355 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3356 * make full use of any rings they may have. We will use the
3357 * PSRTYPE register to control how many rings we use within the PF.
3358 */
3359 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3360 rss_i = 2;
3361
3362 /* Fill out hash function seeds */
3363 for (i = 0; i < 10; i++)
3364 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3365
3366 /* Fill out redirection table */
3367 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3368
3369 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3370 if (j == rss_i)
3371 j = 0;
3372
3373 adapter->rss_indir_tbl[i] = j;
3374 }
3375
3376 ixgbe_store_reta(adapter);
3377}
3378
3379static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3380{
3381 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3382 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3383 unsigned int pf_pool = adapter->num_vfs;
3384 int i, j;
3385
3386 /* Fill out hash function seeds */
3387 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3388 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3389 adapter->rss_key[i]);
0f9b232b
DS		 3390
3391 /* Fill out the redirection table */
3392 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3393 if (j == rss_i)
05abb126 3394 j = 0;
dfaf891d
VZ		 3395
3396 adapter->rss_indir_tbl[i] = j;
05abb126 3397 }
dfaf891d
VZ		 3398
3399 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3400}
3401
3402static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3403{
3404 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3405 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3406 u32 rxcsum;
0cefafad 3407
05abb126
AD		 3408 /* Disable indicating checksum in descriptor, enables RSS hash */
3409 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3410 rxcsum |= IXGBE_RXCSUM_PCSD;
3411 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3412
671c0adb 3413 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3414 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3415 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3416 } else {
671c0adb
AD		 3417 u8 tcs = netdev_get_num_tc(adapter->netdev);
3418
3419 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3420 if (tcs > 4)
3421 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3422 else if (tcs > 1)
3423 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3424 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3425 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3426 else
671c0adb
AD		 3427 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3428 } else {
3429 if (tcs > 4)
8b1c0b24 3430 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3431 else if (tcs > 1)
3432 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3433 else
3434 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3435 }
0cefafad
JB		 3436 }
3437
05abb126 3438 /* Perform hash on these packet types */
d1b849b9
DS		 3439 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3440 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3441 IXGBE_MRQC_RSS_FIELD_IPV6 |
3442 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3443
ef6afc0c 3444 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3445 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3446 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3447 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3448
dfaf891d 3449 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3450 if ((hw->mac.type >= ixgbe_mac_X550) &&
3451 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3452 unsigned int pf_pool = adapter->num_vfs;
3453
3454 /* Enable VF RSS mode */
3455 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3456 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3457
3458 /* Setup RSS through the VF registers */
dfaf891d 3459 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3460 vfmrqc = IXGBE_MRQC_RSSEN;
3461 vfmrqc |= rss_field;
3462 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3463 } else {
dfaf891d 3464 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3465 mrqc |= rss_field;
3466 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3467 }
0cefafad
JB		 3468}
3469
bb5a9ad2
NS		 3470/**
3471 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3472 * @adapter: address of board private structure
3473 * @index: index of ring to set
bb5a9ad2 3474 **/
082757af 3475static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3476 struct ixgbe_ring *ring)
bb5a9ad2 3477{
bb5a9ad2 3478 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3479 u32 rscctrl;
bf29ee6c 3480 u8 reg_idx = ring->reg_idx;
7367096a 3481
7d637bcc 3482 if (!ring_is_rsc_enabled(ring))
7367096a 3483 return;
bb5a9ad2 3484
7367096a 3485 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3486 rscctrl |= IXGBE_RSCCTL_RSCEN;
3487 /*
3488 * we must limit the number of descriptors so that the
3489 * total size of max desc * buf_len is not greater
642c680e 3490 * than 65536
bb5a9ad2 3491 */
f800326d 3492 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3493 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3494}
3495
9e10e045
AD		 3496#define IXGBE_MAX_RX_DESC_POLL 10
3497static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3498 struct ixgbe_ring *ring)
3499{
3500 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3501 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3502 u32 rxdctl;
bf29ee6c 3503 u8 reg_idx = ring->reg_idx;
9e10e045 3504
b0483c8f
MR		 3505 if (ixgbe_removed(hw->hw_addr))
3506 return;
9e10e045
AD		 3507 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3508 if (hw->mac.type == ixgbe_mac_82598EB &&
3509 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3510 return;
3511
3512 do {
032b4325 3513 usleep_range(1000, 2000);
9e10e045
AD		 3514 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3515 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3516
3517 if (!wait_loop) {
3518 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3519 "the polling period\n", reg_idx);
3520 }
3521}
3522
2d39d576
YZ		 3523void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3524 struct ixgbe_ring *ring)
3525{
3526 struct ixgbe_hw *hw = &adapter->hw;
3527 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3528 u32 rxdctl;
3529 u8 reg_idx = ring->reg_idx;
3530
b0483c8f
MR		 3531 if (ixgbe_removed(hw->hw_addr))
3532 return;
2d39d576
YZ		 3533 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3534 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3535
3536 /* write value back with RXDCTL.ENABLE bit cleared */
3537 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3538
3539 if (hw->mac.type == ixgbe_mac_82598EB &&
3540 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3541 return;
3542
3543 /* the hardware may take up to 100us to really disable the rx queue */
3544 do {
3545 udelay(10);
3546 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3547 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3548
3549 if (!wait_loop) {
3550 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3551 "the polling period\n", reg_idx);
3552 }
3553}
3554
84418e3b
AD		 3555void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3556 struct ixgbe_ring *ring)
acd37177
AD		 3557{
3558 struct ixgbe_hw *hw = &adapter->hw;
3559 u64 rdba = ring->dma;
9e10e045 3560 u32 rxdctl;
bf29ee6c 3561 u8 reg_idx = ring->reg_idx;
acd37177 3562
9e10e045
AD		 3563 /* disable queue to avoid issues while updating state */
3564 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3565 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3566
acd37177
AD		 3567 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3568 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3569 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3570 ring->count * sizeof(union ixgbe_adv_rx_desc));
3571 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3572 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3573 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3574
3575 ixgbe_configure_srrctl(adapter, ring);
3576 ixgbe_configure_rscctl(adapter, ring);
3577
3578 if (hw->mac.type == ixgbe_mac_82598EB) {
3579 /*
3580 * enable cache line friendly hardware writes:
3581 * PTHRESH=32 descriptors (half the internal cache),
3582 * this also removes ugly rx_no_buffer_count increment
3583 * HTHRESH=4 descriptors (to minimize latency on fetch)
3584 * WTHRESH=8 burst writeback up to two cache lines
3585 */
3586 rxdctl &= ~0x3FFFFF;
3587 rxdctl |= 0x080420;
3588 }
3589
3590 /* enable receive descriptor ring */
3591 rxdctl |= IXGBE_RXDCTL_ENABLE;
3592 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3593
3594 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3595 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3596}
3597
48654521
AD		 3598static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3599{
3600 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3601 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3602 u16 pool;
48654521
AD		 3603
3604 /* PSRTYPE must be initialized in non 82598 adapters */
3605 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3606 IXGBE_PSRTYPE_UDPHDR |
3607 IXGBE_PSRTYPE_IPV4HDR |
48654521 3608 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3609 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3610
3611 if (hw->mac.type == ixgbe_mac_82598EB)
3612 return;
3613
fbe7ca7f
AD		 3614 if (rss_i > 3)
3615 psrtype |= 2 << 29;
3616 else if (rss_i > 1)
3617 psrtype |= 1 << 29;
48654521 3618
2a47fa45
JF		 3619 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3620 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3621}
3622
f5b4a52e
AD		 3623static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3624{
3625 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3626 u32 reg_offset, vf_shift;
435b19f6 3627 u32 gcr_ext, vmdctl;
de4c7f65 3628 int i;
f5b4a52e
AD		 3629
3630 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3631 return;
3632
3633 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3634 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3635 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3636 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3637 vmdctl |= IXGBE_VT_CTL_REPLEN;
3638 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3639
1d9c0bfd
AD		 3640 vf_shift = VMDQ_P(0) % 32;
3641 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3642
3643 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3644 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3645 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3646 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3647 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3648 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3649 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3650
3651 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3652 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3653
3654 /*
3655 * Set up VF register offsets for selected VT Mode,
3656 * i.e. 32 or 64 VFs for SR-IOV
3657 */
73079ea0
AD		 3658 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3659 case IXGBE_82599_VMDQ_8Q_MASK:
3660 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3661 break;
3662 case IXGBE_82599_VMDQ_4Q_MASK:
3663 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3664 break;
3665 default:
3666 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3667 break;
3668 }
3669
f5b4a52e
AD		 3670 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3671
435b19f6 3672
a985b6c3 3673 /* Enable MAC Anti-Spoofing */
435b19f6 3674 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3675 adapter->num_vfs);
5b7f000f
DS		 3676
3677 /* Ensure LLDP is set for Ethertype Antispoofing if we will be
3678 * calling set_ethertype_anti_spoofing for each VF in loop below
3679 */
3680 if (hw->mac.ops.set_ethertype_anti_spoofing)
3681 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3682 (IXGBE_ETQF_FILTER_EN | /* enable filter */
3683 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */
3684 IXGBE_ETH_P_LLDP)); /* LLDP eth type */
3685
de4c7f65
GR		 3686 /* For VFs that have spoof checking turned off */
3687 for (i = 0; i < adapter->num_vfs; i++) {
3688 if (!adapter->vfinfo[i].spoofchk_enabled)
3689 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3690
3691 /* enable ethertype anti spoofing if hw supports it */
3692 if (hw->mac.ops.set_ethertype_anti_spoofing)
3693 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
e65ce0d3
VZ		 3694
3695 /* Enable/Disable RSS query feature */
3696 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3697 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3698 }
f5b4a52e
AD		 3699}
3700
477de6ed 3701static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3702{
9a799d71
AK		 3703 struct ixgbe_hw *hw = &adapter->hw;
3704 struct net_device *netdev = adapter->netdev;
3705 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3706 struct ixgbe_ring *rx_ring;
3707 int i;
3708 u32 mhadd, hlreg0;
48654521 3709
63f39bd1 3710#ifdef IXGBE_FCOE
477de6ed
AD		 3711 /* adjust max frame to be able to do baby jumbo for FCoE */
3712 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3713 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3714 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3715
477de6ed 3716#endif /* IXGBE_FCOE */
872844dd
AD		 3717
3718 /* adjust max frame to be at least the size of a standard frame */
3719 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3720 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3721
477de6ed
AD		 3722 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3723 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3724 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3725 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3726
3727 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3728 }
3729
3730 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3731 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3732 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3733 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3734
0cefafad
JB		 3735 /*
3736 * Setup the HW Rx Head and Tail Descriptor Pointers and
3737 * the Base and Length of the Rx Descriptor Ring
3738 */
9a799d71 3739 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3740 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3741 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3742 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3743 else
7d637bcc 3744 clear_ring_rsc_enabled(rx_ring);
477de6ed 3745 }
477de6ed
AD		 3746}
3747
7367096a
AD		 3748static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3749{
3750 struct ixgbe_hw *hw = &adapter->hw;
3751 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3752
3753 switch (hw->mac.type) {
9a75a1ac
DS		 3754 case ixgbe_mac_X550:
3755 case ixgbe_mac_X550EM_x:
7367096a
AD		 3756 case ixgbe_mac_82598EB:
3757 /*
3758 * For VMDq support of different descriptor types or
3759 * buffer sizes through the use of multiple SRRCTL
3760 * registers, RDRXCTL.MVMEN must be set to 1
3761 *
3762 * also, the manual doesn't mention it clearly but DCA hints
3763 * will only use queue 0's tags unless this bit is set. Side
3764 * effects of setting this bit are only that SRRCTL must be
3765 * fully programmed [0..15]
3766 */
3767 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3768 break;
3769 case ixgbe_mac_82599EB:
b93a2226 3770 case ixgbe_mac_X540:
7367096a
AD		 3771 /* Disable RSC for ACK packets */
3772 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3773 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3774 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3775 /* hardware requires some bits to be set by default */
3776 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3777 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3778 break;
3779 default:
3780 /* We should do nothing since we don't know this hardware */
3781 return;
3782 }
3783
3784 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3785}
3786
477de6ed
AD		 3787/**
3788 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3789 * @adapter: board private structure
3790 *
3791 * Configure the Rx unit of the MAC after a reset.
3792 **/
3793static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3794{
3795 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3796 int i;
6dcc28b9 3797 u32 rxctrl, rfctl;
477de6ed
AD		 3798
3799 /* disable receives while setting up the descriptors */
1f9ac57c 3800 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3801
3802 ixgbe_setup_psrtype(adapter);
7367096a 3803 ixgbe_setup_rdrxctl(adapter);
477de6ed 3804
6dcc28b9
JK		 3805 /* RSC Setup */
3806 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3807 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3808 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3809 rfctl |= IXGBE_RFCTL_RSC_DIS;
3810 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3811
9e10e045 3812 /* Program registers for the distribution of queues */
f5b4a52e 3813 ixgbe_setup_mrqc(adapter);
f5b4a52e 3814
477de6ed
AD		 3815 /* set_rx_buffer_len must be called before ring initialization */
3816 ixgbe_set_rx_buffer_len(adapter);
3817
3818 /*
3819 * Setup the HW Rx Head and Tail Descriptor Pointers and
3820 * the Base and Length of the Rx Descriptor Ring
3821 */
9e10e045
AD		 3822 for (i = 0; i < adapter->num_rx_queues; i++)
3823 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3824
1f9ac57c 3825 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3826 /* disable drop enable for 82598 parts */
3827 if (hw->mac.type == ixgbe_mac_82598EB)
3828 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3829
3830 /* enable all receives */
3831 rxctrl |= IXGBE_RXCTRL_RXEN;
3832 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3833}
3834
80d5c368
PM		 3835static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3836 __be16 proto, u16 vid)
068c89b0
DS		 3837{
3838 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3839 struct ixgbe_hw *hw = &adapter->hw;
3840
3841 /* add VID to filter table */
1d9c0bfd 3842 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3843 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3844
3845 return 0;
068c89b0
DS		 3846}
3847
80d5c368
PM		 3848static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3849 __be16 proto, u16 vid)
068c89b0
DS		 3850{
3851 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3852 struct ixgbe_hw *hw = &adapter->hw;
3853
068c89b0 3854 /* remove VID from filter table */
1d9c0bfd 3855 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3856 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3857
3858 return 0;
068c89b0
DS		 3859}
3860
f62bbb5e
JG		 3861/**
3862 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3863 * @adapter: driver data
3864 */
3865static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3866{
3867 struct ixgbe_hw *hw = &adapter->hw;
3868 u32 vlnctrl;
5f6c0181
JB		 3869 int i, j;
3870
3871 switch (hw->mac.type) {
3872 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3873 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3874 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3875 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3876 break;
3877 case ixgbe_mac_82599EB:
b93a2226 3878 case ixgbe_mac_X540:
9a75a1ac
DS		 3879 case ixgbe_mac_X550:
3880 case ixgbe_mac_X550EM_x:
5f6c0181 3881 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3882 struct ixgbe_ring *ring = adapter->rx_ring[i];
3883
3884 if (ring->l2_accel_priv)
3885 continue;
3886 j = ring->reg_idx;
5f6c0181
JB		 3887 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3888 vlnctrl &= ~IXGBE_RXDCTL_VME;
3889 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3890 }
3891 break;
3892 default:
3893 break;
3894 }
3895}
3896
3897/**
f62bbb5e 3898 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3899 * @adapter: driver data
3900 */
f62bbb5e 3901static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3902{
3903 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3904 u32 vlnctrl;
5f6c0181
JB		 3905 int i, j;
3906
3907 switch (hw->mac.type) {
3908 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3909 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3910 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3911 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3912 break;
3913 case ixgbe_mac_82599EB:
b93a2226 3914 case ixgbe_mac_X540:
9a75a1ac
DS		 3915 case ixgbe_mac_X550:
3916 case ixgbe_mac_X550EM_x:
5f6c0181 3917 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3918 struct ixgbe_ring *ring = adapter->rx_ring[i];
3919
3920 if (ring->l2_accel_priv)
3921 continue;
3922 j = ring->reg_idx;
5f6c0181
JB		 3923 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3924 vlnctrl |= IXGBE_RXDCTL_VME;
3925 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3926 }
3927 break;
3928 default:
3929 break;
3930 }
3931}
3932
9a799d71
AK		 3933static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3934{
f62bbb5e 3935 u16 vid;
9a799d71 3936
80d5c368 3937 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3938
3939 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3940 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3941}
3942
b335e75b
JK		 3943/**
3944 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3945 * @netdev: network interface device structure
3946 *
3947 * Writes multicast address list to the MTA hash table.
3948 * Returns: -ENOMEM on failure
3949 * 0 on no addresses written
3950 * X on writing X addresses to MTA
3951 **/
3952static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3953{
3954 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3955 struct ixgbe_hw *hw = &adapter->hw;
3956
3957 if (!netif_running(netdev))
3958 return 0;
3959
3960 if (hw->mac.ops.update_mc_addr_list)
3961 hw->mac.ops.update_mc_addr_list(hw, netdev);
3962 else
3963 return -ENOMEM;
3964
3965#ifdef CONFIG_PCI_IOV
5d7daa35 3966 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 3967#endif
3968
3969 return netdev_mc_count(netdev);
3970}
3971
5d7daa35
JK		 3972#ifdef CONFIG_PCI_IOV
3973void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3974{
3975 struct ixgbe_hw *hw = &adapter->hw;
3976 int i;
3977 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3978 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3979 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3980 adapter->mac_table[i].queue,
3981 IXGBE_RAH_AV);
3982 else
3983 hw->mac.ops.clear_rar(hw, i);
3984
3985 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3986 }
3987}
3988#endif
3989
3990static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3991{
3992 struct ixgbe_hw *hw = &adapter->hw;
3993 int i;
3994 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3995 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3996 if (adapter->mac_table[i].state &
3997 IXGBE_MAC_STATE_IN_USE)
3998 hw->mac.ops.set_rar(hw, i,
3999 adapter->mac_table[i].addr,
4000 adapter->mac_table[i].queue,
4001 IXGBE_RAH_AV);
4002 else
4003 hw->mac.ops.clear_rar(hw, i);
4004
4005 adapter->mac_table[i].state &=
4006 ~(IXGBE_MAC_STATE_MODIFIED);
4007 }
4008 }
4009}
4010
4011static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4012{
4013 int i;
4014 struct ixgbe_hw *hw = &adapter->hw;
4015
4016 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4017 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4018 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4019 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4020 adapter->mac_table[i].queue = 0;
4021 }
4022 ixgbe_sync_mac_table(adapter);
4023}
4024
4025static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
4026{
4027 struct ixgbe_hw *hw = &adapter->hw;
4028 int i, count = 0;
4029
4030 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4031 if (adapter->mac_table[i].state == 0)
4032 count++;
4033 }
4034 return count;
4035}
4036
4037/* this function destroys the first RAR entry */
4038static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
4039 u8 *addr)
4040{
4041 struct ixgbe_hw *hw = &adapter->hw;
4042
4043 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
4044 adapter->mac_table[0].queue = VMDQ_P(0);
4045 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
4046 IXGBE_MAC_STATE_IN_USE);
4047 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
4048 adapter->mac_table[0].queue,
4049 IXGBE_RAH_AV);
4050}
4051
4052int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4053{
4054 struct ixgbe_hw *hw = &adapter->hw;
4055 int i;
4056
4057 if (is_zero_ether_addr(addr))
4058 return -EINVAL;
4059
4060 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4061 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4062 continue;
4063 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
4064 IXGBE_MAC_STATE_IN_USE);
4065 ether_addr_copy(adapter->mac_table[i].addr, addr);
4066 adapter->mac_table[i].queue = queue;
4067 ixgbe_sync_mac_table(adapter);
4068 return i;
4069 }
4070 return -ENOMEM;
4071}
4072
4073int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4074{
4075 /* search table for addr, if found, set to 0 and sync */
4076 int i;
4077 struct ixgbe_hw *hw = &adapter->hw;
4078
4079 if (is_zero_ether_addr(addr))
4080 return -EINVAL;
4081
4082 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4083 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
4084 adapter->mac_table[i].queue == queue) {
4085 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4086 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4087 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4088 adapter->mac_table[i].queue = 0;
4089 ixgbe_sync_mac_table(adapter);
4090 return 0;
4091 }
4092 }
4093 return -ENOMEM;
4094}
2850062a
AD		 4095/**
4096 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4097 * @netdev: network interface device structure
4098 *
4099 * Writes unicast address list to the RAR table.
4100 * Returns: -ENOMEM on failure/insufficient address space
4101 * 0 on no addresses written
4102 * X on writing X addresses to the RAR table
4103 **/
5d7daa35 4104static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4105{
4106 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4107 int count = 0;
4108
4109 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 4110 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 4111 return -ENOMEM;
4112
95447461 4113 if (!netdev_uc_empty(netdev)) {
2850062a 4114 struct netdev_hw_addr *ha;
2850062a 4115 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4116 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4117 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4118 count++;
4119 }
4120 }
2850062a
AD		 4121 return count;
4122}
4123
9a799d71 4124/**
2c5645cf 4125 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4126 * @netdev: network interface device structure
4127 *
2c5645cf
CL		 4128 * The set_rx_method entry point is called whenever the unicast/multicast
4129 * address list or the network interface flags are updated. This routine is
4130 * responsible for configuring the hardware for proper unicast, multicast and
4131 * promiscuous mode.
9a799d71 4132 **/
7f870475 4133void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4134{
4135 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4136 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4137 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 4138 u32 vlnctrl;
2850062a 4139 int count;
9a799d71
AK		 4140
4141 /* Check for Promiscuous and All Multicast modes */
9a799d71 4142 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 4143 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 4144
f5dc442b 4145 /* set all bits that we expect to always be set */
3f2d1c0f 4146 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4147 fctrl |= IXGBE_FCTRL_BAM;
4148 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4149 fctrl |= IXGBE_FCTRL_PMCF;
4150
2850062a
AD		 4151 /* clear the bits we are changing the status of */
4152 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 4153 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4154 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4155 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4156 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4157 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 4158 /* Only disable hardware filter vlans in promiscuous mode
4159 * if SR-IOV and VMDQ are disabled - otherwise ensure
4160 * that hardware VLAN filters remain enabled.
4161 */
4556dc59
VY		 4162 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4163 IXGBE_FLAG_SRIOV_ENABLED))
a9b8943e 4164 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4165 } else {
746b9f02
PM		 4166 if (netdev->flags & IFF_ALLMULTI) {
4167 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4168 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4169 }
a9b8943e 4170 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 4171 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4172 }
4173
4174 /*
4175 * Write addresses to available RAR registers, if there is not
4176 * sufficient space to store all the addresses then enable
4177 * unicast promiscuous mode
4178 */
5d7daa35 4179 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 4180 if (count < 0) {
4181 fctrl |= IXGBE_FCTRL_UPE;
4182 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4183 }
4184
cf78959c
ET		 4185 /* Write addresses to the MTA, if the attempt fails
4186 * then we should just turn on promiscuous mode so
4187 * that we can at least receive multicast traffic
4188 */
b335e75b
JK		 4189 count = ixgbe_write_mc_addr_list(netdev);
4190 if (count < 0) {
4191 fctrl |= IXGBE_FCTRL_MPE;
4192 vmolr |= IXGBE_VMOLR_MPE;
4193 } else if (count) {
4194 vmolr |= IXGBE_VMOLR_ROMPE;
4195 }
1d9c0bfd
AD		 4196
4197 if (hw->mac.type != ixgbe_mac_82598EB) {
4198 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4199 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4200 IXGBE_VMOLR_ROPE);
1d9c0bfd 4201 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4202 }
4203
3f2d1c0f
BG		 4204 /* This is useful for sniffing bad packets. */
4205 if (adapter->netdev->features & NETIF_F_RXALL) {
4206 /* UPE and MPE will be handled by normal PROMISC logic
4207 * in e1000e_set_rx_mode */
4208 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4209 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4210 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4211
4212 fctrl &= ~(IXGBE_FCTRL_DPF);
4213 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4214 }
4215
a9b8943e 4216 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4217 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4218
f646968f 4219 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4220 ixgbe_vlan_strip_enable(adapter);
4221 else
4222 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4223}
4224
021230d4
AV		 4225static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4226{
4227 int q_idx;
021230d4 4228
5a85e737
ET		 4229 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4230 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4231 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4232 }
021230d4
AV		 4233}
4234
4235static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4236{
4237 int q_idx;
021230d4 4238
5a85e737 4239 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4240 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4241 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4242 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4243 usleep_range(1000, 20000);
5a85e737
ET		 4244 }
4245 }
021230d4
AV		 4246}
4247
7a6b6f51 4248#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4249/**
2f90b865
AD		 4250 * ixgbe_configure_dcb - Configure DCB hardware
4251 * @adapter: ixgbe adapter struct
4252 *
4253 * This is called by the driver on open to configure the DCB hardware.
4254 * This is also called by the gennetlink interface when reconfiguring
4255 * the DCB state.
4256 */
4257static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4258{
4259 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4260 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4261
67ebd791
AD		 4262 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4263 if (hw->mac.type == ixgbe_mac_82598EB)
4264 netif_set_gso_max_size(adapter->netdev, 65536);
4265 return;
4266 }
4267
4268 if (hw->mac.type == ixgbe_mac_82598EB)
4269 netif_set_gso_max_size(adapter->netdev, 32768);
4270
971060b1 4271#ifdef IXGBE_FCOE
b120818e
JF		 4272 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4273 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4274#endif
b120818e
JF		 4275
4276 /* reconfigure the hardware */
4277 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4278 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4279 DCB_TX_CONFIG);
4280 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4281 DCB_RX_CONFIG);
4282 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4283 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4284 ixgbe_dcb_hw_ets(&adapter->hw,
4285 adapter->ixgbe_ieee_ets,
4286 max_frame);
4287 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4288 adapter->ixgbe_ieee_pfc->pfc_en,
4289 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4290 }
8187cd48
JF		 4291
4292 /* Enable RSS Hash per TC */
4293 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4294 u32 msb = 0;
4295 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4296
d411a936
AD		 4297 while (rss_i) {
4298 msb++;
4299 rss_i >>= 1;
4300 }
8187cd48 4301
4ae63730
AD		 4302 /* write msb to all 8 TCs in one write */
4303 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4304 }
2f90b865 4305}
9da712d2
JF		 4306#endif
4307
4308/* Additional bittime to account for IXGBE framing */
4309#define IXGBE_ETH_FRAMING 20
4310
49ce9c2c 4311/**
9da712d2
JF		 4312 * ixgbe_hpbthresh - calculate high water mark for flow control
4313 *
4314 * @adapter: board private structure to calculate for
49ce9c2c 4315 * @pb: packet buffer to calculate
9da712d2
JF		 4316 */
4317static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4318{
4319 struct ixgbe_hw *hw = &adapter->hw;
4320 struct net_device *dev = adapter->netdev;
4321 int link, tc, kb, marker;
4322 u32 dv_id, rx_pba;
4323
4324 /* Calculate max LAN frame size */
4325 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4326
4327#ifdef IXGBE_FCOE
4328 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4329 if ((dev->features & NETIF_F_FCOE_MTU) &&
4330 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4331 (pb == ixgbe_fcoe_get_tc(adapter)))
4332 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4333#endif
e5776620 4334
9da712d2
JF		 4335 /* Calculate delay value for device */
4336 switch (hw->mac.type) {
4337 case ixgbe_mac_X540:
9a75a1ac
DS		 4338 case ixgbe_mac_X550:
4339 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4340 dv_id = IXGBE_DV_X540(link, tc);
4341 break;
4342 default:
4343 dv_id = IXGBE_DV(link, tc);
4344 break;
4345 }
4346
4347 /* Loopback switch introduces additional latency */
4348 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4349 dv_id += IXGBE_B2BT(tc);
4350
4351 /* Delay value is calculated in bit times convert to KB */
4352 kb = IXGBE_BT2KB(dv_id);
4353 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4354
4355 marker = rx_pba - kb;
4356
4357 /* It is possible that the packet buffer is not large enough
4358 * to provide required headroom. In this case throw an error
4359 * to user and a do the best we can.
4360 */
4361 if (marker < 0) {
4362 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4363 "headroom to support flow control."
4364 "Decrease MTU or number of traffic classes\n", pb);
4365 marker = tc + 1;
4366 }
4367
4368 return marker;
4369}
4370
49ce9c2c 4371/**
9da712d2
JF		 4372 * ixgbe_lpbthresh - calculate low water mark for for flow control
4373 *
4374 * @adapter: board private structure to calculate for
49ce9c2c 4375 * @pb: packet buffer to calculate
9da712d2 4376 */
e5776620 4377static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4378{
4379 struct ixgbe_hw *hw = &adapter->hw;
4380 struct net_device *dev = adapter->netdev;
4381 int tc;
4382 u32 dv_id;
4383
4384 /* Calculate max LAN frame size */
4385 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4386
e5776620
JK		 4387#ifdef IXGBE_FCOE
4388 /* FCoE traffic class uses FCOE jumbo frames */
4389 if ((dev->features & NETIF_F_FCOE_MTU) &&
4390 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4391 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4392 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4393#endif
4394
9da712d2
JF		 4395 /* Calculate delay value for device */
4396 switch (hw->mac.type) {
4397 case ixgbe_mac_X540:
9a75a1ac
DS		 4398 case ixgbe_mac_X550:
4399 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4400 dv_id = IXGBE_LOW_DV_X540(tc);
4401 break;
4402 default:
4403 dv_id = IXGBE_LOW_DV(tc);
4404 break;
4405 }
4406
4407 /* Delay value is calculated in bit times convert to KB */
4408 return IXGBE_BT2KB(dv_id);
4409}
4410
4411/*
4412 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4413 */
4414static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4415{
4416 struct ixgbe_hw *hw = &adapter->hw;
4417 int num_tc = netdev_get_num_tc(adapter->netdev);
4418 int i;
4419
4420 if (!num_tc)
4421 num_tc = 1;
4422
9da712d2
JF		 4423 for (i = 0; i < num_tc; i++) {
4424 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4425 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4426
4427 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4428 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4429 hw->fc.low_water[i] = 0;
9da712d2 4430 }
e5776620
JK		 4431
4432 for (; i < MAX_TRAFFIC_CLASS; i++)
4433 hw->fc.high_water[i] = 0;
9da712d2
JF		 4434}
4435
80605c65
JF		 4436static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4437{
80605c65 4438 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4439 int hdrm;
4440 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4441
4442 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4443 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4444 hdrm = 32 << adapter->fdir_pballoc;
4445 else
4446 hdrm = 0;
80605c65 4447
f7e1027f 4448 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4449 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4450}
4451
e4911d57
AD		 4452static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4453{
4454 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4455 struct hlist_node *node2;
e4911d57
AD		 4456 struct ixgbe_fdir_filter *filter;
4457
4458 spin_lock(&adapter->fdir_perfect_lock);
4459
4460 if (!hlist_empty(&adapter->fdir_filter_list))
4461 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4462
b67bfe0d 4463 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4464 &adapter->fdir_filter_list, fdir_node) {
4465 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4466 &filter->filter,
4467 filter->sw_idx,
4468 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4469 IXGBE_FDIR_DROP_QUEUE :
4470 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4471 }
4472
4473 spin_unlock(&adapter->fdir_perfect_lock);
4474}
4475
2a47fa45
JF		 4476static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4477 struct ixgbe_adapter *adapter)
4478{
4479 struct ixgbe_hw *hw = &adapter->hw;
4480 u32 vmolr;
4481
4482 /* No unicast promiscuous support for VMDQ devices. */
4483 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4484 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4485
4486 /* clear the affected bit */
4487 vmolr &= ~IXGBE_VMOLR_MPE;
4488
4489 if (dev->flags & IFF_ALLMULTI) {
4490 vmolr |= IXGBE_VMOLR_MPE;
4491 } else {
4492 vmolr |= IXGBE_VMOLR_ROMPE;
4493 hw->mac.ops.update_mc_addr_list(hw, dev);
4494 }
5d7daa35 4495 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4496 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4497}
4498
2a47fa45
JF		 4499static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4500{
4501 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4502 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4503 struct ixgbe_hw *hw = &adapter->hw;
4504 u16 pool = vadapter->pool;
4505 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4506 IXGBE_PSRTYPE_UDPHDR |
4507 IXGBE_PSRTYPE_IPV4HDR |
4508 IXGBE_PSRTYPE_L2HDR |
4509 IXGBE_PSRTYPE_IPV6HDR;
4510
4511 if (hw->mac.type == ixgbe_mac_82598EB)
4512 return;
4513
4514 if (rss_i > 3)
4515 psrtype |= 2 << 29;
4516 else if (rss_i > 1)
4517 psrtype |= 1 << 29;
4518
4519 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4520}
4521
4522/**
4523 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4524 * @rx_ring: ring to free buffers from
4525 **/
4526static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4527{
4528 struct device *dev = rx_ring->dev;
4529 unsigned long size;
4530 u16 i;
4531
4532 /* ring already cleared, nothing to do */
4533 if (!rx_ring->rx_buffer_info)
4534 return;
4535
4536 /* Free all the Rx ring sk_buffs */
4537 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4538 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4539
2a47fa45
JF		 4540 if (rx_buffer->skb) {
4541 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4542 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4543 dma_unmap_page(dev,
4544 IXGBE_CB(skb)->dma,
4545 ixgbe_rx_bufsz(rx_ring),
4546 DMA_FROM_DEVICE);
2a47fa45 4547 dev_kfree_skb(skb);
4d2fcfbc 4548 rx_buffer->skb = NULL;
2a47fa45 4549 }
18cb652a
AD		 4550
4551 if (!rx_buffer->page)
4552 continue;
4553
4554 dma_unmap_page(dev, rx_buffer->dma,
4555 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4556 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4557
2a47fa45
JF		 4558 rx_buffer->page = NULL;
4559 }
4560
4561 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4562 memset(rx_ring->rx_buffer_info, 0, size);
4563
4564 /* Zero out the descriptor ring */
4565 memset(rx_ring->desc, 0, rx_ring->size);
4566
4567 rx_ring->next_to_alloc = 0;
4568 rx_ring->next_to_clean = 0;
4569 rx_ring->next_to_use = 0;
4570}
4571
4572static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4573 struct ixgbe_ring *rx_ring)
4574{
4575 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4576 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4577
4578 /* shutdown specific queue receive and wait for dma to settle */
4579 ixgbe_disable_rx_queue(adapter, rx_ring);
4580 usleep_range(10000, 20000);
4581 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4582 ixgbe_clean_rx_ring(rx_ring);
4583 rx_ring->l2_accel_priv = NULL;
4584}
4585
ae72c8d0
JF		 4586static int ixgbe_fwd_ring_down(struct net_device *vdev,
4587 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4588{
4589 struct ixgbe_adapter *adapter = accel->real_adapter;
4590 unsigned int rxbase = accel->rx_base_queue;
4591 unsigned int txbase = accel->tx_base_queue;
4592 int i;
4593
4594 netif_tx_stop_all_queues(vdev);
4595
4596 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4597 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4598 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4599 }
4600
4601 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4602 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4603 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4604 }
4605
4606
4607 return 0;
4608}
4609
4610static int ixgbe_fwd_ring_up(struct net_device *vdev,
4611 struct ixgbe_fwd_adapter *accel)
4612{
4613 struct ixgbe_adapter *adapter = accel->real_adapter;
4614 unsigned int rxbase, txbase, queues;
4615 int i, baseq, err = 0;
4616
4617 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4618 return 0;
4619
4620 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4621 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4622 accel->pool, adapter->num_rx_pools,
4623 baseq, baseq + adapter->num_rx_queues_per_pool,
4624 adapter->fwd_bitmask);
4625
4626 accel->netdev = vdev;
4627 accel->rx_base_queue = rxbase = baseq;
4628 accel->tx_base_queue = txbase = baseq;
4629
4630 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4631 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4632
4633 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4634 adapter->rx_ring[rxbase + i]->netdev = vdev;
4635 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4636 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4637 }
4638
4639 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4640 adapter->tx_ring[txbase + i]->netdev = vdev;
4641 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4642 }
4643
4644 queues = min_t(unsigned int,
4645 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4646 err = netif_set_real_num_tx_queues(vdev, queues);
4647 if (err)
4648 goto fwd_queue_err;
4649
2a47fa45
JF		 4650 err = netif_set_real_num_rx_queues(vdev, queues);
4651 if (err)
4652 goto fwd_queue_err;
4653
4654 if (is_valid_ether_addr(vdev->dev_addr))
4655 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4656
4657 ixgbe_fwd_psrtype(accel);
4658 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4659 return err;
4660fwd_queue_err:
4661 ixgbe_fwd_ring_down(vdev, accel);
4662 return err;
4663}
4664
4665static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4666{
4667 struct net_device *upper;
4668 struct list_head *iter;
4669 int err;
4670
4671 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4672 if (netif_is_macvlan(upper)) {
4673 struct macvlan_dev *dfwd = netdev_priv(upper);
4674 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4675
4676 if (dfwd->fwd_priv) {
4677 err = ixgbe_fwd_ring_up(upper, vadapter);
4678 if (err)
4679 continue;
4680 }
4681 }
4682 }
4683}
4684
9a799d71
AK		 4685static void ixgbe_configure(struct ixgbe_adapter *adapter)
4686{
d2f5e7f3
AS		 4687 struct ixgbe_hw *hw = &adapter->hw;
4688
80605c65 4689 ixgbe_configure_pb(adapter);
7a6b6f51 4690#ifdef CONFIG_IXGBE_DCB
67ebd791 4691 ixgbe_configure_dcb(adapter);
2f90b865 4692#endif
b35d4d42
AD		 4693 /*
4694 * We must restore virtualization before VLANs or else
4695 * the VLVF registers will not be populated
4696 */
4697 ixgbe_configure_virtualization(adapter);
9a799d71 4698
4c1d7b4b 4699 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4700 ixgbe_restore_vlan(adapter);
4701
d2f5e7f3
AS		 4702 switch (hw->mac.type) {
4703 case ixgbe_mac_82599EB:
4704 case ixgbe_mac_X540:
4705 hw->mac.ops.disable_rx_buff(hw);
4706 break;
4707 default:
4708 break;
4709 }
4710
c4cf55e5 4711 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4712 ixgbe_init_fdir_signature_82599(&adapter->hw,
4713 adapter->fdir_pballoc);
e4911d57
AD		 4714 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4715 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4716 adapter->fdir_pballoc);
4717 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4718 }
4c1d7b4b 4719
d2f5e7f3
AS		 4720 switch (hw->mac.type) {
4721 case ixgbe_mac_82599EB:
4722 case ixgbe_mac_X540:
4723 hw->mac.ops.enable_rx_buff(hw);
4724 break;
4725 default:
4726 break;
4727 }
4728
7c8ae65a
AD		 4729#ifdef IXGBE_FCOE
4730 /* configure FCoE L2 filters, redirection table, and Rx control */
4731 ixgbe_configure_fcoe(adapter);
4732
4733#endif /* IXGBE_FCOE */
9a799d71
AK		 4734 ixgbe_configure_tx(adapter);
4735 ixgbe_configure_rx(adapter);
2a47fa45 4736 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4737}
4738
0ecc061d 4739/**
e8e26350
PW		 4740 * ixgbe_sfp_link_config - set up SFP+ link
4741 * @adapter: pointer to private adapter struct
4742 **/
4743static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4744{
7086400d 4745 /*
52f33af8 4746 * We are assuming the worst case scenario here, and that
7086400d
AD		 4747 * is that an SFP was inserted/removed after the reset
4748 * but before SFP detection was enabled. As such the best
4749 * solution is to just start searching as soon as we start
4750 */
4751 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4752 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4753
7086400d 4754 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4755}
4756
4757/**
4758 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4759 * @hw: pointer to private hardware struct
4760 *
4761 * Returns 0 on success, negative on failure
4762 **/
e8e26350 4763static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4764{
3d292265
JH		 4765 u32 speed;
4766 bool autoneg, link_up = false;
a1e869de 4767 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 4768
4769 if (hw->mac.ops.check_link)
3d292265 4770 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4771
4772 if (ret)
e90dd264 4773 return ret;
0ecc061d 4774
3d292265
JH		 4775 speed = hw->phy.autoneg_advertised;
4776 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4777 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4778 &autoneg);
0ecc061d 4779 if (ret)
e90dd264 4780 return ret;
0ecc061d 4781
8620a103 4782 if (hw->mac.ops.setup_link)
fd0326f2 4783 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4784
0ecc061d
PWJ		 4785 return ret;
4786}
4787
a34bcfff 4788static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4789{
9a799d71 4790 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4791 u32 gpie = 0;
9a799d71 4792
9b471446 4793 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4794 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4795 IXGBE_GPIE_OCD;
4796 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4797 /*
4798 * use EIAM to auto-mask when MSI-X interrupt is asserted
4799 * this saves a register write for every interrupt
4800 */
4801 switch (hw->mac.type) {
4802 case ixgbe_mac_82598EB:
4803 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4804 break;
9b471446 4805 case ixgbe_mac_82599EB:
b93a2226 4806 case ixgbe_mac_X540:
9a75a1ac
DS		 4807 case ixgbe_mac_X550:
4808 case ixgbe_mac_X550EM_x:
b93a2226 4809 default:
9b471446
JB		 4810 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4811 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4812 break;
4813 }
4814 } else {
021230d4
AV		 4815 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4816 * specifically only auto mask tx and rx interrupts */
4817 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4818 }
9a799d71 4819
a34bcfff
AD		 4820 /* XXX: to interrupt immediately for EICS writes, enable this */
4821 /* gpie |= IXGBE_GPIE_EIMEN; */
4822
4823 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4824 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4825
4826 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4827 case IXGBE_82599_VMDQ_8Q_MASK:
4828 gpie |= IXGBE_GPIE_VTMODE_16;
4829 break;
4830 case IXGBE_82599_VMDQ_4Q_MASK:
4831 gpie |= IXGBE_GPIE_VTMODE_32;
4832 break;
4833 default:
4834 gpie |= IXGBE_GPIE_VTMODE_64;
4835 break;
4836 }
119fc60a
MC		 4837 }
4838
5fdd31f9 4839 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4840 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4841 switch (adapter->hw.mac.type) {
4842 case ixgbe_mac_82599EB:
9a900eca 4843 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec
DS		 4844 break;
4845 case ixgbe_mac_X540:
4846 gpie |= IXGBE_EIMS_TS;
4847 break;
4848 default:
4849 break;
4850 }
4851 }
5fdd31f9 4852
a34bcfff
AD		 4853 /* Enable fan failure interrupt */
4854 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 4855 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 4856
2698b208 4857 if (hw->mac.type == ixgbe_mac_82599EB) {
9a900eca
DS		 4858 gpie |= IXGBE_SDP1_GPIEN_8259X;
4859 gpie |= IXGBE_SDP2_GPIEN_8259X;
2698b208 4860 }
a34bcfff
AD		 4861
4862 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4863}
4864
c7ccde0f 4865static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4866{
4867 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4868 int err;
a34bcfff
AD		 4869 u32 ctrl_ext;
4870
4871 ixgbe_get_hw_control(adapter);
4872 ixgbe_setup_gpie(adapter);
e8e26350 4873
9a799d71
AK		 4874 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4875 ixgbe_configure_msix(adapter);
4876 else
4877 ixgbe_configure_msi_and_legacy(adapter);
4878
ec74a471
ET		 4879 /* enable the optics for 82599 SFP+ fiber */
4880 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4881 hw->mac.ops.enable_tx_laser(hw);
4882
961fac88
DS		 4883 if (hw->phy.ops.set_phy_power)
4884 hw->phy.ops.set_phy_power(hw, true);
4885
4e857c58 4886 smp_mb__before_atomic();
9a799d71 4887 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4888 ixgbe_napi_enable_all(adapter);
4889
73c4b7cd
AD		 4890 if (ixgbe_is_sfp(hw)) {
4891 ixgbe_sfp_link_config(adapter);
4892 } else {
4893 err = ixgbe_non_sfp_link_config(hw);
4894 if (err)
4895 e_err(probe, "link_config FAILED %d\n", err);
4896 }
4897
021230d4
AV		 4898 /* clear any pending interrupts, may auto mask */
4899 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4900 ixgbe_irq_enable(adapter, true, true);
9a799d71 4901
bf069c97
DS		 4902 /*
4903 * If this adapter has a fan, check to see if we had a failure
4904 * before we enabled the interrupt.
4905 */
4906 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4907 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4908 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4909 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4910 }
4911
9a799d71
AK		 4912 /* bring the link up in the watchdog, this could race with our first
4913 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4914 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4915 adapter->link_check_timeout = jiffies;
7086400d 4916 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4917
4918 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4919 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4920 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4921 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4922}
4923
d4f80882
AV		 4924void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4925{
4926 WARN_ON(in_interrupt());
7086400d
AD		 4927 /* put off any impending NetWatchDogTimeout */
4928 adapter->netdev->trans_start = jiffies;
4929
d4f80882 4930 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4931 usleep_range(1000, 2000);
d4f80882 4932 ixgbe_down(adapter);
5809a1ae
GR		 4933 /*
4934 * If SR-IOV enabled then wait a bit before bringing the adapter
4935 * back up to give the VFs time to respond to the reset. The
4936 * two second wait is based upon the watchdog timer cycle in
4937 * the VF driver.
4938 */
4939 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4940 msleep(2000);
d4f80882
AV		 4941 ixgbe_up(adapter);
4942 clear_bit(__IXGBE_RESETTING, &adapter->state);
4943}
4944
c7ccde0f 4945void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4946{
4947 /* hardware has been reset, we need to reload some things */
4948 ixgbe_configure(adapter);
4949
c7ccde0f 4950 ixgbe_up_complete(adapter);
9a799d71
AK		 4951}
4952
4953void ixgbe_reset(struct ixgbe_adapter *adapter)
4954{
c44ade9e 4955 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 4956 struct net_device *netdev = adapter->netdev;
8ca783ab 4957 int err;
5d7daa35 4958 u8 old_addr[ETH_ALEN];
8ca783ab 4959
b0483c8f
MR		 4960 if (ixgbe_removed(hw->hw_addr))
4961 return;
7086400d
AD		 4962 /* lock SFP init bit to prevent race conditions with the watchdog */
4963 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4964 usleep_range(1000, 2000);
4965
4966 /* clear all SFP and link config related flags while holding SFP_INIT */
4967 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4968 IXGBE_FLAG2_SFP_NEEDS_RESET);
4969 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4970
8ca783ab 4971 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4972 switch (err) {
4973 case 0:
4974 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4975 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4976 break;
4977 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4978 e_dev_err("master disable timed out\n");
da4dd0f7 4979 break;
794caeb2
PWJ		 4980 case IXGBE_ERR_EEPROM_VERSION:
4981 /* We are running on a pre-production device, log a warning */
849c4542 4982 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4983 "Please be aware there may be issues associated with "
849c4542
ET		 4984 "your hardware. If you are experiencing problems "
4985 "please contact your Intel or hardware "
4986 "representative who provided you with this "
4987 "hardware.\n");
794caeb2 4988 break;
da4dd0f7 4989 default:
849c4542 4990 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4991 }
9a799d71 4992
7086400d 4993 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 4994 /* do not flush user set addresses */
4995 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4996 ixgbe_flush_sw_mac_table(adapter);
4997 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 4998
4999 /* update SAN MAC vmdq pool selection */
5000 if (hw->mac.san_mac_rar_index)
5001 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5002
8fecf67c 5003 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5004 ixgbe_ptp_reset(adapter);
961fac88
DS		 5005
5006 if (hw->phy.ops.set_phy_power) {
5007 if (!netif_running(adapter->netdev) && !adapter->wol)
5008 hw->phy.ops.set_phy_power(hw, false);
5009 else
5010 hw->phy.ops.set_phy_power(hw, true);
5011 }
9a799d71
AK		 5012}
5013
9a799d71
AK		 5014/**
5015 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5016 * @tx_ring: ring to be cleaned
5017 **/
b6ec895e 5018static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5019{
5020 struct ixgbe_tx_buffer *tx_buffer_info;
5021 unsigned long size;
b6ec895e 5022 u16 i;
9a799d71 5023
84418e3b
AD		 5024 /* ring already cleared, nothing to do */
5025 if (!tx_ring->tx_buffer_info)
5026 return;
9a799d71 5027
84418e3b 5028 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5029 for (i = 0; i < tx_ring->count; i++) {
5030 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5031 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5032 }
5033
dad8a3b3
JF		 5034 netdev_tx_reset_queue(txring_txq(tx_ring));
5035
9a799d71
AK		 5036 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5037 memset(tx_ring->tx_buffer_info, 0, size);
5038
5039 /* Zero out the descriptor ring */
5040 memset(tx_ring->desc, 0, tx_ring->size);
5041
5042 tx_ring->next_to_use = 0;
5043 tx_ring->next_to_clean = 0;
9a799d71
AK		 5044}
5045
5046/**
021230d4 5047 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5048 * @adapter: board private structure
5049 **/
021230d4 5050static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5051{
5052 int i;
5053
021230d4 5054 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5055 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5056}
5057
5058/**
021230d4 5059 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5060 * @adapter: board private structure
5061 **/
021230d4 5062static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5063{
5064 int i;
5065
021230d4 5066 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5067 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5068}
5069
e4911d57
AD		 5070static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5071{
b67bfe0d 5072 struct hlist_node *node2;
e4911d57
AD		 5073 struct ixgbe_fdir_filter *filter;
5074
5075 spin_lock(&adapter->fdir_perfect_lock);
5076
b67bfe0d 5077 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5078 &adapter->fdir_filter_list, fdir_node) {
5079 hlist_del(&filter->fdir_node);
5080 kfree(filter);
5081 }
5082 adapter->fdir_filter_count = 0;
5083
5084 spin_unlock(&adapter->fdir_perfect_lock);
5085}
5086
9a799d71
AK		 5087void ixgbe_down(struct ixgbe_adapter *adapter)
5088{
5089 struct net_device *netdev = adapter->netdev;
7f821875 5090 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5091 struct net_device *upper;
5092 struct list_head *iter;
bf29ee6c 5093 int i;
9a799d71
AK		 5094
5095 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5096 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5097 return; /* do nothing if already down */
9a799d71
AK		 5098
5099 /* disable receives */
1f9ac57c 5100 hw->mac.ops.disable_rx(hw);
9a799d71 5101
2d39d576
YZ		 5102 /* disable all enabled rx queues */
5103 for (i = 0; i < adapter->num_rx_queues; i++)
5104 /* this call also flushes the previous write */
5105 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5106
032b4325 5107 usleep_range(10000, 20000);
9a799d71 5108
7f821875
JB		 5109 netif_tx_stop_all_queues(netdev);
5110
7086400d 5111 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5112 netif_carrier_off(netdev);
5113 netif_tx_disable(netdev);
5114
2a47fa45
JF		 5115 /* disable any upper devices */
5116 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5117 if (netif_is_macvlan(upper)) {
5118 struct macvlan_dev *vlan = netdev_priv(upper);
5119
5120 if (vlan->fwd_priv) {
5121 netif_tx_stop_all_queues(upper);
5122 netif_carrier_off(upper);
5123 netif_tx_disable(upper);
5124 }
5125 }
5126 }
5127
c0dfb90e
JF		 5128 ixgbe_irq_disable(adapter);
5129
5130 ixgbe_napi_disable_all(adapter);
5131
d034acf1
AD		 5132 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5133 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5134 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5135
5136 del_timer_sync(&adapter->service_timer);
5137
34cecbbf 5138 if (adapter->num_vfs) {
8e34d1aa
AD		 5139 /* Clear EITR Select mapping */
5140 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5141
5142 /* Mark all the VFs as inactive */
5143 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5144 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5145
34cecbbf
AD		 5146 /* ping all the active vfs to let them know we are going down */
5147 ixgbe_ping_all_vfs(adapter);
5148
5149 /* Disable all VFTE/VFRE TX/RX */
5150 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5151 }
5152
7f821875
JB		 5153 /* disable transmits in the hardware now that interrupts are off */
5154 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5155 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5156 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5157 }
34cecbbf 5158
9a75a1ac 5159 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5160 switch (hw->mac.type) {
5161 case ixgbe_mac_82599EB:
b93a2226 5162 case ixgbe_mac_X540:
9a75a1ac
DS		 5163 case ixgbe_mac_X550:
5164 case ixgbe_mac_X550EM_x:
88512539 5165 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5166 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5167 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5168 break;
5169 default:
5170 break;
5171 }
7f821875 5172
6f4a0e45
PL		 5173 if (!pci_channel_offline(adapter->pdev))
5174 ixgbe_reset(adapter);
c6ecf39a 5175
ec74a471
ET		 5176 /* power down the optics for 82599 SFP+ fiber */
5177 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5178 hw->mac.ops.disable_tx_laser(hw);
5179
9a799d71
AK		 5180 ixgbe_clean_all_tx_rings(adapter);
5181 ixgbe_clean_all_rx_rings(adapter);
5182
5dd2d332 5183#ifdef CONFIG_IXGBE_DCA
96b0e0f6 5184 /* since we reset the hardware DCA settings were cleared */
e35ec126 5185 ixgbe_setup_dca(adapter);
96b0e0f6 5186#endif
9a799d71
AK		 5187}
5188
9a799d71
AK		 5189/**
5190 * ixgbe_tx_timeout - Respond to a Tx Hang
5191 * @netdev: network interface device structure
5192 **/
5193static void ixgbe_tx_timeout(struct net_device *netdev)
5194{
5195 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5196
5197 /* Do the reset outside of interrupt context */
c83c6cbd 5198 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5199}
5200
9a799d71
AK		 5201/**
5202 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5203 * @adapter: board private structure to initialize
5204 *
5205 * ixgbe_sw_init initializes the Adapter private data structure.
5206 * Fields are initialized based on PCI device information and
5207 * OS network device settings (MTU size).
5208 **/
9f9a12f8 5209static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5210{
5211 struct ixgbe_hw *hw = &adapter->hw;
5212 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5213 unsigned int rss, fdir;
cb6d0f5e 5214 u32 fwsm;
7a6b6f51 5215#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5216 int j;
5217 struct tc_configuration *tc;
5218#endif
021230d4 5219
c44ade9e
JB		 5220 /* PCI config space info */
5221
5222 hw->vendor_id = pdev->vendor;
5223 hw->device_id = pdev->device;
5224 hw->revision_id = pdev->revision;
5225 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5226 hw->subsystem_device_id = pdev->subsystem_device;
5227
8fc3bb6d 5228 /* Set common capability flags and settings */
0f9b232b 5229 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5230 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5231 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5232 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5233 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5234 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5235 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5236 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5237 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5238#ifdef CONFIG_IXGBE_DCA
5239 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5240#endif
5241#ifdef IXGBE_FCOE
5242 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5243 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5244#ifdef CONFIG_IXGBE_DCB
5245 /* Default traffic class to use for FCoE */
5246 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5247#endif /* CONFIG_IXGBE_DCB */
5248#endif /* IXGBE_FCOE */
5249
5d7daa35
JK		 5250 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5251 hw->mac.num_rar_entries,
5252 GFP_ATOMIC);
5253
8fc3bb6d 5254 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5255 switch (hw->mac.type) {
5256 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5257 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5258 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5259
bf069c97
DS		 5260 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5261 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5262
49c7ffbe 5263 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5264 adapter->ring_feature[RING_F_FDIR].limit = 0;
5265 adapter->atr_sample_rate = 0;
5266 adapter->fdir_pballoc = 0;
5267#ifdef IXGBE_FCOE
5268 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5269 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5270#ifdef CONFIG_IXGBE_DCB
5271 adapter->fcoe.up = 0;
5272#endif /* IXGBE_DCB */
5273#endif /* IXGBE_FCOE */
5274 break;
5275 case ixgbe_mac_82599EB:
5276 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5277 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5278 break;
b93a2226 5279 case ixgbe_mac_X540:
9a900eca 5280 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5281 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5282 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5283 break;
9a75a1ac
DS		 5284 case ixgbe_mac_X550EM_x:
5285 case ixgbe_mac_X550:
5286#ifdef CONFIG_IXGBE_DCA
5287 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5288#endif
5289 break;
bd508178
AD		 5290 default:
5291 break;
f8212f97 5292 }
2f90b865 5293
7c8ae65a
AD		 5294#ifdef IXGBE_FCOE
5295 /* FCoE support exists, always init the FCoE lock */
5296 spin_lock_init(&adapter->fcoe.lock);
5297
5298#endif
1fc5f038
AD		 5299 /* n-tuple support exists, always init our spinlock */
5300 spin_lock_init(&adapter->fdir_perfect_lock);
5301
7a6b6f51 5302#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5303 switch (hw->mac.type) {
5304 case ixgbe_mac_X540:
9a75a1ac
DS		 5305 case ixgbe_mac_X550:
5306 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5307 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5308 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5309 break;
5310 default:
5311 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5312 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5313 break;
5314 }
5315
2f90b865
AD		 5316 /* Configure DCB traffic classes */
5317 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5318 tc = &adapter->dcb_cfg.tc_config[j];
5319 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5320 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5321 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5322 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5323 tc->dcb_pfc = pfc_disabled;
5324 }
4de2a022
JF		 5325
5326 /* Initialize default user to priority mapping, UPx->TC0 */
5327 tc = &adapter->dcb_cfg.tc_config[0];
5328 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5329 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5330
2f90b865
AD		 5331 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5332 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5333 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5334 adapter->dcb_set_bitmap = 0x00;
3032309b 5335 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5336 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5337 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5338
5339#endif
9a799d71
AK		 5340
5341 /* default flow control settings */
cd7664f6 5342 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5343 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5344 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5345 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5346 hw->fc.send_xon = true;
73d80953 5347 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5348
99d74487 5349#ifdef CONFIG_PCI_IOV
170e8543
JK		 5350 if (max_vfs > 0)
5351 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5352
99d74487 5353 /* assign number of SR-IOV VFs */
170e8543 5354 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5355 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5356 adapter->num_vfs = 0;
5357 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5358 } else {
5359 adapter->num_vfs = max_vfs;
5360 }
5361 }
5362#endif /* CONFIG_PCI_IOV */
99d74487 5363
30efa5a3 5364 /* enable itr by default in dynamic mode */
f7554a2b 5365 adapter->rx_itr_setting = 1;
f7554a2b 5366 adapter->tx_itr_setting = 1;
30efa5a3 5367
30efa5a3
JB		 5368 /* set default ring sizes */
5369 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5370 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5371
bd198058 5372 /* set default work limits */
59224555 5373 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5374
9a799d71 5375 /* initialize eeprom parameters */
c44ade9e 5376 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5377 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5378 return -EIO;
5379 }
5380
2a47fa45
JF		 5381 /* PF holds first pool slot */
5382 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5383 set_bit(__IXGBE_DOWN, &adapter->state);
5384
5385 return 0;
5386}
5387
5388/**
5389 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5390 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5391 *
5392 * Return 0 on success, negative on failure
5393 **/
b6ec895e 5394int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5395{
b6ec895e 5396 struct device *dev = tx_ring->dev;
de88eeeb 5397 int orig_node = dev_to_node(dev);
ca8dfe25 5398 int ring_node = -1;
9a799d71
AK		 5399 int size;
5400
3a581073 5401 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5402
5403 if (tx_ring->q_vector)
ca8dfe25 5404 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5405
ca8dfe25 5406 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5407 if (!tx_ring->tx_buffer_info)
89bf67f1 5408 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5409 if (!tx_ring->tx_buffer_info)
5410 goto err;
9a799d71 5411
827da44c
JS		 5412 u64_stats_init(&tx_ring->syncp);
5413
9a799d71 5414 /* round up to nearest 4K */
12207e49 5415 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5416 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5417
ca8dfe25 5418 set_dev_node(dev, ring_node);
de88eeeb
AD		 5419 tx_ring->desc = dma_alloc_coherent(dev,
5420 tx_ring->size,
5421 &tx_ring->dma,
5422 GFP_KERNEL);
5423 set_dev_node(dev, orig_node);
5424 if (!tx_ring->desc)
5425 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5426 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5427 if (!tx_ring->desc)
5428 goto err;
9a799d71 5429
3a581073
JB		 5430 tx_ring->next_to_use = 0;
5431 tx_ring->next_to_clean = 0;
9a799d71 5432 return 0;
e01c31a5
JB		 5433
5434err:
5435 vfree(tx_ring->tx_buffer_info);
5436 tx_ring->tx_buffer_info = NULL;
b6ec895e 5437 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5438 return -ENOMEM;
9a799d71
AK		 5439}
5440
69888674
AD		 5441/**
5442 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5443 * @adapter: board private structure
5444 *
5445 * If this function returns with an error, then it's possible one or
5446 * more of the rings is populated (while the rest are not). It is the
5447 * callers duty to clean those orphaned rings.
5448 *
5449 * Return 0 on success, negative on failure
5450 **/
5451static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5452{
5453 int i, err = 0;
5454
5455 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5456 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5457 if (!err)
5458 continue;
de3d5b94 5459
396e799c 5460 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5461 goto err_setup_tx;
69888674
AD		 5462 }
5463
de3d5b94
AD		 5464 return 0;
5465err_setup_tx:
5466 /* rewind the index freeing the rings as we go */
5467 while (i--)
5468 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5469 return err;
5470}
5471
9a799d71
AK		 5472/**
5473 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5474 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5475 *
5476 * Returns 0 on success, negative on failure
5477 **/
b6ec895e 5478int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5479{
b6ec895e 5480 struct device *dev = rx_ring->dev;
de88eeeb 5481 int orig_node = dev_to_node(dev);
ca8dfe25 5482 int ring_node = -1;
021230d4 5483 int size;
9a799d71 5484
3a581073 5485 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5486
5487 if (rx_ring->q_vector)
ca8dfe25 5488 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5489
ca8dfe25 5490 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5491 if (!rx_ring->rx_buffer_info)
89bf67f1 5492 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5493 if (!rx_ring->rx_buffer_info)
5494 goto err;
9a799d71 5495
827da44c
JS		 5496 u64_stats_init(&rx_ring->syncp);
5497
9a799d71 5498 /* Round up to nearest 4K */
3a581073
JB		 5499 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5500 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5501
ca8dfe25 5502 set_dev_node(dev, ring_node);
de88eeeb
AD		 5503 rx_ring->desc = dma_alloc_coherent(dev,
5504 rx_ring->size,
5505 &rx_ring->dma,
5506 GFP_KERNEL);
5507 set_dev_node(dev, orig_node);
5508 if (!rx_ring->desc)
5509 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5510 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5511 if (!rx_ring->desc)
5512 goto err;
9a799d71 5513
3a581073
JB		 5514 rx_ring->next_to_clean = 0;
5515 rx_ring->next_to_use = 0;
9a799d71
AK		 5516
5517 return 0;
b6ec895e
AD		 5518err:
5519 vfree(rx_ring->rx_buffer_info);
5520 rx_ring->rx_buffer_info = NULL;
5521 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5522 return -ENOMEM;
9a799d71
AK		 5523}
5524
69888674
AD		 5525/**
5526 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5527 * @adapter: board private structure
5528 *
5529 * If this function returns with an error, then it's possible one or
5530 * more of the rings is populated (while the rest are not). It is the
5531 * callers duty to clean those orphaned rings.
5532 *
5533 * Return 0 on success, negative on failure
5534 **/
69888674
AD		 5535static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5536{
5537 int i, err = 0;
5538
5539 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5540 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5541 if (!err)
5542 continue;
de3d5b94 5543
396e799c 5544 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5545 goto err_setup_rx;
69888674
AD		 5546 }
5547
7c8ae65a
AD		 5548#ifdef IXGBE_FCOE
5549 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5550 if (!err)
5551#endif
5552 return 0;
de3d5b94
AD		 5553err_setup_rx:
5554 /* rewind the index freeing the rings as we go */
5555 while (i--)
5556 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5557 return err;
5558}
5559
9a799d71
AK		 5560/**
5561 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5562 * @tx_ring: Tx descriptor ring for a specific queue
5563 *
5564 * Free all transmit software resources
5565 **/
b6ec895e 5566void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5567{
b6ec895e 5568 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5569
5570 vfree(tx_ring->tx_buffer_info);
5571 tx_ring->tx_buffer_info = NULL;
5572
b6ec895e
AD		 5573 /* if not set, then don't free */
5574 if (!tx_ring->desc)
5575 return;
5576
5577 dma_free_coherent(tx_ring->dev, tx_ring->size,
5578 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5579
5580 tx_ring->desc = NULL;
5581}
5582
5583/**
5584 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5585 * @adapter: board private structure
5586 *
5587 * Free all transmit software resources
5588 **/
5589static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5590{
5591 int i;
5592
5593 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5594 if (adapter->tx_ring[i]->desc)
b6ec895e 5595 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5596}
5597
5598/**
b4617240 5599 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5600 * @rx_ring: ring to clean the resources from
5601 *
5602 * Free all receive software resources
5603 **/
b6ec895e 5604void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5605{
b6ec895e 5606 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5607
5608 vfree(rx_ring->rx_buffer_info);
5609 rx_ring->rx_buffer_info = NULL;
5610
b6ec895e
AD		 5611 /* if not set, then don't free */
5612 if (!rx_ring->desc)
5613 return;
5614
5615 dma_free_coherent(rx_ring->dev, rx_ring->size,
5616 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5617
5618 rx_ring->desc = NULL;
5619}
5620
5621/**
5622 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5623 * @adapter: board private structure
5624 *
5625 * Free all receive software resources
5626 **/
5627static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5628{
5629 int i;
5630
7c8ae65a
AD		 5631#ifdef IXGBE_FCOE
5632 ixgbe_free_fcoe_ddp_resources(adapter);
5633
5634#endif
9a799d71 5635 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5636 if (adapter->rx_ring[i]->desc)
b6ec895e 5637 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5638}
5639
9a799d71
AK		 5640/**
5641 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5642 * @netdev: network interface device structure
5643 * @new_mtu: new value for maximum frame size
5644 *
5645 * Returns 0 on success, negative on failure
5646 **/
5647static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5648{
5649 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5650 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5651
42c783c5 5652 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5653 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5654 return -EINVAL;
5655
5656 /*
872844dd
AD		 5657 * For 82599EB we cannot allow legacy VFs to enable their receive
5658 * paths when MTU greater than 1500 is configured. So display a
5659 * warning that legacy VFs will be disabled.
655309e9
AD		 5660 */
5661 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5662 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5663 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5664 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5665
396e799c 5666 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5667
021230d4 5668 /* must set new MTU before calling down or up */
9a799d71
AK		 5669 netdev->mtu = new_mtu;
5670
d4f80882
AV		 5671 if (netif_running(netdev))
5672 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5673
5674 return 0;
5675}
5676
5677/**
5678 * ixgbe_open - Called when a network interface is made active
5679 * @netdev: network interface device structure
5680 *
5681 * Returns 0 on success, negative value on failure
5682 *
5683 * The open entry point is called when a network interface is made
5684 * active by the system (IFF_UP). At this point all resources needed
5685 * for transmit and receive operations are allocated, the interrupt
5686 * handler is registered with the OS, the watchdog timer is started,
5687 * and the stack is notified that the interface is ready.
5688 **/
5689static int ixgbe_open(struct net_device *netdev)
5690{
5691 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 5692 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 5693 int err, queues;
4bebfaa5
AK		 5694
5695 /* disallow open during test */
5696 if (test_bit(__IXGBE_TESTING, &adapter->state))
5697 return -EBUSY;
9a799d71 5698
54386467
JB		 5699 netif_carrier_off(netdev);
5700
9a799d71
AK		 5701 /* allocate transmit descriptors */
5702 err = ixgbe_setup_all_tx_resources(adapter);
5703 if (err)
5704 goto err_setup_tx;
5705
9a799d71
AK		 5706 /* allocate receive descriptors */
5707 err = ixgbe_setup_all_rx_resources(adapter);
5708 if (err)
5709 goto err_setup_rx;
5710
5711 ixgbe_configure(adapter);
5712
021230d4 5713 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5714 if (err)
5715 goto err_req_irq;
5716
ac802f5d 5717 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5718 if (adapter->num_rx_pools > 1)
5719 queues = adapter->num_rx_queues_per_pool;
5720 else
5721 queues = adapter->num_tx_queues;
5722
5723 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5724 if (err)
5725 goto err_set_queues;
5726
2a47fa45
JF		 5727 if (adapter->num_rx_pools > 1 &&
5728 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5729 queues = IXGBE_MAX_L2A_QUEUES;
5730 else
5731 queues = adapter->num_rx_queues;
5732 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5733 if (err)
5734 goto err_set_queues;
5735
1a71ab24 5736 ixgbe_ptp_init(adapter);
1a71ab24 5737
c7ccde0f 5738 ixgbe_up_complete(adapter);
9a799d71 5739
3f207800
DS		 5740#if IS_ENABLED(CONFIG_IXGBE_VXLAN)
5741 vxlan_get_rx_port(netdev);
5742
5743#endif
9a799d71
AK		 5744 return 0;
5745
ac802f5d
AD		 5746err_set_queues:
5747 ixgbe_free_irq(adapter);
9a799d71 5748err_req_irq:
a20a1199 5749 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 5750 if (hw->phy.ops.set_phy_power && !adapter->wol)
5751 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 5752err_setup_rx:
a20a1199 5753 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5754err_setup_tx:
9a799d71
AK		 5755 ixgbe_reset(adapter);
5756
5757 return err;
5758}
5759
a0cccce2
JK		 5760static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5761{
5762 ixgbe_ptp_suspend(adapter);
5763
5764 ixgbe_down(adapter);
5765 ixgbe_free_irq(adapter);
5766
5767 ixgbe_free_all_tx_resources(adapter);
5768 ixgbe_free_all_rx_resources(adapter);
5769}
5770
9a799d71
AK		 5771/**
5772 * ixgbe_close - Disables a network interface
5773 * @netdev: network interface device structure
5774 *
5775 * Returns 0, this is not allowed to fail
5776 *
5777 * The close entry point is called when an interface is de-activated
5778 * by the OS. The hardware is still under the drivers control, but
5779 * needs to be disabled. A global MAC reset is issued to stop the
5780 * hardware, and all transmit and receive resources are freed.
5781 **/
5782static int ixgbe_close(struct net_device *netdev)
5783{
5784 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5785
1a71ab24 5786 ixgbe_ptp_stop(adapter);
1a71ab24 5787
a0cccce2 5788 ixgbe_close_suspend(adapter);
9a799d71 5789
e4911d57
AD		 5790 ixgbe_fdir_filter_exit(adapter);
5791
5eba3699 5792 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5793
5794 return 0;
5795}
5796
b3c8b4ba
AD		 5797#ifdef CONFIG_PM
5798static int ixgbe_resume(struct pci_dev *pdev)
5799{
c60fbb00
AD		 5800 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5801 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5802 u32 err;
5803
0391bbe3 5804 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5805 pci_set_power_state(pdev, PCI_D0);
5806 pci_restore_state(pdev);
656ab817
DS		 5807 /*
5808 * pci_restore_state clears dev->state_saved so call
5809 * pci_save_state to restore it.
5810 */
5811 pci_save_state(pdev);
9ce77666 5812
5813 err = pci_enable_device_mem(pdev);
b3c8b4ba 5814 if (err) {
849c4542 5815 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5816 return err;
5817 }
4e857c58 5818 smp_mb__before_atomic();
41c62843 5819 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5820 pci_set_master(pdev);
5821
dd4d8ca6 5822 pci_wake_from_d3(pdev, false);
b3c8b4ba 5823
b3c8b4ba
AD		 5824 ixgbe_reset(adapter);
5825
495dce12
WJP		 5826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5827
ac802f5d
AD		 5828 rtnl_lock();
5829 err = ixgbe_init_interrupt_scheme(adapter);
5830 if (!err && netif_running(netdev))
c60fbb00 5831 err = ixgbe_open(netdev);
ac802f5d
AD		 5832
5833 rtnl_unlock();
5834
5835 if (err)
5836 return err;
b3c8b4ba
AD		 5837
5838 netif_device_attach(netdev);
5839
5840 return 0;
5841}
b3c8b4ba 5842#endif /* CONFIG_PM */
9d8d05ae
RW		 5843
5844static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5845{
c60fbb00
AD		 5846 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5847 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5848 struct ixgbe_hw *hw = &adapter->hw;
5849 u32 ctrl, fctrl;
5850 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5851#ifdef CONFIG_PM
5852 int retval = 0;
5853#endif
5854
5855 netif_device_detach(netdev);
5856
499ab5cc 5857 rtnl_lock();
a0cccce2
JK		 5858 if (netif_running(netdev))
5859 ixgbe_close_suspend(adapter);
499ab5cc 5860 rtnl_unlock();
b3c8b4ba 5861
5f5ae6fc
AD		 5862 ixgbe_clear_interrupt_scheme(adapter);
5863
b3c8b4ba
AD		 5864#ifdef CONFIG_PM
5865 retval = pci_save_state(pdev);
5866 if (retval)
5867 return retval;
4df10466 5868
b3c8b4ba 5869#endif
f4f1040a
JK		 5870 if (hw->mac.ops.stop_link_on_d3)
5871 hw->mac.ops.stop_link_on_d3(hw);
5872
e8e26350
PW		 5873 if (wufc) {
5874 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5875
ec74a471
ET		 5876 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5877 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5878 hw->mac.ops.enable_tx_laser(hw);
5879
e8e26350
PW		 5880 /* turn on all-multi mode if wake on multicast is enabled */
5881 if (wufc & IXGBE_WUFC_MC) {
5882 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5883 fctrl |= IXGBE_FCTRL_MPE;
5884 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5885 }
5886
5887 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5888 ctrl |= IXGBE_CTRL_GIO_DIS;
5889 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5890
5891 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5892 } else {
5893 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5894 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5895 }
5896
bd508178
AD		 5897 switch (hw->mac.type) {
5898 case ixgbe_mac_82598EB:
dd4d8ca6 5899 pci_wake_from_d3(pdev, false);
bd508178
AD		 5900 break;
5901 case ixgbe_mac_82599EB:
b93a2226 5902 case ixgbe_mac_X540:
9a75a1ac
DS		 5903 case ixgbe_mac_X550:
5904 case ixgbe_mac_X550EM_x:
bd508178
AD		 5905 pci_wake_from_d3(pdev, !!wufc);
5906 break;
5907 default:
5908 break;
5909 }
b3c8b4ba 5910
9d8d05ae 5911 *enable_wake = !!wufc;
961fac88
DS		 5912 if (hw->phy.ops.set_phy_power && !*enable_wake)
5913 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 5914
b3c8b4ba
AD		 5915 ixgbe_release_hw_control(adapter);
5916
41c62843
MR		 5917 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5918 pci_disable_device(pdev);
b3c8b4ba 5919
9d8d05ae
RW		 5920 return 0;
5921}
5922
5923#ifdef CONFIG_PM
5924static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5925{
5926 int retval;
5927 bool wake;
5928
5929 retval = __ixgbe_shutdown(pdev, &wake);
5930 if (retval)
5931 return retval;
5932
5933 if (wake) {
5934 pci_prepare_to_sleep(pdev);
5935 } else {
5936 pci_wake_from_d3(pdev, false);
5937 pci_set_power_state(pdev, PCI_D3hot);
5938 }
b3c8b4ba
AD		 5939
5940 return 0;
5941}
9d8d05ae 5942#endif /* CONFIG_PM */
b3c8b4ba
AD		 5943
5944static void ixgbe_shutdown(struct pci_dev *pdev)
5945{
9d8d05ae
RW		 5946 bool wake;
5947
5948 __ixgbe_shutdown(pdev, &wake);
5949
5950 if (system_state == SYSTEM_POWER_OFF) {
5951 pci_wake_from_d3(pdev, wake);
5952 pci_set_power_state(pdev, PCI_D3hot);
5953 }
b3c8b4ba
AD		 5954}
5955
9a799d71
AK		 5956/**
5957 * ixgbe_update_stats - Update the board statistics counters.
5958 * @adapter: board private structure
5959 **/
5960void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5961{
2d86f139 5962 struct net_device *netdev = adapter->netdev;
9a799d71 5963 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5964 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5965 u64 total_mpc = 0;
5966 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5967 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5968 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5969 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5970
d08935c2
DS		 5971 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5972 test_bit(__IXGBE_RESETTING, &adapter->state))
5973 return;
5974
94b982b2 5975 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5976 u64 rsc_count = 0;
94b982b2 5977 u64 rsc_flush = 0;
94b982b2 5978 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5979 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5980 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5981 }
5982 adapter->rsc_total_count = rsc_count;
5983 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5984 }
5985
5b7da515
AD		 5986 for (i = 0; i < adapter->num_rx_queues; i++) {
5987 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5988 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5989 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5990 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5991 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5992 bytes += rx_ring->stats.bytes;
5993 packets += rx_ring->stats.packets;
5994 }
5995 adapter->non_eop_descs = non_eop_descs;
5996 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5997 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5998 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5999 netdev->stats.rx_bytes = bytes;
6000 netdev->stats.rx_packets = packets;
6001
6002 bytes = 0;
6003 packets = 0;
7ca3bc58 6004 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6005 for (i = 0; i < adapter->num_tx_queues; i++) {
6006 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6007 restart_queue += tx_ring->tx_stats.restart_queue;
6008 tx_busy += tx_ring->tx_stats.tx_busy;
6009 bytes += tx_ring->stats.bytes;
6010 packets += tx_ring->stats.packets;
6011 }
eb985f09 6012 adapter->restart_queue = restart_queue;
5b7da515
AD		 6013 adapter->tx_busy = tx_busy;
6014 netdev->stats.tx_bytes = bytes;
6015 netdev->stats.tx_packets = packets;
7ca3bc58 6016
7ca647bd 6017 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6018
6019 /* 8 register reads */
6f11eef7
AV		 6020 for (i = 0; i < 8; i++) {
6021 /* for packet buffers not used, the register should read 0 */
6022 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6023 missed_rx += mpc;
7ca647bd
JP		 6024 hwstats->mpc[i] += mpc;
6025 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6026 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6027 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6028 switch (hw->mac.type) {
6029 case ixgbe_mac_82598EB:
1a70db4b
ET		 6030 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6031 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6032 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6033 hwstats->pxonrxc[i] +=
6034 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6035 break;
6036 case ixgbe_mac_82599EB:
b93a2226 6037 case ixgbe_mac_X540:
9a75a1ac
DS		 6038 case ixgbe_mac_X550:
6039 case ixgbe_mac_X550EM_x:
bd508178
AD		 6040 hwstats->pxonrxc[i] +=
6041 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6042 break;
6043 default:
6044 break;
e8e26350 6045 }
6f11eef7 6046 }
1a70db4b
ET		 6047
6048 /*16 register reads */
6049 for (i = 0; i < 16; i++) {
6050 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6051 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6052 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6053 (hw->mac.type == ixgbe_mac_X540) ||
6054 (hw->mac.type == ixgbe_mac_X550) ||
6055 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 6056 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6057 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6058 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6059 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6060 }
6061 }
6062
7ca647bd 6063 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6064 /* work around hardware counting issue */
7ca647bd 6065 hwstats->gprc -= missed_rx;
6f11eef7 6066
c84d324c
JF		 6067 ixgbe_update_xoff_received(adapter);
6068
6f11eef7 6069 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6070 switch (hw->mac.type) {
6071 case ixgbe_mac_82598EB:
6072 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6073 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6074 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6075 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6076 break;
b93a2226 6077 case ixgbe_mac_X540:
9a75a1ac
DS		 6078 case ixgbe_mac_X550:
6079 case ixgbe_mac_X550EM_x:
6080 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6081 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6082 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6083 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6084 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6085 case ixgbe_mac_82599EB:
a4d4f629
AD		 6086 for (i = 0; i < 16; i++)
6087 adapter->hw_rx_no_dma_resources +=
6088 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6089 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6090 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6091 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6092 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6093 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6094 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6095 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6096 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6097 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6098#ifdef IXGBE_FCOE
7ca647bd
JP		 6099 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6100 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6101 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6102 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6103 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6104 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6105 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6106 if (adapter->fcoe.ddp_pool) {
6107 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6108 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6109 unsigned int cpu;
6110 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6111 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6112 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6113 noddp += ddp_pool->noddp;
6114 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6115 }
5a1ee270
AD		 6116 hwstats->fcoe_noddp = noddp;
6117 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6118 }
6d45522c 6119#endif /* IXGBE_FCOE */
bd508178
AD		 6120 break;
6121 default:
6122 break;
e8e26350 6123 }
9a799d71 6124 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6125 hwstats->bprc += bprc;
6126 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6127 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6128 hwstats->mprc -= bprc;
6129 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6130 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6131 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6132 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6133 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6134 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6135 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6136 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6137 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6138 hwstats->lxontxc += lxon;
6f11eef7 6139 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6140 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6141 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6142 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6143 /*
6144 * 82598 errata - tx of flow control packets is included in tx counters
6145 */
6146 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6147 hwstats->gptc -= xon_off_tot;
6148 hwstats->mptc -= xon_off_tot;
6149 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6150 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6151 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6152 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6153 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6154 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6155 hwstats->ptc64 -= xon_off_tot;
6156 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6157 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6158 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6159 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6160 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6161 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6162
6163 /* Fill out the OS statistics structure */
7ca647bd 6164 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6165
6166 /* Rx Errors */
7ca647bd 6167 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6168 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6169 netdev->stats.rx_length_errors = hwstats->rlec;
6170 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6171 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6172}
6173
6174/**
d034acf1 6175 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6176 * @adapter: pointer to the device adapter structure
9a799d71 6177 **/
d034acf1 6178static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6179{
cf8280ee 6180 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6181 int i;
cf8280ee 6182
d034acf1
AD		 6183 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6184 return;
6185
6186 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6187
d034acf1 6188 /* if interface is down do nothing */
fe49f04a 6189 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6190 return;
6191
6192 /* do nothing if we are not using signature filters */
6193 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6194 return;
6195
6196 adapter->fdir_overflow++;
6197
93c52dd0
AD		 6198 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6199 for (i = 0; i < adapter->num_tx_queues; i++)
6200 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6201 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6202 /* re-enable flow director interrupts */
6203 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6204 } else {
6205 e_err(probe, "failed to finish FDIR re-initialization, "
6206 "ignored adding FDIR ATR filters\n");
6207 }
93c52dd0
AD		 6208}
6209
6210/**
6211 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6212 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6213 *
6214 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6215 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6216 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6217 * determine if a hang has occurred.
93c52dd0
AD		 6218 */
6219static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6220{
cf8280ee 6221 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6222 u64 eics = 0;
6223 int i;
cf8280ee 6224
09f40aed 6225 /* If we're down, removing or resetting, just bail */
93c52dd0 6226 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6227 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6228 test_bit(__IXGBE_RESETTING, &adapter->state))
6229 return;
22d5a71b 6230
93c52dd0
AD		 6231 /* Force detection of hung controller */
6232 if (netif_carrier_ok(adapter->netdev)) {
6233 for (i = 0; i < adapter->num_tx_queues; i++)
6234 set_check_for_tx_hang(adapter->tx_ring[i]);
6235 }
22d5a71b 6236
fe49f04a
AD		 6237 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6238 /*
6239 * for legacy and MSI interrupts don't set any bits
6240 * that are enabled for EIAM, because this operation
6241 * would set *both* EIMS and EICS for any bit in EIAM
6242 */
6243 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6244 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6245 } else {
6246 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6247 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6248 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6249 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6250 eics |= ((u64)1 << i);
6251 }
cf8280ee 6252 }
9a799d71 6253
93c52dd0 6254 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6255 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6256}
6257
e8e26350 6258/**
93c52dd0 6259 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6260 * @adapter: pointer to the device adapter structure
6261 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6262 **/
93c52dd0 6263static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6264{
e8e26350 6265 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6266 u32 link_speed = adapter->link_speed;
6267 bool link_up = adapter->link_up;
041441d0 6268 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6269
93c52dd0
AD		 6270 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6271 return;
6272
6273 if (hw->mac.ops.check_link) {
6274 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6275 } else {
93c52dd0
AD		 6276 /* always assume link is up, if no check link function */
6277 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6278 link_up = true;
c4cf55e5 6279 }
041441d0
AD		 6280
6281 if (adapter->ixgbe_ieee_pfc)
6282 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6283
3ebe8fde 6284 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6285 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6286 ixgbe_set_rx_drop_en(adapter);
6287 }
93c52dd0
AD		 6288
6289 if (link_up ||
6290 time_after(jiffies, (adapter->link_check_timeout +
6291 IXGBE_TRY_LINK_TIMEOUT))) {
6292 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6293 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6294 IXGBE_WRITE_FLUSH(hw);
6295 }
6296
6297 adapter->link_up = link_up;
6298 adapter->link_speed = link_speed;
e8e26350
PW		 6299}
6300
107d3018
AD		 6301static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6302{
6303#ifdef CONFIG_IXGBE_DCB
6304 struct net_device *netdev = adapter->netdev;
6305 struct dcb_app app = {
6306 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6307 .protocol = 0,
6308 };
6309 u8 up = 0;
6310
6311 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6312 up = dcb_ieee_getapp_mask(netdev, &app);
6313
6314 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6315#endif
6316}
6317
e8e26350 6318/**
93c52dd0
AD		 6319 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6320 * print link up message
49ce9c2c 6321 * @adapter: pointer to the device adapter structure
e8e26350 6322 **/
93c52dd0 6323static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6324{
93c52dd0 6325 struct net_device *netdev = adapter->netdev;
e8e26350 6326 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6327 struct net_device *upper;
6328 struct list_head *iter;
93c52dd0
AD		 6329 u32 link_speed = adapter->link_speed;
6330 bool flow_rx, flow_tx;
e8e26350 6331
93c52dd0
AD		 6332 /* only continue if link was previously down */
6333 if (netif_carrier_ok(netdev))
a985b6c3 6334 return;
63d6e1d8 6335
93c52dd0 6336 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6337
93c52dd0
AD		 6338 switch (hw->mac.type) {
6339 case ixgbe_mac_82598EB: {
6340 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6341 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6342 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6343 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6344 }
6345 break;
6346 case ixgbe_mac_X540:
9a75a1ac
DS		 6347 case ixgbe_mac_X550:
6348 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6349 case ixgbe_mac_82599EB: {
6350 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6351 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6352 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6353 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6354 }
6355 break;
6356 default:
6357 flow_tx = false;
6358 flow_rx = false;
6359 break;
e8e26350 6360 }
3a6a4eda 6361
6cb562d6
JK		 6362 adapter->last_rx_ptp_check = jiffies;
6363
8fecf67c 6364 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6365 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6366
93c52dd0
AD		 6367 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6368 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6369 "10 Gbps" :
6370 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6371 "1 Gbps" :
6372 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6373 "100 Mbps" :
6374 "unknown speed"))),
6375 ((flow_rx && flow_tx) ? "RX/TX" :
6376 (flow_rx ? "RX" :
6377 (flow_tx ? "TX" : "None"))));
e8e26350 6378
93c52dd0 6379 netif_carrier_on(netdev);
93c52dd0 6380 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6381
cdc04dcc
ET		 6382 /* enable transmits */
6383 netif_tx_wake_all_queues(adapter->netdev);
6384
6385 /* enable any upper devices */
6386 rtnl_lock();
6387 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6388 if (netif_is_macvlan(upper)) {
6389 struct macvlan_dev *vlan = netdev_priv(upper);
6390
6391 if (vlan->fwd_priv)
6392 netif_tx_wake_all_queues(upper);
6393 }
6394 }
6395 rtnl_unlock();
6396
107d3018
AD		 6397 /* update the default user priority for VFs */
6398 ixgbe_update_default_up(adapter);
6399
befa2af7
AD		 6400 /* ping all the active vfs to let them know link has changed */
6401 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6402}
6403
c4cf55e5 6404/**
93c52dd0
AD		 6405 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6406 * print link down message
49ce9c2c 6407 * @adapter: pointer to the adapter structure
c4cf55e5 6408 **/
581330ba 6409static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6410{
cf8280ee 6411 struct net_device *netdev = adapter->netdev;
c4cf55e5 6412 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6413
93c52dd0
AD		 6414 adapter->link_up = false;
6415 adapter->link_speed = 0;
cf8280ee 6416
93c52dd0
AD		 6417 /* only continue if link was up previously */
6418 if (!netif_carrier_ok(netdev))
6419 return;
264857b8 6420
93c52dd0
AD		 6421 /* poll for SFP+ cable when link is down */
6422 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6423 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6424
8fecf67c 6425 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6426 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6427
93c52dd0
AD		 6428 e_info(drv, "NIC Link is Down\n");
6429 netif_carrier_off(netdev);
befa2af7
AD		 6430
6431 /* ping all the active vfs to let them know link has changed */
6432 ixgbe_ping_all_vfs(adapter);
93c52dd0 6433}
e8e26350 6434
07923c17
ET		 6435static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6436{
6437 int i;
6438
6439 for (i = 0; i < adapter->num_tx_queues; i++) {
6440 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6441
6442 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6443 return true;
6444 }
6445
6446 return false;
6447}
6448
6449static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6450{
6451 struct ixgbe_hw *hw = &adapter->hw;
6452 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6453 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6454
6455 int i, j;
6456
6457 if (!adapter->num_vfs)
6458 return false;
6459
9a75a1ac
DS		 6460 /* resetting the PF is only needed for MAC before X550 */
6461 if (hw->mac.type >= ixgbe_mac_X550)
6462 return false;
6463
07923c17
ET		 6464 for (i = 0; i < adapter->num_vfs; i++) {
6465 for (j = 0; j < q_per_pool; j++) {
6466 u32 h, t;
6467
6468 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6469 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6470
6471 if (h != t)
6472 return true;
6473 }
6474 }
6475
6476 return false;
6477}
6478
93c52dd0
AD		 6479/**
6480 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6481 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6482 **/
6483static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6484{
93c52dd0 6485 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6486 if (ixgbe_ring_tx_pending(adapter) ||
6487 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6488 /* We've lost link, so the controller stops DMA,
6489 * but we've got queued Tx work that's never going
6490 * to get done, so reset controller to flush Tx.
6491 * (Do the reset outside of interrupt context).
6492 */
12ff3f3b 6493 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6494 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6495 }
c4cf55e5 6496 }
c4cf55e5
PWJ		 6497}
6498
9079e416
ET		 6499#ifdef CONFIG_PCI_IOV
6500static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6501 struct pci_dev *vfdev)
6502{
6503 if (!pci_wait_for_pending_transaction(vfdev))
6504 e_dev_warn("Issuing VFLR with pending transactions\n");
6505
6506 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6507 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6508
6509 msleep(100);
6510}
6511
6512static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6513{
6514 struct ixgbe_hw *hw = &adapter->hw;
6515 struct pci_dev *pdev = adapter->pdev;
6516 struct pci_dev *vfdev;
6517 u32 gpc;
6518 int pos;
6519 unsigned short vf_id;
6520
6521 if (!(netif_carrier_ok(adapter->netdev)))
6522 return;
6523
6524 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6525 if (gpc) /* If incrementing then no need for the check below */
6526 return;
6527 /* Check to see if a bad DMA write target from an errant or
6528 * malicious VF has caused a PCIe error. If so then we can
6529 * issue a VFLR to the offending VF(s) and then resume without
6530 * requesting a full slot reset.
6531 */
6532
6533 if (!pdev)
6534 return;
6535
6536 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6537 if (!pos)
6538 return;
6539
6540 /* get the device ID for the VF */
6541 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6542
6543 /* check status reg for all VFs owned by this PF */
6544 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6545 while (vfdev) {
6546 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6547 u16 status_reg;
6548
6549 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6550 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6551 /* issue VFLR */
6552 ixgbe_issue_vf_flr(adapter, vfdev);
6553 }
6554
6555 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6556 }
6557}
6558
a985b6c3
GR		 6559static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6560{
6561 u32 ssvpc;
6562
0584d999
GR		 6563 /* Do not perform spoof check for 82598 or if not in IOV mode */
6564 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6565 adapter->num_vfs == 0)
a985b6c3
GR		 6566 return;
6567
6568 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6569
6570 /*
6571 * ssvpc register is cleared on read, if zero then no
6572 * spoofed packets in the last interval.
6573 */
6574 if (!ssvpc)
6575 return;
6576
d6ea0754 6577 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6578}
9079e416
ET		 6579#else
6580static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6581{
6582}
6583
6584static void
6585ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6586{
6587}
6588#endif /* CONFIG_PCI_IOV */
6589
a985b6c3 6590
93c52dd0
AD		 6591/**
6592 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6593 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6594 **/
6595static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6596{
09f40aed 6597 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6598 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6599 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6600 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6601 return;
6602
6603 ixgbe_watchdog_update_link(adapter);
6604
6605 if (adapter->link_up)
6606 ixgbe_watchdog_link_is_up(adapter);
6607 else
6608 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6609
9079e416 6610 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6611 ixgbe_spoof_check(adapter);
9a799d71 6612 ixgbe_update_stats(adapter);
93c52dd0
AD		 6613
6614 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6615}
10eec955 6616
cf8280ee 6617/**
7086400d 6618 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6619 * @adapter: the ixgbe adapter structure
cf8280ee 6620 **/
7086400d 6621static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6622{
cf8280ee 6623 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6624 s32 err;
cf8280ee 6625
7086400d
AD		 6626 /* not searching for SFP so there is nothing to do here */
6627 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6628 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6629 return;
10eec955 6630
7086400d
AD		 6631 /* someone else is in init, wait until next service event */
6632 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6633 return;
cf8280ee 6634
7086400d
AD		 6635 err = hw->phy.ops.identify_sfp(hw);
6636 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6637 goto sfp_out;
264857b8 6638
7086400d
AD		 6639 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6640 /* If no cable is present, then we need to reset
6641 * the next time we find a good cable. */
6642 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6643 }
9a799d71 6644
7086400d
AD		 6645 /* exit on error */
6646 if (err)
6647 goto sfp_out;
e8e26350 6648
7086400d
AD		 6649 /* exit if reset not needed */
6650 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6651 goto sfp_out;
9a799d71 6652
7086400d 6653 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6654
7086400d
AD		 6655 /*
6656 * A module may be identified correctly, but the EEPROM may not have
6657 * support for that module. setup_sfp() will fail in that case, so
6658 * we should not allow that module to load.
6659 */
6660 if (hw->mac.type == ixgbe_mac_82598EB)
6661 err = hw->phy.ops.reset(hw);
6662 else
6663 err = hw->mac.ops.setup_sfp(hw);
6664
6665 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6666 goto sfp_out;
6667
6668 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6669 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6670
6671sfp_out:
6672 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6673
6674 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6675 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6676 e_dev_err("failed to initialize because an unsupported "
6677 "SFP+ module type was detected.\n");
6678 e_dev_err("Reload the driver after installing a "
6679 "supported module.\n");
6680 unregister_netdev(adapter->netdev);
bc59fcda 6681 }
7086400d 6682}
bc59fcda 6683
7086400d
AD		 6684/**
6685 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6686 * @adapter: the ixgbe adapter structure
7086400d
AD		 6687 **/
6688static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6689{
6690 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6691 u32 speed;
6692 bool autoneg = false;
7086400d
AD		 6693
6694 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6695 return;
6696
6697 /* someone else is in init, wait until next service event */
6698 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6699 return;
6700
6701 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6702
3d292265 6703 speed = hw->phy.autoneg_advertised;
ed33ff66 6704 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6705 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6706
6707 /* setup the highest link when no autoneg */
6708 if (!autoneg) {
6709 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6710 speed = IXGBE_LINK_SPEED_10GB_FULL;
6711 }
6712 }
6713
7086400d 6714 if (hw->mac.ops.setup_link)
fd0326f2 6715 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6716
6717 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6718 adapter->link_check_timeout = jiffies;
6719 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6720}
6721
6722/**
6723 * ixgbe_service_timer - Timer Call-back
6724 * @data: pointer to adapter cast into an unsigned long
6725 **/
6726static void ixgbe_service_timer(unsigned long data)
6727{
6728 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6729 unsigned long next_event_offset;
6730
6bb78cfb
AD		 6731 /* poll faster when waiting for link */
6732 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6733 next_event_offset = HZ / 10;
6734 else
6735 next_event_offset = HZ * 2;
83c61fa9 6736
7086400d
AD		 6737 /* Reset the timer */
6738 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6739
9079e416 6740 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6741}
6742
597f22d6
DS		 6743static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
6744{
6745 struct ixgbe_hw *hw = &adapter->hw;
6746 u32 status;
6747
6748 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
6749 return;
6750
6751 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
6752
6753 if (!hw->phy.ops.handle_lasi)
6754 return;
6755
6756 status = hw->phy.ops.handle_lasi(&adapter->hw);
6757 if (status != IXGBE_ERR_OVERTEMP)
6758 return;
6759
6760 e_crit(drv, "%s\n", ixgbe_overheat_msg);
6761}
6762
c83c6cbd
AD		 6763static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6764{
6765 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6766 return;
6767
6768 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6769
09f40aed 6770 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6771 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6772 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6773 test_bit(__IXGBE_RESETTING, &adapter->state))
6774 return;
6775
6776 ixgbe_dump(adapter);
6777 netdev_err(adapter->netdev, "Reset adapter\n");
6778 adapter->tx_timeout_count++;
6779
8f4c5c9f 6780 rtnl_lock();
c83c6cbd 6781 ixgbe_reinit_locked(adapter);
8f4c5c9f 6782 rtnl_unlock();
c83c6cbd
AD		 6783}
6784
7086400d
AD		 6785/**
6786 * ixgbe_service_task - manages and runs subtasks
6787 * @work: pointer to work_struct containing our data
6788 **/
6789static void ixgbe_service_task(struct work_struct *work)
6790{
6791 struct ixgbe_adapter *adapter = container_of(work,
6792 struct ixgbe_adapter,
6793 service_task);
b0483c8f
MR		 6794 if (ixgbe_removed(adapter->hw.hw_addr)) {
6795 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6796 rtnl_lock();
6797 ixgbe_down(adapter);
6798 rtnl_unlock();
6799 }
6800 ixgbe_service_event_complete(adapter);
6801 return;
6802 }
c83c6cbd 6803 ixgbe_reset_subtask(adapter);
597f22d6 6804 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 6805 ixgbe_sfp_detection_subtask(adapter);
6806 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6807 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6808 ixgbe_watchdog_subtask(adapter);
d034acf1 6809 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6810 ixgbe_check_hang_subtask(adapter);
891dc082 6811
8fecf67c 6812 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6813 ixgbe_ptp_overflow_check(adapter);
6814 ixgbe_ptp_rx_hang(adapter);
6815 }
7086400d
AD		 6816
6817 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6818}
6819
fd0db0ed
AD		 6820static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6821 struct ixgbe_tx_buffer *first,
244e27ad 6822 u8 *hdr_len)
897ab156 6823{
fd0db0ed 6824 struct sk_buff *skb = first->skb;
897ab156
AD		 6825 u32 vlan_macip_lens, type_tucmd;
6826 u32 mss_l4len_idx, l4len;
2049e1f6 6827 int err;
9a799d71 6828
8f4fbb9b
AD		 6829 if (skb->ip_summed != CHECKSUM_PARTIAL)
6830 return 0;
6831
897ab156
AD		 6832 if (!skb_is_gso(skb))
6833 return 0;
9a799d71 6834
2049e1f6
FR		 6835 err = skb_cow_head(skb, 0);
6836 if (err < 0)
6837 return err;
9a799d71 6838
897ab156
AD		 6839 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6840 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6841
a1108ffd 6842 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6843 struct iphdr *iph = ip_hdr(skb);
6844 iph->tot_len = 0;
6845 iph->check = 0;
6846 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6847 iph->daddr, 0,
6848 IPPROTO_TCP,
6849 0);
6850 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6851 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6852 IXGBE_TX_FLAGS_CSUM |
6853 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6854 } else if (skb_is_gso_v6(skb)) {
6855 ipv6_hdr(skb)->payload_len = 0;
6856 tcp_hdr(skb)->check =
6857 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6858 &ipv6_hdr(skb)->daddr,
6859 0, IPPROTO_TCP, 0);
244e27ad
AD		 6860 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6861 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6862 }
6863
091a6246 6864 /* compute header lengths */
897ab156
AD		 6865 l4len = tcp_hdrlen(skb);
6866 *hdr_len = skb_transport_offset(skb) + l4len;
6867
091a6246
AD		 6868 /* update gso size and bytecount with header size */
6869 first->gso_segs = skb_shinfo(skb)->gso_segs;
6870 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6871
c44f5f51 6872 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6873 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6874 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6875
6876 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6877 vlan_macip_lens = skb_network_header_len(skb);
6878 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6879 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6880
6881 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6882 mss_l4len_idx);
897ab156
AD		 6883
6884 return 1;
6885}
6886
244e27ad
AD		 6887static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6888 struct ixgbe_tx_buffer *first)
7ca647bd 6889{
fd0db0ed 6890 struct sk_buff *skb = first->skb;
897ab156
AD		 6891 u32 vlan_macip_lens = 0;
6892 u32 mss_l4len_idx = 0;
6893 u32 type_tucmd = 0;
7ca647bd 6894
897ab156 6895 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6896 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6897 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6898 return;
897ab156
AD		 6899 } else {
6900 u8 l4_hdr = 0;
244e27ad 6901 switch (first->protocol) {
a1108ffd 6902 case htons(ETH_P_IP):
897ab156
AD		 6903 vlan_macip_lens |= skb_network_header_len(skb);
6904 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6905 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6906 break;
a1108ffd 6907 case htons(ETH_P_IPV6):
897ab156
AD		 6908 vlan_macip_lens |= skb_network_header_len(skb);
6909 l4_hdr = ipv6_hdr(skb)->nexthdr;
6910 break;
6911 default:
6912 if (unlikely(net_ratelimit())) {
6913 dev_warn(tx_ring->dev,
6914 "partial checksum but proto=%x!\n",
244e27ad 6915 first->protocol);
897ab156 6916 }
7ca647bd
JP		 6917 break;
6918 }
897ab156
AD		 6919
6920 switch (l4_hdr) {
7ca647bd 6921 case IPPROTO_TCP:
897ab156
AD		 6922 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6923 mss_l4len_idx = tcp_hdrlen(skb) <<
6924 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6925 break;
6926 case IPPROTO_SCTP:
897ab156
AD		 6927 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6928 mss_l4len_idx = sizeof(struct sctphdr) <<
6929 IXGBE_ADVTXD_L4LEN_SHIFT;
6930 break;
6931 case IPPROTO_UDP:
6932 mss_l4len_idx = sizeof(struct udphdr) <<
6933 IXGBE_ADVTXD_L4LEN_SHIFT;
6934 break;
6935 default:
6936 if (unlikely(net_ratelimit())) {
6937 dev_warn(tx_ring->dev,
6938 "partial checksum but l4 proto=%x!\n",
244e27ad 6939 l4_hdr);
897ab156 6940 }
7ca647bd
JP		 6941 break;
6942 }
244e27ad
AD		 6943
6944 /* update TX checksum flag */
6945 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6946 }
6947
244e27ad 6948 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6949 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6950 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6951
897ab156
AD		 6952 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6953 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6954}
6955
472148c3
AD		 6956#define IXGBE_SET_FLAG(_input, _flag, _result) \
6957 ((_flag <= _result) ? \
6958 ((u32)(_input & _flag) * (_result / _flag)) : \
6959 ((u32)(_input & _flag) / (_flag / _result)))
6960
6961static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6962{
d3d00239 6963 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6964 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6965 IXGBE_ADVTXD_DCMD_DEXT |
6966 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6967
d3d00239 6968 /* set HW vlan bit if vlan is present */
472148c3
AD		 6969 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6970 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6971
d3d00239 6972 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6973 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6974 IXGBE_ADVTXD_DCMD_TSE);
6975
6976 /* set timestamp bit if present */
6977 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6978 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6979
62748b7b 6980 /* insert frame checksum */
472148c3 6981 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6982
d3d00239
AD		 6983 return cmd_type;
6984}
9a799d71 6985
729739b7
AD		 6986static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6987 u32 tx_flags, unsigned int paylen)
d3d00239 6988{
472148c3 6989 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6990
d3d00239 6991 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6992 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6993 IXGBE_TX_FLAGS_CSUM,
6994 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6995
93f5b3c1 6996 /* enble IPv4 checksum for TSO */
472148c3
AD		 6997 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6998 IXGBE_TX_FLAGS_IPV4,
6999 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7000
7f9643fd
AD		 7001 /*
7002 * Check Context must be set if Tx switch is enabled, which it
7003 * always is for case where virtual functions are running
7004 */
472148c3
AD		 7005 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7006 IXGBE_TX_FLAGS_CC,
7007 IXGBE_ADVTXD_CC);
7f9643fd 7008
472148c3 7009 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7010}
44df32c5 7011
2367a173
DB		 7012static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7013{
7014 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7015
7016 /* Herbert's original patch had:
7017 * smp_mb__after_netif_stop_queue();
7018 * but since that doesn't exist yet, just open code it.
7019 */
7020 smp_mb();
7021
7022 /* We need to check again in a case another CPU has just
7023 * made room available.
7024 */
7025 if (likely(ixgbe_desc_unused(tx_ring) < size))
7026 return -EBUSY;
7027
7028 /* A reprieve! - use start_queue because it doesn't call schedule */
7029 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7030 ++tx_ring->tx_stats.restart_queue;
7031 return 0;
7032}
7033
7034static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7035{
7036 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7037 return 0;
7038
7039 return __ixgbe_maybe_stop_tx(tx_ring, size);
7040}
7041
d3d00239
AD		 7042#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7043 IXGBE_TXD_CMD_RS)
7044
7045static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7046 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7047 const u8 hdr_len)
7048{
fd0db0ed 7049 struct sk_buff *skb = first->skb;
729739b7 7050 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7051 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7052 struct skb_frag_struct *frag;
7053 dma_addr_t dma;
7054 unsigned int data_len, size;
244e27ad 7055 u32 tx_flags = first->tx_flags;
472148c3 7056 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7057 u16 i = tx_ring->next_to_use;
d3d00239 7058
729739b7
AD		 7059 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7060
ec718254
AD		 7061 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7062
7063 size = skb_headlen(skb);
7064 data_len = skb->data_len;
729739b7 7065
d3d00239
AD		 7066#ifdef IXGBE_FCOE
7067 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7068 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7069 size -= sizeof(struct fcoe_crc_eof) - data_len;
7070 data_len = 0;
729739b7
AD		 7071 } else {
7072 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7073 }
7074 }
44df32c5 7075
d3d00239 7076#endif
729739b7 7077 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7078
ec718254 7079 tx_buffer = first;
9a799d71 7080
ec718254
AD		 7081 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7082 if (dma_mapping_error(tx_ring->dev, dma))
7083 goto dma_error;
7084
7085 /* record length, and DMA address */
7086 dma_unmap_len_set(tx_buffer, len, size);
7087 dma_unmap_addr_set(tx_buffer, dma, dma);
7088
7089 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7090
729739b7 7091 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7092 tx_desc->read.cmd_type_len =
472148c3 7093 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7094
d3d00239 7095 i++;
729739b7 7096 tx_desc++;
d3d00239 7097 if (i == tx_ring->count) {
e4f74028 7098 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7099 i = 0;
7100 }
ec718254 7101 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7102
7103 dma += IXGBE_MAX_DATA_PER_TXD;
7104 size -= IXGBE_MAX_DATA_PER_TXD;
7105
7106 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7107 }
e5a43549 7108
729739b7
AD		 7109 if (likely(!data_len))
7110 break;
9a799d71 7111
472148c3 7112 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7113
729739b7
AD		 7114 i++;
7115 tx_desc++;
7116 if (i == tx_ring->count) {
7117 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7118 i = 0;
7119 }
ec718254 7120 tx_desc->read.olinfo_status = 0;
9a799d71 7121
d3d00239 7122#ifdef IXGBE_FCOE
9e903e08 7123 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7124#else
9e903e08 7125 size = skb_frag_size(frag);
d3d00239
AD		 7126#endif
7127 data_len -= size;
9a799d71 7128
729739b7
AD		 7129 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7130 DMA_TO_DEVICE);
9a799d71 7131
729739b7 7132 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7133 }
9a799d71 7134
729739b7 7135 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7136 cmd_type |= size | IXGBE_TXD_CMD;
7137 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7138
091a6246 7139 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7140
d3d00239
AD		 7141 /* set the timestamp */
7142 first->time_stamp = jiffies;
9a799d71
AK		 7143
7144 /*
729739b7
AD		 7145 * Force memory writes to complete before letting h/w know there
7146 * are new descriptors to fetch. (Only applicable for weak-ordered
7147 * memory model archs, such as IA-64).
7148 *
7149 * We also need this memory barrier to make certain all of the
7150 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7151 */
7152 wmb();
7153
d3d00239
AD		 7154 /* set next_to_watch value indicating a packet is present */
7155 first->next_to_watch = tx_desc;
7156
729739b7
AD		 7157 i++;
7158 if (i == tx_ring->count)
7159 i = 0;
7160
7161 tx_ring->next_to_use = i;
7162
2367a173
DB		 7163 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7164
7165 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7166 writel(i, tx_ring->tail);
7167
7168 /* we need this if more than one processor can write to our tail
7169 * at a time, it synchronizes IO on IA64/Altix systems
7170 */
7171 mmiowb();
9c938cdd 7172 }
2367a173 7173
d3d00239
AD		 7174 return;
7175dma_error:
729739b7 7176 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7177
7178 /* clear dma mappings for failed tx_buffer_info map */
7179 for (;;) {
729739b7
AD		 7180 tx_buffer = &tx_ring->tx_buffer_info[i];
7181 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7182 if (tx_buffer == first)
d3d00239
AD		 7183 break;
7184 if (i == 0)
7185 i = tx_ring->count;
7186 i--;
7187 }
7188
d3d00239 7189 tx_ring->next_to_use = i;
9a799d71
AK		 7190}
7191
fd0db0ed 7192static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7193 struct ixgbe_tx_buffer *first)
69830529
AD		 7194{
7195 struct ixgbe_q_vector *q_vector = ring->q_vector;
7196 union ixgbe_atr_hash_dword input = { .dword = 0 };
7197 union ixgbe_atr_hash_dword common = { .dword = 0 };
7198 union {
7199 unsigned char *network;
7200 struct iphdr *ipv4;
7201 struct ipv6hdr *ipv6;
7202 } hdr;
ee9e0f0b 7203 struct tcphdr *th;
905e4a41 7204 __be16 vlan_id;
c4cf55e5 7205
69830529
AD		 7206 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7207 if (!q_vector)
7208 return;
7209
7210 /* do nothing if sampling is disabled */
7211 if (!ring->atr_sample_rate)
d3ead241 7212 return;
c4cf55e5 7213
69830529 7214 ring->atr_count++;
c4cf55e5 7215
69830529 7216 /* snag network header to get L4 type and address */
fd0db0ed 7217 hdr.network = skb_network_header(first->skb);
69830529
AD		 7218
7219 /* Currently only IPv4/IPv6 with TCP is supported */
a1108ffd 7220 if ((first->protocol != htons(ETH_P_IPV6) ||
69830529 7221 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
a1108ffd 7222 (first->protocol != htons(ETH_P_IP) ||
69830529
AD		 7223 hdr.ipv4->protocol != IPPROTO_TCP))
7224 return;
ee9e0f0b 7225
fd0db0ed 7226 th = tcp_hdr(first->skb);
c4cf55e5 7227
66f32a8b
AD		 7228 /* skip this packet since it is invalid or the socket is closing */
7229 if (!th || th->fin)
69830529
AD		 7230 return;
7231
7232 /* sample on all syn packets or once every atr sample count */
7233 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7234 return;
7235
7236 /* reset sample count */
7237 ring->atr_count = 0;
7238
244e27ad 7239 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7240
7241 /*
7242 * src and dst are inverted, think how the receiver sees them
7243 *
7244 * The input is broken into two sections, a non-compressed section
7245 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7246 * is XORed together and stored in the compressed dword.
7247 */
7248 input.formatted.vlan_id = vlan_id;
7249
7250 /*
7251 * since src port and flex bytes occupy the same word XOR them together
7252 * and write the value to source port portion of compressed dword
7253 */
244e27ad 7254 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7255 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7256 else
244e27ad 7257 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7258 common.port.dst ^= th->source;
7259
a1108ffd 7260 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7261 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7262 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7263 } else {
7264 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7265 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7266 hdr.ipv6->saddr.s6_addr32[1] ^
7267 hdr.ipv6->saddr.s6_addr32[2] ^
7268 hdr.ipv6->saddr.s6_addr32[3] ^
7269 hdr.ipv6->daddr.s6_addr32[0] ^
7270 hdr.ipv6->daddr.s6_addr32[1] ^
7271 hdr.ipv6->daddr.s6_addr32[2] ^
7272 hdr.ipv6->daddr.s6_addr32[3];
7273 }
c4cf55e5
PWJ		 7274
7275 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7276 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7277 input, common, ring->queue_index);
c4cf55e5
PWJ		 7278}
7279
f663dd9a 7280static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7281 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7282{
f663dd9a
JW		 7283 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7284#ifdef IXGBE_FCOE
97488bd1
AD		 7285 struct ixgbe_adapter *adapter;
7286 struct ixgbe_ring_feature *f;
7287 int txq;
f663dd9a
JW		 7288#endif
7289
7290 if (fwd_adapter)
7291 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7292
7293#ifdef IXGBE_FCOE
5e09a105 7294
97488bd1
AD		 7295 /*
7296 * only execute the code below if protocol is FCoE
7297 * or FIP and we have FCoE enabled on the adapter
7298 */
7299 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7300 case htons(ETH_P_FCOE):
7301 case htons(ETH_P_FIP):
97488bd1 7302 adapter = netdev_priv(dev);
c087663e 7303
97488bd1
AD		 7304 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7305 break;
7306 default:
99932d4f 7307 return fallback(dev, skb);
97488bd1 7308 }
c087663e 7309
97488bd1 7310 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7311
97488bd1
AD		 7312 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7313 smp_processor_id();
56075a98 7314
97488bd1
AD		 7315 while (txq >= f->indices)
7316 txq -= f->indices;
c4cf55e5 7317
97488bd1 7318 return txq + f->offset;
f663dd9a 7319#else
99932d4f 7320 return fallback(dev, skb);
f663dd9a 7321#endif
09a3b1f8
SH		 7322}
7323
fc77dc3c 7324netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7325 struct ixgbe_adapter *adapter,
7326 struct ixgbe_ring *tx_ring)
9a799d71 7327{
d3d00239 7328 struct ixgbe_tx_buffer *first;
5f715823 7329 int tso;
d3d00239 7330 u32 tx_flags = 0;
a535c30e 7331 unsigned short f;
a535c30e 7332 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7333 __be16 protocol = skb->protocol;
63544e9c 7334 u8 hdr_len = 0;
5e09a105 7335
a535c30e
AD		 7336 /*
7337 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7338 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7339 * + 2 desc gap to keep tail from touching head,
7340 * + 1 desc for context descriptor,
7341 * otherwise try next time
7342 */
a535c30e
AD		 7343 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7344 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7345
a535c30e
AD		 7346 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7347 tx_ring->tx_stats.tx_busy++;
7348 return NETDEV_TX_BUSY;
7349 }
7350
fd0db0ed
AD		 7351 /* record the location of the first descriptor for this packet */
7352 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7353 first->skb = skb;
091a6246
AD		 7354 first->bytecount = skb->len;
7355 first->gso_segs = 1;
fd0db0ed 7356
66f32a8b 7357 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7358 if (skb_vlan_tag_present(skb)) {
7359 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7360 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7361 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7362 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7363 struct vlan_hdr *vhdr, _vhdr;
7364 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7365 if (!vhdr)
7366 goto out_drop;
7367
9e0c5648
AD		 7368 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7369 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7370 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7371 }
0213668f 7372 protocol = vlan_get_protocol(skb);
66f32a8b 7373
d5234933
MR		 7374 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7375 adapter->ptp_clock &&
7376 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7377 &adapter->state)) {
3a6a4eda
JK		 7378 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7379 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7380
7381 /* schedule check for Tx timestamp */
7382 adapter->ptp_tx_skb = skb_get(skb);
7383 adapter->ptp_tx_start = jiffies;
7384 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7385 }
3a6a4eda 7386
ff29a86e
JK		 7387 skb_tx_timestamp(skb);
7388
9e0c5648
AD		 7389#ifdef CONFIG_PCI_IOV
7390 /*
7391 * Use the l2switch_enable flag - would be false if the DMA
7392 * Tx switch had been disabled.
7393 */
7394 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7395 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7396
7397#endif
32701dc2 7398 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7399 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7400 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7401 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7402 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7403 tx_flags |= (skb->priority & 0x7) <<
7404 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7405 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7406 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7407
7408 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7409 goto out_drop;
7410 vhdr = (struct vlan_ethhdr *)skb->data;
7411 vhdr->h_vlan_TCI = htons(tx_flags >>
7412 IXGBE_TX_FLAGS_VLAN_SHIFT);
7413 } else {
7414 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7415 }
9a799d71 7416 }
eacd73f7 7417
244e27ad
AD		 7418 /* record initial flags and protocol */
7419 first->tx_flags = tx_flags;
7420 first->protocol = protocol;
7421
eacd73f7 7422#ifdef IXGBE_FCOE
66f32a8b 7423 /* setup tx offload for FCoE */
a1108ffd 7424 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7425 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7426 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7427 if (tso < 0)
7428 goto out_drop;
9a799d71 7429
66f32a8b 7430 goto xmit_fcoe;
eacd73f7 7431 }
9a799d71 7432
66f32a8b 7433#endif /* IXGBE_FCOE */
244e27ad 7434 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7435 if (tso < 0)
897ab156 7436 goto out_drop;
244e27ad
AD		 7437 else if (!tso)
7438 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7439
7440 /* add the ATR filter if ATR is on */
7441 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7442 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7443
7444#ifdef IXGBE_FCOE
7445xmit_fcoe:
7446#endif /* IXGBE_FCOE */
244e27ad 7447 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7448
9a799d71 7449 return NETDEV_TX_OK;
897ab156
AD		 7450
7451out_drop:
fd0db0ed
AD		 7452 dev_kfree_skb_any(first->skb);
7453 first->skb = NULL;
7454
897ab156 7455 return NETDEV_TX_OK;
9a799d71
AK		 7456}
7457
2a47fa45
JF		 7458static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7459 struct net_device *netdev,
7460 struct ixgbe_ring *ring)
84418e3b
AD		 7461{
7462 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7463 struct ixgbe_ring *tx_ring;
7464
a50c29dd
AD		 7465 /*
7466 * The minimum packet size for olinfo paylen is 17 so pad the skb
7467 * in order to meet this minimum size requirement.
7468 */
a94d9e22
AD		 7469 if (skb_put_padto(skb, 17))
7470 return NETDEV_TX_OK;
a50c29dd 7471
2a47fa45
JF		 7472 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7473
fc77dc3c 7474 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7475}
7476
2a47fa45
JF		 7477static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7478 struct net_device *netdev)
7479{
7480 return __ixgbe_xmit_frame(skb, netdev, NULL);
7481}
7482
9a799d71
AK		 7483/**
7484 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7485 * @netdev: network interface device structure
7486 * @p: pointer to an address structure
7487 *
7488 * Returns 0 on success, negative on failure
7489 **/
7490static int ixgbe_set_mac(struct net_device *netdev, void *p)
7491{
7492 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7493 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7494 struct sockaddr *addr = p;
5d7daa35 7495 int ret;
9a799d71
AK		 7496
7497 if (!is_valid_ether_addr(addr->sa_data))
7498 return -EADDRNOTAVAIL;
7499
5d7daa35 7500 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7501 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7502 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7503
5d7daa35
JK		 7504 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7505 return ret > 0 ? 0 : ret;
9a799d71
AK		 7506}
7507
6b73e10d
BH		 7508static int
7509ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7510{
7511 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7512 struct ixgbe_hw *hw = &adapter->hw;
7513 u16 value;
7514 int rc;
7515
7516 if (prtad != hw->phy.mdio.prtad)
7517 return -EINVAL;
7518 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7519 if (!rc)
7520 rc = value;
7521 return rc;
7522}
7523
7524static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7525 u16 addr, u16 value)
7526{
7527 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7528 struct ixgbe_hw *hw = &adapter->hw;
7529
7530 if (prtad != hw->phy.mdio.prtad)
7531 return -EINVAL;
7532 return hw->phy.ops.write_reg(hw, addr, devad, value);
7533}
7534
7535static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7536{
7537 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7538
3a6a4eda 7539 switch (cmd) {
3a6a4eda 7540 case SIOCSHWTSTAMP:
93501d48
JK		 7541 return ixgbe_ptp_set_ts_config(adapter, req);
7542 case SIOCGHWTSTAMP:
7543 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7544 default:
7545 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7546 }
6b73e10d
BH		 7547}
7548
0365e6e4
PW		 7549/**
7550 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7551 * netdev->dev_addrs
0365e6e4
PW		 7552 * @netdev: network interface device structure
7553 *
7554 * Returns non-zero on failure
7555 **/
7556static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7557{
7558 int err = 0;
7559 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7560 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7561
7fa7c9dc 7562 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7563 rtnl_lock();
7fa7c9dc 7564 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7565 rtnl_unlock();
7fa7c9dc
AD		 7566
7567 /* update SAN MAC vmdq pool selection */
7568 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7569 }
7570 return err;
7571}
7572
7573/**
7574 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7575 * netdev->dev_addrs
0365e6e4
PW		 7576 * @netdev: network interface device structure
7577 *
7578 * Returns non-zero on failure
7579 **/
7580static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7581{
7582 int err = 0;
7583 struct ixgbe_adapter *adapter = netdev_priv(dev);
7584 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7585
7586 if (is_valid_ether_addr(mac->san_addr)) {
7587 rtnl_lock();
7588 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7589 rtnl_unlock();
7590 }
7591 return err;
7592}
7593
9a799d71
AK		 7594#ifdef CONFIG_NET_POLL_CONTROLLER
7595/*
7596 * Polling 'interrupt' - used by things like netconsole to send skbs
7597 * without having to re-enable interrupts. It's not called while
7598 * the interrupt routine is executing.
7599 */
7600static void ixgbe_netpoll(struct net_device *netdev)
7601{
7602 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7603 int i;
9a799d71 7604
1a647bd2
AD		 7605 /* if interface is down do nothing */
7606 if (test_bit(__IXGBE_DOWN, &adapter->state))
7607 return;
7608
856f606e
AD		 7609 /* loop through and schedule all active queues */
7610 for (i = 0; i < adapter->num_q_vectors; i++)
7611 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 7612}
9a799d71 7613
581330ba 7614#endif
de1036b1
ED		 7615static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7616 struct rtnl_link_stats64 *stats)
7617{
7618 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7619 int i;
7620
1a51502b 7621 rcu_read_lock();
de1036b1 7622 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7623 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7624 u64 bytes, packets;
7625 unsigned int start;
7626
1a51502b
ED		 7627 if (ring) {
7628 do {
57a7744e 7629 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7630 packets = ring->stats.packets;
7631 bytes = ring->stats.bytes;
57a7744e 7632 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7633 stats->rx_packets += packets;
7634 stats->rx_bytes += bytes;
7635 }
de1036b1 7636 }
1ac9ad13
ED		 7637
7638 for (i = 0; i < adapter->num_tx_queues; i++) {
7639 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7640 u64 bytes, packets;
7641 unsigned int start;
7642
7643 if (ring) {
7644 do {
57a7744e 7645 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7646 packets = ring->stats.packets;
7647 bytes = ring->stats.bytes;
57a7744e 7648 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7649 stats->tx_packets += packets;
7650 stats->tx_bytes += bytes;
7651 }
7652 }
1a51502b 7653 rcu_read_unlock();
de1036b1
ED		 7654 /* following stats updated by ixgbe_watchdog_task() */
7655 stats->multicast = netdev->stats.multicast;
7656 stats->rx_errors = netdev->stats.rx_errors;
7657 stats->rx_length_errors = netdev->stats.rx_length_errors;
7658 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7659 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7660 return stats;
7661}
7662
8af3c33f 7663#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7664/**
7665 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7666 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7667 * @tc: number of traffic classes currently enabled
7668 *
7669 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7670 * 802.1Q priority maps to a packet buffer that exists.
7671 */
7672static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7673{
7674 struct ixgbe_hw *hw = &adapter->hw;
7675 u32 reg, rsave;
7676 int i;
7677
7678 /* 82598 have a static priority to TC mapping that can not
7679 * be changed so no validation is needed.
7680 */
7681 if (hw->mac.type == ixgbe_mac_82598EB)
7682 return;
7683
7684 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7685 rsave = reg;
7686
7687 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7688 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7689
7690 /* If up2tc is out of bounds default to zero */
7691 if (up2tc > tc)
7692 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7693 }
7694
7695 if (reg != rsave)
7696 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7697
7698 return;
7699}
7700
02debdc9
AD		 7701/**
7702 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7703 * @adapter: Pointer to adapter struct
7704 *
7705 * Populate the netdev user priority to tc map
7706 */
7707static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7708{
7709 struct net_device *dev = adapter->netdev;
7710 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7711 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7712 u8 prio;
7713
7714 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7715 u8 tc = 0;
7716
7717 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7718 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7719 else if (ets)
7720 tc = ets->prio_tc[prio];
7721
7722 netdev_set_prio_tc_map(dev, prio, tc);
7723 }
7724}
7725
cca73c59 7726#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7727/**
7728 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7729 *
7730 * @netdev: net device to configure
7731 * @tc: number of traffic classes to enable
7732 */
7733int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7734{
8b1c0b24
JF		 7735 struct ixgbe_adapter *adapter = netdev_priv(dev);
7736 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7737 bool pools;
8b1c0b24 7738
8b1c0b24 7739 /* Hardware supports up to 8 traffic classes */
4de2a022 7740 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7741 (hw->mac.type == ixgbe_mac_82598EB &&
7742 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7743 return -EINVAL;
7744
2a47fa45
JF		 7745 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7746 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7747 return -EBUSY;
7748
8b1c0b24 7749 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7750 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7751 * hardware is not flexible enough to do this dynamically.
7752 */
7753 if (netif_running(dev))
7754 ixgbe_close(dev);
7755 ixgbe_clear_interrupt_scheme(adapter);
7756
cca73c59 7757#ifdef CONFIG_IXGBE_DCB
e7589eab 7758 if (tc) {
8b1c0b24 7759 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7760 ixgbe_set_prio_tc_map(adapter);
7761
e7589eab 7762 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7763
943561d3
AD		 7764 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7765 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7766 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7767 }
e7589eab 7768 } else {
8b1c0b24 7769 netdev_reset_tc(dev);
02debdc9 7770
943561d3
AD		 7771 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7772 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7773
7774 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7775
7776 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7777 adapter->dcb_cfg.pfc_mode_enable = false;
7778 }
7779
8b1c0b24 7780 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7781
7782#endif /* CONFIG_IXGBE_DCB */
7783 ixgbe_init_interrupt_scheme(adapter);
7784
8b1c0b24 7785 if (netif_running(dev))
cca73c59 7786 return ixgbe_open(dev);
8b1c0b24
JF		 7787
7788 return 0;
7789}
de1036b1 7790
da36b647
GR		 7791#ifdef CONFIG_PCI_IOV
7792void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7793{
7794 struct net_device *netdev = adapter->netdev;
7795
7796 rtnl_lock();
da36b647 7797 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7798 rtnl_unlock();
7799}
7800
7801#endif
082757af
DS		 7802void ixgbe_do_reset(struct net_device *netdev)
7803{
7804 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7805
7806 if (netif_running(netdev))
7807 ixgbe_reinit_locked(adapter);
7808 else
7809 ixgbe_reset(adapter);
7810}
7811
c8f44aff 7812static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7813 netdev_features_t features)
082757af
DS		 7814{
7815 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7816
082757af 7817 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7818 if (!(features & NETIF_F_RXCSUM))
7819 features &= ~NETIF_F_LRO;
082757af 7820
567d2de2
AD		 7821 /* Turn off LRO if not RSC capable */
7822 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7823 features &= ~NETIF_F_LRO;
8e2813f5 7824
567d2de2 7825 return features;
082757af
DS		 7826}
7827
c8f44aff 7828static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7829 netdev_features_t features)
082757af
DS		 7830{
7831 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7832 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7833 bool need_reset = false;
7834
082757af 7835 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7836 if (!(features & NETIF_F_LRO)) {
7837 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7838 need_reset = true;
567d2de2
AD		 7839 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7840 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7841 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7842 if (adapter->rx_itr_setting == 1 ||
7843 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7844 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7845 need_reset = true;
7846 } else if ((changed ^ features) & NETIF_F_LRO) {
7847 e_info(probe, "rx-usecs set too low, "
7848 "disabling RSC\n");
082757af
DS		 7849 }
7850 }
7851
7852 /*
7853 * Check if Flow Director n-tuple support was enabled or disabled. If
7854 * the state changed, we need to reset.
7855 */
39cb681b
AD		 7856 switch (features & NETIF_F_NTUPLE) {
7857 case NETIF_F_NTUPLE:
567d2de2 7858 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7859 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7860 need_reset = true;
7861
567d2de2
AD		 7862 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7863 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7864 break;
7865 default:
7866 /* turn off perfect filters, enable ATR and reset */
7867 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7868 need_reset = true;
7869
7870 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7871
7872 /* We cannot enable ATR if SR-IOV is enabled */
7873 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7874 break;
7875
7876 /* We cannot enable ATR if we have 2 or more traffic classes */
7877 if (netdev_get_num_tc(netdev) > 1)
7878 break;
7879
7880 /* We cannot enable ATR if RSS is disabled */
7881 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7882 break;
7883
7884 /* A sample rate of 0 indicates ATR disabled */
7885 if (!adapter->atr_sample_rate)
7886 break;
7887
7888 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7889 break;
082757af
DS		 7890 }
7891
f646968f 7892 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7893 ixgbe_vlan_strip_enable(adapter);
7894 else
7895 ixgbe_vlan_strip_disable(adapter);
7896
3f2d1c0f
BG		 7897 if (changed & NETIF_F_RXALL)
7898 need_reset = true;
7899
567d2de2 7900 netdev->features = features;
082757af
DS		 7901 if (need_reset)
7902 ixgbe_do_reset(netdev);
7903
7904 return 0;
082757af
DS		 7905}
7906
3f207800
DS		 7907/**
7908 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
7909 * @dev: The port's netdev
7910 * @sa_family: Socket Family that VXLAN is notifiying us about
7911 * @port: New UDP port number that VXLAN started listening to
7912 **/
7913static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
7914 __be16 port)
7915{
7916 struct ixgbe_adapter *adapter = netdev_priv(dev);
7917 struct ixgbe_hw *hw = &adapter->hw;
7918 u16 new_port = ntohs(port);
7919
7920 if (sa_family == AF_INET6)
7921 return;
7922
7923 if (adapter->vxlan_port == new_port) {
7924 netdev_info(dev, "Port %d already offloaded\n", new_port);
7925 return;
7926 }
7927
7928 if (adapter->vxlan_port) {
7929 netdev_info(dev,
7930 "Hit Max num of UDP ports, not adding port %d\n",
7931 new_port);
7932 return;
7933 }
7934
7935 adapter->vxlan_port = new_port;
7936 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
7937}
7938
7939/**
7940 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
7941 * @dev: The port's netdev
7942 * @sa_family: Socket Family that VXLAN is notifying us about
7943 * @port: UDP port number that VXLAN stopped listening to
7944 **/
7945static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
7946 __be16 port)
7947{
7948 struct ixgbe_adapter *adapter = netdev_priv(dev);
7949 struct ixgbe_hw *hw = &adapter->hw;
7950 u16 new_port = ntohs(port);
7951
7952 if (sa_family == AF_INET6)
7953 return;
7954
7955 if (adapter->vxlan_port != new_port) {
7956 netdev_info(dev, "Port %d was not found, not deleting\n",
7957 new_port);
7958 return;
7959 }
7960
7961 adapter->vxlan_port = 0;
7962 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 0);
7963}
7964
edc7d573 7965static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7966 struct net_device *dev,
f6f6424b 7967 const unsigned char *addr, u16 vid,
0f4b0add
JF		 7968 u16 flags)
7969{
bcfd3432 7970 /* guarantee we can provide a unique filter for the unicast address */
46acc460 7971 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 7972 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
7973 return -ENOMEM;
0f4b0add
JF		 7974 }
7975
f6f6424b 7976 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 7977}
7978
219efe97
DS		 7979/**
7980 * ixgbe_configure_bridge_mode - set various bridge modes
7981 * @adapter - the private structure
7982 * @mode - requested bridge mode
7983 *
7984 * Configure some settings require for various bridge modes.
7985 **/
7986static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
7987 __u16 mode)
7988{
6d4c96ad
DS		 7989 struct ixgbe_hw *hw = &adapter->hw;
7990 unsigned int p, num_pools;
7991 u32 vmdctl;
7992
219efe97
DS		 7993 switch (mode) {
7994 case BRIDGE_MODE_VEPA:
6d4c96ad 7995 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 7996 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 7997
7998 /* must enable Rx switching replication to allow multicast
7999 * packet reception on all VFs, and to enable source address
8000 * pruning.
8001 */
8002 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8003 vmdctl |= IXGBE_VT_CTL_REPLEN;
8004 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8005
8006 /* enable Rx source address pruning. Note, this requires
8007 * replication to be enabled or else it does nothing.
8008 */
8009 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8010 for (p = 0; p < num_pools; p++) {
8011 if (hw->mac.ops.set_source_address_pruning)
8012 hw->mac.ops.set_source_address_pruning(hw,
8013 true,
8014 p);
8015 }
219efe97
DS		 8016 break;
8017 case BRIDGE_MODE_VEB:
6d4c96ad 8018 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8019 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8020 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8021
8022 /* disable Rx switching replication unless we have SR-IOV
8023 * virtual functions
8024 */
8025 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8026 if (!adapter->num_vfs)
8027 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8028 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8029
8030 /* disable Rx source address pruning, since we don't expect to
8031 * be receiving external loopback of our transmitted frames.
8032 */
8033 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8034 for (p = 0; p < num_pools; p++) {
8035 if (hw->mac.ops.set_source_address_pruning)
8036 hw->mac.ops.set_source_address_pruning(hw,
8037 false,
8038 p);
8039 }
219efe97
DS		 8040 break;
8041 default:
8042 return -EINVAL;
8043 }
8044
8045 adapter->bridge_mode = mode;
8046
8047 e_info(drv, "enabling bridge mode: %s\n",
8048 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8049
8050 return 0;
8051}
8052
815cccbf 8053static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8054 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8055{
8056 struct ixgbe_adapter *adapter = netdev_priv(dev);
8057 struct nlattr *attr, *br_spec;
8058 int rem;
8059
8060 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8061 return -EOPNOTSUPP;
8062
8063 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8064 if (!br_spec)
8065 return -EINVAL;
815cccbf
JF		 8066
8067 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8068 int status;
815cccbf 8069 __u16 mode;
815cccbf
JF		 8070
8071 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8072 continue;
8073
b7c1a314
TG		 8074 if (nla_len(attr) < sizeof(mode))
8075 return -EINVAL;
8076
815cccbf 8077 mode = nla_get_u16(attr);
219efe97
DS		 8078 status = ixgbe_configure_bridge_mode(adapter, mode);
8079 if (status)
8080 return status;
aa2bacb6
DS		 8081
8082 break;
815cccbf
JF		 8083 }
8084
8085 return 0;
8086}
8087
8088static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8089 struct net_device *dev,
46c264da 8090 u32 filter_mask, int nlflags)
815cccbf
JF		 8091{
8092 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8093
8094 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8095 return 0;
8096
aa2bacb6 8097 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8098 adapter->bridge_mode, 0, 0, nlflags,
8099 filter_mask, NULL);
815cccbf
JF		 8100}
8101
2a47fa45
JF		 8102static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8103{
8104 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8105 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8106 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8107 unsigned int limit;
2a47fa45
JF		 8108 int pool, err;
8109
aac2f1bf
JK		 8110 /* Hardware has a limited number of available pools. Each VF, and the
8111 * PF require a pool. Check to ensure we don't attempt to use more
8112 * then the available number of pools.
8113 */
8114 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8115 return ERR_PTR(-EINVAL);
8116
219354d4
JF		 8117#ifdef CONFIG_RPS
8118 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8119 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8120 vdev->name);
8121 return ERR_PTR(-EINVAL);
8122 }
8123#endif
2a47fa45 8124 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8125 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8126 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8127 netdev_info(pdev,
8128 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8129 pdev->name);
8130 return ERR_PTR(-EINVAL);
8131 }
8132
8133 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8134 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8135 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8136 return ERR_PTR(-EBUSY);
8137
8138 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
8139 if (!fwd_adapter)
8140 return ERR_PTR(-ENOMEM);
8141
8142 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8143 adapter->num_rx_pools++;
8144 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8145 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8146
8147 /* Enable VMDq flag so device will be set in VM mode */
8148 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8149 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8150 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8151
8152 /* Force reinit of ring allocation with VMDQ enabled */
8153 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8154 if (err)
8155 goto fwd_add_err;
8156 fwd_adapter->pool = pool;
8157 fwd_adapter->real_adapter = adapter;
8158 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8159 if (err)
8160 goto fwd_add_err;
8161 netif_tx_start_all_queues(vdev);
8162 return fwd_adapter;
8163fwd_add_err:
8164 /* unwind counter and free adapter struct */
8165 netdev_info(pdev,
8166 "%s: dfwd hardware acceleration failed\n", vdev->name);
8167 clear_bit(pool, &adapter->fwd_bitmask);
8168 adapter->num_rx_pools--;
8169 kfree(fwd_adapter);
8170 return ERR_PTR(err);
8171}
8172
8173static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8174{
8175 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8176 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8177 unsigned int limit;
2a47fa45
JF		 8178
8179 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8180 adapter->num_rx_pools--;
8181
51f3773b
JF		 8182 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8183 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8184 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8185 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8186 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8187 fwd_adapter->pool, adapter->num_rx_pools,
8188 fwd_adapter->rx_base_queue,
8189 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8190 adapter->fwd_bitmask);
8191 kfree(fwd_adapter);
8192}
8193
0edc3527 8194static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8195 .ndo_open = ixgbe_open,
0edc3527 8196 .ndo_stop = ixgbe_close,
00829823 8197 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8198 .ndo_select_queue = ixgbe_select_queue,
581330ba 8199 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8200 .ndo_validate_addr = eth_validate_addr,
8201 .ndo_set_mac_address = ixgbe_set_mac,
8202 .ndo_change_mtu = ixgbe_change_mtu,
8203 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8204 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8205 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8206 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8207 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8208 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8209 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8210 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8211 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
7f01648a 8212 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8213 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 8214#ifdef CONFIG_IXGBE_DCB
24095aa3 8215 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 8216#endif
0edc3527
SH		 8217#ifdef CONFIG_NET_POLL_CONTROLLER
8218 .ndo_poll_controller = ixgbe_netpoll,
8219#endif
e0d1095a 8220#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8221 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8222#endif
332d4a7d
YZ		 8223#ifdef IXGBE_FCOE
8224 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8225 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8226 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8227 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8228 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8229 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8230 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8231#endif /* IXGBE_FCOE */
082757af
DS		 8232 .ndo_set_features = ixgbe_set_features,
8233 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8234 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8235 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8236 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8237 .ndo_dfwd_add_station = ixgbe_fwd_add,
8238 .ndo_dfwd_del_station = ixgbe_fwd_del,
3f207800
DS		 8239 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8240 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
0edc3527
SH		 8241};
8242
e027d1ae
JK		 8243/**
8244 * ixgbe_enumerate_functions - Get the number of ports this device has
8245 * @adapter: adapter structure
8246 *
8247 * This function enumerates the phsyical functions co-located on a single slot,
8248 * in order to determine how many ports a device has. This is most useful in
8249 * determining the required GT/s of PCIe bandwidth necessary for optimal
8250 * performance.
8251 **/
8252static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8253{
caafb95d 8254 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8255 int physfns = 0;
8256
f1f96579
JK		 8257 /* Some cards can not use the generic count PCIe functions method,
8258 * because they are behind a parent switch, so we hardcode these with
8259 * the correct number of functions.
e027d1ae 8260 */
8818970d 8261 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8262 physfns = 4;
8818970d
JK		 8263
8264 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8265 /* don't count virtual functions */
caafb95d
JK		 8266 if (entry->is_virtfn)
8267 continue;
8268
8269 /* When the devices on the bus don't all match our device ID,
8270 * we can't reliably determine the correct number of
8271 * functions. This can occur if a function has been direct
8272 * attached to a virtual machine using VT-d, for example. In
8273 * this case, simply return -1 to indicate this.
8274 */
8275 if ((entry->vendor != pdev->vendor) ||
8276 (entry->device != pdev->device))
8277 return -1;
8278
8279 physfns++;
e027d1ae
JK		 8280 }
8281
8282 return physfns;
8283}
8284
8e2813f5
JK		 8285/**
8286 * ixgbe_wol_supported - Check whether device supports WoL
8287 * @hw: hw specific details
8288 * @device_id: the device ID
8289 * @subdev_id: the subsystem device ID
8290 *
8291 * This function is used by probe and ethtool to determine
8292 * which devices have WoL support
8293 *
8294 **/
8295int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8296 u16 subdevice_id)
8297{
8298 struct ixgbe_hw *hw = &adapter->hw;
8299 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8300 int is_wol_supported = 0;
8301
8302 switch (device_id) {
8303 case IXGBE_DEV_ID_82599_SFP:
8304 /* Only these subdevices could supports WOL */
8305 switch (subdevice_id) {
87557440 8306 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8307 case IXGBE_SUBDEV_ID_82599_560FLR:
8308 /* only support first port */
8309 if (hw->bus.func != 0)
8310 break;
5700ff26 8311 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8312 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8313 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8314 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8315 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8316 is_wol_supported = 1;
8317 break;
8318 }
8319 break;
5daebbb0
DS		 8320 case IXGBE_DEV_ID_82599EN_SFP:
8321 /* Only this subdevice supports WOL */
8322 switch (subdevice_id) {
8323 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8324 is_wol_supported = 1;
8325 break;
8326 }
8327 break;
8e2813f5
JK		 8328 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8329 /* All except this subdevice support WOL */
8330 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8331 is_wol_supported = 1;
8332 break;
8333 case IXGBE_DEV_ID_82599_KX4:
8334 is_wol_supported = 1;
8335 break;
8336 case IXGBE_DEV_ID_X540T:
df376f0d 8337 case IXGBE_DEV_ID_X540T1:
df8c26fd
DS		 8338 case IXGBE_DEV_ID_X550T:
8339 case IXGBE_DEV_ID_X550EM_X_KX4:
8340 case IXGBE_DEV_ID_X550EM_X_KR:
8341 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 8342 /* check eeprom to see if enabled wol */
8343 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8344 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8345 (hw->bus.func == 0))) {
8346 is_wol_supported = 1;
8347 }
8348 break;
8349 }
8350
8351 return is_wol_supported;
8352}
8353
c762dff2
MP		 8354/**
8355 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8356 * @adapter: Pointer to adapter struct
8357 */
8358static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8359{
8360#ifdef CONFIG_OF
8361 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8362 struct ixgbe_hw *hw = &adapter->hw;
8363 const unsigned char *addr;
8364
8365 addr = of_get_mac_address(dp);
8366 if (addr) {
8367 ether_addr_copy(hw->mac.perm_addr, addr);
8368 return;
8369 }
8370#endif /* CONFIG_OF */
8371
8372#ifdef CONFIG_SPARC
8373 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8374#endif /* CONFIG_SPARC */
8375}
8376
9a799d71
AK		 8377/**
8378 * ixgbe_probe - Device Initialization Routine
8379 * @pdev: PCI device information struct
8380 * @ent: entry in ixgbe_pci_tbl
8381 *
8382 * Returns 0 on success, negative on failure
8383 *
8384 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8385 * The OS initialization, configuring of the adapter private structure,
8386 * and a hardware reset occur.
8387 **/
1dd06ae8 8388static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8389{
8390 struct net_device *netdev;
8391 struct ixgbe_adapter *adapter = NULL;
8392 struct ixgbe_hw *hw;
8393 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8394 int i, err, pci_using_dac, expected_gts;
d3cb9869 8395 unsigned int indices = MAX_TX_QUEUES;
289700db 8396 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8397 bool disable_dev = false;
eacd73f7
YZ		 8398#ifdef IXGBE_FCOE
8399 u16 device_caps;
8400#endif
289700db 8401 u32 eec;
9a799d71 8402
bded64a7
AG		 8403 /* Catch broken hardware that put the wrong VF device ID in
8404 * the PCIe SR-IOV capability.
8405 */
8406 if (pdev->is_virtfn) {
8407 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8408 pci_name(pdev), pdev->vendor, pdev->device);
8409 return -EINVAL;
8410 }
8411
9ce77666 8412 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8413 if (err)
8414 return err;
8415
f5f2eda8 8416 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8417 pci_using_dac = 1;
8418 } else {
f5f2eda8 8419 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8420 if (err) {
f5f2eda8
RK		 8421 dev_err(&pdev->dev,
8422 "No usable DMA configuration, aborting\n");
8423 goto err_dma;
9a799d71
AK		 8424 }
8425 pci_using_dac = 0;
8426 }
8427
9ce77666 8428 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8429 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8430 if (err) {
b8bc0421
DC		 8431 dev_err(&pdev->dev,
8432 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8433 goto err_pci_reg;
8434 }
8435
19d5afd4 8436 pci_enable_pcie_error_reporting(pdev);
6fabd715 8437
9a799d71 8438 pci_set_master(pdev);
fb3b27bc 8439 pci_save_state(pdev);
9a799d71 8440
d3cb9869 8441 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8442#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8443 /* 8 TC w/ 4 queues per TC */
8444 indices = 4 * MAX_TRAFFIC_CLASS;
8445#else
8446 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8447#endif
d3cb9869 8448 }
e901acd6 8449
c85a2618 8450 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8451 if (!netdev) {
8452 err = -ENOMEM;
8453 goto err_alloc_etherdev;
8454 }
8455
9a799d71
AK		 8456 SET_NETDEV_DEV(netdev, &pdev->dev);
8457
9a799d71
AK		 8458 adapter = netdev_priv(netdev);
8459
8460 adapter->netdev = netdev;
8461 adapter->pdev = pdev;
8462 hw = &adapter->hw;
8463 hw->back = adapter;
b3f4d599 8464 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8465
05857980 8466 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8467 pci_resource_len(pdev, 0));
2a1a091c 8468 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8469 if (!hw->hw_addr) {
8470 err = -EIO;
8471 goto err_ioremap;
8472 }
8473
0edc3527 8474 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8475 ixgbe_set_ethtool_ops(netdev);
9a799d71 8476 netdev->watchdog_timeo = 5 * HZ;
339de30f 8477 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8478
9a799d71
AK		 8479 /* Setup hw api */
8480 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8481 hw->mac.type = ii->mac;
9a900eca 8482 hw->mvals = ii->mvals;
9a799d71 8483
c44ade9e
JB		 8484 /* EEPROM */
8485 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
9a900eca 8486 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 8487 if (ixgbe_removed(hw->hw_addr)) {
8488 err = -EIO;
8489 goto err_ioremap;
8490 }
c44ade9e
JB		 8491 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8492 if (!(eec & (1 << 8)))
8493 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8494
8495 /* PHY */
8496 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8497 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8498 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8499 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8500 hw->phy.mdio.mmds = 0;
8501 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8502 hw->phy.mdio.dev = netdev;
8503 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8504 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8505
8ca783ab 8506 ii->get_invariants(hw);
9a799d71
AK		 8507
8508 /* setup the private structure */
8509 err = ixgbe_sw_init(adapter);
8510 if (err)
8511 goto err_sw_init;
8512
e86bff0e 8513 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8514 switch (adapter->hw.mac.type) {
8515 case ixgbe_mac_82599EB:
8516 case ixgbe_mac_X540:
9a75a1ac
DS		 8517 case ixgbe_mac_X550:
8518 case ixgbe_mac_X550EM_x:
e86bff0e 8519 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8520 break;
8521 default:
8522 break;
8523 }
e86bff0e 8524
bf069c97
DS		 8525 /*
8526 * If there is a fan on this device and it has failed log the
8527 * failure.
8528 */
8529 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8530 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8531 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8532 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8533 }
8534
8ef78adc
PWJ		 8535 if (allow_unsupported_sfp)
8536 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8537
c44ade9e 8538 /* reset_hw fills in the perm_addr as well */
119fc60a 8539 hw->phy.reset_if_overtemp = true;
c44ade9e 8540 err = hw->mac.ops.reset_hw(hw);
119fc60a 8541 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8542 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8543 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8544 err = 0;
8545 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8546 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8547 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8548 goto err_sw_init;
8549 } else if (err) {
849c4542 8550 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8551 goto err_sw_init;
8552 }
8553
99d74487 8554#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8555 /* SR-IOV not supported on the 82598 */
8556 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8557 goto skip_sriov;
8558 /* Mailbox */
8559 ixgbe_init_mbx_params_pf(hw);
8560 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8561 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8562 ixgbe_enable_sriov(adapter);
60a1a680 8563skip_sriov:
1cdd1ec8 8564
99d74487 8565#endif
396e799c 8566 netdev->features = NETIF_F_SG |
e8e9f696 8567 NETIF_F_IP_CSUM |
082757af 8568 NETIF_F_IPV6_CSUM |
f646968f
PM		 8569 NETIF_F_HW_VLAN_CTAG_TX |
8570 NETIF_F_HW_VLAN_CTAG_RX |
082757af
DS		 8571 NETIF_F_TSO |
8572 NETIF_F_TSO6 |
082757af 8573 NETIF_F_RXHASH |
8bf1264d 8574 NETIF_F_RXCSUM;
9a799d71 8575
8bf1264d 8576 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8577
58be7666
DS		 8578 switch (adapter->hw.mac.type) {
8579 case ixgbe_mac_82599EB:
8580 case ixgbe_mac_X540:
9a75a1ac
DS		 8581 case ixgbe_mac_X550:
8582 case ixgbe_mac_X550EM_x:
45a5ead0 8583 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8584 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8585 NETIF_F_NTUPLE;
58be7666
DS		 8586 break;
8587 default:
8588 break;
8589 }
45a5ead0 8590
3f2d1c0f 8591 netdev->hw_features |= NETIF_F_RXALL;
87031c0d 8592 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3f2d1c0f 8593
ad31c402
JK		 8594 netdev->vlan_features |= NETIF_F_TSO;
8595 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8596 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8597 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8598 netdev->vlan_features |= NETIF_F_SG;
8599
01789349 8600 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8601 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8602
3f207800
DS		 8603 switch (adapter->hw.mac.type) {
8604 case ixgbe_mac_X550:
8605 case ixgbe_mac_X550EM_x:
8606 netdev->hw_enc_features |= NETIF_F_RXCSUM;
8607 break;
8608 default:
8609 break;
8610 }
8611
7a6b6f51 8612#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8613 netdev->dcbnl_ops = &dcbnl_ops;
8614#endif
8615
eacd73f7 8616#ifdef IXGBE_FCOE
0d551589 8617 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8618 unsigned int fcoe_l;
8619
eacd73f7
YZ		 8620 if (hw->mac.ops.get_device_caps) {
8621 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8622 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8623 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8624 }
7c8ae65a 8625
d3cb9869
AD		 8626
8627 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8628 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8629
a58915c7
AD		 8630 netdev->features |= NETIF_F_FSO |
8631 NETIF_F_FCOE_CRC;
8632
7c8ae65a
AD		 8633 netdev->vlan_features |= NETIF_F_FSO |
8634 NETIF_F_FCOE_CRC |
8635 NETIF_F_FCOE_MTU;
5e09d7f6 8636 }
eacd73f7 8637#endif /* IXGBE_FCOE */
7b872a55 8638 if (pci_using_dac) {
9a799d71 8639 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8640 netdev->vlan_features |= NETIF_F_HIGHDMA;
8641 }
9a799d71 8642
082757af
DS		 8643 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8644 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8645 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8646 netdev->features |= NETIF_F_LRO;
8647
9a799d71 8648 /* make sure the EEPROM is good */
c44ade9e 8649 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8650 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8651 err = -EIO;
35937c05 8652 goto err_sw_init;
9a799d71
AK		 8653 }
8654
c762dff2
MP		 8655 ixgbe_get_platform_mac_addr(adapter);
8656
9a799d71 8657 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8658
aaeb6cdf 8659 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8660 e_dev_err("invalid MAC address\n");
9a799d71 8661 err = -EIO;
35937c05 8662 goto err_sw_init;
9a799d71
AK		 8663 }
8664
5d7daa35
JK		 8665 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8666
7086400d 8667 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8668 (unsigned long) adapter);
9a799d71 8669
58cf663f
MR		 8670 if (ixgbe_removed(hw->hw_addr)) {
8671 err = -EIO;
8672 goto err_sw_init;
8673 }
7086400d 8674 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8675 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8676 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8677
021230d4
AV		 8678 err = ixgbe_init_interrupt_scheme(adapter);
8679 if (err)
8680 goto err_sw_init;
9a799d71 8681
8e2813f5 8682 /* WOL not supported for all devices */
c23f5b6b 8683 adapter->wol = 0;
8e2813f5 8684 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8685 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8686 pdev->subsystem_device);
6b92b0ba 8687 if (hw->wol_enabled)
9417c464 8688 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8689
e8e26350
PW		 8690 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8691
15e5209f
ET		 8692 /* save off EEPROM version number */
8693 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8694 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8695
04f165ef
PW		 8696 /* pick up the PCI bus settings for reporting later */
8697 hw->mac.ops.get_bus_info(hw);
e027d1ae 8698 if (ixgbe_pcie_from_parent(hw))
b8e82001 8699 ixgbe_get_parent_bus_info(adapter);
04f165ef 8700
e027d1ae
JK		 8701 /* calculate the expected PCIe bandwidth required for optimal
8702 * performance. Note that some older parts will never have enough
8703 * bandwidth due to being older generation PCIe parts. We clamp these
8704 * parts to ensure no warning is displayed if it can't be fixed.
8705 */
8706 switch (hw->mac.type) {
8707 case ixgbe_mac_82598EB:
8708 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8709 break;
8710 default:
8711 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8712 break;
0c254d86 8713 }
caafb95d
JK		 8714
8715 /* don't check link if we failed to enumerate functions */
8716 if (expected_gts > 0)
8717 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8718
339de30f 8719 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8720 if (err)
339de30f 8721 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8722 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8723 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8724 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8725 part_str);
6a2aae5a
JK		 8726 else
8727 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8728 hw->mac.type, hw->phy.type, part_str);
8729
8730 e_dev_info("%pM\n", netdev->dev_addr);
8731
9a799d71 8732 /* reset the hardware with the new settings */
794caeb2 8733 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8734 if (err == IXGBE_ERR_EEPROM_VERSION) {
8735 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8736 e_dev_warn("This device is a pre-production adapter/LOM. "
8737 "Please be aware there may be issues associated "
8738 "with your hardware. If you are experiencing "
8739 "problems please contact your Intel or hardware "
8740 "representative who provided you with this "
8741 "hardware.\n");
794caeb2 8742 }
9a799d71
AK		 8743 strcpy(netdev->name, "eth%d");
8744 err = register_netdev(netdev);
8745 if (err)
8746 goto err_register;
8747
0fb6a55c
ET		 8748 pci_set_drvdata(pdev, adapter);
8749
ec74a471
ET		 8750 /* power down the optics for 82599 SFP+ fiber */
8751 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8752 hw->mac.ops.disable_tx_laser(hw);
8753
54386467
JB		 8754 /* carrier off reporting is important to ethtool even BEFORE open */
8755 netif_carrier_off(netdev);
8756
5dd2d332 8757#ifdef CONFIG_IXGBE_DCA
652f093f 8758 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8759 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8760 ixgbe_setup_dca(adapter);
8761 }
8762#endif
1cdd1ec8 8763 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8764 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8765 for (i = 0; i < adapter->num_vfs; i++)
8766 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8767 }
8768
2466dd9c
JK		 8769 /* firmware requires driver version to be 0xFFFFFFFF
8770 * since os does not support feature
8771 */
9612de92 8772 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8773 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8774 0xFF);
9612de92 8775
0365e6e4
PW		 8776 /* add san mac addr to netdev */
8777 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8778
ea81875a 8779 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 8780
1210982b 8781#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8782 if (ixgbe_sysfs_init(adapter))
8783 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8784#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8785
00949167 8786 ixgbe_dbg_adapter_init(adapter);
00949167 8787
d1a35ee2
ET		 8788 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8789 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8790 hw->mac.ops.setup_link(hw,
8791 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8792 true);
8793
9a799d71
AK		 8794 return 0;
8795
8796err_register:
5eba3699 8797 ixgbe_release_hw_control(adapter);
7a921c93 8798 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8799err_sw_init:
99d74487 8800 ixgbe_disable_sriov(adapter);
7086400d 8801 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8802 iounmap(adapter->io_addr);
5d7daa35 8803 kfree(adapter->mac_table);
9a799d71 8804err_ioremap:
b5b2ffc0 8805 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8806 free_netdev(netdev);
8807err_alloc_etherdev:
e8e9f696
JP		 8808 pci_release_selected_regions(pdev,
8809 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8810err_pci_reg:
8811err_dma:
b5b2ffc0 8812 if (!adapter || disable_dev)
41c62843 8813 pci_disable_device(pdev);
9a799d71
AK		 8814 return err;
8815}
8816
8817/**
8818 * ixgbe_remove - Device Removal Routine
8819 * @pdev: PCI device information struct
8820 *
8821 * ixgbe_remove is called by the PCI subsystem to alert the driver
8822 * that it should release a PCI device. The could be caused by a
8823 * Hot-Plug event, or because the driver is going to be removed from
8824 * memory.
8825 **/
9f9a12f8 8826static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8827{
c60fbb00 8828 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 8829 struct net_device *netdev;
b5b2ffc0 8830 bool disable_dev;
9a799d71 8831
0fb6a55c
ET		 8832 /* if !adapter then we already cleaned up in probe */
8833 if (!adapter)
8834 return;
8835
8836 netdev = adapter->netdev;
00949167 8837 ixgbe_dbg_adapter_exit(adapter);
00949167 8838
09f40aed 8839 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8840 cancel_work_sync(&adapter->service_task);
9a799d71 8841
3a6a4eda 8842
5dd2d332 8843#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8844 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8845 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8846 dca_remove_requester(&pdev->dev);
8847 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8848 }
8849
8850#endif
1210982b 8851#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8852 ixgbe_sysfs_exit(adapter);
1210982b 8853#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8854
0365e6e4
PW		 8855 /* remove the added san mac */
8856 ixgbe_del_sanmac_netdev(netdev);
8857
c4900be0
DS		 8858 if (netdev->reg_state == NETREG_REGISTERED)
8859 unregister_netdev(netdev);
9a799d71 8860
da36b647
GR		 8861#ifdef CONFIG_PCI_IOV
8862 /*
8863 * Only disable SR-IOV on unload if the user specified the now
8864 * deprecated max_vfs module parameter.
8865 */
8866 if (max_vfs)
8867 ixgbe_disable_sriov(adapter);
8868#endif
7a921c93 8869 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8870
021230d4 8871 ixgbe_release_hw_control(adapter);
9a799d71 8872
2b1588c3
AD		 8873#ifdef CONFIG_DCB
8874 kfree(adapter->ixgbe_ieee_pfc);
8875 kfree(adapter->ixgbe_ieee_ets);
8876
8877#endif
2a1a091c 8878 iounmap(adapter->io_addr);
9ce77666 8879 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8880 IORESOURCE_MEM));
9a799d71 8881
849c4542 8882 e_dev_info("complete\n");
021230d4 8883
5d7daa35 8884 kfree(adapter->mac_table);
b5b2ffc0 8885 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8886 free_netdev(netdev);
8887
19d5afd4 8888 pci_disable_pcie_error_reporting(pdev);
6fabd715 8889
b5b2ffc0 8890 if (disable_dev)
41c62843 8891 pci_disable_device(pdev);
9a799d71
AK		 8892}
8893
8894/**
8895 * ixgbe_io_error_detected - called when PCI error is detected
8896 * @pdev: Pointer to PCI device
8897 * @state: The current pci connection state
8898 *
8899 * This function is called after a PCI bus error affecting
8900 * this device has been detected.
8901 */
8902static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8903 pci_channel_state_t state)
9a799d71 8904{
c60fbb00
AD		 8905 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8906 struct net_device *netdev = adapter->netdev;
9a799d71 8907
83c61fa9 8908#ifdef CONFIG_PCI_IOV
14438464 8909 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8910 struct pci_dev *bdev, *vfdev;
8911 u32 dw0, dw1, dw2, dw3;
8912 int vf, pos;
8913 u16 req_id, pf_func;
8914
8915 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8916 adapter->num_vfs == 0)
8917 goto skip_bad_vf_detection;
8918
8919 bdev = pdev->bus->self;
62f87c0e 8920 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8921 bdev = bdev->bus->self;
8922
8923 if (!bdev)
8924 goto skip_bad_vf_detection;
8925
8926 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8927 if (!pos)
8928 goto skip_bad_vf_detection;
8929
14438464
MR		 8930 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8931 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8932 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8933 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8934 if (ixgbe_removed(hw->hw_addr))
8935 goto skip_bad_vf_detection;
83c61fa9
GR		 8936
8937 req_id = dw1 >> 16;
8938 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8939 if (!(req_id & 0x0080))
8940 goto skip_bad_vf_detection;
8941
8942 pf_func = req_id & 0x01;
8943 if ((pf_func & 1) == (pdev->devfn & 1)) {
8944 unsigned int device_id;
8945
8946 vf = (req_id & 0x7F) >> 1;
8947 e_dev_err("VF %d has caused a PCIe error\n", vf);
8948 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8949 "%8.8x\tdw3: %8.8x\n",
8950 dw0, dw1, dw2, dw3);
8951 switch (adapter->hw.mac.type) {
8952 case ixgbe_mac_82599EB:
8953 device_id = IXGBE_82599_VF_DEVICE_ID;
8954 break;
8955 case ixgbe_mac_X540:
8956 device_id = IXGBE_X540_VF_DEVICE_ID;
8957 break;
9a75a1ac
DS		 8958 case ixgbe_mac_X550:
8959 device_id = IXGBE_DEV_ID_X550_VF;
8960 break;
8961 case ixgbe_mac_X550EM_x:
8962 device_id = IXGBE_DEV_ID_X550EM_X_VF;
8963 break;
83c61fa9
GR		 8964 default:
8965 device_id = 0;
8966 break;
8967 }
8968
8969 /* Find the pci device of the offending VF */
36e90319 8970 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8971 while (vfdev) {
8972 if (vfdev->devfn == (req_id & 0xFF))
8973 break;
36e90319 8974 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8975 device_id, vfdev);
8976 }
8977 /*
8978 * There's a slim chance the VF could have been hot plugged,
8979 * so if it is no longer present we don't need to issue the
8980 * VFLR. Just clean up the AER in that case.
8981 */
8982 if (vfdev) {
9079e416 8983 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 8984 /* Free device reference count */
8985 pci_dev_put(vfdev);
83c61fa9
GR		 8986 }
8987
8988 pci_cleanup_aer_uncorrect_error_status(pdev);
8989 }
8990
8991 /*
8992 * Even though the error may have occurred on the other port
8993 * we still need to increment the vf error reference count for
8994 * both ports because the I/O resume function will be called
8995 * for both of them.
8996 */
8997 adapter->vferr_refcount++;
8998
8999 return PCI_ERS_RESULT_RECOVERED;
9000
9001skip_bad_vf_detection:
9002#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9003 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9004 return PCI_ERS_RESULT_DISCONNECT;
9005
41c62843 9006 rtnl_lock();
9a799d71
AK		 9007 netif_device_detach(netdev);
9008
41c62843
MR		 9009 if (state == pci_channel_io_perm_failure) {
9010 rtnl_unlock();
3044b8d1 9011 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9012 }
3044b8d1 9013
9a799d71
AK		 9014 if (netif_running(netdev))
9015 ixgbe_down(adapter);
41c62843
MR		 9016
9017 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9018 pci_disable_device(pdev);
9019 rtnl_unlock();
9a799d71 9020
b4617240 9021 /* Request a slot reset. */
9a799d71
AK		 9022 return PCI_ERS_RESULT_NEED_RESET;
9023}
9024
9025/**
9026 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9027 * @pdev: Pointer to PCI device
9028 *
9029 * Restart the card from scratch, as if from a cold-boot.
9030 */
9031static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9032{
c60fbb00 9033 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9034 pci_ers_result_t result;
9035 int err;
9a799d71 9036
9ce77666 9037 if (pci_enable_device_mem(pdev)) {
396e799c 9038 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9039 result = PCI_ERS_RESULT_DISCONNECT;
9040 } else {
4e857c58 9041 smp_mb__before_atomic();
41c62843 9042 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9043 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9044 pci_set_master(pdev);
9045 pci_restore_state(pdev);
c0e1f68b 9046 pci_save_state(pdev);
9a799d71 9047
dd4d8ca6 9048 pci_wake_from_d3(pdev, false);
9a799d71 9049
6fabd715 9050 ixgbe_reset(adapter);
88512539 9051 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9052 result = PCI_ERS_RESULT_RECOVERED;
9053 }
9054
9055 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9056 if (err) {
849c4542
ET		 9057 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9058 "failed 0x%0x\n", err);
6fabd715
PWJ		 9059 /* non-fatal, continue */
9060 }
9a799d71 9061
6fabd715 9062 return result;
9a799d71
AK		 9063}
9064
9065/**
9066 * ixgbe_io_resume - called when traffic can start flowing again.
9067 * @pdev: Pointer to PCI device
9068 *
9069 * This callback is called when the error recovery driver tells us that
9070 * its OK to resume normal operation.
9071 */
9072static void ixgbe_io_resume(struct pci_dev *pdev)
9073{
c60fbb00
AD		 9074 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9075 struct net_device *netdev = adapter->netdev;
9a799d71 9076
83c61fa9
GR		 9077#ifdef CONFIG_PCI_IOV
9078 if (adapter->vferr_refcount) {
9079 e_info(drv, "Resuming after VF err\n");
9080 adapter->vferr_refcount--;
9081 return;
9082 }
9083
9084#endif
c7ccde0f
AD		 9085 if (netif_running(netdev))
9086 ixgbe_up(adapter);
9a799d71
AK		 9087
9088 netif_device_attach(netdev);
9a799d71
AK		 9089}
9090
3646f0e5 9091static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9092 .error_detected = ixgbe_io_error_detected,
9093 .slot_reset = ixgbe_io_slot_reset,
9094 .resume = ixgbe_io_resume,
9095};
9096
9097static struct pci_driver ixgbe_driver = {
9098 .name = ixgbe_driver_name,
9099 .id_table = ixgbe_pci_tbl,
9100 .probe = ixgbe_probe,
9f9a12f8 9101 .remove = ixgbe_remove,
9a799d71
AK		 9102#ifdef CONFIG_PM
9103 .suspend = ixgbe_suspend,
9104 .resume = ixgbe_resume,
9105#endif
9106 .shutdown = ixgbe_shutdown,
da36b647 9107 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9108 .err_handler = &ixgbe_err_handler
9109};
9110
9111/**
9112 * ixgbe_init_module - Driver Registration Routine
9113 *
9114 * ixgbe_init_module is the first routine called when the driver is
9115 * loaded. All it does is register with the PCI subsystem.
9116 **/
9117static int __init ixgbe_init_module(void)
9118{
9119 int ret;
c7689578 9120 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9121 pr_info("%s\n", ixgbe_copyright);
9a799d71 9122
00949167 9123 ixgbe_dbg_init();
00949167 9124
f01fc1a8
JK		 9125 ret = pci_register_driver(&ixgbe_driver);
9126 if (ret) {
f01fc1a8 9127 ixgbe_dbg_exit();
f01fc1a8
JK		 9128 return ret;
9129 }
9130
5dd2d332 9131#ifdef CONFIG_IXGBE_DCA
bd0362dd 9132 dca_register_notify(&dca_notifier);
bd0362dd 9133#endif
5dd2d332 9134
f01fc1a8 9135 return 0;
9a799d71 9136}
b4617240 9137
9a799d71
AK		 9138module_init(ixgbe_init_module);
9139
9140/**
9141 * ixgbe_exit_module - Driver Exit Cleanup Routine
9142 *
9143 * ixgbe_exit_module is called just before the driver is removed
9144 * from memory.
9145 **/
9146static void __exit ixgbe_exit_module(void)
9147{
5dd2d332 9148#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9149 dca_unregister_notify(&dca_notifier);
9150#endif
9a799d71 9151 pci_unregister_driver(&ixgbe_driver);
00949167 9152
00949167 9153 ixgbe_dbg_exit();
9a799d71 9154}
bd0362dd 9155
5dd2d332 9156#ifdef CONFIG_IXGBE_DCA
bd0362dd 9157static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9158 void *p)
bd0362dd
JC		 9159{
9160 int ret_val;
9161
9162 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9163 __ixgbe_notify_dca);
bd0362dd
JC		 9164
9165 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9166}
b453368d 9167
5dd2d332 9168#endif /* CONFIG_IXGBE_DCA */
849c4542 9169
9a799d71
AK		 9170module_exit(ixgbe_exit_module);
9171
9172/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)