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dev_ioctl: split out ndo_eth_ioctl
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
51dce24b
JK		 1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
9a799d71
AK		 3
4#include <linux/types.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7#include <linux/netdevice.h>
8#include <linux/vmalloc.h>
9#include <linux/string.h>
10#include <linux/in.h>
a6b7a407 11#include <linux/interrupt.h>
9a799d71
AK		 12#include <linux/ip.h>
13#include <linux/tcp.h>
897ab156 14#include <linux/sctp.h>
60127865 15#include <linux/pkt_sched.h>
9a799d71 16#include <linux/ipv6.h>
5a0e3ad6 17#include <linux/slab.h>
9a799d71
AK		 18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
c762dff2 20#include <linux/etherdevice.h>
9a799d71 21#include <linux/ethtool.h>
01789349 22#include <linux/if.h>
9a799d71 23#include <linux/if_vlan.h>
2a47fa45 24#include <linux/if_macvlan.h>
815cccbf 25#include <linux/if_bridge.h>
70c71606 26#include <linux/prefetch.h>
92470808
JF		 27#include <linux/bpf.h>
28#include <linux/bpf_trace.h>
29#include <linux/atomic.h>
98fa15f3 30#include <linux/numa.h>
34a2a3b8 31#include <generated/utsrelease.h>
eacd73f7 32#include <scsi/fc/fc_fcoe.h>
b3a49557 33#include <net/udp_tunnel.h>
b82b17d9
JF		 34#include <net/pkt_cls.h>
35#include <net/tc_act/tc_gact.h>
947f8a45 36#include <net/tc_act/tc_mirred.h>
9f3c7504 37#include <net/vxlan.h>
2a20525b 38#include <net/mpls.h>
7117132b 39#include <net/xdp_sock_drv.h>
f39b683d 40#include <net/xfrm.h>
9a799d71
AK		 41
42#include "ixgbe.h"
43#include "ixgbe_common.h"
ee5f784a 44#include "ixgbe_dcb_82599.h"
8fa10ef0 45#include "ixgbe_phy.h"
1cdd1ec8 46#include "ixgbe_sriov.h"
b82b17d9 47#include "ixgbe_model.h"
46515fdb 48#include "ixgbe_txrx_common.h"
9a799d71
AK		 49
50char ixgbe_driver_name[] = "ixgbe";
9c8eb720 51static const char ixgbe_driver_string[] =
e8e9f696 52 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 53#ifdef IXGBE_FCOE
ea81875a
NP		 54char ixgbe_default_device_descr[] =
55 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 56#else
57static char ixgbe_default_device_descr[] =
58 "Intel(R) 10 Gigabit Network Connection";
59#endif
a52055e0 60static const char ixgbe_copyright[] =
49425dfc 61 "Copyright (c) 1999-2016 Intel Corporation.";
9a799d71 62
f44e751b
DS		 63static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
64
9a799d71 65static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 66 [board_82598] = &ixgbe_82598_info,
67 [board_82599] = &ixgbe_82599_info,
68 [board_X540] = &ixgbe_X540_info,
69 [board_X550] = &ixgbe_X550_info,
70 [board_X550EM_x] = &ixgbe_X550EM_x_info,
8dc963e1 71 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info,
49425dfc 72 [board_x550em_a] = &ixgbe_x550em_a_info,
b3eb4e18 73 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info,
9a799d71
AK		 74};
75
76/* ixgbe_pci_tbl - PCI Device ID Table
77 *
78 * Wildcard entries (PCI_ANY_ID) should come last
79 * Last entry must be all 0s
80 *
81 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
82 * Class, Class Mask, private data (not used) }
83 */
9baa3c34 84static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
a711ad89 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
6a14ee0c 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
18e01ee7 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x},
6a14ee0c 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
8dc963e1 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw},
f572b2c4
MR		 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
49425dfc 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
200157c2
MR		 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
92ed8430 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
2d40cd17 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
b3eb4e18
MR		 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw },
9a799d71
AK		 132 /* required last entry */
133 {0, }
134};
135MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
136
5dd2d332 137#ifdef CONFIG_IXGBE_DCA
bd0362dd 138static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 139 void *p);
bd0362dd
JC		 140static struct notifier_block dca_notifier = {
141 .notifier_call = ixgbe_notify_dca,
142 .next = NULL,
143 .priority = 0
144};
145#endif
146
1cdd1ec8
GR		 147#ifdef CONFIG_PCI_IOV
148static unsigned int max_vfs;
149module_param(max_vfs, uint, 0);
e8e9f696 150MODULE_PARM_DESC(max_vfs,
170e8543 151 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 152#endif /* CONFIG_PCI_IOV */
153
8ef78adc
PWJ		 154static unsigned int allow_unsupported_sfp;
155module_param(allow_unsupported_sfp, uint, 0);
156MODULE_PARM_DESC(allow_unsupported_sfp,
157 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
158
b3f4d599 159#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
160static int debug = -1;
161module_param(debug, int, 0);
162MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
163
9a799d71
AK		 164MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
165MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
98674ebe 166MODULE_LICENSE("GPL v2");
9a799d71 167
780484d8
MR		 168static struct workqueue_struct *ixgbe_wq;
169
14438464 170static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
b3eb4e18 171static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *);
14438464 172
68ae7424
AD		 173static const struct net_device_ops ixgbe_netdev_ops;
174
175static bool netif_is_ixgbe(struct net_device *dev)
176{
177 return dev && (dev->netdev_ops == &ixgbe_netdev_ops);
178}
179
b8e82001
JK		 180static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
181 u32 reg, u16 *value)
182{
b8e82001
JK		 183 struct pci_dev *parent_dev;
184 struct pci_bus *parent_bus;
185
186 parent_bus = adapter->pdev->bus->parent;
187 if (!parent_bus)
188 return -1;
189
190 parent_dev = parent_bus->self;
191 if (!parent_dev)
192 return -1;
193
c0798edf 194 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 195 return -1;
196
c0798edf 197 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 198 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
199 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
200 return -1;
b8e82001
JK		 201 return 0;
202}
203
204static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
205{
206 struct ixgbe_hw *hw = &adapter->hw;
207 u16 link_status = 0;
208 int err;
209
210 hw->bus.type = ixgbe_bus_type_pci_express;
211
212 /* Get the negotiated link width and speed from PCI config space of the
213 * parent, as this device is behind a switch
214 */
215 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
216
217 /* assume caller will handle error case */
218 if (err)
219 return err;
220
221 hw->bus.width = ixgbe_convert_bus_width(link_status);
222 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
223
224 return 0;
225}
226
e027d1ae 227/**
262de08f 228 * ixgbe_pcie_from_parent - Determine whether PCIe info should come from parent
e027d1ae
JK		 229 * @hw: hw specific details
230 *
231 * This function is used by probe to determine whether a device's PCI-Express
232 * bandwidth details should be gathered from the parent bus instead of from the
233 * device. Used to ensure that various locations all have the correct device ID
234 * checks.
235 */
236static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
237{
238 switch (hw->device_id) {
239 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 240 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 241 return true;
242 default:
243 return false;
244 }
245}
246
247static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
248 int expected_gts)
249{
f9328bc6 250 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 251 struct pci_dev *pdev;
252
f9328bc6
DS		 253 /* Some devices are not connected over PCIe and thus do not negotiate
254 * speed. These devices do not have valid bus info, and thus any report
255 * we generate may not be correct.
256 */
257 if (hw->bus.type == ixgbe_bus_type_internal)
258 return;
259
56d1392f 260 /* determine whether to use the parent device */
e027d1ae
JK		 261 if (ixgbe_pcie_from_parent(&adapter->hw))
262 pdev = adapter->pdev->bus->parent->self;
263 else
264 pdev = adapter->pdev;
265
4695ca9d 266 pcie_print_link_status(pdev);
e027d1ae
JK		 267}
268
7086400d
AD		 269static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
270{
271 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 272 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d 273 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
780484d8 274 queue_work(ixgbe_wq, &adapter->service_task);
7086400d
AD		 275}
276
2a1a091c
MR		 277static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
278{
279 struct ixgbe_adapter *adapter = hw->back;
280
281 if (!hw->hw_addr)
282 return;
283 hw->hw_addr = NULL;
284 e_dev_err("Adapter removed\n");
58cf663f
MR		 285 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
286 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 287}
288
1aa37845 289static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c 290{
1aa37845 291 u8 __iomem *reg_addr;
2a1a091c 292 u32 value;
1aa37845 293 int i;
2a1a091c 294
1aa37845
PG		 295 reg_addr = READ_ONCE(hw->hw_addr);
296 if (ixgbe_removed(reg_addr))
297 return IXGBE_FAILED_READ_REG;
298
299 /* Register read of 0xFFFFFFF can indicate the adapter has been removed,
300 * so perform several status register reads to determine if the adapter
301 * has been removed.
2a1a091c 302 */
1aa37845
PG		 303 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) {
304 value = readl(reg_addr + IXGBE_STATUS);
305 if (value != IXGBE_FAILED_READ_REG)
306 break;
307 mdelay(3);
2a1a091c 308 }
1aa37845 309
2a1a091c
MR		 310 if (value == IXGBE_FAILED_READ_REG)
311 ixgbe_remove_adapter(hw);
1aa37845
PG		 312 else
313 value = readl(reg_addr + reg);
314 return value;
2a1a091c
MR		 315}
316
f8e2472f
MR		 317/**
318 * ixgbe_read_reg - Read from device register
319 * @hw: hw specific details
320 * @reg: offset of register to read
321 *
322 * Returns : value read or IXGBE_FAILED_READ_REG if removed
323 *
324 * This function is used to read device registers. It checks for device
325 * removal by confirming any read that returns all ones by checking the
326 * status register value for all ones. This function avoids reading from
327 * the hardware if a removal was previously detected in which case it
328 * returns IXGBE_FAILED_READ_REG (all ones).
329 */
330u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
331{
6aa7de05 332 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
f8e2472f
MR		 333 u32 value;
334
335 if (ixgbe_removed(reg_addr))
336 return IXGBE_FAILED_READ_REG;
2f2219be 337 if (unlikely(hw->phy.nw_mng_if_sel &
48301cf2 338 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) {
2f2219be
MR		 339 struct ixgbe_adapter *adapter;
340 int i;
341
342 for (i = 0; i < 200; ++i) {
343 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
344 if (likely(!value))
345 goto writes_completed;
346 if (value == IXGBE_FAILED_READ_REG) {
347 ixgbe_remove_adapter(hw);
348 return IXGBE_FAILED_READ_REG;
349 }
350 udelay(5);
351 }
352
353 adapter = hw->back;
354 e_warn(hw, "register writes incomplete %08x\n", value);
355 }
356
357writes_completed:
f8e2472f
MR		 358 value = readl(reg_addr + reg);
359 if (unlikely(value == IXGBE_FAILED_READ_REG))
1aa37845 360 value = ixgbe_check_remove(hw, reg);
f8e2472f
MR		 361 return value;
362}
363
14438464
MR		 364static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
365{
366 u16 value;
367
368 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD) {
370 ixgbe_remove_adapter(hw);
371 return true;
372 }
373 return false;
374}
375
376u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
377{
378 struct ixgbe_adapter *adapter = hw->back;
379 u16 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_WORD;
383 pci_read_config_word(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_WORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_WORD;
387 return value;
388}
389
390#ifdef CONFIG_PCI_IOV
391static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
392{
393 struct ixgbe_adapter *adapter = hw->back;
394 u32 value;
395
396 if (ixgbe_removed(hw->hw_addr))
397 return IXGBE_FAILED_READ_CFG_DWORD;
398 pci_read_config_dword(adapter->pdev, reg, &value);
399 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
400 ixgbe_check_cfg_remove(hw, adapter->pdev))
401 return IXGBE_FAILED_READ_CFG_DWORD;
402 return value;
403}
404#endif /* CONFIG_PCI_IOV */
405
ed19231c
JK		 406void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
407{
408 struct ixgbe_adapter *adapter = hw->back;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return;
412 pci_write_config_word(adapter->pdev, reg, value);
413}
414
7086400d
AD		 415static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
416{
417 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
418
52f33af8 419 /* flush memory to make sure state is correct before next watchdog */
4e857c58 420 smp_mb__before_atomic();
7086400d
AD		 421 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
422}
423
dcd79aeb
TI		 424struct ixgbe_reg_info {
425 u32 ofs;
426 char *name;
427};
428
429static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
430
431 /* General Registers */
432 {IXGBE_CTRL, "CTRL"},
433 {IXGBE_STATUS, "STATUS"},
434 {IXGBE_CTRL_EXT, "CTRL_EXT"},
435
436 /* Interrupt Registers */
437 {IXGBE_EICR, "EICR"},
438
439 /* RX Registers */
440 {IXGBE_SRRCTL(0), "SRRCTL"},
441 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
442 {IXGBE_RDLEN(0), "RDLEN"},
443 {IXGBE_RDH(0), "RDH"},
444 {IXGBE_RDT(0), "RDT"},
445 {IXGBE_RXDCTL(0), "RXDCTL"},
446 {IXGBE_RDBAL(0), "RDBAL"},
447 {IXGBE_RDBAH(0), "RDBAH"},
448
449 /* TX Registers */
450 {IXGBE_TDBAL(0), "TDBAL"},
451 {IXGBE_TDBAH(0), "TDBAH"},
452 {IXGBE_TDLEN(0), "TDLEN"},
453 {IXGBE_TDH(0), "TDH"},
454 {IXGBE_TDT(0), "TDT"},
455 {IXGBE_TXDCTL(0), "TXDCTL"},
456
457 /* List Terminator */
ca8dfe25 458 { .name = NULL }
dcd79aeb
TI		 459};
460
461
462/*
463 * ixgbe_regdump - register printout routine
464 */
465static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
466{
332f2358 467 int i;
dcd79aeb
TI		 468 char rname[16];
469 u32 regs[64];
470
471 switch (reginfo->ofs) {
472 case IXGBE_SRRCTL(0):
473 for (i = 0; i < 64; i++)
474 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
475 break;
476 case IXGBE_DCA_RXCTRL(0):
477 for (i = 0; i < 64; i++)
478 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
479 break;
480 case IXGBE_RDLEN(0):
481 for (i = 0; i < 64; i++)
482 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
483 break;
484 case IXGBE_RDH(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
487 break;
488 case IXGBE_RDT(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
491 break;
492 case IXGBE_RXDCTL(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
495 break;
496 case IXGBE_RDBAL(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
499 break;
500 case IXGBE_RDBAH(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
503 break;
504 case IXGBE_TDBAL(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
507 break;
508 case IXGBE_TDBAH(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
511 break;
512 case IXGBE_TDLEN(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
515 break;
516 case IXGBE_TDH(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
519 break;
520 case IXGBE_TDT(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
523 break;
524 case IXGBE_TXDCTL(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
527 break;
528 default:
332f2358
JP		 529 pr_info("%-15s %08x\n",
530 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs));
dcd79aeb
TI		 531 return;
532 }
533
332f2358
JP		 534 i = 0;
535 while (i < 64) {
536 int j;
537 char buf[9 * 8 + 1];
538 char *p = buf;
539
540 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7);
dcd79aeb 541 for (j = 0; j < 8; j++)
332f2358
JP		 542 p += sprintf(p, " %08x", regs[i++]);
543 pr_err("%-15s%s\n", rname, buf);
dcd79aeb
TI		 544 }
545
546}
547
33fdc82f
JF		 548static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n)
549{
550 struct ixgbe_tx_buffer *tx_buffer;
551
552 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean];
553 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
554 n, ring->next_to_use, ring->next_to_clean,
555 (u64)dma_unmap_addr(tx_buffer, dma),
556 dma_unmap_len(tx_buffer, len),
557 tx_buffer->next_to_watch,
558 (u64)tx_buffer->time_stamp);
559}
560
dcd79aeb
TI		 561/*
562 * ixgbe_dump - Print registers, tx-rings and rx-rings
563 */
564static void ixgbe_dump(struct ixgbe_adapter *adapter)
565{
566 struct net_device *netdev = adapter->netdev;
567 struct ixgbe_hw *hw = &adapter->hw;
568 struct ixgbe_reg_info *reginfo;
569 int n = 0;
33fdc82f 570 struct ixgbe_ring *ring;
729739b7 571 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 572 union ixgbe_adv_tx_desc *tx_desc;
573 struct my_u0 { u64 a; u64 b; } *u0;
574 struct ixgbe_ring *rx_ring;
575 union ixgbe_adv_rx_desc *rx_desc;
576 struct ixgbe_rx_buffer *rx_buffer_info;
dcd79aeb
TI		 577 int i = 0;
578
579 if (!netif_msg_hw(adapter))
580 return;
581
582 /* Print netdevice Info */
583 if (netdev) {
584 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 585 pr_info("Device Name state "
4a7c9726
TK		 586 "trans_start\n");
587 pr_info("%-15s %016lX %016lX\n",
c7689578
JP		 588 netdev->name,
589 netdev->state,
4a7c9726 590 dev_trans_start(netdev));
dcd79aeb
TI		 591 }
592
593 /* Print Registers */
594 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 595 pr_info(" Register Name Value\n");
dcd79aeb
TI		 596 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
597 reginfo->name; reginfo++) {
598 ixgbe_regdump(hw, reginfo);
599 }
600
601 /* Print TX Ring Summary */
602 if (!netdev || !netif_running(netdev))
e90dd264 603 return;
dcd79aeb
TI		 604
605 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 606 pr_info(" %s %s %s %s\n",
607 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
608 "leng", "ntw", "timestamp");
dcd79aeb 609 for (n = 0; n < adapter->num_tx_queues; n++) {
33fdc82f
JF		 610 ring = adapter->tx_ring[n];
611 ixgbe_print_buffer(ring, n);
612 }
613
614 for (n = 0; n < adapter->num_xdp_queues; n++) {
615 ring = adapter->xdp_ring[n];
616 ixgbe_print_buffer(ring, n);
dcd79aeb
TI		 617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
39ac868a 627 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
39ac868a 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
dcd79aeb
TI		 658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
33fdc82f 661 ring = adapter->tx_ring[n];
c7689578 662 pr_info("------------------------------------\n");
33fdc82f 663 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index);
c7689578 664 pr_info("------------------------------------\n");
8ad88e37
JH		 665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb 669
33fdc82f
JF		 670 for (i = 0; ring->desc && (i < ring->count); i++) {
671 tx_desc = IXGBE_TX_DESC(ring, i);
672 tx_buffer = &ring->tx_buffer_info[i];
dcd79aeb 673 u0 = (struct my_u0 *)tx_desc;
8ad88e37 674 if (dma_unmap_len(tx_buffer, len) > 0) {
332f2358
JP		 675 const char *ring_desc;
676
33fdc82f
JF		 677 if (i == ring->next_to_use &&
678 i == ring->next_to_clean)
332f2358 679 ring_desc = " NTC/U";
33fdc82f 680 else if (i == ring->next_to_use)
332f2358 681 ring_desc = " NTU";
33fdc82f 682 else if (i == ring->next_to_clean)
332f2358
JP		 683 ring_desc = " NTC";
684 else
685 ring_desc = "";
686 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s",
8ad88e37 687 i,
9cfbfa70
CZ		 688 le64_to_cpu((__force __le64)u0->a),
689 le64_to_cpu((__force __le64)u0->b),
8ad88e37 690 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 691 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 692 tx_buffer->next_to_watch,
693 (u64)tx_buffer->time_stamp,
332f2358
JP		 694 tx_buffer->skb,
695 ring_desc);
8ad88e37
JH		 696
697 if (netif_msg_pktdata(adapter) &&
698 tx_buffer->skb)
699 print_hex_dump(KERN_INFO, "",
700 DUMP_PREFIX_ADDRESS, 16, 1,
701 tx_buffer->skb->data,
702 dma_unmap_len(tx_buffer, len),
703 true);
704 }
dcd79aeb
TI		 705 }
706 }
707
708 /* Print RX Rings Summary */
709rx_ring_summary:
710 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 711 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 712 for (n = 0; n < adapter->num_rx_queues; n++) {
713 rx_ring = adapter->rx_ring[n];
c7689578
JP		 714 pr_info("%5d %5X %5X\n",
715 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 716 }
717
718 /* Print RX Rings */
719 if (!netif_msg_rx_status(adapter))
e90dd264 720 return;
dcd79aeb
TI		 721
722 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
723
39ac868a
JH		 724 /* Receive Descriptor Formats
725 *
726 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 727 * 63 1 0
728 * +-----------------------------------------------------+
729 * 0 | Packet Buffer Address [63:1] |A0/NSE|
730 * +----------------------------------------------+------+
731 * 8 | Header Buffer Address [63:1] | DD |
732 * +-----------------------------------------------------+
733 *
734 *
39ac868a 735 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 736 *
737 * 63 48 47 32 31 30 21 20 16 15 4 3 0
738 * +------------------------------------------------------+
39ac868a
JH		 739 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
740 * | Packet | IP | | | | Type | Type |
741 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 742 * +------------------------------------------------------+
743 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
744 * +------------------------------------------------------+
745 * 63 48 47 32 31 20 19 0
39ac868a
JH		 746 *
747 * 82599+ Advanced Receive Descriptor (Read) Format
748 * 63 1 0
749 * +-----------------------------------------------------+
750 * 0 | Packet Buffer Address [63:1] |A0/NSE|
751 * +----------------------------------------------+------+
752 * 8 | Header Buffer Address [63:1] | DD |
753 * +-----------------------------------------------------+
754 *
755 *
756 * 82599+ Advanced Receive Descriptor (Write-Back) Format
757 *
758 * 63 48 47 32 31 30 21 20 17 16 4 3 0
759 * +------------------------------------------------------+
760 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
761 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
762 * |/ Flow Dir Flt ID | | | | | |
763 * +------------------------------------------------------+
764 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
765 * +------------------------------------------------------+
766 * 63 48 47 32 31 20 19 0
dcd79aeb 767 */
39ac868a 768
dcd79aeb
TI		 769 for (n = 0; n < adapter->num_rx_queues; n++) {
770 rx_ring = adapter->rx_ring[n];
c7689578
JP		 771 pr_info("------------------------------------\n");
772 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
773 pr_info("------------------------------------\n");
332f2358 774 pr_info("%s%s%s\n",
8ad88e37
JH		 775 "R [desc] [ PktBuf A0] ",
776 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
332f2358
JP		 777 "<-- Adv Rx Read format");
778 pr_info("%s%s%s\n",
8ad88e37
JH		 779 "RWB[desc] [PcsmIpSHl PtRs] ",
780 "[vl er S cks ln] ---------------- [bi->skb ] ",
332f2358 781 "<-- Adv Rx Write-Back format");
dcd79aeb
TI		 782
783 for (i = 0; i < rx_ring->count; i++) {
332f2358
JP		 784 const char *ring_desc;
785
786 if (i == rx_ring->next_to_use)
787 ring_desc = " NTU";
788 else if (i == rx_ring->next_to_clean)
789 ring_desc = " NTC";
790 else
791 ring_desc = "";
792
dcd79aeb 793 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 794 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb 795 u0 = (struct my_u0 *)rx_desc;
18a8cc98 796 if (rx_desc->wb.upper.length) {
dcd79aeb 797 /* Descriptor Done */
332f2358
JP		 798 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n",
799 i,
9cfbfa70
CZ		 800 le64_to_cpu((__force __le64)u0->a),
801 le64_to_cpu((__force __le64)u0->b),
332f2358
JP		 802 rx_buffer_info->skb,
803 ring_desc);
dcd79aeb 804 } else {
332f2358
JP		 805 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n",
806 i,
9cfbfa70
CZ		 807 le64_to_cpu((__force __le64)u0->a),
808 le64_to_cpu((__force __le64)u0->b),
dcd79aeb 809 (u64)rx_buffer_info->dma,
332f2358
JP		 810 rx_buffer_info->skb,
811 ring_desc);
dcd79aeb 812
9c50c035
ET		 813 if (netif_msg_pktdata(adapter) &&
814 rx_buffer_info->dma) {
dcd79aeb
TI		 815 print_hex_dump(KERN_INFO, "",
816 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 817 page_address(rx_buffer_info->page) +
818 rx_buffer_info->page_offset,
f800326d 819 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 820 }
821 }
dcd79aeb
TI		 822 }
823 }
dcd79aeb
TI		 824}
825
5eba3699
AV		 826static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
827{
828 u32 ctrl_ext;
829
830 /* Let firmware take over control of h/w */
831 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
832 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 833 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 834}
835
836static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
837{
838 u32 ctrl_ext;
839
840 /* Let firmware know the driver has taken over */
841 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 843 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 844}
9a799d71 845
49ce9c2c 846/**
e8e26350
PW		 847 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
848 * @adapter: pointer to adapter struct
849 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
850 * @queue: queue to map the corresponding interrupt to
851 * @msix_vector: the vector to map to the corresponding queue
852 *
853 */
854static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 855 u8 queue, u8 msix_vector)
9a799d71
AK		 856{
857 u32 ivar, index;
e8e26350
PW		 858 struct ixgbe_hw *hw = &adapter->hw;
859 switch (hw->mac.type) {
860 case ixgbe_mac_82598EB:
861 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
862 if (direction == -1)
863 direction = 0;
864 index = (((direction * 64) + queue) >> 2) & 0x1F;
865 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
866 ivar &= ~(0xFF << (8 * (queue & 0x3)));
867 ivar |= (msix_vector << (8 * (queue & 0x3)));
868 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
869 break;
870 case ixgbe_mac_82599EB:
b93a2226 871 case ixgbe_mac_X540:
9a75a1ac
DS		 872 case ixgbe_mac_X550:
873 case ixgbe_mac_X550EM_x:
49425dfc 874 case ixgbe_mac_x550em_a:
e8e26350
PW		 875 if (direction == -1) {
876 /* other causes */
877 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
878 index = ((queue & 1) * 8);
879 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
880 ivar &= ~(0xFF << index);
881 ivar |= (msix_vector << index);
882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
883 break;
884 } else {
885 /* tx or rx causes */
886 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
887 index = ((16 * (queue & 1)) + (8 * direction));
888 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
889 ivar &= ~(0xFF << index);
890 ivar |= (msix_vector << index);
891 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
892 break;
893 }
894 default:
895 break;
896 }
9a799d71
AK		 897}
898
05ae8614
BT		 899void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
900 u64 qmask)
fe49f04a
AD		 901{
902 u32 mask;
903
bd508178
AD		 904 switch (adapter->hw.mac.type) {
905 case ixgbe_mac_82598EB:
fe49f04a
AD		 906 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 908 break;
909 case ixgbe_mac_82599EB:
b93a2226 910 case ixgbe_mac_X540:
9a75a1ac
DS		 911 case ixgbe_mac_X550:
912 case ixgbe_mac_X550EM_x:
49425dfc 913 case ixgbe_mac_x550em_a:
fe49f04a
AD		 914 mask = (qmask & 0xFFFFFFFF);
915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
916 mask = (qmask >> 32);
917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 918 break;
919 default:
920 break;
fe49f04a
AD		 921 }
922}
923
943561d3 924static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 925{
926 struct ixgbe_hw *hw = &adapter->hw;
927 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 928 int i;
943561d3 929 u32 data;
c84d324c 930
943561d3
AD		 931 if ((hw->fc.current_mode != ixgbe_fc_full) &&
932 (hw->fc.current_mode != ixgbe_fc_rx_pause))
933 return;
c84d324c 934
943561d3
AD		 935 switch (hw->mac.type) {
936 case ixgbe_mac_82598EB:
937 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
938 break;
939 default:
940 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
941 }
942 hwstats->lxoffrxc += data;
c84d324c 943
943561d3
AD		 944 /* refill credits (no tx hang) if we received xoff */
945 if (!data)
c84d324c 946 return;
943561d3
AD		 947
948 for (i = 0; i < adapter->num_tx_queues; i++)
949 clear_bit(__IXGBE_HANG_CHECK_ARMED,
950 &adapter->tx_ring[i]->state);
33fdc82f
JF		 951
952 for (i = 0; i < adapter->num_xdp_queues; i++)
953 clear_bit(__IXGBE_HANG_CHECK_ARMED,
954 &adapter->xdp_ring[i]->state);
943561d3
AD		 955}
956
957static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
958{
959 struct ixgbe_hw *hw = &adapter->hw;
960 struct ixgbe_hw_stats *hwstats = &adapter->stats;
961 u32 xoff[8] = {0};
2afaa00d 962 u8 tc;
943561d3
AD		 963 int i;
964 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
965
966 if (adapter->ixgbe_ieee_pfc)
967 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
968
969 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
970 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 971 return;
943561d3 972 }
c84d324c
JF		 973
974 /* update stats for each tc, only valid with PFC enabled */
975 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 976 u32 pxoffrxc;
977
c84d324c
JF		 978 switch (hw->mac.type) {
979 case ixgbe_mac_82598EB:
2afaa00d 980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 981 break;
c84d324c 982 default:
2afaa00d 983 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 984 }
2afaa00d
PN		 985 hwstats->pxoffrxc[i] += pxoffrxc;
986 /* Get the TC for given UP */
987 tc = netdev_get_prio_tc_map(adapter->netdev, i);
988 xoff[tc] += pxoffrxc;
c84d324c
JF		 989 }
990
991 /* disarm tx queues that have received xoff frames */
992 for (i = 0; i < adapter->num_tx_queues; i++) {
993 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 994
2afaa00d 995 tc = tx_ring->dcb_tc;
c84d324c
JF		 996 if (xoff[tc])
997 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 998 }
33fdc82f
JF		 999
1000 for (i = 0; i < adapter->num_xdp_queues; i++) {
1001 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
1002
1003 tc = xdp_ring->dcb_tc;
1004 if (xoff[tc])
1005 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state);
1006 }
26f23d82
YZ		 1007}
1008
c84d324c 1009static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1010{
7d7ce682 1011 return ring->stats.packets;
c84d324c
JF		 1012}
1013
1014static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1015{
1489542b 1016 unsigned int head, tail;
2a47fa45 1017
1489542b
AD		 1018 head = ring->next_to_clean;
1019 tail = ring->next_to_use;
c84d324c 1020
1489542b 1021 return ((head <= tail) ? tail : tail + ring->count) - head;
c84d324c
JF		 1022}
1023
1024static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1025{
1026 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1027 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1028 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1029
7d637bcc 1030 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1031
1032 /*
1033 * Check for a hung queue, but be thorough. This verifies
1034 * that a transmit has been completed since the previous
1035 * check AND there is at least one packet pending. The
1036 * ARMED bit is set to indicate a potential hang. The
1037 * bit is cleared if a pause frame is received to remove
1038 * false hang detection due to PFC or 802.3x frames. By
1039 * requiring this to fail twice we avoid races with
1040 * pfc clearing the ARMED bit and conditions where we
1041 * run the check_tx_hang logic with a transmit completion
1042 * pending but without time to complete it yet.
1043 */
e90dd264 1044 if (tx_done_old == tx_done && tx_pending)
c84d324c 1045 /* make sure it is true for two checks in a row */
e90dd264
MR		 1046 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1047 &tx_ring->state);
1048 /* update completed stats and continue */
1049 tx_ring->tx_stats.tx_done_old = tx_done;
1050 /* reset the countdown */
1051 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1052
e90dd264 1053 return false;
9a799d71
AK		 1054}
1055
c83c6cbd
AD		 1056/**
1057 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1058 * @adapter: driver private struct
1059 **/
1060static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1061{
1062
1063 /* Do the reset outside of interrupt context */
1064 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
57ca2a4f 1065 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
12ff3f3b 1066 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1067 ixgbe_service_event_schedule(adapter);
1068 }
1069}
e01c31a5 1070
c04f90e5
RP		 1071/**
1072 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
5ba643c6
TN		 1073 * @netdev: network interface device structure
1074 * @queue_index: Tx queue to set
1075 * @maxrate: desired maximum transmit bitrate
c04f90e5
RP		 1076 **/
1077static int ixgbe_tx_maxrate(struct net_device *netdev,
1078 int queue_index, u32 maxrate)
1079{
1080 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1081 struct ixgbe_hw *hw = &adapter->hw;
1082 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1083
1084 if (!maxrate)
1085 return 0;
1086
1087 /* Calculate the rate factor values to set */
1088 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1089 bcnrc_val /= maxrate;
1090
1091 /* clear everything but the rate factor */
1092 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1093 IXGBE_RTTBCNRC_RF_DEC_MASK;
1094
1095 /* enable the rate scheduler */
1096 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1097
1098 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1099 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1100
1101 return 0;
1102}
1103
9a799d71
AK		 1104/**
1105 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1106 * @q_vector: structure containing interrupt and ring information
e01c31a5 1107 * @tx_ring: tx ring to clean
8220bbc1 1108 * @napi_budget: Used to determine if we are in netpoll
9a799d71 1109 **/
fe49f04a 1110static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
a3a8749d 1111 struct ixgbe_ring *tx_ring, int napi_budget)
9a799d71 1112{
fe49f04a 1113 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1114 struct ixgbe_tx_buffer *tx_buffer;
1115 union ixgbe_adv_tx_desc *tx_desc;
a8a43fda 1116 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0;
59224555 1117 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1118 unsigned int i = tx_ring->next_to_clean;
1119
1120 if (test_bit(__IXGBE_DOWN, &adapter->state))
1121 return true;
9a799d71 1122
d3d00239 1123 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1124 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1125 i -= tx_ring->count;
12207e49 1126
729739b7 1127 do {
d3d00239
AD		 1128 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1129
1130 /* if next_to_watch is not set then there is no work pending */
1131 if (!eop_desc)
1132 break;
1133
7f83a9e6 1134 /* prevent any other reads prior to eop_desc */
0a9a17e3 1135 smp_rmb();
7f83a9e6 1136
d3d00239
AD		 1137 /* if DD is not set pending work has not been completed */
1138 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1139 break;
8ad494b0 1140
d3d00239
AD		 1141 /* clear next_to_watch to prevent false hangs */
1142 tx_buffer->next_to_watch = NULL;
8ad494b0 1143
091a6246
AD		 1144 /* update the statistics for this packet */
1145 total_bytes += tx_buffer->bytecount;
1146 total_packets += tx_buffer->gso_segs;
a8a43fda
SN		 1147 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC)
1148 total_ipsec++;
091a6246 1149
fd0db0ed 1150 /* free the skb */
33fdc82f 1151 if (ring_is_xdp(tx_ring))
03993094 1152 xdp_return_frame(tx_buffer->xdpf);
33fdc82f
JF		 1153 else
1154 napi_consume_skb(tx_buffer->skb, napi_budget);
fd0db0ed 1155
729739b7
AD		 1156 /* unmap skb header data */
1157 dma_unmap_single(tx_ring->dev,
1158 dma_unmap_addr(tx_buffer, dma),
1159 dma_unmap_len(tx_buffer, len),
1160 DMA_TO_DEVICE);
1161
fd0db0ed 1162 /* clear tx_buffer data */
729739b7 1163 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1164
729739b7
AD		 1165 /* unmap remaining buffers */
1166 while (tx_desc != eop_desc) {
d3d00239
AD		 1167 tx_buffer++;
1168 tx_desc++;
8ad494b0 1169 i++;
729739b7
AD		 1170 if (unlikely(!i)) {
1171 i -= tx_ring->count;
d3d00239 1172 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1173 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1174 }
e01c31a5 1175
729739b7
AD		 1176 /* unmap any remaining paged data */
1177 if (dma_unmap_len(tx_buffer, len)) {
1178 dma_unmap_page(tx_ring->dev,
1179 dma_unmap_addr(tx_buffer, dma),
1180 dma_unmap_len(tx_buffer, len),
1181 DMA_TO_DEVICE);
1182 dma_unmap_len_set(tx_buffer, len, 0);
1183 }
1184 }
1185
1186 /* move us one more past the eop_desc for start of next pkt */
1187 tx_buffer++;
1188 tx_desc++;
1189 i++;
1190 if (unlikely(!i)) {
1191 i -= tx_ring->count;
1192 tx_buffer = tx_ring->tx_buffer_info;
1193 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1194 }
1195
1196 /* issue prefetch for next Tx descriptor */
1197 prefetch(tx_desc);
12207e49 1198
729739b7
AD		 1199 /* update budget accounting */
1200 budget--;
1201 } while (likely(budget));
1202
1203 i += tx_ring->count;
9a799d71 1204 tx_ring->next_to_clean = i;
d3d00239 1205 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1206 tx_ring->stats.bytes += total_bytes;
bd198058 1207 tx_ring->stats.packets += total_packets;
d3d00239 1208 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1209 q_vector->tx.total_bytes += total_bytes;
1210 q_vector->tx.total_packets += total_packets;
a8a43fda 1211 adapter->tx_ipsec += total_ipsec;
b953799e 1212
c84d324c
JF		 1213 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1214 /* schedule immediate reset if we believe we hung */
1215 struct ixgbe_hw *hw = &adapter->hw;
33fdc82f 1216 e_err(drv, "Detected Tx Unit Hang %s\n"
c84d324c
JF		 1217 " Tx Queue <%d>\n"
1218 " TDH, TDT <%x>, <%x>\n"
1219 " next_to_use <%x>\n"
1220 " next_to_clean <%x>\n"
1221 "tx_buffer_info[next_to_clean]\n"
1222 " time_stamp <%lx>\n"
1223 " jiffies <%lx>\n",
33fdc82f 1224 ring_is_xdp(tx_ring) ? "(XDP)" : "",
c84d324c
JF		 1225 tx_ring->queue_index,
1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1228 tx_ring->next_to_use, i,
1229 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c 1230
33fdc82f
JF		 1231 if (!ring_is_xdp(tx_ring))
1232 netif_stop_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
c84d324c
JF		 1234
1235 e_info(probe,
1236 "tx hang %d detected on queue %d, resetting adapter\n",
1237 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1238
b953799e 1239 /* schedule immediate reset if we believe we hung */
c83c6cbd 1240 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1241
1242 /* the adapter is about to reset, no point in enabling stuff */
59224555 1243 return true;
b953799e 1244 }
9a799d71 1245
33fdc82f
JF		 1246 if (ring_is_xdp(tx_ring))
1247 return !!budget;
1248
b2d96e0a
AD		 1249 netdev_tx_completed_queue(txring_txq(tx_ring),
1250 total_packets, total_bytes);
1251
e092be60 1252#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1253 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1254 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1255 /* Make sure that anybody stopping the queue after this
1256 * sees the new next_to_clean.
1257 */
1258 smp_mb();
729739b7
AD		 1259 if (__netif_subqueue_stopped(tx_ring->netdev,
1260 tx_ring->queue_index)
1261 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1262 netif_wake_subqueue(tx_ring->netdev,
1263 tx_ring->queue_index);
5b7da515 1264 ++tx_ring->tx_stats.restart_queue;
30eba97a 1265 }
e092be60 1266 }
9a799d71 1267
59224555 1268 return !!budget;
9a799d71
AK		 1269}
1270
5dd2d332 1271#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1272static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1273 struct ixgbe_ring *tx_ring,
33cf09c9 1274 int cpu)
bd0362dd 1275{
33cf09c9 1276 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1277 u32 txctrl = 0;
bdda1a61 1278 u16 reg_offset;
33cf09c9 1279
9de7605e
MR		 1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1282
33cf09c9
AD		 1283 switch (hw->mac.type) {
1284 case ixgbe_mac_82598EB:
bdda1a61 1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1286 break;
1287 case ixgbe_mac_82599EB:
b93a2226 1288 case ixgbe_mac_X540:
bdda1a61
AD		 1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1290 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1291 break;
1292 default:
bdda1a61
AD		 1293 /* for unknown hardware do not write register */
1294 return;
bd0362dd 1295 }
bdda1a61
AD		 1296
1297 /*
1298 * We can enable relaxed ordering for reads, but not writes when
1299 * DCA is enabled. This is due to a known issue in some chipsets
1300 * which will cause the DCA tag to be cleared.
1301 */
1302 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1303 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1304 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1305
1306 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1307}
1308
bdda1a61
AD		 1309static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1310 struct ixgbe_ring *rx_ring,
33cf09c9 1311 int cpu)
bd0362dd 1312{
33cf09c9 1313 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1314 u32 rxctrl = 0;
bdda1a61
AD		 1315 u8 reg_idx = rx_ring->reg_idx;
1316
9de7605e
MR		 1317 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1318 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1319
1320 switch (hw->mac.type) {
33cf09c9 1321 case ixgbe_mac_82599EB:
b93a2226 1322 case ixgbe_mac_X540:
bdda1a61 1323 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1324 break;
1325 default:
1326 break;
1327 }
bdda1a61
AD		 1328
1329 /*
1330 * We can enable relaxed ordering for reads, but not writes when
1331 * DCA is enabled. This is due to a known issue in some chipsets
1332 * which will cause the DCA tag to be cleared.
1333 */
1334 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1335 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1336 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1337
1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1339}
1340
1341static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1342{
1343 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1344 struct ixgbe_ring *ring;
bd0362dd 1345 int cpu = get_cpu();
bd0362dd 1346
33cf09c9
AD		 1347 if (q_vector->cpu == cpu)
1348 goto out_no_update;
1349
a557928e 1350 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1351 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1352
a557928e 1353 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1354 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1355
1356 q_vector->cpu = cpu;
1357out_no_update:
bd0362dd
JC		 1358 put_cpu();
1359}
1360
1361static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1362{
1363 int i;
1364
e35ec126 1365 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1366 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1368 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1369 else
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1371 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1372
49c7ffbe 1373 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1374 adapter->q_vector[i]->cpu = -1;
1375 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1376 }
1377}
1378
1379static int __ixgbe_notify_dca(struct device *dev, void *data)
1380{
c60fbb00 1381 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1382 unsigned long event = *(unsigned long *)data;
1383
2a72c31e 1384 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1385 return 0;
1386
bd0362dd
JC		 1387 switch (event) {
1388 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1389 /* if we're already enabled, don't do it again */
1390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1391 break;
652f093f 1392 if (dca_add_requester(dev) == 0) {
96b0e0f6 1393 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1395 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1396 break;
1397 }
5463fce6 1398 fallthrough; /* DCA is disabled. */
bd0362dd
JC		 1399 case DCA_PROVIDER_REMOVE:
1400 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1401 dca_remove_requester(dev);
1402 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1404 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1405 }
1406 break;
1407 }
1408
652f093f 1409 return 0;
bd0362dd 1410}
67a74ee2 1411
bdda1a61 1412#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1413
1414#define IXGBE_RSS_L4_TYPES_MASK \
1415 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1416 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1419
8a0da21b
AD		 1420static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1421 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1422 struct sk_buff *skb)
1423{
7edda4b8
FD		 1424 u16 rss_type;
1425
1426 if (!(ring->netdev->features & NETIF_F_RXHASH))
1427 return;
1428
1429 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1430 IXGBE_RXDADV_RSSTYPE_MASK;
1431
1432 if (!rss_type)
1433 return;
1434
1435 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1436 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1437 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1438}
1439
f800326d 1440#ifdef IXGBE_FCOE
ff886dfc
AD		 1441/**
1442 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1443 * @ring: structure containing ring specific data
ff886dfc
AD		 1444 * @rx_desc: advanced rx descriptor
1445 *
1446 * Returns : true if it is FCoE pkt
1447 */
57efd44c 1448static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1449 union ixgbe_adv_rx_desc *rx_desc)
1450{
1451 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1452
57efd44c 1453 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1454 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1455 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1456 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1457}
1458
f800326d 1459#endif /* IXGBE_FCOE */
e59bd25d
AV		 1460/**
1461 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1462 * @ring: structure containing ring specific data
1463 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1464 * @skb: skb currently being received and modified
1465 **/
8a0da21b 1466static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1467 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1468 struct sk_buff *skb)
9a799d71 1469{
3f207800 1470 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
3f207800
DS		 1471 bool encap_pkt = false;
1472
8a0da21b 1473 skb_checksum_none_assert(skb);
9a799d71 1474
712744be 1475 /* Rx csum disabled */
8a0da21b 1476 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1477 return;
e59bd25d 1478
a21d0822
ET		 1479 /* check for VXLAN and Geneve packets */
1480 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
3f207800
DS		 1481 encap_pkt = true;
1482 skb->encapsulation = 1;
3f207800
DS		 1483 }
1484
e59bd25d 1485 /* if IP and error */
f56e0cb1
AD		 1486 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1487 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1488 ring->rx_stats.csum_err++;
9a799d71
AK		 1489 return;
1490 }
e59bd25d 1491
f56e0cb1 1492 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1493 return;
1494
f56e0cb1 1495 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1496 /*
1497 * 82599 errata, UDP frames with a 0 checksum can be marked as
1498 * checksum errors.
1499 */
8a0da21b
AD		 1500 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1501 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1502 return;
1503
8a0da21b 1504 ring->rx_stats.csum_err++;
e59bd25d
AV		 1505 return;
1506 }
1507
9a799d71 1508 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1509 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1510 if (encap_pkt) {
1511 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1512 return;
1513
1514 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
d469251b 1515 skb->ip_summed = CHECKSUM_NONE;
3f207800
DS		 1516 return;
1517 }
1518 /* If we checked the outer header let the stack know */
1519 skb->csum_level = 1;
1520 }
9a799d71
AK		 1521}
1522
c0d4e9d2 1523static unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring)
2de6aa3a
AD		 1524{
1525 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0;
1526}
1527
f990b79b
AD		 1528static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1529 struct ixgbe_rx_buffer *bi)
1530{
1531 struct page *page = bi->page;
18cb652a 1532 dma_addr_t dma;
f990b79b 1533
f800326d 1534 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1535 if (likely(page))
f990b79b
AD		 1536 return true;
1537
f800326d 1538 /* alloc new page for storage */
18cb652a
AD		 1539 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1540 if (unlikely(!page)) {
1541 rx_ring->rx_stats.alloc_rx_page_failed++;
1542 return false;
f990b79b
AD		 1543 }
1544
f800326d 1545 /* map page for use */
f3213d93
AD		 1546 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1547 ixgbe_rx_pg_size(rx_ring),
1548 DMA_FROM_DEVICE,
1549 IXGBE_RX_DMA_ATTR);
f800326d
AD		 1550
1551 /*
1552 * if mapping failed free memory back to system since
1553 * there isn't much point in holding memory we can't use
1554 */
1555 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1556 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1557
f990b79b
AD		 1558 rx_ring->rx_stats.alloc_rx_page_failed++;
1559 return false;
1560 }
1561
f800326d 1562 bi->dma = dma;
18cb652a 1563 bi->page = page;
c0d4e9d2 1564 bi->page_offset = rx_ring->rx_offset;
ed93a398
BT		 1565 page_ref_add(page, USHRT_MAX - 1);
1566 bi->pagecnt_bias = USHRT_MAX;
86e23494 1567 rx_ring->rx_stats.alloc_rx_page++;
f800326d 1568
f990b79b
AD		 1569 return true;
1570}
1571
9a799d71 1572/**
f990b79b 1573 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1574 * @rx_ring: ring to place buffers on
1575 * @cleaned_count: number of buffers to replace
9a799d71 1576 **/
fc77dc3c 1577void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1578{
9a799d71 1579 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1580 struct ixgbe_rx_buffer *bi;
d5f398ed 1581 u16 i = rx_ring->next_to_use;
4f4542bf 1582 u16 bufsz;
9a799d71 1583
f800326d
AD		 1584 /* nothing to do */
1585 if (!cleaned_count)
fc77dc3c
AD		 1586 return;
1587
e4f74028 1588 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1589 bi = &rx_ring->rx_buffer_info[i];
1590 i -= rx_ring->count;
9a799d71 1591
4f4542bf
AD		 1592 bufsz = ixgbe_rx_bufsz(rx_ring);
1593
f800326d
AD		 1594 do {
1595 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1596 break;
d5f398ed 1597
f3213d93
AD		 1598 /* sync the buffer for use by the device */
1599 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
4f4542bf 1600 bi->page_offset, bufsz,
f3213d93
AD		 1601 DMA_FROM_DEVICE);
1602
f800326d
AD		 1603 /*
1604 * Refresh the desc even if buffer_addrs didn't change
1605 * because each write-back erases this info.
1606 */
1607 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1608
f990b79b
AD		 1609 rx_desc++;
1610 bi++;
9a799d71 1611 i++;
f990b79b 1612 if (unlikely(!i)) {
e4f74028 1613 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1614 bi = rx_ring->rx_buffer_info;
1615 i -= rx_ring->count;
1616 }
1617
c3630cc4
AD		 1618 /* clear the length for the next_to_use descriptor */
1619 rx_desc->wb.upper.length = 0;
f800326d
AD		 1620
1621 cleaned_count--;
1622 } while (cleaned_count);
7c6e0a43 1623
f990b79b
AD		 1624 i += rx_ring->count;
1625
ad435ec6
AD		 1626 if (rx_ring->next_to_use != i) {
1627 rx_ring->next_to_use = i;
1628
1629 /* update next to alloc since we have filled the ring */
1630 rx_ring->next_to_alloc = i;
1631
1632 /* Force memory writes to complete before letting h/w
1633 * know there are new descriptors to fetch. (Only
1634 * applicable for weak-ordered memory model archs,
1635 * such as IA-64).
1636 */
1637 wmb();
1638 writel(i, rx_ring->tail);
1639 }
9a799d71
AK		 1640}
1641
1d2024f6
AD		 1642static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1643 struct sk_buff *skb)
1644{
f800326d 1645 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1646
1647 /* set gso_size to avoid messing up TCP MSS */
1648 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1649 IXGBE_CB(skb)->append_cnt);
96be80ab 1650 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1651}
1652
1653static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1654 struct sk_buff *skb)
1655{
1656 /* if append_cnt is 0 then frame is not RSC */
1657 if (!IXGBE_CB(skb)->append_cnt)
1658 return;
1659
1660 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1661 rx_ring->rx_stats.rsc_flush++;
1662
1663 ixgbe_set_rsc_gso_size(rx_ring, skb);
1664
1665 /* gso_size is computed using append_cnt so always clear it last */
1666 IXGBE_CB(skb)->append_cnt = 0;
1667}
1668
8a0da21b
AD		 1669/**
1670 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1671 * @rx_ring: rx descriptor ring packet is being transacted on
1672 * @rx_desc: pointer to the EOP Rx descriptor
1673 * @skb: pointer to current skb being populated
f8212f97 1674 *
8a0da21b
AD		 1675 * This function checks the ring, descriptor, and packet information in
1676 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1677 * other fields within the skb.
f8212f97 1678 **/
46515fdb
BT		 1679void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1680 union ixgbe_adv_rx_desc *rx_desc,
1681 struct sk_buff *skb)
f8212f97 1682{
43e95f11 1683 struct net_device *dev = rx_ring->netdev;
a9763f3c 1684 u32 flags = rx_ring->q_vector->adapter->flags;
43e95f11 1685
8a0da21b
AD		 1686 ixgbe_update_rsc_stats(rx_ring, skb);
1687
1688 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1689
8a0da21b
AD		 1690 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1691
a9763f3c
MR		 1692 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1693 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1694
f646968f 1695 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1696 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1697 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1699 }
1700
92103199
SN		 1701 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP))
1702 ixgbe_ipsec_rx(rx_ring, rx_desc, skb);
1703
58918df0
AD		 1704 /* record Rx queue, or update MACVLAN statistics */
1705 if (netif_is_ixgbe(dev))
1706 skb_record_rx_queue(skb, rx_ring->queue_index);
1707 else
1708 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true,
8d80ac43
AD		 1709 false);
1710
1711 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1712}
1713
46515fdb
BT		 1714void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1715 struct sk_buff *skb)
aa80175a 1716{
3ffc1af5 1717 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1718}
43634e82 1719
f800326d
AD		 1720/**
1721 * ixgbe_is_non_eop - process handling of non-EOP buffers
1722 * @rx_ring: Rx ring being processed
1723 * @rx_desc: Rx descriptor for current buffer
1724 * @skb: Current socket buffer containing buffer in progress
1725 *
1726 * This function updates next to clean. If the buffer is an EOP buffer
1727 * this function exits returning false, otherwise it will place the
1728 * sk_buff in the next buffer to be chained and return true indicating
1729 * that this is in fact a non-EOP buffer.
1730 **/
1731static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1732 union ixgbe_adv_rx_desc *rx_desc,
1733 struct sk_buff *skb)
1734{
1735 u32 ntc = rx_ring->next_to_clean + 1;
1736
1737 /* fetch, update, and store next to clean */
1738 ntc = (ntc < rx_ring->count) ? ntc : 0;
1739 rx_ring->next_to_clean = ntc;
1740
1741 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1742
5a02cbd1
AD		 1743 /* update RSC append count if present */
1744 if (ring_is_rsc_enabled(rx_ring)) {
1745 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1746 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1747
1748 if (unlikely(rsc_enabled)) {
1749 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1750
1751 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1752 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1753
5a02cbd1
AD		 1754 /* update ntc based on RSC value */
1755 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1756 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1757 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1758 }
f800326d
AD		 1759 }
1760
5a02cbd1
AD		 1761 /* if we are the last buffer then there is nothing else to do */
1762 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1763 return false;
1764
f800326d
AD		 1765 /* place skb in next buffer to be received */
1766 rx_ring->rx_buffer_info[ntc].skb = skb;
1767 rx_ring->rx_stats.non_eop_descs++;
1768
1769 return true;
1770}
1771
19861ce2
AD		 1772/**
1773 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1774 * @rx_ring: rx descriptor ring packet is being transacted on
1775 * @skb: pointer to current skb being adjusted
1776 *
1777 * This function is an ixgbe specific version of __pskb_pull_tail. The
1778 * main difference between this version and the original function is that
1779 * this function can make several assumptions about the state of things
1780 * that allow for significant optimizations versus the standard function.
1781 * As a result we can do things like drop a frag and maintain an accurate
1782 * truesize for the skb.
1783 */
1784static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1785 struct sk_buff *skb)
1786{
d7840976 1787 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
19861ce2
AD		 1788 unsigned char *va;
1789 unsigned int pull_len;
1790
1791 /*
1792 * it is valid to use page_address instead of kmap since we are
1793 * working with pages allocated out of the lomem pool per
1794 * alloc_page(GFP_ATOMIC)
1795 */
1796 va = skb_frag_address(frag);
1797
1798 /*
1799 * we need the header to contain the greater of either ETH_HLEN or
1800 * 60 bytes if the skb->len is less than 60 for skb_pad.
1801 */
c43f1255 1802 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1803
1804 /* align pull length to size of long to optimize memcpy performance */
1805 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1806
1807 /* update all of the pointers */
1808 skb_frag_size_sub(frag, pull_len);
b54c9d5b 1809 skb_frag_off_add(frag, pull_len);
19861ce2
AD		 1810 skb->data_len -= pull_len;
1811 skb->tail += pull_len;
19861ce2
AD		 1812}
1813
42073d91
AD		 1814/**
1815 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1816 * @rx_ring: rx descriptor ring packet is being transacted on
1817 * @skb: pointer to current skb being updated
1818 *
1819 * This function provides a basic DMA sync up for the first fragment of an
1820 * skb. The reason for doing this is that the first fragment cannot be
1821 * unmapped until we have reached the end of packet descriptor for a buffer
1822 * chain.
1823 */
1824static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1825 struct sk_buff *skb)
1826{
e7ba676c 1827 if (ring_uses_build_skb(rx_ring)) {
09cfae9f
MB		 1828 unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1;
1829 unsigned long offset = (unsigned long)(skb->data) & mask;
0c5661ec
ET		 1830
1831 dma_sync_single_range_for_cpu(rx_ring->dev,
1832 IXGBE_CB(skb)->dma,
1833 offset,
1834 skb_headlen(skb),
1835 DMA_FROM_DEVICE);
42073d91 1836 } else {
d7840976 1837 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
42073d91
AD		 1838
1839 dma_sync_single_range_for_cpu(rx_ring->dev,
1840 IXGBE_CB(skb)->dma,
b54c9d5b 1841 skb_frag_off(frag),
f215af8c 1842 skb_frag_size(frag),
42073d91
AD		 1843 DMA_FROM_DEVICE);
1844 }
e7ba676c
FY		 1845
1846 /* If the page was released, just unmap it. */
1847 if (unlikely(IXGBE_CB(skb)->page_released)) {
1848 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
1849 ixgbe_rx_pg_size(rx_ring),
1850 DMA_FROM_DEVICE,
1851 IXGBE_RX_DMA_ATTR);
1852 }
42073d91
AD		 1853}
1854
f800326d
AD		 1855/**
1856 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1857 * @rx_ring: rx descriptor ring packet is being transacted on
1858 * @rx_desc: pointer to the EOP Rx descriptor
1859 * @skb: pointer to current skb being fixed
1860 *
92470808
JF		 1861 * Check if the skb is valid in the XDP case it will be an error pointer.
1862 * Return true in this case to abort processing and advance to next
1863 * descriptor.
1864 *
f800326d
AD		 1865 * Check for corrupted packet headers caused by senders on the local L2
1866 * embedded NIC switch not setting up their Tx Descriptors right. These
1867 * should be very rare.
1868 *
1869 * Also address the case where we are pulling data in on pages only
1870 * and as such no data is present in the skb header.
1871 *
1872 * In addition if skb is not at least 60 bytes we need to pad it so that
1873 * it is large enough to qualify as a valid Ethernet frame.
1874 *
1875 * Returns true if an error was encountered and skb was freed.
1876 **/
46515fdb
BT		 1877bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1878 union ixgbe_adv_rx_desc *rx_desc,
1879 struct sk_buff *skb)
f800326d 1880{
f800326d 1881 struct net_device *netdev = rx_ring->netdev;
f800326d 1882
92470808
JF		 1883 /* XDP packets use error pointer so abort at this point */
1884 if (IS_ERR(skb))
1885 return true;
1886
b5f69ccf
AD		 1887 /* Verify netdev is present, and that packet does not have any
1888 * errors that would be unacceptable to the netdev.
1889 */
1890 if (!netdev ||
1891 (unlikely(ixgbe_test_staterr(rx_desc,
1892 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1893 !(netdev->features & NETIF_F_RXALL)))) {
f800326d
AD		 1894 dev_kfree_skb_any(skb);
1895 return true;
1896 }
1897
19861ce2 1898 /* place header in linear portion of buffer */
6f429223 1899 if (!skb_headlen(skb))
cf3fe7ac 1900 ixgbe_pull_tail(rx_ring, skb);
f800326d 1901
57efd44c
AD		 1902#ifdef IXGBE_FCOE
1903 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1904 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1905 return false;
1906
1907#endif
a94d9e22
AD		 1908 /* if eth_skb_pad returns an error the skb was freed */
1909 if (eth_skb_pad(skb))
1910 return true;
f800326d
AD		 1911
1912 return false;
1913}
1914
f800326d
AD		 1915/**
1916 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1917 * @rx_ring: rx descriptor ring to store buffers on
1918 * @old_buff: donor buffer to have page reused
1919 *
0549ae20 1920 * Synchronizes page for reuse by the adapter
f800326d
AD		 1921 **/
1922static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1923 struct ixgbe_rx_buffer *old_buff)
1924{
1925 struct ixgbe_rx_buffer *new_buff;
1926 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1927
1928 new_buff = &rx_ring->rx_buffer_info[nta];
1929
1930 /* update, and store next to alloc */
1931 nta++;
1932 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1933
3fd21876
AD		 1934 /* Transfer page from old buffer to new buffer.
1935 * Move each member individually to avoid possible store
1936 * forwarding stalls and unnecessary copy of skb.
1937 */
1938 new_buff->dma = old_buff->dma;
1939 new_buff->page = old_buff->page;
1940 new_buff->page_offset = old_buff->page_offset;
1941 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
f800326d
AD		 1942}
1943
a06316dc
BT		 1944static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer,
1945 int rx_buffer_pgcnt)
af43da0d 1946{
3fd21876
AD		 1947 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1948 struct page *page = rx_buffer->page;
1b56cf49 1949
a79afa78
AL		 1950 /* avoid re-using remote and pfmemalloc pages */
1951 if (!dev_page_is_reusable(page))
af43da0d
AD		 1952 return false;
1953
1954#if (PAGE_SIZE < 8192)
1955 /* if we are only owner of page we can reuse it */
a06316dc 1956 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
af43da0d 1957 return false;
af43da0d 1958#else
3fd21876
AD		 1959 /* The last offset is a bit aggressive in that we assume the
1960 * worst case of FCoE being enabled and using a 3K buffer.
1961 * However this should have minimal impact as the 1K extra is
1962 * still less than one buffer in size.
1963 */
1964#define IXGBE_LAST_OFFSET \
1965 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K)
1966 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET)
af43da0d
AD		 1967 return false;
1968#endif
1969
1b56cf49
AD		 1970 /* If we have drained the page fragment pool we need to update
1971 * the pagecnt_bias and page count so that we fully restock the
1972 * number of references the driver holds.
af43da0d 1973 */
ed93a398
BT		 1974 if (unlikely(pagecnt_bias == 1)) {
1975 page_ref_add(page, USHRT_MAX - 1);
1b56cf49
AD		 1976 rx_buffer->pagecnt_bias = USHRT_MAX;
1977 }
af43da0d
AD		 1978
1979 return true;
1980}
1981
f800326d
AD		 1982/**
1983 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1984 * @rx_ring: rx descriptor ring to transact packets on
1985 * @rx_buffer: buffer containing page to add
f800326d 1986 * @skb: sk_buff to place the data into
5ba643c6 1987 * @size: size of data in rx_buffer
f800326d 1988 *
0549ae20
AD		 1989 * This function will add the data contained in rx_buffer->page to the skb.
1990 * This is done either through a direct copy if the data in the buffer is
1991 * less than the skb header size, otherwise it will just attach the page as
1992 * a frag to the skb.
1993 *
1994 * The function will then update the page offset if necessary and return
1995 * true if the buffer can be reused by the adapter.
f800326d 1996 **/
3fd21876 1997static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1998 struct ixgbe_rx_buffer *rx_buffer,
3fd21876
AD		 1999 struct sk_buff *skb,
2000 unsigned int size)
f800326d 2001{
09816fbe 2002#if (PAGE_SIZE < 8192)
4f4542bf 2003 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
09816fbe 2004#else
c0d4e9d2
MF		 2005 unsigned int truesize = rx_ring->rx_offset ?
2006 SKB_DATA_ALIGN(rx_ring->rx_offset + size) :
2de6aa3a 2007 SKB_DATA_ALIGN(size);
09816fbe 2008#endif
3fd21876 2009 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
0549ae20 2010 rx_buffer->page_offset, size, truesize);
3fd21876
AD		 2011#if (PAGE_SIZE < 8192)
2012 rx_buffer->page_offset ^= truesize;
2013#else
2014 rx_buffer->page_offset += truesize;
2015#endif
f800326d
AD		 2016}
2017
3fd21876
AD		 2018static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring,
2019 union ixgbe_adv_rx_desc *rx_desc,
2020 struct sk_buff **skb,
a06316dc
BT		 2021 const unsigned int size,
2022 int *rx_buffer_pgcnt)
18806c9e
AD		 2023{
2024 struct ixgbe_rx_buffer *rx_buffer;
18806c9e
AD		 2025
2026 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
a06316dc
BT		 2027 *rx_buffer_pgcnt =
2028#if (PAGE_SIZE < 8192)
2029 page_count(rx_buffer->page);
2030#else
2031 0;
2032#endif
3fd21876
AD		 2033 prefetchw(rx_buffer->page);
2034 *skb = rx_buffer->skb;
18806c9e 2035
3fd21876
AD		 2036 /* Delay unmapping of the first packet. It carries the header
2037 * information, HW may still access the header after the writeback.
2038 * Only unmap it when EOP is reached
2039 */
2040 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) {
2041 if (!*skb)
2042 goto skip_sync;
18806c9e 2043 } else {
3fd21876
AD		 2044 if (*skb)
2045 ixgbe_dma_sync_frag(rx_ring, *skb);
2046 }
18806c9e 2047
3fd21876
AD		 2048 /* we are reusing so sync this buffer for CPU use */
2049 dma_sync_single_range_for_cpu(rx_ring->dev,
2050 rx_buffer->dma,
2051 rx_buffer->page_offset,
2052 size,
2053 DMA_FROM_DEVICE);
2054skip_sync:
2055 rx_buffer->pagecnt_bias--;
18cb652a 2056
3fd21876
AD		 2057 return rx_buffer;
2058}
18806c9e 2059
3fd21876
AD		 2060static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring,
2061 struct ixgbe_rx_buffer *rx_buffer,
a06316dc
BT		 2062 struct sk_buff *skb,
2063 int rx_buffer_pgcnt)
3fd21876 2064{
a06316dc 2065 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
18806c9e
AD		 2066 /* hand second half of page back to the ring */
2067 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
18806c9e 2068 } else {
92470808 2069 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) {
1b56cf49
AD		 2070 /* the page has been released from the ring */
2071 IXGBE_CB(skb)->page_released = true;
2072 } else {
2073 /* we are not reusing the buffer so unmap it */
2074 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2075 ixgbe_rx_pg_size(rx_ring),
2076 DMA_FROM_DEVICE,
2077 IXGBE_RX_DMA_ATTR);
2078 }
3fd21876 2079 __page_frag_cache_drain(rx_buffer->page,
1b56cf49 2080 rx_buffer->pagecnt_bias);
18806c9e
AD		 2081 }
2082
3fd21876 2083 /* clear contents of rx_buffer */
18806c9e 2084 rx_buffer->page = NULL;
3fd21876
AD		 2085 rx_buffer->skb = NULL;
2086}
2087
2088static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring,
2089 struct ixgbe_rx_buffer *rx_buffer,
92470808
JF		 2090 struct xdp_buff *xdp,
2091 union ixgbe_adv_rx_desc *rx_desc)
3fd21876 2092{
92470808 2093 unsigned int size = xdp->data_end - xdp->data;
3fd21876
AD		 2094#if (PAGE_SIZE < 8192)
2095 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2096#else
92470808
JF		 2097 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
2098 xdp->data_hard_start);
3fd21876
AD		 2099#endif
2100 struct sk_buff *skb;
2101
2102 /* prefetch first cache line of first page */
f468f21b
TT		 2103 net_prefetch(xdp->data);
2104
366a88fe
DB		 2105 /* Note, we get here by enabling legacy-rx via:
2106 *
2107 * ethtool --set-priv-flags <dev> legacy-rx on
2108 *
2109 * In this mode, we currently get 0 extra XDP headroom as
2110 * opposed to having legacy-rx off, where we process XDP
2111 * packets going to stack via ixgbe_build_skb(). The latter
2112 * provides us currently with 192 bytes of headroom.
2113 *
2114 * For ixgbe_construct_skb() mode it means that the
2115 * xdp->data_meta will always point to xdp->data, since
2116 * the helper cannot expand the head. Should this ever
2117 * change in future for legacy-rx mode on, then lets also
2118 * add xdp->data_meta handling here.
2119 */
3fd21876
AD		 2120
2121 /* allocate a skb to store the frags */
2122 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE);
2123 if (unlikely(!skb))
2124 return NULL;
2125
2126 if (size > IXGBE_RX_HDR_SIZE) {
2127 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2128 IXGBE_CB(skb)->dma = rx_buffer->dma;
2129
2130 skb_add_rx_frag(skb, 0, rx_buffer->page,
92470808 2131 xdp->data - page_address(rx_buffer->page),
3fd21876
AD		 2132 size, truesize);
2133#if (PAGE_SIZE < 8192)
2134 rx_buffer->page_offset ^= truesize;
2135#else
2136 rx_buffer->page_offset += truesize;
2137#endif
2138 } else {
92470808
JF		 2139 memcpy(__skb_put(skb, size),
2140 xdp->data, ALIGN(size, sizeof(long)));
3fd21876
AD		 2141 rx_buffer->pagecnt_bias++;
2142 }
18806c9e
AD		 2143
2144 return skb;
f800326d
AD		 2145}
2146
6f429223
AD		 2147static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring,
2148 struct ixgbe_rx_buffer *rx_buffer,
92470808
JF		 2149 struct xdp_buff *xdp,
2150 union ixgbe_adv_rx_desc *rx_desc)
6f429223 2151{
366a88fe 2152 unsigned int metasize = xdp->data - xdp->data_meta;
6f429223
AD		 2153#if (PAGE_SIZE < 8192)
2154 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2155#else
2156 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
92470808
JF		 2157 SKB_DATA_ALIGN(xdp->data_end -
2158 xdp->data_hard_start);
6f429223
AD		 2159#endif
2160 struct sk_buff *skb;
2161
366a88fe
DB		 2162 /* Prefetch first cache line of first page. If xdp->data_meta
2163 * is unused, this points extactly as xdp->data, otherwise we
2164 * likely have a consumer accessing first few bytes of meta
2165 * data, and then actual data.
2166 */
f468f21b 2167 net_prefetch(xdp->data_meta);
6f429223 2168
92470808
JF		 2169 /* build an skb to around the page buffer */
2170 skb = build_skb(xdp->data_hard_start, truesize);
6f429223
AD		 2171 if (unlikely(!skb))
2172 return NULL;
2173
2174 /* update pointers within the skb to store the data */
92470808
JF		 2175 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2176 __skb_put(skb, xdp->data_end - xdp->data);
366a88fe
DB		 2177 if (metasize)
2178 skb_metadata_set(skb, metasize);
6f429223
AD		 2179
2180 /* record DMA address if this is the start of a chain of buffers */
2181 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2182 IXGBE_CB(skb)->dma = rx_buffer->dma;
2183
2184 /* update buffer offset */
2185#if (PAGE_SIZE < 8192)
2186 rx_buffer->page_offset ^= truesize;
2187#else
2188 rx_buffer->page_offset += truesize;
2189#endif
2190
2191 return skb;
2192}
2193
33fdc82f
JF		 2194static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter,
2195 struct ixgbe_ring *rx_ring,
92470808
JF		 2196 struct xdp_buff *xdp)
2197{
64530739 2198 int err, result = IXGBE_XDP_PASS;
92470808 2199 struct bpf_prog *xdp_prog;
44fa2dbd 2200 struct xdp_frame *xdpf;
92470808
JF		 2201 u32 act;
2202
92470808
JF		 2203 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2204
2205 if (!xdp_prog)
2206 goto xdp_out;
2207
44fa2dbd
JDB		 2208 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2209
92470808
JF		 2210 act = bpf_prog_run_xdp(xdp_prog, xdp);
2211 switch (act) {
2212 case XDP_PASS:
2213 break;
33fdc82f 2214 case XDP_TX:
1b698fa5 2215 xdpf = xdp_convert_buff_to_frame(xdp);
8281356b
MK		 2216 if (unlikely(!xdpf))
2217 goto out_failure;
44fa2dbd 2218 result = ixgbe_xmit_xdp_ring(adapter, xdpf);
8281356b
MK		 2219 if (result == IXGBE_XDP_CONSUMED)
2220 goto out_failure;
33fdc82f 2221 break;
64530739 2222 case XDP_REDIRECT:
5acaee0a 2223 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
8281356b
MK		 2224 if (err)
2225 goto out_failure;
2226 result = IXGBE_XDP_REDIR;
64530739 2227 break;
92470808
JF		 2228 default:
2229 bpf_warn_invalid_xdp_action(act);
5463fce6 2230 fallthrough;
92470808 2231 case XDP_ABORTED:
8281356b 2232out_failure:
92470808 2233 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
5463fce6 2234 fallthrough; /* handle aborts by dropping packet */
92470808
JF		 2235 case XDP_DROP:
2236 result = IXGBE_XDP_CONSUMED;
2237 break;
2238 }
2239xdp_out:
92470808
JF		 2240 return ERR_PTR(-result);
2241}
2242
cf025128
JDB		 2243static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring,
2244 unsigned int size)
2245{
2246 unsigned int truesize;
2247
2248#if (PAGE_SIZE < 8192)
2249 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
2250#else
c0d4e9d2
MF		 2251 truesize = rx_ring->rx_offset ?
2252 SKB_DATA_ALIGN(rx_ring->rx_offset + size) +
cf025128
JDB		 2253 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
2254 SKB_DATA_ALIGN(size);
2255#endif
2256 return truesize;
2257}
2258
33fdc82f
JF		 2259static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring,
2260 struct ixgbe_rx_buffer *rx_buffer,
2261 unsigned int size)
2262{
cf025128 2263 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size);
33fdc82f 2264#if (PAGE_SIZE < 8192)
33fdc82f
JF		 2265 rx_buffer->page_offset ^= truesize;
2266#else
33fdc82f
JF		 2267 rx_buffer->page_offset += truesize;
2268#endif
2269}
2270
f800326d
AD		 2271/**
2272 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2273 * @q_vector: structure containing interrupt and ring information
2274 * @rx_ring: rx descriptor ring to transact packets on
2275 * @budget: Total limit on number of packets to process
2276 *
2277 * This function provides a "bounce buffer" approach to Rx interrupt
2278 * processing. The advantage to this is that on systems that have
2279 * expensive overhead for IOMMU access this provides a means of avoiding
2280 * it by maintaining the mapping of the page to the syste.
2281 *
5a85e737 2282 * Returns amount of work completed
f800326d 2283 **/
5a85e737 2284static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2285 struct ixgbe_ring *rx_ring,
f4de00ed 2286 const int budget)
9a799d71 2287{
43b5169d 2288 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0;
f800326d 2289 struct ixgbe_adapter *adapter = q_vector->adapter;
33fdc82f 2290#ifdef IXGBE_FCOE
4ffdf91a
MR		 2291 int ddp_bytes;
2292 unsigned int mss = 0;
3d8fd385 2293#endif /* IXGBE_FCOE */
f800326d 2294 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
c0d4e9d2 2295 unsigned int offset = rx_ring->rx_offset;
ad088ec4 2296 unsigned int xdp_xmit = 0;
99ffc5ad
JDB		 2297 struct xdp_buff xdp;
2298
cf025128
JDB		 2299 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
2300#if (PAGE_SIZE < 8192)
43b5169d 2301 frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0);
cf025128 2302#endif
43b5169d 2303 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
cf025128 2304
fdabfc8a 2305 while (likely(total_rx_packets < budget)) {
f800326d 2306 union ixgbe_adv_rx_desc *rx_desc;
3fd21876 2307 struct ixgbe_rx_buffer *rx_buffer;
f800326d 2308 struct sk_buff *skb;
a06316dc 2309 int rx_buffer_pgcnt;
3fd21876 2310 unsigned int size;
f800326d
AD		 2311
2312 /* return some buffers to hardware, one at a time is too slow */
2313 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2314 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2315 cleaned_count = 0;
2316 }
2317
18806c9e 2318 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
3fd21876
AD		 2319 size = le16_to_cpu(rx_desc->wb.upper.length);
2320 if (!size)
f800326d 2321 break;
9a799d71 2322
124b74c1 2323 /* This memory barrier is needed to keep us from reading
f800326d 2324 * any other fields out of the rx_desc until we know the
124b74c1 2325 * descriptor has been written back
f800326d 2326 */
124b74c1 2327 dma_rmb();
9a799d71 2328
a06316dc 2329 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt);
3fd21876 2330
18806c9e 2331 /* retrieve a buffer from the ring */
92470808 2332 if (!skb) {
be9df4af
LB		 2333 unsigned char *hard_start;
2334
2335 hard_start = page_address(rx_buffer->page) +
2336 rx_buffer->page_offset - offset;
2337 xdp_prepare_buff(&xdp, hard_start, offset, size, true);
cf025128
JDB		 2338#if (PAGE_SIZE > 4096)
2339 /* At larger PAGE_SIZE, frame_sz depend on len size */
2340 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size);
2341#endif
33fdc82f 2342 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp);
92470808
JF		 2343 }
2344
2345 if (IS_ERR(skb)) {
ad088ec4
JDB		 2346 unsigned int xdp_res = -PTR_ERR(skb);
2347
2348 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) {
2349 xdp_xmit |= xdp_res;
33fdc82f 2350 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size);
7379f97a 2351 } else {
33fdc82f 2352 rx_buffer->pagecnt_bias++;
7379f97a 2353 }
92470808
JF		 2354 total_rx_packets++;
2355 total_rx_bytes += size;
92470808 2356 } else if (skb) {
3fd21876 2357 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size);
92470808 2358 } else if (ring_uses_build_skb(rx_ring)) {
6f429223 2359 skb = ixgbe_build_skb(rx_ring, rx_buffer,
92470808
JF		 2360 &xdp, rx_desc);
2361 } else {
3fd21876 2362 skb = ixgbe_construct_skb(rx_ring, rx_buffer,
92470808
JF		 2363 &xdp, rx_desc);
2364 }
f800326d 2365
18806c9e 2366 /* exit if we failed to retrieve a buffer */
3fd21876
AD		 2367 if (!skb) {
2368 rx_ring->rx_stats.alloc_rx_buff_failed++;
2369 rx_buffer->pagecnt_bias++;
18806c9e 2370 break;
3fd21876 2371 }
9a799d71 2372
a06316dc 2373 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt);
9a799d71 2374 cleaned_count++;
f8212f97 2375
f800326d
AD		 2376 /* place incomplete frames back on ring for completion */
2377 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2378 continue;
c267fc16 2379
f800326d
AD		 2380 /* verify the packet layout is correct */
2381 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2382 continue;
9a799d71 2383
d2f4fbe2
AV		 2384 /* probably a little skewed due to removing CRC */
2385 total_rx_bytes += skb->len;
d2f4fbe2 2386
8a0da21b
AD		 2387 /* populate checksum, timestamp, VLAN, and protocol */
2388 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2389
332d4a7d
YZ		 2390#ifdef IXGBE_FCOE
2391 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2392 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2393 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2394 /* include DDPed FCoE data */
2395 if (ddp_bytes > 0) {
2396 if (!mss) {
2397 mss = rx_ring->netdev->mtu -
2398 sizeof(struct fcoe_hdr) -
2399 sizeof(struct fc_frame_header) -
2400 sizeof(struct fcoe_crc_eof);
2401 if (mss > 512)
2402 mss &= ~511;
2403 }
2404 total_rx_bytes += ddp_bytes;
2405 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2406 mss);
2407 }
63d635b2
AD		 2408 if (!ddp_bytes) {
2409 dev_kfree_skb_any(skb);
f800326d 2410 continue;
63d635b2 2411 }
3d8fd385 2412 }
f800326d 2413
332d4a7d 2414#endif /* IXGBE_FCOE */
8a0da21b 2415 ixgbe_rx_skb(q_vector, skb);
9a799d71 2416
f800326d 2417 /* update budget accounting */
f4de00ed 2418 total_rx_packets++;
fdabfc8a 2419 }
9a799d71 2420
ad088ec4
JDB		 2421 if (xdp_xmit & IXGBE_XDP_REDIR)
2422 xdp_do_flush_map();
2423
2424 if (xdp_xmit & IXGBE_XDP_TX) {
7379f97a
JF		 2425 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
2426
2427 /* Force memory writes to complete before letting h/w
2428 * know there are new descriptors to fetch.
2429 */
2430 wmb();
2431 writel(ring->next_to_use, ring->tail);
2432 }
2433
c267fc16
AD		 2434 u64_stats_update_begin(&rx_ring->syncp);
2435 rx_ring->stats.packets += total_rx_packets;
2436 rx_ring->stats.bytes += total_rx_bytes;
2437 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2438 q_vector->rx.total_packets += total_rx_packets;
2439 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2440
5a85e737 2441 return total_rx_packets;
9a799d71
AK		 2442}
2443
9a799d71
AK		 2444/**
2445 * ixgbe_configure_msix - Configure MSI-X hardware
2446 * @adapter: board private structure
2447 *
2448 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2449 * interrupts.
2450 **/
2451static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2452{
021230d4 2453 struct ixgbe_q_vector *q_vector;
49c7ffbe 2454 int v_idx;
021230d4 2455 u32 mask;
9a799d71 2456
8e34d1aa
AD		 2457 /* Populate MSIX to EITR Select */
2458 if (adapter->num_vfs > 32) {
b4f47a48 2459 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
8e34d1aa
AD		 2460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2461 }
2462
4df10466
JB		 2463 /*
2464 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2465 * corresponding register.
2466 */
49c7ffbe 2467 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2468 struct ixgbe_ring *ring;
7a921c93 2469 q_vector = adapter->q_vector[v_idx];
021230d4 2470
a557928e 2471 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2472 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2473
a557928e 2474 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2475 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2476
fe49f04a 2477 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2478 }
2479
bd508178
AD		 2480 switch (adapter->hw.mac.type) {
2481 case ixgbe_mac_82598EB:
e8e26350 2482 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2483 v_idx);
bd508178
AD		 2484 break;
2485 case ixgbe_mac_82599EB:
b93a2226 2486 case ixgbe_mac_X540:
9a75a1ac
DS		 2487 case ixgbe_mac_X550:
2488 case ixgbe_mac_X550EM_x:
49425dfc 2489 case ixgbe_mac_x550em_a:
e8e26350 2490 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2491 break;
bd508178
AD		 2492 default:
2493 break;
2494 }
021230d4
AV		 2495 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2496
41fb9248 2497 /* set up to autoclear timer, and the vectors */
021230d4 2498 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2499 mask &= ~(IXGBE_EIMS_OTHER |
2500 IXGBE_EIMS_MAILBOX |
2501 IXGBE_EIMS_LSC);
2502
021230d4 2503 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2504}
2505
f494e8fa
AV		 2506/**
2507 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2508 * @q_vector: structure containing interrupt and ring information
2509 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2510 *
2511 * Stores a new ITR value based on packets and byte
2512 * counts during the last interrupt. The advantage of per interrupt
2513 * computation is faster updates and more accurate ITR for the current
2514 * traffic pattern. Constants in this function were computed
2515 * based on theoretical maximum wire speed and thresholds were set based
2516 * on testing data as well as attempting to minimize response time
2517 * while increasing bulk throughput.
f494e8fa 2518 **/
bd198058
AD		 2519static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2520 struct ixgbe_ring_container *ring_container)
f494e8fa 2521{
b4ded832
AD		 2522 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS |
2523 IXGBE_ITR_ADAPTIVE_LATENCY;
2524 unsigned int avg_wire_size, packets, bytes;
2525 unsigned long next_update = jiffies;
f494e8fa 2526
b4ded832
AD		 2527 /* If we don't have any rings just leave ourselves set for maximum
2528 * possible latency so we take ourselves out of the equation.
2529 */
2530 if (!ring_container->ring)
bd198058 2531 return;
f494e8fa 2532
b4ded832
AD		 2533 /* If we didn't update within up to 1 - 2 jiffies we can assume
2534 * that either packets are coming in so slow there hasn't been
2535 * any work, or that there is so much work that NAPI is dealing
2536 * with interrupt moderation and we don't need to do anything.
f494e8fa 2537 */
b4ded832
AD		 2538 if (time_after(next_update, ring_container->next_update))
2539 goto clear_counts;
bdbeefe8 2540
b4ded832 2541 packets = ring_container->total_packets;
f494e8fa 2542
b4ded832
AD		 2543 /* We have no packets to actually measure against. This means
2544 * either one of the other queues on this vector is active or
2545 * we are a Tx queue doing TSO with too high of an interrupt rate.
2546 *
2547 * When this occurs just tick up our delay by the minimum value
2548 * and hope that this extra delay will prevent us from being called
2549 * without any work on our queue.
2550 */
2551 if (!packets) {
2552 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2553 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2554 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2555 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY;
2556 goto clear_counts;
2557 }
2558
2559 bytes = ring_container->total_bytes;
2560
2561 /* If packets are less than 4 or bytes are less than 9000 assume
2562 * insufficient data to use bulk rate limiting approach. We are
2563 * likely latency driven.
2564 */
2565 if (packets < 4 && bytes < 9000) {
2566 itr = IXGBE_ITR_ADAPTIVE_LATENCY;
2567 goto adjust_by_size;
2568 }
2569
2570 /* Between 4 and 48 we can assume that our current interrupt delay
2571 * is only slightly too low. As such we should increase it by a small
2572 * fixed amount.
2573 */
2574 if (packets < 48) {
2575 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2576 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2577 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2578 goto clear_counts;
2579 }
2580
2581 /* Between 48 and 96 is our "goldilocks" zone where we are working
2582 * out "just right". Just report that our current ITR is good for us.
2583 */
2584 if (packets < 96) {
2585 itr = q_vector->itr >> 2;
2586 goto clear_counts;
2587 }
2588
2589 /* If packet count is 96 or greater we are likely looking at a slight
2590 * overrun of the delay we want. Try halving our delay to see if that
2591 * will cut the number of packets in half per interrupt.
2592 */
2593 if (packets < 256) {
2594 itr = q_vector->itr >> 3;
2595 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS)
2596 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS;
2597 goto clear_counts;
2598 }
2599
2600 /* The paths below assume we are dealing with a bulk ITR since number
2601 * of packets is 256 or greater. We are just going to have to compute
2602 * a value and try to bring the count under control, though for smaller
2603 * packet sizes there isn't much we can do as NAPI polling will likely
2604 * be kicking in sooner rather than later.
2605 */
2606 itr = IXGBE_ITR_ADAPTIVE_BULK;
2607
2608adjust_by_size:
2609 /* If packet counts are 256 or greater we can assume we have a gross
2610 * overestimation of what the rate should be. Instead of trying to fine
2611 * tune it just use the formula below to try and dial in an exact value
2612 * give the current packet size of the frame.
2613 */
2614 avg_wire_size = bytes / packets;
2615
2616 /* The following is a crude approximation of:
2617 * wmem_default / (size + overhead) = desired_pkts_per_int
2618 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
2619 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
2620 *
2621 * Assuming wmem_default is 212992 and overhead is 640 bytes per
2622 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
2623 * formula down to
2624 *
2625 * (170 * (size + 24)) / (size + 640) = ITR
2626 *
2627 * We first do some math on the packet size and then finally bitshift
2628 * by 8 after rounding up. We also have to account for PCIe link speed
2629 * difference as ITR scales based on this.
2630 */
2631 if (avg_wire_size <= 60) {
2632 /* Start at 50k ints/sec */
2633 avg_wire_size = 5120;
2634 } else if (avg_wire_size <= 316) {
2635 /* 50K ints/sec to 16K ints/sec */
2636 avg_wire_size *= 40;
2637 avg_wire_size += 2720;
2638 } else if (avg_wire_size <= 1084) {
2639 /* 16K ints/sec to 9.2K ints/sec */
2640 avg_wire_size *= 15;
2641 avg_wire_size += 11452;
377228ac 2642 } else if (avg_wire_size < 1968) {
b4ded832
AD		 2643 /* 9.2K ints/sec to 8K ints/sec */
2644 avg_wire_size *= 5;
2645 avg_wire_size += 22420;
2646 } else {
2647 /* plateau at a limit of 8K ints/sec */
2648 avg_wire_size = 32256;
2649 }
2650
2651 /* If we are in low latency mode half our delay which doubles the rate
2652 * to somewhere between 100K to 16K ints/sec
2653 */
2654 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY)
2655 avg_wire_size >>= 1;
2656
2657 /* Resultant value is 256 times larger than it needs to be. This
2658 * gives us room to adjust the value as needed to either increase
2659 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
2660 *
2661 * Use addition as we have already recorded the new latency flag
2662 * for the ITR value.
2663 */
2664 switch (q_vector->adapter->link_speed) {
2665 case IXGBE_LINK_SPEED_10GB_FULL:
2666 case IXGBE_LINK_SPEED_100_FULL:
2667 default:
2668 itr += DIV_ROUND_UP(avg_wire_size,
2669 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) *
2670 IXGBE_ITR_ADAPTIVE_MIN_INC;
f494e8fa 2671 break;
b4ded832
AD		 2672 case IXGBE_LINK_SPEED_2_5GB_FULL:
2673 case IXGBE_LINK_SPEED_1GB_FULL:
2674 case IXGBE_LINK_SPEED_10_FULL:
377228ac
AD		 2675 if (avg_wire_size > 8064)
2676 avg_wire_size = 8064;
b4ded832
AD		 2677 itr += DIV_ROUND_UP(avg_wire_size,
2678 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) *
2679 IXGBE_ITR_ADAPTIVE_MIN_INC;
f494e8fa
AV		 2680 break;
2681 }
2682
b4ded832
AD		 2683clear_counts:
2684 /* write back value */
2685 ring_container->itr = itr;
2686
2687 /* next update should occur within next jiffy */
2688 ring_container->next_update = next_update + 1;
2689
bd198058
AD		 2690 ring_container->total_bytes = 0;
2691 ring_container->total_packets = 0;
f494e8fa
AV		 2692}
2693
509ee935
JB		 2694/**
2695 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2696 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2697 *
2698 * This function is made to be called by ethtool and by the driver
2699 * when it needs to update EITR registers at runtime. Hardware
2700 * specific quirks/differences are taken care of here.
2701 */
fe49f04a 2702void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2703{
fe49f04a 2704 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2705 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2706 int v_idx = q_vector->v_idx;
5d967eb7 2707 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2708
bd508178
AD		 2709 switch (adapter->hw.mac.type) {
2710 case ixgbe_mac_82598EB:
509ee935
JB		 2711 /* must write high and low 16 bits to reset counter */
2712 itr_reg |= (itr_reg << 16);
bd508178
AD		 2713 break;
2714 case ixgbe_mac_82599EB:
b93a2226 2715 case ixgbe_mac_X540:
9a75a1ac
DS		 2716 case ixgbe_mac_X550:
2717 case ixgbe_mac_X550EM_x:
49425dfc 2718 case ixgbe_mac_x550em_a:
509ee935
JB		 2719 /*
2720 * set the WDIS bit to not clear the timer bits and cause an
2721 * immediate assertion of the interrupt
2722 */
2723 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2724 break;
2725 default:
2726 break;
509ee935
JB		 2727 }
2728 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2729}
2730
bd198058 2731static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2732{
b4ded832 2733 u32 new_itr;
f494e8fa 2734
bd198058
AD		 2735 ixgbe_update_itr(q_vector, &q_vector->tx);
2736 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2737
b4ded832
AD		 2738 /* use the smallest value of new ITR delay calculations */
2739 new_itr = min(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa 2740
b4ded832
AD		 2741 /* Clear latency flag if set, shift into correct position */
2742 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY;
2743 new_itr <<= 2;
f494e8fa 2744
d5bf4f67 2745 if (new_itr != q_vector->itr) {
bd198058 2746 /* save the algorithm value here */
5d967eb7 2747 q_vector->itr = new_itr;
fe49f04a
AD		 2748
2749 ixgbe_write_eitr(q_vector);
f494e8fa 2750 }
f494e8fa
AV		 2751}
2752
119fc60a 2753/**
de88eeeb 2754 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2755 * @adapter: pointer to adapter
119fc60a 2756 **/
f0f9778d 2757static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2758{
119fc60a
MC		 2759 struct ixgbe_hw *hw = &adapter->hw;
2760 u32 eicr = adapter->interrupt_event;
b3eb4e18 2761 s32 rc;
119fc60a 2762
f0f9778d 2763 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2764 return;
2765
22cb4fff 2766 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
f0f9778d
AD		 2767 return;
2768
2769 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2770
7ca647bd 2771 switch (hw->device_id) {
f0f9778d
AD		 2772 case IXGBE_DEV_ID_82599_T3_LOM:
2773 /*
2774 * Since the warning interrupt is for both ports
2775 * we don't have to check if:
2776 * - This interrupt wasn't for our port.
2777 * - We may have missed the interrupt so always have to
2778 * check if we got a LSC
2779 */
9a900eca 2780 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2781 !(eicr & IXGBE_EICR_LSC))
2782 return;
2783
2784 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2785 u32 speed;
f0f9778d 2786 bool link_up = false;
7ca647bd 2787
3d292265 2788 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2789
f0f9778d
AD		 2790 if (link_up)
2791 return;
2792 }
2793
2794 /* Check if this is not due to overtemp */
2795 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2796 return;
2797
2798 break;
b3eb4e18
MR		 2799 case IXGBE_DEV_ID_X550EM_A_1G_T:
2800 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2801 rc = hw->phy.ops.check_overtemp(hw);
2802 if (rc != IXGBE_ERR_OVERTEMP)
2803 return;
2804 break;
7ca647bd 2805 default:
597f22d6
DS		 2806 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2807 return;
9a900eca 2808 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2809 return;
7ca647bd 2810 break;
119fc60a 2811 }
f44e751b 2812 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2813
2814 adapter->interrupt_event = 0;
119fc60a
MC		 2815}
2816
0befdb3e
JB		 2817static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2818{
2819 struct ixgbe_hw *hw = &adapter->hw;
2820
2821 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2822 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2823 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2824 /* write to clear the interrupt */
9a900eca 2825 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2826 }
2827}
cf8280ee 2828
4f51bf70
JK		 2829static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2830{
9a900eca
DS		 2831 struct ixgbe_hw *hw = &adapter->hw;
2832
4f51bf70
JK		 2833 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2834 return;
2835
2836 switch (adapter->hw.mac.type) {
2837 case ixgbe_mac_82599EB:
2838 /*
2839 * Need to check link state so complete overtemp check
2840 * on service task
2841 */
9a900eca
DS		 2842 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2843 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2844 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2845 adapter->interrupt_event = eicr;
2846 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2847 ixgbe_service_event_schedule(adapter);
2848 return;
2849 }
2850 return;
b3eb4e18
MR		 2851 case ixgbe_mac_x550em_a:
2852 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) {
2853 adapter->interrupt_event = eicr;
2854 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2855 ixgbe_service_event_schedule(adapter);
2856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
2857 IXGBE_EICR_GPI_SDP0_X550EM_a);
2858 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR,
2859 IXGBE_EICR_GPI_SDP0_X550EM_a);
2860 }
2861 return;
2862 case ixgbe_mac_X550:
4f51bf70
JK		 2863 case ixgbe_mac_X540:
2864 if (!(eicr & IXGBE_EICR_TS))
2865 return;
2866 break;
2867 default:
2868 return;
2869 }
2870
f44e751b 2871 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2872}
2873
45788d2a
DS		 2874static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2875{
2876 switch (hw->mac.type) {
2877 case ixgbe_mac_82598EB:
2878 if (hw->phy.type == ixgbe_phy_nl)
2879 return true;
2880 return false;
2881 case ixgbe_mac_82599EB:
2882 case ixgbe_mac_X550EM_x:
49425dfc 2883 case ixgbe_mac_x550em_a:
45788d2a
DS		 2884 switch (hw->mac.ops.get_media_type(hw)) {
2885 case ixgbe_media_type_fiber:
2886 case ixgbe_media_type_fiber_qsfp:
2887 return true;
2888 default:
2889 return false;
2890 }
2891 default:
2892 return false;
2893 }
2894}
2895
e8e26350
PW		 2896static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2897{
2898 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2899 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2900
4ccc650c
DS		 2901 if (!ixgbe_is_sfp(hw))
2902 return;
2903
2904 /* Later MAC's use different SDP */
2905 if (hw->mac.type >= ixgbe_mac_X540)
2906 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2907
2908 if (eicr & eicr_mask) {
73c4b7cd 2909 /* Clear the interrupt */
4ccc650c 2910 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2911 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2912 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2913 adapter->sfp_poll_time = 0;
7086400d
AD		 2914 ixgbe_service_event_schedule(adapter);
2915 }
73c4b7cd
AD		 2916 }
2917
4ccc650c
DS		 2918 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2919 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2920 /* Clear the interrupt */
9a900eca 2921 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2922 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2923 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2924 ixgbe_service_event_schedule(adapter);
2925 }
e8e26350
PW		 2926 }
2927}
2928
cf8280ee
JB		 2929static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2930{
2931 struct ixgbe_hw *hw = &adapter->hw;
2932
2933 adapter->lsc_int++;
2934 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2935 adapter->link_check_timeout = jiffies;
2936 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2937 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2938 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2939 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2940 }
2941}
2942
fe49f04a
AD		 2943static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2944 u64 qmask)
2945{
2946 u32 mask;
bd508178 2947 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2948
bd508178
AD		 2949 switch (hw->mac.type) {
2950 case ixgbe_mac_82598EB:
fe49f04a 2951 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2952 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2953 break;
2954 case ixgbe_mac_82599EB:
b93a2226 2955 case ixgbe_mac_X540:
9a75a1ac
DS		 2956 case ixgbe_mac_X550:
2957 case ixgbe_mac_X550EM_x:
49425dfc 2958 case ixgbe_mac_x550em_a:
fe49f04a 2959 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2960 if (mask)
2961 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2962 mask = (qmask >> 32);
bd508178
AD		 2963 if (mask)
2964 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2965 break;
2966 default:
2967 break;
fe49f04a
AD		 2968 }
2969 /* skip the flush */
2970}
2971
021230d4 2972/**
2c4af694
AD		 2973 * ixgbe_irq_enable - Enable default interrupt generation settings
2974 * @adapter: board private structure
5ba643c6
TN		 2975 * @queues: enable irqs for queues
2976 * @flush: flush register write
021230d4 2977 **/
2c4af694
AD		 2978static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2979 bool flush)
9a799d71 2980{
9a900eca 2981 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2982 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2983
2c4af694
AD		 2984 /* don't reenable LSC while waiting for link */
2985 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2986 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2987
2c4af694 2988 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2989 switch (adapter->hw.mac.type) {
2990 case ixgbe_mac_82599EB:
9a900eca 2991 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2992 break;
2993 case ixgbe_mac_X540:
9a75a1ac
DS		 2994 case ixgbe_mac_X550:
2995 case ixgbe_mac_X550EM_x:
49425dfc 2996 case ixgbe_mac_x550em_a:
4f51bf70
JK		 2997 mask |= IXGBE_EIMS_TS;
2998 break;
2999 default:
3000 break;
3001 }
2c4af694 3002 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 3003 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 3004 switch (adapter->hw.mac.type) {
3005 case ixgbe_mac_82599EB:
9a900eca
DS		 3006 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3007 mask |= IXGBE_EIMS_GPI_SDP2(hw);
5463fce6 3008 fallthrough;
858bc081 3009 case ixgbe_mac_X540:
9a75a1ac
DS		 3010 case ixgbe_mac_X550:
3011 case ixgbe_mac_X550EM_x:
49425dfc
MR		 3012 case ixgbe_mac_x550em_a:
3013 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
2d40cd17 3014 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
49425dfc 3015 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
cbd45ec7 3016 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 3017 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
3018 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 3019 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 3020 mask |= IXGBE_EIMS_MAILBOX;
3021 break;
3022 default:
3023 break;
9a799d71 3024 }
db0677fa 3025
2c4af694
AD		 3026 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
3027 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
3028 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 3029
2c4af694
AD		 3030 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
3031 if (queues)
3032 ixgbe_irq_enable_queues(adapter, ~0);
3033 if (flush)
3034 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 3035}
3036
2c4af694 3037static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 3038{
a65151ba 3039 struct ixgbe_adapter *adapter = data;
9a799d71 3040 struct ixgbe_hw *hw = &adapter->hw;
54037505 3041 u32 eicr;
91281fd3 3042
54037505
DS		 3043 /*
3044 * Workaround for Silicon errata. Use clear-by-write instead
3045 * of clear-by-read. Reading with EICS will return the
3046 * interrupt causes without clearing, which later be done
3047 * with the write to EICR.
3048 */
3049 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 3050
3051 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 3052 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 3053 * the bits are high when ixgbe_msix_other is called. There is a race
3054 * condition otherwise which results in possible performance loss
3055 * especially if the ixgbe_msix_other interrupt is triggering
3056 * consistently (as it would when PPS is turned on for the X540 device)
3057 */
3058 eicr &= 0xFFFF0000;
3059
54037505 3060 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 3061
cf8280ee
JB		 3062 if (eicr & IXGBE_EICR_LSC)
3063 ixgbe_check_lsc(adapter);
f0848276 3064
1cdd1ec8
GR		 3065 if (eicr & IXGBE_EICR_MAILBOX)
3066 ixgbe_msg_task(adapter);
efe3d3c8 3067
bd508178
AD		 3068 switch (hw->mac.type) {
3069 case ixgbe_mac_82599EB:
b93a2226 3070 case ixgbe_mac_X540:
9a75a1ac
DS		 3071 case ixgbe_mac_X550:
3072 case ixgbe_mac_X550EM_x:
49425dfc 3073 case ixgbe_mac_x550em_a:
597f22d6
DS		 3074 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
3075 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
3076 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
3077 ixgbe_service_event_schedule(adapter);
3078 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3079 IXGBE_EICR_GPI_SDP0_X540);
3080 }
d773ce2d
DS		 3081 if (eicr & IXGBE_EICR_ECC) {
3082 e_info(link, "Received ECC Err, initiating reset\n");
57ca2a4f 3083 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
d773ce2d
DS		 3084 ixgbe_service_event_schedule(adapter);
3085 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3086 }
c4cf55e5
PWJ		 3087 /* Handle Flow Director Full threshold interrupt */
3088 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 3089 int reinit_count = 0;
c4cf55e5 3090 int i;
c4cf55e5 3091 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 3092 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 3093 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 3094 &ring->state))
3095 reinit_count++;
3096 }
3097 if (reinit_count) {
3098 /* no more flow director interrupts until after init */
3099 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 3100 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
3101 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 3102 }
3103 }
f0f9778d 3104 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 3105 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 3106 break;
3107 default:
3108 break;
c4cf55e5 3109 }
f0848276 3110
bd508178 3111 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 3112
db0677fa 3113 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 3114 ixgbe_ptp_check_pps_event(adapter);
efe3d3c8 3115
7086400d 3116 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 3117 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 3118 ixgbe_irq_enable(adapter, false, false);
f0848276 3119
9a799d71 3120 return IRQ_HANDLED;
f0848276 3121}
91281fd3 3122
4ff7fb12 3123static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 3124{
021230d4 3125 struct ixgbe_q_vector *q_vector = data;
91281fd3 3126
9b471446 3127 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 3128
4ff7fb12 3129 if (q_vector->rx.ring || q_vector->tx.ring)
ef2662b2 3130 napi_schedule_irqoff(&q_vector->napi);
91281fd3 3131
9a799d71 3132 return IRQ_HANDLED;
91281fd3
AD		 3133}
3134
eb01b975
AD		 3135/**
3136 * ixgbe_poll - NAPI Rx polling callback
3137 * @napi: structure for representing this polling device
3138 * @budget: how many packets driver is allowed to clean
3139 *
3140 * This function is used for legacy and MSI, NAPI mode
3141 **/
8af3c33f 3142int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 3143{
3144 struct ixgbe_q_vector *q_vector =
3145 container_of(napi, struct ixgbe_q_vector, napi);
3146 struct ixgbe_adapter *adapter = q_vector->adapter;
3147 struct ixgbe_ring *ring;
32b3e08f 3148 int per_ring_budget, work_done = 0;
eb01b975
AD		 3149 bool clean_complete = true;
3150
3151#ifdef CONFIG_IXGBE_DCA
3152 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3153 ixgbe_update_dca(q_vector);
3154#endif
3155
8220bbc1 3156 ixgbe_for_each_ring(ring, q_vector->tx) {
1742b3d5 3157 bool wd = ring->xsk_pool ?
8221c5eb
BT		 3158 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) :
3159 ixgbe_clean_tx_irq(q_vector, ring, budget);
3160
3161 if (!wd)
8220bbc1
AD		 3162 clean_complete = false;
3163 }
eb01b975 3164
3ffc1af5
ED		 3165 /* Exit if we are called by netpoll */
3166 if (budget <= 0)
5a85e737
ET		 3167 return budget;
3168
eb01b975
AD		 3169 /* attempt to distribute budget to each queue fairly, but don't allow
3170 * the budget to go below 1 because we'll exit polling */
3171 if (q_vector->rx.count > 1)
3172 per_ring_budget = max(budget/q_vector->rx.count, 1);
3173 else
3174 per_ring_budget = budget;
3175
32b3e08f 3176 ixgbe_for_each_ring(ring, q_vector->rx) {
1742b3d5 3177 int cleaned = ring->xsk_pool ?
d0bcacd0
BT		 3178 ixgbe_clean_rx_irq_zc(q_vector, ring,
3179 per_ring_budget) :
3180 ixgbe_clean_rx_irq(q_vector, ring,
32b3e08f
JB		 3181 per_ring_budget);
3182
3183 work_done += cleaned;
8220bbc1
AD		 3184 if (cleaned >= per_ring_budget)
3185 clean_complete = false;
32b3e08f 3186 }
eb01b975
AD		 3187
3188 /* If all work not completed, return budget and keep polling */
3189 if (!clean_complete)
3190 return budget;
3191
3192 /* all work done, exit the polling mode */
4233cfe6
SL		 3193 if (likely(napi_complete_done(napi, work_done))) {
3194 if (adapter->rx_itr_setting & 1)
3195 ixgbe_set_itr(q_vector);
3196 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3197 ixgbe_irq_enable_queues(adapter,
3198 BIT_ULL(q_vector->v_idx));
3199 }
eb01b975 3200
4b732cd4 3201 return min(work_done, budget - 1);
eb01b975
AD		 3202}
3203
021230d4
AV		 3204/**
3205 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
3206 * @adapter: board private structure
3207 *
3208 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
3209 * interrupts from the kernel.
3210 **/
3211static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
3212{
3213 struct net_device *netdev = adapter->netdev;
e61e4c8b 3214 unsigned int ri = 0, ti = 0;
207867f5 3215 int vector, err;
021230d4 3216
49c7ffbe 3217 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 3218 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 3219 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 3220
4ff7fb12 3221 if (q_vector->tx.ring && q_vector->rx.ring) {
e61e4c8b
TN		 3222 snprintf(q_vector->name, sizeof(q_vector->name),
3223 "%s-TxRx-%u", netdev->name, ri++);
4ff7fb12
AD		 3224 ti++;
3225 } else if (q_vector->rx.ring) {
e61e4c8b
TN		 3226 snprintf(q_vector->name, sizeof(q_vector->name),
3227 "%s-rx-%u", netdev->name, ri++);
4ff7fb12 3228 } else if (q_vector->tx.ring) {
e61e4c8b
TN		 3229 snprintf(q_vector->name, sizeof(q_vector->name),
3230 "%s-tx-%u", netdev->name, ti++);
d0759ebb
AD		 3231 } else {
3232 /* skip this unused q_vector */
3233 continue;
32aa77a4 3234 }
207867f5
AD		 3235 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
3236 q_vector->name, q_vector);
9a799d71 3237 if (err) {
396e799c 3238 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 3239 "Error: %d\n", err);
021230d4 3240 goto free_queue_irqs;
9a799d71 3241 }
207867f5
AD		 3242 /* If Flow Director is enabled, set interrupt affinity */
3243 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3244 /* assign the mask for this irq */
3245 irq_set_affinity_hint(entry->vector,
de88eeeb 3246 &q_vector->affinity_mask);
207867f5 3247 }
9a799d71
AK		 3248 }
3249
021230d4 3250 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 3251 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 3252 if (err) {
de88eeeb 3253 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 3254 goto free_queue_irqs;
9a799d71
AK		 3255 }
3256
9a799d71
AK		 3257 return 0;
3258
021230d4 3259free_queue_irqs:
207867f5
AD		 3260 while (vector) {
3261 vector--;
3262 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
3263 NULL);
3264 free_irq(adapter->msix_entries[vector].vector,
3265 adapter->q_vector[vector]);
3266 }
021230d4
AV		 3267 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3268 pci_disable_msix(adapter->pdev);
9a799d71
AK		 3269 kfree(adapter->msix_entries);
3270 adapter->msix_entries = NULL;
9a799d71
AK		 3271 return err;
3272}
3273
3274/**
021230d4 3275 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 3276 * @irq: interrupt number
3277 * @data: pointer to a network interface device structure
9a799d71
AK		 3278 **/
3279static irqreturn_t ixgbe_intr(int irq, void *data)
3280{
a65151ba 3281 struct ixgbe_adapter *adapter = data;
9a799d71 3282 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 3283 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 3284 u32 eicr;
3285
54037505 3286 /*
24ddd967 3287 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 3288 * before the read of EICR.
3289 */
3290 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
3291
021230d4 3292 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 3293 * therefore no explicit interrupt disable is necessary */
021230d4 3294 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 3295 if (!eicr) {
6af3b9eb
ET		 3296 /*
3297 * shared interrupt alert!
f47cf66e 3298 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 3299 * have disabled interrupts due to EIAM
3300 * finish the workaround of silicon errata on 82598. Unmask
3301 * the interrupt that we masked before the EICR read.
3302 */
3303 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3304 ixgbe_irq_enable(adapter, true, true);
9a799d71 3305 return IRQ_NONE; /* Not our interrupt */
f47cf66e 3306 }
9a799d71 3307
cf8280ee
JB		 3308 if (eicr & IXGBE_EICR_LSC)
3309 ixgbe_check_lsc(adapter);
021230d4 3310
bd508178
AD		 3311 switch (hw->mac.type) {
3312 case ixgbe_mac_82599EB:
e8e26350 3313 ixgbe_check_sfp_event(adapter, eicr);
5463fce6 3314 fallthrough;
0ccb974d 3315 case ixgbe_mac_X540:
9a75a1ac
DS		 3316 case ixgbe_mac_X550:
3317 case ixgbe_mac_X550EM_x:
49425dfc 3318 case ixgbe_mac_x550em_a:
d773ce2d
DS		 3319 if (eicr & IXGBE_EICR_ECC) {
3320 e_info(link, "Received ECC Err, initiating reset\n");
57ca2a4f 3321 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
d773ce2d
DS		 3322 ixgbe_service_event_schedule(adapter);
3323 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3324 }
4f51bf70 3325 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 3326 break;
3327 default:
3328 break;
3329 }
e8e26350 3330
0befdb3e 3331 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 3332 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 3333 ixgbe_ptp_check_pps_event(adapter);
0befdb3e 3334
b9f6ed2b 3335 /* would disable interrupts here but EIAM disabled it */
ef2662b2 3336 napi_schedule_irqoff(&q_vector->napi);
9a799d71 3337
6af3b9eb
ET		 3338 /*
3339 * re-enable link(maybe) and non-queue interrupts, no flush.
3340 * ixgbe_poll will re-enable the queue interrupts
3341 */
6af3b9eb
ET		 3342 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3343 ixgbe_irq_enable(adapter, false, false);
3344
9a799d71
AK		 3345 return IRQ_HANDLED;
3346}
3347
3348/**
3349 * ixgbe_request_irq - initialize interrupts
3350 * @adapter: board private structure
3351 *
3352 * Attempts to configure interrupts using the best available
3353 * capabilities of the hardware and kernel.
3354 **/
021230d4 3355static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 3356{
3357 struct net_device *netdev = adapter->netdev;
021230d4 3358 int err;
9a799d71 3359
4cc6df29 3360 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 3361 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 3362 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 3363 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 3364 netdev->name, adapter);
4cc6df29 3365 else
a0607fd3 3366 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 3367 netdev->name, adapter);
9a799d71 3368
de88eeeb 3369 if (err)
396e799c 3370 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 3371
9a799d71
AK		 3372 return err;
3373}
3374
3375static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3376{
49c7ffbe 3377 int vector;
9a799d71 3378
49c7ffbe
AD		 3379 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3380 free_irq(adapter->pdev->irq, adapter);
3381 return;
3382 }
4cc6df29 3383
1fa71252
MR		 3384 if (!adapter->msix_entries)
3385 return;
3386
49c7ffbe
AD		 3387 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3388 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3389 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3390
49c7ffbe
AD		 3391 /* free only the irqs that were actually requested */
3392 if (!q_vector->rx.ring && !q_vector->tx.ring)
3393 continue;
207867f5 3394
49c7ffbe
AD		 3395 /* clear the affinity_mask in the IRQ descriptor */
3396 irq_set_affinity_hint(entry->vector, NULL);
3397
3398 free_irq(entry->vector, q_vector);
9a799d71 3399 }
49c7ffbe 3400
90c6f877 3401 free_irq(adapter->msix_entries[vector].vector, adapter);
9a799d71
AK		 3402}
3403
22d5a71b
JB		 3404/**
3405 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3406 * @adapter: board private structure
3407 **/
3408static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3409{
bd508178
AD		 3410 switch (adapter->hw.mac.type) {
3411 case ixgbe_mac_82598EB:
835462fc 3412 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3413 break;
3414 case ixgbe_mac_82599EB:
b93a2226 3415 case ixgbe_mac_X540:
9a75a1ac
DS		 3416 case ixgbe_mac_X550:
3417 case ixgbe_mac_X550EM_x:
49425dfc 3418 case ixgbe_mac_x550em_a:
835462fc
NS		 3419 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3420 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3422 break;
3423 default:
3424 break;
22d5a71b
JB		 3425 }
3426 IXGBE_WRITE_FLUSH(&adapter->hw);
3427 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3428 int vector;
3429
3430 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3431 synchronize_irq(adapter->msix_entries[vector].vector);
3432
3433 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3434 } else {
3435 synchronize_irq(adapter->pdev->irq);
3436 }
3437}
3438
9a799d71
AK		 3439/**
3440 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
5ba643c6 3441 * @adapter: board private structure
9a799d71
AK		 3442 *
3443 **/
3444static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3445{
d5bf4f67 3446 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3447
d5bf4f67 3448 ixgbe_write_eitr(q_vector);
9a799d71 3449
e8e26350
PW		 3450 ixgbe_set_ivar(adapter, 0, 0, 0);
3451 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3452
396e799c 3453 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3454}
3455
43e69bf0
AD		 3456/**
3457 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3458 * @adapter: board private structure
3459 * @ring: structure containing ring specific data
3460 *
3461 * Configure the Tx descriptor ring after a reset.
3462 **/
84418e3b
AD		 3463void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3464 struct ixgbe_ring *ring)
43e69bf0
AD		 3465{
3466 struct ixgbe_hw *hw = &adapter->hw;
3467 u64 tdba = ring->dma;
2f1860b8 3468 int wait_loop = 10;
b88c6de2 3469 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3470 u8 reg_idx = ring->reg_idx;
43e69bf0 3471
1742b3d5 3472 ring->xsk_pool = NULL;
8221c5eb 3473 if (ring_is_xdp(ring))
1742b3d5 3474 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring);
8221c5eb 3475
2f1860b8 3476 /* disable queue to avoid issues while updating state */
b88c6de2 3477 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3478 IXGBE_WRITE_FLUSH(hw);
3479
43e69bf0 3480 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3481 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3482 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3483 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3484 ring->count * sizeof(union ixgbe_adv_tx_desc));
3485 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3486 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3487 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3488
b88c6de2
AD		 3489 /*
3490 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3491 * higher than 1 when:
3492 * - ITR is 0 as it could cause false TX hangs
3493 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3494 *
3495 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3496 * to or less than the number of on chip descriptors, which is
3497 * currently 40.
3498 */
67da097e 3499 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b4f47a48 3500 txdctl |= 1u << 16; /* WTHRESH = 1 */
b88c6de2 3501 else
b4f47a48 3502 txdctl |= 8u << 16; /* WTHRESH = 8 */
b88c6de2 3503
e954b374
AD		 3504 /*
3505 * Setting PTHRESH to 32 both improves performance
3506 * and avoids a TX hang with DFP enabled
3507 */
b4f47a48 3508 txdctl |= (1u << 8) | /* HTHRESH = 1 */
b88c6de2 3509 32; /* PTHRESH = 32 */
2f1860b8
AD		 3510
3511 /* reinitialize flowdirector state */
39cb681b 3512 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3513 ring->atr_sample_rate = adapter->atr_sample_rate;
3514 ring->atr_count = 0;
3515 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3516 } else {
3517 ring->atr_sample_rate = 0;
3518 }
2f1860b8 3519
fd786b7b
AD		 3520 /* initialize XPS */
3521 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3522 struct ixgbe_q_vector *q_vector = ring->q_vector;
3523
3524 if (q_vector)
2a47fa45 3525 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3526 &q_vector->affinity_mask,
3527 ring->queue_index);
3528 }
3529
c84d324c
JF		 3530 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3531
ffed21bc
AD		 3532 /* reinitialize tx_buffer_info */
3533 memset(ring->tx_buffer_info, 0,
3534 sizeof(struct ixgbe_tx_buffer) * ring->count);
3535
2f1860b8 3536 /* enable queue */
2f1860b8
AD		 3537 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3538
3539 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3540 if (hw->mac.type == ixgbe_mac_82598EB &&
3541 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3542 return;
3543
3544 /* poll to verify queue is enabled */
3545 do {
032b4325 3546 usleep_range(1000, 2000);
2f1860b8
AD		 3547 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3548 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3549 if (!wait_loop)
a55defd8 3550 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3551}
3552
120ff942
AD		 3553static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3554{
3555 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3556 u32 rttdcs, mtqc;
0efbf12b 3557 u8 tcs = adapter->hw_tcs;
120ff942
AD		 3558
3559 if (hw->mac.type == ixgbe_mac_82598EB)
3560 return;
3561
3562 /* disable the arbiter while setting MTQC */
3563 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3564 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3565 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3566
3567 /* set transmit pool layout */
671c0adb
AD		 3568 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3569 mtqc = IXGBE_MTQC_VT_ENA;
3570 if (tcs > 4)
3571 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3572 else if (tcs > 1)
3573 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
e24fcf28
AD		 3574 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3575 IXGBE_82599_VMDQ_4Q_MASK)
671c0adb
AD		 3576 mtqc |= IXGBE_MTQC_32VF;
3577 else
3578 mtqc |= IXGBE_MTQC_64VF;
3579 } else {
8d7179b1 3580 if (tcs > 4) {
671c0adb 3581 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
8d7179b1 3582 } else if (tcs > 1) {
671c0adb 3583 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8d7179b1
RT		 3584 } else {
3585 u8 max_txq = adapter->num_tx_queues +
3586 adapter->num_xdp_queues;
3587 if (max_txq > 63)
3588 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3589 else
3590 mtqc = IXGBE_MTQC_64Q_1PB;
3591 }
671c0adb 3592 }
120ff942 3593
671c0adb 3594 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3595
671c0adb
AD		 3596 /* Enable Security TX Buffer IFG for multiple pb */
3597 if (tcs) {
3598 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3599 sectx |= IXGBE_SECTX_DCB;
3600 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3601 }
3602
3603 /* re-enable the arbiter */
3604 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3605 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3606}
3607
9a799d71 3608/**
3a581073 3609 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3610 * @adapter: board private structure
3611 *
3612 * Configure the Tx unit of the MAC after a reset.
3613 **/
3614static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3615{
2f1860b8
AD		 3616 struct ixgbe_hw *hw = &adapter->hw;
3617 u32 dmatxctl;
43e69bf0 3618 u32 i;
9a799d71 3619
2f1860b8
AD		 3620 ixgbe_setup_mtqc(adapter);
3621
3622 if (hw->mac.type != ixgbe_mac_82598EB) {
3623 /* DMATXCTL.EN must be before Tx queues are enabled */
3624 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3625 dmatxctl |= IXGBE_DMATXCTL_TE;
3626 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3627 }
3628
9a799d71 3629 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3630 for (i = 0; i < adapter->num_tx_queues; i++)
3631 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
33fdc82f
JF		 3632 for (i = 0; i < adapter->num_xdp_queues; i++)
3633 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]);
9a799d71
AK		 3634}
3635
3ebe8fde
AD		 3636static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3637 struct ixgbe_ring *ring)
3638{
3639 struct ixgbe_hw *hw = &adapter->hw;
3640 u8 reg_idx = ring->reg_idx;
3641 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3642
3643 srrctl |= IXGBE_SRRCTL_DROP_EN;
3644
3645 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3646}
3647
3648static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3649 struct ixgbe_ring *ring)
3650{
3651 struct ixgbe_hw *hw = &adapter->hw;
3652 u8 reg_idx = ring->reg_idx;
3653 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3654
3655 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3656
3657 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3658}
3659
3660#ifdef CONFIG_IXGBE_DCB
3661void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3662#else
3663static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3664#endif
3665{
3666 int i;
3667 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3668
3669 if (adapter->ixgbe_ieee_pfc)
3670 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3671
3672 /*
3673 * We should set the drop enable bit if:
3674 * SR-IOV is enabled
3675 * or
3676 * Number of Rx queues > 1 and flow control is disabled
3677 *
3678 * This allows us to avoid head of line blocking for security
3679 * and performance reasons.
3680 */
3681 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3682 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3683 for (i = 0; i < adapter->num_rx_queues; i++)
3684 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3685 } else {
3686 for (i = 0; i < adapter->num_rx_queues; i++)
3687 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3688 }
3689}
3690
e8e26350 3691#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3692
a6616b42 3693static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3694 struct ixgbe_ring *rx_ring)
cc41ac7c 3695{
45e9baa5 3696 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3697 u32 srrctl;
bf29ee6c 3698 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3699
45e9baa5
AD		 3700 if (hw->mac.type == ixgbe_mac_82598EB) {
3701 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3702
45e9baa5
AD		 3703 /*
3704 * if VMDq is not active we must program one srrctl register
3705 * per RSS queue since we have enabled RDRXCTL.MVMEN
3706 */
3707 reg_idx &= mask;
3708 }
cc41ac7c 3709
45e9baa5
AD		 3710 /* configure header buffer length, needed for RSC */
3711 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3712
45e9baa5 3713 /* configure the packet buffer length */
1742b3d5 3714 if (rx_ring->xsk_pool) {
c4655761 3715 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool);
d0bcacd0
BT		 3716
3717 /* If the MAC support setting RXDCTL.RLPML, the
3718 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and
3719 * RXDCTL.RLPML is set to the actual UMEM buffer
3720 * size. If not, then we are stuck with a 1k buffer
3721 * size resolution. In this case frames larger than
3722 * the UMEM buffer size viewed in a 1k resolution will
3723 * be dropped.
3724 */
3725 if (hw->mac.type != ixgbe_mac_82599EB)
3726 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3727 else
3728 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3729 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) {
2de6aa3a 3730 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
d0bcacd0 3731 } else {
2de6aa3a 3732 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
d0bcacd0 3733 }
45e9baa5
AD		 3734
3735 /* configure descriptor type */
f800326d 3736 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3737
45e9baa5 3738 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3739}
9a799d71 3740
dfaf891d 3741/**
a897a2ad 3742 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3743 * @adapter: device handle
3744 *
3745 * - 82598/82599/X540: 128
3746 * - X550(non-SRIOV mode): 512
3747 * - X550(SRIOV mode): 64
3748 */
7f276efb 3749u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3750{
3751 if (adapter->hw.mac.type < ixgbe_mac_X550)
3752 return 128;
3753 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3754 return 64;
3755 else
3756 return 512;
3757}
3758
d3aa9c9f
PA		 3759/**
3760 * ixgbe_store_key - Write the RSS key to HW
3761 * @adapter: device handle
3762 *
3763 * Write the RSS key stored in adapter.rss_key to HW.
3764 */
3765void ixgbe_store_key(struct ixgbe_adapter *adapter)
3766{
3767 struct ixgbe_hw *hw = &adapter->hw;
3768 int i;
3769
3770 for (i = 0; i < 10; i++)
3771 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3772}
3773
3dfbfc7e
TN		 3774/**
3775 * ixgbe_init_rss_key - Initialize adapter RSS key
3776 * @adapter: device handle
3777 *
3778 * Allocates and initializes the RSS key if it is not allocated.
3779 **/
3780static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter)
3781{
3782 u32 *rss_key;
3783
3784 if (!adapter->rss_key) {
3785 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL);
3786 if (unlikely(!rss_key))
3787 return -ENOMEM;
3788
3789 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE);
3790 adapter->rss_key = rss_key;
3791 }
3792
3793 return 0;
3794}
3795
dfaf891d 3796/**
a897a2ad 3797 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3798 * @adapter: device handle
3799 *
3800 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3801 */
1c7cf078 3802void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3803{
dfaf891d 3804 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3805 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3806 u32 reta = 0;
dfaf891d
VZ		 3807 u32 indices_multi;
3808 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3809
0f9b232b 3810 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3811 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3812 * indices.
3813 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3814 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3815 */
3816 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3817 indices_multi = 0x11;
3818 else
3819 indices_multi = 0x1;
3820
dfaf891d
VZ		 3821 /* Write redirection table to HW */
3822 for (i = 0; i < reta_entries; i++) {
3823 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3824 if ((i & 3) == 3) {
3825 if (i < 128)
3826 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3827 else
3828 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3829 reta);
dfaf891d 3830 reta = 0;
0f9b232b
DS		 3831 }
3832 }
3833}
3834
dfaf891d 3835/**
a897a2ad 3836 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3837 * @adapter: device handle
3838 *
3839 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3840 */
3841static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3842{
dfaf891d 3843 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3844 struct ixgbe_hw *hw = &adapter->hw;
3845 u32 vfreta = 0;
dfaf891d
VZ		 3846
3847 /* Write redirection table to HW */
3848 for (i = 0; i < reta_entries; i++) {
2af62c56
AD		 3849 u16 pool = adapter->num_rx_pools;
3850
dfaf891d 3851 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
2af62c56
AD		 3852 if ((i & 3) != 3)
3853 continue;
3854
3855 while (pool--)
3856 IXGBE_WRITE_REG(hw,
3857 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)),
dfaf891d 3858 vfreta);
2af62c56 3859 vfreta = 0;
dfaf891d
VZ		 3860 }
3861}
3862
3863static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3864{
dfaf891d
VZ		 3865 u32 i, j;
3866 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3867 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3868
e24fcf28 3869 /* Program table for at least 4 queues w/ SR-IOV so that VFs can
dfaf891d
VZ		 3870 * make full use of any rings they may have. We will use the
3871 * PSRTYPE register to control how many rings we use within the PF.
3872 */
e24fcf28
AD		 3873 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3874 rss_i = 4;
dfaf891d
VZ		 3875
3876 /* Fill out hash function seeds */
d3aa9c9f 3877 ixgbe_store_key(adapter);
dfaf891d
VZ		 3878
3879 /* Fill out redirection table */
3880 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3881
3882 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3883 if (j == rss_i)
3884 j = 0;
3885
3886 adapter->rss_indir_tbl[i] = j;
3887 }
3888
3889 ixgbe_store_reta(adapter);
3890}
3891
3892static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3893{
3894 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3895 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
0f9b232b
DS		 3896 int i, j;
3897
3898 /* Fill out hash function seeds */
2af62c56
AD		 3899 for (i = 0; i < 10; i++) {
3900 u16 pool = adapter->num_rx_pools;
3901
3902 while (pool--)
3903 IXGBE_WRITE_REG(hw,
3904 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)),
3905 *(adapter->rss_key + i));
3906 }
0f9b232b
DS		 3907
3908 /* Fill out the redirection table */
3909 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3910 if (j == rss_i)
05abb126 3911 j = 0;
dfaf891d
VZ		 3912
3913 adapter->rss_indir_tbl[i] = j;
05abb126 3914 }
dfaf891d
VZ		 3915
3916 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3917}
3918
3919static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3920{
3921 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3922 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3923 u32 rxcsum;
0cefafad 3924
05abb126
AD		 3925 /* Disable indicating checksum in descriptor, enables RSS hash */
3926 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3927 rxcsum |= IXGBE_RXCSUM_PCSD;
3928 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3929
671c0adb 3930 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3931 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3932 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3933 } else {
0efbf12b 3934 u8 tcs = adapter->hw_tcs;
671c0adb
AD		 3935
3936 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3937 if (tcs > 4)
3938 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3939 else if (tcs > 1)
3940 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
e24fcf28
AD		 3941 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3942 IXGBE_82599_VMDQ_4Q_MASK)
671c0adb 3943 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3944 else
671c0adb 3945 mrqc = IXGBE_MRQC_VMDQRSS64EN;
e6b41c88 3946
156a67a9
JK		 3947 /* Enable L3/L4 for Tx Switched packets only for X550,
3948 * older devices do not support this feature
3949 */
3950 if (hw->mac.type >= ixgbe_mac_X550)
3951 mrqc |= IXGBE_MRQC_L3L4TXSWEN;
671c0adb
AD		 3952 } else {
3953 if (tcs > 4)
8b1c0b24 3954 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3955 else if (tcs > 1)
3956 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3957 else
3958 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3959 }
0cefafad
JB		 3960 }
3961
05abb126 3962 /* Perform hash on these packet types */
d1b849b9
DS		 3963 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3964 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3965 IXGBE_MRQC_RSS_FIELD_IPV6 |
3966 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3967
ef6afc0c 3968 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3969 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3970 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3971 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3972
0f9b232b
DS		 3973 if ((hw->mac.type >= ixgbe_mac_X550) &&
3974 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
2af62c56 3975 u16 pool = adapter->num_rx_pools;
0f9b232b
DS		 3976
3977 /* Enable VF RSS mode */
3978 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3979 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3980
3981 /* Setup RSS through the VF registers */
dfaf891d 3982 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3983 vfmrqc = IXGBE_MRQC_RSSEN;
3984 vfmrqc |= rss_field;
2af62c56
AD		 3985
3986 while (pool--)
3987 IXGBE_WRITE_REG(hw,
3988 IXGBE_PFVFMRQC(VMDQ_P(pool)),
3989 vfmrqc);
0f9b232b 3990 } else {
dfaf891d 3991 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3992 mrqc |= rss_field;
3993 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3994 }
0cefafad
JB		 3995}
3996
bb5a9ad2
NS		 3997/**
3998 * ixgbe_configure_rscctl - enable RSC for the indicated ring
5ba643c6
TN		 3999 * @adapter: address of board private structure
4000 * @ring: structure containing ring specific data
bb5a9ad2 4001 **/
082757af 4002static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 4003 struct ixgbe_ring *ring)
bb5a9ad2 4004{
bb5a9ad2 4005 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 4006 u32 rscctrl;
bf29ee6c 4007 u8 reg_idx = ring->reg_idx;
7367096a 4008
7d637bcc 4009 if (!ring_is_rsc_enabled(ring))
7367096a 4010 return;
bb5a9ad2 4011
7367096a 4012 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 4013 rscctrl |= IXGBE_RSCCTL_RSCEN;
4014 /*
4015 * we must limit the number of descriptors so that the
4016 * total size of max desc * buf_len is not greater
642c680e 4017 * than 65536
bb5a9ad2 4018 */
f800326d 4019 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 4020 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 4021}
4022
9e10e045
AD		 4023#define IXGBE_MAX_RX_DESC_POLL 10
4024static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
4025 struct ixgbe_ring *ring)
4026{
4027 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 4028 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
4029 u32 rxdctl;
bf29ee6c 4030 u8 reg_idx = ring->reg_idx;
9e10e045 4031
b0483c8f
MR		 4032 if (ixgbe_removed(hw->hw_addr))
4033 return;
9e10e045
AD		 4034 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
4035 if (hw->mac.type == ixgbe_mac_82598EB &&
4036 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
4037 return;
4038
4039 do {
032b4325 4040 usleep_range(1000, 2000);
9e10e045
AD		 4041 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4042 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4043
4044 if (!wait_loop) {
4045 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
4046 "the polling period\n", reg_idx);
4047 }
4048}
4049
84418e3b
AD		 4050void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
4051 struct ixgbe_ring *ring)
acd37177
AD		 4052{
4053 struct ixgbe_hw *hw = &adapter->hw;
c3630cc4 4054 union ixgbe_adv_rx_desc *rx_desc;
acd37177 4055 u64 rdba = ring->dma;
9e10e045 4056 u32 rxdctl;
bf29ee6c 4057 u8 reg_idx = ring->reg_idx;
acd37177 4058
d0bcacd0 4059 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
1742b3d5
MK		 4060 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring);
4061 if (ring->xsk_pool) {
d0bcacd0 4062 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
7117132b
BT		 4063 MEM_TYPE_XSK_BUFF_POOL,
4064 NULL));
c4655761 4065 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
d0bcacd0
BT		 4066 } else {
4067 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4068 MEM_TYPE_PAGE_SHARED, NULL));
4069 }
4070
1918e937 4071 /* disable queue to avoid use of these values while updating state */
9e10e045 4072 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
1918e937
AD		 4073 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4074
4075 /* write value back with RXDCTL.ENABLE bit cleared */
4076 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4077 IXGBE_WRITE_FLUSH(hw);
9e10e045 4078
acd37177
AD		 4079 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
4080 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
4081 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
4082 ring->count * sizeof(union ixgbe_adv_rx_desc));
8b75451b
NP		 4083 /* Force flushing of IXGBE_RDLEN to prevent MDD */
4084 IXGBE_WRITE_FLUSH(hw);
4085
acd37177
AD		 4086 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
4087 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 4088 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 4089
4090 ixgbe_configure_srrctl(adapter, ring);
4091 ixgbe_configure_rscctl(adapter, ring);
4092
4093 if (hw->mac.type == ixgbe_mac_82598EB) {
4094 /*
4095 * enable cache line friendly hardware writes:
4096 * PTHRESH=32 descriptors (half the internal cache),
4097 * this also removes ugly rx_no_buffer_count increment
4098 * HTHRESH=4 descriptors (to minimize latency on fetch)
4099 * WTHRESH=8 burst writeback up to two cache lines
4100 */
4101 rxdctl &= ~0x3FFFFF;
4102 rxdctl |= 0x080420;
2de6aa3a 4103#if (PAGE_SIZE < 8192)
2bafa8fa
ET		 4104 /* RXDCTL.RLPML does not work on 82599 */
4105 } else if (hw->mac.type != ixgbe_mac_82599EB) {
2de6aa3a
AD		 4106 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4107 IXGBE_RXDCTL_RLPML_EN);
4108
2bafa8fa
ET		 4109 /* Limit the maximum frame size so we don't overrun the skb.
4110 * This can happen in SRIOV mode when the MTU of the VF is
4111 * higher than the MTU of the PF.
4112 */
2de6aa3a
AD		 4113 if (ring_uses_build_skb(ring) &&
4114 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
541ea69a 4115 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB |
2de6aa3a
AD		 4116 IXGBE_RXDCTL_RLPML_EN;
4117#endif
9e10e045
AD		 4118 }
4119
76064573
MF		 4120 ring->rx_offset = ixgbe_rx_offset(ring);
4121
1742b3d5 4122 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) {
c4655761 4123 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool);
d0bcacd0
BT		 4124
4125 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4126 IXGBE_RXDCTL_RLPML_EN);
4127 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN;
4128
4129 ring->rx_buf_len = xsk_buf_len;
4130 }
4131
ffed21bc
AD		 4132 /* initialize rx_buffer_info */
4133 memset(ring->rx_buffer_info, 0,
4134 sizeof(struct ixgbe_rx_buffer) * ring->count);
4135
c3630cc4
AD		 4136 /* initialize Rx descriptor 0 */
4137 rx_desc = IXGBE_RX_DESC(ring, 0);
4138 rx_desc->wb.upper.length = 0;
4139
9e10e045
AD		 4140 /* enable receive descriptor ring */
4141 rxdctl |= IXGBE_RXDCTL_ENABLE;
4142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4143
4144 ixgbe_rx_desc_queue_enable(adapter, ring);
1742b3d5 4145 if (ring->xsk_pool)
d0bcacd0
BT		 4146 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring));
4147 else
4148 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 4149}
4150
48654521
AD		 4151static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
4152{
4153 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 4154 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2af62c56 4155 u16 pool = adapter->num_rx_pools;
48654521
AD		 4156
4157 /* PSRTYPE must be initialized in non 82598 adapters */
4158 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 4159 IXGBE_PSRTYPE_UDPHDR |
4160 IXGBE_PSRTYPE_IPV4HDR |
48654521 4161 IXGBE_PSRTYPE_L2HDR |
e8e9f696 4162 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 4163
4164 if (hw->mac.type == ixgbe_mac_82598EB)
4165 return;
4166
fbe7ca7f 4167 if (rss_i > 3)
b4f47a48 4168 psrtype |= 2u << 29;
fbe7ca7f 4169 else if (rss_i > 1)
b4f47a48 4170 psrtype |= 1u << 29;
48654521 4171
2af62c56 4172 while (pool--)
2a47fa45 4173 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 4174}
4175
f5b4a52e
AD		 4176static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
4177{
4178 struct ixgbe_hw *hw = &adapter->hw;
81d4e91c
AD		 4179 u16 pool = adapter->num_rx_pools;
4180 u32 reg_offset, vf_shift, vmolr;
435b19f6 4181 u32 gcr_ext, vmdctl;
de4c7f65 4182 int i;
f5b4a52e
AD		 4183
4184 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
4185 return;
4186
4187 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 4188 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
4189 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 4190 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 4191 vmdctl |= IXGBE_VT_CTL_REPLEN;
4192 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 4193
81d4e91c
AD		 4194 /* accept untagged packets until a vlan tag is
4195 * specifically set for the VMDQ queue/pool
4196 */
4197 vmolr = IXGBE_VMOLR_AUPE;
4198 while (pool--)
4199 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr);
4200
1d9c0bfd
AD		 4201 vf_shift = VMDQ_P(0) % 32;
4202 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 4203
4204 /* Enable only the PF's pool for Tx/Rx */
11f2b494 4205 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
435b19f6 4206 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
11f2b494 4207 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
435b19f6 4208 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 4209 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 4210 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 4211
4212 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 4213 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e 4214
16369564
AD		 4215 /* clear VLAN promisc flag so VFTA will be updated if necessary */
4216 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4217
f5b4a52e
AD		 4218 /*
4219 * Set up VF register offsets for selected VT Mode,
4220 * i.e. 32 or 64 VFs for SR-IOV
4221 */
73079ea0
AD		 4222 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4223 case IXGBE_82599_VMDQ_8Q_MASK:
4224 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
4225 break;
4226 case IXGBE_82599_VMDQ_4Q_MASK:
4227 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
4228 break;
4229 default:
4230 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
4231 break;
4232 }
4233
f5b4a52e
AD		 4234 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4235
de4c7f65 4236 for (i = 0; i < adapter->num_vfs; i++) {
77f192af
ET		 4237 /* configure spoof checking */
4238 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
4239 adapter->vfinfo[i].spoofchk_enabled);
e65ce0d3
VZ		 4240
4241 /* Enable/Disable RSS query feature */
4242 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
4243 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 4244 }
f5b4a52e
AD		 4245}
4246
477de6ed 4247static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 4248{
9a799d71
AK		 4249 struct ixgbe_hw *hw = &adapter->hw;
4250 struct net_device *netdev = adapter->netdev;
4251 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 4252 struct ixgbe_ring *rx_ring;
4253 int i;
4254 u32 mhadd, hlreg0;
48654521 4255
63f39bd1 4256#ifdef IXGBE_FCOE
477de6ed
AD		 4257 /* adjust max frame to be able to do baby jumbo for FCoE */
4258 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4259 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
4260 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 4261
477de6ed 4262#endif /* IXGBE_FCOE */
872844dd
AD		 4263
4264 /* adjust max frame to be at least the size of a standard frame */
4265 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4266 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
4267
477de6ed
AD		 4268 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4269 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
4270 mhadd &= ~IXGBE_MHADD_MFS_MASK;
4271 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
4272
4273 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4274 }
4275
4276 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4277 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
4278 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4279 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 4280
0cefafad
JB		 4281 /*
4282 * Setup the HW Rx Head and Tail Descriptor Pointers and
4283 * the Base and Length of the Rx Descriptor Ring
4284 */
9a799d71 4285 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4286 rx_ring = adapter->rx_ring[i];
4f4542bf
AD		 4287
4288 clear_ring_rsc_enabled(rx_ring);
4289 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
2de6aa3a 4290 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4f4542bf 4291
7d637bcc
AD		 4292 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4293 set_ring_rsc_enabled(rx_ring);
4f4542bf
AD		 4294
4295 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state))
4296 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
2de6aa3a
AD		 4297
4298 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
4299 continue;
4300
4301 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4302
4303#if (PAGE_SIZE < 8192)
4304 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4305 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4306
541ea69a
AD		 4307 if (IXGBE_2K_TOO_SMALL_WITH_PADDING ||
4308 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
2de6aa3a
AD		 4309 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4310#endif
477de6ed 4311 }
477de6ed
AD		 4312}
4313
7367096a
AD		 4314static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
4315{
4316 struct ixgbe_hw *hw = &adapter->hw;
4317 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4318
4319 switch (hw->mac.type) {
4320 case ixgbe_mac_82598EB:
4321 /*
4322 * For VMDq support of different descriptor types or
4323 * buffer sizes through the use of multiple SRRCTL
4324 * registers, RDRXCTL.MVMEN must be set to 1
4325 *
4326 * also, the manual doesn't mention it clearly but DCA hints
4327 * will only use queue 0's tags unless this bit is set. Side
4328 * effects of setting this bit are only that SRRCTL must be
4329 * fully programmed [0..15]
4330 */
4331 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
4332 break;
052a1a72
MR		 4333 case ixgbe_mac_X550:
4334 case ixgbe_mac_X550EM_x:
49425dfc 4335 case ixgbe_mac_x550em_a:
f961ddae
MR		 4336 if (adapter->num_vfs)
4337 rdrxctl |= IXGBE_RDRXCTL_PSP;
5463fce6 4338 fallthrough;
7367096a 4339 case ixgbe_mac_82599EB:
b93a2226 4340 case ixgbe_mac_X540:
7367096a
AD		 4341 /* Disable RSC for ACK packets */
4342 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
4343 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
4344 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4345 /* hardware requires some bits to be set by default */
4346 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
4347 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4348 break;
4349 default:
4350 /* We should do nothing since we don't know this hardware */
4351 return;
4352 }
4353
4354 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4355}
4356
477de6ed
AD		 4357/**
4358 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
4359 * @adapter: board private structure
4360 *
4361 * Configure the Rx unit of the MAC after a reset.
4362 **/
4363static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
4364{
4365 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 4366 int i;
6dcc28b9 4367 u32 rxctrl, rfctl;
477de6ed
AD		 4368
4369 /* disable receives while setting up the descriptors */
1f9ac57c 4370 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 4371
4372 ixgbe_setup_psrtype(adapter);
7367096a 4373 ixgbe_setup_rdrxctl(adapter);
477de6ed 4374
6dcc28b9
JK		 4375 /* RSC Setup */
4376 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4377 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4378 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
4379 rfctl |= IXGBE_RFCTL_RSC_DIS;
a21d0822
ET		 4380
4381 /* disable NFS filtering */
4382 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
6dcc28b9
JK		 4383 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4384
9e10e045 4385 /* Program registers for the distribution of queues */
f5b4a52e 4386 ixgbe_setup_mrqc(adapter);
f5b4a52e 4387
477de6ed
AD		 4388 /* set_rx_buffer_len must be called before ring initialization */
4389 ixgbe_set_rx_buffer_len(adapter);
4390
4391 /*
4392 * Setup the HW Rx Head and Tail Descriptor Pointers and
4393 * the Base and Length of the Rx Descriptor Ring
4394 */
9e10e045
AD		 4395 for (i = 0; i < adapter->num_rx_queues; i++)
4396 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 4397
1f9ac57c 4398 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 4399 /* disable drop enable for 82598 parts */
4400 if (hw->mac.type == ixgbe_mac_82598EB)
4401 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4402
4403 /* enable all receives */
4404 rxctrl |= IXGBE_RXCTRL_RXEN;
4405 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 4406}
4407
80d5c368
PM		 4408static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
4409 __be16 proto, u16 vid)
068c89b0
DS		 4410{
4411 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4412 struct ixgbe_hw *hw = &adapter->hw;
4413
4414 /* add VID to filter table */
18be4fce
AD		 4415 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4416 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
4417
f62bbb5e 4418 set_bit(vid, adapter->active_vlans);
8e586137
JP		 4419
4420 return 0;
068c89b0
DS		 4421}
4422
e1d0a2af
AD		 4423static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
4424{
4425 u32 vlvf;
4426 int idx;
4427
4428 /* short cut the special case */
4429 if (vlan == 0)
4430 return 0;
4431
4432 /* Search for the vlan id in the VLVF entries */
4433 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
4434 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
4435 if ((vlvf & VLAN_VID_MASK) == vlan)
4436 break;
4437 }
4438
4439 return idx;
4440}
4441
4442void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
4443{
4444 struct ixgbe_hw *hw = &adapter->hw;
4445 u32 bits, word;
4446 int idx;
4447
4448 idx = ixgbe_find_vlvf_entry(hw, vid);
4449 if (!idx)
4450 return;
4451
4452 /* See if any other pools are set for this VLAN filter
4453 * entry other than the PF.
4454 */
4455 word = idx * 2 + (VMDQ_P(0) / 32);
b4f47a48 4456 bits = ~BIT(VMDQ_P(0) % 32);
e1d0a2af
AD		 4457 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4458
4459 /* Disable the filter so this falls into the default pool. */
4460 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4461 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4462 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4463 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4464 }
4465}
4466
80d5c368
PM		 4467static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4468 __be16 proto, u16 vid)
068c89b0
DS		 4469{
4470 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4471 struct ixgbe_hw *hw = &adapter->hw;
4472
068c89b0 4473 /* remove VID from filter table */
18be4fce 4474 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
e1d0a2af
AD		 4475 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4476
f62bbb5e 4477 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 4478
4479 return 0;
068c89b0
DS		 4480}
4481
f62bbb5e
JG		 4482/**
4483 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4484 * @adapter: driver data
4485 */
4486static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4487{
4488 struct ixgbe_hw *hw = &adapter->hw;
4489 u32 vlnctrl;
5f6c0181
JB		 4490 int i, j;
4491
4492 switch (hw->mac.type) {
4493 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4494 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4495 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4496 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4497 break;
4498 case ixgbe_mac_82599EB:
b93a2226 4499 case ixgbe_mac_X540:
9a75a1ac
DS		 4500 case ixgbe_mac_X550:
4501 case ixgbe_mac_X550EM_x:
49425dfc 4502 case ixgbe_mac_x550em_a:
5f6c0181 4503 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4504 struct ixgbe_ring *ring = adapter->rx_ring[i];
4505
68ae7424 4506 if (!netif_is_ixgbe(ring->netdev))
2a47fa45 4507 continue;
68ae7424 4508
2a47fa45 4509 j = ring->reg_idx;
5f6c0181
JB		 4510 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4511 vlnctrl &= ~IXGBE_RXDCTL_VME;
4512 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4513 }
4514 break;
4515 default:
4516 break;
4517 }
4518}
4519
4520/**
f62bbb5e 4521 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 4522 * @adapter: driver data
4523 */
f62bbb5e 4524static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 4525{
4526 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 4527 u32 vlnctrl;
5f6c0181
JB		 4528 int i, j;
4529
4530 switch (hw->mac.type) {
4531 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4532 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4533 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4534 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4535 break;
4536 case ixgbe_mac_82599EB:
b93a2226 4537 case ixgbe_mac_X540:
9a75a1ac
DS		 4538 case ixgbe_mac_X550:
4539 case ixgbe_mac_X550EM_x:
49425dfc 4540 case ixgbe_mac_x550em_a:
5f6c0181 4541 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4542 struct ixgbe_ring *ring = adapter->rx_ring[i];
4543
68ae7424 4544 if (!netif_is_ixgbe(ring->netdev))
2a47fa45 4545 continue;
68ae7424 4546
2a47fa45 4547 j = ring->reg_idx;
5f6c0181
JB		 4548 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4549 vlnctrl |= IXGBE_RXDCTL_VME;
4550 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4551 }
4552 break;
4553 default:
4554 break;
4555 }
4556}
4557
16369564
AD		 4558static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4559{
4560 struct ixgbe_hw *hw = &adapter->hw;
4561 u32 vlnctrl, i;
4562
f60439bc
AD		 4563 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4564
691e4121
ET		 4565 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4566 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4567 vlnctrl |= IXGBE_VLNCTRL_VFE;
4568 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4569 } else {
f60439bc 4570 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
16369564
AD		 4571 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4572 return;
4573 }
4574
691e4121
ET		 4575 /* Nothing to do for 82598 */
4576 if (hw->mac.type == ixgbe_mac_82598EB)
4577 return;
4578
16369564
AD		 4579 /* We are already in VLAN promisc, nothing to do */
4580 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4581 return;
4582
4583 /* Set flag so we don't redo unnecessary work */
4584 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4585
4586 /* Add PF to all active pools */
4587 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4588 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4589 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4590
b4f47a48 4591 vlvfb |= BIT(VMDQ_P(0) % 32);
16369564
AD		 4592 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4593 }
4594
4595 /* Set all bits in the VLAN filter table array */
4596 for (i = hw->mac.vft_size; i--;)
4597 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4598}
4599
4600#define VFTA_BLOCK_SIZE 8
4601static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4602{
4603 struct ixgbe_hw *hw = &adapter->hw;
4604 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4605 u32 vid_start = vfta_offset * 32;
4606 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4607 u32 i, vid, word, bits;
4608
4609 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4610 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4611
4612 /* pull VLAN ID from VLVF */
4613 vid = vlvf & VLAN_VID_MASK;
4614
4615 /* only concern outselves with a certain range */
4616 if (vid < vid_start || vid >= vid_end)
4617 continue;
4618
4619 if (vlvf) {
4620 /* record VLAN ID in VFTA */
b4f47a48 4621 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16369564
AD		 4622
4623 /* if PF is part of this then continue */
4624 if (test_bit(vid, adapter->active_vlans))
4625 continue;
4626 }
4627
4628 /* remove PF from the pool */
4629 word = i * 2 + VMDQ_P(0) / 32;
b4f47a48 4630 bits = ~BIT(VMDQ_P(0) % 32);
16369564
AD		 4631 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4632 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4633 }
4634
4635 /* extract values from active_vlans and write back to VFTA */
4636 for (i = VFTA_BLOCK_SIZE; i--;) {
4637 vid = (vfta_offset + i) * 32;
4638 word = vid / BITS_PER_LONG;
4639 bits = vid % BITS_PER_LONG;
4640
4641 vfta[i] |= adapter->active_vlans[word] >> bits;
4642
4643 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4644 }
4645}
4646
4647static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4648{
4649 struct ixgbe_hw *hw = &adapter->hw;
4650 u32 vlnctrl, i;
4651
f60439bc
AD		 4652 /* Set VLAN filtering to enabled */
4653 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4654 vlnctrl |= IXGBE_VLNCTRL_VFE;
4655 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4656
691e4121
ET		 4657 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4658 hw->mac.type == ixgbe_mac_82598EB)
16369564 4659 return;
16369564
AD		 4660
4661 /* We are not in VLAN promisc, nothing to do */
4662 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4663 return;
4664
4665 /* Set flag so we don't redo unnecessary work */
4666 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4667
4668 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4669 ixgbe_scrub_vfta(adapter, i);
4670}
4671
9a799d71
AK		 4672static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4673{
06bb1c39 4674 u16 vid = 1;
9a799d71 4675
80d5c368 4676 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e 4677
06bb1c39 4678 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 4679 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 4680}
4681
b335e75b
JK		 4682/**
4683 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4684 * @netdev: network interface device structure
4685 *
4686 * Writes multicast address list to the MTA hash table.
4687 * Returns: -ENOMEM on failure
4688 * 0 on no addresses written
4689 * X on writing X addresses to MTA
4690 **/
4691static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4692{
4693 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4694 struct ixgbe_hw *hw = &adapter->hw;
4695
4696 if (!netif_running(netdev))
4697 return 0;
4698
4699 if (hw->mac.ops.update_mc_addr_list)
4700 hw->mac.ops.update_mc_addr_list(hw, netdev);
4701 else
4702 return -ENOMEM;
4703
4704#ifdef CONFIG_PCI_IOV
5d7daa35 4705 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4706#endif
4707
4708 return netdev_mc_count(netdev);
4709}
4710
5d7daa35
JK		 4711#ifdef CONFIG_PCI_IOV
4712void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4713{
c9f53e63 4714 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4715 struct ixgbe_hw *hw = &adapter->hw;
4716 int i;
c9f53e63
AD		 4717
4718 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4719 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4720
4721 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4722 hw->mac.ops.set_rar(hw, i,
4723 mac_table->addr,
4724 mac_table->pool,
5d7daa35
JK		 4725 IXGBE_RAH_AV);
4726 else
4727 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4728 }
4729}
5d7daa35 4730
c9f53e63 4731#endif
5d7daa35
JK		 4732static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4733{
c9f53e63 4734 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4735 struct ixgbe_hw *hw = &adapter->hw;
4736 int i;
5d7daa35 4737
c9f53e63
AD		 4738 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4739 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4740 continue;
4741
4742 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4743
4744 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4745 hw->mac.ops.set_rar(hw, i,
4746 mac_table->addr,
4747 mac_table->pool,
4748 IXGBE_RAH_AV);
4749 else
4750 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4751 }
4752}
4753
4754static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4755{
c9f53e63 4756 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4757 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4758 int i;
5d7daa35 4759
c9f53e63
AD		 4760 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4761 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4762 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
5d7daa35 4763 }
c9f53e63 4764
5d7daa35
JK		 4765 ixgbe_sync_mac_table(adapter);
4766}
4767
c9f53e63 4768static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
5d7daa35 4769{
c9f53e63 4770 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4771 struct ixgbe_hw *hw = &adapter->hw;
4772 int i, count = 0;
4773
c9f53e63
AD		 4774 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4775 /* do not count default RAR as available */
4776 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4777 continue;
4778
4779 /* only count unused and addresses that belong to us */
4780 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4781 if (mac_table->pool != pool)
4782 continue;
4783 }
4784
4785 count++;
5d7daa35 4786 }
c9f53e63 4787
5d7daa35
JK		 4788 return count;
4789}
4790
4791/* this function destroys the first RAR entry */
c9f53e63 4792static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
5d7daa35 4793{
c9f53e63 4794 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4795 struct ixgbe_hw *hw = &adapter->hw;
4796
c9f53e63
AD		 4797 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4798 mac_table->pool = VMDQ_P(0);
4799
4800 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4801
4802 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
5d7daa35
JK		 4803 IXGBE_RAH_AV);
4804}
4805
c9f53e63
AD		 4806int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4807 const u8 *addr, u16 pool)
5d7daa35 4808{
c9f53e63 4809 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4810 struct ixgbe_hw *hw = &adapter->hw;
4811 int i;
4812
4813 if (is_zero_ether_addr(addr))
4814 return -EINVAL;
4815
c9f53e63
AD		 4816 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4817 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
5d7daa35 4818 continue;
c9f53e63
AD		 4819
4820 ether_addr_copy(mac_table->addr, addr);
4821 mac_table->pool = pool;
4822
4823 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4824 IXGBE_MAC_STATE_IN_USE;
4825
5d7daa35 4826 ixgbe_sync_mac_table(adapter);
c9f53e63 4827
5d7daa35
JK		 4828 return i;
4829 }
c9f53e63 4830
5d7daa35
JK		 4831 return -ENOMEM;
4832}
4833
c9f53e63
AD		 4834int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4835 const u8 *addr, u16 pool)
5d7daa35 4836{
c9f53e63 4837 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4838 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4839 int i;
5d7daa35
JK		 4840
4841 if (is_zero_ether_addr(addr))
4842 return -EINVAL;
4843
c9f53e63
AD		 4844 /* search table for addr, if found clear IN_USE flag and sync */
4845 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4846 /* we can only delete an entry if it is in use */
4847 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4848 continue;
4849 /* we only care about entries that belong to the given pool */
4850 if (mac_table->pool != pool)
4851 continue;
4852 /* we only care about a specific MAC address */
4853 if (!ether_addr_equal(addr, mac_table->addr))
4854 continue;
4855
4856 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4857 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4858
4859 ixgbe_sync_mac_table(adapter);
4860
4861 return 0;
5d7daa35 4862 }
c9f53e63 4863
5d7daa35
JK		 4864 return -ENOMEM;
4865}
5ba643c6 4866
0f079d22
AD		 4867static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4868{
4869 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4870 int ret;
4871
4872 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4873
4874 return min_t(int, ret, 0);
4875}
4876
4877static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4878{
4879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4880
4881 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4882
4883 return 0;
4884}
4885
9a799d71 4886/**
2c5645cf 4887 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4888 * @netdev: network interface device structure
4889 *
2c5645cf
CL		 4890 * The set_rx_method entry point is called whenever the unicast/multicast
4891 * address list or the network interface flags are updated. This routine is
4892 * responsible for configuring the hardware for proper unicast, multicast and
4893 * promiscuous mode.
9a799d71 4894 **/
7f870475 4895void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4896{
4897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4898 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4899 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
0c5a6166 4900 netdev_features_t features = netdev->features;
2850062a 4901 int count;
9a799d71
AK		 4902
4903 /* Check for Promiscuous and All Multicast modes */
9a799d71
AK		 4904 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4905
f5dc442b 4906 /* set all bits that we expect to always be set */
3f2d1c0f 4907 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4908 fctrl |= IXGBE_FCTRL_BAM;
4909 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4910 fctrl |= IXGBE_FCTRL_PMCF;
4911
2850062a
AD		 4912 /* clear the bits we are changing the status of */
4913 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
9a799d71 4914 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4915 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4916 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4917 vmolr |= IXGBE_VMOLR_MPE;
0c5a6166 4918 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
9a799d71 4919 } else {
746b9f02
PM		 4920 if (netdev->flags & IFF_ALLMULTI) {
4921 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4922 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4923 }
e433ea1f 4924 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4925 }
4926
4927 /*
4928 * Write addresses to available RAR registers, if there is not
4929 * sufficient space to store all the addresses then enable
4930 * unicast promiscuous mode
4931 */
0f079d22 4932 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
9dcb373c
JF		 4933 fctrl |= IXGBE_FCTRL_UPE;
4934 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4935 }
4936
cf78959c
ET		 4937 /* Write addresses to the MTA, if the attempt fails
4938 * then we should just turn on promiscuous mode so
4939 * that we can at least receive multicast traffic
4940 */
b335e75b
JK		 4941 count = ixgbe_write_mc_addr_list(netdev);
4942 if (count < 0) {
4943 fctrl |= IXGBE_FCTRL_MPE;
4944 vmolr |= IXGBE_VMOLR_MPE;
4945 } else if (count) {
4946 vmolr |= IXGBE_VMOLR_ROMPE;
4947 }
1d9c0bfd
AD		 4948
4949 if (hw->mac.type != ixgbe_mac_82598EB) {
4950 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4951 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4952 IXGBE_VMOLR_ROPE);
1d9c0bfd 4953 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4954 }
4955
3f2d1c0f 4956 /* This is useful for sniffing bad packets. */
0c5a6166 4957 if (features & NETIF_F_RXALL) {
3f2d1c0f
BG		 4958 /* UPE and MPE will be handled by normal PROMISC logic
4959 * in e1000e_set_rx_mode */
4960 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4961 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4962 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4963
4964 fctrl &= ~(IXGBE_FCTRL_DPF);
4965 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4966 }
4967
2850062a 4968 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4969
0c5a6166 4970 if (features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4971 ixgbe_vlan_strip_enable(adapter);
4972 else
4973 ixgbe_vlan_strip_disable(adapter);
0c5a6166
AD		 4974
4975 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4976 ixgbe_vlan_promisc_disable(adapter);
4977 else
4978 ixgbe_vlan_promisc_enable(adapter);
9a799d71
AK		 4979}
4980
021230d4
AV		 4981static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4982{
4983 int q_idx;
021230d4 4984
3ffc1af5 4985 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
49c7ffbe 4986 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 4987}
4988
4989static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4990{
4991 int q_idx;
021230d4 4992
3ffc1af5 4993 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
49c7ffbe 4994 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 4995}
4996
dc221851 4997static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table)
67359c3c 4998{
dc221851 4999 struct ixgbe_adapter *adapter = netdev_priv(dev);
a21d0822 5000 struct ixgbe_hw *hw = &adapter->hw;
dc221851 5001 struct udp_tunnel_info ti;
a21d0822 5002
dc221851
JK		 5003 udp_tunnel_nic_get_port(dev, table, 0, &ti);
5004 if (ti.type == UDP_TUNNEL_TYPE_VXLAN)
5005 adapter->vxlan_port = ti.port;
5006 else
5007 adapter->geneve_port = ti.port;
a21d0822 5008
dc221851
JK		 5009 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL,
5010 ntohs(adapter->vxlan_port) |
5011 ntohs(adapter->geneve_port) <<
5012 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT);
5013 return 0;
5014}
a21d0822 5015
dc221851
JK		 5016static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = {
5017 .sync_table = ixgbe_udp_tunnel_sync,
5018 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5019 .tables = {
5020 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
5021 },
5022};
a21d0822 5023
dc221851
JK		 5024static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = {
5025 .sync_table = ixgbe_udp_tunnel_sync,
5026 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5027 .tables = {
5028 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
5029 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
5030 },
5031};
67359c3c 5032
7a6b6f51 5033#ifdef CONFIG_IXGBE_DCB
49ce9c2c 5034/**
2f90b865
AD		 5035 * ixgbe_configure_dcb - Configure DCB hardware
5036 * @adapter: ixgbe adapter struct
5037 *
5038 * This is called by the driver on open to configure the DCB hardware.
5039 * This is also called by the gennetlink interface when reconfiguring
5040 * the DCB state.
5041 */
5042static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
5043{
5044 struct ixgbe_hw *hw = &adapter->hw;
9806307a 5045 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 5046
67ebd791
AD		 5047 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
5048 if (hw->mac.type == ixgbe_mac_82598EB)
5049 netif_set_gso_max_size(adapter->netdev, 65536);
5050 return;
5051 }
5052
5053 if (hw->mac.type == ixgbe_mac_82598EB)
5054 netif_set_gso_max_size(adapter->netdev, 32768);
5055
971060b1 5056#ifdef IXGBE_FCOE
b120818e
JF		 5057 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
5058 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 5059#endif
b120818e
JF		 5060
5061 /* reconfigure the hardware */
5062 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 5063 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5064 DCB_TX_CONFIG);
5065 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5066 DCB_RX_CONFIG);
5067 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 5068 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
5069 ixgbe_dcb_hw_ets(&adapter->hw,
5070 adapter->ixgbe_ieee_ets,
5071 max_frame);
5072 ixgbe_dcb_hw_pfc_config(&adapter->hw,
5073 adapter->ixgbe_ieee_pfc->pfc_en,
5074 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 5075 }
8187cd48
JF		 5076
5077 /* Enable RSS Hash per TC */
5078 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 5079 u32 msb = 0;
5080 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 5081
d411a936
AD		 5082 while (rss_i) {
5083 msb++;
5084 rss_i >>= 1;
5085 }
8187cd48 5086
4ae63730
AD		 5087 /* write msb to all 8 TCs in one write */
5088 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 5089 }
2f90b865 5090}
9da712d2
JF		 5091#endif
5092
5093/* Additional bittime to account for IXGBE framing */
5094#define IXGBE_ETH_FRAMING 20
5095
49ce9c2c 5096/**
9da712d2
JF		 5097 * ixgbe_hpbthresh - calculate high water mark for flow control
5098 *
5099 * @adapter: board private structure to calculate for
49ce9c2c 5100 * @pb: packet buffer to calculate
9da712d2
JF		 5101 */
5102static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
5103{
5104 struct ixgbe_hw *hw = &adapter->hw;
5105 struct net_device *dev = adapter->netdev;
5106 int link, tc, kb, marker;
5107 u32 dv_id, rx_pba;
5108
5109 /* Calculate max LAN frame size */
5110 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
5111
5112#ifdef IXGBE_FCOE
5113 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 5114 if ((dev->features & NETIF_F_FCOE_MTU) &&
5115 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5116 (pb == ixgbe_fcoe_get_tc(adapter)))
5117 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 5118#endif
e5776620 5119
9da712d2
JF		 5120 /* Calculate delay value for device */
5121 switch (hw->mac.type) {
5122 case ixgbe_mac_X540:
9a75a1ac
DS		 5123 case ixgbe_mac_X550:
5124 case ixgbe_mac_X550EM_x:
49425dfc 5125 case ixgbe_mac_x550em_a:
9da712d2
JF		 5126 dv_id = IXGBE_DV_X540(link, tc);
5127 break;
5128 default:
5129 dv_id = IXGBE_DV(link, tc);
5130 break;
5131 }
5132
5133 /* Loopback switch introduces additional latency */
5134 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5135 dv_id += IXGBE_B2BT(tc);
5136
5137 /* Delay value is calculated in bit times convert to KB */
5138 kb = IXGBE_BT2KB(dv_id);
5139 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
5140
5141 marker = rx_pba - kb;
5142
5143 /* It is possible that the packet buffer is not large enough
5144 * to provide required headroom. In this case throw an error
5145 * to user and a do the best we can.
5146 */
5147 if (marker < 0) {
5148 e_warn(drv, "Packet Buffer(%i) can not provide enough"
5149 "headroom to support flow control."
5150 "Decrease MTU or number of traffic classes\n", pb);
5151 marker = tc + 1;
5152 }
5153
5154 return marker;
5155}
5156
49ce9c2c 5157/**
9da712d2
JF		 5158 * ixgbe_lpbthresh - calculate low water mark for for flow control
5159 *
5160 * @adapter: board private structure to calculate for
49ce9c2c 5161 * @pb: packet buffer to calculate
9da712d2 5162 */
e5776620 5163static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 5164{
5165 struct ixgbe_hw *hw = &adapter->hw;
5166 struct net_device *dev = adapter->netdev;
5167 int tc;
5168 u32 dv_id;
5169
5170 /* Calculate max LAN frame size */
5171 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5172
e5776620
JK		 5173#ifdef IXGBE_FCOE
5174 /* FCoE traffic class uses FCOE jumbo frames */
5175 if ((dev->features & NETIF_F_FCOE_MTU) &&
5176 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5177 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
5178 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5179#endif
5180
9da712d2
JF		 5181 /* Calculate delay value for device */
5182 switch (hw->mac.type) {
5183 case ixgbe_mac_X540:
9a75a1ac
DS		 5184 case ixgbe_mac_X550:
5185 case ixgbe_mac_X550EM_x:
49425dfc 5186 case ixgbe_mac_x550em_a:
9da712d2
JF		 5187 dv_id = IXGBE_LOW_DV_X540(tc);
5188 break;
5189 default:
5190 dv_id = IXGBE_LOW_DV(tc);
5191 break;
5192 }
5193
5194 /* Delay value is calculated in bit times convert to KB */
5195 return IXGBE_BT2KB(dv_id);
5196}
5197
5198/*
5199 * ixgbe_pbthresh_setup - calculate and setup high low water marks
5200 */
5201static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
5202{
5203 struct ixgbe_hw *hw = &adapter->hw;
0efbf12b 5204 int num_tc = adapter->hw_tcs;
9da712d2
JF		 5205 int i;
5206
5207 if (!num_tc)
5208 num_tc = 1;
5209
9da712d2
JF		 5210 for (i = 0; i < num_tc; i++) {
5211 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 5212 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 5213
5214 /* Low water marks must not be larger than high water marks */
e5776620
JK		 5215 if (hw->fc.low_water[i] > hw->fc.high_water[i])
5216 hw->fc.low_water[i] = 0;
9da712d2 5217 }
e5776620
JK		 5218
5219 for (; i < MAX_TRAFFIC_CLASS; i++)
5220 hw->fc.high_water[i] = 0;
9da712d2
JF		 5221}
5222
80605c65
JF		 5223static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
5224{
80605c65 5225 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f 5226 int hdrm;
0efbf12b 5227 u8 tc = adapter->hw_tcs;
80605c65
JF		 5228
5229 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5230 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 5231 hdrm = 32 << adapter->fdir_pballoc;
5232 else
5233 hdrm = 0;
80605c65 5234
f7e1027f 5235 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 5236 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 5237}
5238
e4911d57
AD		 5239static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
5240{
5241 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 5242 struct hlist_node *node2;
e4911d57 5243 struct ixgbe_fdir_filter *filter;
4fad78ad 5244 u8 queue;
e4911d57
AD		 5245
5246 spin_lock(&adapter->fdir_perfect_lock);
5247
5248 if (!hlist_empty(&adapter->fdir_filter_list))
5249 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
5250
b67bfe0d 5251 hlist_for_each_entry_safe(filter, node2,
e4911d57 5252 &adapter->fdir_filter_list, fdir_node) {
4fad78ad
CZ		 5253 if (filter->action == IXGBE_FDIR_DROP_QUEUE) {
5254 queue = IXGBE_FDIR_DROP_QUEUE;
5255 } else {
5256 u32 ring = ethtool_get_flow_spec_ring(filter->action);
5257 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action);
5258
5259 if (!vf && (ring >= adapter->num_rx_queues)) {
5260 e_err(drv, "FDIR restore failed without VF, ring: %u\n",
5261 ring);
5262 continue;
5263 } else if (vf &&
5264 ((vf > adapter->num_vfs) ||
5265 ring >= adapter->num_rx_queues_per_pool)) {
5266 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n",
5267 vf, ring);
5268 continue;
5269 }
5270
5271 /* Map the ring onto the absolute queue index */
5272 if (!vf)
5273 queue = adapter->rx_ring[ring]->reg_idx;
5274 else
5275 queue = ((vf - 1) *
5276 adapter->num_rx_queues_per_pool) + ring;
5277 }
5d826d20 5278
e4911d57 5279 ixgbe_fdir_write_perfect_filter_82599(hw,
4fad78ad 5280 &filter->filter, filter->sw_idx, queue);
e4911d57
AD		 5281 }
5282
5283 spin_unlock(&adapter->fdir_perfect_lock);
5284}
5285
2a47fa45
JF		 5286/**
5287 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
5288 * @rx_ring: ring to free buffers from
5289 **/
5290static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
5291{
ffed21bc
AD		 5292 u16 i = rx_ring->next_to_clean;
5293 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 5294
1742b3d5 5295 if (rx_ring->xsk_pool) {
d0bcacd0
BT		 5296 ixgbe_xsk_clean_rx_ring(rx_ring);
5297 goto skip_free;
5298 }
5299
2a47fa45 5300 /* Free all the Rx ring sk_buffs */
ffed21bc 5301 while (i != rx_ring->next_to_alloc) {
2a47fa45
JF		 5302 if (rx_buffer->skb) {
5303 struct sk_buff *skb = rx_buffer->skb;
18cb652a 5304 if (IXGBE_CB(skb)->page_released)
ffed21bc 5305 dma_unmap_page_attrs(rx_ring->dev,
f3213d93
AD		 5306 IXGBE_CB(skb)->dma,
5307 ixgbe_rx_pg_size(rx_ring),
5308 DMA_FROM_DEVICE,
5309 IXGBE_RX_DMA_ATTR);
2a47fa45
JF		 5310 dev_kfree_skb(skb);
5311 }
18cb652a 5312
f3213d93
AD		 5313 /* Invalidate cache lines that may have been written to by
5314 * device so that we avoid corrupting memory.
5315 */
5316 dma_sync_single_range_for_cpu(rx_ring->dev,
5317 rx_buffer->dma,
5318 rx_buffer->page_offset,
5319 ixgbe_rx_bufsz(rx_ring),
5320 DMA_FROM_DEVICE);
5321
5322 /* free resources associated with mapping */
ffed21bc 5323 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
f3213d93
AD		 5324 ixgbe_rx_pg_size(rx_ring),
5325 DMA_FROM_DEVICE,
5326 IXGBE_RX_DMA_ATTR);
1b56cf49
AD		 5327 __page_frag_cache_drain(rx_buffer->page,
5328 rx_buffer->pagecnt_bias);
18cb652a 5329
ffed21bc
AD		 5330 i++;
5331 rx_buffer++;
5332 if (i == rx_ring->count) {
5333 i = 0;
5334 rx_buffer = rx_ring->rx_buffer_info;
5335 }
2a47fa45
JF		 5336 }
5337
d0bcacd0 5338skip_free:
2a47fa45
JF		 5339 rx_ring->next_to_alloc = 0;
5340 rx_ring->next_to_clean = 0;
5341 rx_ring->next_to_use = 0;
5342}
5343
865255b5 5344static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter,
2a47fa45
JF		 5345 struct ixgbe_fwd_adapter *accel)
5346{
58b0b3ed
AD		 5347 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
5348 int num_tc = netdev_get_num_tc(adapter->netdev);
865255b5 5349 struct net_device *vdev = accel->netdev;
16be45bc 5350 int i, baseq, err;
2a47fa45 5351
2a47fa45 5352 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4e039c16 5353 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n",
2a47fa45 5354 accel->pool, adapter->num_rx_pools,
4e039c16 5355 baseq, baseq + adapter->num_rx_queues_per_pool);
2a47fa45 5356
16be45bc
AD		 5357 accel->rx_base_queue = baseq;
5358 accel->tx_base_queue = baseq;
2a47fa45 5359
58b0b3ed
AD		 5360 /* record configuration for macvlan interface in vdev */
5361 for (i = 0; i < num_tc; i++)
5362 netdev_bind_sb_channel_queue(adapter->netdev, vdev,
5363 i, rss_i, baseq + (rss_i * i));
5364
2a47fa45 5365 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
16be45bc 5366 adapter->rx_ring[baseq + i]->netdev = vdev;
b5f69ccf
AD		 5367
5368 /* Guarantee all rings are updated before we update the
5369 * MAC address filter.
5370 */
5371 wmb();
2a47fa45 5372
4a2512cf
AD		 5373 /* ixgbe_add_mac_filter will return an index if it succeeds, so we
5374 * need to only treat it as an error value if it is negative.
5375 */
5376 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr,
5377 VMDQ_P(accel->pool));
81d4e91c 5378 if (err >= 0)
b5f69ccf 5379 return 0;
b5f69ccf 5380
8315ef6f
AD		 5381 /* if we cannot add the MAC rule then disable the offload */
5382 macvlan_release_l2fw_offload(vdev);
5383
b5f69ccf
AD		 5384 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5385 adapter->rx_ring[baseq + i]->netdev = NULL;
2a47fa45 5386
8315ef6f
AD		 5387 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n");
5388
58b0b3ed
AD		 5389 /* unbind the queues and drop the subordinate channel config */
5390 netdev_unbind_sb_channel(adapter->netdev, vdev);
5391 netdev_set_sb_channel(vdev, 0);
5392
8315ef6f
AD		 5393 clear_bit(accel->pool, adapter->fwd_bitmask);
5394 kfree(accel);
5395
2a47fa45
JF		 5396 return err;
5397}
5398
eff74233
TY		 5399static int ixgbe_macvlan_up(struct net_device *vdev,
5400 struct netdev_nested_priv *priv)
2a47fa45 5401{
eff74233 5402 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
865255b5 5403 struct ixgbe_fwd_adapter *accel;
2a47fa45 5404
865255b5
AD		 5405 if (!netif_is_macvlan(vdev))
5406 return 0;
5407
5408 accel = macvlan_accel_priv(vdev);
5409 if (!accel)
5410 return 0;
5411
5412 ixgbe_fwd_ring_up(adapter, accel);
1cd127fc
DA		 5413
5414 return 0;
5415}
5416
5417static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5418{
eff74233
TY		 5419 struct netdev_nested_priv priv = {
5420 .data = (void *)adapter,
5421 };
5422
1cd127fc 5423 netdev_walk_all_upper_dev_rcu(adapter->netdev,
eff74233 5424 ixgbe_macvlan_up, &priv);
2a47fa45
JF		 5425}
5426
9a799d71
AK		 5427static void ixgbe_configure(struct ixgbe_adapter *adapter)
5428{
d2f5e7f3
AS		 5429 struct ixgbe_hw *hw = &adapter->hw;
5430
80605c65 5431 ixgbe_configure_pb(adapter);
7a6b6f51 5432#ifdef CONFIG_IXGBE_DCB
67ebd791 5433 ixgbe_configure_dcb(adapter);
2f90b865 5434#endif
b35d4d42
AD		 5435 /*
5436 * We must restore virtualization before VLANs or else
5437 * the VLVF registers will not be populated
5438 */
5439 ixgbe_configure_virtualization(adapter);
9a799d71 5440
4c1d7b4b 5441 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e 5442 ixgbe_restore_vlan(adapter);
6d73a154 5443 ixgbe_ipsec_restore(adapter);
f62bbb5e 5444
d2f5e7f3
AS		 5445 switch (hw->mac.type) {
5446 case ixgbe_mac_82599EB:
5447 case ixgbe_mac_X540:
5448 hw->mac.ops.disable_rx_buff(hw);
5449 break;
5450 default:
5451 break;
5452 }
5453
c4cf55e5 5454 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 5455 ixgbe_init_fdir_signature_82599(&adapter->hw,
5456 adapter->fdir_pballoc);
e4911d57
AD		 5457 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5458 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5459 adapter->fdir_pballoc);
5460 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 5461 }
4c1d7b4b 5462
d2f5e7f3
AS		 5463 switch (hw->mac.type) {
5464 case ixgbe_mac_82599EB:
5465 case ixgbe_mac_X540:
5466 hw->mac.ops.enable_rx_buff(hw);
5467 break;
5468 default:
5469 break;
5470 }
5471
9de7605e
MR		 5472#ifdef CONFIG_IXGBE_DCA
5473 /* configure DCA */
5474 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5475 ixgbe_setup_dca(adapter);
5476#endif /* CONFIG_IXGBE_DCA */
5477
7c8ae65a
AD		 5478#ifdef IXGBE_FCOE
5479 /* configure FCoE L2 filters, redirection table, and Rx control */
5480 ixgbe_configure_fcoe(adapter);
5481
5482#endif /* IXGBE_FCOE */
9a799d71
AK		 5483 ixgbe_configure_tx(adapter);
5484 ixgbe_configure_rx(adapter);
2a47fa45 5485 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 5486}
5487
0ecc061d 5488/**
e8e26350
PW		 5489 * ixgbe_sfp_link_config - set up SFP+ link
5490 * @adapter: pointer to private adapter struct
5491 **/
5492static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5493{
7086400d 5494 /*
52f33af8 5495 * We are assuming the worst case scenario here, and that
7086400d
AD		 5496 * is that an SFP was inserted/removed after the reset
5497 * but before SFP detection was enabled. As such the best
5498 * solution is to just start searching as soon as we start
5499 */
5500 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5501 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 5502
7086400d 5503 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 5504 adapter->sfp_poll_time = 0;
e8e26350
PW		 5505}
5506
5507/**
5508 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 5509 * @hw: pointer to private hardware struct
5510 *
5511 * Returns 0 on success, negative on failure
5512 **/
e8e26350 5513static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 5514{
3d292265
JH		 5515 u32 speed;
5516 bool autoneg, link_up = false;
a1e869de 5517 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 5518
5519 if (hw->mac.ops.check_link)
3d292265 5520 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 5521
5522 if (ret)
e90dd264 5523 return ret;
0ecc061d 5524
3d292265 5525 speed = hw->phy.autoneg_advertised;
a296d665 5526 if (!speed && hw->mac.ops.get_link_capabilities) {
3d292265
JH		 5527 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5528 &autoneg);
a296d665
RT		 5529 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL |
5530 IXGBE_LINK_SPEED_2_5GB_FULL);
5531 }
5532
0ecc061d 5533 if (ret)
e90dd264 5534 return ret;
0ecc061d 5535
8620a103 5536 if (hw->mac.ops.setup_link)
fd0326f2 5537 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 5538
0ecc061d
PWJ		 5539 return ret;
5540}
5541
a34bcfff 5542static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 5543{
9a799d71 5544 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5545 u32 gpie = 0;
9a799d71 5546
9b471446 5547 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 5548 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5549 IXGBE_GPIE_OCD;
5550 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 5551 /*
5552 * use EIAM to auto-mask when MSI-X interrupt is asserted
5553 * this saves a register write for every interrupt
5554 */
5555 switch (hw->mac.type) {
5556 case ixgbe_mac_82598EB:
5557 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5558 break;
9b471446 5559 case ixgbe_mac_82599EB:
b93a2226 5560 case ixgbe_mac_X540:
9a75a1ac
DS		 5561 case ixgbe_mac_X550:
5562 case ixgbe_mac_X550EM_x:
49425dfc 5563 case ixgbe_mac_x550em_a:
b93a2226 5564 default:
9b471446
JB		 5565 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5566 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5567 break;
5568 }
5569 } else {
021230d4
AV		 5570 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5571 * specifically only auto mask tx and rx interrupts */
5572 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5573 }
9a799d71 5574
a34bcfff
AD		 5575 /* XXX: to interrupt immediately for EICS writes, enable this */
5576 /* gpie |= IXGBE_GPIE_EIMEN; */
5577
5578 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5579 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 5580
5581 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5582 case IXGBE_82599_VMDQ_8Q_MASK:
5583 gpie |= IXGBE_GPIE_VTMODE_16;
5584 break;
5585 case IXGBE_82599_VMDQ_4Q_MASK:
5586 gpie |= IXGBE_GPIE_VTMODE_32;
5587 break;
5588 default:
5589 gpie |= IXGBE_GPIE_VTMODE_64;
5590 break;
5591 }
119fc60a
MC		 5592 }
5593
5fdd31f9 5594 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 5595 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5596 switch (adapter->hw.mac.type) {
5597 case ixgbe_mac_82599EB:
9a900eca 5598 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 5599 break;
f3df98ec
DS		 5600 default:
5601 break;
5602 }
5603 }
5fdd31f9 5604
a34bcfff
AD		 5605 /* Enable fan failure interrupt */
5606 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 5607 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 5608
a023bbd0
DS		 5609 switch (hw->mac.type) {
5610 case ixgbe_mac_82599EB:
5611 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5612 break;
5613 case ixgbe_mac_X550EM_x:
49425dfc 5614 case ixgbe_mac_x550em_a:
a023bbd0
DS		 5615 gpie |= IXGBE_SDP0_GPIEN_X540;
5616 break;
5617 default:
5618 break;
2698b208 5619 }
a34bcfff
AD		 5620
5621 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5622}
5623
c7ccde0f 5624static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 5625{
5626 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5627 int err;
a34bcfff
AD		 5628 u32 ctrl_ext;
5629
5630 ixgbe_get_hw_control(adapter);
5631 ixgbe_setup_gpie(adapter);
e8e26350 5632
9a799d71
AK		 5633 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5634 ixgbe_configure_msix(adapter);
5635 else
5636 ixgbe_configure_msi_and_legacy(adapter);
5637
ec74a471
ET		 5638 /* enable the optics for 82599 SFP+ fiber */
5639 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 5640 hw->mac.ops.enable_tx_laser(hw);
5641
961fac88
DS		 5642 if (hw->phy.ops.set_phy_power)
5643 hw->phy.ops.set_phy_power(hw, true);
5644
4e857c58 5645 smp_mb__before_atomic();
9a799d71 5646 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 5647 ixgbe_napi_enable_all(adapter);
5648
73c4b7cd
AD		 5649 if (ixgbe_is_sfp(hw)) {
5650 ixgbe_sfp_link_config(adapter);
5651 } else {
5652 err = ixgbe_non_sfp_link_config(hw);
5653 if (err)
5654 e_err(probe, "link_config FAILED %d\n", err);
5655 }
5656
021230d4
AV		 5657 /* clear any pending interrupts, may auto mask */
5658 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 5659 ixgbe_irq_enable(adapter, true, true);
9a799d71 5660
bf069c97
DS		 5661 /*
5662 * If this adapter has a fan, check to see if we had a failure
5663 * before we enabled the interrupt.
5664 */
5665 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5666 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5667 if (esdp & IXGBE_ESDP_SDP1)
396e799c 5668 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 5669 }
5670
9a799d71
AK		 5671 /* bring the link up in the watchdog, this could race with our first
5672 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 5673 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5674 adapter->link_check_timeout = jiffies;
7086400d 5675 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 5676
5677 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5678 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5679 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5680 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5681}
5682
d4f80882
AV		 5683void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5684{
7086400d 5685 /* put off any impending NetWatchDogTimeout */
860e9538 5686 netif_trans_update(adapter->netdev);
7086400d 5687
d4f80882 5688 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5689 usleep_range(1000, 2000);
b3eb4e18
MR		 5690 if (adapter->hw.phy.type == ixgbe_phy_fw)
5691 ixgbe_watchdog_link_is_down(adapter);
d4f80882 5692 ixgbe_down(adapter);
5809a1ae
GR		 5693 /*
5694 * If SR-IOV enabled then wait a bit before bringing the adapter
5695 * back up to give the VFs time to respond to the reset. The
5696 * two second wait is based upon the watchdog timer cycle in
5697 * the VF driver.
5698 */
5699 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5700 msleep(2000);
d4f80882
AV		 5701 ixgbe_up(adapter);
5702 clear_bit(__IXGBE_RESETTING, &adapter->state);
5703}
5704
c7ccde0f 5705void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5706{
5707 /* hardware has been reset, we need to reload some things */
5708 ixgbe_configure(adapter);
5709
c7ccde0f 5710 ixgbe_up_complete(adapter);
9a799d71
AK		 5711}
5712
1918e937
AD		 5713static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter)
5714{
5715 u16 devctl2;
5716
5717 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2);
5718
5719 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) {
5720 case IXGBE_PCIDEVCTRL2_17_34s:
5721 case IXGBE_PCIDEVCTRL2_4_8s:
5722 /* For now we cap the upper limit on delay to 2 seconds
5723 * as we end up going up to 34 seconds of delay in worst
5724 * case timeout value.
5725 */
5726 case IXGBE_PCIDEVCTRL2_1_2s:
5727 return 2000000ul; /* 2.0 s */
5728 case IXGBE_PCIDEVCTRL2_260_520ms:
5729 return 520000ul; /* 520 ms */
5730 case IXGBE_PCIDEVCTRL2_65_130ms:
5731 return 130000ul; /* 130 ms */
5732 case IXGBE_PCIDEVCTRL2_16_32ms:
5733 return 32000ul; /* 32 ms */
5734 case IXGBE_PCIDEVCTRL2_1_2ms:
5735 return 2000ul; /* 2 ms */
5736 case IXGBE_PCIDEVCTRL2_50_100us:
5737 return 100ul; /* 100 us */
5738 case IXGBE_PCIDEVCTRL2_16_32ms_def:
5739 return 32000ul; /* 32 ms */
5740 default:
5741 break;
5742 }
5743
5744 /* We shouldn't need to hit this path, but just in case default as
5745 * though completion timeout is not supported and support 32ms.
5746 */
5747 return 32000ul;
5748}
5749
5750void ixgbe_disable_rx(struct ixgbe_adapter *adapter)
5751{
5752 unsigned long wait_delay, delay_interval;
5753 struct ixgbe_hw *hw = &adapter->hw;
5754 int i, wait_loop;
5755 u32 rxdctl;
5756
5757 /* disable receives */
5758 hw->mac.ops.disable_rx(hw);
5759
5760 if (ixgbe_removed(hw->hw_addr))
5761 return;
5762
5763 /* disable all enabled Rx queues */
5764 for (i = 0; i < adapter->num_rx_queues; i++) {
5765 struct ixgbe_ring *ring = adapter->rx_ring[i];
5766 u8 reg_idx = ring->reg_idx;
5767
5768 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5769 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5770 rxdctl |= IXGBE_RXDCTL_SWFLSH;
5771
5772 /* write value back with RXDCTL.ENABLE bit cleared */
5773 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
5774 }
5775
5776 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
5777 if (hw->mac.type == ixgbe_mac_82598EB &&
5778 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5779 return;
5780
5781 /* Determine our minimum delay interval. We will increase this value
5782 * with each subsequent test. This way if the device returns quickly
5783 * we should spend as little time as possible waiting, however as
5784 * the time increases we will wait for larger periods of time.
5785 *
5786 * The trick here is that we increase the interval using the
5787 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5788 * of that wait is that it totals up to 100x whatever interval we
5789 * choose. Since our minimum wait is 100us we can just divide the
5790 * total timeout by 100 to get our minimum delay interval.
5791 */
5792 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5793
5794 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5795 wait_delay = delay_interval;
5796
5797 while (wait_loop--) {
5798 usleep_range(wait_delay, wait_delay + 10);
5799 wait_delay += delay_interval * 2;
5800 rxdctl = 0;
5801
5802 /* OR together the reading of all the active RXDCTL registers,
5803 * and then test the result. We need the disable to complete
5804 * before we start freeing the memory and invalidating the
5805 * DMA mappings.
5806 */
5807 for (i = 0; i < adapter->num_rx_queues; i++) {
5808 struct ixgbe_ring *ring = adapter->rx_ring[i];
5809 u8 reg_idx = ring->reg_idx;
5810
5811 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5812 }
5813
5814 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
5815 return;
5816 }
5817
5818 e_err(drv,
5819 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5820}
5821
5822void ixgbe_disable_tx(struct ixgbe_adapter *adapter)
5823{
5824 unsigned long wait_delay, delay_interval;
5825 struct ixgbe_hw *hw = &adapter->hw;
5826 int i, wait_loop;
5827 u32 txdctl;
5828
5829 if (ixgbe_removed(hw->hw_addr))
5830 return;
5831
5832 /* disable all enabled Tx queues */
5833 for (i = 0; i < adapter->num_tx_queues; i++) {
5834 struct ixgbe_ring *ring = adapter->tx_ring[i];
5835 u8 reg_idx = ring->reg_idx;
5836
5837 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5838 }
5839
5840 /* disable all enabled XDP Tx queues */
5841 for (i = 0; i < adapter->num_xdp_queues; i++) {
5842 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5843 u8 reg_idx = ring->reg_idx;
5844
5845 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5846 }
5847
5848 /* If the link is not up there shouldn't be much in the way of
5849 * pending transactions. Those that are left will be flushed out
5850 * when the reset logic goes through the flush sequence to clean out
5851 * the pending Tx transactions.
5852 */
5853 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5854 goto dma_engine_disable;
5855
5856 /* Determine our minimum delay interval. We will increase this value
5857 * with each subsequent test. This way if the device returns quickly
5858 * we should spend as little time as possible waiting, however as
5859 * the time increases we will wait for larger periods of time.
5860 *
5861 * The trick here is that we increase the interval using the
5862 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5863 * of that wait is that it totals up to 100x whatever interval we
5864 * choose. Since our minimum wait is 100us we can just divide the
5865 * total timeout by 100 to get our minimum delay interval.
5866 */
5867 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5868
5869 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5870 wait_delay = delay_interval;
5871
5872 while (wait_loop--) {
5873 usleep_range(wait_delay, wait_delay + 10);
5874 wait_delay += delay_interval * 2;
5875 txdctl = 0;
5876
5877 /* OR together the reading of all the active TXDCTL registers,
5878 * and then test the result. We need the disable to complete
5879 * before we start freeing the memory and invalidating the
5880 * DMA mappings.
5881 */
5882 for (i = 0; i < adapter->num_tx_queues; i++) {
5883 struct ixgbe_ring *ring = adapter->tx_ring[i];
5884 u8 reg_idx = ring->reg_idx;
5885
5886 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5887 }
5888 for (i = 0; i < adapter->num_xdp_queues; i++) {
5889 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5890 u8 reg_idx = ring->reg_idx;
5891
5892 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5893 }
5894
5895 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
5896 goto dma_engine_disable;
5897 }
5898
5899 e_err(drv,
5900 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5901
5902dma_engine_disable:
5903 /* Disable the Tx DMA engine on 82599 and later MAC */
5904 switch (hw->mac.type) {
5905 case ixgbe_mac_82599EB:
5906 case ixgbe_mac_X540:
5907 case ixgbe_mac_X550:
5908 case ixgbe_mac_X550EM_x:
5909 case ixgbe_mac_x550em_a:
5910 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5911 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5912 ~IXGBE_DMATXCTL_TE));
5463fce6 5913 fallthrough;
1918e937
AD		 5914 default:
5915 break;
5916 }
5917}
5918
9a799d71
AK		 5919void ixgbe_reset(struct ixgbe_adapter *adapter)
5920{
c44ade9e 5921 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5922 struct net_device *netdev = adapter->netdev;
8ca783ab
DS		 5923 int err;
5924
b0483c8f
MR		 5925 if (ixgbe_removed(hw->hw_addr))
5926 return;
7086400d
AD		 5927 /* lock SFP init bit to prevent race conditions with the watchdog */
5928 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5929 usleep_range(1000, 2000);
5930
5931 /* clear all SFP and link config related flags while holding SFP_INIT */
5932 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5933 IXGBE_FLAG2_SFP_NEEDS_RESET);
5934 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5935
8ca783ab 5936 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5937 switch (err) {
5938 case 0:
5939 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5940 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5941 break;
5942 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5943 e_dev_err("master disable timed out\n");
da4dd0f7 5944 break;
794caeb2
PWJ		 5945 case IXGBE_ERR_EEPROM_VERSION:
5946 /* We are running on a pre-production device, log a warning */
849c4542 5947 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5948 "Please be aware there may be issues associated with "
849c4542
ET		 5949 "your hardware. If you are experiencing problems "
5950 "please contact your Intel or hardware "
5951 "representative who provided you with this "
5952 "hardware.\n");
794caeb2 5953 break;
da4dd0f7 5954 default:
849c4542 5955 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5956 }
9a799d71 5957
7086400d 5958 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
0f079d22
AD		 5959
5960 /* flush entries out of MAC table */
5d7daa35 5961 ixgbe_flush_sw_mac_table(adapter);
0f079d22
AD		 5962 __dev_uc_unsync(netdev, NULL);
5963
5964 /* do not flush user set addresses */
c9f53e63 5965 ixgbe_mac_set_default_filter(adapter);
7fa7c9dc
AD		 5966
5967 /* update SAN MAC vmdq pool selection */
5968 if (hw->mac.san_mac_rar_index)
5969 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5970
8fecf67c 5971 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5972 ixgbe_ptp_reset(adapter);
961fac88
DS		 5973
5974 if (hw->phy.ops.set_phy_power) {
5975 if (!netif_running(adapter->netdev) && !adapter->wol)
5976 hw->phy.ops.set_phy_power(hw, false);
5977 else
5978 hw->phy.ops.set_phy_power(hw, true);
5979 }
9a799d71
AK		 5980}
5981
9a799d71
AK		 5982/**
5983 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5984 * @tx_ring: ring to be cleaned
5985 **/
b6ec895e 5986static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71 5987{
ffed21bc
AD		 5988 u16 i = tx_ring->next_to_clean;
5989 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
9a799d71 5990
1742b3d5 5991 if (tx_ring->xsk_pool) {
8221c5eb
BT		 5992 ixgbe_xsk_clean_tx_ring(tx_ring);
5993 goto out;
5994 }
5995
ffed21bc
AD		 5996 while (i != tx_ring->next_to_use) {
5997 union ixgbe_adv_tx_desc *eop_desc, *tx_desc;
9a799d71 5998
ffed21bc 5999 /* Free all the Tx ring sk_buffs */
33fdc82f 6000 if (ring_is_xdp(tx_ring))
03993094 6001 xdp_return_frame(tx_buffer->xdpf);
33fdc82f
JF		 6002 else
6003 dev_kfree_skb_any(tx_buffer->skb);
9a799d71 6004
ffed21bc
AD		 6005 /* unmap skb header data */
6006 dma_unmap_single(tx_ring->dev,
6007 dma_unmap_addr(tx_buffer, dma),
6008 dma_unmap_len(tx_buffer, len),
6009 DMA_TO_DEVICE);
dad8a3b3 6010
ffed21bc
AD		 6011 /* check for eop_desc to determine the end of the packet */
6012 eop_desc = tx_buffer->next_to_watch;
6013 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6014
6015 /* unmap remaining buffers */
6016 while (tx_desc != eop_desc) {
6017 tx_buffer++;
6018 tx_desc++;
6019 i++;
6020 if (unlikely(i == tx_ring->count)) {
6021 i = 0;
6022 tx_buffer = tx_ring->tx_buffer_info;
6023 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6024 }
9a799d71 6025
ffed21bc
AD		 6026 /* unmap any remaining paged data */
6027 if (dma_unmap_len(tx_buffer, len))
6028 dma_unmap_page(tx_ring->dev,
6029 dma_unmap_addr(tx_buffer, dma),
6030 dma_unmap_len(tx_buffer, len),
6031 DMA_TO_DEVICE);
6032 }
9a799d71 6033
ffed21bc
AD		 6034 /* move us one more past the eop_desc for start of next pkt */
6035 tx_buffer++;
6036 i++;
6037 if (unlikely(i == tx_ring->count)) {
6038 i = 0;
6039 tx_buffer = tx_ring->tx_buffer_info;
6040 }
6041 }
6042
6043 /* reset BQL for queue */
33fdc82f
JF		 6044 if (!ring_is_xdp(tx_ring))
6045 netdev_tx_reset_queue(txring_txq(tx_ring));
ffed21bc 6046
8221c5eb 6047out:
ffed21bc 6048 /* reset next_to_use and next_to_clean */
9a799d71
AK		 6049 tx_ring->next_to_use = 0;
6050 tx_ring->next_to_clean = 0;
9a799d71
AK		 6051}
6052
6053/**
021230d4 6054 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 6055 * @adapter: board private structure
6056 **/
021230d4 6057static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 6058{
6059 int i;
6060
021230d4 6061 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 6062 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 6063}
6064
6065/**
021230d4 6066 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 6067 * @adapter: board private structure
6068 **/
021230d4 6069static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 6070{
6071 int i;
6072
021230d4 6073 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 6074 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
33fdc82f
JF		 6075 for (i = 0; i < adapter->num_xdp_queues; i++)
6076 ixgbe_clean_tx_ring(adapter->xdp_ring[i]);
9a799d71
AK		 6077}
6078
e4911d57
AD		 6079static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
6080{
b67bfe0d 6081 struct hlist_node *node2;
e4911d57
AD		 6082 struct ixgbe_fdir_filter *filter;
6083
6084 spin_lock(&adapter->fdir_perfect_lock);
6085
b67bfe0d 6086 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 6087 &adapter->fdir_filter_list, fdir_node) {
6088 hlist_del(&filter->fdir_node);
6089 kfree(filter);
6090 }
6091 adapter->fdir_filter_count = 0;
6092
6093 spin_unlock(&adapter->fdir_perfect_lock);
6094}
6095
9a799d71
AK		 6096void ixgbe_down(struct ixgbe_adapter *adapter)
6097{
6098 struct net_device *netdev = adapter->netdev;
7f821875 6099 struct ixgbe_hw *hw = &adapter->hw;
bf29ee6c 6100 int i;
9a799d71
AK		 6101
6102 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 6103 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
6104 return; /* do nothing if already down */
9a799d71 6105
3b5f14b5
AD		 6106 /* Shut off incoming Tx traffic */
6107 netif_tx_stop_all_queues(netdev);
6108
6109 /* call carrier off first to avoid false dev_watchdog timeouts */
6110 netif_carrier_off(netdev);
6111 netif_tx_disable(netdev);
6112
1918e937
AD		 6113 /* Disable Rx */
6114 ixgbe_disable_rx(adapter);
2d39d576 6115
8166abb1 6116 /* synchronize_rcu() needed for pending XDP buffers to drain */
11393cc9 6117 if (adapter->xdp_ring[0])
8166abb1 6118 synchronize_rcu();
c0dfb90e
JF		 6119
6120 ixgbe_irq_disable(adapter);
6121
6122 ixgbe_napi_disable_all(adapter);
6123
57ca2a4f
ET		 6124 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
6125 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7086400d
AD		 6126 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6127
6128 del_timer_sync(&adapter->service_timer);
6129
34cecbbf 6130 if (adapter->num_vfs) {
8e34d1aa
AD		 6131 /* Clear EITR Select mapping */
6132 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 6133
6134 /* Mark all the VFs as inactive */
6135 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 6136 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 6137
34cecbbf
AD		 6138 /* ping all the active vfs to let them know we are going down */
6139 ixgbe_ping_all_vfs(adapter);
6140
6141 /* Disable all VFTE/VFRE TX/RX */
6142 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 6143 }
6144
7f821875 6145 /* disable transmits in the hardware now that interrupts are off */
1918e937 6146 ixgbe_disable_tx(adapter);
7f821875 6147
6f4a0e45
PL		 6148 if (!pci_channel_offline(adapter->pdev))
6149 ixgbe_reset(adapter);
c6ecf39a 6150
ec74a471
ET		 6151 /* power down the optics for 82599 SFP+ fiber */
6152 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 6153 hw->mac.ops.disable_tx_laser(hw);
6154
9a799d71
AK		 6155 ixgbe_clean_all_tx_rings(adapter);
6156 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 6157}
6158
b3eb4e18 6159/**
262de08f 6160 * ixgbe_set_eee_capable - helper function to determine EEE support on X550
b3eb4e18
MR		 6161 * @adapter: board private structure
6162 */
6163static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter)
6164{
6165 struct ixgbe_hw *hw = &adapter->hw;
6166
6167 switch (hw->device_id) {
6168 case IXGBE_DEV_ID_X550EM_A_1G_T:
6169 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6170 if (!hw->phy.eee_speeds_supported)
6171 break;
6172 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE;
6173 if (!hw->phy.eee_speeds_advertised)
6174 break;
6175 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
6176 break;
6177 default:
6178 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE;
6179 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
6180 break;
6181 }
6182}
6183
9a799d71
AK		 6184/**
6185 * ixgbe_tx_timeout - Respond to a Tx Hang
6186 * @netdev: network interface device structure
b50f7bca 6187 * @txqueue: queue number that timed out
9a799d71 6188 **/
b50f7bca 6189static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
9a799d71
AK		 6190{
6191 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6192
6193 /* Do the reset outside of interrupt context */
c83c6cbd 6194 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 6195}
6196
8829009d
UK		 6197#ifdef CONFIG_IXGBE_DCB
6198static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
6199{
6200 struct ixgbe_hw *hw = &adapter->hw;
6201 struct tc_configuration *tc;
6202 int j;
6203
6204 switch (hw->mac.type) {
6205 case ixgbe_mac_82598EB:
6206 case ixgbe_mac_82599EB:
6207 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
6208 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
6209 break;
6210 case ixgbe_mac_X540:
6211 case ixgbe_mac_X550:
6212 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
6213 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
6214 break;
6215 case ixgbe_mac_X550EM_x:
6216 case ixgbe_mac_x550em_a:
6217 default:
6218 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
6219 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
6220 break;
6221 }
6222
6223 /* Configure DCB traffic classes */
6224 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
6225 tc = &adapter->dcb_cfg.tc_config[j];
6226 tc->path[DCB_TX_CONFIG].bwg_id = 0;
6227 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
6228 tc->path[DCB_RX_CONFIG].bwg_id = 0;
6229 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
6230 tc->dcb_pfc = pfc_disabled;
6231 }
6232
6233 /* Initialize default user to priority mapping, UPx->TC0 */
6234 tc = &adapter->dcb_cfg.tc_config[0];
6235 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
6236 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
6237
6238 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
6239 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
6240 adapter->dcb_cfg.pfc_mode_enable = false;
6241 adapter->dcb_set_bitmap = 0x00;
6242 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
6243 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
6244 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
6245 sizeof(adapter->temp_dcb_cfg));
6246}
6247#endif
6248
9a799d71
AK		 6249/**
6250 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
6251 * @adapter: board private structure to initialize
5ba643c6 6252 * @ii: pointer to ixgbe_info for device
9a799d71
AK		 6253 *
6254 * ixgbe_sw_init initializes the Adapter private data structure.
6255 * Fields are initialized based on PCI device information and
6256 * OS network device settings (MTU size).
6257 **/
55570b6f
ET		 6258static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
6259 const struct ixgbe_info *ii)
9a799d71
AK		 6260{
6261 struct ixgbe_hw *hw = &adapter->hw;
6262 struct pci_dev *pdev = adapter->pdev;
d3cb9869 6263 unsigned int rss, fdir;
cb6d0f5e 6264 u32 fwsm;
1cdaaf54 6265 int i;
021230d4 6266
c44ade9e
JB		 6267 /* PCI config space info */
6268
6269 hw->vendor_id = pdev->vendor;
6270 hw->device_id = pdev->device;
6271 hw->revision_id = pdev->revision;
6272 hw->subsystem_vendor_id = pdev->subsystem_vendor;
6273 hw->subsystem_device_id = pdev->subsystem_device;
6274
55570b6f
ET		 6275 /* get_invariants needs the device IDs */
6276 ii->get_invariants(hw);
6277
8fc3bb6d 6278 /* Set common capability flags and settings */
0f9b232b 6279 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 6280 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 6281 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 6282 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
6283 adapter->atr_sample_rate = 20;
d3cb9869
AD		 6284 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
6285 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d 6286 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
a8e87d9f 6287 adapter->ring_feature[RING_F_VMDQ].limit = 1;
8fc3bb6d
ET		 6288#ifdef CONFIG_IXGBE_DCA
6289 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
6290#endif
8829009d
UK		 6291#ifdef CONFIG_IXGBE_DCB
6292 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
6293 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6294#endif
8fc3bb6d
ET		 6295#ifdef IXGBE_FCOE
6296 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
6297 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6298#ifdef CONFIG_IXGBE_DCB
6299 /* Default traffic class to use for FCoE */
6300 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
6301#endif /* CONFIG_IXGBE_DCB */
6302#endif /* IXGBE_FCOE */
6303
b82b17d9 6304 /* initialize static ixgbe jump table entries */
1cdaaf54
AN		 6305 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
6306 GFP_KERNEL);
6307 if (!adapter->jump_tables[0])
6308 return -ENOMEM;
6309 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
6310
6311 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
6312 adapter->jump_tables[i] = NULL;
b82b17d9 6313
6396bb22
KC		 6314 adapter->mac_table = kcalloc(hw->mac.num_rar_entries,
6315 sizeof(struct ixgbe_mac_addr),
374f78f7 6316 GFP_KERNEL);
530fd82a
AD		 6317 if (!adapter->mac_table)
6318 return -ENOMEM;
5d7daa35 6319
3dfbfc7e
TN		 6320 if (ixgbe_init_rss_key(adapter))
6321 return -ENOMEM;
6322
d49e286d
JS		 6323 adapter->af_xdp_zc_qps = bitmap_zalloc(MAX_XDP_QUEUES, GFP_KERNEL);
6324 if (!adapter->af_xdp_zc_qps)
6325 return -ENOMEM;
6326
8fc3bb6d 6327 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 6328 switch (hw->mac.type) {
6329 case ixgbe_mac_82598EB:
8fc3bb6d 6330 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 6331
bf069c97
DS		 6332 if (hw->device_id == IXGBE_DEV_ID_82598AT)
6333 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 6334
49c7ffbe 6335 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 6336 adapter->ring_feature[RING_F_FDIR].limit = 0;
6337 adapter->atr_sample_rate = 0;
6338 adapter->fdir_pballoc = 0;
6339#ifdef IXGBE_FCOE
6340 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6341 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6342#ifdef CONFIG_IXGBE_DCB
6343 adapter->fcoe.up = 0;
6344#endif /* IXGBE_DCB */
6345#endif /* IXGBE_FCOE */
6346 break;
6347 case ixgbe_mac_82599EB:
6348 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
6349 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 6350 break;
b93a2226 6351 case ixgbe_mac_X540:
9a900eca 6352 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 6353 if (fwsm & IXGBE_FWSM_TS_ENABLED)
6354 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 6355 break;
49425dfc 6356 case ixgbe_mac_x550em_a:
b3eb4e18
MR		 6357 switch (hw->device_id) {
6358 case IXGBE_DEV_ID_X550EM_A_1G_T:
6359 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6360 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6361 break;
6362 default:
6363 break;
6364 }
5463fce6 6365 fallthrough;
a21d0822 6366 case ixgbe_mac_X550EM_x:
8829009d
UK		 6367#ifdef CONFIG_IXGBE_DCB
6368 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
6369#endif
6370#ifdef IXGBE_FCOE
6371 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6372#ifdef CONFIG_IXGBE_DCB
6373 adapter->fcoe.up = 0;
6374#endif /* IXGBE_DCB */
6375#endif /* IXGBE_FCOE */
5463fce6 6376 fallthrough;
9a75a1ac 6377 case ixgbe_mac_X550:
b3eb4e18
MR		 6378 if (hw->mac.type == ixgbe_mac_X550)
6379 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a75a1ac
DS		 6380#ifdef CONFIG_IXGBE_DCA
6381 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c 6382#endif
9a75a1ac 6383 break;
bd508178
AD		 6384 default:
6385 break;
f8212f97 6386 }
2f90b865 6387
7c8ae65a
AD		 6388#ifdef IXGBE_FCOE
6389 /* FCoE support exists, always init the FCoE lock */
6390 spin_lock_init(&adapter->fcoe.lock);
6391
6392#endif
1fc5f038
AD		 6393 /* n-tuple support exists, always init our spinlock */
6394 spin_lock_init(&adapter->fdir_perfect_lock);
6395
7a6b6f51 6396#ifdef CONFIG_IXGBE_DCB
8829009d 6397 ixgbe_init_dcb(adapter);
2f90b865 6398#endif
de7a7e34 6399 ixgbe_init_ipsec_offload(adapter);
9a799d71
AK		 6400
6401 /* default flow control settings */
cd7664f6 6402 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 6403 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 6404 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 6405 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
6406 hw->fc.send_xon = true;
73d80953 6407 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 6408
99d74487 6409#ifdef CONFIG_PCI_IOV
170e8543
JK		 6410 if (max_vfs > 0)
6411 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
6412
99d74487 6413 /* assign number of SR-IOV VFs */
170e8543 6414 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 6415 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5c11f00d 6416 max_vfs = 0;
170e8543 6417 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
170e8543
JK		 6418 }
6419 }
6420#endif /* CONFIG_PCI_IOV */
99d74487 6421
30efa5a3 6422 /* enable itr by default in dynamic mode */
f7554a2b 6423 adapter->rx_itr_setting = 1;
f7554a2b 6424 adapter->tx_itr_setting = 1;
30efa5a3 6425
30efa5a3
JB		 6426 /* set default ring sizes */
6427 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
6428 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
6429
bd198058 6430 /* set default work limits */
59224555 6431 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 6432
9a799d71 6433 /* initialize eeprom parameters */
c44ade9e 6434 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 6435 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 6436 return -EIO;
6437 }
6438
2a47fa45 6439 /* PF holds first pool slot */
4e039c16 6440 set_bit(0, adapter->fwd_bitmask);
9a799d71
AK		 6441 set_bit(__IXGBE_DOWN, &adapter->state);
6442
6443 return 0;
6444}
6445
6446/**
6447 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 6448 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 6449 *
6450 * Return 0 on success, negative on failure
6451 **/
b6ec895e 6452int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 6453{
b6ec895e 6454 struct device *dev = tx_ring->dev;
de88eeeb 6455 int orig_node = dev_to_node(dev);
98fa15f3 6456 int ring_node = NUMA_NO_NODE;
9a799d71
AK		 6457 int size;
6458
3a581073 6459 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 6460
6461 if (tx_ring->q_vector)
ca8dfe25 6462 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 6463
ffed21bc 6464 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node);
1a6c14a2 6465 if (!tx_ring->tx_buffer_info)
ffed21bc 6466 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 6467 if (!tx_ring->tx_buffer_info)
6468 goto err;
9a799d71
AK		 6469
6470 /* round up to nearest 4K */
12207e49 6471 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 6472 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 6473
ca8dfe25 6474 set_dev_node(dev, ring_node);
de88eeeb
AD		 6475 tx_ring->desc = dma_alloc_coherent(dev,
6476 tx_ring->size,
6477 &tx_ring->dma,
6478 GFP_KERNEL);
6479 set_dev_node(dev, orig_node);
6480 if (!tx_ring->desc)
6481 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
6482 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 6483 if (!tx_ring->desc)
6484 goto err;
9a799d71 6485
3a581073
JB		 6486 tx_ring->next_to_use = 0;
6487 tx_ring->next_to_clean = 0;
9a799d71 6488 return 0;
e01c31a5
JB		 6489
6490err:
6491 vfree(tx_ring->tx_buffer_info);
6492 tx_ring->tx_buffer_info = NULL;
b6ec895e 6493 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 6494 return -ENOMEM;
9a799d71
AK		 6495}
6496
69888674
AD		 6497/**
6498 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
6499 * @adapter: board private structure
6500 *
6501 * If this function returns with an error, then it's possible one or
6502 * more of the rings is populated (while the rest are not). It is the
6503 * callers duty to clean those orphaned rings.
6504 *
6505 * Return 0 on success, negative on failure
6506 **/
6507static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
6508{
33fdc82f 6509 int i, j = 0, err = 0;
69888674
AD		 6510
6511 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 6512 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 6513 if (!err)
6514 continue;
de3d5b94 6515
396e799c 6516 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 6517 goto err_setup_tx;
69888674 6518 }
33fdc82f
JF		 6519 for (j = 0; j < adapter->num_xdp_queues; j++) {
6520 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]);
6521 if (!err)
6522 continue;
6523
6524 e_err(probe, "Allocation for Tx Queue %u failed\n", j);
6525 goto err_setup_tx;
6526 }
69888674 6527
de3d5b94
AD		 6528 return 0;
6529err_setup_tx:
6530 /* rewind the index freeing the rings as we go */
33fdc82f
JF		 6531 while (j--)
6532 ixgbe_free_tx_resources(adapter->xdp_ring[j]);
de3d5b94
AD		 6533 while (i--)
6534 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 6535 return err;
6536}
6537
31166efb
AD		 6538static int ixgbe_rx_napi_id(struct ixgbe_ring *rx_ring)
6539{
6540 struct ixgbe_q_vector *q_vector = rx_ring->q_vector;
6541
6542 return q_vector ? q_vector->napi.napi_id : 0;
6543}
6544
9a799d71
AK		 6545/**
6546 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5ba643c6 6547 * @adapter: pointer to ixgbe_adapter
3a581073 6548 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 6549 *
6550 * Returns 0 on success, negative on failure
6551 **/
92470808
JF		 6552int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
6553 struct ixgbe_ring *rx_ring)
9a799d71 6554{
b6ec895e 6555 struct device *dev = rx_ring->dev;
de88eeeb 6556 int orig_node = dev_to_node(dev);
98fa15f3 6557 int ring_node = NUMA_NO_NODE;
d0bcacd0 6558 int size;
9a799d71 6559
3a581073 6560 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 6561
6562 if (rx_ring->q_vector)
ca8dfe25 6563 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 6564
ffed21bc 6565 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node);
1a6c14a2 6566 if (!rx_ring->rx_buffer_info)
ffed21bc 6567 rx_ring->rx_buffer_info = vmalloc(size);
b6ec895e
AD		 6568 if (!rx_ring->rx_buffer_info)
6569 goto err;
9a799d71 6570
9a799d71 6571 /* Round up to nearest 4K */
3a581073
JB		 6572 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
6573 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 6574
ca8dfe25 6575 set_dev_node(dev, ring_node);
de88eeeb
AD		 6576 rx_ring->desc = dma_alloc_coherent(dev,
6577 rx_ring->size,
6578 &rx_ring->dma,
6579 GFP_KERNEL);
6580 set_dev_node(dev, orig_node);
6581 if (!rx_ring->desc)
6582 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
6583 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 6584 if (!rx_ring->desc)
6585 goto err;
9a799d71 6586
3a581073
JB		 6587 rx_ring->next_to_clean = 0;
6588 rx_ring->next_to_use = 0;
9a799d71 6589
99ffc5ad
JDB		 6590 /* XDP RX-queue info */
6591 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev,
31166efb 6592 rx_ring->queue_index, ixgbe_rx_napi_id(rx_ring)) < 0)
99ffc5ad
JDB		 6593 goto err;
6594
92470808
JF		 6595 rx_ring->xdp_prog = adapter->xdp_prog;
6596
9a799d71 6597 return 0;
b6ec895e
AD		 6598err:
6599 vfree(rx_ring->rx_buffer_info);
6600 rx_ring->rx_buffer_info = NULL;
6601 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 6602 return -ENOMEM;
9a799d71
AK		 6603}
6604
69888674
AD		 6605/**
6606 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
6607 * @adapter: board private structure
6608 *
6609 * If this function returns with an error, then it's possible one or
6610 * more of the rings is populated (while the rest are not). It is the
6611 * callers duty to clean those orphaned rings.
6612 *
6613 * Return 0 on success, negative on failure
6614 **/
69888674
AD		 6615static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
6616{
6617 int i, err = 0;
6618
6619 for (i = 0; i < adapter->num_rx_queues; i++) {
92470808 6620 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 6621 if (!err)
6622 continue;
de3d5b94 6623
396e799c 6624 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 6625 goto err_setup_rx;
69888674
AD		 6626 }
6627
7c8ae65a
AD		 6628#ifdef IXGBE_FCOE
6629 err = ixgbe_setup_fcoe_ddp_resources(adapter);
6630 if (!err)
6631#endif
6632 return 0;
de3d5b94
AD		 6633err_setup_rx:
6634 /* rewind the index freeing the rings as we go */
6635 while (i--)
6636 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 6637 return err;
6638}
6639
9a799d71
AK		 6640/**
6641 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 6642 * @tx_ring: Tx descriptor ring for a specific queue
6643 *
6644 * Free all transmit software resources
6645 **/
b6ec895e 6646void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 6647{
b6ec895e 6648 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 6649
6650 vfree(tx_ring->tx_buffer_info);
6651 tx_ring->tx_buffer_info = NULL;
6652
b6ec895e
AD		 6653 /* if not set, then don't free */
6654 if (!tx_ring->desc)
6655 return;
6656
6657 dma_free_coherent(tx_ring->dev, tx_ring->size,
6658 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 6659
6660 tx_ring->desc = NULL;
6661}
6662
6663/**
6664 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
6665 * @adapter: board private structure
6666 *
6667 * Free all transmit software resources
6668 **/
6669static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6670{
6671 int i;
6672
6673 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 6674 if (adapter->tx_ring[i]->desc)
b6ec895e 6675 ixgbe_free_tx_resources(adapter->tx_ring[i]);
33fdc82f
JF		 6676 for (i = 0; i < adapter->num_xdp_queues; i++)
6677 if (adapter->xdp_ring[i]->desc)
6678 ixgbe_free_tx_resources(adapter->xdp_ring[i]);
9a799d71
AK		 6679}
6680
6681/**
b4617240 6682 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 6683 * @rx_ring: ring to clean the resources from
6684 *
6685 * Free all receive software resources
6686 **/
b6ec895e 6687void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 6688{
b6ec895e 6689 ixgbe_clean_rx_ring(rx_ring);
9a799d71 6690
92470808 6691 rx_ring->xdp_prog = NULL;
99ffc5ad 6692 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
9a799d71
AK		 6693 vfree(rx_ring->rx_buffer_info);
6694 rx_ring->rx_buffer_info = NULL;
6695
b6ec895e
AD		 6696 /* if not set, then don't free */
6697 if (!rx_ring->desc)
6698 return;
6699
6700 dma_free_coherent(rx_ring->dev, rx_ring->size,
6701 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 6702
6703 rx_ring->desc = NULL;
6704}
6705
6706/**
6707 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6708 * @adapter: board private structure
6709 *
6710 * Free all receive software resources
6711 **/
6712static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6713{
6714 int i;
6715
7c8ae65a
AD		 6716#ifdef IXGBE_FCOE
6717 ixgbe_free_fcoe_ddp_resources(adapter);
6718
6719#endif
9a799d71 6720 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 6721 if (adapter->rx_ring[i]->desc)
b6ec895e 6722 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 6723}
6724
9a799d71
AK		 6725/**
6726 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6727 * @netdev: network interface device structure
6728 * @new_mtu: new value for maximum frame size
6729 *
6730 * Returns 0 on success, negative on failure
6731 **/
6732static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6733{
6734 struct ixgbe_adapter *adapter = netdev_priv(netdev);
655309e9 6735
38b7e7f8 6736 if (adapter->xdp_prog) {
fabf1bce
TN		 6737 int new_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN +
6738 VLAN_HLEN;
6739 int i;
6740
6741 for (i = 0; i < adapter->num_rx_queues; i++) {
6742 struct ixgbe_ring *ring = adapter->rx_ring[i];
6743
6744 if (new_frame_size > ixgbe_rx_bufsz(ring)) {
6745 e_warn(probe, "Requested MTU size is not supported with XDP\n");
6746 return -EINVAL;
6747 }
6748 }
38b7e7f8
TN		 6749 }
6750
655309e9 6751 /*
872844dd
AD		 6752 * For 82599EB we cannot allow legacy VFs to enable their receive
6753 * paths when MTU greater than 1500 is configured. So display a
6754 * warning that legacy VFs will be disabled.
655309e9
AD		 6755 */
6756 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6757 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
91c527a5 6758 (new_mtu > ETH_DATA_LEN))
872844dd 6759 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 6760
12299132
FF		 6761 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6762 netdev->mtu, new_mtu);
655309e9 6763
021230d4 6764 /* must set new MTU before calling down or up */
9a799d71
AK		 6765 netdev->mtu = new_mtu;
6766
d4f80882
AV		 6767 if (netif_running(netdev))
6768 ixgbe_reinit_locked(adapter);
9a799d71
AK		 6769
6770 return 0;
6771}
6772
6773/**
6774 * ixgbe_open - Called when a network interface is made active
6775 * @netdev: network interface device structure
6776 *
6777 * Returns 0 on success, negative value on failure
6778 *
6779 * The open entry point is called when a network interface is made
6780 * active by the system (IFF_UP). At this point all resources needed
6781 * for transmit and receive operations are allocated, the interrupt
6782 * handler is registered with the OS, the watchdog timer is started,
6783 * and the stack is notified that the interface is ready.
6784 **/
6c211fe1 6785int ixgbe_open(struct net_device *netdev)
9a799d71
AK		 6786{
6787 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 6788 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 6789 int err, queues;
4bebfaa5
AK		 6790
6791 /* disallow open during test */
6792 if (test_bit(__IXGBE_TESTING, &adapter->state))
6793 return -EBUSY;
9a799d71 6794
54386467
JB		 6795 netif_carrier_off(netdev);
6796
9a799d71
AK		 6797 /* allocate transmit descriptors */
6798 err = ixgbe_setup_all_tx_resources(adapter);
6799 if (err)
6800 goto err_setup_tx;
6801
9a799d71
AK		 6802 /* allocate receive descriptors */
6803 err = ixgbe_setup_all_rx_resources(adapter);
6804 if (err)
6805 goto err_setup_rx;
6806
6807 ixgbe_configure(adapter);
6808
021230d4 6809 err = ixgbe_request_irq(adapter);
9a799d71
AK		 6810 if (err)
6811 goto err_req_irq;
6812
ac802f5d 6813 /* Notify the stack of the actual queue counts. */
49cfbeb7 6814 queues = adapter->num_tx_queues;
2a47fa45 6815 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 6816 if (err)
6817 goto err_set_queues;
6818
49cfbeb7 6819 queues = adapter->num_rx_queues;
2a47fa45 6820 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 6821 if (err)
6822 goto err_set_queues;
6823
1a71ab24 6824 ixgbe_ptp_init(adapter);
1a71ab24 6825
c7ccde0f 6826 ixgbe_up_complete(adapter);
9a799d71 6827
dc221851 6828 udp_tunnel_nic_reset_ntf(netdev);
67359c3c 6829
9a799d71
AK		 6830 return 0;
6831
ac802f5d
AD		 6832err_set_queues:
6833 ixgbe_free_irq(adapter);
9a799d71 6834err_req_irq:
a20a1199 6835 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 6836 if (hw->phy.ops.set_phy_power && !adapter->wol)
6837 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 6838err_setup_rx:
a20a1199 6839 ixgbe_free_all_tx_resources(adapter);
de3d5b94 6840err_setup_tx:
9a799d71
AK		 6841 ixgbe_reset(adapter);
6842
6843 return err;
6844}
6845
a0cccce2
JK		 6846static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6847{
6848 ixgbe_ptp_suspend(adapter);
6849
6ac74394
DS		 6850 if (adapter->hw.phy.ops.enter_lplu) {
6851 adapter->hw.phy.reset_disable = true;
6852 ixgbe_down(adapter);
6853 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6854 adapter->hw.phy.reset_disable = false;
6855 } else {
6856 ixgbe_down(adapter);
6857 }
6858
a0cccce2
JK		 6859 ixgbe_free_irq(adapter);
6860
6861 ixgbe_free_all_tx_resources(adapter);
6862 ixgbe_free_all_rx_resources(adapter);
6863}
6864
9a799d71
AK		 6865/**
6866 * ixgbe_close - Disables a network interface
6867 * @netdev: network interface device structure
6868 *
6869 * Returns 0, this is not allowed to fail
6870 *
6871 * The close entry point is called when an interface is de-activated
6872 * by the OS. The hardware is still under the drivers control, but
6873 * needs to be disabled. A global MAC reset is issued to stop the
6874 * hardware, and all transmit and receive resources are freed.
6875 **/
6c211fe1 6876int ixgbe_close(struct net_device *netdev)
9a799d71
AK		 6877{
6878 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 6879
1a71ab24 6880 ixgbe_ptp_stop(adapter);
1a71ab24 6881
f7f37e7f
ET		 6882 if (netif_device_present(netdev))
6883 ixgbe_close_suspend(adapter);
9a799d71 6884
e4911d57
AD		 6885 ixgbe_fdir_filter_exit(adapter);
6886
5eba3699 6887 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6888
6889 return 0;
6890}
6891
6f82b255 6892static int __maybe_unused ixgbe_resume(struct device *dev_d)
b3c8b4ba 6893{
6f82b255 6894 struct pci_dev *pdev = to_pci_dev(dev_d);
c60fbb00
AD		 6895 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6896 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 6897 u32 err;
6898
0391bbe3 6899 adapter->hw.hw_addr = adapter->io_addr;
9ce77666 6900
debb9df3
YL		 6901 err = pci_enable_device_mem(pdev);
6902 if (err) {
6903 e_dev_err("Cannot enable PCI device from suspend\n");
6904 return err;
6905 }
4e857c58 6906 smp_mb__before_atomic();
41c62843 6907 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 6908 pci_set_master(pdev);
6909
6f82b255 6910 device_wakeup_disable(dev_d);
b3c8b4ba 6911
b3c8b4ba
AD		 6912 ixgbe_reset(adapter);
6913
495dce12
WJP		 6914 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6915
ac802f5d
AD		 6916 rtnl_lock();
6917 err = ixgbe_init_interrupt_scheme(adapter);
6918 if (!err && netif_running(netdev))
c60fbb00 6919 err = ixgbe_open(netdev);
ac802f5d 6920
ac802f5d 6921
f7f37e7f
ET		 6922 if (!err)
6923 netif_device_attach(netdev);
6924 rtnl_unlock();
b3c8b4ba 6925
f7f37e7f 6926 return err;
b3c8b4ba 6927}
9d8d05ae
RW		 6928
6929static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 6930{
c60fbb00
AD		 6931 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6932 struct net_device *netdev = adapter->netdev;
e8e26350 6933 struct ixgbe_hw *hw = &adapter->hw;
d9d11eb3 6934 u32 ctrl;
e8e26350 6935 u32 wufc = adapter->wol;
b3c8b4ba 6936
f7f37e7f 6937 rtnl_lock();
b3c8b4ba
AD		 6938 netif_device_detach(netdev);
6939
f0b99e3a 6940 if (netif_running(netdev))
a0cccce2 6941 ixgbe_close_suspend(adapter);
b3c8b4ba 6942
5f5ae6fc 6943 ixgbe_clear_interrupt_scheme(adapter);
f7f37e7f 6944 rtnl_unlock();
5f5ae6fc 6945
f4f1040a
JK		 6946 if (hw->mac.ops.stop_link_on_d3)
6947 hw->mac.ops.stop_link_on_d3(hw);
6948
e8e26350 6949 if (wufc) {
d9d11eb3
ET		 6950 u32 fctrl;
6951
e8e26350 6952 ixgbe_set_rx_mode(netdev);
b3c8b4ba 6953
ec74a471
ET		 6954 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6955 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 6956 hw->mac.ops.enable_tx_laser(hw);
6957
d9d11eb3
ET		 6958 /* enable the reception of multicast packets */
6959 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6960 fctrl |= IXGBE_FCTRL_MPE;
6961 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
e8e26350
PW		 6962
6963 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6964 ctrl |= IXGBE_CTRL_GIO_DIS;
6965 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6966
6967 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6968 } else {
6969 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6970 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6971 }
6972
bd508178
AD		 6973 switch (hw->mac.type) {
6974 case ixgbe_mac_82598EB:
dd4d8ca6 6975 pci_wake_from_d3(pdev, false);
bd508178
AD		 6976 break;
6977 case ixgbe_mac_82599EB:
b93a2226 6978 case ixgbe_mac_X540:
9a75a1ac
DS		 6979 case ixgbe_mac_X550:
6980 case ixgbe_mac_X550EM_x:
49425dfc 6981 case ixgbe_mac_x550em_a:
bd508178
AD		 6982 pci_wake_from_d3(pdev, !!wufc);
6983 break;
6984 default:
6985 break;
6986 }
b3c8b4ba 6987
9d8d05ae 6988 *enable_wake = !!wufc;
961fac88
DS		 6989 if (hw->phy.ops.set_phy_power && !*enable_wake)
6990 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6991
b3c8b4ba
AD		 6992 ixgbe_release_hw_control(adapter);
6993
41c62843
MR		 6994 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6995 pci_disable_device(pdev);
b3c8b4ba 6996
9d8d05ae
RW		 6997 return 0;
6998}
6999
6f82b255 7000static int __maybe_unused ixgbe_suspend(struct device *dev_d)
9d8d05ae 7001{
6f82b255 7002 struct pci_dev *pdev = to_pci_dev(dev_d);
9d8d05ae
RW		 7003 int retval;
7004 bool wake;
7005
7006 retval = __ixgbe_shutdown(pdev, &wake);
9d8d05ae 7007
6f82b255 7008 device_set_wakeup_enable(dev_d, wake);
b3c8b4ba 7009
6f82b255 7010 return retval;
b3c8b4ba
AD		 7011}
7012
7013static void ixgbe_shutdown(struct pci_dev *pdev)
7014{
9d8d05ae
RW		 7015 bool wake;
7016
7017 __ixgbe_shutdown(pdev, &wake);
7018
7019 if (system_state == SYSTEM_POWER_OFF) {
7020 pci_wake_from_d3(pdev, wake);
7021 pci_set_power_state(pdev, PCI_D3hot);
7022 }
b3c8b4ba
AD		 7023}
7024
9a799d71
AK		 7025/**
7026 * ixgbe_update_stats - Update the board statistics counters.
7027 * @adapter: board private structure
7028 **/
7029void ixgbe_update_stats(struct ixgbe_adapter *adapter)
7030{
2d86f139 7031 struct net_device *netdev = adapter->netdev;
9a799d71 7032 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 7033 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 7034 u64 total_mpc = 0;
7035 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 7036 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
7037 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
86e23494 7038 u64 alloc_rx_page = 0;
8a0da21b 7039 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 7040
d08935c2
DS		 7041 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7042 test_bit(__IXGBE_RESETTING, &adapter->state))
7043 return;
7044
94b982b2 7045 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 7046 u64 rsc_count = 0;
94b982b2 7047 u64 rsc_flush = 0;
94b982b2 7048 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 7049 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
7050 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 7051 }
7052 adapter->rsc_total_count = rsc_count;
7053 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 7054 }
7055
5b7da515 7056 for (i = 0; i < adapter->num_rx_queues; i++) {
f140ad9f
CL		 7057 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]);
7058
7059 if (!rx_ring)
7060 continue;
5b7da515 7061 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
86e23494 7062 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page;
5b7da515
AD		 7063 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
7064 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 7065 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 7066 bytes += rx_ring->stats.bytes;
7067 packets += rx_ring->stats.packets;
7068 }
7069 adapter->non_eop_descs = non_eop_descs;
86e23494 7070 adapter->alloc_rx_page = alloc_rx_page;
5b7da515
AD		 7071 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
7072 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 7073 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 7074 netdev->stats.rx_bytes = bytes;
7075 netdev->stats.rx_packets = packets;
7076
7077 bytes = 0;
7078 packets = 0;
7ca3bc58 7079 /* gather some stats to the adapter struct that are per queue */
5b7da515 7080 for (i = 0; i < adapter->num_tx_queues; i++) {
f140ad9f
CL		 7081 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]);
7082
7083 if (!tx_ring)
7084 continue;
5b7da515
AD		 7085 restart_queue += tx_ring->tx_stats.restart_queue;
7086 tx_busy += tx_ring->tx_stats.tx_busy;
7087 bytes += tx_ring->stats.bytes;
7088 packets += tx_ring->stats.packets;
7089 }
33fdc82f 7090 for (i = 0; i < adapter->num_xdp_queues; i++) {
f140ad9f 7091 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]);
33fdc82f 7092
f140ad9f
CL		 7093 if (!xdp_ring)
7094 continue;
33fdc82f
JF		 7095 restart_queue += xdp_ring->tx_stats.restart_queue;
7096 tx_busy += xdp_ring->tx_stats.tx_busy;
7097 bytes += xdp_ring->stats.bytes;
7098 packets += xdp_ring->stats.packets;
7099 }
eb985f09 7100 adapter->restart_queue = restart_queue;
5b7da515
AD		 7101 adapter->tx_busy = tx_busy;
7102 netdev->stats.tx_bytes = bytes;
7103 netdev->stats.tx_packets = packets;
7ca3bc58 7104
7ca647bd 7105 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 7106
7107 /* 8 register reads */
6f11eef7
AV		 7108 for (i = 0; i < 8; i++) {
7109 /* for packet buffers not used, the register should read 0 */
7110 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
7111 missed_rx += mpc;
7ca647bd
JP		 7112 hwstats->mpc[i] += mpc;
7113 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 7114 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
7115 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 7116 switch (hw->mac.type) {
7117 case ixgbe_mac_82598EB:
1a70db4b
ET		 7118 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
7119 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
7120 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 7121 hwstats->pxonrxc[i] +=
7122 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 7123 break;
7124 case ixgbe_mac_82599EB:
b93a2226 7125 case ixgbe_mac_X540:
9a75a1ac
DS		 7126 case ixgbe_mac_X550:
7127 case ixgbe_mac_X550EM_x:
49425dfc 7128 case ixgbe_mac_x550em_a:
bd508178
AD		 7129 hwstats->pxonrxc[i] +=
7130 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 7131 break;
7132 default:
7133 break;
e8e26350 7134 }
6f11eef7 7135 }
1a70db4b
ET		 7136
7137 /*16 register reads */
7138 for (i = 0; i < 16; i++) {
7139 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
7140 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
7141 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 7142 (hw->mac.type == ixgbe_mac_X540) ||
7143 (hw->mac.type == ixgbe_mac_X550) ||
49425dfc
MR		 7144 (hw->mac.type == ixgbe_mac_X550EM_x) ||
7145 (hw->mac.type == ixgbe_mac_x550em_a)) {
1a70db4b
ET		 7146 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
7147 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
7148 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
7149 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
7150 }
7151 }
7152
7ca647bd 7153 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 7154 /* work around hardware counting issue */
7ca647bd 7155 hwstats->gprc -= missed_rx;
6f11eef7 7156
c84d324c
JF		 7157 ixgbe_update_xoff_received(adapter);
7158
6f11eef7 7159 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 7160 switch (hw->mac.type) {
7161 case ixgbe_mac_82598EB:
7162 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 7163 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
7164 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
7165 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
7166 break;
b93a2226 7167 case ixgbe_mac_X540:
9a75a1ac
DS		 7168 case ixgbe_mac_X550:
7169 case ixgbe_mac_X550EM_x:
49425dfc 7170 case ixgbe_mac_x550em_a:
9a75a1ac 7171 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 7172 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
7173 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
7174 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
7175 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5463fce6 7176 fallthrough;
58f6bcf9 7177 case ixgbe_mac_82599EB:
a4d4f629
AD		 7178 for (i = 0; i < 16; i++)
7179 adapter->hw_rx_no_dma_resources +=
7180 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 7181 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 7182 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 7183 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 7184 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 7185 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 7186 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 7187 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 7188 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
7189 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 7190#ifdef IXGBE_FCOE
7ca647bd
JP		 7191 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
7192 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
7193 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
7194 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
7195 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
7196 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 7197 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 7198 if (adapter->fcoe.ddp_pool) {
7199 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
7200 struct ixgbe_fcoe_ddp_pool *ddp_pool;
7201 unsigned int cpu;
7202 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 7203 for_each_possible_cpu(cpu) {
5a1ee270
AD		 7204 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
7205 noddp += ddp_pool->noddp;
7206 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 7207 }
5a1ee270
AD		 7208 hwstats->fcoe_noddp = noddp;
7209 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 7210 }
6d45522c 7211#endif /* IXGBE_FCOE */
bd508178
AD		 7212 break;
7213 default:
7214 break;
e8e26350 7215 }
9a799d71 7216 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 7217 hwstats->bprc += bprc;
7218 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 7219 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 7220 hwstats->mprc -= bprc;
7221 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
7222 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
7223 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
7224 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
7225 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
7226 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
7227 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
7228 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 7229 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 7230 hwstats->lxontxc += lxon;
6f11eef7 7231 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 7232 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 7233 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
7234 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 7235 /*
7236 * 82598 errata - tx of flow control packets is included in tx counters
7237 */
7238 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 7239 hwstats->gptc -= xon_off_tot;
7240 hwstats->mptc -= xon_off_tot;
7241 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
7242 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
7243 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
7244 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
7245 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
7246 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
7247 hwstats->ptc64 -= xon_off_tot;
7248 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
7249 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
7250 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
7251 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
7252 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
7253 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 7254
7255 /* Fill out the OS statistics structure */
7ca647bd 7256 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 7257
7258 /* Rx Errors */
7ca647bd 7259 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 7260 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 7261 netdev->stats.rx_length_errors = hwstats->rlec;
7262 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 7263 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 7264}
7265
7266/**
d034acf1 7267 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 7268 * @adapter: pointer to the device adapter structure
9a799d71 7269 **/
d034acf1 7270static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 7271{
cf8280ee 7272 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 7273 int i;
cf8280ee 7274
d034acf1
AD		 7275 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
7276 return;
7277
7278 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 7279
d034acf1 7280 /* if interface is down do nothing */
fe49f04a 7281 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 7282 return;
7283
7284 /* do nothing if we are not using signature filters */
7285 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
7286 return;
7287
7288 adapter->fdir_overflow++;
7289
93c52dd0
AD		 7290 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
7291 for (i = 0; i < adapter->num_tx_queues; i++)
7292 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 7293 &(adapter->tx_ring[i]->state));
33fdc82f
JF		 7294 for (i = 0; i < adapter->num_xdp_queues; i++)
7295 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7296 &adapter->xdp_ring[i]->state);
d034acf1
AD		 7297 /* re-enable flow director interrupts */
7298 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 7299 } else {
7300 e_err(probe, "failed to finish FDIR re-initialization, "
7301 "ignored adding FDIR ATR filters\n");
7302 }
93c52dd0
AD		 7303}
7304
7305/**
7306 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 7307 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 7308 *
7309 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 7310 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 7311 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 7312 * determine if a hang has occurred.
93c52dd0
AD		 7313 */
7314static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 7315{
cf8280ee 7316 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 7317 u64 eics = 0;
7318 int i;
cf8280ee 7319
09f40aed 7320 /* If we're down, removing or resetting, just bail */
93c52dd0 7321 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7322 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 7323 test_bit(__IXGBE_RESETTING, &adapter->state))
7324 return;
22d5a71b 7325
93c52dd0
AD		 7326 /* Force detection of hung controller */
7327 if (netif_carrier_ok(adapter->netdev)) {
7328 for (i = 0; i < adapter->num_tx_queues; i++)
7329 set_check_for_tx_hang(adapter->tx_ring[i]);
33fdc82f
JF		 7330 for (i = 0; i < adapter->num_xdp_queues; i++)
7331 set_check_for_tx_hang(adapter->xdp_ring[i]);
93c52dd0 7332 }
22d5a71b 7333
fe49f04a
AD		 7334 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7335 /*
7336 * for legacy and MSI interrupts don't set any bits
7337 * that are enabled for EIAM, because this operation
7338 * would set *both* EIMS and EICS for any bit in EIAM
7339 */
7340 IXGBE_WRITE_REG(hw, IXGBE_EICS,
7341 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 7342 } else {
7343 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 7344 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 7345 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 7346 if (qv->rx.ring || qv->tx.ring)
b4f47a48 7347 eics |= BIT_ULL(i);
93c52dd0 7348 }
cf8280ee 7349 }
9a799d71 7350
93c52dd0 7351 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 7352 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 7353}
7354
e8e26350 7355/**
93c52dd0 7356 * ixgbe_watchdog_update_link - update the link status
49ce9c2c 7357 * @adapter: pointer to the device adapter structure
e8e26350 7358 **/
93c52dd0 7359static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 7360{
e8e26350 7361 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 7362 u32 link_speed = adapter->link_speed;
7363 bool link_up = adapter->link_up;
041441d0 7364 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 7365
93c52dd0
AD		 7366 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
7367 return;
7368
7369 if (hw->mac.ops.check_link) {
7370 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 7371 } else {
93c52dd0
AD		 7372 /* always assume link is up, if no check link function */
7373 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
7374 link_up = true;
c4cf55e5 7375 }
041441d0
AD		 7376
7377 if (adapter->ixgbe_ieee_pfc)
7378 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
7379
3ebe8fde 7380 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 7381 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 7382 ixgbe_set_rx_drop_en(adapter);
7383 }
93c52dd0
AD		 7384
7385 if (link_up ||
7386 time_after(jiffies, (adapter->link_check_timeout +
7387 IXGBE_TRY_LINK_TIMEOUT))) {
7388 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
7389 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
7390 IXGBE_WRITE_FLUSH(hw);
7391 }
7392
7393 adapter->link_up = link_up;
7394 adapter->link_speed = link_speed;
e8e26350
PW		 7395}
7396
107d3018
AD		 7397static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
7398{
7399#ifdef CONFIG_IXGBE_DCB
7400 struct net_device *netdev = adapter->netdev;
7401 struct dcb_app app = {
7402 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
7403 .protocol = 0,
7404 };
7405 u8 up = 0;
7406
7407 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
7408 up = dcb_ieee_getapp_mask(netdev, &app);
7409
7410 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
7411#endif
7412}
7413
e8e26350 7414/**
93c52dd0
AD		 7415 * ixgbe_watchdog_link_is_up - update netif_carrier status and
7416 * print link up message
49ce9c2c 7417 * @adapter: pointer to the device adapter structure
e8e26350 7418 **/
93c52dd0 7419static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 7420{
93c52dd0 7421 struct net_device *netdev = adapter->netdev;
e8e26350 7422 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0 7423 u32 link_speed = adapter->link_speed;
454adb00 7424 const char *speed_str;
93c52dd0 7425 bool flow_rx, flow_tx;
e8e26350 7426
93c52dd0
AD		 7427 /* only continue if link was previously down */
7428 if (netif_carrier_ok(netdev))
a985b6c3 7429 return;
63d6e1d8 7430
93c52dd0 7431 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 7432
93c52dd0
AD		 7433 switch (hw->mac.type) {
7434 case ixgbe_mac_82598EB: {
7435 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
7436 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
7437 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
7438 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
7439 }
7440 break;
7441 case ixgbe_mac_X540:
9a75a1ac
DS		 7442 case ixgbe_mac_X550:
7443 case ixgbe_mac_X550EM_x:
49425dfc 7444 case ixgbe_mac_x550em_a:
93c52dd0
AD		 7445 case ixgbe_mac_82599EB: {
7446 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
7447 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
7448 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
7449 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
7450 }
7451 break;
7452 default:
7453 flow_tx = false;
7454 flow_rx = false;
7455 break;
e8e26350 7456 }
3a6a4eda 7457
6cb562d6
JK		 7458 adapter->last_rx_ptp_check = jiffies;
7459
8fecf67c 7460 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 7461 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 7462
454adb00
MR		 7463 switch (link_speed) {
7464 case IXGBE_LINK_SPEED_10GB_FULL:
7465 speed_str = "10 Gbps";
7466 break;
06e3f949
PG		 7467 case IXGBE_LINK_SPEED_5GB_FULL:
7468 speed_str = "5 Gbps";
7469 break;
454adb00
MR		 7470 case IXGBE_LINK_SPEED_2_5GB_FULL:
7471 speed_str = "2.5 Gbps";
7472 break;
7473 case IXGBE_LINK_SPEED_1GB_FULL:
7474 speed_str = "1 Gbps";
7475 break;
7476 case IXGBE_LINK_SPEED_100_FULL:
7477 speed_str = "100 Mbps";
7478 break;
b3eb4e18
MR		 7479 case IXGBE_LINK_SPEED_10_FULL:
7480 speed_str = "10 Mbps";
7481 break;
454adb00
MR		 7482 default:
7483 speed_str = "unknown speed";
7484 break;
7485 }
7486 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 7487 ((flow_rx && flow_tx) ? "RX/TX" :
7488 (flow_rx ? "RX" :
7489 (flow_tx ? "TX" : "None"))));
e8e26350 7490
93c52dd0 7491 netif_carrier_on(netdev);
93c52dd0 7492 ixgbe_check_vf_rate_limit(adapter);
befa2af7 7493
cdc04dcc
ET		 7494 /* enable transmits */
7495 netif_tx_wake_all_queues(adapter->netdev);
7496
107d3018
AD		 7497 /* update the default user priority for VFs */
7498 ixgbe_update_default_up(adapter);
7499
befa2af7
AD		 7500 /* ping all the active vfs to let them know link has changed */
7501 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 7502}
7503
c4cf55e5 7504/**
93c52dd0
AD		 7505 * ixgbe_watchdog_link_is_down - update netif_carrier status and
7506 * print link down message
49ce9c2c 7507 * @adapter: pointer to the adapter structure
c4cf55e5 7508 **/
581330ba 7509static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 7510{
cf8280ee 7511 struct net_device *netdev = adapter->netdev;
c4cf55e5 7512 struct ixgbe_hw *hw = &adapter->hw;
10eec955 7513
93c52dd0
AD		 7514 adapter->link_up = false;
7515 adapter->link_speed = 0;
cf8280ee 7516
93c52dd0
AD		 7517 /* only continue if link was up previously */
7518 if (!netif_carrier_ok(netdev))
7519 return;
264857b8 7520
93c52dd0
AD		 7521 /* poll for SFP+ cable when link is down */
7522 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
7523 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 7524
8fecf67c 7525 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 7526 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 7527
93c52dd0
AD		 7528 e_info(drv, "NIC Link is Down\n");
7529 netif_carrier_off(netdev);
befa2af7
AD		 7530
7531 /* ping all the active vfs to let them know link has changed */
7532 ixgbe_ping_all_vfs(adapter);
93c52dd0 7533}
e8e26350 7534
07923c17
ET		 7535static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
7536{
7537 int i;
7538
7539 for (i = 0; i < adapter->num_tx_queues; i++) {
7540 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
7541
7542 if (tx_ring->next_to_use != tx_ring->next_to_clean)
7543 return true;
7544 }
7545
33fdc82f
JF		 7546 for (i = 0; i < adapter->num_xdp_queues; i++) {
7547 struct ixgbe_ring *ring = adapter->xdp_ring[i];
7548
7549 if (ring->next_to_use != ring->next_to_clean)
7550 return true;
7551 }
7552
07923c17
ET		 7553 return false;
7554}
7555
7556static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
7557{
7558 struct ixgbe_hw *hw = &adapter->hw;
7559 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
7560 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
7561
7562 int i, j;
7563
7564 if (!adapter->num_vfs)
7565 return false;
7566
9a75a1ac
DS		 7567 /* resetting the PF is only needed for MAC before X550 */
7568 if (hw->mac.type >= ixgbe_mac_X550)
7569 return false;
7570
07923c17
ET		 7571 for (i = 0; i < adapter->num_vfs; i++) {
7572 for (j = 0; j < q_per_pool; j++) {
7573 u32 h, t;
7574
7575 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
7576 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
7577
7578 if (h != t)
7579 return true;
7580 }
7581 }
7582
7583 return false;
7584}
7585
93c52dd0
AD		 7586/**
7587 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 7588 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 7589 **/
7590static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
7591{
93c52dd0 7592 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 7593 if (ixgbe_ring_tx_pending(adapter) ||
7594 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 7595 /* We've lost link, so the controller stops DMA,
7596 * but we've got queued Tx work that's never going
7597 * to get done, so reset controller to flush Tx.
7598 * (Do the reset outside of interrupt context).
7599 */
12ff3f3b 7600 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
57ca2a4f 7601 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
bc59fcda 7602 }
c4cf55e5 7603 }
c4cf55e5
PWJ		 7604}
7605
9079e416 7606#ifdef CONFIG_PCI_IOV
9079e416
ET		 7607static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
7608{
7609 struct ixgbe_hw *hw = &adapter->hw;
7610 struct pci_dev *pdev = adapter->pdev;
988d1307 7611 unsigned int vf;
9079e416 7612 u32 gpc;
9079e416
ET		 7613
7614 if (!(netif_carrier_ok(adapter->netdev)))
7615 return;
7616
7617 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
7618 if (gpc) /* If incrementing then no need for the check below */
7619 return;
7620 /* Check to see if a bad DMA write target from an errant or
7621 * malicious VF has caused a PCIe error. If so then we can
7622 * issue a VFLR to the offending VF(s) and then resume without
7623 * requesting a full slot reset.
7624 */
7625
7626 if (!pdev)
7627 return;
7628
9079e416 7629 /* check status reg for all VFs owned by this PF */
988d1307
MR		 7630 for (vf = 0; vf < adapter->num_vfs; ++vf) {
7631 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
7632 u16 status_reg;
9079e416 7633
988d1307
MR		 7634 if (!vfdev)
7635 continue;
7636 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
7637 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
7638 status_reg & PCI_STATUS_REC_MASTER_ABORT)
63af8f7a 7639 pcie_flr(vfdev);
9079e416
ET		 7640 }
7641}
7642
a985b6c3
GR		 7643static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
7644{
7645 u32 ssvpc;
7646
0584d999
GR		 7647 /* Do not perform spoof check for 82598 or if not in IOV mode */
7648 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7649 adapter->num_vfs == 0)
a985b6c3
GR		 7650 return;
7651
7652 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
7653
7654 /*
7655 * ssvpc register is cleared on read, if zero then no
7656 * spoofed packets in the last interval.
7657 */
7658 if (!ssvpc)
7659 return;
7660
d6ea0754 7661 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 7662}
9079e416
ET		 7663#else
7664static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7665{
7666}
7667
7668static void
7669ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7670{
7671}
7672#endif /* CONFIG_PCI_IOV */
7673
a985b6c3 7674
93c52dd0
AD		 7675/**
7676 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 7677 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 7678 **/
7679static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7680{
09f40aed 7681 /* if interface is down, removing or resetting, do nothing */
7edebf9a 7682 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7683 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 7684 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 7685 return;
7686
7687 ixgbe_watchdog_update_link(adapter);
7688
7689 if (adapter->link_up)
7690 ixgbe_watchdog_link_is_up(adapter);
7691 else
7692 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 7693
9079e416 7694 ixgbe_check_for_bad_vf(adapter);
a985b6c3 7695 ixgbe_spoof_check(adapter);
9a799d71 7696 ixgbe_update_stats(adapter);
93c52dd0
AD		 7697
7698 ixgbe_watchdog_flush_tx(adapter);
9a799d71 7699}
10eec955 7700
cf8280ee 7701/**
7086400d 7702 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 7703 * @adapter: the ixgbe adapter structure
cf8280ee 7704 **/
7086400d 7705static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 7706{
cf8280ee 7707 struct ixgbe_hw *hw = &adapter->hw;
7086400d 7708 s32 err;
cf8280ee 7709
7086400d
AD		 7710 /* not searching for SFP so there is nothing to do here */
7711 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7712 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7713 return;
10eec955 7714
58e7cd24
MR		 7715 if (adapter->sfp_poll_time &&
7716 time_after(adapter->sfp_poll_time, jiffies))
7717 return; /* If not yet time to poll for SFP */
7718
7086400d
AD		 7719 /* someone else is in init, wait until next service event */
7720 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7721 return;
cf8280ee 7722
58e7cd24
MR		 7723 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7724
7086400d
AD		 7725 err = hw->phy.ops.identify_sfp(hw);
7726 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7727 goto sfp_out;
264857b8 7728
7086400d
AD		 7729 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7730 /* If no cable is present, then we need to reset
7731 * the next time we find a good cable. */
7732 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 7733 }
9a799d71 7734
7086400d
AD		 7735 /* exit on error */
7736 if (err)
7737 goto sfp_out;
e8e26350 7738
7086400d
AD		 7739 /* exit if reset not needed */
7740 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7741 goto sfp_out;
9a799d71 7742
7086400d 7743 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 7744
7086400d
AD		 7745 /*
7746 * A module may be identified correctly, but the EEPROM may not have
7747 * support for that module. setup_sfp() will fail in that case, so
7748 * we should not allow that module to load.
7749 */
7750 if (hw->mac.type == ixgbe_mac_82598EB)
7751 err = hw->phy.ops.reset(hw);
7752 else
7753 err = hw->mac.ops.setup_sfp(hw);
7754
7755 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7756 goto sfp_out;
7757
7758 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7759 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7760
7761sfp_out:
7762 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7763
7764 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7765 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7766 e_dev_err("failed to initialize because an unsupported "
7767 "SFP+ module type was detected.\n");
7768 e_dev_err("Reload the driver after installing a "
7769 "supported module.\n");
7770 unregister_netdev(adapter->netdev);
bc59fcda 7771 }
7086400d 7772}
bc59fcda 7773
7086400d
AD		 7774/**
7775 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 7776 * @adapter: the ixgbe adapter structure
7086400d
AD		 7777 **/
7778static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7779{
7780 struct ixgbe_hw *hw = &adapter->hw;
3ead7c2e 7781 u32 cap_speed;
3d292265
JH		 7782 u32 speed;
7783 bool autoneg = false;
7086400d
AD		 7784
7785 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7786 return;
7787
7788 /* someone else is in init, wait until next service event */
7789 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7790 return;
7791
7792 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7793
3ead7c2e 7794 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg);
ed33ff66 7795
3ead7c2e
PG		 7796 /* advertise highest capable link speed */
7797 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL))
7798 speed = IXGBE_LINK_SPEED_10GB_FULL;
7799 else
7800 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL |
7801 IXGBE_LINK_SPEED_1GB_FULL);
ed33ff66 7802
7086400d 7803 if (hw->mac.ops.setup_link)
fd0326f2 7804 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 7805
7806 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7807 adapter->link_check_timeout = jiffies;
7808 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7809}
7810
7811/**
7812 * ixgbe_service_timer - Timer Call-back
5ba643c6 7813 * @t: pointer to timer_list structure
7086400d 7814 **/
26566eae 7815static void ixgbe_service_timer(struct timer_list *t)
7086400d 7816{
26566eae 7817 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer);
7086400d
AD		 7818 unsigned long next_event_offset;
7819
6bb78cfb
AD		 7820 /* poll faster when waiting for link */
7821 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7822 next_event_offset = HZ / 10;
7823 else
7824 next_event_offset = HZ * 2;
83c61fa9 7825
7086400d
AD		 7826 /* Reset the timer */
7827 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7828
9079e416 7829 ixgbe_service_event_schedule(adapter);
7086400d
AD		 7830}
7831
597f22d6
DS		 7832static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7833{
7834 struct ixgbe_hw *hw = &adapter->hw;
7835 u32 status;
7836
7837 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7838 return;
7839
7840 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7841
7842 if (!hw->phy.ops.handle_lasi)
7843 return;
7844
7845 status = hw->phy.ops.handle_lasi(&adapter->hw);
7846 if (status != IXGBE_ERR_OVERTEMP)
7847 return;
7848
7849 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7850}
7851
c83c6cbd
AD		 7852static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7853{
57ca2a4f 7854 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
c83c6cbd
AD		 7855 return;
7856
88adce4e 7857 rtnl_lock();
09f40aed 7858 /* If we're already down, removing or resetting, just bail */
c83c6cbd 7859 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7860 test_bit(__IXGBE_REMOVING, &adapter->state) ||
88adce4e
TN		 7861 test_bit(__IXGBE_RESETTING, &adapter->state)) {
7862 rtnl_unlock();
c83c6cbd 7863 return;
88adce4e 7864 }
c83c6cbd
AD		 7865
7866 ixgbe_dump(adapter);
7867 netdev_err(adapter->netdev, "Reset adapter\n");
7868 adapter->tx_timeout_count++;
7869
7870 ixgbe_reinit_locked(adapter);
8f4c5c9f 7871 rtnl_unlock();
c83c6cbd
AD		 7872}
7873
59dd45d5
SB		 7874/**
7875 * ixgbe_check_fw_error - Check firmware for errors
7876 * @adapter: the adapter private structure
7877 *
7878 * Check firmware errors in register FWSM
7879 */
7880static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter)
7881{
7882 struct ixgbe_hw *hw = &adapter->hw;
7883 u32 fwsm;
7884
7885 /* read fwsm.ext_err_ind register and log errors */
7886 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
7887
7888 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK ||
7889 !(fwsm & IXGBE_FWSM_FW_VAL_BIT))
7890 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n",
7891 fwsm);
7892
7893 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
7894 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n");
7895 return true;
7896 }
7897
7898 return false;
7899}
7900
7086400d
AD		 7901/**
7902 * ixgbe_service_task - manages and runs subtasks
7903 * @work: pointer to work_struct containing our data
7904 **/
7905static void ixgbe_service_task(struct work_struct *work)
7906{
7907 struct ixgbe_adapter *adapter = container_of(work,
7908 struct ixgbe_adapter,
7909 service_task);
b0483c8f
MR		 7910 if (ixgbe_removed(adapter->hw.hw_addr)) {
7911 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7912 rtnl_lock();
7913 ixgbe_down(adapter);
7914 rtnl_unlock();
7915 }
7916 ixgbe_service_event_complete(adapter);
7917 return;
7918 }
59dd45d5 7919 if (ixgbe_check_fw_error(adapter)) {
8b638160 7920 if (!test_bit(__IXGBE_DOWN, &adapter->state))
59dd45d5 7921 unregister_netdev(adapter->netdev);
59dd45d5
SB		 7922 ixgbe_service_event_complete(adapter);
7923 return;
7924 }
c83c6cbd 7925 ixgbe_reset_subtask(adapter);
597f22d6 7926 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 7927 ixgbe_sfp_detection_subtask(adapter);
7928 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 7929 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 7930 ixgbe_watchdog_subtask(adapter);
d034acf1 7931 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 7932 ixgbe_check_hang_subtask(adapter);
891dc082 7933
8fecf67c 7934 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082 7935 ixgbe_ptp_overflow_check(adapter);
6704a3ab
JK		 7936 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER)
7937 ixgbe_ptp_rx_hang(adapter);
622a2ef5 7938 ixgbe_ptp_tx_hang(adapter);
891dc082 7939 }
7086400d
AD		 7940
7941 ixgbe_service_event_complete(adapter);
9a799d71
AK		 7942}
7943
fd0db0ed
AD		 7944static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7945 struct ixgbe_tx_buffer *first,
70da6824
SN		 7946 u8 *hdr_len,
7947 struct ixgbe_ipsec_tx_data *itd)
897ab156 7948{
b83e3010 7949 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
fd0db0ed 7950 struct sk_buff *skb = first->skb;
b83e3010
AD		 7951 union {
7952 struct iphdr *v4;
7953 struct ipv6hdr *v6;
7954 unsigned char *hdr;
7955 } ip;
7956 union {
7957 struct tcphdr *tcp;
c74d4bdb 7958 struct udphdr *udp;
b83e3010
AD		 7959 unsigned char *hdr;
7960 } l4;
7961 u32 paylen, l4_offset;
70da6824 7962 u32 fceof_saidx = 0;
2049e1f6 7963 int err;
9a799d71 7964
8f4fbb9b
AD		 7965 if (skb->ip_summed != CHECKSUM_PARTIAL)
7966 return 0;
7967
897ab156
AD		 7968 if (!skb_is_gso(skb))
7969 return 0;
9a799d71 7970
2049e1f6
FR		 7971 err = skb_cow_head(skb, 0);
7972 if (err < 0)
7973 return err;
9a799d71 7974
2a20525b
SP		 7975 if (eth_p_mpls(first->protocol))
7976 ip.hdr = skb_inner_network_header(skb);
7977 else
7978 ip.hdr = skb_network_header(skb);
b83e3010
AD		 7979 l4.hdr = skb_checksum_start(skb);
7980
897ab156 7981 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
c74d4bdb
JH		 7982 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
7983 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP;
897ab156 7984
b83e3010
AD		 7985 /* initialize outer IP header fields */
7986 if (ip.v4->version == 4) {
c54cdc31
AD		 7987 unsigned char *csum_start = skb_checksum_start(skb);
7988 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
70da6824 7989 int len = csum_start - trans_start;
c54cdc31 7990
b83e3010 7991 /* IP header will have to cancel out any data that
70da6824
SN		 7992 * is not a part of the outer IP header, so set to
7993 * a reverse csum if needed, else init check to 0.
b83e3010 7994 */
70da6824
SN		 7995 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ?
7996 csum_fold(csum_partial(trans_start,
7997 len, 0)) : 0;
897ab156 7998 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
b83e3010
AD		 7999
8000 ip.v4->tot_len = 0;
244e27ad
AD		 8001 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
8002 IXGBE_TX_FLAGS_CSUM |
8003 IXGBE_TX_FLAGS_IPV4;
b83e3010
AD		 8004 } else {
8005 ip.v6->payload_len = 0;
244e27ad
AD		 8006 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
8007 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 8008 }
8009
b83e3010
AD		 8010 /* determine offset of inner transport header */
8011 l4_offset = l4.hdr - skb->data;
8012
b83e3010
AD		 8013 /* remove payload length from inner checksum */
8014 paylen = skb->len - l4_offset;
c74d4bdb
JH		 8015
8016 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) {
8017 /* compute length of segmentation header */
8018 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
8019 csum_replace_by_diff(&l4.tcp->check,
8020 (__force __wsum)htonl(paylen));
8021 } else {
8022 /* compute length of segmentation header */
8023 *hdr_len = sizeof(*l4.udp) + l4_offset;
8024 csum_replace_by_diff(&l4.udp->check,
8025 (__force __wsum)htonl(paylen));
8026 }
897ab156 8027
091a6246
AD		 8028 /* update gso size and bytecount with header size */
8029 first->gso_segs = skb_shinfo(skb)->gso_segs;
8030 first->bytecount += (first->gso_segs - 1) * *hdr_len;
8031
c44f5f51 8032 /* mss_l4len_id: use 0 as index for TSO */
b83e3010 8033 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
897ab156 8034 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156 8035
70da6824
SN		 8036 fceof_saidx |= itd->sa_idx;
8037 type_tucmd |= itd->flags | itd->trailer_len;
8038
897ab156 8039 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
b83e3010
AD		 8040 vlan_macip_lens = l4.hdr - ip.hdr;
8041 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 8042 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156 8043
70da6824 8044 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd,
244e27ad 8045 mss_l4len_idx);
897ab156
AD		 8046
8047 return 1;
8048}
8049
244e27ad 8050static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
59259470
SN		 8051 struct ixgbe_tx_buffer *first,
8052 struct ixgbe_ipsec_tx_data *itd)
7ca647bd 8053{
fd0db0ed 8054 struct sk_buff *skb = first->skb;
897ab156 8055 u32 vlan_macip_lens = 0;
59259470 8056 u32 fceof_saidx = 0;
897ab156 8057 u32 type_tucmd = 0;
7ca647bd 8058
897ab156 8059 if (skb->ip_summed != CHECKSUM_PARTIAL) {
49763de0
AD		 8060csum_failed:
8061 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
8062 IXGBE_TX_FLAGS_CC)))
472148c3 8063 return;
49763de0
AD		 8064 goto no_csum;
8065 }
897ab156 8066
49763de0
AD		 8067 switch (skb->csum_offset) {
8068 case offsetof(struct tcphdr, check):
8069 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5463fce6 8070 fallthrough;
49763de0
AD		 8071 case offsetof(struct udphdr, check):
8072 break;
8073 case offsetof(struct sctphdr, checksum):
8074 /* validate that this is actually an SCTP request */
f8c4b01d 8075 if (skb_csum_is_sctp(skb)) {
49763de0 8076 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
897ab156 8077 break;
7ca647bd 8078 }
5463fce6 8079 fallthrough;
49763de0
AD		 8080 default:
8081 skb_checksum_help(skb);
8082 goto csum_failed;
7ca647bd
JP		 8083 }
8084
49763de0
AD		 8085 /* update TX checksum flag */
8086 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
8087 vlan_macip_lens = skb_checksum_start_offset(skb) -
8088 skb_network_offset(skb);
36a92d71 8089no_csum:
244e27ad 8090 /* vlan_macip_lens: MACLEN, VLAN tag */
49763de0 8091 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 8092 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 8093
871dd09b
SN		 8094 fceof_saidx |= itd->sa_idx;
8095 type_tucmd |= itd->flags | itd->trailer_len;
59259470
SN		 8096
8097 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0);
9a799d71
AK		 8098}
8099
472148c3
AD		 8100#define IXGBE_SET_FLAG(_input, _flag, _result) \
8101 ((_flag <= _result) ? \
8102 ((u32)(_input & _flag) * (_result / _flag)) : \
8103 ((u32)(_input & _flag) / (_flag / _result)))
8104
8105static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 8106{
d3d00239 8107 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 8108 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8109 IXGBE_ADVTXD_DCMD_DEXT |
8110 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 8111
d3d00239 8112 /* set HW vlan bit if vlan is present */
472148c3
AD		 8113 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
8114 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 8115
d3d00239 8116 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 8117 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
8118 IXGBE_ADVTXD_DCMD_TSE);
8119
8120 /* set timestamp bit if present */
8121 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
8122 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 8123
62748b7b 8124 /* insert frame checksum */
472148c3 8125 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 8126
d3d00239
AD		 8127 return cmd_type;
8128}
9a799d71 8129
729739b7
AD		 8130static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
8131 u32 tx_flags, unsigned int paylen)
d3d00239 8132{
472148c3 8133 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 8134
d3d00239 8135 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 8136 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8137 IXGBE_TX_FLAGS_CSUM,
8138 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 8139
59259470 8140 /* enable IPv4 checksum for TSO */
472148c3
AD		 8141 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8142 IXGBE_TX_FLAGS_IPV4,
8143 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 8144
59259470
SN		 8145 /* enable IPsec */
8146 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8147 IXGBE_TX_FLAGS_IPSEC,
8148 IXGBE_ADVTXD_POPTS_IPSEC);
8149
7f9643fd
AD		 8150 /*
8151 * Check Context must be set if Tx switch is enabled, which it
8152 * always is for case where virtual functions are running
8153 */
472148c3
AD		 8154 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8155 IXGBE_TX_FLAGS_CC,
8156 IXGBE_ADVTXD_CC);
7f9643fd 8157
472148c3 8158 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 8159}
44df32c5 8160
2367a173
DB		 8161static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8162{
8163 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
8164
8165 /* Herbert's original patch had:
8166 * smp_mb__after_netif_stop_queue();
8167 * but since that doesn't exist yet, just open code it.
8168 */
8169 smp_mb();
8170
8171 /* We need to check again in a case another CPU has just
8172 * made room available.
8173 */
8174 if (likely(ixgbe_desc_unused(tx_ring) < size))
8175 return -EBUSY;
8176
8177 /* A reprieve! - use start_queue because it doesn't call schedule */
8178 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
8179 ++tx_ring->tx_stats.restart_queue;
8180 return 0;
8181}
8182
8183static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8184{
8185 if (likely(ixgbe_desc_unused(tx_ring) >= size))
8186 return 0;
8187
8188 return __ixgbe_maybe_stop_tx(tx_ring, size);
8189}
8190
5fef124d
JK		 8191static int ixgbe_tx_map(struct ixgbe_ring *tx_ring,
8192 struct ixgbe_tx_buffer *first,
8193 const u8 hdr_len)
d3d00239 8194{
fd0db0ed 8195 struct sk_buff *skb = first->skb;
729739b7 8196 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 8197 union ixgbe_adv_tx_desc *tx_desc;
d7840976 8198 skb_frag_t *frag;
ec718254
AD		 8199 dma_addr_t dma;
8200 unsigned int data_len, size;
244e27ad 8201 u32 tx_flags = first->tx_flags;
472148c3 8202 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 8203 u16 i = tx_ring->next_to_use;
d3d00239 8204
729739b7
AD		 8205 tx_desc = IXGBE_TX_DESC(tx_ring, i);
8206
ec718254
AD		 8207 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
8208
8209 size = skb_headlen(skb);
8210 data_len = skb->data_len;
729739b7 8211
d3d00239
AD		 8212#ifdef IXGBE_FCOE
8213 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 8214 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 8215 size -= sizeof(struct fcoe_crc_eof) - data_len;
8216 data_len = 0;
729739b7
AD		 8217 } else {
8218 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 8219 }
8220 }
44df32c5 8221
d3d00239 8222#endif
729739b7 8223 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 8224
ec718254 8225 tx_buffer = first;
9a799d71 8226
ec718254
AD		 8227 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
8228 if (dma_mapping_error(tx_ring->dev, dma))
8229 goto dma_error;
8230
8231 /* record length, and DMA address */
8232 dma_unmap_len_set(tx_buffer, len, size);
8233 dma_unmap_addr_set(tx_buffer, dma, dma);
8234
8235 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 8236
729739b7 8237 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 8238 tx_desc->read.cmd_type_len =
472148c3 8239 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 8240
d3d00239 8241 i++;
729739b7 8242 tx_desc++;
d3d00239 8243 if (i == tx_ring->count) {
e4f74028 8244 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 8245 i = 0;
8246 }
ec718254 8247 tx_desc->read.olinfo_status = 0;
729739b7
AD		 8248
8249 dma += IXGBE_MAX_DATA_PER_TXD;
8250 size -= IXGBE_MAX_DATA_PER_TXD;
8251
8252 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 8253 }
e5a43549 8254
729739b7
AD		 8255 if (likely(!data_len))
8256 break;
9a799d71 8257
472148c3 8258 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 8259
729739b7
AD		 8260 i++;
8261 tx_desc++;
8262 if (i == tx_ring->count) {
8263 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8264 i = 0;
8265 }
ec718254 8266 tx_desc->read.olinfo_status = 0;
9a799d71 8267
d3d00239 8268#ifdef IXGBE_FCOE
9e903e08 8269 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 8270#else
9e903e08 8271 size = skb_frag_size(frag);
d3d00239
AD		 8272#endif
8273 data_len -= size;
9a799d71 8274
729739b7
AD		 8275 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
8276 DMA_TO_DEVICE);
9a799d71 8277
729739b7 8278 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 8279 }
9a799d71 8280
729739b7 8281 /* write last descriptor with RS and EOP bits */
472148c3
AD		 8282 cmd_type |= size | IXGBE_TXD_CMD;
8283 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 8284
091a6246 8285 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 8286
d3d00239
AD		 8287 /* set the timestamp */
8288 first->time_stamp = jiffies;
9a799d71 8289
a9e51058
JK		 8290 skb_tx_timestamp(skb);
8291
9a799d71 8292 /*
729739b7
AD		 8293 * Force memory writes to complete before letting h/w know there
8294 * are new descriptors to fetch. (Only applicable for weak-ordered
8295 * memory model archs, such as IA-64).
8296 *
8297 * We also need this memory barrier to make certain all of the
8298 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 8299 */
8300 wmb();
8301
d3d00239
AD		 8302 /* set next_to_watch value indicating a packet is present */
8303 first->next_to_watch = tx_desc;
8304
729739b7
AD		 8305 i++;
8306 if (i == tx_ring->count)
8307 i = 0;
8308
8309 tx_ring->next_to_use = i;
8310
2367a173
DB		 8311 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
8312
6b16f9ee 8313 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
ad435ec6 8314 writel(i, tx_ring->tail);
9c938cdd 8315 }
2367a173 8316
5fef124d 8317 return 0;
d3d00239 8318dma_error:
729739b7 8319 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 8320
8321 /* clear dma mappings for failed tx_buffer_info map */
069db9cd
AD		 8322 for (;;) {
8323 tx_buffer = &tx_ring->tx_buffer_info[i];
ffed21bc
AD		 8324 if (dma_unmap_len(tx_buffer, len))
8325 dma_unmap_page(tx_ring->dev,
8326 dma_unmap_addr(tx_buffer, dma),
8327 dma_unmap_len(tx_buffer, len),
8328 DMA_TO_DEVICE);
8329 dma_unmap_len_set(tx_buffer, len, 0);
069db9cd
AD		 8330 if (tx_buffer == first)
8331 break;
8332 if (i == 0)
ffed21bc 8333 i += tx_ring->count;
069db9cd 8334 i--;
d3d00239
AD		 8335 }
8336
ffed21bc
AD		 8337 dev_kfree_skb_any(first->skb);
8338 first->skb = NULL;
8339
d3d00239 8340 tx_ring->next_to_use = i;
5fef124d
JK		 8341
8342 return -1;
9a799d71
AK		 8343}
8344
fd0db0ed 8345static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 8346 struct ixgbe_tx_buffer *first)
69830529
AD		 8347{
8348 struct ixgbe_q_vector *q_vector = ring->q_vector;
8349 union ixgbe_atr_hash_dword input = { .dword = 0 };
8350 union ixgbe_atr_hash_dword common = { .dword = 0 };
8351 union {
8352 unsigned char *network;
8353 struct iphdr *ipv4;
8354 struct ipv6hdr *ipv6;
8355 } hdr;
ee9e0f0b 8356 struct tcphdr *th;
e2873d43 8357 unsigned int hlen;
67359c3c 8358 struct sk_buff *skb;
905e4a41 8359 __be16 vlan_id;
e2873d43 8360 int l4_proto;
c4cf55e5 8361
69830529
AD		 8362 /* if ring doesn't have a interrupt vector, cannot perform ATR */
8363 if (!q_vector)
8364 return;
8365
8366 /* do nothing if sampling is disabled */
8367 if (!ring->atr_sample_rate)
d3ead241 8368 return;
c4cf55e5 8369
69830529 8370 ring->atr_count++;
c4cf55e5 8371
e2873d43
AD		 8372 /* currently only IPv4/IPv6 with TCP is supported */
8373 if ((first->protocol != htons(ETH_P_IP)) &&
8374 (first->protocol != htons(ETH_P_IPV6)))
8375 return;
8376
69830529 8377 /* snag network header to get L4 type and address */
67359c3c
MR		 8378 skb = first->skb;
8379 hdr.network = skb_network_header(skb);
9f3c7504
SV		 8380 if (unlikely(hdr.network <= skb->data))
8381 return;
9f12df90
AD		 8382 if (skb->encapsulation &&
8383 first->protocol == htons(ETH_P_IP) &&
52028821 8384 hdr.ipv4->protocol == IPPROTO_UDP) {
67359c3c 8385 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 8386
9f3c7504
SV		 8387 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8388 VXLAN_HEADROOM))
8389 return;
8390
9f12df90
AD		 8391 /* verify the port is recognized as VXLAN */
8392 if (adapter->vxlan_port &&
e2873d43 8393 udp_hdr(skb)->dest == adapter->vxlan_port)
9f12df90 8394 hdr.network = skb_inner_network_header(skb);
a21d0822
ET		 8395
8396 if (adapter->geneve_port &&
8397 udp_hdr(skb)->dest == adapter->geneve_port)
8398 hdr.network = skb_inner_network_header(skb);
e19dcdeb
MR		 8399 }
8400
9f3c7504
SV		 8401 /* Make sure we have at least [minimum IPv4 header + TCP]
8402 * or [IPv6 header] bytes
8403 */
8404 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40))
8405 return;
8406
e19dcdeb
MR		 8407 /* Currently only IPv4/IPv6 with TCP is supported */
8408 switch (hdr.ipv4->version) {
8409 case IPVERSION:
e2873d43
AD		 8410 /* access ihl as u8 to avoid unaligned access on ia64 */
8411 hlen = (hdr.network[0] & 0x0F) << 2;
8412 l4_proto = hdr.ipv4->protocol;
e19dcdeb
MR		 8413 break;
8414 case 6:
e2873d43
AD		 8415 hlen = hdr.network - skb->data;
8416 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
8417 hlen -= hdr.network - skb->data;
e19dcdeb
MR		 8418 break;
8419 default:
8420 return;
67359c3c 8421 }
c4cf55e5 8422
e2873d43
AD		 8423 if (l4_proto != IPPROTO_TCP)
8424 return;
8425
9f3c7504
SV		 8426 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8427 hlen + sizeof(struct tcphdr)))
8428 return;
8429
e2873d43
AD		 8430 th = (struct tcphdr *)(hdr.network + hlen);
8431
8432 /* skip this packet since the socket is closing */
8433 if (th->fin)
69830529
AD		 8434 return;
8435
8436 /* sample on all syn packets or once every atr sample count */
8437 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
8438 return;
8439
8440 /* reset sample count */
8441 ring->atr_count = 0;
8442
244e27ad 8443 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 8444
8445 /*
8446 * src and dst are inverted, think how the receiver sees them
8447 *
8448 * The input is broken into two sections, a non-compressed section
8449 * containing vm_pool, vlan_id, and flow_type. The rest of the data
8450 * is XORed together and stored in the compressed dword.
8451 */
8452 input.formatted.vlan_id = vlan_id;
8453
8454 /*
8455 * since src port and flex bytes occupy the same word XOR them together
8456 * and write the value to source port portion of compressed dword
8457 */
244e27ad 8458 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 8459 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 8460 else
244e27ad 8461 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 8462 common.port.dst ^= th->source;
8463
e19dcdeb
MR		 8464 switch (hdr.ipv4->version) {
8465 case IPVERSION:
69830529
AD		 8466 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
8467 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
e19dcdeb
MR		 8468 break;
8469 case 6:
69830529
AD		 8470 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
8471 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
8472 hdr.ipv6->saddr.s6_addr32[1] ^
8473 hdr.ipv6->saddr.s6_addr32[2] ^
8474 hdr.ipv6->saddr.s6_addr32[3] ^
8475 hdr.ipv6->daddr.s6_addr32[0] ^
8476 hdr.ipv6->daddr.s6_addr32[1] ^
8477 hdr.ipv6->daddr.s6_addr32[2] ^
8478 hdr.ipv6->daddr.s6_addr32[3];
e19dcdeb
MR		 8479 break;
8480 default:
8481 break;
69830529 8482 }
c4cf55e5 8483
9f12df90 8484 if (hdr.network != skb_network_header(skb))
67359c3c 8485 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
67359c3c 8486
c4cf55e5 8487 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 8488 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
8489 input, common, ring->queue_index);
c4cf55e5
PWJ		 8490}
8491
eadec877 8492#ifdef IXGBE_FCOE
f663dd9a 8493static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
a350ecce 8494 struct net_device *sb_dev)
09a3b1f8 8495{
58b0b3ed 8496 struct ixgbe_adapter *adapter;
16be45bc 8497 struct ixgbe_ring_feature *f;
58b0b3ed 8498 int txq;
f663dd9a 8499
4f49dec9 8500 if (sb_dev) {
eadec877 8501 u8 tc = netdev_get_prio_tc_map(dev, skb->priority);
4f49dec9 8502 struct net_device *vdev = sb_dev;
58b0b3ed
AD		 8503
8504 txq = vdev->tc_to_txq[tc].offset;
8505 txq += reciprocal_scale(skb_get_hash(skb),
8506 vdev->tc_to_txq[tc].count);
16be45bc 8507
58b0b3ed 8508 return txq;
16be45bc 8509 }
f663dd9a 8510
97488bd1
AD		 8511 /*
8512 * only execute the code below if protocol is FCoE
8513 * or FIP and we have FCoE enabled on the adapter
8514 */
8515 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 8516 case htons(ETH_P_FCOE):
8517 case htons(ETH_P_FIP):
97488bd1 8518 adapter = netdev_priv(dev);
c087663e 8519
8ec56fc3 8520 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
97488bd1 8521 break;
5463fce6 8522 fallthrough;
97488bd1 8523 default:
a350ecce 8524 return netdev_pick_tx(dev, skb, sb_dev);
97488bd1 8525 }
c087663e 8526
97488bd1 8527 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 8528
97488bd1
AD		 8529 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
8530 smp_processor_id();
56075a98 8531
97488bd1
AD		 8532 while (txq >= f->indices)
8533 txq -= f->indices;
c4cf55e5 8534
97488bd1 8535 return txq + f->offset;
09a3b1f8
SH		 8536}
8537
eadec877 8538#endif
46515fdb
BT		 8539int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
8540 struct xdp_frame *xdpf)
33fdc82f
JF		 8541{
8542 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
8543 struct ixgbe_tx_buffer *tx_buffer;
8544 union ixgbe_adv_tx_desc *tx_desc;
8545 u32 len, cmd_type;
8546 dma_addr_t dma;
8547 u16 i;
8548
03993094 8549 len = xdpf->len;
33fdc82f
JF		 8550
8551 if (unlikely(!ixgbe_desc_unused(ring)))
8552 return IXGBE_XDP_CONSUMED;
8553
03993094 8554 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE);
33fdc82f
JF		 8555 if (dma_mapping_error(ring->dev, dma))
8556 return IXGBE_XDP_CONSUMED;
8557
8558 /* record the location of the first descriptor for this packet */
8559 tx_buffer = &ring->tx_buffer_info[ring->next_to_use];
8560 tx_buffer->bytecount = len;
8561 tx_buffer->gso_segs = 1;
8562 tx_buffer->protocol = 0;
8563
8564 i = ring->next_to_use;
8565 tx_desc = IXGBE_TX_DESC(ring, i);
8566
8567 dma_unmap_len_set(tx_buffer, len, len);
8568 dma_unmap_addr_set(tx_buffer, dma, dma);
03993094 8569 tx_buffer->xdpf = xdpf;
189ead81 8570
33fdc82f
JF		 8571 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8572
8573 /* put descriptor type bits */
8574 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8575 IXGBE_ADVTXD_DCMD_DEXT |
8576 IXGBE_ADVTXD_DCMD_IFCS;
8577 cmd_type |= len | IXGBE_TXD_CMD;
8578 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8579 tx_desc->read.olinfo_status =
8580 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT);
8581
7379f97a
JF		 8582 /* Avoid any potential race with xdp_xmit and cleanup */
8583 smp_wmb();
33fdc82f
JF		 8584
8585 /* set next_to_watch value indicating a packet is present */
8586 i++;
8587 if (i == ring->count)
8588 i = 0;
8589
8590 tx_buffer->next_to_watch = tx_desc;
8591 ring->next_to_use = i;
8592
33fdc82f
JF		 8593 return IXGBE_XDP_TX;
8594}
8595
fc77dc3c 8596netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 8597 struct ixgbe_adapter *adapter,
8598 struct ixgbe_ring *tx_ring)
9a799d71 8599{
d3d00239 8600 struct ixgbe_tx_buffer *first;
5f715823 8601 int tso;
d3d00239 8602 u32 tx_flags = 0;
a535c30e 8603 unsigned short f;
a535c30e 8604 u16 count = TXD_USE_COUNT(skb_headlen(skb));
59259470 8605 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 };
66f32a8b 8606 __be16 protocol = skb->protocol;
63544e9c 8607 u8 hdr_len = 0;
5e09a105 8608
a535c30e
AD		 8609 /*
8610 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 8611 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 8612 * + 2 desc gap to keep tail from touching head,
8613 * + 1 desc for context descriptor,
8614 * otherwise try next time
8615 */
a535c30e 8616 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
d7840976
MWO		 8617 count += TXD_USE_COUNT(skb_frag_size(
8618 &skb_shinfo(skb)->frags[f]));
7f66162b 8619
a535c30e
AD		 8620 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
8621 tx_ring->tx_stats.tx_busy++;
8622 return NETDEV_TX_BUSY;
8623 }
8624
fd0db0ed
AD		 8625 /* record the location of the first descriptor for this packet */
8626 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
8627 first->skb = skb;
091a6246
AD		 8628 first->bytecount = skb->len;
8629 first->gso_segs = 1;
fd0db0ed 8630
66f32a8b 8631 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 8632 if (skb_vlan_tag_present(skb)) {
8633 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 8634 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8635 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 8636 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 8637 struct vlan_hdr *vhdr, _vhdr;
8638 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
8639 if (!vhdr)
8640 goto out_drop;
8641
9e0c5648
AD		 8642 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
8643 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 8644 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
8645 }
0213668f 8646 protocol = vlan_get_protocol(skb);
66f32a8b 8647
d5234933 8648 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4cc74c01 8649 adapter->ptp_clock) {
07066d9d
MP		 8650 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
8651 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
4cc74c01
JK		 8652 &adapter->state)) {
8653 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8654 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
8655
8656 /* schedule check for Tx timestamp */
8657 adapter->ptp_tx_skb = skb_get(skb);
8658 adapter->ptp_tx_start = jiffies;
8659 schedule_work(&adapter->ptp_tx_work);
8660 } else {
8661 adapter->tx_hwtstamp_skipped++;
8662 }
3a6a4eda 8663 }
3a6a4eda 8664
9e0c5648
AD		 8665#ifdef CONFIG_PCI_IOV
8666 /*
8667 * Use the l2switch_enable flag - would be false if the DMA
8668 * Tx switch had been disabled.
8669 */
8670 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 8671 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 8672
8673#endif
32701dc2 8674 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 8675 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 8676 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
8677 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 8678 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 8679 tx_flags |= (skb->priority & 0x7) <<
8680 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 8681 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
8682 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 8683
8684 if (skb_cow_head(skb, 0))
66f32a8b
AD		 8685 goto out_drop;
8686 vhdr = (struct vlan_ethhdr *)skb->data;
8687 vhdr->h_vlan_TCI = htons(tx_flags >>
8688 IXGBE_TX_FLAGS_VLAN_SHIFT);
8689 } else {
8690 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 8691 }
9a799d71 8692 }
eacd73f7 8693
244e27ad
AD		 8694 /* record initial flags and protocol */
8695 first->tx_flags = tx_flags;
8696 first->protocol = protocol;
8697
eacd73f7 8698#ifdef IXGBE_FCOE
66f32a8b 8699 /* setup tx offload for FCoE */
a1108ffd 8700 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 8701 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 8702 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 8703 if (tso < 0)
8704 goto out_drop;
9a799d71 8705
66f32a8b 8706 goto xmit_fcoe;
eacd73f7 8707 }
9a799d71 8708
66f32a8b 8709#endif /* IXGBE_FCOE */
59259470 8710
48e01e00 8711#ifdef CONFIG_IXGBE_IPSEC
f39b683d 8712 if (xfrm_offload(skb) &&
2fdb435b 8713 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx))
59259470
SN		 8714 goto out_drop;
8715#endif
70da6824 8716 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx);
66f32a8b 8717 if (tso < 0)
897ab156 8718 goto out_drop;
244e27ad 8719 else if (!tso)
59259470 8720 ixgbe_tx_csum(tx_ring, first, &ipsec_tx);
66f32a8b
AD		 8721
8722 /* add the ATR filter if ATR is on */
8723 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 8724 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 8725
8726#ifdef IXGBE_FCOE
8727xmit_fcoe:
8728#endif /* IXGBE_FCOE */
5fef124d
JK		 8729 if (ixgbe_tx_map(tx_ring, first, hdr_len))
8730 goto cleanup_tx_timestamp;
d3d00239 8731
9a799d71 8732 return NETDEV_TX_OK;
897ab156
AD		 8733
8734out_drop:
fd0db0ed
AD		 8735 dev_kfree_skb_any(first->skb);
8736 first->skb = NULL;
5fef124d
JK		 8737cleanup_tx_timestamp:
8738 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) {
8739 dev_kfree_skb_any(adapter->ptp_tx_skb);
8740 adapter->ptp_tx_skb = NULL;
8741 cancel_work_sync(&adapter->ptp_tx_work);
8742 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
8743 }
fd0db0ed 8744
897ab156 8745 return NETDEV_TX_OK;
9a799d71
AK		 8746}
8747
2a47fa45
JF		 8748static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
8749 struct net_device *netdev,
8750 struct ixgbe_ring *ring)
84418e3b
AD		 8751{
8752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8753 struct ixgbe_ring *tx_ring;
8754
a50c29dd
AD		 8755 /*
8756 * The minimum packet size for olinfo paylen is 17 so pad the skb
8757 * in order to meet this minimum size requirement.
8758 */
a94d9e22
AD		 8759 if (skb_put_padto(skb, 17))
8760 return NETDEV_TX_OK;
a50c29dd 8761
fb91a8bb 8762 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)];
024aa580
BT		 8763 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state)))
8764 return NETDEV_TX_BUSY;
2a47fa45 8765
fc77dc3c 8766 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 8767}
8768
2a47fa45
JF		 8769static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
8770 struct net_device *netdev)
8771{
8772 return __ixgbe_xmit_frame(skb, netdev, NULL);
8773}
8774
9a799d71
AK		 8775/**
8776 * ixgbe_set_mac - Change the Ethernet Address of the NIC
8777 * @netdev: network interface device structure
8778 * @p: pointer to an address structure
8779 *
8780 * Returns 0 on success, negative on failure
8781 **/
8782static int ixgbe_set_mac(struct net_device *netdev, void *p)
8783{
8784 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 8785 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 8786 struct sockaddr *addr = p;
8787
8788 if (!is_valid_ether_addr(addr->sa_data))
8789 return -EADDRNOTAVAIL;
8790
8791 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 8792 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 8793
c9f53e63
AD		 8794 ixgbe_mac_set_default_filter(adapter);
8795
8796 return 0;
9a799d71
AK		 8797}
8798
6b73e10d
BH		 8799static int
8800ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
8801{
8802 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8803 struct ixgbe_hw *hw = &adapter->hw;
8804 u16 value;
8805 int rc;
8806
643bae17
SD		 8807 if (adapter->mii_bus) {
8808 int regnum = addr;
8809
8810 if (devad != MDIO_DEVAD_NONE)
8811 regnum |= (devad << 16) | MII_ADDR_C45;
8812
8813 return mdiobus_read(adapter->mii_bus, prtad, regnum);
8814 }
8815
6b73e10d
BH		 8816 if (prtad != hw->phy.mdio.prtad)
8817 return -EINVAL;
8818 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
8819 if (!rc)
8820 rc = value;
8821 return rc;
8822}
8823
8824static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8825 u16 addr, u16 value)
8826{
8827 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8828 struct ixgbe_hw *hw = &adapter->hw;
8829
643bae17
SD		 8830 if (adapter->mii_bus) {
8831 int regnum = addr;
8832
8833 if (devad != MDIO_DEVAD_NONE)
8834 regnum |= (devad << 16) | MII_ADDR_C45;
8835
8836 return mdiobus_write(adapter->mii_bus, prtad, regnum, value);
8837 }
8838
6b73e10d
BH		 8839 if (prtad != hw->phy.mdio.prtad)
8840 return -EINVAL;
8841 return hw->phy.ops.write_reg(hw, addr, devad, value);
8842}
8843
8844static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8845{
8846 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8847
3a6a4eda 8848 switch (cmd) {
3a6a4eda 8849 case SIOCSHWTSTAMP:
93501d48
JK		 8850 return ixgbe_ptp_set_ts_config(adapter, req);
8851 case SIOCGHWTSTAMP:
8852 return ixgbe_ptp_get_ts_config(adapter, req);
e0f06bba
MR		 8853 case SIOCGMIIPHY:
8854 if (!adapter->hw.phy.ops.read_reg)
8855 return -EOPNOTSUPP;
5463fce6 8856 fallthrough;
3a6a4eda
JK		 8857 default:
8858 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8859 }
6b73e10d
BH		 8860}
8861
0365e6e4
PW		 8862/**
8863 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 8864 * netdev->dev_addrs
5ba643c6 8865 * @dev: network interface device structure
0365e6e4
PW		 8866 *
8867 * Returns non-zero on failure
8868 **/
8869static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8870{
8871 int err = 0;
8872 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 8873 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 8874
7fa7c9dc 8875 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 8876 rtnl_lock();
7fa7c9dc 8877 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 8878 rtnl_unlock();
7fa7c9dc
AD		 8879
8880 /* update SAN MAC vmdq pool selection */
8881 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 8882 }
8883 return err;
8884}
8885
8886/**
8887 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 8888 * netdev->dev_addrs
5ba643c6 8889 * @dev: network interface device structure
0365e6e4
PW		 8890 *
8891 * Returns non-zero on failure
8892 **/
8893static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8894{
8895 int err = 0;
8896 struct ixgbe_adapter *adapter = netdev_priv(dev);
8897 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8898
8899 if (is_valid_ether_addr(mac->san_addr)) {
8900 rtnl_lock();
8901 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8902 rtnl_unlock();
8903 }
8904 return err;
8905}
8906
33fdc82f
JF		 8907static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats,
8908 struct ixgbe_ring *ring)
8909{
8910 u64 bytes, packets;
8911 unsigned int start;
8912
8913 if (ring) {
8914 do {
8915 start = u64_stats_fetch_begin_irq(&ring->syncp);
8916 packets = ring->stats.packets;
8917 bytes = ring->stats.bytes;
8918 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8919 stats->tx_packets += packets;
8920 stats->tx_bytes += bytes;
8921 }
8922}
8923
bc1f4470 8924static void ixgbe_get_stats64(struct net_device *netdev,
8925 struct rtnl_link_stats64 *stats)
de1036b1
ED		 8926{
8927 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8928 int i;
8929
1a51502b 8930 rcu_read_lock();
de1036b1 8931 for (i = 0; i < adapter->num_rx_queues; i++) {
6aa7de05 8932 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 8933 u64 bytes, packets;
8934 unsigned int start;
8935
1a51502b
ED		 8936 if (ring) {
8937 do {
57a7744e 8938 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 8939 packets = ring->stats.packets;
8940 bytes = ring->stats.bytes;
57a7744e 8941 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 8942 stats->rx_packets += packets;
8943 stats->rx_bytes += bytes;
8944 }
de1036b1 8945 }
1ac9ad13
ED		 8946
8947 for (i = 0; i < adapter->num_tx_queues; i++) {
6aa7de05 8948 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]);
1ac9ad13 8949
33fdc82f
JF		 8950 ixgbe_get_ring_stats64(stats, ring);
8951 }
8952 for (i = 0; i < adapter->num_xdp_queues; i++) {
6aa7de05 8953 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]);
33fdc82f
JF		 8954
8955 ixgbe_get_ring_stats64(stats, ring);
1ac9ad13 8956 }
1a51502b 8957 rcu_read_unlock();
bc1f4470 8958
de1036b1
ED		 8959 /* following stats updated by ixgbe_watchdog_task() */
8960 stats->multicast = netdev->stats.multicast;
8961 stats->rx_errors = netdev->stats.rx_errors;
8962 stats->rx_length_errors = netdev->stats.rx_length_errors;
8963 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8964 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
de1036b1
ED		 8965}
8966
8af3c33f 8967#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 8968/**
8969 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8970 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 8971 * @tc: number of traffic classes currently enabled
8972 *
8973 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8974 * 802.1Q priority maps to a packet buffer that exists.
8975 */
8976static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8977{
8978 struct ixgbe_hw *hw = &adapter->hw;
8979 u32 reg, rsave;
8980 int i;
8981
8982 /* 82598 have a static priority to TC mapping that can not
8983 * be changed so no validation is needed.
8984 */
8985 if (hw->mac.type == ixgbe_mac_82598EB)
8986 return;
8987
8988 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8989 rsave = reg;
8990
8991 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8992 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8993
8994 /* If up2tc is out of bounds default to zero */
8995 if (up2tc > tc)
8996 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8997 }
8998
8999 if (reg != rsave)
9000 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
9001
9002 return;
9003}
9004
02debdc9
AD		 9005/**
9006 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
9007 * @adapter: Pointer to adapter struct
9008 *
9009 * Populate the netdev user priority to tc map
9010 */
9011static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
9012{
9013 struct net_device *dev = adapter->netdev;
9014 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
9015 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
9016 u8 prio;
9017
9018 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
9019 u8 tc = 0;
9020
9021 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
9022 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
9023 else if (ets)
9024 tc = ets->prio_tc[prio];
9025
9026 netdev_set_prio_tc_map(dev, prio, tc);
9027 }
9028}
9029
cca73c59 9030#endif /* CONFIG_IXGBE_DCB */
eff74233
TY		 9031static int ixgbe_reassign_macvlan_pool(struct net_device *vdev,
9032 struct netdev_nested_priv *priv)
8315ef6f 9033{
eff74233 9034 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
8315ef6f
AD		 9035 struct ixgbe_fwd_adapter *accel;
9036 int pool;
9037
9038 /* we only care about macvlans... */
9039 if (!netif_is_macvlan(vdev))
9040 return 0;
9041
9042 /* that have hardware offload enabled... */
9043 accel = macvlan_accel_priv(vdev);
9044 if (!accel)
9045 return 0;
9046
9047 /* If we can relocate to a different bit do so */
9048 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9049 if (pool < adapter->num_rx_pools) {
9050 set_bit(pool, adapter->fwd_bitmask);
9051 accel->pool = pool;
9052 return 0;
9053 }
9054
9055 /* if we cannot find a free pool then disable the offload */
9056 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n");
9057 macvlan_release_l2fw_offload(vdev);
58b0b3ed
AD		 9058
9059 /* unbind the queues and drop the subordinate channel config */
9060 netdev_unbind_sb_channel(adapter->netdev, vdev);
9061 netdev_set_sb_channel(vdev, 0);
9062
8315ef6f
AD		 9063 kfree(accel);
9064
9065 return 0;
9066}
9067
9068static void ixgbe_defrag_macvlan_pools(struct net_device *dev)
9069{
9070 struct ixgbe_adapter *adapter = netdev_priv(dev);
eff74233
TY		 9071 struct netdev_nested_priv priv = {
9072 .data = (void *)adapter,
9073 };
8315ef6f
AD		 9074
9075 /* flush any stale bits out of the fwd bitmask */
9076 bitmap_clear(adapter->fwd_bitmask, 1, 63);
9077
9078 /* walk through upper devices reassigning pools */
9079 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool,
eff74233 9080 &priv);
8315ef6f
AD		 9081}
9082
49ce9c2c
BH		 9083/**
9084 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24 9085 *
5ba643c6 9086 * @dev: net device to configure
8b1c0b24
JF		 9087 * @tc: number of traffic classes to enable
9088 */
9089int ixgbe_setup_tc(struct net_device *dev, u8 tc)
9090{
8b1c0b24
JF		 9091 struct ixgbe_adapter *adapter = netdev_priv(dev);
9092 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 9093
8b1c0b24 9094 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 9095 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
9096 return -EINVAL;
9097
9098 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 9099 return -EINVAL;
9100
9101 /* Hardware has to reinitialize queues and interrupts to
52f33af8 9102 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 9103 * hardware is not flexible enough to do this dynamically.
9104 */
9105 if (netif_running(dev))
9106 ixgbe_close(dev);
bf4d67d9
AD		 9107 else
9108 ixgbe_reset(adapter);
9109
8b1c0b24
JF		 9110 ixgbe_clear_interrupt_scheme(adapter);
9111
cca73c59 9112#ifdef CONFIG_IXGBE_DCB
e7589eab 9113 if (tc) {
fabf1bce
TN		 9114 if (adapter->xdp_prog) {
9115 e_warn(probe, "DCB is not supported with XDP\n");
9116
9117 ixgbe_init_interrupt_scheme(adapter);
9118 if (netif_running(dev))
9119 ixgbe_open(dev);
9120 return -EINVAL;
9121 }
9122
8b1c0b24 9123 netdev_set_num_tc(dev, tc);
02debdc9
AD		 9124 ixgbe_set_prio_tc_map(adapter);
9125
0efbf12b 9126 adapter->hw_tcs = tc;
e7589eab 9127 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 9128
943561d3
AD		 9129 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
9130 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 9131 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 9132 }
e7589eab 9133 } else {
8b1c0b24 9134 netdev_reset_tc(dev);
02debdc9 9135
943561d3
AD		 9136 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9137 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 9138
9139 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
0efbf12b 9140 adapter->hw_tcs = tc;
e7589eab
JF		 9141
9142 adapter->temp_dcb_cfg.pfc_mode_enable = false;
9143 adapter->dcb_cfg.pfc_mode_enable = false;
9144 }
9145
8b1c0b24 9146 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 9147
9148#endif /* CONFIG_IXGBE_DCB */
9149 ixgbe_init_interrupt_scheme(adapter);
9150
8315ef6f
AD		 9151 ixgbe_defrag_macvlan_pools(dev);
9152
8b1c0b24 9153 if (netif_running(dev))
cca73c59 9154 return ixgbe_open(dev);
8b1c0b24
JF		 9155
9156 return 0;
9157}
de1036b1 9158
b82b17d9
JF		 9159static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
9160 struct tc_cls_u32_offload *cls)
9161{
1ecedc92 9162 u32 hdl = cls->knode.handle;
176621c9 9163 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
1ecedc92
AN		 9164 u32 loc = cls->knode.handle & 0xfffff;
9165 int err = 0, i, j;
9166 struct ixgbe_jump_table *jump = NULL;
9167
9168 if (loc > IXGBE_MAX_HW_ENTRIES)
9169 return -EINVAL;
b82b17d9 9170
176621c9
SS		 9171 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
9172 return -EINVAL;
9173
1ecedc92
AN		 9174 /* Clear this filter in the link data it is associated with */
9175 if (uhtid != 0x800) {
9176 jump = adapter->jump_tables[uhtid];
12746fd2
AN		 9177 if (!jump)
9178 return -EINVAL;
9179 if (!test_bit(loc - 1, jump->child_loc_map))
9180 return -EINVAL;
9181 clear_bit(loc - 1, jump->child_loc_map);
1ecedc92
AN		 9182 }
9183
9184 /* Check if the filter being deleted is a link */
9185 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9186 jump = adapter->jump_tables[i];
9187 if (jump && jump->link_hdl == hdl) {
9188 /* Delete filters in the hardware in the child hash
9189 * table associated with this link
9190 */
9191 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
9192 if (!test_bit(j, jump->child_loc_map))
9193 continue;
9194 spin_lock(&adapter->fdir_perfect_lock);
9195 err = ixgbe_update_ethtool_fdir_entry(adapter,
9196 NULL,
9197 j + 1);
9198 spin_unlock(&adapter->fdir_perfect_lock);
9199 clear_bit(j, jump->child_loc_map);
9200 }
9201 /* Remove resources for this link */
9202 kfree(jump->input);
9203 kfree(jump->mask);
9204 kfree(jump);
9205 adapter->jump_tables[i] = NULL;
9206 return err;
9207 }
9208 }
176621c9 9209
b82b17d9 9210 spin_lock(&adapter->fdir_perfect_lock);
176621c9 9211 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
b82b17d9
JF		 9212 spin_unlock(&adapter->fdir_perfect_lock);
9213 return err;
9214}
9215
db956ae8 9216static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
db956ae8
JF		 9217 struct tc_cls_u32_offload *cls)
9218{
176621c9
SS		 9219 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9220
9221 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9222 return -EINVAL;
9223
db956ae8
JF		 9224 /* This ixgbe devices do not support hash tables at the moment
9225 * so abort when given hash tables.
9226 */
9227 if (cls->hnode.divisor > 0)
9228 return -EINVAL;
9229
176621c9 9230 set_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 9231 return 0;
9232}
9233
9234static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
9235 struct tc_cls_u32_offload *cls)
9236{
176621c9
SS		 9237 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9238
9239 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9240 return -EINVAL;
9241
9242 clear_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 9243 return 0;
9244}
9245
947f8a45 9246#ifdef CONFIG_NET_CLS_ACT
1cd127fc
DA		 9247struct upper_walk_data {
9248 struct ixgbe_adapter *adapter;
9249 u64 action;
9250 int ifindex;
9251 u8 queue;
9252};
9253
eff74233
TY		 9254static int get_macvlan_queue(struct net_device *upper,
9255 struct netdev_nested_priv *priv)
1cd127fc
DA		 9256{
9257 if (netif_is_macvlan(upper)) {
7d775f63 9258 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper);
eff74233
TY		 9259 struct ixgbe_adapter *adapter;
9260 struct upper_walk_data *data;
9261 int ifindex;
1cd127fc 9262
eff74233
TY		 9263 data = (struct upper_walk_data *)priv->data;
9264 ifindex = data->ifindex;
9265 adapter = data->adapter;
7d775f63 9266 if (vadapter && upper->ifindex == ifindex) {
1cd127fc
DA		 9267 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
9268 data->action = data->queue;
9269 return 1;
9270 }
9271 }
9272
9273 return 0;
9274}
9275
947f8a45
SS		 9276static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
9277 u8 *queue, u64 *action)
9278{
361b5343 9279 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
947f8a45 9280 unsigned int num_vfs = adapter->num_vfs, vf;
eff74233 9281 struct netdev_nested_priv priv;
1cd127fc 9282 struct upper_walk_data data;
947f8a45 9283 struct net_device *upper;
947f8a45
SS		 9284
9285 /* redirect to a SRIOV VF */
9286 for (vf = 0; vf < num_vfs; ++vf) {
9287 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
9288 if (upper->ifindex == ifindex) {
361b5343 9289 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask);
947f8a45
SS		 9290 *action = vf + 1;
9291 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
9292 return 0;
9293 }
9294 }
9295
9296 /* redirect to a offloaded macvlan netdev */
1cd127fc
DA		 9297 data.adapter = adapter;
9298 data.ifindex = ifindex;
9299 data.action = 0;
9300 data.queue = 0;
eff74233 9301 priv.data = (void *)&data;
1cd127fc 9302 if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
eff74233 9303 get_macvlan_queue, &priv)) {
1cd127fc
DA		 9304 *action = data.action;
9305 *queue = data.queue;
9306
9307 return 0;
947f8a45
SS		 9308 }
9309
9310 return -EINVAL;
9311}
9312
9313static int parse_tc_actions(struct ixgbe_adapter *adapter,
9314 struct tcf_exts *exts, u64 *action, u8 *queue)
9315{
9316 const struct tc_action *a;
244cd96a 9317 int i;
947f8a45 9318
3bcc0cec 9319 if (!tcf_exts_has_actions(exts))
947f8a45
SS		 9320 return -EINVAL;
9321
244cd96a 9322 tcf_exts_for_each_action(i, a, exts) {
947f8a45
SS		 9323 /* Drop action */
9324 if (is_tcf_gact_shot(a)) {
9325 *action = IXGBE_FDIR_DROP_QUEUE;
9326 *queue = IXGBE_FDIR_DROP_QUEUE;
9327 return 0;
9328 }
9329
9330 /* Redirect to a VF or a offloaded macvlan */
5724b8b5 9331 if (is_tcf_mirred_egress_redirect(a)) {
9f8a739e 9332 struct net_device *dev = tcf_mirred_dev(a);
947f8a45 9333
9f8a739e
CW		 9334 if (!dev)
9335 return -EINVAL;
16e6653c
OH		 9336 return handle_redirect_action(adapter, dev->ifindex,
9337 queue, action);
947f8a45 9338 }
16e6653c
OH		 9339
9340 return -EINVAL;
947f8a45
SS		 9341 }
9342
9343 return -EINVAL;
9344}
9345#else
9346static int parse_tc_actions(struct ixgbe_adapter *adapter,
9347 struct tcf_exts *exts, u64 *action, u8 *queue)
9348{
9349 return -EINVAL;
9350}
9351#endif /* CONFIG_NET_CLS_ACT */
9352
1cdaaf54
AN		 9353static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
9354 union ixgbe_atr_input *mask,
9355 struct tc_cls_u32_offload *cls,
9356 struct ixgbe_mat_field *field_ptr,
9357 struct ixgbe_nexthdr *nexthdr)
9358{
9359 int i, j, off;
9360 __be32 val, m;
9361 bool found_entry = false, found_jump_field = false;
9362
9363 for (i = 0; i < cls->knode.sel->nkeys; i++) {
9364 off = cls->knode.sel->keys[i].off;
9365 val = cls->knode.sel->keys[i].val;
9366 m = cls->knode.sel->keys[i].mask;
9367
9368 for (j = 0; field_ptr[j].val; j++) {
9369 if (field_ptr[j].off == off) {
9cfbfa70
CZ		 9370 field_ptr[j].val(input, mask, (__force u32)val,
9371 (__force u32)m);
1cdaaf54
AN		 9372 input->filter.formatted.flow_type |=
9373 field_ptr[j].type;
9374 found_entry = true;
9375 break;
9376 }
9377 }
9378 if (nexthdr) {
9379 if (nexthdr->off == cls->knode.sel->keys[i].off &&
9cfbfa70
CZ		 9380 nexthdr->val ==
9381 (__force u32)cls->knode.sel->keys[i].val &&
9382 nexthdr->mask ==
9383 (__force u32)cls->knode.sel->keys[i].mask)
1cdaaf54
AN		 9384 found_jump_field = true;
9385 else
9386 continue;
9387 }
9388 }
9389
9390 if (nexthdr && !found_jump_field)
9391 return -EINVAL;
9392
9393 if (!found_entry)
9394 return 0;
9395
9396 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
9397 IXGBE_ATR_L4TYPE_MASK;
9398
9399 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
9400 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
9401
9402 return 0;
9403}
9404
b82b17d9 9405static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
b82b17d9
JF		 9406 struct tc_cls_u32_offload *cls)
9407{
5fd9fc4e 9408 __be16 protocol = cls->common.protocol;
b82b17d9
JF		 9409 u32 loc = cls->knode.handle & 0xfffff;
9410 struct ixgbe_hw *hw = &adapter->hw;
9411 struct ixgbe_mat_field *field_ptr;
1cdaaf54
AN		 9412 struct ixgbe_fdir_filter *input = NULL;
9413 union ixgbe_atr_input *mask = NULL;
9414 struct ixgbe_jump_table *jump = NULL;
9415 int i, err = -EINVAL;
b82b17d9 9416 u8 queue;
176621c9 9417 u32 uhtid, link_uhtid;
b82b17d9 9418
176621c9
SS		 9419 uhtid = TC_U32_USERHTID(cls->knode.handle);
9420 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
b82b17d9 9421
176621c9 9422 /* At the moment cls_u32 jumps to network layer and skips past
b82b17d9
JF		 9423 * L2 headers. The canonical method to match L2 frames is to use
9424 * negative values. However this is error prone at best but really
9425 * just broken because there is no way to "know" what sort of hdr
176621c9 9426 * is in front of the network layer. Fix cls_u32 to support L2
b82b17d9
JF		 9427 * headers when needed.
9428 */
9429 if (protocol != htons(ETH_P_IP))
1cdaaf54 9430 return err;
b82b17d9
JF		 9431
9432 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
9433 e_err(drv, "Location out of range\n");
1cdaaf54 9434 return err;
b82b17d9
JF		 9435 }
9436
9437 /* cls u32 is a graph starting at root node 0x800. The driver tracks
9438 * links and also the fields used to advance the parser across each
9439 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
9440 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
9441 * To add support for new nodes update ixgbe_model.h parse structures
9442 * this function _should_ be generic try not to hardcode values here.
9443 */
176621c9 9444 if (uhtid == 0x800) {
1cdaaf54 9445 field_ptr = (adapter->jump_tables[0])->mat;
b82b17d9 9446 } else {
176621c9 9447 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
1cdaaf54
AN		 9448 return err;
9449 if (!adapter->jump_tables[uhtid])
9450 return err;
9451 field_ptr = (adapter->jump_tables[uhtid])->mat;
b82b17d9
JF		 9452 }
9453
9454 if (!field_ptr)
1cdaaf54 9455 return err;
b82b17d9 9456
1cdaaf54
AN		 9457 /* At this point we know the field_ptr is valid and need to either
9458 * build cls_u32 link or attach filter. Because adding a link to
9459 * a handle that does not exist is invalid and the same for adding
9460 * rules to handles that don't exist.
9461 */
b82b17d9 9462
1cdaaf54
AN		 9463 if (link_uhtid) {
9464 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
b82b17d9 9465
1cdaaf54
AN		 9466 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
9467 return err;
9468
9469 if (!test_bit(link_uhtid - 1, &adapter->tables))
9470 return err;
9471
1ecedc92
AN		 9472 /* Multiple filters as links to the same hash table are not
9473 * supported. To add a new filter with the same next header
9474 * but different match/jump conditions, create a new hash table
9475 * and link to it.
9476 */
9477 if (adapter->jump_tables[link_uhtid] &&
9478 (adapter->jump_tables[link_uhtid])->link_hdl) {
9479 e_err(drv, "Link filter exists for link: %x\n",
9480 link_uhtid);
9481 return err;
9482 }
9483
1cdaaf54
AN		 9484 for (i = 0; nexthdr[i].jump; i++) {
9485 if (nexthdr[i].o != cls->knode.sel->offoff ||
9486 nexthdr[i].s != cls->knode.sel->offshift ||
9cfbfa70
CZ		 9487 nexthdr[i].m !=
9488 (__force u32)cls->knode.sel->offmask)
1cdaaf54
AN		 9489 return err;
9490
9491 jump = kzalloc(sizeof(*jump), GFP_KERNEL);
9492 if (!jump)
9493 return -ENOMEM;
9494 input = kzalloc(sizeof(*input), GFP_KERNEL);
9495 if (!input) {
9496 err = -ENOMEM;
9497 goto free_jump;
9498 }
9499 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9500 if (!mask) {
9501 err = -ENOMEM;
12746fd2 9502 goto free_input;
1cdaaf54
AN		 9503 }
9504 jump->input = input;
9505 jump->mask = mask;
1ecedc92
AN		 9506 jump->link_hdl = cls->knode.handle;
9507
1cdaaf54
AN		 9508 err = ixgbe_clsu32_build_input(input, mask, cls,
9509 field_ptr, &nexthdr[i]);
9510 if (!err) {
9511 jump->mat = nexthdr[i].jump;
9512 adapter->jump_tables[link_uhtid] = jump;
b82b17d9 9513 break;
22d11eac
WW		 9514 } else {
9515 kfree(mask);
9516 kfree(input);
9517 kfree(jump);
b82b17d9
JF		 9518 }
9519 }
1cdaaf54 9520 return 0;
b82b17d9
JF		 9521 }
9522
1cdaaf54
AN		 9523 input = kzalloc(sizeof(*input), GFP_KERNEL);
9524 if (!input)
9525 return -ENOMEM;
9526 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9527 if (!mask) {
9528 err = -ENOMEM;
12746fd2 9529 goto free_input;
1cdaaf54 9530 }
b82b17d9 9531
1cdaaf54
AN		 9532 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
9533 if ((adapter->jump_tables[uhtid])->input)
9534 memcpy(input, (adapter->jump_tables[uhtid])->input,
9535 sizeof(*input));
9536 if ((adapter->jump_tables[uhtid])->mask)
9537 memcpy(mask, (adapter->jump_tables[uhtid])->mask,
9538 sizeof(*mask));
12746fd2
AN		 9539
9540 /* Lookup in all child hash tables if this location is already
9541 * filled with a filter
9542 */
9543 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9544 struct ixgbe_jump_table *link = adapter->jump_tables[i];
9545
9546 if (link && (test_bit(loc - 1, link->child_loc_map))) {
9547 e_err(drv, "Filter exists in location: %x\n",
9548 loc);
9549 err = -EINVAL;
9550 goto err_out;
9551 }
9552 }
1cdaaf54
AN		 9553 }
9554 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
9555 if (err)
b82b17d9
JF		 9556 goto err_out;
9557
947f8a45
SS		 9558 err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
9559 &queue);
9560 if (err < 0)
b82b17d9 9561 goto err_out;
b82b17d9 9562
b82b17d9
JF		 9563 input->sw_idx = loc;
9564
9565 spin_lock(&adapter->fdir_perfect_lock);
9566
9567 if (hlist_empty(&adapter->fdir_filter_list)) {
1cdaaf54
AN		 9568 memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
9569 err = ixgbe_fdir_set_input_mask_82599(hw, mask);
b82b17d9
JF		 9570 if (err)
9571 goto err_out_w_lock;
1cdaaf54 9572 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
b82b17d9
JF		 9573 err = -EINVAL;
9574 goto err_out_w_lock;
9575 }
9576
1cdaaf54 9577 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
b82b17d9
JF		 9578 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
9579 input->sw_idx, queue);
7a766381
DL		 9580 if (err)
9581 goto err_out_w_lock;
9582
9583 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
b82b17d9
JF		 9584 spin_unlock(&adapter->fdir_perfect_lock);
9585
12746fd2
AN		 9586 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
9587 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
1ecedc92 9588
1cdaaf54 9589 kfree(mask);
b82b17d9
JF		 9590 return err;
9591err_out_w_lock:
9592 spin_unlock(&adapter->fdir_perfect_lock);
9593err_out:
1ecedc92 9594 kfree(mask);
12746fd2
AN		 9595free_input:
9596 kfree(input);
1cdaaf54
AN		 9597free_jump:
9598 kfree(jump);
9599 return err;
b82b17d9
JF		 9600}
9601
6ea30f8a 9602static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter,
bc32afdb 9603 struct tc_cls_u32_offload *cls_u32)
e4c6734e 9604{
bc32afdb
JP		 9605 switch (cls_u32->command) {
9606 case TC_CLSU32_NEW_KNODE:
9607 case TC_CLSU32_REPLACE_KNODE:
5fd9fc4e 9608 return ixgbe_configure_clsu32(adapter, cls_u32);
bc32afdb
JP		 9609 case TC_CLSU32_DELETE_KNODE:
9610 return ixgbe_delete_clsu32(adapter, cls_u32);
9611 case TC_CLSU32_NEW_HNODE:
9612 case TC_CLSU32_REPLACE_HNODE:
5fd9fc4e 9613 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32);
bc32afdb
JP		 9614 case TC_CLSU32_DELETE_HNODE:
9615 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32);
9616 default:
9617 return -EOPNOTSUPP;
b82b17d9 9618 }
bc32afdb 9619}
b82b17d9 9620
6ea30f8a
JP		 9621static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9622 void *cb_priv)
9623{
9624 struct ixgbe_adapter *adapter = cb_priv;
9625
a60c3fd6 9626 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
44ae12a7
JP		 9627 return -EOPNOTSUPP;
9628
6ea30f8a
JP		 9629 switch (type) {
9630 case TC_SETUP_CLSU32:
9631 return ixgbe_setup_tc_cls_u32(adapter, type_data);
9632 default:
9633 return -EOPNOTSUPP;
9634 }
9635}
9636
bc32afdb
JP		 9637static int ixgbe_setup_tc_mqprio(struct net_device *dev,
9638 struct tc_mqprio_qopt *mqprio)
9639{
9640 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9641 return ixgbe_setup_tc(dev, mqprio->num_tc);
9642}
56f36acd 9643
955bcb6e
PNA		 9644static LIST_HEAD(ixgbe_block_cb_list);
9645
bc32afdb 9646static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 9647 void *type_data)
bc32afdb 9648{
4e95bc26
PNA		 9649 struct ixgbe_adapter *adapter = netdev_priv(dev);
9650
bc32afdb 9651 switch (type) {
6ea30f8a 9652 case TC_SETUP_BLOCK:
955bcb6e
PNA		 9653 return flow_block_cb_setup_simple(type_data,
9654 &ixgbe_block_cb_list,
4e95bc26
PNA		 9655 ixgbe_setup_tc_block_cb,
9656 adapter, adapter, true);
575ed7d3 9657 case TC_SETUP_QDISC_MQPRIO:
de4784ca 9658 return ixgbe_setup_tc_mqprio(dev, type_data);
bc32afdb
JP		 9659 default:
9660 return -EOPNOTSUPP;
9661 }
e4c6734e
JF		 9662}
9663
da36b647
GR		 9664#ifdef CONFIG_PCI_IOV
9665void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
9666{
9667 struct net_device *netdev = adapter->netdev;
9668
9669 rtnl_lock();
0efbf12b 9670 ixgbe_setup_tc(netdev, adapter->hw_tcs);
da36b647
GR		 9671 rtnl_unlock();
9672}
9673
9674#endif
082757af
DS		 9675void ixgbe_do_reset(struct net_device *netdev)
9676{
9677 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9678
9679 if (netif_running(netdev))
9680 ixgbe_reinit_locked(adapter);
9681 else
9682 ixgbe_reset(adapter);
9683}
9684
c8f44aff 9685static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 9686 netdev_features_t features)
082757af
DS		 9687{
9688 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9689
082757af 9690 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 9691 if (!(features & NETIF_F_RXCSUM))
9692 features &= ~NETIF_F_LRO;
082757af 9693
567d2de2
AD		 9694 /* Turn off LRO if not RSC capable */
9695 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
9696 features &= ~NETIF_F_LRO;
8e2813f5 9697
38b7e7f8
TN		 9698 if (adapter->xdp_prog && (features & NETIF_F_LRO)) {
9699 e_dev_err("LRO is not supported with XDP\n");
9700 features &= ~NETIF_F_LRO;
9701 }
9702
567d2de2 9703 return features;
082757af
DS		 9704}
9705
8315ef6f
AD		 9706static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter)
9707{
9708 int rss = min_t(int, ixgbe_max_rss_indices(adapter),
9709 num_online_cpus());
9710
9711 /* go back to full RSS if we're not running SR-IOV */
9712 if (!adapter->ring_feature[RING_F_VMDQ].offset)
9713 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED |
9714 IXGBE_FLAG_SRIOV_ENABLED);
9715
9716 adapter->ring_feature[RING_F_RSS].limit = rss;
9717 adapter->ring_feature[RING_F_VMDQ].limit = 1;
9718
9719 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs);
9720}
9721
c8f44aff 9722static int ixgbe_set_features(struct net_device *netdev,
567d2de2 9723 netdev_features_t features)
082757af
DS		 9724{
9725 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 9726 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 9727 bool need_reset = false;
9728
082757af 9729 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 9730 if (!(features & NETIF_F_LRO)) {
9731 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 9732 need_reset = true;
567d2de2
AD		 9733 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
9734 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
9735 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
9736 if (adapter->rx_itr_setting == 1 ||
9737 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
9738 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9739 need_reset = true;
9740 } else if ((changed ^ features) & NETIF_F_LRO) {
9741 e_info(probe, "rx-usecs set too low, "
9742 "disabling RSC\n");
082757af
DS		 9743 }
9744 }
9745
9746 /*
b82b17d9
JF		 9747 * Check if Flow Director n-tuple support or hw_tc support was
9748 * enabled or disabled. If the state changed, we need to reset.
082757af 9749 */
b82b17d9 9750 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
567d2de2 9751 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 9752 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
9753 need_reset = true;
9754
567d2de2
AD		 9755 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
9756 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
b82b17d9 9757 } else {
39cb681b
AD		 9758 /* turn off perfect filters, enable ATR and reset */
9759 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
9760 need_reset = true;
9761
9762 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9763
9764 /* We cannot enable ATR if SR-IOV is enabled */
b82b17d9
JF		 9765 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
9766 /* We cannot enable ATR if we have 2 or more tcs */
0efbf12b 9767 (adapter->hw_tcs > 1) ||
b82b17d9
JF		 9768 /* We cannot enable ATR if RSS is disabled */
9769 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
9770 /* A sample rate of 0 indicates ATR disabled */
9771 (!adapter->atr_sample_rate))
9772 ; /* do nothing not supported */
9773 else /* otherwise supported and set the flag */
9774 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 9775 }
9776
3f2d1c0f
BG		 9777 if (changed & NETIF_F_RXALL)
9778 need_reset = true;
9779
567d2de2 9780 netdev->features = features;
67359c3c 9781
8315ef6f
AD		 9782 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1)
9783 ixgbe_reset_l2fw_offload(adapter);
9784 else if (need_reset)
082757af 9785 ixgbe_do_reset(netdev);
0c5a6166
AD		 9786 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
9787 NETIF_F_HW_VLAN_CTAG_FILTER))
9788 ixgbe_set_rx_mode(netdev);
082757af 9789
b0ddfe2b 9790 return 1;
082757af
DS		 9791}
9792
edc7d573 9793static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 9794 struct net_device *dev,
f6f6424b 9795 const unsigned char *addr, u16 vid,
87b0984e
PM		 9796 u16 flags,
9797 struct netlink_ext_ack *extack)
0f4b0add 9798{
bcfd3432 9799 /* guarantee we can provide a unique filter for the unicast address */
46acc460 9800 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2f9be166
AD		 9801 struct ixgbe_adapter *adapter = netdev_priv(dev);
9802 u16 pool = VMDQ_P(0);
9803
9804 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
bcfd3432 9805 return -ENOMEM;
0f4b0add
JF		 9806 }
9807
f6f6424b 9808 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 9809}
9810
219efe97
DS		 9811/**
9812 * ixgbe_configure_bridge_mode - set various bridge modes
5ba643c6
TN		 9813 * @adapter: the private structure
9814 * @mode: requested bridge mode
219efe97
DS		 9815 *
9816 * Configure some settings require for various bridge modes.
9817 **/
9818static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9819 __u16 mode)
9820{
6d4c96ad
DS		 9821 struct ixgbe_hw *hw = &adapter->hw;
9822 unsigned int p, num_pools;
9823 u32 vmdctl;
9824
219efe97
DS		 9825 switch (mode) {
9826 case BRIDGE_MODE_VEPA:
6d4c96ad 9827 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 9828 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 9829
9830 /* must enable Rx switching replication to allow multicast
9831 * packet reception on all VFs, and to enable source address
9832 * pruning.
9833 */
9834 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9835 vmdctl |= IXGBE_VT_CTL_REPLEN;
9836 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9837
9838 /* enable Rx source address pruning. Note, this requires
9839 * replication to be enabled or else it does nothing.
9840 */
9841 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9842 for (p = 0; p < num_pools; p++) {
9843 if (hw->mac.ops.set_source_address_pruning)
9844 hw->mac.ops.set_source_address_pruning(hw,
9845 true,
9846 p);
9847 }
219efe97
DS		 9848 break;
9849 case BRIDGE_MODE_VEB:
6d4c96ad 9850 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 9851 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
9852 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 9853
9854 /* disable Rx switching replication unless we have SR-IOV
9855 * virtual functions
9856 */
9857 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9858 if (!adapter->num_vfs)
9859 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
9860 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9861
9862 /* disable Rx source address pruning, since we don't expect to
9863 * be receiving external loopback of our transmitted frames.
9864 */
9865 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9866 for (p = 0; p < num_pools; p++) {
9867 if (hw->mac.ops.set_source_address_pruning)
9868 hw->mac.ops.set_source_address_pruning(hw,
9869 false,
9870 p);
9871 }
219efe97
DS		 9872 break;
9873 default:
9874 return -EINVAL;
9875 }
9876
9877 adapter->bridge_mode = mode;
9878
9879 e_info(drv, "enabling bridge mode: %s\n",
9880 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
9881
9882 return 0;
9883}
9884
815cccbf 9885static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
2fd527b7
PM		 9886 struct nlmsghdr *nlh, u16 flags,
9887 struct netlink_ext_ack *extack)
815cccbf
JF		 9888{
9889 struct ixgbe_adapter *adapter = netdev_priv(dev);
9890 struct nlattr *attr, *br_spec;
9891 int rem;
9892
9893 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9894 return -EOPNOTSUPP;
9895
9896 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 9897 if (!br_spec)
9898 return -EINVAL;
815cccbf
JF		 9899
9900 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 9901 int status;
815cccbf 9902 __u16 mode;
815cccbf
JF		 9903
9904 if (nla_type(attr) != IFLA_BRIDGE_MODE)
9905 continue;
9906
b7c1a314
TG		 9907 if (nla_len(attr) < sizeof(mode))
9908 return -EINVAL;
9909
815cccbf 9910 mode = nla_get_u16(attr);
219efe97
DS		 9911 status = ixgbe_configure_bridge_mode(adapter, mode);
9912 if (status)
9913 return status;
aa2bacb6
DS		 9914
9915 break;
815cccbf
JF		 9916 }
9917
9918 return 0;
9919}
9920
9921static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 9922 struct net_device *dev,
46c264da 9923 u32 filter_mask, int nlflags)
815cccbf
JF		 9924{
9925 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 9926
9927 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9928 return 0;
9929
aa2bacb6 9930 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 9931 adapter->bridge_mode, 0, 0, nlflags,
9932 filter_mask, NULL);
815cccbf
JF		 9933}
9934
2a47fa45
JF		 9935static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
9936{
2a47fa45 9937 struct ixgbe_adapter *adapter = netdev_priv(pdev);
8315ef6f 9938 struct ixgbe_fwd_adapter *accel;
0efbf12b 9939 int tcs = adapter->hw_tcs ? : 1;
2a47fa45
JF		 9940 int pool, err;
9941
fabf1bce
TN		 9942 if (adapter->xdp_prog) {
9943 e_warn(probe, "L2FW offload is not supported with XDP\n");
9944 return ERR_PTR(-EINVAL);
9945 }
9946
3335915d
AD		 9947 /* The hardware supported by ixgbe only filters on the destination MAC
9948 * address. In order to avoid issues we only support offloading modes
9949 * where the hardware can actually provide the functionality.
9950 */
9951 if (!macvlan_supports_dest_filter(vdev))
9952 return ERR_PTR(-EMEDIUMTYPE);
9953
58b0b3ed
AD		 9954 /* We need to lock down the macvlan to be a single queue device so that
9955 * we can reuse the tc_to_txq field in the macvlan netdev to represent
9956 * the queue mapping to our netdev.
9957 */
9958 if (netif_is_multiqueue(vdev))
9959 return ERR_PTR(-ERANGE);
9960
8315ef6f
AD		 9961 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9962 if (pool == adapter->num_rx_pools) {
9963 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools;
9964 u16 reserved_pools;
9965
9966 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
9967 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) ||
9968 adapter->num_rx_pools > IXGBE_MAX_MACVLANS)
9969 return ERR_PTR(-EBUSY);
9970
9971 /* Hardware has a limited number of available pools. Each VF,
9972 * and the PF require a pool. Check to ensure we don't
9973 * attempt to use more then the available number of pools.
9974 */
9975 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
9976 return ERR_PTR(-EBUSY);
aac2f1bf 9977
8315ef6f
AD		 9978 /* Enable VMDq flag so device will be set in VM mode */
9979 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED |
9980 IXGBE_FLAG_SRIOV_ENABLED;
2a47fa45 9981
8315ef6f
AD		 9982 /* Try to reserve as many queues per pool as possible,
9983 * we start with the configurations that support 4 queues
9984 * per pools, followed by 2, and then by just 1 per pool.
9985 */
9986 if (used_pools < 32 && adapter->num_rx_pools < 16)
9987 reserved_pools = min_t(u16,
9988 32 - used_pools,
9989 16 - adapter->num_rx_pools);
9990 else if (adapter->num_rx_pools < 32)
9991 reserved_pools = min_t(u16,
9992 64 - used_pools,
9993 32 - adapter->num_rx_pools);
9994 else
9995 reserved_pools = 64 - used_pools;
2a47fa45 9996
2a47fa45 9997
8315ef6f
AD		 9998 if (!reserved_pools)
9999 return ERR_PTR(-EBUSY);
2a47fa45 10000
8315ef6f 10001 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools;
a3b8cb1f 10002
8315ef6f
AD		 10003 /* Force reinit of ring allocation with VMDQ enabled */
10004 err = ixgbe_setup_tc(pdev, adapter->hw_tcs);
10005 if (err)
10006 return ERR_PTR(err);
16be45bc 10007
8315ef6f
AD		 10008 if (pool >= adapter->num_rx_pools)
10009 return ERR_PTR(-ENOMEM);
10010 }
a3b8cb1f 10011
8315ef6f
AD		 10012 accel = kzalloc(sizeof(*accel), GFP_KERNEL);
10013 if (!accel)
10014 return ERR_PTR(-ENOMEM);
10015
10016 set_bit(pool, adapter->fwd_bitmask);
58b0b3ed 10017 netdev_set_sb_channel(vdev, pool);
8315ef6f
AD		 10018 accel->pool = pool;
10019 accel->netdev = vdev;
16be45bc 10020
8315ef6f
AD		 10021 if (!netif_running(pdev))
10022 return accel;
10023
10024 err = ixgbe_fwd_ring_up(adapter, accel);
10025 if (err)
10026 return ERR_PTR(err);
10027
10028 return accel;
2a47fa45
JF		 10029}
10030
10031static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
10032{
b5f69ccf 10033 struct ixgbe_fwd_adapter *accel = priv;
865255b5 10034 struct ixgbe_adapter *adapter = netdev_priv(pdev);
b5f69ccf 10035 unsigned int rxbase = accel->rx_base_queue;
8315ef6f 10036 unsigned int i;
2a47fa45 10037
b5f69ccf
AD		 10038 /* delete unicast filter associated with offloaded interface */
10039 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr,
10040 VMDQ_P(accel->pool));
2a47fa45 10041
b5f69ccf
AD		 10042 /* Allow remaining Rx packets to get flushed out of the
10043 * Rx FIFO before we drop the netdev for the ring.
10044 */
10045 usleep_range(10000, 20000);
10046
10047 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
10048 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i];
10049 struct ixgbe_q_vector *qv = ring->q_vector;
10050
10051 /* Make sure we aren't processing any packets and clear
10052 * netdev to shut down the ring.
10053 */
10054 if (netif_running(adapter->netdev))
10055 napi_synchronize(&qv->napi);
10056 ring->netdev = NULL;
10057 }
10058
58b0b3ed
AD		 10059 /* unbind the queues and drop the subordinate channel config */
10060 netdev_unbind_sb_channel(pdev, accel->netdev);
10061 netdev_set_sb_channel(accel->netdev, 0);
10062
b5f69ccf 10063 clear_bit(accel->pool, adapter->fwd_bitmask);
b5f69ccf 10064 kfree(accel);
2a47fa45
JF		 10065}
10066
b83e3010
AD		 10067#define IXGBE_MAX_MAC_HDR_LEN 127
10068#define IXGBE_MAX_NETWORK_HDR_LEN 511
10069
f467bc06
MR		 10070static netdev_features_t
10071ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
10072 netdev_features_t features)
10073{
b83e3010
AD		 10074 unsigned int network_hdr_len, mac_hdr_len;
10075
10076 /* Make certain the headers can be described by a context descriptor */
10077 mac_hdr_len = skb_network_header(skb) - skb->data;
10078 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
10079 return features & ~(NETIF_F_HW_CSUM |
10080 NETIF_F_SCTP_CRC |
c74d4bdb 10081 NETIF_F_GSO_UDP_L4 |
b83e3010
AD		 10082 NETIF_F_HW_VLAN_CTAG_TX |
10083 NETIF_F_TSO |
10084 NETIF_F_TSO6);
10085
10086 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
10087 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
10088 return features & ~(NETIF_F_HW_CSUM |
10089 NETIF_F_SCTP_CRC |
c74d4bdb 10090 NETIF_F_GSO_UDP_L4 |
b83e3010
AD		 10091 NETIF_F_TSO |
10092 NETIF_F_TSO6);
10093
10094 /* We can only support IPV4 TSO in tunnels if we can mangle the
10095 * inner IP ID field, so strip TSO if MANGLEID is not supported.
70da6824
SN		 10096 * IPsec offoad sets skb->encapsulation but still can handle
10097 * the TSO, so it's the exception.
b83e3010 10098 */
70da6824 10099 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) {
48e01e00 10100#ifdef CONFIG_IXGBE_IPSEC
2fdb435b 10101 if (!secpath_exists(skb))
70da6824
SN		 10102#endif
10103 features &= ~NETIF_F_TSO;
10104 }
f467bc06
MR		 10105
10106 return features;
10107}
10108
92470808
JF		 10109static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog)
10110{
10111 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
10112 struct ixgbe_adapter *adapter = netdev_priv(dev);
10113 struct bpf_prog *old_prog;
4a9b32f3 10114 bool need_reset;
92470808
JF		 10115
10116 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
10117 return -EINVAL;
10118
10119 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
10120 return -EINVAL;
10121
10122 /* verify ixgbe ring attributes are sufficient for XDP */
10123 for (i = 0; i < adapter->num_rx_queues; i++) {
10124 struct ixgbe_ring *ring = adapter->rx_ring[i];
10125
10126 if (ring_is_rsc_enabled(ring))
10127 return -EINVAL;
10128
10129 if (frame_size > ixgbe_rx_bufsz(ring))
10130 return -EINVAL;
10131 }
10132
33fdc82f
JF		 10133 if (nr_cpu_ids > MAX_XDP_QUEUES)
10134 return -ENOMEM;
10135
92470808 10136 old_prog = xchg(&adapter->xdp_prog, prog);
4a9b32f3 10137 need_reset = (!!prog != !!old_prog);
33fdc82f
JF		 10138
10139 /* If transitioning XDP modes reconfigure rings */
4a9b32f3 10140 if (need_reset) {
c0fdccfd
MM		 10141 int err;
10142
10143 if (!prog)
10144 /* Wait until ndo_xsk_wakeup completes. */
10145 synchronize_rcu();
10146 err = ixgbe_setup_tc(dev, adapter->hw_tcs);
33fdc82f
JF		 10147
10148 if (err) {
10149 rcu_assign_pointer(adapter->xdp_prog, old_prog);
10150 return -EINVAL;
10151 }
10152 } else {
10153 for (i = 0; i < adapter->num_rx_queues; i++)
9cfbfa70
CZ		 10154 (void)xchg(&adapter->rx_ring[i]->xdp_prog,
10155 adapter->xdp_prog);
33fdc82f 10156 }
92470808
JF		 10157
10158 if (old_prog)
10159 bpf_prog_put(old_prog);
10160
4a9b32f3
MK		 10161 /* Kick start the NAPI context if there is an AF_XDP socket open
10162 * on that queue id. This so that receiving will start.
10163 */
10164 if (need_reset && prog)
10165 for (i = 0; i < adapter->num_rx_queues; i++)
1742b3d5 10166 if (adapter->xdp_ring[i]->xsk_pool)
9116e5e2
MK		 10167 (void)ixgbe_xsk_wakeup(adapter->netdev, i,
10168 XDP_WAKEUP_RX);
92470808
JF		 10169
10170 return 0;
10171}
10172
f4e63525 10173static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp)
92470808
JF		 10174{
10175 struct ixgbe_adapter *adapter = netdev_priv(dev);
10176
10177 switch (xdp->command) {
10178 case XDP_SETUP_PROG:
10179 return ixgbe_xdp_setup(dev, xdp->prog);
1742b3d5
MK		 10180 case XDP_SETUP_XSK_POOL:
10181 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool,
d0bcacd0
BT		 10182 xdp->xsk.queue_id);
10183
92470808
JF		 10184 default:
10185 return -EINVAL;
10186 }
10187}
10188
05ae8614 10189void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring)
5e2e6095
JDB		 10190{
10191 /* Force memory writes to complete before letting h/w know there
10192 * are new descriptors to fetch.
10193 */
10194 wmb();
10195 writel(ring->next_to_use, ring->tail);
10196}
10197
735fc405 10198static int ixgbe_xdp_xmit(struct net_device *dev, int n,
42b33468 10199 struct xdp_frame **frames, u32 flags)
64530739
JF		 10200{
10201 struct ixgbe_adapter *adapter = netdev_priv(dev);
10202 struct ixgbe_ring *ring;
fdc13979 10203 int nxmit = 0;
735fc405 10204 int i;
64530739
JF		 10205
10206 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state)))
2886447d 10207 return -ENETDOWN;
64530739 10208
5e2e6095 10209 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
42b33468
JDB		 10210 return -EINVAL;
10211
64530739
JF		 10212 /* During program transitions its possible adapter->xdp_prog is assigned
10213 * but ring has not been configured yet. In this case simply abort xmit.
10214 */
10215 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL;
10216 if (unlikely(!ring))
2886447d 10217 return -ENXIO;
64530739 10218
024aa580
BT		 10219 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state)))
10220 return -ENXIO;
10221
735fc405
JDB		 10222 for (i = 0; i < n; i++) {
10223 struct xdp_frame *xdpf = frames[i];
10224 int err;
64530739 10225
735fc405 10226 err = ixgbe_xmit_xdp_ring(adapter, xdpf);
fdc13979
LB		 10227 if (err != IXGBE_XDP_TX)
10228 break;
10229 nxmit++;
735fc405
JDB		 10230 }
10231
5e2e6095
JDB		 10232 if (unlikely(flags & XDP_XMIT_FLUSH))
10233 ixgbe_xdp_ring_update_tail(ring);
64530739 10234
fdc13979 10235 return nxmit;
64530739
JF		 10236}
10237
0edc3527 10238static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 10239 .ndo_open = ixgbe_open,
0edc3527 10240 .ndo_stop = ixgbe_close,
00829823 10241 .ndo_start_xmit = ixgbe_xmit_frame,
581330ba 10242 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 10243 .ndo_validate_addr = eth_validate_addr,
10244 .ndo_set_mac_address = ixgbe_set_mac,
10245 .ndo_change_mtu = ixgbe_change_mtu,
10246 .ndo_tx_timeout = ixgbe_tx_timeout,
c04f90e5 10247 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
0edc3527
SH		 10248 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
10249 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
a7605370 10250 .ndo_eth_ioctl = ixgbe_ioctl,
7f01648a
GR		 10251 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
10252 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 10253 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 10254 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 10255 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 10256 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 10257 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 10258 .ndo_get_stats64 = ixgbe_get_stats64,
e4c6734e 10259 .ndo_setup_tc = __ixgbe_setup_tc,
332d4a7d 10260#ifdef IXGBE_FCOE
eadec877 10261 .ndo_select_queue = ixgbe_select_queue,
332d4a7d 10262 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 10263 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 10264 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 10265 .ndo_fcoe_enable = ixgbe_fcoe_enable,
10266 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 10267 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 10268 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 10269#endif /* IXGBE_FCOE */
082757af
DS		 10270 .ndo_set_features = ixgbe_set_features,
10271 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 10272 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 10273 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
10274 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 10275 .ndo_dfwd_add_station = ixgbe_fwd_add,
10276 .ndo_dfwd_del_station = ixgbe_fwd_del,
f467bc06 10277 .ndo_features_check = ixgbe_features_check,
f4e63525 10278 .ndo_bpf = ixgbe_xdp,
64530739 10279 .ndo_xdp_xmit = ixgbe_xdp_xmit,
9116e5e2 10280 .ndo_xsk_wakeup = ixgbe_xsk_wakeup,
0edc3527
SH		 10281};
10282
024aa580
BT		 10283static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter,
10284 struct ixgbe_ring *tx_ring)
10285{
10286 unsigned long wait_delay, delay_interval;
10287 struct ixgbe_hw *hw = &adapter->hw;
10288 u8 reg_idx = tx_ring->reg_idx;
10289 int wait_loop;
10290 u32 txdctl;
10291
10292 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
10293
10294 /* delay mechanism from ixgbe_disable_tx */
10295 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10296
10297 wait_loop = IXGBE_MAX_RX_DESC_POLL;
10298 wait_delay = delay_interval;
10299
10300 while (wait_loop--) {
10301 usleep_range(wait_delay, wait_delay + 10);
10302 wait_delay += delay_interval * 2;
10303 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
10304
10305 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
10306 return;
10307 }
10308
10309 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n");
10310}
10311
10312static void ixgbe_disable_txr(struct ixgbe_adapter *adapter,
10313 struct ixgbe_ring *tx_ring)
10314{
10315 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10316 ixgbe_disable_txr_hw(adapter, tx_ring);
10317}
10318
10319static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter,
10320 struct ixgbe_ring *rx_ring)
10321{
10322 unsigned long wait_delay, delay_interval;
10323 struct ixgbe_hw *hw = &adapter->hw;
10324 u8 reg_idx = rx_ring->reg_idx;
10325 int wait_loop;
10326 u32 rxdctl;
10327
10328 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10329 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
10330 rxdctl |= IXGBE_RXDCTL_SWFLSH;
10331
10332 /* write value back with RXDCTL.ENABLE bit cleared */
10333 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
10334
10335 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
10336 if (hw->mac.type == ixgbe_mac_82598EB &&
10337 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
10338 return;
10339
10340 /* delay mechanism from ixgbe_disable_rx */
10341 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10342
10343 wait_loop = IXGBE_MAX_RX_DESC_POLL;
10344 wait_delay = delay_interval;
10345
10346 while (wait_loop--) {
10347 usleep_range(wait_delay, wait_delay + 10);
10348 wait_delay += delay_interval * 2;
10349 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10350
10351 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
10352 return;
10353 }
10354
10355 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n");
10356}
10357
10358static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring)
10359{
10360 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats));
10361 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats));
10362}
10363
10364static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring)
10365{
10366 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats));
10367 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats));
10368}
10369
10370/**
10371 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings
10372 * @adapter: adapter structure
10373 * @ring: ring index
10374 *
10375 * This function disables a certain Rx/Tx/XDP Tx ring. The function
10376 * assumes that the netdev is running.
10377 **/
10378void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring)
10379{
10380 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10381
10382 rx_ring = adapter->rx_ring[ring];
10383 tx_ring = adapter->tx_ring[ring];
10384 xdp_ring = adapter->xdp_ring[ring];
10385
10386 ixgbe_disable_txr(adapter, tx_ring);
10387 if (xdp_ring)
10388 ixgbe_disable_txr(adapter, xdp_ring);
10389 ixgbe_disable_rxr_hw(adapter, rx_ring);
10390
10391 if (xdp_ring)
8166abb1 10392 synchronize_rcu();
024aa580
BT		 10393
10394 /* Rx/Tx/XDP Tx share the same napi context. */
10395 napi_disable(&rx_ring->q_vector->napi);
10396
10397 ixgbe_clean_tx_ring(tx_ring);
10398 if (xdp_ring)
10399 ixgbe_clean_tx_ring(xdp_ring);
10400 ixgbe_clean_rx_ring(rx_ring);
10401
10402 ixgbe_reset_txr_stats(tx_ring);
10403 if (xdp_ring)
10404 ixgbe_reset_txr_stats(xdp_ring);
10405 ixgbe_reset_rxr_stats(rx_ring);
10406}
10407
10408/**
10409 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings
10410 * @adapter: adapter structure
10411 * @ring: ring index
10412 *
10413 * This function enables a certain Rx/Tx/XDP Tx ring. The function
10414 * assumes that the netdev is running.
10415 **/
10416void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring)
10417{
10418 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10419
10420 rx_ring = adapter->rx_ring[ring];
10421 tx_ring = adapter->tx_ring[ring];
10422 xdp_ring = adapter->xdp_ring[ring];
10423
10424 /* Rx/Tx/XDP Tx share the same napi context. */
10425 napi_enable(&rx_ring->q_vector->napi);
10426
10427 ixgbe_configure_tx_ring(adapter, tx_ring);
10428 if (xdp_ring)
10429 ixgbe_configure_tx_ring(adapter, xdp_ring);
10430 ixgbe_configure_rx_ring(adapter, rx_ring);
10431
10432 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
0db4a47c
CIK		 10433 if (xdp_ring)
10434 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state);
024aa580
BT		 10435}
10436
e027d1ae
JK		 10437/**
10438 * ixgbe_enumerate_functions - Get the number of ports this device has
10439 * @adapter: adapter structure
10440 *
10441 * This function enumerates the phsyical functions co-located on a single slot,
10442 * in order to determine how many ports a device has. This is most useful in
10443 * determining the required GT/s of PCIe bandwidth necessary for optimal
10444 * performance.
10445 **/
10446static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
10447{
caafb95d 10448 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 10449 int physfns = 0;
10450
f1f96579
JK		 10451 /* Some cards can not use the generic count PCIe functions method,
10452 * because they are behind a parent switch, so we hardcode these with
10453 * the correct number of functions.
e027d1ae 10454 */
8818970d 10455 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 10456 physfns = 4;
8818970d
JK		 10457
10458 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
10459 /* don't count virtual functions */
caafb95d
JK		 10460 if (entry->is_virtfn)
10461 continue;
10462
10463 /* When the devices on the bus don't all match our device ID,
10464 * we can't reliably determine the correct number of
10465 * functions. This can occur if a function has been direct
10466 * attached to a virtual machine using VT-d, for example. In
10467 * this case, simply return -1 to indicate this.
10468 */
10469 if ((entry->vendor != pdev->vendor) ||
10470 (entry->device != pdev->device))
10471 return -1;
10472
10473 physfns++;
e027d1ae
JK		 10474 }
10475
10476 return physfns;
10477}
10478
8e2813f5
JK		 10479/**
10480 * ixgbe_wol_supported - Check whether device supports WoL
740234f0 10481 * @adapter: the adapter private structure
8e2813f5 10482 * @device_id: the device ID
5ba643c6 10483 * @subdevice_id: the subsystem device ID
8e2813f5
JK		 10484 *
10485 * This function is used by probe and ethtool to determine
10486 * which devices have WoL support
10487 *
10488 **/
740234f0
ET		 10489bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
10490 u16 subdevice_id)
8e2813f5
JK		 10491{
10492 struct ixgbe_hw *hw = &adapter->hw;
10493 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8e2813f5 10494
740234f0
ET		 10495 /* WOL not supported on 82598 */
10496 if (hw->mac.type == ixgbe_mac_82598EB)
10497 return false;
10498
10499 /* check eeprom to see if WOL is enabled for X540 and newer */
10500 if (hw->mac.type >= ixgbe_mac_X540) {
10501 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
10502 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
10503 (hw->bus.func == 0)))
10504 return true;
10505 }
10506
10507 /* WOL is determined based on device IDs for 82599 MACs */
8e2813f5
JK		 10508 switch (device_id) {
10509 case IXGBE_DEV_ID_82599_SFP:
10510 /* Only these subdevices could supports WOL */
10511 switch (subdevice_id) {
10512 case IXGBE_SUBDEV_ID_82599_560FLR:
00103a6c
ET		 10513 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
10514 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
10515 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
8e2813f5
JK		 10516 /* only support first port */
10517 if (hw->bus.func != 0)
10518 break;
5463fce6 10519 fallthrough;
5700ff26 10520 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 10521 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 10522 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 10523 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
00103a6c
ET		 10524 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
10525 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
10526 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
740234f0 10527 return true;
8e2813f5
JK		 10528 }
10529 break;
5daebbb0 10530 case IXGBE_DEV_ID_82599EN_SFP:
740234f0 10531 /* Only these subdevices support WOL */
5daebbb0
DS		 10532 switch (subdevice_id) {
10533 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
740234f0 10534 return true;
5daebbb0
DS		 10535 }
10536 break;
8e2813f5
JK		 10537 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
10538 /* All except this subdevice support WOL */
10539 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
740234f0 10540 return true;
8e2813f5
JK		 10541 break;
10542 case IXGBE_DEV_ID_82599_KX4:
740234f0
ET		 10543 return true;
10544 default:
8e2813f5
JK		 10545 break;
10546 }
10547
740234f0 10548 return false;
8e2813f5
JK		 10549}
10550
73834aec
PG		 10551/**
10552 * ixgbe_set_fw_version - Set FW version
10553 * @adapter: the adapter private structure
10554 *
10555 * This function is used by probe and ethtool to determine the FW version to
10556 * format to display. The FW version is taken from the EEPROM/NVM.
10557 */
10558static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter)
10559{
10560 struct ixgbe_hw *hw = &adapter->hw;
10561 struct ixgbe_nvm_version nvm_ver;
10562
10563 ixgbe_get_oem_prod_version(hw, &nvm_ver);
10564 if (nvm_ver.oem_valid) {
10565 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10566 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor,
10567 nvm_ver.oem_release);
10568 return;
10569 }
10570
10571 ixgbe_get_etk_id(hw, &nvm_ver);
10572 ixgbe_get_orom_version(hw, &nvm_ver);
10573
10574 if (nvm_ver.or_valid) {
10575 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10576 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major,
10577 nvm_ver.or_build, nvm_ver.or_patch);
10578 return;
10579 }
10580
10581 /* Set ETrack ID format */
10582 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10583 "0x%08x", nvm_ver.etk_id);
10584}
10585
9a799d71
AK		 10586/**
10587 * ixgbe_probe - Device Initialization Routine
10588 * @pdev: PCI device information struct
10589 * @ent: entry in ixgbe_pci_tbl
10590 *
10591 * Returns 0 on success, negative on failure
10592 *
10593 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
10594 * The OS initialization, configuring of the adapter private structure,
10595 * and a hardware reset occur.
10596 **/
1dd06ae8 10597static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 10598{
10599 struct net_device *netdev;
10600 struct ixgbe_adapter *adapter = NULL;
10601 struct ixgbe_hw *hw;
10602 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 10603 int i, err, pci_using_dac, expected_gts;
d3cb9869 10604 unsigned int indices = MAX_TX_QUEUES;
289700db 10605 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 10606 bool disable_dev = false;
eacd73f7
YZ		 10607#ifdef IXGBE_FCOE
10608 u16 device_caps;
10609#endif
289700db 10610 u32 eec;
9a799d71 10611
bded64a7
AG		 10612 /* Catch broken hardware that put the wrong VF device ID in
10613 * the PCIe SR-IOV capability.
10614 */
10615 if (pdev->is_virtfn) {
10616 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
10617 pci_name(pdev), pdev->vendor, pdev->device);
10618 return -EINVAL;
10619 }
10620
9ce77666 10621 err = pci_enable_device_mem(pdev);
9a799d71
AK		 10622 if (err)
10623 return err;
10624
f5f2eda8 10625 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 10626 pci_using_dac = 1;
10627 } else {
f5f2eda8 10628 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 10629 if (err) {
f5f2eda8
RK		 10630 dev_err(&pdev->dev,
10631 "No usable DMA configuration, aborting\n");
10632 goto err_dma;
9a799d71
AK		 10633 }
10634 pci_using_dac = 0;
10635 }
10636
56d766d6 10637 err = pci_request_mem_regions(pdev, ixgbe_driver_name);
9a799d71 10638 if (err) {
b8bc0421
DC		 10639 dev_err(&pdev->dev,
10640 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 10641 goto err_pci_reg;
10642 }
10643
19d5afd4 10644 pci_enable_pcie_error_reporting(pdev);
6fabd715 10645
9a799d71 10646 pci_set_master(pdev);
fb3b27bc 10647 pci_save_state(pdev);
9a799d71 10648
d3cb9869 10649 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 10650#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 10651 /* 8 TC w/ 4 queues per TC */
10652 indices = 4 * MAX_TRAFFIC_CLASS;
10653#else
10654 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 10655#endif
d3cb9869 10656 }
e901acd6 10657
c85a2618 10658 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 10659 if (!netdev) {
10660 err = -ENOMEM;
10661 goto err_alloc_etherdev;
10662 }
10663
9a799d71
AK		 10664 SET_NETDEV_DEV(netdev, &pdev->dev);
10665
9a799d71
AK		 10666 adapter = netdev_priv(netdev);
10667
10668 adapter->netdev = netdev;
10669 adapter->pdev = pdev;
10670 hw = &adapter->hw;
10671 hw->back = adapter;
b3f4d599 10672 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 10673
05857980 10674 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 10675 pci_resource_len(pdev, 0));
2a1a091c 10676 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 10677 if (!hw->hw_addr) {
10678 err = -EIO;
10679 goto err_ioremap;
10680 }
10681
0edc3527 10682 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 10683 ixgbe_set_ethtool_ops(netdev);
9a799d71 10684 netdev->watchdog_timeo = 5 * HZ;
339de30f 10685 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 10686
9a799d71 10687 /* Setup hw api */
37689010 10688 hw->mac.ops = *ii->mac_ops;
021230d4 10689 hw->mac.type = ii->mac;
9a900eca 10690 hw->mvals = ii->mvals;
b71f6c40
ET		 10691 if (ii->link_ops)
10692 hw->link.ops = *ii->link_ops;
9a799d71 10693
c44ade9e 10694 /* EEPROM */
37689010 10695 hw->eeprom.ops = *ii->eeprom_ops;
9a900eca 10696 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 10697 if (ixgbe_removed(hw->hw_addr)) {
10698 err = -EIO;
10699 goto err_ioremap;
10700 }
c44ade9e 10701 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
b4f47a48 10702 if (!(eec & BIT(8)))
c44ade9e
JB		 10703 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
10704
10705 /* PHY */
37689010 10706 hw->phy.ops = *ii->phy_ops;
c4900be0 10707 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 10708 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
10709 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
10710 hw->phy.mdio.mmds = 0;
10711 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10712 hw->phy.mdio.dev = netdev;
10713 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
10714 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 10715
9a799d71 10716 /* setup the private structure */
55570b6f 10717 err = ixgbe_sw_init(adapter, ii);
9a799d71
AK		 10718 if (err)
10719 goto err_sw_init;
10720
dc221851
JK		 10721 switch (adapter->hw.mac.type) {
10722 case ixgbe_mac_X550:
10723 case ixgbe_mac_X550EM_x:
10724 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550;
10725 break;
10726 case ixgbe_mac_x550em_a:
10727 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a;
10728 break;
10729 default:
10730 break;
10731 }
10732
dbd15b8f
DS		 10733 /* Make sure the SWFW semaphore is in a valid state */
10734 if (hw->mac.ops.init_swfw_sync)
10735 hw->mac.ops.init_swfw_sync(hw);
10736
e86bff0e 10737 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 10738 switch (adapter->hw.mac.type) {
10739 case ixgbe_mac_82599EB:
10740 case ixgbe_mac_X540:
9a75a1ac
DS		 10741 case ixgbe_mac_X550:
10742 case ixgbe_mac_X550EM_x:
49425dfc 10743 case ixgbe_mac_x550em_a:
e86bff0e 10744 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 10745 break;
10746 default:
10747 break;
10748 }
e86bff0e 10749
bf069c97
DS		 10750 /*
10751 * If there is a fan on this device and it has failed log the
10752 * failure.
10753 */
10754 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
10755 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
10756 if (esdp & IXGBE_ESDP_SDP1)
396e799c 10757 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 10758 }
10759
8ef78adc
PWJ		 10760 if (allow_unsupported_sfp)
10761 hw->allow_unsupported_sfp = allow_unsupported_sfp;
10762
c44ade9e 10763 /* reset_hw fills in the perm_addr as well */
119fc60a 10764 hw->phy.reset_if_overtemp = true;
c44ade9e 10765 err = hw->mac.ops.reset_hw(hw);
119fc60a 10766 hw->phy.reset_if_overtemp = false;
b3eb4e18 10767 ixgbe_set_eee_capable(adapter);
29a8dca1 10768 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 10769 err = 0;
10770 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 10771 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
10772 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 10773 goto err_sw_init;
10774 } else if (err) {
849c4542 10775 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 10776 goto err_sw_init;
10777 }
10778
99d74487 10779#ifdef CONFIG_PCI_IOV
60a1a680
GR		 10780 /* SR-IOV not supported on the 82598 */
10781 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
10782 goto skip_sriov;
10783 /* Mailbox */
10784 ixgbe_init_mbx_params_pf(hw);
37689010 10785 hw->mbx.ops = ii->mbx_ops;
dcc23e3a 10786 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
5c11f00d 10787 ixgbe_enable_sriov(adapter, max_vfs);
60a1a680 10788skip_sriov:
1cdd1ec8 10789
99d74487 10790#endif
396e799c 10791 netdev->features = NETIF_F_SG |
082757af
DS		 10792 NETIF_F_TSO |
10793 NETIF_F_TSO6 |
082757af 10794 NETIF_F_RXHASH |
49763de0 10795 NETIF_F_RXCSUM |
b83e3010
AD		 10796 NETIF_F_HW_CSUM;
10797
10798#define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
10799 NETIF_F_GSO_GRE_CSUM | \
7e13318d 10800 NETIF_F_GSO_IPXIP4 | \
bf2d1df3 10801 NETIF_F_GSO_IPXIP6 | \
b83e3010
AD		 10802 NETIF_F_GSO_UDP_TUNNEL | \
10803 NETIF_F_GSO_UDP_TUNNEL_CSUM)
10804
10805 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
10806 netdev->features |= NETIF_F_GSO_PARTIAL |
10807 IXGBE_GSO_PARTIAL_FEATURES;
ad31c402 10808
49763de0 10809 if (hw->mac.type >= ixgbe_mac_82599EB)
c74d4bdb 10810 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
49763de0 10811
48e01e00 10812#ifdef CONFIG_IXGBE_IPSEC
de7a7e34
AD		 10813#define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \
10814 NETIF_F_HW_ESP_TX_CSUM | \
10815 NETIF_F_GSO_ESP)
10816
10817 if (adapter->ipsec)
10818 netdev->features |= IXGBE_ESP_FEATURES;
10819#endif
49763de0 10820 /* copy netdev features into list of user selectable features */
b83e3010 10821 netdev->hw_features |= netdev->features |
3d951822 10822 NETIF_F_HW_VLAN_CTAG_FILTER |
b83e3010
AD		 10823 NETIF_F_HW_VLAN_CTAG_RX |
10824 NETIF_F_HW_VLAN_CTAG_TX |
10825 NETIF_F_RXALL |
49763de0
AD		 10826 NETIF_F_HW_L2FW_DOFFLOAD;
10827
10828 if (hw->mac.type >= ixgbe_mac_82599EB)
10829 netdev->hw_features |= NETIF_F_NTUPLE |
b82b17d9 10830 NETIF_F_HW_TC;
45a5ead0 10831
b83e3010
AD		 10832 if (pci_using_dac)
10833 netdev->features |= NETIF_F_HIGHDMA;
10834
5eee87cd
AD		 10835 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
10836 netdev->hw_enc_features |= netdev->vlan_features;
2a20525b
SP		 10837 netdev->mpls_features |= NETIF_F_SG |
10838 NETIF_F_TSO |
10839 NETIF_F_TSO6 |
10840 NETIF_F_HW_CSUM;
10841 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES;
5eee87cd 10842
b83e3010
AD		 10843 /* set this bit last since it cannot be part of vlan_features */
10844 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
10845 NETIF_F_HW_VLAN_CTAG_RX |
10846 NETIF_F_HW_VLAN_CTAG_TX;
ad31c402 10847
01789349 10848 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 10849 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 10850
91c527a5
JW		 10851 /* MTU range: 68 - 9710 */
10852 netdev->min_mtu = ETH_MIN_MTU;
10853 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
10854
7a6b6f51 10855#ifdef CONFIG_IXGBE_DCB
8829009d 10856 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
3f40c74c 10857 netdev->dcbnl_ops = &ixgbe_dcbnl_ops;
2f90b865
AD		 10858#endif
10859
eacd73f7 10860#ifdef IXGBE_FCOE
0d551589 10861 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 10862 unsigned int fcoe_l;
10863
eacd73f7
YZ		 10864 if (hw->mac.ops.get_device_caps) {
10865 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 10866 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
10867 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 10868 }
7c8ae65a 10869
d3cb9869
AD		 10870
10871 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
10872 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 10873
a58915c7
AD		 10874 netdev->features |= NETIF_F_FSO |
10875 NETIF_F_FCOE_CRC;
10876
7c8ae65a
AD		 10877 netdev->vlan_features |= NETIF_F_FSO |
10878 NETIF_F_FCOE_CRC |
10879 NETIF_F_FCOE_MTU;
5e09d7f6 10880 }
eacd73f7 10881#endif /* IXGBE_FCOE */
082757af
DS		 10882 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
10883 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 10884 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 10885 netdev->features |= NETIF_F_LRO;
10886
59dd45d5
SB		 10887 if (ixgbe_check_fw_error(adapter)) {
10888 err = -EIO;
10889 goto err_sw_init;
10890 }
10891
9a799d71 10892 /* make sure the EEPROM is good */
c44ade9e 10893 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 10894 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 10895 err = -EIO;
35937c05 10896 goto err_sw_init;
9a799d71
AK		 10897 }
10898
c7374b5a
SV		 10899 eth_platform_get_mac_address(&adapter->pdev->dev,
10900 adapter->hw.mac.perm_addr);
c762dff2 10901
9a799d71 10902 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 10903
aaeb6cdf 10904 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 10905 e_dev_err("invalid MAC address\n");
9a799d71 10906 err = -EIO;
35937c05 10907 goto err_sw_init;
9a799d71
AK		 10908 }
10909
56768045
TD		 10910 /* Set hw->mac.addr to permanent MAC address */
10911 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
c9f53e63 10912 ixgbe_mac_set_default_filter(adapter);
5d7daa35 10913
26566eae 10914 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0);
9a799d71 10915
58cf663f
MR		 10916 if (ixgbe_removed(hw->hw_addr)) {
10917 err = -EIO;
10918 goto err_sw_init;
10919 }
7086400d 10920 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 10921 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 10922 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 10923
021230d4
AV		 10924 err = ixgbe_init_interrupt_scheme(adapter);
10925 if (err)
10926 goto err_sw_init;
9a799d71 10927
b09457e7
LS		 10928 for (i = 0; i < adapter->num_rx_queues; i++)
10929 u64_stats_init(&adapter->rx_ring[i]->syncp);
10930 for (i = 0; i < adapter->num_tx_queues; i++)
10931 u64_stats_init(&adapter->tx_ring[i]->syncp);
33fdc82f
JF		 10932 for (i = 0; i < adapter->num_xdp_queues; i++)
10933 u64_stats_init(&adapter->xdp_ring[i]->syncp);
10934
8e2813f5 10935 /* WOL not supported for all devices */
c23f5b6b 10936 adapter->wol = 0;
8e2813f5 10937 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 10938 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 10939 pdev->subsystem_device);
6b92b0ba 10940 if (hw->wol_enabled)
9417c464 10941 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 10942
e8e26350
PW		 10943 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
10944
15e5209f 10945 /* save off EEPROM version number */
73834aec 10946 ixgbe_set_fw_version(adapter);
15e5209f 10947
04f165ef 10948 /* pick up the PCI bus settings for reporting later */
e027d1ae 10949 if (ixgbe_pcie_from_parent(hw))
b8e82001 10950 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 10951 else
10952 hw->mac.ops.get_bus_info(hw);
04f165ef 10953
e027d1ae
JK		 10954 /* calculate the expected PCIe bandwidth required for optimal
10955 * performance. Note that some older parts will never have enough
10956 * bandwidth due to being older generation PCIe parts. We clamp these
10957 * parts to ensure no warning is displayed if it can't be fixed.
10958 */
10959 switch (hw->mac.type) {
10960 case ixgbe_mac_82598EB:
10961 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
10962 break;
10963 default:
10964 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
10965 break;
0c254d86 10966 }
caafb95d
JK		 10967
10968 /* don't check link if we failed to enumerate functions */
10969 if (expected_gts > 0)
10970 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 10971
339de30f 10972 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 10973 if (err)
339de30f 10974 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 10975 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
10976 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
10977 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 10978 part_str);
6a2aae5a
JK		 10979 else
10980 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
10981 hw->mac.type, hw->phy.type, part_str);
10982
10983 e_dev_info("%pM\n", netdev->dev_addr);
10984
9a799d71 10985 /* reset the hardware with the new settings */
794caeb2 10986 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 10987 if (err == IXGBE_ERR_EEPROM_VERSION) {
10988 /* We are running on a pre-production device, log a warning */
849c4542
ET		 10989 e_dev_warn("This device is a pre-production adapter/LOM. "
10990 "Please be aware there may be issues associated "
10991 "with your hardware. If you are experiencing "
10992 "problems please contact your Intel or hardware "
10993 "representative who provided you with this "
10994 "hardware.\n");
794caeb2 10995 }
9a799d71 10996 strcpy(netdev->name, "eth%d");
a09c0fc3 10997 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 10998 err = register_netdev(netdev);
10999 if (err)
11000 goto err_register;
11001
0fb6a55c 11002
ec74a471
ET		 11003 /* power down the optics for 82599 SFP+ fiber */
11004 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 11005 hw->mac.ops.disable_tx_laser(hw);
11006
54386467
JB		 11007 /* carrier off reporting is important to ethtool even BEFORE open */
11008 netif_carrier_off(netdev);
11009
5dd2d332 11010#ifdef CONFIG_IXGBE_DCA
652f093f 11011 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 11012 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 11013 ixgbe_setup_dca(adapter);
11014 }
11015#endif
1cdd1ec8 11016 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 11017 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 11018 for (i = 0; i < adapter->num_vfs; i++)
11019 ixgbe_vf_configuration(pdev, (i | 0x10000000));
11020 }
11021
2466dd9c
JK		 11022 /* firmware requires driver version to be 0xFFFFFFFF
11023 * since os does not support feature
11024 */
9612de92 11025 if (hw->mac.ops.set_fw_drv_ver)
cb8e0514 11026 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF,
34a2a3b8
JK		 11027 sizeof(UTS_RELEASE) - 1,
11028 UTS_RELEASE);
9612de92 11029
0365e6e4
PW		 11030 /* add san mac addr to netdev */
11031 ixgbe_add_sanmac_netdev(netdev);
9a799d71 11032
ea81875a 11033 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 11034
1210982b 11035#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 11036 if (ixgbe_sysfs_init(adapter))
11037 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 11038#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 11039
00949167 11040 ixgbe_dbg_adapter_init(adapter);
00949167 11041
d1a35ee2
ET		 11042 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
11043 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 11044 hw->mac.ops.setup_link(hw,
11045 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
11046 true);
11047
09ef193f
BG		 11048 err = ixgbe_mii_bus_init(hw);
11049 if (err)
11050 goto err_netdev;
8fa10ef0 11051
9a799d71
AK		 11052 return 0;
11053
09ef193f
BG		 11054err_netdev:
11055 unregister_netdev(netdev);
9a799d71 11056err_register:
5eba3699 11057 ixgbe_release_hw_control(adapter);
7a921c93 11058 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 11059err_sw_init:
99d74487 11060 ixgbe_disable_sriov(adapter);
7086400d 11061 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 11062 iounmap(adapter->io_addr);
1cdaaf54 11063 kfree(adapter->jump_tables[0]);
5d7daa35 11064 kfree(adapter->mac_table);
3dfbfc7e 11065 kfree(adapter->rss_key);
d49e286d 11066 bitmap_free(adapter->af_xdp_zc_qps);
9a799d71 11067err_ioremap:
b5b2ffc0 11068 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 11069 free_netdev(netdev);
11070err_alloc_etherdev:
dd2aefcd 11071 pci_disable_pcie_error_reporting(pdev);
56d766d6 11072 pci_release_mem_regions(pdev);
9a799d71
AK		 11073err_pci_reg:
11074err_dma:
b5b2ffc0 11075 if (!adapter || disable_dev)
41c62843 11076 pci_disable_device(pdev);
9a799d71
AK		 11077 return err;
11078}
11079
11080/**
11081 * ixgbe_remove - Device Removal Routine
11082 * @pdev: PCI device information struct
11083 *
11084 * ixgbe_remove is called by the PCI subsystem to alert the driver
11085 * that it should release a PCI device. The could be caused by a
11086 * Hot-Plug event, or because the driver is going to be removed from
11087 * memory.
11088 **/
9f9a12f8 11089static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 11090{
c60fbb00 11091 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 11092 struct net_device *netdev;
b5b2ffc0 11093 bool disable_dev;
1cdaaf54 11094 int i;
9a799d71 11095
0fb6a55c
ET		 11096 /* if !adapter then we already cleaned up in probe */
11097 if (!adapter)
11098 return;
11099
11100 netdev = adapter->netdev;
00949167 11101 ixgbe_dbg_adapter_exit(adapter);
00949167 11102
09f40aed 11103 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 11104 cancel_work_sync(&adapter->service_task);
9a799d71 11105
8fa10ef0
SD		 11106 if (adapter->mii_bus)
11107 mdiobus_unregister(adapter->mii_bus);
3a6a4eda 11108
5dd2d332 11109#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 11110 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
11111 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
11112 dca_remove_requester(&pdev->dev);
9de7605e
MR		 11113 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
11114 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 11115 }
11116
11117#endif
1210982b 11118#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 11119 ixgbe_sysfs_exit(adapter);
1210982b 11120#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 11121
0365e6e4
PW		 11122 /* remove the added san mac */
11123 ixgbe_del_sanmac_netdev(netdev);
11124
da36b647 11125#ifdef CONFIG_PCI_IOV
7837e286 11126 ixgbe_disable_sriov(adapter);
da36b647 11127#endif
6b010e9b
AW		 11128 if (netdev->reg_state == NETREG_REGISTERED)
11129 unregister_netdev(netdev);
11130
63a67fe2 11131 ixgbe_stop_ipsec_offload(adapter);
7a921c93 11132 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 11133
021230d4 11134 ixgbe_release_hw_control(adapter);
9a799d71 11135
2b1588c3
AD		 11136#ifdef CONFIG_DCB
11137 kfree(adapter->ixgbe_ieee_pfc);
11138 kfree(adapter->ixgbe_ieee_ets);
11139
11140#endif
2a1a091c 11141 iounmap(adapter->io_addr);
56d766d6 11142 pci_release_mem_regions(pdev);
9a799d71 11143
849c4542 11144 e_dev_info("complete\n");
021230d4 11145
1cdaaf54
AN		 11146 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
11147 if (adapter->jump_tables[i]) {
11148 kfree(adapter->jump_tables[i]->input);
11149 kfree(adapter->jump_tables[i]->mask);
11150 }
11151 kfree(adapter->jump_tables[i]);
11152 }
11153
5d7daa35 11154 kfree(adapter->mac_table);
3dfbfc7e 11155 kfree(adapter->rss_key);
d49e286d 11156 bitmap_free(adapter->af_xdp_zc_qps);
b5b2ffc0 11157 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 11158 free_netdev(netdev);
11159
19d5afd4 11160 pci_disable_pcie_error_reporting(pdev);
6fabd715 11161
b5b2ffc0 11162 if (disable_dev)
41c62843 11163 pci_disable_device(pdev);
9a799d71
AK		 11164}
11165
11166/**
11167 * ixgbe_io_error_detected - called when PCI error is detected
11168 * @pdev: Pointer to PCI device
11169 * @state: The current pci connection state
11170 *
11171 * This function is called after a PCI bus error affecting
11172 * this device has been detected.
11173 */
11174static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 11175 pci_channel_state_t state)
9a799d71 11176{
c60fbb00
AD		 11177 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11178 struct net_device *netdev = adapter->netdev;
9a799d71 11179
83c61fa9 11180#ifdef CONFIG_PCI_IOV
14438464 11181 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 11182 struct pci_dev *bdev, *vfdev;
11183 u32 dw0, dw1, dw2, dw3;
11184 int vf, pos;
11185 u16 req_id, pf_func;
11186
11187 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
11188 adapter->num_vfs == 0)
11189 goto skip_bad_vf_detection;
11190
11191 bdev = pdev->bus->self;
62f87c0e 11192 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 11193 bdev = bdev->bus->self;
11194
11195 if (!bdev)
11196 goto skip_bad_vf_detection;
11197
11198 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
11199 if (!pos)
11200 goto skip_bad_vf_detection;
11201
14438464
MR		 11202 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
11203 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
11204 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
11205 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
11206 if (ixgbe_removed(hw->hw_addr))
11207 goto skip_bad_vf_detection;
83c61fa9
GR		 11208
11209 req_id = dw1 >> 16;
11210 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
11211 if (!(req_id & 0x0080))
11212 goto skip_bad_vf_detection;
11213
11214 pf_func = req_id & 0x01;
11215 if ((pf_func & 1) == (pdev->devfn & 1)) {
11216 unsigned int device_id;
11217
11218 vf = (req_id & 0x7F) >> 1;
11219 e_dev_err("VF %d has caused a PCIe error\n", vf);
11220 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
11221 "%8.8x\tdw3: %8.8x\n",
11222 dw0, dw1, dw2, dw3);
11223 switch (adapter->hw.mac.type) {
11224 case ixgbe_mac_82599EB:
11225 device_id = IXGBE_82599_VF_DEVICE_ID;
11226 break;
11227 case ixgbe_mac_X540:
11228 device_id = IXGBE_X540_VF_DEVICE_ID;
11229 break;
9a75a1ac
DS		 11230 case ixgbe_mac_X550:
11231 device_id = IXGBE_DEV_ID_X550_VF;
11232 break;
11233 case ixgbe_mac_X550EM_x:
11234 device_id = IXGBE_DEV_ID_X550EM_X_VF;
11235 break;
49425dfc
MR		 11236 case ixgbe_mac_x550em_a:
11237 device_id = IXGBE_DEV_ID_X550EM_A_VF;
11238 break;
83c61fa9
GR		 11239 default:
11240 device_id = 0;
11241 break;
11242 }
11243
11244 /* Find the pci device of the offending VF */
36e90319 11245 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 11246 while (vfdev) {
11247 if (vfdev->devfn == (req_id & 0xFF))
11248 break;
36e90319 11249 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 11250 device_id, vfdev);
11251 }
11252 /*
11253 * There's a slim chance the VF could have been hot plugged,
11254 * so if it is no longer present we don't need to issue the
11255 * VFLR. Just clean up the AER in that case.
11256 */
11257 if (vfdev) {
63af8f7a 11258 pcie_flr(vfdev);
b4fafbe9
GR		 11259 /* Free device reference count */
11260 pci_dev_put(vfdev);
83c61fa9 11261 }
83c61fa9
GR		 11262 }
11263
11264 /*
11265 * Even though the error may have occurred on the other port
11266 * we still need to increment the vf error reference count for
11267 * both ports because the I/O resume function will be called
11268 * for both of them.
11269 */
11270 adapter->vferr_refcount++;
11271
11272 return PCI_ERS_RESULT_RECOVERED;
11273
11274skip_bad_vf_detection:
11275#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 11276 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
11277 return PCI_ERS_RESULT_DISCONNECT;
b64666ae
ET		 11278
11279 if (!netif_device_present(netdev))
11280 return PCI_ERS_RESULT_DISCONNECT;
58cf663f 11281
41c62843 11282 rtnl_lock();
9a799d71
AK		 11283 netif_device_detach(netdev);
11284
b212d815
MR		 11285 if (netif_running(netdev))
11286 ixgbe_close_suspend(adapter);
11287
41c62843
MR		 11288 if (state == pci_channel_io_perm_failure) {
11289 rtnl_unlock();
3044b8d1 11290 return PCI_ERS_RESULT_DISCONNECT;
41c62843 11291 }
3044b8d1 11292
41c62843
MR		 11293 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
11294 pci_disable_device(pdev);
11295 rtnl_unlock();
9a799d71 11296
b4617240 11297 /* Request a slot reset. */
9a799d71
AK		 11298 return PCI_ERS_RESULT_NEED_RESET;
11299}
11300
11301/**
11302 * ixgbe_io_slot_reset - called after the pci bus has been reset.
11303 * @pdev: Pointer to PCI device
11304 *
11305 * Restart the card from scratch, as if from a cold-boot.
11306 */
11307static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
11308{
c60fbb00 11309 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715 11310 pci_ers_result_t result;
9a799d71 11311
9ce77666 11312 if (pci_enable_device_mem(pdev)) {
396e799c 11313 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 11314 result = PCI_ERS_RESULT_DISCONNECT;
11315 } else {
4e857c58 11316 smp_mb__before_atomic();
41c62843 11317 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 11318 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 11319 pci_set_master(pdev);
11320 pci_restore_state(pdev);
c0e1f68b 11321 pci_save_state(pdev);
9a799d71 11322
dd4d8ca6 11323 pci_wake_from_d3(pdev, false);
9a799d71 11324
6fabd715 11325 ixgbe_reset(adapter);
88512539 11326 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 11327 result = PCI_ERS_RESULT_RECOVERED;
11328 }
11329
6fabd715 11330 return result;
9a799d71
AK		 11331}
11332
11333/**
11334 * ixgbe_io_resume - called when traffic can start flowing again.
11335 * @pdev: Pointer to PCI device
11336 *
11337 * This callback is called when the error recovery driver tells us that
11338 * its OK to resume normal operation.
11339 */
11340static void ixgbe_io_resume(struct pci_dev *pdev)
11341{
c60fbb00
AD		 11342 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11343 struct net_device *netdev = adapter->netdev;
9a799d71 11344
83c61fa9
GR		 11345#ifdef CONFIG_PCI_IOV
11346 if (adapter->vferr_refcount) {
11347 e_info(drv, "Resuming after VF err\n");
11348 adapter->vferr_refcount--;
11349 return;
11350 }
11351
11352#endif
126db13f 11353 rtnl_lock();
c7ccde0f 11354 if (netif_running(netdev))
126db13f 11355 ixgbe_open(netdev);
9a799d71
AK		 11356
11357 netif_device_attach(netdev);
126db13f 11358 rtnl_unlock();
9a799d71
AK		 11359}
11360
3646f0e5 11361static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 11362 .error_detected = ixgbe_io_error_detected,
11363 .slot_reset = ixgbe_io_slot_reset,
11364 .resume = ixgbe_io_resume,
11365};
11366
6f82b255
VG		 11367static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume);
11368
9a799d71 11369static struct pci_driver ixgbe_driver = {
6f82b255
VG		 11370 .name = ixgbe_driver_name,
11371 .id_table = ixgbe_pci_tbl,
11372 .probe = ixgbe_probe,
11373 .remove = ixgbe_remove,
11374 .driver.pm = &ixgbe_pm_ops,
11375 .shutdown = ixgbe_shutdown,
da36b647 11376 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 11377 .err_handler = &ixgbe_err_handler
11378};
11379
11380/**
11381 * ixgbe_init_module - Driver Registration Routine
11382 *
11383 * ixgbe_init_module is the first routine called when the driver is
11384 * loaded. All it does is register with the PCI subsystem.
11385 **/
11386static int __init ixgbe_init_module(void)
11387{
11388 int ret;
34a2a3b8 11389 pr_info("%s\n", ixgbe_driver_string);
849c4542 11390 pr_info("%s\n", ixgbe_copyright);
9a799d71 11391
780484d8
MR		 11392 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
11393 if (!ixgbe_wq) {
11394 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
11395 return -ENOMEM;
11396 }
11397
00949167 11398 ixgbe_dbg_init();
00949167 11399
f01fc1a8
JK		 11400 ret = pci_register_driver(&ixgbe_driver);
11401 if (ret) {
6b836879 11402 destroy_workqueue(ixgbe_wq);
f01fc1a8 11403 ixgbe_dbg_exit();
f01fc1a8
JK		 11404 return ret;
11405 }
11406
5dd2d332 11407#ifdef CONFIG_IXGBE_DCA
bd0362dd 11408 dca_register_notify(&dca_notifier);
bd0362dd 11409#endif
5dd2d332 11410
f01fc1a8 11411 return 0;
9a799d71 11412}
b4617240 11413
9a799d71
AK		 11414module_init(ixgbe_init_module);
11415
11416/**
11417 * ixgbe_exit_module - Driver Exit Cleanup Routine
11418 *
11419 * ixgbe_exit_module is called just before the driver is removed
11420 * from memory.
11421 **/
11422static void __exit ixgbe_exit_module(void)
11423{
5dd2d332 11424#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 11425 dca_unregister_notify(&dca_notifier);
11426#endif
9a799d71 11427 pci_unregister_driver(&ixgbe_driver);
00949167 11428
00949167 11429 ixgbe_dbg_exit();
780484d8
MR		 11430 if (ixgbe_wq) {
11431 destroy_workqueue(ixgbe_wq);
11432 ixgbe_wq = NULL;
11433 }
9a799d71 11434}
bd0362dd 11435
5dd2d332 11436#ifdef CONFIG_IXGBE_DCA
bd0362dd 11437static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 11438 void *p)
bd0362dd
JC		 11439{
11440 int ret_val;
11441
11442 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 11443 __ixgbe_notify_dca);
bd0362dd
JC		 11444
11445 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
11446}
b453368d 11447
5dd2d332 11448#endif /* CONFIG_IXGBE_DCA */
849c4542 11449
9a799d71
AK		 11450module_exit(ixgbe_exit_module);
11451
11452/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)