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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
94971820 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
9a799d71 AK |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
897ab156 | 38 | #include <linux/sctp.h> |
60127865 | 39 | #include <linux/pkt_sched.h> |
9a799d71 | 40 | #include <linux/ipv6.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
9a799d71 AK |
42 | #include <net/checksum.h> |
43 | #include <net/ip6_checksum.h> | |
44 | #include <linux/ethtool.h> | |
01789349 | 45 | #include <linux/if.h> |
9a799d71 | 46 | #include <linux/if_vlan.h> |
70c71606 | 47 | #include <linux/prefetch.h> |
eacd73f7 | 48 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
49 | |
50 | #include "ixgbe.h" | |
51 | #include "ixgbe_common.h" | |
ee5f784a | 52 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 53 | #include "ixgbe_sriov.h" |
9a799d71 AK |
54 | |
55 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 56 | static const char ixgbe_driver_string[] = |
e8e9f696 | 57 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
8af3c33f | 58 | #ifdef IXGBE_FCOE |
ea81875a NP |
59 | char ixgbe_default_device_descr[] = |
60 | "Intel(R) 10 Gigabit Network Connection"; | |
8af3c33f JK |
61 | #else |
62 | static char ixgbe_default_device_descr[] = | |
63 | "Intel(R) 10 Gigabit Network Connection"; | |
64 | #endif | |
75e3d3c6 | 65 | #define MAJ 3 |
8e4f3250 DS |
66 | #define MIN 8 |
67 | #define BUILD 21 | |
75e3d3c6 | 68 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
a38a104d | 69 | __stringify(BUILD) "-k" |
9c8eb720 | 70 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 71 | static const char ixgbe_copyright[] = |
94971820 | 72 | "Copyright (c) 1999-2012 Intel Corporation."; |
9a799d71 AK |
73 | |
74 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 75 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 76 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 77 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
78 | }; |
79 | ||
80 | /* ixgbe_pci_tbl - PCI Device ID Table | |
81 | * | |
82 | * Wildcard entries (PCI_ANY_ID) should come last | |
83 | * Last entry must be all 0s | |
84 | * | |
85 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
86 | * Class, Class Mask, private data (not used) } | |
87 | */ | |
a3aa1884 | 88 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
54239c67 AD |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
112 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
114 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
7d145282 | 115 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 116 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
9a799d71 AK |
117 | /* required last entry */ |
118 | {0, } | |
119 | }; | |
120 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
121 | ||
5dd2d332 | 122 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 123 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 124 | void *p); |
bd0362dd JC |
125 | static struct notifier_block dca_notifier = { |
126 | .notifier_call = ixgbe_notify_dca, | |
127 | .next = NULL, | |
128 | .priority = 0 | |
129 | }; | |
130 | #endif | |
131 | ||
1cdd1ec8 GR |
132 | #ifdef CONFIG_PCI_IOV |
133 | static unsigned int max_vfs; | |
134 | module_param(max_vfs, uint, 0); | |
e8e9f696 | 135 | MODULE_PARM_DESC(max_vfs, |
6b42a9c5 | 136 | "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63"); |
1cdd1ec8 GR |
137 | #endif /* CONFIG_PCI_IOV */ |
138 | ||
8ef78adc PWJ |
139 | static unsigned int allow_unsupported_sfp; |
140 | module_param(allow_unsupported_sfp, uint, 0); | |
141 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
142 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
143 | ||
b3f4d599 | 144 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
145 | static int debug = -1; | |
146 | module_param(debug, int, 0); | |
147 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
148 | ||
9a799d71 AK |
149 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
150 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
151 | MODULE_LICENSE("GPL"); | |
152 | MODULE_VERSION(DRV_VERSION); | |
153 | ||
7086400d AD |
154 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
155 | { | |
156 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
157 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) | |
158 | schedule_work(&adapter->service_task); | |
159 | } | |
160 | ||
161 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) | |
162 | { | |
163 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
164 | ||
52f33af8 | 165 | /* flush memory to make sure state is correct before next watchdog */ |
7086400d AD |
166 | smp_mb__before_clear_bit(); |
167 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
168 | } | |
169 | ||
dcd79aeb TI |
170 | struct ixgbe_reg_info { |
171 | u32 ofs; | |
172 | char *name; | |
173 | }; | |
174 | ||
175 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
176 | ||
177 | /* General Registers */ | |
178 | {IXGBE_CTRL, "CTRL"}, | |
179 | {IXGBE_STATUS, "STATUS"}, | |
180 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
181 | ||
182 | /* Interrupt Registers */ | |
183 | {IXGBE_EICR, "EICR"}, | |
184 | ||
185 | /* RX Registers */ | |
186 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
187 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
188 | {IXGBE_RDLEN(0), "RDLEN"}, | |
189 | {IXGBE_RDH(0), "RDH"}, | |
190 | {IXGBE_RDT(0), "RDT"}, | |
191 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
192 | {IXGBE_RDBAL(0), "RDBAL"}, | |
193 | {IXGBE_RDBAH(0), "RDBAH"}, | |
194 | ||
195 | /* TX Registers */ | |
196 | {IXGBE_TDBAL(0), "TDBAL"}, | |
197 | {IXGBE_TDBAH(0), "TDBAH"}, | |
198 | {IXGBE_TDLEN(0), "TDLEN"}, | |
199 | {IXGBE_TDH(0), "TDH"}, | |
200 | {IXGBE_TDT(0), "TDT"}, | |
201 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
202 | ||
203 | /* List Terminator */ | |
204 | {} | |
205 | }; | |
206 | ||
207 | ||
208 | /* | |
209 | * ixgbe_regdump - register printout routine | |
210 | */ | |
211 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
212 | { | |
213 | int i = 0, j = 0; | |
214 | char rname[16]; | |
215 | u32 regs[64]; | |
216 | ||
217 | switch (reginfo->ofs) { | |
218 | case IXGBE_SRRCTL(0): | |
219 | for (i = 0; i < 64; i++) | |
220 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
221 | break; | |
222 | case IXGBE_DCA_RXCTRL(0): | |
223 | for (i = 0; i < 64; i++) | |
224 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
225 | break; | |
226 | case IXGBE_RDLEN(0): | |
227 | for (i = 0; i < 64; i++) | |
228 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
229 | break; | |
230 | case IXGBE_RDH(0): | |
231 | for (i = 0; i < 64; i++) | |
232 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
233 | break; | |
234 | case IXGBE_RDT(0): | |
235 | for (i = 0; i < 64; i++) | |
236 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
237 | break; | |
238 | case IXGBE_RXDCTL(0): | |
239 | for (i = 0; i < 64; i++) | |
240 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
241 | break; | |
242 | case IXGBE_RDBAL(0): | |
243 | for (i = 0; i < 64; i++) | |
244 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
245 | break; | |
246 | case IXGBE_RDBAH(0): | |
247 | for (i = 0; i < 64; i++) | |
248 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
249 | break; | |
250 | case IXGBE_TDBAL(0): | |
251 | for (i = 0; i < 64; i++) | |
252 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
253 | break; | |
254 | case IXGBE_TDBAH(0): | |
255 | for (i = 0; i < 64; i++) | |
256 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
257 | break; | |
258 | case IXGBE_TDLEN(0): | |
259 | for (i = 0; i < 64; i++) | |
260 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
261 | break; | |
262 | case IXGBE_TDH(0): | |
263 | for (i = 0; i < 64; i++) | |
264 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
265 | break; | |
266 | case IXGBE_TDT(0): | |
267 | for (i = 0; i < 64; i++) | |
268 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
269 | break; | |
270 | case IXGBE_TXDCTL(0): | |
271 | for (i = 0; i < 64; i++) | |
272 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
273 | break; | |
274 | default: | |
c7689578 | 275 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
276 | IXGBE_READ_REG(hw, reginfo->ofs)); |
277 | return; | |
278 | } | |
279 | ||
280 | for (i = 0; i < 8; i++) { | |
281 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 282 | pr_err("%-15s", rname); |
dcd79aeb | 283 | for (j = 0; j < 8; j++) |
c7689578 JP |
284 | pr_cont(" %08x", regs[i*8+j]); |
285 | pr_cont("\n"); | |
dcd79aeb TI |
286 | } |
287 | ||
288 | } | |
289 | ||
290 | /* | |
291 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
292 | */ | |
293 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
294 | { | |
295 | struct net_device *netdev = adapter->netdev; | |
296 | struct ixgbe_hw *hw = &adapter->hw; | |
297 | struct ixgbe_reg_info *reginfo; | |
298 | int n = 0; | |
299 | struct ixgbe_ring *tx_ring; | |
729739b7 | 300 | struct ixgbe_tx_buffer *tx_buffer; |
dcd79aeb TI |
301 | union ixgbe_adv_tx_desc *tx_desc; |
302 | struct my_u0 { u64 a; u64 b; } *u0; | |
303 | struct ixgbe_ring *rx_ring; | |
304 | union ixgbe_adv_rx_desc *rx_desc; | |
305 | struct ixgbe_rx_buffer *rx_buffer_info; | |
306 | u32 staterr; | |
307 | int i = 0; | |
308 | ||
309 | if (!netif_msg_hw(adapter)) | |
310 | return; | |
311 | ||
312 | /* Print netdevice Info */ | |
313 | if (netdev) { | |
314 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 315 | pr_info("Device Name state " |
dcd79aeb | 316 | "trans_start last_rx\n"); |
c7689578 JP |
317 | pr_info("%-15s %016lX %016lX %016lX\n", |
318 | netdev->name, | |
319 | netdev->state, | |
320 | netdev->trans_start, | |
321 | netdev->last_rx); | |
dcd79aeb TI |
322 | } |
323 | ||
324 | /* Print Registers */ | |
325 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 326 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
327 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
328 | reginfo->name; reginfo++) { | |
329 | ixgbe_regdump(hw, reginfo); | |
330 | } | |
331 | ||
332 | /* Print TX Ring Summary */ | |
333 | if (!netdev || !netif_running(netdev)) | |
334 | goto exit; | |
335 | ||
336 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 337 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
338 | for (n = 0; n < adapter->num_tx_queues; n++) { |
339 | tx_ring = adapter->tx_ring[n]; | |
729739b7 | 340 | tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
d3d00239 | 341 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
dcd79aeb | 342 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
729739b7 AD |
343 | (u64)dma_unmap_addr(tx_buffer, dma), |
344 | dma_unmap_len(tx_buffer, len), | |
345 | tx_buffer->next_to_watch, | |
346 | (u64)tx_buffer->time_stamp); | |
dcd79aeb TI |
347 | } |
348 | ||
349 | /* Print TX Rings */ | |
350 | if (!netif_msg_tx_done(adapter)) | |
351 | goto rx_ring_summary; | |
352 | ||
353 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
354 | ||
355 | /* Transmit Descriptor Formats | |
356 | * | |
357 | * Advanced Transmit Descriptor | |
358 | * +--------------------------------------------------------------+ | |
359 | * 0 | Buffer Address [63:0] | | |
360 | * +--------------------------------------------------------------+ | |
361 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
362 | * +--------------------------------------------------------------+ | |
363 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
364 | */ | |
365 | ||
366 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
367 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
368 | pr_info("------------------------------------\n"); |
369 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
370 | pr_info("------------------------------------\n"); | |
371 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
372 | "[PlPOIdStDDt Ln] [bi->dma ] " |
373 | "leng ntw timestamp bi->skb\n"); | |
374 | ||
375 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
e4f74028 | 376 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 377 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
dcd79aeb | 378 | u0 = (struct my_u0 *)tx_desc; |
c7689578 | 379 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
d3d00239 | 380 | " %04X %p %016llX %p", i, |
dcd79aeb TI |
381 | le64_to_cpu(u0->a), |
382 | le64_to_cpu(u0->b), | |
729739b7 AD |
383 | (u64)dma_unmap_addr(tx_buffer, dma), |
384 | dma_unmap_len(tx_buffer, len), | |
385 | tx_buffer->next_to_watch, | |
386 | (u64)tx_buffer->time_stamp, | |
387 | tx_buffer->skb); | |
dcd79aeb TI |
388 | if (i == tx_ring->next_to_use && |
389 | i == tx_ring->next_to_clean) | |
c7689578 | 390 | pr_cont(" NTC/U\n"); |
dcd79aeb | 391 | else if (i == tx_ring->next_to_use) |
c7689578 | 392 | pr_cont(" NTU\n"); |
dcd79aeb | 393 | else if (i == tx_ring->next_to_clean) |
c7689578 | 394 | pr_cont(" NTC\n"); |
dcd79aeb | 395 | else |
c7689578 | 396 | pr_cont("\n"); |
dcd79aeb TI |
397 | |
398 | if (netif_msg_pktdata(adapter) && | |
729739b7 | 399 | dma_unmap_len(tx_buffer, len) != 0) |
dcd79aeb TI |
400 | print_hex_dump(KERN_INFO, "", |
401 | DUMP_PREFIX_ADDRESS, 16, 1, | |
729739b7 AD |
402 | phys_to_virt(dma_unmap_addr(tx_buffer, |
403 | dma)), | |
404 | dma_unmap_len(tx_buffer, len), | |
405 | true); | |
dcd79aeb TI |
406 | } |
407 | } | |
408 | ||
409 | /* Print RX Rings Summary */ | |
410 | rx_ring_summary: | |
411 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 412 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
413 | for (n = 0; n < adapter->num_rx_queues; n++) { |
414 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
415 | pr_info("%5d %5X %5X\n", |
416 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
417 | } |
418 | ||
419 | /* Print RX Rings */ | |
420 | if (!netif_msg_rx_status(adapter)) | |
421 | goto exit; | |
422 | ||
423 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
424 | ||
425 | /* Advanced Receive Descriptor (Read) Format | |
426 | * 63 1 0 | |
427 | * +-----------------------------------------------------+ | |
428 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
429 | * +----------------------------------------------+------+ | |
430 | * 8 | Header Buffer Address [63:1] | DD | | |
431 | * +-----------------------------------------------------+ | |
432 | * | |
433 | * | |
434 | * Advanced Receive Descriptor (Write-Back) Format | |
435 | * | |
436 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
437 | * +------------------------------------------------------+ | |
438 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
439 | * | Checksum Ident | | | | Type | Type | | |
440 | * +------------------------------------------------------+ | |
441 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
442 | * +------------------------------------------------------+ | |
443 | * 63 48 47 32 31 20 19 0 | |
444 | */ | |
445 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
446 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
447 | pr_info("------------------------------------\n"); |
448 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
449 | pr_info("------------------------------------\n"); | |
450 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
451 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
452 | "<-- Adv Rx Read format\n"); | |
c7689578 | 453 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
454 | "[vl er S cks ln] ---------------- [bi->skb] " |
455 | "<-- Adv Rx Write-Back format\n"); | |
456 | ||
457 | for (i = 0; i < rx_ring->count; i++) { | |
458 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
e4f74028 | 459 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb TI |
460 | u0 = (struct my_u0 *)rx_desc; |
461 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
462 | if (staterr & IXGBE_RXD_STAT_DD) { | |
463 | /* Descriptor Done */ | |
c7689578 | 464 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
465 | "%016llX ---------------- %p", i, |
466 | le64_to_cpu(u0->a), | |
467 | le64_to_cpu(u0->b), | |
468 | rx_buffer_info->skb); | |
469 | } else { | |
c7689578 | 470 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
471 | "%016llX %016llX %p", i, |
472 | le64_to_cpu(u0->a), | |
473 | le64_to_cpu(u0->b), | |
474 | (u64)rx_buffer_info->dma, | |
475 | rx_buffer_info->skb); | |
476 | ||
477 | if (netif_msg_pktdata(adapter)) { | |
478 | print_hex_dump(KERN_INFO, "", | |
479 | DUMP_PREFIX_ADDRESS, 16, 1, | |
480 | phys_to_virt(rx_buffer_info->dma), | |
f800326d | 481 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
482 | } |
483 | } | |
484 | ||
485 | if (i == rx_ring->next_to_use) | |
c7689578 | 486 | pr_cont(" NTU\n"); |
dcd79aeb | 487 | else if (i == rx_ring->next_to_clean) |
c7689578 | 488 | pr_cont(" NTC\n"); |
dcd79aeb | 489 | else |
c7689578 | 490 | pr_cont("\n"); |
dcd79aeb TI |
491 | |
492 | } | |
493 | } | |
494 | ||
495 | exit: | |
496 | return; | |
497 | } | |
498 | ||
5eba3699 AV |
499 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
500 | { | |
501 | u32 ctrl_ext; | |
502 | ||
503 | /* Let firmware take over control of h/w */ | |
504 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
505 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 506 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
507 | } |
508 | ||
509 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
510 | { | |
511 | u32 ctrl_ext; | |
512 | ||
513 | /* Let firmware know the driver has taken over */ | |
514 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
515 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 516 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 517 | } |
9a799d71 | 518 | |
e8e26350 PW |
519 | /* |
520 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
521 | * @adapter: pointer to adapter struct | |
522 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
523 | * @queue: queue to map the corresponding interrupt to | |
524 | * @msix_vector: the vector to map to the corresponding queue | |
525 | * | |
526 | */ | |
527 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 528 | u8 queue, u8 msix_vector) |
9a799d71 AK |
529 | { |
530 | u32 ivar, index; | |
e8e26350 PW |
531 | struct ixgbe_hw *hw = &adapter->hw; |
532 | switch (hw->mac.type) { | |
533 | case ixgbe_mac_82598EB: | |
534 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
535 | if (direction == -1) | |
536 | direction = 0; | |
537 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
538 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
539 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
540 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
541 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
542 | break; | |
543 | case ixgbe_mac_82599EB: | |
b93a2226 | 544 | case ixgbe_mac_X540: |
e8e26350 PW |
545 | if (direction == -1) { |
546 | /* other causes */ | |
547 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
548 | index = ((queue & 1) * 8); | |
549 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
550 | ivar &= ~(0xFF << index); | |
551 | ivar |= (msix_vector << index); | |
552 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
553 | break; | |
554 | } else { | |
555 | /* tx or rx causes */ | |
556 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
557 | index = ((16 * (queue & 1)) + (8 * direction)); | |
558 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
559 | ivar &= ~(0xFF << index); | |
560 | ivar |= (msix_vector << index); | |
561 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
562 | break; | |
563 | } | |
564 | default: | |
565 | break; | |
566 | } | |
9a799d71 AK |
567 | } |
568 | ||
fe49f04a | 569 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 570 | u64 qmask) |
fe49f04a AD |
571 | { |
572 | u32 mask; | |
573 | ||
bd508178 AD |
574 | switch (adapter->hw.mac.type) { |
575 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
576 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
577 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
578 | break; |
579 | case ixgbe_mac_82599EB: | |
b93a2226 | 580 | case ixgbe_mac_X540: |
fe49f04a AD |
581 | mask = (qmask & 0xFFFFFFFF); |
582 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
583 | mask = (qmask >> 32); | |
584 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
585 | break; |
586 | default: | |
587 | break; | |
fe49f04a AD |
588 | } |
589 | } | |
590 | ||
729739b7 AD |
591 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, |
592 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 593 | { |
729739b7 AD |
594 | if (tx_buffer->skb) { |
595 | dev_kfree_skb_any(tx_buffer->skb); | |
596 | if (dma_unmap_len(tx_buffer, len)) | |
d3d00239 | 597 | dma_unmap_single(ring->dev, |
729739b7 AD |
598 | dma_unmap_addr(tx_buffer, dma), |
599 | dma_unmap_len(tx_buffer, len), | |
600 | DMA_TO_DEVICE); | |
601 | } else if (dma_unmap_len(tx_buffer, len)) { | |
602 | dma_unmap_page(ring->dev, | |
603 | dma_unmap_addr(tx_buffer, dma), | |
604 | dma_unmap_len(tx_buffer, len), | |
605 | DMA_TO_DEVICE); | |
e5a43549 | 606 | } |
729739b7 AD |
607 | tx_buffer->next_to_watch = NULL; |
608 | tx_buffer->skb = NULL; | |
609 | dma_unmap_len_set(tx_buffer, len, 0); | |
610 | /* tx_buffer must be completely set up in the transmit path */ | |
9a799d71 AK |
611 | } |
612 | ||
943561d3 | 613 | static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) |
c84d324c JF |
614 | { |
615 | struct ixgbe_hw *hw = &adapter->hw; | |
616 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
c84d324c | 617 | int i; |
943561d3 | 618 | u32 data; |
c84d324c | 619 | |
943561d3 AD |
620 | if ((hw->fc.current_mode != ixgbe_fc_full) && |
621 | (hw->fc.current_mode != ixgbe_fc_rx_pause)) | |
622 | return; | |
c84d324c | 623 | |
943561d3 AD |
624 | switch (hw->mac.type) { |
625 | case ixgbe_mac_82598EB: | |
626 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
627 | break; | |
628 | default: | |
629 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
630 | } | |
631 | hwstats->lxoffrxc += data; | |
c84d324c | 632 | |
943561d3 AD |
633 | /* refill credits (no tx hang) if we received xoff */ |
634 | if (!data) | |
c84d324c | 635 | return; |
943561d3 AD |
636 | |
637 | for (i = 0; i < adapter->num_tx_queues; i++) | |
638 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
639 | &adapter->tx_ring[i]->state); | |
640 | } | |
641 | ||
642 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
643 | { | |
644 | struct ixgbe_hw *hw = &adapter->hw; | |
645 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
646 | u32 xoff[8] = {0}; | |
647 | int i; | |
648 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
649 | ||
650 | if (adapter->ixgbe_ieee_pfc) | |
651 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
652 | ||
653 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { | |
654 | ixgbe_update_xoff_rx_lfc(adapter); | |
c84d324c | 655 | return; |
943561d3 | 656 | } |
c84d324c JF |
657 | |
658 | /* update stats for each tc, only valid with PFC enabled */ | |
659 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
660 | switch (hw->mac.type) { | |
661 | case ixgbe_mac_82598EB: | |
662 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 663 | break; |
c84d324c JF |
664 | default: |
665 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 666 | } |
c84d324c JF |
667 | hwstats->pxoffrxc[i] += xoff[i]; |
668 | } | |
669 | ||
670 | /* disarm tx queues that have received xoff frames */ | |
671 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
672 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
fb5475ff | 673 | u8 tc = tx_ring->dcb_tc; |
c84d324c JF |
674 | |
675 | if (xoff[tc]) | |
676 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 677 | } |
26f23d82 YZ |
678 | } |
679 | ||
c84d324c | 680 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 681 | { |
7d7ce682 | 682 | return ring->stats.packets; |
c84d324c JF |
683 | } |
684 | ||
685 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
686 | { | |
687 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 688 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 689 | |
c84d324c JF |
690 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
691 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
692 | ||
693 | if (head != tail) | |
694 | return (head < tail) ? | |
695 | tail - head : (tail + ring->count - head); | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
701 | { | |
702 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
703 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
704 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
705 | bool ret = false; | |
706 | ||
7d637bcc | 707 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
708 | |
709 | /* | |
710 | * Check for a hung queue, but be thorough. This verifies | |
711 | * that a transmit has been completed since the previous | |
712 | * check AND there is at least one packet pending. The | |
713 | * ARMED bit is set to indicate a potential hang. The | |
714 | * bit is cleared if a pause frame is received to remove | |
715 | * false hang detection due to PFC or 802.3x frames. By | |
716 | * requiring this to fail twice we avoid races with | |
717 | * pfc clearing the ARMED bit and conditions where we | |
718 | * run the check_tx_hang logic with a transmit completion | |
719 | * pending but without time to complete it yet. | |
720 | */ | |
721 | if ((tx_done_old == tx_done) && tx_pending) { | |
722 | /* make sure it is true for two checks in a row */ | |
723 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
724 | &tx_ring->state); | |
725 | } else { | |
726 | /* update completed stats and continue */ | |
727 | tx_ring->tx_stats.tx_done_old = tx_done; | |
728 | /* reset the countdown */ | |
729 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
730 | } |
731 | ||
c84d324c | 732 | return ret; |
9a799d71 AK |
733 | } |
734 | ||
c83c6cbd AD |
735 | /** |
736 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
737 | * @adapter: driver private struct | |
738 | **/ | |
739 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
740 | { | |
741 | ||
742 | /* Do the reset outside of interrupt context */ | |
743 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
744 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
745 | ixgbe_service_event_schedule(adapter); | |
746 | } | |
747 | } | |
e01c31a5 | 748 | |
9a799d71 AK |
749 | /** |
750 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 751 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 752 | * @tx_ring: tx ring to clean |
9a799d71 | 753 | **/ |
fe49f04a | 754 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 755 | struct ixgbe_ring *tx_ring) |
9a799d71 | 756 | { |
fe49f04a | 757 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
758 | struct ixgbe_tx_buffer *tx_buffer; |
759 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 760 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 761 | unsigned int budget = q_vector->tx.work_limit; |
729739b7 AD |
762 | unsigned int i = tx_ring->next_to_clean; |
763 | ||
764 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
765 | return true; | |
9a799d71 | 766 | |
d3d00239 | 767 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 768 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 769 | i -= tx_ring->count; |
12207e49 | 770 | |
729739b7 | 771 | do { |
d3d00239 AD |
772 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
773 | ||
774 | /* if next_to_watch is not set then there is no work pending */ | |
775 | if (!eop_desc) | |
776 | break; | |
777 | ||
7f83a9e6 AD |
778 | /* prevent any other reads prior to eop_desc */ |
779 | rmb(); | |
780 | ||
d3d00239 AD |
781 | /* if DD is not set pending work has not been completed */ |
782 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
783 | break; | |
8ad494b0 | 784 | |
d3d00239 AD |
785 | /* clear next_to_watch to prevent false hangs */ |
786 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 787 | |
091a6246 AD |
788 | /* update the statistics for this packet */ |
789 | total_bytes += tx_buffer->bytecount; | |
790 | total_packets += tx_buffer->gso_segs; | |
791 | ||
fd0db0ed AD |
792 | /* free the skb */ |
793 | dev_kfree_skb_any(tx_buffer->skb); | |
794 | ||
729739b7 AD |
795 | /* unmap skb header data */ |
796 | dma_unmap_single(tx_ring->dev, | |
797 | dma_unmap_addr(tx_buffer, dma), | |
798 | dma_unmap_len(tx_buffer, len), | |
799 | DMA_TO_DEVICE); | |
800 | ||
fd0db0ed AD |
801 | /* clear tx_buffer data */ |
802 | tx_buffer->skb = NULL; | |
729739b7 | 803 | dma_unmap_len_set(tx_buffer, len, 0); |
fd0db0ed | 804 | |
729739b7 AD |
805 | /* unmap remaining buffers */ |
806 | while (tx_desc != eop_desc) { | |
d3d00239 AD |
807 | tx_buffer++; |
808 | tx_desc++; | |
8ad494b0 | 809 | i++; |
729739b7 AD |
810 | if (unlikely(!i)) { |
811 | i -= tx_ring->count; | |
d3d00239 | 812 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 813 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 814 | } |
e01c31a5 | 815 | |
729739b7 AD |
816 | /* unmap any remaining paged data */ |
817 | if (dma_unmap_len(tx_buffer, len)) { | |
818 | dma_unmap_page(tx_ring->dev, | |
819 | dma_unmap_addr(tx_buffer, dma), | |
820 | dma_unmap_len(tx_buffer, len), | |
821 | DMA_TO_DEVICE); | |
822 | dma_unmap_len_set(tx_buffer, len, 0); | |
823 | } | |
824 | } | |
825 | ||
826 | /* move us one more past the eop_desc for start of next pkt */ | |
827 | tx_buffer++; | |
828 | tx_desc++; | |
829 | i++; | |
830 | if (unlikely(!i)) { | |
831 | i -= tx_ring->count; | |
832 | tx_buffer = tx_ring->tx_buffer_info; | |
833 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
834 | } | |
835 | ||
836 | /* issue prefetch for next Tx descriptor */ | |
837 | prefetch(tx_desc); | |
12207e49 | 838 | |
729739b7 AD |
839 | /* update budget accounting */ |
840 | budget--; | |
841 | } while (likely(budget)); | |
842 | ||
843 | i += tx_ring->count; | |
9a799d71 | 844 | tx_ring->next_to_clean = i; |
d3d00239 | 845 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 846 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 847 | tx_ring->stats.packets += total_packets; |
d3d00239 | 848 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
849 | q_vector->tx.total_bytes += total_bytes; |
850 | q_vector->tx.total_packets += total_packets; | |
b953799e | 851 | |
c84d324c JF |
852 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
853 | /* schedule immediate reset if we believe we hung */ | |
854 | struct ixgbe_hw *hw = &adapter->hw; | |
c84d324c JF |
855 | e_err(drv, "Detected Tx Unit Hang\n" |
856 | " Tx Queue <%d>\n" | |
857 | " TDH, TDT <%x>, <%x>\n" | |
858 | " next_to_use <%x>\n" | |
859 | " next_to_clean <%x>\n" | |
860 | "tx_buffer_info[next_to_clean]\n" | |
861 | " time_stamp <%lx>\n" | |
862 | " jiffies <%lx>\n", | |
863 | tx_ring->queue_index, | |
864 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
865 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
866 | tx_ring->next_to_use, i, |
867 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
868 | |
869 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
870 | ||
871 | e_info(probe, | |
872 | "tx hang %d detected on queue %d, resetting adapter\n", | |
873 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
874 | ||
b953799e | 875 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 876 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
877 | |
878 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 879 | return true; |
b953799e | 880 | } |
9a799d71 | 881 | |
b2d96e0a AD |
882 | netdev_tx_completed_queue(txring_txq(tx_ring), |
883 | total_packets, total_bytes); | |
884 | ||
e092be60 | 885 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 886 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 887 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
888 | /* Make sure that anybody stopping the queue after this |
889 | * sees the new next_to_clean. | |
890 | */ | |
891 | smp_mb(); | |
729739b7 AD |
892 | if (__netif_subqueue_stopped(tx_ring->netdev, |
893 | tx_ring->queue_index) | |
894 | && !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
895 | netif_wake_subqueue(tx_ring->netdev, | |
896 | tx_ring->queue_index); | |
5b7da515 | 897 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 898 | } |
e092be60 | 899 | } |
9a799d71 | 900 | |
59224555 | 901 | return !!budget; |
9a799d71 AK |
902 | } |
903 | ||
5dd2d332 | 904 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
905 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
906 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 907 | int cpu) |
bd0362dd | 908 | { |
33cf09c9 | 909 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
910 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); |
911 | u16 reg_offset; | |
33cf09c9 | 912 | |
33cf09c9 AD |
913 | switch (hw->mac.type) { |
914 | case ixgbe_mac_82598EB: | |
bdda1a61 | 915 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
916 | break; |
917 | case ixgbe_mac_82599EB: | |
b93a2226 | 918 | case ixgbe_mac_X540: |
bdda1a61 AD |
919 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
920 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
921 | break; |
922 | default: | |
bdda1a61 AD |
923 | /* for unknown hardware do not write register */ |
924 | return; | |
bd0362dd | 925 | } |
bdda1a61 AD |
926 | |
927 | /* | |
928 | * We can enable relaxed ordering for reads, but not writes when | |
929 | * DCA is enabled. This is due to a known issue in some chipsets | |
930 | * which will cause the DCA tag to be cleared. | |
931 | */ | |
932 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
933 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
934 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
935 | ||
936 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
937 | } |
938 | ||
bdda1a61 AD |
939 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
940 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 941 | int cpu) |
bd0362dd | 942 | { |
33cf09c9 | 943 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
944 | u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); |
945 | u8 reg_idx = rx_ring->reg_idx; | |
946 | ||
33cf09c9 AD |
947 | |
948 | switch (hw->mac.type) { | |
33cf09c9 | 949 | case ixgbe_mac_82599EB: |
b93a2226 | 950 | case ixgbe_mac_X540: |
bdda1a61 | 951 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
952 | break; |
953 | default: | |
954 | break; | |
955 | } | |
bdda1a61 AD |
956 | |
957 | /* | |
958 | * We can enable relaxed ordering for reads, but not writes when | |
959 | * DCA is enabled. This is due to a known issue in some chipsets | |
960 | * which will cause the DCA tag to be cleared. | |
961 | */ | |
962 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
963 | IXGBE_DCA_RXCTRL_DATA_DCA_EN | | |
964 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; | |
965 | ||
966 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
967 | } |
968 | ||
969 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
970 | { | |
971 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 972 | struct ixgbe_ring *ring; |
bd0362dd | 973 | int cpu = get_cpu(); |
bd0362dd | 974 | |
33cf09c9 AD |
975 | if (q_vector->cpu == cpu) |
976 | goto out_no_update; | |
977 | ||
a557928e | 978 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 979 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 980 | |
a557928e | 981 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 982 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
983 | |
984 | q_vector->cpu = cpu; | |
985 | out_no_update: | |
bd0362dd JC |
986 | put_cpu(); |
987 | } | |
988 | ||
989 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
990 | { | |
33cf09c9 | 991 | int num_q_vectors; |
bd0362dd JC |
992 | int i; |
993 | ||
994 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
995 | return; | |
996 | ||
e35ec126 AD |
997 | /* always use CB2 mode, difference is masked in the CB driver */ |
998 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
999 | ||
33cf09c9 AD |
1000 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
1001 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1002 | else | |
1003 | num_q_vectors = 1; | |
1004 | ||
1005 | for (i = 0; i < num_q_vectors; i++) { | |
1006 | adapter->q_vector[i]->cpu = -1; | |
1007 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1008 | } |
1009 | } | |
1010 | ||
1011 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1012 | { | |
c60fbb00 | 1013 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1014 | unsigned long event = *(unsigned long *)data; |
1015 | ||
2a72c31e | 1016 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
1017 | return 0; |
1018 | ||
bd0362dd JC |
1019 | switch (event) { |
1020 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1021 | /* if we're already enabled, don't do it again */ |
1022 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1023 | break; | |
652f093f | 1024 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1025 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1026 | ixgbe_setup_dca(adapter); |
1027 | break; | |
1028 | } | |
1029 | /* Fall Through since DCA is disabled. */ | |
1030 | case DCA_PROVIDER_REMOVE: | |
1031 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1032 | dca_remove_requester(dev); | |
1033 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1034 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1035 | } | |
1036 | break; | |
1037 | } | |
1038 | ||
652f093f | 1039 | return 0; |
bd0362dd | 1040 | } |
67a74ee2 | 1041 | |
bdda1a61 | 1042 | #endif /* CONFIG_IXGBE_DCA */ |
8a0da21b AD |
1043 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
1044 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
1045 | struct sk_buff *skb) |
1046 | { | |
8a0da21b AD |
1047 | if (ring->netdev->features & NETIF_F_RXHASH) |
1048 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
67a74ee2 ET |
1049 | } |
1050 | ||
f800326d | 1051 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1052 | /** |
1053 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
1054 | * @adapter: address of board private structure | |
1055 | * @rx_desc: advanced rx descriptor | |
1056 | * | |
1057 | * Returns : true if it is FCoE pkt | |
1058 | */ | |
1059 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter, | |
1060 | union ixgbe_adv_rx_desc *rx_desc) | |
1061 | { | |
1062 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1063 | ||
1064 | return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
1065 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == | |
1066 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1067 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1068 | } | |
1069 | ||
f800326d | 1070 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1071 | /** |
1072 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1073 | * @ring: structure containing ring specific data |
1074 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1075 | * @skb: skb currently being received and modified |
1076 | **/ | |
8a0da21b | 1077 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1078 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1079 | struct sk_buff *skb) |
9a799d71 | 1080 | { |
8a0da21b | 1081 | skb_checksum_none_assert(skb); |
9a799d71 | 1082 | |
712744be | 1083 | /* Rx csum disabled */ |
8a0da21b | 1084 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1085 | return; |
e59bd25d AV |
1086 | |
1087 | /* if IP and error */ | |
f56e0cb1 AD |
1088 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1089 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1090 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1091 | return; |
1092 | } | |
e59bd25d | 1093 | |
f56e0cb1 | 1094 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1095 | return; |
1096 | ||
f56e0cb1 | 1097 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
f800326d | 1098 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
8bae1b2b DS |
1099 | |
1100 | /* | |
1101 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1102 | * checksum errors. | |
1103 | */ | |
8a0da21b AD |
1104 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1105 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1106 | return; |
1107 | ||
8a0da21b | 1108 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1109 | return; |
1110 | } | |
1111 | ||
9a799d71 | 1112 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1113 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1114 | } |
1115 | ||
84ea2591 | 1116 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 | 1117 | { |
f56e0cb1 | 1118 | rx_ring->next_to_use = val; |
f800326d AD |
1119 | |
1120 | /* update next to alloc since we have filled the ring */ | |
1121 | rx_ring->next_to_alloc = val; | |
e8e26350 PW |
1122 | /* |
1123 | * Force memory writes to complete before letting h/w | |
1124 | * know there are new descriptors to fetch. (Only | |
1125 | * applicable for weak-ordered memory model archs, | |
1126 | * such as IA-64). | |
1127 | */ | |
1128 | wmb(); | |
84ea2591 | 1129 | writel(val, rx_ring->tail); |
e8e26350 PW |
1130 | } |
1131 | ||
f990b79b AD |
1132 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1133 | struct ixgbe_rx_buffer *bi) | |
1134 | { | |
1135 | struct page *page = bi->page; | |
f800326d | 1136 | dma_addr_t dma = bi->dma; |
f990b79b | 1137 | |
f800326d AD |
1138 | /* since we are recycling buffers we should seldom need to alloc */ |
1139 | if (likely(dma)) | |
f990b79b AD |
1140 | return true; |
1141 | ||
f800326d AD |
1142 | /* alloc new page for storage */ |
1143 | if (likely(!page)) { | |
1144 | page = alloc_pages(GFP_ATOMIC | __GFP_COLD, | |
1145 | ixgbe_rx_pg_order(rx_ring)); | |
f990b79b AD |
1146 | if (unlikely(!page)) { |
1147 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1148 | return false; | |
1149 | } | |
f800326d | 1150 | bi->page = page; |
f990b79b AD |
1151 | } |
1152 | ||
f800326d AD |
1153 | /* map page for use */ |
1154 | dma = dma_map_page(rx_ring->dev, page, 0, | |
1155 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1156 | ||
1157 | /* | |
1158 | * if mapping failed free memory back to system since | |
1159 | * there isn't much point in holding memory we can't use | |
1160 | */ | |
1161 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
dd411ec4 | 1162 | __free_pages(page, ixgbe_rx_pg_order(rx_ring)); |
f800326d | 1163 | bi->page = NULL; |
f990b79b | 1164 | |
f990b79b AD |
1165 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1166 | return false; | |
1167 | } | |
1168 | ||
f800326d AD |
1169 | bi->dma = dma; |
1170 | bi->page_offset ^= ixgbe_rx_bufsz(rx_ring); | |
1171 | ||
f990b79b AD |
1172 | return true; |
1173 | } | |
1174 | ||
9a799d71 | 1175 | /** |
f990b79b | 1176 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1177 | * @rx_ring: ring to place buffers on |
1178 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1179 | **/ |
fc77dc3c | 1180 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1181 | { |
9a799d71 | 1182 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1183 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1184 | u16 i = rx_ring->next_to_use; |
9a799d71 | 1185 | |
f800326d AD |
1186 | /* nothing to do */ |
1187 | if (!cleaned_count) | |
fc77dc3c AD |
1188 | return; |
1189 | ||
e4f74028 | 1190 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1191 | bi = &rx_ring->rx_buffer_info[i]; |
1192 | i -= rx_ring->count; | |
9a799d71 | 1193 | |
f800326d AD |
1194 | do { |
1195 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1196 | break; |
d5f398ed | 1197 | |
f800326d AD |
1198 | /* |
1199 | * Refresh the desc even if buffer_addrs didn't change | |
1200 | * because each write-back erases this info. | |
1201 | */ | |
1202 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1203 | |
f990b79b AD |
1204 | rx_desc++; |
1205 | bi++; | |
9a799d71 | 1206 | i++; |
f990b79b | 1207 | if (unlikely(!i)) { |
e4f74028 | 1208 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1209 | bi = rx_ring->rx_buffer_info; |
1210 | i -= rx_ring->count; | |
1211 | } | |
1212 | ||
1213 | /* clear the hdr_addr for the next_to_use descriptor */ | |
1214 | rx_desc->read.hdr_addr = 0; | |
f800326d AD |
1215 | |
1216 | cleaned_count--; | |
1217 | } while (cleaned_count); | |
7c6e0a43 | 1218 | |
f990b79b AD |
1219 | i += rx_ring->count; |
1220 | ||
f56e0cb1 | 1221 | if (rx_ring->next_to_use != i) |
84ea2591 | 1222 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1223 | } |
1224 | ||
1d2024f6 AD |
1225 | /** |
1226 | * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE | |
1227 | * @data: pointer to the start of the headers | |
1228 | * @max_len: total length of section to find headers in | |
1229 | * | |
1230 | * This function is meant to determine the length of headers that will | |
1231 | * be recognized by hardware for LRO, GRO, and RSC offloads. The main | |
1232 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
1233 | * packets so that we can do basic things like calculating the gso_size | |
1234 | * based on the average data per packet. | |
1235 | **/ | |
1236 | static unsigned int ixgbe_get_headlen(unsigned char *data, | |
1237 | unsigned int max_len) | |
1238 | { | |
1239 | union { | |
1240 | unsigned char *network; | |
1241 | /* l2 headers */ | |
1242 | struct ethhdr *eth; | |
1243 | struct vlan_hdr *vlan; | |
1244 | /* l3 headers */ | |
1245 | struct iphdr *ipv4; | |
1246 | } hdr; | |
1247 | __be16 protocol; | |
1248 | u8 nexthdr = 0; /* default to not TCP */ | |
1249 | u8 hlen; | |
1250 | ||
1251 | /* this should never happen, but better safe than sorry */ | |
1252 | if (max_len < ETH_HLEN) | |
1253 | return max_len; | |
1254 | ||
1255 | /* initialize network frame pointer */ | |
1256 | hdr.network = data; | |
1257 | ||
1258 | /* set first protocol and move network header forward */ | |
1259 | protocol = hdr.eth->h_proto; | |
1260 | hdr.network += ETH_HLEN; | |
1261 | ||
1262 | /* handle any vlan tag if present */ | |
1263 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
1264 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
1265 | return max_len; | |
1266 | ||
1267 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
1268 | hdr.network += VLAN_HLEN; | |
1269 | } | |
1270 | ||
1271 | /* handle L3 protocols */ | |
1272 | if (protocol == __constant_htons(ETH_P_IP)) { | |
1273 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
1274 | return max_len; | |
1275 | ||
1276 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
1277 | hlen = (hdr.network[0] & 0x0F) << 2; | |
1278 | ||
1279 | /* verify hlen meets minimum size requirements */ | |
1280 | if (hlen < sizeof(struct iphdr)) | |
1281 | return hdr.network - data; | |
1282 | ||
1283 | /* record next protocol */ | |
1284 | nexthdr = hdr.ipv4->protocol; | |
1285 | hdr.network += hlen; | |
f800326d | 1286 | #ifdef IXGBE_FCOE |
1d2024f6 AD |
1287 | } else if (protocol == __constant_htons(ETH_P_FCOE)) { |
1288 | if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN)) | |
1289 | return max_len; | |
1290 | hdr.network += FCOE_HEADER_LEN; | |
1291 | #endif | |
1292 | } else { | |
1293 | return hdr.network - data; | |
1294 | } | |
1295 | ||
1296 | /* finally sort out TCP */ | |
1297 | if (nexthdr == IPPROTO_TCP) { | |
1298 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
1299 | return max_len; | |
1300 | ||
1301 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
1302 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
1303 | ||
1304 | /* verify hlen meets minimum size requirements */ | |
1305 | if (hlen < sizeof(struct tcphdr)) | |
1306 | return hdr.network - data; | |
1307 | ||
1308 | hdr.network += hlen; | |
1309 | } | |
1310 | ||
1311 | /* | |
1312 | * If everything has gone correctly hdr.network should be the | |
1313 | * data section of the packet and will be the end of the header. | |
1314 | * If not then it probably represents the end of the last recognized | |
1315 | * header. | |
1316 | */ | |
1317 | if ((hdr.network - data) < max_len) | |
1318 | return hdr.network - data; | |
1319 | else | |
1320 | return max_len; | |
1321 | } | |
1322 | ||
4c1975d7 AD |
1323 | static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring, |
1324 | union ixgbe_adv_rx_desc *rx_desc, | |
1325 | struct sk_buff *skb) | |
aa80175a | 1326 | { |
4c1975d7 AD |
1327 | __le32 rsc_enabled; |
1328 | u32 rsc_cnt; | |
1329 | ||
1330 | if (!ring_is_rsc_enabled(rx_ring)) | |
1331 | return; | |
1332 | ||
1333 | rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1334 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1335 | ||
1336 | /* If this is an RSC frame rsc_cnt should be non-zero */ | |
1337 | if (!rsc_enabled) | |
1338 | return; | |
1339 | ||
1340 | rsc_cnt = le32_to_cpu(rsc_enabled); | |
1341 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1342 | ||
1343 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
aa80175a | 1344 | } |
43634e82 | 1345 | |
1d2024f6 AD |
1346 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1347 | struct sk_buff *skb) | |
1348 | { | |
f800326d | 1349 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1350 | |
1351 | /* set gso_size to avoid messing up TCP MSS */ | |
1352 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1353 | IXGBE_CB(skb)->append_cnt); | |
1354 | } | |
1355 | ||
1356 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1357 | struct sk_buff *skb) | |
1358 | { | |
1359 | /* if append_cnt is 0 then frame is not RSC */ | |
1360 | if (!IXGBE_CB(skb)->append_cnt) | |
1361 | return; | |
1362 | ||
1363 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1364 | rx_ring->rx_stats.rsc_flush++; | |
1365 | ||
1366 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1367 | ||
1368 | /* gso_size is computed using append_cnt so always clear it last */ | |
1369 | IXGBE_CB(skb)->append_cnt = 0; | |
1370 | } | |
1371 | ||
8a0da21b AD |
1372 | /** |
1373 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1374 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1375 | * @rx_desc: pointer to the EOP Rx descriptor | |
1376 | * @skb: pointer to current skb being populated | |
f8212f97 | 1377 | * |
8a0da21b AD |
1378 | * This function checks the ring, descriptor, and packet information in |
1379 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1380 | * other fields within the skb. | |
f8212f97 | 1381 | **/ |
8a0da21b AD |
1382 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1383 | union ixgbe_adv_rx_desc *rx_desc, | |
1384 | struct sk_buff *skb) | |
f8212f97 | 1385 | { |
8a0da21b AD |
1386 | ixgbe_update_rsc_stats(rx_ring, skb); |
1387 | ||
1388 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1389 | |
8a0da21b AD |
1390 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1391 | ||
1392 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { | |
1393 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); | |
1394 | __vlan_hwaccel_put_tag(skb, vid); | |
f8212f97 AD |
1395 | } |
1396 | ||
8a0da21b | 1397 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1398 | |
8a0da21b | 1399 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
f8212f97 AD |
1400 | } |
1401 | ||
8a0da21b AD |
1402 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1403 | struct sk_buff *skb) | |
aa80175a | 1404 | { |
8a0da21b AD |
1405 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1406 | ||
1407 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1408 | napi_gro_receive(&q_vector->napi, skb); | |
1409 | else | |
1410 | netif_rx(skb); | |
aa80175a | 1411 | } |
43634e82 | 1412 | |
f800326d AD |
1413 | /** |
1414 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1415 | * @rx_ring: Rx ring being processed | |
1416 | * @rx_desc: Rx descriptor for current buffer | |
1417 | * @skb: Current socket buffer containing buffer in progress | |
1418 | * | |
1419 | * This function updates next to clean. If the buffer is an EOP buffer | |
1420 | * this function exits returning false, otherwise it will place the | |
1421 | * sk_buff in the next buffer to be chained and return true indicating | |
1422 | * that this is in fact a non-EOP buffer. | |
1423 | **/ | |
1424 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1425 | union ixgbe_adv_rx_desc *rx_desc, | |
1426 | struct sk_buff *skb) | |
1427 | { | |
1428 | u32 ntc = rx_ring->next_to_clean + 1; | |
1429 | ||
1430 | /* fetch, update, and store next to clean */ | |
1431 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1432 | rx_ring->next_to_clean = ntc; | |
1433 | ||
1434 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1435 | ||
1436 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1437 | return false; | |
1438 | ||
1439 | /* append_cnt indicates packet is RSC, if so fetch nextp */ | |
1440 | if (IXGBE_CB(skb)->append_cnt) { | |
1441 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1442 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1443 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1444 | } | |
1445 | ||
1446 | /* place skb in next buffer to be received */ | |
1447 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1448 | rx_ring->rx_stats.non_eop_descs++; | |
1449 | ||
1450 | return true; | |
1451 | } | |
1452 | ||
1453 | /** | |
1454 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1455 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1456 | * @rx_desc: pointer to the EOP Rx descriptor | |
1457 | * @skb: pointer to current skb being fixed | |
1458 | * | |
1459 | * Check for corrupted packet headers caused by senders on the local L2 | |
1460 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1461 | * should be very rare. | |
1462 | * | |
1463 | * Also address the case where we are pulling data in on pages only | |
1464 | * and as such no data is present in the skb header. | |
1465 | * | |
1466 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1467 | * it is large enough to qualify as a valid Ethernet frame. | |
1468 | * | |
1469 | * Returns true if an error was encountered and skb was freed. | |
1470 | **/ | |
1471 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1472 | union ixgbe_adv_rx_desc *rx_desc, | |
1473 | struct sk_buff *skb) | |
1474 | { | |
1475 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1476 | struct net_device *netdev = rx_ring->netdev; | |
1477 | unsigned char *va; | |
1478 | unsigned int pull_len; | |
1479 | ||
1480 | /* if the page was released unmap it, else just sync our portion */ | |
1481 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
1482 | dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, | |
1483 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1484 | IXGBE_CB(skb)->page_released = false; | |
1485 | } else { | |
1486 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1487 | IXGBE_CB(skb)->dma, | |
1488 | frag->page_offset, | |
1489 | ixgbe_rx_bufsz(rx_ring), | |
1490 | DMA_FROM_DEVICE); | |
1491 | } | |
1492 | IXGBE_CB(skb)->dma = 0; | |
1493 | ||
1494 | /* verify that the packet does not have any known errors */ | |
1495 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1496 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1497 | !(netdev->features & NETIF_F_RXALL))) { | |
1498 | dev_kfree_skb_any(skb); | |
1499 | return true; | |
1500 | } | |
1501 | ||
1502 | /* | |
1503 | * it is valid to use page_address instead of kmap since we are | |
1504 | * working with pages allocated out of the lomem pool per | |
1505 | * alloc_page(GFP_ATOMIC) | |
1506 | */ | |
1507 | va = skb_frag_address(frag); | |
1508 | ||
1509 | /* | |
1510 | * we need the header to contain the greater of either ETH_HLEN or | |
1511 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1512 | */ | |
1513 | pull_len = skb_frag_size(frag); | |
1514 | if (pull_len > 256) | |
1515 | pull_len = ixgbe_get_headlen(va, pull_len); | |
1516 | ||
1517 | /* align pull length to size of long to optimize memcpy performance */ | |
1518 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1519 | ||
1520 | /* update all of the pointers */ | |
1521 | skb_frag_size_sub(frag, pull_len); | |
1522 | frag->page_offset += pull_len; | |
1523 | skb->data_len -= pull_len; | |
1524 | skb->tail += pull_len; | |
1525 | ||
1526 | /* | |
1527 | * if we sucked the frag empty then we should free it, | |
1528 | * if there are other frags here something is screwed up in hardware | |
1529 | */ | |
1530 | if (skb_frag_size(frag) == 0) { | |
1531 | BUG_ON(skb_shinfo(skb)->nr_frags != 1); | |
1532 | skb_shinfo(skb)->nr_frags = 0; | |
1533 | __skb_frag_unref(frag); | |
1534 | skb->truesize -= ixgbe_rx_bufsz(rx_ring); | |
1535 | } | |
1536 | ||
1537 | /* if skb_pad returns an error the skb was freed */ | |
1538 | if (unlikely(skb->len < 60)) { | |
1539 | int pad_len = 60 - skb->len; | |
1540 | ||
1541 | if (skb_pad(skb, pad_len)) | |
1542 | return true; | |
1543 | __skb_put(skb, pad_len); | |
1544 | } | |
1545 | ||
1546 | return false; | |
1547 | } | |
1548 | ||
1549 | /** | |
1550 | * ixgbe_can_reuse_page - determine if we can reuse a page | |
1551 | * @rx_buffer: pointer to rx_buffer containing the page we want to reuse | |
1552 | * | |
1553 | * Returns true if page can be reused in another Rx buffer | |
1554 | **/ | |
1555 | static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer) | |
1556 | { | |
1557 | struct page *page = rx_buffer->page; | |
1558 | ||
1559 | /* if we are only owner of page and it is local we can reuse it */ | |
1560 | return likely(page_count(page) == 1) && | |
1561 | likely(page_to_nid(page) == numa_node_id()); | |
1562 | } | |
1563 | ||
1564 | /** | |
1565 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1566 | * @rx_ring: rx descriptor ring to store buffers on | |
1567 | * @old_buff: donor buffer to have page reused | |
1568 | * | |
1569 | * Syncronizes page for reuse by the adapter | |
1570 | **/ | |
1571 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1572 | struct ixgbe_rx_buffer *old_buff) | |
1573 | { | |
1574 | struct ixgbe_rx_buffer *new_buff; | |
1575 | u16 nta = rx_ring->next_to_alloc; | |
1576 | u16 bufsz = ixgbe_rx_bufsz(rx_ring); | |
1577 | ||
1578 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1579 | ||
1580 | /* update, and store next to alloc */ | |
1581 | nta++; | |
1582 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1583 | ||
1584 | /* transfer page from old buffer to new buffer */ | |
1585 | new_buff->page = old_buff->page; | |
1586 | new_buff->dma = old_buff->dma; | |
1587 | ||
1588 | /* flip page offset to other buffer and store to new_buff */ | |
1589 | new_buff->page_offset = old_buff->page_offset ^ bufsz; | |
1590 | ||
1591 | /* sync the buffer for use by the device */ | |
1592 | dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, | |
1593 | new_buff->page_offset, bufsz, | |
1594 | DMA_FROM_DEVICE); | |
1595 | ||
1596 | /* bump ref count on page before it is given to the stack */ | |
1597 | get_page(new_buff->page); | |
1598 | } | |
1599 | ||
1600 | /** | |
1601 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1602 | * @rx_ring: rx descriptor ring to transact packets on | |
1603 | * @rx_buffer: buffer containing page to add | |
1604 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1605 | * @skb: sk_buff to place the data into | |
1606 | * | |
1607 | * This function is based on skb_add_rx_frag. I would have used that | |
1608 | * function however it doesn't handle the truesize case correctly since we | |
1609 | * are allocating more memory than might be used for a single receive. | |
1610 | **/ | |
1611 | static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, | |
1612 | struct ixgbe_rx_buffer *rx_buffer, | |
1613 | struct sk_buff *skb, int size) | |
1614 | { | |
1615 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
1616 | rx_buffer->page, rx_buffer->page_offset, | |
1617 | size); | |
1618 | skb->len += size; | |
1619 | skb->data_len += size; | |
1620 | skb->truesize += ixgbe_rx_bufsz(rx_ring); | |
1621 | } | |
1622 | ||
1623 | /** | |
1624 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1625 | * @q_vector: structure containing interrupt and ring information | |
1626 | * @rx_ring: rx descriptor ring to transact packets on | |
1627 | * @budget: Total limit on number of packets to process | |
1628 | * | |
1629 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1630 | * processing. The advantage to this is that on systems that have | |
1631 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1632 | * it by maintaining the mapping of the page to the syste. | |
1633 | * | |
1634 | * Returns true if all work is completed without reaching budget | |
1635 | **/ | |
4ff7fb12 | 1636 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 1637 | struct ixgbe_ring *rx_ring, |
4ff7fb12 | 1638 | int budget) |
9a799d71 | 1639 | { |
d2f4fbe2 | 1640 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3f2d1c0f | 1641 | #ifdef IXGBE_FCOE |
f800326d | 1642 | struct ixgbe_adapter *adapter = q_vector->adapter; |
3d8fd385 YZ |
1643 | int ddp_bytes = 0; |
1644 | #endif /* IXGBE_FCOE */ | |
f800326d | 1645 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 | 1646 | |
f800326d AD |
1647 | do { |
1648 | struct ixgbe_rx_buffer *rx_buffer; | |
1649 | union ixgbe_adv_rx_desc *rx_desc; | |
1650 | struct sk_buff *skb; | |
1651 | struct page *page; | |
1652 | u16 ntc; | |
1653 | ||
1654 | /* return some buffers to hardware, one at a time is too slow */ | |
1655 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
1656 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1657 | cleaned_count = 0; | |
1658 | } | |
1659 | ||
1660 | ntc = rx_ring->next_to_clean; | |
1661 | rx_desc = IXGBE_RX_DESC(rx_ring, ntc); | |
1662 | rx_buffer = &rx_ring->rx_buffer_info[ntc]; | |
1663 | ||
1664 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) | |
1665 | break; | |
9a799d71 | 1666 | |
f800326d AD |
1667 | /* |
1668 | * This memory barrier is needed to keep us from reading | |
1669 | * any other fields out of the rx_desc until we know the | |
1670 | * RXD_STAT_DD bit is set | |
1671 | */ | |
1672 | rmb(); | |
9a799d71 | 1673 | |
f800326d AD |
1674 | page = rx_buffer->page; |
1675 | prefetchw(page); | |
9a799d71 | 1676 | |
f800326d | 1677 | skb = rx_buffer->skb; |
c267fc16 | 1678 | |
f800326d AD |
1679 | if (likely(!skb)) { |
1680 | void *page_addr = page_address(page) + | |
1681 | rx_buffer->page_offset; | |
9a799d71 | 1682 | |
f800326d AD |
1683 | /* prefetch first cache line of first page */ |
1684 | prefetch(page_addr); | |
1685 | #if L1_CACHE_BYTES < 128 | |
1686 | prefetch(page_addr + L1_CACHE_BYTES); | |
1687 | #endif | |
1688 | ||
1689 | /* allocate a skb to store the frags */ | |
1690 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
1691 | IXGBE_RX_HDR_SIZE); | |
1692 | if (unlikely(!skb)) { | |
1693 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
1694 | break; | |
c267fc16 AD |
1695 | } |
1696 | ||
f800326d AD |
1697 | /* |
1698 | * we will be copying header into skb->data in | |
1699 | * pskb_may_pull so it is in our interest to prefetch | |
1700 | * it now to avoid a possible cache miss | |
1701 | */ | |
1702 | prefetchw(skb->data); | |
4c1975d7 AD |
1703 | |
1704 | /* | |
1705 | * Delay unmapping of the first packet. It carries the | |
1706 | * header information, HW may still access the header | |
f800326d AD |
1707 | * after the writeback. Only unmap it when EOP is |
1708 | * reached | |
4c1975d7 | 1709 | */ |
f800326d | 1710 | IXGBE_CB(skb)->dma = rx_buffer->dma; |
c267fc16 | 1711 | } else { |
f800326d AD |
1712 | /* we are reusing so sync this buffer for CPU use */ |
1713 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1714 | rx_buffer->dma, | |
1715 | rx_buffer->page_offset, | |
1716 | ixgbe_rx_bufsz(rx_ring), | |
1717 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1718 | } |
1719 | ||
f800326d AD |
1720 | /* pull page into skb */ |
1721 | ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, | |
1722 | le16_to_cpu(rx_desc->wb.upper.length)); | |
9a799d71 | 1723 | |
f800326d AD |
1724 | if (ixgbe_can_reuse_page(rx_buffer)) { |
1725 | /* hand second half of page back to the ring */ | |
1726 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
1727 | } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { | |
1728 | /* the page has been released from the ring */ | |
1729 | IXGBE_CB(skb)->page_released = true; | |
1730 | } else { | |
1731 | /* we are not reusing the buffer so unmap it */ | |
1732 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
1733 | ixgbe_rx_pg_size(rx_ring), | |
1734 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1735 | } |
1736 | ||
f800326d AD |
1737 | /* clear contents of buffer_info */ |
1738 | rx_buffer->skb = NULL; | |
1739 | rx_buffer->dma = 0; | |
1740 | rx_buffer->page = NULL; | |
4c1975d7 | 1741 | |
f800326d | 1742 | ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb); |
9a799d71 | 1743 | |
9a799d71 | 1744 | cleaned_count++; |
f8212f97 | 1745 | |
f800326d AD |
1746 | /* place incomplete frames back on ring for completion */ |
1747 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
1748 | continue; | |
c267fc16 | 1749 | |
f800326d AD |
1750 | /* verify the packet layout is correct */ |
1751 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
1752 | continue; | |
9a799d71 | 1753 | |
d2f4fbe2 AV |
1754 | /* probably a little skewed due to removing CRC */ |
1755 | total_rx_bytes += skb->len; | |
1756 | total_rx_packets++; | |
1757 | ||
8a0da21b AD |
1758 | /* populate checksum, timestamp, VLAN, and protocol */ |
1759 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
1760 | ||
332d4a7d YZ |
1761 | #ifdef IXGBE_FCOE |
1762 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
ff886dfc | 1763 | if (ixgbe_rx_is_fcoe(adapter, rx_desc)) { |
f56e0cb1 | 1764 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
63d635b2 AD |
1765 | if (!ddp_bytes) { |
1766 | dev_kfree_skb_any(skb); | |
f800326d | 1767 | continue; |
63d635b2 | 1768 | } |
3d8fd385 | 1769 | } |
f800326d | 1770 | |
332d4a7d | 1771 | #endif /* IXGBE_FCOE */ |
8a0da21b | 1772 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 1773 | |
f800326d | 1774 | /* update budget accounting */ |
4ff7fb12 | 1775 | budget--; |
f800326d | 1776 | } while (likely(budget)); |
9a799d71 | 1777 | |
3d8fd385 YZ |
1778 | #ifdef IXGBE_FCOE |
1779 | /* include DDPed FCoE data */ | |
1780 | if (ddp_bytes > 0) { | |
1781 | unsigned int mss; | |
1782 | ||
fc77dc3c | 1783 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1784 | sizeof(struct fc_frame_header) - |
1785 | sizeof(struct fcoe_crc_eof); | |
1786 | if (mss > 512) | |
1787 | mss &= ~511; | |
1788 | total_rx_bytes += ddp_bytes; | |
1789 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1790 | } | |
3d8fd385 | 1791 | |
f800326d | 1792 | #endif /* IXGBE_FCOE */ |
c267fc16 AD |
1793 | u64_stats_update_begin(&rx_ring->syncp); |
1794 | rx_ring->stats.packets += total_rx_packets; | |
1795 | rx_ring->stats.bytes += total_rx_bytes; | |
1796 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
1797 | q_vector->rx.total_packets += total_rx_packets; |
1798 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 1799 | |
f800326d AD |
1800 | if (cleaned_count) |
1801 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1802 | ||
4ff7fb12 | 1803 | return !!budget; |
9a799d71 AK |
1804 | } |
1805 | ||
9a799d71 AK |
1806 | /** |
1807 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1808 | * @adapter: board private structure | |
1809 | * | |
1810 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1811 | * interrupts. | |
1812 | **/ | |
1813 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1814 | { | |
021230d4 | 1815 | struct ixgbe_q_vector *q_vector; |
efe3d3c8 | 1816 | int q_vectors, v_idx; |
021230d4 | 1817 | u32 mask; |
9a799d71 | 1818 | |
021230d4 | 1819 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1820 | |
8e34d1aa AD |
1821 | /* Populate MSIX to EITR Select */ |
1822 | if (adapter->num_vfs > 32) { | |
1823 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1824 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1825 | } | |
1826 | ||
4df10466 JB |
1827 | /* |
1828 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1829 | * corresponding register. |
1830 | */ | |
1831 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
efe3d3c8 | 1832 | struct ixgbe_ring *ring; |
7a921c93 | 1833 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 1834 | |
a557928e | 1835 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
1836 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
1837 | ||
a557928e | 1838 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
1839 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
1840 | ||
d5bf4f67 ET |
1841 | if (q_vector->tx.ring && !q_vector->rx.ring) { |
1842 | /* tx only vector */ | |
1843 | if (adapter->tx_itr_setting == 1) | |
1844 | q_vector->itr = IXGBE_10K_ITR; | |
1845 | else | |
1846 | q_vector->itr = adapter->tx_itr_setting; | |
1847 | } else { | |
1848 | /* rx or rx/tx vector */ | |
1849 | if (adapter->rx_itr_setting == 1) | |
1850 | q_vector->itr = IXGBE_20K_ITR; | |
1851 | else | |
1852 | q_vector->itr = adapter->rx_itr_setting; | |
1853 | } | |
021230d4 | 1854 | |
fe49f04a | 1855 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1856 | } |
1857 | ||
bd508178 AD |
1858 | switch (adapter->hw.mac.type) { |
1859 | case ixgbe_mac_82598EB: | |
e8e26350 | 1860 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1861 | v_idx); |
bd508178 AD |
1862 | break; |
1863 | case ixgbe_mac_82599EB: | |
b93a2226 | 1864 | case ixgbe_mac_X540: |
e8e26350 | 1865 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 1866 | break; |
bd508178 AD |
1867 | default: |
1868 | break; | |
1869 | } | |
021230d4 AV |
1870 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1871 | ||
41fb9248 | 1872 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1873 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
1874 | mask &= ~(IXGBE_EIMS_OTHER | |
1875 | IXGBE_EIMS_MAILBOX | | |
1876 | IXGBE_EIMS_LSC); | |
1877 | ||
021230d4 | 1878 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1879 | } |
1880 | ||
f494e8fa AV |
1881 | enum latency_range { |
1882 | lowest_latency = 0, | |
1883 | low_latency = 1, | |
1884 | bulk_latency = 2, | |
1885 | latency_invalid = 255 | |
1886 | }; | |
1887 | ||
1888 | /** | |
1889 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
1890 | * @q_vector: structure containing interrupt and ring information |
1891 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
1892 | * |
1893 | * Stores a new ITR value based on packets and byte | |
1894 | * counts during the last interrupt. The advantage of per interrupt | |
1895 | * computation is faster updates and more accurate ITR for the current | |
1896 | * traffic pattern. Constants in this function were computed | |
1897 | * based on theoretical maximum wire speed and thresholds were set based | |
1898 | * on testing data as well as attempting to minimize response time | |
1899 | * while increasing bulk throughput. | |
1900 | * this functionality is controlled by the InterruptThrottleRate module | |
1901 | * parameter (see ixgbe_param.c) | |
1902 | **/ | |
bd198058 AD |
1903 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
1904 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 1905 | { |
bd198058 AD |
1906 | int bytes = ring_container->total_bytes; |
1907 | int packets = ring_container->total_packets; | |
1908 | u32 timepassed_us; | |
621bd70e | 1909 | u64 bytes_perint; |
bd198058 | 1910 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
1911 | |
1912 | if (packets == 0) | |
bd198058 | 1913 | return; |
f494e8fa AV |
1914 | |
1915 | /* simple throttlerate management | |
621bd70e AD |
1916 | * 0-10MB/s lowest (100000 ints/s) |
1917 | * 10-20MB/s low (20000 ints/s) | |
1918 | * 20-1249MB/s bulk (8000 ints/s) | |
f494e8fa AV |
1919 | */ |
1920 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 1921 | timepassed_us = q_vector->itr >> 2; |
f494e8fa AV |
1922 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
1923 | ||
1924 | switch (itr_setting) { | |
1925 | case lowest_latency: | |
621bd70e | 1926 | if (bytes_perint > 10) |
bd198058 | 1927 | itr_setting = low_latency; |
f494e8fa AV |
1928 | break; |
1929 | case low_latency: | |
621bd70e | 1930 | if (bytes_perint > 20) |
bd198058 | 1931 | itr_setting = bulk_latency; |
621bd70e | 1932 | else if (bytes_perint <= 10) |
bd198058 | 1933 | itr_setting = lowest_latency; |
f494e8fa AV |
1934 | break; |
1935 | case bulk_latency: | |
621bd70e | 1936 | if (bytes_perint <= 20) |
bd198058 | 1937 | itr_setting = low_latency; |
f494e8fa AV |
1938 | break; |
1939 | } | |
1940 | ||
bd198058 AD |
1941 | /* clear work counters since we have the values we need */ |
1942 | ring_container->total_bytes = 0; | |
1943 | ring_container->total_packets = 0; | |
1944 | ||
1945 | /* write updated itr to ring container */ | |
1946 | ring_container->itr = itr_setting; | |
f494e8fa AV |
1947 | } |
1948 | ||
509ee935 JB |
1949 | /** |
1950 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1951 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1952 | * |
1953 | * This function is made to be called by ethtool and by the driver | |
1954 | * when it needs to update EITR registers at runtime. Hardware | |
1955 | * specific quirks/differences are taken care of here. | |
1956 | */ | |
fe49f04a | 1957 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1958 | { |
fe49f04a | 1959 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1960 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1961 | int v_idx = q_vector->v_idx; |
5d967eb7 | 1962 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 1963 | |
bd508178 AD |
1964 | switch (adapter->hw.mac.type) { |
1965 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1966 | /* must write high and low 16 bits to reset counter */ |
1967 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1968 | break; |
1969 | case ixgbe_mac_82599EB: | |
b93a2226 | 1970 | case ixgbe_mac_X540: |
509ee935 JB |
1971 | /* |
1972 | * set the WDIS bit to not clear the timer bits and cause an | |
1973 | * immediate assertion of the interrupt | |
1974 | */ | |
1975 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1976 | break; |
1977 | default: | |
1978 | break; | |
509ee935 JB |
1979 | } |
1980 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1981 | } | |
1982 | ||
bd198058 | 1983 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 1984 | { |
d5bf4f67 | 1985 | u32 new_itr = q_vector->itr; |
bd198058 | 1986 | u8 current_itr; |
f494e8fa | 1987 | |
bd198058 AD |
1988 | ixgbe_update_itr(q_vector, &q_vector->tx); |
1989 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 1990 | |
08c8833b | 1991 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
1992 | |
1993 | switch (current_itr) { | |
1994 | /* counts and packets in update_itr are dependent on these numbers */ | |
1995 | case lowest_latency: | |
d5bf4f67 | 1996 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
1997 | break; |
1998 | case low_latency: | |
d5bf4f67 | 1999 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
2000 | break; |
2001 | case bulk_latency: | |
d5bf4f67 | 2002 | new_itr = IXGBE_8K_ITR; |
f494e8fa | 2003 | break; |
bd198058 AD |
2004 | default: |
2005 | break; | |
f494e8fa AV |
2006 | } |
2007 | ||
d5bf4f67 | 2008 | if (new_itr != q_vector->itr) { |
fe49f04a | 2009 | /* do an exponential smoothing */ |
d5bf4f67 ET |
2010 | new_itr = (10 * new_itr * q_vector->itr) / |
2011 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 2012 | |
bd198058 | 2013 | /* save the algorithm value here */ |
5d967eb7 | 2014 | q_vector->itr = new_itr; |
fe49f04a AD |
2015 | |
2016 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2017 | } |
f494e8fa AV |
2018 | } |
2019 | ||
119fc60a | 2020 | /** |
de88eeeb | 2021 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 2022 | * @adapter: pointer to adapter |
119fc60a | 2023 | **/ |
f0f9778d | 2024 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 2025 | { |
119fc60a MC |
2026 | struct ixgbe_hw *hw = &adapter->hw; |
2027 | u32 eicr = adapter->interrupt_event; | |
2028 | ||
f0f9778d | 2029 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
2030 | return; |
2031 | ||
f0f9778d AD |
2032 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2033 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
2034 | return; | |
2035 | ||
2036 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2037 | ||
7ca647bd | 2038 | switch (hw->device_id) { |
f0f9778d AD |
2039 | case IXGBE_DEV_ID_82599_T3_LOM: |
2040 | /* | |
2041 | * Since the warning interrupt is for both ports | |
2042 | * we don't have to check if: | |
2043 | * - This interrupt wasn't for our port. | |
2044 | * - We may have missed the interrupt so always have to | |
2045 | * check if we got a LSC | |
2046 | */ | |
2047 | if (!(eicr & IXGBE_EICR_GPI_SDP0) && | |
2048 | !(eicr & IXGBE_EICR_LSC)) | |
2049 | return; | |
2050 | ||
2051 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
2052 | u32 autoneg; | |
2053 | bool link_up = false; | |
7ca647bd | 2054 | |
7ca647bd JP |
2055 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); |
2056 | ||
f0f9778d AD |
2057 | if (link_up) |
2058 | return; | |
2059 | } | |
2060 | ||
2061 | /* Check if this is not due to overtemp */ | |
2062 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2063 | return; | |
2064 | ||
2065 | break; | |
7ca647bd JP |
2066 | default: |
2067 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 2068 | return; |
7ca647bd | 2069 | break; |
119fc60a | 2070 | } |
7ca647bd JP |
2071 | e_crit(drv, |
2072 | "Network adapter has been stopped because it has over heated. " | |
2073 | "Restart the computer. If the problem persists, " | |
2074 | "power off the system and replace the adapter\n"); | |
f0f9778d AD |
2075 | |
2076 | adapter->interrupt_event = 0; | |
119fc60a MC |
2077 | } |
2078 | ||
0befdb3e JB |
2079 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2080 | { | |
2081 | struct ixgbe_hw *hw = &adapter->hw; | |
2082 | ||
2083 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
2084 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 2085 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
2086 | /* write to clear the interrupt */ |
2087 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
2088 | } | |
2089 | } | |
cf8280ee | 2090 | |
4f51bf70 JK |
2091 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2092 | { | |
2093 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) | |
2094 | return; | |
2095 | ||
2096 | switch (adapter->hw.mac.type) { | |
2097 | case ixgbe_mac_82599EB: | |
2098 | /* | |
2099 | * Need to check link state so complete overtemp check | |
2100 | * on service task | |
2101 | */ | |
2102 | if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && | |
2103 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { | |
2104 | adapter->interrupt_event = eicr; | |
2105 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2106 | ixgbe_service_event_schedule(adapter); | |
2107 | return; | |
2108 | } | |
2109 | return; | |
2110 | case ixgbe_mac_X540: | |
2111 | if (!(eicr & IXGBE_EICR_TS)) | |
2112 | return; | |
2113 | break; | |
2114 | default: | |
2115 | return; | |
2116 | } | |
2117 | ||
2118 | e_crit(drv, | |
2119 | "Network adapter has been stopped because it has over heated. " | |
2120 | "Restart the computer. If the problem persists, " | |
2121 | "power off the system and replace the adapter\n"); | |
2122 | } | |
2123 | ||
e8e26350 PW |
2124 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2125 | { | |
2126 | struct ixgbe_hw *hw = &adapter->hw; | |
2127 | ||
73c4b7cd AD |
2128 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
2129 | /* Clear the interrupt */ | |
2130 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
7086400d AD |
2131 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2132 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
2133 | ixgbe_service_event_schedule(adapter); | |
2134 | } | |
73c4b7cd AD |
2135 | } |
2136 | ||
e8e26350 PW |
2137 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
2138 | /* Clear the interrupt */ | |
2139 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
7086400d AD |
2140 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2141 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2142 | ixgbe_service_event_schedule(adapter); | |
2143 | } | |
e8e26350 PW |
2144 | } |
2145 | } | |
2146 | ||
cf8280ee JB |
2147 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2148 | { | |
2149 | struct ixgbe_hw *hw = &adapter->hw; | |
2150 | ||
2151 | adapter->lsc_int++; | |
2152 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2153 | adapter->link_check_timeout = jiffies; | |
2154 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2155 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2156 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2157 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2158 | } |
2159 | } | |
2160 | ||
fe49f04a AD |
2161 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2162 | u64 qmask) | |
2163 | { | |
2164 | u32 mask; | |
bd508178 | 2165 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2166 | |
bd508178 AD |
2167 | switch (hw->mac.type) { |
2168 | case ixgbe_mac_82598EB: | |
fe49f04a | 2169 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2170 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2171 | break; | |
2172 | case ixgbe_mac_82599EB: | |
b93a2226 | 2173 | case ixgbe_mac_X540: |
fe49f04a | 2174 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2175 | if (mask) |
2176 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2177 | mask = (qmask >> 32); |
bd508178 AD |
2178 | if (mask) |
2179 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2180 | break; | |
2181 | default: | |
2182 | break; | |
fe49f04a AD |
2183 | } |
2184 | /* skip the flush */ | |
2185 | } | |
2186 | ||
2187 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2188 | u64 qmask) |
fe49f04a AD |
2189 | { |
2190 | u32 mask; | |
bd508178 | 2191 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2192 | |
bd508178 AD |
2193 | switch (hw->mac.type) { |
2194 | case ixgbe_mac_82598EB: | |
fe49f04a | 2195 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2196 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2197 | break; | |
2198 | case ixgbe_mac_82599EB: | |
b93a2226 | 2199 | case ixgbe_mac_X540: |
fe49f04a | 2200 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2201 | if (mask) |
2202 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2203 | mask = (qmask >> 32); |
bd508178 AD |
2204 | if (mask) |
2205 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2206 | break; | |
2207 | default: | |
2208 | break; | |
fe49f04a AD |
2209 | } |
2210 | /* skip the flush */ | |
2211 | } | |
2212 | ||
021230d4 | 2213 | /** |
2c4af694 AD |
2214 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2215 | * @adapter: board private structure | |
021230d4 | 2216 | **/ |
2c4af694 AD |
2217 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2218 | bool flush) | |
9a799d71 | 2219 | { |
2c4af694 | 2220 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2221 | |
2c4af694 AD |
2222 | /* don't reenable LSC while waiting for link */ |
2223 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2224 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2225 | |
2c4af694 | 2226 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2227 | switch (adapter->hw.mac.type) { |
2228 | case ixgbe_mac_82599EB: | |
2229 | mask |= IXGBE_EIMS_GPI_SDP0; | |
2230 | break; | |
2231 | case ixgbe_mac_X540: | |
2232 | mask |= IXGBE_EIMS_TS; | |
2233 | break; | |
2234 | default: | |
2235 | break; | |
2236 | } | |
2c4af694 AD |
2237 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2238 | mask |= IXGBE_EIMS_GPI_SDP1; | |
2239 | switch (adapter->hw.mac.type) { | |
2240 | case ixgbe_mac_82599EB: | |
2c4af694 AD |
2241 | mask |= IXGBE_EIMS_GPI_SDP1; |
2242 | mask |= IXGBE_EIMS_GPI_SDP2; | |
858bc081 DS |
2243 | case ixgbe_mac_X540: |
2244 | mask |= IXGBE_EIMS_ECC; | |
2c4af694 AD |
2245 | mask |= IXGBE_EIMS_MAILBOX; |
2246 | break; | |
2247 | default: | |
2248 | break; | |
9a799d71 | 2249 | } |
2c4af694 AD |
2250 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2251 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2252 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2253 | |
2c4af694 AD |
2254 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2255 | if (queues) | |
2256 | ixgbe_irq_enable_queues(adapter, ~0); | |
2257 | if (flush) | |
2258 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2259 | } |
2260 | ||
2c4af694 | 2261 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2262 | { |
a65151ba | 2263 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2264 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2265 | u32 eicr; |
91281fd3 | 2266 | |
54037505 DS |
2267 | /* |
2268 | * Workaround for Silicon errata. Use clear-by-write instead | |
2269 | * of clear-by-read. Reading with EICS will return the | |
2270 | * interrupt causes without clearing, which later be done | |
2271 | * with the write to EICR. | |
2272 | */ | |
2273 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
2274 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
33cf09c9 | 2275 | |
cf8280ee JB |
2276 | if (eicr & IXGBE_EICR_LSC) |
2277 | ixgbe_check_lsc(adapter); | |
f0848276 | 2278 | |
1cdd1ec8 GR |
2279 | if (eicr & IXGBE_EICR_MAILBOX) |
2280 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2281 | |
bd508178 AD |
2282 | switch (hw->mac.type) { |
2283 | case ixgbe_mac_82599EB: | |
b93a2226 | 2284 | case ixgbe_mac_X540: |
2c4af694 AD |
2285 | if (eicr & IXGBE_EICR_ECC) |
2286 | e_info(link, "Received unrecoverable ECC Err, please " | |
2287 | "reboot\n"); | |
c4cf55e5 PWJ |
2288 | /* Handle Flow Director Full threshold interrupt */ |
2289 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2290 | int reinit_count = 0; |
c4cf55e5 | 2291 | int i; |
c4cf55e5 | 2292 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2293 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2294 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2295 | &ring->state)) |
2296 | reinit_count++; | |
2297 | } | |
2298 | if (reinit_count) { | |
2299 | /* no more flow director interrupts until after init */ | |
2300 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
2301 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
2302 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
2303 | } |
2304 | } | |
f0f9778d | 2305 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 2306 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2307 | break; |
2308 | default: | |
2309 | break; | |
c4cf55e5 | 2310 | } |
f0848276 | 2311 | |
bd508178 | 2312 | ixgbe_check_fan_failure(adapter, eicr); |
efe3d3c8 | 2313 | |
7086400d | 2314 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 2315 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 2316 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 2317 | |
9a799d71 | 2318 | return IRQ_HANDLED; |
f0848276 | 2319 | } |
91281fd3 | 2320 | |
4ff7fb12 | 2321 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 2322 | { |
021230d4 | 2323 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 2324 | |
9b471446 | 2325 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2326 | |
4ff7fb12 AD |
2327 | if (q_vector->rx.ring || q_vector->tx.ring) |
2328 | napi_schedule(&q_vector->napi); | |
91281fd3 | 2329 | |
9a799d71 | 2330 | return IRQ_HANDLED; |
91281fd3 AD |
2331 | } |
2332 | ||
eb01b975 AD |
2333 | /** |
2334 | * ixgbe_poll - NAPI Rx polling callback | |
2335 | * @napi: structure for representing this polling device | |
2336 | * @budget: how many packets driver is allowed to clean | |
2337 | * | |
2338 | * This function is used for legacy and MSI, NAPI mode | |
2339 | **/ | |
8af3c33f | 2340 | int ixgbe_poll(struct napi_struct *napi, int budget) |
eb01b975 AD |
2341 | { |
2342 | struct ixgbe_q_vector *q_vector = | |
2343 | container_of(napi, struct ixgbe_q_vector, napi); | |
2344 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2345 | struct ixgbe_ring *ring; | |
2346 | int per_ring_budget; | |
2347 | bool clean_complete = true; | |
2348 | ||
2349 | #ifdef CONFIG_IXGBE_DCA | |
2350 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2351 | ixgbe_update_dca(q_vector); | |
2352 | #endif | |
2353 | ||
2354 | ixgbe_for_each_ring(ring, q_vector->tx) | |
2355 | clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); | |
2356 | ||
2357 | /* attempt to distribute budget to each queue fairly, but don't allow | |
2358 | * the budget to go below 1 because we'll exit polling */ | |
2359 | if (q_vector->rx.count > 1) | |
2360 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
2361 | else | |
2362 | per_ring_budget = budget; | |
2363 | ||
2364 | ixgbe_for_each_ring(ring, q_vector->rx) | |
2365 | clean_complete &= ixgbe_clean_rx_irq(q_vector, ring, | |
2366 | per_ring_budget); | |
2367 | ||
2368 | /* If all work not completed, return budget and keep polling */ | |
2369 | if (!clean_complete) | |
2370 | return budget; | |
2371 | ||
2372 | /* all work done, exit the polling mode */ | |
2373 | napi_complete(napi); | |
2374 | if (adapter->rx_itr_setting & 1) | |
2375 | ixgbe_set_itr(q_vector); | |
2376 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2377 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
2378 | ||
2379 | return 0; | |
2380 | } | |
2381 | ||
021230d4 AV |
2382 | /** |
2383 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2384 | * @adapter: board private structure | |
2385 | * | |
2386 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2387 | * interrupts from the kernel. | |
2388 | **/ | |
2389 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2390 | { | |
2391 | struct net_device *netdev = adapter->netdev; | |
207867f5 AD |
2392 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2393 | int vector, err; | |
e8e9f696 | 2394 | int ri = 0, ti = 0; |
021230d4 | 2395 | |
021230d4 | 2396 | for (vector = 0; vector < q_vectors; vector++) { |
d0759ebb | 2397 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2398 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2399 | |
4ff7fb12 | 2400 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2401 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2402 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2403 | ti++; | |
2404 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2405 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2406 | "%s-%s-%d", netdev->name, "rx", ri++); |
2407 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2408 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2409 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2410 | } else { |
2411 | /* skip this unused q_vector */ | |
2412 | continue; | |
32aa77a4 | 2413 | } |
207867f5 AD |
2414 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2415 | q_vector->name, q_vector); | |
9a799d71 | 2416 | if (err) { |
396e799c | 2417 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2418 | "Error: %d\n", err); |
021230d4 | 2419 | goto free_queue_irqs; |
9a799d71 | 2420 | } |
207867f5 AD |
2421 | /* If Flow Director is enabled, set interrupt affinity */ |
2422 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2423 | /* assign the mask for this irq */ | |
2424 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 2425 | &q_vector->affinity_mask); |
207867f5 | 2426 | } |
9a799d71 AK |
2427 | } |
2428 | ||
021230d4 | 2429 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2430 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2431 | if (err) { |
de88eeeb | 2432 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 2433 | goto free_queue_irqs; |
9a799d71 AK |
2434 | } |
2435 | ||
9a799d71 AK |
2436 | return 0; |
2437 | ||
021230d4 | 2438 | free_queue_irqs: |
207867f5 AD |
2439 | while (vector) { |
2440 | vector--; | |
2441 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2442 | NULL); | |
2443 | free_irq(adapter->msix_entries[vector].vector, | |
2444 | adapter->q_vector[vector]); | |
2445 | } | |
021230d4 AV |
2446 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2447 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2448 | kfree(adapter->msix_entries); |
2449 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2450 | return err; |
2451 | } | |
2452 | ||
2453 | /** | |
021230d4 | 2454 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2455 | * @irq: interrupt number |
2456 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2457 | **/ |
2458 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2459 | { | |
a65151ba | 2460 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2461 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2462 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2463 | u32 eicr; |
2464 | ||
54037505 | 2465 | /* |
24ddd967 | 2466 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
2467 | * before the read of EICR. |
2468 | */ | |
2469 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2470 | ||
021230d4 | 2471 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 2472 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 2473 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 2474 | if (!eicr) { |
6af3b9eb ET |
2475 | /* |
2476 | * shared interrupt alert! | |
f47cf66e | 2477 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2478 | * have disabled interrupts due to EIAM |
2479 | * finish the workaround of silicon errata on 82598. Unmask | |
2480 | * the interrupt that we masked before the EICR read. | |
2481 | */ | |
2482 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2483 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2484 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2485 | } |
9a799d71 | 2486 | |
cf8280ee JB |
2487 | if (eicr & IXGBE_EICR_LSC) |
2488 | ixgbe_check_lsc(adapter); | |
021230d4 | 2489 | |
bd508178 AD |
2490 | switch (hw->mac.type) { |
2491 | case ixgbe_mac_82599EB: | |
e8e26350 | 2492 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
2493 | /* Fall through */ |
2494 | case ixgbe_mac_X540: | |
2495 | if (eicr & IXGBE_EICR_ECC) | |
2496 | e_info(link, "Received unrecoverable ECC err, please " | |
2497 | "reboot\n"); | |
4f51bf70 | 2498 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2499 | break; |
2500 | default: | |
2501 | break; | |
2502 | } | |
e8e26350 | 2503 | |
0befdb3e JB |
2504 | ixgbe_check_fan_failure(adapter, eicr); |
2505 | ||
b9f6ed2b AD |
2506 | /* would disable interrupts here but EIAM disabled it */ |
2507 | napi_schedule(&q_vector->napi); | |
9a799d71 | 2508 | |
6af3b9eb ET |
2509 | /* |
2510 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2511 | * ixgbe_poll will re-enable the queue interrupts | |
2512 | */ | |
6af3b9eb ET |
2513 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2514 | ixgbe_irq_enable(adapter, false, false); | |
2515 | ||
9a799d71 AK |
2516 | return IRQ_HANDLED; |
2517 | } | |
2518 | ||
2519 | /** | |
2520 | * ixgbe_request_irq - initialize interrupts | |
2521 | * @adapter: board private structure | |
2522 | * | |
2523 | * Attempts to configure interrupts using the best available | |
2524 | * capabilities of the hardware and kernel. | |
2525 | **/ | |
021230d4 | 2526 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2527 | { |
2528 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2529 | int err; |
9a799d71 | 2530 | |
4cc6df29 | 2531 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 2532 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 2533 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 2534 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 2535 | netdev->name, adapter); |
4cc6df29 | 2536 | else |
a0607fd3 | 2537 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 2538 | netdev->name, adapter); |
9a799d71 | 2539 | |
de88eeeb | 2540 | if (err) |
396e799c | 2541 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2542 | |
9a799d71 AK |
2543 | return err; |
2544 | } | |
2545 | ||
2546 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2547 | { | |
9a799d71 | 2548 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
021230d4 | 2549 | int i, q_vectors; |
9a799d71 | 2550 | |
021230d4 | 2551 | q_vectors = adapter->num_msix_vectors; |
021230d4 | 2552 | i = q_vectors - 1; |
a65151ba | 2553 | free_irq(adapter->msix_entries[i].vector, adapter); |
021230d4 | 2554 | i--; |
4cc6df29 | 2555 | |
021230d4 | 2556 | for (; i >= 0; i--) { |
894ff7cf | 2557 | /* free only the irqs that were actually requested */ |
4ff7fb12 AD |
2558 | if (!adapter->q_vector[i]->rx.ring && |
2559 | !adapter->q_vector[i]->tx.ring) | |
894ff7cf AD |
2560 | continue; |
2561 | ||
207867f5 AD |
2562 | /* clear the affinity_mask in the IRQ descriptor */ |
2563 | irq_set_affinity_hint(adapter->msix_entries[i].vector, | |
2564 | NULL); | |
2565 | ||
021230d4 | 2566 | free_irq(adapter->msix_entries[i].vector, |
e8e9f696 | 2567 | adapter->q_vector[i]); |
021230d4 | 2568 | } |
021230d4 | 2569 | } else { |
a65151ba | 2570 | free_irq(adapter->pdev->irq, adapter); |
9a799d71 AK |
2571 | } |
2572 | } | |
2573 | ||
22d5a71b JB |
2574 | /** |
2575 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2576 | * @adapter: board private structure | |
2577 | **/ | |
2578 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2579 | { | |
bd508178 AD |
2580 | switch (adapter->hw.mac.type) { |
2581 | case ixgbe_mac_82598EB: | |
835462fc | 2582 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2583 | break; |
2584 | case ixgbe_mac_82599EB: | |
b93a2226 | 2585 | case ixgbe_mac_X540: |
835462fc NS |
2586 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2587 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2588 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
2589 | break; |
2590 | default: | |
2591 | break; | |
22d5a71b JB |
2592 | } |
2593 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2594 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2595 | int i; | |
2596 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
2597 | synchronize_irq(adapter->msix_entries[i].vector); | |
2598 | } else { | |
2599 | synchronize_irq(adapter->pdev->irq); | |
2600 | } | |
2601 | } | |
2602 | ||
9a799d71 AK |
2603 | /** |
2604 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2605 | * | |
2606 | **/ | |
2607 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2608 | { | |
d5bf4f67 | 2609 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 2610 | |
d5bf4f67 ET |
2611 | /* rx/tx vector */ |
2612 | if (adapter->rx_itr_setting == 1) | |
2613 | q_vector->itr = IXGBE_20K_ITR; | |
2614 | else | |
2615 | q_vector->itr = adapter->rx_itr_setting; | |
2616 | ||
2617 | ixgbe_write_eitr(q_vector); | |
9a799d71 | 2618 | |
e8e26350 PW |
2619 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2620 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 2621 | |
396e799c | 2622 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2623 | } |
2624 | ||
43e69bf0 AD |
2625 | /** |
2626 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2627 | * @adapter: board private structure | |
2628 | * @ring: structure containing ring specific data | |
2629 | * | |
2630 | * Configure the Tx descriptor ring after a reset. | |
2631 | **/ | |
84418e3b AD |
2632 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2633 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2634 | { |
2635 | struct ixgbe_hw *hw = &adapter->hw; | |
2636 | u64 tdba = ring->dma; | |
2f1860b8 | 2637 | int wait_loop = 10; |
b88c6de2 | 2638 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 2639 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2640 | |
2f1860b8 | 2641 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 2642 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
2643 | IXGBE_WRITE_FLUSH(hw); |
2644 | ||
43e69bf0 | 2645 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2646 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2647 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2648 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2649 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2650 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2651 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2652 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2653 | |
b88c6de2 AD |
2654 | /* |
2655 | * set WTHRESH to encourage burst writeback, it should not be set | |
2656 | * higher than 1 when ITR is 0 as it could cause false TX hangs | |
2657 | * | |
2658 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
2659 | * to or less than the number of on chip descriptors, which is | |
2660 | * currently 40. | |
2661 | */ | |
e954b374 | 2662 | if (!ring->q_vector || (ring->q_vector->itr < 8)) |
b88c6de2 AD |
2663 | txdctl |= (1 << 16); /* WTHRESH = 1 */ |
2664 | else | |
2665 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
2666 | ||
e954b374 AD |
2667 | /* |
2668 | * Setting PTHRESH to 32 both improves performance | |
2669 | * and avoids a TX hang with DFP enabled | |
2670 | */ | |
b88c6de2 AD |
2671 | txdctl |= (1 << 8) | /* HTHRESH = 1 */ |
2672 | 32; /* PTHRESH = 32 */ | |
2f1860b8 AD |
2673 | |
2674 | /* reinitialize flowdirector state */ | |
ee9e0f0b AD |
2675 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2676 | adapter->atr_sample_rate) { | |
2677 | ring->atr_sample_rate = adapter->atr_sample_rate; | |
2678 | ring->atr_count = 0; | |
2679 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2680 | } else { | |
2681 | ring->atr_sample_rate = 0; | |
2682 | } | |
2f1860b8 | 2683 | |
c84d324c JF |
2684 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2685 | ||
2f1860b8 | 2686 | /* enable queue */ |
2f1860b8 AD |
2687 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
2688 | ||
2689 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2690 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2691 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2692 | return; | |
2693 | ||
2694 | /* poll to verify queue is enabled */ | |
2695 | do { | |
032b4325 | 2696 | usleep_range(1000, 2000); |
2f1860b8 AD |
2697 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2698 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2699 | if (!wait_loop) | |
2700 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2701 | } |
2702 | ||
120ff942 AD |
2703 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2704 | { | |
2705 | struct ixgbe_hw *hw = &adapter->hw; | |
2706 | u32 rttdcs; | |
72a32f1f | 2707 | u32 reg; |
8b1c0b24 | 2708 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
2709 | |
2710 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2711 | return; | |
2712 | ||
2713 | /* disable the arbiter while setting MTQC */ | |
2714 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2715 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2716 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2717 | ||
2718 | /* set transmit pool layout */ | |
8b1c0b24 | 2719 | switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
120ff942 AD |
2720 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2721 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2722 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2723 | break; | |
8b1c0b24 JF |
2724 | default: |
2725 | if (!tcs) | |
2726 | reg = IXGBE_MTQC_64Q_1PB; | |
2727 | else if (tcs <= 4) | |
2728 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
2729 | else | |
2730 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
120ff942 | 2731 | |
8b1c0b24 | 2732 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg); |
120ff942 | 2733 | |
8b1c0b24 JF |
2734 | /* Enable Security TX Buffer IFG for multiple pb */ |
2735 | if (tcs) { | |
2736 | reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
2737 | reg |= IXGBE_SECTX_DCB; | |
2738 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); | |
2739 | } | |
120ff942 AD |
2740 | break; |
2741 | } | |
2742 | ||
2743 | /* re-enable the arbiter */ | |
2744 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2745 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2746 | } | |
2747 | ||
9a799d71 | 2748 | /** |
3a581073 | 2749 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2750 | * @adapter: board private structure |
2751 | * | |
2752 | * Configure the Tx unit of the MAC after a reset. | |
2753 | **/ | |
2754 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2755 | { | |
2f1860b8 AD |
2756 | struct ixgbe_hw *hw = &adapter->hw; |
2757 | u32 dmatxctl; | |
43e69bf0 | 2758 | u32 i; |
9a799d71 | 2759 | |
2f1860b8 AD |
2760 | ixgbe_setup_mtqc(adapter); |
2761 | ||
2762 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2763 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2764 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2765 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2766 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2767 | } | |
2768 | ||
9a799d71 | 2769 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2770 | for (i = 0; i < adapter->num_tx_queues; i++) |
2771 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2772 | } |
2773 | ||
e8e26350 | 2774 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2775 | |
a6616b42 | 2776 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2777 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2778 | { |
cc41ac7c | 2779 | u32 srrctl; |
bf29ee6c | 2780 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2781 | |
bd508178 AD |
2782 | switch (adapter->hw.mac.type) { |
2783 | case ixgbe_mac_82598EB: { | |
2784 | struct ixgbe_ring_feature *feature = adapter->ring_feature; | |
2785 | const int mask = feature[RING_F_RSS].mask; | |
bf29ee6c | 2786 | reg_idx = reg_idx & mask; |
cc41ac7c | 2787 | } |
bd508178 AD |
2788 | break; |
2789 | case ixgbe_mac_82599EB: | |
b93a2226 | 2790 | case ixgbe_mac_X540: |
bd508178 AD |
2791 | default: |
2792 | break; | |
2793 | } | |
2794 | ||
bf29ee6c | 2795 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx)); |
cc41ac7c JB |
2796 | |
2797 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2798 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
9e10e045 AD |
2799 | if (adapter->num_vfs) |
2800 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
cc41ac7c | 2801 | |
afafd5b0 AD |
2802 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2803 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2804 | ||
f800326d AD |
2805 | #if PAGE_SIZE > IXGBE_MAX_RXBUFFER |
2806 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
afafd5b0 | 2807 | #else |
f800326d | 2808 | srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; |
afafd5b0 | 2809 | #endif |
f800326d | 2810 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 2811 | |
bf29ee6c | 2812 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2813 | } |
9a799d71 | 2814 | |
05abb126 | 2815 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2816 | { |
05abb126 AD |
2817 | struct ixgbe_hw *hw = &adapter->hw; |
2818 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2819 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2820 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2821 | u32 mrqc = 0, reta = 0; |
2822 | u32 rxcsum; | |
2823 | int i, j; | |
8b1c0b24 | 2824 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
86b4db3b JF |
2825 | int maxq = adapter->ring_feature[RING_F_RSS].indices; |
2826 | ||
2827 | if (tcs) | |
2828 | maxq = min(maxq, adapter->num_tx_queues / tcs); | |
0cefafad | 2829 | |
05abb126 AD |
2830 | /* Fill out hash function seeds */ |
2831 | for (i = 0; i < 10; i++) | |
2832 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2833 | ||
2834 | /* Fill out redirection table */ | |
2835 | for (i = 0, j = 0; i < 128; i++, j++) { | |
86b4db3b | 2836 | if (j == maxq) |
05abb126 AD |
2837 | j = 0; |
2838 | /* reta = 4-byte sliding window of | |
2839 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2840 | reta = (reta << 8) | (j * 0x11); | |
2841 | if ((i & 3) == 3) | |
2842 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2843 | } | |
0cefafad | 2844 | |
05abb126 AD |
2845 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2846 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2847 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2848 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2849 | ||
8b1c0b24 JF |
2850 | if (adapter->hw.mac.type == ixgbe_mac_82598EB && |
2851 | (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { | |
0cefafad | 2852 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 JF |
2853 | } else { |
2854 | int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
2855 | | IXGBE_FLAG_SRIOV_ENABLED); | |
2856 | ||
2857 | switch (mask) { | |
2858 | case (IXGBE_FLAG_RSS_ENABLED): | |
2859 | if (!tcs) | |
2860 | mrqc = IXGBE_MRQC_RSSEN; | |
2861 | else if (tcs <= 4) | |
2862 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
2863 | else | |
2864 | mrqc = IXGBE_MRQC_RTRSS8TCEN; | |
2865 | break; | |
2866 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2867 | mrqc = IXGBE_MRQC_VMDQEN; | |
2868 | break; | |
2869 | default: | |
2870 | break; | |
2871 | } | |
0cefafad JB |
2872 | } |
2873 | ||
05abb126 AD |
2874 | /* Perform hash on these packet types */ |
2875 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2876 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2877 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2878 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
2879 | ||
ef6afc0c AD |
2880 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) |
2881 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; | |
2882 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) | |
2883 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
2884 | ||
05abb126 | 2885 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
0cefafad JB |
2886 | } |
2887 | ||
bb5a9ad2 NS |
2888 | /** |
2889 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2890 | * @adapter: address of board private structure | |
2891 | * @index: index of ring to set | |
bb5a9ad2 | 2892 | **/ |
082757af | 2893 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 2894 | struct ixgbe_ring *ring) |
bb5a9ad2 | 2895 | { |
bb5a9ad2 | 2896 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2897 | u32 rscctrl; |
bf29ee6c | 2898 | u8 reg_idx = ring->reg_idx; |
7367096a | 2899 | |
7d637bcc | 2900 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 2901 | return; |
bb5a9ad2 | 2902 | |
7367096a | 2903 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
2904 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2905 | /* | |
2906 | * we must limit the number of descriptors so that the | |
2907 | * total size of max desc * buf_len is not greater | |
642c680e | 2908 | * than 65536 |
bb5a9ad2 | 2909 | */ |
f800326d AD |
2910 | #if (PAGE_SIZE <= 8192) |
2911 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2912 | #elif (PAGE_SIZE <= 16384) | |
2913 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
bb5a9ad2 | 2914 | #else |
f800326d | 2915 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; |
bb5a9ad2 | 2916 | #endif |
7367096a | 2917 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2918 | } |
2919 | ||
9e10e045 AD |
2920 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2921 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2922 | struct ixgbe_ring *ring) | |
2923 | { | |
2924 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
2925 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
2926 | u32 rxdctl; | |
bf29ee6c | 2927 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
2928 | |
2929 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2930 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2931 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2932 | return; | |
2933 | ||
2934 | do { | |
032b4325 | 2935 | usleep_range(1000, 2000); |
9e10e045 AD |
2936 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
2937 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2938 | ||
2939 | if (!wait_loop) { | |
2940 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
2941 | "the polling period\n", reg_idx); | |
2942 | } | |
2943 | } | |
2944 | ||
2d39d576 YZ |
2945 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
2946 | struct ixgbe_ring *ring) | |
2947 | { | |
2948 | struct ixgbe_hw *hw = &adapter->hw; | |
2949 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
2950 | u32 rxdctl; | |
2951 | u8 reg_idx = ring->reg_idx; | |
2952 | ||
2953 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2954 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
2955 | ||
2956 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
2957 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
2958 | ||
2959 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2960 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2961 | return; | |
2962 | ||
2963 | /* the hardware may take up to 100us to really disable the rx queue */ | |
2964 | do { | |
2965 | udelay(10); | |
2966 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2967 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2968 | ||
2969 | if (!wait_loop) { | |
2970 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
2971 | "the polling period\n", reg_idx); | |
2972 | } | |
2973 | } | |
2974 | ||
84418e3b AD |
2975 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
2976 | struct ixgbe_ring *ring) | |
acd37177 AD |
2977 | { |
2978 | struct ixgbe_hw *hw = &adapter->hw; | |
2979 | u64 rdba = ring->dma; | |
9e10e045 | 2980 | u32 rxdctl; |
bf29ee6c | 2981 | u8 reg_idx = ring->reg_idx; |
acd37177 | 2982 | |
9e10e045 AD |
2983 | /* disable queue to avoid issues while updating state */ |
2984 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 2985 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 2986 | |
acd37177 AD |
2987 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
2988 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
2989 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
2990 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
2991 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
2992 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 2993 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
2994 | |
2995 | ixgbe_configure_srrctl(adapter, ring); | |
2996 | ixgbe_configure_rscctl(adapter, ring); | |
2997 | ||
e9f98072 GR |
2998 | /* If operating in IOV mode set RLPML for X540 */ |
2999 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
3000 | hw->mac.type == ixgbe_mac_X540) { | |
3001 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
3002 | rxdctl |= ((ring->netdev->mtu + ETH_HLEN + | |
3003 | ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN); | |
3004 | } | |
3005 | ||
9e10e045 AD |
3006 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3007 | /* | |
3008 | * enable cache line friendly hardware writes: | |
3009 | * PTHRESH=32 descriptors (half the internal cache), | |
3010 | * this also removes ugly rx_no_buffer_count increment | |
3011 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3012 | * WTHRESH=8 burst writeback up to two cache lines | |
3013 | */ | |
3014 | rxdctl &= ~0x3FFFFF; | |
3015 | rxdctl |= 0x080420; | |
3016 | } | |
3017 | ||
3018 | /* enable receive descriptor ring */ | |
3019 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3020 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3021 | ||
3022 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 3023 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
3024 | } |
3025 | ||
48654521 AD |
3026 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3027 | { | |
3028 | struct ixgbe_hw *hw = &adapter->hw; | |
3029 | int p; | |
3030 | ||
3031 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3032 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3033 | IXGBE_PSRTYPE_UDPHDR | |
3034 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3035 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3036 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3037 | |
3038 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3039 | return; | |
3040 | ||
3041 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
3042 | psrtype |= (adapter->num_rx_queues_per_pool << 29); | |
3043 | ||
3044 | for (p = 0; p < adapter->num_rx_pools; p++) | |
3045 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
3046 | psrtype); | |
3047 | } | |
3048 | ||
f5b4a52e AD |
3049 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3050 | { | |
3051 | struct ixgbe_hw *hw = &adapter->hw; | |
3052 | u32 gcr_ext; | |
3053 | u32 vt_reg_bits; | |
3054 | u32 reg_offset, vf_shift; | |
3055 | u32 vmdctl; | |
de4c7f65 | 3056 | int i; |
f5b4a52e AD |
3057 | |
3058 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3059 | return; | |
3060 | ||
3061 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
3062 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN; | |
3063 | vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
3064 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
3065 | ||
3066 | vf_shift = adapter->num_vfs % 32; | |
4cd6923d | 3067 | reg_offset = (adapter->num_vfs >= 32) ? 1 : 0; |
f5b4a52e AD |
3068 | |
3069 | /* Enable only the PF's pool for Tx/Rx */ | |
3070 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
3071 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0); | |
3072 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
3073 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0); | |
3074 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
3075 | ||
3076 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
3077 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
3078 | ||
3079 | /* | |
3080 | * Set up VF register offsets for selected VT Mode, | |
3081 | * i.e. 32 or 64 VFs for SR-IOV | |
3082 | */ | |
3083 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
3084 | gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; | |
3085 | gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; | |
3086 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
3087 | ||
3088 | /* enable Tx loopback for VF/PF communication */ | |
3089 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
a985b6c3 | 3090 | /* Enable MAC Anti-Spoofing */ |
a1cbb15c | 3091 | hw->mac.ops.set_mac_anti_spoofing(hw, |
de4c7f65 | 3092 | (adapter->num_vfs != 0), |
a985b6c3 | 3093 | adapter->num_vfs); |
de4c7f65 GR |
3094 | /* For VFs that have spoof checking turned off */ |
3095 | for (i = 0; i < adapter->num_vfs; i++) { | |
3096 | if (!adapter->vfinfo[i].spoofchk_enabled) | |
3097 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); | |
3098 | } | |
f5b4a52e AD |
3099 | } |
3100 | ||
477de6ed | 3101 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3102 | { |
9a799d71 AK |
3103 | struct ixgbe_hw *hw = &adapter->hw; |
3104 | struct net_device *netdev = adapter->netdev; | |
3105 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
3106 | struct ixgbe_ring *rx_ring; |
3107 | int i; | |
3108 | u32 mhadd, hlreg0; | |
48654521 | 3109 | |
63f39bd1 | 3110 | #ifdef IXGBE_FCOE |
477de6ed AD |
3111 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3112 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3113 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3114 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3115 | |
477de6ed AD |
3116 | #endif /* IXGBE_FCOE */ |
3117 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
3118 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3119 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3120 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3121 | ||
3122 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3123 | } | |
3124 | ||
919e78a6 AD |
3125 | /* MHADD will allow an extra 4 bytes past for vlan tagged frames */ |
3126 | max_frame += VLAN_HLEN; | |
3127 | ||
477de6ed AD |
3128 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); |
3129 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3130 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3131 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3132 | |
0cefafad JB |
3133 | /* |
3134 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3135 | * the Base and Length of the Rx Descriptor Ring | |
3136 | */ | |
9a799d71 | 3137 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3138 | rx_ring = adapter->rx_ring[i]; |
7d637bcc AD |
3139 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
3140 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3141 | else |
7d637bcc | 3142 | clear_ring_rsc_enabled(rx_ring); |
477de6ed | 3143 | } |
477de6ed AD |
3144 | } |
3145 | ||
7367096a AD |
3146 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3147 | { | |
3148 | struct ixgbe_hw *hw = &adapter->hw; | |
3149 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3150 | ||
3151 | switch (hw->mac.type) { | |
3152 | case ixgbe_mac_82598EB: | |
3153 | /* | |
3154 | * For VMDq support of different descriptor types or | |
3155 | * buffer sizes through the use of multiple SRRCTL | |
3156 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3157 | * | |
3158 | * also, the manual doesn't mention it clearly but DCA hints | |
3159 | * will only use queue 0's tags unless this bit is set. Side | |
3160 | * effects of setting this bit are only that SRRCTL must be | |
3161 | * fully programmed [0..15] | |
3162 | */ | |
3163 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3164 | break; | |
3165 | case ixgbe_mac_82599EB: | |
b93a2226 | 3166 | case ixgbe_mac_X540: |
7367096a AD |
3167 | /* Disable RSC for ACK packets */ |
3168 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3169 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3170 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3171 | /* hardware requires some bits to be set by default */ | |
3172 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3173 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3174 | break; | |
3175 | default: | |
3176 | /* We should do nothing since we don't know this hardware */ | |
3177 | return; | |
3178 | } | |
3179 | ||
3180 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3181 | } | |
3182 | ||
477de6ed AD |
3183 | /** |
3184 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3185 | * @adapter: board private structure | |
3186 | * | |
3187 | * Configure the Rx unit of the MAC after a reset. | |
3188 | **/ | |
3189 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3190 | { | |
3191 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3192 | int i; |
3193 | u32 rxctrl; | |
477de6ed AD |
3194 | |
3195 | /* disable receives while setting up the descriptors */ | |
3196 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3197 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3198 | ||
3199 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3200 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3201 | |
9e10e045 | 3202 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3203 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3204 | |
477de6ed AD |
3205 | /* set_rx_buffer_len must be called before ring initialization */ |
3206 | ixgbe_set_rx_buffer_len(adapter); | |
3207 | ||
3208 | /* | |
3209 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3210 | * the Base and Length of the Rx Descriptor Ring | |
3211 | */ | |
9e10e045 AD |
3212 | for (i = 0; i < adapter->num_rx_queues; i++) |
3213 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3214 | |
9e10e045 AD |
3215 | /* disable drop enable for 82598 parts */ |
3216 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3217 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3218 | ||
3219 | /* enable all receives */ | |
3220 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3221 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3222 | } |
3223 | ||
8e586137 | 3224 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3225 | { |
3226 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3227 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3228 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3229 | |
3230 | /* add VID to filter table */ | |
1ada1b1b | 3231 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3232 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
3233 | |
3234 | return 0; | |
068c89b0 DS |
3235 | } |
3236 | ||
8e586137 | 3237 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3238 | { |
3239 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3240 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3241 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3242 | |
068c89b0 | 3243 | /* remove VID from filter table */ |
1ada1b1b | 3244 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3245 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
3246 | |
3247 | return 0; | |
068c89b0 DS |
3248 | } |
3249 | ||
5f6c0181 JB |
3250 | /** |
3251 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3252 | * @adapter: driver data | |
3253 | */ | |
3254 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3255 | { | |
3256 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3257 | u32 vlnctrl; |
3258 | ||
3259 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3260 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3261 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3262 | } | |
3263 | ||
3264 | /** | |
3265 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3266 | * @adapter: driver data | |
3267 | */ | |
3268 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3269 | { | |
3270 | struct ixgbe_hw *hw = &adapter->hw; | |
3271 | u32 vlnctrl; | |
3272 | ||
3273 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3274 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3275 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3276 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3277 | } | |
3278 | ||
3279 | /** | |
3280 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3281 | * @adapter: driver data | |
3282 | */ | |
3283 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3284 | { | |
3285 | struct ixgbe_hw *hw = &adapter->hw; | |
3286 | u32 vlnctrl; | |
5f6c0181 JB |
3287 | int i, j; |
3288 | ||
3289 | switch (hw->mac.type) { | |
3290 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3291 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3292 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3293 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3294 | break; | |
3295 | case ixgbe_mac_82599EB: | |
b93a2226 | 3296 | case ixgbe_mac_X540: |
5f6c0181 JB |
3297 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3298 | j = adapter->rx_ring[i]->reg_idx; | |
3299 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3300 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3301 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3302 | } | |
3303 | break; | |
3304 | default: | |
3305 | break; | |
3306 | } | |
3307 | } | |
3308 | ||
3309 | /** | |
f62bbb5e | 3310 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3311 | * @adapter: driver data |
3312 | */ | |
f62bbb5e | 3313 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3314 | { |
3315 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3316 | u32 vlnctrl; |
5f6c0181 JB |
3317 | int i, j; |
3318 | ||
3319 | switch (hw->mac.type) { | |
3320 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3321 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3322 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3323 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3324 | break; | |
3325 | case ixgbe_mac_82599EB: | |
b93a2226 | 3326 | case ixgbe_mac_X540: |
5f6c0181 JB |
3327 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3328 | j = adapter->rx_ring[i]->reg_idx; | |
3329 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3330 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3331 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3332 | } | |
3333 | break; | |
3334 | default: | |
3335 | break; | |
3336 | } | |
3337 | } | |
3338 | ||
9a799d71 AK |
3339 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3340 | { | |
f62bbb5e | 3341 | u16 vid; |
9a799d71 | 3342 | |
f62bbb5e JG |
3343 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3344 | ||
3345 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3346 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3347 | } |
3348 | ||
2850062a AD |
3349 | /** |
3350 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3351 | * @netdev: network interface device structure | |
3352 | * | |
3353 | * Writes unicast address list to the RAR table. | |
3354 | * Returns: -ENOMEM on failure/insufficient address space | |
3355 | * 0 on no addresses written | |
3356 | * X on writing X addresses to the RAR table | |
3357 | **/ | |
3358 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3359 | { | |
3360 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3361 | struct ixgbe_hw *hw = &adapter->hw; | |
3362 | unsigned int vfn = adapter->num_vfs; | |
a1cbb15c | 3363 | unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS; |
2850062a AD |
3364 | int count = 0; |
3365 | ||
3366 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3367 | if (netdev_uc_count(netdev) > rar_entries) | |
3368 | return -ENOMEM; | |
3369 | ||
3370 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3371 | struct netdev_hw_addr *ha; | |
3372 | /* return error if we do not support writing to RAR table */ | |
3373 | if (!hw->mac.ops.set_rar) | |
3374 | return -ENOMEM; | |
3375 | ||
3376 | netdev_for_each_uc_addr(ha, netdev) { | |
3377 | if (!rar_entries) | |
3378 | break; | |
3379 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3380 | vfn, IXGBE_RAH_AV); | |
3381 | count++; | |
3382 | } | |
3383 | } | |
3384 | /* write the addresses in reverse order to avoid write combining */ | |
3385 | for (; rar_entries > 0 ; rar_entries--) | |
3386 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3387 | ||
3388 | return count; | |
3389 | } | |
3390 | ||
9a799d71 | 3391 | /** |
2c5645cf | 3392 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3393 | * @netdev: network interface device structure |
3394 | * | |
2c5645cf CL |
3395 | * The set_rx_method entry point is called whenever the unicast/multicast |
3396 | * address list or the network interface flags are updated. This routine is | |
3397 | * responsible for configuring the hardware for proper unicast, multicast and | |
3398 | * promiscuous mode. | |
9a799d71 | 3399 | **/ |
7f870475 | 3400 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3401 | { |
3402 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3403 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3404 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3405 | int count; | |
9a799d71 AK |
3406 | |
3407 | /* Check for Promiscuous and All Multicast modes */ | |
3408 | ||
3409 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3410 | ||
f5dc442b | 3411 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 3412 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
3413 | fctrl |= IXGBE_FCTRL_BAM; |
3414 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3415 | fctrl |= IXGBE_FCTRL_PMCF; | |
3416 | ||
2850062a AD |
3417 | /* clear the bits we are changing the status of */ |
3418 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3419 | ||
9a799d71 | 3420 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3421 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3422 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3423 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3424 | /* don't hardware filter vlans in promisc mode */ |
3425 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3426 | } else { |
746b9f02 PM |
3427 | if (netdev->flags & IFF_ALLMULTI) { |
3428 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3429 | vmolr |= IXGBE_VMOLR_MPE; |
3430 | } else { | |
3431 | /* | |
3432 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3433 | * then we should just turn on promiscuous mode so |
2850062a AD |
3434 | * that we can at least receive multicast traffic |
3435 | */ | |
3436 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3437 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3438 | } |
5f6c0181 | 3439 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3440 | hw->addr_ctrl.user_set_promisc = false; |
9dcb373c JF |
3441 | } |
3442 | ||
3443 | /* | |
3444 | * Write addresses to available RAR registers, if there is not | |
3445 | * sufficient space to store all the addresses then enable | |
3446 | * unicast promiscuous mode | |
3447 | */ | |
3448 | count = ixgbe_write_uc_addr_list(netdev); | |
3449 | if (count < 0) { | |
3450 | fctrl |= IXGBE_FCTRL_UPE; | |
3451 | vmolr |= IXGBE_VMOLR_ROPE; | |
9a799d71 AK |
3452 | } |
3453 | ||
2850062a | 3454 | if (adapter->num_vfs) { |
1cdd1ec8 | 3455 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3456 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3457 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3458 | IXGBE_VMOLR_ROPE); | |
3459 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3460 | } | |
3461 | ||
3f2d1c0f BG |
3462 | /* This is useful for sniffing bad packets. */ |
3463 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3464 | /* UPE and MPE will be handled by normal PROMISC logic | |
3465 | * in e1000e_set_rx_mode */ | |
3466 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
3467 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
3468 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3469 | ||
3470 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
3471 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
3472 | } | |
3473 | ||
2850062a | 3474 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e JG |
3475 | |
3476 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3477 | ixgbe_vlan_strip_enable(adapter); | |
3478 | else | |
3479 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3480 | } |
3481 | ||
021230d4 AV |
3482 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3483 | { | |
3484 | int q_idx; | |
3485 | struct ixgbe_q_vector *q_vector; | |
3486 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3487 | ||
3488 | /* legacy and MSI only use one vector */ | |
3489 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3490 | q_vectors = 1; | |
3491 | ||
3492 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3493 | q_vector = adapter->q_vector[q_idx]; |
4ff7fb12 | 3494 | napi_enable(&q_vector->napi); |
021230d4 AV |
3495 | } |
3496 | } | |
3497 | ||
3498 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3499 | { | |
3500 | int q_idx; | |
3501 | struct ixgbe_q_vector *q_vector; | |
3502 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3503 | ||
3504 | /* legacy and MSI only use one vector */ | |
3505 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3506 | q_vectors = 1; | |
3507 | ||
3508 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3509 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
3510 | napi_disable(&q_vector->napi); |
3511 | } | |
3512 | } | |
3513 | ||
7a6b6f51 | 3514 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3515 | /* |
3516 | * ixgbe_configure_dcb - Configure DCB hardware | |
3517 | * @adapter: ixgbe adapter struct | |
3518 | * | |
3519 | * This is called by the driver on open to configure the DCB hardware. | |
3520 | * This is also called by the gennetlink interface when reconfiguring | |
3521 | * the DCB state. | |
3522 | */ | |
3523 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3524 | { | |
3525 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3526 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3527 | |
67ebd791 AD |
3528 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3529 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3530 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3531 | return; | |
3532 | } | |
3533 | ||
3534 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3535 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3536 | ||
2f90b865 | 3537 | |
2f90b865 | 3538 | /* Enable VLAN tag insert/strip */ |
f62bbb5e | 3539 | adapter->netdev->features |= NETIF_F_HW_VLAN_RX; |
5f6c0181 | 3540 | |
2f90b865 | 3541 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 | 3542 | |
971060b1 | 3543 | #ifdef IXGBE_FCOE |
b120818e JF |
3544 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
3545 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 3546 | #endif |
b120818e JF |
3547 | |
3548 | /* reconfigure the hardware */ | |
3549 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
3550 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
3551 | DCB_TX_CONFIG); | |
3552 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3553 | DCB_RX_CONFIG); | |
3554 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
3555 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
3556 | ixgbe_dcb_hw_ets(&adapter->hw, | |
3557 | adapter->ixgbe_ieee_ets, | |
3558 | max_frame); | |
3559 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
3560 | adapter->ixgbe_ieee_pfc->pfc_en, | |
3561 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 3562 | } |
8187cd48 JF |
3563 | |
3564 | /* Enable RSS Hash per TC */ | |
3565 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3566 | int i; | |
3567 | u32 reg = 0; | |
3568 | ||
3569 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
3570 | u8 msb = 0; | |
3571 | u8 cnt = adapter->netdev->tc_to_txq[i].count; | |
3572 | ||
3573 | while (cnt >>= 1) | |
3574 | msb++; | |
3575 | ||
3576 | reg |= msb << IXGBE_RQTC_SHIFT_TC(i); | |
3577 | } | |
3578 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg); | |
3579 | } | |
2f90b865 | 3580 | } |
9da712d2 JF |
3581 | #endif |
3582 | ||
3583 | /* Additional bittime to account for IXGBE framing */ | |
3584 | #define IXGBE_ETH_FRAMING 20 | |
3585 | ||
3586 | /* | |
3587 | * ixgbe_hpbthresh - calculate high water mark for flow control | |
3588 | * | |
3589 | * @adapter: board private structure to calculate for | |
3590 | * @pb - packet buffer to calculate | |
3591 | */ | |
3592 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
3593 | { | |
3594 | struct ixgbe_hw *hw = &adapter->hw; | |
3595 | struct net_device *dev = adapter->netdev; | |
3596 | int link, tc, kb, marker; | |
3597 | u32 dv_id, rx_pba; | |
3598 | ||
3599 | /* Calculate max LAN frame size */ | |
3600 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
3601 | ||
3602 | #ifdef IXGBE_FCOE | |
3603 | /* FCoE traffic class uses FCOE jumbo frames */ | |
3604 | if (dev->features & NETIF_F_FCOE_MTU) { | |
3605 | int fcoe_pb = 0; | |
2f90b865 | 3606 | |
9da712d2 JF |
3607 | #ifdef CONFIG_IXGBE_DCB |
3608 | fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up); | |
3609 | ||
3610 | #endif | |
3611 | if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) | |
3612 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
3613 | } | |
2f90b865 | 3614 | #endif |
80605c65 | 3615 | |
9da712d2 JF |
3616 | /* Calculate delay value for device */ |
3617 | switch (hw->mac.type) { | |
3618 | case ixgbe_mac_X540: | |
3619 | dv_id = IXGBE_DV_X540(link, tc); | |
3620 | break; | |
3621 | default: | |
3622 | dv_id = IXGBE_DV(link, tc); | |
3623 | break; | |
3624 | } | |
3625 | ||
3626 | /* Loopback switch introduces additional latency */ | |
3627 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3628 | dv_id += IXGBE_B2BT(tc); | |
3629 | ||
3630 | /* Delay value is calculated in bit times convert to KB */ | |
3631 | kb = IXGBE_BT2KB(dv_id); | |
3632 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
3633 | ||
3634 | marker = rx_pba - kb; | |
3635 | ||
3636 | /* It is possible that the packet buffer is not large enough | |
3637 | * to provide required headroom. In this case throw an error | |
3638 | * to user and a do the best we can. | |
3639 | */ | |
3640 | if (marker < 0) { | |
3641 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
3642 | "headroom to support flow control." | |
3643 | "Decrease MTU or number of traffic classes\n", pb); | |
3644 | marker = tc + 1; | |
3645 | } | |
3646 | ||
3647 | return marker; | |
3648 | } | |
3649 | ||
3650 | /* | |
3651 | * ixgbe_lpbthresh - calculate low water mark for for flow control | |
3652 | * | |
3653 | * @adapter: board private structure to calculate for | |
3654 | * @pb - packet buffer to calculate | |
3655 | */ | |
3656 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter) | |
3657 | { | |
3658 | struct ixgbe_hw *hw = &adapter->hw; | |
3659 | struct net_device *dev = adapter->netdev; | |
3660 | int tc; | |
3661 | u32 dv_id; | |
3662 | ||
3663 | /* Calculate max LAN frame size */ | |
3664 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
3665 | ||
3666 | /* Calculate delay value for device */ | |
3667 | switch (hw->mac.type) { | |
3668 | case ixgbe_mac_X540: | |
3669 | dv_id = IXGBE_LOW_DV_X540(tc); | |
3670 | break; | |
3671 | default: | |
3672 | dv_id = IXGBE_LOW_DV(tc); | |
3673 | break; | |
3674 | } | |
3675 | ||
3676 | /* Delay value is calculated in bit times convert to KB */ | |
3677 | return IXGBE_BT2KB(dv_id); | |
3678 | } | |
3679 | ||
3680 | /* | |
3681 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
3682 | */ | |
3683 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
3684 | { | |
3685 | struct ixgbe_hw *hw = &adapter->hw; | |
3686 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
3687 | int i; | |
3688 | ||
3689 | if (!num_tc) | |
3690 | num_tc = 1; | |
3691 | ||
3692 | hw->fc.low_water = ixgbe_lpbthresh(adapter); | |
3693 | ||
3694 | for (i = 0; i < num_tc; i++) { | |
3695 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
3696 | ||
3697 | /* Low water marks must not be larger than high water marks */ | |
3698 | if (hw->fc.low_water > hw->fc.high_water[i]) | |
3699 | hw->fc.low_water = 0; | |
3700 | } | |
3701 | } | |
3702 | ||
80605c65 JF |
3703 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
3704 | { | |
80605c65 | 3705 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
3706 | int hdrm; |
3707 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
3708 | |
3709 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3710 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
3711 | hdrm = 32 << adapter->fdir_pballoc; |
3712 | else | |
3713 | hdrm = 0; | |
80605c65 | 3714 | |
f7e1027f | 3715 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 3716 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
3717 | } |
3718 | ||
e4911d57 AD |
3719 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
3720 | { | |
3721 | struct ixgbe_hw *hw = &adapter->hw; | |
3722 | struct hlist_node *node, *node2; | |
3723 | struct ixgbe_fdir_filter *filter; | |
3724 | ||
3725 | spin_lock(&adapter->fdir_perfect_lock); | |
3726 | ||
3727 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
3728 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
3729 | ||
3730 | hlist_for_each_entry_safe(filter, node, node2, | |
3731 | &adapter->fdir_filter_list, fdir_node) { | |
3732 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
3733 | &filter->filter, |
3734 | filter->sw_idx, | |
3735 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
3736 | IXGBE_FDIR_DROP_QUEUE : | |
3737 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
3738 | } |
3739 | ||
3740 | spin_unlock(&adapter->fdir_perfect_lock); | |
3741 | } | |
3742 | ||
9a799d71 AK |
3743 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3744 | { | |
d2f5e7f3 AS |
3745 | struct ixgbe_hw *hw = &adapter->hw; |
3746 | ||
80605c65 | 3747 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 3748 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3749 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3750 | #endif |
9a799d71 | 3751 | |
4c1d7b4b | 3752 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
3753 | ixgbe_restore_vlan(adapter); |
3754 | ||
eacd73f7 YZ |
3755 | #ifdef IXGBE_FCOE |
3756 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3757 | ixgbe_configure_fcoe(adapter); | |
3758 | ||
3759 | #endif /* IXGBE_FCOE */ | |
d2f5e7f3 AS |
3760 | |
3761 | switch (hw->mac.type) { | |
3762 | case ixgbe_mac_82599EB: | |
3763 | case ixgbe_mac_X540: | |
3764 | hw->mac.ops.disable_rx_buff(hw); | |
3765 | break; | |
3766 | default: | |
3767 | break; | |
3768 | } | |
3769 | ||
c4cf55e5 | 3770 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
3771 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
3772 | adapter->fdir_pballoc); | |
e4911d57 AD |
3773 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
3774 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
3775 | adapter->fdir_pballoc); | |
3776 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 3777 | } |
4c1d7b4b | 3778 | |
d2f5e7f3 AS |
3779 | switch (hw->mac.type) { |
3780 | case ixgbe_mac_82599EB: | |
3781 | case ixgbe_mac_X540: | |
3782 | hw->mac.ops.enable_rx_buff(hw); | |
3783 | break; | |
3784 | default: | |
3785 | break; | |
3786 | } | |
3787 | ||
933d41f1 | 3788 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3789 | |
9a799d71 AK |
3790 | ixgbe_configure_tx(adapter); |
3791 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3792 | } |
3793 | ||
e8e26350 PW |
3794 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3795 | { | |
3796 | switch (hw->phy.type) { | |
3797 | case ixgbe_phy_sfp_avago: | |
3798 | case ixgbe_phy_sfp_ftl: | |
3799 | case ixgbe_phy_sfp_intel: | |
3800 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3801 | case ixgbe_phy_sfp_passive_tyco: |
3802 | case ixgbe_phy_sfp_passive_unknown: | |
3803 | case ixgbe_phy_sfp_active_unknown: | |
3804 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 | 3805 | return true; |
8917b447 AD |
3806 | case ixgbe_phy_nl: |
3807 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3808 | return true; | |
e8e26350 PW |
3809 | default: |
3810 | return false; | |
3811 | } | |
3812 | } | |
3813 | ||
0ecc061d | 3814 | /** |
e8e26350 PW |
3815 | * ixgbe_sfp_link_config - set up SFP+ link |
3816 | * @adapter: pointer to private adapter struct | |
3817 | **/ | |
3818 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3819 | { | |
7086400d | 3820 | /* |
52f33af8 | 3821 | * We are assuming the worst case scenario here, and that |
7086400d AD |
3822 | * is that an SFP was inserted/removed after the reset |
3823 | * but before SFP detection was enabled. As such the best | |
3824 | * solution is to just start searching as soon as we start | |
3825 | */ | |
3826 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3827 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 3828 | |
7086400d | 3829 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
e8e26350 PW |
3830 | } |
3831 | ||
3832 | /** | |
3833 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3834 | * @hw: pointer to private hardware struct |
3835 | * | |
3836 | * Returns 0 on success, negative on failure | |
3837 | **/ | |
e8e26350 | 3838 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3839 | { |
3840 | u32 autoneg; | |
8620a103 | 3841 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3842 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3843 | ||
3844 | if (hw->mac.ops.check_link) | |
3845 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3846 | ||
3847 | if (ret) | |
3848 | goto link_cfg_out; | |
3849 | ||
0b0c2b31 ET |
3850 | autoneg = hw->phy.autoneg_advertised; |
3851 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
3852 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3853 | &negotiation); | |
0ecc061d PWJ |
3854 | if (ret) |
3855 | goto link_cfg_out; | |
3856 | ||
8620a103 MC |
3857 | if (hw->mac.ops.setup_link) |
3858 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3859 | link_cfg_out: |
3860 | return ret; | |
3861 | } | |
3862 | ||
a34bcfff | 3863 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3864 | { |
9a799d71 | 3865 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3866 | u32 gpie = 0; |
9a799d71 | 3867 | |
9b471446 | 3868 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3869 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3870 | IXGBE_GPIE_OCD; | |
3871 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3872 | /* |
3873 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3874 | * this saves a register write for every interrupt | |
3875 | */ | |
3876 | switch (hw->mac.type) { | |
3877 | case ixgbe_mac_82598EB: | |
3878 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3879 | break; | |
9b471446 | 3880 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3881 | case ixgbe_mac_X540: |
3882 | default: | |
9b471446 JB |
3883 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3884 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3885 | break; | |
3886 | } | |
3887 | } else { | |
021230d4 AV |
3888 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3889 | * specifically only auto mask tx and rx interrupts */ | |
3890 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3891 | } | |
9a799d71 | 3892 | |
a34bcfff AD |
3893 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3894 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3895 | ||
3896 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3897 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3898 | gpie |= IXGBE_GPIE_VTMODE_64; | |
119fc60a MC |
3899 | } |
3900 | ||
5fdd31f9 | 3901 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
3902 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
3903 | switch (adapter->hw.mac.type) { | |
3904 | case ixgbe_mac_82599EB: | |
3905 | gpie |= IXGBE_SDP0_GPIEN; | |
3906 | break; | |
3907 | case ixgbe_mac_X540: | |
3908 | gpie |= IXGBE_EIMS_TS; | |
3909 | break; | |
3910 | default: | |
3911 | break; | |
3912 | } | |
3913 | } | |
5fdd31f9 | 3914 | |
a34bcfff AD |
3915 | /* Enable fan failure interrupt */ |
3916 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3917 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3918 | |
2698b208 | 3919 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
3920 | gpie |= IXGBE_SDP1_GPIEN; |
3921 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 3922 | } |
a34bcfff AD |
3923 | |
3924 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3925 | } | |
3926 | ||
c7ccde0f | 3927 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
3928 | { |
3929 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3930 | int err; |
a34bcfff AD |
3931 | u32 ctrl_ext; |
3932 | ||
3933 | ixgbe_get_hw_control(adapter); | |
3934 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 3935 | |
9a799d71 AK |
3936 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3937 | ixgbe_configure_msix(adapter); | |
3938 | else | |
3939 | ixgbe_configure_msi_and_legacy(adapter); | |
3940 | ||
c6ecf39a DS |
3941 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
3942 | if (hw->mac.ops.enable_tx_laser && | |
3943 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 3944 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 3945 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
3946 | hw->mac.ops.enable_tx_laser(hw); |
3947 | ||
9a799d71 | 3948 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3949 | ixgbe_napi_enable_all(adapter); |
3950 | ||
73c4b7cd AD |
3951 | if (ixgbe_is_sfp(hw)) { |
3952 | ixgbe_sfp_link_config(adapter); | |
3953 | } else { | |
3954 | err = ixgbe_non_sfp_link_config(hw); | |
3955 | if (err) | |
3956 | e_err(probe, "link_config FAILED %d\n", err); | |
3957 | } | |
3958 | ||
021230d4 AV |
3959 | /* clear any pending interrupts, may auto mask */ |
3960 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 3961 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 3962 | |
bf069c97 DS |
3963 | /* |
3964 | * If this adapter has a fan, check to see if we had a failure | |
3965 | * before we enabled the interrupt. | |
3966 | */ | |
3967 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3968 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
3969 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 3970 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
3971 | } |
3972 | ||
1da100bb | 3973 | /* enable transmits */ |
477de6ed | 3974 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 3975 | |
9a799d71 AK |
3976 | /* bring the link up in the watchdog, this could race with our first |
3977 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
3978 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
3979 | adapter->link_check_timeout = jiffies; | |
7086400d | 3980 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
3981 | |
3982 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
3983 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
3984 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
3985 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
3986 | } |
3987 | ||
d4f80882 AV |
3988 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
3989 | { | |
3990 | WARN_ON(in_interrupt()); | |
7086400d AD |
3991 | /* put off any impending NetWatchDogTimeout */ |
3992 | adapter->netdev->trans_start = jiffies; | |
3993 | ||
d4f80882 | 3994 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 3995 | usleep_range(1000, 2000); |
d4f80882 | 3996 | ixgbe_down(adapter); |
5809a1ae GR |
3997 | /* |
3998 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
3999 | * back up to give the VFs time to respond to the reset. The | |
4000 | * two second wait is based upon the watchdog timer cycle in | |
4001 | * the VF driver. | |
4002 | */ | |
4003 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4004 | msleep(2000); | |
d4f80882 AV |
4005 | ixgbe_up(adapter); |
4006 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
4007 | } | |
4008 | ||
c7ccde0f | 4009 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4010 | { |
4011 | /* hardware has been reset, we need to reload some things */ | |
4012 | ixgbe_configure(adapter); | |
4013 | ||
c7ccde0f | 4014 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4015 | } |
4016 | ||
4017 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
4018 | { | |
c44ade9e | 4019 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
4020 | int err; |
4021 | ||
7086400d AD |
4022 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
4023 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
4024 | usleep_range(1000, 2000); | |
4025 | ||
4026 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
4027 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
4028 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
4029 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
4030 | ||
8ca783ab | 4031 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
4032 | switch (err) { |
4033 | case 0: | |
4034 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 4035 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
4036 | break; |
4037 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 4038 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 4039 | break; |
794caeb2 PWJ |
4040 | case IXGBE_ERR_EEPROM_VERSION: |
4041 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 4042 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 4043 | "Please be aware there may be issues associated with " |
849c4542 ET |
4044 | "your hardware. If you are experiencing problems " |
4045 | "please contact your Intel or hardware " | |
4046 | "representative who provided you with this " | |
4047 | "hardware.\n"); | |
794caeb2 | 4048 | break; |
da4dd0f7 | 4049 | default: |
849c4542 | 4050 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 4051 | } |
9a799d71 | 4052 | |
7086400d AD |
4053 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
4054 | ||
9a799d71 | 4055 | /* reprogram the RAR[0] in case user changed it. */ |
1cdd1ec8 GR |
4056 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
4057 | IXGBE_RAH_AV); | |
9a799d71 AK |
4058 | } |
4059 | ||
f800326d AD |
4060 | /** |
4061 | * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers | |
4062 | * @rx_ring: ring to setup | |
4063 | * | |
4064 | * On many IA platforms the L1 cache has a critical stride of 4K, this | |
4065 | * results in each receive buffer starting in the same cache set. To help | |
4066 | * reduce the pressure on this cache set we can interleave the offsets so | |
4067 | * that only every other buffer will be in the same cache set. | |
4068 | **/ | |
4069 | static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring) | |
4070 | { | |
4071 | struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info; | |
4072 | u16 i; | |
4073 | ||
4074 | for (i = 0; i < rx_ring->count; i += 2) { | |
4075 | rx_buffer[0].page_offset = 0; | |
4076 | rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring); | |
4077 | rx_buffer = &rx_buffer[2]; | |
4078 | } | |
4079 | } | |
4080 | ||
9a799d71 AK |
4081 | /** |
4082 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
4083 | * @rx_ring: ring to free buffers from |
4084 | **/ | |
b6ec895e | 4085 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 4086 | { |
b6ec895e | 4087 | struct device *dev = rx_ring->dev; |
9a799d71 | 4088 | unsigned long size; |
b6ec895e | 4089 | u16 i; |
9a799d71 | 4090 | |
84418e3b AD |
4091 | /* ring already cleared, nothing to do */ |
4092 | if (!rx_ring->rx_buffer_info) | |
4093 | return; | |
9a799d71 | 4094 | |
84418e3b | 4095 | /* Free all the Rx ring sk_buffs */ |
9a799d71 | 4096 | for (i = 0; i < rx_ring->count; i++) { |
f800326d AD |
4097 | struct ixgbe_rx_buffer *rx_buffer; |
4098 | ||
4099 | rx_buffer = &rx_ring->rx_buffer_info[i]; | |
4100 | if (rx_buffer->skb) { | |
4101 | struct sk_buff *skb = rx_buffer->skb; | |
4102 | if (IXGBE_CB(skb)->page_released) { | |
4103 | dma_unmap_page(dev, | |
4104 | IXGBE_CB(skb)->dma, | |
4105 | ixgbe_rx_bufsz(rx_ring), | |
4106 | DMA_FROM_DEVICE); | |
4107 | IXGBE_CB(skb)->page_released = false; | |
4c1975d7 AD |
4108 | } |
4109 | dev_kfree_skb(skb); | |
9a799d71 | 4110 | } |
f800326d AD |
4111 | rx_buffer->skb = NULL; |
4112 | if (rx_buffer->dma) | |
4113 | dma_unmap_page(dev, rx_buffer->dma, | |
4114 | ixgbe_rx_pg_size(rx_ring), | |
4115 | DMA_FROM_DEVICE); | |
4116 | rx_buffer->dma = 0; | |
4117 | if (rx_buffer->page) | |
dd411ec4 AD |
4118 | __free_pages(rx_buffer->page, |
4119 | ixgbe_rx_pg_order(rx_ring)); | |
f800326d | 4120 | rx_buffer->page = NULL; |
9a799d71 AK |
4121 | } |
4122 | ||
4123 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4124 | memset(rx_ring->rx_buffer_info, 0, size); | |
4125 | ||
f800326d AD |
4126 | ixgbe_init_rx_page_offset(rx_ring); |
4127 | ||
9a799d71 AK |
4128 | /* Zero out the descriptor ring */ |
4129 | memset(rx_ring->desc, 0, rx_ring->size); | |
4130 | ||
f800326d | 4131 | rx_ring->next_to_alloc = 0; |
9a799d71 AK |
4132 | rx_ring->next_to_clean = 0; |
4133 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4134 | } |
4135 | ||
4136 | /** | |
4137 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4138 | * @tx_ring: ring to be cleaned |
4139 | **/ | |
b6ec895e | 4140 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4141 | { |
4142 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4143 | unsigned long size; | |
b6ec895e | 4144 | u16 i; |
9a799d71 | 4145 | |
84418e3b AD |
4146 | /* ring already cleared, nothing to do */ |
4147 | if (!tx_ring->tx_buffer_info) | |
4148 | return; | |
9a799d71 | 4149 | |
84418e3b | 4150 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4151 | for (i = 0; i < tx_ring->count; i++) { |
4152 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4153 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4154 | } |
4155 | ||
dad8a3b3 JF |
4156 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
4157 | ||
9a799d71 AK |
4158 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
4159 | memset(tx_ring->tx_buffer_info, 0, size); | |
4160 | ||
4161 | /* Zero out the descriptor ring */ | |
4162 | memset(tx_ring->desc, 0, tx_ring->size); | |
4163 | ||
4164 | tx_ring->next_to_use = 0; | |
4165 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4166 | } |
4167 | ||
4168 | /** | |
021230d4 | 4169 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4170 | * @adapter: board private structure |
4171 | **/ | |
021230d4 | 4172 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4173 | { |
4174 | int i; | |
4175 | ||
021230d4 | 4176 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4177 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4178 | } |
4179 | ||
4180 | /** | |
021230d4 | 4181 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4182 | * @adapter: board private structure |
4183 | **/ | |
021230d4 | 4184 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4185 | { |
4186 | int i; | |
4187 | ||
021230d4 | 4188 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4189 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4190 | } |
4191 | ||
e4911d57 AD |
4192 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
4193 | { | |
4194 | struct hlist_node *node, *node2; | |
4195 | struct ixgbe_fdir_filter *filter; | |
4196 | ||
4197 | spin_lock(&adapter->fdir_perfect_lock); | |
4198 | ||
4199 | hlist_for_each_entry_safe(filter, node, node2, | |
4200 | &adapter->fdir_filter_list, fdir_node) { | |
4201 | hlist_del(&filter->fdir_node); | |
4202 | kfree(filter); | |
4203 | } | |
4204 | adapter->fdir_filter_count = 0; | |
4205 | ||
4206 | spin_unlock(&adapter->fdir_perfect_lock); | |
4207 | } | |
4208 | ||
9a799d71 AK |
4209 | void ixgbe_down(struct ixgbe_adapter *adapter) |
4210 | { | |
4211 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4212 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4213 | u32 rxctrl; |
bf29ee6c | 4214 | int i; |
9a799d71 AK |
4215 | |
4216 | /* signal that we are down to the interrupt handler */ | |
4217 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4218 | ||
4219 | /* disable receives */ | |
7f821875 JB |
4220 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4221 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4222 | |
2d39d576 YZ |
4223 | /* disable all enabled rx queues */ |
4224 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4225 | /* this call also flushes the previous write */ | |
4226 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4227 | ||
032b4325 | 4228 | usleep_range(10000, 20000); |
9a799d71 | 4229 | |
7f821875 JB |
4230 | netif_tx_stop_all_queues(netdev); |
4231 | ||
7086400d | 4232 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
4233 | netif_carrier_off(netdev); |
4234 | netif_tx_disable(netdev); | |
4235 | ||
4236 | ixgbe_irq_disable(adapter); | |
4237 | ||
4238 | ixgbe_napi_disable_all(adapter); | |
4239 | ||
d034acf1 AD |
4240 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
4241 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
4242 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
4243 | ||
4244 | del_timer_sync(&adapter->service_timer); | |
4245 | ||
34cecbbf | 4246 | if (adapter->num_vfs) { |
8e34d1aa AD |
4247 | /* Clear EITR Select mapping */ |
4248 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
4249 | |
4250 | /* Mark all the VFs as inactive */ | |
4251 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 4252 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 4253 | |
34cecbbf AD |
4254 | /* ping all the active vfs to let them know we are going down */ |
4255 | ixgbe_ping_all_vfs(adapter); | |
4256 | ||
4257 | /* Disable all VFTE/VFRE TX/RX */ | |
4258 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
4259 | } |
4260 | ||
7f821875 JB |
4261 | /* disable transmits in the hardware now that interrupts are off */ |
4262 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 4263 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 4264 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 4265 | } |
34cecbbf AD |
4266 | |
4267 | /* Disable the Tx DMA engine on 82599 and X540 */ | |
bd508178 AD |
4268 | switch (hw->mac.type) { |
4269 | case ixgbe_mac_82599EB: | |
b93a2226 | 4270 | case ixgbe_mac_X540: |
88512539 | 4271 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4272 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4273 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4274 | break; |
4275 | default: | |
4276 | break; | |
4277 | } | |
7f821875 | 4278 | |
6f4a0e45 PL |
4279 | if (!pci_channel_offline(adapter->pdev)) |
4280 | ixgbe_reset(adapter); | |
c6ecf39a DS |
4281 | |
4282 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
4283 | if (hw->mac.ops.disable_tx_laser && | |
4284 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4285 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
4286 | (hw->mac.type == ixgbe_mac_82599EB)))) |
4287 | hw->mac.ops.disable_tx_laser(hw); | |
4288 | ||
9a799d71 AK |
4289 | ixgbe_clean_all_tx_rings(adapter); |
4290 | ixgbe_clean_all_rx_rings(adapter); | |
4291 | ||
5dd2d332 | 4292 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4293 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4294 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4295 | #endif |
9a799d71 AK |
4296 | } |
4297 | ||
9a799d71 AK |
4298 | /** |
4299 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4300 | * @netdev: network interface device structure | |
4301 | **/ | |
4302 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4303 | { | |
4304 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4305 | ||
4306 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 4307 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
4308 | } |
4309 | ||
9a799d71 AK |
4310 | /** |
4311 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4312 | * @adapter: board private structure to initialize | |
4313 | * | |
4314 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4315 | * Fields are initialized based on PCI device information and | |
4316 | * OS network device settings (MTU size). | |
4317 | **/ | |
4318 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4319 | { | |
4320 | struct ixgbe_hw *hw = &adapter->hw; | |
4321 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 4322 | unsigned int rss; |
7a6b6f51 | 4323 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4324 | int j; |
4325 | struct tc_configuration *tc; | |
4326 | #endif | |
021230d4 | 4327 | |
c44ade9e JB |
4328 | /* PCI config space info */ |
4329 | ||
4330 | hw->vendor_id = pdev->vendor; | |
4331 | hw->device_id = pdev->device; | |
4332 | hw->revision_id = pdev->revision; | |
4333 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4334 | hw->subsystem_device_id = pdev->subsystem_device; | |
4335 | ||
021230d4 | 4336 | /* Set capability flags */ |
3ed69d7e | 4337 | rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus()); |
021230d4 AV |
4338 | adapter->ring_feature[RING_F_RSS].indices = rss; |
4339 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
bd508178 AD |
4340 | switch (hw->mac.type) { |
4341 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
4342 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
4343 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 4344 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bd508178 | 4345 | break; |
b93a2226 | 4346 | case ixgbe_mac_X540: |
4f51bf70 JK |
4347 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; |
4348 | case ixgbe_mac_82599EB: | |
e8e26350 | 4349 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
4350 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4351 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
4352 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
4353 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 AD |
4354 | /* Flow Director hash filters enabled */ |
4355 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4356 | adapter->atr_sample_rate = 20; | |
c4cf55e5 | 4357 | adapter->ring_feature[RING_F_FDIR].indices = |
e8e9f696 | 4358 | IXGBE_MAX_FDIR_INDICES; |
c04f6ca8 | 4359 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
eacd73f7 | 4360 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4361 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4362 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
4363 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 4364 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 | 4365 | /* Default traffic class to use for FCoE */ |
56075a98 | 4366 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 4367 | #endif |
eacd73f7 | 4368 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
4369 | break; |
4370 | default: | |
4371 | break; | |
f8212f97 | 4372 | } |
2f90b865 | 4373 | |
1fc5f038 AD |
4374 | /* n-tuple support exists, always init our spinlock */ |
4375 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4376 | ||
7a6b6f51 | 4377 | #ifdef CONFIG_IXGBE_DCB |
4de2a022 JF |
4378 | switch (hw->mac.type) { |
4379 | case ixgbe_mac_X540: | |
4380 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; | |
4381 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
4382 | break; | |
4383 | default: | |
4384 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
4385 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
4386 | break; | |
4387 | } | |
4388 | ||
2f90b865 AD |
4389 | /* Configure DCB traffic classes */ |
4390 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4391 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4392 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4393 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4394 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4395 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4396 | tc->dcb_pfc = pfc_disabled; | |
4397 | } | |
4de2a022 JF |
4398 | |
4399 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
4400 | tc = &adapter->dcb_cfg.tc_config[0]; | |
4401 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4402 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4403 | ||
2f90b865 AD |
4404 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; |
4405 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 4406 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 4407 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 4408 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
f525c6d2 JF |
4409 | memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, |
4410 | sizeof(adapter->temp_dcb_cfg)); | |
2f90b865 AD |
4411 | |
4412 | #endif | |
9a799d71 AK |
4413 | |
4414 | /* default flow control settings */ | |
cd7664f6 | 4415 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4416 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
9da712d2 | 4417 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
4418 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
4419 | hw->fc.send_xon = true; | |
71fd570b | 4420 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4421 | |
30efa5a3 | 4422 | /* enable itr by default in dynamic mode */ |
f7554a2b | 4423 | adapter->rx_itr_setting = 1; |
f7554a2b | 4424 | adapter->tx_itr_setting = 1; |
30efa5a3 | 4425 | |
30efa5a3 JB |
4426 | /* set default ring sizes */ |
4427 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4428 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4429 | ||
bd198058 | 4430 | /* set default work limits */ |
59224555 | 4431 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 4432 | |
9a799d71 | 4433 | /* initialize eeprom parameters */ |
c44ade9e | 4434 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 4435 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
4436 | return -EIO; |
4437 | } | |
4438 | ||
9a799d71 AK |
4439 | set_bit(__IXGBE_DOWN, &adapter->state); |
4440 | ||
4441 | return 0; | |
4442 | } | |
4443 | ||
4444 | /** | |
4445 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 4446 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4447 | * |
4448 | * Return 0 on success, negative on failure | |
4449 | **/ | |
b6ec895e | 4450 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4451 | { |
b6ec895e | 4452 | struct device *dev = tx_ring->dev; |
de88eeeb AD |
4453 | int orig_node = dev_to_node(dev); |
4454 | int numa_node = -1; | |
9a799d71 AK |
4455 | int size; |
4456 | ||
3a581073 | 4457 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
4458 | |
4459 | if (tx_ring->q_vector) | |
4460 | numa_node = tx_ring->q_vector->numa_node; | |
4461 | ||
4462 | tx_ring->tx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4463 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 4464 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
4465 | if (!tx_ring->tx_buffer_info) |
4466 | goto err; | |
9a799d71 AK |
4467 | |
4468 | /* round up to nearest 4K */ | |
12207e49 | 4469 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4470 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4471 | |
de88eeeb AD |
4472 | set_dev_node(dev, numa_node); |
4473 | tx_ring->desc = dma_alloc_coherent(dev, | |
4474 | tx_ring->size, | |
4475 | &tx_ring->dma, | |
4476 | GFP_KERNEL); | |
4477 | set_dev_node(dev, orig_node); | |
4478 | if (!tx_ring->desc) | |
4479 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
4480 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
4481 | if (!tx_ring->desc) |
4482 | goto err; | |
9a799d71 | 4483 | |
3a581073 JB |
4484 | tx_ring->next_to_use = 0; |
4485 | tx_ring->next_to_clean = 0; | |
9a799d71 | 4486 | return 0; |
e01c31a5 JB |
4487 | |
4488 | err: | |
4489 | vfree(tx_ring->tx_buffer_info); | |
4490 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 4491 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 4492 | return -ENOMEM; |
9a799d71 AK |
4493 | } |
4494 | ||
69888674 AD |
4495 | /** |
4496 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4497 | * @adapter: board private structure | |
4498 | * | |
4499 | * If this function returns with an error, then it's possible one or | |
4500 | * more of the rings is populated (while the rest are not). It is the | |
4501 | * callers duty to clean those orphaned rings. | |
4502 | * | |
4503 | * Return 0 on success, negative on failure | |
4504 | **/ | |
4505 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4506 | { | |
4507 | int i, err = 0; | |
4508 | ||
4509 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 4510 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
4511 | if (!err) |
4512 | continue; | |
396e799c | 4513 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
69888674 AD |
4514 | break; |
4515 | } | |
4516 | ||
4517 | return err; | |
4518 | } | |
4519 | ||
9a799d71 AK |
4520 | /** |
4521 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 4522 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4523 | * |
4524 | * Returns 0 on success, negative on failure | |
4525 | **/ | |
b6ec895e | 4526 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4527 | { |
b6ec895e | 4528 | struct device *dev = rx_ring->dev; |
de88eeeb AD |
4529 | int orig_node = dev_to_node(dev); |
4530 | int numa_node = -1; | |
021230d4 | 4531 | int size; |
9a799d71 | 4532 | |
3a581073 | 4533 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
4534 | |
4535 | if (rx_ring->q_vector) | |
4536 | numa_node = rx_ring->q_vector->numa_node; | |
4537 | ||
4538 | rx_ring->rx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4539 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 4540 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
4541 | if (!rx_ring->rx_buffer_info) |
4542 | goto err; | |
9a799d71 | 4543 | |
9a799d71 | 4544 | /* Round up to nearest 4K */ |
3a581073 JB |
4545 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
4546 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 4547 | |
de88eeeb AD |
4548 | set_dev_node(dev, numa_node); |
4549 | rx_ring->desc = dma_alloc_coherent(dev, | |
4550 | rx_ring->size, | |
4551 | &rx_ring->dma, | |
4552 | GFP_KERNEL); | |
4553 | set_dev_node(dev, orig_node); | |
4554 | if (!rx_ring->desc) | |
4555 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
4556 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
4557 | if (!rx_ring->desc) |
4558 | goto err; | |
9a799d71 | 4559 | |
3a581073 JB |
4560 | rx_ring->next_to_clean = 0; |
4561 | rx_ring->next_to_use = 0; | |
9a799d71 | 4562 | |
f800326d AD |
4563 | ixgbe_init_rx_page_offset(rx_ring); |
4564 | ||
9a799d71 | 4565 | return 0; |
b6ec895e AD |
4566 | err: |
4567 | vfree(rx_ring->rx_buffer_info); | |
4568 | rx_ring->rx_buffer_info = NULL; | |
4569 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 4570 | return -ENOMEM; |
9a799d71 AK |
4571 | } |
4572 | ||
69888674 AD |
4573 | /** |
4574 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
4575 | * @adapter: board private structure | |
4576 | * | |
4577 | * If this function returns with an error, then it's possible one or | |
4578 | * more of the rings is populated (while the rest are not). It is the | |
4579 | * callers duty to clean those orphaned rings. | |
4580 | * | |
4581 | * Return 0 on success, negative on failure | |
4582 | **/ | |
69888674 AD |
4583 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
4584 | { | |
4585 | int i, err = 0; | |
4586 | ||
4587 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 4588 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
4589 | if (!err) |
4590 | continue; | |
396e799c | 4591 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
69888674 AD |
4592 | break; |
4593 | } | |
4594 | ||
4595 | return err; | |
4596 | } | |
4597 | ||
9a799d71 AK |
4598 | /** |
4599 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
4600 | * @tx_ring: Tx descriptor ring for a specific queue |
4601 | * | |
4602 | * Free all transmit software resources | |
4603 | **/ | |
b6ec895e | 4604 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4605 | { |
b6ec895e | 4606 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
4607 | |
4608 | vfree(tx_ring->tx_buffer_info); | |
4609 | tx_ring->tx_buffer_info = NULL; | |
4610 | ||
b6ec895e AD |
4611 | /* if not set, then don't free */ |
4612 | if (!tx_ring->desc) | |
4613 | return; | |
4614 | ||
4615 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
4616 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
4617 | |
4618 | tx_ring->desc = NULL; | |
4619 | } | |
4620 | ||
4621 | /** | |
4622 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4623 | * @adapter: board private structure | |
4624 | * | |
4625 | * Free all transmit software resources | |
4626 | **/ | |
4627 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4628 | { | |
4629 | int i; | |
4630 | ||
4631 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 4632 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 4633 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
4634 | } |
4635 | ||
4636 | /** | |
b4617240 | 4637 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4638 | * @rx_ring: ring to clean the resources from |
4639 | * | |
4640 | * Free all receive software resources | |
4641 | **/ | |
b6ec895e | 4642 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4643 | { |
b6ec895e | 4644 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
4645 | |
4646 | vfree(rx_ring->rx_buffer_info); | |
4647 | rx_ring->rx_buffer_info = NULL; | |
4648 | ||
b6ec895e AD |
4649 | /* if not set, then don't free */ |
4650 | if (!rx_ring->desc) | |
4651 | return; | |
4652 | ||
4653 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
4654 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
4655 | |
4656 | rx_ring->desc = NULL; | |
4657 | } | |
4658 | ||
4659 | /** | |
4660 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4661 | * @adapter: board private structure | |
4662 | * | |
4663 | * Free all receive software resources | |
4664 | **/ | |
4665 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4666 | { | |
4667 | int i; | |
4668 | ||
4669 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4670 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 4671 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
4672 | } |
4673 | ||
9a799d71 AK |
4674 | /** |
4675 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4676 | * @netdev: network interface device structure | |
4677 | * @new_mtu: new value for maximum frame size | |
4678 | * | |
4679 | * Returns 0 on success, negative on failure | |
4680 | **/ | |
4681 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4682 | { | |
4683 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4684 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4685 | ||
42c783c5 | 4686 | /* MTU < 68 is an error and causes problems on some kernels */ |
655309e9 AD |
4687 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) |
4688 | return -EINVAL; | |
4689 | ||
4690 | /* | |
4691 | * For 82599EB we cannot allow PF to change MTU greater than 1500 | |
4692 | * in SR-IOV mode as it may cause buffer overruns in guest VFs that | |
4693 | * don't allocate and chain buffers correctly. | |
4694 | */ | |
4695 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
4696 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
4697 | (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
e9f98072 | 4698 | return -EINVAL; |
9a799d71 | 4699 | |
396e799c | 4700 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 4701 | |
021230d4 | 4702 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4703 | netdev->mtu = new_mtu; |
4704 | ||
d4f80882 AV |
4705 | if (netif_running(netdev)) |
4706 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4707 | |
4708 | return 0; | |
4709 | } | |
4710 | ||
4711 | /** | |
4712 | * ixgbe_open - Called when a network interface is made active | |
4713 | * @netdev: network interface device structure | |
4714 | * | |
4715 | * Returns 0 on success, negative value on failure | |
4716 | * | |
4717 | * The open entry point is called when a network interface is made | |
4718 | * active by the system (IFF_UP). At this point all resources needed | |
4719 | * for transmit and receive operations are allocated, the interrupt | |
4720 | * handler is registered with the OS, the watchdog timer is started, | |
4721 | * and the stack is notified that the interface is ready. | |
4722 | **/ | |
4723 | static int ixgbe_open(struct net_device *netdev) | |
4724 | { | |
4725 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4726 | int err; | |
4bebfaa5 AK |
4727 | |
4728 | /* disallow open during test */ | |
4729 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4730 | return -EBUSY; | |
9a799d71 | 4731 | |
54386467 JB |
4732 | netif_carrier_off(netdev); |
4733 | ||
9a799d71 AK |
4734 | /* allocate transmit descriptors */ |
4735 | err = ixgbe_setup_all_tx_resources(adapter); | |
4736 | if (err) | |
4737 | goto err_setup_tx; | |
4738 | ||
9a799d71 AK |
4739 | /* allocate receive descriptors */ |
4740 | err = ixgbe_setup_all_rx_resources(adapter); | |
4741 | if (err) | |
4742 | goto err_setup_rx; | |
4743 | ||
4744 | ixgbe_configure(adapter); | |
4745 | ||
021230d4 | 4746 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4747 | if (err) |
4748 | goto err_req_irq; | |
4749 | ||
c7ccde0f | 4750 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4751 | |
4752 | return 0; | |
4753 | ||
9a799d71 | 4754 | err_req_irq: |
9a799d71 | 4755 | err_setup_rx: |
a20a1199 | 4756 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 4757 | err_setup_tx: |
a20a1199 | 4758 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
4759 | ixgbe_reset(adapter); |
4760 | ||
4761 | return err; | |
4762 | } | |
4763 | ||
4764 | /** | |
4765 | * ixgbe_close - Disables a network interface | |
4766 | * @netdev: network interface device structure | |
4767 | * | |
4768 | * Returns 0, this is not allowed to fail | |
4769 | * | |
4770 | * The close entry point is called when an interface is de-activated | |
4771 | * by the OS. The hardware is still under the drivers control, but | |
4772 | * needs to be disabled. A global MAC reset is issued to stop the | |
4773 | * hardware, and all transmit and receive resources are freed. | |
4774 | **/ | |
4775 | static int ixgbe_close(struct net_device *netdev) | |
4776 | { | |
4777 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
4778 | |
4779 | ixgbe_down(adapter); | |
4780 | ixgbe_free_irq(adapter); | |
4781 | ||
e4911d57 AD |
4782 | ixgbe_fdir_filter_exit(adapter); |
4783 | ||
9a799d71 AK |
4784 | ixgbe_free_all_tx_resources(adapter); |
4785 | ixgbe_free_all_rx_resources(adapter); | |
4786 | ||
5eba3699 | 4787 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4788 | |
4789 | return 0; | |
4790 | } | |
4791 | ||
b3c8b4ba AD |
4792 | #ifdef CONFIG_PM |
4793 | static int ixgbe_resume(struct pci_dev *pdev) | |
4794 | { | |
c60fbb00 AD |
4795 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4796 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
4797 | u32 err; |
4798 | ||
4799 | pci_set_power_state(pdev, PCI_D0); | |
4800 | pci_restore_state(pdev); | |
656ab817 DS |
4801 | /* |
4802 | * pci_restore_state clears dev->state_saved so call | |
4803 | * pci_save_state to restore it. | |
4804 | */ | |
4805 | pci_save_state(pdev); | |
9ce77666 | 4806 | |
4807 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4808 | if (err) { |
849c4542 | 4809 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
4810 | return err; |
4811 | } | |
4812 | pci_set_master(pdev); | |
4813 | ||
dd4d8ca6 | 4814 | pci_wake_from_d3(pdev, false); |
b3c8b4ba | 4815 | |
34948a94 | 4816 | rtnl_lock(); |
b3c8b4ba | 4817 | err = ixgbe_init_interrupt_scheme(adapter); |
34948a94 | 4818 | rtnl_unlock(); |
b3c8b4ba | 4819 | if (err) { |
849c4542 | 4820 | e_dev_err("Cannot initialize interrupts for device\n"); |
b3c8b4ba AD |
4821 | return err; |
4822 | } | |
4823 | ||
b3c8b4ba AD |
4824 | ixgbe_reset(adapter); |
4825 | ||
495dce12 WJP |
4826 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
4827 | ||
b3c8b4ba | 4828 | if (netif_running(netdev)) { |
c60fbb00 | 4829 | err = ixgbe_open(netdev); |
b3c8b4ba AD |
4830 | if (err) |
4831 | return err; | |
4832 | } | |
4833 | ||
4834 | netif_device_attach(netdev); | |
4835 | ||
4836 | return 0; | |
4837 | } | |
b3c8b4ba | 4838 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
4839 | |
4840 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 4841 | { |
c60fbb00 AD |
4842 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4843 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
4844 | struct ixgbe_hw *hw = &adapter->hw; |
4845 | u32 ctrl, fctrl; | |
4846 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
4847 | #ifdef CONFIG_PM |
4848 | int retval = 0; | |
4849 | #endif | |
4850 | ||
4851 | netif_device_detach(netdev); | |
4852 | ||
4853 | if (netif_running(netdev)) { | |
ab6039a7 | 4854 | rtnl_lock(); |
b3c8b4ba AD |
4855 | ixgbe_down(adapter); |
4856 | ixgbe_free_irq(adapter); | |
4857 | ixgbe_free_all_tx_resources(adapter); | |
4858 | ixgbe_free_all_rx_resources(adapter); | |
ab6039a7 | 4859 | rtnl_unlock(); |
b3c8b4ba | 4860 | } |
b3c8b4ba | 4861 | |
5f5ae6fc AD |
4862 | ixgbe_clear_interrupt_scheme(adapter); |
4863 | ||
b3c8b4ba AD |
4864 | #ifdef CONFIG_PM |
4865 | retval = pci_save_state(pdev); | |
4866 | if (retval) | |
4867 | return retval; | |
4df10466 | 4868 | |
b3c8b4ba | 4869 | #endif |
e8e26350 PW |
4870 | if (wufc) { |
4871 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4872 | |
c509e754 DS |
4873 | /* |
4874 | * enable the optics for both mult-speed fiber and | |
4875 | * 82599 SFP+ fiber as we can WoL. | |
4876 | */ | |
4877 | if (hw->mac.ops.enable_tx_laser && | |
4878 | (hw->phy.multispeed_fiber || | |
4879 | (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber && | |
4880 | hw->mac.type == ixgbe_mac_82599EB))) | |
4881 | hw->mac.ops.enable_tx_laser(hw); | |
4882 | ||
e8e26350 PW |
4883 | /* turn on all-multi mode if wake on multicast is enabled */ |
4884 | if (wufc & IXGBE_WUFC_MC) { | |
4885 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4886 | fctrl |= IXGBE_FCTRL_MPE; | |
4887 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4888 | } | |
4889 | ||
4890 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4891 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4892 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4893 | ||
4894 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4895 | } else { | |
4896 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4897 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4898 | } | |
4899 | ||
bd508178 AD |
4900 | switch (hw->mac.type) { |
4901 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 4902 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
4903 | break; |
4904 | case ixgbe_mac_82599EB: | |
b93a2226 | 4905 | case ixgbe_mac_X540: |
bd508178 AD |
4906 | pci_wake_from_d3(pdev, !!wufc); |
4907 | break; | |
4908 | default: | |
4909 | break; | |
4910 | } | |
b3c8b4ba | 4911 | |
9d8d05ae RW |
4912 | *enable_wake = !!wufc; |
4913 | ||
b3c8b4ba AD |
4914 | ixgbe_release_hw_control(adapter); |
4915 | ||
4916 | pci_disable_device(pdev); | |
4917 | ||
9d8d05ae RW |
4918 | return 0; |
4919 | } | |
4920 | ||
4921 | #ifdef CONFIG_PM | |
4922 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
4923 | { | |
4924 | int retval; | |
4925 | bool wake; | |
4926 | ||
4927 | retval = __ixgbe_shutdown(pdev, &wake); | |
4928 | if (retval) | |
4929 | return retval; | |
4930 | ||
4931 | if (wake) { | |
4932 | pci_prepare_to_sleep(pdev); | |
4933 | } else { | |
4934 | pci_wake_from_d3(pdev, false); | |
4935 | pci_set_power_state(pdev, PCI_D3hot); | |
4936 | } | |
b3c8b4ba AD |
4937 | |
4938 | return 0; | |
4939 | } | |
9d8d05ae | 4940 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
4941 | |
4942 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
4943 | { | |
9d8d05ae RW |
4944 | bool wake; |
4945 | ||
4946 | __ixgbe_shutdown(pdev, &wake); | |
4947 | ||
4948 | if (system_state == SYSTEM_POWER_OFF) { | |
4949 | pci_wake_from_d3(pdev, wake); | |
4950 | pci_set_power_state(pdev, PCI_D3hot); | |
4951 | } | |
b3c8b4ba AD |
4952 | } |
4953 | ||
9a799d71 AK |
4954 | /** |
4955 | * ixgbe_update_stats - Update the board statistics counters. | |
4956 | * @adapter: board private structure | |
4957 | **/ | |
4958 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
4959 | { | |
2d86f139 | 4960 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 4961 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 4962 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
4963 | u64 total_mpc = 0; |
4964 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
4965 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
4966 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 4967 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
7b859ebc AH |
4968 | #ifdef IXGBE_FCOE |
4969 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
4970 | unsigned int cpu; | |
4971 | u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0; | |
4972 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 4973 | |
d08935c2 DS |
4974 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
4975 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
4976 | return; | |
4977 | ||
94b982b2 | 4978 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 4979 | u64 rsc_count = 0; |
94b982b2 | 4980 | u64 rsc_flush = 0; |
94b982b2 | 4981 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
4982 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
4983 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
4984 | } |
4985 | adapter->rsc_total_count = rsc_count; | |
4986 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
4987 | } |
4988 | ||
5b7da515 AD |
4989 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4990 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
4991 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
4992 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
4993 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 4994 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
4995 | bytes += rx_ring->stats.bytes; |
4996 | packets += rx_ring->stats.packets; | |
4997 | } | |
4998 | adapter->non_eop_descs = non_eop_descs; | |
4999 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5000 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 5001 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
5002 | netdev->stats.rx_bytes = bytes; |
5003 | netdev->stats.rx_packets = packets; | |
5004 | ||
5005 | bytes = 0; | |
5006 | packets = 0; | |
7ca3bc58 | 5007 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5008 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5009 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5010 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5011 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5012 | bytes += tx_ring->stats.bytes; | |
5013 | packets += tx_ring->stats.packets; | |
5014 | } | |
eb985f09 | 5015 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5016 | adapter->tx_busy = tx_busy; |
5017 | netdev->stats.tx_bytes = bytes; | |
5018 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5019 | |
7ca647bd | 5020 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
5021 | |
5022 | /* 8 register reads */ | |
6f11eef7 AV |
5023 | for (i = 0; i < 8; i++) { |
5024 | /* for packet buffers not used, the register should read 0 */ | |
5025 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5026 | missed_rx += mpc; | |
7ca647bd JP |
5027 | hwstats->mpc[i] += mpc; |
5028 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
5029 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5030 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
5031 | switch (hw->mac.type) { |
5032 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
5033 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5034 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5035 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
5036 | hwstats->pxonrxc[i] += |
5037 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5038 | break; |
5039 | case ixgbe_mac_82599EB: | |
b93a2226 | 5040 | case ixgbe_mac_X540: |
bd508178 AD |
5041 | hwstats->pxonrxc[i] += |
5042 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5043 | break; |
5044 | default: | |
5045 | break; | |
e8e26350 | 5046 | } |
6f11eef7 | 5047 | } |
1a70db4b ET |
5048 | |
5049 | /*16 register reads */ | |
5050 | for (i = 0; i < 16; i++) { | |
5051 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5052 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5053 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
5054 | (hw->mac.type == ixgbe_mac_X540)) { | |
5055 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); | |
5056 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
5057 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
5058 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
5059 | } | |
5060 | } | |
5061 | ||
7ca647bd | 5062 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5063 | /* work around hardware counting issue */ |
7ca647bd | 5064 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5065 | |
c84d324c JF |
5066 | ixgbe_update_xoff_received(adapter); |
5067 | ||
6f11eef7 | 5068 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5069 | switch (hw->mac.type) { |
5070 | case ixgbe_mac_82598EB: | |
5071 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5072 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5073 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5074 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5075 | break; | |
b93a2226 | 5076 | case ixgbe_mac_X540: |
58f6bcf9 ET |
5077 | /* OS2BMC stats are X540 only*/ |
5078 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); | |
5079 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
5080 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
5081 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
5082 | case ixgbe_mac_82599EB: | |
a4d4f629 AD |
5083 | for (i = 0; i < 16; i++) |
5084 | adapter->hw_rx_no_dma_resources += | |
5085 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
7ca647bd | 5086 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5087 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5088 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5089 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5090 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5091 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5092 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5093 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5094 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5095 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5096 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5097 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5098 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5099 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5100 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5101 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc AH |
5102 | /* Add up per cpu counters for total ddp aloc fail */ |
5103 | if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) { | |
5104 | for_each_possible_cpu(cpu) { | |
5105 | fcoe_noddp_counts_sum += | |
5106 | *per_cpu_ptr(fcoe->pcpu_noddp, cpu); | |
5107 | fcoe_noddp_ext_buff_counts_sum += | |
5108 | *per_cpu_ptr(fcoe-> | |
5109 | pcpu_noddp_ext_buff, cpu); | |
5110 | } | |
5111 | } | |
5112 | hwstats->fcoe_noddp = fcoe_noddp_counts_sum; | |
5113 | hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum; | |
6d45522c | 5114 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5115 | break; |
5116 | default: | |
5117 | break; | |
e8e26350 | 5118 | } |
9a799d71 | 5119 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5120 | hwstats->bprc += bprc; |
5121 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5122 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5123 | hwstats->mprc -= bprc; |
5124 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5125 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5126 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5127 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5128 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5129 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5130 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5131 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5132 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5133 | hwstats->lxontxc += lxon; |
6f11eef7 | 5134 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 5135 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
5136 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
5137 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5138 | /* |
5139 | * 82598 errata - tx of flow control packets is included in tx counters | |
5140 | */ | |
5141 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5142 | hwstats->gptc -= xon_off_tot; |
5143 | hwstats->mptc -= xon_off_tot; | |
5144 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5145 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5146 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5147 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5148 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5149 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5150 | hwstats->ptc64 -= xon_off_tot; | |
5151 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5152 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5153 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5154 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5155 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5156 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5157 | |
5158 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5159 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5160 | |
5161 | /* Rx Errors */ | |
7ca647bd | 5162 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5163 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5164 | netdev->stats.rx_length_errors = hwstats->rlec; |
5165 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5166 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5167 | } |
5168 | ||
5169 | /** | |
d034acf1 AD |
5170 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
5171 | * @adapter - pointer to the device adapter structure | |
9a799d71 | 5172 | **/ |
d034acf1 | 5173 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 5174 | { |
cf8280ee | 5175 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 5176 | int i; |
cf8280ee | 5177 | |
d034acf1 AD |
5178 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
5179 | return; | |
5180 | ||
5181 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 5182 | |
d034acf1 | 5183 | /* if interface is down do nothing */ |
fe49f04a | 5184 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
5185 | return; |
5186 | ||
5187 | /* do nothing if we are not using signature filters */ | |
5188 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
5189 | return; | |
5190 | ||
5191 | adapter->fdir_overflow++; | |
5192 | ||
93c52dd0 AD |
5193 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
5194 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5195 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
f0f9778d | 5196 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
5197 | /* re-enable flow director interrupts */ |
5198 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
5199 | } else { |
5200 | e_err(probe, "failed to finish FDIR re-initialization, " | |
5201 | "ignored adding FDIR ATR filters\n"); | |
5202 | } | |
93c52dd0 AD |
5203 | } |
5204 | ||
5205 | /** | |
5206 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
5207 | * @adapter - pointer to the device adapter structure | |
5208 | * | |
5209 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 5210 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 5211 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 5212 | * determine if a hang has occurred. |
93c52dd0 AD |
5213 | */ |
5214 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 5215 | { |
cf8280ee | 5216 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5217 | u64 eics = 0; |
5218 | int i; | |
cf8280ee | 5219 | |
93c52dd0 AD |
5220 | /* If we're down or resetting, just bail */ |
5221 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5222 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5223 | return; | |
22d5a71b | 5224 | |
93c52dd0 AD |
5225 | /* Force detection of hung controller */ |
5226 | if (netif_carrier_ok(adapter->netdev)) { | |
5227 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5228 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
5229 | } | |
22d5a71b | 5230 | |
fe49f04a AD |
5231 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
5232 | /* | |
5233 | * for legacy and MSI interrupts don't set any bits | |
5234 | * that are enabled for EIAM, because this operation | |
5235 | * would set *both* EIMS and EICS for any bit in EIAM | |
5236 | */ | |
5237 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
5238 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
5239 | } else { |
5240 | /* get one bit for every active tx/rx interrupt vector */ | |
5241 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
5242 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
efe3d3c8 | 5243 | if (qv->rx.ring || qv->tx.ring) |
93c52dd0 AD |
5244 | eics |= ((u64)1 << i); |
5245 | } | |
cf8280ee | 5246 | } |
9a799d71 | 5247 | |
93c52dd0 | 5248 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a AD |
5249 | ixgbe_irq_rearm_queues(adapter, eics); |
5250 | ||
cf8280ee JB |
5251 | } |
5252 | ||
e8e26350 | 5253 | /** |
93c52dd0 AD |
5254 | * ixgbe_watchdog_update_link - update the link status |
5255 | * @adapter - pointer to the device adapter structure | |
5256 | * @link_speed - pointer to a u32 to store the link_speed | |
e8e26350 | 5257 | **/ |
93c52dd0 | 5258 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 5259 | { |
e8e26350 | 5260 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5261 | u32 link_speed = adapter->link_speed; |
5262 | bool link_up = adapter->link_up; | |
041441d0 | 5263 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; |
e8e26350 | 5264 | |
93c52dd0 AD |
5265 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
5266 | return; | |
5267 | ||
5268 | if (hw->mac.ops.check_link) { | |
5269 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 5270 | } else { |
93c52dd0 AD |
5271 | /* always assume link is up, if no check link function */ |
5272 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
5273 | link_up = true; | |
c4cf55e5 | 5274 | } |
041441d0 AD |
5275 | |
5276 | if (adapter->ixgbe_ieee_pfc) | |
5277 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
5278 | ||
5279 | if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) | |
5280 | hw->mac.ops.fc_enable(hw); | |
93c52dd0 AD |
5281 | |
5282 | if (link_up || | |
5283 | time_after(jiffies, (adapter->link_check_timeout + | |
5284 | IXGBE_TRY_LINK_TIMEOUT))) { | |
5285 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
5286 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
5287 | IXGBE_WRITE_FLUSH(hw); | |
5288 | } | |
5289 | ||
5290 | adapter->link_up = link_up; | |
5291 | adapter->link_speed = link_speed; | |
e8e26350 PW |
5292 | } |
5293 | ||
5294 | /** | |
93c52dd0 AD |
5295 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
5296 | * print link up message | |
5297 | * @adapter - pointer to the device adapter structure | |
e8e26350 | 5298 | **/ |
93c52dd0 | 5299 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 5300 | { |
93c52dd0 | 5301 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 5302 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5303 | u32 link_speed = adapter->link_speed; |
5304 | bool flow_rx, flow_tx; | |
e8e26350 | 5305 | |
93c52dd0 AD |
5306 | /* only continue if link was previously down */ |
5307 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 5308 | return; |
63d6e1d8 | 5309 | |
93c52dd0 | 5310 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 5311 | |
93c52dd0 AD |
5312 | switch (hw->mac.type) { |
5313 | case ixgbe_mac_82598EB: { | |
5314 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5315 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
5316 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
5317 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
5318 | } | |
5319 | break; | |
5320 | case ixgbe_mac_X540: | |
5321 | case ixgbe_mac_82599EB: { | |
5322 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5323 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
5324 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
5325 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
5326 | } | |
5327 | break; | |
5328 | default: | |
5329 | flow_tx = false; | |
5330 | flow_rx = false; | |
5331 | break; | |
e8e26350 | 5332 | } |
93c52dd0 AD |
5333 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
5334 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
5335 | "10 Gbps" : | |
5336 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5337 | "1 Gbps" : | |
5338 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
5339 | "100 Mbps" : | |
5340 | "unknown speed"))), | |
5341 | ((flow_rx && flow_tx) ? "RX/TX" : | |
5342 | (flow_rx ? "RX" : | |
5343 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 5344 | |
93c52dd0 | 5345 | netif_carrier_on(netdev); |
93c52dd0 | 5346 | ixgbe_check_vf_rate_limit(adapter); |
e8e26350 PW |
5347 | } |
5348 | ||
c4cf55e5 | 5349 | /** |
93c52dd0 AD |
5350 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
5351 | * print link down message | |
5352 | * @adapter - pointer to the adapter structure | |
c4cf55e5 | 5353 | **/ |
581330ba | 5354 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) |
c4cf55e5 | 5355 | { |
cf8280ee | 5356 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 5357 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 5358 | |
93c52dd0 AD |
5359 | adapter->link_up = false; |
5360 | adapter->link_speed = 0; | |
cf8280ee | 5361 | |
93c52dd0 AD |
5362 | /* only continue if link was up previously */ |
5363 | if (!netif_carrier_ok(netdev)) | |
5364 | return; | |
264857b8 | 5365 | |
93c52dd0 AD |
5366 | /* poll for SFP+ cable when link is down */ |
5367 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
5368 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 5369 | |
93c52dd0 AD |
5370 | e_info(drv, "NIC Link is Down\n"); |
5371 | netif_carrier_off(netdev); | |
5372 | } | |
e8e26350 | 5373 | |
93c52dd0 AD |
5374 | /** |
5375 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
5376 | * @adapter - pointer to the device adapter structure | |
5377 | **/ | |
5378 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
5379 | { | |
c4cf55e5 | 5380 | int i; |
93c52dd0 | 5381 | int some_tx_pending = 0; |
c4cf55e5 | 5382 | |
93c52dd0 | 5383 | if (!netif_carrier_ok(adapter->netdev)) { |
bc59fcda | 5384 | for (i = 0; i < adapter->num_tx_queues; i++) { |
93c52dd0 | 5385 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5386 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5387 | some_tx_pending = 1; | |
5388 | break; | |
5389 | } | |
5390 | } | |
5391 | ||
5392 | if (some_tx_pending) { | |
5393 | /* We've lost link, so the controller stops DMA, | |
5394 | * but we've got queued Tx work that's never going | |
5395 | * to get done, so reset controller to flush Tx. | |
5396 | * (Do the reset outside of interrupt context). | |
5397 | */ | |
c83c6cbd | 5398 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 5399 | } |
c4cf55e5 | 5400 | } |
c4cf55e5 PWJ |
5401 | } |
5402 | ||
a985b6c3 GR |
5403 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
5404 | { | |
5405 | u32 ssvpc; | |
5406 | ||
5407 | /* Do not perform spoof check for 82598 */ | |
5408 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
5409 | return; | |
5410 | ||
5411 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
5412 | ||
5413 | /* | |
5414 | * ssvpc register is cleared on read, if zero then no | |
5415 | * spoofed packets in the last interval. | |
5416 | */ | |
5417 | if (!ssvpc) | |
5418 | return; | |
5419 | ||
5420 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
5421 | } | |
5422 | ||
93c52dd0 AD |
5423 | /** |
5424 | * ixgbe_watchdog_subtask - check and bring link up | |
5425 | * @adapter - pointer to the device adapter structure | |
5426 | **/ | |
5427 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
5428 | { | |
5429 | /* if interface is down do nothing */ | |
7edebf9a ET |
5430 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5431 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
93c52dd0 AD |
5432 | return; |
5433 | ||
5434 | ixgbe_watchdog_update_link(adapter); | |
5435 | ||
5436 | if (adapter->link_up) | |
5437 | ixgbe_watchdog_link_is_up(adapter); | |
5438 | else | |
5439 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 5440 | |
a985b6c3 | 5441 | ixgbe_spoof_check(adapter); |
9a799d71 | 5442 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
5443 | |
5444 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 5445 | } |
10eec955 | 5446 | |
cf8280ee | 5447 | /** |
7086400d AD |
5448 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
5449 | * @adapter - the ixgbe adapter structure | |
cf8280ee | 5450 | **/ |
7086400d | 5451 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 5452 | { |
cf8280ee | 5453 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 5454 | s32 err; |
cf8280ee | 5455 | |
7086400d AD |
5456 | /* not searching for SFP so there is nothing to do here */ |
5457 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
5458 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5459 | return; | |
10eec955 | 5460 | |
7086400d AD |
5461 | /* someone else is in init, wait until next service event */ |
5462 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5463 | return; | |
cf8280ee | 5464 | |
7086400d AD |
5465 | err = hw->phy.ops.identify_sfp(hw); |
5466 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5467 | goto sfp_out; | |
264857b8 | 5468 | |
7086400d AD |
5469 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
5470 | /* If no cable is present, then we need to reset | |
5471 | * the next time we find a good cable. */ | |
5472 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 5473 | } |
9a799d71 | 5474 | |
7086400d AD |
5475 | /* exit on error */ |
5476 | if (err) | |
5477 | goto sfp_out; | |
e8e26350 | 5478 | |
7086400d AD |
5479 | /* exit if reset not needed */ |
5480 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5481 | goto sfp_out; | |
9a799d71 | 5482 | |
7086400d | 5483 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 5484 | |
7086400d AD |
5485 | /* |
5486 | * A module may be identified correctly, but the EEPROM may not have | |
5487 | * support for that module. setup_sfp() will fail in that case, so | |
5488 | * we should not allow that module to load. | |
5489 | */ | |
5490 | if (hw->mac.type == ixgbe_mac_82598EB) | |
5491 | err = hw->phy.ops.reset(hw); | |
5492 | else | |
5493 | err = hw->mac.ops.setup_sfp(hw); | |
5494 | ||
5495 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5496 | goto sfp_out; | |
5497 | ||
5498 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
5499 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
5500 | ||
5501 | sfp_out: | |
5502 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5503 | ||
5504 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
5505 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
5506 | e_dev_err("failed to initialize because an unsupported " | |
5507 | "SFP+ module type was detected.\n"); | |
5508 | e_dev_err("Reload the driver after installing a " | |
5509 | "supported module.\n"); | |
5510 | unregister_netdev(adapter->netdev); | |
bc59fcda | 5511 | } |
7086400d | 5512 | } |
bc59fcda | 5513 | |
7086400d AD |
5514 | /** |
5515 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
5516 | * @adapter - the ixgbe adapter structure | |
5517 | **/ | |
5518 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
5519 | { | |
5520 | struct ixgbe_hw *hw = &adapter->hw; | |
5521 | u32 autoneg; | |
5522 | bool negotiation; | |
5523 | ||
5524 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
5525 | return; | |
5526 | ||
5527 | /* someone else is in init, wait until next service event */ | |
5528 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5529 | return; | |
5530 | ||
5531 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
5532 | ||
5533 | autoneg = hw->phy.autoneg_advertised; | |
5534 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
5535 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); | |
7086400d AD |
5536 | if (hw->mac.ops.setup_link) |
5537 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
5538 | ||
5539 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
5540 | adapter->link_check_timeout = jiffies; | |
5541 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5542 | } | |
5543 | ||
83c61fa9 GR |
5544 | #ifdef CONFIG_PCI_IOV |
5545 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) | |
5546 | { | |
5547 | int vf; | |
5548 | struct ixgbe_hw *hw = &adapter->hw; | |
5549 | struct net_device *netdev = adapter->netdev; | |
5550 | u32 gpc; | |
5551 | u32 ciaa, ciad; | |
5552 | ||
5553 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
5554 | if (gpc) /* If incrementing then no need for the check below */ | |
5555 | return; | |
5556 | /* | |
5557 | * Check to see if a bad DMA write target from an errant or | |
5558 | * malicious VF has caused a PCIe error. If so then we can | |
5559 | * issue a VFLR to the offending VF(s) and then resume without | |
5560 | * requesting a full slot reset. | |
5561 | */ | |
5562 | ||
5563 | for (vf = 0; vf < adapter->num_vfs; vf++) { | |
5564 | ciaa = (vf << 16) | 0x80000000; | |
5565 | /* 32 bit read so align, we really want status at offset 6 */ | |
5566 | ciaa |= PCI_COMMAND; | |
5567 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5568 | ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599); | |
5569 | ciaa &= 0x7FFFFFFF; | |
5570 | /* disable debug mode asap after reading data */ | |
5571 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5572 | /* Get the upper 16 bits which will be the PCI status reg */ | |
5573 | ciad >>= 16; | |
5574 | if (ciad & PCI_STATUS_REC_MASTER_ABORT) { | |
5575 | netdev_err(netdev, "VF %d Hung DMA\n", vf); | |
5576 | /* Issue VFLR */ | |
5577 | ciaa = (vf << 16) | 0x80000000; | |
5578 | ciaa |= 0xA8; | |
5579 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5580 | ciad = 0x00008000; /* VFLR */ | |
5581 | IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad); | |
5582 | ciaa &= 0x7FFFFFFF; | |
5583 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5584 | } | |
5585 | } | |
5586 | } | |
5587 | ||
5588 | #endif | |
7086400d AD |
5589 | /** |
5590 | * ixgbe_service_timer - Timer Call-back | |
5591 | * @data: pointer to adapter cast into an unsigned long | |
5592 | **/ | |
5593 | static void ixgbe_service_timer(unsigned long data) | |
5594 | { | |
5595 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
5596 | unsigned long next_event_offset; | |
83c61fa9 | 5597 | bool ready = true; |
7086400d | 5598 | |
6bb78cfb AD |
5599 | /* poll faster when waiting for link */ |
5600 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
5601 | next_event_offset = HZ / 10; | |
5602 | else | |
5603 | next_event_offset = HZ * 2; | |
83c61fa9 | 5604 | |
6bb78cfb | 5605 | #ifdef CONFIG_PCI_IOV |
83c61fa9 GR |
5606 | /* |
5607 | * don't bother with SR-IOV VF DMA hang check if there are | |
5608 | * no VFs or the link is down | |
5609 | */ | |
5610 | if (!adapter->num_vfs || | |
6bb78cfb | 5611 | (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
83c61fa9 | 5612 | goto normal_timer_service; |
83c61fa9 GR |
5613 | |
5614 | /* If we have VFs allocated then we must check for DMA hangs */ | |
5615 | ixgbe_check_for_bad_vf(adapter); | |
5616 | next_event_offset = HZ / 50; | |
5617 | adapter->timer_event_accumulator++; | |
5618 | ||
6bb78cfb | 5619 | if (adapter->timer_event_accumulator >= 100) |
83c61fa9 | 5620 | adapter->timer_event_accumulator = 0; |
7086400d | 5621 | else |
6bb78cfb | 5622 | ready = false; |
7086400d | 5623 | |
6bb78cfb | 5624 | normal_timer_service: |
83c61fa9 | 5625 | #endif |
7086400d AD |
5626 | /* Reset the timer */ |
5627 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
5628 | ||
83c61fa9 GR |
5629 | if (ready) |
5630 | ixgbe_service_event_schedule(adapter); | |
7086400d AD |
5631 | } |
5632 | ||
c83c6cbd AD |
5633 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
5634 | { | |
5635 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
5636 | return; | |
5637 | ||
5638 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
5639 | ||
5640 | /* If we're already down or resetting, just bail */ | |
5641 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5642 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5643 | return; | |
5644 | ||
5645 | ixgbe_dump(adapter); | |
5646 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
5647 | adapter->tx_timeout_count++; | |
5648 | ||
5649 | ixgbe_reinit_locked(adapter); | |
5650 | } | |
5651 | ||
7086400d AD |
5652 | /** |
5653 | * ixgbe_service_task - manages and runs subtasks | |
5654 | * @work: pointer to work_struct containing our data | |
5655 | **/ | |
5656 | static void ixgbe_service_task(struct work_struct *work) | |
5657 | { | |
5658 | struct ixgbe_adapter *adapter = container_of(work, | |
5659 | struct ixgbe_adapter, | |
5660 | service_task); | |
5661 | ||
c83c6cbd | 5662 | ixgbe_reset_subtask(adapter); |
7086400d AD |
5663 | ixgbe_sfp_detection_subtask(adapter); |
5664 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 5665 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 5666 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 5667 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 5668 | ixgbe_check_hang_subtask(adapter); |
7086400d AD |
5669 | |
5670 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
5671 | } |
5672 | ||
fd0db0ed AD |
5673 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
5674 | struct ixgbe_tx_buffer *first, | |
244e27ad | 5675 | u8 *hdr_len) |
897ab156 | 5676 | { |
fd0db0ed | 5677 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5678 | u32 vlan_macip_lens, type_tucmd; |
5679 | u32 mss_l4len_idx, l4len; | |
9a799d71 | 5680 | |
897ab156 AD |
5681 | if (!skb_is_gso(skb)) |
5682 | return 0; | |
9a799d71 | 5683 | |
897ab156 | 5684 | if (skb_header_cloned(skb)) { |
244e27ad | 5685 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
897ab156 AD |
5686 | if (err) |
5687 | return err; | |
9a799d71 | 5688 | } |
9a799d71 | 5689 | |
897ab156 AD |
5690 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
5691 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5692 | ||
244e27ad | 5693 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
897ab156 AD |
5694 | struct iphdr *iph = ip_hdr(skb); |
5695 | iph->tot_len = 0; | |
5696 | iph->check = 0; | |
5697 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5698 | iph->daddr, 0, | |
5699 | IPPROTO_TCP, | |
5700 | 0); | |
5701 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
244e27ad AD |
5702 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5703 | IXGBE_TX_FLAGS_CSUM | | |
5704 | IXGBE_TX_FLAGS_IPV4; | |
897ab156 AD |
5705 | } else if (skb_is_gso_v6(skb)) { |
5706 | ipv6_hdr(skb)->payload_len = 0; | |
5707 | tcp_hdr(skb)->check = | |
5708 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
5709 | &ipv6_hdr(skb)->daddr, | |
5710 | 0, IPPROTO_TCP, 0); | |
244e27ad AD |
5711 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5712 | IXGBE_TX_FLAGS_CSUM; | |
897ab156 AD |
5713 | } |
5714 | ||
091a6246 | 5715 | /* compute header lengths */ |
897ab156 AD |
5716 | l4len = tcp_hdrlen(skb); |
5717 | *hdr_len = skb_transport_offset(skb) + l4len; | |
5718 | ||
091a6246 AD |
5719 | /* update gso size and bytecount with header size */ |
5720 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
5721 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
5722 | ||
897ab156 AD |
5723 | /* mss_l4len_id: use 1 as index for TSO */ |
5724 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; | |
5725 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
5726 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
5727 | ||
5728 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
5729 | vlan_macip_lens = skb_network_header_len(skb); | |
5730 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
244e27ad | 5731 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
897ab156 AD |
5732 | |
5733 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
244e27ad | 5734 | mss_l4len_idx); |
897ab156 AD |
5735 | |
5736 | return 1; | |
5737 | } | |
5738 | ||
244e27ad AD |
5739 | static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, |
5740 | struct ixgbe_tx_buffer *first) | |
7ca647bd | 5741 | { |
fd0db0ed | 5742 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5743 | u32 vlan_macip_lens = 0; |
5744 | u32 mss_l4len_idx = 0; | |
5745 | u32 type_tucmd = 0; | |
7ca647bd | 5746 | |
897ab156 | 5747 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
244e27ad AD |
5748 | if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && |
5749 | !(first->tx_flags & IXGBE_TX_FLAGS_TXSW)) | |
5750 | return; | |
897ab156 AD |
5751 | } else { |
5752 | u8 l4_hdr = 0; | |
244e27ad | 5753 | switch (first->protocol) { |
897ab156 AD |
5754 | case __constant_htons(ETH_P_IP): |
5755 | vlan_macip_lens |= skb_network_header_len(skb); | |
5756 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
5757 | l4_hdr = ip_hdr(skb)->protocol; | |
7ca647bd | 5758 | break; |
897ab156 AD |
5759 | case __constant_htons(ETH_P_IPV6): |
5760 | vlan_macip_lens |= skb_network_header_len(skb); | |
5761 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
5762 | break; | |
5763 | default: | |
5764 | if (unlikely(net_ratelimit())) { | |
5765 | dev_warn(tx_ring->dev, | |
5766 | "partial checksum but proto=%x!\n", | |
244e27ad | 5767 | first->protocol); |
897ab156 | 5768 | } |
7ca647bd JP |
5769 | break; |
5770 | } | |
897ab156 AD |
5771 | |
5772 | switch (l4_hdr) { | |
7ca647bd | 5773 | case IPPROTO_TCP: |
897ab156 AD |
5774 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; |
5775 | mss_l4len_idx = tcp_hdrlen(skb) << | |
5776 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7ca647bd JP |
5777 | break; |
5778 | case IPPROTO_SCTP: | |
897ab156 AD |
5779 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
5780 | mss_l4len_idx = sizeof(struct sctphdr) << | |
5781 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
5782 | break; | |
5783 | case IPPROTO_UDP: | |
5784 | mss_l4len_idx = sizeof(struct udphdr) << | |
5785 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
5786 | break; | |
5787 | default: | |
5788 | if (unlikely(net_ratelimit())) { | |
5789 | dev_warn(tx_ring->dev, | |
5790 | "partial checksum but l4 proto=%x!\n", | |
244e27ad | 5791 | l4_hdr); |
897ab156 | 5792 | } |
7ca647bd JP |
5793 | break; |
5794 | } | |
244e27ad AD |
5795 | |
5796 | /* update TX checksum flag */ | |
5797 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7ca647bd JP |
5798 | } |
5799 | ||
244e27ad | 5800 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
897ab156 | 5801 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
244e27ad | 5802 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
9a799d71 | 5803 | |
897ab156 AD |
5804 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, |
5805 | type_tucmd, mss_l4len_idx); | |
9a799d71 AK |
5806 | } |
5807 | ||
d3d00239 | 5808 | static __le32 ixgbe_tx_cmd_type(u32 tx_flags) |
9a799d71 | 5809 | { |
d3d00239 AD |
5810 | /* set type for advanced descriptor with frame checksum insertion */ |
5811 | __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | | |
5812 | IXGBE_ADVTXD_DCMD_IFCS | | |
5813 | IXGBE_ADVTXD_DCMD_DEXT); | |
9a799d71 | 5814 | |
d3d00239 | 5815 | /* set HW vlan bit if vlan is present */ |
66f32a8b | 5816 | if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN) |
d3d00239 | 5817 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); |
9a799d71 | 5818 | |
d3d00239 AD |
5819 | /* set segmentation enable bits for TSO/FSO */ |
5820 | #ifdef IXGBE_FCOE | |
93f5b3c1 | 5821 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO)) |
d3d00239 AD |
5822 | #else |
5823 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
5824 | #endif | |
5825 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); | |
eacd73f7 | 5826 | |
d3d00239 AD |
5827 | return cmd_type; |
5828 | } | |
9a799d71 | 5829 | |
729739b7 AD |
5830 | static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
5831 | u32 tx_flags, unsigned int paylen) | |
d3d00239 | 5832 | { |
93f5b3c1 | 5833 | __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); |
9a799d71 | 5834 | |
d3d00239 AD |
5835 | /* enable L4 checksum for TSO and TX checksum offload */ |
5836 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
5837 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 5838 | |
93f5b3c1 AD |
5839 | /* enble IPv4 checksum for TSO */ |
5840 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
5841 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 5842 | |
93f5b3c1 AD |
5843 | /* use index 1 context for TSO/FSO/FCOE */ |
5844 | #ifdef IXGBE_FCOE | |
5845 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE)) | |
5846 | #else | |
5847 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
d3d00239 | 5848 | #endif |
93f5b3c1 AD |
5849 | olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT); |
5850 | ||
7f9643fd AD |
5851 | /* |
5852 | * Check Context must be set if Tx switch is enabled, which it | |
5853 | * always is for case where virtual functions are running | |
5854 | */ | |
93f5b3c1 AD |
5855 | #ifdef IXGBE_FCOE |
5856 | if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE)) | |
5857 | #else | |
7f9643fd | 5858 | if (tx_flags & IXGBE_TX_FLAGS_TXSW) |
93f5b3c1 | 5859 | #endif |
7f9643fd AD |
5860 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); |
5861 | ||
729739b7 | 5862 | tx_desc->read.olinfo_status = olinfo_status; |
d3d00239 | 5863 | } |
44df32c5 | 5864 | |
d3d00239 AD |
5865 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
5866 | IXGBE_TXD_CMD_RS) | |
5867 | ||
5868 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 | 5869 | struct ixgbe_tx_buffer *first, |
d3d00239 AD |
5870 | const u8 hdr_len) |
5871 | { | |
729739b7 | 5872 | dma_addr_t dma; |
fd0db0ed | 5873 | struct sk_buff *skb = first->skb; |
729739b7 | 5874 | struct ixgbe_tx_buffer *tx_buffer; |
d3d00239 | 5875 | union ixgbe_adv_tx_desc *tx_desc; |
729739b7 | 5876 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
d3d00239 AD |
5877 | unsigned int data_len = skb->data_len; |
5878 | unsigned int size = skb_headlen(skb); | |
729739b7 | 5879 | unsigned int paylen = skb->len - hdr_len; |
244e27ad | 5880 | u32 tx_flags = first->tx_flags; |
729739b7 | 5881 | __le32 cmd_type; |
d3d00239 | 5882 | u16 i = tx_ring->next_to_use; |
d3d00239 | 5883 | |
729739b7 AD |
5884 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
5885 | ||
5886 | ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen); | |
5887 | cmd_type = ixgbe_tx_cmd_type(tx_flags); | |
5888 | ||
d3d00239 AD |
5889 | #ifdef IXGBE_FCOE |
5890 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
729739b7 | 5891 | if (data_len < sizeof(struct fcoe_crc_eof)) { |
d3d00239 AD |
5892 | size -= sizeof(struct fcoe_crc_eof) - data_len; |
5893 | data_len = 0; | |
729739b7 AD |
5894 | } else { |
5895 | data_len -= sizeof(struct fcoe_crc_eof); | |
9a799d71 AK |
5896 | } |
5897 | } | |
44df32c5 | 5898 | |
d3d00239 | 5899 | #endif |
729739b7 AD |
5900 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
5901 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 5902 | goto dma_error; |
8ad494b0 | 5903 | |
729739b7 AD |
5904 | /* record length, and DMA address */ |
5905 | dma_unmap_len_set(first, len, size); | |
5906 | dma_unmap_addr_set(first, dma, dma); | |
9a799d71 | 5907 | |
729739b7 | 5908 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
e5a43549 | 5909 | |
d3d00239 | 5910 | for (;;) { |
729739b7 | 5911 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
d3d00239 AD |
5912 | tx_desc->read.cmd_type_len = |
5913 | cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); | |
e5a43549 | 5914 | |
d3d00239 | 5915 | i++; |
729739b7 | 5916 | tx_desc++; |
d3d00239 | 5917 | if (i == tx_ring->count) { |
e4f74028 | 5918 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
5919 | i = 0; |
5920 | } | |
729739b7 AD |
5921 | |
5922 | dma += IXGBE_MAX_DATA_PER_TXD; | |
5923 | size -= IXGBE_MAX_DATA_PER_TXD; | |
5924 | ||
5925 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
5926 | tx_desc->read.olinfo_status = 0; | |
d3d00239 | 5927 | } |
e5a43549 | 5928 | |
729739b7 AD |
5929 | if (likely(!data_len)) |
5930 | break; | |
9a799d71 | 5931 | |
f43f313e BG |
5932 | if (unlikely(skb->no_fcs)) |
5933 | cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS)); | |
d3d00239 | 5934 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
9a799d71 | 5935 | |
729739b7 AD |
5936 | i++; |
5937 | tx_desc++; | |
5938 | if (i == tx_ring->count) { | |
5939 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
5940 | i = 0; | |
5941 | } | |
9a799d71 | 5942 | |
d3d00239 | 5943 | #ifdef IXGBE_FCOE |
9e903e08 | 5944 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 5945 | #else |
9e903e08 | 5946 | size = skb_frag_size(frag); |
d3d00239 AD |
5947 | #endif |
5948 | data_len -= size; | |
9a799d71 | 5949 | |
729739b7 AD |
5950 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
5951 | DMA_TO_DEVICE); | |
5952 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 5953 | goto dma_error; |
9a799d71 | 5954 | |
729739b7 AD |
5955 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
5956 | dma_unmap_len_set(tx_buffer, len, size); | |
5957 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
9a799d71 | 5958 | |
729739b7 AD |
5959 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
5960 | tx_desc->read.olinfo_status = 0; | |
9a799d71 | 5961 | |
729739b7 AD |
5962 | frag++; |
5963 | } | |
9a799d71 | 5964 | |
729739b7 AD |
5965 | /* write last descriptor with RS and EOP bits */ |
5966 | cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD); | |
5967 | tx_desc->read.cmd_type_len = cmd_type; | |
eacd73f7 | 5968 | |
091a6246 | 5969 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
b2d96e0a | 5970 | |
d3d00239 AD |
5971 | /* set the timestamp */ |
5972 | first->time_stamp = jiffies; | |
9a799d71 AK |
5973 | |
5974 | /* | |
729739b7 AD |
5975 | * Force memory writes to complete before letting h/w know there |
5976 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
5977 | * memory model archs, such as IA-64). | |
5978 | * | |
5979 | * We also need this memory barrier to make certain all of the | |
5980 | * status bits have been updated before next_to_watch is written. | |
9a799d71 AK |
5981 | */ |
5982 | wmb(); | |
5983 | ||
d3d00239 AD |
5984 | /* set next_to_watch value indicating a packet is present */ |
5985 | first->next_to_watch = tx_desc; | |
5986 | ||
729739b7 AD |
5987 | i++; |
5988 | if (i == tx_ring->count) | |
5989 | i = 0; | |
5990 | ||
5991 | tx_ring->next_to_use = i; | |
5992 | ||
d3d00239 | 5993 | /* notify HW of packet */ |
84ea2591 | 5994 | writel(i, tx_ring->tail); |
d3d00239 AD |
5995 | |
5996 | return; | |
5997 | dma_error: | |
729739b7 | 5998 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
d3d00239 AD |
5999 | |
6000 | /* clear dma mappings for failed tx_buffer_info map */ | |
6001 | for (;;) { | |
729739b7 AD |
6002 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6003 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
6004 | if (tx_buffer == first) | |
d3d00239 AD |
6005 | break; |
6006 | if (i == 0) | |
6007 | i = tx_ring->count; | |
6008 | i--; | |
6009 | } | |
6010 | ||
d3d00239 | 6011 | tx_ring->next_to_use = i; |
9a799d71 AK |
6012 | } |
6013 | ||
fd0db0ed | 6014 | static void ixgbe_atr(struct ixgbe_ring *ring, |
244e27ad | 6015 | struct ixgbe_tx_buffer *first) |
69830529 AD |
6016 | { |
6017 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6018 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6019 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6020 | union { | |
6021 | unsigned char *network; | |
6022 | struct iphdr *ipv4; | |
6023 | struct ipv6hdr *ipv6; | |
6024 | } hdr; | |
ee9e0f0b | 6025 | struct tcphdr *th; |
905e4a41 | 6026 | __be16 vlan_id; |
c4cf55e5 | 6027 | |
69830529 AD |
6028 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6029 | if (!q_vector) | |
6030 | return; | |
6031 | ||
6032 | /* do nothing if sampling is disabled */ | |
6033 | if (!ring->atr_sample_rate) | |
d3ead241 | 6034 | return; |
c4cf55e5 | 6035 | |
69830529 | 6036 | ring->atr_count++; |
c4cf55e5 | 6037 | |
69830529 | 6038 | /* snag network header to get L4 type and address */ |
fd0db0ed | 6039 | hdr.network = skb_network_header(first->skb); |
69830529 AD |
6040 | |
6041 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
244e27ad | 6042 | if ((first->protocol != __constant_htons(ETH_P_IPV6) || |
69830529 | 6043 | hdr.ipv6->nexthdr != IPPROTO_TCP) && |
244e27ad | 6044 | (first->protocol != __constant_htons(ETH_P_IP) || |
69830529 AD |
6045 | hdr.ipv4->protocol != IPPROTO_TCP)) |
6046 | return; | |
ee9e0f0b | 6047 | |
fd0db0ed | 6048 | th = tcp_hdr(first->skb); |
c4cf55e5 | 6049 | |
66f32a8b AD |
6050 | /* skip this packet since it is invalid or the socket is closing */ |
6051 | if (!th || th->fin) | |
69830529 AD |
6052 | return; |
6053 | ||
6054 | /* sample on all syn packets or once every atr sample count */ | |
6055 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6056 | return; | |
6057 | ||
6058 | /* reset sample count */ | |
6059 | ring->atr_count = 0; | |
6060 | ||
244e27ad | 6061 | vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); |
69830529 AD |
6062 | |
6063 | /* | |
6064 | * src and dst are inverted, think how the receiver sees them | |
6065 | * | |
6066 | * The input is broken into two sections, a non-compressed section | |
6067 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6068 | * is XORed together and stored in the compressed dword. | |
6069 | */ | |
6070 | input.formatted.vlan_id = vlan_id; | |
6071 | ||
6072 | /* | |
6073 | * since src port and flex bytes occupy the same word XOR them together | |
6074 | * and write the value to source port portion of compressed dword | |
6075 | */ | |
244e27ad | 6076 | if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
69830529 AD |
6077 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); |
6078 | else | |
244e27ad | 6079 | common.port.src ^= th->dest ^ first->protocol; |
69830529 AD |
6080 | common.port.dst ^= th->source; |
6081 | ||
244e27ad | 6082 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
69830529 AD |
6083 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; |
6084 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6085 | } else { | |
6086 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6087 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6088 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6089 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6090 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6091 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6092 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6093 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6094 | hdr.ipv6->daddr.s6_addr32[3]; | |
6095 | } | |
c4cf55e5 PWJ |
6096 | |
6097 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6098 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6099 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6100 | } |
6101 | ||
63544e9c | 6102 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6103 | { |
fc77dc3c | 6104 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6105 | /* Herbert's original patch had: |
6106 | * smp_mb__after_netif_stop_queue(); | |
6107 | * but since that doesn't exist yet, just open code it. */ | |
6108 | smp_mb(); | |
6109 | ||
6110 | /* We need to check again in a case another CPU has just | |
6111 | * made room available. */ | |
7d4987de | 6112 | if (likely(ixgbe_desc_unused(tx_ring) < size)) |
e092be60 AV |
6113 | return -EBUSY; |
6114 | ||
6115 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 6116 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 6117 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
6118 | return 0; |
6119 | } | |
6120 | ||
82d4e46e | 6121 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6122 | { |
7d4987de | 6123 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) |
e092be60 | 6124 | return 0; |
fc77dc3c | 6125 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
6126 | } |
6127 | ||
09a3b1f8 SH |
6128 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6129 | { | |
6130 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6440752c AD |
6131 | int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
6132 | smp_processor_id(); | |
56075a98 | 6133 | #ifdef IXGBE_FCOE |
6440752c | 6134 | __be16 protocol = vlan_get_protocol(skb); |
5e09a105 | 6135 | |
e5b64635 JF |
6136 | if (((protocol == htons(ETH_P_FCOE)) || |
6137 | (protocol == htons(ETH_P_FIP))) && | |
6138 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
6139 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
6140 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
6141 | return txq; | |
56075a98 JF |
6142 | } |
6143 | #endif | |
6144 | ||
fdd3d631 KK |
6145 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6146 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6147 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6148 | return txq; |
fdd3d631 | 6149 | } |
c4cf55e5 | 6150 | |
09a3b1f8 SH |
6151 | return skb_tx_hash(dev, skb); |
6152 | } | |
6153 | ||
fc77dc3c | 6154 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
6155 | struct ixgbe_adapter *adapter, |
6156 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6157 | { |
d3d00239 | 6158 | struct ixgbe_tx_buffer *first; |
5f715823 | 6159 | int tso; |
d3d00239 | 6160 | u32 tx_flags = 0; |
a535c30e AD |
6161 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD |
6162 | unsigned short f; | |
6163 | #endif | |
a535c30e | 6164 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 6165 | __be16 protocol = skb->protocol; |
63544e9c | 6166 | u8 hdr_len = 0; |
5e09a105 | 6167 | |
a535c30e AD |
6168 | /* |
6169 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 6170 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
6171 | * + 2 desc gap to keep tail from touching head, |
6172 | * + 1 desc for context descriptor, | |
6173 | * otherwise try next time | |
6174 | */ | |
6175 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
6176 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
6177 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
6178 | #else | |
6179 | count += skb_shinfo(skb)->nr_frags; | |
6180 | #endif | |
6181 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { | |
6182 | tx_ring->tx_stats.tx_busy++; | |
6183 | return NETDEV_TX_BUSY; | |
6184 | } | |
6185 | ||
fd0db0ed AD |
6186 | /* record the location of the first descriptor for this packet */ |
6187 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
6188 | first->skb = skb; | |
091a6246 AD |
6189 | first->bytecount = skb->len; |
6190 | first->gso_segs = 1; | |
fd0db0ed | 6191 | |
66f32a8b | 6192 | /* if we have a HW VLAN tag being added default to the HW one */ |
eab6d18d | 6193 | if (vlan_tx_tag_present(skb)) { |
66f32a8b AD |
6194 | tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; |
6195 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
6196 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
6197 | } else if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6198 | struct vlan_hdr *vhdr, _vhdr; | |
6199 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
6200 | if (!vhdr) | |
6201 | goto out_drop; | |
6202 | ||
6203 | protocol = vhdr->h_vlan_encapsulated_proto; | |
9e0c5648 AD |
6204 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
6205 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
6206 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
6207 | } | |
6208 | ||
9e0c5648 AD |
6209 | #ifdef CONFIG_PCI_IOV |
6210 | /* | |
6211 | * Use the l2switch_enable flag - would be false if the DMA | |
6212 | * Tx switch had been disabled. | |
6213 | */ | |
6214 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6215 | tx_flags |= IXGBE_TX_FLAGS_TXSW; | |
6216 | ||
6217 | #endif | |
32701dc2 | 6218 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 6219 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
6220 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
6221 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 6222 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
6223 | tx_flags |= (skb->priority & 0x7) << |
6224 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
6225 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
6226 | struct vlan_ethhdr *vhdr; | |
6227 | if (skb_header_cloned(skb) && | |
6228 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) | |
6229 | goto out_drop; | |
6230 | vhdr = (struct vlan_ethhdr *)skb->data; | |
6231 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
6232 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6233 | } else { | |
6234 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 6235 | } |
9a799d71 | 6236 | } |
eacd73f7 | 6237 | |
244e27ad AD |
6238 | /* record initial flags and protocol */ |
6239 | first->tx_flags = tx_flags; | |
6240 | first->protocol = protocol; | |
6241 | ||
eacd73f7 | 6242 | #ifdef IXGBE_FCOE |
66f32a8b AD |
6243 | /* setup tx offload for FCoE */ |
6244 | if ((protocol == __constant_htons(ETH_P_FCOE)) && | |
6245 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
244e27ad | 6246 | tso = ixgbe_fso(tx_ring, first, &hdr_len); |
897ab156 AD |
6247 | if (tso < 0) |
6248 | goto out_drop; | |
9a799d71 | 6249 | |
66f32a8b | 6250 | goto xmit_fcoe; |
eacd73f7 | 6251 | } |
9a799d71 | 6252 | |
66f32a8b | 6253 | #endif /* IXGBE_FCOE */ |
244e27ad | 6254 | tso = ixgbe_tso(tx_ring, first, &hdr_len); |
66f32a8b | 6255 | if (tso < 0) |
897ab156 | 6256 | goto out_drop; |
244e27ad AD |
6257 | else if (!tso) |
6258 | ixgbe_tx_csum(tx_ring, first); | |
66f32a8b AD |
6259 | |
6260 | /* add the ATR filter if ATR is on */ | |
6261 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
244e27ad | 6262 | ixgbe_atr(tx_ring, first); |
66f32a8b AD |
6263 | |
6264 | #ifdef IXGBE_FCOE | |
6265 | xmit_fcoe: | |
6266 | #endif /* IXGBE_FCOE */ | |
244e27ad | 6267 | ixgbe_tx_map(tx_ring, first, hdr_len); |
d3d00239 AD |
6268 | |
6269 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
9a799d71 AK |
6270 | |
6271 | return NETDEV_TX_OK; | |
897ab156 AD |
6272 | |
6273 | out_drop: | |
fd0db0ed AD |
6274 | dev_kfree_skb_any(first->skb); |
6275 | first->skb = NULL; | |
6276 | ||
897ab156 | 6277 | return NETDEV_TX_OK; |
9a799d71 AK |
6278 | } |
6279 | ||
a50c29dd AD |
6280 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
6281 | struct net_device *netdev) | |
84418e3b AD |
6282 | { |
6283 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6284 | struct ixgbe_ring *tx_ring; | |
6285 | ||
a50c29dd AD |
6286 | if (skb->len <= 0) { |
6287 | dev_kfree_skb_any(skb); | |
6288 | return NETDEV_TX_OK; | |
6289 | } | |
6290 | ||
6291 | /* | |
6292 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
6293 | * in order to meet this minimum size requirement. | |
6294 | */ | |
6295 | if (skb->len < 17) { | |
6296 | if (skb_padto(skb, 17)) | |
6297 | return NETDEV_TX_OK; | |
6298 | skb->len = 17; | |
6299 | } | |
6300 | ||
84418e3b | 6301 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
fc77dc3c | 6302 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
6303 | } |
6304 | ||
9a799d71 AK |
6305 | /** |
6306 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6307 | * @netdev: network interface device structure | |
6308 | * @p: pointer to an address structure | |
6309 | * | |
6310 | * Returns 0 on success, negative on failure | |
6311 | **/ | |
6312 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6313 | { | |
6314 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6315 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6316 | struct sockaddr *addr = p; |
6317 | ||
6318 | if (!is_valid_ether_addr(addr->sa_data)) | |
6319 | return -EADDRNOTAVAIL; | |
6320 | ||
6321 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6322 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6323 | |
1cdd1ec8 GR |
6324 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
6325 | IXGBE_RAH_AV); | |
9a799d71 AK |
6326 | |
6327 | return 0; | |
6328 | } | |
6329 | ||
6b73e10d BH |
6330 | static int |
6331 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6332 | { | |
6333 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6334 | struct ixgbe_hw *hw = &adapter->hw; | |
6335 | u16 value; | |
6336 | int rc; | |
6337 | ||
6338 | if (prtad != hw->phy.mdio.prtad) | |
6339 | return -EINVAL; | |
6340 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6341 | if (!rc) | |
6342 | rc = value; | |
6343 | return rc; | |
6344 | } | |
6345 | ||
6346 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6347 | u16 addr, u16 value) | |
6348 | { | |
6349 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6350 | struct ixgbe_hw *hw = &adapter->hw; | |
6351 | ||
6352 | if (prtad != hw->phy.mdio.prtad) | |
6353 | return -EINVAL; | |
6354 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6355 | } | |
6356 | ||
6357 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6358 | { | |
6359 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6360 | ||
6361 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6362 | } | |
6363 | ||
0365e6e4 PW |
6364 | /** |
6365 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6366 | * netdev->dev_addrs |
0365e6e4 PW |
6367 | * @netdev: network interface device structure |
6368 | * | |
6369 | * Returns non-zero on failure | |
6370 | **/ | |
6371 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6372 | { | |
6373 | int err = 0; | |
6374 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6375 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6376 | ||
6377 | if (is_valid_ether_addr(mac->san_addr)) { | |
6378 | rtnl_lock(); | |
6379 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6380 | rtnl_unlock(); | |
6381 | } | |
6382 | return err; | |
6383 | } | |
6384 | ||
6385 | /** | |
6386 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6387 | * netdev->dev_addrs |
0365e6e4 PW |
6388 | * @netdev: network interface device structure |
6389 | * | |
6390 | * Returns non-zero on failure | |
6391 | **/ | |
6392 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6393 | { | |
6394 | int err = 0; | |
6395 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6396 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6397 | ||
6398 | if (is_valid_ether_addr(mac->san_addr)) { | |
6399 | rtnl_lock(); | |
6400 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6401 | rtnl_unlock(); | |
6402 | } | |
6403 | return err; | |
6404 | } | |
6405 | ||
9a799d71 AK |
6406 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6407 | /* | |
6408 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6409 | * without having to re-enable interrupts. It's not called while | |
6410 | * the interrupt routine is executing. | |
6411 | */ | |
6412 | static void ixgbe_netpoll(struct net_device *netdev) | |
6413 | { | |
6414 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6415 | int i; |
9a799d71 | 6416 | |
1a647bd2 AD |
6417 | /* if interface is down do nothing */ |
6418 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6419 | return; | |
6420 | ||
9a799d71 | 6421 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
6422 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
6423 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
6424 | for (i = 0; i < num_q_vectors; i++) { | |
6425 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
4ff7fb12 | 6426 | ixgbe_msix_clean_rings(0, q_vector); |
8f9a7167 PWJ |
6427 | } |
6428 | } else { | |
6429 | ixgbe_intr(adapter->pdev->irq, netdev); | |
6430 | } | |
9a799d71 | 6431 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 | 6432 | } |
9a799d71 | 6433 | |
581330ba | 6434 | #endif |
de1036b1 ED |
6435 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
6436 | struct rtnl_link_stats64 *stats) | |
6437 | { | |
6438 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6439 | int i; | |
6440 | ||
1a51502b | 6441 | rcu_read_lock(); |
de1036b1 | 6442 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 6443 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
6444 | u64 bytes, packets; |
6445 | unsigned int start; | |
6446 | ||
1a51502b ED |
6447 | if (ring) { |
6448 | do { | |
6449 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6450 | packets = ring->stats.packets; | |
6451 | bytes = ring->stats.bytes; | |
6452 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6453 | stats->rx_packets += packets; | |
6454 | stats->rx_bytes += bytes; | |
6455 | } | |
de1036b1 | 6456 | } |
1ac9ad13 ED |
6457 | |
6458 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
6459 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
6460 | u64 bytes, packets; | |
6461 | unsigned int start; | |
6462 | ||
6463 | if (ring) { | |
6464 | do { | |
6465 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6466 | packets = ring->stats.packets; | |
6467 | bytes = ring->stats.bytes; | |
6468 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6469 | stats->tx_packets += packets; | |
6470 | stats->tx_bytes += bytes; | |
6471 | } | |
6472 | } | |
1a51502b | 6473 | rcu_read_unlock(); |
de1036b1 ED |
6474 | /* following stats updated by ixgbe_watchdog_task() */ |
6475 | stats->multicast = netdev->stats.multicast; | |
6476 | stats->rx_errors = netdev->stats.rx_errors; | |
6477 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
6478 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
6479 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
6480 | return stats; | |
6481 | } | |
6482 | ||
8af3c33f | 6483 | #ifdef CONFIG_IXGBE_DCB |
8b1c0b24 JF |
6484 | /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. |
6485 | * #adapter: pointer to ixgbe_adapter | |
6486 | * @tc: number of traffic classes currently enabled | |
6487 | * | |
6488 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
6489 | * 802.1Q priority maps to a packet buffer that exists. | |
6490 | */ | |
6491 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
6492 | { | |
6493 | struct ixgbe_hw *hw = &adapter->hw; | |
6494 | u32 reg, rsave; | |
6495 | int i; | |
6496 | ||
6497 | /* 82598 have a static priority to TC mapping that can not | |
6498 | * be changed so no validation is needed. | |
6499 | */ | |
6500 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6501 | return; | |
6502 | ||
6503 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
6504 | rsave = reg; | |
6505 | ||
6506 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
6507 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
6508 | ||
6509 | /* If up2tc is out of bounds default to zero */ | |
6510 | if (up2tc > tc) | |
6511 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
6512 | } | |
6513 | ||
6514 | if (reg != rsave) | |
6515 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
6516 | ||
6517 | return; | |
6518 | } | |
6519 | ||
8b1c0b24 JF |
6520 | /* ixgbe_setup_tc - routine to configure net_device for multiple traffic |
6521 | * classes. | |
6522 | * | |
6523 | * @netdev: net device to configure | |
6524 | * @tc: number of traffic classes to enable | |
6525 | */ | |
6526 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
6527 | { | |
8b1c0b24 JF |
6528 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
6529 | struct ixgbe_hw *hw = &adapter->hw; | |
8b1c0b24 | 6530 | |
e7589eab JF |
6531 | /* Multiple traffic classes requires multiple queues */ |
6532 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { | |
6533 | e_err(drv, "Enable failed, needs MSI-X\n"); | |
6534 | return -EINVAL; | |
6535 | } | |
8b1c0b24 JF |
6536 | |
6537 | /* Hardware supports up to 8 traffic classes */ | |
4de2a022 | 6538 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || |
581330ba AD |
6539 | (hw->mac.type == ixgbe_mac_82598EB && |
6540 | tc < MAX_TRAFFIC_CLASS)) | |
8b1c0b24 JF |
6541 | return -EINVAL; |
6542 | ||
6543 | /* Hardware has to reinitialize queues and interrupts to | |
52f33af8 | 6544 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
6545 | * hardware is not flexible enough to do this dynamically. |
6546 | */ | |
6547 | if (netif_running(dev)) | |
6548 | ixgbe_close(dev); | |
6549 | ixgbe_clear_interrupt_scheme(adapter); | |
6550 | ||
e7589eab | 6551 | if (tc) { |
8b1c0b24 | 6552 | netdev_set_num_tc(dev, tc); |
e7589eab JF |
6553 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
6554 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6555 | ||
943561d3 AD |
6556 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
6557 | adapter->last_lfc_mode = adapter->hw.fc.requested_mode; | |
e7589eab | 6558 | adapter->hw.fc.requested_mode = ixgbe_fc_none; |
943561d3 | 6559 | } |
e7589eab | 6560 | } else { |
8b1c0b24 | 6561 | netdev_reset_tc(dev); |
943561d3 AD |
6562 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
6563 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; | |
e7589eab JF |
6564 | |
6565 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
6566 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6567 | ||
6568 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
6569 | adapter->dcb_cfg.pfc_mode_enable = false; | |
6570 | } | |
6571 | ||
8b1c0b24 JF |
6572 | ixgbe_init_interrupt_scheme(adapter); |
6573 | ixgbe_validate_rtr(adapter, tc); | |
6574 | if (netif_running(dev)) | |
6575 | ixgbe_open(dev); | |
6576 | ||
6577 | return 0; | |
6578 | } | |
de1036b1 | 6579 | |
8af3c33f | 6580 | #endif /* CONFIG_IXGBE_DCB */ |
082757af DS |
6581 | void ixgbe_do_reset(struct net_device *netdev) |
6582 | { | |
6583 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6584 | ||
6585 | if (netif_running(netdev)) | |
6586 | ixgbe_reinit_locked(adapter); | |
6587 | else | |
6588 | ixgbe_reset(adapter); | |
6589 | } | |
6590 | ||
c8f44aff | 6591 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
567d2de2 | 6592 | netdev_features_t features) |
082757af DS |
6593 | { |
6594 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6595 | ||
6596 | #ifdef CONFIG_DCB | |
6597 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
567d2de2 | 6598 | features &= ~NETIF_F_HW_VLAN_RX; |
082757af DS |
6599 | #endif |
6600 | ||
6601 | /* return error if RXHASH is being enabled when RSS is not supported */ | |
6602 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) | |
567d2de2 | 6603 | features &= ~NETIF_F_RXHASH; |
082757af DS |
6604 | |
6605 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ | |
567d2de2 AD |
6606 | if (!(features & NETIF_F_RXCSUM)) |
6607 | features &= ~NETIF_F_LRO; | |
082757af | 6608 | |
567d2de2 AD |
6609 | /* Turn off LRO if not RSC capable */ |
6610 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) | |
6611 | features &= ~NETIF_F_LRO; | |
8e2813f5 | 6612 | |
082757af | 6613 | |
567d2de2 | 6614 | return features; |
082757af DS |
6615 | } |
6616 | ||
c8f44aff | 6617 | static int ixgbe_set_features(struct net_device *netdev, |
567d2de2 | 6618 | netdev_features_t features) |
082757af DS |
6619 | { |
6620 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
567d2de2 | 6621 | netdev_features_t changed = netdev->features ^ features; |
082757af DS |
6622 | bool need_reset = false; |
6623 | ||
082757af | 6624 | /* Make sure RSC matches LRO, reset if change */ |
567d2de2 AD |
6625 | if (!(features & NETIF_F_LRO)) { |
6626 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
082757af | 6627 | need_reset = true; |
567d2de2 AD |
6628 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; |
6629 | } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && | |
6630 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
6631 | if (adapter->rx_itr_setting == 1 || | |
6632 | adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { | |
6633 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
6634 | need_reset = true; | |
6635 | } else if ((changed ^ features) & NETIF_F_LRO) { | |
6636 | e_info(probe, "rx-usecs set too low, " | |
6637 | "disabling RSC\n"); | |
082757af DS |
6638 | } |
6639 | } | |
6640 | ||
6641 | /* | |
6642 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
6643 | * the state changed, we need to reset. | |
6644 | */ | |
567d2de2 AD |
6645 | if (!(features & NETIF_F_NTUPLE)) { |
6646 | if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
6647 | /* turn off Flow Director, set ATR and reset */ | |
6648 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && | |
6649 | !(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
6650 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
082757af DS |
6651 | need_reset = true; |
6652 | } | |
082757af | 6653 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; |
567d2de2 AD |
6654 | } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { |
6655 | /* turn off ATR, enable perfect filters and reset */ | |
6656 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6657 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
082757af DS |
6658 | need_reset = true; |
6659 | } | |
6660 | ||
3f2d1c0f BG |
6661 | if (changed & NETIF_F_RXALL) |
6662 | need_reset = true; | |
6663 | ||
567d2de2 | 6664 | netdev->features = features; |
082757af DS |
6665 | if (need_reset) |
6666 | ixgbe_do_reset(netdev); | |
6667 | ||
6668 | return 0; | |
082757af DS |
6669 | } |
6670 | ||
0f4b0add JF |
6671 | static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, |
6672 | struct net_device *dev, | |
6673 | unsigned char *addr, | |
6674 | u16 flags) | |
6675 | { | |
6676 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6677 | int err = -EOPNOTSUPP; | |
6678 | ||
6679 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6680 | pr_info("%s: FDB only supports static addresses\n", | |
6681 | ixgbe_driver_name); | |
6682 | return -EINVAL; | |
6683 | } | |
6684 | ||
6685 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
6686 | if (is_unicast_ether_addr(addr)) | |
6687 | err = dev_uc_add_excl(dev, addr); | |
6688 | else if (is_multicast_ether_addr(addr)) | |
6689 | err = dev_mc_add_excl(dev, addr); | |
6690 | else | |
6691 | err = -EINVAL; | |
6692 | } | |
6693 | ||
6694 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
6695 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
6696 | err = 0; | |
6697 | ||
6698 | return err; | |
6699 | } | |
6700 | ||
6701 | static int ixgbe_ndo_fdb_del(struct ndmsg *ndm, | |
6702 | struct net_device *dev, | |
6703 | unsigned char *addr) | |
6704 | { | |
6705 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6706 | int err = -EOPNOTSUPP; | |
6707 | ||
6708 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6709 | pr_info("%s: FDB only supports static addresses\n", | |
6710 | ixgbe_driver_name); | |
6711 | return -EINVAL; | |
6712 | } | |
6713 | ||
6714 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
6715 | if (is_unicast_ether_addr(addr)) | |
6716 | err = dev_uc_del(dev, addr); | |
6717 | else if (is_multicast_ether_addr(addr)) | |
6718 | err = dev_mc_del(dev, addr); | |
6719 | else | |
6720 | err = -EINVAL; | |
6721 | } | |
6722 | ||
6723 | return err; | |
6724 | } | |
6725 | ||
6726 | static int ixgbe_ndo_fdb_dump(struct sk_buff *skb, | |
6727 | struct netlink_callback *cb, | |
6728 | struct net_device *dev, | |
6729 | int idx) | |
6730 | { | |
6731 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6732 | ||
6733 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6734 | idx = ndo_dflt_fdb_dump(skb, cb, dev, idx); | |
6735 | ||
6736 | return idx; | |
6737 | } | |
6738 | ||
0edc3527 | 6739 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 6740 | .ndo_open = ixgbe_open, |
0edc3527 | 6741 | .ndo_stop = ixgbe_close, |
00829823 | 6742 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 6743 | .ndo_select_queue = ixgbe_select_queue, |
581330ba | 6744 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
6745 | .ndo_validate_addr = eth_validate_addr, |
6746 | .ndo_set_mac_address = ixgbe_set_mac, | |
6747 | .ndo_change_mtu = ixgbe_change_mtu, | |
6748 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
6749 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
6750 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 6751 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
6752 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
6753 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
6754 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
581330ba | 6755 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
7f01648a | 6756 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 6757 | .ndo_get_stats64 = ixgbe_get_stats64, |
8af3c33f | 6758 | #ifdef CONFIG_IXGBE_DCB |
24095aa3 | 6759 | .ndo_setup_tc = ixgbe_setup_tc, |
8af3c33f | 6760 | #endif |
0edc3527 SH |
6761 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6762 | .ndo_poll_controller = ixgbe_netpoll, | |
6763 | #endif | |
332d4a7d YZ |
6764 | #ifdef IXGBE_FCOE |
6765 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 6766 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 6767 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
6768 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
6769 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 6770 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 6771 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 6772 | #endif /* IXGBE_FCOE */ |
082757af DS |
6773 | .ndo_set_features = ixgbe_set_features, |
6774 | .ndo_fix_features = ixgbe_fix_features, | |
0f4b0add JF |
6775 | .ndo_fdb_add = ixgbe_ndo_fdb_add, |
6776 | .ndo_fdb_del = ixgbe_ndo_fdb_del, | |
6777 | .ndo_fdb_dump = ixgbe_ndo_fdb_dump, | |
0edc3527 SH |
6778 | }; |
6779 | ||
1cdd1ec8 | 6780 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
567d2de2 | 6781 | const struct ixgbe_info *ii) |
1cdd1ec8 GR |
6782 | { |
6783 | #ifdef CONFIG_PCI_IOV | |
6784 | struct ixgbe_hw *hw = &adapter->hw; | |
1cdd1ec8 | 6785 | |
c6bda30a | 6786 | if (hw->mac.type == ixgbe_mac_82598EB) |
1cdd1ec8 GR |
6787 | return; |
6788 | ||
6789 | /* The 82599 supports up to 64 VFs per physical function | |
6790 | * but this implementation limits allocation to 63 so that | |
6791 | * basic networking resources are still available to the | |
6b42a9c5 GR |
6792 | * physical function. If the user requests greater thn |
6793 | * 63 VFs then it is an error - reset to default of zero. | |
1cdd1ec8 | 6794 | */ |
6b42a9c5 | 6795 | adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs; |
c6bda30a | 6796 | ixgbe_enable_sriov(adapter, ii); |
1cdd1ec8 GR |
6797 | #endif /* CONFIG_PCI_IOV */ |
6798 | } | |
6799 | ||
8e2813f5 JK |
6800 | /** |
6801 | * ixgbe_wol_supported - Check whether device supports WoL | |
6802 | * @hw: hw specific details | |
6803 | * @device_id: the device ID | |
6804 | * @subdev_id: the subsystem device ID | |
6805 | * | |
6806 | * This function is used by probe and ethtool to determine | |
6807 | * which devices have WoL support | |
6808 | * | |
6809 | **/ | |
6810 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
6811 | u16 subdevice_id) | |
6812 | { | |
6813 | struct ixgbe_hw *hw = &adapter->hw; | |
6814 | u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
6815 | int is_wol_supported = 0; | |
6816 | ||
6817 | switch (device_id) { | |
6818 | case IXGBE_DEV_ID_82599_SFP: | |
6819 | /* Only these subdevices could supports WOL */ | |
6820 | switch (subdevice_id) { | |
6821 | case IXGBE_SUBDEV_ID_82599_560FLR: | |
6822 | /* only support first port */ | |
6823 | if (hw->bus.func != 0) | |
6824 | break; | |
6825 | case IXGBE_SUBDEV_ID_82599_SFP: | |
6826 | is_wol_supported = 1; | |
6827 | break; | |
6828 | } | |
6829 | break; | |
6830 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: | |
6831 | /* All except this subdevice support WOL */ | |
6832 | if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) | |
6833 | is_wol_supported = 1; | |
6834 | break; | |
6835 | case IXGBE_DEV_ID_82599_KX4: | |
6836 | is_wol_supported = 1; | |
6837 | break; | |
6838 | case IXGBE_DEV_ID_X540T: | |
6839 | /* check eeprom to see if enabled wol */ | |
6840 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
6841 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
6842 | (hw->bus.func == 0))) { | |
6843 | is_wol_supported = 1; | |
6844 | } | |
6845 | break; | |
6846 | } | |
6847 | ||
6848 | return is_wol_supported; | |
6849 | } | |
6850 | ||
9a799d71 AK |
6851 | /** |
6852 | * ixgbe_probe - Device Initialization Routine | |
6853 | * @pdev: PCI device information struct | |
6854 | * @ent: entry in ixgbe_pci_tbl | |
6855 | * | |
6856 | * Returns 0 on success, negative on failure | |
6857 | * | |
6858 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
6859 | * The OS initialization, configuring of the adapter private structure, | |
6860 | * and a hardware reset occur. | |
6861 | **/ | |
6862 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 6863 | const struct pci_device_id *ent) |
9a799d71 AK |
6864 | { |
6865 | struct net_device *netdev; | |
6866 | struct ixgbe_adapter *adapter = NULL; | |
6867 | struct ixgbe_hw *hw; | |
6868 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
6869 | static int cards_found; |
6870 | int i, err, pci_using_dac; | |
289700db | 6871 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 6872 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
6873 | #ifdef IXGBE_FCOE |
6874 | u16 device_caps; | |
6875 | #endif | |
289700db | 6876 | u32 eec; |
9a799d71 | 6877 | |
bded64a7 AG |
6878 | /* Catch broken hardware that put the wrong VF device ID in |
6879 | * the PCIe SR-IOV capability. | |
6880 | */ | |
6881 | if (pdev->is_virtfn) { | |
6882 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
6883 | pci_name(pdev), pdev->vendor, pdev->device); | |
6884 | return -EINVAL; | |
6885 | } | |
6886 | ||
9ce77666 | 6887 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
6888 | if (err) |
6889 | return err; | |
6890 | ||
1b507730 NN |
6891 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
6892 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
6893 | pci_using_dac = 1; |
6894 | } else { | |
1b507730 | 6895 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 6896 | if (err) { |
1b507730 NN |
6897 | err = dma_set_coherent_mask(&pdev->dev, |
6898 | DMA_BIT_MASK(32)); | |
9a799d71 | 6899 | if (err) { |
b8bc0421 DC |
6900 | dev_err(&pdev->dev, |
6901 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
6902 | goto err_dma; |
6903 | } | |
6904 | } | |
6905 | pci_using_dac = 0; | |
6906 | } | |
6907 | ||
9ce77666 | 6908 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 6909 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 6910 | if (err) { |
b8bc0421 DC |
6911 | dev_err(&pdev->dev, |
6912 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
6913 | goto err_pci_reg; |
6914 | } | |
6915 | ||
19d5afd4 | 6916 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 6917 | |
9a799d71 | 6918 | pci_set_master(pdev); |
fb3b27bc | 6919 | pci_save_state(pdev); |
9a799d71 | 6920 | |
e901acd6 JF |
6921 | #ifdef CONFIG_IXGBE_DCB |
6922 | indices *= MAX_TRAFFIC_CLASS; | |
6923 | #endif | |
6924 | ||
c85a2618 JF |
6925 | if (ii->mac == ixgbe_mac_82598EB) |
6926 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
6927 | else | |
6928 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
6929 | ||
e901acd6 | 6930 | #ifdef IXGBE_FCOE |
c85a2618 JF |
6931 | indices += min_t(unsigned int, num_possible_cpus(), |
6932 | IXGBE_MAX_FCOE_INDICES); | |
6933 | #endif | |
c85a2618 | 6934 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
6935 | if (!netdev) { |
6936 | err = -ENOMEM; | |
6937 | goto err_alloc_etherdev; | |
6938 | } | |
6939 | ||
9a799d71 AK |
6940 | SET_NETDEV_DEV(netdev, &pdev->dev); |
6941 | ||
9a799d71 | 6942 | adapter = netdev_priv(netdev); |
c60fbb00 | 6943 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
6944 | |
6945 | adapter->netdev = netdev; | |
6946 | adapter->pdev = pdev; | |
6947 | hw = &adapter->hw; | |
6948 | hw->back = adapter; | |
b3f4d599 | 6949 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9a799d71 | 6950 | |
05857980 | 6951 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 6952 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
6953 | if (!hw->hw_addr) { |
6954 | err = -EIO; | |
6955 | goto err_ioremap; | |
6956 | } | |
6957 | ||
6958 | for (i = 1; i <= 5; i++) { | |
6959 | if (pci_resource_len(pdev, i) == 0) | |
6960 | continue; | |
6961 | } | |
6962 | ||
0edc3527 | 6963 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 6964 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 6965 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 6966 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 6967 | |
9a799d71 AK |
6968 | adapter->bd_number = cards_found; |
6969 | ||
9a799d71 AK |
6970 | /* Setup hw api */ |
6971 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 6972 | hw->mac.type = ii->mac; |
9a799d71 | 6973 | |
c44ade9e JB |
6974 | /* EEPROM */ |
6975 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
6976 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
6977 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
6978 | if (!(eec & (1 << 8))) | |
6979 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
6980 | ||
6981 | /* PHY */ | |
6982 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 6983 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
6984 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
6985 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
6986 | hw->phy.mdio.mmds = 0; | |
6987 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
6988 | hw->phy.mdio.dev = netdev; | |
6989 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
6990 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 6991 | |
8ca783ab | 6992 | ii->get_invariants(hw); |
9a799d71 AK |
6993 | |
6994 | /* setup the private structure */ | |
6995 | err = ixgbe_sw_init(adapter); | |
6996 | if (err) | |
6997 | goto err_sw_init; | |
6998 | ||
e86bff0e | 6999 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7000 | switch (adapter->hw.mac.type) { |
7001 | case ixgbe_mac_82599EB: | |
7002 | case ixgbe_mac_X540: | |
e86bff0e | 7003 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7004 | break; |
7005 | default: | |
7006 | break; | |
7007 | } | |
e86bff0e | 7008 | |
bf069c97 DS |
7009 | /* |
7010 | * If there is a fan on this device and it has failed log the | |
7011 | * failure. | |
7012 | */ | |
7013 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7014 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7015 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7016 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7017 | } |
7018 | ||
8ef78adc PWJ |
7019 | if (allow_unsupported_sfp) |
7020 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
7021 | ||
c44ade9e | 7022 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7023 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7024 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7025 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7026 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7027 | hw->mac.type == ixgbe_mac_82598EB) { | |
8ca783ab DS |
7028 | err = 0; |
7029 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
7086400d | 7030 | e_dev_err("failed to load because an unsupported SFP+ " |
849c4542 ET |
7031 | "module type was detected.\n"); |
7032 | e_dev_err("Reload the driver after installing a supported " | |
7033 | "module.\n"); | |
04f165ef PW |
7034 | goto err_sw_init; |
7035 | } else if (err) { | |
849c4542 | 7036 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7037 | goto err_sw_init; |
7038 | } | |
7039 | ||
1cdd1ec8 GR |
7040 | ixgbe_probe_vf(adapter, ii); |
7041 | ||
396e799c | 7042 | netdev->features = NETIF_F_SG | |
e8e9f696 | 7043 | NETIF_F_IP_CSUM | |
082757af | 7044 | NETIF_F_IPV6_CSUM | |
e8e9f696 JP |
7045 | NETIF_F_HW_VLAN_TX | |
7046 | NETIF_F_HW_VLAN_RX | | |
082757af DS |
7047 | NETIF_F_HW_VLAN_FILTER | |
7048 | NETIF_F_TSO | | |
7049 | NETIF_F_TSO6 | | |
082757af DS |
7050 | NETIF_F_RXHASH | |
7051 | NETIF_F_RXCSUM; | |
9a799d71 | 7052 | |
082757af | 7053 | netdev->hw_features = netdev->features; |
ad31c402 | 7054 | |
58be7666 DS |
7055 | switch (adapter->hw.mac.type) { |
7056 | case ixgbe_mac_82599EB: | |
7057 | case ixgbe_mac_X540: | |
45a5ead0 | 7058 | netdev->features |= NETIF_F_SCTP_CSUM; |
082757af DS |
7059 | netdev->hw_features |= NETIF_F_SCTP_CSUM | |
7060 | NETIF_F_NTUPLE; | |
58be7666 DS |
7061 | break; |
7062 | default: | |
7063 | break; | |
7064 | } | |
45a5ead0 | 7065 | |
3f2d1c0f BG |
7066 | netdev->hw_features |= NETIF_F_RXALL; |
7067 | ||
ad31c402 JK |
7068 | netdev->vlan_features |= NETIF_F_TSO; |
7069 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7070 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7071 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7072 | netdev->vlan_features |= NETIF_F_SG; |
7073 | ||
01789349 | 7074 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 7075 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 7076 | |
1cdd1ec8 GR |
7077 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7078 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
7079 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 | 7080 | |
7a6b6f51 | 7081 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7082 | netdev->dcbnl_ops = &dcbnl_ops; |
7083 | #endif | |
7084 | ||
eacd73f7 | 7085 | #ifdef IXGBE_FCOE |
0d551589 | 7086 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7087 | if (hw->mac.ops.get_device_caps) { |
7088 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7089 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7090 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
7091 | } |
7092 | } | |
5e09d7f6 YZ |
7093 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
7094 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
7095 | netdev->vlan_features |= NETIF_F_FSO; | |
7096 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
7097 | } | |
eacd73f7 | 7098 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7099 | if (pci_using_dac) { |
9a799d71 | 7100 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7101 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7102 | } | |
9a799d71 | 7103 | |
082757af DS |
7104 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
7105 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 7106 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7107 | netdev->features |= NETIF_F_LRO; |
7108 | ||
9a799d71 | 7109 | /* make sure the EEPROM is good */ |
c44ade9e | 7110 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7111 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 | 7112 | err = -EIO; |
35937c05 | 7113 | goto err_sw_init; |
9a799d71 AK |
7114 | } |
7115 | ||
7116 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7117 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7118 | ||
c44ade9e | 7119 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7120 | e_dev_err("invalid MAC address\n"); |
9a799d71 | 7121 | err = -EIO; |
35937c05 | 7122 | goto err_sw_init; |
9a799d71 AK |
7123 | } |
7124 | ||
7086400d | 7125 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
581330ba | 7126 | (unsigned long) adapter); |
9a799d71 | 7127 | |
7086400d AD |
7128 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
7129 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
9a799d71 | 7130 | |
021230d4 AV |
7131 | err = ixgbe_init_interrupt_scheme(adapter); |
7132 | if (err) | |
7133 | goto err_sw_init; | |
9a799d71 | 7134 | |
082757af DS |
7135 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { |
7136 | netdev->hw_features &= ~NETIF_F_RXHASH; | |
67a74ee2 | 7137 | netdev->features &= ~NETIF_F_RXHASH; |
082757af | 7138 | } |
67a74ee2 | 7139 | |
8e2813f5 | 7140 | /* WOL not supported for all devices */ |
c23f5b6b | 7141 | adapter->wol = 0; |
8e2813f5 JK |
7142 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); |
7143 | if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device)) | |
9417c464 | 7144 | adapter->wol = IXGBE_WUFC_MAG; |
c23f5b6b | 7145 | |
e8e26350 PW |
7146 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7147 | ||
15e5209f ET |
7148 | /* save off EEPROM version number */ |
7149 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
7150 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
7151 | ||
04f165ef PW |
7152 | /* pick up the PCI bus settings for reporting later */ |
7153 | hw->mac.ops.get_bus_info(hw); | |
7154 | ||
9a799d71 | 7155 | /* print bus type/speed/width info */ |
849c4542 | 7156 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
6716344c DS |
7157 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : |
7158 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : | |
e8e9f696 JP |
7159 | "Unknown"), |
7160 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7161 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7162 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7163 | "Unknown"), | |
7164 | netdev->dev_addr); | |
289700db DS |
7165 | |
7166 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7167 | if (err) | |
9fe93afd | 7168 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7169 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7170 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7171 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7172 | part_str); |
e8e26350 | 7173 | else |
289700db DS |
7174 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7175 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7176 | |
e8e26350 | 7177 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7178 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7179 | "not sufficient for optimal performance.\n"); | |
7180 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7181 | "is required.\n"); | |
0c254d86 AK |
7182 | } |
7183 | ||
9a799d71 | 7184 | /* reset the hardware with the new settings */ |
794caeb2 | 7185 | err = hw->mac.ops.start_hw(hw); |
794caeb2 PWJ |
7186 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7187 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7188 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7189 | "Please be aware there may be issues associated " | |
7190 | "with your hardware. If you are experiencing " | |
7191 | "problems please contact your Intel or hardware " | |
7192 | "representative who provided you with this " | |
7193 | "hardware.\n"); | |
794caeb2 | 7194 | } |
9a799d71 AK |
7195 | strcpy(netdev->name, "eth%d"); |
7196 | err = register_netdev(netdev); | |
7197 | if (err) | |
7198 | goto err_register; | |
7199 | ||
93d3ce8f ET |
7200 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
7201 | if (hw->mac.ops.disable_tx_laser && | |
7202 | ((hw->phy.multispeed_fiber) || | |
7203 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && | |
7204 | (hw->mac.type == ixgbe_mac_82599EB)))) | |
7205 | hw->mac.ops.disable_tx_laser(hw); | |
7206 | ||
54386467 JB |
7207 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7208 | netif_carrier_off(netdev); | |
7209 | ||
5dd2d332 | 7210 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7211 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7212 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7213 | ixgbe_setup_dca(adapter); |
7214 | } | |
7215 | #endif | |
1cdd1ec8 | 7216 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7217 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7218 | for (i = 0; i < adapter->num_vfs; i++) |
7219 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7220 | } | |
7221 | ||
2466dd9c JK |
7222 | /* firmware requires driver version to be 0xFFFFFFFF |
7223 | * since os does not support feature | |
7224 | */ | |
9612de92 | 7225 | if (hw->mac.ops.set_fw_drv_ver) |
2466dd9c JK |
7226 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, |
7227 | 0xFF); | |
9612de92 | 7228 | |
0365e6e4 PW |
7229 | /* add san mac addr to netdev */ |
7230 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7231 | |
ea81875a | 7232 | e_dev_info("%s\n", ixgbe_default_device_descr); |
9a799d71 | 7233 | cards_found++; |
3ca8bc6d DS |
7234 | |
7235 | if (ixgbe_sysfs_init(adapter)) | |
7236 | e_err(probe, "failed to allocate sysfs resources\n"); | |
7237 | ||
9a799d71 AK |
7238 | return 0; |
7239 | ||
7240 | err_register: | |
5eba3699 | 7241 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7242 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 | 7243 | err_sw_init: |
1cdd1ec8 GR |
7244 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7245 | ixgbe_disable_sriov(adapter); | |
7086400d | 7246 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
9a799d71 AK |
7247 | iounmap(hw->hw_addr); |
7248 | err_ioremap: | |
7249 | free_netdev(netdev); | |
7250 | err_alloc_etherdev: | |
e8e9f696 JP |
7251 | pci_release_selected_regions(pdev, |
7252 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7253 | err_pci_reg: |
7254 | err_dma: | |
7255 | pci_disable_device(pdev); | |
7256 | return err; | |
7257 | } | |
7258 | ||
7259 | /** | |
7260 | * ixgbe_remove - Device Removal Routine | |
7261 | * @pdev: PCI device information struct | |
7262 | * | |
7263 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7264 | * that it should release a PCI device. The could be caused by a | |
7265 | * Hot-Plug event, or because the driver is going to be removed from | |
7266 | * memory. | |
7267 | **/ | |
7268 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7269 | { | |
c60fbb00 AD |
7270 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7271 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7272 | |
7273 | set_bit(__IXGBE_DOWN, &adapter->state); | |
7086400d | 7274 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 7275 | |
5dd2d332 | 7276 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7277 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7278 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7279 | dca_remove_requester(&pdev->dev); | |
7280 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7281 | } | |
7282 | ||
7283 | #endif | |
3ca8bc6d DS |
7284 | ixgbe_sysfs_exit(adapter); |
7285 | ||
332d4a7d YZ |
7286 | #ifdef IXGBE_FCOE |
7287 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
7288 | ixgbe_cleanup_fcoe(adapter); | |
7289 | ||
7290 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
7291 | |
7292 | /* remove the added san mac */ | |
7293 | ixgbe_del_sanmac_netdev(netdev); | |
7294 | ||
c4900be0 DS |
7295 | if (netdev->reg_state == NETREG_REGISTERED) |
7296 | unregister_netdev(netdev); | |
9a799d71 | 7297 | |
c6bda30a GR |
7298 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
7299 | if (!(ixgbe_check_vf_assignment(adapter))) | |
7300 | ixgbe_disable_sriov(adapter); | |
7301 | else | |
7302 | e_dev_warn("Unloading driver while VFs are assigned " | |
7303 | "- VFs will not be deallocated\n"); | |
7304 | } | |
1cdd1ec8 | 7305 | |
7a921c93 | 7306 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7307 | |
021230d4 | 7308 | ixgbe_release_hw_control(adapter); |
9a799d71 | 7309 | |
2b1588c3 AD |
7310 | #ifdef CONFIG_DCB |
7311 | kfree(adapter->ixgbe_ieee_pfc); | |
7312 | kfree(adapter->ixgbe_ieee_ets); | |
7313 | ||
7314 | #endif | |
9a799d71 | 7315 | iounmap(adapter->hw.hw_addr); |
9ce77666 | 7316 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7317 | IORESOURCE_MEM)); |
9a799d71 | 7318 | |
849c4542 | 7319 | e_dev_info("complete\n"); |
021230d4 | 7320 | |
9a799d71 AK |
7321 | free_netdev(netdev); |
7322 | ||
19d5afd4 | 7323 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7324 | |
9a799d71 AK |
7325 | pci_disable_device(pdev); |
7326 | } | |
7327 | ||
7328 | /** | |
7329 | * ixgbe_io_error_detected - called when PCI error is detected | |
7330 | * @pdev: Pointer to PCI device | |
7331 | * @state: The current pci connection state | |
7332 | * | |
7333 | * This function is called after a PCI bus error affecting | |
7334 | * this device has been detected. | |
7335 | */ | |
7336 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7337 | pci_channel_state_t state) |
9a799d71 | 7338 | { |
c60fbb00 AD |
7339 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7340 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7341 | |
83c61fa9 GR |
7342 | #ifdef CONFIG_PCI_IOV |
7343 | struct pci_dev *bdev, *vfdev; | |
7344 | u32 dw0, dw1, dw2, dw3; | |
7345 | int vf, pos; | |
7346 | u16 req_id, pf_func; | |
7347 | ||
7348 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
7349 | adapter->num_vfs == 0) | |
7350 | goto skip_bad_vf_detection; | |
7351 | ||
7352 | bdev = pdev->bus->self; | |
7353 | while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT)) | |
7354 | bdev = bdev->bus->self; | |
7355 | ||
7356 | if (!bdev) | |
7357 | goto skip_bad_vf_detection; | |
7358 | ||
7359 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
7360 | if (!pos) | |
7361 | goto skip_bad_vf_detection; | |
7362 | ||
7363 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0); | |
7364 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1); | |
7365 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2); | |
7366 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3); | |
7367 | ||
7368 | req_id = dw1 >> 16; | |
7369 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
7370 | if (!(req_id & 0x0080)) | |
7371 | goto skip_bad_vf_detection; | |
7372 | ||
7373 | pf_func = req_id & 0x01; | |
7374 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
7375 | unsigned int device_id; | |
7376 | ||
7377 | vf = (req_id & 0x7F) >> 1; | |
7378 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
7379 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
7380 | "%8.8x\tdw3: %8.8x\n", | |
7381 | dw0, dw1, dw2, dw3); | |
7382 | switch (adapter->hw.mac.type) { | |
7383 | case ixgbe_mac_82599EB: | |
7384 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
7385 | break; | |
7386 | case ixgbe_mac_X540: | |
7387 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
7388 | break; | |
7389 | default: | |
7390 | device_id = 0; | |
7391 | break; | |
7392 | } | |
7393 | ||
7394 | /* Find the pci device of the offending VF */ | |
7395 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL); | |
7396 | while (vfdev) { | |
7397 | if (vfdev->devfn == (req_id & 0xFF)) | |
7398 | break; | |
7399 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, | |
7400 | device_id, vfdev); | |
7401 | } | |
7402 | /* | |
7403 | * There's a slim chance the VF could have been hot plugged, | |
7404 | * so if it is no longer present we don't need to issue the | |
7405 | * VFLR. Just clean up the AER in that case. | |
7406 | */ | |
7407 | if (vfdev) { | |
7408 | e_dev_err("Issuing VFLR to VF %d\n", vf); | |
7409 | pci_write_config_dword(vfdev, 0xA8, 0x00008000); | |
7410 | } | |
7411 | ||
7412 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
7413 | } | |
7414 | ||
7415 | /* | |
7416 | * Even though the error may have occurred on the other port | |
7417 | * we still need to increment the vf error reference count for | |
7418 | * both ports because the I/O resume function will be called | |
7419 | * for both of them. | |
7420 | */ | |
7421 | adapter->vferr_refcount++; | |
7422 | ||
7423 | return PCI_ERS_RESULT_RECOVERED; | |
7424 | ||
7425 | skip_bad_vf_detection: | |
7426 | #endif /* CONFIG_PCI_IOV */ | |
9a799d71 AK |
7427 | netif_device_detach(netdev); |
7428 | ||
3044b8d1 BL |
7429 | if (state == pci_channel_io_perm_failure) |
7430 | return PCI_ERS_RESULT_DISCONNECT; | |
7431 | ||
9a799d71 AK |
7432 | if (netif_running(netdev)) |
7433 | ixgbe_down(adapter); | |
7434 | pci_disable_device(pdev); | |
7435 | ||
b4617240 | 7436 | /* Request a slot reset. */ |
9a799d71 AK |
7437 | return PCI_ERS_RESULT_NEED_RESET; |
7438 | } | |
7439 | ||
7440 | /** | |
7441 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7442 | * @pdev: Pointer to PCI device | |
7443 | * | |
7444 | * Restart the card from scratch, as if from a cold-boot. | |
7445 | */ | |
7446 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7447 | { | |
c60fbb00 | 7448 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
7449 | pci_ers_result_t result; |
7450 | int err; | |
9a799d71 | 7451 | |
9ce77666 | 7452 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7453 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7454 | result = PCI_ERS_RESULT_DISCONNECT; |
7455 | } else { | |
7456 | pci_set_master(pdev); | |
7457 | pci_restore_state(pdev); | |
c0e1f68b | 7458 | pci_save_state(pdev); |
9a799d71 | 7459 | |
dd4d8ca6 | 7460 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7461 | |
6fabd715 | 7462 | ixgbe_reset(adapter); |
88512539 | 7463 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7464 | result = PCI_ERS_RESULT_RECOVERED; |
7465 | } | |
7466 | ||
7467 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7468 | if (err) { | |
849c4542 ET |
7469 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7470 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7471 | /* non-fatal, continue */ |
7472 | } | |
9a799d71 | 7473 | |
6fabd715 | 7474 | return result; |
9a799d71 AK |
7475 | } |
7476 | ||
7477 | /** | |
7478 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7479 | * @pdev: Pointer to PCI device | |
7480 | * | |
7481 | * This callback is called when the error recovery driver tells us that | |
7482 | * its OK to resume normal operation. | |
7483 | */ | |
7484 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7485 | { | |
c60fbb00 AD |
7486 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7487 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7488 | |
83c61fa9 GR |
7489 | #ifdef CONFIG_PCI_IOV |
7490 | if (adapter->vferr_refcount) { | |
7491 | e_info(drv, "Resuming after VF err\n"); | |
7492 | adapter->vferr_refcount--; | |
7493 | return; | |
7494 | } | |
7495 | ||
7496 | #endif | |
c7ccde0f AD |
7497 | if (netif_running(netdev)) |
7498 | ixgbe_up(adapter); | |
9a799d71 AK |
7499 | |
7500 | netif_device_attach(netdev); | |
9a799d71 AK |
7501 | } |
7502 | ||
7503 | static struct pci_error_handlers ixgbe_err_handler = { | |
7504 | .error_detected = ixgbe_io_error_detected, | |
7505 | .slot_reset = ixgbe_io_slot_reset, | |
7506 | .resume = ixgbe_io_resume, | |
7507 | }; | |
7508 | ||
7509 | static struct pci_driver ixgbe_driver = { | |
7510 | .name = ixgbe_driver_name, | |
7511 | .id_table = ixgbe_pci_tbl, | |
7512 | .probe = ixgbe_probe, | |
7513 | .remove = __devexit_p(ixgbe_remove), | |
7514 | #ifdef CONFIG_PM | |
7515 | .suspend = ixgbe_suspend, | |
7516 | .resume = ixgbe_resume, | |
7517 | #endif | |
7518 | .shutdown = ixgbe_shutdown, | |
7519 | .err_handler = &ixgbe_err_handler | |
7520 | }; | |
7521 | ||
7522 | /** | |
7523 | * ixgbe_init_module - Driver Registration Routine | |
7524 | * | |
7525 | * ixgbe_init_module is the first routine called when the driver is | |
7526 | * loaded. All it does is register with the PCI subsystem. | |
7527 | **/ | |
7528 | static int __init ixgbe_init_module(void) | |
7529 | { | |
7530 | int ret; | |
c7689578 | 7531 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7532 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7533 | |
5dd2d332 | 7534 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7535 | dca_register_notify(&dca_notifier); |
bd0362dd | 7536 | #endif |
5dd2d332 | 7537 | |
9a799d71 AK |
7538 | ret = pci_register_driver(&ixgbe_driver); |
7539 | return ret; | |
7540 | } | |
b4617240 | 7541 | |
9a799d71 AK |
7542 | module_init(ixgbe_init_module); |
7543 | ||
7544 | /** | |
7545 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7546 | * | |
7547 | * ixgbe_exit_module is called just before the driver is removed | |
7548 | * from memory. | |
7549 | **/ | |
7550 | static void __exit ixgbe_exit_module(void) | |
7551 | { | |
5dd2d332 | 7552 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7553 | dca_unregister_notify(&dca_notifier); |
7554 | #endif | |
9a799d71 | 7555 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 7556 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7557 | } |
bd0362dd | 7558 | |
5dd2d332 | 7559 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7560 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7561 | void *p) |
bd0362dd JC |
7562 | { |
7563 | int ret_val; | |
7564 | ||
7565 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7566 | __ixgbe_notify_dca); |
bd0362dd JC |
7567 | |
7568 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7569 | } | |
b453368d | 7570 | |
5dd2d332 | 7571 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7572 | |
9a799d71 AK |
7573 | module_exit(ixgbe_exit_module); |
7574 | ||
7575 | /* ixgbe_main.c */ |