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ixgbe: Add support for build_skb
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
37689010 4 Copyright(c) 1999 - 2016 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
b3a49557 53#include <net/udp_tunnel.h>
b82b17d9
JF		 54#include <net/pkt_cls.h>
55#include <net/tc_act/tc_gact.h>
947f8a45 56#include <net/tc_act/tc_mirred.h>
9f3c7504 57#include <net/vxlan.h>
9a799d71
AK		 58
59#include "ixgbe.h"
60#include "ixgbe_common.h"
ee5f784a 61#include "ixgbe_dcb_82599.h"
1cdd1ec8 62#include "ixgbe_sriov.h"
b82b17d9 63#include "ixgbe_model.h"
9a799d71
AK		 64
65char ixgbe_driver_name[] = "ixgbe";
9c8eb720 66static const char ixgbe_driver_string[] =
e8e9f696 67 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 68#ifdef IXGBE_FCOE
ea81875a
NP		 69char ixgbe_default_device_descr[] =
70 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 71#else
72static char ixgbe_default_device_descr[] =
73 "Intel(R) 10 Gigabit Network Connection";
74#endif
1733284d 75#define DRV_VERSION "5.0.0-k"
9c8eb720 76const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 77static const char ixgbe_copyright[] =
49425dfc 78 "Copyright (c) 1999-2016 Intel Corporation.";
9a799d71 79
f44e751b
DS		 80static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
81
9a799d71 82static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 83 [board_82598] = &ixgbe_82598_info,
84 [board_82599] = &ixgbe_82599_info,
85 [board_X540] = &ixgbe_X540_info,
86 [board_X550] = &ixgbe_X550_info,
87 [board_X550EM_x] = &ixgbe_X550EM_x_info,
49425dfc 88 [board_x550em_a] = &ixgbe_x550em_a_info,
b3eb4e18 89 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info,
9a799d71
AK		 90};
91
92/* ixgbe_pci_tbl - PCI Device ID Table
93 *
94 * Wildcard entries (PCI_ANY_ID) should come last
95 * Last entry must be all 0s
96 *
97 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
98 * Class, Class Mask, private data (not used) }
99 */
9baa3c34 100static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
a711ad89 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
6a14ee0c
DS		 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
f572b2c4
MR		 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
49425dfc 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
200157c2
MR		 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
92ed8430 142 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
2d40cd17 143 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
b3eb4e18
MR		 144 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw },
145 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw },
9a799d71
AK		 146 /* required last entry */
147 {0, }
148};
149MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
150
5dd2d332 151#ifdef CONFIG_IXGBE_DCA
bd0362dd 152static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 153 void *p);
bd0362dd
JC		 154static struct notifier_block dca_notifier = {
155 .notifier_call = ixgbe_notify_dca,
156 .next = NULL,
157 .priority = 0
158};
159#endif
160
1cdd1ec8
GR		 161#ifdef CONFIG_PCI_IOV
162static unsigned int max_vfs;
163module_param(max_vfs, uint, 0);
e8e9f696 164MODULE_PARM_DESC(max_vfs,
170e8543 165 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 166#endif /* CONFIG_PCI_IOV */
167
8ef78adc
PWJ		 168static unsigned int allow_unsupported_sfp;
169module_param(allow_unsupported_sfp, uint, 0);
170MODULE_PARM_DESC(allow_unsupported_sfp,
171 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
172
b3f4d599 173#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
174static int debug = -1;
175module_param(debug, int, 0);
176MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
177
9a799d71
AK		 178MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
179MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
180MODULE_LICENSE("GPL");
181MODULE_VERSION(DRV_VERSION);
182
780484d8
MR		 183static struct workqueue_struct *ixgbe_wq;
184
14438464 185static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
b3eb4e18 186static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *);
14438464 187
b8e82001
JK		 188static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
189 u32 reg, u16 *value)
190{
b8e82001
JK		 191 struct pci_dev *parent_dev;
192 struct pci_bus *parent_bus;
193
194 parent_bus = adapter->pdev->bus->parent;
195 if (!parent_bus)
196 return -1;
197
198 parent_dev = parent_bus->self;
199 if (!parent_dev)
200 return -1;
201
c0798edf 202 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 203 return -1;
204
c0798edf 205 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 206 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
207 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
208 return -1;
b8e82001
JK		 209 return 0;
210}
211
212static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
213{
214 struct ixgbe_hw *hw = &adapter->hw;
215 u16 link_status = 0;
216 int err;
217
218 hw->bus.type = ixgbe_bus_type_pci_express;
219
220 /* Get the negotiated link width and speed from PCI config space of the
221 * parent, as this device is behind a switch
222 */
223 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
224
225 /* assume caller will handle error case */
226 if (err)
227 return err;
228
229 hw->bus.width = ixgbe_convert_bus_width(link_status);
230 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
231
232 return 0;
233}
234
e027d1ae
JK		 235/**
236 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
237 * @hw: hw specific details
238 *
239 * This function is used by probe to determine whether a device's PCI-Express
240 * bandwidth details should be gathered from the parent bus instead of from the
241 * device. Used to ensure that various locations all have the correct device ID
242 * checks.
243 */
244static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
245{
246 switch (hw->device_id) {
247 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 248 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 249 return true;
250 default:
251 return false;
252 }
253}
254
255static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
256 int expected_gts)
257{
f9328bc6 258 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 259 int max_gts = 0;
260 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
261 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
262 struct pci_dev *pdev;
263
f9328bc6
DS		 264 /* Some devices are not connected over PCIe and thus do not negotiate
265 * speed. These devices do not have valid bus info, and thus any report
266 * we generate may not be correct.
267 */
268 if (hw->bus.type == ixgbe_bus_type_internal)
269 return;
270
56d1392f 271 /* determine whether to use the parent device */
e027d1ae
JK		 272 if (ixgbe_pcie_from_parent(&adapter->hw))
273 pdev = adapter->pdev->bus->parent->self;
274 else
275 pdev = adapter->pdev;
276
277 if (pcie_get_minimum_link(pdev, &speed, &width) ||
278 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
279 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
280 return;
281 }
282
283 switch (speed) {
284 case PCIE_SPEED_2_5GT:
285 /* 8b/10b encoding reduces max throughput by 20% */
286 max_gts = 2 * width;
287 break;
288 case PCIE_SPEED_5_0GT:
289 /* 8b/10b encoding reduces max throughput by 20% */
290 max_gts = 4 * width;
291 break;
292 case PCIE_SPEED_8_0GT:
9f0a433c 293 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 294 max_gts = 8 * width;
295 break;
296 default:
297 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
298 return;
299 }
300
301 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
302 max_gts);
303 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
304 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
305 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
306 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
307 "Unknown"),
308 width,
309 (speed == PCIE_SPEED_2_5GT ? "20%" :
310 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 311 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 312 "Unknown"));
313
314 if (max_gts < expected_gts) {
315 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
316 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
317 expected_gts);
318 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
319 }
320}
321
7086400d
AD		 322static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
323{
324 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 325 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d 326 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
780484d8 327 queue_work(ixgbe_wq, &adapter->service_task);
7086400d
AD		 328}
329
2a1a091c
MR		 330static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
331{
332 struct ixgbe_adapter *adapter = hw->back;
333
334 if (!hw->hw_addr)
335 return;
336 hw->hw_addr = NULL;
337 e_dev_err("Adapter removed\n");
58cf663f
MR		 338 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
339 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 340}
341
f8e2472f 342static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 343{
344 u32 value;
345
346 /* The following check not only optimizes a bit by not
347 * performing a read on the status register when the
348 * register just read was a status register read that
349 * returned IXGBE_FAILED_READ_REG. It also blocks any
350 * potential recursion.
351 */
352 if (reg == IXGBE_STATUS) {
353 ixgbe_remove_adapter(hw);
354 return;
355 }
356 value = ixgbe_read_reg(hw, IXGBE_STATUS);
357 if (value == IXGBE_FAILED_READ_REG)
358 ixgbe_remove_adapter(hw);
359}
360
f8e2472f
MR		 361/**
362 * ixgbe_read_reg - Read from device register
363 * @hw: hw specific details
364 * @reg: offset of register to read
365 *
366 * Returns : value read or IXGBE_FAILED_READ_REG if removed
367 *
368 * This function is used to read device registers. It checks for device
369 * removal by confirming any read that returns all ones by checking the
370 * status register value for all ones. This function avoids reading from
371 * the hardware if a removal was previously detected in which case it
372 * returns IXGBE_FAILED_READ_REG (all ones).
373 */
374u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
375{
376 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
377 u32 value;
378
379 if (ixgbe_removed(reg_addr))
380 return IXGBE_FAILED_READ_REG;
2f2219be
MR		 381 if (unlikely(hw->phy.nw_mng_if_sel &
382 IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M)) {
383 struct ixgbe_adapter *adapter;
384 int i;
385
386 for (i = 0; i < 200; ++i) {
387 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
388 if (likely(!value))
389 goto writes_completed;
390 if (value == IXGBE_FAILED_READ_REG) {
391 ixgbe_remove_adapter(hw);
392 return IXGBE_FAILED_READ_REG;
393 }
394 udelay(5);
395 }
396
397 adapter = hw->back;
398 e_warn(hw, "register writes incomplete %08x\n", value);
399 }
400
401writes_completed:
f8e2472f
MR		 402 value = readl(reg_addr + reg);
403 if (unlikely(value == IXGBE_FAILED_READ_REG))
404 ixgbe_check_remove(hw, reg);
405 return value;
406}
407
14438464
MR		 408static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
409{
410 u16 value;
411
412 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
413 if (value == IXGBE_FAILED_READ_CFG_WORD) {
414 ixgbe_remove_adapter(hw);
415 return true;
416 }
417 return false;
418}
419
420u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
421{
422 struct ixgbe_adapter *adapter = hw->back;
423 u16 value;
424
425 if (ixgbe_removed(hw->hw_addr))
426 return IXGBE_FAILED_READ_CFG_WORD;
427 pci_read_config_word(adapter->pdev, reg, &value);
428 if (value == IXGBE_FAILED_READ_CFG_WORD &&
429 ixgbe_check_cfg_remove(hw, adapter->pdev))
430 return IXGBE_FAILED_READ_CFG_WORD;
431 return value;
432}
433
434#ifdef CONFIG_PCI_IOV
435static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
436{
437 struct ixgbe_adapter *adapter = hw->back;
438 u32 value;
439
440 if (ixgbe_removed(hw->hw_addr))
441 return IXGBE_FAILED_READ_CFG_DWORD;
442 pci_read_config_dword(adapter->pdev, reg, &value);
443 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
444 ixgbe_check_cfg_remove(hw, adapter->pdev))
445 return IXGBE_FAILED_READ_CFG_DWORD;
446 return value;
447}
448#endif /* CONFIG_PCI_IOV */
449
ed19231c
JK		 450void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
451{
452 struct ixgbe_adapter *adapter = hw->back;
453
454 if (ixgbe_removed(hw->hw_addr))
455 return;
456 pci_write_config_word(adapter->pdev, reg, value);
457}
458
7086400d
AD		 459static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
460{
461 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
462
52f33af8 463 /* flush memory to make sure state is correct before next watchdog */
4e857c58 464 smp_mb__before_atomic();
7086400d
AD		 465 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
466}
467
dcd79aeb
TI		 468struct ixgbe_reg_info {
469 u32 ofs;
470 char *name;
471};
472
473static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
474
475 /* General Registers */
476 {IXGBE_CTRL, "CTRL"},
477 {IXGBE_STATUS, "STATUS"},
478 {IXGBE_CTRL_EXT, "CTRL_EXT"},
479
480 /* Interrupt Registers */
481 {IXGBE_EICR, "EICR"},
482
483 /* RX Registers */
484 {IXGBE_SRRCTL(0), "SRRCTL"},
485 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
486 {IXGBE_RDLEN(0), "RDLEN"},
487 {IXGBE_RDH(0), "RDH"},
488 {IXGBE_RDT(0), "RDT"},
489 {IXGBE_RXDCTL(0), "RXDCTL"},
490 {IXGBE_RDBAL(0), "RDBAL"},
491 {IXGBE_RDBAH(0), "RDBAH"},
492
493 /* TX Registers */
494 {IXGBE_TDBAL(0), "TDBAL"},
495 {IXGBE_TDBAH(0), "TDBAH"},
496 {IXGBE_TDLEN(0), "TDLEN"},
497 {IXGBE_TDH(0), "TDH"},
498 {IXGBE_TDT(0), "TDT"},
499 {IXGBE_TXDCTL(0), "TXDCTL"},
500
501 /* List Terminator */
ca8dfe25 502 { .name = NULL }
dcd79aeb
TI		 503};
504
505
506/*
507 * ixgbe_regdump - register printout routine
508 */
509static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
510{
511 int i = 0, j = 0;
512 char rname[16];
513 u32 regs[64];
514
515 switch (reginfo->ofs) {
516 case IXGBE_SRRCTL(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
519 break;
520 case IXGBE_DCA_RXCTRL(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
523 break;
524 case IXGBE_RDLEN(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
527 break;
528 case IXGBE_RDH(0):
529 for (i = 0; i < 64; i++)
530 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
531 break;
532 case IXGBE_RDT(0):
533 for (i = 0; i < 64; i++)
534 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
535 break;
536 case IXGBE_RXDCTL(0):
537 for (i = 0; i < 64; i++)
538 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
539 break;
540 case IXGBE_RDBAL(0):
541 for (i = 0; i < 64; i++)
542 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
543 break;
544 case IXGBE_RDBAH(0):
545 for (i = 0; i < 64; i++)
546 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
547 break;
548 case IXGBE_TDBAL(0):
549 for (i = 0; i < 64; i++)
550 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
551 break;
552 case IXGBE_TDBAH(0):
553 for (i = 0; i < 64; i++)
554 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
555 break;
556 case IXGBE_TDLEN(0):
557 for (i = 0; i < 64; i++)
558 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
559 break;
560 case IXGBE_TDH(0):
561 for (i = 0; i < 64; i++)
562 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
563 break;
564 case IXGBE_TDT(0):
565 for (i = 0; i < 64; i++)
566 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
567 break;
568 case IXGBE_TXDCTL(0):
569 for (i = 0; i < 64; i++)
570 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
571 break;
572 default:
c7689578 573 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 574 IXGBE_READ_REG(hw, reginfo->ofs));
575 return;
576 }
577
578 for (i = 0; i < 8; i++) {
579 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 580 pr_err("%-15s", rname);
dcd79aeb 581 for (j = 0; j < 8; j++)
c7689578
JP		 582 pr_cont(" %08x", regs[i*8+j]);
583 pr_cont("\n");
dcd79aeb
TI		 584 }
585
586}
587
588/*
589 * ixgbe_dump - Print registers, tx-rings and rx-rings
590 */
591static void ixgbe_dump(struct ixgbe_adapter *adapter)
592{
593 struct net_device *netdev = adapter->netdev;
594 struct ixgbe_hw *hw = &adapter->hw;
595 struct ixgbe_reg_info *reginfo;
596 int n = 0;
597 struct ixgbe_ring *tx_ring;
729739b7 598 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 599 union ixgbe_adv_tx_desc *tx_desc;
600 struct my_u0 { u64 a; u64 b; } *u0;
601 struct ixgbe_ring *rx_ring;
602 union ixgbe_adv_rx_desc *rx_desc;
603 struct ixgbe_rx_buffer *rx_buffer_info;
604 u32 staterr;
605 int i = 0;
606
607 if (!netif_msg_hw(adapter))
608 return;
609
610 /* Print netdevice Info */
611 if (netdev) {
612 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 613 pr_info("Device Name state "
4a7c9726
TK		 614 "trans_start\n");
615 pr_info("%-15s %016lX %016lX\n",
c7689578
JP		 616 netdev->name,
617 netdev->state,
4a7c9726 618 dev_trans_start(netdev));
dcd79aeb
TI		 619 }
620
621 /* Print Registers */
622 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 623 pr_info(" Register Name Value\n");
dcd79aeb
TI		 624 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
625 reginfo->name; reginfo++) {
626 ixgbe_regdump(hw, reginfo);
627 }
628
629 /* Print TX Ring Summary */
630 if (!netdev || !netif_running(netdev))
e90dd264 631 return;
dcd79aeb
TI		 632
633 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 634 pr_info(" %s %s %s %s\n",
635 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
636 "leng", "ntw", "timestamp");
dcd79aeb
TI		 637 for (n = 0; n < adapter->num_tx_queues; n++) {
638 tx_ring = adapter->tx_ring[n];
729739b7 639 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 640 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 641 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 642 (u64)dma_unmap_addr(tx_buffer, dma),
643 dma_unmap_len(tx_buffer, len),
644 tx_buffer->next_to_watch,
645 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 646 }
647
648 /* Print TX Rings */
649 if (!netif_msg_tx_done(adapter))
650 goto rx_ring_summary;
651
652 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
653
654 /* Transmit Descriptor Formats
655 *
39ac868a 656 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 657 * +--------------------------------------------------------------+
658 * 0 | Buffer Address [63:0] |
659 * +--------------------------------------------------------------+
39ac868a 660 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 661 * +--------------------------------------------------------------+
662 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 663 *
664 * 82598 Advanced Transmit Descriptor (Write-Back Format)
665 * +--------------------------------------------------------------+
666 * 0 | RSV [63:0] |
667 * +--------------------------------------------------------------+
668 * 8 | RSV | STA | NXTSEQ |
669 * +--------------------------------------------------------------+
670 * 63 36 35 32 31 0
671 *
672 * 82599+ Advanced Transmit Descriptor
673 * +--------------------------------------------------------------+
674 * 0 | Buffer Address [63:0] |
675 * +--------------------------------------------------------------+
676 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
677 * +--------------------------------------------------------------+
678 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
679 *
680 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
681 * +--------------------------------------------------------------+
682 * 0 | RSV [63:0] |
683 * +--------------------------------------------------------------+
684 * 8 | RSV | STA | RSV |
685 * +--------------------------------------------------------------+
686 * 63 36 35 32 31 0
dcd79aeb
TI		 687 */
688
689 for (n = 0; n < adapter->num_tx_queues; n++) {
690 tx_ring = adapter->tx_ring[n];
c7689578
JP		 691 pr_info("------------------------------------\n");
692 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
693 pr_info("------------------------------------\n");
8ad88e37
JH		 694 pr_info("%s%s %s %s %s %s\n",
695 "T [desc] [address 63:0 ] ",
696 "[PlPOIdStDDt Ln] [bi->dma ] ",
697 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 698
699 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 700 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 701 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 702 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 703 if (dma_unmap_len(tx_buffer, len) > 0) {
704 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
705 i,
706 le64_to_cpu(u0->a),
707 le64_to_cpu(u0->b),
708 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 709 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 710 tx_buffer->next_to_watch,
711 (u64)tx_buffer->time_stamp,
712 tx_buffer->skb);
713 if (i == tx_ring->next_to_use &&
714 i == tx_ring->next_to_clean)
715 pr_cont(" NTC/U\n");
716 else if (i == tx_ring->next_to_use)
717 pr_cont(" NTU\n");
718 else if (i == tx_ring->next_to_clean)
719 pr_cont(" NTC\n");
720 else
721 pr_cont("\n");
722
723 if (netif_msg_pktdata(adapter) &&
724 tx_buffer->skb)
725 print_hex_dump(KERN_INFO, "",
726 DUMP_PREFIX_ADDRESS, 16, 1,
727 tx_buffer->skb->data,
728 dma_unmap_len(tx_buffer, len),
729 true);
730 }
dcd79aeb
TI		 731 }
732 }
733
734 /* Print RX Rings Summary */
735rx_ring_summary:
736 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 737 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 738 for (n = 0; n < adapter->num_rx_queues; n++) {
739 rx_ring = adapter->rx_ring[n];
c7689578
JP		 740 pr_info("%5d %5X %5X\n",
741 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 742 }
743
744 /* Print RX Rings */
745 if (!netif_msg_rx_status(adapter))
e90dd264 746 return;
dcd79aeb
TI		 747
748 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
749
39ac868a
JH		 750 /* Receive Descriptor Formats
751 *
752 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 753 * 63 1 0
754 * +-----------------------------------------------------+
755 * 0 | Packet Buffer Address [63:1] |A0/NSE|
756 * +----------------------------------------------+------+
757 * 8 | Header Buffer Address [63:1] | DD |
758 * +-----------------------------------------------------+
759 *
760 *
39ac868a 761 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 762 *
763 * 63 48 47 32 31 30 21 20 16 15 4 3 0
764 * +------------------------------------------------------+
39ac868a
JH		 765 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
766 * | Packet | IP | | | | Type | Type |
767 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 768 * +------------------------------------------------------+
769 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
770 * +------------------------------------------------------+
771 * 63 48 47 32 31 20 19 0
39ac868a
JH		 772 *
773 * 82599+ Advanced Receive Descriptor (Read) Format
774 * 63 1 0
775 * +-----------------------------------------------------+
776 * 0 | Packet Buffer Address [63:1] |A0/NSE|
777 * +----------------------------------------------+------+
778 * 8 | Header Buffer Address [63:1] | DD |
779 * +-----------------------------------------------------+
780 *
781 *
782 * 82599+ Advanced Receive Descriptor (Write-Back) Format
783 *
784 * 63 48 47 32 31 30 21 20 17 16 4 3 0
785 * +------------------------------------------------------+
786 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
787 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
788 * |/ Flow Dir Flt ID | | | | | |
789 * +------------------------------------------------------+
790 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
791 * +------------------------------------------------------+
792 * 63 48 47 32 31 20 19 0
dcd79aeb 793 */
39ac868a 794
dcd79aeb
TI		 795 for (n = 0; n < adapter->num_rx_queues; n++) {
796 rx_ring = adapter->rx_ring[n];
c7689578
JP		 797 pr_info("------------------------------------\n");
798 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
799 pr_info("------------------------------------\n");
8ad88e37
JH		 800 pr_info("%s%s%s",
801 "R [desc] [ PktBuf A0] ",
802 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 803 "<-- Adv Rx Read format\n");
8ad88e37
JH		 804 pr_info("%s%s%s",
805 "RWB[desc] [PcsmIpSHl PtRs] ",
806 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 807 "<-- Adv Rx Write-Back format\n");
808
809 for (i = 0; i < rx_ring->count; i++) {
810 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 811 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 812 u0 = (struct my_u0 *)rx_desc;
813 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
814 if (staterr & IXGBE_RXD_STAT_DD) {
815 /* Descriptor Done */
c7689578 816 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 817 "%016llX ---------------- %p", i,
818 le64_to_cpu(u0->a),
819 le64_to_cpu(u0->b),
820 rx_buffer_info->skb);
821 } else {
c7689578 822 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 823 "%016llX %016llX %p", i,
824 le64_to_cpu(u0->a),
825 le64_to_cpu(u0->b),
826 (u64)rx_buffer_info->dma,
827 rx_buffer_info->skb);
828
9c50c035
ET		 829 if (netif_msg_pktdata(adapter) &&
830 rx_buffer_info->dma) {
dcd79aeb
TI		 831 print_hex_dump(KERN_INFO, "",
832 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 833 page_address(rx_buffer_info->page) +
834 rx_buffer_info->page_offset,
f800326d 835 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 836 }
837 }
838
839 if (i == rx_ring->next_to_use)
c7689578 840 pr_cont(" NTU\n");
dcd79aeb 841 else if (i == rx_ring->next_to_clean)
c7689578 842 pr_cont(" NTC\n");
dcd79aeb 843 else
c7689578 844 pr_cont("\n");
dcd79aeb
TI		 845
846 }
847 }
dcd79aeb
TI		 848}
849
5eba3699
AV		 850static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
851{
852 u32 ctrl_ext;
853
854 /* Let firmware take over control of h/w */
855 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 857 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 858}
859
860static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
861{
862 u32 ctrl_ext;
863
864 /* Let firmware know the driver has taken over */
865 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
866 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 867 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 868}
9a799d71 869
49ce9c2c 870/**
e8e26350
PW		 871 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
872 * @adapter: pointer to adapter struct
873 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
874 * @queue: queue to map the corresponding interrupt to
875 * @msix_vector: the vector to map to the corresponding queue
876 *
877 */
878static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 879 u8 queue, u8 msix_vector)
9a799d71
AK		 880{
881 u32 ivar, index;
e8e26350
PW		 882 struct ixgbe_hw *hw = &adapter->hw;
883 switch (hw->mac.type) {
884 case ixgbe_mac_82598EB:
885 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
886 if (direction == -1)
887 direction = 0;
888 index = (((direction * 64) + queue) >> 2) & 0x1F;
889 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
890 ivar &= ~(0xFF << (8 * (queue & 0x3)));
891 ivar |= (msix_vector << (8 * (queue & 0x3)));
892 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
893 break;
894 case ixgbe_mac_82599EB:
b93a2226 895 case ixgbe_mac_X540:
9a75a1ac
DS		 896 case ixgbe_mac_X550:
897 case ixgbe_mac_X550EM_x:
49425dfc 898 case ixgbe_mac_x550em_a:
e8e26350
PW		 899 if (direction == -1) {
900 /* other causes */
901 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
902 index = ((queue & 1) * 8);
903 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
904 ivar &= ~(0xFF << index);
905 ivar |= (msix_vector << index);
906 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
907 break;
908 } else {
909 /* tx or rx causes */
910 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
911 index = ((16 * (queue & 1)) + (8 * direction));
912 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
913 ivar &= ~(0xFF << index);
914 ivar |= (msix_vector << index);
915 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
916 break;
917 }
918 default:
919 break;
920 }
9a799d71
AK		 921}
922
fe49f04a 923static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 924 u64 qmask)
fe49f04a
AD		 925{
926 u32 mask;
927
bd508178
AD		 928 switch (adapter->hw.mac.type) {
929 case ixgbe_mac_82598EB:
fe49f04a
AD		 930 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 932 break;
933 case ixgbe_mac_82599EB:
b93a2226 934 case ixgbe_mac_X540:
9a75a1ac
DS		 935 case ixgbe_mac_X550:
936 case ixgbe_mac_X550EM_x:
49425dfc 937 case ixgbe_mac_x550em_a:
fe49f04a
AD		 938 mask = (qmask & 0xFFFFFFFF);
939 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
940 mask = (qmask >> 32);
941 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 942 break;
943 default:
944 break;
fe49f04a
AD		 945 }
946}
947
729739b7
AD		 948void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
949 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 950{
729739b7
AD		 951 if (tx_buffer->skb) {
952 dev_kfree_skb_any(tx_buffer->skb);
953 if (dma_unmap_len(tx_buffer, len))
d3d00239 954 dma_unmap_single(ring->dev,
729739b7
AD		 955 dma_unmap_addr(tx_buffer, dma),
956 dma_unmap_len(tx_buffer, len),
957 DMA_TO_DEVICE);
958 } else if (dma_unmap_len(tx_buffer, len)) {
959 dma_unmap_page(ring->dev,
960 dma_unmap_addr(tx_buffer, dma),
961 dma_unmap_len(tx_buffer, len),
962 DMA_TO_DEVICE);
e5a43549 963 }
729739b7
AD		 964 tx_buffer->next_to_watch = NULL;
965 tx_buffer->skb = NULL;
966 dma_unmap_len_set(tx_buffer, len, 0);
967 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 968}
969
943561d3 970static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 971{
972 struct ixgbe_hw *hw = &adapter->hw;
973 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 974 int i;
943561d3 975 u32 data;
c84d324c 976
943561d3
AD		 977 if ((hw->fc.current_mode != ixgbe_fc_full) &&
978 (hw->fc.current_mode != ixgbe_fc_rx_pause))
979 return;
c84d324c 980
943561d3
AD		 981 switch (hw->mac.type) {
982 case ixgbe_mac_82598EB:
983 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
984 break;
985 default:
986 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
987 }
988 hwstats->lxoffrxc += data;
c84d324c 989
943561d3
AD		 990 /* refill credits (no tx hang) if we received xoff */
991 if (!data)
c84d324c 992 return;
943561d3
AD		 993
994 for (i = 0; i < adapter->num_tx_queues; i++)
995 clear_bit(__IXGBE_HANG_CHECK_ARMED,
996 &adapter->tx_ring[i]->state);
997}
998
999static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
1000{
1001 struct ixgbe_hw *hw = &adapter->hw;
1002 struct ixgbe_hw_stats *hwstats = &adapter->stats;
1003 u32 xoff[8] = {0};
2afaa00d 1004 u8 tc;
943561d3
AD		 1005 int i;
1006 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
1007
1008 if (adapter->ixgbe_ieee_pfc)
1009 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
1010
1011 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
1012 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 1013 return;
943561d3 1014 }
c84d324c
JF		 1015
1016 /* update stats for each tc, only valid with PFC enabled */
1017 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 1018 u32 pxoffrxc;
1019
c84d324c
JF		 1020 switch (hw->mac.type) {
1021 case ixgbe_mac_82598EB:
2afaa00d 1022 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 1023 break;
c84d324c 1024 default:
2afaa00d 1025 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 1026 }
2afaa00d
PN		 1027 hwstats->pxoffrxc[i] += pxoffrxc;
1028 /* Get the TC for given UP */
1029 tc = netdev_get_prio_tc_map(adapter->netdev, i);
1030 xoff[tc] += pxoffrxc;
c84d324c
JF		 1031 }
1032
1033 /* disarm tx queues that have received xoff frames */
1034 for (i = 0; i < adapter->num_tx_queues; i++) {
1035 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1036
2afaa00d 1037 tc = tx_ring->dcb_tc;
c84d324c
JF		 1038 if (xoff[tc])
1039 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1040 }
26f23d82
YZ		 1041}
1042
c84d324c 1043static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1044{
7d7ce682 1045 return ring->stats.packets;
c84d324c
JF		 1046}
1047
1048static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1049{
2a47fa45
JF		 1050 struct ixgbe_adapter *adapter;
1051 struct ixgbe_hw *hw;
1052 u32 head, tail;
1053
1054 if (ring->l2_accel_priv)
1055 adapter = ring->l2_accel_priv->real_adapter;
1056 else
1057 adapter = netdev_priv(ring->netdev);
e01c31a5 1058
2a47fa45
JF		 1059 hw = &adapter->hw;
1060 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1061 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1062
1063 if (head != tail)
1064 return (head < tail) ?
1065 tail - head : (tail + ring->count - head);
1066
1067 return 0;
1068}
1069
1070static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1071{
1072 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1073 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1074 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1075
7d637bcc 1076 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1077
1078 /*
1079 * Check for a hung queue, but be thorough. This verifies
1080 * that a transmit has been completed since the previous
1081 * check AND there is at least one packet pending. The
1082 * ARMED bit is set to indicate a potential hang. The
1083 * bit is cleared if a pause frame is received to remove
1084 * false hang detection due to PFC or 802.3x frames. By
1085 * requiring this to fail twice we avoid races with
1086 * pfc clearing the ARMED bit and conditions where we
1087 * run the check_tx_hang logic with a transmit completion
1088 * pending but without time to complete it yet.
1089 */
e90dd264 1090 if (tx_done_old == tx_done && tx_pending)
c84d324c 1091 /* make sure it is true for two checks in a row */
e90dd264
MR		 1092 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1093 &tx_ring->state);
1094 /* update completed stats and continue */
1095 tx_ring->tx_stats.tx_done_old = tx_done;
1096 /* reset the countdown */
1097 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1098
e90dd264 1099 return false;
9a799d71
AK		 1100}
1101
c83c6cbd
AD		 1102/**
1103 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1104 * @adapter: driver private struct
1105 **/
1106static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1107{
1108
1109 /* Do the reset outside of interrupt context */
1110 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
57ca2a4f 1111 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
12ff3f3b 1112 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1113 ixgbe_service_event_schedule(adapter);
1114 }
1115}
e01c31a5 1116
c04f90e5
RP		 1117/**
1118 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1119 **/
1120static int ixgbe_tx_maxrate(struct net_device *netdev,
1121 int queue_index, u32 maxrate)
1122{
1123 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1124 struct ixgbe_hw *hw = &adapter->hw;
1125 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1126
1127 if (!maxrate)
1128 return 0;
1129
1130 /* Calculate the rate factor values to set */
1131 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1132 bcnrc_val /= maxrate;
1133
1134 /* clear everything but the rate factor */
1135 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1136 IXGBE_RTTBCNRC_RF_DEC_MASK;
1137
1138 /* enable the rate scheduler */
1139 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1140
1141 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1142 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1143
1144 return 0;
1145}
1146
9a799d71
AK		 1147/**
1148 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1149 * @q_vector: structure containing interrupt and ring information
e01c31a5 1150 * @tx_ring: tx ring to clean
8220bbc1 1151 * @napi_budget: Used to determine if we are in netpoll
9a799d71 1152 **/
fe49f04a 1153static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
a3a8749d 1154 struct ixgbe_ring *tx_ring, int napi_budget)
9a799d71 1155{
fe49f04a 1156 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1157 struct ixgbe_tx_buffer *tx_buffer;
1158 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1159 unsigned int total_bytes = 0, total_packets = 0;
59224555 1160 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1161 unsigned int i = tx_ring->next_to_clean;
1162
1163 if (test_bit(__IXGBE_DOWN, &adapter->state))
1164 return true;
9a799d71 1165
d3d00239 1166 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1167 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1168 i -= tx_ring->count;
12207e49 1169
729739b7 1170 do {
d3d00239
AD		 1171 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1172
1173 /* if next_to_watch is not set then there is no work pending */
1174 if (!eop_desc)
1175 break;
1176
7f83a9e6 1177 /* prevent any other reads prior to eop_desc */
7e63bf49 1178 read_barrier_depends();
7f83a9e6 1179
d3d00239
AD		 1180 /* if DD is not set pending work has not been completed */
1181 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1182 break;
8ad494b0 1183
d3d00239
AD		 1184 /* clear next_to_watch to prevent false hangs */
1185 tx_buffer->next_to_watch = NULL;
8ad494b0 1186
091a6246
AD		 1187 /* update the statistics for this packet */
1188 total_bytes += tx_buffer->bytecount;
1189 total_packets += tx_buffer->gso_segs;
1190
fd0db0ed 1191 /* free the skb */
a3a8749d 1192 napi_consume_skb(tx_buffer->skb, napi_budget);
fd0db0ed 1193
729739b7
AD		 1194 /* unmap skb header data */
1195 dma_unmap_single(tx_ring->dev,
1196 dma_unmap_addr(tx_buffer, dma),
1197 dma_unmap_len(tx_buffer, len),
1198 DMA_TO_DEVICE);
1199
fd0db0ed
AD		 1200 /* clear tx_buffer data */
1201 tx_buffer->skb = NULL;
729739b7 1202 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1203
729739b7
AD		 1204 /* unmap remaining buffers */
1205 while (tx_desc != eop_desc) {
d3d00239
AD		 1206 tx_buffer++;
1207 tx_desc++;
8ad494b0 1208 i++;
729739b7
AD		 1209 if (unlikely(!i)) {
1210 i -= tx_ring->count;
d3d00239 1211 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1212 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1213 }
e01c31a5 1214
729739b7
AD		 1215 /* unmap any remaining paged data */
1216 if (dma_unmap_len(tx_buffer, len)) {
1217 dma_unmap_page(tx_ring->dev,
1218 dma_unmap_addr(tx_buffer, dma),
1219 dma_unmap_len(tx_buffer, len),
1220 DMA_TO_DEVICE);
1221 dma_unmap_len_set(tx_buffer, len, 0);
1222 }
1223 }
1224
1225 /* move us one more past the eop_desc for start of next pkt */
1226 tx_buffer++;
1227 tx_desc++;
1228 i++;
1229 if (unlikely(!i)) {
1230 i -= tx_ring->count;
1231 tx_buffer = tx_ring->tx_buffer_info;
1232 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1233 }
1234
1235 /* issue prefetch for next Tx descriptor */
1236 prefetch(tx_desc);
12207e49 1237
729739b7
AD		 1238 /* update budget accounting */
1239 budget--;
1240 } while (likely(budget));
1241
1242 i += tx_ring->count;
9a799d71 1243 tx_ring->next_to_clean = i;
d3d00239 1244 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1245 tx_ring->stats.bytes += total_bytes;
bd198058 1246 tx_ring->stats.packets += total_packets;
d3d00239 1247 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1248 q_vector->tx.total_bytes += total_bytes;
1249 q_vector->tx.total_packets += total_packets;
b953799e 1250
c84d324c
JF		 1251 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1252 /* schedule immediate reset if we believe we hung */
1253 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1254 e_err(drv, "Detected Tx Unit Hang\n"
1255 " Tx Queue <%d>\n"
1256 " TDH, TDT <%x>, <%x>\n"
1257 " next_to_use <%x>\n"
1258 " next_to_clean <%x>\n"
1259 "tx_buffer_info[next_to_clean]\n"
1260 " time_stamp <%lx>\n"
1261 " jiffies <%lx>\n",
1262 tx_ring->queue_index,
1263 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1264 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1265 tx_ring->next_to_use, i,
1266 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1267
1268 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1269
1270 e_info(probe,
1271 "tx hang %d detected on queue %d, resetting adapter\n",
1272 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1273
b953799e 1274 /* schedule immediate reset if we believe we hung */
c83c6cbd 1275 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1276
1277 /* the adapter is about to reset, no point in enabling stuff */
59224555 1278 return true;
b953799e 1279 }
9a799d71 1280
b2d96e0a
AD		 1281 netdev_tx_completed_queue(txring_txq(tx_ring),
1282 total_packets, total_bytes);
1283
e092be60 1284#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1285 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1286 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1287 /* Make sure that anybody stopping the queue after this
1288 * sees the new next_to_clean.
1289 */
1290 smp_mb();
729739b7
AD		 1291 if (__netif_subqueue_stopped(tx_ring->netdev,
1292 tx_ring->queue_index)
1293 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1294 netif_wake_subqueue(tx_ring->netdev,
1295 tx_ring->queue_index);
5b7da515 1296 ++tx_ring->tx_stats.restart_queue;
30eba97a 1297 }
e092be60 1298 }
9a799d71 1299
59224555 1300 return !!budget;
9a799d71
AK		 1301}
1302
5dd2d332 1303#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1304static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1305 struct ixgbe_ring *tx_ring,
33cf09c9 1306 int cpu)
bd0362dd 1307{
33cf09c9 1308 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1309 u32 txctrl = 0;
bdda1a61 1310 u16 reg_offset;
33cf09c9 1311
9de7605e
MR		 1312 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1313 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1314
33cf09c9
AD		 1315 switch (hw->mac.type) {
1316 case ixgbe_mac_82598EB:
bdda1a61 1317 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1318 break;
1319 case ixgbe_mac_82599EB:
b93a2226 1320 case ixgbe_mac_X540:
bdda1a61
AD		 1321 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1322 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1323 break;
1324 default:
bdda1a61
AD		 1325 /* for unknown hardware do not write register */
1326 return;
bd0362dd 1327 }
bdda1a61
AD		 1328
1329 /*
1330 * We can enable relaxed ordering for reads, but not writes when
1331 * DCA is enabled. This is due to a known issue in some chipsets
1332 * which will cause the DCA tag to be cleared.
1333 */
1334 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1335 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1336 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1337
1338 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1339}
1340
bdda1a61
AD		 1341static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1342 struct ixgbe_ring *rx_ring,
33cf09c9 1343 int cpu)
bd0362dd 1344{
33cf09c9 1345 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1346 u32 rxctrl = 0;
bdda1a61
AD		 1347 u8 reg_idx = rx_ring->reg_idx;
1348
9de7605e
MR		 1349 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1350 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1351
1352 switch (hw->mac.type) {
33cf09c9 1353 case ixgbe_mac_82599EB:
b93a2226 1354 case ixgbe_mac_X540:
bdda1a61 1355 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1356 break;
1357 default:
1358 break;
1359 }
bdda1a61
AD		 1360
1361 /*
1362 * We can enable relaxed ordering for reads, but not writes when
1363 * DCA is enabled. This is due to a known issue in some chipsets
1364 * which will cause the DCA tag to be cleared.
1365 */
1366 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1367 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1368 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1369
1370 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1371}
1372
1373static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1374{
1375 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1376 struct ixgbe_ring *ring;
bd0362dd 1377 int cpu = get_cpu();
bd0362dd 1378
33cf09c9
AD		 1379 if (q_vector->cpu == cpu)
1380 goto out_no_update;
1381
a557928e 1382 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1383 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1384
a557928e 1385 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1386 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1387
1388 q_vector->cpu = cpu;
1389out_no_update:
bd0362dd
JC		 1390 put_cpu();
1391}
1392
1393static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1394{
1395 int i;
1396
e35ec126 1397 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1398 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1400 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1401 else
1402 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1403 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1404
49c7ffbe 1405 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1406 adapter->q_vector[i]->cpu = -1;
1407 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1408 }
1409}
1410
1411static int __ixgbe_notify_dca(struct device *dev, void *data)
1412{
c60fbb00 1413 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1414 unsigned long event = *(unsigned long *)data;
1415
2a72c31e 1416 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1417 return 0;
1418
bd0362dd
JC		 1419 switch (event) {
1420 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1421 /* if we're already enabled, don't do it again */
1422 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1423 break;
652f093f 1424 if (dca_add_requester(dev) == 0) {
96b0e0f6 1425 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1427 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1428 break;
1429 }
1430 /* Fall Through since DCA is disabled. */
1431 case DCA_PROVIDER_REMOVE:
1432 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1433 dca_remove_requester(dev);
1434 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1436 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1437 }
1438 break;
1439 }
1440
652f093f 1441 return 0;
bd0362dd 1442}
67a74ee2 1443
bdda1a61 1444#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1445
1446#define IXGBE_RSS_L4_TYPES_MASK \
1447 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1448 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1449 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1450 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1451
8a0da21b
AD		 1452static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1453 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1454 struct sk_buff *skb)
1455{
7edda4b8
FD		 1456 u16 rss_type;
1457
1458 if (!(ring->netdev->features & NETIF_F_RXHASH))
1459 return;
1460
1461 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1462 IXGBE_RXDADV_RSSTYPE_MASK;
1463
1464 if (!rss_type)
1465 return;
1466
1467 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1468 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1469 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1470}
1471
f800326d 1472#ifdef IXGBE_FCOE
ff886dfc
AD		 1473/**
1474 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1475 * @ring: structure containing ring specific data
ff886dfc
AD		 1476 * @rx_desc: advanced rx descriptor
1477 *
1478 * Returns : true if it is FCoE pkt
1479 */
57efd44c 1480static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1481 union ixgbe_adv_rx_desc *rx_desc)
1482{
1483 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1484
57efd44c 1485 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1486 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1487 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1488 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1489}
1490
f800326d 1491#endif /* IXGBE_FCOE */
e59bd25d
AV		 1492/**
1493 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1494 * @ring: structure containing ring specific data
1495 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1496 * @skb: skb currently being received and modified
1497 **/
8a0da21b 1498static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1499 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1500 struct sk_buff *skb)
9a799d71 1501{
3f207800 1502 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
3f207800
DS		 1503 bool encap_pkt = false;
1504
8a0da21b 1505 skb_checksum_none_assert(skb);
9a799d71 1506
712744be 1507 /* Rx csum disabled */
8a0da21b 1508 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1509 return;
e59bd25d 1510
a21d0822
ET		 1511 /* check for VXLAN and Geneve packets */
1512 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
3f207800
DS		 1513 encap_pkt = true;
1514 skb->encapsulation = 1;
3f207800
DS		 1515 }
1516
e59bd25d 1517 /* if IP and error */
f56e0cb1
AD		 1518 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1519 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1520 ring->rx_stats.csum_err++;
9a799d71
AK		 1521 return;
1522 }
e59bd25d 1523
f56e0cb1 1524 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1525 return;
1526
f56e0cb1 1527 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1528 /*
1529 * 82599 errata, UDP frames with a 0 checksum can be marked as
1530 * checksum errors.
1531 */
8a0da21b
AD		 1532 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1533 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1534 return;
1535
8a0da21b 1536 ring->rx_stats.csum_err++;
e59bd25d
AV		 1537 return;
1538 }
1539
9a799d71 1540 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1541 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1542 if (encap_pkt) {
1543 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1544 return;
1545
1546 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
d469251b 1547 skb->ip_summed = CHECKSUM_NONE;
3f207800
DS		 1548 return;
1549 }
1550 /* If we checked the outer header let the stack know */
1551 skb->csum_level = 1;
1552 }
9a799d71
AK		 1553}
1554
2de6aa3a
AD		 1555static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring)
1556{
1557 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0;
1558}
1559
f990b79b
AD		 1560static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1561 struct ixgbe_rx_buffer *bi)
1562{
1563 struct page *page = bi->page;
18cb652a 1564 dma_addr_t dma;
f990b79b 1565
f800326d 1566 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1567 if (likely(page))
f990b79b
AD		 1568 return true;
1569
f800326d 1570 /* alloc new page for storage */
18cb652a
AD		 1571 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1572 if (unlikely(!page)) {
1573 rx_ring->rx_stats.alloc_rx_page_failed++;
1574 return false;
f990b79b
AD		 1575 }
1576
f800326d 1577 /* map page for use */
f3213d93
AD		 1578 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1579 ixgbe_rx_pg_size(rx_ring),
1580 DMA_FROM_DEVICE,
1581 IXGBE_RX_DMA_ATTR);
f800326d
AD		 1582
1583 /*
1584 * if mapping failed free memory back to system since
1585 * there isn't much point in holding memory we can't use
1586 */
1587 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1588 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1589
f990b79b
AD		 1590 rx_ring->rx_stats.alloc_rx_page_failed++;
1591 return false;
1592 }
1593
f800326d 1594 bi->dma = dma;
18cb652a 1595 bi->page = page;
2de6aa3a 1596 bi->page_offset = ixgbe_rx_offset(rx_ring);
1b56cf49 1597 bi->pagecnt_bias = 1;
f800326d 1598
f990b79b
AD		 1599 return true;
1600}
1601
9a799d71 1602/**
f990b79b 1603 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1604 * @rx_ring: ring to place buffers on
1605 * @cleaned_count: number of buffers to replace
9a799d71 1606 **/
fc77dc3c 1607void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1608{
9a799d71 1609 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1610 struct ixgbe_rx_buffer *bi;
d5f398ed 1611 u16 i = rx_ring->next_to_use;
4f4542bf 1612 u16 bufsz;
9a799d71 1613
f800326d
AD		 1614 /* nothing to do */
1615 if (!cleaned_count)
fc77dc3c
AD		 1616 return;
1617
e4f74028 1618 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1619 bi = &rx_ring->rx_buffer_info[i];
1620 i -= rx_ring->count;
9a799d71 1621
4f4542bf
AD		 1622 bufsz = ixgbe_rx_bufsz(rx_ring);
1623
f800326d
AD		 1624 do {
1625 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1626 break;
d5f398ed 1627
f3213d93
AD		 1628 /* sync the buffer for use by the device */
1629 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
4f4542bf 1630 bi->page_offset, bufsz,
f3213d93
AD		 1631 DMA_FROM_DEVICE);
1632
f800326d
AD		 1633 /*
1634 * Refresh the desc even if buffer_addrs didn't change
1635 * because each write-back erases this info.
1636 */
1637 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1638
f990b79b
AD		 1639 rx_desc++;
1640 bi++;
9a799d71 1641 i++;
f990b79b 1642 if (unlikely(!i)) {
e4f74028 1643 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1644 bi = rx_ring->rx_buffer_info;
1645 i -= rx_ring->count;
1646 }
1647
c3630cc4
AD		 1648 /* clear the length for the next_to_use descriptor */
1649 rx_desc->wb.upper.length = 0;
f800326d
AD		 1650
1651 cleaned_count--;
1652 } while (cleaned_count);
7c6e0a43 1653
f990b79b
AD		 1654 i += rx_ring->count;
1655
ad435ec6
AD		 1656 if (rx_ring->next_to_use != i) {
1657 rx_ring->next_to_use = i;
1658
1659 /* update next to alloc since we have filled the ring */
1660 rx_ring->next_to_alloc = i;
1661
1662 /* Force memory writes to complete before letting h/w
1663 * know there are new descriptors to fetch. (Only
1664 * applicable for weak-ordered memory model archs,
1665 * such as IA-64).
1666 */
1667 wmb();
1668 writel(i, rx_ring->tail);
1669 }
9a799d71
AK		 1670}
1671
1d2024f6
AD		 1672static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1673 struct sk_buff *skb)
1674{
f800326d 1675 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1676
1677 /* set gso_size to avoid messing up TCP MSS */
1678 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1679 IXGBE_CB(skb)->append_cnt);
96be80ab 1680 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1681}
1682
1683static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1684 struct sk_buff *skb)
1685{
1686 /* if append_cnt is 0 then frame is not RSC */
1687 if (!IXGBE_CB(skb)->append_cnt)
1688 return;
1689
1690 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1691 rx_ring->rx_stats.rsc_flush++;
1692
1693 ixgbe_set_rsc_gso_size(rx_ring, skb);
1694
1695 /* gso_size is computed using append_cnt so always clear it last */
1696 IXGBE_CB(skb)->append_cnt = 0;
1697}
1698
8a0da21b
AD		 1699/**
1700 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1701 * @rx_ring: rx descriptor ring packet is being transacted on
1702 * @rx_desc: pointer to the EOP Rx descriptor
1703 * @skb: pointer to current skb being populated
f8212f97 1704 *
8a0da21b
AD		 1705 * This function checks the ring, descriptor, and packet information in
1706 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1707 * other fields within the skb.
f8212f97 1708 **/
8a0da21b
AD		 1709static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1710 union ixgbe_adv_rx_desc *rx_desc,
1711 struct sk_buff *skb)
f8212f97 1712{
43e95f11 1713 struct net_device *dev = rx_ring->netdev;
a9763f3c 1714 u32 flags = rx_ring->q_vector->adapter->flags;
43e95f11 1715
8a0da21b
AD		 1716 ixgbe_update_rsc_stats(rx_ring, skb);
1717
1718 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1719
8a0da21b
AD		 1720 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1721
a9763f3c
MR		 1722 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1723 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1724
f646968f 1725 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1726 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1727 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1728 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1729 }
1730
8a0da21b 1731 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1732
43e95f11 1733 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1734}
1735
8a0da21b
AD		 1736static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1737 struct sk_buff *skb)
aa80175a 1738{
3ffc1af5 1739 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1740}
43634e82 1741
f800326d
AD		 1742/**
1743 * ixgbe_is_non_eop - process handling of non-EOP buffers
1744 * @rx_ring: Rx ring being processed
1745 * @rx_desc: Rx descriptor for current buffer
1746 * @skb: Current socket buffer containing buffer in progress
1747 *
1748 * This function updates next to clean. If the buffer is an EOP buffer
1749 * this function exits returning false, otherwise it will place the
1750 * sk_buff in the next buffer to be chained and return true indicating
1751 * that this is in fact a non-EOP buffer.
1752 **/
1753static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1754 union ixgbe_adv_rx_desc *rx_desc,
1755 struct sk_buff *skb)
1756{
1757 u32 ntc = rx_ring->next_to_clean + 1;
1758
1759 /* fetch, update, and store next to clean */
1760 ntc = (ntc < rx_ring->count) ? ntc : 0;
1761 rx_ring->next_to_clean = ntc;
1762
1763 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1764
5a02cbd1
AD		 1765 /* update RSC append count if present */
1766 if (ring_is_rsc_enabled(rx_ring)) {
1767 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1768 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1769
1770 if (unlikely(rsc_enabled)) {
1771 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1772
1773 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1774 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1775
5a02cbd1
AD		 1776 /* update ntc based on RSC value */
1777 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1778 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1779 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1780 }
f800326d
AD		 1781 }
1782
5a02cbd1
AD		 1783 /* if we are the last buffer then there is nothing else to do */
1784 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1785 return false;
1786
f800326d
AD		 1787 /* place skb in next buffer to be received */
1788 rx_ring->rx_buffer_info[ntc].skb = skb;
1789 rx_ring->rx_stats.non_eop_descs++;
1790
1791 return true;
1792}
1793
19861ce2
AD		 1794/**
1795 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1796 * @rx_ring: rx descriptor ring packet is being transacted on
1797 * @skb: pointer to current skb being adjusted
1798 *
1799 * This function is an ixgbe specific version of __pskb_pull_tail. The
1800 * main difference between this version and the original function is that
1801 * this function can make several assumptions about the state of things
1802 * that allow for significant optimizations versus the standard function.
1803 * As a result we can do things like drop a frag and maintain an accurate
1804 * truesize for the skb.
1805 */
1806static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1807 struct sk_buff *skb)
1808{
1809 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1810 unsigned char *va;
1811 unsigned int pull_len;
1812
1813 /*
1814 * it is valid to use page_address instead of kmap since we are
1815 * working with pages allocated out of the lomem pool per
1816 * alloc_page(GFP_ATOMIC)
1817 */
1818 va = skb_frag_address(frag);
1819
1820 /*
1821 * we need the header to contain the greater of either ETH_HLEN or
1822 * 60 bytes if the skb->len is less than 60 for skb_pad.
1823 */
8496e338 1824 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1825
1826 /* align pull length to size of long to optimize memcpy performance */
1827 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1828
1829 /* update all of the pointers */
1830 skb_frag_size_sub(frag, pull_len);
1831 frag->page_offset += pull_len;
1832 skb->data_len -= pull_len;
1833 skb->tail += pull_len;
19861ce2
AD		 1834}
1835
42073d91
AD		 1836/**
1837 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1838 * @rx_ring: rx descriptor ring packet is being transacted on
1839 * @skb: pointer to current skb being updated
1840 *
1841 * This function provides a basic DMA sync up for the first fragment of an
1842 * skb. The reason for doing this is that the first fragment cannot be
1843 * unmapped until we have reached the end of packet descriptor for a buffer
1844 * chain.
1845 */
1846static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1847 struct sk_buff *skb)
1848{
1849 /* if the page was released unmap it, else just sync our portion */
1850 if (unlikely(IXGBE_CB(skb)->page_released)) {
f3213d93
AD		 1851 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
1852 ixgbe_rx_pg_size(rx_ring),
1853 DMA_FROM_DEVICE,
1854 IXGBE_RX_DMA_ATTR);
42073d91
AD		 1855 } else {
1856 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1857
1858 dma_sync_single_range_for_cpu(rx_ring->dev,
1859 IXGBE_CB(skb)->dma,
1860 frag->page_offset,
f215af8c 1861 skb_frag_size(frag),
42073d91
AD		 1862 DMA_FROM_DEVICE);
1863 }
42073d91
AD		 1864}
1865
f800326d
AD		 1866/**
1867 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1868 * @rx_ring: rx descriptor ring packet is being transacted on
1869 * @rx_desc: pointer to the EOP Rx descriptor
1870 * @skb: pointer to current skb being fixed
1871 *
1872 * Check for corrupted packet headers caused by senders on the local L2
1873 * embedded NIC switch not setting up their Tx Descriptors right. These
1874 * should be very rare.
1875 *
1876 * Also address the case where we are pulling data in on pages only
1877 * and as such no data is present in the skb header.
1878 *
1879 * In addition if skb is not at least 60 bytes we need to pad it so that
1880 * it is large enough to qualify as a valid Ethernet frame.
1881 *
1882 * Returns true if an error was encountered and skb was freed.
1883 **/
1884static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1885 union ixgbe_adv_rx_desc *rx_desc,
1886 struct sk_buff *skb)
1887{
f800326d 1888 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1889
1890 /* verify that the packet does not have any known errors */
1891 if (unlikely(ixgbe_test_staterr(rx_desc,
1892 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1893 !(netdev->features & NETIF_F_RXALL))) {
1894 dev_kfree_skb_any(skb);
1895 return true;
1896 }
1897
19861ce2 1898 /* place header in linear portion of buffer */
6f429223 1899 if (!skb_headlen(skb))
cf3fe7ac 1900 ixgbe_pull_tail(rx_ring, skb);
f800326d 1901
57efd44c
AD		 1902#ifdef IXGBE_FCOE
1903 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1904 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1905 return false;
1906
1907#endif
a94d9e22
AD		 1908 /* if eth_skb_pad returns an error the skb was freed */
1909 if (eth_skb_pad(skb))
1910 return true;
f800326d
AD		 1911
1912 return false;
1913}
1914
f800326d
AD		 1915/**
1916 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1917 * @rx_ring: rx descriptor ring to store buffers on
1918 * @old_buff: donor buffer to have page reused
1919 *
0549ae20 1920 * Synchronizes page for reuse by the adapter
f800326d
AD		 1921 **/
1922static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1923 struct ixgbe_rx_buffer *old_buff)
1924{
1925 struct ixgbe_rx_buffer *new_buff;
1926 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1927
1928 new_buff = &rx_ring->rx_buffer_info[nta];
1929
1930 /* update, and store next to alloc */
1931 nta++;
1932 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1933
3fd21876
AD		 1934 /* Transfer page from old buffer to new buffer.
1935 * Move each member individually to avoid possible store
1936 * forwarding stalls and unnecessary copy of skb.
1937 */
1938 new_buff->dma = old_buff->dma;
1939 new_buff->page = old_buff->page;
1940 new_buff->page_offset = old_buff->page_offset;
1941 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
f800326d
AD		 1942}
1943
18cb652a
AD		 1944static inline bool ixgbe_page_is_reserved(struct page *page)
1945{
2f064f34 1946 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1947}
1948
3fd21876 1949static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer)
af43da0d 1950{
3fd21876
AD		 1951 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1952 struct page *page = rx_buffer->page;
1b56cf49 1953
af43da0d
AD		 1954 /* avoid re-using remote pages */
1955 if (unlikely(ixgbe_page_is_reserved(page)))
1956 return false;
1957
1958#if (PAGE_SIZE < 8192)
1959 /* if we are only owner of page we can reuse it */
3fd21876 1960 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
af43da0d 1961 return false;
af43da0d 1962#else
3fd21876
AD		 1963 /* The last offset is a bit aggressive in that we assume the
1964 * worst case of FCoE being enabled and using a 3K buffer.
1965 * However this should have minimal impact as the 1K extra is
1966 * still less than one buffer in size.
1967 */
1968#define IXGBE_LAST_OFFSET \
1969 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K)
1970 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET)
af43da0d
AD		 1971 return false;
1972#endif
1973
1b56cf49
AD		 1974 /* If we have drained the page fragment pool we need to update
1975 * the pagecnt_bias and page count so that we fully restock the
1976 * number of references the driver holds.
af43da0d 1977 */
3fd21876 1978 if (unlikely(!pagecnt_bias)) {
1b56cf49
AD		 1979 page_ref_add(page, USHRT_MAX);
1980 rx_buffer->pagecnt_bias = USHRT_MAX;
1981 }
af43da0d
AD		 1982
1983 return true;
1984}
1985
f800326d
AD		 1986/**
1987 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1988 * @rx_ring: rx descriptor ring to transact packets on
1989 * @rx_buffer: buffer containing page to add
1990 * @rx_desc: descriptor containing length of buffer written by hardware
1991 * @skb: sk_buff to place the data into
1992 *
0549ae20
AD		 1993 * This function will add the data contained in rx_buffer->page to the skb.
1994 * This is done either through a direct copy if the data in the buffer is
1995 * less than the skb header size, otherwise it will just attach the page as
1996 * a frag to the skb.
1997 *
1998 * The function will then update the page offset if necessary and return
1999 * true if the buffer can be reused by the adapter.
f800326d 2000 **/
3fd21876 2001static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 2002 struct ixgbe_rx_buffer *rx_buffer,
3fd21876
AD		 2003 struct sk_buff *skb,
2004 unsigned int size)
f800326d 2005{
09816fbe 2006#if (PAGE_SIZE < 8192)
4f4542bf 2007 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
09816fbe 2008#else
2de6aa3a
AD		 2009 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
2010 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) :
2011 SKB_DATA_ALIGN(size);
09816fbe 2012#endif
3fd21876 2013 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
0549ae20 2014 rx_buffer->page_offset, size, truesize);
3fd21876
AD		 2015#if (PAGE_SIZE < 8192)
2016 rx_buffer->page_offset ^= truesize;
2017#else
2018 rx_buffer->page_offset += truesize;
2019#endif
f800326d
AD		 2020}
2021
3fd21876
AD		 2022static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring,
2023 union ixgbe_adv_rx_desc *rx_desc,
2024 struct sk_buff **skb,
2025 const unsigned int size)
18806c9e
AD		 2026{
2027 struct ixgbe_rx_buffer *rx_buffer;
18806c9e
AD		 2028
2029 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
3fd21876
AD		 2030 prefetchw(rx_buffer->page);
2031 *skb = rx_buffer->skb;
18806c9e 2032
3fd21876
AD		 2033 /* Delay unmapping of the first packet. It carries the header
2034 * information, HW may still access the header after the writeback.
2035 * Only unmap it when EOP is reached
2036 */
2037 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) {
2038 if (!*skb)
2039 goto skip_sync;
18806c9e 2040 } else {
3fd21876
AD		 2041 if (*skb)
2042 ixgbe_dma_sync_frag(rx_ring, *skb);
2043 }
18806c9e 2044
3fd21876
AD		 2045 /* we are reusing so sync this buffer for CPU use */
2046 dma_sync_single_range_for_cpu(rx_ring->dev,
2047 rx_buffer->dma,
2048 rx_buffer->page_offset,
2049 size,
2050 DMA_FROM_DEVICE);
2051skip_sync:
2052 rx_buffer->pagecnt_bias--;
18cb652a 2053
3fd21876
AD		 2054 return rx_buffer;
2055}
18806c9e 2056
3fd21876
AD		 2057static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring,
2058 struct ixgbe_rx_buffer *rx_buffer,
2059 struct sk_buff *skb)
2060{
2061 if (ixgbe_can_reuse_rx_page(rx_buffer)) {
18806c9e
AD		 2062 /* hand second half of page back to the ring */
2063 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
18806c9e 2064 } else {
1b56cf49
AD		 2065 if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2066 /* the page has been released from the ring */
2067 IXGBE_CB(skb)->page_released = true;
2068 } else {
2069 /* we are not reusing the buffer so unmap it */
2070 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2071 ixgbe_rx_pg_size(rx_ring),
2072 DMA_FROM_DEVICE,
2073 IXGBE_RX_DMA_ATTR);
2074 }
3fd21876 2075 __page_frag_cache_drain(rx_buffer->page,
1b56cf49 2076 rx_buffer->pagecnt_bias);
18806c9e
AD		 2077 }
2078
3fd21876 2079 /* clear contents of rx_buffer */
18806c9e 2080 rx_buffer->page = NULL;
3fd21876
AD		 2081 rx_buffer->skb = NULL;
2082}
2083
2084static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring,
2085 struct ixgbe_rx_buffer *rx_buffer,
2086 union ixgbe_adv_rx_desc *rx_desc,
2087 unsigned int size)
2088{
2089 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
2090#if (PAGE_SIZE < 8192)
2091 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2092#else
2de6aa3a 2093 unsigned int truesize = SKB_DATA_ALIGN(size);
3fd21876
AD		 2094#endif
2095 struct sk_buff *skb;
2096
2097 /* prefetch first cache line of first page */
2098 prefetch(va);
2099#if L1_CACHE_BYTES < 128
2100 prefetch(va + L1_CACHE_BYTES);
2101#endif
2102
2103 /* allocate a skb to store the frags */
2104 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE);
2105 if (unlikely(!skb))
2106 return NULL;
2107
2108 if (size > IXGBE_RX_HDR_SIZE) {
2109 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2110 IXGBE_CB(skb)->dma = rx_buffer->dma;
2111
2112 skb_add_rx_frag(skb, 0, rx_buffer->page,
2113 rx_buffer->page_offset,
2114 size, truesize);
2115#if (PAGE_SIZE < 8192)
2116 rx_buffer->page_offset ^= truesize;
2117#else
2118 rx_buffer->page_offset += truesize;
2119#endif
2120 } else {
2121 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
2122 rx_buffer->pagecnt_bias++;
2123 }
18806c9e
AD		 2124
2125 return skb;
f800326d
AD		 2126}
2127
6f429223
AD		 2128static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring,
2129 struct ixgbe_rx_buffer *rx_buffer,
2130 union ixgbe_adv_rx_desc *rx_desc,
2131 unsigned int size)
2132{
2133 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
2134#if (PAGE_SIZE < 8192)
2135 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2136#else
2137 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2138 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size);
2139#endif
2140 struct sk_buff *skb;
2141
2142 /* prefetch first cache line of first page */
2143 prefetch(va);
2144#if L1_CACHE_BYTES < 128
2145 prefetch(va + L1_CACHE_BYTES);
2146#endif
2147
2148 /* build an skb to around the page buffer */
2149 skb = build_skb(va - IXGBE_SKB_PAD, truesize);
2150 if (unlikely(!skb))
2151 return NULL;
2152
2153 /* update pointers within the skb to store the data */
2154 skb_reserve(skb, IXGBE_SKB_PAD);
2155 __skb_put(skb, size);
2156
2157 /* record DMA address if this is the start of a chain of buffers */
2158 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2159 IXGBE_CB(skb)->dma = rx_buffer->dma;
2160
2161 /* update buffer offset */
2162#if (PAGE_SIZE < 8192)
2163 rx_buffer->page_offset ^= truesize;
2164#else
2165 rx_buffer->page_offset += truesize;
2166#endif
2167
2168 return skb;
2169}
2170
f800326d
AD		 2171/**
2172 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2173 * @q_vector: structure containing interrupt and ring information
2174 * @rx_ring: rx descriptor ring to transact packets on
2175 * @budget: Total limit on number of packets to process
2176 *
2177 * This function provides a "bounce buffer" approach to Rx interrupt
2178 * processing. The advantage to this is that on systems that have
2179 * expensive overhead for IOMMU access this provides a means of avoiding
2180 * it by maintaining the mapping of the page to the syste.
2181 *
5a85e737 2182 * Returns amount of work completed
f800326d 2183 **/
5a85e737 2184static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2185 struct ixgbe_ring *rx_ring,
f4de00ed 2186 const int budget)
9a799d71 2187{
d2f4fbe2 2188 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2189#ifdef IXGBE_FCOE
f800326d 2190 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2191 int ddp_bytes;
2192 unsigned int mss = 0;
3d8fd385 2193#endif /* IXGBE_FCOE */
f800326d 2194 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2195
fdabfc8a 2196 while (likely(total_rx_packets < budget)) {
f800326d 2197 union ixgbe_adv_rx_desc *rx_desc;
3fd21876 2198 struct ixgbe_rx_buffer *rx_buffer;
f800326d 2199 struct sk_buff *skb;
3fd21876 2200 unsigned int size;
f800326d
AD		 2201
2202 /* return some buffers to hardware, one at a time is too slow */
2203 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2204 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2205 cleaned_count = 0;
2206 }
2207
18806c9e 2208 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
3fd21876
AD		 2209 size = le16_to_cpu(rx_desc->wb.upper.length);
2210 if (!size)
f800326d 2211 break;
9a799d71 2212
124b74c1 2213 /* This memory barrier is needed to keep us from reading
f800326d 2214 * any other fields out of the rx_desc until we know the
124b74c1 2215 * descriptor has been written back
f800326d 2216 */
124b74c1 2217 dma_rmb();
9a799d71 2218
3fd21876
AD		 2219 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size);
2220
18806c9e 2221 /* retrieve a buffer from the ring */
3fd21876
AD		 2222 if (skb)
2223 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size);
6f429223
AD		 2224 else if (ring_uses_build_skb(rx_ring))
2225 skb = ixgbe_build_skb(rx_ring, rx_buffer,
2226 rx_desc, size);
3fd21876
AD		 2227 else
2228 skb = ixgbe_construct_skb(rx_ring, rx_buffer,
2229 rx_desc, size);
f800326d 2230
18806c9e 2231 /* exit if we failed to retrieve a buffer */
3fd21876
AD		 2232 if (!skb) {
2233 rx_ring->rx_stats.alloc_rx_buff_failed++;
2234 rx_buffer->pagecnt_bias++;
18806c9e 2235 break;
3fd21876 2236 }
9a799d71 2237
3fd21876 2238 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb);
9a799d71 2239 cleaned_count++;
f8212f97 2240
f800326d
AD		 2241 /* place incomplete frames back on ring for completion */
2242 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2243 continue;
c267fc16 2244
f800326d
AD		 2245 /* verify the packet layout is correct */
2246 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2247 continue;
9a799d71 2248
d2f4fbe2
AV		 2249 /* probably a little skewed due to removing CRC */
2250 total_rx_bytes += skb->len;
d2f4fbe2 2251
8a0da21b
AD		 2252 /* populate checksum, timestamp, VLAN, and protocol */
2253 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2254
332d4a7d
YZ		 2255#ifdef IXGBE_FCOE
2256 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2257 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2258 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2259 /* include DDPed FCoE data */
2260 if (ddp_bytes > 0) {
2261 if (!mss) {
2262 mss = rx_ring->netdev->mtu -
2263 sizeof(struct fcoe_hdr) -
2264 sizeof(struct fc_frame_header) -
2265 sizeof(struct fcoe_crc_eof);
2266 if (mss > 512)
2267 mss &= ~511;
2268 }
2269 total_rx_bytes += ddp_bytes;
2270 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2271 mss);
2272 }
63d635b2
AD		 2273 if (!ddp_bytes) {
2274 dev_kfree_skb_any(skb);
f800326d 2275 continue;
63d635b2 2276 }
3d8fd385 2277 }
f800326d 2278
332d4a7d 2279#endif /* IXGBE_FCOE */
8a0da21b 2280 ixgbe_rx_skb(q_vector, skb);
9a799d71 2281
f800326d 2282 /* update budget accounting */
f4de00ed 2283 total_rx_packets++;
fdabfc8a 2284 }
9a799d71 2285
c267fc16
AD		 2286 u64_stats_update_begin(&rx_ring->syncp);
2287 rx_ring->stats.packets += total_rx_packets;
2288 rx_ring->stats.bytes += total_rx_bytes;
2289 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2290 q_vector->rx.total_packets += total_rx_packets;
2291 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2292
5a85e737 2293 return total_rx_packets;
9a799d71
AK		 2294}
2295
9a799d71
AK		 2296/**
2297 * ixgbe_configure_msix - Configure MSI-X hardware
2298 * @adapter: board private structure
2299 *
2300 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2301 * interrupts.
2302 **/
2303static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2304{
021230d4 2305 struct ixgbe_q_vector *q_vector;
49c7ffbe 2306 int v_idx;
021230d4 2307 u32 mask;
9a799d71 2308
8e34d1aa
AD		 2309 /* Populate MSIX to EITR Select */
2310 if (adapter->num_vfs > 32) {
b4f47a48 2311 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
8e34d1aa
AD		 2312 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2313 }
2314
4df10466
JB		 2315 /*
2316 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2317 * corresponding register.
2318 */
49c7ffbe 2319 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2320 struct ixgbe_ring *ring;
7a921c93 2321 q_vector = adapter->q_vector[v_idx];
021230d4 2322
a557928e 2323 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2324 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2325
a557928e 2326 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2327 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2328
fe49f04a 2329 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2330 }
2331
bd508178
AD		 2332 switch (adapter->hw.mac.type) {
2333 case ixgbe_mac_82598EB:
e8e26350 2334 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2335 v_idx);
bd508178
AD		 2336 break;
2337 case ixgbe_mac_82599EB:
b93a2226 2338 case ixgbe_mac_X540:
9a75a1ac
DS		 2339 case ixgbe_mac_X550:
2340 case ixgbe_mac_X550EM_x:
49425dfc 2341 case ixgbe_mac_x550em_a:
e8e26350 2342 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2343 break;
bd508178
AD		 2344 default:
2345 break;
2346 }
021230d4
AV		 2347 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2348
41fb9248 2349 /* set up to autoclear timer, and the vectors */
021230d4 2350 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2351 mask &= ~(IXGBE_EIMS_OTHER |
2352 IXGBE_EIMS_MAILBOX |
2353 IXGBE_EIMS_LSC);
2354
021230d4 2355 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2356}
2357
f494e8fa
AV		 2358enum latency_range {
2359 lowest_latency = 0,
2360 low_latency = 1,
2361 bulk_latency = 2,
2362 latency_invalid = 255
2363};
2364
2365/**
2366 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2367 * @q_vector: structure containing interrupt and ring information
2368 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2369 *
2370 * Stores a new ITR value based on packets and byte
2371 * counts during the last interrupt. The advantage of per interrupt
2372 * computation is faster updates and more accurate ITR for the current
2373 * traffic pattern. Constants in this function were computed
2374 * based on theoretical maximum wire speed and thresholds were set based
2375 * on testing data as well as attempting to minimize response time
2376 * while increasing bulk throughput.
2377 * this functionality is controlled by the InterruptThrottleRate module
2378 * parameter (see ixgbe_param.c)
2379 **/
bd198058
AD		 2380static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2381 struct ixgbe_ring_container *ring_container)
f494e8fa 2382{
bd198058
AD		 2383 int bytes = ring_container->total_bytes;
2384 int packets = ring_container->total_packets;
2385 u32 timepassed_us;
621bd70e 2386 u64 bytes_perint;
bd198058 2387 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2388
2389 if (packets == 0)
bd198058 2390 return;
f494e8fa
AV		 2391
2392 /* simple throttlerate management
621bd70e
AD		 2393 * 0-10MB/s lowest (100000 ints/s)
2394 * 10-20MB/s low (20000 ints/s)
8ac34f10 2395 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2396 */
2397 /* what was last interrupt timeslice? */
d5bf4f67 2398 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2399 if (timepassed_us == 0)
2400 return;
2401
f494e8fa
AV		 2402 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2403
2404 switch (itr_setting) {
2405 case lowest_latency:
621bd70e 2406 if (bytes_perint > 10)
bd198058 2407 itr_setting = low_latency;
f494e8fa
AV		 2408 break;
2409 case low_latency:
621bd70e 2410 if (bytes_perint > 20)
bd198058 2411 itr_setting = bulk_latency;
621bd70e 2412 else if (bytes_perint <= 10)
bd198058 2413 itr_setting = lowest_latency;
f494e8fa
AV		 2414 break;
2415 case bulk_latency:
621bd70e 2416 if (bytes_perint <= 20)
bd198058 2417 itr_setting = low_latency;
f494e8fa
AV		 2418 break;
2419 }
2420
bd198058
AD		 2421 /* clear work counters since we have the values we need */
2422 ring_container->total_bytes = 0;
2423 ring_container->total_packets = 0;
2424
2425 /* write updated itr to ring container */
2426 ring_container->itr = itr_setting;
f494e8fa
AV		 2427}
2428
509ee935
JB		 2429/**
2430 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2431 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2432 *
2433 * This function is made to be called by ethtool and by the driver
2434 * when it needs to update EITR registers at runtime. Hardware
2435 * specific quirks/differences are taken care of here.
2436 */
fe49f04a 2437void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2438{
fe49f04a 2439 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2440 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2441 int v_idx = q_vector->v_idx;
5d967eb7 2442 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2443
bd508178
AD		 2444 switch (adapter->hw.mac.type) {
2445 case ixgbe_mac_82598EB:
509ee935
JB		 2446 /* must write high and low 16 bits to reset counter */
2447 itr_reg |= (itr_reg << 16);
bd508178
AD		 2448 break;
2449 case ixgbe_mac_82599EB:
b93a2226 2450 case ixgbe_mac_X540:
9a75a1ac
DS		 2451 case ixgbe_mac_X550:
2452 case ixgbe_mac_X550EM_x:
49425dfc 2453 case ixgbe_mac_x550em_a:
509ee935
JB		 2454 /*
2455 * set the WDIS bit to not clear the timer bits and cause an
2456 * immediate assertion of the interrupt
2457 */
2458 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2459 break;
2460 default:
2461 break;
509ee935
JB		 2462 }
2463 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2464}
2465
bd198058 2466static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2467{
d5bf4f67 2468 u32 new_itr = q_vector->itr;
bd198058 2469 u8 current_itr;
f494e8fa 2470
bd198058
AD		 2471 ixgbe_update_itr(q_vector, &q_vector->tx);
2472 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2473
08c8833b 2474 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2475
2476 switch (current_itr) {
2477 /* counts and packets in update_itr are dependent on these numbers */
2478 case lowest_latency:
d5bf4f67 2479 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2480 break;
2481 case low_latency:
d5bf4f67 2482 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2483 break;
2484 case bulk_latency:
8ac34f10 2485 new_itr = IXGBE_12K_ITR;
f494e8fa 2486 break;
bd198058
AD		 2487 default:
2488 break;
f494e8fa
AV		 2489 }
2490
d5bf4f67 2491 if (new_itr != q_vector->itr) {
fe49f04a 2492 /* do an exponential smoothing */
d5bf4f67
ET		 2493 new_itr = (10 * new_itr * q_vector->itr) /
2494 ((9 * new_itr) + q_vector->itr);
509ee935 2495
bd198058 2496 /* save the algorithm value here */
5d967eb7 2497 q_vector->itr = new_itr;
fe49f04a
AD		 2498
2499 ixgbe_write_eitr(q_vector);
f494e8fa 2500 }
f494e8fa
AV		 2501}
2502
119fc60a 2503/**
de88eeeb 2504 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2505 * @adapter: pointer to adapter
119fc60a 2506 **/
f0f9778d 2507static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2508{
119fc60a
MC		 2509 struct ixgbe_hw *hw = &adapter->hw;
2510 u32 eicr = adapter->interrupt_event;
b3eb4e18 2511 s32 rc;
119fc60a 2512
f0f9778d 2513 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2514 return;
2515
f0f9778d
AD		 2516 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2517 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2518 return;
2519
2520 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2521
7ca647bd 2522 switch (hw->device_id) {
f0f9778d
AD		 2523 case IXGBE_DEV_ID_82599_T3_LOM:
2524 /*
2525 * Since the warning interrupt is for both ports
2526 * we don't have to check if:
2527 * - This interrupt wasn't for our port.
2528 * - We may have missed the interrupt so always have to
2529 * check if we got a LSC
2530 */
9a900eca 2531 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2532 !(eicr & IXGBE_EICR_LSC))
2533 return;
2534
2535 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2536 u32 speed;
f0f9778d 2537 bool link_up = false;
7ca647bd 2538
3d292265 2539 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2540
f0f9778d
AD		 2541 if (link_up)
2542 return;
2543 }
2544
2545 /* Check if this is not due to overtemp */
2546 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2547 return;
2548
2549 break;
b3eb4e18
MR		 2550 case IXGBE_DEV_ID_X550EM_A_1G_T:
2551 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2552 rc = hw->phy.ops.check_overtemp(hw);
2553 if (rc != IXGBE_ERR_OVERTEMP)
2554 return;
2555 break;
7ca647bd 2556 default:
597f22d6
DS		 2557 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2558 return;
9a900eca 2559 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2560 return;
7ca647bd 2561 break;
119fc60a 2562 }
f44e751b 2563 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2564
2565 adapter->interrupt_event = 0;
119fc60a
MC		 2566}
2567
0befdb3e
JB		 2568static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2569{
2570 struct ixgbe_hw *hw = &adapter->hw;
2571
2572 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2573 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2574 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2575 /* write to clear the interrupt */
9a900eca 2576 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2577 }
2578}
cf8280ee 2579
4f51bf70
JK		 2580static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2581{
9a900eca
DS		 2582 struct ixgbe_hw *hw = &adapter->hw;
2583
4f51bf70
JK		 2584 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2585 return;
2586
2587 switch (adapter->hw.mac.type) {
2588 case ixgbe_mac_82599EB:
2589 /*
2590 * Need to check link state so complete overtemp check
2591 * on service task
2592 */
9a900eca
DS		 2593 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2594 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2595 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2596 adapter->interrupt_event = eicr;
2597 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2598 ixgbe_service_event_schedule(adapter);
2599 return;
2600 }
2601 return;
b3eb4e18
MR		 2602 case ixgbe_mac_x550em_a:
2603 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) {
2604 adapter->interrupt_event = eicr;
2605 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2606 ixgbe_service_event_schedule(adapter);
2607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
2608 IXGBE_EICR_GPI_SDP0_X550EM_a);
2609 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR,
2610 IXGBE_EICR_GPI_SDP0_X550EM_a);
2611 }
2612 return;
2613 case ixgbe_mac_X550:
4f51bf70
JK		 2614 case ixgbe_mac_X540:
2615 if (!(eicr & IXGBE_EICR_TS))
2616 return;
2617 break;
2618 default:
2619 return;
2620 }
2621
f44e751b 2622 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2623}
2624
45788d2a
DS		 2625static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2626{
2627 switch (hw->mac.type) {
2628 case ixgbe_mac_82598EB:
2629 if (hw->phy.type == ixgbe_phy_nl)
2630 return true;
2631 return false;
2632 case ixgbe_mac_82599EB:
2633 case ixgbe_mac_X550EM_x:
49425dfc 2634 case ixgbe_mac_x550em_a:
45788d2a
DS		 2635 switch (hw->mac.ops.get_media_type(hw)) {
2636 case ixgbe_media_type_fiber:
2637 case ixgbe_media_type_fiber_qsfp:
2638 return true;
2639 default:
2640 return false;
2641 }
2642 default:
2643 return false;
2644 }
2645}
2646
e8e26350
PW		 2647static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2648{
2649 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2650 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2651
4ccc650c
DS		 2652 if (!ixgbe_is_sfp(hw))
2653 return;
2654
2655 /* Later MAC's use different SDP */
2656 if (hw->mac.type >= ixgbe_mac_X540)
2657 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2658
2659 if (eicr & eicr_mask) {
73c4b7cd 2660 /* Clear the interrupt */
4ccc650c 2661 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2662 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2663 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2664 adapter->sfp_poll_time = 0;
7086400d
AD		 2665 ixgbe_service_event_schedule(adapter);
2666 }
73c4b7cd
AD		 2667 }
2668
4ccc650c
DS		 2669 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2670 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2671 /* Clear the interrupt */
9a900eca 2672 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2673 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2674 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2675 ixgbe_service_event_schedule(adapter);
2676 }
e8e26350
PW		 2677 }
2678}
2679
cf8280ee
JB		 2680static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2681{
2682 struct ixgbe_hw *hw = &adapter->hw;
2683
2684 adapter->lsc_int++;
2685 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2686 adapter->link_check_timeout = jiffies;
2687 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2688 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2689 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2690 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2691 }
2692}
2693
fe49f04a
AD		 2694static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2695 u64 qmask)
2696{
2697 u32 mask;
bd508178 2698 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2699
bd508178
AD		 2700 switch (hw->mac.type) {
2701 case ixgbe_mac_82598EB:
fe49f04a 2702 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2703 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2704 break;
2705 case ixgbe_mac_82599EB:
b93a2226 2706 case ixgbe_mac_X540:
9a75a1ac
DS		 2707 case ixgbe_mac_X550:
2708 case ixgbe_mac_X550EM_x:
49425dfc 2709 case ixgbe_mac_x550em_a:
fe49f04a 2710 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2711 if (mask)
2712 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2713 mask = (qmask >> 32);
bd508178
AD		 2714 if (mask)
2715 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2716 break;
2717 default:
2718 break;
fe49f04a
AD		 2719 }
2720 /* skip the flush */
2721}
2722
2723static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2724 u64 qmask)
fe49f04a
AD		 2725{
2726 u32 mask;
bd508178 2727 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2728
bd508178
AD		 2729 switch (hw->mac.type) {
2730 case ixgbe_mac_82598EB:
fe49f04a 2731 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2732 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2733 break;
2734 case ixgbe_mac_82599EB:
b93a2226 2735 case ixgbe_mac_X540:
9a75a1ac
DS		 2736 case ixgbe_mac_X550:
2737 case ixgbe_mac_X550EM_x:
49425dfc 2738 case ixgbe_mac_x550em_a:
fe49f04a 2739 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2740 if (mask)
2741 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2742 mask = (qmask >> 32);
bd508178
AD		 2743 if (mask)
2744 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2745 break;
2746 default:
2747 break;
fe49f04a
AD		 2748 }
2749 /* skip the flush */
2750}
2751
021230d4 2752/**
2c4af694
AD		 2753 * ixgbe_irq_enable - Enable default interrupt generation settings
2754 * @adapter: board private structure
021230d4 2755 **/
2c4af694
AD		 2756static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2757 bool flush)
9a799d71 2758{
9a900eca 2759 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2760 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2761
2c4af694
AD		 2762 /* don't reenable LSC while waiting for link */
2763 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2764 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2765
2c4af694 2766 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2767 switch (adapter->hw.mac.type) {
2768 case ixgbe_mac_82599EB:
9a900eca 2769 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2770 break;
2771 case ixgbe_mac_X540:
9a75a1ac
DS		 2772 case ixgbe_mac_X550:
2773 case ixgbe_mac_X550EM_x:
49425dfc 2774 case ixgbe_mac_x550em_a:
4f51bf70
JK		 2775 mask |= IXGBE_EIMS_TS;
2776 break;
2777 default:
2778 break;
2779 }
2c4af694 2780 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2781 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2782 switch (adapter->hw.mac.type) {
2783 case ixgbe_mac_82599EB:
9a900eca
DS		 2784 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2785 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2786 /* fall through */
858bc081 2787 case ixgbe_mac_X540:
9a75a1ac
DS		 2788 case ixgbe_mac_X550:
2789 case ixgbe_mac_X550EM_x:
49425dfc
MR		 2790 case ixgbe_mac_x550em_a:
2791 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
2d40cd17 2792 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
49425dfc 2793 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
cbd45ec7 2794 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2795 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2796 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2797 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2798 mask |= IXGBE_EIMS_MAILBOX;
2799 break;
2800 default:
2801 break;
9a799d71 2802 }
db0677fa 2803
2c4af694
AD		 2804 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2805 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2806 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2807
2c4af694
AD		 2808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2809 if (queues)
2810 ixgbe_irq_enable_queues(adapter, ~0);
2811 if (flush)
2812 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2813}
2814
2c4af694 2815static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2816{
a65151ba 2817 struct ixgbe_adapter *adapter = data;
9a799d71 2818 struct ixgbe_hw *hw = &adapter->hw;
54037505 2819 u32 eicr;
91281fd3 2820
54037505
DS		 2821 /*
2822 * Workaround for Silicon errata. Use clear-by-write instead
2823 * of clear-by-read. Reading with EICS will return the
2824 * interrupt causes without clearing, which later be done
2825 * with the write to EICR.
2826 */
2827 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2828
2829 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2830 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2831 * the bits are high when ixgbe_msix_other is called. There is a race
2832 * condition otherwise which results in possible performance loss
2833 * especially if the ixgbe_msix_other interrupt is triggering
2834 * consistently (as it would when PPS is turned on for the X540 device)
2835 */
2836 eicr &= 0xFFFF0000;
2837
54037505 2838 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2839
cf8280ee
JB		 2840 if (eicr & IXGBE_EICR_LSC)
2841 ixgbe_check_lsc(adapter);
f0848276 2842
1cdd1ec8
GR		 2843 if (eicr & IXGBE_EICR_MAILBOX)
2844 ixgbe_msg_task(adapter);
efe3d3c8 2845
bd508178
AD		 2846 switch (hw->mac.type) {
2847 case ixgbe_mac_82599EB:
b93a2226 2848 case ixgbe_mac_X540:
9a75a1ac
DS		 2849 case ixgbe_mac_X550:
2850 case ixgbe_mac_X550EM_x:
49425dfc 2851 case ixgbe_mac_x550em_a:
597f22d6
DS		 2852 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2853 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2854 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2855 ixgbe_service_event_schedule(adapter);
2856 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2857 IXGBE_EICR_GPI_SDP0_X540);
2858 }
d773ce2d
DS		 2859 if (eicr & IXGBE_EICR_ECC) {
2860 e_info(link, "Received ECC Err, initiating reset\n");
57ca2a4f 2861 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
d773ce2d
DS		 2862 ixgbe_service_event_schedule(adapter);
2863 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2864 }
c4cf55e5
PWJ		 2865 /* Handle Flow Director Full threshold interrupt */
2866 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2867 int reinit_count = 0;
c4cf55e5 2868 int i;
c4cf55e5 2869 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2870 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2871 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2872 &ring->state))
2873 reinit_count++;
2874 }
2875 if (reinit_count) {
2876 /* no more flow director interrupts until after init */
2877 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2878 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2879 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2880 }
2881 }
f0f9778d 2882 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2883 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2884 break;
2885 default:
2886 break;
c4cf55e5 2887 }
f0848276 2888
bd508178 2889 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2890
db0677fa 2891 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2892 ixgbe_ptp_check_pps_event(adapter);
efe3d3c8 2893
7086400d 2894 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2895 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2896 ixgbe_irq_enable(adapter, false, false);
f0848276 2897
9a799d71 2898 return IRQ_HANDLED;
f0848276 2899}
91281fd3 2900
4ff7fb12 2901static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2902{
021230d4 2903 struct ixgbe_q_vector *q_vector = data;
91281fd3 2904
9b471446 2905 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2906
4ff7fb12 2907 if (q_vector->rx.ring || q_vector->tx.ring)
ef2662b2 2908 napi_schedule_irqoff(&q_vector->napi);
91281fd3 2909
9a799d71 2910 return IRQ_HANDLED;
91281fd3
AD		 2911}
2912
eb01b975
AD		 2913/**
2914 * ixgbe_poll - NAPI Rx polling callback
2915 * @napi: structure for representing this polling device
2916 * @budget: how many packets driver is allowed to clean
2917 *
2918 * This function is used for legacy and MSI, NAPI mode
2919 **/
8af3c33f 2920int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2921{
2922 struct ixgbe_q_vector *q_vector =
2923 container_of(napi, struct ixgbe_q_vector, napi);
2924 struct ixgbe_adapter *adapter = q_vector->adapter;
2925 struct ixgbe_ring *ring;
32b3e08f 2926 int per_ring_budget, work_done = 0;
eb01b975
AD		 2927 bool clean_complete = true;
2928
2929#ifdef CONFIG_IXGBE_DCA
2930 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2931 ixgbe_update_dca(q_vector);
2932#endif
2933
8220bbc1
AD		 2934 ixgbe_for_each_ring(ring, q_vector->tx) {
2935 if (!ixgbe_clean_tx_irq(q_vector, ring, budget))
2936 clean_complete = false;
2937 }
eb01b975 2938
3ffc1af5
ED		 2939 /* Exit if we are called by netpoll */
2940 if (budget <= 0)
5a85e737
ET		 2941 return budget;
2942
eb01b975
AD		 2943 /* attempt to distribute budget to each queue fairly, but don't allow
2944 * the budget to go below 1 because we'll exit polling */
2945 if (q_vector->rx.count > 1)
2946 per_ring_budget = max(budget/q_vector->rx.count, 1);
2947 else
2948 per_ring_budget = budget;
2949
32b3e08f
JB		 2950 ixgbe_for_each_ring(ring, q_vector->rx) {
2951 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2952 per_ring_budget);
2953
2954 work_done += cleaned;
8220bbc1
AD		 2955 if (cleaned >= per_ring_budget)
2956 clean_complete = false;
32b3e08f 2957 }
eb01b975
AD		 2958
2959 /* If all work not completed, return budget and keep polling */
2960 if (!clean_complete)
2961 return budget;
2962
2963 /* all work done, exit the polling mode */
32b3e08f 2964 napi_complete_done(napi, work_done);
eb01b975
AD		 2965 if (adapter->rx_itr_setting & 1)
2966 ixgbe_set_itr(q_vector);
2967 if (!test_bit(__IXGBE_DOWN, &adapter->state))
b4f47a48 2968 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx));
eb01b975 2969
4b732cd4 2970 return min(work_done, budget - 1);
eb01b975
AD		 2971}
2972
021230d4
AV		 2973/**
2974 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2975 * @adapter: board private structure
2976 *
2977 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2978 * interrupts from the kernel.
2979 **/
2980static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2981{
2982 struct net_device *netdev = adapter->netdev;
207867f5 2983 int vector, err;
e8e9f696 2984 int ri = 0, ti = 0;
021230d4 2985
49c7ffbe 2986 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2987 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2988 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2989
4ff7fb12 2990 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2991 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2992 "%s-%s-%d", netdev->name, "TxRx", ri++);
2993 ti++;
2994 } else if (q_vector->rx.ring) {
9fe93afd 2995 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2996 "%s-%s-%d", netdev->name, "rx", ri++);
2997 } else if (q_vector->tx.ring) {
9fe93afd 2998 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2999 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 3000 } else {
3001 /* skip this unused q_vector */
3002 continue;
32aa77a4 3003 }
207867f5
AD		 3004 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
3005 q_vector->name, q_vector);
9a799d71 3006 if (err) {
396e799c 3007 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 3008 "Error: %d\n", err);
021230d4 3009 goto free_queue_irqs;
9a799d71 3010 }
207867f5
AD		 3011 /* If Flow Director is enabled, set interrupt affinity */
3012 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3013 /* assign the mask for this irq */
3014 irq_set_affinity_hint(entry->vector,
de88eeeb 3015 &q_vector->affinity_mask);
207867f5 3016 }
9a799d71
AK		 3017 }
3018
021230d4 3019 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 3020 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 3021 if (err) {
de88eeeb 3022 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 3023 goto free_queue_irqs;
9a799d71
AK		 3024 }
3025
9a799d71
AK		 3026 return 0;
3027
021230d4 3028free_queue_irqs:
207867f5
AD		 3029 while (vector) {
3030 vector--;
3031 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
3032 NULL);
3033 free_irq(adapter->msix_entries[vector].vector,
3034 adapter->q_vector[vector]);
3035 }
021230d4
AV		 3036 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3037 pci_disable_msix(adapter->pdev);
9a799d71
AK		 3038 kfree(adapter->msix_entries);
3039 adapter->msix_entries = NULL;
9a799d71
AK		 3040 return err;
3041}
3042
3043/**
021230d4 3044 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 3045 * @irq: interrupt number
3046 * @data: pointer to a network interface device structure
9a799d71
AK		 3047 **/
3048static irqreturn_t ixgbe_intr(int irq, void *data)
3049{
a65151ba 3050 struct ixgbe_adapter *adapter = data;
9a799d71 3051 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 3052 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 3053 u32 eicr;
3054
54037505 3055 /*
24ddd967 3056 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 3057 * before the read of EICR.
3058 */
3059 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
3060
021230d4 3061 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 3062 * therefore no explicit interrupt disable is necessary */
021230d4 3063 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 3064 if (!eicr) {
6af3b9eb
ET		 3065 /*
3066 * shared interrupt alert!
f47cf66e 3067 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 3068 * have disabled interrupts due to EIAM
3069 * finish the workaround of silicon errata on 82598. Unmask
3070 * the interrupt that we masked before the EICR read.
3071 */
3072 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3073 ixgbe_irq_enable(adapter, true, true);
9a799d71 3074 return IRQ_NONE; /* Not our interrupt */
f47cf66e 3075 }
9a799d71 3076
cf8280ee
JB		 3077 if (eicr & IXGBE_EICR_LSC)
3078 ixgbe_check_lsc(adapter);
021230d4 3079
bd508178
AD		 3080 switch (hw->mac.type) {
3081 case ixgbe_mac_82599EB:
e8e26350 3082 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 3083 /* Fall through */
3084 case ixgbe_mac_X540:
9a75a1ac
DS		 3085 case ixgbe_mac_X550:
3086 case ixgbe_mac_X550EM_x:
49425dfc 3087 case ixgbe_mac_x550em_a:
d773ce2d
DS		 3088 if (eicr & IXGBE_EICR_ECC) {
3089 e_info(link, "Received ECC Err, initiating reset\n");
57ca2a4f 3090 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
d773ce2d
DS		 3091 ixgbe_service_event_schedule(adapter);
3092 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3093 }
4f51bf70 3094 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 3095 break;
3096 default:
3097 break;
3098 }
e8e26350 3099
0befdb3e 3100 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 3101 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 3102 ixgbe_ptp_check_pps_event(adapter);
0befdb3e 3103
b9f6ed2b 3104 /* would disable interrupts here but EIAM disabled it */
ef2662b2 3105 napi_schedule_irqoff(&q_vector->napi);
9a799d71 3106
6af3b9eb
ET		 3107 /*
3108 * re-enable link(maybe) and non-queue interrupts, no flush.
3109 * ixgbe_poll will re-enable the queue interrupts
3110 */
6af3b9eb
ET		 3111 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3112 ixgbe_irq_enable(adapter, false, false);
3113
9a799d71
AK		 3114 return IRQ_HANDLED;
3115}
3116
3117/**
3118 * ixgbe_request_irq - initialize interrupts
3119 * @adapter: board private structure
3120 *
3121 * Attempts to configure interrupts using the best available
3122 * capabilities of the hardware and kernel.
3123 **/
021230d4 3124static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 3125{
3126 struct net_device *netdev = adapter->netdev;
021230d4 3127 int err;
9a799d71 3128
4cc6df29 3129 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 3130 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 3131 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 3132 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 3133 netdev->name, adapter);
4cc6df29 3134 else
a0607fd3 3135 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 3136 netdev->name, adapter);
9a799d71 3137
de88eeeb 3138 if (err)
396e799c 3139 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 3140
9a799d71
AK		 3141 return err;
3142}
3143
3144static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3145{
49c7ffbe 3146 int vector;
9a799d71 3147
49c7ffbe
AD		 3148 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3149 free_irq(adapter->pdev->irq, adapter);
3150 return;
3151 }
4cc6df29 3152
1fa71252
MR		 3153 if (!adapter->msix_entries)
3154 return;
3155
49c7ffbe
AD		 3156 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3157 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3158 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3159
49c7ffbe
AD		 3160 /* free only the irqs that were actually requested */
3161 if (!q_vector->rx.ring && !q_vector->tx.ring)
3162 continue;
207867f5 3163
49c7ffbe
AD		 3164 /* clear the affinity_mask in the IRQ descriptor */
3165 irq_set_affinity_hint(entry->vector, NULL);
3166
3167 free_irq(entry->vector, q_vector);
9a799d71 3168 }
49c7ffbe 3169
90c6f877 3170 free_irq(adapter->msix_entries[vector].vector, adapter);
9a799d71
AK		 3171}
3172
22d5a71b
JB		 3173/**
3174 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3175 * @adapter: board private structure
3176 **/
3177static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3178{
bd508178
AD		 3179 switch (adapter->hw.mac.type) {
3180 case ixgbe_mac_82598EB:
835462fc 3181 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3182 break;
3183 case ixgbe_mac_82599EB:
b93a2226 3184 case ixgbe_mac_X540:
9a75a1ac
DS		 3185 case ixgbe_mac_X550:
3186 case ixgbe_mac_X550EM_x:
49425dfc 3187 case ixgbe_mac_x550em_a:
835462fc
NS		 3188 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3189 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3190 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3191 break;
3192 default:
3193 break;
22d5a71b
JB		 3194 }
3195 IXGBE_WRITE_FLUSH(&adapter->hw);
3196 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3197 int vector;
3198
3199 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3200 synchronize_irq(adapter->msix_entries[vector].vector);
3201
3202 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3203 } else {
3204 synchronize_irq(adapter->pdev->irq);
3205 }
3206}
3207
9a799d71
AK		 3208/**
3209 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3210 *
3211 **/
3212static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3213{
d5bf4f67 3214 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3215
d5bf4f67 3216 ixgbe_write_eitr(q_vector);
9a799d71 3217
e8e26350
PW		 3218 ixgbe_set_ivar(adapter, 0, 0, 0);
3219 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3220
396e799c 3221 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3222}
3223
43e69bf0
AD		 3224/**
3225 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3226 * @adapter: board private structure
3227 * @ring: structure containing ring specific data
3228 *
3229 * Configure the Tx descriptor ring after a reset.
3230 **/
84418e3b
AD		 3231void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3232 struct ixgbe_ring *ring)
43e69bf0
AD		 3233{
3234 struct ixgbe_hw *hw = &adapter->hw;
3235 u64 tdba = ring->dma;
2f1860b8 3236 int wait_loop = 10;
b88c6de2 3237 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3238 u8 reg_idx = ring->reg_idx;
43e69bf0 3239
2f1860b8 3240 /* disable queue to avoid issues while updating state */
b88c6de2 3241 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3242 IXGBE_WRITE_FLUSH(hw);
3243
43e69bf0 3244 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3245 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3246 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3247 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3248 ring->count * sizeof(union ixgbe_adv_tx_desc));
3249 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3250 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3251 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3252
b88c6de2
AD		 3253 /*
3254 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3255 * higher than 1 when:
3256 * - ITR is 0 as it could cause false TX hangs
3257 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3258 *
3259 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3260 * to or less than the number of on chip descriptors, which is
3261 * currently 40.
3262 */
67da097e 3263 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b4f47a48 3264 txdctl |= 1u << 16; /* WTHRESH = 1 */
b88c6de2 3265 else
b4f47a48 3266 txdctl |= 8u << 16; /* WTHRESH = 8 */
b88c6de2 3267
e954b374
AD		 3268 /*
3269 * Setting PTHRESH to 32 both improves performance
3270 * and avoids a TX hang with DFP enabled
3271 */
b4f47a48 3272 txdctl |= (1u << 8) | /* HTHRESH = 1 */
b88c6de2 3273 32; /* PTHRESH = 32 */
2f1860b8
AD		 3274
3275 /* reinitialize flowdirector state */
39cb681b 3276 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3277 ring->atr_sample_rate = adapter->atr_sample_rate;
3278 ring->atr_count = 0;
3279 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3280 } else {
3281 ring->atr_sample_rate = 0;
3282 }
2f1860b8 3283
fd786b7b
AD		 3284 /* initialize XPS */
3285 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3286 struct ixgbe_q_vector *q_vector = ring->q_vector;
3287
3288 if (q_vector)
2a47fa45 3289 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3290 &q_vector->affinity_mask,
3291 ring->queue_index);
3292 }
3293
c84d324c
JF		 3294 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3295
2f1860b8 3296 /* enable queue */
2f1860b8
AD		 3297 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3298
3299 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3300 if (hw->mac.type == ixgbe_mac_82598EB &&
3301 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3302 return;
3303
3304 /* poll to verify queue is enabled */
3305 do {
032b4325 3306 usleep_range(1000, 2000);
2f1860b8
AD		 3307 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3308 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3309 if (!wait_loop)
a55defd8 3310 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3311}
3312
120ff942
AD		 3313static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3314{
3315 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3316 u32 rttdcs, mtqc;
8b1c0b24 3317 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3318
3319 if (hw->mac.type == ixgbe_mac_82598EB)
3320 return;
3321
3322 /* disable the arbiter while setting MTQC */
3323 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3324 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3325 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3326
3327 /* set transmit pool layout */
671c0adb
AD		 3328 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3329 mtqc = IXGBE_MTQC_VT_ENA;
3330 if (tcs > 4)
3331 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3332 else if (tcs > 1)
3333 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
e24fcf28
AD		 3334 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3335 IXGBE_82599_VMDQ_4Q_MASK)
671c0adb
AD		 3336 mtqc |= IXGBE_MTQC_32VF;
3337 else
3338 mtqc |= IXGBE_MTQC_64VF;
3339 } else {
3340 if (tcs > 4)
3341 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3342 else if (tcs > 1)
3343 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3344 else
671c0adb
AD		 3345 mtqc = IXGBE_MTQC_64Q_1PB;
3346 }
120ff942 3347
671c0adb 3348 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3349
671c0adb
AD		 3350 /* Enable Security TX Buffer IFG for multiple pb */
3351 if (tcs) {
3352 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3353 sectx |= IXGBE_SECTX_DCB;
3354 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3355 }
3356
3357 /* re-enable the arbiter */
3358 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3359 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3360}
3361
9a799d71 3362/**
3a581073 3363 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3364 * @adapter: board private structure
3365 *
3366 * Configure the Tx unit of the MAC after a reset.
3367 **/
3368static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3369{
2f1860b8
AD		 3370 struct ixgbe_hw *hw = &adapter->hw;
3371 u32 dmatxctl;
43e69bf0 3372 u32 i;
9a799d71 3373
2f1860b8
AD		 3374 ixgbe_setup_mtqc(adapter);
3375
3376 if (hw->mac.type != ixgbe_mac_82598EB) {
3377 /* DMATXCTL.EN must be before Tx queues are enabled */
3378 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3379 dmatxctl |= IXGBE_DMATXCTL_TE;
3380 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3381 }
3382
9a799d71 3383 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3384 for (i = 0; i < adapter->num_tx_queues; i++)
3385 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3386}
3387
3ebe8fde
AD		 3388static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3389 struct ixgbe_ring *ring)
3390{
3391 struct ixgbe_hw *hw = &adapter->hw;
3392 u8 reg_idx = ring->reg_idx;
3393 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3394
3395 srrctl |= IXGBE_SRRCTL_DROP_EN;
3396
3397 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3398}
3399
3400static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3401 struct ixgbe_ring *ring)
3402{
3403 struct ixgbe_hw *hw = &adapter->hw;
3404 u8 reg_idx = ring->reg_idx;
3405 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3406
3407 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3408
3409 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3410}
3411
3412#ifdef CONFIG_IXGBE_DCB
3413void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3414#else
3415static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3416#endif
3417{
3418 int i;
3419 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3420
3421 if (adapter->ixgbe_ieee_pfc)
3422 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3423
3424 /*
3425 * We should set the drop enable bit if:
3426 * SR-IOV is enabled
3427 * or
3428 * Number of Rx queues > 1 and flow control is disabled
3429 *
3430 * This allows us to avoid head of line blocking for security
3431 * and performance reasons.
3432 */
3433 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3434 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3435 for (i = 0; i < adapter->num_rx_queues; i++)
3436 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3437 } else {
3438 for (i = 0; i < adapter->num_rx_queues; i++)
3439 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3440 }
3441}
3442
e8e26350 3443#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3444
a6616b42 3445static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3446 struct ixgbe_ring *rx_ring)
cc41ac7c 3447{
45e9baa5 3448 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3449 u32 srrctl;
bf29ee6c 3450 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3451
45e9baa5
AD		 3452 if (hw->mac.type == ixgbe_mac_82598EB) {
3453 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3454
45e9baa5
AD		 3455 /*
3456 * if VMDq is not active we must program one srrctl register
3457 * per RSS queue since we have enabled RDRXCTL.MVMEN
3458 */
3459 reg_idx &= mask;
3460 }
cc41ac7c 3461
45e9baa5
AD		 3462 /* configure header buffer length, needed for RSC */
3463 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3464
45e9baa5 3465 /* configure the packet buffer length */
2de6aa3a
AD		 3466 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state))
3467 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3468 else
3469 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3470
3471 /* configure descriptor type */
f800326d 3472 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3473
45e9baa5 3474 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3475}
9a799d71 3476
dfaf891d 3477/**
a897a2ad 3478 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3479 * @adapter: device handle
3480 *
3481 * - 82598/82599/X540: 128
3482 * - X550(non-SRIOV mode): 512
3483 * - X550(SRIOV mode): 64
3484 */
7f276efb 3485u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3486{
3487 if (adapter->hw.mac.type < ixgbe_mac_X550)
3488 return 128;
3489 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3490 return 64;
3491 else
3492 return 512;
3493}
3494
3495/**
a897a2ad 3496 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3497 * @adapter: device handle
3498 *
3499 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3500 */
1c7cf078 3501void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3502{
dfaf891d 3503 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3504 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3505 u32 reta = 0;
dfaf891d
VZ		 3506 u32 indices_multi;
3507 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3508
0f9b232b 3509 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3510 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3511 * indices.
3512 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3513 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3514 */
3515 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3516 indices_multi = 0x11;
3517 else
3518 indices_multi = 0x1;
3519
dfaf891d
VZ		 3520 /* Write redirection table to HW */
3521 for (i = 0; i < reta_entries; i++) {
3522 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3523 if ((i & 3) == 3) {
3524 if (i < 128)
3525 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3526 else
3527 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3528 reta);
dfaf891d 3529 reta = 0;
0f9b232b
DS		 3530 }
3531 }
3532}
3533
dfaf891d 3534/**
a897a2ad 3535 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3536 * @adapter: device handle
3537 *
3538 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3539 */
3540static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3541{
dfaf891d 3542 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3543 struct ixgbe_hw *hw = &adapter->hw;
3544 u32 vfreta = 0;
dfaf891d
VZ		 3545 unsigned int pf_pool = adapter->num_vfs;
3546
3547 /* Write redirection table to HW */
3548 for (i = 0; i < reta_entries; i++) {
3549 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3550 if ((i & 3) == 3) {
3551 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3552 vfreta);
3553 vfreta = 0;
3554 }
3555 }
3556}
3557
3558static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3559{
3560 struct ixgbe_hw *hw = &adapter->hw;
3561 u32 i, j;
3562 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3563 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3564
e24fcf28 3565 /* Program table for at least 4 queues w/ SR-IOV so that VFs can
dfaf891d
VZ		 3566 * make full use of any rings they may have. We will use the
3567 * PSRTYPE register to control how many rings we use within the PF.
3568 */
e24fcf28
AD		 3569 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3570 rss_i = 4;
dfaf891d
VZ		 3571
3572 /* Fill out hash function seeds */
3573 for (i = 0; i < 10; i++)
3574 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3575
3576 /* Fill out redirection table */
3577 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3578
3579 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3580 if (j == rss_i)
3581 j = 0;
3582
3583 adapter->rss_indir_tbl[i] = j;
3584 }
3585
3586 ixgbe_store_reta(adapter);
3587}
3588
3589static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3590{
3591 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3592 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3593 unsigned int pf_pool = adapter->num_vfs;
3594 int i, j;
3595
3596 /* Fill out hash function seeds */
3597 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3598 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3599 adapter->rss_key[i]);
0f9b232b
DS		 3600
3601 /* Fill out the redirection table */
3602 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3603 if (j == rss_i)
05abb126 3604 j = 0;
dfaf891d
VZ		 3605
3606 adapter->rss_indir_tbl[i] = j;
05abb126 3607 }
dfaf891d
VZ		 3608
3609 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3610}
3611
3612static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3613{
3614 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3615 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3616 u32 rxcsum;
0cefafad 3617
05abb126
AD		 3618 /* Disable indicating checksum in descriptor, enables RSS hash */
3619 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3620 rxcsum |= IXGBE_RXCSUM_PCSD;
3621 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3622
671c0adb 3623 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3624 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3625 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3626 } else {
671c0adb
AD		 3627 u8 tcs = netdev_get_num_tc(adapter->netdev);
3628
3629 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3630 if (tcs > 4)
3631 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3632 else if (tcs > 1)
3633 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
e24fcf28
AD		 3634 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3635 IXGBE_82599_VMDQ_4Q_MASK)
671c0adb 3636 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3637 else
671c0adb
AD		 3638 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3639 } else {
3640 if (tcs > 4)
8b1c0b24 3641 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3642 else if (tcs > 1)
3643 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3644 else
3645 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3646 }
0cefafad
JB		 3647 }
3648
05abb126 3649 /* Perform hash on these packet types */
d1b849b9
DS		 3650 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3651 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3652 IXGBE_MRQC_RSS_FIELD_IPV6 |
3653 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3654
ef6afc0c 3655 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3656 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3657 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3658 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3659
dfaf891d 3660 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3661 if ((hw->mac.type >= ixgbe_mac_X550) &&
3662 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3663 unsigned int pf_pool = adapter->num_vfs;
3664
3665 /* Enable VF RSS mode */
3666 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3667 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3668
3669 /* Setup RSS through the VF registers */
dfaf891d 3670 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3671 vfmrqc = IXGBE_MRQC_RSSEN;
3672 vfmrqc |= rss_field;
3673 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3674 } else {
dfaf891d 3675 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3676 mrqc |= rss_field;
3677 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3678 }
0cefafad
JB		 3679}
3680
bb5a9ad2
NS		 3681/**
3682 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3683 * @adapter: address of board private structure
3684 * @index: index of ring to set
bb5a9ad2 3685 **/
082757af 3686static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3687 struct ixgbe_ring *ring)
bb5a9ad2 3688{
bb5a9ad2 3689 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3690 u32 rscctrl;
bf29ee6c 3691 u8 reg_idx = ring->reg_idx;
7367096a 3692
7d637bcc 3693 if (!ring_is_rsc_enabled(ring))
7367096a 3694 return;
bb5a9ad2 3695
7367096a 3696 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3697 rscctrl |= IXGBE_RSCCTL_RSCEN;
3698 /*
3699 * we must limit the number of descriptors so that the
3700 * total size of max desc * buf_len is not greater
642c680e 3701 * than 65536
bb5a9ad2 3702 */
f800326d 3703 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3704 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3705}
3706
9e10e045
AD		 3707#define IXGBE_MAX_RX_DESC_POLL 10
3708static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3709 struct ixgbe_ring *ring)
3710{
3711 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3712 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3713 u32 rxdctl;
bf29ee6c 3714 u8 reg_idx = ring->reg_idx;
9e10e045 3715
b0483c8f
MR		 3716 if (ixgbe_removed(hw->hw_addr))
3717 return;
9e10e045
AD		 3718 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3719 if (hw->mac.type == ixgbe_mac_82598EB &&
3720 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3721 return;
3722
3723 do {
032b4325 3724 usleep_range(1000, 2000);
9e10e045
AD		 3725 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3726 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3727
3728 if (!wait_loop) {
3729 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3730 "the polling period\n", reg_idx);
3731 }
3732}
3733
2d39d576
YZ		 3734void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3735 struct ixgbe_ring *ring)
3736{
3737 struct ixgbe_hw *hw = &adapter->hw;
3738 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3739 u32 rxdctl;
3740 u8 reg_idx = ring->reg_idx;
3741
b0483c8f
MR		 3742 if (ixgbe_removed(hw->hw_addr))
3743 return;
2d39d576
YZ		 3744 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3745 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3746
3747 /* write value back with RXDCTL.ENABLE bit cleared */
3748 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3749
3750 if (hw->mac.type == ixgbe_mac_82598EB &&
3751 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3752 return;
3753
3754 /* the hardware may take up to 100us to really disable the rx queue */
3755 do {
3756 udelay(10);
3757 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3758 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3759
3760 if (!wait_loop) {
3761 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3762 "the polling period\n", reg_idx);
3763 }
3764}
3765
84418e3b
AD		 3766void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3767 struct ixgbe_ring *ring)
acd37177
AD		 3768{
3769 struct ixgbe_hw *hw = &adapter->hw;
c3630cc4 3770 union ixgbe_adv_rx_desc *rx_desc;
acd37177 3771 u64 rdba = ring->dma;
9e10e045 3772 u32 rxdctl;
bf29ee6c 3773 u8 reg_idx = ring->reg_idx;
acd37177 3774
9e10e045
AD		 3775 /* disable queue to avoid issues while updating state */
3776 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3777 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3778
acd37177
AD		 3779 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3780 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3781 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3782 ring->count * sizeof(union ixgbe_adv_rx_desc));
8b75451b
NP		 3783 /* Force flushing of IXGBE_RDLEN to prevent MDD */
3784 IXGBE_WRITE_FLUSH(hw);
3785
acd37177
AD		 3786 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3787 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3788 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3789
3790 ixgbe_configure_srrctl(adapter, ring);
3791 ixgbe_configure_rscctl(adapter, ring);
3792
3793 if (hw->mac.type == ixgbe_mac_82598EB) {
3794 /*
3795 * enable cache line friendly hardware writes:
3796 * PTHRESH=32 descriptors (half the internal cache),
3797 * this also removes ugly rx_no_buffer_count increment
3798 * HTHRESH=4 descriptors (to minimize latency on fetch)
3799 * WTHRESH=8 burst writeback up to two cache lines
3800 */
3801 rxdctl &= ~0x3FFFFF;
3802 rxdctl |= 0x080420;
2de6aa3a
AD		 3803#if (PAGE_SIZE < 8192)
3804 } else {
3805 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
3806 IXGBE_RXDCTL_RLPML_EN);
3807
3808 /* Limit the maximum frame size so we don't overrun the skb */
3809 if (ring_uses_build_skb(ring) &&
3810 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
3811 rxdctl |= IXGBE_MAX_FRAME_BUILD_SKB |
3812 IXGBE_RXDCTL_RLPML_EN;
3813#endif
9e10e045
AD		 3814 }
3815
c3630cc4
AD		 3816 /* initialize Rx descriptor 0 */
3817 rx_desc = IXGBE_RX_DESC(ring, 0);
3818 rx_desc->wb.upper.length = 0;
3819
9e10e045
AD		 3820 /* enable receive descriptor ring */
3821 rxdctl |= IXGBE_RXDCTL_ENABLE;
3822 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3823
3824 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3825 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3826}
3827
48654521
AD		 3828static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3829{
3830 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3831 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3832 u16 pool;
48654521
AD		 3833
3834 /* PSRTYPE must be initialized in non 82598 adapters */
3835 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3836 IXGBE_PSRTYPE_UDPHDR |
3837 IXGBE_PSRTYPE_IPV4HDR |
48654521 3838 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3839 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3840
3841 if (hw->mac.type == ixgbe_mac_82598EB)
3842 return;
3843
fbe7ca7f 3844 if (rss_i > 3)
b4f47a48 3845 psrtype |= 2u << 29;
fbe7ca7f 3846 else if (rss_i > 1)
b4f47a48 3847 psrtype |= 1u << 29;
48654521 3848
2a47fa45
JF		 3849 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3850 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3851}
3852
f5b4a52e
AD		 3853static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3854{
3855 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3856 u32 reg_offset, vf_shift;
435b19f6 3857 u32 gcr_ext, vmdctl;
de4c7f65 3858 int i;
f5b4a52e
AD		 3859
3860 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3861 return;
3862
3863 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3864 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3865 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3866 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3867 vmdctl |= IXGBE_VT_CTL_REPLEN;
3868 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3869
1d9c0bfd
AD		 3870 vf_shift = VMDQ_P(0) % 32;
3871 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3872
3873 /* Enable only the PF's pool for Tx/Rx */
11f2b494 3874 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
435b19f6 3875 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
11f2b494 3876 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
435b19f6 3877 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3878 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3879 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3880
3881 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3882 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e 3883
16369564
AD		 3884 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3885 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
3886
f5b4a52e
AD		 3887 /*
3888 * Set up VF register offsets for selected VT Mode,
3889 * i.e. 32 or 64 VFs for SR-IOV
3890 */
73079ea0
AD		 3891 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3892 case IXGBE_82599_VMDQ_8Q_MASK:
3893 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3894 break;
3895 case IXGBE_82599_VMDQ_4Q_MASK:
3896 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3897 break;
3898 default:
3899 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3900 break;
3901 }
3902
f5b4a52e
AD		 3903 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3904
de4c7f65 3905 for (i = 0; i < adapter->num_vfs; i++) {
77f192af
ET		 3906 /* configure spoof checking */
3907 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
3908 adapter->vfinfo[i].spoofchk_enabled);
e65ce0d3
VZ		 3909
3910 /* Enable/Disable RSS query feature */
3911 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3912 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3913 }
f5b4a52e
AD		 3914}
3915
477de6ed 3916static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3917{
9a799d71
AK		 3918 struct ixgbe_hw *hw = &adapter->hw;
3919 struct net_device *netdev = adapter->netdev;
3920 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3921 struct ixgbe_ring *rx_ring;
3922 int i;
3923 u32 mhadd, hlreg0;
48654521 3924
63f39bd1 3925#ifdef IXGBE_FCOE
477de6ed
AD		 3926 /* adjust max frame to be able to do baby jumbo for FCoE */
3927 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3928 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3929 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3930
477de6ed 3931#endif /* IXGBE_FCOE */
872844dd
AD		 3932
3933 /* adjust max frame to be at least the size of a standard frame */
3934 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3935 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3936
477de6ed
AD		 3937 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3938 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3939 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3940 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3941
3942 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3943 }
3944
3945 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3946 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3947 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3948 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3949
0cefafad
JB		 3950 /*
3951 * Setup the HW Rx Head and Tail Descriptor Pointers and
3952 * the Base and Length of the Rx Descriptor Ring
3953 */
9a799d71 3954 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3955 rx_ring = adapter->rx_ring[i];
4f4542bf
AD		 3956
3957 clear_ring_rsc_enabled(rx_ring);
3958 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
2de6aa3a 3959 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4f4542bf 3960
7d637bcc
AD		 3961 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3962 set_ring_rsc_enabled(rx_ring);
4f4542bf
AD		 3963
3964 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state))
3965 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
2de6aa3a 3966
6f429223 3967 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
2de6aa3a
AD		 3968 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
3969 continue;
3970
3971 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
3972
3973#if (PAGE_SIZE < 8192)
3974 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3975 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
3976
3977 if (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))
3978 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
3979#endif
477de6ed 3980 }
477de6ed
AD		 3981}
3982
7367096a
AD		 3983static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3984{
3985 struct ixgbe_hw *hw = &adapter->hw;
3986 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3987
3988 switch (hw->mac.type) {
3989 case ixgbe_mac_82598EB:
3990 /*
3991 * For VMDq support of different descriptor types or
3992 * buffer sizes through the use of multiple SRRCTL
3993 * registers, RDRXCTL.MVMEN must be set to 1
3994 *
3995 * also, the manual doesn't mention it clearly but DCA hints
3996 * will only use queue 0's tags unless this bit is set. Side
3997 * effects of setting this bit are only that SRRCTL must be
3998 * fully programmed [0..15]
3999 */
4000 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
4001 break;
052a1a72
MR		 4002 case ixgbe_mac_X550:
4003 case ixgbe_mac_X550EM_x:
49425dfc 4004 case ixgbe_mac_x550em_a:
f961ddae
MR		 4005 if (adapter->num_vfs)
4006 rdrxctl |= IXGBE_RDRXCTL_PSP;
4007 /* fall through for older HW */
7367096a 4008 case ixgbe_mac_82599EB:
b93a2226 4009 case ixgbe_mac_X540:
7367096a
AD		 4010 /* Disable RSC for ACK packets */
4011 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
4012 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
4013 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4014 /* hardware requires some bits to be set by default */
4015 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
4016 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4017 break;
4018 default:
4019 /* We should do nothing since we don't know this hardware */
4020 return;
4021 }
4022
4023 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4024}
4025
477de6ed
AD		 4026/**
4027 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
4028 * @adapter: board private structure
4029 *
4030 * Configure the Rx unit of the MAC after a reset.
4031 **/
4032static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
4033{
4034 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 4035 int i;
6dcc28b9 4036 u32 rxctrl, rfctl;
477de6ed
AD		 4037
4038 /* disable receives while setting up the descriptors */
1f9ac57c 4039 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 4040
4041 ixgbe_setup_psrtype(adapter);
7367096a 4042 ixgbe_setup_rdrxctl(adapter);
477de6ed 4043
6dcc28b9
JK		 4044 /* RSC Setup */
4045 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4046 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4047 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
4048 rfctl |= IXGBE_RFCTL_RSC_DIS;
a21d0822
ET		 4049
4050 /* disable NFS filtering */
4051 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
6dcc28b9
JK		 4052 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4053
9e10e045 4054 /* Program registers for the distribution of queues */
f5b4a52e 4055 ixgbe_setup_mrqc(adapter);
f5b4a52e 4056
477de6ed
AD		 4057 /* set_rx_buffer_len must be called before ring initialization */
4058 ixgbe_set_rx_buffer_len(adapter);
4059
4060 /*
4061 * Setup the HW Rx Head and Tail Descriptor Pointers and
4062 * the Base and Length of the Rx Descriptor Ring
4063 */
9e10e045
AD		 4064 for (i = 0; i < adapter->num_rx_queues; i++)
4065 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 4066
1f9ac57c 4067 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 4068 /* disable drop enable for 82598 parts */
4069 if (hw->mac.type == ixgbe_mac_82598EB)
4070 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4071
4072 /* enable all receives */
4073 rxctrl |= IXGBE_RXCTRL_RXEN;
4074 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 4075}
4076
80d5c368
PM		 4077static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
4078 __be16 proto, u16 vid)
068c89b0
DS		 4079{
4080 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4081 struct ixgbe_hw *hw = &adapter->hw;
4082
4083 /* add VID to filter table */
18be4fce
AD		 4084 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4085 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
4086
f62bbb5e 4087 set_bit(vid, adapter->active_vlans);
8e586137
JP		 4088
4089 return 0;
068c89b0
DS		 4090}
4091
e1d0a2af
AD		 4092static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
4093{
4094 u32 vlvf;
4095 int idx;
4096
4097 /* short cut the special case */
4098 if (vlan == 0)
4099 return 0;
4100
4101 /* Search for the vlan id in the VLVF entries */
4102 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
4103 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
4104 if ((vlvf & VLAN_VID_MASK) == vlan)
4105 break;
4106 }
4107
4108 return idx;
4109}
4110
4111void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
4112{
4113 struct ixgbe_hw *hw = &adapter->hw;
4114 u32 bits, word;
4115 int idx;
4116
4117 idx = ixgbe_find_vlvf_entry(hw, vid);
4118 if (!idx)
4119 return;
4120
4121 /* See if any other pools are set for this VLAN filter
4122 * entry other than the PF.
4123 */
4124 word = idx * 2 + (VMDQ_P(0) / 32);
b4f47a48 4125 bits = ~BIT(VMDQ_P(0) % 32);
e1d0a2af
AD		 4126 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4127
4128 /* Disable the filter so this falls into the default pool. */
4129 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4130 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4131 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4132 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4133 }
4134}
4135
80d5c368
PM		 4136static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4137 __be16 proto, u16 vid)
068c89b0
DS		 4138{
4139 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4140 struct ixgbe_hw *hw = &adapter->hw;
4141
068c89b0 4142 /* remove VID from filter table */
18be4fce 4143 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
e1d0a2af
AD		 4144 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4145
f62bbb5e 4146 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 4147
4148 return 0;
068c89b0
DS		 4149}
4150
f62bbb5e
JG		 4151/**
4152 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4153 * @adapter: driver data
4154 */
4155static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4156{
4157 struct ixgbe_hw *hw = &adapter->hw;
4158 u32 vlnctrl;
5f6c0181
JB		 4159 int i, j;
4160
4161 switch (hw->mac.type) {
4162 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4163 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4164 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4165 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4166 break;
4167 case ixgbe_mac_82599EB:
b93a2226 4168 case ixgbe_mac_X540:
9a75a1ac
DS		 4169 case ixgbe_mac_X550:
4170 case ixgbe_mac_X550EM_x:
49425dfc 4171 case ixgbe_mac_x550em_a:
5f6c0181 4172 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4173 struct ixgbe_ring *ring = adapter->rx_ring[i];
4174
4175 if (ring->l2_accel_priv)
4176 continue;
4177 j = ring->reg_idx;
5f6c0181
JB		 4178 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4179 vlnctrl &= ~IXGBE_RXDCTL_VME;
4180 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4181 }
4182 break;
4183 default:
4184 break;
4185 }
4186}
4187
4188/**
f62bbb5e 4189 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 4190 * @adapter: driver data
4191 */
f62bbb5e 4192static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 4193{
4194 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 4195 u32 vlnctrl;
5f6c0181
JB		 4196 int i, j;
4197
4198 switch (hw->mac.type) {
4199 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4200 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4201 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4202 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4203 break;
4204 case ixgbe_mac_82599EB:
b93a2226 4205 case ixgbe_mac_X540:
9a75a1ac
DS		 4206 case ixgbe_mac_X550:
4207 case ixgbe_mac_X550EM_x:
49425dfc 4208 case ixgbe_mac_x550em_a:
5f6c0181 4209 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4210 struct ixgbe_ring *ring = adapter->rx_ring[i];
4211
4212 if (ring->l2_accel_priv)
4213 continue;
4214 j = ring->reg_idx;
5f6c0181
JB		 4215 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4216 vlnctrl |= IXGBE_RXDCTL_VME;
4217 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4218 }
4219 break;
4220 default:
4221 break;
4222 }
4223}
4224
16369564
AD		 4225static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4226{
4227 struct ixgbe_hw *hw = &adapter->hw;
4228 u32 vlnctrl, i;
4229
f60439bc
AD		 4230 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4231
691e4121
ET		 4232 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4233 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4234 vlnctrl |= IXGBE_VLNCTRL_VFE;
4235 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4236 } else {
f60439bc 4237 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
16369564
AD		 4238 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4239 return;
4240 }
4241
691e4121
ET		 4242 /* Nothing to do for 82598 */
4243 if (hw->mac.type == ixgbe_mac_82598EB)
4244 return;
4245
16369564
AD		 4246 /* We are already in VLAN promisc, nothing to do */
4247 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4248 return;
4249
4250 /* Set flag so we don't redo unnecessary work */
4251 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4252
4253 /* Add PF to all active pools */
4254 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4255 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4256 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4257
b4f47a48 4258 vlvfb |= BIT(VMDQ_P(0) % 32);
16369564
AD		 4259 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4260 }
4261
4262 /* Set all bits in the VLAN filter table array */
4263 for (i = hw->mac.vft_size; i--;)
4264 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4265}
4266
4267#define VFTA_BLOCK_SIZE 8
4268static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4269{
4270 struct ixgbe_hw *hw = &adapter->hw;
4271 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4272 u32 vid_start = vfta_offset * 32;
4273 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4274 u32 i, vid, word, bits;
4275
4276 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4277 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4278
4279 /* pull VLAN ID from VLVF */
4280 vid = vlvf & VLAN_VID_MASK;
4281
4282 /* only concern outselves with a certain range */
4283 if (vid < vid_start || vid >= vid_end)
4284 continue;
4285
4286 if (vlvf) {
4287 /* record VLAN ID in VFTA */
b4f47a48 4288 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16369564
AD		 4289
4290 /* if PF is part of this then continue */
4291 if (test_bit(vid, adapter->active_vlans))
4292 continue;
4293 }
4294
4295 /* remove PF from the pool */
4296 word = i * 2 + VMDQ_P(0) / 32;
b4f47a48 4297 bits = ~BIT(VMDQ_P(0) % 32);
16369564
AD		 4298 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4299 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4300 }
4301
4302 /* extract values from active_vlans and write back to VFTA */
4303 for (i = VFTA_BLOCK_SIZE; i--;) {
4304 vid = (vfta_offset + i) * 32;
4305 word = vid / BITS_PER_LONG;
4306 bits = vid % BITS_PER_LONG;
4307
4308 vfta[i] |= adapter->active_vlans[word] >> bits;
4309
4310 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4311 }
4312}
4313
4314static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4315{
4316 struct ixgbe_hw *hw = &adapter->hw;
4317 u32 vlnctrl, i;
4318
f60439bc
AD		 4319 /* Set VLAN filtering to enabled */
4320 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4321 vlnctrl |= IXGBE_VLNCTRL_VFE;
4322 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4323
691e4121
ET		 4324 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4325 hw->mac.type == ixgbe_mac_82598EB)
16369564 4326 return;
16369564
AD		 4327
4328 /* We are not in VLAN promisc, nothing to do */
4329 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4330 return;
4331
4332 /* Set flag so we don't redo unnecessary work */
4333 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4334
4335 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4336 ixgbe_scrub_vfta(adapter, i);
4337}
4338
9a799d71
AK		 4339static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4340{
06bb1c39 4341 u16 vid = 1;
9a799d71 4342
80d5c368 4343 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e 4344
06bb1c39 4345 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 4346 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 4347}
4348
b335e75b
JK		 4349/**
4350 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4351 * @netdev: network interface device structure
4352 *
4353 * Writes multicast address list to the MTA hash table.
4354 * Returns: -ENOMEM on failure
4355 * 0 on no addresses written
4356 * X on writing X addresses to MTA
4357 **/
4358static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4359{
4360 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4361 struct ixgbe_hw *hw = &adapter->hw;
4362
4363 if (!netif_running(netdev))
4364 return 0;
4365
4366 if (hw->mac.ops.update_mc_addr_list)
4367 hw->mac.ops.update_mc_addr_list(hw, netdev);
4368 else
4369 return -ENOMEM;
4370
4371#ifdef CONFIG_PCI_IOV
5d7daa35 4372 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4373#endif
4374
4375 return netdev_mc_count(netdev);
4376}
4377
5d7daa35
JK		 4378#ifdef CONFIG_PCI_IOV
4379void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4380{
c9f53e63 4381 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4382 struct ixgbe_hw *hw = &adapter->hw;
4383 int i;
c9f53e63
AD		 4384
4385 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4386 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4387
4388 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4389 hw->mac.ops.set_rar(hw, i,
4390 mac_table->addr,
4391 mac_table->pool,
5d7daa35
JK		 4392 IXGBE_RAH_AV);
4393 else
4394 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4395 }
4396}
5d7daa35 4397
c9f53e63 4398#endif
5d7daa35
JK		 4399static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4400{
c9f53e63 4401 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4402 struct ixgbe_hw *hw = &adapter->hw;
4403 int i;
5d7daa35 4404
c9f53e63
AD		 4405 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4406 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4407 continue;
4408
4409 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4410
4411 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4412 hw->mac.ops.set_rar(hw, i,
4413 mac_table->addr,
4414 mac_table->pool,
4415 IXGBE_RAH_AV);
4416 else
4417 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4418 }
4419}
4420
4421static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4422{
c9f53e63 4423 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4424 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4425 int i;
5d7daa35 4426
c9f53e63
AD		 4427 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4428 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4429 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
5d7daa35 4430 }
c9f53e63 4431
5d7daa35
JK		 4432 ixgbe_sync_mac_table(adapter);
4433}
4434
c9f53e63 4435static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
5d7daa35 4436{
c9f53e63 4437 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4438 struct ixgbe_hw *hw = &adapter->hw;
4439 int i, count = 0;
4440
c9f53e63
AD		 4441 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4442 /* do not count default RAR as available */
4443 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4444 continue;
4445
4446 /* only count unused and addresses that belong to us */
4447 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4448 if (mac_table->pool != pool)
4449 continue;
4450 }
4451
4452 count++;
5d7daa35 4453 }
c9f53e63 4454
5d7daa35
JK		 4455 return count;
4456}
4457
4458/* this function destroys the first RAR entry */
c9f53e63 4459static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
5d7daa35 4460{
c9f53e63 4461 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4462 struct ixgbe_hw *hw = &adapter->hw;
4463
c9f53e63
AD		 4464 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4465 mac_table->pool = VMDQ_P(0);
4466
4467 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4468
4469 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
5d7daa35
JK		 4470 IXGBE_RAH_AV);
4471}
4472
c9f53e63
AD		 4473int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4474 const u8 *addr, u16 pool)
5d7daa35 4475{
c9f53e63 4476 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4477 struct ixgbe_hw *hw = &adapter->hw;
4478 int i;
4479
4480 if (is_zero_ether_addr(addr))
4481 return -EINVAL;
4482
c9f53e63
AD		 4483 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4484 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
5d7daa35 4485 continue;
c9f53e63
AD		 4486
4487 ether_addr_copy(mac_table->addr, addr);
4488 mac_table->pool = pool;
4489
4490 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4491 IXGBE_MAC_STATE_IN_USE;
4492
5d7daa35 4493 ixgbe_sync_mac_table(adapter);
c9f53e63 4494
5d7daa35
JK		 4495 return i;
4496 }
c9f53e63 4497
5d7daa35
JK		 4498 return -ENOMEM;
4499}
4500
c9f53e63
AD		 4501int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4502 const u8 *addr, u16 pool)
5d7daa35 4503{
c9f53e63 4504 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4505 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4506 int i;
5d7daa35
JK		 4507
4508 if (is_zero_ether_addr(addr))
4509 return -EINVAL;
4510
c9f53e63
AD		 4511 /* search table for addr, if found clear IN_USE flag and sync */
4512 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4513 /* we can only delete an entry if it is in use */
4514 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4515 continue;
4516 /* we only care about entries that belong to the given pool */
4517 if (mac_table->pool != pool)
4518 continue;
4519 /* we only care about a specific MAC address */
4520 if (!ether_addr_equal(addr, mac_table->addr))
4521 continue;
4522
4523 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4524 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4525
4526 ixgbe_sync_mac_table(adapter);
4527
4528 return 0;
5d7daa35 4529 }
c9f53e63 4530
5d7daa35
JK		 4531 return -ENOMEM;
4532}
2850062a
AD		 4533/**
4534 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4535 * @netdev: network interface device structure
4536 *
4537 * Writes unicast address list to the RAR table.
4538 * Returns: -ENOMEM on failure/insufficient address space
4539 * 0 on no addresses written
4540 * X on writing X addresses to the RAR table
4541 **/
5d7daa35 4542static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4543{
4544 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4545 int count = 0;
4546
4547 /* return ENOMEM indicating insufficient memory for addresses */
c9f53e63 4548 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
2850062a
AD		 4549 return -ENOMEM;
4550
95447461 4551 if (!netdev_uc_empty(netdev)) {
2850062a 4552 struct netdev_hw_addr *ha;
2850062a 4553 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4554 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4555 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4556 count++;
4557 }
4558 }
2850062a
AD		 4559 return count;
4560}
4561
0f079d22
AD		 4562static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4563{
4564 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4565 int ret;
4566
4567 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4568
4569 return min_t(int, ret, 0);
4570}
4571
4572static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4573{
4574 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4575
4576 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4577
4578 return 0;
4579}
4580
9a799d71 4581/**
2c5645cf 4582 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4583 * @netdev: network interface device structure
4584 *
2c5645cf
CL		 4585 * The set_rx_method entry point is called whenever the unicast/multicast
4586 * address list or the network interface flags are updated. This routine is
4587 * responsible for configuring the hardware for proper unicast, multicast and
4588 * promiscuous mode.
9a799d71 4589 **/
7f870475 4590void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4591{
4592 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4593 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4594 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
0c5a6166 4595 netdev_features_t features = netdev->features;
2850062a 4596 int count;
9a799d71
AK		 4597
4598 /* Check for Promiscuous and All Multicast modes */
9a799d71
AK		 4599 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4600
f5dc442b 4601 /* set all bits that we expect to always be set */
3f2d1c0f 4602 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4603 fctrl |= IXGBE_FCTRL_BAM;
4604 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4605 fctrl |= IXGBE_FCTRL_PMCF;
4606
2850062a
AD		 4607 /* clear the bits we are changing the status of */
4608 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
9a799d71 4609 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4610 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4611 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4612 vmolr |= IXGBE_VMOLR_MPE;
0c5a6166 4613 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
9a799d71 4614 } else {
746b9f02
PM		 4615 if (netdev->flags & IFF_ALLMULTI) {
4616 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4617 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4618 }
e433ea1f 4619 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4620 }
4621
4622 /*
4623 * Write addresses to available RAR registers, if there is not
4624 * sufficient space to store all the addresses then enable
4625 * unicast promiscuous mode
4626 */
0f079d22 4627 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
9dcb373c
JF		 4628 fctrl |= IXGBE_FCTRL_UPE;
4629 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4630 }
4631
cf78959c
ET		 4632 /* Write addresses to the MTA, if the attempt fails
4633 * then we should just turn on promiscuous mode so
4634 * that we can at least receive multicast traffic
4635 */
b335e75b
JK		 4636 count = ixgbe_write_mc_addr_list(netdev);
4637 if (count < 0) {
4638 fctrl |= IXGBE_FCTRL_MPE;
4639 vmolr |= IXGBE_VMOLR_MPE;
4640 } else if (count) {
4641 vmolr |= IXGBE_VMOLR_ROMPE;
4642 }
1d9c0bfd
AD		 4643
4644 if (hw->mac.type != ixgbe_mac_82598EB) {
4645 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4646 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4647 IXGBE_VMOLR_ROPE);
1d9c0bfd 4648 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4649 }
4650
3f2d1c0f 4651 /* This is useful for sniffing bad packets. */
0c5a6166 4652 if (features & NETIF_F_RXALL) {
3f2d1c0f
BG		 4653 /* UPE and MPE will be handled by normal PROMISC logic
4654 * in e1000e_set_rx_mode */
4655 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4656 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4657 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4658
4659 fctrl &= ~(IXGBE_FCTRL_DPF);
4660 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4661 }
4662
2850062a 4663 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4664
0c5a6166 4665 if (features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4666 ixgbe_vlan_strip_enable(adapter);
4667 else
4668 ixgbe_vlan_strip_disable(adapter);
0c5a6166
AD		 4669
4670 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4671 ixgbe_vlan_promisc_disable(adapter);
4672 else
4673 ixgbe_vlan_promisc_enable(adapter);
9a799d71
AK		 4674}
4675
021230d4
AV		 4676static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4677{
4678 int q_idx;
021230d4 4679
3ffc1af5 4680 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
49c7ffbe 4681 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 4682}
4683
4684static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4685{
4686 int q_idx;
021230d4 4687
3ffc1af5 4688 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
49c7ffbe 4689 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 4690}
4691
a21d0822 4692static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask)
67359c3c 4693{
a21d0822
ET		 4694 struct ixgbe_hw *hw = &adapter->hw;
4695 u32 vxlanctrl;
4696
4697 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE |
4698 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)))
4699 return;
4700
4701 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) && ~mask;
4702 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl);
4703
4704 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK)
67359c3c 4705 adapter->vxlan_port = 0;
a21d0822
ET		 4706
4707 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK)
4708 adapter->geneve_port = 0;
67359c3c
MR		 4709}
4710
7a6b6f51 4711#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4712/**
2f90b865
AD		 4713 * ixgbe_configure_dcb - Configure DCB hardware
4714 * @adapter: ixgbe adapter struct
4715 *
4716 * This is called by the driver on open to configure the DCB hardware.
4717 * This is also called by the gennetlink interface when reconfiguring
4718 * the DCB state.
4719 */
4720static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4721{
4722 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4723 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4724
67ebd791
AD		 4725 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4726 if (hw->mac.type == ixgbe_mac_82598EB)
4727 netif_set_gso_max_size(adapter->netdev, 65536);
4728 return;
4729 }
4730
4731 if (hw->mac.type == ixgbe_mac_82598EB)
4732 netif_set_gso_max_size(adapter->netdev, 32768);
4733
971060b1 4734#ifdef IXGBE_FCOE
b120818e
JF		 4735 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4736 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4737#endif
b120818e
JF		 4738
4739 /* reconfigure the hardware */
4740 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4741 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4742 DCB_TX_CONFIG);
4743 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4744 DCB_RX_CONFIG);
4745 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4746 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4747 ixgbe_dcb_hw_ets(&adapter->hw,
4748 adapter->ixgbe_ieee_ets,
4749 max_frame);
4750 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4751 adapter->ixgbe_ieee_pfc->pfc_en,
4752 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4753 }
8187cd48
JF		 4754
4755 /* Enable RSS Hash per TC */
4756 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4757 u32 msb = 0;
4758 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4759
d411a936
AD		 4760 while (rss_i) {
4761 msb++;
4762 rss_i >>= 1;
4763 }
8187cd48 4764
4ae63730
AD		 4765 /* write msb to all 8 TCs in one write */
4766 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4767 }
2f90b865 4768}
9da712d2
JF		 4769#endif
4770
4771/* Additional bittime to account for IXGBE framing */
4772#define IXGBE_ETH_FRAMING 20
4773
49ce9c2c 4774/**
9da712d2
JF		 4775 * ixgbe_hpbthresh - calculate high water mark for flow control
4776 *
4777 * @adapter: board private structure to calculate for
49ce9c2c 4778 * @pb: packet buffer to calculate
9da712d2
JF		 4779 */
4780static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4781{
4782 struct ixgbe_hw *hw = &adapter->hw;
4783 struct net_device *dev = adapter->netdev;
4784 int link, tc, kb, marker;
4785 u32 dv_id, rx_pba;
4786
4787 /* Calculate max LAN frame size */
4788 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4789
4790#ifdef IXGBE_FCOE
4791 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4792 if ((dev->features & NETIF_F_FCOE_MTU) &&
4793 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4794 (pb == ixgbe_fcoe_get_tc(adapter)))
4795 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4796#endif
e5776620 4797
9da712d2
JF		 4798 /* Calculate delay value for device */
4799 switch (hw->mac.type) {
4800 case ixgbe_mac_X540:
9a75a1ac
DS		 4801 case ixgbe_mac_X550:
4802 case ixgbe_mac_X550EM_x:
49425dfc 4803 case ixgbe_mac_x550em_a:
9da712d2
JF		 4804 dv_id = IXGBE_DV_X540(link, tc);
4805 break;
4806 default:
4807 dv_id = IXGBE_DV(link, tc);
4808 break;
4809 }
4810
4811 /* Loopback switch introduces additional latency */
4812 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4813 dv_id += IXGBE_B2BT(tc);
4814
4815 /* Delay value is calculated in bit times convert to KB */
4816 kb = IXGBE_BT2KB(dv_id);
4817 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4818
4819 marker = rx_pba - kb;
4820
4821 /* It is possible that the packet buffer is not large enough
4822 * to provide required headroom. In this case throw an error
4823 * to user and a do the best we can.
4824 */
4825 if (marker < 0) {
4826 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4827 "headroom to support flow control."
4828 "Decrease MTU or number of traffic classes\n", pb);
4829 marker = tc + 1;
4830 }
4831
4832 return marker;
4833}
4834
49ce9c2c 4835/**
9da712d2
JF		 4836 * ixgbe_lpbthresh - calculate low water mark for for flow control
4837 *
4838 * @adapter: board private structure to calculate for
49ce9c2c 4839 * @pb: packet buffer to calculate
9da712d2 4840 */
e5776620 4841static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4842{
4843 struct ixgbe_hw *hw = &adapter->hw;
4844 struct net_device *dev = adapter->netdev;
4845 int tc;
4846 u32 dv_id;
4847
4848 /* Calculate max LAN frame size */
4849 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4850
e5776620
JK		 4851#ifdef IXGBE_FCOE
4852 /* FCoE traffic class uses FCOE jumbo frames */
4853 if ((dev->features & NETIF_F_FCOE_MTU) &&
4854 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4855 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4856 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4857#endif
4858
9da712d2
JF		 4859 /* Calculate delay value for device */
4860 switch (hw->mac.type) {
4861 case ixgbe_mac_X540:
9a75a1ac
DS		 4862 case ixgbe_mac_X550:
4863 case ixgbe_mac_X550EM_x:
49425dfc 4864 case ixgbe_mac_x550em_a:
9da712d2
JF		 4865 dv_id = IXGBE_LOW_DV_X540(tc);
4866 break;
4867 default:
4868 dv_id = IXGBE_LOW_DV(tc);
4869 break;
4870 }
4871
4872 /* Delay value is calculated in bit times convert to KB */
4873 return IXGBE_BT2KB(dv_id);
4874}
4875
4876/*
4877 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4878 */
4879static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4880{
4881 struct ixgbe_hw *hw = &adapter->hw;
4882 int num_tc = netdev_get_num_tc(adapter->netdev);
4883 int i;
4884
4885 if (!num_tc)
4886 num_tc = 1;
4887
9da712d2
JF		 4888 for (i = 0; i < num_tc; i++) {
4889 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4890 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4891
4892 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4893 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4894 hw->fc.low_water[i] = 0;
9da712d2 4895 }
e5776620
JK		 4896
4897 for (; i < MAX_TRAFFIC_CLASS; i++)
4898 hw->fc.high_water[i] = 0;
9da712d2
JF		 4899}
4900
80605c65
JF		 4901static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4902{
80605c65 4903 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4904 int hdrm;
4905 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4906
4907 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4908 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4909 hdrm = 32 << adapter->fdir_pballoc;
4910 else
4911 hdrm = 0;
80605c65 4912
f7e1027f 4913 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4914 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4915}
4916
e4911d57
AD		 4917static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4918{
4919 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4920 struct hlist_node *node2;
e4911d57
AD		 4921 struct ixgbe_fdir_filter *filter;
4922
4923 spin_lock(&adapter->fdir_perfect_lock);
4924
4925 if (!hlist_empty(&adapter->fdir_filter_list))
4926 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4927
b67bfe0d 4928 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4929 &adapter->fdir_filter_list, fdir_node) {
4930 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4931 &filter->filter,
4932 filter->sw_idx,
4933 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4934 IXGBE_FDIR_DROP_QUEUE :
4935 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4936 }
4937
4938 spin_unlock(&adapter->fdir_perfect_lock);
4939}
4940
2a47fa45
JF		 4941static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4942 struct ixgbe_adapter *adapter)
4943{
4944 struct ixgbe_hw *hw = &adapter->hw;
4945 u32 vmolr;
4946
4947 /* No unicast promiscuous support for VMDQ devices. */
4948 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4949 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4950
4951 /* clear the affected bit */
4952 vmolr &= ~IXGBE_VMOLR_MPE;
4953
4954 if (dev->flags & IFF_ALLMULTI) {
4955 vmolr |= IXGBE_VMOLR_MPE;
4956 } else {
4957 vmolr |= IXGBE_VMOLR_ROMPE;
4958 hw->mac.ops.update_mc_addr_list(hw, dev);
4959 }
5d7daa35 4960 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4961 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4962}
4963
2a47fa45
JF		 4964static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4965{
4966 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4967 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4968 struct ixgbe_hw *hw = &adapter->hw;
4969 u16 pool = vadapter->pool;
4970 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4971 IXGBE_PSRTYPE_UDPHDR |
4972 IXGBE_PSRTYPE_IPV4HDR |
4973 IXGBE_PSRTYPE_L2HDR |
4974 IXGBE_PSRTYPE_IPV6HDR;
4975
4976 if (hw->mac.type == ixgbe_mac_82598EB)
4977 return;
4978
4979 if (rss_i > 3)
b4f47a48 4980 psrtype |= 2u << 29;
2a47fa45 4981 else if (rss_i > 1)
b4f47a48 4982 psrtype |= 1u << 29;
2a47fa45
JF		 4983
4984 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4985}
4986
4987/**
4988 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4989 * @rx_ring: ring to free buffers from
4990 **/
4991static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4992{
4993 struct device *dev = rx_ring->dev;
4994 unsigned long size;
4995 u16 i;
4996
4997 /* ring already cleared, nothing to do */
4998 if (!rx_ring->rx_buffer_info)
4999 return;
5000
5001 /* Free all the Rx ring sk_buffs */
5002 for (i = 0; i < rx_ring->count; i++) {
18cb652a 5003 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 5004
2a47fa45
JF		 5005 if (rx_buffer->skb) {
5006 struct sk_buff *skb = rx_buffer->skb;
18cb652a 5007 if (IXGBE_CB(skb)->page_released)
f3213d93
AD		 5008 dma_unmap_page_attrs(dev,
5009 IXGBE_CB(skb)->dma,
5010 ixgbe_rx_pg_size(rx_ring),
5011 DMA_FROM_DEVICE,
5012 IXGBE_RX_DMA_ATTR);
2a47fa45 5013 dev_kfree_skb(skb);
4d2fcfbc 5014 rx_buffer->skb = NULL;
2a47fa45 5015 }
18cb652a
AD		 5016
5017 if (!rx_buffer->page)
5018 continue;
5019
f3213d93
AD		 5020 /* Invalidate cache lines that may have been written to by
5021 * device so that we avoid corrupting memory.
5022 */
5023 dma_sync_single_range_for_cpu(rx_ring->dev,
5024 rx_buffer->dma,
5025 rx_buffer->page_offset,
5026 ixgbe_rx_bufsz(rx_ring),
5027 DMA_FROM_DEVICE);
5028
5029 /* free resources associated with mapping */
5030 dma_unmap_page_attrs(dev, rx_buffer->dma,
5031 ixgbe_rx_pg_size(rx_ring),
5032 DMA_FROM_DEVICE,
5033 IXGBE_RX_DMA_ATTR);
1b56cf49
AD		 5034 __page_frag_cache_drain(rx_buffer->page,
5035 rx_buffer->pagecnt_bias);
18cb652a 5036
2a47fa45
JF		 5037 rx_buffer->page = NULL;
5038 }
5039
5040 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5041 memset(rx_ring->rx_buffer_info, 0, size);
5042
2a47fa45
JF		 5043 rx_ring->next_to_alloc = 0;
5044 rx_ring->next_to_clean = 0;
5045 rx_ring->next_to_use = 0;
5046}
5047
5048static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
5049 struct ixgbe_ring *rx_ring)
5050{
5051 struct ixgbe_adapter *adapter = vadapter->real_adapter;
5052 int index = rx_ring->queue_index + vadapter->rx_base_queue;
5053
5054 /* shutdown specific queue receive and wait for dma to settle */
5055 ixgbe_disable_rx_queue(adapter, rx_ring);
5056 usleep_range(10000, 20000);
b4f47a48 5057 ixgbe_irq_disable_queues(adapter, BIT_ULL(index));
2a47fa45
JF		 5058 ixgbe_clean_rx_ring(rx_ring);
5059 rx_ring->l2_accel_priv = NULL;
5060}
5061
ae72c8d0
JF		 5062static int ixgbe_fwd_ring_down(struct net_device *vdev,
5063 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 5064{
5065 struct ixgbe_adapter *adapter = accel->real_adapter;
5066 unsigned int rxbase = accel->rx_base_queue;
5067 unsigned int txbase = accel->tx_base_queue;
5068 int i;
5069
5070 netif_tx_stop_all_queues(vdev);
5071
5072 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
5073 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
5074 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
5075 }
5076
5077 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
5078 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
5079 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
5080 }
5081
5082
5083 return 0;
5084}
5085
5086static int ixgbe_fwd_ring_up(struct net_device *vdev,
5087 struct ixgbe_fwd_adapter *accel)
5088{
5089 struct ixgbe_adapter *adapter = accel->real_adapter;
5090 unsigned int rxbase, txbase, queues;
5091 int i, baseq, err = 0;
5092
5093 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
5094 return 0;
5095
5096 baseq = accel->pool * adapter->num_rx_queues_per_pool;
5097 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
5098 accel->pool, adapter->num_rx_pools,
5099 baseq, baseq + adapter->num_rx_queues_per_pool,
5100 adapter->fwd_bitmask);
5101
5102 accel->netdev = vdev;
5103 accel->rx_base_queue = rxbase = baseq;
5104 accel->tx_base_queue = txbase = baseq;
5105
5106 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5107 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
5108
5109 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
5110 adapter->rx_ring[rxbase + i]->netdev = vdev;
5111 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
5112 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
5113 }
5114
5115 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
5116 adapter->tx_ring[txbase + i]->netdev = vdev;
5117 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
5118 }
5119
5120 queues = min_t(unsigned int,
5121 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
5122 err = netif_set_real_num_tx_queues(vdev, queues);
5123 if (err)
5124 goto fwd_queue_err;
5125
2a47fa45
JF		 5126 err = netif_set_real_num_rx_queues(vdev, queues);
5127 if (err)
5128 goto fwd_queue_err;
5129
5130 if (is_valid_ether_addr(vdev->dev_addr))
5131 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
5132
5133 ixgbe_fwd_psrtype(accel);
5134 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
5135 return err;
5136fwd_queue_err:
5137 ixgbe_fwd_ring_down(vdev, accel);
5138 return err;
5139}
5140
1cd127fc 5141static int ixgbe_upper_dev_walk(struct net_device *upper, void *data)
2a47fa45 5142{
1cd127fc
DA		 5143 if (netif_is_macvlan(upper)) {
5144 struct macvlan_dev *dfwd = netdev_priv(upper);
5145 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
2a47fa45 5146
1cd127fc
DA		 5147 if (dfwd->fwd_priv)
5148 ixgbe_fwd_ring_up(upper, vadapter);
2a47fa45 5149 }
1cd127fc
DA		 5150
5151 return 0;
5152}
5153
5154static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5155{
5156 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5157 ixgbe_upper_dev_walk, NULL);
2a47fa45
JF		 5158}
5159
9a799d71
AK		 5160static void ixgbe_configure(struct ixgbe_adapter *adapter)
5161{
d2f5e7f3
AS		 5162 struct ixgbe_hw *hw = &adapter->hw;
5163
80605c65 5164 ixgbe_configure_pb(adapter);
7a6b6f51 5165#ifdef CONFIG_IXGBE_DCB
67ebd791 5166 ixgbe_configure_dcb(adapter);
2f90b865 5167#endif
b35d4d42
AD		 5168 /*
5169 * We must restore virtualization before VLANs or else
5170 * the VLVF registers will not be populated
5171 */
5172 ixgbe_configure_virtualization(adapter);
9a799d71 5173
4c1d7b4b 5174 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 5175 ixgbe_restore_vlan(adapter);
5176
d2f5e7f3
AS		 5177 switch (hw->mac.type) {
5178 case ixgbe_mac_82599EB:
5179 case ixgbe_mac_X540:
5180 hw->mac.ops.disable_rx_buff(hw);
5181 break;
5182 default:
5183 break;
5184 }
5185
c4cf55e5 5186 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 5187 ixgbe_init_fdir_signature_82599(&adapter->hw,
5188 adapter->fdir_pballoc);
e4911d57
AD		 5189 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5190 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5191 adapter->fdir_pballoc);
5192 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 5193 }
4c1d7b4b 5194
d2f5e7f3
AS		 5195 switch (hw->mac.type) {
5196 case ixgbe_mac_82599EB:
5197 case ixgbe_mac_X540:
5198 hw->mac.ops.enable_rx_buff(hw);
5199 break;
5200 default:
5201 break;
5202 }
5203
9de7605e
MR		 5204#ifdef CONFIG_IXGBE_DCA
5205 /* configure DCA */
5206 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5207 ixgbe_setup_dca(adapter);
5208#endif /* CONFIG_IXGBE_DCA */
5209
7c8ae65a
AD		 5210#ifdef IXGBE_FCOE
5211 /* configure FCoE L2 filters, redirection table, and Rx control */
5212 ixgbe_configure_fcoe(adapter);
5213
5214#endif /* IXGBE_FCOE */
9a799d71
AK		 5215 ixgbe_configure_tx(adapter);
5216 ixgbe_configure_rx(adapter);
2a47fa45 5217 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 5218}
5219
0ecc061d 5220/**
e8e26350
PW		 5221 * ixgbe_sfp_link_config - set up SFP+ link
5222 * @adapter: pointer to private adapter struct
5223 **/
5224static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5225{
7086400d 5226 /*
52f33af8 5227 * We are assuming the worst case scenario here, and that
7086400d
AD		 5228 * is that an SFP was inserted/removed after the reset
5229 * but before SFP detection was enabled. As such the best
5230 * solution is to just start searching as soon as we start
5231 */
5232 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5233 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 5234
7086400d 5235 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 5236 adapter->sfp_poll_time = 0;
e8e26350
PW		 5237}
5238
5239/**
5240 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 5241 * @hw: pointer to private hardware struct
5242 *
5243 * Returns 0 on success, negative on failure
5244 **/
e8e26350 5245static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 5246{
3d292265
JH		 5247 u32 speed;
5248 bool autoneg, link_up = false;
a1e869de 5249 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 5250
5251 if (hw->mac.ops.check_link)
3d292265 5252 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 5253
5254 if (ret)
e90dd264 5255 return ret;
0ecc061d 5256
3d292265
JH		 5257 speed = hw->phy.autoneg_advertised;
5258 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5259 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5260 &autoneg);
0ecc061d 5261 if (ret)
e90dd264 5262 return ret;
0ecc061d 5263
8620a103 5264 if (hw->mac.ops.setup_link)
fd0326f2 5265 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 5266
0ecc061d
PWJ		 5267 return ret;
5268}
5269
a34bcfff 5270static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 5271{
9a799d71 5272 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5273 u32 gpie = 0;
9a799d71 5274
9b471446 5275 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 5276 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5277 IXGBE_GPIE_OCD;
5278 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 5279 /*
5280 * use EIAM to auto-mask when MSI-X interrupt is asserted
5281 * this saves a register write for every interrupt
5282 */
5283 switch (hw->mac.type) {
5284 case ixgbe_mac_82598EB:
5285 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5286 break;
9b471446 5287 case ixgbe_mac_82599EB:
b93a2226 5288 case ixgbe_mac_X540:
9a75a1ac
DS		 5289 case ixgbe_mac_X550:
5290 case ixgbe_mac_X550EM_x:
49425dfc 5291 case ixgbe_mac_x550em_a:
b93a2226 5292 default:
9b471446
JB		 5293 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5294 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5295 break;
5296 }
5297 } else {
021230d4
AV		 5298 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5299 * specifically only auto mask tx and rx interrupts */
5300 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5301 }
9a799d71 5302
a34bcfff
AD		 5303 /* XXX: to interrupt immediately for EICS writes, enable this */
5304 /* gpie |= IXGBE_GPIE_EIMEN; */
5305
5306 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5307 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 5308
5309 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5310 case IXGBE_82599_VMDQ_8Q_MASK:
5311 gpie |= IXGBE_GPIE_VTMODE_16;
5312 break;
5313 case IXGBE_82599_VMDQ_4Q_MASK:
5314 gpie |= IXGBE_GPIE_VTMODE_32;
5315 break;
5316 default:
5317 gpie |= IXGBE_GPIE_VTMODE_64;
5318 break;
5319 }
119fc60a
MC		 5320 }
5321
5fdd31f9 5322 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 5323 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5324 switch (adapter->hw.mac.type) {
5325 case ixgbe_mac_82599EB:
9a900eca 5326 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 5327 break;
f3df98ec
DS		 5328 default:
5329 break;
5330 }
5331 }
5fdd31f9 5332
a34bcfff
AD		 5333 /* Enable fan failure interrupt */
5334 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 5335 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 5336
a023bbd0
DS		 5337 switch (hw->mac.type) {
5338 case ixgbe_mac_82599EB:
5339 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5340 break;
5341 case ixgbe_mac_X550EM_x:
49425dfc 5342 case ixgbe_mac_x550em_a:
a023bbd0
DS		 5343 gpie |= IXGBE_SDP0_GPIEN_X540;
5344 break;
5345 default:
5346 break;
2698b208 5347 }
a34bcfff
AD		 5348
5349 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5350}
5351
c7ccde0f 5352static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 5353{
5354 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5355 int err;
a34bcfff
AD		 5356 u32 ctrl_ext;
5357
5358 ixgbe_get_hw_control(adapter);
5359 ixgbe_setup_gpie(adapter);
e8e26350 5360
9a799d71
AK		 5361 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5362 ixgbe_configure_msix(adapter);
5363 else
5364 ixgbe_configure_msi_and_legacy(adapter);
5365
ec74a471
ET		 5366 /* enable the optics for 82599 SFP+ fiber */
5367 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 5368 hw->mac.ops.enable_tx_laser(hw);
5369
961fac88
DS		 5370 if (hw->phy.ops.set_phy_power)
5371 hw->phy.ops.set_phy_power(hw, true);
5372
4e857c58 5373 smp_mb__before_atomic();
9a799d71 5374 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 5375 ixgbe_napi_enable_all(adapter);
5376
73c4b7cd
AD		 5377 if (ixgbe_is_sfp(hw)) {
5378 ixgbe_sfp_link_config(adapter);
5379 } else {
5380 err = ixgbe_non_sfp_link_config(hw);
5381 if (err)
5382 e_err(probe, "link_config FAILED %d\n", err);
5383 }
5384
021230d4
AV		 5385 /* clear any pending interrupts, may auto mask */
5386 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 5387 ixgbe_irq_enable(adapter, true, true);
9a799d71 5388
bf069c97
DS		 5389 /*
5390 * If this adapter has a fan, check to see if we had a failure
5391 * before we enabled the interrupt.
5392 */
5393 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5394 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5395 if (esdp & IXGBE_ESDP_SDP1)
396e799c 5396 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 5397 }
5398
9a799d71
AK		 5399 /* bring the link up in the watchdog, this could race with our first
5400 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 5401 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5402 adapter->link_check_timeout = jiffies;
7086400d 5403 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 5404
5405 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5406 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5407 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5408 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5409}
5410
d4f80882
AV		 5411void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5412{
5413 WARN_ON(in_interrupt());
7086400d 5414 /* put off any impending NetWatchDogTimeout */
860e9538 5415 netif_trans_update(adapter->netdev);
7086400d 5416
d4f80882 5417 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5418 usleep_range(1000, 2000);
b3eb4e18
MR		 5419 if (adapter->hw.phy.type == ixgbe_phy_fw)
5420 ixgbe_watchdog_link_is_down(adapter);
d4f80882 5421 ixgbe_down(adapter);
5809a1ae
GR		 5422 /*
5423 * If SR-IOV enabled then wait a bit before bringing the adapter
5424 * back up to give the VFs time to respond to the reset. The
5425 * two second wait is based upon the watchdog timer cycle in
5426 * the VF driver.
5427 */
5428 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5429 msleep(2000);
d4f80882
AV		 5430 ixgbe_up(adapter);
5431 clear_bit(__IXGBE_RESETTING, &adapter->state);
5432}
5433
c7ccde0f 5434void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5435{
5436 /* hardware has been reset, we need to reload some things */
5437 ixgbe_configure(adapter);
5438
c7ccde0f 5439 ixgbe_up_complete(adapter);
9a799d71
AK		 5440}
5441
5442void ixgbe_reset(struct ixgbe_adapter *adapter)
5443{
c44ade9e 5444 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5445 struct net_device *netdev = adapter->netdev;
8ca783ab
DS		 5446 int err;
5447
b0483c8f
MR		 5448 if (ixgbe_removed(hw->hw_addr))
5449 return;
7086400d
AD		 5450 /* lock SFP init bit to prevent race conditions with the watchdog */
5451 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5452 usleep_range(1000, 2000);
5453
5454 /* clear all SFP and link config related flags while holding SFP_INIT */
5455 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5456 IXGBE_FLAG2_SFP_NEEDS_RESET);
5457 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5458
8ca783ab 5459 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5460 switch (err) {
5461 case 0:
5462 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5463 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5464 break;
5465 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5466 e_dev_err("master disable timed out\n");
da4dd0f7 5467 break;
794caeb2
PWJ		 5468 case IXGBE_ERR_EEPROM_VERSION:
5469 /* We are running on a pre-production device, log a warning */
849c4542 5470 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5471 "Please be aware there may be issues associated with "
849c4542
ET		 5472 "your hardware. If you are experiencing problems "
5473 "please contact your Intel or hardware "
5474 "representative who provided you with this "
5475 "hardware.\n");
794caeb2 5476 break;
da4dd0f7 5477 default:
849c4542 5478 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5479 }
9a799d71 5480
7086400d 5481 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
0f079d22
AD		 5482
5483 /* flush entries out of MAC table */
5d7daa35 5484 ixgbe_flush_sw_mac_table(adapter);
0f079d22
AD		 5485 __dev_uc_unsync(netdev, NULL);
5486
5487 /* do not flush user set addresses */
c9f53e63 5488 ixgbe_mac_set_default_filter(adapter);
7fa7c9dc
AD		 5489
5490 /* update SAN MAC vmdq pool selection */
5491 if (hw->mac.san_mac_rar_index)
5492 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5493
8fecf67c 5494 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5495 ixgbe_ptp_reset(adapter);
961fac88
DS		 5496
5497 if (hw->phy.ops.set_phy_power) {
5498 if (!netif_running(adapter->netdev) && !adapter->wol)
5499 hw->phy.ops.set_phy_power(hw, false);
5500 else
5501 hw->phy.ops.set_phy_power(hw, true);
5502 }
9a799d71
AK		 5503}
5504
9a799d71
AK		 5505/**
5506 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5507 * @tx_ring: ring to be cleaned
5508 **/
b6ec895e 5509static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5510{
5511 struct ixgbe_tx_buffer *tx_buffer_info;
5512 unsigned long size;
b6ec895e 5513 u16 i;
9a799d71 5514
84418e3b
AD		 5515 /* ring already cleared, nothing to do */
5516 if (!tx_ring->tx_buffer_info)
5517 return;
9a799d71 5518
84418e3b 5519 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5520 for (i = 0; i < tx_ring->count; i++) {
5521 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5522 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5523 }
5524
dad8a3b3
JF		 5525 netdev_tx_reset_queue(txring_txq(tx_ring));
5526
9a799d71
AK		 5527 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5528 memset(tx_ring->tx_buffer_info, 0, size);
5529
5530 /* Zero out the descriptor ring */
5531 memset(tx_ring->desc, 0, tx_ring->size);
5532
5533 tx_ring->next_to_use = 0;
5534 tx_ring->next_to_clean = 0;
9a799d71
AK		 5535}
5536
5537/**
021230d4 5538 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5539 * @adapter: board private structure
5540 **/
021230d4 5541static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5542{
5543 int i;
5544
021230d4 5545 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5546 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5547}
5548
5549/**
021230d4 5550 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5551 * @adapter: board private structure
5552 **/
021230d4 5553static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5554{
5555 int i;
5556
021230d4 5557 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5558 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5559}
5560
e4911d57
AD		 5561static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5562{
b67bfe0d 5563 struct hlist_node *node2;
e4911d57
AD		 5564 struct ixgbe_fdir_filter *filter;
5565
5566 spin_lock(&adapter->fdir_perfect_lock);
5567
b67bfe0d 5568 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5569 &adapter->fdir_filter_list, fdir_node) {
5570 hlist_del(&filter->fdir_node);
5571 kfree(filter);
5572 }
5573 adapter->fdir_filter_count = 0;
5574
5575 spin_unlock(&adapter->fdir_perfect_lock);
5576}
5577
1cd127fc
DA		 5578static int ixgbe_disable_macvlan(struct net_device *upper, void *data)
5579{
5580 if (netif_is_macvlan(upper)) {
5581 struct macvlan_dev *vlan = netdev_priv(upper);
5582
5583 if (vlan->fwd_priv) {
5584 netif_tx_stop_all_queues(upper);
5585 netif_carrier_off(upper);
5586 netif_tx_disable(upper);
5587 }
5588 }
5589
5590 return 0;
5591}
5592
9a799d71
AK		 5593void ixgbe_down(struct ixgbe_adapter *adapter)
5594{
5595 struct net_device *netdev = adapter->netdev;
7f821875 5596 struct ixgbe_hw *hw = &adapter->hw;
bf29ee6c 5597 int i;
9a799d71
AK		 5598
5599 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5600 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5601 return; /* do nothing if already down */
9a799d71
AK		 5602
5603 /* disable receives */
1f9ac57c 5604 hw->mac.ops.disable_rx(hw);
9a799d71 5605
2d39d576
YZ		 5606 /* disable all enabled rx queues */
5607 for (i = 0; i < adapter->num_rx_queues; i++)
5608 /* this call also flushes the previous write */
5609 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5610
032b4325 5611 usleep_range(10000, 20000);
9a799d71 5612
7f821875
JB		 5613 netif_tx_stop_all_queues(netdev);
5614
7086400d 5615 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5616 netif_carrier_off(netdev);
5617 netif_tx_disable(netdev);
5618
2a47fa45 5619 /* disable any upper devices */
1cd127fc
DA		 5620 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5621 ixgbe_disable_macvlan, NULL);
2a47fa45 5622
c0dfb90e
JF		 5623 ixgbe_irq_disable(adapter);
5624
5625 ixgbe_napi_disable_all(adapter);
5626
57ca2a4f
ET		 5627 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
5628 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7086400d
AD		 5629 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5630
5631 del_timer_sync(&adapter->service_timer);
5632
34cecbbf 5633 if (adapter->num_vfs) {
8e34d1aa
AD		 5634 /* Clear EITR Select mapping */
5635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5636
5637 /* Mark all the VFs as inactive */
5638 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5639 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5640
34cecbbf
AD		 5641 /* ping all the active vfs to let them know we are going down */
5642 ixgbe_ping_all_vfs(adapter);
5643
5644 /* Disable all VFTE/VFRE TX/RX */
5645 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5646 }
5647
7f821875
JB		 5648 /* disable transmits in the hardware now that interrupts are off */
5649 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5650 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5651 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5652 }
34cecbbf 5653
9a75a1ac 5654 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5655 switch (hw->mac.type) {
5656 case ixgbe_mac_82599EB:
b93a2226 5657 case ixgbe_mac_X540:
9a75a1ac
DS		 5658 case ixgbe_mac_X550:
5659 case ixgbe_mac_X550EM_x:
49425dfc 5660 case ixgbe_mac_x550em_a:
88512539 5661 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5662 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5663 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5664 break;
5665 default:
5666 break;
5667 }
7f821875 5668
6f4a0e45
PL		 5669 if (!pci_channel_offline(adapter->pdev))
5670 ixgbe_reset(adapter);
c6ecf39a 5671
ec74a471
ET		 5672 /* power down the optics for 82599 SFP+ fiber */
5673 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5674 hw->mac.ops.disable_tx_laser(hw);
5675
9a799d71
AK		 5676 ixgbe_clean_all_tx_rings(adapter);
5677 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 5678}
5679
b3eb4e18
MR		 5680/**
5681 * ixgbe_eee_capable - helper function to determine EEE support on X550
5682 * @adapter: board private structure
5683 */
5684static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter)
5685{
5686 struct ixgbe_hw *hw = &adapter->hw;
5687
5688 switch (hw->device_id) {
5689 case IXGBE_DEV_ID_X550EM_A_1G_T:
5690 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
5691 if (!hw->phy.eee_speeds_supported)
5692 break;
5693 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE;
5694 if (!hw->phy.eee_speeds_advertised)
5695 break;
5696 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
5697 break;
5698 default:
5699 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE;
5700 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
5701 break;
5702 }
5703}
5704
9a799d71
AK		 5705/**
5706 * ixgbe_tx_timeout - Respond to a Tx Hang
5707 * @netdev: network interface device structure
5708 **/
5709static void ixgbe_tx_timeout(struct net_device *netdev)
5710{
5711 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5712
5713 /* Do the reset outside of interrupt context */
c83c6cbd 5714 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5715}
5716
8829009d
UK		 5717#ifdef CONFIG_IXGBE_DCB
5718static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
5719{
5720 struct ixgbe_hw *hw = &adapter->hw;
5721 struct tc_configuration *tc;
5722 int j;
5723
5724 switch (hw->mac.type) {
5725 case ixgbe_mac_82598EB:
5726 case ixgbe_mac_82599EB:
5727 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5728 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5729 break;
5730 case ixgbe_mac_X540:
5731 case ixgbe_mac_X550:
5732 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5733 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5734 break;
5735 case ixgbe_mac_X550EM_x:
5736 case ixgbe_mac_x550em_a:
5737 default:
5738 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
5739 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
5740 break;
5741 }
5742
5743 /* Configure DCB traffic classes */
5744 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5745 tc = &adapter->dcb_cfg.tc_config[j];
5746 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5747 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5748 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5749 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5750 tc->dcb_pfc = pfc_disabled;
5751 }
5752
5753 /* Initialize default user to priority mapping, UPx->TC0 */
5754 tc = &adapter->dcb_cfg.tc_config[0];
5755 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5756 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5757
5758 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5759 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5760 adapter->dcb_cfg.pfc_mode_enable = false;
5761 adapter->dcb_set_bitmap = 0x00;
5762 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
5763 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5764 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5765 sizeof(adapter->temp_dcb_cfg));
5766}
5767#endif
5768
9a799d71
AK		 5769/**
5770 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5771 * @adapter: board private structure to initialize
5772 *
5773 * ixgbe_sw_init initializes the Adapter private data structure.
5774 * Fields are initialized based on PCI device information and
5775 * OS network device settings (MTU size).
5776 **/
55570b6f
ET		 5777static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
5778 const struct ixgbe_info *ii)
9a799d71
AK		 5779{
5780 struct ixgbe_hw *hw = &adapter->hw;
5781 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5782 unsigned int rss, fdir;
cb6d0f5e 5783 u32 fwsm;
1cdaaf54 5784 int i;
021230d4 5785
c44ade9e
JB		 5786 /* PCI config space info */
5787
5788 hw->vendor_id = pdev->vendor;
5789 hw->device_id = pdev->device;
5790 hw->revision_id = pdev->revision;
5791 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5792 hw->subsystem_device_id = pdev->subsystem_device;
5793
55570b6f
ET		 5794 /* get_invariants needs the device IDs */
5795 ii->get_invariants(hw);
5796
8fc3bb6d 5797 /* Set common capability flags and settings */
0f9b232b 5798 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5799 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 5800 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 5801 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5802 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5803 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5804 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5805 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5806#ifdef CONFIG_IXGBE_DCA
5807 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5808#endif
8829009d
UK		 5809#ifdef CONFIG_IXGBE_DCB
5810 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
5811 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
5812#endif
8fc3bb6d
ET		 5813#ifdef IXGBE_FCOE
5814 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5815 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5816#ifdef CONFIG_IXGBE_DCB
5817 /* Default traffic class to use for FCoE */
5818 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5819#endif /* CONFIG_IXGBE_DCB */
5820#endif /* IXGBE_FCOE */
5821
b82b17d9 5822 /* initialize static ixgbe jump table entries */
1cdaaf54
AN		 5823 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
5824 GFP_KERNEL);
5825 if (!adapter->jump_tables[0])
5826 return -ENOMEM;
5827 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
5828
5829 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
5830 adapter->jump_tables[i] = NULL;
b82b17d9 5831
5d7daa35
JK		 5832 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5833 hw->mac.num_rar_entries,
5834 GFP_ATOMIC);
530fd82a
AD		 5835 if (!adapter->mac_table)
5836 return -ENOMEM;
5d7daa35 5837
8fc3bb6d 5838 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5839 switch (hw->mac.type) {
5840 case ixgbe_mac_82598EB:
8fc3bb6d 5841 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 5842
bf069c97
DS		 5843 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5844 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5845
49c7ffbe 5846 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5847 adapter->ring_feature[RING_F_FDIR].limit = 0;
5848 adapter->atr_sample_rate = 0;
5849 adapter->fdir_pballoc = 0;
5850#ifdef IXGBE_FCOE
5851 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5852 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5853#ifdef CONFIG_IXGBE_DCB
5854 adapter->fcoe.up = 0;
5855#endif /* IXGBE_DCB */
5856#endif /* IXGBE_FCOE */
5857 break;
5858 case ixgbe_mac_82599EB:
5859 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5860 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5861 break;
b93a2226 5862 case ixgbe_mac_X540:
9a900eca 5863 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5864 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5865 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5866 break;
49425dfc 5867 case ixgbe_mac_x550em_a:
a21d0822 5868 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE;
b3eb4e18
MR		 5869 switch (hw->device_id) {
5870 case IXGBE_DEV_ID_X550EM_A_1G_T:
5871 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
5872 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5873 break;
5874 default:
5875 break;
5876 }
a21d0822
ET		 5877 /* fall through */
5878 case ixgbe_mac_X550EM_x:
8829009d
UK		 5879#ifdef CONFIG_IXGBE_DCB
5880 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
5881#endif
5882#ifdef IXGBE_FCOE
5883 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5884#ifdef CONFIG_IXGBE_DCB
5885 adapter->fcoe.up = 0;
5886#endif /* IXGBE_DCB */
5887#endif /* IXGBE_FCOE */
5888 /* Fall Through */
9a75a1ac 5889 case ixgbe_mac_X550:
b3eb4e18
MR		 5890 if (hw->mac.type == ixgbe_mac_X550)
5891 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a75a1ac
DS		 5892#ifdef CONFIG_IXGBE_DCA
5893 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c 5894#endif
67359c3c 5895 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac 5896 break;
bd508178
AD		 5897 default:
5898 break;
f8212f97 5899 }
2f90b865 5900
7c8ae65a
AD		 5901#ifdef IXGBE_FCOE
5902 /* FCoE support exists, always init the FCoE lock */
5903 spin_lock_init(&adapter->fcoe.lock);
5904
5905#endif
1fc5f038
AD		 5906 /* n-tuple support exists, always init our spinlock */
5907 spin_lock_init(&adapter->fdir_perfect_lock);
5908
7a6b6f51 5909#ifdef CONFIG_IXGBE_DCB
8829009d 5910 ixgbe_init_dcb(adapter);
2f90b865 5911#endif
9a799d71
AK		 5912
5913 /* default flow control settings */
cd7664f6 5914 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5915 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5916 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5917 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5918 hw->fc.send_xon = true;
73d80953 5919 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5920
99d74487 5921#ifdef CONFIG_PCI_IOV
170e8543
JK		 5922 if (max_vfs > 0)
5923 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5924
99d74487 5925 /* assign number of SR-IOV VFs */
170e8543 5926 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5927 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5928 adapter->num_vfs = 0;
5929 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5930 } else {
5931 adapter->num_vfs = max_vfs;
5932 }
5933 }
5934#endif /* CONFIG_PCI_IOV */
99d74487 5935
30efa5a3 5936 /* enable itr by default in dynamic mode */
f7554a2b 5937 adapter->rx_itr_setting = 1;
f7554a2b 5938 adapter->tx_itr_setting = 1;
30efa5a3 5939
30efa5a3
JB		 5940 /* set default ring sizes */
5941 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5942 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5943
bd198058 5944 /* set default work limits */
59224555 5945 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5946
9a799d71 5947 /* initialize eeprom parameters */
c44ade9e 5948 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5949 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5950 return -EIO;
5951 }
5952
2a47fa45
JF		 5953 /* PF holds first pool slot */
5954 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5955 set_bit(__IXGBE_DOWN, &adapter->state);
5956
5957 return 0;
5958}
5959
5960/**
5961 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5962 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5963 *
5964 * Return 0 on success, negative on failure
5965 **/
b6ec895e 5966int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5967{
b6ec895e 5968 struct device *dev = tx_ring->dev;
de88eeeb 5969 int orig_node = dev_to_node(dev);
ca8dfe25 5970 int ring_node = -1;
9a799d71
AK		 5971 int size;
5972
3a581073 5973 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5974
5975 if (tx_ring->q_vector)
ca8dfe25 5976 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5977
ca8dfe25 5978 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5979 if (!tx_ring->tx_buffer_info)
89bf67f1 5980 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5981 if (!tx_ring->tx_buffer_info)
5982 goto err;
9a799d71 5983
827da44c
JS		 5984 u64_stats_init(&tx_ring->syncp);
5985
9a799d71 5986 /* round up to nearest 4K */
12207e49 5987 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5988 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5989
ca8dfe25 5990 set_dev_node(dev, ring_node);
de88eeeb
AD		 5991 tx_ring->desc = dma_alloc_coherent(dev,
5992 tx_ring->size,
5993 &tx_ring->dma,
5994 GFP_KERNEL);
5995 set_dev_node(dev, orig_node);
5996 if (!tx_ring->desc)
5997 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5998 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5999 if (!tx_ring->desc)
6000 goto err;
9a799d71 6001
3a581073
JB		 6002 tx_ring->next_to_use = 0;
6003 tx_ring->next_to_clean = 0;
9a799d71 6004 return 0;
e01c31a5
JB		 6005
6006err:
6007 vfree(tx_ring->tx_buffer_info);
6008 tx_ring->tx_buffer_info = NULL;
b6ec895e 6009 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 6010 return -ENOMEM;
9a799d71
AK		 6011}
6012
69888674
AD		 6013/**
6014 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
6015 * @adapter: board private structure
6016 *
6017 * If this function returns with an error, then it's possible one or
6018 * more of the rings is populated (while the rest are not). It is the
6019 * callers duty to clean those orphaned rings.
6020 *
6021 * Return 0 on success, negative on failure
6022 **/
6023static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
6024{
6025 int i, err = 0;
6026
6027 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 6028 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 6029 if (!err)
6030 continue;
de3d5b94 6031
396e799c 6032 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 6033 goto err_setup_tx;
69888674
AD		 6034 }
6035
de3d5b94
AD		 6036 return 0;
6037err_setup_tx:
6038 /* rewind the index freeing the rings as we go */
6039 while (i--)
6040 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 6041 return err;
6042}
6043
9a799d71
AK		 6044/**
6045 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 6046 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 6047 *
6048 * Returns 0 on success, negative on failure
6049 **/
b6ec895e 6050int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 6051{
b6ec895e 6052 struct device *dev = rx_ring->dev;
de88eeeb 6053 int orig_node = dev_to_node(dev);
ca8dfe25 6054 int ring_node = -1;
021230d4 6055 int size;
9a799d71 6056
3a581073 6057 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 6058
6059 if (rx_ring->q_vector)
ca8dfe25 6060 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 6061
ca8dfe25 6062 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 6063 if (!rx_ring->rx_buffer_info)
89bf67f1 6064 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 6065 if (!rx_ring->rx_buffer_info)
6066 goto err;
9a799d71 6067
827da44c
JS		 6068 u64_stats_init(&rx_ring->syncp);
6069
9a799d71 6070 /* Round up to nearest 4K */
3a581073
JB		 6071 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
6072 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 6073
ca8dfe25 6074 set_dev_node(dev, ring_node);
de88eeeb
AD		 6075 rx_ring->desc = dma_alloc_coherent(dev,
6076 rx_ring->size,
6077 &rx_ring->dma,
6078 GFP_KERNEL);
6079 set_dev_node(dev, orig_node);
6080 if (!rx_ring->desc)
6081 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
6082 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 6083 if (!rx_ring->desc)
6084 goto err;
9a799d71 6085
3a581073
JB		 6086 rx_ring->next_to_clean = 0;
6087 rx_ring->next_to_use = 0;
9a799d71
AK		 6088
6089 return 0;
b6ec895e
AD		 6090err:
6091 vfree(rx_ring->rx_buffer_info);
6092 rx_ring->rx_buffer_info = NULL;
6093 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 6094 return -ENOMEM;
9a799d71
AK		 6095}
6096
69888674
AD		 6097/**
6098 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
6099 * @adapter: board private structure
6100 *
6101 * If this function returns with an error, then it's possible one or
6102 * more of the rings is populated (while the rest are not). It is the
6103 * callers duty to clean those orphaned rings.
6104 *
6105 * Return 0 on success, negative on failure
6106 **/
69888674
AD		 6107static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
6108{
6109 int i, err = 0;
6110
6111 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 6112 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 6113 if (!err)
6114 continue;
de3d5b94 6115
396e799c 6116 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 6117 goto err_setup_rx;
69888674
AD		 6118 }
6119
7c8ae65a
AD		 6120#ifdef IXGBE_FCOE
6121 err = ixgbe_setup_fcoe_ddp_resources(adapter);
6122 if (!err)
6123#endif
6124 return 0;
de3d5b94
AD		 6125err_setup_rx:
6126 /* rewind the index freeing the rings as we go */
6127 while (i--)
6128 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 6129 return err;
6130}
6131
9a799d71
AK		 6132/**
6133 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 6134 * @tx_ring: Tx descriptor ring for a specific queue
6135 *
6136 * Free all transmit software resources
6137 **/
b6ec895e 6138void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 6139{
b6ec895e 6140 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 6141
6142 vfree(tx_ring->tx_buffer_info);
6143 tx_ring->tx_buffer_info = NULL;
6144
b6ec895e
AD		 6145 /* if not set, then don't free */
6146 if (!tx_ring->desc)
6147 return;
6148
6149 dma_free_coherent(tx_ring->dev, tx_ring->size,
6150 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 6151
6152 tx_ring->desc = NULL;
6153}
6154
6155/**
6156 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
6157 * @adapter: board private structure
6158 *
6159 * Free all transmit software resources
6160 **/
6161static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6162{
6163 int i;
6164
6165 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 6166 if (adapter->tx_ring[i]->desc)
b6ec895e 6167 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 6168}
6169
6170/**
b4617240 6171 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 6172 * @rx_ring: ring to clean the resources from
6173 *
6174 * Free all receive software resources
6175 **/
b6ec895e 6176void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 6177{
b6ec895e 6178 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 6179
6180 vfree(rx_ring->rx_buffer_info);
6181 rx_ring->rx_buffer_info = NULL;
6182
b6ec895e
AD		 6183 /* if not set, then don't free */
6184 if (!rx_ring->desc)
6185 return;
6186
6187 dma_free_coherent(rx_ring->dev, rx_ring->size,
6188 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 6189
6190 rx_ring->desc = NULL;
6191}
6192
6193/**
6194 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6195 * @adapter: board private structure
6196 *
6197 * Free all receive software resources
6198 **/
6199static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6200{
6201 int i;
6202
7c8ae65a
AD		 6203#ifdef IXGBE_FCOE
6204 ixgbe_free_fcoe_ddp_resources(adapter);
6205
6206#endif
9a799d71 6207 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 6208 if (adapter->rx_ring[i]->desc)
b6ec895e 6209 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 6210}
6211
9a799d71
AK		 6212/**
6213 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6214 * @netdev: network interface device structure
6215 * @new_mtu: new value for maximum frame size
6216 *
6217 * Returns 0 on success, negative on failure
6218 **/
6219static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6220{
6221 struct ixgbe_adapter *adapter = netdev_priv(netdev);
655309e9
AD		 6222
6223 /*
872844dd
AD		 6224 * For 82599EB we cannot allow legacy VFs to enable their receive
6225 * paths when MTU greater than 1500 is configured. So display a
6226 * warning that legacy VFs will be disabled.
655309e9
AD		 6227 */
6228 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6229 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
91c527a5 6230 (new_mtu > ETH_DATA_LEN))
872844dd 6231 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 6232
396e799c 6233 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 6234
021230d4 6235 /* must set new MTU before calling down or up */
9a799d71
AK		 6236 netdev->mtu = new_mtu;
6237
d4f80882
AV		 6238 if (netif_running(netdev))
6239 ixgbe_reinit_locked(adapter);
9a799d71
AK		 6240
6241 return 0;
6242}
6243
6244/**
6245 * ixgbe_open - Called when a network interface is made active
6246 * @netdev: network interface device structure
6247 *
6248 * Returns 0 on success, negative value on failure
6249 *
6250 * The open entry point is called when a network interface is made
6251 * active by the system (IFF_UP). At this point all resources needed
6252 * for transmit and receive operations are allocated, the interrupt
6253 * handler is registered with the OS, the watchdog timer is started,
6254 * and the stack is notified that the interface is ready.
6255 **/
6c211fe1 6256int ixgbe_open(struct net_device *netdev)
9a799d71
AK		 6257{
6258 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 6259 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 6260 int err, queues;
4bebfaa5
AK		 6261
6262 /* disallow open during test */
6263 if (test_bit(__IXGBE_TESTING, &adapter->state))
6264 return -EBUSY;
9a799d71 6265
54386467
JB		 6266 netif_carrier_off(netdev);
6267
9a799d71
AK		 6268 /* allocate transmit descriptors */
6269 err = ixgbe_setup_all_tx_resources(adapter);
6270 if (err)
6271 goto err_setup_tx;
6272
9a799d71
AK		 6273 /* allocate receive descriptors */
6274 err = ixgbe_setup_all_rx_resources(adapter);
6275 if (err)
6276 goto err_setup_rx;
6277
6278 ixgbe_configure(adapter);
6279
021230d4 6280 err = ixgbe_request_irq(adapter);
9a799d71
AK		 6281 if (err)
6282 goto err_req_irq;
6283
ac802f5d 6284 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 6285 if (adapter->num_rx_pools > 1)
6286 queues = adapter->num_rx_queues_per_pool;
6287 else
6288 queues = adapter->num_tx_queues;
6289
6290 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 6291 if (err)
6292 goto err_set_queues;
6293
2a47fa45
JF		 6294 if (adapter->num_rx_pools > 1 &&
6295 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6296 queues = IXGBE_MAX_L2A_QUEUES;
6297 else
6298 queues = adapter->num_rx_queues;
6299 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 6300 if (err)
6301 goto err_set_queues;
6302
1a71ab24 6303 ixgbe_ptp_init(adapter);
1a71ab24 6304
c7ccde0f 6305 ixgbe_up_complete(adapter);
9a799d71 6306
a21d0822 6307 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK);
b3a49557 6308 udp_tunnel_get_rx_info(netdev);
67359c3c 6309
9a799d71
AK		 6310 return 0;
6311
ac802f5d
AD		 6312err_set_queues:
6313 ixgbe_free_irq(adapter);
9a799d71 6314err_req_irq:
a20a1199 6315 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 6316 if (hw->phy.ops.set_phy_power && !adapter->wol)
6317 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 6318err_setup_rx:
a20a1199 6319 ixgbe_free_all_tx_resources(adapter);
de3d5b94 6320err_setup_tx:
9a799d71
AK		 6321 ixgbe_reset(adapter);
6322
6323 return err;
6324}
6325
a0cccce2
JK		 6326static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6327{
6328 ixgbe_ptp_suspend(adapter);
6329
6ac74394
DS		 6330 if (adapter->hw.phy.ops.enter_lplu) {
6331 adapter->hw.phy.reset_disable = true;
6332 ixgbe_down(adapter);
6333 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6334 adapter->hw.phy.reset_disable = false;
6335 } else {
6336 ixgbe_down(adapter);
6337 }
6338
a0cccce2
JK		 6339 ixgbe_free_irq(adapter);
6340
6341 ixgbe_free_all_tx_resources(adapter);
6342 ixgbe_free_all_rx_resources(adapter);
6343}
6344
9a799d71
AK		 6345/**
6346 * ixgbe_close - Disables a network interface
6347 * @netdev: network interface device structure
6348 *
6349 * Returns 0, this is not allowed to fail
6350 *
6351 * The close entry point is called when an interface is de-activated
6352 * by the OS. The hardware is still under the drivers control, but
6353 * needs to be disabled. A global MAC reset is issued to stop the
6354 * hardware, and all transmit and receive resources are freed.
6355 **/
6c211fe1 6356int ixgbe_close(struct net_device *netdev)
9a799d71
AK		 6357{
6358 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 6359
1a71ab24 6360 ixgbe_ptp_stop(adapter);
1a71ab24 6361
f7f37e7f
ET		 6362 if (netif_device_present(netdev))
6363 ixgbe_close_suspend(adapter);
9a799d71 6364
e4911d57
AD		 6365 ixgbe_fdir_filter_exit(adapter);
6366
5eba3699 6367 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6368
6369 return 0;
6370}
6371
b3c8b4ba
AD		 6372#ifdef CONFIG_PM
6373static int ixgbe_resume(struct pci_dev *pdev)
6374{
c60fbb00
AD		 6375 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6376 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 6377 u32 err;
6378
0391bbe3 6379 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 6380 pci_set_power_state(pdev, PCI_D0);
6381 pci_restore_state(pdev);
656ab817
DS		 6382 /*
6383 * pci_restore_state clears dev->state_saved so call
6384 * pci_save_state to restore it.
6385 */
6386 pci_save_state(pdev);
9ce77666 6387
6388 err = pci_enable_device_mem(pdev);
b3c8b4ba 6389 if (err) {
849c4542 6390 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 6391 return err;
6392 }
4e857c58 6393 smp_mb__before_atomic();
41c62843 6394 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 6395 pci_set_master(pdev);
6396
dd4d8ca6 6397 pci_wake_from_d3(pdev, false);
b3c8b4ba 6398
b3c8b4ba
AD		 6399 ixgbe_reset(adapter);
6400
495dce12
WJP		 6401 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6402
ac802f5d
AD		 6403 rtnl_lock();
6404 err = ixgbe_init_interrupt_scheme(adapter);
6405 if (!err && netif_running(netdev))
c60fbb00 6406 err = ixgbe_open(netdev);
ac802f5d 6407
ac802f5d 6408
f7f37e7f
ET		 6409 if (!err)
6410 netif_device_attach(netdev);
6411 rtnl_unlock();
b3c8b4ba 6412
f7f37e7f 6413 return err;
b3c8b4ba 6414}
b3c8b4ba 6415#endif /* CONFIG_PM */
9d8d05ae
RW		 6416
6417static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 6418{
c60fbb00
AD		 6419 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6420 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 6421 struct ixgbe_hw *hw = &adapter->hw;
6422 u32 ctrl, fctrl;
6423 u32 wufc = adapter->wol;
b3c8b4ba
AD		 6424#ifdef CONFIG_PM
6425 int retval = 0;
6426#endif
6427
f7f37e7f 6428 rtnl_lock();
b3c8b4ba
AD		 6429 netif_device_detach(netdev);
6430
a0cccce2
JK		 6431 if (netif_running(netdev))
6432 ixgbe_close_suspend(adapter);
b3c8b4ba 6433
5f5ae6fc 6434 ixgbe_clear_interrupt_scheme(adapter);
f7f37e7f 6435 rtnl_unlock();
5f5ae6fc 6436
b3c8b4ba
AD		 6437#ifdef CONFIG_PM
6438 retval = pci_save_state(pdev);
6439 if (retval)
6440 return retval;
4df10466 6441
b3c8b4ba 6442#endif
f4f1040a
JK		 6443 if (hw->mac.ops.stop_link_on_d3)
6444 hw->mac.ops.stop_link_on_d3(hw);
6445
e8e26350
PW		 6446 if (wufc) {
6447 ixgbe_set_rx_mode(netdev);
b3c8b4ba 6448
ec74a471
ET		 6449 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6450 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 6451 hw->mac.ops.enable_tx_laser(hw);
6452
e8e26350
PW		 6453 /* turn on all-multi mode if wake on multicast is enabled */
6454 if (wufc & IXGBE_WUFC_MC) {
6455 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6456 fctrl |= IXGBE_FCTRL_MPE;
6457 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6458 }
6459
6460 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6461 ctrl |= IXGBE_CTRL_GIO_DIS;
6462 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6463
6464 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6465 } else {
6466 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6467 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6468 }
6469
bd508178
AD		 6470 switch (hw->mac.type) {
6471 case ixgbe_mac_82598EB:
dd4d8ca6 6472 pci_wake_from_d3(pdev, false);
bd508178
AD		 6473 break;
6474 case ixgbe_mac_82599EB:
b93a2226 6475 case ixgbe_mac_X540:
9a75a1ac
DS		 6476 case ixgbe_mac_X550:
6477 case ixgbe_mac_X550EM_x:
49425dfc 6478 case ixgbe_mac_x550em_a:
bd508178
AD		 6479 pci_wake_from_d3(pdev, !!wufc);
6480 break;
6481 default:
6482 break;
6483 }
b3c8b4ba 6484
9d8d05ae 6485 *enable_wake = !!wufc;
961fac88
DS		 6486 if (hw->phy.ops.set_phy_power && !*enable_wake)
6487 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6488
b3c8b4ba
AD		 6489 ixgbe_release_hw_control(adapter);
6490
41c62843
MR		 6491 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6492 pci_disable_device(pdev);
b3c8b4ba 6493
9d8d05ae
RW		 6494 return 0;
6495}
6496
6497#ifdef CONFIG_PM
6498static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6499{
6500 int retval;
6501 bool wake;
6502
6503 retval = __ixgbe_shutdown(pdev, &wake);
6504 if (retval)
6505 return retval;
6506
6507 if (wake) {
6508 pci_prepare_to_sleep(pdev);
6509 } else {
6510 pci_wake_from_d3(pdev, false);
6511 pci_set_power_state(pdev, PCI_D3hot);
6512 }
b3c8b4ba
AD		 6513
6514 return 0;
6515}
9d8d05ae 6516#endif /* CONFIG_PM */
b3c8b4ba
AD		 6517
6518static void ixgbe_shutdown(struct pci_dev *pdev)
6519{
9d8d05ae
RW		 6520 bool wake;
6521
6522 __ixgbe_shutdown(pdev, &wake);
6523
6524 if (system_state == SYSTEM_POWER_OFF) {
6525 pci_wake_from_d3(pdev, wake);
6526 pci_set_power_state(pdev, PCI_D3hot);
6527 }
b3c8b4ba
AD		 6528}
6529
9a799d71
AK		 6530/**
6531 * ixgbe_update_stats - Update the board statistics counters.
6532 * @adapter: board private structure
6533 **/
6534void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6535{
2d86f139 6536 struct net_device *netdev = adapter->netdev;
9a799d71 6537 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6538 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6539 u64 total_mpc = 0;
6540 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6541 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6542 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6543 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6544
d08935c2
DS		 6545 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6546 test_bit(__IXGBE_RESETTING, &adapter->state))
6547 return;
6548
94b982b2 6549 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6550 u64 rsc_count = 0;
94b982b2 6551 u64 rsc_flush = 0;
94b982b2 6552 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6553 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6554 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6555 }
6556 adapter->rsc_total_count = rsc_count;
6557 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6558 }
6559
5b7da515
AD		 6560 for (i = 0; i < adapter->num_rx_queues; i++) {
6561 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6562 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6563 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6564 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6565 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6566 bytes += rx_ring->stats.bytes;
6567 packets += rx_ring->stats.packets;
6568 }
6569 adapter->non_eop_descs = non_eop_descs;
6570 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6571 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6572 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6573 netdev->stats.rx_bytes = bytes;
6574 netdev->stats.rx_packets = packets;
6575
6576 bytes = 0;
6577 packets = 0;
7ca3bc58 6578 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6579 for (i = 0; i < adapter->num_tx_queues; i++) {
6580 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6581 restart_queue += tx_ring->tx_stats.restart_queue;
6582 tx_busy += tx_ring->tx_stats.tx_busy;
6583 bytes += tx_ring->stats.bytes;
6584 packets += tx_ring->stats.packets;
6585 }
eb985f09 6586 adapter->restart_queue = restart_queue;
5b7da515
AD		 6587 adapter->tx_busy = tx_busy;
6588 netdev->stats.tx_bytes = bytes;
6589 netdev->stats.tx_packets = packets;
7ca3bc58 6590
7ca647bd 6591 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6592
6593 /* 8 register reads */
6f11eef7
AV		 6594 for (i = 0; i < 8; i++) {
6595 /* for packet buffers not used, the register should read 0 */
6596 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6597 missed_rx += mpc;
7ca647bd
JP		 6598 hwstats->mpc[i] += mpc;
6599 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6600 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6601 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6602 switch (hw->mac.type) {
6603 case ixgbe_mac_82598EB:
1a70db4b
ET		 6604 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6605 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6606 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6607 hwstats->pxonrxc[i] +=
6608 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6609 break;
6610 case ixgbe_mac_82599EB:
b93a2226 6611 case ixgbe_mac_X540:
9a75a1ac
DS		 6612 case ixgbe_mac_X550:
6613 case ixgbe_mac_X550EM_x:
49425dfc 6614 case ixgbe_mac_x550em_a:
bd508178
AD		 6615 hwstats->pxonrxc[i] +=
6616 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6617 break;
6618 default:
6619 break;
e8e26350 6620 }
6f11eef7 6621 }
1a70db4b
ET		 6622
6623 /*16 register reads */
6624 for (i = 0; i < 16; i++) {
6625 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6626 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6627 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6628 (hw->mac.type == ixgbe_mac_X540) ||
6629 (hw->mac.type == ixgbe_mac_X550) ||
49425dfc
MR		 6630 (hw->mac.type == ixgbe_mac_X550EM_x) ||
6631 (hw->mac.type == ixgbe_mac_x550em_a)) {
1a70db4b
ET		 6632 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6633 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6634 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6635 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6636 }
6637 }
6638
7ca647bd 6639 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6640 /* work around hardware counting issue */
7ca647bd 6641 hwstats->gprc -= missed_rx;
6f11eef7 6642
c84d324c
JF		 6643 ixgbe_update_xoff_received(adapter);
6644
6f11eef7 6645 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6646 switch (hw->mac.type) {
6647 case ixgbe_mac_82598EB:
6648 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6649 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6650 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6651 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6652 break;
b93a2226 6653 case ixgbe_mac_X540:
9a75a1ac
DS		 6654 case ixgbe_mac_X550:
6655 case ixgbe_mac_X550EM_x:
49425dfc 6656 case ixgbe_mac_x550em_a:
9a75a1ac 6657 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6658 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6659 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6660 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6661 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6662 case ixgbe_mac_82599EB:
a4d4f629
AD		 6663 for (i = 0; i < 16; i++)
6664 adapter->hw_rx_no_dma_resources +=
6665 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6666 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6667 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6668 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6669 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6670 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6671 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6672 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6673 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6674 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6675#ifdef IXGBE_FCOE
7ca647bd
JP		 6676 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6677 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6678 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6679 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6680 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6681 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6682 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6683 if (adapter->fcoe.ddp_pool) {
6684 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6685 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6686 unsigned int cpu;
6687 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6688 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6689 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6690 noddp += ddp_pool->noddp;
6691 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6692 }
5a1ee270
AD		 6693 hwstats->fcoe_noddp = noddp;
6694 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6695 }
6d45522c 6696#endif /* IXGBE_FCOE */
bd508178
AD		 6697 break;
6698 default:
6699 break;
e8e26350 6700 }
9a799d71 6701 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6702 hwstats->bprc += bprc;
6703 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6704 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6705 hwstats->mprc -= bprc;
6706 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6707 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6708 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6709 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6710 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6711 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6712 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6713 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6714 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6715 hwstats->lxontxc += lxon;
6f11eef7 6716 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6717 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6718 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6719 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6720 /*
6721 * 82598 errata - tx of flow control packets is included in tx counters
6722 */
6723 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6724 hwstats->gptc -= xon_off_tot;
6725 hwstats->mptc -= xon_off_tot;
6726 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6727 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6728 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6729 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6730 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6731 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6732 hwstats->ptc64 -= xon_off_tot;
6733 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6734 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6735 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6736 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6737 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6738 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6739
6740 /* Fill out the OS statistics structure */
7ca647bd 6741 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6742
6743 /* Rx Errors */
7ca647bd 6744 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6745 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6746 netdev->stats.rx_length_errors = hwstats->rlec;
6747 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6748 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6749}
6750
6751/**
d034acf1 6752 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6753 * @adapter: pointer to the device adapter structure
9a799d71 6754 **/
d034acf1 6755static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6756{
cf8280ee 6757 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6758 int i;
cf8280ee 6759
d034acf1
AD		 6760 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6761 return;
6762
6763 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6764
d034acf1 6765 /* if interface is down do nothing */
fe49f04a 6766 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6767 return;
6768
6769 /* do nothing if we are not using signature filters */
6770 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6771 return;
6772
6773 adapter->fdir_overflow++;
6774
93c52dd0
AD		 6775 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6776 for (i = 0; i < adapter->num_tx_queues; i++)
6777 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6778 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6779 /* re-enable flow director interrupts */
6780 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6781 } else {
6782 e_err(probe, "failed to finish FDIR re-initialization, "
6783 "ignored adding FDIR ATR filters\n");
6784 }
93c52dd0
AD		 6785}
6786
6787/**
6788 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6789 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6790 *
6791 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6792 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6793 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6794 * determine if a hang has occurred.
93c52dd0
AD		 6795 */
6796static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6797{
cf8280ee 6798 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6799 u64 eics = 0;
6800 int i;
cf8280ee 6801
09f40aed 6802 /* If we're down, removing or resetting, just bail */
93c52dd0 6803 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6804 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6805 test_bit(__IXGBE_RESETTING, &adapter->state))
6806 return;
22d5a71b 6807
93c52dd0
AD		 6808 /* Force detection of hung controller */
6809 if (netif_carrier_ok(adapter->netdev)) {
6810 for (i = 0; i < adapter->num_tx_queues; i++)
6811 set_check_for_tx_hang(adapter->tx_ring[i]);
6812 }
22d5a71b 6813
fe49f04a
AD		 6814 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6815 /*
6816 * for legacy and MSI interrupts don't set any bits
6817 * that are enabled for EIAM, because this operation
6818 * would set *both* EIMS and EICS for any bit in EIAM
6819 */
6820 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6821 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6822 } else {
6823 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6824 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6825 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6826 if (qv->rx.ring || qv->tx.ring)
b4f47a48 6827 eics |= BIT_ULL(i);
93c52dd0 6828 }
cf8280ee 6829 }
9a799d71 6830
93c52dd0 6831 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6832 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6833}
6834
e8e26350 6835/**
93c52dd0 6836 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6837 * @adapter: pointer to the device adapter structure
6838 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6839 **/
93c52dd0 6840static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6841{
e8e26350 6842 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6843 u32 link_speed = adapter->link_speed;
6844 bool link_up = adapter->link_up;
041441d0 6845 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6846
93c52dd0
AD		 6847 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6848 return;
6849
6850 if (hw->mac.ops.check_link) {
6851 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6852 } else {
93c52dd0
AD		 6853 /* always assume link is up, if no check link function */
6854 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6855 link_up = true;
c4cf55e5 6856 }
041441d0
AD		 6857
6858 if (adapter->ixgbe_ieee_pfc)
6859 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6860
3ebe8fde 6861 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6862 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6863 ixgbe_set_rx_drop_en(adapter);
6864 }
93c52dd0
AD		 6865
6866 if (link_up ||
6867 time_after(jiffies, (adapter->link_check_timeout +
6868 IXGBE_TRY_LINK_TIMEOUT))) {
6869 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6870 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6871 IXGBE_WRITE_FLUSH(hw);
6872 }
6873
6874 adapter->link_up = link_up;
6875 adapter->link_speed = link_speed;
e8e26350
PW		 6876}
6877
107d3018
AD		 6878static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6879{
6880#ifdef CONFIG_IXGBE_DCB
6881 struct net_device *netdev = adapter->netdev;
6882 struct dcb_app app = {
6883 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6884 .protocol = 0,
6885 };
6886 u8 up = 0;
6887
6888 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6889 up = dcb_ieee_getapp_mask(netdev, &app);
6890
6891 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6892#endif
6893}
6894
1cd127fc
DA		 6895static int ixgbe_enable_macvlan(struct net_device *upper, void *data)
6896{
6897 if (netif_is_macvlan(upper)) {
6898 struct macvlan_dev *vlan = netdev_priv(upper);
6899
6900 if (vlan->fwd_priv)
6901 netif_tx_wake_all_queues(upper);
6902 }
6903
6904 return 0;
6905}
6906
e8e26350 6907/**
93c52dd0
AD		 6908 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6909 * print link up message
49ce9c2c 6910 * @adapter: pointer to the device adapter structure
e8e26350 6911 **/
93c52dd0 6912static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6913{
93c52dd0 6914 struct net_device *netdev = adapter->netdev;
e8e26350 6915 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0 6916 u32 link_speed = adapter->link_speed;
454adb00 6917 const char *speed_str;
93c52dd0 6918 bool flow_rx, flow_tx;
e8e26350 6919
93c52dd0
AD		 6920 /* only continue if link was previously down */
6921 if (netif_carrier_ok(netdev))
a985b6c3 6922 return;
63d6e1d8 6923
93c52dd0 6924 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6925
93c52dd0
AD		 6926 switch (hw->mac.type) {
6927 case ixgbe_mac_82598EB: {
6928 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6929 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6930 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6931 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6932 }
6933 break;
6934 case ixgbe_mac_X540:
9a75a1ac
DS		 6935 case ixgbe_mac_X550:
6936 case ixgbe_mac_X550EM_x:
49425dfc 6937 case ixgbe_mac_x550em_a:
93c52dd0
AD		 6938 case ixgbe_mac_82599EB: {
6939 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6940 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6941 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6942 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6943 }
6944 break;
6945 default:
6946 flow_tx = false;
6947 flow_rx = false;
6948 break;
e8e26350 6949 }
3a6a4eda 6950
6cb562d6
JK		 6951 adapter->last_rx_ptp_check = jiffies;
6952
8fecf67c 6953 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6954 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6955
454adb00
MR		 6956 switch (link_speed) {
6957 case IXGBE_LINK_SPEED_10GB_FULL:
6958 speed_str = "10 Gbps";
6959 break;
6960 case IXGBE_LINK_SPEED_2_5GB_FULL:
6961 speed_str = "2.5 Gbps";
6962 break;
6963 case IXGBE_LINK_SPEED_1GB_FULL:
6964 speed_str = "1 Gbps";
6965 break;
6966 case IXGBE_LINK_SPEED_100_FULL:
6967 speed_str = "100 Mbps";
6968 break;
b3eb4e18
MR		 6969 case IXGBE_LINK_SPEED_10_FULL:
6970 speed_str = "10 Mbps";
6971 break;
454adb00
MR		 6972 default:
6973 speed_str = "unknown speed";
6974 break;
6975 }
6976 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6977 ((flow_rx && flow_tx) ? "RX/TX" :
6978 (flow_rx ? "RX" :
6979 (flow_tx ? "TX" : "None"))));
e8e26350 6980
93c52dd0 6981 netif_carrier_on(netdev);
93c52dd0 6982 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6983
cdc04dcc
ET		 6984 /* enable transmits */
6985 netif_tx_wake_all_queues(adapter->netdev);
6986
6987 /* enable any upper devices */
6988 rtnl_lock();
1cd127fc
DA		 6989 netdev_walk_all_upper_dev_rcu(adapter->netdev,
6990 ixgbe_enable_macvlan, NULL);
cdc04dcc
ET		 6991 rtnl_unlock();
6992
107d3018
AD		 6993 /* update the default user priority for VFs */
6994 ixgbe_update_default_up(adapter);
6995
befa2af7
AD		 6996 /* ping all the active vfs to let them know link has changed */
6997 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6998}
6999
c4cf55e5 7000/**
93c52dd0
AD		 7001 * ixgbe_watchdog_link_is_down - update netif_carrier status and
7002 * print link down message
49ce9c2c 7003 * @adapter: pointer to the adapter structure
c4cf55e5 7004 **/
581330ba 7005static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 7006{
cf8280ee 7007 struct net_device *netdev = adapter->netdev;
c4cf55e5 7008 struct ixgbe_hw *hw = &adapter->hw;
10eec955 7009
93c52dd0
AD		 7010 adapter->link_up = false;
7011 adapter->link_speed = 0;
cf8280ee 7012
93c52dd0
AD		 7013 /* only continue if link was up previously */
7014 if (!netif_carrier_ok(netdev))
7015 return;
264857b8 7016
93c52dd0
AD		 7017 /* poll for SFP+ cable when link is down */
7018 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
7019 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 7020
8fecf67c 7021 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 7022 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 7023
93c52dd0
AD		 7024 e_info(drv, "NIC Link is Down\n");
7025 netif_carrier_off(netdev);
befa2af7
AD		 7026
7027 /* ping all the active vfs to let them know link has changed */
7028 ixgbe_ping_all_vfs(adapter);
93c52dd0 7029}
e8e26350 7030
07923c17
ET		 7031static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
7032{
7033 int i;
7034
7035 for (i = 0; i < adapter->num_tx_queues; i++) {
7036 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
7037
7038 if (tx_ring->next_to_use != tx_ring->next_to_clean)
7039 return true;
7040 }
7041
7042 return false;
7043}
7044
7045static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
7046{
7047 struct ixgbe_hw *hw = &adapter->hw;
7048 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
7049 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
7050
7051 int i, j;
7052
7053 if (!adapter->num_vfs)
7054 return false;
7055
9a75a1ac
DS		 7056 /* resetting the PF is only needed for MAC before X550 */
7057 if (hw->mac.type >= ixgbe_mac_X550)
7058 return false;
7059
07923c17
ET		 7060 for (i = 0; i < adapter->num_vfs; i++) {
7061 for (j = 0; j < q_per_pool; j++) {
7062 u32 h, t;
7063
7064 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
7065 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
7066
7067 if (h != t)
7068 return true;
7069 }
7070 }
7071
7072 return false;
7073}
7074
93c52dd0
AD		 7075/**
7076 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 7077 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 7078 **/
7079static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
7080{
93c52dd0 7081 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 7082 if (ixgbe_ring_tx_pending(adapter) ||
7083 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 7084 /* We've lost link, so the controller stops DMA,
7085 * but we've got queued Tx work that's never going
7086 * to get done, so reset controller to flush Tx.
7087 * (Do the reset outside of interrupt context).
7088 */
12ff3f3b 7089 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
57ca2a4f 7090 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
bc59fcda 7091 }
c4cf55e5 7092 }
c4cf55e5
PWJ		 7093}
7094
9079e416
ET		 7095#ifdef CONFIG_PCI_IOV
7096static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
7097 struct pci_dev *vfdev)
7098{
7099 if (!pci_wait_for_pending_transaction(vfdev))
7100 e_dev_warn("Issuing VFLR with pending transactions\n");
7101
7102 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
7103 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
7104
7105 msleep(100);
7106}
7107
7108static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
7109{
7110 struct ixgbe_hw *hw = &adapter->hw;
7111 struct pci_dev *pdev = adapter->pdev;
988d1307 7112 unsigned int vf;
9079e416 7113 u32 gpc;
9079e416
ET		 7114
7115 if (!(netif_carrier_ok(adapter->netdev)))
7116 return;
7117
7118 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
7119 if (gpc) /* If incrementing then no need for the check below */
7120 return;
7121 /* Check to see if a bad DMA write target from an errant or
7122 * malicious VF has caused a PCIe error. If so then we can
7123 * issue a VFLR to the offending VF(s) and then resume without
7124 * requesting a full slot reset.
7125 */
7126
7127 if (!pdev)
7128 return;
7129
9079e416 7130 /* check status reg for all VFs owned by this PF */
988d1307
MR		 7131 for (vf = 0; vf < adapter->num_vfs; ++vf) {
7132 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
7133 u16 status_reg;
9079e416 7134
988d1307
MR		 7135 if (!vfdev)
7136 continue;
7137 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
7138 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
7139 status_reg & PCI_STATUS_REC_MASTER_ABORT)
7140 ixgbe_issue_vf_flr(adapter, vfdev);
9079e416
ET		 7141 }
7142}
7143
a985b6c3
GR		 7144static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
7145{
7146 u32 ssvpc;
7147
0584d999
GR		 7148 /* Do not perform spoof check for 82598 or if not in IOV mode */
7149 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7150 adapter->num_vfs == 0)
a985b6c3
GR		 7151 return;
7152
7153 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
7154
7155 /*
7156 * ssvpc register is cleared on read, if zero then no
7157 * spoofed packets in the last interval.
7158 */
7159 if (!ssvpc)
7160 return;
7161
d6ea0754 7162 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 7163}
9079e416
ET		 7164#else
7165static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7166{
7167}
7168
7169static void
7170ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7171{
7172}
7173#endif /* CONFIG_PCI_IOV */
7174
a985b6c3 7175
93c52dd0
AD		 7176/**
7177 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 7178 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 7179 **/
7180static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7181{
09f40aed 7182 /* if interface is down, removing or resetting, do nothing */
7edebf9a 7183 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7184 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 7185 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 7186 return;
7187
7188 ixgbe_watchdog_update_link(adapter);
7189
7190 if (adapter->link_up)
7191 ixgbe_watchdog_link_is_up(adapter);
7192 else
7193 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 7194
9079e416 7195 ixgbe_check_for_bad_vf(adapter);
a985b6c3 7196 ixgbe_spoof_check(adapter);
9a799d71 7197 ixgbe_update_stats(adapter);
93c52dd0
AD		 7198
7199 ixgbe_watchdog_flush_tx(adapter);
9a799d71 7200}
10eec955 7201
cf8280ee 7202/**
7086400d 7203 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 7204 * @adapter: the ixgbe adapter structure
cf8280ee 7205 **/
7086400d 7206static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 7207{
cf8280ee 7208 struct ixgbe_hw *hw = &adapter->hw;
7086400d 7209 s32 err;
cf8280ee 7210
7086400d
AD		 7211 /* not searching for SFP so there is nothing to do here */
7212 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7213 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7214 return;
10eec955 7215
58e7cd24
MR		 7216 if (adapter->sfp_poll_time &&
7217 time_after(adapter->sfp_poll_time, jiffies))
7218 return; /* If not yet time to poll for SFP */
7219
7086400d
AD		 7220 /* someone else is in init, wait until next service event */
7221 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7222 return;
cf8280ee 7223
58e7cd24
MR		 7224 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7225
7086400d
AD		 7226 err = hw->phy.ops.identify_sfp(hw);
7227 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7228 goto sfp_out;
264857b8 7229
7086400d
AD		 7230 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7231 /* If no cable is present, then we need to reset
7232 * the next time we find a good cable. */
7233 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 7234 }
9a799d71 7235
7086400d
AD		 7236 /* exit on error */
7237 if (err)
7238 goto sfp_out;
e8e26350 7239
7086400d
AD		 7240 /* exit if reset not needed */
7241 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7242 goto sfp_out;
9a799d71 7243
7086400d 7244 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 7245
7086400d
AD		 7246 /*
7247 * A module may be identified correctly, but the EEPROM may not have
7248 * support for that module. setup_sfp() will fail in that case, so
7249 * we should not allow that module to load.
7250 */
7251 if (hw->mac.type == ixgbe_mac_82598EB)
7252 err = hw->phy.ops.reset(hw);
7253 else
7254 err = hw->mac.ops.setup_sfp(hw);
7255
7256 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7257 goto sfp_out;
7258
7259 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7260 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7261
7262sfp_out:
7263 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7264
7265 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7266 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7267 e_dev_err("failed to initialize because an unsupported "
7268 "SFP+ module type was detected.\n");
7269 e_dev_err("Reload the driver after installing a "
7270 "supported module.\n");
7271 unregister_netdev(adapter->netdev);
bc59fcda 7272 }
7086400d 7273}
bc59fcda 7274
7086400d
AD		 7275/**
7276 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 7277 * @adapter: the ixgbe adapter structure
7086400d
AD		 7278 **/
7279static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7280{
7281 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 7282 u32 speed;
7283 bool autoneg = false;
7086400d
AD		 7284
7285 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7286 return;
7287
7288 /* someone else is in init, wait until next service event */
7289 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7290 return;
7291
7292 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7293
3d292265 7294 speed = hw->phy.autoneg_advertised;
ed33ff66 7295 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 7296 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 7297
7298 /* setup the highest link when no autoneg */
7299 if (!autoneg) {
7300 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7301 speed = IXGBE_LINK_SPEED_10GB_FULL;
7302 }
7303 }
7304
7086400d 7305 if (hw->mac.ops.setup_link)
fd0326f2 7306 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 7307
7308 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7309 adapter->link_check_timeout = jiffies;
7310 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7311}
7312
7313/**
7314 * ixgbe_service_timer - Timer Call-back
7315 * @data: pointer to adapter cast into an unsigned long
7316 **/
7317static void ixgbe_service_timer(unsigned long data)
7318{
7319 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7320 unsigned long next_event_offset;
7321
6bb78cfb
AD		 7322 /* poll faster when waiting for link */
7323 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7324 next_event_offset = HZ / 10;
7325 else
7326 next_event_offset = HZ * 2;
83c61fa9 7327
7086400d
AD		 7328 /* Reset the timer */
7329 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7330
9079e416 7331 ixgbe_service_event_schedule(adapter);
7086400d
AD		 7332}
7333
597f22d6
DS		 7334static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7335{
7336 struct ixgbe_hw *hw = &adapter->hw;
7337 u32 status;
7338
7339 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7340 return;
7341
7342 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7343
7344 if (!hw->phy.ops.handle_lasi)
7345 return;
7346
7347 status = hw->phy.ops.handle_lasi(&adapter->hw);
7348 if (status != IXGBE_ERR_OVERTEMP)
7349 return;
7350
7351 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7352}
7353
c83c6cbd
AD		 7354static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7355{
57ca2a4f 7356 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
c83c6cbd
AD		 7357 return;
7358
09f40aed 7359 /* If we're already down, removing or resetting, just bail */
c83c6cbd 7360 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7361 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 7362 test_bit(__IXGBE_RESETTING, &adapter->state))
7363 return;
7364
7365 ixgbe_dump(adapter);
7366 netdev_err(adapter->netdev, "Reset adapter\n");
7367 adapter->tx_timeout_count++;
7368
8f4c5c9f 7369 rtnl_lock();
c83c6cbd 7370 ixgbe_reinit_locked(adapter);
8f4c5c9f 7371 rtnl_unlock();
c83c6cbd
AD		 7372}
7373
7086400d
AD		 7374/**
7375 * ixgbe_service_task - manages and runs subtasks
7376 * @work: pointer to work_struct containing our data
7377 **/
7378static void ixgbe_service_task(struct work_struct *work)
7379{
7380 struct ixgbe_adapter *adapter = container_of(work,
7381 struct ixgbe_adapter,
7382 service_task);
b0483c8f
MR		 7383 if (ixgbe_removed(adapter->hw.hw_addr)) {
7384 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7385 rtnl_lock();
7386 ixgbe_down(adapter);
7387 rtnl_unlock();
7388 }
7389 ixgbe_service_event_complete(adapter);
7390 return;
7391 }
a21d0822 7392 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) {
b3a49557 7393 rtnl_lock();
a21d0822 7394 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
b3a49557
AD		 7395 udp_tunnel_get_rx_info(adapter->netdev);
7396 rtnl_unlock();
67359c3c 7397 }
c83c6cbd 7398 ixgbe_reset_subtask(adapter);
597f22d6 7399 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 7400 ixgbe_sfp_detection_subtask(adapter);
7401 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 7402 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 7403 ixgbe_watchdog_subtask(adapter);
d034acf1 7404 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 7405 ixgbe_check_hang_subtask(adapter);
891dc082 7406
8fecf67c 7407 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 7408 ixgbe_ptp_overflow_check(adapter);
7409 ixgbe_ptp_rx_hang(adapter);
7410 }
7086400d
AD		 7411
7412 ixgbe_service_event_complete(adapter);
9a799d71
AK		 7413}
7414
fd0db0ed
AD		 7415static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7416 struct ixgbe_tx_buffer *first,
244e27ad 7417 u8 *hdr_len)
897ab156 7418{
b83e3010 7419 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
fd0db0ed 7420 struct sk_buff *skb = first->skb;
b83e3010
AD		 7421 union {
7422 struct iphdr *v4;
7423 struct ipv6hdr *v6;
7424 unsigned char *hdr;
7425 } ip;
7426 union {
7427 struct tcphdr *tcp;
7428 unsigned char *hdr;
7429 } l4;
7430 u32 paylen, l4_offset;
2049e1f6 7431 int err;
9a799d71 7432
8f4fbb9b
AD		 7433 if (skb->ip_summed != CHECKSUM_PARTIAL)
7434 return 0;
7435
897ab156
AD		 7436 if (!skb_is_gso(skb))
7437 return 0;
9a799d71 7438
2049e1f6
FR		 7439 err = skb_cow_head(skb, 0);
7440 if (err < 0)
7441 return err;
9a799d71 7442
b83e3010
AD		 7443 ip.hdr = skb_network_header(skb);
7444 l4.hdr = skb_checksum_start(skb);
7445
897ab156
AD		 7446 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7447 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7448
b83e3010
AD		 7449 /* initialize outer IP header fields */
7450 if (ip.v4->version == 4) {
c54cdc31
AD		 7451 unsigned char *csum_start = skb_checksum_start(skb);
7452 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
7453
b83e3010
AD		 7454 /* IP header will have to cancel out any data that
7455 * is not a part of the outer IP header
7456 */
c54cdc31
AD		 7457 ip.v4->check = csum_fold(csum_partial(trans_start,
7458 csum_start - trans_start,
7459 0));
897ab156 7460 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
b83e3010
AD		 7461
7462 ip.v4->tot_len = 0;
244e27ad
AD		 7463 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7464 IXGBE_TX_FLAGS_CSUM |
7465 IXGBE_TX_FLAGS_IPV4;
b83e3010
AD		 7466 } else {
7467 ip.v6->payload_len = 0;
244e27ad
AD		 7468 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7469 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 7470 }
7471
b83e3010
AD		 7472 /* determine offset of inner transport header */
7473 l4_offset = l4.hdr - skb->data;
7474
7475 /* compute length of segmentation header */
7476 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
7477
7478 /* remove payload length from inner checksum */
7479 paylen = skb->len - l4_offset;
7480 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
897ab156 7481
091a6246
AD		 7482 /* update gso size and bytecount with header size */
7483 first->gso_segs = skb_shinfo(skb)->gso_segs;
7484 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7485
c44f5f51 7486 /* mss_l4len_id: use 0 as index for TSO */
b83e3010 7487 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
897ab156 7488 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 7489
7490 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
b83e3010
AD		 7491 vlan_macip_lens = l4.hdr - ip.hdr;
7492 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7493 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 7494
7495 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 7496 mss_l4len_idx);
897ab156
AD		 7497
7498 return 1;
7499}
7500
49763de0
AD		 7501static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
7502{
7503 unsigned int offset = 0;
7504
7505 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
7506
7507 return offset == skb_checksum_start_offset(skb);
7508}
7509
244e27ad
AD		 7510static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7511 struct ixgbe_tx_buffer *first)
7ca647bd 7512{
fd0db0ed 7513 struct sk_buff *skb = first->skb;
897ab156 7514 u32 vlan_macip_lens = 0;
897ab156 7515 u32 type_tucmd = 0;
7ca647bd 7516
897ab156 7517 if (skb->ip_summed != CHECKSUM_PARTIAL) {
49763de0
AD		 7518csum_failed:
7519 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
7520 IXGBE_TX_FLAGS_CC)))
472148c3 7521 return;
49763de0
AD		 7522 goto no_csum;
7523 }
897ab156 7524
49763de0
AD		 7525 switch (skb->csum_offset) {
7526 case offsetof(struct tcphdr, check):
7527 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7528 /* fall through */
7529 case offsetof(struct udphdr, check):
7530 break;
7531 case offsetof(struct sctphdr, checksum):
7532 /* validate that this is actually an SCTP request */
7533 if (((first->protocol == htons(ETH_P_IP)) &&
7534 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
7535 ((first->protocol == htons(ETH_P_IPV6)) &&
7536 ixgbe_ipv6_csum_is_sctp(skb))) {
7537 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
897ab156 7538 break;
7ca647bd 7539 }
49763de0
AD		 7540 /* fall through */
7541 default:
7542 skb_checksum_help(skb);
7543 goto csum_failed;
7ca647bd
JP		 7544 }
7545
49763de0
AD		 7546 /* update TX checksum flag */
7547 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7548 vlan_macip_lens = skb_checksum_start_offset(skb) -
7549 skb_network_offset(skb);
36a92d71 7550no_csum:
244e27ad 7551 /* vlan_macip_lens: MACLEN, VLAN tag */
49763de0 7552 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7553 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7554
49763de0 7555 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0);
9a799d71
AK		 7556}
7557
472148c3
AD		 7558#define IXGBE_SET_FLAG(_input, _flag, _result) \
7559 ((_flag <= _result) ? \
7560 ((u32)(_input & _flag) * (_result / _flag)) : \
7561 ((u32)(_input & _flag) / (_flag / _result)))
7562
7563static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7564{
d3d00239 7565 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7566 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7567 IXGBE_ADVTXD_DCMD_DEXT |
7568 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7569
d3d00239 7570 /* set HW vlan bit if vlan is present */
472148c3
AD		 7571 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7572 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7573
d3d00239 7574 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7575 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7576 IXGBE_ADVTXD_DCMD_TSE);
7577
7578 /* set timestamp bit if present */
7579 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7580 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7581
62748b7b 7582 /* insert frame checksum */
472148c3 7583 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7584
d3d00239
AD		 7585 return cmd_type;
7586}
9a799d71 7587
729739b7
AD		 7588static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7589 u32 tx_flags, unsigned int paylen)
d3d00239 7590{
472148c3 7591 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7592
d3d00239 7593 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7594 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7595 IXGBE_TX_FLAGS_CSUM,
7596 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7597
93f5b3c1 7598 /* enble IPv4 checksum for TSO */
472148c3
AD		 7599 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7600 IXGBE_TX_FLAGS_IPV4,
7601 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7602
7f9643fd
AD		 7603 /*
7604 * Check Context must be set if Tx switch is enabled, which it
7605 * always is for case where virtual functions are running
7606 */
472148c3
AD		 7607 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7608 IXGBE_TX_FLAGS_CC,
7609 IXGBE_ADVTXD_CC);
7f9643fd 7610
472148c3 7611 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7612}
44df32c5 7613
2367a173
DB		 7614static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7615{
7616 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7617
7618 /* Herbert's original patch had:
7619 * smp_mb__after_netif_stop_queue();
7620 * but since that doesn't exist yet, just open code it.
7621 */
7622 smp_mb();
7623
7624 /* We need to check again in a case another CPU has just
7625 * made room available.
7626 */
7627 if (likely(ixgbe_desc_unused(tx_ring) < size))
7628 return -EBUSY;
7629
7630 /* A reprieve! - use start_queue because it doesn't call schedule */
7631 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7632 ++tx_ring->tx_stats.restart_queue;
7633 return 0;
7634}
7635
7636static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7637{
7638 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7639 return 0;
7640
7641 return __ixgbe_maybe_stop_tx(tx_ring, size);
7642}
7643
d3d00239
AD		 7644#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7645 IXGBE_TXD_CMD_RS)
7646
7647static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7648 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7649 const u8 hdr_len)
7650{
fd0db0ed 7651 struct sk_buff *skb = first->skb;
729739b7 7652 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7653 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7654 struct skb_frag_struct *frag;
7655 dma_addr_t dma;
7656 unsigned int data_len, size;
244e27ad 7657 u32 tx_flags = first->tx_flags;
472148c3 7658 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7659 u16 i = tx_ring->next_to_use;
d3d00239 7660
729739b7
AD		 7661 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7662
ec718254
AD		 7663 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7664
7665 size = skb_headlen(skb);
7666 data_len = skb->data_len;
729739b7 7667
d3d00239
AD		 7668#ifdef IXGBE_FCOE
7669 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7670 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7671 size -= sizeof(struct fcoe_crc_eof) - data_len;
7672 data_len = 0;
729739b7
AD		 7673 } else {
7674 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7675 }
7676 }
44df32c5 7677
d3d00239 7678#endif
729739b7 7679 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7680
ec718254 7681 tx_buffer = first;
9a799d71 7682
ec718254
AD		 7683 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7684 if (dma_mapping_error(tx_ring->dev, dma))
7685 goto dma_error;
7686
7687 /* record length, and DMA address */
7688 dma_unmap_len_set(tx_buffer, len, size);
7689 dma_unmap_addr_set(tx_buffer, dma, dma);
7690
7691 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7692
729739b7 7693 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7694 tx_desc->read.cmd_type_len =
472148c3 7695 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7696
d3d00239 7697 i++;
729739b7 7698 tx_desc++;
d3d00239 7699 if (i == tx_ring->count) {
e4f74028 7700 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7701 i = 0;
7702 }
ec718254 7703 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7704
7705 dma += IXGBE_MAX_DATA_PER_TXD;
7706 size -= IXGBE_MAX_DATA_PER_TXD;
7707
7708 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7709 }
e5a43549 7710
729739b7
AD		 7711 if (likely(!data_len))
7712 break;
9a799d71 7713
472148c3 7714 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7715
729739b7
AD		 7716 i++;
7717 tx_desc++;
7718 if (i == tx_ring->count) {
7719 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7720 i = 0;
7721 }
ec718254 7722 tx_desc->read.olinfo_status = 0;
9a799d71 7723
d3d00239 7724#ifdef IXGBE_FCOE
9e903e08 7725 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7726#else
9e903e08 7727 size = skb_frag_size(frag);
d3d00239
AD		 7728#endif
7729 data_len -= size;
9a799d71 7730
729739b7
AD		 7731 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7732 DMA_TO_DEVICE);
9a799d71 7733
729739b7 7734 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7735 }
9a799d71 7736
729739b7 7737 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7738 cmd_type |= size | IXGBE_TXD_CMD;
7739 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7740
091a6246 7741 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7742
d3d00239
AD		 7743 /* set the timestamp */
7744 first->time_stamp = jiffies;
9a799d71
AK		 7745
7746 /*
729739b7
AD		 7747 * Force memory writes to complete before letting h/w know there
7748 * are new descriptors to fetch. (Only applicable for weak-ordered
7749 * memory model archs, such as IA-64).
7750 *
7751 * We also need this memory barrier to make certain all of the
7752 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7753 */
7754 wmb();
7755
d3d00239
AD		 7756 /* set next_to_watch value indicating a packet is present */
7757 first->next_to_watch = tx_desc;
7758
729739b7
AD		 7759 i++;
7760 if (i == tx_ring->count)
7761 i = 0;
7762
7763 tx_ring->next_to_use = i;
7764
2367a173
DB		 7765 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7766
7767 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7768 writel(i, tx_ring->tail);
7769
7770 /* we need this if more than one processor can write to our tail
7771 * at a time, it synchronizes IO on IA64/Altix systems
7772 */
7773 mmiowb();
9c938cdd 7774 }
2367a173 7775
d3d00239
AD		 7776 return;
7777dma_error:
729739b7 7778 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7779
7780 /* clear dma mappings for failed tx_buffer_info map */
7781 for (;;) {
729739b7
AD		 7782 tx_buffer = &tx_ring->tx_buffer_info[i];
7783 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7784 if (tx_buffer == first)
d3d00239
AD		 7785 break;
7786 if (i == 0)
7787 i = tx_ring->count;
7788 i--;
7789 }
7790
d3d00239 7791 tx_ring->next_to_use = i;
9a799d71
AK		 7792}
7793
fd0db0ed 7794static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7795 struct ixgbe_tx_buffer *first)
69830529
AD		 7796{
7797 struct ixgbe_q_vector *q_vector = ring->q_vector;
7798 union ixgbe_atr_hash_dword input = { .dword = 0 };
7799 union ixgbe_atr_hash_dword common = { .dword = 0 };
7800 union {
7801 unsigned char *network;
7802 struct iphdr *ipv4;
7803 struct ipv6hdr *ipv6;
7804 } hdr;
ee9e0f0b 7805 struct tcphdr *th;
e2873d43 7806 unsigned int hlen;
67359c3c 7807 struct sk_buff *skb;
905e4a41 7808 __be16 vlan_id;
e2873d43 7809 int l4_proto;
c4cf55e5 7810
69830529
AD		 7811 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7812 if (!q_vector)
7813 return;
7814
7815 /* do nothing if sampling is disabled */
7816 if (!ring->atr_sample_rate)
d3ead241 7817 return;
c4cf55e5 7818
69830529 7819 ring->atr_count++;
c4cf55e5 7820
e2873d43
AD		 7821 /* currently only IPv4/IPv6 with TCP is supported */
7822 if ((first->protocol != htons(ETH_P_IP)) &&
7823 (first->protocol != htons(ETH_P_IPV6)))
7824 return;
7825
69830529 7826 /* snag network header to get L4 type and address */
67359c3c
MR		 7827 skb = first->skb;
7828 hdr.network = skb_network_header(skb);
9f3c7504
SV		 7829 if (unlikely(hdr.network <= skb->data))
7830 return;
9f12df90
AD		 7831 if (skb->encapsulation &&
7832 first->protocol == htons(ETH_P_IP) &&
52028821 7833 hdr.ipv4->protocol == IPPROTO_UDP) {
67359c3c 7834 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7835
9f3c7504
SV		 7836 if (unlikely(skb_tail_pointer(skb) < hdr.network +
7837 VXLAN_HEADROOM))
7838 return;
7839
9f12df90
AD		 7840 /* verify the port is recognized as VXLAN */
7841 if (adapter->vxlan_port &&
e2873d43 7842 udp_hdr(skb)->dest == adapter->vxlan_port)
9f12df90 7843 hdr.network = skb_inner_network_header(skb);
a21d0822
ET		 7844
7845 if (adapter->geneve_port &&
7846 udp_hdr(skb)->dest == adapter->geneve_port)
7847 hdr.network = skb_inner_network_header(skb);
e19dcdeb
MR		 7848 }
7849
9f3c7504
SV		 7850 /* Make sure we have at least [minimum IPv4 header + TCP]
7851 * or [IPv6 header] bytes
7852 */
7853 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40))
7854 return;
7855
e19dcdeb
MR		 7856 /* Currently only IPv4/IPv6 with TCP is supported */
7857 switch (hdr.ipv4->version) {
7858 case IPVERSION:
e2873d43
AD		 7859 /* access ihl as u8 to avoid unaligned access on ia64 */
7860 hlen = (hdr.network[0] & 0x0F) << 2;
7861 l4_proto = hdr.ipv4->protocol;
e19dcdeb
MR		 7862 break;
7863 case 6:
e2873d43
AD		 7864 hlen = hdr.network - skb->data;
7865 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
7866 hlen -= hdr.network - skb->data;
e19dcdeb
MR		 7867 break;
7868 default:
7869 return;
67359c3c 7870 }
c4cf55e5 7871
e2873d43
AD		 7872 if (l4_proto != IPPROTO_TCP)
7873 return;
7874
9f3c7504
SV		 7875 if (unlikely(skb_tail_pointer(skb) < hdr.network +
7876 hlen + sizeof(struct tcphdr)))
7877 return;
7878
e2873d43
AD		 7879 th = (struct tcphdr *)(hdr.network + hlen);
7880
7881 /* skip this packet since the socket is closing */
7882 if (th->fin)
69830529
AD		 7883 return;
7884
7885 /* sample on all syn packets or once every atr sample count */
7886 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7887 return;
7888
7889 /* reset sample count */
7890 ring->atr_count = 0;
7891
244e27ad 7892 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7893
7894 /*
7895 * src and dst are inverted, think how the receiver sees them
7896 *
7897 * The input is broken into two sections, a non-compressed section
7898 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7899 * is XORed together and stored in the compressed dword.
7900 */
7901 input.formatted.vlan_id = vlan_id;
7902
7903 /*
7904 * since src port and flex bytes occupy the same word XOR them together
7905 * and write the value to source port portion of compressed dword
7906 */
244e27ad 7907 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7908 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7909 else
244e27ad 7910 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7911 common.port.dst ^= th->source;
7912
e19dcdeb
MR		 7913 switch (hdr.ipv4->version) {
7914 case IPVERSION:
69830529
AD		 7915 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7916 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
e19dcdeb
MR		 7917 break;
7918 case 6:
69830529
AD		 7919 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7920 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7921 hdr.ipv6->saddr.s6_addr32[1] ^
7922 hdr.ipv6->saddr.s6_addr32[2] ^
7923 hdr.ipv6->saddr.s6_addr32[3] ^
7924 hdr.ipv6->daddr.s6_addr32[0] ^
7925 hdr.ipv6->daddr.s6_addr32[1] ^
7926 hdr.ipv6->daddr.s6_addr32[2] ^
7927 hdr.ipv6->daddr.s6_addr32[3];
e19dcdeb
MR		 7928 break;
7929 default:
7930 break;
69830529 7931 }
c4cf55e5 7932
9f12df90 7933 if (hdr.network != skb_network_header(skb))
67359c3c 7934 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
67359c3c 7935
c4cf55e5 7936 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7937 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7938 input, common, ring->queue_index);
c4cf55e5
PWJ		 7939}
7940
f663dd9a 7941static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7942 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7943{
f663dd9a
JW		 7944 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7945#ifdef IXGBE_FCOE
97488bd1
AD		 7946 struct ixgbe_adapter *adapter;
7947 struct ixgbe_ring_feature *f;
7948 int txq;
f663dd9a
JW		 7949#endif
7950
7951 if (fwd_adapter)
7952 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7953
7954#ifdef IXGBE_FCOE
5e09a105 7955
97488bd1
AD		 7956 /*
7957 * only execute the code below if protocol is FCoE
7958 * or FIP and we have FCoE enabled on the adapter
7959 */
7960 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7961 case htons(ETH_P_FCOE):
7962 case htons(ETH_P_FIP):
97488bd1 7963 adapter = netdev_priv(dev);
c087663e 7964
97488bd1
AD		 7965 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7966 break;
7967 default:
99932d4f 7968 return fallback(dev, skb);
97488bd1 7969 }
c087663e 7970
97488bd1 7971 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7972
97488bd1
AD		 7973 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7974 smp_processor_id();
56075a98 7975
97488bd1
AD		 7976 while (txq >= f->indices)
7977 txq -= f->indices;
c4cf55e5 7978
97488bd1 7979 return txq + f->offset;
f663dd9a 7980#else
99932d4f 7981 return fallback(dev, skb);
f663dd9a 7982#endif
09a3b1f8
SH		 7983}
7984
fc77dc3c 7985netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7986 struct ixgbe_adapter *adapter,
7987 struct ixgbe_ring *tx_ring)
9a799d71 7988{
d3d00239 7989 struct ixgbe_tx_buffer *first;
5f715823 7990 int tso;
d3d00239 7991 u32 tx_flags = 0;
a535c30e 7992 unsigned short f;
a535c30e 7993 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7994 __be16 protocol = skb->protocol;
63544e9c 7995 u8 hdr_len = 0;
5e09a105 7996
a535c30e
AD		 7997 /*
7998 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7999 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 8000 * + 2 desc gap to keep tail from touching head,
8001 * + 1 desc for context descriptor,
8002 * otherwise try next time
8003 */
a535c30e
AD		 8004 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
8005 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 8006
a535c30e
AD		 8007 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
8008 tx_ring->tx_stats.tx_busy++;
8009 return NETDEV_TX_BUSY;
8010 }
8011
fd0db0ed
AD		 8012 /* record the location of the first descriptor for this packet */
8013 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
8014 first->skb = skb;
091a6246
AD		 8015 first->bytecount = skb->len;
8016 first->gso_segs = 1;
fd0db0ed 8017
66f32a8b 8018 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 8019 if (skb_vlan_tag_present(skb)) {
8020 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 8021 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8022 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 8023 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 8024 struct vlan_hdr *vhdr, _vhdr;
8025 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
8026 if (!vhdr)
8027 goto out_drop;
8028
9e0c5648
AD		 8029 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
8030 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 8031 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
8032 }
0213668f 8033 protocol = vlan_get_protocol(skb);
66f32a8b 8034
d5234933
MR		 8035 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
8036 adapter->ptp_clock &&
8037 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
8038 &adapter->state)) {
3a6a4eda
JK		 8039 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8040 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 8041
8042 /* schedule check for Tx timestamp */
8043 adapter->ptp_tx_skb = skb_get(skb);
8044 adapter->ptp_tx_start = jiffies;
8045 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 8046 }
3a6a4eda 8047
ff29a86e
JK		 8048 skb_tx_timestamp(skb);
8049
9e0c5648
AD		 8050#ifdef CONFIG_PCI_IOV
8051 /*
8052 * Use the l2switch_enable flag - would be false if the DMA
8053 * Tx switch had been disabled.
8054 */
8055 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 8056 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 8057
8058#endif
32701dc2 8059 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 8060 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 8061 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
8062 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 8063 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 8064 tx_flags |= (skb->priority & 0x7) <<
8065 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 8066 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
8067 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 8068
8069 if (skb_cow_head(skb, 0))
66f32a8b
AD		 8070 goto out_drop;
8071 vhdr = (struct vlan_ethhdr *)skb->data;
8072 vhdr->h_vlan_TCI = htons(tx_flags >>
8073 IXGBE_TX_FLAGS_VLAN_SHIFT);
8074 } else {
8075 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 8076 }
9a799d71 8077 }
eacd73f7 8078
244e27ad
AD		 8079 /* record initial flags and protocol */
8080 first->tx_flags = tx_flags;
8081 first->protocol = protocol;
8082
eacd73f7 8083#ifdef IXGBE_FCOE
66f32a8b 8084 /* setup tx offload for FCoE */
a1108ffd 8085 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 8086 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 8087 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 8088 if (tso < 0)
8089 goto out_drop;
9a799d71 8090
66f32a8b 8091 goto xmit_fcoe;
eacd73f7 8092 }
9a799d71 8093
66f32a8b 8094#endif /* IXGBE_FCOE */
244e27ad 8095 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 8096 if (tso < 0)
897ab156 8097 goto out_drop;
244e27ad
AD		 8098 else if (!tso)
8099 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 8100
8101 /* add the ATR filter if ATR is on */
8102 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 8103 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 8104
8105#ifdef IXGBE_FCOE
8106xmit_fcoe:
8107#endif /* IXGBE_FCOE */
244e27ad 8108 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 8109
9a799d71 8110 return NETDEV_TX_OK;
897ab156
AD		 8111
8112out_drop:
fd0db0ed
AD		 8113 dev_kfree_skb_any(first->skb);
8114 first->skb = NULL;
8115
897ab156 8116 return NETDEV_TX_OK;
9a799d71
AK		 8117}
8118
2a47fa45
JF		 8119static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
8120 struct net_device *netdev,
8121 struct ixgbe_ring *ring)
84418e3b
AD		 8122{
8123 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8124 struct ixgbe_ring *tx_ring;
8125
a50c29dd
AD		 8126 /*
8127 * The minimum packet size for olinfo paylen is 17 so pad the skb
8128 * in order to meet this minimum size requirement.
8129 */
a94d9e22
AD		 8130 if (skb_put_padto(skb, 17))
8131 return NETDEV_TX_OK;
a50c29dd 8132
2a47fa45
JF		 8133 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
8134
fc77dc3c 8135 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 8136}
8137
2a47fa45
JF		 8138static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
8139 struct net_device *netdev)
8140{
8141 return __ixgbe_xmit_frame(skb, netdev, NULL);
8142}
8143
9a799d71
AK		 8144/**
8145 * ixgbe_set_mac - Change the Ethernet Address of the NIC
8146 * @netdev: network interface device structure
8147 * @p: pointer to an address structure
8148 *
8149 * Returns 0 on success, negative on failure
8150 **/
8151static int ixgbe_set_mac(struct net_device *netdev, void *p)
8152{
8153 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 8154 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 8155 struct sockaddr *addr = p;
8156
8157 if (!is_valid_ether_addr(addr->sa_data))
8158 return -EADDRNOTAVAIL;
8159
8160 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 8161 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 8162
c9f53e63
AD		 8163 ixgbe_mac_set_default_filter(adapter);
8164
8165 return 0;
9a799d71
AK		 8166}
8167
6b73e10d
BH		 8168static int
8169ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
8170{
8171 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8172 struct ixgbe_hw *hw = &adapter->hw;
8173 u16 value;
8174 int rc;
8175
8176 if (prtad != hw->phy.mdio.prtad)
8177 return -EINVAL;
8178 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
8179 if (!rc)
8180 rc = value;
8181 return rc;
8182}
8183
8184static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8185 u16 addr, u16 value)
8186{
8187 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8188 struct ixgbe_hw *hw = &adapter->hw;
8189
8190 if (prtad != hw->phy.mdio.prtad)
8191 return -EINVAL;
8192 return hw->phy.ops.write_reg(hw, addr, devad, value);
8193}
8194
8195static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8196{
8197 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8198
3a6a4eda 8199 switch (cmd) {
3a6a4eda 8200 case SIOCSHWTSTAMP:
93501d48
JK		 8201 return ixgbe_ptp_set_ts_config(adapter, req);
8202 case SIOCGHWTSTAMP:
8203 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 8204 default:
8205 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8206 }
6b73e10d
BH		 8207}
8208
0365e6e4
PW		 8209/**
8210 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 8211 * netdev->dev_addrs
0365e6e4
PW		 8212 * @netdev: network interface device structure
8213 *
8214 * Returns non-zero on failure
8215 **/
8216static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8217{
8218 int err = 0;
8219 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 8220 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 8221
7fa7c9dc 8222 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 8223 rtnl_lock();
7fa7c9dc 8224 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 8225 rtnl_unlock();
7fa7c9dc
AD		 8226
8227 /* update SAN MAC vmdq pool selection */
8228 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 8229 }
8230 return err;
8231}
8232
8233/**
8234 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 8235 * netdev->dev_addrs
0365e6e4
PW		 8236 * @netdev: network interface device structure
8237 *
8238 * Returns non-zero on failure
8239 **/
8240static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8241{
8242 int err = 0;
8243 struct ixgbe_adapter *adapter = netdev_priv(dev);
8244 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8245
8246 if (is_valid_ether_addr(mac->san_addr)) {
8247 rtnl_lock();
8248 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8249 rtnl_unlock();
8250 }
8251 return err;
8252}
8253
9a799d71
AK		 8254#ifdef CONFIG_NET_POLL_CONTROLLER
8255/*
8256 * Polling 'interrupt' - used by things like netconsole to send skbs
8257 * without having to re-enable interrupts. It's not called while
8258 * the interrupt routine is executing.
8259 */
8260static void ixgbe_netpoll(struct net_device *netdev)
8261{
8262 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 8263 int i;
9a799d71 8264
1a647bd2
AD		 8265 /* if interface is down do nothing */
8266 if (test_bit(__IXGBE_DOWN, &adapter->state))
8267 return;
8268
856f606e
AD		 8269 /* loop through and schedule all active queues */
8270 for (i = 0; i < adapter->num_q_vectors; i++)
8271 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 8272}
9a799d71 8273
581330ba 8274#endif
bc1f4470 8275
8276static void ixgbe_get_stats64(struct net_device *netdev,
8277 struct rtnl_link_stats64 *stats)
de1036b1
ED		 8278{
8279 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8280 int i;
8281
1a51502b 8282 rcu_read_lock();
de1036b1 8283 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 8284 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 8285 u64 bytes, packets;
8286 unsigned int start;
8287
1a51502b
ED		 8288 if (ring) {
8289 do {
57a7744e 8290 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 8291 packets = ring->stats.packets;
8292 bytes = ring->stats.bytes;
57a7744e 8293 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 8294 stats->rx_packets += packets;
8295 stats->rx_bytes += bytes;
8296 }
de1036b1 8297 }
1ac9ad13
ED		 8298
8299 for (i = 0; i < adapter->num_tx_queues; i++) {
8300 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
8301 u64 bytes, packets;
8302 unsigned int start;
8303
8304 if (ring) {
8305 do {
57a7744e 8306 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 8307 packets = ring->stats.packets;
8308 bytes = ring->stats.bytes;
57a7744e 8309 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 8310 stats->tx_packets += packets;
8311 stats->tx_bytes += bytes;
8312 }
8313 }
1a51502b 8314 rcu_read_unlock();
bc1f4470 8315
de1036b1
ED		 8316 /* following stats updated by ixgbe_watchdog_task() */
8317 stats->multicast = netdev->stats.multicast;
8318 stats->rx_errors = netdev->stats.rx_errors;
8319 stats->rx_length_errors = netdev->stats.rx_length_errors;
8320 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8321 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
de1036b1
ED		 8322}
8323
8af3c33f 8324#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 8325/**
8326 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8327 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 8328 * @tc: number of traffic classes currently enabled
8329 *
8330 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8331 * 802.1Q priority maps to a packet buffer that exists.
8332 */
8333static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8334{
8335 struct ixgbe_hw *hw = &adapter->hw;
8336 u32 reg, rsave;
8337 int i;
8338
8339 /* 82598 have a static priority to TC mapping that can not
8340 * be changed so no validation is needed.
8341 */
8342 if (hw->mac.type == ixgbe_mac_82598EB)
8343 return;
8344
8345 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8346 rsave = reg;
8347
8348 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8349 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8350
8351 /* If up2tc is out of bounds default to zero */
8352 if (up2tc > tc)
8353 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8354 }
8355
8356 if (reg != rsave)
8357 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8358
8359 return;
8360}
8361
02debdc9
AD		 8362/**
8363 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8364 * @adapter: Pointer to adapter struct
8365 *
8366 * Populate the netdev user priority to tc map
8367 */
8368static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8369{
8370 struct net_device *dev = adapter->netdev;
8371 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8372 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8373 u8 prio;
8374
8375 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8376 u8 tc = 0;
8377
8378 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8379 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8380 else if (ets)
8381 tc = ets->prio_tc[prio];
8382
8383 netdev_set_prio_tc_map(dev, prio, tc);
8384 }
8385}
8386
cca73c59 8387#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 8388/**
8389 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 8390 *
8391 * @netdev: net device to configure
8392 * @tc: number of traffic classes to enable
8393 */
8394int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8395{
8b1c0b24
JF		 8396 struct ixgbe_adapter *adapter = netdev_priv(dev);
8397 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 8398 bool pools;
8b1c0b24 8399
8b1c0b24 8400 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 8401 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8402 return -EINVAL;
8403
8404 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 8405 return -EINVAL;
8406
2a47fa45
JF		 8407 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8408 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8409 return -EBUSY;
8410
8b1c0b24 8411 /* Hardware has to reinitialize queues and interrupts to
52f33af8 8412 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 8413 * hardware is not flexible enough to do this dynamically.
8414 */
8415 if (netif_running(dev))
8416 ixgbe_close(dev);
bf4d67d9
AD		 8417 else
8418 ixgbe_reset(adapter);
8419
8b1c0b24
JF		 8420 ixgbe_clear_interrupt_scheme(adapter);
8421
cca73c59 8422#ifdef CONFIG_IXGBE_DCB
e7589eab 8423 if (tc) {
8b1c0b24 8424 netdev_set_num_tc(dev, tc);
02debdc9
AD		 8425 ixgbe_set_prio_tc_map(adapter);
8426
e7589eab 8427 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 8428
943561d3
AD		 8429 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8430 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 8431 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 8432 }
e7589eab 8433 } else {
8b1c0b24 8434 netdev_reset_tc(dev);
02debdc9 8435
943561d3
AD		 8436 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8437 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 8438
8439 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 8440
8441 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8442 adapter->dcb_cfg.pfc_mode_enable = false;
8443 }
8444
8b1c0b24 8445 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 8446
8447#endif /* CONFIG_IXGBE_DCB */
8448 ixgbe_init_interrupt_scheme(adapter);
8449
8b1c0b24 8450 if (netif_running(dev))
cca73c59 8451 return ixgbe_open(dev);
8b1c0b24
JF		 8452
8453 return 0;
8454}
de1036b1 8455
b82b17d9
JF		 8456static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
8457 struct tc_cls_u32_offload *cls)
8458{
1ecedc92 8459 u32 hdl = cls->knode.handle;
176621c9 8460 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
1ecedc92
AN		 8461 u32 loc = cls->knode.handle & 0xfffff;
8462 int err = 0, i, j;
8463 struct ixgbe_jump_table *jump = NULL;
8464
8465 if (loc > IXGBE_MAX_HW_ENTRIES)
8466 return -EINVAL;
b82b17d9 8467
176621c9
SS		 8468 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
8469 return -EINVAL;
8470
1ecedc92
AN		 8471 /* Clear this filter in the link data it is associated with */
8472 if (uhtid != 0x800) {
8473 jump = adapter->jump_tables[uhtid];
12746fd2
AN		 8474 if (!jump)
8475 return -EINVAL;
8476 if (!test_bit(loc - 1, jump->child_loc_map))
8477 return -EINVAL;
8478 clear_bit(loc - 1, jump->child_loc_map);
1ecedc92
AN		 8479 }
8480
8481 /* Check if the filter being deleted is a link */
8482 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
8483 jump = adapter->jump_tables[i];
8484 if (jump && jump->link_hdl == hdl) {
8485 /* Delete filters in the hardware in the child hash
8486 * table associated with this link
8487 */
8488 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
8489 if (!test_bit(j, jump->child_loc_map))
8490 continue;
8491 spin_lock(&adapter->fdir_perfect_lock);
8492 err = ixgbe_update_ethtool_fdir_entry(adapter,
8493 NULL,
8494 j + 1);
8495 spin_unlock(&adapter->fdir_perfect_lock);
8496 clear_bit(j, jump->child_loc_map);
8497 }
8498 /* Remove resources for this link */
8499 kfree(jump->input);
8500 kfree(jump->mask);
8501 kfree(jump);
8502 adapter->jump_tables[i] = NULL;
8503 return err;
8504 }
8505 }
176621c9 8506
b82b17d9 8507 spin_lock(&adapter->fdir_perfect_lock);
176621c9 8508 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
b82b17d9
JF		 8509 spin_unlock(&adapter->fdir_perfect_lock);
8510 return err;
8511}
8512
db956ae8
JF		 8513static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
8514 __be16 protocol,
8515 struct tc_cls_u32_offload *cls)
8516{
176621c9
SS		 8517 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8518
8519 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8520 return -EINVAL;
8521
db956ae8
JF		 8522 /* This ixgbe devices do not support hash tables at the moment
8523 * so abort when given hash tables.
8524 */
8525 if (cls->hnode.divisor > 0)
8526 return -EINVAL;
8527
176621c9 8528 set_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 8529 return 0;
8530}
8531
8532static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
8533 struct tc_cls_u32_offload *cls)
8534{
176621c9
SS		 8535 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8536
8537 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8538 return -EINVAL;
8539
8540 clear_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 8541 return 0;
8542}
8543
947f8a45 8544#ifdef CONFIG_NET_CLS_ACT
1cd127fc
DA		 8545struct upper_walk_data {
8546 struct ixgbe_adapter *adapter;
8547 u64 action;
8548 int ifindex;
8549 u8 queue;
8550};
8551
8552static int get_macvlan_queue(struct net_device *upper, void *_data)
8553{
8554 if (netif_is_macvlan(upper)) {
8555 struct macvlan_dev *dfwd = netdev_priv(upper);
8556 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
8557 struct upper_walk_data *data = _data;
8558 struct ixgbe_adapter *adapter = data->adapter;
8559 int ifindex = data->ifindex;
8560
8561 if (vadapter && vadapter->netdev->ifindex == ifindex) {
8562 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
8563 data->action = data->queue;
8564 return 1;
8565 }
8566 }
8567
8568 return 0;
8569}
8570
947f8a45
SS		 8571static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
8572 u8 *queue, u64 *action)
8573{
8574 unsigned int num_vfs = adapter->num_vfs, vf;
1cd127fc 8575 struct upper_walk_data data;
947f8a45 8576 struct net_device *upper;
947f8a45
SS		 8577
8578 /* redirect to a SRIOV VF */
8579 for (vf = 0; vf < num_vfs; ++vf) {
8580 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
8581 if (upper->ifindex == ifindex) {
8582 if (adapter->num_rx_pools > 1)
8583 *queue = vf * 2;
8584 else
8585 *queue = vf * adapter->num_rx_queues_per_pool;
8586
8587 *action = vf + 1;
8588 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
8589 return 0;
8590 }
8591 }
8592
8593 /* redirect to a offloaded macvlan netdev */
1cd127fc
DA		 8594 data.adapter = adapter;
8595 data.ifindex = ifindex;
8596 data.action = 0;
8597 data.queue = 0;
8598 if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
8599 get_macvlan_queue, &data)) {
8600 *action = data.action;
8601 *queue = data.queue;
8602
8603 return 0;
947f8a45
SS		 8604 }
8605
8606 return -EINVAL;
8607}
8608
8609static int parse_tc_actions(struct ixgbe_adapter *adapter,
8610 struct tcf_exts *exts, u64 *action, u8 *queue)
8611{
8612 const struct tc_action *a;
22dc13c8 8613 LIST_HEAD(actions);
947f8a45
SS		 8614 int err;
8615
8616 if (tc_no_actions(exts))
8617 return -EINVAL;
8618
22dc13c8
WC		 8619 tcf_exts_to_list(exts, &actions);
8620 list_for_each_entry(a, &actions, list) {
947f8a45
SS		 8621
8622 /* Drop action */
8623 if (is_tcf_gact_shot(a)) {
8624 *action = IXGBE_FDIR_DROP_QUEUE;
8625 *queue = IXGBE_FDIR_DROP_QUEUE;
8626 return 0;
8627 }
8628
8629 /* Redirect to a VF or a offloaded macvlan */
5724b8b5 8630 if (is_tcf_mirred_egress_redirect(a)) {
947f8a45
SS		 8631 int ifindex = tcf_mirred_ifindex(a);
8632
8633 err = handle_redirect_action(adapter, ifindex, queue,
8634 action);
8635 if (err == 0)
8636 return err;
8637 }
8638 }
8639
8640 return -EINVAL;
8641}
8642#else
8643static int parse_tc_actions(struct ixgbe_adapter *adapter,
8644 struct tcf_exts *exts, u64 *action, u8 *queue)
8645{
8646 return -EINVAL;
8647}
8648#endif /* CONFIG_NET_CLS_ACT */
8649
1cdaaf54
AN		 8650static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
8651 union ixgbe_atr_input *mask,
8652 struct tc_cls_u32_offload *cls,
8653 struct ixgbe_mat_field *field_ptr,
8654 struct ixgbe_nexthdr *nexthdr)
8655{
8656 int i, j, off;
8657 __be32 val, m;
8658 bool found_entry = false, found_jump_field = false;
8659
8660 for (i = 0; i < cls->knode.sel->nkeys; i++) {
8661 off = cls->knode.sel->keys[i].off;
8662 val = cls->knode.sel->keys[i].val;
8663 m = cls->knode.sel->keys[i].mask;
8664
8665 for (j = 0; field_ptr[j].val; j++) {
8666 if (field_ptr[j].off == off) {
8667 field_ptr[j].val(input, mask, val, m);
8668 input->filter.formatted.flow_type |=
8669 field_ptr[j].type;
8670 found_entry = true;
8671 break;
8672 }
8673 }
8674 if (nexthdr) {
8675 if (nexthdr->off == cls->knode.sel->keys[i].off &&
8676 nexthdr->val == cls->knode.sel->keys[i].val &&
8677 nexthdr->mask == cls->knode.sel->keys[i].mask)
8678 found_jump_field = true;
8679 else
8680 continue;
8681 }
8682 }
8683
8684 if (nexthdr && !found_jump_field)
8685 return -EINVAL;
8686
8687 if (!found_entry)
8688 return 0;
8689
8690 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
8691 IXGBE_ATR_L4TYPE_MASK;
8692
8693 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
8694 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
8695
8696 return 0;
8697}
8698
b82b17d9
JF		 8699static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
8700 __be16 protocol,
8701 struct tc_cls_u32_offload *cls)
8702{
8703 u32 loc = cls->knode.handle & 0xfffff;
8704 struct ixgbe_hw *hw = &adapter->hw;
8705 struct ixgbe_mat_field *field_ptr;
1cdaaf54
AN		 8706 struct ixgbe_fdir_filter *input = NULL;
8707 union ixgbe_atr_input *mask = NULL;
8708 struct ixgbe_jump_table *jump = NULL;
8709 int i, err = -EINVAL;
b82b17d9 8710 u8 queue;
176621c9 8711 u32 uhtid, link_uhtid;
b82b17d9 8712
176621c9
SS		 8713 uhtid = TC_U32_USERHTID(cls->knode.handle);
8714 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
b82b17d9 8715
176621c9 8716 /* At the moment cls_u32 jumps to network layer and skips past
b82b17d9
JF		 8717 * L2 headers. The canonical method to match L2 frames is to use
8718 * negative values. However this is error prone at best but really
8719 * just broken because there is no way to "know" what sort of hdr
176621c9 8720 * is in front of the network layer. Fix cls_u32 to support L2
b82b17d9
JF		 8721 * headers when needed.
8722 */
8723 if (protocol != htons(ETH_P_IP))
1cdaaf54 8724 return err;
b82b17d9
JF		 8725
8726 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
8727 e_err(drv, "Location out of range\n");
1cdaaf54 8728 return err;
b82b17d9
JF		 8729 }
8730
8731 /* cls u32 is a graph starting at root node 0x800. The driver tracks
8732 * links and also the fields used to advance the parser across each
8733 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
8734 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
8735 * To add support for new nodes update ixgbe_model.h parse structures
8736 * this function _should_ be generic try not to hardcode values here.
8737 */
176621c9 8738 if (uhtid == 0x800) {
1cdaaf54 8739 field_ptr = (adapter->jump_tables[0])->mat;
b82b17d9 8740 } else {
176621c9 8741 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
1cdaaf54
AN		 8742 return err;
8743 if (!adapter->jump_tables[uhtid])
8744 return err;
8745 field_ptr = (adapter->jump_tables[uhtid])->mat;
b82b17d9
JF		 8746 }
8747
8748 if (!field_ptr)
1cdaaf54 8749 return err;
b82b17d9 8750
1cdaaf54
AN		 8751 /* At this point we know the field_ptr is valid and need to either
8752 * build cls_u32 link or attach filter. Because adding a link to
8753 * a handle that does not exist is invalid and the same for adding
8754 * rules to handles that don't exist.
8755 */
b82b17d9 8756
1cdaaf54
AN		 8757 if (link_uhtid) {
8758 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
b82b17d9 8759
1cdaaf54
AN		 8760 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
8761 return err;
8762
8763 if (!test_bit(link_uhtid - 1, &adapter->tables))
8764 return err;
8765
1ecedc92
AN		 8766 /* Multiple filters as links to the same hash table are not
8767 * supported. To add a new filter with the same next header
8768 * but different match/jump conditions, create a new hash table
8769 * and link to it.
8770 */
8771 if (adapter->jump_tables[link_uhtid] &&
8772 (adapter->jump_tables[link_uhtid])->link_hdl) {
8773 e_err(drv, "Link filter exists for link: %x\n",
8774 link_uhtid);
8775 return err;
8776 }
8777
1cdaaf54
AN		 8778 for (i = 0; nexthdr[i].jump; i++) {
8779 if (nexthdr[i].o != cls->knode.sel->offoff ||
8780 nexthdr[i].s != cls->knode.sel->offshift ||
8781 nexthdr[i].m != cls->knode.sel->offmask)
8782 return err;
8783
8784 jump = kzalloc(sizeof(*jump), GFP_KERNEL);
8785 if (!jump)
8786 return -ENOMEM;
8787 input = kzalloc(sizeof(*input), GFP_KERNEL);
8788 if (!input) {
8789 err = -ENOMEM;
8790 goto free_jump;
8791 }
8792 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
8793 if (!mask) {
8794 err = -ENOMEM;
12746fd2 8795 goto free_input;
1cdaaf54
AN		 8796 }
8797 jump->input = input;
8798 jump->mask = mask;
1ecedc92
AN		 8799 jump->link_hdl = cls->knode.handle;
8800
1cdaaf54
AN		 8801 err = ixgbe_clsu32_build_input(input, mask, cls,
8802 field_ptr, &nexthdr[i]);
8803 if (!err) {
8804 jump->mat = nexthdr[i].jump;
8805 adapter->jump_tables[link_uhtid] = jump;
b82b17d9
JF		 8806 break;
8807 }
8808 }
1cdaaf54 8809 return 0;
b82b17d9
JF		 8810 }
8811
1cdaaf54
AN		 8812 input = kzalloc(sizeof(*input), GFP_KERNEL);
8813 if (!input)
8814 return -ENOMEM;
8815 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
8816 if (!mask) {
8817 err = -ENOMEM;
12746fd2 8818 goto free_input;
1cdaaf54 8819 }
b82b17d9 8820
1cdaaf54
AN		 8821 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
8822 if ((adapter->jump_tables[uhtid])->input)
8823 memcpy(input, (adapter->jump_tables[uhtid])->input,
8824 sizeof(*input));
8825 if ((adapter->jump_tables[uhtid])->mask)
8826 memcpy(mask, (adapter->jump_tables[uhtid])->mask,
8827 sizeof(*mask));
12746fd2
AN		 8828
8829 /* Lookup in all child hash tables if this location is already
8830 * filled with a filter
8831 */
8832 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
8833 struct ixgbe_jump_table *link = adapter->jump_tables[i];
8834
8835 if (link && (test_bit(loc - 1, link->child_loc_map))) {
8836 e_err(drv, "Filter exists in location: %x\n",
8837 loc);
8838 err = -EINVAL;
8839 goto err_out;
8840 }
8841 }
1cdaaf54
AN		 8842 }
8843 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
8844 if (err)
b82b17d9
JF		 8845 goto err_out;
8846
947f8a45
SS		 8847 err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
8848 &queue);
8849 if (err < 0)
b82b17d9 8850 goto err_out;
b82b17d9 8851
b82b17d9
JF		 8852 input->sw_idx = loc;
8853
8854 spin_lock(&adapter->fdir_perfect_lock);
8855
8856 if (hlist_empty(&adapter->fdir_filter_list)) {
1cdaaf54
AN		 8857 memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
8858 err = ixgbe_fdir_set_input_mask_82599(hw, mask);
b82b17d9
JF		 8859 if (err)
8860 goto err_out_w_lock;
1cdaaf54 8861 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
b82b17d9
JF		 8862 err = -EINVAL;
8863 goto err_out_w_lock;
8864 }
8865
1cdaaf54 8866 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
b82b17d9
JF		 8867 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
8868 input->sw_idx, queue);
8869 if (!err)
8870 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
8871 spin_unlock(&adapter->fdir_perfect_lock);
8872
12746fd2
AN		 8873 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
8874 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
1ecedc92 8875
1cdaaf54 8876 kfree(mask);
b82b17d9
JF		 8877 return err;
8878err_out_w_lock:
8879 spin_unlock(&adapter->fdir_perfect_lock);
8880err_out:
1ecedc92 8881 kfree(mask);
12746fd2
AN		 8882free_input:
8883 kfree(input);
1cdaaf54
AN		 8884free_jump:
8885 kfree(jump);
8886 return err;
b82b17d9
JF		 8887}
8888
6e2a60b5
ET		 8889static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
8890 struct tc_to_netdev *tc)
e4c6734e 8891{
b82b17d9
JF		 8892 struct ixgbe_adapter *adapter = netdev_priv(dev);
8893
8894 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
8895 tc->type == TC_SETUP_CLSU32) {
b82b17d9
JF		 8896 switch (tc->cls_u32->command) {
8897 case TC_CLSU32_NEW_KNODE:
8898 case TC_CLSU32_REPLACE_KNODE:
8899 return ixgbe_configure_clsu32(adapter,
8900 proto, tc->cls_u32);
8901 case TC_CLSU32_DELETE_KNODE:
8902 return ixgbe_delete_clsu32(adapter, tc->cls_u32);
db956ae8
JF		 8903 case TC_CLSU32_NEW_HNODE:
8904 case TC_CLSU32_REPLACE_HNODE:
8905 return ixgbe_configure_clsu32_add_hnode(adapter, proto,
8906 tc->cls_u32);
8907 case TC_CLSU32_DELETE_HNODE:
8908 return ixgbe_configure_clsu32_del_hnode(adapter,
8909 tc->cls_u32);
b82b17d9
JF		 8910 default:
8911 return -EINVAL;
8912 }
8913 }
8914
5eb4dce3 8915 if (tc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 8916 return -EINVAL;
8917
16e5cc64 8918 return ixgbe_setup_tc(dev, tc->tc);
e4c6734e
JF		 8919}
8920
da36b647
GR		 8921#ifdef CONFIG_PCI_IOV
8922void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8923{
8924 struct net_device *netdev = adapter->netdev;
8925
8926 rtnl_lock();
da36b647 8927 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 8928 rtnl_unlock();
8929}
8930
8931#endif
082757af
DS		 8932void ixgbe_do_reset(struct net_device *netdev)
8933{
8934 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8935
8936 if (netif_running(netdev))
8937 ixgbe_reinit_locked(adapter);
8938 else
8939 ixgbe_reset(adapter);
8940}
8941
c8f44aff 8942static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 8943 netdev_features_t features)
082757af
DS		 8944{
8945 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8946
082757af 8947 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 8948 if (!(features & NETIF_F_RXCSUM))
8949 features &= ~NETIF_F_LRO;
082757af 8950
567d2de2
AD		 8951 /* Turn off LRO if not RSC capable */
8952 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8953 features &= ~NETIF_F_LRO;
8e2813f5 8954
567d2de2 8955 return features;
082757af
DS		 8956}
8957
c8f44aff 8958static int ixgbe_set_features(struct net_device *netdev,
567d2de2 8959 netdev_features_t features)
082757af
DS		 8960{
8961 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 8962 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 8963 bool need_reset = false;
8964
082757af 8965 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 8966 if (!(features & NETIF_F_LRO)) {
8967 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 8968 need_reset = true;
567d2de2
AD		 8969 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8970 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8971 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8972 if (adapter->rx_itr_setting == 1 ||
8973 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8974 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8975 need_reset = true;
8976 } else if ((changed ^ features) & NETIF_F_LRO) {
8977 e_info(probe, "rx-usecs set too low, "
8978 "disabling RSC\n");
082757af
DS		 8979 }
8980 }
8981
8982 /*
b82b17d9
JF		 8983 * Check if Flow Director n-tuple support or hw_tc support was
8984 * enabled or disabled. If the state changed, we need to reset.
082757af 8985 */
b82b17d9 8986 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
567d2de2 8987 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8988 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8989 need_reset = true;
8990
567d2de2
AD		 8991 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8992 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
b82b17d9 8993 } else {
39cb681b
AD		 8994 /* turn off perfect filters, enable ATR and reset */
8995 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8996 need_reset = true;
8997
8998 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8999
9000 /* We cannot enable ATR if SR-IOV is enabled */
b82b17d9
JF		 9001 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
9002 /* We cannot enable ATR if we have 2 or more tcs */
9003 (netdev_get_num_tc(netdev) > 1) ||
9004 /* We cannot enable ATR if RSS is disabled */
9005 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
9006 /* A sample rate of 0 indicates ATR disabled */
9007 (!adapter->atr_sample_rate))
9008 ; /* do nothing not supported */
9009 else /* otherwise supported and set the flag */
9010 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 9011 }
9012
3f2d1c0f
BG		 9013 if (changed & NETIF_F_RXALL)
9014 need_reset = true;
9015
567d2de2 9016 netdev->features = features;
67359c3c 9017
67359c3c 9018 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
a21d0822
ET		 9019 if (features & NETIF_F_RXCSUM) {
9020 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
9021 } else {
9022 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK;
9023
9024 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9025 }
9026 }
9027
9028 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) {
9029 if (features & NETIF_F_RXCSUM) {
9030 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
9031 } else {
9032 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK;
9033
9034 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9035 }
67359c3c 9036 }
67359c3c 9037
082757af
DS		 9038 if (need_reset)
9039 ixgbe_do_reset(netdev);
0c5a6166
AD		 9040 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
9041 NETIF_F_HW_VLAN_CTAG_FILTER))
9042 ixgbe_set_rx_mode(netdev);
082757af
DS		 9043
9044 return 0;
082757af
DS		 9045}
9046
3f207800 9047/**
a21d0822 9048 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports
3f207800 9049 * @dev: The port's netdev
e5de25dc 9050 * @ti: Tunnel endpoint information
3f207800 9051 **/
a21d0822
ET		 9052static void ixgbe_add_udp_tunnel_port(struct net_device *dev,
9053 struct udp_tunnel_info *ti)
3f207800
DS		 9054{
9055 struct ixgbe_adapter *adapter = netdev_priv(dev);
9056 struct ixgbe_hw *hw = &adapter->hw;
b3a49557 9057 __be16 port = ti->port;
a21d0822
ET		 9058 u32 port_shift = 0;
9059 u32 reg;
67359c3c 9060
b3a49557
AD		 9061 if (ti->sa_family != AF_INET)
9062 return;
9063
a21d0822
ET		 9064 switch (ti->type) {
9065 case UDP_TUNNEL_TYPE_VXLAN:
9066 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
9067 return;
3f207800 9068
a21d0822
ET		 9069 if (adapter->vxlan_port == port)
9070 return;
9071
9072 if (adapter->vxlan_port) {
9073 netdev_info(dev,
9074 "VXLAN port %d set, not adding port %d\n",
9075 ntohs(adapter->vxlan_port),
9076 ntohs(port));
9077 return;
9078 }
9079
9080 adapter->vxlan_port = port;
9081 break;
9082 case UDP_TUNNEL_TYPE_GENEVE:
9083 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))
9084 return;
9085
9086 if (adapter->geneve_port == port)
9087 return;
9088
9089 if (adapter->geneve_port) {
9090 netdev_info(dev,
9091 "GENEVE port %d set, not adding port %d\n",
9092 ntohs(adapter->geneve_port),
9093 ntohs(port));
9094 return;
9095 }
3f207800 9096
a21d0822
ET		 9097 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT;
9098 adapter->geneve_port = port;
9099 break;
9100 default:
3f207800
DS		 9101 return;
9102 }
9103
a21d0822
ET		 9104 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift;
9105 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg);
3f207800
DS		 9106}
9107
9108/**
a21d0822 9109 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports
3f207800 9110 * @dev: The port's netdev
e5de25dc 9111 * @ti: Tunnel endpoint information
3f207800 9112 **/
a21d0822
ET		 9113static void ixgbe_del_udp_tunnel_port(struct net_device *dev,
9114 struct udp_tunnel_info *ti)
3f207800
DS		 9115{
9116 struct ixgbe_adapter *adapter = netdev_priv(dev);
a21d0822 9117 u32 port_mask;
3f207800 9118
a21d0822
ET		 9119 if (ti->type != UDP_TUNNEL_TYPE_VXLAN &&
9120 ti->type != UDP_TUNNEL_TYPE_GENEVE)
67359c3c
MR		 9121 return;
9122
b3a49557 9123 if (ti->sa_family != AF_INET)
3f207800
DS		 9124 return;
9125
a21d0822
ET		 9126 switch (ti->type) {
9127 case UDP_TUNNEL_TYPE_VXLAN:
9128 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
9129 return;
b3a49557 9130
a21d0822
ET		 9131 if (adapter->vxlan_port != ti->port) {
9132 netdev_info(dev, "VXLAN port %d not found\n",
9133 ntohs(ti->port));
9134 return;
9135 }
9136
9137 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK;
9138 break;
9139 case UDP_TUNNEL_TYPE_GENEVE:
9140 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))
9141 return;
9142
9143 if (adapter->geneve_port != ti->port) {
9144 netdev_info(dev, "GENEVE port %d not found\n",
9145 ntohs(ti->port));
9146 return;
9147 }
9148
9149 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK;
9150 break;
9151 default:
3f207800
DS		 9152 return;
9153 }
9154
a21d0822
ET		 9155 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9156 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
3f207800
DS		 9157}
9158
edc7d573 9159static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 9160 struct net_device *dev,
f6f6424b 9161 const unsigned char *addr, u16 vid,
0f4b0add
JF		 9162 u16 flags)
9163{
bcfd3432 9164 /* guarantee we can provide a unique filter for the unicast address */
46acc460 9165 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2f9be166
AD		 9166 struct ixgbe_adapter *adapter = netdev_priv(dev);
9167 u16 pool = VMDQ_P(0);
9168
9169 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
bcfd3432 9170 return -ENOMEM;
0f4b0add
JF		 9171 }
9172
f6f6424b 9173 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 9174}
9175
219efe97
DS		 9176/**
9177 * ixgbe_configure_bridge_mode - set various bridge modes
9178 * @adapter - the private structure
9179 * @mode - requested bridge mode
9180 *
9181 * Configure some settings require for various bridge modes.
9182 **/
9183static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9184 __u16 mode)
9185{
6d4c96ad
DS		 9186 struct ixgbe_hw *hw = &adapter->hw;
9187 unsigned int p, num_pools;
9188 u32 vmdctl;
9189
219efe97
DS		 9190 switch (mode) {
9191 case BRIDGE_MODE_VEPA:
6d4c96ad 9192 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 9193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 9194
9195 /* must enable Rx switching replication to allow multicast
9196 * packet reception on all VFs, and to enable source address
9197 * pruning.
9198 */
9199 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9200 vmdctl |= IXGBE_VT_CTL_REPLEN;
9201 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9202
9203 /* enable Rx source address pruning. Note, this requires
9204 * replication to be enabled or else it does nothing.
9205 */
9206 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9207 for (p = 0; p < num_pools; p++) {
9208 if (hw->mac.ops.set_source_address_pruning)
9209 hw->mac.ops.set_source_address_pruning(hw,
9210 true,
9211 p);
9212 }
219efe97
DS		 9213 break;
9214 case BRIDGE_MODE_VEB:
6d4c96ad 9215 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 9216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
9217 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 9218
9219 /* disable Rx switching replication unless we have SR-IOV
9220 * virtual functions
9221 */
9222 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9223 if (!adapter->num_vfs)
9224 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
9225 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9226
9227 /* disable Rx source address pruning, since we don't expect to
9228 * be receiving external loopback of our transmitted frames.
9229 */
9230 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9231 for (p = 0; p < num_pools; p++) {
9232 if (hw->mac.ops.set_source_address_pruning)
9233 hw->mac.ops.set_source_address_pruning(hw,
9234 false,
9235 p);
9236 }
219efe97
DS		 9237 break;
9238 default:
9239 return -EINVAL;
9240 }
9241
9242 adapter->bridge_mode = mode;
9243
9244 e_info(drv, "enabling bridge mode: %s\n",
9245 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
9246
9247 return 0;
9248}
9249
815cccbf 9250static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 9251 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 9252{
9253 struct ixgbe_adapter *adapter = netdev_priv(dev);
9254 struct nlattr *attr, *br_spec;
9255 int rem;
9256
9257 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9258 return -EOPNOTSUPP;
9259
9260 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 9261 if (!br_spec)
9262 return -EINVAL;
815cccbf
JF		 9263
9264 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 9265 int status;
815cccbf 9266 __u16 mode;
815cccbf
JF		 9267
9268 if (nla_type(attr) != IFLA_BRIDGE_MODE)
9269 continue;
9270
b7c1a314
TG		 9271 if (nla_len(attr) < sizeof(mode))
9272 return -EINVAL;
9273
815cccbf 9274 mode = nla_get_u16(attr);
219efe97
DS		 9275 status = ixgbe_configure_bridge_mode(adapter, mode);
9276 if (status)
9277 return status;
aa2bacb6
DS		 9278
9279 break;
815cccbf
JF		 9280 }
9281
9282 return 0;
9283}
9284
9285static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 9286 struct net_device *dev,
46c264da 9287 u32 filter_mask, int nlflags)
815cccbf
JF		 9288{
9289 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 9290
9291 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9292 return 0;
9293
aa2bacb6 9294 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 9295 adapter->bridge_mode, 0, 0, nlflags,
9296 filter_mask, NULL);
815cccbf
JF		 9297}
9298
2a47fa45
JF		 9299static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
9300{
9301 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
9302 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 9303 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 9304 unsigned int limit;
2a47fa45
JF		 9305 int pool, err;
9306
aac2f1bf
JK		 9307 /* Hardware has a limited number of available pools. Each VF, and the
9308 * PF require a pool. Check to ensure we don't attempt to use more
9309 * then the available number of pools.
9310 */
9311 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
9312 return ERR_PTR(-EINVAL);
9313
219354d4
JF		 9314#ifdef CONFIG_RPS
9315 if (vdev->num_rx_queues != vdev->num_tx_queues) {
9316 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
9317 vdev->name);
9318 return ERR_PTR(-EINVAL);
9319 }
9320#endif
2a47fa45 9321 /* Check for hardware restriction on number of rx/tx queues */
219354d4 9322 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 9323 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
9324 netdev_info(pdev,
9325 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
9326 pdev->name);
9327 return ERR_PTR(-EINVAL);
9328 }
9329
9330 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
9331 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
9332 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
9333 return ERR_PTR(-EBUSY);
9334
bc52f951 9335 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 9336 if (!fwd_adapter)
9337 return ERR_PTR(-ENOMEM);
9338
9339 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
9340 adapter->num_rx_pools++;
9341 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 9342 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 9343
9344 /* Enable VMDq flag so device will be set in VM mode */
9345 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 9346 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 9347 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 9348
9349 /* Force reinit of ring allocation with VMDQ enabled */
9350 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
9351 if (err)
9352 goto fwd_add_err;
9353 fwd_adapter->pool = pool;
9354 fwd_adapter->real_adapter = adapter;
a3b8cb1f
ET		 9355
9356 if (netif_running(pdev)) {
9357 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
9358 if (err)
9359 goto fwd_add_err;
9360 netif_tx_start_all_queues(vdev);
9361 }
9362
2a47fa45
JF		 9363 return fwd_adapter;
9364fwd_add_err:
9365 /* unwind counter and free adapter struct */
9366 netdev_info(pdev,
9367 "%s: dfwd hardware acceleration failed\n", vdev->name);
9368 clear_bit(pool, &adapter->fwd_bitmask);
9369 adapter->num_rx_pools--;
9370 kfree(fwd_adapter);
9371 return ERR_PTR(err);
9372}
9373
9374static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
9375{
9376 struct ixgbe_fwd_adapter *fwd_adapter = priv;
9377 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 9378 unsigned int limit;
2a47fa45
JF		 9379
9380 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
9381 adapter->num_rx_pools--;
9382
51f3773b
JF		 9383 limit = find_last_bit(&adapter->fwd_bitmask, 32);
9384 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 9385 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
9386 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
9387 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
9388 fwd_adapter->pool, adapter->num_rx_pools,
9389 fwd_adapter->rx_base_queue,
9390 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
9391 adapter->fwd_bitmask);
9392 kfree(fwd_adapter);
9393}
9394
b83e3010
AD		 9395#define IXGBE_MAX_MAC_HDR_LEN 127
9396#define IXGBE_MAX_NETWORK_HDR_LEN 511
9397
f467bc06
MR		 9398static netdev_features_t
9399ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
9400 netdev_features_t features)
9401{
b83e3010
AD		 9402 unsigned int network_hdr_len, mac_hdr_len;
9403
9404 /* Make certain the headers can be described by a context descriptor */
9405 mac_hdr_len = skb_network_header(skb) - skb->data;
9406 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
9407 return features & ~(NETIF_F_HW_CSUM |
9408 NETIF_F_SCTP_CRC |
9409 NETIF_F_HW_VLAN_CTAG_TX |
9410 NETIF_F_TSO |
9411 NETIF_F_TSO6);
9412
9413 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
9414 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
9415 return features & ~(NETIF_F_HW_CSUM |
9416 NETIF_F_SCTP_CRC |
9417 NETIF_F_TSO |
9418 NETIF_F_TSO6);
9419
9420 /* We can only support IPV4 TSO in tunnels if we can mangle the
9421 * inner IP ID field, so strip TSO if MANGLEID is not supported.
9422 */
9423 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
9424 features &= ~NETIF_F_TSO;
f467bc06
MR		 9425
9426 return features;
9427}
9428
0edc3527 9429static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 9430 .ndo_open = ixgbe_open,
0edc3527 9431 .ndo_stop = ixgbe_close,
00829823 9432 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 9433 .ndo_select_queue = ixgbe_select_queue,
581330ba 9434 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 9435 .ndo_validate_addr = eth_validate_addr,
9436 .ndo_set_mac_address = ixgbe_set_mac,
9437 .ndo_change_mtu = ixgbe_change_mtu,
9438 .ndo_tx_timeout = ixgbe_tx_timeout,
c04f90e5 9439 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
0edc3527
SH		 9440 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
9441 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 9442 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 9443 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
9444 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 9445 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 9446 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 9447 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 9448 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 9449 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 9450 .ndo_get_stats64 = ixgbe_get_stats64,
e4c6734e 9451 .ndo_setup_tc = __ixgbe_setup_tc,
0edc3527
SH		 9452#ifdef CONFIG_NET_POLL_CONTROLLER
9453 .ndo_poll_controller = ixgbe_netpoll,
9454#endif
332d4a7d
YZ		 9455#ifdef IXGBE_FCOE
9456 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 9457 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 9458 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 9459 .ndo_fcoe_enable = ixgbe_fcoe_enable,
9460 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 9461 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 9462 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 9463#endif /* IXGBE_FCOE */
082757af
DS		 9464 .ndo_set_features = ixgbe_set_features,
9465 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 9466 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 9467 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
9468 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 9469 .ndo_dfwd_add_station = ixgbe_fwd_add,
9470 .ndo_dfwd_del_station = ixgbe_fwd_del,
a21d0822
ET		 9471 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port,
9472 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port,
f467bc06 9473 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 9474};
9475
e027d1ae
JK		 9476/**
9477 * ixgbe_enumerate_functions - Get the number of ports this device has
9478 * @adapter: adapter structure
9479 *
9480 * This function enumerates the phsyical functions co-located on a single slot,
9481 * in order to determine how many ports a device has. This is most useful in
9482 * determining the required GT/s of PCIe bandwidth necessary for optimal
9483 * performance.
9484 **/
9485static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
9486{
caafb95d 9487 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 9488 int physfns = 0;
9489
f1f96579
JK		 9490 /* Some cards can not use the generic count PCIe functions method,
9491 * because they are behind a parent switch, so we hardcode these with
9492 * the correct number of functions.
e027d1ae 9493 */
8818970d 9494 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 9495 physfns = 4;
8818970d
JK		 9496
9497 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
9498 /* don't count virtual functions */
caafb95d
JK		 9499 if (entry->is_virtfn)
9500 continue;
9501
9502 /* When the devices on the bus don't all match our device ID,
9503 * we can't reliably determine the correct number of
9504 * functions. This can occur if a function has been direct
9505 * attached to a virtual machine using VT-d, for example. In
9506 * this case, simply return -1 to indicate this.
9507 */
9508 if ((entry->vendor != pdev->vendor) ||
9509 (entry->device != pdev->device))
9510 return -1;
9511
9512 physfns++;
e027d1ae
JK		 9513 }
9514
9515 return physfns;
9516}
9517
8e2813f5
JK		 9518/**
9519 * ixgbe_wol_supported - Check whether device supports WoL
740234f0 9520 * @adapter: the adapter private structure
8e2813f5
JK		 9521 * @device_id: the device ID
9522 * @subdev_id: the subsystem device ID
9523 *
9524 * This function is used by probe and ethtool to determine
9525 * which devices have WoL support
9526 *
9527 **/
740234f0
ET		 9528bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
9529 u16 subdevice_id)
8e2813f5
JK		 9530{
9531 struct ixgbe_hw *hw = &adapter->hw;
9532 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8e2813f5 9533
740234f0
ET		 9534 /* WOL not supported on 82598 */
9535 if (hw->mac.type == ixgbe_mac_82598EB)
9536 return false;
9537
9538 /* check eeprom to see if WOL is enabled for X540 and newer */
9539 if (hw->mac.type >= ixgbe_mac_X540) {
9540 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
9541 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
9542 (hw->bus.func == 0)))
9543 return true;
9544 }
9545
9546 /* WOL is determined based on device IDs for 82599 MACs */
8e2813f5
JK		 9547 switch (device_id) {
9548 case IXGBE_DEV_ID_82599_SFP:
9549 /* Only these subdevices could supports WOL */
9550 switch (subdevice_id) {
9551 case IXGBE_SUBDEV_ID_82599_560FLR:
00103a6c
ET		 9552 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
9553 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
9554 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
8e2813f5
JK		 9555 /* only support first port */
9556 if (hw->bus.func != 0)
9557 break;
5700ff26 9558 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 9559 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 9560 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 9561 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
00103a6c
ET		 9562 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
9563 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
9564 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
740234f0 9565 return true;
8e2813f5
JK		 9566 }
9567 break;
5daebbb0 9568 case IXGBE_DEV_ID_82599EN_SFP:
740234f0 9569 /* Only these subdevices support WOL */
5daebbb0
DS		 9570 switch (subdevice_id) {
9571 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
740234f0 9572 return true;
5daebbb0
DS		 9573 }
9574 break;
8e2813f5
JK		 9575 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
9576 /* All except this subdevice support WOL */
9577 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
740234f0 9578 return true;
8e2813f5
JK		 9579 break;
9580 case IXGBE_DEV_ID_82599_KX4:
740234f0
ET		 9581 return true;
9582 default:
8e2813f5
JK		 9583 break;
9584 }
9585
740234f0 9586 return false;
8e2813f5
JK		 9587}
9588
9a799d71
AK		 9589/**
9590 * ixgbe_probe - Device Initialization Routine
9591 * @pdev: PCI device information struct
9592 * @ent: entry in ixgbe_pci_tbl
9593 *
9594 * Returns 0 on success, negative on failure
9595 *
9596 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
9597 * The OS initialization, configuring of the adapter private structure,
9598 * and a hardware reset occur.
9599 **/
1dd06ae8 9600static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 9601{
9602 struct net_device *netdev;
9603 struct ixgbe_adapter *adapter = NULL;
9604 struct ixgbe_hw *hw;
9605 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 9606 int i, err, pci_using_dac, expected_gts;
d3cb9869 9607 unsigned int indices = MAX_TX_QUEUES;
289700db 9608 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 9609 bool disable_dev = false;
eacd73f7
YZ		 9610#ifdef IXGBE_FCOE
9611 u16 device_caps;
9612#endif
289700db 9613 u32 eec;
9a799d71 9614
bded64a7
AG		 9615 /* Catch broken hardware that put the wrong VF device ID in
9616 * the PCIe SR-IOV capability.
9617 */
9618 if (pdev->is_virtfn) {
9619 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
9620 pci_name(pdev), pdev->vendor, pdev->device);
9621 return -EINVAL;
9622 }
9623
9ce77666 9624 err = pci_enable_device_mem(pdev);
9a799d71
AK		 9625 if (err)
9626 return err;
9627
f5f2eda8 9628 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 9629 pci_using_dac = 1;
9630 } else {
f5f2eda8 9631 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 9632 if (err) {
f5f2eda8
RK		 9633 dev_err(&pdev->dev,
9634 "No usable DMA configuration, aborting\n");
9635 goto err_dma;
9a799d71
AK		 9636 }
9637 pci_using_dac = 0;
9638 }
9639
56d766d6 9640 err = pci_request_mem_regions(pdev, ixgbe_driver_name);
9a799d71 9641 if (err) {
b8bc0421
DC		 9642 dev_err(&pdev->dev,
9643 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 9644 goto err_pci_reg;
9645 }
9646
19d5afd4 9647 pci_enable_pcie_error_reporting(pdev);
6fabd715 9648
9a799d71 9649 pci_set_master(pdev);
fb3b27bc 9650 pci_save_state(pdev);
9a799d71 9651
d3cb9869 9652 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 9653#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 9654 /* 8 TC w/ 4 queues per TC */
9655 indices = 4 * MAX_TRAFFIC_CLASS;
9656#else
9657 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 9658#endif
d3cb9869 9659 }
e901acd6 9660
c85a2618 9661 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 9662 if (!netdev) {
9663 err = -ENOMEM;
9664 goto err_alloc_etherdev;
9665 }
9666
9a799d71
AK		 9667 SET_NETDEV_DEV(netdev, &pdev->dev);
9668
9a799d71
AK		 9669 adapter = netdev_priv(netdev);
9670
9671 adapter->netdev = netdev;
9672 adapter->pdev = pdev;
9673 hw = &adapter->hw;
9674 hw->back = adapter;
b3f4d599 9675 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 9676
05857980 9677 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 9678 pci_resource_len(pdev, 0));
2a1a091c 9679 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 9680 if (!hw->hw_addr) {
9681 err = -EIO;
9682 goto err_ioremap;
9683 }
9684
0edc3527 9685 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 9686 ixgbe_set_ethtool_ops(netdev);
9a799d71 9687 netdev->watchdog_timeo = 5 * HZ;
339de30f 9688 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 9689
9a799d71 9690 /* Setup hw api */
37689010 9691 hw->mac.ops = *ii->mac_ops;
021230d4 9692 hw->mac.type = ii->mac;
9a900eca 9693 hw->mvals = ii->mvals;
b71f6c40
ET		 9694 if (ii->link_ops)
9695 hw->link.ops = *ii->link_ops;
9a799d71 9696
c44ade9e 9697 /* EEPROM */
37689010 9698 hw->eeprom.ops = *ii->eeprom_ops;
9a900eca 9699 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 9700 if (ixgbe_removed(hw->hw_addr)) {
9701 err = -EIO;
9702 goto err_ioremap;
9703 }
c44ade9e 9704 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
b4f47a48 9705 if (!(eec & BIT(8)))
c44ade9e
JB		 9706 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
9707
9708 /* PHY */
37689010 9709 hw->phy.ops = *ii->phy_ops;
c4900be0 9710 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 9711 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
9712 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
9713 hw->phy.mdio.mmds = 0;
9714 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9715 hw->phy.mdio.dev = netdev;
9716 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
9717 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 9718
9a799d71 9719 /* setup the private structure */
55570b6f 9720 err = ixgbe_sw_init(adapter, ii);
9a799d71
AK		 9721 if (err)
9722 goto err_sw_init;
9723
dbd15b8f
DS		 9724 /* Make sure the SWFW semaphore is in a valid state */
9725 if (hw->mac.ops.init_swfw_sync)
9726 hw->mac.ops.init_swfw_sync(hw);
9727
e86bff0e 9728 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 9729 switch (adapter->hw.mac.type) {
9730 case ixgbe_mac_82599EB:
9731 case ixgbe_mac_X540:
9a75a1ac
DS		 9732 case ixgbe_mac_X550:
9733 case ixgbe_mac_X550EM_x:
49425dfc 9734 case ixgbe_mac_x550em_a:
e86bff0e 9735 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 9736 break;
9737 default:
9738 break;
9739 }
e86bff0e 9740
bf069c97
DS		 9741 /*
9742 * If there is a fan on this device and it has failed log the
9743 * failure.
9744 */
9745 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
9746 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
9747 if (esdp & IXGBE_ESDP_SDP1)
396e799c 9748 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 9749 }
9750
8ef78adc
PWJ		 9751 if (allow_unsupported_sfp)
9752 hw->allow_unsupported_sfp = allow_unsupported_sfp;
9753
c44ade9e 9754 /* reset_hw fills in the perm_addr as well */
119fc60a 9755 hw->phy.reset_if_overtemp = true;
c44ade9e 9756 err = hw->mac.ops.reset_hw(hw);
119fc60a 9757 hw->phy.reset_if_overtemp = false;
b3eb4e18 9758 ixgbe_set_eee_capable(adapter);
29a8dca1 9759 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 9760 err = 0;
9761 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 9762 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
9763 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 9764 goto err_sw_init;
9765 } else if (err) {
849c4542 9766 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 9767 goto err_sw_init;
9768 }
9769
99d74487 9770#ifdef CONFIG_PCI_IOV
60a1a680
GR		 9771 /* SR-IOV not supported on the 82598 */
9772 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9773 goto skip_sriov;
9774 /* Mailbox */
9775 ixgbe_init_mbx_params_pf(hw);
37689010 9776 hw->mbx.ops = ii->mbx_ops;
dcc23e3a 9777 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 9778 ixgbe_enable_sriov(adapter);
60a1a680 9779skip_sriov:
1cdd1ec8 9780
99d74487 9781#endif
396e799c 9782 netdev->features = NETIF_F_SG |
082757af
DS		 9783 NETIF_F_TSO |
9784 NETIF_F_TSO6 |
082757af 9785 NETIF_F_RXHASH |
49763de0 9786 NETIF_F_RXCSUM |
b83e3010
AD		 9787 NETIF_F_HW_CSUM;
9788
9789#define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
9790 NETIF_F_GSO_GRE_CSUM | \
7e13318d 9791 NETIF_F_GSO_IPXIP4 | \
bf2d1df3 9792 NETIF_F_GSO_IPXIP6 | \
b83e3010
AD		 9793 NETIF_F_GSO_UDP_TUNNEL | \
9794 NETIF_F_GSO_UDP_TUNNEL_CSUM)
9795
9796 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
9797 netdev->features |= NETIF_F_GSO_PARTIAL |
9798 IXGBE_GSO_PARTIAL_FEATURES;
ad31c402 9799
49763de0 9800 if (hw->mac.type >= ixgbe_mac_82599EB)
53692b1d 9801 netdev->features |= NETIF_F_SCTP_CRC;
49763de0
AD		 9802
9803 /* copy netdev features into list of user selectable features */
b83e3010 9804 netdev->hw_features |= netdev->features |
3d951822 9805 NETIF_F_HW_VLAN_CTAG_FILTER |
b83e3010
AD		 9806 NETIF_F_HW_VLAN_CTAG_RX |
9807 NETIF_F_HW_VLAN_CTAG_TX |
9808 NETIF_F_RXALL |
49763de0
AD		 9809 NETIF_F_HW_L2FW_DOFFLOAD;
9810
9811 if (hw->mac.type >= ixgbe_mac_82599EB)
9812 netdev->hw_features |= NETIF_F_NTUPLE |
b82b17d9 9813 NETIF_F_HW_TC;
45a5ead0 9814
b83e3010
AD		 9815 if (pci_using_dac)
9816 netdev->features |= NETIF_F_HIGHDMA;
9817
5eee87cd
AD		 9818 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
9819 netdev->hw_enc_features |= netdev->vlan_features;
9820 netdev->mpls_features |= NETIF_F_HW_CSUM;
9821
b83e3010
AD		 9822 /* set this bit last since it cannot be part of vlan_features */
9823 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
9824 NETIF_F_HW_VLAN_CTAG_RX |
9825 NETIF_F_HW_VLAN_CTAG_TX;
ad31c402 9826
01789349 9827 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 9828 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 9829
91c527a5
JW		 9830 /* MTU range: 68 - 9710 */
9831 netdev->min_mtu = ETH_MIN_MTU;
9832 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
9833
7a6b6f51 9834#ifdef CONFIG_IXGBE_DCB
8829009d 9835 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
3f40c74c 9836 netdev->dcbnl_ops = &ixgbe_dcbnl_ops;
2f90b865
AD		 9837#endif
9838
eacd73f7 9839#ifdef IXGBE_FCOE
0d551589 9840 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 9841 unsigned int fcoe_l;
9842
eacd73f7
YZ		 9843 if (hw->mac.ops.get_device_caps) {
9844 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 9845 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
9846 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 9847 }
7c8ae65a 9848
d3cb9869
AD		 9849
9850 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
9851 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 9852
a58915c7
AD		 9853 netdev->features |= NETIF_F_FSO |
9854 NETIF_F_FCOE_CRC;
9855
7c8ae65a
AD		 9856 netdev->vlan_features |= NETIF_F_FSO |
9857 NETIF_F_FCOE_CRC |
9858 NETIF_F_FCOE_MTU;
5e09d7f6 9859 }
eacd73f7 9860#endif /* IXGBE_FCOE */
9a799d71 9861
082757af
DS		 9862 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9863 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 9864 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 9865 netdev->features |= NETIF_F_LRO;
9866
9a799d71 9867 /* make sure the EEPROM is good */
c44ade9e 9868 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 9869 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 9870 err = -EIO;
35937c05 9871 goto err_sw_init;
9a799d71
AK		 9872 }
9873
c7374b5a
SV		 9874 eth_platform_get_mac_address(&adapter->pdev->dev,
9875 adapter->hw.mac.perm_addr);
c762dff2 9876
9a799d71 9877 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 9878
aaeb6cdf 9879 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 9880 e_dev_err("invalid MAC address\n");
9a799d71 9881 err = -EIO;
35937c05 9882 goto err_sw_init;
9a799d71
AK		 9883 }
9884
56768045
TD		 9885 /* Set hw->mac.addr to permanent MAC address */
9886 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
c9f53e63 9887 ixgbe_mac_set_default_filter(adapter);
5d7daa35 9888
7086400d 9889 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 9890 (unsigned long) adapter);
9a799d71 9891
58cf663f
MR		 9892 if (ixgbe_removed(hw->hw_addr)) {
9893 err = -EIO;
9894 goto err_sw_init;
9895 }
7086400d 9896 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 9897 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 9898 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 9899
021230d4
AV		 9900 err = ixgbe_init_interrupt_scheme(adapter);
9901 if (err)
9902 goto err_sw_init;
9a799d71 9903
8e2813f5 9904 /* WOL not supported for all devices */
c23f5b6b 9905 adapter->wol = 0;
8e2813f5 9906 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 9907 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 9908 pdev->subsystem_device);
6b92b0ba 9909 if (hw->wol_enabled)
9417c464 9910 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 9911
e8e26350
PW		 9912 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9913
15e5209f
ET		 9914 /* save off EEPROM version number */
9915 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
9916 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
9917
04f165ef 9918 /* pick up the PCI bus settings for reporting later */
e027d1ae 9919 if (ixgbe_pcie_from_parent(hw))
b8e82001 9920 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 9921 else
9922 hw->mac.ops.get_bus_info(hw);
04f165ef 9923
e027d1ae
JK		 9924 /* calculate the expected PCIe bandwidth required for optimal
9925 * performance. Note that some older parts will never have enough
9926 * bandwidth due to being older generation PCIe parts. We clamp these
9927 * parts to ensure no warning is displayed if it can't be fixed.
9928 */
9929 switch (hw->mac.type) {
9930 case ixgbe_mac_82598EB:
9931 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
9932 break;
9933 default:
9934 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
9935 break;
0c254d86 9936 }
caafb95d
JK		 9937
9938 /* don't check link if we failed to enumerate functions */
9939 if (expected_gts > 0)
9940 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 9941
339de30f 9942 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 9943 if (err)
339de30f 9944 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 9945 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
9946 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
9947 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 9948 part_str);
6a2aae5a
JK		 9949 else
9950 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
9951 hw->mac.type, hw->phy.type, part_str);
9952
9953 e_dev_info("%pM\n", netdev->dev_addr);
9954
9a799d71 9955 /* reset the hardware with the new settings */
794caeb2 9956 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 9957 if (err == IXGBE_ERR_EEPROM_VERSION) {
9958 /* We are running on a pre-production device, log a warning */
849c4542
ET		 9959 e_dev_warn("This device is a pre-production adapter/LOM. "
9960 "Please be aware there may be issues associated "
9961 "with your hardware. If you are experiencing "
9962 "problems please contact your Intel or hardware "
9963 "representative who provided you with this "
9964 "hardware.\n");
794caeb2 9965 }
9a799d71
AK		 9966 strcpy(netdev->name, "eth%d");
9967 err = register_netdev(netdev);
9968 if (err)
9969 goto err_register;
9970
0fb6a55c
ET		 9971 pci_set_drvdata(pdev, adapter);
9972
ec74a471
ET		 9973 /* power down the optics for 82599 SFP+ fiber */
9974 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 9975 hw->mac.ops.disable_tx_laser(hw);
9976
54386467
JB		 9977 /* carrier off reporting is important to ethtool even BEFORE open */
9978 netif_carrier_off(netdev);
9979
5dd2d332 9980#ifdef CONFIG_IXGBE_DCA
652f093f 9981 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 9982 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 9983 ixgbe_setup_dca(adapter);
9984 }
9985#endif
1cdd1ec8 9986 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 9987 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 9988 for (i = 0; i < adapter->num_vfs; i++)
9989 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9990 }
9991
2466dd9c
JK		 9992 /* firmware requires driver version to be 0xFFFFFFFF
9993 * since os does not support feature
9994 */
9612de92 9995 if (hw->mac.ops.set_fw_drv_ver)
cb8e0514
TN		 9996 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF,
9997 sizeof(ixgbe_driver_version) - 1,
9998 ixgbe_driver_version);
9612de92 9999
0365e6e4
PW		 10000 /* add san mac addr to netdev */
10001 ixgbe_add_sanmac_netdev(netdev);
9a799d71 10002
ea81875a 10003 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 10004
1210982b 10005#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 10006 if (ixgbe_sysfs_init(adapter))
10007 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 10008#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 10009
00949167 10010 ixgbe_dbg_adapter_init(adapter);
00949167 10011
d1a35ee2
ET		 10012 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
10013 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 10014 hw->mac.ops.setup_link(hw,
10015 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
10016 true);
10017
9a799d71
AK		 10018 return 0;
10019
10020err_register:
5eba3699 10021 ixgbe_release_hw_control(adapter);
7a921c93 10022 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 10023err_sw_init:
99d74487 10024 ixgbe_disable_sriov(adapter);
7086400d 10025 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 10026 iounmap(adapter->io_addr);
1cdaaf54 10027 kfree(adapter->jump_tables[0]);
5d7daa35 10028 kfree(adapter->mac_table);
9a799d71 10029err_ioremap:
b5b2ffc0 10030 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 10031 free_netdev(netdev);
10032err_alloc_etherdev:
56d766d6 10033 pci_release_mem_regions(pdev);
9a799d71
AK		 10034err_pci_reg:
10035err_dma:
b5b2ffc0 10036 if (!adapter || disable_dev)
41c62843 10037 pci_disable_device(pdev);
9a799d71
AK		 10038 return err;
10039}
10040
10041/**
10042 * ixgbe_remove - Device Removal Routine
10043 * @pdev: PCI device information struct
10044 *
10045 * ixgbe_remove is called by the PCI subsystem to alert the driver
10046 * that it should release a PCI device. The could be caused by a
10047 * Hot-Plug event, or because the driver is going to be removed from
10048 * memory.
10049 **/
9f9a12f8 10050static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 10051{
c60fbb00 10052 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 10053 struct net_device *netdev;
b5b2ffc0 10054 bool disable_dev;
1cdaaf54 10055 int i;
9a799d71 10056
0fb6a55c
ET		 10057 /* if !adapter then we already cleaned up in probe */
10058 if (!adapter)
10059 return;
10060
10061 netdev = adapter->netdev;
00949167 10062 ixgbe_dbg_adapter_exit(adapter);
00949167 10063
09f40aed 10064 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 10065 cancel_work_sync(&adapter->service_task);
9a799d71 10066
3a6a4eda 10067
5dd2d332 10068#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 10069 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
10070 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
10071 dca_remove_requester(&pdev->dev);
9de7605e
MR		 10072 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
10073 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 10074 }
10075
10076#endif
1210982b 10077#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 10078 ixgbe_sysfs_exit(adapter);
1210982b 10079#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 10080
0365e6e4
PW		 10081 /* remove the added san mac */
10082 ixgbe_del_sanmac_netdev(netdev);
10083
da36b647 10084#ifdef CONFIG_PCI_IOV
7837e286 10085 ixgbe_disable_sriov(adapter);
da36b647 10086#endif
6b010e9b
AW		 10087 if (netdev->reg_state == NETREG_REGISTERED)
10088 unregister_netdev(netdev);
10089
7a921c93 10090 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 10091
021230d4 10092 ixgbe_release_hw_control(adapter);
9a799d71 10093
2b1588c3
AD		 10094#ifdef CONFIG_DCB
10095 kfree(adapter->ixgbe_ieee_pfc);
10096 kfree(adapter->ixgbe_ieee_ets);
10097
10098#endif
2a1a091c 10099 iounmap(adapter->io_addr);
56d766d6 10100 pci_release_mem_regions(pdev);
9a799d71 10101
849c4542 10102 e_dev_info("complete\n");
021230d4 10103
1cdaaf54
AN		 10104 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
10105 if (adapter->jump_tables[i]) {
10106 kfree(adapter->jump_tables[i]->input);
10107 kfree(adapter->jump_tables[i]->mask);
10108 }
10109 kfree(adapter->jump_tables[i]);
10110 }
10111
5d7daa35 10112 kfree(adapter->mac_table);
b5b2ffc0 10113 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 10114 free_netdev(netdev);
10115
19d5afd4 10116 pci_disable_pcie_error_reporting(pdev);
6fabd715 10117
b5b2ffc0 10118 if (disable_dev)
41c62843 10119 pci_disable_device(pdev);
9a799d71
AK		 10120}
10121
10122/**
10123 * ixgbe_io_error_detected - called when PCI error is detected
10124 * @pdev: Pointer to PCI device
10125 * @state: The current pci connection state
10126 *
10127 * This function is called after a PCI bus error affecting
10128 * this device has been detected.
10129 */
10130static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 10131 pci_channel_state_t state)
9a799d71 10132{
c60fbb00
AD		 10133 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
10134 struct net_device *netdev = adapter->netdev;
9a799d71 10135
83c61fa9 10136#ifdef CONFIG_PCI_IOV
14438464 10137 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 10138 struct pci_dev *bdev, *vfdev;
10139 u32 dw0, dw1, dw2, dw3;
10140 int vf, pos;
10141 u16 req_id, pf_func;
10142
10143 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
10144 adapter->num_vfs == 0)
10145 goto skip_bad_vf_detection;
10146
10147 bdev = pdev->bus->self;
62f87c0e 10148 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 10149 bdev = bdev->bus->self;
10150
10151 if (!bdev)
10152 goto skip_bad_vf_detection;
10153
10154 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
10155 if (!pos)
10156 goto skip_bad_vf_detection;
10157
14438464
MR		 10158 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
10159 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
10160 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
10161 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
10162 if (ixgbe_removed(hw->hw_addr))
10163 goto skip_bad_vf_detection;
83c61fa9
GR		 10164
10165 req_id = dw1 >> 16;
10166 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
10167 if (!(req_id & 0x0080))
10168 goto skip_bad_vf_detection;
10169
10170 pf_func = req_id & 0x01;
10171 if ((pf_func & 1) == (pdev->devfn & 1)) {
10172 unsigned int device_id;
10173
10174 vf = (req_id & 0x7F) >> 1;
10175 e_dev_err("VF %d has caused a PCIe error\n", vf);
10176 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
10177 "%8.8x\tdw3: %8.8x\n",
10178 dw0, dw1, dw2, dw3);
10179 switch (adapter->hw.mac.type) {
10180 case ixgbe_mac_82599EB:
10181 device_id = IXGBE_82599_VF_DEVICE_ID;
10182 break;
10183 case ixgbe_mac_X540:
10184 device_id = IXGBE_X540_VF_DEVICE_ID;
10185 break;
9a75a1ac
DS		 10186 case ixgbe_mac_X550:
10187 device_id = IXGBE_DEV_ID_X550_VF;
10188 break;
10189 case ixgbe_mac_X550EM_x:
10190 device_id = IXGBE_DEV_ID_X550EM_X_VF;
10191 break;
49425dfc
MR		 10192 case ixgbe_mac_x550em_a:
10193 device_id = IXGBE_DEV_ID_X550EM_A_VF;
10194 break;
83c61fa9
GR		 10195 default:
10196 device_id = 0;
10197 break;
10198 }
10199
10200 /* Find the pci device of the offending VF */
36e90319 10201 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 10202 while (vfdev) {
10203 if (vfdev->devfn == (req_id & 0xFF))
10204 break;
36e90319 10205 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 10206 device_id, vfdev);
10207 }
10208 /*
10209 * There's a slim chance the VF could have been hot plugged,
10210 * so if it is no longer present we don't need to issue the
10211 * VFLR. Just clean up the AER in that case.
10212 */
10213 if (vfdev) {
9079e416 10214 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 10215 /* Free device reference count */
10216 pci_dev_put(vfdev);
83c61fa9
GR		 10217 }
10218
10219 pci_cleanup_aer_uncorrect_error_status(pdev);
10220 }
10221
10222 /*
10223 * Even though the error may have occurred on the other port
10224 * we still need to increment the vf error reference count for
10225 * both ports because the I/O resume function will be called
10226 * for both of them.
10227 */
10228 adapter->vferr_refcount++;
10229
10230 return PCI_ERS_RESULT_RECOVERED;
10231
10232skip_bad_vf_detection:
10233#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 10234 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
10235 return PCI_ERS_RESULT_DISCONNECT;
10236
41c62843 10237 rtnl_lock();
9a799d71
AK		 10238 netif_device_detach(netdev);
10239
41c62843
MR		 10240 if (state == pci_channel_io_perm_failure) {
10241 rtnl_unlock();
3044b8d1 10242 return PCI_ERS_RESULT_DISCONNECT;
41c62843 10243 }
3044b8d1 10244
9a799d71 10245 if (netif_running(netdev))
126db13f 10246 ixgbe_close_suspend(adapter);
41c62843
MR		 10247
10248 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
10249 pci_disable_device(pdev);
10250 rtnl_unlock();
9a799d71 10251
b4617240 10252 /* Request a slot reset. */
9a799d71
AK		 10253 return PCI_ERS_RESULT_NEED_RESET;
10254}
10255
10256/**
10257 * ixgbe_io_slot_reset - called after the pci bus has been reset.
10258 * @pdev: Pointer to PCI device
10259 *
10260 * Restart the card from scratch, as if from a cold-boot.
10261 */
10262static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
10263{
c60fbb00 10264 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 10265 pci_ers_result_t result;
10266 int err;
9a799d71 10267
9ce77666 10268 if (pci_enable_device_mem(pdev)) {
396e799c 10269 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 10270 result = PCI_ERS_RESULT_DISCONNECT;
10271 } else {
4e857c58 10272 smp_mb__before_atomic();
41c62843 10273 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 10274 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 10275 pci_set_master(pdev);
10276 pci_restore_state(pdev);
c0e1f68b 10277 pci_save_state(pdev);
9a799d71 10278
dd4d8ca6 10279 pci_wake_from_d3(pdev, false);
9a799d71 10280
6fabd715 10281 ixgbe_reset(adapter);
88512539 10282 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 10283 result = PCI_ERS_RESULT_RECOVERED;
10284 }
10285
10286 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10287 if (err) {
849c4542
ET		 10288 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
10289 "failed 0x%0x\n", err);
6fabd715
PWJ		 10290 /* non-fatal, continue */
10291 }
9a799d71 10292
6fabd715 10293 return result;
9a799d71
AK		 10294}
10295
10296/**
10297 * ixgbe_io_resume - called when traffic can start flowing again.
10298 * @pdev: Pointer to PCI device
10299 *
10300 * This callback is called when the error recovery driver tells us that
10301 * its OK to resume normal operation.
10302 */
10303static void ixgbe_io_resume(struct pci_dev *pdev)
10304{
c60fbb00
AD		 10305 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
10306 struct net_device *netdev = adapter->netdev;
9a799d71 10307
83c61fa9
GR		 10308#ifdef CONFIG_PCI_IOV
10309 if (adapter->vferr_refcount) {
10310 e_info(drv, "Resuming after VF err\n");
10311 adapter->vferr_refcount--;
10312 return;
10313 }
10314
10315#endif
126db13f 10316 rtnl_lock();
c7ccde0f 10317 if (netif_running(netdev))
126db13f 10318 ixgbe_open(netdev);
9a799d71
AK		 10319
10320 netif_device_attach(netdev);
126db13f 10321 rtnl_unlock();
9a799d71
AK		 10322}
10323
3646f0e5 10324static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 10325 .error_detected = ixgbe_io_error_detected,
10326 .slot_reset = ixgbe_io_slot_reset,
10327 .resume = ixgbe_io_resume,
10328};
10329
10330static struct pci_driver ixgbe_driver = {
10331 .name = ixgbe_driver_name,
10332 .id_table = ixgbe_pci_tbl,
10333 .probe = ixgbe_probe,
9f9a12f8 10334 .remove = ixgbe_remove,
9a799d71
AK		 10335#ifdef CONFIG_PM
10336 .suspend = ixgbe_suspend,
10337 .resume = ixgbe_resume,
10338#endif
10339 .shutdown = ixgbe_shutdown,
da36b647 10340 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 10341 .err_handler = &ixgbe_err_handler
10342};
10343
10344/**
10345 * ixgbe_init_module - Driver Registration Routine
10346 *
10347 * ixgbe_init_module is the first routine called when the driver is
10348 * loaded. All it does is register with the PCI subsystem.
10349 **/
10350static int __init ixgbe_init_module(void)
10351{
10352 int ret;
c7689578 10353 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 10354 pr_info("%s\n", ixgbe_copyright);
9a799d71 10355
780484d8
MR		 10356 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
10357 if (!ixgbe_wq) {
10358 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
10359 return -ENOMEM;
10360 }
10361
00949167 10362 ixgbe_dbg_init();
00949167 10363
f01fc1a8
JK		 10364 ret = pci_register_driver(&ixgbe_driver);
10365 if (ret) {
6b836879 10366 destroy_workqueue(ixgbe_wq);
f01fc1a8 10367 ixgbe_dbg_exit();
f01fc1a8
JK		 10368 return ret;
10369 }
10370
5dd2d332 10371#ifdef CONFIG_IXGBE_DCA
bd0362dd 10372 dca_register_notify(&dca_notifier);
bd0362dd 10373#endif
5dd2d332 10374
f01fc1a8 10375 return 0;
9a799d71 10376}
b4617240 10377
9a799d71
AK		 10378module_init(ixgbe_init_module);
10379
10380/**
10381 * ixgbe_exit_module - Driver Exit Cleanup Routine
10382 *
10383 * ixgbe_exit_module is called just before the driver is removed
10384 * from memory.
10385 **/
10386static void __exit ixgbe_exit_module(void)
10387{
5dd2d332 10388#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 10389 dca_unregister_notify(&dca_notifier);
10390#endif
9a799d71 10391 pci_unregister_driver(&ixgbe_driver);
00949167 10392
00949167 10393 ixgbe_dbg_exit();
780484d8
MR		 10394 if (ixgbe_wq) {
10395 destroy_workqueue(ixgbe_wq);
10396 ixgbe_wq = NULL;
10397 }
9a799d71 10398}
bd0362dd 10399
5dd2d332 10400#ifdef CONFIG_IXGBE_DCA
bd0362dd 10401static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 10402 void *p)
bd0362dd
JC		 10403{
10404 int ret_val;
10405
10406 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 10407 __ixgbe_notify_dca);
bd0362dd
JC		 10408
10409 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
10410}
b453368d 10411
5dd2d332 10412#endif /* CONFIG_IXGBE_DCA */
849c4542 10413
9a799d71
AK		 10414module_exit(ixgbe_exit_module);
10415
10416/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)