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net: sched: push cls related args into cls_common structure
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
37689010 4 Copyright(c) 1999 - 2016 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
92470808
JF		 52#include <linux/bpf.h>
53#include <linux/bpf_trace.h>
54#include <linux/atomic.h>
eacd73f7 55#include <scsi/fc/fc_fcoe.h>
b3a49557 56#include <net/udp_tunnel.h>
b82b17d9
JF		 57#include <net/pkt_cls.h>
58#include <net/tc_act/tc_gact.h>
947f8a45 59#include <net/tc_act/tc_mirred.h>
9f3c7504 60#include <net/vxlan.h>
2a20525b 61#include <net/mpls.h>
9a799d71
AK		 62
63#include "ixgbe.h"
64#include "ixgbe_common.h"
ee5f784a 65#include "ixgbe_dcb_82599.h"
1cdd1ec8 66#include "ixgbe_sriov.h"
b82b17d9 67#include "ixgbe_model.h"
9a799d71
AK		 68
69char ixgbe_driver_name[] = "ixgbe";
9c8eb720 70static const char ixgbe_driver_string[] =
e8e9f696 71 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 72#ifdef IXGBE_FCOE
ea81875a
NP		 73char ixgbe_default_device_descr[] =
74 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 75#else
76static char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78#endif
01ec5525 79#define DRV_VERSION "5.1.0-k"
9c8eb720 80const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 81static const char ixgbe_copyright[] =
49425dfc 82 "Copyright (c) 1999-2016 Intel Corporation.";
9a799d71 83
f44e751b
DS		 84static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
85
9a799d71 86static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 87 [board_82598] = &ixgbe_82598_info,
88 [board_82599] = &ixgbe_82599_info,
89 [board_X540] = &ixgbe_X540_info,
90 [board_X550] = &ixgbe_X550_info,
91 [board_X550EM_x] = &ixgbe_X550EM_x_info,
8dc963e1 92 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info,
49425dfc 93 [board_x550em_a] = &ixgbe_x550em_a_info,
b3eb4e18 94 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info,
9a799d71
AK		 95};
96
97/* ixgbe_pci_tbl - PCI Device ID Table
98 *
99 * Wildcard entries (PCI_ANY_ID) should come last
100 * Last entry must be all 0s
101 *
102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
103 * Class, Class Mask, private data (not used) }
104 */
9baa3c34 105static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
a711ad89 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
6a14ee0c 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
18e01ee7 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x},
6a14ee0c 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 142 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
8dc963e1 143 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw},
f572b2c4
MR		 144 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
145 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
49425dfc 146 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
200157c2
MR		 147 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
148 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
92ed8430 149 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
2d40cd17 150 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
b3eb4e18
MR		 151 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw },
152 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw },
9a799d71
AK		 153 /* required last entry */
154 {0, }
155};
156MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
157
5dd2d332 158#ifdef CONFIG_IXGBE_DCA
bd0362dd 159static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 160 void *p);
bd0362dd
JC		 161static struct notifier_block dca_notifier = {
162 .notifier_call = ixgbe_notify_dca,
163 .next = NULL,
164 .priority = 0
165};
166#endif
167
1cdd1ec8
GR		 168#ifdef CONFIG_PCI_IOV
169static unsigned int max_vfs;
170module_param(max_vfs, uint, 0);
e8e9f696 171MODULE_PARM_DESC(max_vfs,
170e8543 172 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 173#endif /* CONFIG_PCI_IOV */
174
8ef78adc
PWJ		 175static unsigned int allow_unsupported_sfp;
176module_param(allow_unsupported_sfp, uint, 0);
177MODULE_PARM_DESC(allow_unsupported_sfp,
178 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
179
b3f4d599 180#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
181static int debug = -1;
182module_param(debug, int, 0);
183MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
184
9a799d71
AK		 185MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
186MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
187MODULE_LICENSE("GPL");
188MODULE_VERSION(DRV_VERSION);
189
780484d8
MR		 190static struct workqueue_struct *ixgbe_wq;
191
14438464 192static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
b3eb4e18 193static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *);
14438464 194
b8e82001
JK		 195static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
196 u32 reg, u16 *value)
197{
b8e82001
JK		 198 struct pci_dev *parent_dev;
199 struct pci_bus *parent_bus;
200
201 parent_bus = adapter->pdev->bus->parent;
202 if (!parent_bus)
203 return -1;
204
205 parent_dev = parent_bus->self;
206 if (!parent_dev)
207 return -1;
208
c0798edf 209 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 210 return -1;
211
c0798edf 212 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 213 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
214 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
215 return -1;
b8e82001
JK		 216 return 0;
217}
218
219static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
220{
221 struct ixgbe_hw *hw = &adapter->hw;
222 u16 link_status = 0;
223 int err;
224
225 hw->bus.type = ixgbe_bus_type_pci_express;
226
227 /* Get the negotiated link width and speed from PCI config space of the
228 * parent, as this device is behind a switch
229 */
230 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
231
232 /* assume caller will handle error case */
233 if (err)
234 return err;
235
236 hw->bus.width = ixgbe_convert_bus_width(link_status);
237 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
238
239 return 0;
240}
241
e027d1ae
JK		 242/**
243 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
244 * @hw: hw specific details
245 *
246 * This function is used by probe to determine whether a device's PCI-Express
247 * bandwidth details should be gathered from the parent bus instead of from the
248 * device. Used to ensure that various locations all have the correct device ID
249 * checks.
250 */
251static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
252{
253 switch (hw->device_id) {
254 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 255 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 256 return true;
257 default:
258 return false;
259 }
260}
261
262static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
263 int expected_gts)
264{
f9328bc6 265 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 266 int max_gts = 0;
267 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
268 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
269 struct pci_dev *pdev;
270
f9328bc6
DS		 271 /* Some devices are not connected over PCIe and thus do not negotiate
272 * speed. These devices do not have valid bus info, and thus any report
273 * we generate may not be correct.
274 */
275 if (hw->bus.type == ixgbe_bus_type_internal)
276 return;
277
56d1392f 278 /* determine whether to use the parent device */
e027d1ae
JK		 279 if (ixgbe_pcie_from_parent(&adapter->hw))
280 pdev = adapter->pdev->bus->parent->self;
281 else
282 pdev = adapter->pdev;
283
284 if (pcie_get_minimum_link(pdev, &speed, &width) ||
285 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
286 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
287 return;
288 }
289
290 switch (speed) {
291 case PCIE_SPEED_2_5GT:
292 /* 8b/10b encoding reduces max throughput by 20% */
293 max_gts = 2 * width;
294 break;
295 case PCIE_SPEED_5_0GT:
296 /* 8b/10b encoding reduces max throughput by 20% */
297 max_gts = 4 * width;
298 break;
299 case PCIE_SPEED_8_0GT:
9f0a433c 300 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 301 max_gts = 8 * width;
302 break;
303 default:
304 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
305 return;
306 }
307
308 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
309 max_gts);
310 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
311 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
312 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
313 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
314 "Unknown"),
315 width,
316 (speed == PCIE_SPEED_2_5GT ? "20%" :
317 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 318 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 319 "Unknown"));
320
321 if (max_gts < expected_gts) {
322 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
323 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
324 expected_gts);
325 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
326 }
327}
328
7086400d
AD		 329static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
330{
331 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 332 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d 333 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
780484d8 334 queue_work(ixgbe_wq, &adapter->service_task);
7086400d
AD		 335}
336
2a1a091c
MR		 337static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
338{
339 struct ixgbe_adapter *adapter = hw->back;
340
341 if (!hw->hw_addr)
342 return;
343 hw->hw_addr = NULL;
344 e_dev_err("Adapter removed\n");
58cf663f
MR		 345 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
346 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 347}
348
f8e2472f 349static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 350{
351 u32 value;
352
353 /* The following check not only optimizes a bit by not
354 * performing a read on the status register when the
355 * register just read was a status register read that
356 * returned IXGBE_FAILED_READ_REG. It also blocks any
357 * potential recursion.
358 */
359 if (reg == IXGBE_STATUS) {
360 ixgbe_remove_adapter(hw);
361 return;
362 }
363 value = ixgbe_read_reg(hw, IXGBE_STATUS);
364 if (value == IXGBE_FAILED_READ_REG)
365 ixgbe_remove_adapter(hw);
366}
367
f8e2472f
MR		 368/**
369 * ixgbe_read_reg - Read from device register
370 * @hw: hw specific details
371 * @reg: offset of register to read
372 *
373 * Returns : value read or IXGBE_FAILED_READ_REG if removed
374 *
375 * This function is used to read device registers. It checks for device
376 * removal by confirming any read that returns all ones by checking the
377 * status register value for all ones. This function avoids reading from
378 * the hardware if a removal was previously detected in which case it
379 * returns IXGBE_FAILED_READ_REG (all ones).
380 */
381u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
382{
383 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
384 u32 value;
385
386 if (ixgbe_removed(reg_addr))
387 return IXGBE_FAILED_READ_REG;
2f2219be 388 if (unlikely(hw->phy.nw_mng_if_sel &
48301cf2 389 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) {
2f2219be
MR		 390 struct ixgbe_adapter *adapter;
391 int i;
392
393 for (i = 0; i < 200; ++i) {
394 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
395 if (likely(!value))
396 goto writes_completed;
397 if (value == IXGBE_FAILED_READ_REG) {
398 ixgbe_remove_adapter(hw);
399 return IXGBE_FAILED_READ_REG;
400 }
401 udelay(5);
402 }
403
404 adapter = hw->back;
405 e_warn(hw, "register writes incomplete %08x\n", value);
406 }
407
408writes_completed:
f8e2472f
MR		 409 value = readl(reg_addr + reg);
410 if (unlikely(value == IXGBE_FAILED_READ_REG))
411 ixgbe_check_remove(hw, reg);
412 return value;
413}
414
14438464
MR		 415static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
416{
417 u16 value;
418
419 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
420 if (value == IXGBE_FAILED_READ_CFG_WORD) {
421 ixgbe_remove_adapter(hw);
422 return true;
423 }
424 return false;
425}
426
427u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
428{
429 struct ixgbe_adapter *adapter = hw->back;
430 u16 value;
431
432 if (ixgbe_removed(hw->hw_addr))
433 return IXGBE_FAILED_READ_CFG_WORD;
434 pci_read_config_word(adapter->pdev, reg, &value);
435 if (value == IXGBE_FAILED_READ_CFG_WORD &&
436 ixgbe_check_cfg_remove(hw, adapter->pdev))
437 return IXGBE_FAILED_READ_CFG_WORD;
438 return value;
439}
440
441#ifdef CONFIG_PCI_IOV
442static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
443{
444 struct ixgbe_adapter *adapter = hw->back;
445 u32 value;
446
447 if (ixgbe_removed(hw->hw_addr))
448 return IXGBE_FAILED_READ_CFG_DWORD;
449 pci_read_config_dword(adapter->pdev, reg, &value);
450 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
451 ixgbe_check_cfg_remove(hw, adapter->pdev))
452 return IXGBE_FAILED_READ_CFG_DWORD;
453 return value;
454}
455#endif /* CONFIG_PCI_IOV */
456
ed19231c
JK		 457void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
458{
459 struct ixgbe_adapter *adapter = hw->back;
460
461 if (ixgbe_removed(hw->hw_addr))
462 return;
463 pci_write_config_word(adapter->pdev, reg, value);
464}
465
7086400d
AD		 466static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
467{
468 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
469
52f33af8 470 /* flush memory to make sure state is correct before next watchdog */
4e857c58 471 smp_mb__before_atomic();
7086400d
AD		 472 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
473}
474
dcd79aeb
TI		 475struct ixgbe_reg_info {
476 u32 ofs;
477 char *name;
478};
479
480static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
481
482 /* General Registers */
483 {IXGBE_CTRL, "CTRL"},
484 {IXGBE_STATUS, "STATUS"},
485 {IXGBE_CTRL_EXT, "CTRL_EXT"},
486
487 /* Interrupt Registers */
488 {IXGBE_EICR, "EICR"},
489
490 /* RX Registers */
491 {IXGBE_SRRCTL(0), "SRRCTL"},
492 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
493 {IXGBE_RDLEN(0), "RDLEN"},
494 {IXGBE_RDH(0), "RDH"},
495 {IXGBE_RDT(0), "RDT"},
496 {IXGBE_RXDCTL(0), "RXDCTL"},
497 {IXGBE_RDBAL(0), "RDBAL"},
498 {IXGBE_RDBAH(0), "RDBAH"},
499
500 /* TX Registers */
501 {IXGBE_TDBAL(0), "TDBAL"},
502 {IXGBE_TDBAH(0), "TDBAH"},
503 {IXGBE_TDLEN(0), "TDLEN"},
504 {IXGBE_TDH(0), "TDH"},
505 {IXGBE_TDT(0), "TDT"},
506 {IXGBE_TXDCTL(0), "TXDCTL"},
507
508 /* List Terminator */
ca8dfe25 509 { .name = NULL }
dcd79aeb
TI		 510};
511
512
513/*
514 * ixgbe_regdump - register printout routine
515 */
516static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
517{
332f2358 518 int i;
dcd79aeb
TI		 519 char rname[16];
520 u32 regs[64];
521
522 switch (reginfo->ofs) {
523 case IXGBE_SRRCTL(0):
524 for (i = 0; i < 64; i++)
525 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
526 break;
527 case IXGBE_DCA_RXCTRL(0):
528 for (i = 0; i < 64; i++)
529 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
530 break;
531 case IXGBE_RDLEN(0):
532 for (i = 0; i < 64; i++)
533 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
534 break;
535 case IXGBE_RDH(0):
536 for (i = 0; i < 64; i++)
537 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
538 break;
539 case IXGBE_RDT(0):
540 for (i = 0; i < 64; i++)
541 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
542 break;
543 case IXGBE_RXDCTL(0):
544 for (i = 0; i < 64; i++)
545 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
546 break;
547 case IXGBE_RDBAL(0):
548 for (i = 0; i < 64; i++)
549 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
550 break;
551 case IXGBE_RDBAH(0):
552 for (i = 0; i < 64; i++)
553 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
554 break;
555 case IXGBE_TDBAL(0):
556 for (i = 0; i < 64; i++)
557 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
558 break;
559 case IXGBE_TDBAH(0):
560 for (i = 0; i < 64; i++)
561 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
562 break;
563 case IXGBE_TDLEN(0):
564 for (i = 0; i < 64; i++)
565 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
566 break;
567 case IXGBE_TDH(0):
568 for (i = 0; i < 64; i++)
569 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
570 break;
571 case IXGBE_TDT(0):
572 for (i = 0; i < 64; i++)
573 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
574 break;
575 case IXGBE_TXDCTL(0):
576 for (i = 0; i < 64; i++)
577 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
578 break;
579 default:
332f2358
JP		 580 pr_info("%-15s %08x\n",
581 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs));
dcd79aeb
TI		 582 return;
583 }
584
332f2358
JP		 585 i = 0;
586 while (i < 64) {
587 int j;
588 char buf[9 * 8 + 1];
589 char *p = buf;
590
591 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7);
dcd79aeb 592 for (j = 0; j < 8; j++)
332f2358
JP		 593 p += sprintf(p, " %08x", regs[i++]);
594 pr_err("%-15s%s\n", rname, buf);
dcd79aeb
TI		 595 }
596
597}
598
33fdc82f
JF		 599static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n)
600{
601 struct ixgbe_tx_buffer *tx_buffer;
602
603 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean];
604 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
605 n, ring->next_to_use, ring->next_to_clean,
606 (u64)dma_unmap_addr(tx_buffer, dma),
607 dma_unmap_len(tx_buffer, len),
608 tx_buffer->next_to_watch,
609 (u64)tx_buffer->time_stamp);
610}
611
dcd79aeb
TI		 612/*
613 * ixgbe_dump - Print registers, tx-rings and rx-rings
614 */
615static void ixgbe_dump(struct ixgbe_adapter *adapter)
616{
617 struct net_device *netdev = adapter->netdev;
618 struct ixgbe_hw *hw = &adapter->hw;
619 struct ixgbe_reg_info *reginfo;
620 int n = 0;
33fdc82f 621 struct ixgbe_ring *ring;
729739b7 622 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 623 union ixgbe_adv_tx_desc *tx_desc;
624 struct my_u0 { u64 a; u64 b; } *u0;
625 struct ixgbe_ring *rx_ring;
626 union ixgbe_adv_rx_desc *rx_desc;
627 struct ixgbe_rx_buffer *rx_buffer_info;
dcd79aeb
TI		 628 int i = 0;
629
630 if (!netif_msg_hw(adapter))
631 return;
632
633 /* Print netdevice Info */
634 if (netdev) {
635 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 636 pr_info("Device Name state "
4a7c9726
TK		 637 "trans_start\n");
638 pr_info("%-15s %016lX %016lX\n",
c7689578
JP		 639 netdev->name,
640 netdev->state,
4a7c9726 641 dev_trans_start(netdev));
dcd79aeb
TI		 642 }
643
644 /* Print Registers */
645 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 646 pr_info(" Register Name Value\n");
dcd79aeb
TI		 647 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
648 reginfo->name; reginfo++) {
649 ixgbe_regdump(hw, reginfo);
650 }
651
652 /* Print TX Ring Summary */
653 if (!netdev || !netif_running(netdev))
e90dd264 654 return;
dcd79aeb
TI		 655
656 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 657 pr_info(" %s %s %s %s\n",
658 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
659 "leng", "ntw", "timestamp");
dcd79aeb 660 for (n = 0; n < adapter->num_tx_queues; n++) {
33fdc82f
JF		 661 ring = adapter->tx_ring[n];
662 ixgbe_print_buffer(ring, n);
663 }
664
665 for (n = 0; n < adapter->num_xdp_queues; n++) {
666 ring = adapter->xdp_ring[n];
667 ixgbe_print_buffer(ring, n);
dcd79aeb
TI		 668 }
669
670 /* Print TX Rings */
671 if (!netif_msg_tx_done(adapter))
672 goto rx_ring_summary;
673
674 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
675
676 /* Transmit Descriptor Formats
677 *
39ac868a 678 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 679 * +--------------------------------------------------------------+
680 * 0 | Buffer Address [63:0] |
681 * +--------------------------------------------------------------+
39ac868a 682 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 683 * +--------------------------------------------------------------+
684 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 685 *
686 * 82598 Advanced Transmit Descriptor (Write-Back Format)
687 * +--------------------------------------------------------------+
688 * 0 | RSV [63:0] |
689 * +--------------------------------------------------------------+
690 * 8 | RSV | STA | NXTSEQ |
691 * +--------------------------------------------------------------+
692 * 63 36 35 32 31 0
693 *
694 * 82599+ Advanced Transmit Descriptor
695 * +--------------------------------------------------------------+
696 * 0 | Buffer Address [63:0] |
697 * +--------------------------------------------------------------+
698 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
699 * +--------------------------------------------------------------+
700 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
701 *
702 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
703 * +--------------------------------------------------------------+
704 * 0 | RSV [63:0] |
705 * +--------------------------------------------------------------+
706 * 8 | RSV | STA | RSV |
707 * +--------------------------------------------------------------+
708 * 63 36 35 32 31 0
dcd79aeb
TI		 709 */
710
711 for (n = 0; n < adapter->num_tx_queues; n++) {
33fdc82f 712 ring = adapter->tx_ring[n];
c7689578 713 pr_info("------------------------------------\n");
33fdc82f 714 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index);
c7689578 715 pr_info("------------------------------------\n");
8ad88e37
JH		 716 pr_info("%s%s %s %s %s %s\n",
717 "T [desc] [address 63:0 ] ",
718 "[PlPOIdStDDt Ln] [bi->dma ] ",
719 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb 720
33fdc82f
JF		 721 for (i = 0; ring->desc && (i < ring->count); i++) {
722 tx_desc = IXGBE_TX_DESC(ring, i);
723 tx_buffer = &ring->tx_buffer_info[i];
dcd79aeb 724 u0 = (struct my_u0 *)tx_desc;
8ad88e37 725 if (dma_unmap_len(tx_buffer, len) > 0) {
332f2358
JP		 726 const char *ring_desc;
727
33fdc82f
JF		 728 if (i == ring->next_to_use &&
729 i == ring->next_to_clean)
332f2358 730 ring_desc = " NTC/U";
33fdc82f 731 else if (i == ring->next_to_use)
332f2358 732 ring_desc = " NTU";
33fdc82f 733 else if (i == ring->next_to_clean)
332f2358
JP		 734 ring_desc = " NTC";
735 else
736 ring_desc = "";
737 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s",
8ad88e37
JH		 738 i,
739 le64_to_cpu(u0->a),
740 le64_to_cpu(u0->b),
741 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 742 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 743 tx_buffer->next_to_watch,
744 (u64)tx_buffer->time_stamp,
332f2358
JP		 745 tx_buffer->skb,
746 ring_desc);
8ad88e37
JH		 747
748 if (netif_msg_pktdata(adapter) &&
749 tx_buffer->skb)
750 print_hex_dump(KERN_INFO, "",
751 DUMP_PREFIX_ADDRESS, 16, 1,
752 tx_buffer->skb->data,
753 dma_unmap_len(tx_buffer, len),
754 true);
755 }
dcd79aeb
TI		 756 }
757 }
758
759 /* Print RX Rings Summary */
760rx_ring_summary:
761 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 762 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 763 for (n = 0; n < adapter->num_rx_queues; n++) {
764 rx_ring = adapter->rx_ring[n];
c7689578
JP		 765 pr_info("%5d %5X %5X\n",
766 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 767 }
768
769 /* Print RX Rings */
770 if (!netif_msg_rx_status(adapter))
e90dd264 771 return;
dcd79aeb
TI		 772
773 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
774
39ac868a
JH		 775 /* Receive Descriptor Formats
776 *
777 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 778 * 63 1 0
779 * +-----------------------------------------------------+
780 * 0 | Packet Buffer Address [63:1] |A0/NSE|
781 * +----------------------------------------------+------+
782 * 8 | Header Buffer Address [63:1] | DD |
783 * +-----------------------------------------------------+
784 *
785 *
39ac868a 786 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 787 *
788 * 63 48 47 32 31 30 21 20 16 15 4 3 0
789 * +------------------------------------------------------+
39ac868a
JH		 790 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
791 * | Packet | IP | | | | Type | Type |
792 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 793 * +------------------------------------------------------+
794 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
795 * +------------------------------------------------------+
796 * 63 48 47 32 31 20 19 0
39ac868a
JH		 797 *
798 * 82599+ Advanced Receive Descriptor (Read) Format
799 * 63 1 0
800 * +-----------------------------------------------------+
801 * 0 | Packet Buffer Address [63:1] |A0/NSE|
802 * +----------------------------------------------+------+
803 * 8 | Header Buffer Address [63:1] | DD |
804 * +-----------------------------------------------------+
805 *
806 *
807 * 82599+ Advanced Receive Descriptor (Write-Back) Format
808 *
809 * 63 48 47 32 31 30 21 20 17 16 4 3 0
810 * +------------------------------------------------------+
811 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
812 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
813 * |/ Flow Dir Flt ID | | | | | |
814 * +------------------------------------------------------+
815 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
816 * +------------------------------------------------------+
817 * 63 48 47 32 31 20 19 0
dcd79aeb 818 */
39ac868a 819
dcd79aeb
TI		 820 for (n = 0; n < adapter->num_rx_queues; n++) {
821 rx_ring = adapter->rx_ring[n];
c7689578
JP		 822 pr_info("------------------------------------\n");
823 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
824 pr_info("------------------------------------\n");
332f2358 825 pr_info("%s%s%s\n",
8ad88e37
JH		 826 "R [desc] [ PktBuf A0] ",
827 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
332f2358
JP		 828 "<-- Adv Rx Read format");
829 pr_info("%s%s%s\n",
8ad88e37
JH		 830 "RWB[desc] [PcsmIpSHl PtRs] ",
831 "[vl er S cks ln] ---------------- [bi->skb ] ",
332f2358 832 "<-- Adv Rx Write-Back format");
dcd79aeb
TI		 833
834 for (i = 0; i < rx_ring->count; i++) {
332f2358
JP		 835 const char *ring_desc;
836
837 if (i == rx_ring->next_to_use)
838 ring_desc = " NTU";
839 else if (i == rx_ring->next_to_clean)
840 ring_desc = " NTC";
841 else
842 ring_desc = "";
843
dcd79aeb 844 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 845 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb 846 u0 = (struct my_u0 *)rx_desc;
18a8cc98 847 if (rx_desc->wb.upper.length) {
dcd79aeb 848 /* Descriptor Done */
332f2358
JP		 849 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n",
850 i,
dcd79aeb
TI		 851 le64_to_cpu(u0->a),
852 le64_to_cpu(u0->b),
332f2358
JP		 853 rx_buffer_info->skb,
854 ring_desc);
dcd79aeb 855 } else {
332f2358
JP		 856 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n",
857 i,
dcd79aeb
TI		 858 le64_to_cpu(u0->a),
859 le64_to_cpu(u0->b),
860 (u64)rx_buffer_info->dma,
332f2358
JP		 861 rx_buffer_info->skb,
862 ring_desc);
dcd79aeb 863
9c50c035
ET		 864 if (netif_msg_pktdata(adapter) &&
865 rx_buffer_info->dma) {
dcd79aeb
TI		 866 print_hex_dump(KERN_INFO, "",
867 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 868 page_address(rx_buffer_info->page) +
869 rx_buffer_info->page_offset,
f800326d 870 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 871 }
872 }
dcd79aeb
TI		 873 }
874 }
dcd79aeb
TI		 875}
876
5eba3699
AV		 877static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
878{
879 u32 ctrl_ext;
880
881 /* Let firmware take over control of h/w */
882 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
883 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 884 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 885}
886
887static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
888{
889 u32 ctrl_ext;
890
891 /* Let firmware know the driver has taken over */
892 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
893 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 894 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 895}
9a799d71 896
49ce9c2c 897/**
e8e26350
PW		 898 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
899 * @adapter: pointer to adapter struct
900 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
901 * @queue: queue to map the corresponding interrupt to
902 * @msix_vector: the vector to map to the corresponding queue
903 *
904 */
905static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 906 u8 queue, u8 msix_vector)
9a799d71
AK		 907{
908 u32 ivar, index;
e8e26350
PW		 909 struct ixgbe_hw *hw = &adapter->hw;
910 switch (hw->mac.type) {
911 case ixgbe_mac_82598EB:
912 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
913 if (direction == -1)
914 direction = 0;
915 index = (((direction * 64) + queue) >> 2) & 0x1F;
916 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
917 ivar &= ~(0xFF << (8 * (queue & 0x3)));
918 ivar |= (msix_vector << (8 * (queue & 0x3)));
919 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
920 break;
921 case ixgbe_mac_82599EB:
b93a2226 922 case ixgbe_mac_X540:
9a75a1ac
DS		 923 case ixgbe_mac_X550:
924 case ixgbe_mac_X550EM_x:
49425dfc 925 case ixgbe_mac_x550em_a:
e8e26350
PW		 926 if (direction == -1) {
927 /* other causes */
928 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
929 index = ((queue & 1) * 8);
930 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
931 ivar &= ~(0xFF << index);
932 ivar |= (msix_vector << index);
933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
934 break;
935 } else {
936 /* tx or rx causes */
937 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
938 index = ((16 * (queue & 1)) + (8 * direction));
939 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
940 ivar &= ~(0xFF << index);
941 ivar |= (msix_vector << index);
942 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
943 break;
944 }
945 default:
946 break;
947 }
9a799d71
AK		 948}
949
fe49f04a 950static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 951 u64 qmask)
fe49f04a
AD		 952{
953 u32 mask;
954
bd508178
AD		 955 switch (adapter->hw.mac.type) {
956 case ixgbe_mac_82598EB:
fe49f04a
AD		 957 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
958 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 959 break;
960 case ixgbe_mac_82599EB:
b93a2226 961 case ixgbe_mac_X540:
9a75a1ac
DS		 962 case ixgbe_mac_X550:
963 case ixgbe_mac_X550EM_x:
49425dfc 964 case ixgbe_mac_x550em_a:
fe49f04a
AD		 965 mask = (qmask & 0xFFFFFFFF);
966 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
967 mask = (qmask >> 32);
968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 969 break;
970 default:
971 break;
fe49f04a
AD		 972 }
973}
974
943561d3 975static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 976{
977 struct ixgbe_hw *hw = &adapter->hw;
978 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 979 int i;
943561d3 980 u32 data;
c84d324c 981
943561d3
AD		 982 if ((hw->fc.current_mode != ixgbe_fc_full) &&
983 (hw->fc.current_mode != ixgbe_fc_rx_pause))
984 return;
c84d324c 985
943561d3
AD		 986 switch (hw->mac.type) {
987 case ixgbe_mac_82598EB:
988 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
989 break;
990 default:
991 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
992 }
993 hwstats->lxoffrxc += data;
c84d324c 994
943561d3
AD		 995 /* refill credits (no tx hang) if we received xoff */
996 if (!data)
c84d324c 997 return;
943561d3
AD		 998
999 for (i = 0; i < adapter->num_tx_queues; i++)
1000 clear_bit(__IXGBE_HANG_CHECK_ARMED,
1001 &adapter->tx_ring[i]->state);
33fdc82f
JF		 1002
1003 for (i = 0; i < adapter->num_xdp_queues; i++)
1004 clear_bit(__IXGBE_HANG_CHECK_ARMED,
1005 &adapter->xdp_ring[i]->state);
943561d3
AD		 1006}
1007
1008static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
1009{
1010 struct ixgbe_hw *hw = &adapter->hw;
1011 struct ixgbe_hw_stats *hwstats = &adapter->stats;
1012 u32 xoff[8] = {0};
2afaa00d 1013 u8 tc;
943561d3
AD		 1014 int i;
1015 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
1016
1017 if (adapter->ixgbe_ieee_pfc)
1018 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
1019
1020 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
1021 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 1022 return;
943561d3 1023 }
c84d324c
JF		 1024
1025 /* update stats for each tc, only valid with PFC enabled */
1026 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 1027 u32 pxoffrxc;
1028
c84d324c
JF		 1029 switch (hw->mac.type) {
1030 case ixgbe_mac_82598EB:
2afaa00d 1031 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 1032 break;
c84d324c 1033 default:
2afaa00d 1034 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 1035 }
2afaa00d
PN		 1036 hwstats->pxoffrxc[i] += pxoffrxc;
1037 /* Get the TC for given UP */
1038 tc = netdev_get_prio_tc_map(adapter->netdev, i);
1039 xoff[tc] += pxoffrxc;
c84d324c
JF		 1040 }
1041
1042 /* disarm tx queues that have received xoff frames */
1043 for (i = 0; i < adapter->num_tx_queues; i++) {
1044 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1045
2afaa00d 1046 tc = tx_ring->dcb_tc;
c84d324c
JF		 1047 if (xoff[tc])
1048 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1049 }
33fdc82f
JF		 1050
1051 for (i = 0; i < adapter->num_xdp_queues; i++) {
1052 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
1053
1054 tc = xdp_ring->dcb_tc;
1055 if (xoff[tc])
1056 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state);
1057 }
26f23d82
YZ		 1058}
1059
c84d324c 1060static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1061{
7d7ce682 1062 return ring->stats.packets;
c84d324c
JF		 1063}
1064
1065static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1066{
2a47fa45
JF		 1067 struct ixgbe_adapter *adapter;
1068 struct ixgbe_hw *hw;
1069 u32 head, tail;
1070
1071 if (ring->l2_accel_priv)
1072 adapter = ring->l2_accel_priv->real_adapter;
1073 else
1074 adapter = netdev_priv(ring->netdev);
e01c31a5 1075
2a47fa45
JF		 1076 hw = &adapter->hw;
1077 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1078 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1079
1080 if (head != tail)
1081 return (head < tail) ?
1082 tail - head : (tail + ring->count - head);
1083
1084 return 0;
1085}
1086
1087static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1088{
1089 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1090 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1091 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1092
7d637bcc 1093 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1094
1095 /*
1096 * Check for a hung queue, but be thorough. This verifies
1097 * that a transmit has been completed since the previous
1098 * check AND there is at least one packet pending. The
1099 * ARMED bit is set to indicate a potential hang. The
1100 * bit is cleared if a pause frame is received to remove
1101 * false hang detection due to PFC or 802.3x frames. By
1102 * requiring this to fail twice we avoid races with
1103 * pfc clearing the ARMED bit and conditions where we
1104 * run the check_tx_hang logic with a transmit completion
1105 * pending but without time to complete it yet.
1106 */
e90dd264 1107 if (tx_done_old == tx_done && tx_pending)
c84d324c 1108 /* make sure it is true for two checks in a row */
e90dd264
MR		 1109 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1110 &tx_ring->state);
1111 /* update completed stats and continue */
1112 tx_ring->tx_stats.tx_done_old = tx_done;
1113 /* reset the countdown */
1114 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1115
e90dd264 1116 return false;
9a799d71
AK		 1117}
1118
c83c6cbd
AD		 1119/**
1120 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1121 * @adapter: driver private struct
1122 **/
1123static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1124{
1125
1126 /* Do the reset outside of interrupt context */
1127 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
57ca2a4f 1128 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
12ff3f3b 1129 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1130 ixgbe_service_event_schedule(adapter);
1131 }
1132}
e01c31a5 1133
c04f90e5
RP		 1134/**
1135 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1136 **/
1137static int ixgbe_tx_maxrate(struct net_device *netdev,
1138 int queue_index, u32 maxrate)
1139{
1140 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1141 struct ixgbe_hw *hw = &adapter->hw;
1142 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1143
1144 if (!maxrate)
1145 return 0;
1146
1147 /* Calculate the rate factor values to set */
1148 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1149 bcnrc_val /= maxrate;
1150
1151 /* clear everything but the rate factor */
1152 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1153 IXGBE_RTTBCNRC_RF_DEC_MASK;
1154
1155 /* enable the rate scheduler */
1156 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1157
1158 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1159 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1160
1161 return 0;
1162}
1163
9a799d71
AK		 1164/**
1165 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1166 * @q_vector: structure containing interrupt and ring information
e01c31a5 1167 * @tx_ring: tx ring to clean
8220bbc1 1168 * @napi_budget: Used to determine if we are in netpoll
9a799d71 1169 **/
fe49f04a 1170static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
a3a8749d 1171 struct ixgbe_ring *tx_ring, int napi_budget)
9a799d71 1172{
fe49f04a 1173 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1174 struct ixgbe_tx_buffer *tx_buffer;
1175 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1176 unsigned int total_bytes = 0, total_packets = 0;
59224555 1177 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1178 unsigned int i = tx_ring->next_to_clean;
1179
1180 if (test_bit(__IXGBE_DOWN, &adapter->state))
1181 return true;
9a799d71 1182
d3d00239 1183 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1184 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1185 i -= tx_ring->count;
12207e49 1186
729739b7 1187 do {
d3d00239
AD		 1188 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1189
1190 /* if next_to_watch is not set then there is no work pending */
1191 if (!eop_desc)
1192 break;
1193
7f83a9e6 1194 /* prevent any other reads prior to eop_desc */
7e63bf49 1195 read_barrier_depends();
7f83a9e6 1196
d3d00239
AD		 1197 /* if DD is not set pending work has not been completed */
1198 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1199 break;
8ad494b0 1200
d3d00239
AD		 1201 /* clear next_to_watch to prevent false hangs */
1202 tx_buffer->next_to_watch = NULL;
8ad494b0 1203
091a6246
AD		 1204 /* update the statistics for this packet */
1205 total_bytes += tx_buffer->bytecount;
1206 total_packets += tx_buffer->gso_segs;
1207
fd0db0ed 1208 /* free the skb */
33fdc82f
JF		 1209 if (ring_is_xdp(tx_ring))
1210 page_frag_free(tx_buffer->data);
1211 else
1212 napi_consume_skb(tx_buffer->skb, napi_budget);
fd0db0ed 1213
729739b7
AD		 1214 /* unmap skb header data */
1215 dma_unmap_single(tx_ring->dev,
1216 dma_unmap_addr(tx_buffer, dma),
1217 dma_unmap_len(tx_buffer, len),
1218 DMA_TO_DEVICE);
1219
fd0db0ed 1220 /* clear tx_buffer data */
729739b7 1221 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1222
729739b7
AD		 1223 /* unmap remaining buffers */
1224 while (tx_desc != eop_desc) {
d3d00239
AD		 1225 tx_buffer++;
1226 tx_desc++;
8ad494b0 1227 i++;
729739b7
AD		 1228 if (unlikely(!i)) {
1229 i -= tx_ring->count;
d3d00239 1230 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1231 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1232 }
e01c31a5 1233
729739b7
AD		 1234 /* unmap any remaining paged data */
1235 if (dma_unmap_len(tx_buffer, len)) {
1236 dma_unmap_page(tx_ring->dev,
1237 dma_unmap_addr(tx_buffer, dma),
1238 dma_unmap_len(tx_buffer, len),
1239 DMA_TO_DEVICE);
1240 dma_unmap_len_set(tx_buffer, len, 0);
1241 }
1242 }
1243
1244 /* move us one more past the eop_desc for start of next pkt */
1245 tx_buffer++;
1246 tx_desc++;
1247 i++;
1248 if (unlikely(!i)) {
1249 i -= tx_ring->count;
1250 tx_buffer = tx_ring->tx_buffer_info;
1251 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1252 }
1253
1254 /* issue prefetch for next Tx descriptor */
1255 prefetch(tx_desc);
12207e49 1256
729739b7
AD		 1257 /* update budget accounting */
1258 budget--;
1259 } while (likely(budget));
1260
1261 i += tx_ring->count;
9a799d71 1262 tx_ring->next_to_clean = i;
d3d00239 1263 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1264 tx_ring->stats.bytes += total_bytes;
bd198058 1265 tx_ring->stats.packets += total_packets;
d3d00239 1266 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1267 q_vector->tx.total_bytes += total_bytes;
1268 q_vector->tx.total_packets += total_packets;
b953799e 1269
c84d324c
JF		 1270 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1271 /* schedule immediate reset if we believe we hung */
1272 struct ixgbe_hw *hw = &adapter->hw;
33fdc82f 1273 e_err(drv, "Detected Tx Unit Hang %s\n"
c84d324c
JF		 1274 " Tx Queue <%d>\n"
1275 " TDH, TDT <%x>, <%x>\n"
1276 " next_to_use <%x>\n"
1277 " next_to_clean <%x>\n"
1278 "tx_buffer_info[next_to_clean]\n"
1279 " time_stamp <%lx>\n"
1280 " jiffies <%lx>\n",
33fdc82f 1281 ring_is_xdp(tx_ring) ? "(XDP)" : "",
c84d324c
JF		 1282 tx_ring->queue_index,
1283 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1284 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1285 tx_ring->next_to_use, i,
1286 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c 1287
33fdc82f
JF		 1288 if (!ring_is_xdp(tx_ring))
1289 netif_stop_subqueue(tx_ring->netdev,
1290 tx_ring->queue_index);
c84d324c
JF		 1291
1292 e_info(probe,
1293 "tx hang %d detected on queue %d, resetting adapter\n",
1294 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1295
b953799e 1296 /* schedule immediate reset if we believe we hung */
c83c6cbd 1297 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1298
1299 /* the adapter is about to reset, no point in enabling stuff */
59224555 1300 return true;
b953799e 1301 }
9a799d71 1302
33fdc82f
JF		 1303 if (ring_is_xdp(tx_ring))
1304 return !!budget;
1305
b2d96e0a
AD		 1306 netdev_tx_completed_queue(txring_txq(tx_ring),
1307 total_packets, total_bytes);
1308
e092be60 1309#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1310 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1311 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1312 /* Make sure that anybody stopping the queue after this
1313 * sees the new next_to_clean.
1314 */
1315 smp_mb();
729739b7
AD		 1316 if (__netif_subqueue_stopped(tx_ring->netdev,
1317 tx_ring->queue_index)
1318 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1319 netif_wake_subqueue(tx_ring->netdev,
1320 tx_ring->queue_index);
5b7da515 1321 ++tx_ring->tx_stats.restart_queue;
30eba97a 1322 }
e092be60 1323 }
9a799d71 1324
59224555 1325 return !!budget;
9a799d71
AK		 1326}
1327
5dd2d332 1328#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1329static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1330 struct ixgbe_ring *tx_ring,
33cf09c9 1331 int cpu)
bd0362dd 1332{
33cf09c9 1333 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1334 u32 txctrl = 0;
bdda1a61 1335 u16 reg_offset;
33cf09c9 1336
9de7605e
MR		 1337 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1338 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1339
33cf09c9
AD		 1340 switch (hw->mac.type) {
1341 case ixgbe_mac_82598EB:
bdda1a61 1342 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1343 break;
1344 case ixgbe_mac_82599EB:
b93a2226 1345 case ixgbe_mac_X540:
bdda1a61
AD		 1346 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1347 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1348 break;
1349 default:
bdda1a61
AD		 1350 /* for unknown hardware do not write register */
1351 return;
bd0362dd 1352 }
bdda1a61
AD		 1353
1354 /*
1355 * We can enable relaxed ordering for reads, but not writes when
1356 * DCA is enabled. This is due to a known issue in some chipsets
1357 * which will cause the DCA tag to be cleared.
1358 */
1359 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1360 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1361 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1362
1363 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1364}
1365
bdda1a61
AD		 1366static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1367 struct ixgbe_ring *rx_ring,
33cf09c9 1368 int cpu)
bd0362dd 1369{
33cf09c9 1370 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1371 u32 rxctrl = 0;
bdda1a61
AD		 1372 u8 reg_idx = rx_ring->reg_idx;
1373
9de7605e
MR		 1374 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1375 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1376
1377 switch (hw->mac.type) {
33cf09c9 1378 case ixgbe_mac_82599EB:
b93a2226 1379 case ixgbe_mac_X540:
bdda1a61 1380 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1381 break;
1382 default:
1383 break;
1384 }
bdda1a61
AD		 1385
1386 /*
1387 * We can enable relaxed ordering for reads, but not writes when
1388 * DCA is enabled. This is due to a known issue in some chipsets
1389 * which will cause the DCA tag to be cleared.
1390 */
1391 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1392 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1393 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1394
1395 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1396}
1397
1398static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1399{
1400 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1401 struct ixgbe_ring *ring;
bd0362dd 1402 int cpu = get_cpu();
bd0362dd 1403
33cf09c9
AD		 1404 if (q_vector->cpu == cpu)
1405 goto out_no_update;
1406
a557928e 1407 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1408 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1409
a557928e 1410 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1411 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1412
1413 q_vector->cpu = cpu;
1414out_no_update:
bd0362dd
JC		 1415 put_cpu();
1416}
1417
1418static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1419{
1420 int i;
1421
e35ec126 1422 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1423 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1425 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1426 else
1427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1428 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1429
49c7ffbe 1430 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1431 adapter->q_vector[i]->cpu = -1;
1432 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1433 }
1434}
1435
1436static int __ixgbe_notify_dca(struct device *dev, void *data)
1437{
c60fbb00 1438 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1439 unsigned long event = *(unsigned long *)data;
1440
2a72c31e 1441 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1442 return 0;
1443
bd0362dd
JC		 1444 switch (event) {
1445 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1446 /* if we're already enabled, don't do it again */
1447 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1448 break;
652f093f 1449 if (dca_add_requester(dev) == 0) {
96b0e0f6 1450 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1452 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1453 break;
1454 }
93df9465 1455 /* fall through - DCA is disabled. */
bd0362dd
JC		 1456 case DCA_PROVIDER_REMOVE:
1457 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1458 dca_remove_requester(dev);
1459 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1461 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1462 }
1463 break;
1464 }
1465
652f093f 1466 return 0;
bd0362dd 1467}
67a74ee2 1468
bdda1a61 1469#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1470
1471#define IXGBE_RSS_L4_TYPES_MASK \
1472 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1473 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1474 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1475 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1476
8a0da21b
AD		 1477static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1479 struct sk_buff *skb)
1480{
7edda4b8
FD		 1481 u16 rss_type;
1482
1483 if (!(ring->netdev->features & NETIF_F_RXHASH))
1484 return;
1485
1486 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1487 IXGBE_RXDADV_RSSTYPE_MASK;
1488
1489 if (!rss_type)
1490 return;
1491
1492 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1493 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1494 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1495}
1496
f800326d 1497#ifdef IXGBE_FCOE
ff886dfc
AD		 1498/**
1499 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1500 * @ring: structure containing ring specific data
ff886dfc
AD		 1501 * @rx_desc: advanced rx descriptor
1502 *
1503 * Returns : true if it is FCoE pkt
1504 */
57efd44c 1505static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1506 union ixgbe_adv_rx_desc *rx_desc)
1507{
1508 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1509
57efd44c 1510 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1511 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1512 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1513 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1514}
1515
f800326d 1516#endif /* IXGBE_FCOE */
e59bd25d
AV		 1517/**
1518 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1519 * @ring: structure containing ring specific data
1520 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1521 * @skb: skb currently being received and modified
1522 **/
8a0da21b 1523static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1524 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1525 struct sk_buff *skb)
9a799d71 1526{
3f207800 1527 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
3f207800
DS		 1528 bool encap_pkt = false;
1529
8a0da21b 1530 skb_checksum_none_assert(skb);
9a799d71 1531
712744be 1532 /* Rx csum disabled */
8a0da21b 1533 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1534 return;
e59bd25d 1535
a21d0822
ET		 1536 /* check for VXLAN and Geneve packets */
1537 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
3f207800
DS		 1538 encap_pkt = true;
1539 skb->encapsulation = 1;
3f207800
DS		 1540 }
1541
e59bd25d 1542 /* if IP and error */
f56e0cb1
AD		 1543 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1544 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1545 ring->rx_stats.csum_err++;
9a799d71
AK		 1546 return;
1547 }
e59bd25d 1548
f56e0cb1 1549 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1550 return;
1551
f56e0cb1 1552 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1553 /*
1554 * 82599 errata, UDP frames with a 0 checksum can be marked as
1555 * checksum errors.
1556 */
8a0da21b
AD		 1557 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1558 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1559 return;
1560
8a0da21b 1561 ring->rx_stats.csum_err++;
e59bd25d
AV		 1562 return;
1563 }
1564
9a799d71 1565 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1566 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1567 if (encap_pkt) {
1568 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1569 return;
1570
1571 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
d469251b 1572 skb->ip_summed = CHECKSUM_NONE;
3f207800
DS		 1573 return;
1574 }
1575 /* If we checked the outer header let the stack know */
1576 skb->csum_level = 1;
1577 }
9a799d71
AK		 1578}
1579
2de6aa3a
AD		 1580static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring)
1581{
1582 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0;
1583}
1584
f990b79b
AD		 1585static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1586 struct ixgbe_rx_buffer *bi)
1587{
1588 struct page *page = bi->page;
18cb652a 1589 dma_addr_t dma;
f990b79b 1590
f800326d 1591 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1592 if (likely(page))
f990b79b
AD		 1593 return true;
1594
f800326d 1595 /* alloc new page for storage */
18cb652a
AD		 1596 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1597 if (unlikely(!page)) {
1598 rx_ring->rx_stats.alloc_rx_page_failed++;
1599 return false;
f990b79b
AD		 1600 }
1601
f800326d 1602 /* map page for use */
f3213d93
AD		 1603 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1604 ixgbe_rx_pg_size(rx_ring),
1605 DMA_FROM_DEVICE,
1606 IXGBE_RX_DMA_ATTR);
f800326d
AD		 1607
1608 /*
1609 * if mapping failed free memory back to system since
1610 * there isn't much point in holding memory we can't use
1611 */
1612 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1613 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1614
f990b79b
AD		 1615 rx_ring->rx_stats.alloc_rx_page_failed++;
1616 return false;
1617 }
1618
f800326d 1619 bi->dma = dma;
18cb652a 1620 bi->page = page;
2de6aa3a 1621 bi->page_offset = ixgbe_rx_offset(rx_ring);
1b56cf49 1622 bi->pagecnt_bias = 1;
f800326d 1623
f990b79b
AD		 1624 return true;
1625}
1626
9a799d71 1627/**
f990b79b 1628 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1629 * @rx_ring: ring to place buffers on
1630 * @cleaned_count: number of buffers to replace
9a799d71 1631 **/
fc77dc3c 1632void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1633{
9a799d71 1634 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1635 struct ixgbe_rx_buffer *bi;
d5f398ed 1636 u16 i = rx_ring->next_to_use;
4f4542bf 1637 u16 bufsz;
9a799d71 1638
f800326d
AD		 1639 /* nothing to do */
1640 if (!cleaned_count)
fc77dc3c
AD		 1641 return;
1642
e4f74028 1643 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1644 bi = &rx_ring->rx_buffer_info[i];
1645 i -= rx_ring->count;
9a799d71 1646
4f4542bf
AD		 1647 bufsz = ixgbe_rx_bufsz(rx_ring);
1648
f800326d
AD		 1649 do {
1650 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1651 break;
d5f398ed 1652
f3213d93
AD		 1653 /* sync the buffer for use by the device */
1654 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
4f4542bf 1655 bi->page_offset, bufsz,
f3213d93
AD		 1656 DMA_FROM_DEVICE);
1657
f800326d
AD		 1658 /*
1659 * Refresh the desc even if buffer_addrs didn't change
1660 * because each write-back erases this info.
1661 */
1662 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1663
f990b79b
AD		 1664 rx_desc++;
1665 bi++;
9a799d71 1666 i++;
f990b79b 1667 if (unlikely(!i)) {
e4f74028 1668 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1669 bi = rx_ring->rx_buffer_info;
1670 i -= rx_ring->count;
1671 }
1672
c3630cc4
AD		 1673 /* clear the length for the next_to_use descriptor */
1674 rx_desc->wb.upper.length = 0;
f800326d
AD		 1675
1676 cleaned_count--;
1677 } while (cleaned_count);
7c6e0a43 1678
f990b79b
AD		 1679 i += rx_ring->count;
1680
ad435ec6
AD		 1681 if (rx_ring->next_to_use != i) {
1682 rx_ring->next_to_use = i;
1683
1684 /* update next to alloc since we have filled the ring */
1685 rx_ring->next_to_alloc = i;
1686
1687 /* Force memory writes to complete before letting h/w
1688 * know there are new descriptors to fetch. (Only
1689 * applicable for weak-ordered memory model archs,
1690 * such as IA-64).
1691 */
1692 wmb();
1693 writel(i, rx_ring->tail);
1694 }
9a799d71
AK		 1695}
1696
1d2024f6
AD		 1697static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1698 struct sk_buff *skb)
1699{
f800326d 1700 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1701
1702 /* set gso_size to avoid messing up TCP MSS */
1703 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1704 IXGBE_CB(skb)->append_cnt);
96be80ab 1705 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1706}
1707
1708static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1709 struct sk_buff *skb)
1710{
1711 /* if append_cnt is 0 then frame is not RSC */
1712 if (!IXGBE_CB(skb)->append_cnt)
1713 return;
1714
1715 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1716 rx_ring->rx_stats.rsc_flush++;
1717
1718 ixgbe_set_rsc_gso_size(rx_ring, skb);
1719
1720 /* gso_size is computed using append_cnt so always clear it last */
1721 IXGBE_CB(skb)->append_cnt = 0;
1722}
1723
8a0da21b
AD		 1724/**
1725 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1726 * @rx_ring: rx descriptor ring packet is being transacted on
1727 * @rx_desc: pointer to the EOP Rx descriptor
1728 * @skb: pointer to current skb being populated
f8212f97 1729 *
8a0da21b
AD		 1730 * This function checks the ring, descriptor, and packet information in
1731 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1732 * other fields within the skb.
f8212f97 1733 **/
8a0da21b
AD		 1734static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1735 union ixgbe_adv_rx_desc *rx_desc,
1736 struct sk_buff *skb)
f8212f97 1737{
43e95f11 1738 struct net_device *dev = rx_ring->netdev;
a9763f3c 1739 u32 flags = rx_ring->q_vector->adapter->flags;
43e95f11 1740
8a0da21b
AD		 1741 ixgbe_update_rsc_stats(rx_ring, skb);
1742
1743 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1744
8a0da21b
AD		 1745 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1746
a9763f3c
MR		 1747 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1748 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1749
f646968f 1750 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1751 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1752 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1753 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1754 }
1755
8a0da21b 1756 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1757
43e95f11 1758 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1759}
1760
8a0da21b
AD		 1761static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1762 struct sk_buff *skb)
aa80175a 1763{
3ffc1af5 1764 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1765}
43634e82 1766
f800326d
AD		 1767/**
1768 * ixgbe_is_non_eop - process handling of non-EOP buffers
1769 * @rx_ring: Rx ring being processed
1770 * @rx_desc: Rx descriptor for current buffer
1771 * @skb: Current socket buffer containing buffer in progress
1772 *
1773 * This function updates next to clean. If the buffer is an EOP buffer
1774 * this function exits returning false, otherwise it will place the
1775 * sk_buff in the next buffer to be chained and return true indicating
1776 * that this is in fact a non-EOP buffer.
1777 **/
1778static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1779 union ixgbe_adv_rx_desc *rx_desc,
1780 struct sk_buff *skb)
1781{
1782 u32 ntc = rx_ring->next_to_clean + 1;
1783
1784 /* fetch, update, and store next to clean */
1785 ntc = (ntc < rx_ring->count) ? ntc : 0;
1786 rx_ring->next_to_clean = ntc;
1787
1788 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1789
5a02cbd1
AD		 1790 /* update RSC append count if present */
1791 if (ring_is_rsc_enabled(rx_ring)) {
1792 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1793 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1794
1795 if (unlikely(rsc_enabled)) {
1796 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1797
1798 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1799 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1800
5a02cbd1
AD		 1801 /* update ntc based on RSC value */
1802 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1803 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1804 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1805 }
f800326d
AD		 1806 }
1807
5a02cbd1
AD		 1808 /* if we are the last buffer then there is nothing else to do */
1809 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1810 return false;
1811
f800326d
AD		 1812 /* place skb in next buffer to be received */
1813 rx_ring->rx_buffer_info[ntc].skb = skb;
1814 rx_ring->rx_stats.non_eop_descs++;
1815
1816 return true;
1817}
1818
19861ce2
AD		 1819/**
1820 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1821 * @rx_ring: rx descriptor ring packet is being transacted on
1822 * @skb: pointer to current skb being adjusted
1823 *
1824 * This function is an ixgbe specific version of __pskb_pull_tail. The
1825 * main difference between this version and the original function is that
1826 * this function can make several assumptions about the state of things
1827 * that allow for significant optimizations versus the standard function.
1828 * As a result we can do things like drop a frag and maintain an accurate
1829 * truesize for the skb.
1830 */
1831static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1832 struct sk_buff *skb)
1833{
1834 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1835 unsigned char *va;
1836 unsigned int pull_len;
1837
1838 /*
1839 * it is valid to use page_address instead of kmap since we are
1840 * working with pages allocated out of the lomem pool per
1841 * alloc_page(GFP_ATOMIC)
1842 */
1843 va = skb_frag_address(frag);
1844
1845 /*
1846 * we need the header to contain the greater of either ETH_HLEN or
1847 * 60 bytes if the skb->len is less than 60 for skb_pad.
1848 */
8496e338 1849 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1850
1851 /* align pull length to size of long to optimize memcpy performance */
1852 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1853
1854 /* update all of the pointers */
1855 skb_frag_size_sub(frag, pull_len);
1856 frag->page_offset += pull_len;
1857 skb->data_len -= pull_len;
1858 skb->tail += pull_len;
19861ce2
AD		 1859}
1860
42073d91
AD		 1861/**
1862 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1863 * @rx_ring: rx descriptor ring packet is being transacted on
1864 * @skb: pointer to current skb being updated
1865 *
1866 * This function provides a basic DMA sync up for the first fragment of an
1867 * skb. The reason for doing this is that the first fragment cannot be
1868 * unmapped until we have reached the end of packet descriptor for a buffer
1869 * chain.
1870 */
1871static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1872 struct sk_buff *skb)
1873{
1874 /* if the page was released unmap it, else just sync our portion */
1875 if (unlikely(IXGBE_CB(skb)->page_released)) {
f3213d93
AD		 1876 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
1877 ixgbe_rx_pg_size(rx_ring),
1878 DMA_FROM_DEVICE,
1879 IXGBE_RX_DMA_ATTR);
42073d91
AD		 1880 } else {
1881 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1882
1883 dma_sync_single_range_for_cpu(rx_ring->dev,
1884 IXGBE_CB(skb)->dma,
1885 frag->page_offset,
f215af8c 1886 skb_frag_size(frag),
42073d91
AD		 1887 DMA_FROM_DEVICE);
1888 }
42073d91
AD		 1889}
1890
f800326d
AD		 1891/**
1892 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1893 * @rx_ring: rx descriptor ring packet is being transacted on
1894 * @rx_desc: pointer to the EOP Rx descriptor
1895 * @skb: pointer to current skb being fixed
1896 *
92470808
JF		 1897 * Check if the skb is valid in the XDP case it will be an error pointer.
1898 * Return true in this case to abort processing and advance to next
1899 * descriptor.
1900 *
f800326d
AD		 1901 * Check for corrupted packet headers caused by senders on the local L2
1902 * embedded NIC switch not setting up their Tx Descriptors right. These
1903 * should be very rare.
1904 *
1905 * Also address the case where we are pulling data in on pages only
1906 * and as such no data is present in the skb header.
1907 *
1908 * In addition if skb is not at least 60 bytes we need to pad it so that
1909 * it is large enough to qualify as a valid Ethernet frame.
1910 *
1911 * Returns true if an error was encountered and skb was freed.
1912 **/
1913static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1914 union ixgbe_adv_rx_desc *rx_desc,
1915 struct sk_buff *skb)
1916{
f800326d 1917 struct net_device *netdev = rx_ring->netdev;
f800326d 1918
92470808
JF		 1919 /* XDP packets use error pointer so abort at this point */
1920 if (IS_ERR(skb))
1921 return true;
1922
f800326d
AD		 1923 /* verify that the packet does not have any known errors */
1924 if (unlikely(ixgbe_test_staterr(rx_desc,
1925 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1926 !(netdev->features & NETIF_F_RXALL))) {
1927 dev_kfree_skb_any(skb);
1928 return true;
1929 }
1930
19861ce2 1931 /* place header in linear portion of buffer */
6f429223 1932 if (!skb_headlen(skb))
cf3fe7ac 1933 ixgbe_pull_tail(rx_ring, skb);
f800326d 1934
57efd44c
AD		 1935#ifdef IXGBE_FCOE
1936 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1937 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1938 return false;
1939
1940#endif
a94d9e22
AD		 1941 /* if eth_skb_pad returns an error the skb was freed */
1942 if (eth_skb_pad(skb))
1943 return true;
f800326d
AD		 1944
1945 return false;
1946}
1947
f800326d
AD		 1948/**
1949 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1950 * @rx_ring: rx descriptor ring to store buffers on
1951 * @old_buff: donor buffer to have page reused
1952 *
0549ae20 1953 * Synchronizes page for reuse by the adapter
f800326d
AD		 1954 **/
1955static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1956 struct ixgbe_rx_buffer *old_buff)
1957{
1958 struct ixgbe_rx_buffer *new_buff;
1959 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1960
1961 new_buff = &rx_ring->rx_buffer_info[nta];
1962
1963 /* update, and store next to alloc */
1964 nta++;
1965 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1966
3fd21876
AD		 1967 /* Transfer page from old buffer to new buffer.
1968 * Move each member individually to avoid possible store
1969 * forwarding stalls and unnecessary copy of skb.
1970 */
1971 new_buff->dma = old_buff->dma;
1972 new_buff->page = old_buff->page;
1973 new_buff->page_offset = old_buff->page_offset;
1974 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
f800326d
AD		 1975}
1976
18cb652a
AD		 1977static inline bool ixgbe_page_is_reserved(struct page *page)
1978{
2f064f34 1979 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1980}
1981
3fd21876 1982static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer)
af43da0d 1983{
3fd21876
AD		 1984 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1985 struct page *page = rx_buffer->page;
1b56cf49 1986
af43da0d
AD		 1987 /* avoid re-using remote pages */
1988 if (unlikely(ixgbe_page_is_reserved(page)))
1989 return false;
1990
1991#if (PAGE_SIZE < 8192)
1992 /* if we are only owner of page we can reuse it */
3fd21876 1993 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
af43da0d 1994 return false;
af43da0d 1995#else
3fd21876
AD		 1996 /* The last offset is a bit aggressive in that we assume the
1997 * worst case of FCoE being enabled and using a 3K buffer.
1998 * However this should have minimal impact as the 1K extra is
1999 * still less than one buffer in size.
2000 */
2001#define IXGBE_LAST_OFFSET \
2002 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K)
2003 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET)
af43da0d
AD		 2004 return false;
2005#endif
2006
1b56cf49
AD		 2007 /* If we have drained the page fragment pool we need to update
2008 * the pagecnt_bias and page count so that we fully restock the
2009 * number of references the driver holds.
af43da0d 2010 */
3fd21876 2011 if (unlikely(!pagecnt_bias)) {
1b56cf49
AD		 2012 page_ref_add(page, USHRT_MAX);
2013 rx_buffer->pagecnt_bias = USHRT_MAX;
2014 }
af43da0d
AD		 2015
2016 return true;
2017}
2018
f800326d
AD		 2019/**
2020 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
2021 * @rx_ring: rx descriptor ring to transact packets on
2022 * @rx_buffer: buffer containing page to add
2023 * @rx_desc: descriptor containing length of buffer written by hardware
2024 * @skb: sk_buff to place the data into
2025 *
0549ae20
AD		 2026 * This function will add the data contained in rx_buffer->page to the skb.
2027 * This is done either through a direct copy if the data in the buffer is
2028 * less than the skb header size, otherwise it will just attach the page as
2029 * a frag to the skb.
2030 *
2031 * The function will then update the page offset if necessary and return
2032 * true if the buffer can be reused by the adapter.
f800326d 2033 **/
3fd21876 2034static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 2035 struct ixgbe_rx_buffer *rx_buffer,
3fd21876
AD		 2036 struct sk_buff *skb,
2037 unsigned int size)
f800326d 2038{
09816fbe 2039#if (PAGE_SIZE < 8192)
4f4542bf 2040 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
09816fbe 2041#else
2de6aa3a
AD		 2042 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
2043 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) :
2044 SKB_DATA_ALIGN(size);
09816fbe 2045#endif
3fd21876 2046 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
0549ae20 2047 rx_buffer->page_offset, size, truesize);
3fd21876
AD		 2048#if (PAGE_SIZE < 8192)
2049 rx_buffer->page_offset ^= truesize;
2050#else
2051 rx_buffer->page_offset += truesize;
2052#endif
f800326d
AD		 2053}
2054
3fd21876
AD		 2055static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring,
2056 union ixgbe_adv_rx_desc *rx_desc,
2057 struct sk_buff **skb,
2058 const unsigned int size)
18806c9e
AD		 2059{
2060 struct ixgbe_rx_buffer *rx_buffer;
18806c9e
AD		 2061
2062 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
3fd21876
AD		 2063 prefetchw(rx_buffer->page);
2064 *skb = rx_buffer->skb;
18806c9e 2065
3fd21876
AD		 2066 /* Delay unmapping of the first packet. It carries the header
2067 * information, HW may still access the header after the writeback.
2068 * Only unmap it when EOP is reached
2069 */
2070 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) {
2071 if (!*skb)
2072 goto skip_sync;
18806c9e 2073 } else {
3fd21876
AD		 2074 if (*skb)
2075 ixgbe_dma_sync_frag(rx_ring, *skb);
2076 }
18806c9e 2077
3fd21876
AD		 2078 /* we are reusing so sync this buffer for CPU use */
2079 dma_sync_single_range_for_cpu(rx_ring->dev,
2080 rx_buffer->dma,
2081 rx_buffer->page_offset,
2082 size,
2083 DMA_FROM_DEVICE);
2084skip_sync:
2085 rx_buffer->pagecnt_bias--;
18cb652a 2086
3fd21876
AD		 2087 return rx_buffer;
2088}
18806c9e 2089
3fd21876
AD		 2090static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring,
2091 struct ixgbe_rx_buffer *rx_buffer,
2092 struct sk_buff *skb)
2093{
2094 if (ixgbe_can_reuse_rx_page(rx_buffer)) {
18806c9e
AD		 2095 /* hand second half of page back to the ring */
2096 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
18806c9e 2097 } else {
92470808 2098 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) {
1b56cf49
AD		 2099 /* the page has been released from the ring */
2100 IXGBE_CB(skb)->page_released = true;
2101 } else {
2102 /* we are not reusing the buffer so unmap it */
2103 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2104 ixgbe_rx_pg_size(rx_ring),
2105 DMA_FROM_DEVICE,
2106 IXGBE_RX_DMA_ATTR);
2107 }
3fd21876 2108 __page_frag_cache_drain(rx_buffer->page,
1b56cf49 2109 rx_buffer->pagecnt_bias);
18806c9e
AD		 2110 }
2111
3fd21876 2112 /* clear contents of rx_buffer */
18806c9e 2113 rx_buffer->page = NULL;
3fd21876
AD		 2114 rx_buffer->skb = NULL;
2115}
2116
2117static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring,
2118 struct ixgbe_rx_buffer *rx_buffer,
92470808
JF		 2119 struct xdp_buff *xdp,
2120 union ixgbe_adv_rx_desc *rx_desc)
3fd21876 2121{
92470808 2122 unsigned int size = xdp->data_end - xdp->data;
3fd21876
AD		 2123#if (PAGE_SIZE < 8192)
2124 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2125#else
92470808
JF		 2126 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
2127 xdp->data_hard_start);
3fd21876
AD		 2128#endif
2129 struct sk_buff *skb;
2130
2131 /* prefetch first cache line of first page */
92470808 2132 prefetch(xdp->data);
3fd21876 2133#if L1_CACHE_BYTES < 128
92470808 2134 prefetch(xdp->data + L1_CACHE_BYTES);
3fd21876
AD		 2135#endif
2136
2137 /* allocate a skb to store the frags */
2138 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE);
2139 if (unlikely(!skb))
2140 return NULL;
2141
2142 if (size > IXGBE_RX_HDR_SIZE) {
2143 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2144 IXGBE_CB(skb)->dma = rx_buffer->dma;
2145
2146 skb_add_rx_frag(skb, 0, rx_buffer->page,
92470808 2147 xdp->data - page_address(rx_buffer->page),
3fd21876
AD		 2148 size, truesize);
2149#if (PAGE_SIZE < 8192)
2150 rx_buffer->page_offset ^= truesize;
2151#else
2152 rx_buffer->page_offset += truesize;
2153#endif
2154 } else {
92470808
JF		 2155 memcpy(__skb_put(skb, size),
2156 xdp->data, ALIGN(size, sizeof(long)));
3fd21876
AD		 2157 rx_buffer->pagecnt_bias++;
2158 }
18806c9e
AD		 2159
2160 return skb;
f800326d
AD		 2161}
2162
6f429223
AD		 2163static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring,
2164 struct ixgbe_rx_buffer *rx_buffer,
92470808
JF		 2165 struct xdp_buff *xdp,
2166 union ixgbe_adv_rx_desc *rx_desc)
6f429223 2167{
6f429223
AD		 2168#if (PAGE_SIZE < 8192)
2169 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2170#else
2171 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
92470808
JF		 2172 SKB_DATA_ALIGN(xdp->data_end -
2173 xdp->data_hard_start);
6f429223
AD		 2174#endif
2175 struct sk_buff *skb;
2176
2177 /* prefetch first cache line of first page */
92470808 2178 prefetch(xdp->data);
6f429223 2179#if L1_CACHE_BYTES < 128
92470808 2180 prefetch(xdp->data + L1_CACHE_BYTES);
6f429223
AD		 2181#endif
2182
92470808
JF		 2183 /* build an skb to around the page buffer */
2184 skb = build_skb(xdp->data_hard_start, truesize);
6f429223
AD		 2185 if (unlikely(!skb))
2186 return NULL;
2187
2188 /* update pointers within the skb to store the data */
92470808
JF		 2189 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2190 __skb_put(skb, xdp->data_end - xdp->data);
6f429223
AD		 2191
2192 /* record DMA address if this is the start of a chain of buffers */
2193 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2194 IXGBE_CB(skb)->dma = rx_buffer->dma;
2195
2196 /* update buffer offset */
2197#if (PAGE_SIZE < 8192)
2198 rx_buffer->page_offset ^= truesize;
2199#else
2200 rx_buffer->page_offset += truesize;
2201#endif
2202
2203 return skb;
2204}
2205
92470808
JF		 2206#define IXGBE_XDP_PASS 0
2207#define IXGBE_XDP_CONSUMED 1
33fdc82f 2208#define IXGBE_XDP_TX 2
92470808 2209
33fdc82f
JF		 2210static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
2211 struct xdp_buff *xdp);
2212
2213static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter,
2214 struct ixgbe_ring *rx_ring,
92470808
JF		 2215 struct xdp_buff *xdp)
2216{
64530739 2217 int err, result = IXGBE_XDP_PASS;
92470808
JF		 2218 struct bpf_prog *xdp_prog;
2219 u32 act;
2220
2221 rcu_read_lock();
2222 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2223
2224 if (!xdp_prog)
2225 goto xdp_out;
2226
2227 act = bpf_prog_run_xdp(xdp_prog, xdp);
2228 switch (act) {
2229 case XDP_PASS:
2230 break;
33fdc82f
JF		 2231 case XDP_TX:
2232 result = ixgbe_xmit_xdp_ring(adapter, xdp);
2233 break;
64530739 2234 case XDP_REDIRECT:
5acaee0a 2235 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
64530739
JF		 2236 if (!err)
2237 result = IXGBE_XDP_TX;
2238 else
2239 result = IXGBE_XDP_CONSUMED;
2240 break;
92470808
JF		 2241 default:
2242 bpf_warn_invalid_xdp_action(act);
93df9465 2243 /* fallthrough */
92470808
JF		 2244 case XDP_ABORTED:
2245 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2246 /* fallthrough -- handle aborts by dropping packet */
2247 case XDP_DROP:
2248 result = IXGBE_XDP_CONSUMED;
2249 break;
2250 }
2251xdp_out:
2252 rcu_read_unlock();
2253 return ERR_PTR(-result);
2254}
2255
33fdc82f
JF		 2256static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring,
2257 struct ixgbe_rx_buffer *rx_buffer,
2258 unsigned int size)
2259{
2260#if (PAGE_SIZE < 8192)
2261 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2262
2263 rx_buffer->page_offset ^= truesize;
2264#else
2265 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
2266 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) :
2267 SKB_DATA_ALIGN(size);
2268
2269 rx_buffer->page_offset += truesize;
2270#endif
2271}
2272
f800326d
AD		 2273/**
2274 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2275 * @q_vector: structure containing interrupt and ring information
2276 * @rx_ring: rx descriptor ring to transact packets on
2277 * @budget: Total limit on number of packets to process
2278 *
2279 * This function provides a "bounce buffer" approach to Rx interrupt
2280 * processing. The advantage to this is that on systems that have
2281 * expensive overhead for IOMMU access this provides a means of avoiding
2282 * it by maintaining the mapping of the page to the syste.
2283 *
5a85e737 2284 * Returns amount of work completed
f800326d 2285 **/
5a85e737 2286static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2287 struct ixgbe_ring *rx_ring,
f4de00ed 2288 const int budget)
9a799d71 2289{
d2f4fbe2 2290 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
f800326d 2291 struct ixgbe_adapter *adapter = q_vector->adapter;
33fdc82f 2292#ifdef IXGBE_FCOE
4ffdf91a
MR		 2293 int ddp_bytes;
2294 unsigned int mss = 0;
3d8fd385 2295#endif /* IXGBE_FCOE */
f800326d 2296 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
7379f97a 2297 bool xdp_xmit = false;
9a799d71 2298
fdabfc8a 2299 while (likely(total_rx_packets < budget)) {
f800326d 2300 union ixgbe_adv_rx_desc *rx_desc;
3fd21876 2301 struct ixgbe_rx_buffer *rx_buffer;
f800326d 2302 struct sk_buff *skb;
92470808 2303 struct xdp_buff xdp;
3fd21876 2304 unsigned int size;
f800326d
AD		 2305
2306 /* return some buffers to hardware, one at a time is too slow */
2307 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2308 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2309 cleaned_count = 0;
2310 }
2311
18806c9e 2312 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
3fd21876
AD		 2313 size = le16_to_cpu(rx_desc->wb.upper.length);
2314 if (!size)
f800326d 2315 break;
9a799d71 2316
124b74c1 2317 /* This memory barrier is needed to keep us from reading
f800326d 2318 * any other fields out of the rx_desc until we know the
124b74c1 2319 * descriptor has been written back
f800326d 2320 */
124b74c1 2321 dma_rmb();
9a799d71 2322
3fd21876
AD		 2323 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size);
2324
18806c9e 2325 /* retrieve a buffer from the ring */
92470808
JF		 2326 if (!skb) {
2327 xdp.data = page_address(rx_buffer->page) +
2328 rx_buffer->page_offset;
2329 xdp.data_hard_start = xdp.data -
2330 ixgbe_rx_offset(rx_ring);
2331 xdp.data_end = xdp.data + size;
2332
33fdc82f 2333 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp);
92470808
JF		 2334 }
2335
2336 if (IS_ERR(skb)) {
7379f97a
JF		 2337 if (PTR_ERR(skb) == -IXGBE_XDP_TX) {
2338 xdp_xmit = true;
33fdc82f 2339 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size);
7379f97a 2340 } else {
33fdc82f 2341 rx_buffer->pagecnt_bias++;
7379f97a 2342 }
92470808
JF		 2343 total_rx_packets++;
2344 total_rx_bytes += size;
92470808 2345 } else if (skb) {
3fd21876 2346 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size);
92470808 2347 } else if (ring_uses_build_skb(rx_ring)) {
6f429223 2348 skb = ixgbe_build_skb(rx_ring, rx_buffer,
92470808
JF		 2349 &xdp, rx_desc);
2350 } else {
3fd21876 2351 skb = ixgbe_construct_skb(rx_ring, rx_buffer,
92470808
JF		 2352 &xdp, rx_desc);
2353 }
f800326d 2354
18806c9e 2355 /* exit if we failed to retrieve a buffer */
3fd21876
AD		 2356 if (!skb) {
2357 rx_ring->rx_stats.alloc_rx_buff_failed++;
2358 rx_buffer->pagecnt_bias++;
18806c9e 2359 break;
3fd21876 2360 }
9a799d71 2361
3fd21876 2362 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb);
9a799d71 2363 cleaned_count++;
f8212f97 2364
f800326d
AD		 2365 /* place incomplete frames back on ring for completion */
2366 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2367 continue;
c267fc16 2368
f800326d
AD		 2369 /* verify the packet layout is correct */
2370 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2371 continue;
9a799d71 2372
d2f4fbe2
AV		 2373 /* probably a little skewed due to removing CRC */
2374 total_rx_bytes += skb->len;
d2f4fbe2 2375
8a0da21b
AD		 2376 /* populate checksum, timestamp, VLAN, and protocol */
2377 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2378
332d4a7d
YZ		 2379#ifdef IXGBE_FCOE
2380 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2381 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2382 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2383 /* include DDPed FCoE data */
2384 if (ddp_bytes > 0) {
2385 if (!mss) {
2386 mss = rx_ring->netdev->mtu -
2387 sizeof(struct fcoe_hdr) -
2388 sizeof(struct fc_frame_header) -
2389 sizeof(struct fcoe_crc_eof);
2390 if (mss > 512)
2391 mss &= ~511;
2392 }
2393 total_rx_bytes += ddp_bytes;
2394 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2395 mss);
2396 }
63d635b2
AD		 2397 if (!ddp_bytes) {
2398 dev_kfree_skb_any(skb);
f800326d 2399 continue;
63d635b2 2400 }
3d8fd385 2401 }
f800326d 2402
332d4a7d 2403#endif /* IXGBE_FCOE */
8a0da21b 2404 ixgbe_rx_skb(q_vector, skb);
9a799d71 2405
f800326d 2406 /* update budget accounting */
f4de00ed 2407 total_rx_packets++;
fdabfc8a 2408 }
9a799d71 2409
7379f97a
JF		 2410 if (xdp_xmit) {
2411 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
2412
2413 /* Force memory writes to complete before letting h/w
2414 * know there are new descriptors to fetch.
2415 */
2416 wmb();
2417 writel(ring->next_to_use, ring->tail);
11393cc9
JF		 2418
2419 xdp_do_flush_map();
7379f97a
JF		 2420 }
2421
c267fc16
AD		 2422 u64_stats_update_begin(&rx_ring->syncp);
2423 rx_ring->stats.packets += total_rx_packets;
2424 rx_ring->stats.bytes += total_rx_bytes;
2425 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2426 q_vector->rx.total_packets += total_rx_packets;
2427 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2428
5a85e737 2429 return total_rx_packets;
9a799d71
AK		 2430}
2431
9a799d71
AK		 2432/**
2433 * ixgbe_configure_msix - Configure MSI-X hardware
2434 * @adapter: board private structure
2435 *
2436 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2437 * interrupts.
2438 **/
2439static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2440{
021230d4 2441 struct ixgbe_q_vector *q_vector;
49c7ffbe 2442 int v_idx;
021230d4 2443 u32 mask;
9a799d71 2444
8e34d1aa
AD		 2445 /* Populate MSIX to EITR Select */
2446 if (adapter->num_vfs > 32) {
b4f47a48 2447 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
8e34d1aa
AD		 2448 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2449 }
2450
4df10466
JB		 2451 /*
2452 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2453 * corresponding register.
2454 */
49c7ffbe 2455 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2456 struct ixgbe_ring *ring;
7a921c93 2457 q_vector = adapter->q_vector[v_idx];
021230d4 2458
a557928e 2459 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2460 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2461
a557928e 2462 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2463 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2464
fe49f04a 2465 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2466 }
2467
bd508178
AD		 2468 switch (adapter->hw.mac.type) {
2469 case ixgbe_mac_82598EB:
e8e26350 2470 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2471 v_idx);
bd508178
AD		 2472 break;
2473 case ixgbe_mac_82599EB:
b93a2226 2474 case ixgbe_mac_X540:
9a75a1ac
DS		 2475 case ixgbe_mac_X550:
2476 case ixgbe_mac_X550EM_x:
49425dfc 2477 case ixgbe_mac_x550em_a:
e8e26350 2478 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2479 break;
bd508178
AD		 2480 default:
2481 break;
2482 }
021230d4
AV		 2483 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2484
41fb9248 2485 /* set up to autoclear timer, and the vectors */
021230d4 2486 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2487 mask &= ~(IXGBE_EIMS_OTHER |
2488 IXGBE_EIMS_MAILBOX |
2489 IXGBE_EIMS_LSC);
2490
021230d4 2491 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2492}
2493
f494e8fa
AV		 2494enum latency_range {
2495 lowest_latency = 0,
2496 low_latency = 1,
2497 bulk_latency = 2,
2498 latency_invalid = 255
2499};
2500
2501/**
2502 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2503 * @q_vector: structure containing interrupt and ring information
2504 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2505 *
2506 * Stores a new ITR value based on packets and byte
2507 * counts during the last interrupt. The advantage of per interrupt
2508 * computation is faster updates and more accurate ITR for the current
2509 * traffic pattern. Constants in this function were computed
2510 * based on theoretical maximum wire speed and thresholds were set based
2511 * on testing data as well as attempting to minimize response time
2512 * while increasing bulk throughput.
2513 * this functionality is controlled by the InterruptThrottleRate module
2514 * parameter (see ixgbe_param.c)
2515 **/
bd198058
AD		 2516static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2517 struct ixgbe_ring_container *ring_container)
f494e8fa 2518{
bd198058
AD		 2519 int bytes = ring_container->total_bytes;
2520 int packets = ring_container->total_packets;
2521 u32 timepassed_us;
621bd70e 2522 u64 bytes_perint;
bd198058 2523 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2524
2525 if (packets == 0)
bd198058 2526 return;
f494e8fa
AV		 2527
2528 /* simple throttlerate management
621bd70e
AD		 2529 * 0-10MB/s lowest (100000 ints/s)
2530 * 10-20MB/s low (20000 ints/s)
8ac34f10 2531 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2532 */
2533 /* what was last interrupt timeslice? */
d5bf4f67 2534 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2535 if (timepassed_us == 0)
2536 return;
2537
f494e8fa
AV		 2538 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2539
2540 switch (itr_setting) {
2541 case lowest_latency:
621bd70e 2542 if (bytes_perint > 10)
bd198058 2543 itr_setting = low_latency;
f494e8fa
AV		 2544 break;
2545 case low_latency:
621bd70e 2546 if (bytes_perint > 20)
bd198058 2547 itr_setting = bulk_latency;
621bd70e 2548 else if (bytes_perint <= 10)
bd198058 2549 itr_setting = lowest_latency;
f494e8fa
AV		 2550 break;
2551 case bulk_latency:
621bd70e 2552 if (bytes_perint <= 20)
bd198058 2553 itr_setting = low_latency;
f494e8fa
AV		 2554 break;
2555 }
2556
bd198058
AD		 2557 /* clear work counters since we have the values we need */
2558 ring_container->total_bytes = 0;
2559 ring_container->total_packets = 0;
2560
2561 /* write updated itr to ring container */
2562 ring_container->itr = itr_setting;
f494e8fa
AV		 2563}
2564
509ee935
JB		 2565/**
2566 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2567 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2568 *
2569 * This function is made to be called by ethtool and by the driver
2570 * when it needs to update EITR registers at runtime. Hardware
2571 * specific quirks/differences are taken care of here.
2572 */
fe49f04a 2573void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2574{
fe49f04a 2575 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2576 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2577 int v_idx = q_vector->v_idx;
5d967eb7 2578 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2579
bd508178
AD		 2580 switch (adapter->hw.mac.type) {
2581 case ixgbe_mac_82598EB:
509ee935
JB		 2582 /* must write high and low 16 bits to reset counter */
2583 itr_reg |= (itr_reg << 16);
bd508178
AD		 2584 break;
2585 case ixgbe_mac_82599EB:
b93a2226 2586 case ixgbe_mac_X540:
9a75a1ac
DS		 2587 case ixgbe_mac_X550:
2588 case ixgbe_mac_X550EM_x:
49425dfc 2589 case ixgbe_mac_x550em_a:
509ee935
JB		 2590 /*
2591 * set the WDIS bit to not clear the timer bits and cause an
2592 * immediate assertion of the interrupt
2593 */
2594 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2595 break;
2596 default:
2597 break;
509ee935
JB		 2598 }
2599 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2600}
2601
bd198058 2602static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2603{
d5bf4f67 2604 u32 new_itr = q_vector->itr;
bd198058 2605 u8 current_itr;
f494e8fa 2606
bd198058
AD		 2607 ixgbe_update_itr(q_vector, &q_vector->tx);
2608 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2609
08c8833b 2610 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2611
2612 switch (current_itr) {
2613 /* counts and packets in update_itr are dependent on these numbers */
2614 case lowest_latency:
d5bf4f67 2615 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2616 break;
2617 case low_latency:
d5bf4f67 2618 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2619 break;
2620 case bulk_latency:
8ac34f10 2621 new_itr = IXGBE_12K_ITR;
f494e8fa 2622 break;
bd198058
AD		 2623 default:
2624 break;
f494e8fa
AV		 2625 }
2626
d5bf4f67 2627 if (new_itr != q_vector->itr) {
fe49f04a 2628 /* do an exponential smoothing */
d5bf4f67
ET		 2629 new_itr = (10 * new_itr * q_vector->itr) /
2630 ((9 * new_itr) + q_vector->itr);
509ee935 2631
bd198058 2632 /* save the algorithm value here */
5d967eb7 2633 q_vector->itr = new_itr;
fe49f04a
AD		 2634
2635 ixgbe_write_eitr(q_vector);
f494e8fa 2636 }
f494e8fa
AV		 2637}
2638
119fc60a 2639/**
de88eeeb 2640 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2641 * @adapter: pointer to adapter
119fc60a 2642 **/
f0f9778d 2643static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2644{
119fc60a
MC		 2645 struct ixgbe_hw *hw = &adapter->hw;
2646 u32 eicr = adapter->interrupt_event;
b3eb4e18 2647 s32 rc;
119fc60a 2648
f0f9778d 2649 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2650 return;
2651
22cb4fff 2652 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
f0f9778d
AD		 2653 return;
2654
2655 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2656
7ca647bd 2657 switch (hw->device_id) {
f0f9778d
AD		 2658 case IXGBE_DEV_ID_82599_T3_LOM:
2659 /*
2660 * Since the warning interrupt is for both ports
2661 * we don't have to check if:
2662 * - This interrupt wasn't for our port.
2663 * - We may have missed the interrupt so always have to
2664 * check if we got a LSC
2665 */
9a900eca 2666 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2667 !(eicr & IXGBE_EICR_LSC))
2668 return;
2669
2670 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2671 u32 speed;
f0f9778d 2672 bool link_up = false;
7ca647bd 2673
3d292265 2674 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2675
f0f9778d
AD		 2676 if (link_up)
2677 return;
2678 }
2679
2680 /* Check if this is not due to overtemp */
2681 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2682 return;
2683
2684 break;
b3eb4e18
MR		 2685 case IXGBE_DEV_ID_X550EM_A_1G_T:
2686 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2687 rc = hw->phy.ops.check_overtemp(hw);
2688 if (rc != IXGBE_ERR_OVERTEMP)
2689 return;
2690 break;
7ca647bd 2691 default:
597f22d6
DS		 2692 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2693 return;
9a900eca 2694 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2695 return;
7ca647bd 2696 break;
119fc60a 2697 }
f44e751b 2698 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2699
2700 adapter->interrupt_event = 0;
119fc60a
MC		 2701}
2702
0befdb3e
JB		 2703static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2704{
2705 struct ixgbe_hw *hw = &adapter->hw;
2706
2707 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2708 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2709 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2710 /* write to clear the interrupt */
9a900eca 2711 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2712 }
2713}
cf8280ee 2714
4f51bf70
JK		 2715static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2716{
9a900eca
DS		 2717 struct ixgbe_hw *hw = &adapter->hw;
2718
4f51bf70
JK		 2719 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2720 return;
2721
2722 switch (adapter->hw.mac.type) {
2723 case ixgbe_mac_82599EB:
2724 /*
2725 * Need to check link state so complete overtemp check
2726 * on service task
2727 */
9a900eca
DS		 2728 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2729 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2730 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2731 adapter->interrupt_event = eicr;
2732 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2733 ixgbe_service_event_schedule(adapter);
2734 return;
2735 }
2736 return;
b3eb4e18
MR		 2737 case ixgbe_mac_x550em_a:
2738 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) {
2739 adapter->interrupt_event = eicr;
2740 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2741 ixgbe_service_event_schedule(adapter);
2742 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
2743 IXGBE_EICR_GPI_SDP0_X550EM_a);
2744 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR,
2745 IXGBE_EICR_GPI_SDP0_X550EM_a);
2746 }
2747 return;
2748 case ixgbe_mac_X550:
4f51bf70
JK		 2749 case ixgbe_mac_X540:
2750 if (!(eicr & IXGBE_EICR_TS))
2751 return;
2752 break;
2753 default:
2754 return;
2755 }
2756
f44e751b 2757 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2758}
2759
45788d2a
DS		 2760static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2761{
2762 switch (hw->mac.type) {
2763 case ixgbe_mac_82598EB:
2764 if (hw->phy.type == ixgbe_phy_nl)
2765 return true;
2766 return false;
2767 case ixgbe_mac_82599EB:
2768 case ixgbe_mac_X550EM_x:
49425dfc 2769 case ixgbe_mac_x550em_a:
45788d2a
DS		 2770 switch (hw->mac.ops.get_media_type(hw)) {
2771 case ixgbe_media_type_fiber:
2772 case ixgbe_media_type_fiber_qsfp:
2773 return true;
2774 default:
2775 return false;
2776 }
2777 default:
2778 return false;
2779 }
2780}
2781
e8e26350
PW		 2782static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2783{
2784 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2785 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2786
4ccc650c
DS		 2787 if (!ixgbe_is_sfp(hw))
2788 return;
2789
2790 /* Later MAC's use different SDP */
2791 if (hw->mac.type >= ixgbe_mac_X540)
2792 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2793
2794 if (eicr & eicr_mask) {
73c4b7cd 2795 /* Clear the interrupt */
4ccc650c 2796 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2797 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2798 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2799 adapter->sfp_poll_time = 0;
7086400d
AD		 2800 ixgbe_service_event_schedule(adapter);
2801 }
73c4b7cd
AD		 2802 }
2803
4ccc650c
DS		 2804 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2805 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2806 /* Clear the interrupt */
9a900eca 2807 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2808 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2809 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2810 ixgbe_service_event_schedule(adapter);
2811 }
e8e26350
PW		 2812 }
2813}
2814
cf8280ee
JB		 2815static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2816{
2817 struct ixgbe_hw *hw = &adapter->hw;
2818
2819 adapter->lsc_int++;
2820 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2821 adapter->link_check_timeout = jiffies;
2822 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2823 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2824 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2825 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2826 }
2827}
2828
fe49f04a
AD		 2829static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2830 u64 qmask)
2831{
2832 u32 mask;
bd508178 2833 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2834
bd508178
AD		 2835 switch (hw->mac.type) {
2836 case ixgbe_mac_82598EB:
fe49f04a 2837 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2838 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2839 break;
2840 case ixgbe_mac_82599EB:
b93a2226 2841 case ixgbe_mac_X540:
9a75a1ac
DS		 2842 case ixgbe_mac_X550:
2843 case ixgbe_mac_X550EM_x:
49425dfc 2844 case ixgbe_mac_x550em_a:
fe49f04a 2845 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2846 if (mask)
2847 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2848 mask = (qmask >> 32);
bd508178
AD		 2849 if (mask)
2850 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2851 break;
2852 default:
2853 break;
fe49f04a
AD		 2854 }
2855 /* skip the flush */
2856}
2857
2858static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2859 u64 qmask)
fe49f04a
AD		 2860{
2861 u32 mask;
bd508178 2862 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2863
bd508178
AD		 2864 switch (hw->mac.type) {
2865 case ixgbe_mac_82598EB:
fe49f04a 2866 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2867 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2868 break;
2869 case ixgbe_mac_82599EB:
b93a2226 2870 case ixgbe_mac_X540:
9a75a1ac
DS		 2871 case ixgbe_mac_X550:
2872 case ixgbe_mac_X550EM_x:
49425dfc 2873 case ixgbe_mac_x550em_a:
fe49f04a 2874 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2875 if (mask)
2876 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2877 mask = (qmask >> 32);
bd508178
AD		 2878 if (mask)
2879 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2880 break;
2881 default:
2882 break;
fe49f04a
AD		 2883 }
2884 /* skip the flush */
2885}
2886
021230d4 2887/**
2c4af694
AD		 2888 * ixgbe_irq_enable - Enable default interrupt generation settings
2889 * @adapter: board private structure
021230d4 2890 **/
2c4af694
AD		 2891static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2892 bool flush)
9a799d71 2893{
9a900eca 2894 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2895 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2896
2c4af694
AD		 2897 /* don't reenable LSC while waiting for link */
2898 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2899 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2900
2c4af694 2901 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2902 switch (adapter->hw.mac.type) {
2903 case ixgbe_mac_82599EB:
9a900eca 2904 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2905 break;
2906 case ixgbe_mac_X540:
9a75a1ac
DS		 2907 case ixgbe_mac_X550:
2908 case ixgbe_mac_X550EM_x:
49425dfc 2909 case ixgbe_mac_x550em_a:
4f51bf70
JK		 2910 mask |= IXGBE_EIMS_TS;
2911 break;
2912 default:
2913 break;
2914 }
2c4af694 2915 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2916 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2917 switch (adapter->hw.mac.type) {
2918 case ixgbe_mac_82599EB:
9a900eca
DS		 2919 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2920 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2921 /* fall through */
858bc081 2922 case ixgbe_mac_X540:
9a75a1ac
DS		 2923 case ixgbe_mac_X550:
2924 case ixgbe_mac_X550EM_x:
49425dfc
MR		 2925 case ixgbe_mac_x550em_a:
2926 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
2d40cd17 2927 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
49425dfc 2928 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
cbd45ec7 2929 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2930 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2931 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2932 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2933 mask |= IXGBE_EIMS_MAILBOX;
2934 break;
2935 default:
2936 break;
9a799d71 2937 }
db0677fa 2938
2c4af694
AD		 2939 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2940 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2941 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2942
2c4af694
AD		 2943 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2944 if (queues)
2945 ixgbe_irq_enable_queues(adapter, ~0);
2946 if (flush)
2947 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2948}
2949
2c4af694 2950static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2951{
a65151ba 2952 struct ixgbe_adapter *adapter = data;
9a799d71 2953 struct ixgbe_hw *hw = &adapter->hw;
54037505 2954 u32 eicr;
91281fd3 2955
54037505
DS		 2956 /*
2957 * Workaround for Silicon errata. Use clear-by-write instead
2958 * of clear-by-read. Reading with EICS will return the
2959 * interrupt causes without clearing, which later be done
2960 * with the write to EICR.
2961 */
2962 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2963
2964 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2965 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2966 * the bits are high when ixgbe_msix_other is called. There is a race
2967 * condition otherwise which results in possible performance loss
2968 * especially if the ixgbe_msix_other interrupt is triggering
2969 * consistently (as it would when PPS is turned on for the X540 device)
2970 */
2971 eicr &= 0xFFFF0000;
2972
54037505 2973 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2974
cf8280ee
JB		 2975 if (eicr & IXGBE_EICR_LSC)
2976 ixgbe_check_lsc(adapter);
f0848276 2977
1cdd1ec8
GR		 2978 if (eicr & IXGBE_EICR_MAILBOX)
2979 ixgbe_msg_task(adapter);
efe3d3c8 2980
bd508178
AD		 2981 switch (hw->mac.type) {
2982 case ixgbe_mac_82599EB:
b93a2226 2983 case ixgbe_mac_X540:
9a75a1ac
DS		 2984 case ixgbe_mac_X550:
2985 case ixgbe_mac_X550EM_x:
49425dfc 2986 case ixgbe_mac_x550em_a:
597f22d6
DS		 2987 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2988 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2989 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2990 ixgbe_service_event_schedule(adapter);
2991 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2992 IXGBE_EICR_GPI_SDP0_X540);
2993 }
d773ce2d
DS		 2994 if (eicr & IXGBE_EICR_ECC) {
2995 e_info(link, "Received ECC Err, initiating reset\n");
57ca2a4f 2996 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
d773ce2d
DS		 2997 ixgbe_service_event_schedule(adapter);
2998 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2999 }
c4cf55e5
PWJ		 3000 /* Handle Flow Director Full threshold interrupt */
3001 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 3002 int reinit_count = 0;
c4cf55e5 3003 int i;
c4cf55e5 3004 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 3005 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 3006 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 3007 &ring->state))
3008 reinit_count++;
3009 }
3010 if (reinit_count) {
3011 /* no more flow director interrupts until after init */
3012 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 3013 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
3014 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 3015 }
3016 }
f0f9778d 3017 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 3018 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 3019 break;
3020 default:
3021 break;
c4cf55e5 3022 }
f0848276 3023
bd508178 3024 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 3025
db0677fa 3026 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 3027 ixgbe_ptp_check_pps_event(adapter);
efe3d3c8 3028
7086400d 3029 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 3030 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 3031 ixgbe_irq_enable(adapter, false, false);
f0848276 3032
9a799d71 3033 return IRQ_HANDLED;
f0848276 3034}
91281fd3 3035
4ff7fb12 3036static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 3037{
021230d4 3038 struct ixgbe_q_vector *q_vector = data;
91281fd3 3039
9b471446 3040 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 3041
4ff7fb12 3042 if (q_vector->rx.ring || q_vector->tx.ring)
ef2662b2 3043 napi_schedule_irqoff(&q_vector->napi);
91281fd3 3044
9a799d71 3045 return IRQ_HANDLED;
91281fd3
AD		 3046}
3047
eb01b975
AD		 3048/**
3049 * ixgbe_poll - NAPI Rx polling callback
3050 * @napi: structure for representing this polling device
3051 * @budget: how many packets driver is allowed to clean
3052 *
3053 * This function is used for legacy and MSI, NAPI mode
3054 **/
8af3c33f 3055int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 3056{
3057 struct ixgbe_q_vector *q_vector =
3058 container_of(napi, struct ixgbe_q_vector, napi);
3059 struct ixgbe_adapter *adapter = q_vector->adapter;
3060 struct ixgbe_ring *ring;
32b3e08f 3061 int per_ring_budget, work_done = 0;
eb01b975
AD		 3062 bool clean_complete = true;
3063
3064#ifdef CONFIG_IXGBE_DCA
3065 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3066 ixgbe_update_dca(q_vector);
3067#endif
3068
8220bbc1
AD		 3069 ixgbe_for_each_ring(ring, q_vector->tx) {
3070 if (!ixgbe_clean_tx_irq(q_vector, ring, budget))
3071 clean_complete = false;
3072 }
eb01b975 3073
3ffc1af5
ED		 3074 /* Exit if we are called by netpoll */
3075 if (budget <= 0)
5a85e737
ET		 3076 return budget;
3077
eb01b975
AD		 3078 /* attempt to distribute budget to each queue fairly, but don't allow
3079 * the budget to go below 1 because we'll exit polling */
3080 if (q_vector->rx.count > 1)
3081 per_ring_budget = max(budget/q_vector->rx.count, 1);
3082 else
3083 per_ring_budget = budget;
3084
32b3e08f
JB		 3085 ixgbe_for_each_ring(ring, q_vector->rx) {
3086 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
3087 per_ring_budget);
3088
3089 work_done += cleaned;
8220bbc1
AD		 3090 if (cleaned >= per_ring_budget)
3091 clean_complete = false;
32b3e08f 3092 }
eb01b975
AD		 3093
3094 /* If all work not completed, return budget and keep polling */
3095 if (!clean_complete)
3096 return budget;
3097
3098 /* all work done, exit the polling mode */
32b3e08f 3099 napi_complete_done(napi, work_done);
eb01b975
AD		 3100 if (adapter->rx_itr_setting & 1)
3101 ixgbe_set_itr(q_vector);
3102 if (!test_bit(__IXGBE_DOWN, &adapter->state))
b4f47a48 3103 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx));
eb01b975 3104
4b732cd4 3105 return min(work_done, budget - 1);
eb01b975
AD		 3106}
3107
021230d4
AV		 3108/**
3109 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
3110 * @adapter: board private structure
3111 *
3112 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
3113 * interrupts from the kernel.
3114 **/
3115static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
3116{
3117 struct net_device *netdev = adapter->netdev;
e61e4c8b 3118 unsigned int ri = 0, ti = 0;
207867f5 3119 int vector, err;
021230d4 3120
49c7ffbe 3121 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 3122 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 3123 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 3124
4ff7fb12 3125 if (q_vector->tx.ring && q_vector->rx.ring) {
e61e4c8b
TN		 3126 snprintf(q_vector->name, sizeof(q_vector->name),
3127 "%s-TxRx-%u", netdev->name, ri++);
4ff7fb12
AD		 3128 ti++;
3129 } else if (q_vector->rx.ring) {
e61e4c8b
TN		 3130 snprintf(q_vector->name, sizeof(q_vector->name),
3131 "%s-rx-%u", netdev->name, ri++);
4ff7fb12 3132 } else if (q_vector->tx.ring) {
e61e4c8b
TN		 3133 snprintf(q_vector->name, sizeof(q_vector->name),
3134 "%s-tx-%u", netdev->name, ti++);
d0759ebb
AD		 3135 } else {
3136 /* skip this unused q_vector */
3137 continue;
32aa77a4 3138 }
207867f5
AD		 3139 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
3140 q_vector->name, q_vector);
9a799d71 3141 if (err) {
396e799c 3142 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 3143 "Error: %d\n", err);
021230d4 3144 goto free_queue_irqs;
9a799d71 3145 }
207867f5
AD		 3146 /* If Flow Director is enabled, set interrupt affinity */
3147 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3148 /* assign the mask for this irq */
3149 irq_set_affinity_hint(entry->vector,
de88eeeb 3150 &q_vector->affinity_mask);
207867f5 3151 }
9a799d71
AK		 3152 }
3153
021230d4 3154 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 3155 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 3156 if (err) {
de88eeeb 3157 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 3158 goto free_queue_irqs;
9a799d71
AK		 3159 }
3160
9a799d71
AK		 3161 return 0;
3162
021230d4 3163free_queue_irqs:
207867f5
AD		 3164 while (vector) {
3165 vector--;
3166 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
3167 NULL);
3168 free_irq(adapter->msix_entries[vector].vector,
3169 adapter->q_vector[vector]);
3170 }
021230d4
AV		 3171 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3172 pci_disable_msix(adapter->pdev);
9a799d71
AK		 3173 kfree(adapter->msix_entries);
3174 adapter->msix_entries = NULL;
9a799d71
AK		 3175 return err;
3176}
3177
3178/**
021230d4 3179 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 3180 * @irq: interrupt number
3181 * @data: pointer to a network interface device structure
9a799d71
AK		 3182 **/
3183static irqreturn_t ixgbe_intr(int irq, void *data)
3184{
a65151ba 3185 struct ixgbe_adapter *adapter = data;
9a799d71 3186 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 3187 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 3188 u32 eicr;
3189
54037505 3190 /*
24ddd967 3191 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 3192 * before the read of EICR.
3193 */
3194 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
3195
021230d4 3196 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 3197 * therefore no explicit interrupt disable is necessary */
021230d4 3198 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 3199 if (!eicr) {
6af3b9eb
ET		 3200 /*
3201 * shared interrupt alert!
f47cf66e 3202 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 3203 * have disabled interrupts due to EIAM
3204 * finish the workaround of silicon errata on 82598. Unmask
3205 * the interrupt that we masked before the EICR read.
3206 */
3207 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3208 ixgbe_irq_enable(adapter, true, true);
9a799d71 3209 return IRQ_NONE; /* Not our interrupt */
f47cf66e 3210 }
9a799d71 3211
cf8280ee
JB		 3212 if (eicr & IXGBE_EICR_LSC)
3213 ixgbe_check_lsc(adapter);
021230d4 3214
bd508178
AD		 3215 switch (hw->mac.type) {
3216 case ixgbe_mac_82599EB:
e8e26350 3217 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 3218 /* Fall through */
3219 case ixgbe_mac_X540:
9a75a1ac
DS		 3220 case ixgbe_mac_X550:
3221 case ixgbe_mac_X550EM_x:
49425dfc 3222 case ixgbe_mac_x550em_a:
d773ce2d
DS		 3223 if (eicr & IXGBE_EICR_ECC) {
3224 e_info(link, "Received ECC Err, initiating reset\n");
57ca2a4f 3225 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
d773ce2d
DS		 3226 ixgbe_service_event_schedule(adapter);
3227 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3228 }
4f51bf70 3229 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 3230 break;
3231 default:
3232 break;
3233 }
e8e26350 3234
0befdb3e 3235 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 3236 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 3237 ixgbe_ptp_check_pps_event(adapter);
0befdb3e 3238
b9f6ed2b 3239 /* would disable interrupts here but EIAM disabled it */
ef2662b2 3240 napi_schedule_irqoff(&q_vector->napi);
9a799d71 3241
6af3b9eb
ET		 3242 /*
3243 * re-enable link(maybe) and non-queue interrupts, no flush.
3244 * ixgbe_poll will re-enable the queue interrupts
3245 */
6af3b9eb
ET		 3246 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3247 ixgbe_irq_enable(adapter, false, false);
3248
9a799d71
AK		 3249 return IRQ_HANDLED;
3250}
3251
3252/**
3253 * ixgbe_request_irq - initialize interrupts
3254 * @adapter: board private structure
3255 *
3256 * Attempts to configure interrupts using the best available
3257 * capabilities of the hardware and kernel.
3258 **/
021230d4 3259static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 3260{
3261 struct net_device *netdev = adapter->netdev;
021230d4 3262 int err;
9a799d71 3263
4cc6df29 3264 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 3265 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 3266 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 3267 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 3268 netdev->name, adapter);
4cc6df29 3269 else
a0607fd3 3270 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 3271 netdev->name, adapter);
9a799d71 3272
de88eeeb 3273 if (err)
396e799c 3274 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 3275
9a799d71
AK		 3276 return err;
3277}
3278
3279static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3280{
49c7ffbe 3281 int vector;
9a799d71 3282
49c7ffbe
AD		 3283 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3284 free_irq(adapter->pdev->irq, adapter);
3285 return;
3286 }
4cc6df29 3287
1fa71252
MR		 3288 if (!adapter->msix_entries)
3289 return;
3290
49c7ffbe
AD		 3291 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3292 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3293 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3294
49c7ffbe
AD		 3295 /* free only the irqs that were actually requested */
3296 if (!q_vector->rx.ring && !q_vector->tx.ring)
3297 continue;
207867f5 3298
49c7ffbe
AD		 3299 /* clear the affinity_mask in the IRQ descriptor */
3300 irq_set_affinity_hint(entry->vector, NULL);
3301
3302 free_irq(entry->vector, q_vector);
9a799d71 3303 }
49c7ffbe 3304
90c6f877 3305 free_irq(adapter->msix_entries[vector].vector, adapter);
9a799d71
AK		 3306}
3307
22d5a71b
JB		 3308/**
3309 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3310 * @adapter: board private structure
3311 **/
3312static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3313{
bd508178
AD		 3314 switch (adapter->hw.mac.type) {
3315 case ixgbe_mac_82598EB:
835462fc 3316 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3317 break;
3318 case ixgbe_mac_82599EB:
b93a2226 3319 case ixgbe_mac_X540:
9a75a1ac
DS		 3320 case ixgbe_mac_X550:
3321 case ixgbe_mac_X550EM_x:
49425dfc 3322 case ixgbe_mac_x550em_a:
835462fc
NS		 3323 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3324 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3325 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3326 break;
3327 default:
3328 break;
22d5a71b
JB		 3329 }
3330 IXGBE_WRITE_FLUSH(&adapter->hw);
3331 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3332 int vector;
3333
3334 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3335 synchronize_irq(adapter->msix_entries[vector].vector);
3336
3337 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3338 } else {
3339 synchronize_irq(adapter->pdev->irq);
3340 }
3341}
3342
9a799d71
AK		 3343/**
3344 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3345 *
3346 **/
3347static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3348{
d5bf4f67 3349 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3350
d5bf4f67 3351 ixgbe_write_eitr(q_vector);
9a799d71 3352
e8e26350
PW		 3353 ixgbe_set_ivar(adapter, 0, 0, 0);
3354 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3355
396e799c 3356 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3357}
3358
43e69bf0
AD		 3359/**
3360 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3361 * @adapter: board private structure
3362 * @ring: structure containing ring specific data
3363 *
3364 * Configure the Tx descriptor ring after a reset.
3365 **/
84418e3b
AD		 3366void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3367 struct ixgbe_ring *ring)
43e69bf0
AD		 3368{
3369 struct ixgbe_hw *hw = &adapter->hw;
3370 u64 tdba = ring->dma;
2f1860b8 3371 int wait_loop = 10;
b88c6de2 3372 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3373 u8 reg_idx = ring->reg_idx;
43e69bf0 3374
2f1860b8 3375 /* disable queue to avoid issues while updating state */
b88c6de2 3376 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3377 IXGBE_WRITE_FLUSH(hw);
3378
43e69bf0 3379 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3380 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3381 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3382 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3383 ring->count * sizeof(union ixgbe_adv_tx_desc));
3384 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3385 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3386 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3387
b88c6de2
AD		 3388 /*
3389 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3390 * higher than 1 when:
3391 * - ITR is 0 as it could cause false TX hangs
3392 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3393 *
3394 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3395 * to or less than the number of on chip descriptors, which is
3396 * currently 40.
3397 */
67da097e 3398 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b4f47a48 3399 txdctl |= 1u << 16; /* WTHRESH = 1 */
b88c6de2 3400 else
b4f47a48 3401 txdctl |= 8u << 16; /* WTHRESH = 8 */
b88c6de2 3402
e954b374
AD		 3403 /*
3404 * Setting PTHRESH to 32 both improves performance
3405 * and avoids a TX hang with DFP enabled
3406 */
b4f47a48 3407 txdctl |= (1u << 8) | /* HTHRESH = 1 */
b88c6de2 3408 32; /* PTHRESH = 32 */
2f1860b8
AD		 3409
3410 /* reinitialize flowdirector state */
39cb681b 3411 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3412 ring->atr_sample_rate = adapter->atr_sample_rate;
3413 ring->atr_count = 0;
3414 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3415 } else {
3416 ring->atr_sample_rate = 0;
3417 }
2f1860b8 3418
fd786b7b
AD		 3419 /* initialize XPS */
3420 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3421 struct ixgbe_q_vector *q_vector = ring->q_vector;
3422
3423 if (q_vector)
2a47fa45 3424 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3425 &q_vector->affinity_mask,
3426 ring->queue_index);
3427 }
3428
c84d324c
JF		 3429 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3430
ffed21bc
AD		 3431 /* reinitialize tx_buffer_info */
3432 memset(ring->tx_buffer_info, 0,
3433 sizeof(struct ixgbe_tx_buffer) * ring->count);
3434
2f1860b8 3435 /* enable queue */
2f1860b8
AD		 3436 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3437
3438 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3439 if (hw->mac.type == ixgbe_mac_82598EB &&
3440 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3441 return;
3442
3443 /* poll to verify queue is enabled */
3444 do {
032b4325 3445 usleep_range(1000, 2000);
2f1860b8
AD		 3446 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3447 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3448 if (!wait_loop)
a55defd8 3449 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3450}
3451
120ff942
AD		 3452static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3453{
3454 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3455 u32 rttdcs, mtqc;
8b1c0b24 3456 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3457
3458 if (hw->mac.type == ixgbe_mac_82598EB)
3459 return;
3460
3461 /* disable the arbiter while setting MTQC */
3462 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3463 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3464 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3465
3466 /* set transmit pool layout */
671c0adb
AD		 3467 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3468 mtqc = IXGBE_MTQC_VT_ENA;
3469 if (tcs > 4)
3470 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3471 else if (tcs > 1)
3472 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
e24fcf28
AD		 3473 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3474 IXGBE_82599_VMDQ_4Q_MASK)
671c0adb
AD		 3475 mtqc |= IXGBE_MTQC_32VF;
3476 else
3477 mtqc |= IXGBE_MTQC_64VF;
3478 } else {
3479 if (tcs > 4)
3480 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3481 else if (tcs > 1)
3482 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3483 else
671c0adb
AD		 3484 mtqc = IXGBE_MTQC_64Q_1PB;
3485 }
120ff942 3486
671c0adb 3487 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3488
671c0adb
AD		 3489 /* Enable Security TX Buffer IFG for multiple pb */
3490 if (tcs) {
3491 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3492 sectx |= IXGBE_SECTX_DCB;
3493 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3494 }
3495
3496 /* re-enable the arbiter */
3497 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3498 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3499}
3500
9a799d71 3501/**
3a581073 3502 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3503 * @adapter: board private structure
3504 *
3505 * Configure the Tx unit of the MAC after a reset.
3506 **/
3507static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3508{
2f1860b8
AD		 3509 struct ixgbe_hw *hw = &adapter->hw;
3510 u32 dmatxctl;
43e69bf0 3511 u32 i;
9a799d71 3512
2f1860b8
AD		 3513 ixgbe_setup_mtqc(adapter);
3514
3515 if (hw->mac.type != ixgbe_mac_82598EB) {
3516 /* DMATXCTL.EN must be before Tx queues are enabled */
3517 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3518 dmatxctl |= IXGBE_DMATXCTL_TE;
3519 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3520 }
3521
9a799d71 3522 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3523 for (i = 0; i < adapter->num_tx_queues; i++)
3524 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
33fdc82f
JF		 3525 for (i = 0; i < adapter->num_xdp_queues; i++)
3526 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]);
9a799d71
AK		 3527}
3528
3ebe8fde
AD		 3529static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3530 struct ixgbe_ring *ring)
3531{
3532 struct ixgbe_hw *hw = &adapter->hw;
3533 u8 reg_idx = ring->reg_idx;
3534 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3535
3536 srrctl |= IXGBE_SRRCTL_DROP_EN;
3537
3538 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3539}
3540
3541static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3542 struct ixgbe_ring *ring)
3543{
3544 struct ixgbe_hw *hw = &adapter->hw;
3545 u8 reg_idx = ring->reg_idx;
3546 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3547
3548 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3549
3550 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3551}
3552
3553#ifdef CONFIG_IXGBE_DCB
3554void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3555#else
3556static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3557#endif
3558{
3559 int i;
3560 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3561
3562 if (adapter->ixgbe_ieee_pfc)
3563 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3564
3565 /*
3566 * We should set the drop enable bit if:
3567 * SR-IOV is enabled
3568 * or
3569 * Number of Rx queues > 1 and flow control is disabled
3570 *
3571 * This allows us to avoid head of line blocking for security
3572 * and performance reasons.
3573 */
3574 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3575 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3576 for (i = 0; i < adapter->num_rx_queues; i++)
3577 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3578 } else {
3579 for (i = 0; i < adapter->num_rx_queues; i++)
3580 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3581 }
3582}
3583
e8e26350 3584#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3585
a6616b42 3586static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3587 struct ixgbe_ring *rx_ring)
cc41ac7c 3588{
45e9baa5 3589 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3590 u32 srrctl;
bf29ee6c 3591 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3592
45e9baa5
AD		 3593 if (hw->mac.type == ixgbe_mac_82598EB) {
3594 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3595
45e9baa5
AD		 3596 /*
3597 * if VMDq is not active we must program one srrctl register
3598 * per RSS queue since we have enabled RDRXCTL.MVMEN
3599 */
3600 reg_idx &= mask;
3601 }
cc41ac7c 3602
45e9baa5
AD		 3603 /* configure header buffer length, needed for RSC */
3604 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3605
45e9baa5 3606 /* configure the packet buffer length */
2de6aa3a
AD		 3607 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state))
3608 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3609 else
3610 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3611
3612 /* configure descriptor type */
f800326d 3613 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3614
45e9baa5 3615 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3616}
9a799d71 3617
dfaf891d 3618/**
a897a2ad 3619 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3620 * @adapter: device handle
3621 *
3622 * - 82598/82599/X540: 128
3623 * - X550(non-SRIOV mode): 512
3624 * - X550(SRIOV mode): 64
3625 */
7f276efb 3626u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3627{
3628 if (adapter->hw.mac.type < ixgbe_mac_X550)
3629 return 128;
3630 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3631 return 64;
3632 else
3633 return 512;
3634}
3635
d3aa9c9f
PA		 3636/**
3637 * ixgbe_store_key - Write the RSS key to HW
3638 * @adapter: device handle
3639 *
3640 * Write the RSS key stored in adapter.rss_key to HW.
3641 */
3642void ixgbe_store_key(struct ixgbe_adapter *adapter)
3643{
3644 struct ixgbe_hw *hw = &adapter->hw;
3645 int i;
3646
3647 for (i = 0; i < 10; i++)
3648 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3649}
3650
3dfbfc7e
TN		 3651/**
3652 * ixgbe_init_rss_key - Initialize adapter RSS key
3653 * @adapter: device handle
3654 *
3655 * Allocates and initializes the RSS key if it is not allocated.
3656 **/
3657static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter)
3658{
3659 u32 *rss_key;
3660
3661 if (!adapter->rss_key) {
3662 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL);
3663 if (unlikely(!rss_key))
3664 return -ENOMEM;
3665
3666 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE);
3667 adapter->rss_key = rss_key;
3668 }
3669
3670 return 0;
3671}
3672
dfaf891d 3673/**
a897a2ad 3674 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3675 * @adapter: device handle
3676 *
3677 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3678 */
1c7cf078 3679void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3680{
dfaf891d 3681 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3682 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3683 u32 reta = 0;
dfaf891d
VZ		 3684 u32 indices_multi;
3685 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3686
0f9b232b 3687 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3688 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3689 * indices.
3690 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3691 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3692 */
3693 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3694 indices_multi = 0x11;
3695 else
3696 indices_multi = 0x1;
3697
dfaf891d
VZ		 3698 /* Write redirection table to HW */
3699 for (i = 0; i < reta_entries; i++) {
3700 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3701 if ((i & 3) == 3) {
3702 if (i < 128)
3703 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3704 else
3705 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3706 reta);
dfaf891d 3707 reta = 0;
0f9b232b
DS		 3708 }
3709 }
3710}
3711
dfaf891d 3712/**
a897a2ad 3713 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3714 * @adapter: device handle
3715 *
3716 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3717 */
3718static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3719{
dfaf891d 3720 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3721 struct ixgbe_hw *hw = &adapter->hw;
3722 u32 vfreta = 0;
dfaf891d
VZ		 3723 unsigned int pf_pool = adapter->num_vfs;
3724
3725 /* Write redirection table to HW */
3726 for (i = 0; i < reta_entries; i++) {
3727 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3728 if ((i & 3) == 3) {
3729 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3730 vfreta);
3731 vfreta = 0;
3732 }
3733 }
3734}
3735
3736static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3737{
dfaf891d
VZ		 3738 u32 i, j;
3739 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3740 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3741
e24fcf28 3742 /* Program table for at least 4 queues w/ SR-IOV so that VFs can
dfaf891d
VZ		 3743 * make full use of any rings they may have. We will use the
3744 * PSRTYPE register to control how many rings we use within the PF.
3745 */
e24fcf28
AD		 3746 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3747 rss_i = 4;
dfaf891d
VZ		 3748
3749 /* Fill out hash function seeds */
d3aa9c9f 3750 ixgbe_store_key(adapter);
dfaf891d
VZ		 3751
3752 /* Fill out redirection table */
3753 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3754
3755 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3756 if (j == rss_i)
3757 j = 0;
3758
3759 adapter->rss_indir_tbl[i] = j;
3760 }
3761
3762 ixgbe_store_reta(adapter);
3763}
3764
3765static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3766{
3767 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3768 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3769 unsigned int pf_pool = adapter->num_vfs;
3770 int i, j;
3771
3772 /* Fill out hash function seeds */
3773 for (i = 0; i < 10; i++)
dfaf891d 3774 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3dfbfc7e 3775 *(adapter->rss_key + i));
0f9b232b
DS		 3776
3777 /* Fill out the redirection table */
3778 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3779 if (j == rss_i)
05abb126 3780 j = 0;
dfaf891d
VZ		 3781
3782 adapter->rss_indir_tbl[i] = j;
05abb126 3783 }
dfaf891d
VZ		 3784
3785 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3786}
3787
3788static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3789{
3790 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3791 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3792 u32 rxcsum;
0cefafad 3793
05abb126
AD		 3794 /* Disable indicating checksum in descriptor, enables RSS hash */
3795 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3796 rxcsum |= IXGBE_RXCSUM_PCSD;
3797 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3798
671c0adb 3799 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3800 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3801 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3802 } else {
671c0adb
AD		 3803 u8 tcs = netdev_get_num_tc(adapter->netdev);
3804
3805 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3806 if (tcs > 4)
3807 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3808 else if (tcs > 1)
3809 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
e24fcf28
AD		 3810 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3811 IXGBE_82599_VMDQ_4Q_MASK)
671c0adb 3812 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3813 else
671c0adb 3814 mrqc = IXGBE_MRQC_VMDQRSS64EN;
e6b41c88
ET		 3815
3816 /* Enable L3/L4 for Tx Switched packets */
3817 mrqc |= IXGBE_MRQC_L3L4TXSWEN;
671c0adb
AD		 3818 } else {
3819 if (tcs > 4)
8b1c0b24 3820 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3821 else if (tcs > 1)
3822 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3823 else
3824 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3825 }
0cefafad
JB		 3826 }
3827
05abb126 3828 /* Perform hash on these packet types */
d1b849b9
DS		 3829 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3830 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3831 IXGBE_MRQC_RSS_FIELD_IPV6 |
3832 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3833
ef6afc0c 3834 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3835 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3836 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3837 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3838
0f9b232b
DS		 3839 if ((hw->mac.type >= ixgbe_mac_X550) &&
3840 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3841 unsigned int pf_pool = adapter->num_vfs;
3842
3843 /* Enable VF RSS mode */
3844 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3845 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3846
3847 /* Setup RSS through the VF registers */
dfaf891d 3848 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3849 vfmrqc = IXGBE_MRQC_RSSEN;
3850 vfmrqc |= rss_field;
3851 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3852 } else {
dfaf891d 3853 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3854 mrqc |= rss_field;
3855 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3856 }
0cefafad
JB		 3857}
3858
bb5a9ad2
NS		 3859/**
3860 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3861 * @adapter: address of board private structure
3862 * @index: index of ring to set
bb5a9ad2 3863 **/
082757af 3864static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3865 struct ixgbe_ring *ring)
bb5a9ad2 3866{
bb5a9ad2 3867 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3868 u32 rscctrl;
bf29ee6c 3869 u8 reg_idx = ring->reg_idx;
7367096a 3870
7d637bcc 3871 if (!ring_is_rsc_enabled(ring))
7367096a 3872 return;
bb5a9ad2 3873
7367096a 3874 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3875 rscctrl |= IXGBE_RSCCTL_RSCEN;
3876 /*
3877 * we must limit the number of descriptors so that the
3878 * total size of max desc * buf_len is not greater
642c680e 3879 * than 65536
bb5a9ad2 3880 */
f800326d 3881 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3882 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3883}
3884
9e10e045
AD		 3885#define IXGBE_MAX_RX_DESC_POLL 10
3886static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3887 struct ixgbe_ring *ring)
3888{
3889 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3890 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3891 u32 rxdctl;
bf29ee6c 3892 u8 reg_idx = ring->reg_idx;
9e10e045 3893
b0483c8f
MR		 3894 if (ixgbe_removed(hw->hw_addr))
3895 return;
9e10e045
AD		 3896 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3897 if (hw->mac.type == ixgbe_mac_82598EB &&
3898 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3899 return;
3900
3901 do {
032b4325 3902 usleep_range(1000, 2000);
9e10e045
AD		 3903 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3904 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3905
3906 if (!wait_loop) {
3907 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3908 "the polling period\n", reg_idx);
3909 }
3910}
3911
2d39d576
YZ		 3912void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3913 struct ixgbe_ring *ring)
3914{
3915 struct ixgbe_hw *hw = &adapter->hw;
3916 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3917 u32 rxdctl;
3918 u8 reg_idx = ring->reg_idx;
3919
b0483c8f
MR		 3920 if (ixgbe_removed(hw->hw_addr))
3921 return;
2d39d576
YZ		 3922 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3923 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3924
3925 /* write value back with RXDCTL.ENABLE bit cleared */
3926 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3927
3928 if (hw->mac.type == ixgbe_mac_82598EB &&
3929 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3930 return;
3931
3932 /* the hardware may take up to 100us to really disable the rx queue */
3933 do {
3934 udelay(10);
3935 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3936 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3937
3938 if (!wait_loop) {
3939 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3940 "the polling period\n", reg_idx);
3941 }
3942}
3943
84418e3b
AD		 3944void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3945 struct ixgbe_ring *ring)
acd37177
AD		 3946{
3947 struct ixgbe_hw *hw = &adapter->hw;
c3630cc4 3948 union ixgbe_adv_rx_desc *rx_desc;
acd37177 3949 u64 rdba = ring->dma;
9e10e045 3950 u32 rxdctl;
bf29ee6c 3951 u8 reg_idx = ring->reg_idx;
acd37177 3952
9e10e045
AD		 3953 /* disable queue to avoid issues while updating state */
3954 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3955 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3956
acd37177
AD		 3957 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3958 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3959 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3960 ring->count * sizeof(union ixgbe_adv_rx_desc));
8b75451b
NP		 3961 /* Force flushing of IXGBE_RDLEN to prevent MDD */
3962 IXGBE_WRITE_FLUSH(hw);
3963
acd37177
AD		 3964 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3965 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3966 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3967
3968 ixgbe_configure_srrctl(adapter, ring);
3969 ixgbe_configure_rscctl(adapter, ring);
3970
3971 if (hw->mac.type == ixgbe_mac_82598EB) {
3972 /*
3973 * enable cache line friendly hardware writes:
3974 * PTHRESH=32 descriptors (half the internal cache),
3975 * this also removes ugly rx_no_buffer_count increment
3976 * HTHRESH=4 descriptors (to minimize latency on fetch)
3977 * WTHRESH=8 burst writeback up to two cache lines
3978 */
3979 rxdctl &= ~0x3FFFFF;
3980 rxdctl |= 0x080420;
2de6aa3a
AD		 3981#if (PAGE_SIZE < 8192)
3982 } else {
3983 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
3984 IXGBE_RXDCTL_RLPML_EN);
3985
3986 /* Limit the maximum frame size so we don't overrun the skb */
3987 if (ring_uses_build_skb(ring) &&
3988 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
541ea69a 3989 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB |
2de6aa3a
AD		 3990 IXGBE_RXDCTL_RLPML_EN;
3991#endif
9e10e045
AD		 3992 }
3993
ffed21bc
AD		 3994 /* initialize rx_buffer_info */
3995 memset(ring->rx_buffer_info, 0,
3996 sizeof(struct ixgbe_rx_buffer) * ring->count);
3997
c3630cc4
AD		 3998 /* initialize Rx descriptor 0 */
3999 rx_desc = IXGBE_RX_DESC(ring, 0);
4000 rx_desc->wb.upper.length = 0;
4001
9e10e045
AD		 4002 /* enable receive descriptor ring */
4003 rxdctl |= IXGBE_RXDCTL_ENABLE;
4004 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4005
4006 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 4007 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 4008}
4009
48654521
AD		 4010static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
4011{
4012 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 4013 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 4014 u16 pool;
48654521
AD		 4015
4016 /* PSRTYPE must be initialized in non 82598 adapters */
4017 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 4018 IXGBE_PSRTYPE_UDPHDR |
4019 IXGBE_PSRTYPE_IPV4HDR |
48654521 4020 IXGBE_PSRTYPE_L2HDR |
e8e9f696 4021 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 4022
4023 if (hw->mac.type == ixgbe_mac_82598EB)
4024 return;
4025
fbe7ca7f 4026 if (rss_i > 3)
b4f47a48 4027 psrtype |= 2u << 29;
fbe7ca7f 4028 else if (rss_i > 1)
b4f47a48 4029 psrtype |= 1u << 29;
48654521 4030
2a47fa45
JF		 4031 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
4032 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 4033}
4034
f5b4a52e
AD		 4035static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
4036{
4037 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 4038 u32 reg_offset, vf_shift;
435b19f6 4039 u32 gcr_ext, vmdctl;
de4c7f65 4040 int i;
f5b4a52e
AD		 4041
4042 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
4043 return;
4044
4045 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 4046 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
4047 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 4048 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 4049 vmdctl |= IXGBE_VT_CTL_REPLEN;
4050 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 4051
1d9c0bfd
AD		 4052 vf_shift = VMDQ_P(0) % 32;
4053 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 4054
4055 /* Enable only the PF's pool for Tx/Rx */
11f2b494 4056 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
435b19f6 4057 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
11f2b494 4058 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
435b19f6 4059 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 4060 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 4061 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 4062
4063 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 4064 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e 4065
16369564
AD		 4066 /* clear VLAN promisc flag so VFTA will be updated if necessary */
4067 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4068
f5b4a52e
AD		 4069 /*
4070 * Set up VF register offsets for selected VT Mode,
4071 * i.e. 32 or 64 VFs for SR-IOV
4072 */
73079ea0
AD		 4073 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4074 case IXGBE_82599_VMDQ_8Q_MASK:
4075 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
4076 break;
4077 case IXGBE_82599_VMDQ_4Q_MASK:
4078 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
4079 break;
4080 default:
4081 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
4082 break;
4083 }
4084
f5b4a52e
AD		 4085 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4086
de4c7f65 4087 for (i = 0; i < adapter->num_vfs; i++) {
77f192af
ET		 4088 /* configure spoof checking */
4089 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
4090 adapter->vfinfo[i].spoofchk_enabled);
e65ce0d3
VZ		 4091
4092 /* Enable/Disable RSS query feature */
4093 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
4094 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 4095 }
f5b4a52e
AD		 4096}
4097
477de6ed 4098static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 4099{
9a799d71
AK		 4100 struct ixgbe_hw *hw = &adapter->hw;
4101 struct net_device *netdev = adapter->netdev;
4102 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 4103 struct ixgbe_ring *rx_ring;
4104 int i;
4105 u32 mhadd, hlreg0;
48654521 4106
63f39bd1 4107#ifdef IXGBE_FCOE
477de6ed
AD		 4108 /* adjust max frame to be able to do baby jumbo for FCoE */
4109 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4110 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
4111 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 4112
477de6ed 4113#endif /* IXGBE_FCOE */
872844dd
AD		 4114
4115 /* adjust max frame to be at least the size of a standard frame */
4116 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4117 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
4118
477de6ed
AD		 4119 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4120 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
4121 mhadd &= ~IXGBE_MHADD_MFS_MASK;
4122 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
4123
4124 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4125 }
4126
4127 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4128 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
4129 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4130 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 4131
0cefafad
JB		 4132 /*
4133 * Setup the HW Rx Head and Tail Descriptor Pointers and
4134 * the Base and Length of the Rx Descriptor Ring
4135 */
9a799d71 4136 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4137 rx_ring = adapter->rx_ring[i];
4f4542bf
AD		 4138
4139 clear_ring_rsc_enabled(rx_ring);
4140 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
2de6aa3a 4141 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4f4542bf 4142
7d637bcc
AD		 4143 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4144 set_ring_rsc_enabled(rx_ring);
4f4542bf
AD		 4145
4146 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state))
4147 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
2de6aa3a 4148
6f429223 4149 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
2de6aa3a
AD		 4150 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
4151 continue;
4152
4153 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4154
4155#if (PAGE_SIZE < 8192)
4156 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4157 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4158
541ea69a
AD		 4159 if (IXGBE_2K_TOO_SMALL_WITH_PADDING ||
4160 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
2de6aa3a
AD		 4161 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4162#endif
477de6ed 4163 }
477de6ed
AD		 4164}
4165
7367096a
AD		 4166static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
4167{
4168 struct ixgbe_hw *hw = &adapter->hw;
4169 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4170
4171 switch (hw->mac.type) {
4172 case ixgbe_mac_82598EB:
4173 /*
4174 * For VMDq support of different descriptor types or
4175 * buffer sizes through the use of multiple SRRCTL
4176 * registers, RDRXCTL.MVMEN must be set to 1
4177 *
4178 * also, the manual doesn't mention it clearly but DCA hints
4179 * will only use queue 0's tags unless this bit is set. Side
4180 * effects of setting this bit are only that SRRCTL must be
4181 * fully programmed [0..15]
4182 */
4183 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
4184 break;
052a1a72
MR		 4185 case ixgbe_mac_X550:
4186 case ixgbe_mac_X550EM_x:
49425dfc 4187 case ixgbe_mac_x550em_a:
f961ddae
MR		 4188 if (adapter->num_vfs)
4189 rdrxctl |= IXGBE_RDRXCTL_PSP;
93df9465 4190 /* fall through */
7367096a 4191 case ixgbe_mac_82599EB:
b93a2226 4192 case ixgbe_mac_X540:
7367096a
AD		 4193 /* Disable RSC for ACK packets */
4194 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
4195 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
4196 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4197 /* hardware requires some bits to be set by default */
4198 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
4199 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4200 break;
4201 default:
4202 /* We should do nothing since we don't know this hardware */
4203 return;
4204 }
4205
4206 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4207}
4208
477de6ed
AD		 4209/**
4210 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
4211 * @adapter: board private structure
4212 *
4213 * Configure the Rx unit of the MAC after a reset.
4214 **/
4215static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
4216{
4217 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 4218 int i;
6dcc28b9 4219 u32 rxctrl, rfctl;
477de6ed
AD		 4220
4221 /* disable receives while setting up the descriptors */
1f9ac57c 4222 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 4223
4224 ixgbe_setup_psrtype(adapter);
7367096a 4225 ixgbe_setup_rdrxctl(adapter);
477de6ed 4226
6dcc28b9
JK		 4227 /* RSC Setup */
4228 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4229 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4230 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
4231 rfctl |= IXGBE_RFCTL_RSC_DIS;
a21d0822
ET		 4232
4233 /* disable NFS filtering */
4234 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
6dcc28b9
JK		 4235 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4236
9e10e045 4237 /* Program registers for the distribution of queues */
f5b4a52e 4238 ixgbe_setup_mrqc(adapter);
f5b4a52e 4239
477de6ed
AD		 4240 /* set_rx_buffer_len must be called before ring initialization */
4241 ixgbe_set_rx_buffer_len(adapter);
4242
4243 /*
4244 * Setup the HW Rx Head and Tail Descriptor Pointers and
4245 * the Base and Length of the Rx Descriptor Ring
4246 */
9e10e045
AD		 4247 for (i = 0; i < adapter->num_rx_queues; i++)
4248 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 4249
1f9ac57c 4250 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 4251 /* disable drop enable for 82598 parts */
4252 if (hw->mac.type == ixgbe_mac_82598EB)
4253 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4254
4255 /* enable all receives */
4256 rxctrl |= IXGBE_RXCTRL_RXEN;
4257 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 4258}
4259
80d5c368
PM		 4260static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
4261 __be16 proto, u16 vid)
068c89b0
DS		 4262{
4263 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4264 struct ixgbe_hw *hw = &adapter->hw;
4265
4266 /* add VID to filter table */
18be4fce
AD		 4267 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4268 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
4269
f62bbb5e 4270 set_bit(vid, adapter->active_vlans);
8e586137
JP		 4271
4272 return 0;
068c89b0
DS		 4273}
4274
e1d0a2af
AD		 4275static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
4276{
4277 u32 vlvf;
4278 int idx;
4279
4280 /* short cut the special case */
4281 if (vlan == 0)
4282 return 0;
4283
4284 /* Search for the vlan id in the VLVF entries */
4285 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
4286 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
4287 if ((vlvf & VLAN_VID_MASK) == vlan)
4288 break;
4289 }
4290
4291 return idx;
4292}
4293
4294void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
4295{
4296 struct ixgbe_hw *hw = &adapter->hw;
4297 u32 bits, word;
4298 int idx;
4299
4300 idx = ixgbe_find_vlvf_entry(hw, vid);
4301 if (!idx)
4302 return;
4303
4304 /* See if any other pools are set for this VLAN filter
4305 * entry other than the PF.
4306 */
4307 word = idx * 2 + (VMDQ_P(0) / 32);
b4f47a48 4308 bits = ~BIT(VMDQ_P(0) % 32);
e1d0a2af
AD		 4309 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4310
4311 /* Disable the filter so this falls into the default pool. */
4312 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4313 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4314 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4315 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4316 }
4317}
4318
80d5c368
PM		 4319static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4320 __be16 proto, u16 vid)
068c89b0
DS		 4321{
4322 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4323 struct ixgbe_hw *hw = &adapter->hw;
4324
068c89b0 4325 /* remove VID from filter table */
18be4fce 4326 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
e1d0a2af
AD		 4327 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4328
f62bbb5e 4329 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 4330
4331 return 0;
068c89b0
DS		 4332}
4333
f62bbb5e
JG		 4334/**
4335 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4336 * @adapter: driver data
4337 */
4338static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4339{
4340 struct ixgbe_hw *hw = &adapter->hw;
4341 u32 vlnctrl;
5f6c0181
JB		 4342 int i, j;
4343
4344 switch (hw->mac.type) {
4345 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4346 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4347 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4348 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4349 break;
4350 case ixgbe_mac_82599EB:
b93a2226 4351 case ixgbe_mac_X540:
9a75a1ac
DS		 4352 case ixgbe_mac_X550:
4353 case ixgbe_mac_X550EM_x:
49425dfc 4354 case ixgbe_mac_x550em_a:
5f6c0181 4355 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4356 struct ixgbe_ring *ring = adapter->rx_ring[i];
4357
4358 if (ring->l2_accel_priv)
4359 continue;
4360 j = ring->reg_idx;
5f6c0181
JB		 4361 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4362 vlnctrl &= ~IXGBE_RXDCTL_VME;
4363 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4364 }
4365 break;
4366 default:
4367 break;
4368 }
4369}
4370
4371/**
f62bbb5e 4372 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 4373 * @adapter: driver data
4374 */
f62bbb5e 4375static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 4376{
4377 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 4378 u32 vlnctrl;
5f6c0181
JB		 4379 int i, j;
4380
4381 switch (hw->mac.type) {
4382 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4383 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4384 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4385 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4386 break;
4387 case ixgbe_mac_82599EB:
b93a2226 4388 case ixgbe_mac_X540:
9a75a1ac
DS		 4389 case ixgbe_mac_X550:
4390 case ixgbe_mac_X550EM_x:
49425dfc 4391 case ixgbe_mac_x550em_a:
5f6c0181 4392 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4393 struct ixgbe_ring *ring = adapter->rx_ring[i];
4394
4395 if (ring->l2_accel_priv)
4396 continue;
4397 j = ring->reg_idx;
5f6c0181
JB		 4398 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4399 vlnctrl |= IXGBE_RXDCTL_VME;
4400 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4401 }
4402 break;
4403 default:
4404 break;
4405 }
4406}
4407
16369564
AD		 4408static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4409{
4410 struct ixgbe_hw *hw = &adapter->hw;
4411 u32 vlnctrl, i;
4412
f60439bc
AD		 4413 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4414
691e4121
ET		 4415 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4416 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4417 vlnctrl |= IXGBE_VLNCTRL_VFE;
4418 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4419 } else {
f60439bc 4420 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
16369564
AD		 4421 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4422 return;
4423 }
4424
691e4121
ET		 4425 /* Nothing to do for 82598 */
4426 if (hw->mac.type == ixgbe_mac_82598EB)
4427 return;
4428
16369564
AD		 4429 /* We are already in VLAN promisc, nothing to do */
4430 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4431 return;
4432
4433 /* Set flag so we don't redo unnecessary work */
4434 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4435
4436 /* Add PF to all active pools */
4437 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4438 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4439 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4440
b4f47a48 4441 vlvfb |= BIT(VMDQ_P(0) % 32);
16369564
AD		 4442 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4443 }
4444
4445 /* Set all bits in the VLAN filter table array */
4446 for (i = hw->mac.vft_size; i--;)
4447 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4448}
4449
4450#define VFTA_BLOCK_SIZE 8
4451static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4452{
4453 struct ixgbe_hw *hw = &adapter->hw;
4454 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4455 u32 vid_start = vfta_offset * 32;
4456 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4457 u32 i, vid, word, bits;
4458
4459 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4460 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4461
4462 /* pull VLAN ID from VLVF */
4463 vid = vlvf & VLAN_VID_MASK;
4464
4465 /* only concern outselves with a certain range */
4466 if (vid < vid_start || vid >= vid_end)
4467 continue;
4468
4469 if (vlvf) {
4470 /* record VLAN ID in VFTA */
b4f47a48 4471 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16369564
AD		 4472
4473 /* if PF is part of this then continue */
4474 if (test_bit(vid, adapter->active_vlans))
4475 continue;
4476 }
4477
4478 /* remove PF from the pool */
4479 word = i * 2 + VMDQ_P(0) / 32;
b4f47a48 4480 bits = ~BIT(VMDQ_P(0) % 32);
16369564
AD		 4481 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4482 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4483 }
4484
4485 /* extract values from active_vlans and write back to VFTA */
4486 for (i = VFTA_BLOCK_SIZE; i--;) {
4487 vid = (vfta_offset + i) * 32;
4488 word = vid / BITS_PER_LONG;
4489 bits = vid % BITS_PER_LONG;
4490
4491 vfta[i] |= adapter->active_vlans[word] >> bits;
4492
4493 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4494 }
4495}
4496
4497static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4498{
4499 struct ixgbe_hw *hw = &adapter->hw;
4500 u32 vlnctrl, i;
4501
f60439bc
AD		 4502 /* Set VLAN filtering to enabled */
4503 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4504 vlnctrl |= IXGBE_VLNCTRL_VFE;
4505 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4506
691e4121
ET		 4507 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4508 hw->mac.type == ixgbe_mac_82598EB)
16369564 4509 return;
16369564
AD		 4510
4511 /* We are not in VLAN promisc, nothing to do */
4512 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4513 return;
4514
4515 /* Set flag so we don't redo unnecessary work */
4516 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4517
4518 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4519 ixgbe_scrub_vfta(adapter, i);
4520}
4521
9a799d71
AK		 4522static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4523{
06bb1c39 4524 u16 vid = 1;
9a799d71 4525
80d5c368 4526 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e 4527
06bb1c39 4528 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 4529 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 4530}
4531
b335e75b
JK		 4532/**
4533 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4534 * @netdev: network interface device structure
4535 *
4536 * Writes multicast address list to the MTA hash table.
4537 * Returns: -ENOMEM on failure
4538 * 0 on no addresses written
4539 * X on writing X addresses to MTA
4540 **/
4541static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4542{
4543 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4544 struct ixgbe_hw *hw = &adapter->hw;
4545
4546 if (!netif_running(netdev))
4547 return 0;
4548
4549 if (hw->mac.ops.update_mc_addr_list)
4550 hw->mac.ops.update_mc_addr_list(hw, netdev);
4551 else
4552 return -ENOMEM;
4553
4554#ifdef CONFIG_PCI_IOV
5d7daa35 4555 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4556#endif
4557
4558 return netdev_mc_count(netdev);
4559}
4560
5d7daa35
JK		 4561#ifdef CONFIG_PCI_IOV
4562void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4563{
c9f53e63 4564 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4565 struct ixgbe_hw *hw = &adapter->hw;
4566 int i;
c9f53e63
AD		 4567
4568 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4569 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4570
4571 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4572 hw->mac.ops.set_rar(hw, i,
4573 mac_table->addr,
4574 mac_table->pool,
5d7daa35
JK		 4575 IXGBE_RAH_AV);
4576 else
4577 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4578 }
4579}
5d7daa35 4580
c9f53e63 4581#endif
5d7daa35
JK		 4582static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4583{
c9f53e63 4584 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4585 struct ixgbe_hw *hw = &adapter->hw;
4586 int i;
5d7daa35 4587
c9f53e63
AD		 4588 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4589 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4590 continue;
4591
4592 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4593
4594 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4595 hw->mac.ops.set_rar(hw, i,
4596 mac_table->addr,
4597 mac_table->pool,
4598 IXGBE_RAH_AV);
4599 else
4600 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4601 }
4602}
4603
4604static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4605{
c9f53e63 4606 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4607 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4608 int i;
5d7daa35 4609
c9f53e63
AD		 4610 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4611 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4612 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
5d7daa35 4613 }
c9f53e63 4614
5d7daa35
JK		 4615 ixgbe_sync_mac_table(adapter);
4616}
4617
c9f53e63 4618static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
5d7daa35 4619{
c9f53e63 4620 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4621 struct ixgbe_hw *hw = &adapter->hw;
4622 int i, count = 0;
4623
c9f53e63
AD		 4624 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4625 /* do not count default RAR as available */
4626 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4627 continue;
4628
4629 /* only count unused and addresses that belong to us */
4630 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4631 if (mac_table->pool != pool)
4632 continue;
4633 }
4634
4635 count++;
5d7daa35 4636 }
c9f53e63 4637
5d7daa35
JK		 4638 return count;
4639}
4640
4641/* this function destroys the first RAR entry */
c9f53e63 4642static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
5d7daa35 4643{
c9f53e63 4644 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4645 struct ixgbe_hw *hw = &adapter->hw;
4646
c9f53e63
AD		 4647 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4648 mac_table->pool = VMDQ_P(0);
4649
4650 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4651
4652 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
5d7daa35
JK		 4653 IXGBE_RAH_AV);
4654}
4655
c9f53e63
AD		 4656int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4657 const u8 *addr, u16 pool)
5d7daa35 4658{
c9f53e63 4659 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4660 struct ixgbe_hw *hw = &adapter->hw;
4661 int i;
4662
4663 if (is_zero_ether_addr(addr))
4664 return -EINVAL;
4665
c9f53e63
AD		 4666 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4667 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
5d7daa35 4668 continue;
c9f53e63
AD		 4669
4670 ether_addr_copy(mac_table->addr, addr);
4671 mac_table->pool = pool;
4672
4673 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4674 IXGBE_MAC_STATE_IN_USE;
4675
5d7daa35 4676 ixgbe_sync_mac_table(adapter);
c9f53e63 4677
5d7daa35
JK		 4678 return i;
4679 }
c9f53e63 4680
5d7daa35
JK		 4681 return -ENOMEM;
4682}
4683
c9f53e63
AD		 4684int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4685 const u8 *addr, u16 pool)
5d7daa35 4686{
c9f53e63 4687 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4688 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4689 int i;
5d7daa35
JK		 4690
4691 if (is_zero_ether_addr(addr))
4692 return -EINVAL;
4693
c9f53e63
AD		 4694 /* search table for addr, if found clear IN_USE flag and sync */
4695 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4696 /* we can only delete an entry if it is in use */
4697 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4698 continue;
4699 /* we only care about entries that belong to the given pool */
4700 if (mac_table->pool != pool)
4701 continue;
4702 /* we only care about a specific MAC address */
4703 if (!ether_addr_equal(addr, mac_table->addr))
4704 continue;
4705
4706 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4707 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4708
4709 ixgbe_sync_mac_table(adapter);
4710
4711 return 0;
5d7daa35 4712 }
c9f53e63 4713
5d7daa35
JK		 4714 return -ENOMEM;
4715}
2850062a
AD		 4716/**
4717 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4718 * @netdev: network interface device structure
4719 *
4720 * Writes unicast address list to the RAR table.
4721 * Returns: -ENOMEM on failure/insufficient address space
4722 * 0 on no addresses written
4723 * X on writing X addresses to the RAR table
4724 **/
5d7daa35 4725static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4726{
4727 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4728 int count = 0;
4729
4730 /* return ENOMEM indicating insufficient memory for addresses */
c9f53e63 4731 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
2850062a
AD		 4732 return -ENOMEM;
4733
95447461 4734 if (!netdev_uc_empty(netdev)) {
2850062a 4735 struct netdev_hw_addr *ha;
2850062a 4736 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4737 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4738 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4739 count++;
4740 }
4741 }
2850062a
AD		 4742 return count;
4743}
4744
0f079d22
AD		 4745static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4746{
4747 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4748 int ret;
4749
4750 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4751
4752 return min_t(int, ret, 0);
4753}
4754
4755static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4756{
4757 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4758
4759 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4760
4761 return 0;
4762}
4763
9a799d71 4764/**
2c5645cf 4765 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4766 * @netdev: network interface device structure
4767 *
2c5645cf
CL		 4768 * The set_rx_method entry point is called whenever the unicast/multicast
4769 * address list or the network interface flags are updated. This routine is
4770 * responsible for configuring the hardware for proper unicast, multicast and
4771 * promiscuous mode.
9a799d71 4772 **/
7f870475 4773void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4774{
4775 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4776 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4777 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
0c5a6166 4778 netdev_features_t features = netdev->features;
2850062a 4779 int count;
9a799d71
AK		 4780
4781 /* Check for Promiscuous and All Multicast modes */
9a799d71
AK		 4782 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4783
f5dc442b 4784 /* set all bits that we expect to always be set */
3f2d1c0f 4785 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4786 fctrl |= IXGBE_FCTRL_BAM;
4787 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4788 fctrl |= IXGBE_FCTRL_PMCF;
4789
2850062a
AD		 4790 /* clear the bits we are changing the status of */
4791 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
9a799d71 4792 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4793 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4794 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4795 vmolr |= IXGBE_VMOLR_MPE;
0c5a6166 4796 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
9a799d71 4797 } else {
746b9f02
PM		 4798 if (netdev->flags & IFF_ALLMULTI) {
4799 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4800 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4801 }
e433ea1f 4802 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4803 }
4804
4805 /*
4806 * Write addresses to available RAR registers, if there is not
4807 * sufficient space to store all the addresses then enable
4808 * unicast promiscuous mode
4809 */
0f079d22 4810 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
9dcb373c
JF		 4811 fctrl |= IXGBE_FCTRL_UPE;
4812 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4813 }
4814
cf78959c
ET		 4815 /* Write addresses to the MTA, if the attempt fails
4816 * then we should just turn on promiscuous mode so
4817 * that we can at least receive multicast traffic
4818 */
b335e75b
JK		 4819 count = ixgbe_write_mc_addr_list(netdev);
4820 if (count < 0) {
4821 fctrl |= IXGBE_FCTRL_MPE;
4822 vmolr |= IXGBE_VMOLR_MPE;
4823 } else if (count) {
4824 vmolr |= IXGBE_VMOLR_ROMPE;
4825 }
1d9c0bfd
AD		 4826
4827 if (hw->mac.type != ixgbe_mac_82598EB) {
4828 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4829 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4830 IXGBE_VMOLR_ROPE);
1d9c0bfd 4831 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4832 }
4833
3f2d1c0f 4834 /* This is useful for sniffing bad packets. */
0c5a6166 4835 if (features & NETIF_F_RXALL) {
3f2d1c0f
BG		 4836 /* UPE and MPE will be handled by normal PROMISC logic
4837 * in e1000e_set_rx_mode */
4838 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4839 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4840 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4841
4842 fctrl &= ~(IXGBE_FCTRL_DPF);
4843 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4844 }
4845
2850062a 4846 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4847
0c5a6166 4848 if (features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4849 ixgbe_vlan_strip_enable(adapter);
4850 else
4851 ixgbe_vlan_strip_disable(adapter);
0c5a6166
AD		 4852
4853 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4854 ixgbe_vlan_promisc_disable(adapter);
4855 else
4856 ixgbe_vlan_promisc_enable(adapter);
9a799d71
AK		 4857}
4858
021230d4
AV		 4859static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4860{
4861 int q_idx;
021230d4 4862
3ffc1af5 4863 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
49c7ffbe 4864 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 4865}
4866
4867static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4868{
4869 int q_idx;
021230d4 4870
3ffc1af5 4871 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
49c7ffbe 4872 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 4873}
4874
a21d0822 4875static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask)
67359c3c 4876{
a21d0822
ET		 4877 struct ixgbe_hw *hw = &adapter->hw;
4878 u32 vxlanctrl;
4879
4880 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE |
4881 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)))
4882 return;
4883
4884 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) && ~mask;
4885 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl);
4886
4887 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK)
67359c3c 4888 adapter->vxlan_port = 0;
a21d0822
ET		 4889
4890 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK)
4891 adapter->geneve_port = 0;
67359c3c
MR		 4892}
4893
7a6b6f51 4894#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4895/**
2f90b865
AD		 4896 * ixgbe_configure_dcb - Configure DCB hardware
4897 * @adapter: ixgbe adapter struct
4898 *
4899 * This is called by the driver on open to configure the DCB hardware.
4900 * This is also called by the gennetlink interface when reconfiguring
4901 * the DCB state.
4902 */
4903static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4904{
4905 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4906 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4907
67ebd791
AD		 4908 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4909 if (hw->mac.type == ixgbe_mac_82598EB)
4910 netif_set_gso_max_size(adapter->netdev, 65536);
4911 return;
4912 }
4913
4914 if (hw->mac.type == ixgbe_mac_82598EB)
4915 netif_set_gso_max_size(adapter->netdev, 32768);
4916
971060b1 4917#ifdef IXGBE_FCOE
b120818e
JF		 4918 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4919 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4920#endif
b120818e
JF		 4921
4922 /* reconfigure the hardware */
4923 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4924 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4925 DCB_TX_CONFIG);
4926 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4927 DCB_RX_CONFIG);
4928 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4929 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4930 ixgbe_dcb_hw_ets(&adapter->hw,
4931 adapter->ixgbe_ieee_ets,
4932 max_frame);
4933 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4934 adapter->ixgbe_ieee_pfc->pfc_en,
4935 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4936 }
8187cd48
JF		 4937
4938 /* Enable RSS Hash per TC */
4939 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4940 u32 msb = 0;
4941 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4942
d411a936
AD		 4943 while (rss_i) {
4944 msb++;
4945 rss_i >>= 1;
4946 }
8187cd48 4947
4ae63730
AD		 4948 /* write msb to all 8 TCs in one write */
4949 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4950 }
2f90b865 4951}
9da712d2
JF		 4952#endif
4953
4954/* Additional bittime to account for IXGBE framing */
4955#define IXGBE_ETH_FRAMING 20
4956
49ce9c2c 4957/**
9da712d2
JF		 4958 * ixgbe_hpbthresh - calculate high water mark for flow control
4959 *
4960 * @adapter: board private structure to calculate for
49ce9c2c 4961 * @pb: packet buffer to calculate
9da712d2
JF		 4962 */
4963static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4964{
4965 struct ixgbe_hw *hw = &adapter->hw;
4966 struct net_device *dev = adapter->netdev;
4967 int link, tc, kb, marker;
4968 u32 dv_id, rx_pba;
4969
4970 /* Calculate max LAN frame size */
4971 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4972
4973#ifdef IXGBE_FCOE
4974 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4975 if ((dev->features & NETIF_F_FCOE_MTU) &&
4976 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4977 (pb == ixgbe_fcoe_get_tc(adapter)))
4978 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4979#endif
e5776620 4980
9da712d2
JF		 4981 /* Calculate delay value for device */
4982 switch (hw->mac.type) {
4983 case ixgbe_mac_X540:
9a75a1ac
DS		 4984 case ixgbe_mac_X550:
4985 case ixgbe_mac_X550EM_x:
49425dfc 4986 case ixgbe_mac_x550em_a:
9da712d2
JF		 4987 dv_id = IXGBE_DV_X540(link, tc);
4988 break;
4989 default:
4990 dv_id = IXGBE_DV(link, tc);
4991 break;
4992 }
4993
4994 /* Loopback switch introduces additional latency */
4995 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4996 dv_id += IXGBE_B2BT(tc);
4997
4998 /* Delay value is calculated in bit times convert to KB */
4999 kb = IXGBE_BT2KB(dv_id);
5000 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
5001
5002 marker = rx_pba - kb;
5003
5004 /* It is possible that the packet buffer is not large enough
5005 * to provide required headroom. In this case throw an error
5006 * to user and a do the best we can.
5007 */
5008 if (marker < 0) {
5009 e_warn(drv, "Packet Buffer(%i) can not provide enough"
5010 "headroom to support flow control."
5011 "Decrease MTU or number of traffic classes\n", pb);
5012 marker = tc + 1;
5013 }
5014
5015 return marker;
5016}
5017
49ce9c2c 5018/**
9da712d2
JF		 5019 * ixgbe_lpbthresh - calculate low water mark for for flow control
5020 *
5021 * @adapter: board private structure to calculate for
49ce9c2c 5022 * @pb: packet buffer to calculate
9da712d2 5023 */
e5776620 5024static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 5025{
5026 struct ixgbe_hw *hw = &adapter->hw;
5027 struct net_device *dev = adapter->netdev;
5028 int tc;
5029 u32 dv_id;
5030
5031 /* Calculate max LAN frame size */
5032 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5033
e5776620
JK		 5034#ifdef IXGBE_FCOE
5035 /* FCoE traffic class uses FCOE jumbo frames */
5036 if ((dev->features & NETIF_F_FCOE_MTU) &&
5037 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5038 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
5039 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5040#endif
5041
9da712d2
JF		 5042 /* Calculate delay value for device */
5043 switch (hw->mac.type) {
5044 case ixgbe_mac_X540:
9a75a1ac
DS		 5045 case ixgbe_mac_X550:
5046 case ixgbe_mac_X550EM_x:
49425dfc 5047 case ixgbe_mac_x550em_a:
9da712d2
JF		 5048 dv_id = IXGBE_LOW_DV_X540(tc);
5049 break;
5050 default:
5051 dv_id = IXGBE_LOW_DV(tc);
5052 break;
5053 }
5054
5055 /* Delay value is calculated in bit times convert to KB */
5056 return IXGBE_BT2KB(dv_id);
5057}
5058
5059/*
5060 * ixgbe_pbthresh_setup - calculate and setup high low water marks
5061 */
5062static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
5063{
5064 struct ixgbe_hw *hw = &adapter->hw;
5065 int num_tc = netdev_get_num_tc(adapter->netdev);
5066 int i;
5067
5068 if (!num_tc)
5069 num_tc = 1;
5070
9da712d2
JF		 5071 for (i = 0; i < num_tc; i++) {
5072 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 5073 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 5074
5075 /* Low water marks must not be larger than high water marks */
e5776620
JK		 5076 if (hw->fc.low_water[i] > hw->fc.high_water[i])
5077 hw->fc.low_water[i] = 0;
9da712d2 5078 }
e5776620
JK		 5079
5080 for (; i < MAX_TRAFFIC_CLASS; i++)
5081 hw->fc.high_water[i] = 0;
9da712d2
JF		 5082}
5083
80605c65
JF		 5084static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
5085{
80605c65 5086 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 5087 int hdrm;
5088 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 5089
5090 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5091 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 5092 hdrm = 32 << adapter->fdir_pballoc;
5093 else
5094 hdrm = 0;
80605c65 5095
f7e1027f 5096 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 5097 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 5098}
5099
e4911d57
AD		 5100static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
5101{
5102 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 5103 struct hlist_node *node2;
e4911d57
AD		 5104 struct ixgbe_fdir_filter *filter;
5105
5106 spin_lock(&adapter->fdir_perfect_lock);
5107
5108 if (!hlist_empty(&adapter->fdir_filter_list))
5109 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
5110
b67bfe0d 5111 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5112 &adapter->fdir_filter_list, fdir_node) {
5113 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 5114 &filter->filter,
5115 filter->sw_idx,
5116 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
5117 IXGBE_FDIR_DROP_QUEUE :
5118 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 5119 }
5120
5121 spin_unlock(&adapter->fdir_perfect_lock);
5122}
5123
2a47fa45
JF		 5124static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
5125 struct ixgbe_adapter *adapter)
5126{
5127 struct ixgbe_hw *hw = &adapter->hw;
5128 u32 vmolr;
5129
5130 /* No unicast promiscuous support for VMDQ devices. */
5131 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
5132 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
5133
5134 /* clear the affected bit */
5135 vmolr &= ~IXGBE_VMOLR_MPE;
5136
5137 if (dev->flags & IFF_ALLMULTI) {
5138 vmolr |= IXGBE_VMOLR_MPE;
5139 } else {
5140 vmolr |= IXGBE_VMOLR_ROMPE;
5141 hw->mac.ops.update_mc_addr_list(hw, dev);
5142 }
5d7daa35 5143 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 5144 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
5145}
5146
2a47fa45
JF		 5147static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
5148{
5149 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 5150 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 5151 struct ixgbe_hw *hw = &adapter->hw;
5152 u16 pool = vadapter->pool;
5153 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
5154 IXGBE_PSRTYPE_UDPHDR |
5155 IXGBE_PSRTYPE_IPV4HDR |
5156 IXGBE_PSRTYPE_L2HDR |
5157 IXGBE_PSRTYPE_IPV6HDR;
5158
5159 if (hw->mac.type == ixgbe_mac_82598EB)
5160 return;
5161
5162 if (rss_i > 3)
b4f47a48 5163 psrtype |= 2u << 29;
2a47fa45 5164 else if (rss_i > 1)
b4f47a48 5165 psrtype |= 1u << 29;
2a47fa45
JF		 5166
5167 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
5168}
5169
5170/**
5171 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
5172 * @rx_ring: ring to free buffers from
5173 **/
5174static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
5175{
ffed21bc
AD		 5176 u16 i = rx_ring->next_to_clean;
5177 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45
JF		 5178
5179 /* Free all the Rx ring sk_buffs */
ffed21bc 5180 while (i != rx_ring->next_to_alloc) {
2a47fa45
JF		 5181 if (rx_buffer->skb) {
5182 struct sk_buff *skb = rx_buffer->skb;
18cb652a 5183 if (IXGBE_CB(skb)->page_released)
ffed21bc 5184 dma_unmap_page_attrs(rx_ring->dev,
f3213d93
AD		 5185 IXGBE_CB(skb)->dma,
5186 ixgbe_rx_pg_size(rx_ring),
5187 DMA_FROM_DEVICE,
5188 IXGBE_RX_DMA_ATTR);
2a47fa45
JF		 5189 dev_kfree_skb(skb);
5190 }
18cb652a 5191
f3213d93
AD		 5192 /* Invalidate cache lines that may have been written to by
5193 * device so that we avoid corrupting memory.
5194 */
5195 dma_sync_single_range_for_cpu(rx_ring->dev,
5196 rx_buffer->dma,
5197 rx_buffer->page_offset,
5198 ixgbe_rx_bufsz(rx_ring),
5199 DMA_FROM_DEVICE);
5200
5201 /* free resources associated with mapping */
ffed21bc 5202 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
f3213d93
AD		 5203 ixgbe_rx_pg_size(rx_ring),
5204 DMA_FROM_DEVICE,
5205 IXGBE_RX_DMA_ATTR);
1b56cf49
AD		 5206 __page_frag_cache_drain(rx_buffer->page,
5207 rx_buffer->pagecnt_bias);
18cb652a 5208
ffed21bc
AD		 5209 i++;
5210 rx_buffer++;
5211 if (i == rx_ring->count) {
5212 i = 0;
5213 rx_buffer = rx_ring->rx_buffer_info;
5214 }
2a47fa45
JF		 5215 }
5216
2a47fa45
JF		 5217 rx_ring->next_to_alloc = 0;
5218 rx_ring->next_to_clean = 0;
5219 rx_ring->next_to_use = 0;
5220}
5221
5222static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
5223 struct ixgbe_ring *rx_ring)
5224{
5225 struct ixgbe_adapter *adapter = vadapter->real_adapter;
5226 int index = rx_ring->queue_index + vadapter->rx_base_queue;
5227
5228 /* shutdown specific queue receive and wait for dma to settle */
5229 ixgbe_disable_rx_queue(adapter, rx_ring);
5230 usleep_range(10000, 20000);
b4f47a48 5231 ixgbe_irq_disable_queues(adapter, BIT_ULL(index));
2a47fa45
JF		 5232 ixgbe_clean_rx_ring(rx_ring);
5233 rx_ring->l2_accel_priv = NULL;
5234}
5235
ae72c8d0
JF		 5236static int ixgbe_fwd_ring_down(struct net_device *vdev,
5237 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 5238{
5239 struct ixgbe_adapter *adapter = accel->real_adapter;
5240 unsigned int rxbase = accel->rx_base_queue;
5241 unsigned int txbase = accel->tx_base_queue;
5242 int i;
5243
5244 netif_tx_stop_all_queues(vdev);
5245
5246 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
5247 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
5248 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
5249 }
5250
5251 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
5252 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
5253 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
5254 }
5255
5256
5257 return 0;
5258}
5259
5260static int ixgbe_fwd_ring_up(struct net_device *vdev,
5261 struct ixgbe_fwd_adapter *accel)
5262{
5263 struct ixgbe_adapter *adapter = accel->real_adapter;
5264 unsigned int rxbase, txbase, queues;
5265 int i, baseq, err = 0;
5266
5267 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
5268 return 0;
5269
5270 baseq = accel->pool * adapter->num_rx_queues_per_pool;
5271 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
5272 accel->pool, adapter->num_rx_pools,
5273 baseq, baseq + adapter->num_rx_queues_per_pool,
5274 adapter->fwd_bitmask);
5275
5276 accel->netdev = vdev;
5277 accel->rx_base_queue = rxbase = baseq;
5278 accel->tx_base_queue = txbase = baseq;
5279
5280 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5281 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
5282
5283 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
5284 adapter->rx_ring[rxbase + i]->netdev = vdev;
5285 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
5286 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
5287 }
5288
5289 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
5290 adapter->tx_ring[txbase + i]->netdev = vdev;
5291 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
5292 }
5293
5294 queues = min_t(unsigned int,
5295 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
5296 err = netif_set_real_num_tx_queues(vdev, queues);
5297 if (err)
5298 goto fwd_queue_err;
5299
2a47fa45
JF		 5300 err = netif_set_real_num_rx_queues(vdev, queues);
5301 if (err)
5302 goto fwd_queue_err;
5303
5304 if (is_valid_ether_addr(vdev->dev_addr))
5305 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
5306
5307 ixgbe_fwd_psrtype(accel);
5308 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
5309 return err;
5310fwd_queue_err:
5311 ixgbe_fwd_ring_down(vdev, accel);
5312 return err;
5313}
5314
1cd127fc 5315static int ixgbe_upper_dev_walk(struct net_device *upper, void *data)
2a47fa45 5316{
1cd127fc
DA		 5317 if (netif_is_macvlan(upper)) {
5318 struct macvlan_dev *dfwd = netdev_priv(upper);
5319 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
2a47fa45 5320
1cd127fc
DA		 5321 if (dfwd->fwd_priv)
5322 ixgbe_fwd_ring_up(upper, vadapter);
2a47fa45 5323 }
1cd127fc
DA		 5324
5325 return 0;
5326}
5327
5328static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5329{
5330 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5331 ixgbe_upper_dev_walk, NULL);
2a47fa45
JF		 5332}
5333
9a799d71
AK		 5334static void ixgbe_configure(struct ixgbe_adapter *adapter)
5335{
d2f5e7f3
AS		 5336 struct ixgbe_hw *hw = &adapter->hw;
5337
80605c65 5338 ixgbe_configure_pb(adapter);
7a6b6f51 5339#ifdef CONFIG_IXGBE_DCB
67ebd791 5340 ixgbe_configure_dcb(adapter);
2f90b865 5341#endif
b35d4d42
AD		 5342 /*
5343 * We must restore virtualization before VLANs or else
5344 * the VLVF registers will not be populated
5345 */
5346 ixgbe_configure_virtualization(adapter);
9a799d71 5347
4c1d7b4b 5348 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 5349 ixgbe_restore_vlan(adapter);
5350
d2f5e7f3
AS		 5351 switch (hw->mac.type) {
5352 case ixgbe_mac_82599EB:
5353 case ixgbe_mac_X540:
5354 hw->mac.ops.disable_rx_buff(hw);
5355 break;
5356 default:
5357 break;
5358 }
5359
c4cf55e5 5360 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 5361 ixgbe_init_fdir_signature_82599(&adapter->hw,
5362 adapter->fdir_pballoc);
e4911d57
AD		 5363 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5364 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5365 adapter->fdir_pballoc);
5366 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 5367 }
4c1d7b4b 5368
d2f5e7f3
AS		 5369 switch (hw->mac.type) {
5370 case ixgbe_mac_82599EB:
5371 case ixgbe_mac_X540:
5372 hw->mac.ops.enable_rx_buff(hw);
5373 break;
5374 default:
5375 break;
5376 }
5377
9de7605e
MR		 5378#ifdef CONFIG_IXGBE_DCA
5379 /* configure DCA */
5380 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5381 ixgbe_setup_dca(adapter);
5382#endif /* CONFIG_IXGBE_DCA */
5383
7c8ae65a
AD		 5384#ifdef IXGBE_FCOE
5385 /* configure FCoE L2 filters, redirection table, and Rx control */
5386 ixgbe_configure_fcoe(adapter);
5387
5388#endif /* IXGBE_FCOE */
9a799d71
AK		 5389 ixgbe_configure_tx(adapter);
5390 ixgbe_configure_rx(adapter);
2a47fa45 5391 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 5392}
5393
0ecc061d 5394/**
e8e26350
PW		 5395 * ixgbe_sfp_link_config - set up SFP+ link
5396 * @adapter: pointer to private adapter struct
5397 **/
5398static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5399{
7086400d 5400 /*
52f33af8 5401 * We are assuming the worst case scenario here, and that
7086400d
AD		 5402 * is that an SFP was inserted/removed after the reset
5403 * but before SFP detection was enabled. As such the best
5404 * solution is to just start searching as soon as we start
5405 */
5406 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5407 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 5408
7086400d 5409 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 5410 adapter->sfp_poll_time = 0;
e8e26350
PW		 5411}
5412
5413/**
5414 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 5415 * @hw: pointer to private hardware struct
5416 *
5417 * Returns 0 on success, negative on failure
5418 **/
e8e26350 5419static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 5420{
3d292265
JH		 5421 u32 speed;
5422 bool autoneg, link_up = false;
a1e869de 5423 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 5424
5425 if (hw->mac.ops.check_link)
3d292265 5426 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 5427
5428 if (ret)
e90dd264 5429 return ret;
0ecc061d 5430
3d292265
JH		 5431 speed = hw->phy.autoneg_advertised;
5432 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5433 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5434 &autoneg);
0ecc061d 5435 if (ret)
e90dd264 5436 return ret;
0ecc061d 5437
8620a103 5438 if (hw->mac.ops.setup_link)
fd0326f2 5439 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 5440
0ecc061d
PWJ		 5441 return ret;
5442}
5443
a34bcfff 5444static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 5445{
9a799d71 5446 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5447 u32 gpie = 0;
9a799d71 5448
9b471446 5449 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 5450 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5451 IXGBE_GPIE_OCD;
5452 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 5453 /*
5454 * use EIAM to auto-mask when MSI-X interrupt is asserted
5455 * this saves a register write for every interrupt
5456 */
5457 switch (hw->mac.type) {
5458 case ixgbe_mac_82598EB:
5459 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5460 break;
9b471446 5461 case ixgbe_mac_82599EB:
b93a2226 5462 case ixgbe_mac_X540:
9a75a1ac
DS		 5463 case ixgbe_mac_X550:
5464 case ixgbe_mac_X550EM_x:
49425dfc 5465 case ixgbe_mac_x550em_a:
b93a2226 5466 default:
9b471446
JB		 5467 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5468 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5469 break;
5470 }
5471 } else {
021230d4
AV		 5472 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5473 * specifically only auto mask tx and rx interrupts */
5474 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5475 }
9a799d71 5476
a34bcfff
AD		 5477 /* XXX: to interrupt immediately for EICS writes, enable this */
5478 /* gpie |= IXGBE_GPIE_EIMEN; */
5479
5480 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5481 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 5482
5483 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5484 case IXGBE_82599_VMDQ_8Q_MASK:
5485 gpie |= IXGBE_GPIE_VTMODE_16;
5486 break;
5487 case IXGBE_82599_VMDQ_4Q_MASK:
5488 gpie |= IXGBE_GPIE_VTMODE_32;
5489 break;
5490 default:
5491 gpie |= IXGBE_GPIE_VTMODE_64;
5492 break;
5493 }
119fc60a
MC		 5494 }
5495
5fdd31f9 5496 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 5497 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5498 switch (adapter->hw.mac.type) {
5499 case ixgbe_mac_82599EB:
9a900eca 5500 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 5501 break;
f3df98ec
DS		 5502 default:
5503 break;
5504 }
5505 }
5fdd31f9 5506
a34bcfff
AD		 5507 /* Enable fan failure interrupt */
5508 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 5509 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 5510
a023bbd0
DS		 5511 switch (hw->mac.type) {
5512 case ixgbe_mac_82599EB:
5513 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5514 break;
5515 case ixgbe_mac_X550EM_x:
49425dfc 5516 case ixgbe_mac_x550em_a:
a023bbd0
DS		 5517 gpie |= IXGBE_SDP0_GPIEN_X540;
5518 break;
5519 default:
5520 break;
2698b208 5521 }
a34bcfff
AD		 5522
5523 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5524}
5525
c7ccde0f 5526static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 5527{
5528 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5529 int err;
a34bcfff
AD		 5530 u32 ctrl_ext;
5531
5532 ixgbe_get_hw_control(adapter);
5533 ixgbe_setup_gpie(adapter);
e8e26350 5534
9a799d71
AK		 5535 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5536 ixgbe_configure_msix(adapter);
5537 else
5538 ixgbe_configure_msi_and_legacy(adapter);
5539
ec74a471
ET		 5540 /* enable the optics for 82599 SFP+ fiber */
5541 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 5542 hw->mac.ops.enable_tx_laser(hw);
5543
961fac88
DS		 5544 if (hw->phy.ops.set_phy_power)
5545 hw->phy.ops.set_phy_power(hw, true);
5546
4e857c58 5547 smp_mb__before_atomic();
9a799d71 5548 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 5549 ixgbe_napi_enable_all(adapter);
5550
73c4b7cd
AD		 5551 if (ixgbe_is_sfp(hw)) {
5552 ixgbe_sfp_link_config(adapter);
5553 } else {
5554 err = ixgbe_non_sfp_link_config(hw);
5555 if (err)
5556 e_err(probe, "link_config FAILED %d\n", err);
5557 }
5558
021230d4
AV		 5559 /* clear any pending interrupts, may auto mask */
5560 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 5561 ixgbe_irq_enable(adapter, true, true);
9a799d71 5562
bf069c97
DS		 5563 /*
5564 * If this adapter has a fan, check to see if we had a failure
5565 * before we enabled the interrupt.
5566 */
5567 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5568 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5569 if (esdp & IXGBE_ESDP_SDP1)
396e799c 5570 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 5571 }
5572
9a799d71
AK		 5573 /* bring the link up in the watchdog, this could race with our first
5574 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 5575 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5576 adapter->link_check_timeout = jiffies;
7086400d 5577 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 5578
5579 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5580 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5581 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5582 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5583}
5584
d4f80882
AV		 5585void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5586{
5587 WARN_ON(in_interrupt());
7086400d 5588 /* put off any impending NetWatchDogTimeout */
860e9538 5589 netif_trans_update(adapter->netdev);
7086400d 5590
d4f80882 5591 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5592 usleep_range(1000, 2000);
b3eb4e18
MR		 5593 if (adapter->hw.phy.type == ixgbe_phy_fw)
5594 ixgbe_watchdog_link_is_down(adapter);
d4f80882 5595 ixgbe_down(adapter);
5809a1ae
GR		 5596 /*
5597 * If SR-IOV enabled then wait a bit before bringing the adapter
5598 * back up to give the VFs time to respond to the reset. The
5599 * two second wait is based upon the watchdog timer cycle in
5600 * the VF driver.
5601 */
5602 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5603 msleep(2000);
d4f80882
AV		 5604 ixgbe_up(adapter);
5605 clear_bit(__IXGBE_RESETTING, &adapter->state);
5606}
5607
c7ccde0f 5608void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5609{
5610 /* hardware has been reset, we need to reload some things */
5611 ixgbe_configure(adapter);
5612
c7ccde0f 5613 ixgbe_up_complete(adapter);
9a799d71
AK		 5614}
5615
5616void ixgbe_reset(struct ixgbe_adapter *adapter)
5617{
c44ade9e 5618 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5619 struct net_device *netdev = adapter->netdev;
8ca783ab
DS		 5620 int err;
5621
b0483c8f
MR		 5622 if (ixgbe_removed(hw->hw_addr))
5623 return;
7086400d
AD		 5624 /* lock SFP init bit to prevent race conditions with the watchdog */
5625 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5626 usleep_range(1000, 2000);
5627
5628 /* clear all SFP and link config related flags while holding SFP_INIT */
5629 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5630 IXGBE_FLAG2_SFP_NEEDS_RESET);
5631 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5632
8ca783ab 5633 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5634 switch (err) {
5635 case 0:
5636 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5637 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5638 break;
5639 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5640 e_dev_err("master disable timed out\n");
da4dd0f7 5641 break;
794caeb2
PWJ		 5642 case IXGBE_ERR_EEPROM_VERSION:
5643 /* We are running on a pre-production device, log a warning */
849c4542 5644 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5645 "Please be aware there may be issues associated with "
849c4542
ET		 5646 "your hardware. If you are experiencing problems "
5647 "please contact your Intel or hardware "
5648 "representative who provided you with this "
5649 "hardware.\n");
794caeb2 5650 break;
da4dd0f7 5651 default:
849c4542 5652 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5653 }
9a799d71 5654
7086400d 5655 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
0f079d22
AD		 5656
5657 /* flush entries out of MAC table */
5d7daa35 5658 ixgbe_flush_sw_mac_table(adapter);
0f079d22
AD		 5659 __dev_uc_unsync(netdev, NULL);
5660
5661 /* do not flush user set addresses */
c9f53e63 5662 ixgbe_mac_set_default_filter(adapter);
7fa7c9dc
AD		 5663
5664 /* update SAN MAC vmdq pool selection */
5665 if (hw->mac.san_mac_rar_index)
5666 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5667
8fecf67c 5668 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5669 ixgbe_ptp_reset(adapter);
961fac88
DS		 5670
5671 if (hw->phy.ops.set_phy_power) {
5672 if (!netif_running(adapter->netdev) && !adapter->wol)
5673 hw->phy.ops.set_phy_power(hw, false);
5674 else
5675 hw->phy.ops.set_phy_power(hw, true);
5676 }
9a799d71
AK		 5677}
5678
9a799d71
AK		 5679/**
5680 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5681 * @tx_ring: ring to be cleaned
5682 **/
b6ec895e 5683static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71 5684{
ffed21bc
AD		 5685 u16 i = tx_ring->next_to_clean;
5686 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
9a799d71 5687
ffed21bc
AD		 5688 while (i != tx_ring->next_to_use) {
5689 union ixgbe_adv_tx_desc *eop_desc, *tx_desc;
9a799d71 5690
ffed21bc 5691 /* Free all the Tx ring sk_buffs */
33fdc82f
JF		 5692 if (ring_is_xdp(tx_ring))
5693 page_frag_free(tx_buffer->data);
5694 else
5695 dev_kfree_skb_any(tx_buffer->skb);
9a799d71 5696
ffed21bc
AD		 5697 /* unmap skb header data */
5698 dma_unmap_single(tx_ring->dev,
5699 dma_unmap_addr(tx_buffer, dma),
5700 dma_unmap_len(tx_buffer, len),
5701 DMA_TO_DEVICE);
dad8a3b3 5702
ffed21bc
AD		 5703 /* check for eop_desc to determine the end of the packet */
5704 eop_desc = tx_buffer->next_to_watch;
5705 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5706
5707 /* unmap remaining buffers */
5708 while (tx_desc != eop_desc) {
5709 tx_buffer++;
5710 tx_desc++;
5711 i++;
5712 if (unlikely(i == tx_ring->count)) {
5713 i = 0;
5714 tx_buffer = tx_ring->tx_buffer_info;
5715 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5716 }
9a799d71 5717
ffed21bc
AD		 5718 /* unmap any remaining paged data */
5719 if (dma_unmap_len(tx_buffer, len))
5720 dma_unmap_page(tx_ring->dev,
5721 dma_unmap_addr(tx_buffer, dma),
5722 dma_unmap_len(tx_buffer, len),
5723 DMA_TO_DEVICE);
5724 }
9a799d71 5725
ffed21bc
AD		 5726 /* move us one more past the eop_desc for start of next pkt */
5727 tx_buffer++;
5728 i++;
5729 if (unlikely(i == tx_ring->count)) {
5730 i = 0;
5731 tx_buffer = tx_ring->tx_buffer_info;
5732 }
5733 }
5734
5735 /* reset BQL for queue */
33fdc82f
JF		 5736 if (!ring_is_xdp(tx_ring))
5737 netdev_tx_reset_queue(txring_txq(tx_ring));
ffed21bc
AD		 5738
5739 /* reset next_to_use and next_to_clean */
9a799d71
AK		 5740 tx_ring->next_to_use = 0;
5741 tx_ring->next_to_clean = 0;
9a799d71
AK		 5742}
5743
5744/**
021230d4 5745 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5746 * @adapter: board private structure
5747 **/
021230d4 5748static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5749{
5750 int i;
5751
021230d4 5752 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5753 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5754}
5755
5756/**
021230d4 5757 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5758 * @adapter: board private structure
5759 **/
021230d4 5760static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5761{
5762 int i;
5763
021230d4 5764 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5765 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
33fdc82f
JF		 5766 for (i = 0; i < adapter->num_xdp_queues; i++)
5767 ixgbe_clean_tx_ring(adapter->xdp_ring[i]);
9a799d71
AK		 5768}
5769
e4911d57
AD		 5770static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5771{
b67bfe0d 5772 struct hlist_node *node2;
e4911d57
AD		 5773 struct ixgbe_fdir_filter *filter;
5774
5775 spin_lock(&adapter->fdir_perfect_lock);
5776
b67bfe0d 5777 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5778 &adapter->fdir_filter_list, fdir_node) {
5779 hlist_del(&filter->fdir_node);
5780 kfree(filter);
5781 }
5782 adapter->fdir_filter_count = 0;
5783
5784 spin_unlock(&adapter->fdir_perfect_lock);
5785}
5786
1cd127fc
DA		 5787static int ixgbe_disable_macvlan(struct net_device *upper, void *data)
5788{
5789 if (netif_is_macvlan(upper)) {
5790 struct macvlan_dev *vlan = netdev_priv(upper);
5791
5792 if (vlan->fwd_priv) {
5793 netif_tx_stop_all_queues(upper);
5794 netif_carrier_off(upper);
5795 netif_tx_disable(upper);
5796 }
5797 }
5798
5799 return 0;
5800}
5801
9a799d71
AK		 5802void ixgbe_down(struct ixgbe_adapter *adapter)
5803{
5804 struct net_device *netdev = adapter->netdev;
7f821875 5805 struct ixgbe_hw *hw = &adapter->hw;
bf29ee6c 5806 int i;
9a799d71
AK		 5807
5808 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5809 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5810 return; /* do nothing if already down */
9a799d71
AK		 5811
5812 /* disable receives */
1f9ac57c 5813 hw->mac.ops.disable_rx(hw);
9a799d71 5814
2d39d576
YZ		 5815 /* disable all enabled rx queues */
5816 for (i = 0; i < adapter->num_rx_queues; i++)
5817 /* this call also flushes the previous write */
5818 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5819
032b4325 5820 usleep_range(10000, 20000);
9a799d71 5821
11393cc9
JF		 5822 /* synchronize_sched() needed for pending XDP buffers to drain */
5823 if (adapter->xdp_ring[0])
5824 synchronize_sched();
7f821875
JB		 5825 netif_tx_stop_all_queues(netdev);
5826
7086400d 5827 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5828 netif_carrier_off(netdev);
5829 netif_tx_disable(netdev);
5830
2a47fa45 5831 /* disable any upper devices */
1cd127fc
DA		 5832 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5833 ixgbe_disable_macvlan, NULL);
2a47fa45 5834
c0dfb90e
JF		 5835 ixgbe_irq_disable(adapter);
5836
5837 ixgbe_napi_disable_all(adapter);
5838
57ca2a4f
ET		 5839 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
5840 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7086400d
AD		 5841 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5842
5843 del_timer_sync(&adapter->service_timer);
5844
34cecbbf 5845 if (adapter->num_vfs) {
8e34d1aa
AD		 5846 /* Clear EITR Select mapping */
5847 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5848
5849 /* Mark all the VFs as inactive */
5850 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5851 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5852
34cecbbf
AD		 5853 /* ping all the active vfs to let them know we are going down */
5854 ixgbe_ping_all_vfs(adapter);
5855
5856 /* Disable all VFTE/VFRE TX/RX */
5857 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5858 }
5859
7f821875
JB		 5860 /* disable transmits in the hardware now that interrupts are off */
5861 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5862 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5863 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5864 }
33fdc82f
JF		 5865 for (i = 0; i < adapter->num_xdp_queues; i++) {
5866 u8 reg_idx = adapter->xdp_ring[i]->reg_idx;
5867
5868 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5869 }
34cecbbf 5870
9a75a1ac 5871 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5872 switch (hw->mac.type) {
5873 case ixgbe_mac_82599EB:
b93a2226 5874 case ixgbe_mac_X540:
9a75a1ac
DS		 5875 case ixgbe_mac_X550:
5876 case ixgbe_mac_X550EM_x:
49425dfc 5877 case ixgbe_mac_x550em_a:
88512539 5878 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5879 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5880 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5881 break;
5882 default:
5883 break;
5884 }
7f821875 5885
6f4a0e45
PL		 5886 if (!pci_channel_offline(adapter->pdev))
5887 ixgbe_reset(adapter);
c6ecf39a 5888
ec74a471
ET		 5889 /* power down the optics for 82599 SFP+ fiber */
5890 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5891 hw->mac.ops.disable_tx_laser(hw);
5892
9a799d71
AK		 5893 ixgbe_clean_all_tx_rings(adapter);
5894 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 5895}
5896
b3eb4e18
MR		 5897/**
5898 * ixgbe_eee_capable - helper function to determine EEE support on X550
5899 * @adapter: board private structure
5900 */
5901static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter)
5902{
5903 struct ixgbe_hw *hw = &adapter->hw;
5904
5905 switch (hw->device_id) {
5906 case IXGBE_DEV_ID_X550EM_A_1G_T:
5907 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
5908 if (!hw->phy.eee_speeds_supported)
5909 break;
5910 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE;
5911 if (!hw->phy.eee_speeds_advertised)
5912 break;
5913 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
5914 break;
5915 default:
5916 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE;
5917 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
5918 break;
5919 }
5920}
5921
9a799d71
AK		 5922/**
5923 * ixgbe_tx_timeout - Respond to a Tx Hang
5924 * @netdev: network interface device structure
5925 **/
5926static void ixgbe_tx_timeout(struct net_device *netdev)
5927{
5928 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5929
5930 /* Do the reset outside of interrupt context */
c83c6cbd 5931 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5932}
5933
8829009d
UK		 5934#ifdef CONFIG_IXGBE_DCB
5935static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
5936{
5937 struct ixgbe_hw *hw = &adapter->hw;
5938 struct tc_configuration *tc;
5939 int j;
5940
5941 switch (hw->mac.type) {
5942 case ixgbe_mac_82598EB:
5943 case ixgbe_mac_82599EB:
5944 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5945 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5946 break;
5947 case ixgbe_mac_X540:
5948 case ixgbe_mac_X550:
5949 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5950 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5951 break;
5952 case ixgbe_mac_X550EM_x:
5953 case ixgbe_mac_x550em_a:
5954 default:
5955 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
5956 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
5957 break;
5958 }
5959
5960 /* Configure DCB traffic classes */
5961 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5962 tc = &adapter->dcb_cfg.tc_config[j];
5963 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5964 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5965 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5966 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5967 tc->dcb_pfc = pfc_disabled;
5968 }
5969
5970 /* Initialize default user to priority mapping, UPx->TC0 */
5971 tc = &adapter->dcb_cfg.tc_config[0];
5972 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5973 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5974
5975 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5976 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5977 adapter->dcb_cfg.pfc_mode_enable = false;
5978 adapter->dcb_set_bitmap = 0x00;
5979 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
5980 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5981 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5982 sizeof(adapter->temp_dcb_cfg));
5983}
5984#endif
5985
9a799d71
AK		 5986/**
5987 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5988 * @adapter: board private structure to initialize
5989 *
5990 * ixgbe_sw_init initializes the Adapter private data structure.
5991 * Fields are initialized based on PCI device information and
5992 * OS network device settings (MTU size).
5993 **/
55570b6f
ET		 5994static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
5995 const struct ixgbe_info *ii)
9a799d71
AK		 5996{
5997 struct ixgbe_hw *hw = &adapter->hw;
5998 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5999 unsigned int rss, fdir;
cb6d0f5e 6000 u32 fwsm;
1cdaaf54 6001 int i;
021230d4 6002
c44ade9e
JB		 6003 /* PCI config space info */
6004
6005 hw->vendor_id = pdev->vendor;
6006 hw->device_id = pdev->device;
6007 hw->revision_id = pdev->revision;
6008 hw->subsystem_vendor_id = pdev->subsystem_vendor;
6009 hw->subsystem_device_id = pdev->subsystem_device;
6010
55570b6f
ET		 6011 /* get_invariants needs the device IDs */
6012 ii->get_invariants(hw);
6013
8fc3bb6d 6014 /* Set common capability flags and settings */
0f9b232b 6015 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 6016 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 6017 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 6018 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
6019 adapter->atr_sample_rate = 20;
d3cb9869
AD		 6020 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
6021 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 6022 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
6023#ifdef CONFIG_IXGBE_DCA
6024 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
6025#endif
8829009d
UK		 6026#ifdef CONFIG_IXGBE_DCB
6027 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
6028 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6029#endif
8fc3bb6d
ET		 6030#ifdef IXGBE_FCOE
6031 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
6032 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6033#ifdef CONFIG_IXGBE_DCB
6034 /* Default traffic class to use for FCoE */
6035 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
6036#endif /* CONFIG_IXGBE_DCB */
6037#endif /* IXGBE_FCOE */
6038
b82b17d9 6039 /* initialize static ixgbe jump table entries */
1cdaaf54
AN		 6040 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
6041 GFP_KERNEL);
6042 if (!adapter->jump_tables[0])
6043 return -ENOMEM;
6044 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
6045
6046 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
6047 adapter->jump_tables[i] = NULL;
b82b17d9 6048
5d7daa35
JK		 6049 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
6050 hw->mac.num_rar_entries,
6051 GFP_ATOMIC);
530fd82a
AD		 6052 if (!adapter->mac_table)
6053 return -ENOMEM;
5d7daa35 6054
3dfbfc7e
TN		 6055 if (ixgbe_init_rss_key(adapter))
6056 return -ENOMEM;
6057
8fc3bb6d 6058 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 6059 switch (hw->mac.type) {
6060 case ixgbe_mac_82598EB:
8fc3bb6d 6061 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 6062
bf069c97
DS		 6063 if (hw->device_id == IXGBE_DEV_ID_82598AT)
6064 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 6065
49c7ffbe 6066 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 6067 adapter->ring_feature[RING_F_FDIR].limit = 0;
6068 adapter->atr_sample_rate = 0;
6069 adapter->fdir_pballoc = 0;
6070#ifdef IXGBE_FCOE
6071 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6072 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6073#ifdef CONFIG_IXGBE_DCB
6074 adapter->fcoe.up = 0;
6075#endif /* IXGBE_DCB */
6076#endif /* IXGBE_FCOE */
6077 break;
6078 case ixgbe_mac_82599EB:
6079 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
6080 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 6081 break;
b93a2226 6082 case ixgbe_mac_X540:
9a900eca 6083 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 6084 if (fwsm & IXGBE_FWSM_TS_ENABLED)
6085 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 6086 break;
49425dfc 6087 case ixgbe_mac_x550em_a:
a21d0822 6088 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE;
b3eb4e18
MR		 6089 switch (hw->device_id) {
6090 case IXGBE_DEV_ID_X550EM_A_1G_T:
6091 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6092 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6093 break;
6094 default:
6095 break;
6096 }
a21d0822
ET		 6097 /* fall through */
6098 case ixgbe_mac_X550EM_x:
8829009d
UK		 6099#ifdef CONFIG_IXGBE_DCB
6100 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
6101#endif
6102#ifdef IXGBE_FCOE
6103 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6104#ifdef CONFIG_IXGBE_DCB
6105 adapter->fcoe.up = 0;
6106#endif /* IXGBE_DCB */
6107#endif /* IXGBE_FCOE */
6108 /* Fall Through */
9a75a1ac 6109 case ixgbe_mac_X550:
b3eb4e18
MR		 6110 if (hw->mac.type == ixgbe_mac_X550)
6111 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a75a1ac
DS		 6112#ifdef CONFIG_IXGBE_DCA
6113 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c 6114#endif
67359c3c 6115 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac 6116 break;
bd508178
AD		 6117 default:
6118 break;
f8212f97 6119 }
2f90b865 6120
7c8ae65a
AD		 6121#ifdef IXGBE_FCOE
6122 /* FCoE support exists, always init the FCoE lock */
6123 spin_lock_init(&adapter->fcoe.lock);
6124
6125#endif
1fc5f038
AD		 6126 /* n-tuple support exists, always init our spinlock */
6127 spin_lock_init(&adapter->fdir_perfect_lock);
6128
7a6b6f51 6129#ifdef CONFIG_IXGBE_DCB
8829009d 6130 ixgbe_init_dcb(adapter);
2f90b865 6131#endif
9a799d71
AK		 6132
6133 /* default flow control settings */
cd7664f6 6134 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 6135 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 6136 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 6137 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
6138 hw->fc.send_xon = true;
73d80953 6139 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 6140
99d74487 6141#ifdef CONFIG_PCI_IOV
170e8543
JK		 6142 if (max_vfs > 0)
6143 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
6144
99d74487 6145 /* assign number of SR-IOV VFs */
170e8543 6146 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 6147 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5c11f00d 6148 max_vfs = 0;
170e8543 6149 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
170e8543
JK		 6150 }
6151 }
6152#endif /* CONFIG_PCI_IOV */
99d74487 6153
30efa5a3 6154 /* enable itr by default in dynamic mode */
f7554a2b 6155 adapter->rx_itr_setting = 1;
f7554a2b 6156 adapter->tx_itr_setting = 1;
30efa5a3 6157
30efa5a3
JB		 6158 /* set default ring sizes */
6159 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
6160 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
6161
bd198058 6162 /* set default work limits */
59224555 6163 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 6164
9a799d71 6165 /* initialize eeprom parameters */
c44ade9e 6166 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 6167 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 6168 return -EIO;
6169 }
6170
2a47fa45
JF		 6171 /* PF holds first pool slot */
6172 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 6173 set_bit(__IXGBE_DOWN, &adapter->state);
6174
6175 return 0;
6176}
6177
6178/**
6179 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 6180 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 6181 *
6182 * Return 0 on success, negative on failure
6183 **/
b6ec895e 6184int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 6185{
b6ec895e 6186 struct device *dev = tx_ring->dev;
de88eeeb 6187 int orig_node = dev_to_node(dev);
ca8dfe25 6188 int ring_node = -1;
9a799d71
AK		 6189 int size;
6190
3a581073 6191 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 6192
6193 if (tx_ring->q_vector)
ca8dfe25 6194 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 6195
ffed21bc 6196 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node);
1a6c14a2 6197 if (!tx_ring->tx_buffer_info)
ffed21bc 6198 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 6199 if (!tx_ring->tx_buffer_info)
6200 goto err;
9a799d71
AK		 6201
6202 /* round up to nearest 4K */
12207e49 6203 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 6204 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 6205
ca8dfe25 6206 set_dev_node(dev, ring_node);
de88eeeb
AD		 6207 tx_ring->desc = dma_alloc_coherent(dev,
6208 tx_ring->size,
6209 &tx_ring->dma,
6210 GFP_KERNEL);
6211 set_dev_node(dev, orig_node);
6212 if (!tx_ring->desc)
6213 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
6214 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 6215 if (!tx_ring->desc)
6216 goto err;
9a799d71 6217
3a581073
JB		 6218 tx_ring->next_to_use = 0;
6219 tx_ring->next_to_clean = 0;
9a799d71 6220 return 0;
e01c31a5
JB		 6221
6222err:
6223 vfree(tx_ring->tx_buffer_info);
6224 tx_ring->tx_buffer_info = NULL;
b6ec895e 6225 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 6226 return -ENOMEM;
9a799d71
AK		 6227}
6228
69888674
AD		 6229/**
6230 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
6231 * @adapter: board private structure
6232 *
6233 * If this function returns with an error, then it's possible one or
6234 * more of the rings is populated (while the rest are not). It is the
6235 * callers duty to clean those orphaned rings.
6236 *
6237 * Return 0 on success, negative on failure
6238 **/
6239static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
6240{
33fdc82f 6241 int i, j = 0, err = 0;
69888674
AD		 6242
6243 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 6244 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 6245 if (!err)
6246 continue;
de3d5b94 6247
396e799c 6248 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 6249 goto err_setup_tx;
69888674 6250 }
33fdc82f
JF		 6251 for (j = 0; j < adapter->num_xdp_queues; j++) {
6252 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]);
6253 if (!err)
6254 continue;
6255
6256 e_err(probe, "Allocation for Tx Queue %u failed\n", j);
6257 goto err_setup_tx;
6258 }
69888674 6259
de3d5b94
AD		 6260 return 0;
6261err_setup_tx:
6262 /* rewind the index freeing the rings as we go */
33fdc82f
JF		 6263 while (j--)
6264 ixgbe_free_tx_resources(adapter->xdp_ring[j]);
de3d5b94
AD		 6265 while (i--)
6266 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 6267 return err;
6268}
6269
9a799d71
AK		 6270/**
6271 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 6272 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 6273 *
6274 * Returns 0 on success, negative on failure
6275 **/
92470808
JF		 6276int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
6277 struct ixgbe_ring *rx_ring)
9a799d71 6278{
b6ec895e 6279 struct device *dev = rx_ring->dev;
de88eeeb 6280 int orig_node = dev_to_node(dev);
ca8dfe25 6281 int ring_node = -1;
021230d4 6282 int size;
9a799d71 6283
3a581073 6284 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 6285
6286 if (rx_ring->q_vector)
ca8dfe25 6287 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 6288
ffed21bc 6289 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node);
1a6c14a2 6290 if (!rx_ring->rx_buffer_info)
ffed21bc 6291 rx_ring->rx_buffer_info = vmalloc(size);
b6ec895e
AD		 6292 if (!rx_ring->rx_buffer_info)
6293 goto err;
9a799d71 6294
9a799d71 6295 /* Round up to nearest 4K */
3a581073
JB		 6296 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
6297 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 6298
ca8dfe25 6299 set_dev_node(dev, ring_node);
de88eeeb
AD		 6300 rx_ring->desc = dma_alloc_coherent(dev,
6301 rx_ring->size,
6302 &rx_ring->dma,
6303 GFP_KERNEL);
6304 set_dev_node(dev, orig_node);
6305 if (!rx_ring->desc)
6306 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
6307 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 6308 if (!rx_ring->desc)
6309 goto err;
9a799d71 6310
3a581073
JB		 6311 rx_ring->next_to_clean = 0;
6312 rx_ring->next_to_use = 0;
9a799d71 6313
92470808
JF		 6314 rx_ring->xdp_prog = adapter->xdp_prog;
6315
9a799d71 6316 return 0;
b6ec895e
AD		 6317err:
6318 vfree(rx_ring->rx_buffer_info);
6319 rx_ring->rx_buffer_info = NULL;
6320 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 6321 return -ENOMEM;
9a799d71
AK		 6322}
6323
69888674
AD		 6324/**
6325 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
6326 * @adapter: board private structure
6327 *
6328 * If this function returns with an error, then it's possible one or
6329 * more of the rings is populated (while the rest are not). It is the
6330 * callers duty to clean those orphaned rings.
6331 *
6332 * Return 0 on success, negative on failure
6333 **/
69888674
AD		 6334static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
6335{
6336 int i, err = 0;
6337
6338 for (i = 0; i < adapter->num_rx_queues; i++) {
92470808 6339 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 6340 if (!err)
6341 continue;
de3d5b94 6342
396e799c 6343 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 6344 goto err_setup_rx;
69888674
AD		 6345 }
6346
7c8ae65a
AD		 6347#ifdef IXGBE_FCOE
6348 err = ixgbe_setup_fcoe_ddp_resources(adapter);
6349 if (!err)
6350#endif
6351 return 0;
de3d5b94
AD		 6352err_setup_rx:
6353 /* rewind the index freeing the rings as we go */
6354 while (i--)
6355 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 6356 return err;
6357}
6358
9a799d71
AK		 6359/**
6360 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 6361 * @tx_ring: Tx descriptor ring for a specific queue
6362 *
6363 * Free all transmit software resources
6364 **/
b6ec895e 6365void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 6366{
b6ec895e 6367 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 6368
6369 vfree(tx_ring->tx_buffer_info);
6370 tx_ring->tx_buffer_info = NULL;
6371
b6ec895e
AD		 6372 /* if not set, then don't free */
6373 if (!tx_ring->desc)
6374 return;
6375
6376 dma_free_coherent(tx_ring->dev, tx_ring->size,
6377 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 6378
6379 tx_ring->desc = NULL;
6380}
6381
6382/**
6383 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
6384 * @adapter: board private structure
6385 *
6386 * Free all transmit software resources
6387 **/
6388static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6389{
6390 int i;
6391
6392 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 6393 if (adapter->tx_ring[i]->desc)
b6ec895e 6394 ixgbe_free_tx_resources(adapter->tx_ring[i]);
33fdc82f
JF		 6395 for (i = 0; i < adapter->num_xdp_queues; i++)
6396 if (adapter->xdp_ring[i]->desc)
6397 ixgbe_free_tx_resources(adapter->xdp_ring[i]);
9a799d71
AK		 6398}
6399
6400/**
b4617240 6401 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 6402 * @rx_ring: ring to clean the resources from
6403 *
6404 * Free all receive software resources
6405 **/
b6ec895e 6406void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 6407{
b6ec895e 6408 ixgbe_clean_rx_ring(rx_ring);
9a799d71 6409
92470808 6410 rx_ring->xdp_prog = NULL;
9a799d71
AK		 6411 vfree(rx_ring->rx_buffer_info);
6412 rx_ring->rx_buffer_info = NULL;
6413
b6ec895e
AD		 6414 /* if not set, then don't free */
6415 if (!rx_ring->desc)
6416 return;
6417
6418 dma_free_coherent(rx_ring->dev, rx_ring->size,
6419 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 6420
6421 rx_ring->desc = NULL;
6422}
6423
6424/**
6425 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6426 * @adapter: board private structure
6427 *
6428 * Free all receive software resources
6429 **/
6430static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6431{
6432 int i;
6433
7c8ae65a
AD		 6434#ifdef IXGBE_FCOE
6435 ixgbe_free_fcoe_ddp_resources(adapter);
6436
6437#endif
9a799d71 6438 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 6439 if (adapter->rx_ring[i]->desc)
b6ec895e 6440 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 6441}
6442
9a799d71
AK		 6443/**
6444 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6445 * @netdev: network interface device structure
6446 * @new_mtu: new value for maximum frame size
6447 *
6448 * Returns 0 on success, negative on failure
6449 **/
6450static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6451{
6452 struct ixgbe_adapter *adapter = netdev_priv(netdev);
655309e9
AD		 6453
6454 /*
872844dd
AD		 6455 * For 82599EB we cannot allow legacy VFs to enable their receive
6456 * paths when MTU greater than 1500 is configured. So display a
6457 * warning that legacy VFs will be disabled.
655309e9
AD		 6458 */
6459 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6460 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
91c527a5 6461 (new_mtu > ETH_DATA_LEN))
872844dd 6462 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 6463
396e799c 6464 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 6465
021230d4 6466 /* must set new MTU before calling down or up */
9a799d71
AK		 6467 netdev->mtu = new_mtu;
6468
d4f80882
AV		 6469 if (netif_running(netdev))
6470 ixgbe_reinit_locked(adapter);
9a799d71
AK		 6471
6472 return 0;
6473}
6474
6475/**
6476 * ixgbe_open - Called when a network interface is made active
6477 * @netdev: network interface device structure
6478 *
6479 * Returns 0 on success, negative value on failure
6480 *
6481 * The open entry point is called when a network interface is made
6482 * active by the system (IFF_UP). At this point all resources needed
6483 * for transmit and receive operations are allocated, the interrupt
6484 * handler is registered with the OS, the watchdog timer is started,
6485 * and the stack is notified that the interface is ready.
6486 **/
6c211fe1 6487int ixgbe_open(struct net_device *netdev)
9a799d71
AK		 6488{
6489 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 6490 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 6491 int err, queues;
4bebfaa5
AK		 6492
6493 /* disallow open during test */
6494 if (test_bit(__IXGBE_TESTING, &adapter->state))
6495 return -EBUSY;
9a799d71 6496
54386467
JB		 6497 netif_carrier_off(netdev);
6498
9a799d71
AK		 6499 /* allocate transmit descriptors */
6500 err = ixgbe_setup_all_tx_resources(adapter);
6501 if (err)
6502 goto err_setup_tx;
6503
9a799d71
AK		 6504 /* allocate receive descriptors */
6505 err = ixgbe_setup_all_rx_resources(adapter);
6506 if (err)
6507 goto err_setup_rx;
6508
6509 ixgbe_configure(adapter);
6510
021230d4 6511 err = ixgbe_request_irq(adapter);
9a799d71
AK		 6512 if (err)
6513 goto err_req_irq;
6514
ac802f5d 6515 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 6516 if (adapter->num_rx_pools > 1)
6517 queues = adapter->num_rx_queues_per_pool;
6518 else
6519 queues = adapter->num_tx_queues;
6520
6521 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 6522 if (err)
6523 goto err_set_queues;
6524
2a47fa45
JF		 6525 if (adapter->num_rx_pools > 1 &&
6526 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6527 queues = IXGBE_MAX_L2A_QUEUES;
6528 else
6529 queues = adapter->num_rx_queues;
6530 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 6531 if (err)
6532 goto err_set_queues;
6533
1a71ab24 6534 ixgbe_ptp_init(adapter);
1a71ab24 6535
c7ccde0f 6536 ixgbe_up_complete(adapter);
9a799d71 6537
a21d0822 6538 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK);
b3a49557 6539 udp_tunnel_get_rx_info(netdev);
67359c3c 6540
9a799d71
AK		 6541 return 0;
6542
ac802f5d
AD		 6543err_set_queues:
6544 ixgbe_free_irq(adapter);
9a799d71 6545err_req_irq:
a20a1199 6546 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 6547 if (hw->phy.ops.set_phy_power && !adapter->wol)
6548 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 6549err_setup_rx:
a20a1199 6550 ixgbe_free_all_tx_resources(adapter);
de3d5b94 6551err_setup_tx:
9a799d71
AK		 6552 ixgbe_reset(adapter);
6553
6554 return err;
6555}
6556
a0cccce2
JK		 6557static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6558{
6559 ixgbe_ptp_suspend(adapter);
6560
6ac74394
DS		 6561 if (adapter->hw.phy.ops.enter_lplu) {
6562 adapter->hw.phy.reset_disable = true;
6563 ixgbe_down(adapter);
6564 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6565 adapter->hw.phy.reset_disable = false;
6566 } else {
6567 ixgbe_down(adapter);
6568 }
6569
a0cccce2
JK		 6570 ixgbe_free_irq(adapter);
6571
6572 ixgbe_free_all_tx_resources(adapter);
6573 ixgbe_free_all_rx_resources(adapter);
6574}
6575
9a799d71
AK		 6576/**
6577 * ixgbe_close - Disables a network interface
6578 * @netdev: network interface device structure
6579 *
6580 * Returns 0, this is not allowed to fail
6581 *
6582 * The close entry point is called when an interface is de-activated
6583 * by the OS. The hardware is still under the drivers control, but
6584 * needs to be disabled. A global MAC reset is issued to stop the
6585 * hardware, and all transmit and receive resources are freed.
6586 **/
6c211fe1 6587int ixgbe_close(struct net_device *netdev)
9a799d71
AK		 6588{
6589 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 6590
1a71ab24 6591 ixgbe_ptp_stop(adapter);
1a71ab24 6592
f7f37e7f
ET		 6593 if (netif_device_present(netdev))
6594 ixgbe_close_suspend(adapter);
9a799d71 6595
e4911d57
AD		 6596 ixgbe_fdir_filter_exit(adapter);
6597
5eba3699 6598 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6599
6600 return 0;
6601}
6602
b3c8b4ba
AD		 6603#ifdef CONFIG_PM
6604static int ixgbe_resume(struct pci_dev *pdev)
6605{
c60fbb00
AD		 6606 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6607 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 6608 u32 err;
6609
0391bbe3 6610 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 6611 pci_set_power_state(pdev, PCI_D0);
6612 pci_restore_state(pdev);
656ab817
DS		 6613 /*
6614 * pci_restore_state clears dev->state_saved so call
6615 * pci_save_state to restore it.
6616 */
6617 pci_save_state(pdev);
9ce77666 6618
6619 err = pci_enable_device_mem(pdev);
b3c8b4ba 6620 if (err) {
849c4542 6621 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 6622 return err;
6623 }
4e857c58 6624 smp_mb__before_atomic();
41c62843 6625 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 6626 pci_set_master(pdev);
6627
dd4d8ca6 6628 pci_wake_from_d3(pdev, false);
b3c8b4ba 6629
b3c8b4ba
AD		 6630 ixgbe_reset(adapter);
6631
495dce12
WJP		 6632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6633
ac802f5d
AD		 6634 rtnl_lock();
6635 err = ixgbe_init_interrupt_scheme(adapter);
6636 if (!err && netif_running(netdev))
c60fbb00 6637 err = ixgbe_open(netdev);
ac802f5d 6638
ac802f5d 6639
f7f37e7f
ET		 6640 if (!err)
6641 netif_device_attach(netdev);
6642 rtnl_unlock();
b3c8b4ba 6643
f7f37e7f 6644 return err;
b3c8b4ba 6645}
b3c8b4ba 6646#endif /* CONFIG_PM */
9d8d05ae
RW		 6647
6648static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 6649{
c60fbb00
AD		 6650 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6651 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 6652 struct ixgbe_hw *hw = &adapter->hw;
6653 u32 ctrl, fctrl;
6654 u32 wufc = adapter->wol;
b3c8b4ba
AD		 6655#ifdef CONFIG_PM
6656 int retval = 0;
6657#endif
6658
f7f37e7f 6659 rtnl_lock();
b3c8b4ba
AD		 6660 netif_device_detach(netdev);
6661
a0cccce2
JK		 6662 if (netif_running(netdev))
6663 ixgbe_close_suspend(adapter);
b3c8b4ba 6664
5f5ae6fc 6665 ixgbe_clear_interrupt_scheme(adapter);
f7f37e7f 6666 rtnl_unlock();
5f5ae6fc 6667
b3c8b4ba
AD		 6668#ifdef CONFIG_PM
6669 retval = pci_save_state(pdev);
6670 if (retval)
6671 return retval;
4df10466 6672
b3c8b4ba 6673#endif
f4f1040a
JK		 6674 if (hw->mac.ops.stop_link_on_d3)
6675 hw->mac.ops.stop_link_on_d3(hw);
6676
e8e26350
PW		 6677 if (wufc) {
6678 ixgbe_set_rx_mode(netdev);
b3c8b4ba 6679
ec74a471
ET		 6680 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6681 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 6682 hw->mac.ops.enable_tx_laser(hw);
6683
e8e26350
PW		 6684 /* turn on all-multi mode if wake on multicast is enabled */
6685 if (wufc & IXGBE_WUFC_MC) {
6686 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6687 fctrl |= IXGBE_FCTRL_MPE;
6688 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6689 }
6690
6691 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6692 ctrl |= IXGBE_CTRL_GIO_DIS;
6693 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6694
6695 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6696 } else {
6697 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6698 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6699 }
6700
bd508178
AD		 6701 switch (hw->mac.type) {
6702 case ixgbe_mac_82598EB:
dd4d8ca6 6703 pci_wake_from_d3(pdev, false);
bd508178
AD		 6704 break;
6705 case ixgbe_mac_82599EB:
b93a2226 6706 case ixgbe_mac_X540:
9a75a1ac
DS		 6707 case ixgbe_mac_X550:
6708 case ixgbe_mac_X550EM_x:
49425dfc 6709 case ixgbe_mac_x550em_a:
bd508178
AD		 6710 pci_wake_from_d3(pdev, !!wufc);
6711 break;
6712 default:
6713 break;
6714 }
b3c8b4ba 6715
9d8d05ae 6716 *enable_wake = !!wufc;
961fac88
DS		 6717 if (hw->phy.ops.set_phy_power && !*enable_wake)
6718 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6719
b3c8b4ba
AD		 6720 ixgbe_release_hw_control(adapter);
6721
41c62843
MR		 6722 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6723 pci_disable_device(pdev);
b3c8b4ba 6724
9d8d05ae
RW		 6725 return 0;
6726}
6727
6728#ifdef CONFIG_PM
6729static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6730{
6731 int retval;
6732 bool wake;
6733
6734 retval = __ixgbe_shutdown(pdev, &wake);
6735 if (retval)
6736 return retval;
6737
6738 if (wake) {
6739 pci_prepare_to_sleep(pdev);
6740 } else {
6741 pci_wake_from_d3(pdev, false);
6742 pci_set_power_state(pdev, PCI_D3hot);
6743 }
b3c8b4ba
AD		 6744
6745 return 0;
6746}
9d8d05ae 6747#endif /* CONFIG_PM */
b3c8b4ba
AD		 6748
6749static void ixgbe_shutdown(struct pci_dev *pdev)
6750{
9d8d05ae
RW		 6751 bool wake;
6752
6753 __ixgbe_shutdown(pdev, &wake);
6754
6755 if (system_state == SYSTEM_POWER_OFF) {
6756 pci_wake_from_d3(pdev, wake);
6757 pci_set_power_state(pdev, PCI_D3hot);
6758 }
b3c8b4ba
AD		 6759}
6760
9a799d71
AK		 6761/**
6762 * ixgbe_update_stats - Update the board statistics counters.
6763 * @adapter: board private structure
6764 **/
6765void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6766{
2d86f139 6767 struct net_device *netdev = adapter->netdev;
9a799d71 6768 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6769 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6770 u64 total_mpc = 0;
6771 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6772 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6773 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6774 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6775
d08935c2
DS		 6776 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6777 test_bit(__IXGBE_RESETTING, &adapter->state))
6778 return;
6779
94b982b2 6780 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6781 u64 rsc_count = 0;
94b982b2 6782 u64 rsc_flush = 0;
94b982b2 6783 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6784 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6785 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6786 }
6787 adapter->rsc_total_count = rsc_count;
6788 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6789 }
6790
5b7da515
AD		 6791 for (i = 0; i < adapter->num_rx_queues; i++) {
6792 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6793 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6794 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6795 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6796 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6797 bytes += rx_ring->stats.bytes;
6798 packets += rx_ring->stats.packets;
6799 }
6800 adapter->non_eop_descs = non_eop_descs;
6801 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6802 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6803 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6804 netdev->stats.rx_bytes = bytes;
6805 netdev->stats.rx_packets = packets;
6806
6807 bytes = 0;
6808 packets = 0;
7ca3bc58 6809 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6810 for (i = 0; i < adapter->num_tx_queues; i++) {
6811 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6812 restart_queue += tx_ring->tx_stats.restart_queue;
6813 tx_busy += tx_ring->tx_stats.tx_busy;
6814 bytes += tx_ring->stats.bytes;
6815 packets += tx_ring->stats.packets;
6816 }
33fdc82f
JF		 6817 for (i = 0; i < adapter->num_xdp_queues; i++) {
6818 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
6819
6820 restart_queue += xdp_ring->tx_stats.restart_queue;
6821 tx_busy += xdp_ring->tx_stats.tx_busy;
6822 bytes += xdp_ring->stats.bytes;
6823 packets += xdp_ring->stats.packets;
6824 }
eb985f09 6825 adapter->restart_queue = restart_queue;
5b7da515
AD		 6826 adapter->tx_busy = tx_busy;
6827 netdev->stats.tx_bytes = bytes;
6828 netdev->stats.tx_packets = packets;
7ca3bc58 6829
7ca647bd 6830 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6831
6832 /* 8 register reads */
6f11eef7
AV		 6833 for (i = 0; i < 8; i++) {
6834 /* for packet buffers not used, the register should read 0 */
6835 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6836 missed_rx += mpc;
7ca647bd
JP		 6837 hwstats->mpc[i] += mpc;
6838 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6839 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6840 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6841 switch (hw->mac.type) {
6842 case ixgbe_mac_82598EB:
1a70db4b
ET		 6843 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6844 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6845 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6846 hwstats->pxonrxc[i] +=
6847 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6848 break;
6849 case ixgbe_mac_82599EB:
b93a2226 6850 case ixgbe_mac_X540:
9a75a1ac
DS		 6851 case ixgbe_mac_X550:
6852 case ixgbe_mac_X550EM_x:
49425dfc 6853 case ixgbe_mac_x550em_a:
bd508178
AD		 6854 hwstats->pxonrxc[i] +=
6855 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6856 break;
6857 default:
6858 break;
e8e26350 6859 }
6f11eef7 6860 }
1a70db4b
ET		 6861
6862 /*16 register reads */
6863 for (i = 0; i < 16; i++) {
6864 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6865 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6866 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6867 (hw->mac.type == ixgbe_mac_X540) ||
6868 (hw->mac.type == ixgbe_mac_X550) ||
49425dfc
MR		 6869 (hw->mac.type == ixgbe_mac_X550EM_x) ||
6870 (hw->mac.type == ixgbe_mac_x550em_a)) {
1a70db4b
ET		 6871 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6872 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6873 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6874 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6875 }
6876 }
6877
7ca647bd 6878 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6879 /* work around hardware counting issue */
7ca647bd 6880 hwstats->gprc -= missed_rx;
6f11eef7 6881
c84d324c
JF		 6882 ixgbe_update_xoff_received(adapter);
6883
6f11eef7 6884 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6885 switch (hw->mac.type) {
6886 case ixgbe_mac_82598EB:
6887 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6888 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6889 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6890 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6891 break;
b93a2226 6892 case ixgbe_mac_X540:
9a75a1ac
DS		 6893 case ixgbe_mac_X550:
6894 case ixgbe_mac_X550EM_x:
49425dfc 6895 case ixgbe_mac_x550em_a:
9a75a1ac 6896 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6897 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6898 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6899 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6900 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
93df9465 6901 /* fall through */
58f6bcf9 6902 case ixgbe_mac_82599EB:
a4d4f629
AD		 6903 for (i = 0; i < 16; i++)
6904 adapter->hw_rx_no_dma_resources +=
6905 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6906 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6907 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6908 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6909 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6910 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6911 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6912 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6913 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6914 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6915#ifdef IXGBE_FCOE
7ca647bd
JP		 6916 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6917 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6918 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6919 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6920 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6921 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6922 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6923 if (adapter->fcoe.ddp_pool) {
6924 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6925 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6926 unsigned int cpu;
6927 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6928 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6929 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6930 noddp += ddp_pool->noddp;
6931 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6932 }
5a1ee270
AD		 6933 hwstats->fcoe_noddp = noddp;
6934 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6935 }
6d45522c 6936#endif /* IXGBE_FCOE */
bd508178
AD		 6937 break;
6938 default:
6939 break;
e8e26350 6940 }
9a799d71 6941 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6942 hwstats->bprc += bprc;
6943 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6944 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6945 hwstats->mprc -= bprc;
6946 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6947 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6948 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6949 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6950 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6951 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6952 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6953 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6954 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6955 hwstats->lxontxc += lxon;
6f11eef7 6956 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6957 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6958 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6959 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6960 /*
6961 * 82598 errata - tx of flow control packets is included in tx counters
6962 */
6963 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6964 hwstats->gptc -= xon_off_tot;
6965 hwstats->mptc -= xon_off_tot;
6966 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6967 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6968 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6969 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6970 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6971 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6972 hwstats->ptc64 -= xon_off_tot;
6973 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6974 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6975 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6976 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6977 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6978 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6979
6980 /* Fill out the OS statistics structure */
7ca647bd 6981 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6982
6983 /* Rx Errors */
7ca647bd 6984 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6985 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6986 netdev->stats.rx_length_errors = hwstats->rlec;
6987 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6988 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6989}
6990
6991/**
d034acf1 6992 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6993 * @adapter: pointer to the device adapter structure
9a799d71 6994 **/
d034acf1 6995static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6996{
cf8280ee 6997 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6998 int i;
cf8280ee 6999
d034acf1
AD		 7000 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
7001 return;
7002
7003 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 7004
d034acf1 7005 /* if interface is down do nothing */
fe49f04a 7006 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 7007 return;
7008
7009 /* do nothing if we are not using signature filters */
7010 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
7011 return;
7012
7013 adapter->fdir_overflow++;
7014
93c52dd0
AD		 7015 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
7016 for (i = 0; i < adapter->num_tx_queues; i++)
7017 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 7018 &(adapter->tx_ring[i]->state));
33fdc82f
JF		 7019 for (i = 0; i < adapter->num_xdp_queues; i++)
7020 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7021 &adapter->xdp_ring[i]->state);
d034acf1
AD		 7022 /* re-enable flow director interrupts */
7023 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 7024 } else {
7025 e_err(probe, "failed to finish FDIR re-initialization, "
7026 "ignored adding FDIR ATR filters\n");
7027 }
93c52dd0
AD		 7028}
7029
7030/**
7031 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 7032 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 7033 *
7034 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 7035 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 7036 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 7037 * determine if a hang has occurred.
93c52dd0
AD		 7038 */
7039static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 7040{
cf8280ee 7041 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 7042 u64 eics = 0;
7043 int i;
cf8280ee 7044
09f40aed 7045 /* If we're down, removing or resetting, just bail */
93c52dd0 7046 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7047 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 7048 test_bit(__IXGBE_RESETTING, &adapter->state))
7049 return;
22d5a71b 7050
93c52dd0
AD		 7051 /* Force detection of hung controller */
7052 if (netif_carrier_ok(adapter->netdev)) {
7053 for (i = 0; i < adapter->num_tx_queues; i++)
7054 set_check_for_tx_hang(adapter->tx_ring[i]);
33fdc82f
JF		 7055 for (i = 0; i < adapter->num_xdp_queues; i++)
7056 set_check_for_tx_hang(adapter->xdp_ring[i]);
93c52dd0 7057 }
22d5a71b 7058
fe49f04a
AD		 7059 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7060 /*
7061 * for legacy and MSI interrupts don't set any bits
7062 * that are enabled for EIAM, because this operation
7063 * would set *both* EIMS and EICS for any bit in EIAM
7064 */
7065 IXGBE_WRITE_REG(hw, IXGBE_EICS,
7066 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 7067 } else {
7068 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 7069 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 7070 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 7071 if (qv->rx.ring || qv->tx.ring)
b4f47a48 7072 eics |= BIT_ULL(i);
93c52dd0 7073 }
cf8280ee 7074 }
9a799d71 7075
93c52dd0 7076 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 7077 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 7078}
7079
e8e26350 7080/**
93c52dd0 7081 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 7082 * @adapter: pointer to the device adapter structure
7083 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 7084 **/
93c52dd0 7085static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 7086{
e8e26350 7087 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 7088 u32 link_speed = adapter->link_speed;
7089 bool link_up = adapter->link_up;
041441d0 7090 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 7091
93c52dd0
AD		 7092 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
7093 return;
7094
7095 if (hw->mac.ops.check_link) {
7096 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 7097 } else {
93c52dd0
AD		 7098 /* always assume link is up, if no check link function */
7099 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
7100 link_up = true;
c4cf55e5 7101 }
041441d0
AD		 7102
7103 if (adapter->ixgbe_ieee_pfc)
7104 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
7105
3ebe8fde 7106 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 7107 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 7108 ixgbe_set_rx_drop_en(adapter);
7109 }
93c52dd0
AD		 7110
7111 if (link_up ||
7112 time_after(jiffies, (adapter->link_check_timeout +
7113 IXGBE_TRY_LINK_TIMEOUT))) {
7114 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
7115 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
7116 IXGBE_WRITE_FLUSH(hw);
7117 }
7118
7119 adapter->link_up = link_up;
7120 adapter->link_speed = link_speed;
e8e26350
PW		 7121}
7122
107d3018
AD		 7123static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
7124{
7125#ifdef CONFIG_IXGBE_DCB
7126 struct net_device *netdev = adapter->netdev;
7127 struct dcb_app app = {
7128 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
7129 .protocol = 0,
7130 };
7131 u8 up = 0;
7132
7133 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
7134 up = dcb_ieee_getapp_mask(netdev, &app);
7135
7136 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
7137#endif
7138}
7139
1cd127fc
DA		 7140static int ixgbe_enable_macvlan(struct net_device *upper, void *data)
7141{
7142 if (netif_is_macvlan(upper)) {
7143 struct macvlan_dev *vlan = netdev_priv(upper);
7144
7145 if (vlan->fwd_priv)
7146 netif_tx_wake_all_queues(upper);
7147 }
7148
7149 return 0;
7150}
7151
e8e26350 7152/**
93c52dd0
AD		 7153 * ixgbe_watchdog_link_is_up - update netif_carrier status and
7154 * print link up message
49ce9c2c 7155 * @adapter: pointer to the device adapter structure
e8e26350 7156 **/
93c52dd0 7157static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 7158{
93c52dd0 7159 struct net_device *netdev = adapter->netdev;
e8e26350 7160 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0 7161 u32 link_speed = adapter->link_speed;
454adb00 7162 const char *speed_str;
93c52dd0 7163 bool flow_rx, flow_tx;
e8e26350 7164
93c52dd0
AD		 7165 /* only continue if link was previously down */
7166 if (netif_carrier_ok(netdev))
a985b6c3 7167 return;
63d6e1d8 7168
93c52dd0 7169 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 7170
93c52dd0
AD		 7171 switch (hw->mac.type) {
7172 case ixgbe_mac_82598EB: {
7173 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
7174 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
7175 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
7176 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
7177 }
7178 break;
7179 case ixgbe_mac_X540:
9a75a1ac
DS		 7180 case ixgbe_mac_X550:
7181 case ixgbe_mac_X550EM_x:
49425dfc 7182 case ixgbe_mac_x550em_a:
93c52dd0
AD		 7183 case ixgbe_mac_82599EB: {
7184 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
7185 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
7186 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
7187 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
7188 }
7189 break;
7190 default:
7191 flow_tx = false;
7192 flow_rx = false;
7193 break;
e8e26350 7194 }
3a6a4eda 7195
6cb562d6
JK		 7196 adapter->last_rx_ptp_check = jiffies;
7197
8fecf67c 7198 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 7199 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 7200
454adb00
MR		 7201 switch (link_speed) {
7202 case IXGBE_LINK_SPEED_10GB_FULL:
7203 speed_str = "10 Gbps";
7204 break;
7205 case IXGBE_LINK_SPEED_2_5GB_FULL:
7206 speed_str = "2.5 Gbps";
7207 break;
7208 case IXGBE_LINK_SPEED_1GB_FULL:
7209 speed_str = "1 Gbps";
7210 break;
7211 case IXGBE_LINK_SPEED_100_FULL:
7212 speed_str = "100 Mbps";
7213 break;
b3eb4e18
MR		 7214 case IXGBE_LINK_SPEED_10_FULL:
7215 speed_str = "10 Mbps";
7216 break;
454adb00
MR		 7217 default:
7218 speed_str = "unknown speed";
7219 break;
7220 }
7221 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 7222 ((flow_rx && flow_tx) ? "RX/TX" :
7223 (flow_rx ? "RX" :
7224 (flow_tx ? "TX" : "None"))));
e8e26350 7225
93c52dd0 7226 netif_carrier_on(netdev);
93c52dd0 7227 ixgbe_check_vf_rate_limit(adapter);
befa2af7 7228
cdc04dcc
ET		 7229 /* enable transmits */
7230 netif_tx_wake_all_queues(adapter->netdev);
7231
7232 /* enable any upper devices */
7233 rtnl_lock();
1cd127fc
DA		 7234 netdev_walk_all_upper_dev_rcu(adapter->netdev,
7235 ixgbe_enable_macvlan, NULL);
cdc04dcc
ET		 7236 rtnl_unlock();
7237
107d3018
AD		 7238 /* update the default user priority for VFs */
7239 ixgbe_update_default_up(adapter);
7240
befa2af7
AD		 7241 /* ping all the active vfs to let them know link has changed */
7242 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 7243}
7244
c4cf55e5 7245/**
93c52dd0
AD		 7246 * ixgbe_watchdog_link_is_down - update netif_carrier status and
7247 * print link down message
49ce9c2c 7248 * @adapter: pointer to the adapter structure
c4cf55e5 7249 **/
581330ba 7250static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 7251{
cf8280ee 7252 struct net_device *netdev = adapter->netdev;
c4cf55e5 7253 struct ixgbe_hw *hw = &adapter->hw;
10eec955 7254
93c52dd0
AD		 7255 adapter->link_up = false;
7256 adapter->link_speed = 0;
cf8280ee 7257
93c52dd0
AD		 7258 /* only continue if link was up previously */
7259 if (!netif_carrier_ok(netdev))
7260 return;
264857b8 7261
93c52dd0
AD		 7262 /* poll for SFP+ cable when link is down */
7263 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
7264 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 7265
8fecf67c 7266 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 7267 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 7268
93c52dd0
AD		 7269 e_info(drv, "NIC Link is Down\n");
7270 netif_carrier_off(netdev);
befa2af7
AD		 7271
7272 /* ping all the active vfs to let them know link has changed */
7273 ixgbe_ping_all_vfs(adapter);
93c52dd0 7274}
e8e26350 7275
07923c17
ET		 7276static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
7277{
7278 int i;
7279
7280 for (i = 0; i < adapter->num_tx_queues; i++) {
7281 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
7282
7283 if (tx_ring->next_to_use != tx_ring->next_to_clean)
7284 return true;
7285 }
7286
33fdc82f
JF		 7287 for (i = 0; i < adapter->num_xdp_queues; i++) {
7288 struct ixgbe_ring *ring = adapter->xdp_ring[i];
7289
7290 if (ring->next_to_use != ring->next_to_clean)
7291 return true;
7292 }
7293
07923c17
ET		 7294 return false;
7295}
7296
7297static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
7298{
7299 struct ixgbe_hw *hw = &adapter->hw;
7300 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
7301 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
7302
7303 int i, j;
7304
7305 if (!adapter->num_vfs)
7306 return false;
7307
9a75a1ac
DS		 7308 /* resetting the PF is only needed for MAC before X550 */
7309 if (hw->mac.type >= ixgbe_mac_X550)
7310 return false;
7311
07923c17
ET		 7312 for (i = 0; i < adapter->num_vfs; i++) {
7313 for (j = 0; j < q_per_pool; j++) {
7314 u32 h, t;
7315
7316 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
7317 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
7318
7319 if (h != t)
7320 return true;
7321 }
7322 }
7323
7324 return false;
7325}
7326
93c52dd0
AD		 7327/**
7328 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 7329 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 7330 **/
7331static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
7332{
93c52dd0 7333 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 7334 if (ixgbe_ring_tx_pending(adapter) ||
7335 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 7336 /* We've lost link, so the controller stops DMA,
7337 * but we've got queued Tx work that's never going
7338 * to get done, so reset controller to flush Tx.
7339 * (Do the reset outside of interrupt context).
7340 */
12ff3f3b 7341 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
57ca2a4f 7342 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
bc59fcda 7343 }
c4cf55e5 7344 }
c4cf55e5
PWJ		 7345}
7346
9079e416 7347#ifdef CONFIG_PCI_IOV
9079e416
ET		 7348static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
7349{
7350 struct ixgbe_hw *hw = &adapter->hw;
7351 struct pci_dev *pdev = adapter->pdev;
988d1307 7352 unsigned int vf;
9079e416 7353 u32 gpc;
9079e416
ET		 7354
7355 if (!(netif_carrier_ok(adapter->netdev)))
7356 return;
7357
7358 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
7359 if (gpc) /* If incrementing then no need for the check below */
7360 return;
7361 /* Check to see if a bad DMA write target from an errant or
7362 * malicious VF has caused a PCIe error. If so then we can
7363 * issue a VFLR to the offending VF(s) and then resume without
7364 * requesting a full slot reset.
7365 */
7366
7367 if (!pdev)
7368 return;
7369
9079e416 7370 /* check status reg for all VFs owned by this PF */
988d1307
MR		 7371 for (vf = 0; vf < adapter->num_vfs; ++vf) {
7372 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
7373 u16 status_reg;
9079e416 7374
988d1307
MR		 7375 if (!vfdev)
7376 continue;
7377 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
7378 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
7379 status_reg & PCI_STATUS_REC_MASTER_ABORT)
63af8f7a 7380 pcie_flr(vfdev);
9079e416
ET		 7381 }
7382}
7383
a985b6c3
GR		 7384static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
7385{
7386 u32 ssvpc;
7387
0584d999
GR		 7388 /* Do not perform spoof check for 82598 or if not in IOV mode */
7389 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7390 adapter->num_vfs == 0)
a985b6c3
GR		 7391 return;
7392
7393 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
7394
7395 /*
7396 * ssvpc register is cleared on read, if zero then no
7397 * spoofed packets in the last interval.
7398 */
7399 if (!ssvpc)
7400 return;
7401
d6ea0754 7402 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 7403}
9079e416
ET		 7404#else
7405static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7406{
7407}
7408
7409static void
7410ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7411{
7412}
7413#endif /* CONFIG_PCI_IOV */
7414
a985b6c3 7415
93c52dd0
AD		 7416/**
7417 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 7418 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 7419 **/
7420static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7421{
09f40aed 7422 /* if interface is down, removing or resetting, do nothing */
7edebf9a 7423 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7424 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 7425 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 7426 return;
7427
7428 ixgbe_watchdog_update_link(adapter);
7429
7430 if (adapter->link_up)
7431 ixgbe_watchdog_link_is_up(adapter);
7432 else
7433 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 7434
9079e416 7435 ixgbe_check_for_bad_vf(adapter);
a985b6c3 7436 ixgbe_spoof_check(adapter);
9a799d71 7437 ixgbe_update_stats(adapter);
93c52dd0
AD		 7438
7439 ixgbe_watchdog_flush_tx(adapter);
9a799d71 7440}
10eec955 7441
cf8280ee 7442/**
7086400d 7443 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 7444 * @adapter: the ixgbe adapter structure
cf8280ee 7445 **/
7086400d 7446static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 7447{
cf8280ee 7448 struct ixgbe_hw *hw = &adapter->hw;
7086400d 7449 s32 err;
cf8280ee 7450
7086400d
AD		 7451 /* not searching for SFP so there is nothing to do here */
7452 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7453 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7454 return;
10eec955 7455
58e7cd24
MR		 7456 if (adapter->sfp_poll_time &&
7457 time_after(adapter->sfp_poll_time, jiffies))
7458 return; /* If not yet time to poll for SFP */
7459
7086400d
AD		 7460 /* someone else is in init, wait until next service event */
7461 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7462 return;
cf8280ee 7463
58e7cd24
MR		 7464 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7465
7086400d
AD		 7466 err = hw->phy.ops.identify_sfp(hw);
7467 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7468 goto sfp_out;
264857b8 7469
7086400d
AD		 7470 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7471 /* If no cable is present, then we need to reset
7472 * the next time we find a good cable. */
7473 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 7474 }
9a799d71 7475
7086400d
AD		 7476 /* exit on error */
7477 if (err)
7478 goto sfp_out;
e8e26350 7479
7086400d
AD		 7480 /* exit if reset not needed */
7481 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7482 goto sfp_out;
9a799d71 7483
7086400d 7484 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 7485
7086400d
AD		 7486 /*
7487 * A module may be identified correctly, but the EEPROM may not have
7488 * support for that module. setup_sfp() will fail in that case, so
7489 * we should not allow that module to load.
7490 */
7491 if (hw->mac.type == ixgbe_mac_82598EB)
7492 err = hw->phy.ops.reset(hw);
7493 else
7494 err = hw->mac.ops.setup_sfp(hw);
7495
7496 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7497 goto sfp_out;
7498
7499 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7500 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7501
7502sfp_out:
7503 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7504
7505 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7506 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7507 e_dev_err("failed to initialize because an unsupported "
7508 "SFP+ module type was detected.\n");
7509 e_dev_err("Reload the driver after installing a "
7510 "supported module.\n");
7511 unregister_netdev(adapter->netdev);
bc59fcda 7512 }
7086400d 7513}
bc59fcda 7514
7086400d
AD		 7515/**
7516 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 7517 * @adapter: the ixgbe adapter structure
7086400d
AD		 7518 **/
7519static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7520{
7521 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 7522 u32 speed;
7523 bool autoneg = false;
7086400d
AD		 7524
7525 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7526 return;
7527
7528 /* someone else is in init, wait until next service event */
7529 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7530 return;
7531
7532 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7533
3d292265 7534 speed = hw->phy.autoneg_advertised;
ed33ff66 7535 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 7536 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 7537
7538 /* setup the highest link when no autoneg */
7539 if (!autoneg) {
7540 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7541 speed = IXGBE_LINK_SPEED_10GB_FULL;
7542 }
7543 }
7544
7086400d 7545 if (hw->mac.ops.setup_link)
fd0326f2 7546 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 7547
7548 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7549 adapter->link_check_timeout = jiffies;
7550 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7551}
7552
7553/**
7554 * ixgbe_service_timer - Timer Call-back
7555 * @data: pointer to adapter cast into an unsigned long
7556 **/
7557static void ixgbe_service_timer(unsigned long data)
7558{
7559 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7560 unsigned long next_event_offset;
7561
6bb78cfb
AD		 7562 /* poll faster when waiting for link */
7563 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7564 next_event_offset = HZ / 10;
7565 else
7566 next_event_offset = HZ * 2;
83c61fa9 7567
7086400d
AD		 7568 /* Reset the timer */
7569 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7570
9079e416 7571 ixgbe_service_event_schedule(adapter);
7086400d
AD		 7572}
7573
597f22d6
DS		 7574static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7575{
7576 struct ixgbe_hw *hw = &adapter->hw;
7577 u32 status;
7578
7579 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7580 return;
7581
7582 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7583
7584 if (!hw->phy.ops.handle_lasi)
7585 return;
7586
7587 status = hw->phy.ops.handle_lasi(&adapter->hw);
7588 if (status != IXGBE_ERR_OVERTEMP)
7589 return;
7590
7591 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7592}
7593
c83c6cbd
AD		 7594static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7595{
57ca2a4f 7596 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
c83c6cbd
AD		 7597 return;
7598
09f40aed 7599 /* If we're already down, removing or resetting, just bail */
c83c6cbd 7600 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7601 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 7602 test_bit(__IXGBE_RESETTING, &adapter->state))
7603 return;
7604
7605 ixgbe_dump(adapter);
7606 netdev_err(adapter->netdev, "Reset adapter\n");
7607 adapter->tx_timeout_count++;
7608
8f4c5c9f 7609 rtnl_lock();
c83c6cbd 7610 ixgbe_reinit_locked(adapter);
8f4c5c9f 7611 rtnl_unlock();
c83c6cbd
AD		 7612}
7613
7086400d
AD		 7614/**
7615 * ixgbe_service_task - manages and runs subtasks
7616 * @work: pointer to work_struct containing our data
7617 **/
7618static void ixgbe_service_task(struct work_struct *work)
7619{
7620 struct ixgbe_adapter *adapter = container_of(work,
7621 struct ixgbe_adapter,
7622 service_task);
b0483c8f
MR		 7623 if (ixgbe_removed(adapter->hw.hw_addr)) {
7624 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7625 rtnl_lock();
7626 ixgbe_down(adapter);
7627 rtnl_unlock();
7628 }
7629 ixgbe_service_event_complete(adapter);
7630 return;
7631 }
a21d0822 7632 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) {
b3a49557 7633 rtnl_lock();
a21d0822 7634 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
b3a49557
AD		 7635 udp_tunnel_get_rx_info(adapter->netdev);
7636 rtnl_unlock();
67359c3c 7637 }
c83c6cbd 7638 ixgbe_reset_subtask(adapter);
597f22d6 7639 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 7640 ixgbe_sfp_detection_subtask(adapter);
7641 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 7642 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 7643 ixgbe_watchdog_subtask(adapter);
d034acf1 7644 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 7645 ixgbe_check_hang_subtask(adapter);
891dc082 7646
8fecf67c 7647 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 7648 ixgbe_ptp_overflow_check(adapter);
7649 ixgbe_ptp_rx_hang(adapter);
622a2ef5 7650 ixgbe_ptp_tx_hang(adapter);
891dc082 7651 }
7086400d
AD		 7652
7653 ixgbe_service_event_complete(adapter);
9a799d71
AK		 7654}
7655
fd0db0ed
AD		 7656static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7657 struct ixgbe_tx_buffer *first,
244e27ad 7658 u8 *hdr_len)
897ab156 7659{
b83e3010 7660 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
fd0db0ed 7661 struct sk_buff *skb = first->skb;
b83e3010
AD		 7662 union {
7663 struct iphdr *v4;
7664 struct ipv6hdr *v6;
7665 unsigned char *hdr;
7666 } ip;
7667 union {
7668 struct tcphdr *tcp;
7669 unsigned char *hdr;
7670 } l4;
7671 u32 paylen, l4_offset;
2049e1f6 7672 int err;
9a799d71 7673
8f4fbb9b
AD		 7674 if (skb->ip_summed != CHECKSUM_PARTIAL)
7675 return 0;
7676
897ab156
AD		 7677 if (!skb_is_gso(skb))
7678 return 0;
9a799d71 7679
2049e1f6
FR		 7680 err = skb_cow_head(skb, 0);
7681 if (err < 0)
7682 return err;
9a799d71 7683
2a20525b
SP		 7684 if (eth_p_mpls(first->protocol))
7685 ip.hdr = skb_inner_network_header(skb);
7686 else
7687 ip.hdr = skb_network_header(skb);
b83e3010
AD		 7688 l4.hdr = skb_checksum_start(skb);
7689
897ab156
AD		 7690 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7691 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7692
b83e3010
AD		 7693 /* initialize outer IP header fields */
7694 if (ip.v4->version == 4) {
c54cdc31
AD		 7695 unsigned char *csum_start = skb_checksum_start(skb);
7696 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
7697
b83e3010
AD		 7698 /* IP header will have to cancel out any data that
7699 * is not a part of the outer IP header
7700 */
c54cdc31
AD		 7701 ip.v4->check = csum_fold(csum_partial(trans_start,
7702 csum_start - trans_start,
7703 0));
897ab156 7704 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
b83e3010
AD		 7705
7706 ip.v4->tot_len = 0;
244e27ad
AD		 7707 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7708 IXGBE_TX_FLAGS_CSUM |
7709 IXGBE_TX_FLAGS_IPV4;
b83e3010
AD		 7710 } else {
7711 ip.v6->payload_len = 0;
244e27ad
AD		 7712 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7713 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 7714 }
7715
b83e3010
AD		 7716 /* determine offset of inner transport header */
7717 l4_offset = l4.hdr - skb->data;
7718
7719 /* compute length of segmentation header */
7720 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
7721
7722 /* remove payload length from inner checksum */
7723 paylen = skb->len - l4_offset;
7724 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
897ab156 7725
091a6246
AD		 7726 /* update gso size and bytecount with header size */
7727 first->gso_segs = skb_shinfo(skb)->gso_segs;
7728 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7729
c44f5f51 7730 /* mss_l4len_id: use 0 as index for TSO */
b83e3010 7731 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
897ab156 7732 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 7733
7734 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
b83e3010
AD		 7735 vlan_macip_lens = l4.hdr - ip.hdr;
7736 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7737 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 7738
7739 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 7740 mss_l4len_idx);
897ab156
AD		 7741
7742 return 1;
7743}
7744
49763de0
AD		 7745static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
7746{
7747 unsigned int offset = 0;
7748
7749 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
7750
7751 return offset == skb_checksum_start_offset(skb);
7752}
7753
244e27ad
AD		 7754static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7755 struct ixgbe_tx_buffer *first)
7ca647bd 7756{
fd0db0ed 7757 struct sk_buff *skb = first->skb;
897ab156 7758 u32 vlan_macip_lens = 0;
897ab156 7759 u32 type_tucmd = 0;
7ca647bd 7760
897ab156 7761 if (skb->ip_summed != CHECKSUM_PARTIAL) {
49763de0
AD		 7762csum_failed:
7763 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
7764 IXGBE_TX_FLAGS_CC)))
472148c3 7765 return;
49763de0
AD		 7766 goto no_csum;
7767 }
897ab156 7768
49763de0
AD		 7769 switch (skb->csum_offset) {
7770 case offsetof(struct tcphdr, check):
7771 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7772 /* fall through */
7773 case offsetof(struct udphdr, check):
7774 break;
7775 case offsetof(struct sctphdr, checksum):
7776 /* validate that this is actually an SCTP request */
7777 if (((first->protocol == htons(ETH_P_IP)) &&
7778 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
7779 ((first->protocol == htons(ETH_P_IPV6)) &&
7780 ixgbe_ipv6_csum_is_sctp(skb))) {
7781 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
897ab156 7782 break;
7ca647bd 7783 }
49763de0
AD		 7784 /* fall through */
7785 default:
7786 skb_checksum_help(skb);
7787 goto csum_failed;
7ca647bd
JP		 7788 }
7789
49763de0
AD		 7790 /* update TX checksum flag */
7791 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7792 vlan_macip_lens = skb_checksum_start_offset(skb) -
7793 skb_network_offset(skb);
36a92d71 7794no_csum:
244e27ad 7795 /* vlan_macip_lens: MACLEN, VLAN tag */
49763de0 7796 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7797 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7798
49763de0 7799 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0);
9a799d71
AK		 7800}
7801
472148c3
AD		 7802#define IXGBE_SET_FLAG(_input, _flag, _result) \
7803 ((_flag <= _result) ? \
7804 ((u32)(_input & _flag) * (_result / _flag)) : \
7805 ((u32)(_input & _flag) / (_flag / _result)))
7806
7807static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7808{
d3d00239 7809 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7810 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7811 IXGBE_ADVTXD_DCMD_DEXT |
7812 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7813
d3d00239 7814 /* set HW vlan bit if vlan is present */
472148c3
AD		 7815 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7816 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7817
d3d00239 7818 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7819 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7820 IXGBE_ADVTXD_DCMD_TSE);
7821
7822 /* set timestamp bit if present */
7823 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7824 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7825
62748b7b 7826 /* insert frame checksum */
472148c3 7827 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7828
d3d00239
AD		 7829 return cmd_type;
7830}
9a799d71 7831
729739b7
AD		 7832static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7833 u32 tx_flags, unsigned int paylen)
d3d00239 7834{
472148c3 7835 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7836
d3d00239 7837 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7838 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7839 IXGBE_TX_FLAGS_CSUM,
7840 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7841
93f5b3c1 7842 /* enble IPv4 checksum for TSO */
472148c3
AD		 7843 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7844 IXGBE_TX_FLAGS_IPV4,
7845 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7846
7f9643fd
AD		 7847 /*
7848 * Check Context must be set if Tx switch is enabled, which it
7849 * always is for case where virtual functions are running
7850 */
472148c3
AD		 7851 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7852 IXGBE_TX_FLAGS_CC,
7853 IXGBE_ADVTXD_CC);
7f9643fd 7854
472148c3 7855 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7856}
44df32c5 7857
2367a173
DB		 7858static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7859{
7860 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7861
7862 /* Herbert's original patch had:
7863 * smp_mb__after_netif_stop_queue();
7864 * but since that doesn't exist yet, just open code it.
7865 */
7866 smp_mb();
7867
7868 /* We need to check again in a case another CPU has just
7869 * made room available.
7870 */
7871 if (likely(ixgbe_desc_unused(tx_ring) < size))
7872 return -EBUSY;
7873
7874 /* A reprieve! - use start_queue because it doesn't call schedule */
7875 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7876 ++tx_ring->tx_stats.restart_queue;
7877 return 0;
7878}
7879
7880static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7881{
7882 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7883 return 0;
7884
7885 return __ixgbe_maybe_stop_tx(tx_ring, size);
7886}
7887
d3d00239
AD		 7888#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7889 IXGBE_TXD_CMD_RS)
7890
5fef124d
JK		 7891static int ixgbe_tx_map(struct ixgbe_ring *tx_ring,
7892 struct ixgbe_tx_buffer *first,
7893 const u8 hdr_len)
d3d00239 7894{
fd0db0ed 7895 struct sk_buff *skb = first->skb;
729739b7 7896 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7897 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7898 struct skb_frag_struct *frag;
7899 dma_addr_t dma;
7900 unsigned int data_len, size;
244e27ad 7901 u32 tx_flags = first->tx_flags;
472148c3 7902 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7903 u16 i = tx_ring->next_to_use;
d3d00239 7904
729739b7
AD		 7905 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7906
ec718254
AD		 7907 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7908
7909 size = skb_headlen(skb);
7910 data_len = skb->data_len;
729739b7 7911
d3d00239
AD		 7912#ifdef IXGBE_FCOE
7913 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7914 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7915 size -= sizeof(struct fcoe_crc_eof) - data_len;
7916 data_len = 0;
729739b7
AD		 7917 } else {
7918 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7919 }
7920 }
44df32c5 7921
d3d00239 7922#endif
729739b7 7923 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7924
ec718254 7925 tx_buffer = first;
9a799d71 7926
ec718254
AD		 7927 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7928 if (dma_mapping_error(tx_ring->dev, dma))
7929 goto dma_error;
7930
7931 /* record length, and DMA address */
7932 dma_unmap_len_set(tx_buffer, len, size);
7933 dma_unmap_addr_set(tx_buffer, dma, dma);
7934
7935 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7936
729739b7 7937 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7938 tx_desc->read.cmd_type_len =
472148c3 7939 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7940
d3d00239 7941 i++;
729739b7 7942 tx_desc++;
d3d00239 7943 if (i == tx_ring->count) {
e4f74028 7944 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7945 i = 0;
7946 }
ec718254 7947 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7948
7949 dma += IXGBE_MAX_DATA_PER_TXD;
7950 size -= IXGBE_MAX_DATA_PER_TXD;
7951
7952 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7953 }
e5a43549 7954
729739b7
AD		 7955 if (likely(!data_len))
7956 break;
9a799d71 7957
472148c3 7958 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7959
729739b7
AD		 7960 i++;
7961 tx_desc++;
7962 if (i == tx_ring->count) {
7963 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7964 i = 0;
7965 }
ec718254 7966 tx_desc->read.olinfo_status = 0;
9a799d71 7967
d3d00239 7968#ifdef IXGBE_FCOE
9e903e08 7969 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7970#else
9e903e08 7971 size = skb_frag_size(frag);
d3d00239
AD		 7972#endif
7973 data_len -= size;
9a799d71 7974
729739b7
AD		 7975 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7976 DMA_TO_DEVICE);
9a799d71 7977
729739b7 7978 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7979 }
9a799d71 7980
729739b7 7981 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7982 cmd_type |= size | IXGBE_TXD_CMD;
7983 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7984
091a6246 7985 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7986
d3d00239
AD		 7987 /* set the timestamp */
7988 first->time_stamp = jiffies;
9a799d71
AK		 7989
7990 /*
729739b7
AD		 7991 * Force memory writes to complete before letting h/w know there
7992 * are new descriptors to fetch. (Only applicable for weak-ordered
7993 * memory model archs, such as IA-64).
7994 *
7995 * We also need this memory barrier to make certain all of the
7996 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7997 */
7998 wmb();
7999
d3d00239
AD		 8000 /* set next_to_watch value indicating a packet is present */
8001 first->next_to_watch = tx_desc;
8002
729739b7
AD		 8003 i++;
8004 if (i == tx_ring->count)
8005 i = 0;
8006
8007 tx_ring->next_to_use = i;
8008
2367a173
DB		 8009 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
8010
8011 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 8012 writel(i, tx_ring->tail);
8013
8014 /* we need this if more than one processor can write to our tail
8015 * at a time, it synchronizes IO on IA64/Altix systems
8016 */
8017 mmiowb();
9c938cdd 8018 }
2367a173 8019
5fef124d 8020 return 0;
d3d00239 8021dma_error:
729739b7 8022 dev_err(tx_ring->dev, "TX DMA map failed\n");
ffed21bc 8023 tx_buffer = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 8024
8025 /* clear dma mappings for failed tx_buffer_info map */
ffed21bc
AD		 8026 while (tx_buffer != first) {
8027 if (dma_unmap_len(tx_buffer, len))
8028 dma_unmap_page(tx_ring->dev,
8029 dma_unmap_addr(tx_buffer, dma),
8030 dma_unmap_len(tx_buffer, len),
8031 DMA_TO_DEVICE);
8032 dma_unmap_len_set(tx_buffer, len, 0);
8033
8034 if (i--)
8035 i += tx_ring->count;
729739b7 8036 tx_buffer = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 8037 }
8038
ffed21bc
AD		 8039 if (dma_unmap_len(tx_buffer, len))
8040 dma_unmap_single(tx_ring->dev,
8041 dma_unmap_addr(tx_buffer, dma),
8042 dma_unmap_len(tx_buffer, len),
8043 DMA_TO_DEVICE);
8044 dma_unmap_len_set(tx_buffer, len, 0);
8045
8046 dev_kfree_skb_any(first->skb);
8047 first->skb = NULL;
8048
d3d00239 8049 tx_ring->next_to_use = i;
5fef124d
JK		 8050
8051 return -1;
9a799d71
AK		 8052}
8053
fd0db0ed 8054static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 8055 struct ixgbe_tx_buffer *first)
69830529
AD		 8056{
8057 struct ixgbe_q_vector *q_vector = ring->q_vector;
8058 union ixgbe_atr_hash_dword input = { .dword = 0 };
8059 union ixgbe_atr_hash_dword common = { .dword = 0 };
8060 union {
8061 unsigned char *network;
8062 struct iphdr *ipv4;
8063 struct ipv6hdr *ipv6;
8064 } hdr;
ee9e0f0b 8065 struct tcphdr *th;
e2873d43 8066 unsigned int hlen;
67359c3c 8067 struct sk_buff *skb;
905e4a41 8068 __be16 vlan_id;
e2873d43 8069 int l4_proto;
c4cf55e5 8070
69830529
AD		 8071 /* if ring doesn't have a interrupt vector, cannot perform ATR */
8072 if (!q_vector)
8073 return;
8074
8075 /* do nothing if sampling is disabled */
8076 if (!ring->atr_sample_rate)
d3ead241 8077 return;
c4cf55e5 8078
69830529 8079 ring->atr_count++;
c4cf55e5 8080
e2873d43
AD		 8081 /* currently only IPv4/IPv6 with TCP is supported */
8082 if ((first->protocol != htons(ETH_P_IP)) &&
8083 (first->protocol != htons(ETH_P_IPV6)))
8084 return;
8085
69830529 8086 /* snag network header to get L4 type and address */
67359c3c
MR		 8087 skb = first->skb;
8088 hdr.network = skb_network_header(skb);
9f3c7504
SV		 8089 if (unlikely(hdr.network <= skb->data))
8090 return;
9f12df90
AD		 8091 if (skb->encapsulation &&
8092 first->protocol == htons(ETH_P_IP) &&
52028821 8093 hdr.ipv4->protocol == IPPROTO_UDP) {
67359c3c 8094 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 8095
9f3c7504
SV		 8096 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8097 VXLAN_HEADROOM))
8098 return;
8099
9f12df90
AD		 8100 /* verify the port is recognized as VXLAN */
8101 if (adapter->vxlan_port &&
e2873d43 8102 udp_hdr(skb)->dest == adapter->vxlan_port)
9f12df90 8103 hdr.network = skb_inner_network_header(skb);
a21d0822
ET		 8104
8105 if (adapter->geneve_port &&
8106 udp_hdr(skb)->dest == adapter->geneve_port)
8107 hdr.network = skb_inner_network_header(skb);
e19dcdeb
MR		 8108 }
8109
9f3c7504
SV		 8110 /* Make sure we have at least [minimum IPv4 header + TCP]
8111 * or [IPv6 header] bytes
8112 */
8113 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40))
8114 return;
8115
e19dcdeb
MR		 8116 /* Currently only IPv4/IPv6 with TCP is supported */
8117 switch (hdr.ipv4->version) {
8118 case IPVERSION:
e2873d43
AD		 8119 /* access ihl as u8 to avoid unaligned access on ia64 */
8120 hlen = (hdr.network[0] & 0x0F) << 2;
8121 l4_proto = hdr.ipv4->protocol;
e19dcdeb
MR		 8122 break;
8123 case 6:
e2873d43
AD		 8124 hlen = hdr.network - skb->data;
8125 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
8126 hlen -= hdr.network - skb->data;
e19dcdeb
MR		 8127 break;
8128 default:
8129 return;
67359c3c 8130 }
c4cf55e5 8131
e2873d43
AD		 8132 if (l4_proto != IPPROTO_TCP)
8133 return;
8134
9f3c7504
SV		 8135 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8136 hlen + sizeof(struct tcphdr)))
8137 return;
8138
e2873d43
AD		 8139 th = (struct tcphdr *)(hdr.network + hlen);
8140
8141 /* skip this packet since the socket is closing */
8142 if (th->fin)
69830529
AD		 8143 return;
8144
8145 /* sample on all syn packets or once every atr sample count */
8146 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
8147 return;
8148
8149 /* reset sample count */
8150 ring->atr_count = 0;
8151
244e27ad 8152 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 8153
8154 /*
8155 * src and dst are inverted, think how the receiver sees them
8156 *
8157 * The input is broken into two sections, a non-compressed section
8158 * containing vm_pool, vlan_id, and flow_type. The rest of the data
8159 * is XORed together and stored in the compressed dword.
8160 */
8161 input.formatted.vlan_id = vlan_id;
8162
8163 /*
8164 * since src port and flex bytes occupy the same word XOR them together
8165 * and write the value to source port portion of compressed dword
8166 */
244e27ad 8167 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 8168 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 8169 else
244e27ad 8170 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 8171 common.port.dst ^= th->source;
8172
e19dcdeb
MR		 8173 switch (hdr.ipv4->version) {
8174 case IPVERSION:
69830529
AD		 8175 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
8176 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
e19dcdeb
MR		 8177 break;
8178 case 6:
69830529
AD		 8179 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
8180 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
8181 hdr.ipv6->saddr.s6_addr32[1] ^
8182 hdr.ipv6->saddr.s6_addr32[2] ^
8183 hdr.ipv6->saddr.s6_addr32[3] ^
8184 hdr.ipv6->daddr.s6_addr32[0] ^
8185 hdr.ipv6->daddr.s6_addr32[1] ^
8186 hdr.ipv6->daddr.s6_addr32[2] ^
8187 hdr.ipv6->daddr.s6_addr32[3];
e19dcdeb
MR		 8188 break;
8189 default:
8190 break;
69830529 8191 }
c4cf55e5 8192
9f12df90 8193 if (hdr.network != skb_network_header(skb))
67359c3c 8194 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
67359c3c 8195
c4cf55e5 8196 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 8197 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
8198 input, common, ring->queue_index);
c4cf55e5
PWJ		 8199}
8200
f663dd9a 8201static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 8202 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 8203{
f663dd9a
JW		 8204 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
8205#ifdef IXGBE_FCOE
97488bd1
AD		 8206 struct ixgbe_adapter *adapter;
8207 struct ixgbe_ring_feature *f;
8208 int txq;
f663dd9a
JW		 8209#endif
8210
8211 if (fwd_adapter)
8212 return skb->queue_mapping + fwd_adapter->tx_base_queue;
8213
8214#ifdef IXGBE_FCOE
5e09a105 8215
97488bd1
AD		 8216 /*
8217 * only execute the code below if protocol is FCoE
8218 * or FIP and we have FCoE enabled on the adapter
8219 */
8220 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 8221 case htons(ETH_P_FCOE):
8222 case htons(ETH_P_FIP):
97488bd1 8223 adapter = netdev_priv(dev);
c087663e 8224
97488bd1
AD		 8225 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
8226 break;
93df9465 8227 /* fall through */
97488bd1 8228 default:
99932d4f 8229 return fallback(dev, skb);
97488bd1 8230 }
c087663e 8231
97488bd1 8232 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 8233
97488bd1
AD		 8234 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
8235 smp_processor_id();
56075a98 8236
97488bd1
AD		 8237 while (txq >= f->indices)
8238 txq -= f->indices;
c4cf55e5 8239
97488bd1 8240 return txq + f->offset;
f663dd9a 8241#else
99932d4f 8242 return fallback(dev, skb);
f663dd9a 8243#endif
09a3b1f8
SH		 8244}
8245
33fdc82f
JF		 8246static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
8247 struct xdp_buff *xdp)
8248{
8249 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
8250 struct ixgbe_tx_buffer *tx_buffer;
8251 union ixgbe_adv_tx_desc *tx_desc;
8252 u32 len, cmd_type;
8253 dma_addr_t dma;
8254 u16 i;
8255
8256 len = xdp->data_end - xdp->data;
8257
8258 if (unlikely(!ixgbe_desc_unused(ring)))
8259 return IXGBE_XDP_CONSUMED;
8260
8261 dma = dma_map_single(ring->dev, xdp->data, len, DMA_TO_DEVICE);
8262 if (dma_mapping_error(ring->dev, dma))
8263 return IXGBE_XDP_CONSUMED;
8264
8265 /* record the location of the first descriptor for this packet */
8266 tx_buffer = &ring->tx_buffer_info[ring->next_to_use];
8267 tx_buffer->bytecount = len;
8268 tx_buffer->gso_segs = 1;
8269 tx_buffer->protocol = 0;
8270
8271 i = ring->next_to_use;
8272 tx_desc = IXGBE_TX_DESC(ring, i);
8273
8274 dma_unmap_len_set(tx_buffer, len, len);
8275 dma_unmap_addr_set(tx_buffer, dma, dma);
8276 tx_buffer->data = xdp->data;
8277 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8278
8279 /* put descriptor type bits */
8280 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8281 IXGBE_ADVTXD_DCMD_DEXT |
8282 IXGBE_ADVTXD_DCMD_IFCS;
8283 cmd_type |= len | IXGBE_TXD_CMD;
8284 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8285 tx_desc->read.olinfo_status =
8286 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT);
8287
7379f97a
JF		 8288 /* Avoid any potential race with xdp_xmit and cleanup */
8289 smp_wmb();
33fdc82f
JF		 8290
8291 /* set next_to_watch value indicating a packet is present */
8292 i++;
8293 if (i == ring->count)
8294 i = 0;
8295
8296 tx_buffer->next_to_watch = tx_desc;
8297 ring->next_to_use = i;
8298
33fdc82f
JF		 8299 return IXGBE_XDP_TX;
8300}
8301
fc77dc3c 8302netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 8303 struct ixgbe_adapter *adapter,
8304 struct ixgbe_ring *tx_ring)
9a799d71 8305{
d3d00239 8306 struct ixgbe_tx_buffer *first;
5f715823 8307 int tso;
d3d00239 8308 u32 tx_flags = 0;
a535c30e 8309 unsigned short f;
a535c30e 8310 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 8311 __be16 protocol = skb->protocol;
63544e9c 8312 u8 hdr_len = 0;
5e09a105 8313
a535c30e
AD		 8314 /*
8315 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 8316 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 8317 * + 2 desc gap to keep tail from touching head,
8318 * + 1 desc for context descriptor,
8319 * otherwise try next time
8320 */
a535c30e
AD		 8321 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
8322 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 8323
a535c30e
AD		 8324 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
8325 tx_ring->tx_stats.tx_busy++;
8326 return NETDEV_TX_BUSY;
8327 }
8328
fd0db0ed
AD		 8329 /* record the location of the first descriptor for this packet */
8330 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
8331 first->skb = skb;
091a6246
AD		 8332 first->bytecount = skb->len;
8333 first->gso_segs = 1;
fd0db0ed 8334
66f32a8b 8335 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 8336 if (skb_vlan_tag_present(skb)) {
8337 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 8338 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8339 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 8340 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 8341 struct vlan_hdr *vhdr, _vhdr;
8342 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
8343 if (!vhdr)
8344 goto out_drop;
8345
9e0c5648
AD		 8346 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
8347 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 8348 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
8349 }
0213668f 8350 protocol = vlan_get_protocol(skb);
66f32a8b 8351
d5234933 8352 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4cc74c01
JK		 8353 adapter->ptp_clock) {
8354 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
8355 &adapter->state)) {
8356 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8357 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
8358
8359 /* schedule check for Tx timestamp */
8360 adapter->ptp_tx_skb = skb_get(skb);
8361 adapter->ptp_tx_start = jiffies;
8362 schedule_work(&adapter->ptp_tx_work);
8363 } else {
8364 adapter->tx_hwtstamp_skipped++;
8365 }
3a6a4eda 8366 }
3a6a4eda 8367
ff29a86e
JK		 8368 skb_tx_timestamp(skb);
8369
9e0c5648
AD		 8370#ifdef CONFIG_PCI_IOV
8371 /*
8372 * Use the l2switch_enable flag - would be false if the DMA
8373 * Tx switch had been disabled.
8374 */
8375 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 8376 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 8377
8378#endif
32701dc2 8379 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 8380 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 8381 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
8382 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 8383 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 8384 tx_flags |= (skb->priority & 0x7) <<
8385 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 8386 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
8387 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 8388
8389 if (skb_cow_head(skb, 0))
66f32a8b
AD		 8390 goto out_drop;
8391 vhdr = (struct vlan_ethhdr *)skb->data;
8392 vhdr->h_vlan_TCI = htons(tx_flags >>
8393 IXGBE_TX_FLAGS_VLAN_SHIFT);
8394 } else {
8395 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 8396 }
9a799d71 8397 }
eacd73f7 8398
244e27ad
AD		 8399 /* record initial flags and protocol */
8400 first->tx_flags = tx_flags;
8401 first->protocol = protocol;
8402
eacd73f7 8403#ifdef IXGBE_FCOE
66f32a8b 8404 /* setup tx offload for FCoE */
a1108ffd 8405 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 8406 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 8407 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 8408 if (tso < 0)
8409 goto out_drop;
9a799d71 8410
66f32a8b 8411 goto xmit_fcoe;
eacd73f7 8412 }
9a799d71 8413
66f32a8b 8414#endif /* IXGBE_FCOE */
244e27ad 8415 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 8416 if (tso < 0)
897ab156 8417 goto out_drop;
244e27ad
AD		 8418 else if (!tso)
8419 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 8420
8421 /* add the ATR filter if ATR is on */
8422 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 8423 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 8424
8425#ifdef IXGBE_FCOE
8426xmit_fcoe:
8427#endif /* IXGBE_FCOE */
5fef124d
JK		 8428 if (ixgbe_tx_map(tx_ring, first, hdr_len))
8429 goto cleanup_tx_timestamp;
d3d00239 8430
9a799d71 8431 return NETDEV_TX_OK;
897ab156
AD		 8432
8433out_drop:
fd0db0ed
AD		 8434 dev_kfree_skb_any(first->skb);
8435 first->skb = NULL;
5fef124d
JK		 8436cleanup_tx_timestamp:
8437 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) {
8438 dev_kfree_skb_any(adapter->ptp_tx_skb);
8439 adapter->ptp_tx_skb = NULL;
8440 cancel_work_sync(&adapter->ptp_tx_work);
8441 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
8442 }
fd0db0ed 8443
897ab156 8444 return NETDEV_TX_OK;
9a799d71
AK		 8445}
8446
2a47fa45
JF		 8447static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
8448 struct net_device *netdev,
8449 struct ixgbe_ring *ring)
84418e3b
AD		 8450{
8451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8452 struct ixgbe_ring *tx_ring;
8453
a50c29dd
AD		 8454 /*
8455 * The minimum packet size for olinfo paylen is 17 so pad the skb
8456 * in order to meet this minimum size requirement.
8457 */
a94d9e22
AD		 8458 if (skb_put_padto(skb, 17))
8459 return NETDEV_TX_OK;
a50c29dd 8460
2a47fa45
JF		 8461 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
8462
fc77dc3c 8463 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 8464}
8465
2a47fa45
JF		 8466static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
8467 struct net_device *netdev)
8468{
8469 return __ixgbe_xmit_frame(skb, netdev, NULL);
8470}
8471
9a799d71
AK		 8472/**
8473 * ixgbe_set_mac - Change the Ethernet Address of the NIC
8474 * @netdev: network interface device structure
8475 * @p: pointer to an address structure
8476 *
8477 * Returns 0 on success, negative on failure
8478 **/
8479static int ixgbe_set_mac(struct net_device *netdev, void *p)
8480{
8481 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 8482 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 8483 struct sockaddr *addr = p;
8484
8485 if (!is_valid_ether_addr(addr->sa_data))
8486 return -EADDRNOTAVAIL;
8487
8488 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 8489 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 8490
c9f53e63
AD		 8491 ixgbe_mac_set_default_filter(adapter);
8492
8493 return 0;
9a799d71
AK		 8494}
8495
6b73e10d
BH		 8496static int
8497ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
8498{
8499 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8500 struct ixgbe_hw *hw = &adapter->hw;
8501 u16 value;
8502 int rc;
8503
8504 if (prtad != hw->phy.mdio.prtad)
8505 return -EINVAL;
8506 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
8507 if (!rc)
8508 rc = value;
8509 return rc;
8510}
8511
8512static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8513 u16 addr, u16 value)
8514{
8515 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8516 struct ixgbe_hw *hw = &adapter->hw;
8517
8518 if (prtad != hw->phy.mdio.prtad)
8519 return -EINVAL;
8520 return hw->phy.ops.write_reg(hw, addr, devad, value);
8521}
8522
8523static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8524{
8525 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8526
3a6a4eda 8527 switch (cmd) {
3a6a4eda 8528 case SIOCSHWTSTAMP:
93501d48
JK		 8529 return ixgbe_ptp_set_ts_config(adapter, req);
8530 case SIOCGHWTSTAMP:
8531 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 8532 default:
8533 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8534 }
6b73e10d
BH		 8535}
8536
0365e6e4
PW		 8537/**
8538 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 8539 * netdev->dev_addrs
0365e6e4
PW		 8540 * @netdev: network interface device structure
8541 *
8542 * Returns non-zero on failure
8543 **/
8544static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8545{
8546 int err = 0;
8547 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 8548 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 8549
7fa7c9dc 8550 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 8551 rtnl_lock();
7fa7c9dc 8552 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 8553 rtnl_unlock();
7fa7c9dc
AD		 8554
8555 /* update SAN MAC vmdq pool selection */
8556 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 8557 }
8558 return err;
8559}
8560
8561/**
8562 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 8563 * netdev->dev_addrs
0365e6e4
PW		 8564 * @netdev: network interface device structure
8565 *
8566 * Returns non-zero on failure
8567 **/
8568static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8569{
8570 int err = 0;
8571 struct ixgbe_adapter *adapter = netdev_priv(dev);
8572 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8573
8574 if (is_valid_ether_addr(mac->san_addr)) {
8575 rtnl_lock();
8576 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8577 rtnl_unlock();
8578 }
8579 return err;
8580}
8581
9a799d71
AK		 8582#ifdef CONFIG_NET_POLL_CONTROLLER
8583/*
8584 * Polling 'interrupt' - used by things like netconsole to send skbs
8585 * without having to re-enable interrupts. It's not called while
8586 * the interrupt routine is executing.
8587 */
8588static void ixgbe_netpoll(struct net_device *netdev)
8589{
8590 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 8591 int i;
9a799d71 8592
1a647bd2
AD		 8593 /* if interface is down do nothing */
8594 if (test_bit(__IXGBE_DOWN, &adapter->state))
8595 return;
8596
856f606e
AD		 8597 /* loop through and schedule all active queues */
8598 for (i = 0; i < adapter->num_q_vectors; i++)
8599 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 8600}
9a799d71 8601
581330ba 8602#endif
bc1f4470 8603
33fdc82f
JF		 8604static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats,
8605 struct ixgbe_ring *ring)
8606{
8607 u64 bytes, packets;
8608 unsigned int start;
8609
8610 if (ring) {
8611 do {
8612 start = u64_stats_fetch_begin_irq(&ring->syncp);
8613 packets = ring->stats.packets;
8614 bytes = ring->stats.bytes;
8615 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8616 stats->tx_packets += packets;
8617 stats->tx_bytes += bytes;
8618 }
8619}
8620
bc1f4470 8621static void ixgbe_get_stats64(struct net_device *netdev,
8622 struct rtnl_link_stats64 *stats)
de1036b1
ED		 8623{
8624 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8625 int i;
8626
1a51502b 8627 rcu_read_lock();
de1036b1 8628 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 8629 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 8630 u64 bytes, packets;
8631 unsigned int start;
8632
1a51502b
ED		 8633 if (ring) {
8634 do {
57a7744e 8635 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 8636 packets = ring->stats.packets;
8637 bytes = ring->stats.bytes;
57a7744e 8638 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 8639 stats->rx_packets += packets;
8640 stats->rx_bytes += bytes;
8641 }
de1036b1 8642 }
1ac9ad13
ED		 8643
8644 for (i = 0; i < adapter->num_tx_queues; i++) {
8645 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
1ac9ad13 8646
33fdc82f
JF		 8647 ixgbe_get_ring_stats64(stats, ring);
8648 }
8649 for (i = 0; i < adapter->num_xdp_queues; i++) {
8650 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->xdp_ring[i]);
8651
8652 ixgbe_get_ring_stats64(stats, ring);
1ac9ad13 8653 }
1a51502b 8654 rcu_read_unlock();
bc1f4470 8655
de1036b1
ED		 8656 /* following stats updated by ixgbe_watchdog_task() */
8657 stats->multicast = netdev->stats.multicast;
8658 stats->rx_errors = netdev->stats.rx_errors;
8659 stats->rx_length_errors = netdev->stats.rx_length_errors;
8660 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8661 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
de1036b1
ED		 8662}
8663
8af3c33f 8664#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 8665/**
8666 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8667 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 8668 * @tc: number of traffic classes currently enabled
8669 *
8670 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8671 * 802.1Q priority maps to a packet buffer that exists.
8672 */
8673static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8674{
8675 struct ixgbe_hw *hw = &adapter->hw;
8676 u32 reg, rsave;
8677 int i;
8678
8679 /* 82598 have a static priority to TC mapping that can not
8680 * be changed so no validation is needed.
8681 */
8682 if (hw->mac.type == ixgbe_mac_82598EB)
8683 return;
8684
8685 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8686 rsave = reg;
8687
8688 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8689 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8690
8691 /* If up2tc is out of bounds default to zero */
8692 if (up2tc > tc)
8693 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8694 }
8695
8696 if (reg != rsave)
8697 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8698
8699 return;
8700}
8701
02debdc9
AD		 8702/**
8703 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8704 * @adapter: Pointer to adapter struct
8705 *
8706 * Populate the netdev user priority to tc map
8707 */
8708static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8709{
8710 struct net_device *dev = adapter->netdev;
8711 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8712 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8713 u8 prio;
8714
8715 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8716 u8 tc = 0;
8717
8718 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8719 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8720 else if (ets)
8721 tc = ets->prio_tc[prio];
8722
8723 netdev_set_prio_tc_map(dev, prio, tc);
8724 }
8725}
8726
cca73c59 8727#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 8728/**
8729 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 8730 *
8731 * @netdev: net device to configure
8732 * @tc: number of traffic classes to enable
8733 */
8734int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8735{
8b1c0b24
JF		 8736 struct ixgbe_adapter *adapter = netdev_priv(dev);
8737 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 8738 bool pools;
8b1c0b24 8739
8b1c0b24 8740 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 8741 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8742 return -EINVAL;
8743
8744 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 8745 return -EINVAL;
8746
2a47fa45
JF		 8747 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8748 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8749 return -EBUSY;
8750
8b1c0b24 8751 /* Hardware has to reinitialize queues and interrupts to
52f33af8 8752 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 8753 * hardware is not flexible enough to do this dynamically.
8754 */
8755 if (netif_running(dev))
8756 ixgbe_close(dev);
bf4d67d9
AD		 8757 else
8758 ixgbe_reset(adapter);
8759
8b1c0b24
JF		 8760 ixgbe_clear_interrupt_scheme(adapter);
8761
cca73c59 8762#ifdef CONFIG_IXGBE_DCB
e7589eab 8763 if (tc) {
8b1c0b24 8764 netdev_set_num_tc(dev, tc);
02debdc9
AD		 8765 ixgbe_set_prio_tc_map(adapter);
8766
e7589eab 8767 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 8768
943561d3
AD		 8769 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8770 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 8771 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 8772 }
e7589eab 8773 } else {
8b1c0b24 8774 netdev_reset_tc(dev);
02debdc9 8775
943561d3
AD		 8776 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8777 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 8778
8779 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 8780
8781 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8782 adapter->dcb_cfg.pfc_mode_enable = false;
8783 }
8784
8b1c0b24 8785 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 8786
8787#endif /* CONFIG_IXGBE_DCB */
8788 ixgbe_init_interrupt_scheme(adapter);
8789
8b1c0b24 8790 if (netif_running(dev))
cca73c59 8791 return ixgbe_open(dev);
8b1c0b24
JF		 8792
8793 return 0;
8794}
de1036b1 8795
b82b17d9
JF		 8796static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
8797 struct tc_cls_u32_offload *cls)
8798{
1ecedc92 8799 u32 hdl = cls->knode.handle;
176621c9 8800 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
1ecedc92
AN		 8801 u32 loc = cls->knode.handle & 0xfffff;
8802 int err = 0, i, j;
8803 struct ixgbe_jump_table *jump = NULL;
8804
8805 if (loc > IXGBE_MAX_HW_ENTRIES)
8806 return -EINVAL;
b82b17d9 8807
176621c9
SS		 8808 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
8809 return -EINVAL;
8810
1ecedc92
AN		 8811 /* Clear this filter in the link data it is associated with */
8812 if (uhtid != 0x800) {
8813 jump = adapter->jump_tables[uhtid];
12746fd2
AN		 8814 if (!jump)
8815 return -EINVAL;
8816 if (!test_bit(loc - 1, jump->child_loc_map))
8817 return -EINVAL;
8818 clear_bit(loc - 1, jump->child_loc_map);
1ecedc92
AN		 8819 }
8820
8821 /* Check if the filter being deleted is a link */
8822 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
8823 jump = adapter->jump_tables[i];
8824 if (jump && jump->link_hdl == hdl) {
8825 /* Delete filters in the hardware in the child hash
8826 * table associated with this link
8827 */
8828 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
8829 if (!test_bit(j, jump->child_loc_map))
8830 continue;
8831 spin_lock(&adapter->fdir_perfect_lock);
8832 err = ixgbe_update_ethtool_fdir_entry(adapter,
8833 NULL,
8834 j + 1);
8835 spin_unlock(&adapter->fdir_perfect_lock);
8836 clear_bit(j, jump->child_loc_map);
8837 }
8838 /* Remove resources for this link */
8839 kfree(jump->input);
8840 kfree(jump->mask);
8841 kfree(jump);
8842 adapter->jump_tables[i] = NULL;
8843 return err;
8844 }
8845 }
176621c9 8846
b82b17d9 8847 spin_lock(&adapter->fdir_perfect_lock);
176621c9 8848 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
b82b17d9
JF		 8849 spin_unlock(&adapter->fdir_perfect_lock);
8850 return err;
8851}
8852
db956ae8 8853static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
db956ae8
JF		 8854 struct tc_cls_u32_offload *cls)
8855{
176621c9
SS		 8856 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8857
8858 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8859 return -EINVAL;
8860
db956ae8
JF		 8861 /* This ixgbe devices do not support hash tables at the moment
8862 * so abort when given hash tables.
8863 */
8864 if (cls->hnode.divisor > 0)
8865 return -EINVAL;
8866
176621c9 8867 set_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 8868 return 0;
8869}
8870
8871static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
8872 struct tc_cls_u32_offload *cls)
8873{
176621c9
SS		 8874 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8875
8876 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8877 return -EINVAL;
8878
8879 clear_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 8880 return 0;
8881}
8882
947f8a45 8883#ifdef CONFIG_NET_CLS_ACT
1cd127fc
DA		 8884struct upper_walk_data {
8885 struct ixgbe_adapter *adapter;
8886 u64 action;
8887 int ifindex;
8888 u8 queue;
8889};
8890
8891static int get_macvlan_queue(struct net_device *upper, void *_data)
8892{
8893 if (netif_is_macvlan(upper)) {
8894 struct macvlan_dev *dfwd = netdev_priv(upper);
8895 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
8896 struct upper_walk_data *data = _data;
8897 struct ixgbe_adapter *adapter = data->adapter;
8898 int ifindex = data->ifindex;
8899
8900 if (vadapter && vadapter->netdev->ifindex == ifindex) {
8901 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
8902 data->action = data->queue;
8903 return 1;
8904 }
8905 }
8906
8907 return 0;
8908}
8909
947f8a45
SS		 8910static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
8911 u8 *queue, u64 *action)
8912{
8913 unsigned int num_vfs = adapter->num_vfs, vf;
1cd127fc 8914 struct upper_walk_data data;
947f8a45 8915 struct net_device *upper;
947f8a45
SS		 8916
8917 /* redirect to a SRIOV VF */
8918 for (vf = 0; vf < num_vfs; ++vf) {
8919 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
8920 if (upper->ifindex == ifindex) {
8921 if (adapter->num_rx_pools > 1)
8922 *queue = vf * 2;
8923 else
8924 *queue = vf * adapter->num_rx_queues_per_pool;
8925
8926 *action = vf + 1;
8927 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
8928 return 0;
8929 }
8930 }
8931
8932 /* redirect to a offloaded macvlan netdev */
1cd127fc
DA		 8933 data.adapter = adapter;
8934 data.ifindex = ifindex;
8935 data.action = 0;
8936 data.queue = 0;
8937 if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
8938 get_macvlan_queue, &data)) {
8939 *action = data.action;
8940 *queue = data.queue;
8941
8942 return 0;
947f8a45
SS		 8943 }
8944
8945 return -EINVAL;
8946}
8947
8948static int parse_tc_actions(struct ixgbe_adapter *adapter,
8949 struct tcf_exts *exts, u64 *action, u8 *queue)
8950{
8951 const struct tc_action *a;
22dc13c8 8952 LIST_HEAD(actions);
947f8a45
SS		 8953 int err;
8954
3bcc0cec 8955 if (!tcf_exts_has_actions(exts))
947f8a45
SS		 8956 return -EINVAL;
8957
22dc13c8
WC		 8958 tcf_exts_to_list(exts, &actions);
8959 list_for_each_entry(a, &actions, list) {
947f8a45
SS		 8960
8961 /* Drop action */
8962 if (is_tcf_gact_shot(a)) {
8963 *action = IXGBE_FDIR_DROP_QUEUE;
8964 *queue = IXGBE_FDIR_DROP_QUEUE;
8965 return 0;
8966 }
8967
8968 /* Redirect to a VF or a offloaded macvlan */
5724b8b5 8969 if (is_tcf_mirred_egress_redirect(a)) {
947f8a45
SS		 8970 int ifindex = tcf_mirred_ifindex(a);
8971
8972 err = handle_redirect_action(adapter, ifindex, queue,
8973 action);
8974 if (err == 0)
8975 return err;
8976 }
8977 }
8978
8979 return -EINVAL;
8980}
8981#else
8982static int parse_tc_actions(struct ixgbe_adapter *adapter,
8983 struct tcf_exts *exts, u64 *action, u8 *queue)
8984{
8985 return -EINVAL;
8986}
8987#endif /* CONFIG_NET_CLS_ACT */
8988
1cdaaf54
AN		 8989static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
8990 union ixgbe_atr_input *mask,
8991 struct tc_cls_u32_offload *cls,
8992 struct ixgbe_mat_field *field_ptr,
8993 struct ixgbe_nexthdr *nexthdr)
8994{
8995 int i, j, off;
8996 __be32 val, m;
8997 bool found_entry = false, found_jump_field = false;
8998
8999 for (i = 0; i < cls->knode.sel->nkeys; i++) {
9000 off = cls->knode.sel->keys[i].off;
9001 val = cls->knode.sel->keys[i].val;
9002 m = cls->knode.sel->keys[i].mask;
9003
9004 for (j = 0; field_ptr[j].val; j++) {
9005 if (field_ptr[j].off == off) {
9006 field_ptr[j].val(input, mask, val, m);
9007 input->filter.formatted.flow_type |=
9008 field_ptr[j].type;
9009 found_entry = true;
9010 break;
9011 }
9012 }
9013 if (nexthdr) {
9014 if (nexthdr->off == cls->knode.sel->keys[i].off &&
9015 nexthdr->val == cls->knode.sel->keys[i].val &&
9016 nexthdr->mask == cls->knode.sel->keys[i].mask)
9017 found_jump_field = true;
9018 else
9019 continue;
9020 }
9021 }
9022
9023 if (nexthdr && !found_jump_field)
9024 return -EINVAL;
9025
9026 if (!found_entry)
9027 return 0;
9028
9029 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
9030 IXGBE_ATR_L4TYPE_MASK;
9031
9032 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
9033 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
9034
9035 return 0;
9036}
9037
b82b17d9 9038static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
b82b17d9
JF		 9039 struct tc_cls_u32_offload *cls)
9040{
5fd9fc4e 9041 __be16 protocol = cls->common.protocol;
b82b17d9
JF		 9042 u32 loc = cls->knode.handle & 0xfffff;
9043 struct ixgbe_hw *hw = &adapter->hw;
9044 struct ixgbe_mat_field *field_ptr;
1cdaaf54
AN		 9045 struct ixgbe_fdir_filter *input = NULL;
9046 union ixgbe_atr_input *mask = NULL;
9047 struct ixgbe_jump_table *jump = NULL;
9048 int i, err = -EINVAL;
b82b17d9 9049 u8 queue;
176621c9 9050 u32 uhtid, link_uhtid;
b82b17d9 9051
176621c9
SS		 9052 uhtid = TC_U32_USERHTID(cls->knode.handle);
9053 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
b82b17d9 9054
176621c9 9055 /* At the moment cls_u32 jumps to network layer and skips past
b82b17d9
JF		 9056 * L2 headers. The canonical method to match L2 frames is to use
9057 * negative values. However this is error prone at best but really
9058 * just broken because there is no way to "know" what sort of hdr
176621c9 9059 * is in front of the network layer. Fix cls_u32 to support L2
b82b17d9
JF		 9060 * headers when needed.
9061 */
9062 if (protocol != htons(ETH_P_IP))
1cdaaf54 9063 return err;
b82b17d9
JF		 9064
9065 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
9066 e_err(drv, "Location out of range\n");
1cdaaf54 9067 return err;
b82b17d9
JF		 9068 }
9069
9070 /* cls u32 is a graph starting at root node 0x800. The driver tracks
9071 * links and also the fields used to advance the parser across each
9072 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
9073 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
9074 * To add support for new nodes update ixgbe_model.h parse structures
9075 * this function _should_ be generic try not to hardcode values here.
9076 */
176621c9 9077 if (uhtid == 0x800) {
1cdaaf54 9078 field_ptr = (adapter->jump_tables[0])->mat;
b82b17d9 9079 } else {
176621c9 9080 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
1cdaaf54
AN		 9081 return err;
9082 if (!adapter->jump_tables[uhtid])
9083 return err;
9084 field_ptr = (adapter->jump_tables[uhtid])->mat;
b82b17d9
JF		 9085 }
9086
9087 if (!field_ptr)
1cdaaf54 9088 return err;
b82b17d9 9089
1cdaaf54
AN		 9090 /* At this point we know the field_ptr is valid and need to either
9091 * build cls_u32 link or attach filter. Because adding a link to
9092 * a handle that does not exist is invalid and the same for adding
9093 * rules to handles that don't exist.
9094 */
b82b17d9 9095
1cdaaf54
AN		 9096 if (link_uhtid) {
9097 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
b82b17d9 9098
1cdaaf54
AN		 9099 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
9100 return err;
9101
9102 if (!test_bit(link_uhtid - 1, &adapter->tables))
9103 return err;
9104
1ecedc92
AN		 9105 /* Multiple filters as links to the same hash table are not
9106 * supported. To add a new filter with the same next header
9107 * but different match/jump conditions, create a new hash table
9108 * and link to it.
9109 */
9110 if (adapter->jump_tables[link_uhtid] &&
9111 (adapter->jump_tables[link_uhtid])->link_hdl) {
9112 e_err(drv, "Link filter exists for link: %x\n",
9113 link_uhtid);
9114 return err;
9115 }
9116
1cdaaf54
AN		 9117 for (i = 0; nexthdr[i].jump; i++) {
9118 if (nexthdr[i].o != cls->knode.sel->offoff ||
9119 nexthdr[i].s != cls->knode.sel->offshift ||
9120 nexthdr[i].m != cls->knode.sel->offmask)
9121 return err;
9122
9123 jump = kzalloc(sizeof(*jump), GFP_KERNEL);
9124 if (!jump)
9125 return -ENOMEM;
9126 input = kzalloc(sizeof(*input), GFP_KERNEL);
9127 if (!input) {
9128 err = -ENOMEM;
9129 goto free_jump;
9130 }
9131 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9132 if (!mask) {
9133 err = -ENOMEM;
12746fd2 9134 goto free_input;
1cdaaf54
AN		 9135 }
9136 jump->input = input;
9137 jump->mask = mask;
1ecedc92
AN		 9138 jump->link_hdl = cls->knode.handle;
9139
1cdaaf54
AN		 9140 err = ixgbe_clsu32_build_input(input, mask, cls,
9141 field_ptr, &nexthdr[i]);
9142 if (!err) {
9143 jump->mat = nexthdr[i].jump;
9144 adapter->jump_tables[link_uhtid] = jump;
b82b17d9
JF		 9145 break;
9146 }
9147 }
1cdaaf54 9148 return 0;
b82b17d9
JF		 9149 }
9150
1cdaaf54
AN		 9151 input = kzalloc(sizeof(*input), GFP_KERNEL);
9152 if (!input)
9153 return -ENOMEM;
9154 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9155 if (!mask) {
9156 err = -ENOMEM;
12746fd2 9157 goto free_input;
1cdaaf54 9158 }
b82b17d9 9159
1cdaaf54
AN		 9160 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
9161 if ((adapter->jump_tables[uhtid])->input)
9162 memcpy(input, (adapter->jump_tables[uhtid])->input,
9163 sizeof(*input));
9164 if ((adapter->jump_tables[uhtid])->mask)
9165 memcpy(mask, (adapter->jump_tables[uhtid])->mask,
9166 sizeof(*mask));
12746fd2
AN		 9167
9168 /* Lookup in all child hash tables if this location is already
9169 * filled with a filter
9170 */
9171 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9172 struct ixgbe_jump_table *link = adapter->jump_tables[i];
9173
9174 if (link && (test_bit(loc - 1, link->child_loc_map))) {
9175 e_err(drv, "Filter exists in location: %x\n",
9176 loc);
9177 err = -EINVAL;
9178 goto err_out;
9179 }
9180 }
1cdaaf54
AN		 9181 }
9182 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
9183 if (err)
b82b17d9
JF		 9184 goto err_out;
9185
947f8a45
SS		 9186 err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
9187 &queue);
9188 if (err < 0)
b82b17d9 9189 goto err_out;
b82b17d9 9190
b82b17d9
JF		 9191 input->sw_idx = loc;
9192
9193 spin_lock(&adapter->fdir_perfect_lock);
9194
9195 if (hlist_empty(&adapter->fdir_filter_list)) {
1cdaaf54
AN		 9196 memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
9197 err = ixgbe_fdir_set_input_mask_82599(hw, mask);
b82b17d9
JF		 9198 if (err)
9199 goto err_out_w_lock;
1cdaaf54 9200 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
b82b17d9
JF		 9201 err = -EINVAL;
9202 goto err_out_w_lock;
9203 }
9204
1cdaaf54 9205 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
b82b17d9
JF		 9206 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
9207 input->sw_idx, queue);
9208 if (!err)
9209 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
9210 spin_unlock(&adapter->fdir_perfect_lock);
9211
12746fd2
AN		 9212 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
9213 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
1ecedc92 9214
1cdaaf54 9215 kfree(mask);
b82b17d9
JF		 9216 return err;
9217err_out_w_lock:
9218 spin_unlock(&adapter->fdir_perfect_lock);
9219err_out:
1ecedc92 9220 kfree(mask);
12746fd2
AN		 9221free_input:
9222 kfree(input);
1cdaaf54
AN		 9223free_jump:
9224 kfree(jump);
9225 return err;
b82b17d9
JF		 9226}
9227
bc32afdb 9228static int ixgbe_setup_tc_cls_u32(struct net_device *dev,
bc32afdb 9229 struct tc_cls_u32_offload *cls_u32)
e4c6734e 9230{
b82b17d9
JF		 9231 struct ixgbe_adapter *adapter = netdev_priv(dev);
9232
5fd9fc4e
JP		 9233 if (TC_H_MAJ(cls_u32->common.handle) != TC_H_MAJ(TC_H_INGRESS) ||
9234 cls_u32->common.chain_index)
a5fcf8a6
JP		 9235 return -EOPNOTSUPP;
9236
bc32afdb
JP		 9237 switch (cls_u32->command) {
9238 case TC_CLSU32_NEW_KNODE:
9239 case TC_CLSU32_REPLACE_KNODE:
5fd9fc4e 9240 return ixgbe_configure_clsu32(adapter, cls_u32);
bc32afdb
JP		 9241 case TC_CLSU32_DELETE_KNODE:
9242 return ixgbe_delete_clsu32(adapter, cls_u32);
9243 case TC_CLSU32_NEW_HNODE:
9244 case TC_CLSU32_REPLACE_HNODE:
5fd9fc4e 9245 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32);
bc32afdb
JP		 9246 case TC_CLSU32_DELETE_HNODE:
9247 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32);
9248 default:
9249 return -EOPNOTSUPP;
b82b17d9 9250 }
bc32afdb 9251}
b82b17d9 9252
bc32afdb
JP		 9253static int ixgbe_setup_tc_mqprio(struct net_device *dev,
9254 struct tc_mqprio_qopt *mqprio)
9255{
9256 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9257 return ixgbe_setup_tc(dev, mqprio->num_tc);
9258}
56f36acd 9259
bc32afdb 9260static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type,
bc32afdb
JP		 9261 struct tc_to_netdev *tc)
9262{
9263 switch (type) {
9264 case TC_SETUP_CLSU32:
5fd9fc4e 9265 return ixgbe_setup_tc_cls_u32(dev, tc->cls_u32);
bc32afdb
JP		 9266 case TC_SETUP_MQPRIO:
9267 return ixgbe_setup_tc_mqprio(dev, tc->mqprio);
9268 default:
9269 return -EOPNOTSUPP;
9270 }
e4c6734e
JF		 9271}
9272
da36b647
GR		 9273#ifdef CONFIG_PCI_IOV
9274void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
9275{
9276 struct net_device *netdev = adapter->netdev;
9277
9278 rtnl_lock();
da36b647 9279 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 9280 rtnl_unlock();
9281}
9282
9283#endif
082757af
DS		 9284void ixgbe_do_reset(struct net_device *netdev)
9285{
9286 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9287
9288 if (netif_running(netdev))
9289 ixgbe_reinit_locked(adapter);
9290 else
9291 ixgbe_reset(adapter);
9292}
9293
c8f44aff 9294static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 9295 netdev_features_t features)
082757af
DS		 9296{
9297 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9298
082757af 9299 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 9300 if (!(features & NETIF_F_RXCSUM))
9301 features &= ~NETIF_F_LRO;
082757af 9302
567d2de2
AD		 9303 /* Turn off LRO if not RSC capable */
9304 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
9305 features &= ~NETIF_F_LRO;
8e2813f5 9306
567d2de2 9307 return features;
082757af
DS		 9308}
9309
c8f44aff 9310static int ixgbe_set_features(struct net_device *netdev,
567d2de2 9311 netdev_features_t features)
082757af
DS		 9312{
9313 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 9314 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 9315 bool need_reset = false;
9316
082757af 9317 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 9318 if (!(features & NETIF_F_LRO)) {
9319 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 9320 need_reset = true;
567d2de2
AD		 9321 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
9322 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
9323 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
9324 if (adapter->rx_itr_setting == 1 ||
9325 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
9326 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9327 need_reset = true;
9328 } else if ((changed ^ features) & NETIF_F_LRO) {
9329 e_info(probe, "rx-usecs set too low, "
9330 "disabling RSC\n");
082757af
DS		 9331 }
9332 }
9333
9334 /*
b82b17d9
JF		 9335 * Check if Flow Director n-tuple support or hw_tc support was
9336 * enabled or disabled. If the state changed, we need to reset.
082757af 9337 */
b82b17d9 9338 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
567d2de2 9339 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 9340 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
9341 need_reset = true;
9342
567d2de2
AD		 9343 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
9344 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
b82b17d9 9345 } else {
39cb681b
AD		 9346 /* turn off perfect filters, enable ATR and reset */
9347 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
9348 need_reset = true;
9349
9350 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9351
9352 /* We cannot enable ATR if SR-IOV is enabled */
b82b17d9
JF		 9353 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
9354 /* We cannot enable ATR if we have 2 or more tcs */
9355 (netdev_get_num_tc(netdev) > 1) ||
9356 /* We cannot enable ATR if RSS is disabled */
9357 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
9358 /* A sample rate of 0 indicates ATR disabled */
9359 (!adapter->atr_sample_rate))
9360 ; /* do nothing not supported */
9361 else /* otherwise supported and set the flag */
9362 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 9363 }
9364
3f2d1c0f
BG		 9365 if (changed & NETIF_F_RXALL)
9366 need_reset = true;
9367
567d2de2 9368 netdev->features = features;
67359c3c 9369
67359c3c 9370 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
a21d0822
ET		 9371 if (features & NETIF_F_RXCSUM) {
9372 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
9373 } else {
9374 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK;
9375
9376 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9377 }
9378 }
9379
9380 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) {
9381 if (features & NETIF_F_RXCSUM) {
9382 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
9383 } else {
9384 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK;
9385
9386 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9387 }
67359c3c 9388 }
67359c3c 9389
082757af
DS		 9390 if (need_reset)
9391 ixgbe_do_reset(netdev);
0c5a6166
AD		 9392 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
9393 NETIF_F_HW_VLAN_CTAG_FILTER))
9394 ixgbe_set_rx_mode(netdev);
082757af
DS		 9395
9396 return 0;
082757af
DS		 9397}
9398
3f207800 9399/**
a21d0822 9400 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports
3f207800 9401 * @dev: The port's netdev
e5de25dc 9402 * @ti: Tunnel endpoint information
3f207800 9403 **/
a21d0822
ET		 9404static void ixgbe_add_udp_tunnel_port(struct net_device *dev,
9405 struct udp_tunnel_info *ti)
3f207800
DS		 9406{
9407 struct ixgbe_adapter *adapter = netdev_priv(dev);
9408 struct ixgbe_hw *hw = &adapter->hw;
b3a49557 9409 __be16 port = ti->port;
a21d0822
ET		 9410 u32 port_shift = 0;
9411 u32 reg;
67359c3c 9412
b3a49557
AD		 9413 if (ti->sa_family != AF_INET)
9414 return;
9415
a21d0822
ET		 9416 switch (ti->type) {
9417 case UDP_TUNNEL_TYPE_VXLAN:
9418 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
9419 return;
3f207800 9420
a21d0822
ET		 9421 if (adapter->vxlan_port == port)
9422 return;
9423
9424 if (adapter->vxlan_port) {
9425 netdev_info(dev,
9426 "VXLAN port %d set, not adding port %d\n",
9427 ntohs(adapter->vxlan_port),
9428 ntohs(port));
9429 return;
9430 }
9431
9432 adapter->vxlan_port = port;
9433 break;
9434 case UDP_TUNNEL_TYPE_GENEVE:
9435 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))
9436 return;
9437
9438 if (adapter->geneve_port == port)
9439 return;
9440
9441 if (adapter->geneve_port) {
9442 netdev_info(dev,
9443 "GENEVE port %d set, not adding port %d\n",
9444 ntohs(adapter->geneve_port),
9445 ntohs(port));
9446 return;
9447 }
3f207800 9448
a21d0822
ET		 9449 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT;
9450 adapter->geneve_port = port;
9451 break;
9452 default:
3f207800
DS		 9453 return;
9454 }
9455
a21d0822
ET		 9456 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift;
9457 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg);
3f207800
DS		 9458}
9459
9460/**
a21d0822 9461 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports
3f207800 9462 * @dev: The port's netdev
e5de25dc 9463 * @ti: Tunnel endpoint information
3f207800 9464 **/
a21d0822
ET		 9465static void ixgbe_del_udp_tunnel_port(struct net_device *dev,
9466 struct udp_tunnel_info *ti)
3f207800
DS		 9467{
9468 struct ixgbe_adapter *adapter = netdev_priv(dev);
a21d0822 9469 u32 port_mask;
3f207800 9470
a21d0822
ET		 9471 if (ti->type != UDP_TUNNEL_TYPE_VXLAN &&
9472 ti->type != UDP_TUNNEL_TYPE_GENEVE)
67359c3c
MR		 9473 return;
9474
b3a49557 9475 if (ti->sa_family != AF_INET)
3f207800
DS		 9476 return;
9477
a21d0822
ET		 9478 switch (ti->type) {
9479 case UDP_TUNNEL_TYPE_VXLAN:
9480 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
9481 return;
b3a49557 9482
a21d0822
ET		 9483 if (adapter->vxlan_port != ti->port) {
9484 netdev_info(dev, "VXLAN port %d not found\n",
9485 ntohs(ti->port));
9486 return;
9487 }
9488
9489 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK;
9490 break;
9491 case UDP_TUNNEL_TYPE_GENEVE:
9492 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))
9493 return;
9494
9495 if (adapter->geneve_port != ti->port) {
9496 netdev_info(dev, "GENEVE port %d not found\n",
9497 ntohs(ti->port));
9498 return;
9499 }
9500
9501 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK;
9502 break;
9503 default:
3f207800
DS		 9504 return;
9505 }
9506
a21d0822
ET		 9507 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9508 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
3f207800
DS		 9509}
9510
edc7d573 9511static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 9512 struct net_device *dev,
f6f6424b 9513 const unsigned char *addr, u16 vid,
0f4b0add
JF		 9514 u16 flags)
9515{
bcfd3432 9516 /* guarantee we can provide a unique filter for the unicast address */
46acc460 9517 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2f9be166
AD		 9518 struct ixgbe_adapter *adapter = netdev_priv(dev);
9519 u16 pool = VMDQ_P(0);
9520
9521 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
bcfd3432 9522 return -ENOMEM;
0f4b0add
JF		 9523 }
9524
f6f6424b 9525 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 9526}
9527
219efe97
DS		 9528/**
9529 * ixgbe_configure_bridge_mode - set various bridge modes
9530 * @adapter - the private structure
9531 * @mode - requested bridge mode
9532 *
9533 * Configure some settings require for various bridge modes.
9534 **/
9535static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9536 __u16 mode)
9537{
6d4c96ad
DS		 9538 struct ixgbe_hw *hw = &adapter->hw;
9539 unsigned int p, num_pools;
9540 u32 vmdctl;
9541
219efe97
DS		 9542 switch (mode) {
9543 case BRIDGE_MODE_VEPA:
6d4c96ad 9544 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 9545 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 9546
9547 /* must enable Rx switching replication to allow multicast
9548 * packet reception on all VFs, and to enable source address
9549 * pruning.
9550 */
9551 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9552 vmdctl |= IXGBE_VT_CTL_REPLEN;
9553 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9554
9555 /* enable Rx source address pruning. Note, this requires
9556 * replication to be enabled or else it does nothing.
9557 */
9558 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9559 for (p = 0; p < num_pools; p++) {
9560 if (hw->mac.ops.set_source_address_pruning)
9561 hw->mac.ops.set_source_address_pruning(hw,
9562 true,
9563 p);
9564 }
219efe97
DS		 9565 break;
9566 case BRIDGE_MODE_VEB:
6d4c96ad 9567 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 9568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
9569 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 9570
9571 /* disable Rx switching replication unless we have SR-IOV
9572 * virtual functions
9573 */
9574 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9575 if (!adapter->num_vfs)
9576 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
9577 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9578
9579 /* disable Rx source address pruning, since we don't expect to
9580 * be receiving external loopback of our transmitted frames.
9581 */
9582 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9583 for (p = 0; p < num_pools; p++) {
9584 if (hw->mac.ops.set_source_address_pruning)
9585 hw->mac.ops.set_source_address_pruning(hw,
9586 false,
9587 p);
9588 }
219efe97
DS		 9589 break;
9590 default:
9591 return -EINVAL;
9592 }
9593
9594 adapter->bridge_mode = mode;
9595
9596 e_info(drv, "enabling bridge mode: %s\n",
9597 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
9598
9599 return 0;
9600}
9601
815cccbf 9602static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 9603 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 9604{
9605 struct ixgbe_adapter *adapter = netdev_priv(dev);
9606 struct nlattr *attr, *br_spec;
9607 int rem;
9608
9609 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9610 return -EOPNOTSUPP;
9611
9612 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 9613 if (!br_spec)
9614 return -EINVAL;
815cccbf
JF		 9615
9616 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 9617 int status;
815cccbf 9618 __u16 mode;
815cccbf
JF		 9619
9620 if (nla_type(attr) != IFLA_BRIDGE_MODE)
9621 continue;
9622
b7c1a314
TG		 9623 if (nla_len(attr) < sizeof(mode))
9624 return -EINVAL;
9625
815cccbf 9626 mode = nla_get_u16(attr);
219efe97
DS		 9627 status = ixgbe_configure_bridge_mode(adapter, mode);
9628 if (status)
9629 return status;
aa2bacb6
DS		 9630
9631 break;
815cccbf
JF		 9632 }
9633
9634 return 0;
9635}
9636
9637static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 9638 struct net_device *dev,
46c264da 9639 u32 filter_mask, int nlflags)
815cccbf
JF		 9640{
9641 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 9642
9643 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9644 return 0;
9645
aa2bacb6 9646 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 9647 adapter->bridge_mode, 0, 0, nlflags,
9648 filter_mask, NULL);
815cccbf
JF		 9649}
9650
2a47fa45
JF		 9651static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
9652{
9653 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
9654 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 9655 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 9656 unsigned int limit;
2a47fa45
JF		 9657 int pool, err;
9658
aac2f1bf
JK		 9659 /* Hardware has a limited number of available pools. Each VF, and the
9660 * PF require a pool. Check to ensure we don't attempt to use more
9661 * then the available number of pools.
9662 */
9663 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
9664 return ERR_PTR(-EINVAL);
9665
219354d4
JF		 9666#ifdef CONFIG_RPS
9667 if (vdev->num_rx_queues != vdev->num_tx_queues) {
9668 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
9669 vdev->name);
9670 return ERR_PTR(-EINVAL);
9671 }
9672#endif
2a47fa45 9673 /* Check for hardware restriction on number of rx/tx queues */
219354d4 9674 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 9675 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
9676 netdev_info(pdev,
9677 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
9678 pdev->name);
9679 return ERR_PTR(-EINVAL);
9680 }
9681
9682 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
9683 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
9684 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
9685 return ERR_PTR(-EBUSY);
9686
bc52f951 9687 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 9688 if (!fwd_adapter)
9689 return ERR_PTR(-ENOMEM);
9690
9691 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
9692 adapter->num_rx_pools++;
9693 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 9694 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 9695
9696 /* Enable VMDq flag so device will be set in VM mode */
9697 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 9698 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 9699 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 9700
9701 /* Force reinit of ring allocation with VMDQ enabled */
9702 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
9703 if (err)
9704 goto fwd_add_err;
9705 fwd_adapter->pool = pool;
9706 fwd_adapter->real_adapter = adapter;
a3b8cb1f
ET		 9707
9708 if (netif_running(pdev)) {
9709 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
9710 if (err)
9711 goto fwd_add_err;
9712 netif_tx_start_all_queues(vdev);
9713 }
9714
2a47fa45
JF		 9715 return fwd_adapter;
9716fwd_add_err:
9717 /* unwind counter and free adapter struct */
9718 netdev_info(pdev,
9719 "%s: dfwd hardware acceleration failed\n", vdev->name);
9720 clear_bit(pool, &adapter->fwd_bitmask);
9721 adapter->num_rx_pools--;
9722 kfree(fwd_adapter);
9723 return ERR_PTR(err);
9724}
9725
9726static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
9727{
9728 struct ixgbe_fwd_adapter *fwd_adapter = priv;
9729 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 9730 unsigned int limit;
2a47fa45
JF		 9731
9732 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
9733 adapter->num_rx_pools--;
9734
51f3773b
JF		 9735 limit = find_last_bit(&adapter->fwd_bitmask, 32);
9736 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 9737 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
9738 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
9739 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
9740 fwd_adapter->pool, adapter->num_rx_pools,
9741 fwd_adapter->rx_base_queue,
9742 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
9743 adapter->fwd_bitmask);
9744 kfree(fwd_adapter);
9745}
9746
b83e3010
AD		 9747#define IXGBE_MAX_MAC_HDR_LEN 127
9748#define IXGBE_MAX_NETWORK_HDR_LEN 511
9749
f467bc06
MR		 9750static netdev_features_t
9751ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
9752 netdev_features_t features)
9753{
b83e3010
AD		 9754 unsigned int network_hdr_len, mac_hdr_len;
9755
9756 /* Make certain the headers can be described by a context descriptor */
9757 mac_hdr_len = skb_network_header(skb) - skb->data;
9758 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
9759 return features & ~(NETIF_F_HW_CSUM |
9760 NETIF_F_SCTP_CRC |
9761 NETIF_F_HW_VLAN_CTAG_TX |
9762 NETIF_F_TSO |
9763 NETIF_F_TSO6);
9764
9765 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
9766 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
9767 return features & ~(NETIF_F_HW_CSUM |
9768 NETIF_F_SCTP_CRC |
9769 NETIF_F_TSO |
9770 NETIF_F_TSO6);
9771
9772 /* We can only support IPV4 TSO in tunnels if we can mangle the
9773 * inner IP ID field, so strip TSO if MANGLEID is not supported.
9774 */
9775 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
9776 features &= ~NETIF_F_TSO;
f467bc06
MR		 9777
9778 return features;
9779}
9780
92470808
JF		 9781static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog)
9782{
9783 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9784 struct ixgbe_adapter *adapter = netdev_priv(dev);
9785 struct bpf_prog *old_prog;
9786
9787 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
9788 return -EINVAL;
9789
9790 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
9791 return -EINVAL;
9792
9793 /* verify ixgbe ring attributes are sufficient for XDP */
9794 for (i = 0; i < adapter->num_rx_queues; i++) {
9795 struct ixgbe_ring *ring = adapter->rx_ring[i];
9796
9797 if (ring_is_rsc_enabled(ring))
9798 return -EINVAL;
9799
9800 if (frame_size > ixgbe_rx_bufsz(ring))
9801 return -EINVAL;
9802 }
9803
33fdc82f
JF		 9804 if (nr_cpu_ids > MAX_XDP_QUEUES)
9805 return -ENOMEM;
9806
92470808 9807 old_prog = xchg(&adapter->xdp_prog, prog);
33fdc82f
JF		 9808
9809 /* If transitioning XDP modes reconfigure rings */
9810 if (!!prog != !!old_prog) {
9811 int err = ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
9812
9813 if (err) {
9814 rcu_assign_pointer(adapter->xdp_prog, old_prog);
9815 return -EINVAL;
9816 }
9817 } else {
9818 for (i = 0; i < adapter->num_rx_queues; i++)
9819 xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog);
9820 }
92470808
JF		 9821
9822 if (old_prog)
9823 bpf_prog_put(old_prog);
9824
9825 return 0;
9826}
9827
9828static int ixgbe_xdp(struct net_device *dev, struct netdev_xdp *xdp)
9829{
9830 struct ixgbe_adapter *adapter = netdev_priv(dev);
9831
9832 switch (xdp->command) {
9833 case XDP_SETUP_PROG:
9834 return ixgbe_xdp_setup(dev, xdp->prog);
9835 case XDP_QUERY_PROG:
9836 xdp->prog_attached = !!(adapter->xdp_prog);
4792093e
MKL		 9837 xdp->prog_id = adapter->xdp_prog ?
9838 adapter->xdp_prog->aux->id : 0;
92470808
JF		 9839 return 0;
9840 default:
9841 return -EINVAL;
9842 }
9843}
9844
64530739
JF		 9845static int ixgbe_xdp_xmit(struct net_device *dev, struct xdp_buff *xdp)
9846{
9847 struct ixgbe_adapter *adapter = netdev_priv(dev);
9848 struct ixgbe_ring *ring;
9849 int err;
9850
9851 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state)))
9852 return -EINVAL;
9853
9854 /* During program transitions its possible adapter->xdp_prog is assigned
9855 * but ring has not been configured yet. In this case simply abort xmit.
9856 */
9857 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL;
9858 if (unlikely(!ring))
9859 return -EINVAL;
9860
9861 err = ixgbe_xmit_xdp_ring(adapter, xdp);
9862 if (err != IXGBE_XDP_TX)
9863 return -ENOMEM;
9864
11393cc9
JF		 9865 return 0;
9866}
9867
9868static void ixgbe_xdp_flush(struct net_device *dev)
9869{
9870 struct ixgbe_adapter *adapter = netdev_priv(dev);
9871 struct ixgbe_ring *ring;
9872
9873 /* Its possible the device went down between xdp xmit and flush so
9874 * we need to ensure device is still up.
9875 */
9876 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state)))
9877 return;
9878
9879 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL;
9880 if (unlikely(!ring))
9881 return;
9882
64530739
JF		 9883 /* Force memory writes to complete before letting h/w know there
9884 * are new descriptors to fetch.
9885 */
9886 wmb();
64530739
JF		 9887 writel(ring->next_to_use, ring->tail);
9888
11393cc9 9889 return;
64530739
JF		 9890}
9891
0edc3527 9892static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 9893 .ndo_open = ixgbe_open,
0edc3527 9894 .ndo_stop = ixgbe_close,
00829823 9895 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 9896 .ndo_select_queue = ixgbe_select_queue,
581330ba 9897 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 9898 .ndo_validate_addr = eth_validate_addr,
9899 .ndo_set_mac_address = ixgbe_set_mac,
9900 .ndo_change_mtu = ixgbe_change_mtu,
9901 .ndo_tx_timeout = ixgbe_tx_timeout,
c04f90e5 9902 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
0edc3527
SH		 9903 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
9904 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 9905 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 9906 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
9907 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 9908 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 9909 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 9910 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 9911 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 9912 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 9913 .ndo_get_stats64 = ixgbe_get_stats64,
e4c6734e 9914 .ndo_setup_tc = __ixgbe_setup_tc,
0edc3527
SH		 9915#ifdef CONFIG_NET_POLL_CONTROLLER
9916 .ndo_poll_controller = ixgbe_netpoll,
9917#endif
332d4a7d
YZ		 9918#ifdef IXGBE_FCOE
9919 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 9920 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 9921 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 9922 .ndo_fcoe_enable = ixgbe_fcoe_enable,
9923 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 9924 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 9925 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 9926#endif /* IXGBE_FCOE */
082757af
DS		 9927 .ndo_set_features = ixgbe_set_features,
9928 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 9929 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 9930 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
9931 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 9932 .ndo_dfwd_add_station = ixgbe_fwd_add,
9933 .ndo_dfwd_del_station = ixgbe_fwd_del,
a21d0822
ET		 9934 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port,
9935 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port,
f467bc06 9936 .ndo_features_check = ixgbe_features_check,
92470808 9937 .ndo_xdp = ixgbe_xdp,
64530739 9938 .ndo_xdp_xmit = ixgbe_xdp_xmit,
11393cc9 9939 .ndo_xdp_flush = ixgbe_xdp_flush,
0edc3527
SH		 9940};
9941
e027d1ae
JK		 9942/**
9943 * ixgbe_enumerate_functions - Get the number of ports this device has
9944 * @adapter: adapter structure
9945 *
9946 * This function enumerates the phsyical functions co-located on a single slot,
9947 * in order to determine how many ports a device has. This is most useful in
9948 * determining the required GT/s of PCIe bandwidth necessary for optimal
9949 * performance.
9950 **/
9951static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
9952{
caafb95d 9953 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 9954 int physfns = 0;
9955
f1f96579
JK		 9956 /* Some cards can not use the generic count PCIe functions method,
9957 * because they are behind a parent switch, so we hardcode these with
9958 * the correct number of functions.
e027d1ae 9959 */
8818970d 9960 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 9961 physfns = 4;
8818970d
JK		 9962
9963 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
9964 /* don't count virtual functions */
caafb95d
JK		 9965 if (entry->is_virtfn)
9966 continue;
9967
9968 /* When the devices on the bus don't all match our device ID,
9969 * we can't reliably determine the correct number of
9970 * functions. This can occur if a function has been direct
9971 * attached to a virtual machine using VT-d, for example. In
9972 * this case, simply return -1 to indicate this.
9973 */
9974 if ((entry->vendor != pdev->vendor) ||
9975 (entry->device != pdev->device))
9976 return -1;
9977
9978 physfns++;
e027d1ae
JK		 9979 }
9980
9981 return physfns;
9982}
9983
8e2813f5
JK		 9984/**
9985 * ixgbe_wol_supported - Check whether device supports WoL
740234f0 9986 * @adapter: the adapter private structure
8e2813f5
JK		 9987 * @device_id: the device ID
9988 * @subdev_id: the subsystem device ID
9989 *
9990 * This function is used by probe and ethtool to determine
9991 * which devices have WoL support
9992 *
9993 **/
740234f0
ET		 9994bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
9995 u16 subdevice_id)
8e2813f5
JK		 9996{
9997 struct ixgbe_hw *hw = &adapter->hw;
9998 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8e2813f5 9999
740234f0
ET		 10000 /* WOL not supported on 82598 */
10001 if (hw->mac.type == ixgbe_mac_82598EB)
10002 return false;
10003
10004 /* check eeprom to see if WOL is enabled for X540 and newer */
10005 if (hw->mac.type >= ixgbe_mac_X540) {
10006 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
10007 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
10008 (hw->bus.func == 0)))
10009 return true;
10010 }
10011
10012 /* WOL is determined based on device IDs for 82599 MACs */
8e2813f5
JK		 10013 switch (device_id) {
10014 case IXGBE_DEV_ID_82599_SFP:
10015 /* Only these subdevices could supports WOL */
10016 switch (subdevice_id) {
10017 case IXGBE_SUBDEV_ID_82599_560FLR:
00103a6c
ET		 10018 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
10019 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
10020 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
8e2813f5
JK		 10021 /* only support first port */
10022 if (hw->bus.func != 0)
10023 break;
93df9465 10024 /* fall through */
5700ff26 10025 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 10026 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 10027 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 10028 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
00103a6c
ET		 10029 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
10030 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
10031 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
740234f0 10032 return true;
8e2813f5
JK		 10033 }
10034 break;
5daebbb0 10035 case IXGBE_DEV_ID_82599EN_SFP:
740234f0 10036 /* Only these subdevices support WOL */
5daebbb0
DS		 10037 switch (subdevice_id) {
10038 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
740234f0 10039 return true;
5daebbb0
DS		 10040 }
10041 break;
8e2813f5
JK		 10042 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
10043 /* All except this subdevice support WOL */
10044 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
740234f0 10045 return true;
8e2813f5
JK		 10046 break;
10047 case IXGBE_DEV_ID_82599_KX4:
740234f0
ET		 10048 return true;
10049 default:
8e2813f5
JK		 10050 break;
10051 }
10052
740234f0 10053 return false;
8e2813f5
JK		 10054}
10055
9a799d71
AK		 10056/**
10057 * ixgbe_probe - Device Initialization Routine
10058 * @pdev: PCI device information struct
10059 * @ent: entry in ixgbe_pci_tbl
10060 *
10061 * Returns 0 on success, negative on failure
10062 *
10063 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
10064 * The OS initialization, configuring of the adapter private structure,
10065 * and a hardware reset occur.
10066 **/
1dd06ae8 10067static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 10068{
10069 struct net_device *netdev;
10070 struct ixgbe_adapter *adapter = NULL;
10071 struct ixgbe_hw *hw;
10072 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 10073 int i, err, pci_using_dac, expected_gts;
d3cb9869 10074 unsigned int indices = MAX_TX_QUEUES;
289700db 10075 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 10076 bool disable_dev = false;
eacd73f7
YZ		 10077#ifdef IXGBE_FCOE
10078 u16 device_caps;
10079#endif
289700db 10080 u32 eec;
9a799d71 10081
bded64a7
AG		 10082 /* Catch broken hardware that put the wrong VF device ID in
10083 * the PCIe SR-IOV capability.
10084 */
10085 if (pdev->is_virtfn) {
10086 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
10087 pci_name(pdev), pdev->vendor, pdev->device);
10088 return -EINVAL;
10089 }
10090
9ce77666 10091 err = pci_enable_device_mem(pdev);
9a799d71
AK		 10092 if (err)
10093 return err;
10094
f5f2eda8 10095 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 10096 pci_using_dac = 1;
10097 } else {
f5f2eda8 10098 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 10099 if (err) {
f5f2eda8
RK		 10100 dev_err(&pdev->dev,
10101 "No usable DMA configuration, aborting\n");
10102 goto err_dma;
9a799d71
AK		 10103 }
10104 pci_using_dac = 0;
10105 }
10106
56d766d6 10107 err = pci_request_mem_regions(pdev, ixgbe_driver_name);
9a799d71 10108 if (err) {
b8bc0421
DC		 10109 dev_err(&pdev->dev,
10110 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 10111 goto err_pci_reg;
10112 }
10113
19d5afd4 10114 pci_enable_pcie_error_reporting(pdev);
6fabd715 10115
9a799d71 10116 pci_set_master(pdev);
fb3b27bc 10117 pci_save_state(pdev);
9a799d71 10118
d3cb9869 10119 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 10120#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 10121 /* 8 TC w/ 4 queues per TC */
10122 indices = 4 * MAX_TRAFFIC_CLASS;
10123#else
10124 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 10125#endif
d3cb9869 10126 }
e901acd6 10127
c85a2618 10128 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 10129 if (!netdev) {
10130 err = -ENOMEM;
10131 goto err_alloc_etherdev;
10132 }
10133
9a799d71
AK		 10134 SET_NETDEV_DEV(netdev, &pdev->dev);
10135
9a799d71
AK		 10136 adapter = netdev_priv(netdev);
10137
10138 adapter->netdev = netdev;
10139 adapter->pdev = pdev;
10140 hw = &adapter->hw;
10141 hw->back = adapter;
b3f4d599 10142 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 10143
05857980 10144 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 10145 pci_resource_len(pdev, 0));
2a1a091c 10146 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 10147 if (!hw->hw_addr) {
10148 err = -EIO;
10149 goto err_ioremap;
10150 }
10151
0edc3527 10152 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 10153 ixgbe_set_ethtool_ops(netdev);
9a799d71 10154 netdev->watchdog_timeo = 5 * HZ;
339de30f 10155 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 10156
9a799d71 10157 /* Setup hw api */
37689010 10158 hw->mac.ops = *ii->mac_ops;
021230d4 10159 hw->mac.type = ii->mac;
9a900eca 10160 hw->mvals = ii->mvals;
b71f6c40
ET		 10161 if (ii->link_ops)
10162 hw->link.ops = *ii->link_ops;
9a799d71 10163
c44ade9e 10164 /* EEPROM */
37689010 10165 hw->eeprom.ops = *ii->eeprom_ops;
9a900eca 10166 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 10167 if (ixgbe_removed(hw->hw_addr)) {
10168 err = -EIO;
10169 goto err_ioremap;
10170 }
c44ade9e 10171 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
b4f47a48 10172 if (!(eec & BIT(8)))
c44ade9e
JB		 10173 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
10174
10175 /* PHY */
37689010 10176 hw->phy.ops = *ii->phy_ops;
c4900be0 10177 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 10178 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
10179 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
10180 hw->phy.mdio.mmds = 0;
10181 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10182 hw->phy.mdio.dev = netdev;
10183 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
10184 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 10185
9a799d71 10186 /* setup the private structure */
55570b6f 10187 err = ixgbe_sw_init(adapter, ii);
9a799d71
AK		 10188 if (err)
10189 goto err_sw_init;
10190
dbd15b8f
DS		 10191 /* Make sure the SWFW semaphore is in a valid state */
10192 if (hw->mac.ops.init_swfw_sync)
10193 hw->mac.ops.init_swfw_sync(hw);
10194
e86bff0e 10195 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 10196 switch (adapter->hw.mac.type) {
10197 case ixgbe_mac_82599EB:
10198 case ixgbe_mac_X540:
9a75a1ac
DS		 10199 case ixgbe_mac_X550:
10200 case ixgbe_mac_X550EM_x:
49425dfc 10201 case ixgbe_mac_x550em_a:
e86bff0e 10202 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 10203 break;
10204 default:
10205 break;
10206 }
e86bff0e 10207
bf069c97
DS		 10208 /*
10209 * If there is a fan on this device and it has failed log the
10210 * failure.
10211 */
10212 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
10213 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
10214 if (esdp & IXGBE_ESDP_SDP1)
396e799c 10215 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 10216 }
10217
8ef78adc
PWJ		 10218 if (allow_unsupported_sfp)
10219 hw->allow_unsupported_sfp = allow_unsupported_sfp;
10220
c44ade9e 10221 /* reset_hw fills in the perm_addr as well */
119fc60a 10222 hw->phy.reset_if_overtemp = true;
c44ade9e 10223 err = hw->mac.ops.reset_hw(hw);
119fc60a 10224 hw->phy.reset_if_overtemp = false;
b3eb4e18 10225 ixgbe_set_eee_capable(adapter);
29a8dca1 10226 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 10227 err = 0;
10228 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 10229 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
10230 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 10231 goto err_sw_init;
10232 } else if (err) {
849c4542 10233 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 10234 goto err_sw_init;
10235 }
10236
99d74487 10237#ifdef CONFIG_PCI_IOV
60a1a680
GR		 10238 /* SR-IOV not supported on the 82598 */
10239 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
10240 goto skip_sriov;
10241 /* Mailbox */
10242 ixgbe_init_mbx_params_pf(hw);
37689010 10243 hw->mbx.ops = ii->mbx_ops;
dcc23e3a 10244 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
5c11f00d 10245 ixgbe_enable_sriov(adapter, max_vfs);
60a1a680 10246skip_sriov:
1cdd1ec8 10247
99d74487 10248#endif
396e799c 10249 netdev->features = NETIF_F_SG |
082757af
DS		 10250 NETIF_F_TSO |
10251 NETIF_F_TSO6 |
082757af 10252 NETIF_F_RXHASH |
49763de0 10253 NETIF_F_RXCSUM |
b83e3010
AD		 10254 NETIF_F_HW_CSUM;
10255
10256#define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
10257 NETIF_F_GSO_GRE_CSUM | \
7e13318d 10258 NETIF_F_GSO_IPXIP4 | \
bf2d1df3 10259 NETIF_F_GSO_IPXIP6 | \
b83e3010
AD		 10260 NETIF_F_GSO_UDP_TUNNEL | \
10261 NETIF_F_GSO_UDP_TUNNEL_CSUM)
10262
10263 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
10264 netdev->features |= NETIF_F_GSO_PARTIAL |
10265 IXGBE_GSO_PARTIAL_FEATURES;
ad31c402 10266
49763de0 10267 if (hw->mac.type >= ixgbe_mac_82599EB)
53692b1d 10268 netdev->features |= NETIF_F_SCTP_CRC;
49763de0
AD		 10269
10270 /* copy netdev features into list of user selectable features */
b83e3010 10271 netdev->hw_features |= netdev->features |
3d951822 10272 NETIF_F_HW_VLAN_CTAG_FILTER |
b83e3010
AD		 10273 NETIF_F_HW_VLAN_CTAG_RX |
10274 NETIF_F_HW_VLAN_CTAG_TX |
10275 NETIF_F_RXALL |
49763de0
AD		 10276 NETIF_F_HW_L2FW_DOFFLOAD;
10277
10278 if (hw->mac.type >= ixgbe_mac_82599EB)
10279 netdev->hw_features |= NETIF_F_NTUPLE |
b82b17d9 10280 NETIF_F_HW_TC;
45a5ead0 10281
b83e3010
AD		 10282 if (pci_using_dac)
10283 netdev->features |= NETIF_F_HIGHDMA;
10284
5eee87cd
AD		 10285 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
10286 netdev->hw_enc_features |= netdev->vlan_features;
2a20525b
SP		 10287 netdev->mpls_features |= NETIF_F_SG |
10288 NETIF_F_TSO |
10289 NETIF_F_TSO6 |
10290 NETIF_F_HW_CSUM;
10291 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES;
5eee87cd 10292
b83e3010
AD		 10293 /* set this bit last since it cannot be part of vlan_features */
10294 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
10295 NETIF_F_HW_VLAN_CTAG_RX |
10296 NETIF_F_HW_VLAN_CTAG_TX;
ad31c402 10297
01789349 10298 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 10299 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 10300
91c527a5
JW		 10301 /* MTU range: 68 - 9710 */
10302 netdev->min_mtu = ETH_MIN_MTU;
10303 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
10304
7a6b6f51 10305#ifdef CONFIG_IXGBE_DCB
8829009d 10306 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
3f40c74c 10307 netdev->dcbnl_ops = &ixgbe_dcbnl_ops;
2f90b865
AD		 10308#endif
10309
eacd73f7 10310#ifdef IXGBE_FCOE
0d551589 10311 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 10312 unsigned int fcoe_l;
10313
eacd73f7
YZ		 10314 if (hw->mac.ops.get_device_caps) {
10315 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 10316 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
10317 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 10318 }
7c8ae65a 10319
d3cb9869
AD		 10320
10321 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
10322 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 10323
a58915c7
AD		 10324 netdev->features |= NETIF_F_FSO |
10325 NETIF_F_FCOE_CRC;
10326
7c8ae65a
AD		 10327 netdev->vlan_features |= NETIF_F_FSO |
10328 NETIF_F_FCOE_CRC |
10329 NETIF_F_FCOE_MTU;
5e09d7f6 10330 }
eacd73f7 10331#endif /* IXGBE_FCOE */
9a799d71 10332
082757af
DS		 10333 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
10334 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 10335 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 10336 netdev->features |= NETIF_F_LRO;
10337
9a799d71 10338 /* make sure the EEPROM is good */
c44ade9e 10339 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 10340 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 10341 err = -EIO;
35937c05 10342 goto err_sw_init;
9a799d71
AK		 10343 }
10344
c7374b5a
SV		 10345 eth_platform_get_mac_address(&adapter->pdev->dev,
10346 adapter->hw.mac.perm_addr);
c762dff2 10347
9a799d71 10348 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 10349
aaeb6cdf 10350 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 10351 e_dev_err("invalid MAC address\n");
9a799d71 10352 err = -EIO;
35937c05 10353 goto err_sw_init;
9a799d71
AK		 10354 }
10355
56768045
TD		 10356 /* Set hw->mac.addr to permanent MAC address */
10357 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
c9f53e63 10358 ixgbe_mac_set_default_filter(adapter);
5d7daa35 10359
7086400d 10360 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 10361 (unsigned long) adapter);
9a799d71 10362
58cf663f
MR		 10363 if (ixgbe_removed(hw->hw_addr)) {
10364 err = -EIO;
10365 goto err_sw_init;
10366 }
7086400d 10367 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 10368 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 10369 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 10370
021230d4
AV		 10371 err = ixgbe_init_interrupt_scheme(adapter);
10372 if (err)
10373 goto err_sw_init;
9a799d71 10374
b09457e7
LS		 10375 for (i = 0; i < adapter->num_rx_queues; i++)
10376 u64_stats_init(&adapter->rx_ring[i]->syncp);
10377 for (i = 0; i < adapter->num_tx_queues; i++)
10378 u64_stats_init(&adapter->tx_ring[i]->syncp);
33fdc82f
JF		 10379 for (i = 0; i < adapter->num_xdp_queues; i++)
10380 u64_stats_init(&adapter->xdp_ring[i]->syncp);
10381
8e2813f5 10382 /* WOL not supported for all devices */
c23f5b6b 10383 adapter->wol = 0;
8e2813f5 10384 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 10385 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 10386 pdev->subsystem_device);
6b92b0ba 10387 if (hw->wol_enabled)
9417c464 10388 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 10389
e8e26350
PW		 10390 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
10391
15e5209f
ET		 10392 /* save off EEPROM version number */
10393 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
10394 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
10395
04f165ef 10396 /* pick up the PCI bus settings for reporting later */
e027d1ae 10397 if (ixgbe_pcie_from_parent(hw))
b8e82001 10398 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 10399 else
10400 hw->mac.ops.get_bus_info(hw);
04f165ef 10401
e027d1ae
JK		 10402 /* calculate the expected PCIe bandwidth required for optimal
10403 * performance. Note that some older parts will never have enough
10404 * bandwidth due to being older generation PCIe parts. We clamp these
10405 * parts to ensure no warning is displayed if it can't be fixed.
10406 */
10407 switch (hw->mac.type) {
10408 case ixgbe_mac_82598EB:
10409 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
10410 break;
10411 default:
10412 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
10413 break;
0c254d86 10414 }
caafb95d
JK		 10415
10416 /* don't check link if we failed to enumerate functions */
10417 if (expected_gts > 0)
10418 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 10419
339de30f 10420 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 10421 if (err)
339de30f 10422 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 10423 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
10424 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
10425 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 10426 part_str);
6a2aae5a
JK		 10427 else
10428 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
10429 hw->mac.type, hw->phy.type, part_str);
10430
10431 e_dev_info("%pM\n", netdev->dev_addr);
10432
9a799d71 10433 /* reset the hardware with the new settings */
794caeb2 10434 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 10435 if (err == IXGBE_ERR_EEPROM_VERSION) {
10436 /* We are running on a pre-production device, log a warning */
849c4542
ET		 10437 e_dev_warn("This device is a pre-production adapter/LOM. "
10438 "Please be aware there may be issues associated "
10439 "with your hardware. If you are experiencing "
10440 "problems please contact your Intel or hardware "
10441 "representative who provided you with this "
10442 "hardware.\n");
794caeb2 10443 }
9a799d71 10444 strcpy(netdev->name, "eth%d");
a09c0fc3 10445 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 10446 err = register_netdev(netdev);
10447 if (err)
10448 goto err_register;
10449
0fb6a55c 10450
ec74a471
ET		 10451 /* power down the optics for 82599 SFP+ fiber */
10452 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 10453 hw->mac.ops.disable_tx_laser(hw);
10454
54386467
JB		 10455 /* carrier off reporting is important to ethtool even BEFORE open */
10456 netif_carrier_off(netdev);
10457
5dd2d332 10458#ifdef CONFIG_IXGBE_DCA
652f093f 10459 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 10460 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 10461 ixgbe_setup_dca(adapter);
10462 }
10463#endif
1cdd1ec8 10464 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 10465 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 10466 for (i = 0; i < adapter->num_vfs; i++)
10467 ixgbe_vf_configuration(pdev, (i | 0x10000000));
10468 }
10469
2466dd9c
JK		 10470 /* firmware requires driver version to be 0xFFFFFFFF
10471 * since os does not support feature
10472 */
9612de92 10473 if (hw->mac.ops.set_fw_drv_ver)
cb8e0514
TN		 10474 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF,
10475 sizeof(ixgbe_driver_version) - 1,
10476 ixgbe_driver_version);
9612de92 10477
0365e6e4
PW		 10478 /* add san mac addr to netdev */
10479 ixgbe_add_sanmac_netdev(netdev);
9a799d71 10480
ea81875a 10481 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 10482
1210982b 10483#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 10484 if (ixgbe_sysfs_init(adapter))
10485 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 10486#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 10487
00949167 10488 ixgbe_dbg_adapter_init(adapter);
00949167 10489
d1a35ee2
ET		 10490 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
10491 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 10492 hw->mac.ops.setup_link(hw,
10493 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
10494 true);
10495
9a799d71
AK		 10496 return 0;
10497
10498err_register:
5eba3699 10499 ixgbe_release_hw_control(adapter);
7a921c93 10500 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 10501err_sw_init:
99d74487 10502 ixgbe_disable_sriov(adapter);
7086400d 10503 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 10504 iounmap(adapter->io_addr);
1cdaaf54 10505 kfree(adapter->jump_tables[0]);
5d7daa35 10506 kfree(adapter->mac_table);
3dfbfc7e 10507 kfree(adapter->rss_key);
9a799d71 10508err_ioremap:
b5b2ffc0 10509 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 10510 free_netdev(netdev);
10511err_alloc_etherdev:
56d766d6 10512 pci_release_mem_regions(pdev);
9a799d71
AK		 10513err_pci_reg:
10514err_dma:
b5b2ffc0 10515 if (!adapter || disable_dev)
41c62843 10516 pci_disable_device(pdev);
9a799d71
AK		 10517 return err;
10518}
10519
10520/**
10521 * ixgbe_remove - Device Removal Routine
10522 * @pdev: PCI device information struct
10523 *
10524 * ixgbe_remove is called by the PCI subsystem to alert the driver
10525 * that it should release a PCI device. The could be caused by a
10526 * Hot-Plug event, or because the driver is going to be removed from
10527 * memory.
10528 **/
9f9a12f8 10529static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 10530{
c60fbb00 10531 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 10532 struct net_device *netdev;
b5b2ffc0 10533 bool disable_dev;
1cdaaf54 10534 int i;
9a799d71 10535
0fb6a55c
ET		 10536 /* if !adapter then we already cleaned up in probe */
10537 if (!adapter)
10538 return;
10539
10540 netdev = adapter->netdev;
00949167 10541 ixgbe_dbg_adapter_exit(adapter);
00949167 10542
09f40aed 10543 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 10544 cancel_work_sync(&adapter->service_task);
9a799d71 10545
3a6a4eda 10546
5dd2d332 10547#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 10548 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
10549 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
10550 dca_remove_requester(&pdev->dev);
9de7605e
MR		 10551 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
10552 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 10553 }
10554
10555#endif
1210982b 10556#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 10557 ixgbe_sysfs_exit(adapter);
1210982b 10558#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 10559
0365e6e4
PW		 10560 /* remove the added san mac */
10561 ixgbe_del_sanmac_netdev(netdev);
10562
da36b647 10563#ifdef CONFIG_PCI_IOV
7837e286 10564 ixgbe_disable_sriov(adapter);
da36b647 10565#endif
6b010e9b
AW		 10566 if (netdev->reg_state == NETREG_REGISTERED)
10567 unregister_netdev(netdev);
10568
7a921c93 10569 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 10570
021230d4 10571 ixgbe_release_hw_control(adapter);
9a799d71 10572
2b1588c3
AD		 10573#ifdef CONFIG_DCB
10574 kfree(adapter->ixgbe_ieee_pfc);
10575 kfree(adapter->ixgbe_ieee_ets);
10576
10577#endif
2a1a091c 10578 iounmap(adapter->io_addr);
56d766d6 10579 pci_release_mem_regions(pdev);
9a799d71 10580
849c4542 10581 e_dev_info("complete\n");
021230d4 10582
1cdaaf54
AN		 10583 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
10584 if (adapter->jump_tables[i]) {
10585 kfree(adapter->jump_tables[i]->input);
10586 kfree(adapter->jump_tables[i]->mask);
10587 }
10588 kfree(adapter->jump_tables[i]);
10589 }
10590
5d7daa35 10591 kfree(adapter->mac_table);
3dfbfc7e 10592 kfree(adapter->rss_key);
b5b2ffc0 10593 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 10594 free_netdev(netdev);
10595
19d5afd4 10596 pci_disable_pcie_error_reporting(pdev);
6fabd715 10597
b5b2ffc0 10598 if (disable_dev)
41c62843 10599 pci_disable_device(pdev);
9a799d71
AK		 10600}
10601
10602/**
10603 * ixgbe_io_error_detected - called when PCI error is detected
10604 * @pdev: Pointer to PCI device
10605 * @state: The current pci connection state
10606 *
10607 * This function is called after a PCI bus error affecting
10608 * this device has been detected.
10609 */
10610static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 10611 pci_channel_state_t state)
9a799d71 10612{
c60fbb00
AD		 10613 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
10614 struct net_device *netdev = adapter->netdev;
9a799d71 10615
83c61fa9 10616#ifdef CONFIG_PCI_IOV
14438464 10617 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 10618 struct pci_dev *bdev, *vfdev;
10619 u32 dw0, dw1, dw2, dw3;
10620 int vf, pos;
10621 u16 req_id, pf_func;
10622
10623 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
10624 adapter->num_vfs == 0)
10625 goto skip_bad_vf_detection;
10626
10627 bdev = pdev->bus->self;
62f87c0e 10628 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 10629 bdev = bdev->bus->self;
10630
10631 if (!bdev)
10632 goto skip_bad_vf_detection;
10633
10634 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
10635 if (!pos)
10636 goto skip_bad_vf_detection;
10637
14438464
MR		 10638 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
10639 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
10640 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
10641 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
10642 if (ixgbe_removed(hw->hw_addr))
10643 goto skip_bad_vf_detection;
83c61fa9
GR		 10644
10645 req_id = dw1 >> 16;
10646 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
10647 if (!(req_id & 0x0080))
10648 goto skip_bad_vf_detection;
10649
10650 pf_func = req_id & 0x01;
10651 if ((pf_func & 1) == (pdev->devfn & 1)) {
10652 unsigned int device_id;
10653
10654 vf = (req_id & 0x7F) >> 1;
10655 e_dev_err("VF %d has caused a PCIe error\n", vf);
10656 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
10657 "%8.8x\tdw3: %8.8x\n",
10658 dw0, dw1, dw2, dw3);
10659 switch (adapter->hw.mac.type) {
10660 case ixgbe_mac_82599EB:
10661 device_id = IXGBE_82599_VF_DEVICE_ID;
10662 break;
10663 case ixgbe_mac_X540:
10664 device_id = IXGBE_X540_VF_DEVICE_ID;
10665 break;
9a75a1ac
DS		 10666 case ixgbe_mac_X550:
10667 device_id = IXGBE_DEV_ID_X550_VF;
10668 break;
10669 case ixgbe_mac_X550EM_x:
10670 device_id = IXGBE_DEV_ID_X550EM_X_VF;
10671 break;
49425dfc
MR		 10672 case ixgbe_mac_x550em_a:
10673 device_id = IXGBE_DEV_ID_X550EM_A_VF;
10674 break;
83c61fa9
GR		 10675 default:
10676 device_id = 0;
10677 break;
10678 }
10679
10680 /* Find the pci device of the offending VF */
36e90319 10681 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 10682 while (vfdev) {
10683 if (vfdev->devfn == (req_id & 0xFF))
10684 break;
36e90319 10685 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 10686 device_id, vfdev);
10687 }
10688 /*
10689 * There's a slim chance the VF could have been hot plugged,
10690 * so if it is no longer present we don't need to issue the
10691 * VFLR. Just clean up the AER in that case.
10692 */
10693 if (vfdev) {
63af8f7a 10694 pcie_flr(vfdev);
b4fafbe9
GR		 10695 /* Free device reference count */
10696 pci_dev_put(vfdev);
83c61fa9
GR		 10697 }
10698
10699 pci_cleanup_aer_uncorrect_error_status(pdev);
10700 }
10701
10702 /*
10703 * Even though the error may have occurred on the other port
10704 * we still need to increment the vf error reference count for
10705 * both ports because the I/O resume function will be called
10706 * for both of them.
10707 */
10708 adapter->vferr_refcount++;
10709
10710 return PCI_ERS_RESULT_RECOVERED;
10711
10712skip_bad_vf_detection:
10713#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 10714 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
10715 return PCI_ERS_RESULT_DISCONNECT;
10716
41c62843 10717 rtnl_lock();
9a799d71
AK		 10718 netif_device_detach(netdev);
10719
41c62843
MR		 10720 if (state == pci_channel_io_perm_failure) {
10721 rtnl_unlock();
3044b8d1 10722 return PCI_ERS_RESULT_DISCONNECT;
41c62843 10723 }
3044b8d1 10724
9a799d71 10725 if (netif_running(netdev))
126db13f 10726 ixgbe_close_suspend(adapter);
41c62843
MR		 10727
10728 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
10729 pci_disable_device(pdev);
10730 rtnl_unlock();
9a799d71 10731
b4617240 10732 /* Request a slot reset. */
9a799d71
AK		 10733 return PCI_ERS_RESULT_NEED_RESET;
10734}
10735
10736/**
10737 * ixgbe_io_slot_reset - called after the pci bus has been reset.
10738 * @pdev: Pointer to PCI device
10739 *
10740 * Restart the card from scratch, as if from a cold-boot.
10741 */
10742static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
10743{
c60fbb00 10744 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 10745 pci_ers_result_t result;
10746 int err;
9a799d71 10747
9ce77666 10748 if (pci_enable_device_mem(pdev)) {
396e799c 10749 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 10750 result = PCI_ERS_RESULT_DISCONNECT;
10751 } else {
4e857c58 10752 smp_mb__before_atomic();
41c62843 10753 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 10754 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 10755 pci_set_master(pdev);
10756 pci_restore_state(pdev);
c0e1f68b 10757 pci_save_state(pdev);
9a799d71 10758
dd4d8ca6 10759 pci_wake_from_d3(pdev, false);
9a799d71 10760
6fabd715 10761 ixgbe_reset(adapter);
88512539 10762 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 10763 result = PCI_ERS_RESULT_RECOVERED;
10764 }
10765
10766 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10767 if (err) {
849c4542
ET		 10768 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
10769 "failed 0x%0x\n", err);
6fabd715
PWJ		 10770 /* non-fatal, continue */
10771 }
9a799d71 10772
6fabd715 10773 return result;
9a799d71
AK		 10774}
10775
10776/**
10777 * ixgbe_io_resume - called when traffic can start flowing again.
10778 * @pdev: Pointer to PCI device
10779 *
10780 * This callback is called when the error recovery driver tells us that
10781 * its OK to resume normal operation.
10782 */
10783static void ixgbe_io_resume(struct pci_dev *pdev)
10784{
c60fbb00
AD		 10785 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
10786 struct net_device *netdev = adapter->netdev;
9a799d71 10787
83c61fa9
GR		 10788#ifdef CONFIG_PCI_IOV
10789 if (adapter->vferr_refcount) {
10790 e_info(drv, "Resuming after VF err\n");
10791 adapter->vferr_refcount--;
10792 return;
10793 }
10794
10795#endif
126db13f 10796 rtnl_lock();
c7ccde0f 10797 if (netif_running(netdev))
126db13f 10798 ixgbe_open(netdev);
9a799d71
AK		 10799
10800 netif_device_attach(netdev);
126db13f 10801 rtnl_unlock();
9a799d71
AK		 10802}
10803
3646f0e5 10804static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 10805 .error_detected = ixgbe_io_error_detected,
10806 .slot_reset = ixgbe_io_slot_reset,
10807 .resume = ixgbe_io_resume,
10808};
10809
10810static struct pci_driver ixgbe_driver = {
10811 .name = ixgbe_driver_name,
10812 .id_table = ixgbe_pci_tbl,
10813 .probe = ixgbe_probe,
9f9a12f8 10814 .remove = ixgbe_remove,
9a799d71
AK		 10815#ifdef CONFIG_PM
10816 .suspend = ixgbe_suspend,
10817 .resume = ixgbe_resume,
10818#endif
10819 .shutdown = ixgbe_shutdown,
da36b647 10820 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 10821 .err_handler = &ixgbe_err_handler
10822};
10823
10824/**
10825 * ixgbe_init_module - Driver Registration Routine
10826 *
10827 * ixgbe_init_module is the first routine called when the driver is
10828 * loaded. All it does is register with the PCI subsystem.
10829 **/
10830static int __init ixgbe_init_module(void)
10831{
10832 int ret;
c7689578 10833 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 10834 pr_info("%s\n", ixgbe_copyright);
9a799d71 10835
780484d8
MR		 10836 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
10837 if (!ixgbe_wq) {
10838 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
10839 return -ENOMEM;
10840 }
10841
00949167 10842 ixgbe_dbg_init();
00949167 10843
f01fc1a8
JK		 10844 ret = pci_register_driver(&ixgbe_driver);
10845 if (ret) {
6b836879 10846 destroy_workqueue(ixgbe_wq);
f01fc1a8 10847 ixgbe_dbg_exit();
f01fc1a8
JK		 10848 return ret;
10849 }
10850
5dd2d332 10851#ifdef CONFIG_IXGBE_DCA
bd0362dd 10852 dca_register_notify(&dca_notifier);
bd0362dd 10853#endif
5dd2d332 10854
f01fc1a8 10855 return 0;
9a799d71 10856}
b4617240 10857
9a799d71
AK		 10858module_init(ixgbe_init_module);
10859
10860/**
10861 * ixgbe_exit_module - Driver Exit Cleanup Routine
10862 *
10863 * ixgbe_exit_module is called just before the driver is removed
10864 * from memory.
10865 **/
10866static void __exit ixgbe_exit_module(void)
10867{
5dd2d332 10868#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 10869 dca_unregister_notify(&dca_notifier);
10870#endif
9a799d71 10871 pci_unregister_driver(&ixgbe_driver);
00949167 10872
00949167 10873 ixgbe_dbg_exit();
780484d8
MR		 10874 if (ixgbe_wq) {
10875 destroy_workqueue(ixgbe_wq);
10876 ixgbe_wq = NULL;
10877 }
9a799d71 10878}
bd0362dd 10879
5dd2d332 10880#ifdef CONFIG_IXGBE_DCA
bd0362dd 10881static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 10882 void *p)
bd0362dd
JC		 10883{
10884 int ret_val;
10885
10886 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 10887 __ixgbe_notify_dca);
bd0362dd
JC		 10888
10889 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
10890}
b453368d 10891
5dd2d332 10892#endif /* CONFIG_IXGBE_DCA */
849c4542 10893
9a799d71
AK		 10894module_exit(ixgbe_exit_module);
10895
10896/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)