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ixgbe: ixgbe_atr() should access udp_hdr(skb) only for UDP packets
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
37689010 4 Copyright(c) 1999 - 2016 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
b3a49557 53#include <net/udp_tunnel.h>
b82b17d9
JF		 54#include <net/pkt_cls.h>
55#include <net/tc_act/tc_gact.h>
947f8a45 56#include <net/tc_act/tc_mirred.h>
9a799d71
AK		 57
58#include "ixgbe.h"
59#include "ixgbe_common.h"
ee5f784a 60#include "ixgbe_dcb_82599.h"
1cdd1ec8 61#include "ixgbe_sriov.h"
b82b17d9 62#include "ixgbe_model.h"
9a799d71
AK		 63
64char ixgbe_driver_name[] = "ixgbe";
9c8eb720 65static const char ixgbe_driver_string[] =
e8e9f696 66 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 67#ifdef IXGBE_FCOE
ea81875a
NP		 68char ixgbe_default_device_descr[] =
69 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 70#else
71static char ixgbe_default_device_descr[] =
72 "Intel(R) 10 Gigabit Network Connection";
73#endif
10ef00fe 74#define DRV_VERSION "4.4.0-k"
9c8eb720 75const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 76static const char ixgbe_copyright[] =
49425dfc 77 "Copyright (c) 1999-2016 Intel Corporation.";
9a799d71 78
f44e751b
DS		 79static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
80
9a799d71 81static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 82 [board_82598] = &ixgbe_82598_info,
83 [board_82599] = &ixgbe_82599_info,
84 [board_X540] = &ixgbe_X540_info,
85 [board_X550] = &ixgbe_X550_info,
86 [board_X550EM_x] = &ixgbe_X550EM_x_info,
49425dfc 87 [board_x550em_a] = &ixgbe_x550em_a_info,
9a799d71
AK		 88};
89
90/* ixgbe_pci_tbl - PCI Device ID Table
91 *
92 * Wildcard entries (PCI_ANY_ID) should come last
93 * Last entry must be all 0s
94 *
95 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
96 * Class, Class Mask, private data (not used) }
97 */
9baa3c34 98static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
a711ad89 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
6a14ee0c
DS		 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
f572b2c4
MR		 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
49425dfc 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
200157c2
MR		 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
92ed8430 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
2d40cd17 141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
9a799d71
AK		 142 /* required last entry */
143 {0, }
144};
145MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
146
5dd2d332 147#ifdef CONFIG_IXGBE_DCA
bd0362dd 148static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 149 void *p);
bd0362dd
JC		 150static struct notifier_block dca_notifier = {
151 .notifier_call = ixgbe_notify_dca,
152 .next = NULL,
153 .priority = 0
154};
155#endif
156
1cdd1ec8
GR		 157#ifdef CONFIG_PCI_IOV
158static unsigned int max_vfs;
159module_param(max_vfs, uint, 0);
e8e9f696 160MODULE_PARM_DESC(max_vfs,
170e8543 161 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 162#endif /* CONFIG_PCI_IOV */
163
8ef78adc
PWJ		 164static unsigned int allow_unsupported_sfp;
165module_param(allow_unsupported_sfp, uint, 0);
166MODULE_PARM_DESC(allow_unsupported_sfp,
167 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
168
b3f4d599 169#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
170static int debug = -1;
171module_param(debug, int, 0);
172MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
173
9a799d71
AK		 174MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
175MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
176MODULE_LICENSE("GPL");
177MODULE_VERSION(DRV_VERSION);
178
780484d8
MR		 179static struct workqueue_struct *ixgbe_wq;
180
14438464
MR		 181static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
182
b8e82001
JK		 183static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
184 u32 reg, u16 *value)
185{
b8e82001
JK		 186 struct pci_dev *parent_dev;
187 struct pci_bus *parent_bus;
188
189 parent_bus = adapter->pdev->bus->parent;
190 if (!parent_bus)
191 return -1;
192
193 parent_dev = parent_bus->self;
194 if (!parent_dev)
195 return -1;
196
c0798edf 197 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 198 return -1;
199
c0798edf 200 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 201 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
202 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
203 return -1;
b8e82001
JK		 204 return 0;
205}
206
207static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
208{
209 struct ixgbe_hw *hw = &adapter->hw;
210 u16 link_status = 0;
211 int err;
212
213 hw->bus.type = ixgbe_bus_type_pci_express;
214
215 /* Get the negotiated link width and speed from PCI config space of the
216 * parent, as this device is behind a switch
217 */
218 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
219
220 /* assume caller will handle error case */
221 if (err)
222 return err;
223
224 hw->bus.width = ixgbe_convert_bus_width(link_status);
225 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
226
227 return 0;
228}
229
e027d1ae
JK		 230/**
231 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
232 * @hw: hw specific details
233 *
234 * This function is used by probe to determine whether a device's PCI-Express
235 * bandwidth details should be gathered from the parent bus instead of from the
236 * device. Used to ensure that various locations all have the correct device ID
237 * checks.
238 */
239static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
240{
241 switch (hw->device_id) {
242 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 243 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 244 return true;
245 default:
246 return false;
247 }
248}
249
250static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
251 int expected_gts)
252{
f9328bc6 253 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 254 int max_gts = 0;
255 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
256 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
257 struct pci_dev *pdev;
258
f9328bc6
DS		 259 /* Some devices are not connected over PCIe and thus do not negotiate
260 * speed. These devices do not have valid bus info, and thus any report
261 * we generate may not be correct.
262 */
263 if (hw->bus.type == ixgbe_bus_type_internal)
264 return;
265
56d1392f 266 /* determine whether to use the parent device */
e027d1ae
JK		 267 if (ixgbe_pcie_from_parent(&adapter->hw))
268 pdev = adapter->pdev->bus->parent->self;
269 else
270 pdev = adapter->pdev;
271
272 if (pcie_get_minimum_link(pdev, &speed, &width) ||
273 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
274 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
275 return;
276 }
277
278 switch (speed) {
279 case PCIE_SPEED_2_5GT:
280 /* 8b/10b encoding reduces max throughput by 20% */
281 max_gts = 2 * width;
282 break;
283 case PCIE_SPEED_5_0GT:
284 /* 8b/10b encoding reduces max throughput by 20% */
285 max_gts = 4 * width;
286 break;
287 case PCIE_SPEED_8_0GT:
9f0a433c 288 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 289 max_gts = 8 * width;
290 break;
291 default:
292 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
293 return;
294 }
295
296 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
297 max_gts);
298 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
299 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
300 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
301 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
302 "Unknown"),
303 width,
304 (speed == PCIE_SPEED_2_5GT ? "20%" :
305 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 306 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 307 "Unknown"));
308
309 if (max_gts < expected_gts) {
310 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
311 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
312 expected_gts);
313 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
314 }
315}
316
7086400d
AD		 317static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
318{
319 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 320 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d 321 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
780484d8 322 queue_work(ixgbe_wq, &adapter->service_task);
7086400d
AD		 323}
324
2a1a091c
MR		 325static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
326{
327 struct ixgbe_adapter *adapter = hw->back;
328
329 if (!hw->hw_addr)
330 return;
331 hw->hw_addr = NULL;
332 e_dev_err("Adapter removed\n");
58cf663f
MR		 333 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
334 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 335}
336
f8e2472f 337static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 338{
339 u32 value;
340
341 /* The following check not only optimizes a bit by not
342 * performing a read on the status register when the
343 * register just read was a status register read that
344 * returned IXGBE_FAILED_READ_REG. It also blocks any
345 * potential recursion.
346 */
347 if (reg == IXGBE_STATUS) {
348 ixgbe_remove_adapter(hw);
349 return;
350 }
351 value = ixgbe_read_reg(hw, IXGBE_STATUS);
352 if (value == IXGBE_FAILED_READ_REG)
353 ixgbe_remove_adapter(hw);
354}
355
f8e2472f
MR		 356/**
357 * ixgbe_read_reg - Read from device register
358 * @hw: hw specific details
359 * @reg: offset of register to read
360 *
361 * Returns : value read or IXGBE_FAILED_READ_REG if removed
362 *
363 * This function is used to read device registers. It checks for device
364 * removal by confirming any read that returns all ones by checking the
365 * status register value for all ones. This function avoids reading from
366 * the hardware if a removal was previously detected in which case it
367 * returns IXGBE_FAILED_READ_REG (all ones).
368 */
369u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
370{
371 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
372 u32 value;
373
374 if (ixgbe_removed(reg_addr))
375 return IXGBE_FAILED_READ_REG;
2f2219be
MR		 376 if (unlikely(hw->phy.nw_mng_if_sel &
377 IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M)) {
378 struct ixgbe_adapter *adapter;
379 int i;
380
381 for (i = 0; i < 200; ++i) {
382 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
383 if (likely(!value))
384 goto writes_completed;
385 if (value == IXGBE_FAILED_READ_REG) {
386 ixgbe_remove_adapter(hw);
387 return IXGBE_FAILED_READ_REG;
388 }
389 udelay(5);
390 }
391
392 adapter = hw->back;
393 e_warn(hw, "register writes incomplete %08x\n", value);
394 }
395
396writes_completed:
f8e2472f
MR		 397 value = readl(reg_addr + reg);
398 if (unlikely(value == IXGBE_FAILED_READ_REG))
399 ixgbe_check_remove(hw, reg);
400 return value;
401}
402
14438464
MR		 403static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
404{
405 u16 value;
406
407 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
408 if (value == IXGBE_FAILED_READ_CFG_WORD) {
409 ixgbe_remove_adapter(hw);
410 return true;
411 }
412 return false;
413}
414
415u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
416{
417 struct ixgbe_adapter *adapter = hw->back;
418 u16 value;
419
420 if (ixgbe_removed(hw->hw_addr))
421 return IXGBE_FAILED_READ_CFG_WORD;
422 pci_read_config_word(adapter->pdev, reg, &value);
423 if (value == IXGBE_FAILED_READ_CFG_WORD &&
424 ixgbe_check_cfg_remove(hw, adapter->pdev))
425 return IXGBE_FAILED_READ_CFG_WORD;
426 return value;
427}
428
429#ifdef CONFIG_PCI_IOV
430static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
431{
432 struct ixgbe_adapter *adapter = hw->back;
433 u32 value;
434
435 if (ixgbe_removed(hw->hw_addr))
436 return IXGBE_FAILED_READ_CFG_DWORD;
437 pci_read_config_dword(adapter->pdev, reg, &value);
438 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
439 ixgbe_check_cfg_remove(hw, adapter->pdev))
440 return IXGBE_FAILED_READ_CFG_DWORD;
441 return value;
442}
443#endif /* CONFIG_PCI_IOV */
444
ed19231c
JK		 445void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
446{
447 struct ixgbe_adapter *adapter = hw->back;
448
449 if (ixgbe_removed(hw->hw_addr))
450 return;
451 pci_write_config_word(adapter->pdev, reg, value);
452}
453
7086400d
AD		 454static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
455{
456 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
457
52f33af8 458 /* flush memory to make sure state is correct before next watchdog */
4e857c58 459 smp_mb__before_atomic();
7086400d
AD		 460 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
461}
462
dcd79aeb
TI		 463struct ixgbe_reg_info {
464 u32 ofs;
465 char *name;
466};
467
468static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
469
470 /* General Registers */
471 {IXGBE_CTRL, "CTRL"},
472 {IXGBE_STATUS, "STATUS"},
473 {IXGBE_CTRL_EXT, "CTRL_EXT"},
474
475 /* Interrupt Registers */
476 {IXGBE_EICR, "EICR"},
477
478 /* RX Registers */
479 {IXGBE_SRRCTL(0), "SRRCTL"},
480 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
481 {IXGBE_RDLEN(0), "RDLEN"},
482 {IXGBE_RDH(0), "RDH"},
483 {IXGBE_RDT(0), "RDT"},
484 {IXGBE_RXDCTL(0), "RXDCTL"},
485 {IXGBE_RDBAL(0), "RDBAL"},
486 {IXGBE_RDBAH(0), "RDBAH"},
487
488 /* TX Registers */
489 {IXGBE_TDBAL(0), "TDBAL"},
490 {IXGBE_TDBAH(0), "TDBAH"},
491 {IXGBE_TDLEN(0), "TDLEN"},
492 {IXGBE_TDH(0), "TDH"},
493 {IXGBE_TDT(0), "TDT"},
494 {IXGBE_TXDCTL(0), "TXDCTL"},
495
496 /* List Terminator */
ca8dfe25 497 { .name = NULL }
dcd79aeb
TI		 498};
499
500
501/*
502 * ixgbe_regdump - register printout routine
503 */
504static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
505{
506 int i = 0, j = 0;
507 char rname[16];
508 u32 regs[64];
509
510 switch (reginfo->ofs) {
511 case IXGBE_SRRCTL(0):
512 for (i = 0; i < 64; i++)
513 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
514 break;
515 case IXGBE_DCA_RXCTRL(0):
516 for (i = 0; i < 64; i++)
517 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
518 break;
519 case IXGBE_RDLEN(0):
520 for (i = 0; i < 64; i++)
521 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
522 break;
523 case IXGBE_RDH(0):
524 for (i = 0; i < 64; i++)
525 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
526 break;
527 case IXGBE_RDT(0):
528 for (i = 0; i < 64; i++)
529 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
530 break;
531 case IXGBE_RXDCTL(0):
532 for (i = 0; i < 64; i++)
533 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
534 break;
535 case IXGBE_RDBAL(0):
536 for (i = 0; i < 64; i++)
537 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
538 break;
539 case IXGBE_RDBAH(0):
540 for (i = 0; i < 64; i++)
541 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
542 break;
543 case IXGBE_TDBAL(0):
544 for (i = 0; i < 64; i++)
545 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
546 break;
547 case IXGBE_TDBAH(0):
548 for (i = 0; i < 64; i++)
549 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
550 break;
551 case IXGBE_TDLEN(0):
552 for (i = 0; i < 64; i++)
553 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
554 break;
555 case IXGBE_TDH(0):
556 for (i = 0; i < 64; i++)
557 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
558 break;
559 case IXGBE_TDT(0):
560 for (i = 0; i < 64; i++)
561 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
562 break;
563 case IXGBE_TXDCTL(0):
564 for (i = 0; i < 64; i++)
565 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
566 break;
567 default:
c7689578 568 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 569 IXGBE_READ_REG(hw, reginfo->ofs));
570 return;
571 }
572
573 for (i = 0; i < 8; i++) {
574 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 575 pr_err("%-15s", rname);
dcd79aeb 576 for (j = 0; j < 8; j++)
c7689578
JP		 577 pr_cont(" %08x", regs[i*8+j]);
578 pr_cont("\n");
dcd79aeb
TI		 579 }
580
581}
582
583/*
584 * ixgbe_dump - Print registers, tx-rings and rx-rings
585 */
586static void ixgbe_dump(struct ixgbe_adapter *adapter)
587{
588 struct net_device *netdev = adapter->netdev;
589 struct ixgbe_hw *hw = &adapter->hw;
590 struct ixgbe_reg_info *reginfo;
591 int n = 0;
592 struct ixgbe_ring *tx_ring;
729739b7 593 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 594 union ixgbe_adv_tx_desc *tx_desc;
595 struct my_u0 { u64 a; u64 b; } *u0;
596 struct ixgbe_ring *rx_ring;
597 union ixgbe_adv_rx_desc *rx_desc;
598 struct ixgbe_rx_buffer *rx_buffer_info;
599 u32 staterr;
600 int i = 0;
601
602 if (!netif_msg_hw(adapter))
603 return;
604
605 /* Print netdevice Info */
606 if (netdev) {
607 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 608 pr_info("Device Name state "
dcd79aeb 609 "trans_start last_rx\n");
c7689578
JP		 610 pr_info("%-15s %016lX %016lX %016lX\n",
611 netdev->name,
612 netdev->state,
4d0e9657 613 dev_trans_start(netdev),
c7689578 614 netdev->last_rx);
dcd79aeb
TI		 615 }
616
617 /* Print Registers */
618 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 619 pr_info(" Register Name Value\n");
dcd79aeb
TI		 620 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
621 reginfo->name; reginfo++) {
622 ixgbe_regdump(hw, reginfo);
623 }
624
625 /* Print TX Ring Summary */
626 if (!netdev || !netif_running(netdev))
e90dd264 627 return;
dcd79aeb
TI		 628
629 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 630 pr_info(" %s %s %s %s\n",
631 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
632 "leng", "ntw", "timestamp");
dcd79aeb
TI		 633 for (n = 0; n < adapter->num_tx_queues; n++) {
634 tx_ring = adapter->tx_ring[n];
729739b7 635 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 636 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 637 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 638 (u64)dma_unmap_addr(tx_buffer, dma),
639 dma_unmap_len(tx_buffer, len),
640 tx_buffer->next_to_watch,
641 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 642 }
643
644 /* Print TX Rings */
645 if (!netif_msg_tx_done(adapter))
646 goto rx_ring_summary;
647
648 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
649
650 /* Transmit Descriptor Formats
651 *
39ac868a 652 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 653 * +--------------------------------------------------------------+
654 * 0 | Buffer Address [63:0] |
655 * +--------------------------------------------------------------+
39ac868a 656 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 657 * +--------------------------------------------------------------+
658 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 659 *
660 * 82598 Advanced Transmit Descriptor (Write-Back Format)
661 * +--------------------------------------------------------------+
662 * 0 | RSV [63:0] |
663 * +--------------------------------------------------------------+
664 * 8 | RSV | STA | NXTSEQ |
665 * +--------------------------------------------------------------+
666 * 63 36 35 32 31 0
667 *
668 * 82599+ Advanced Transmit Descriptor
669 * +--------------------------------------------------------------+
670 * 0 | Buffer Address [63:0] |
671 * +--------------------------------------------------------------+
672 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
673 * +--------------------------------------------------------------+
674 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
675 *
676 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
677 * +--------------------------------------------------------------+
678 * 0 | RSV [63:0] |
679 * +--------------------------------------------------------------+
680 * 8 | RSV | STA | RSV |
681 * +--------------------------------------------------------------+
682 * 63 36 35 32 31 0
dcd79aeb
TI		 683 */
684
685 for (n = 0; n < adapter->num_tx_queues; n++) {
686 tx_ring = adapter->tx_ring[n];
c7689578
JP		 687 pr_info("------------------------------------\n");
688 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
689 pr_info("------------------------------------\n");
8ad88e37
JH		 690 pr_info("%s%s %s %s %s %s\n",
691 "T [desc] [address 63:0 ] ",
692 "[PlPOIdStDDt Ln] [bi->dma ] ",
693 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 694
695 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 696 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 697 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 698 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 699 if (dma_unmap_len(tx_buffer, len) > 0) {
700 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
701 i,
702 le64_to_cpu(u0->a),
703 le64_to_cpu(u0->b),
704 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 705 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 706 tx_buffer->next_to_watch,
707 (u64)tx_buffer->time_stamp,
708 tx_buffer->skb);
709 if (i == tx_ring->next_to_use &&
710 i == tx_ring->next_to_clean)
711 pr_cont(" NTC/U\n");
712 else if (i == tx_ring->next_to_use)
713 pr_cont(" NTU\n");
714 else if (i == tx_ring->next_to_clean)
715 pr_cont(" NTC\n");
716 else
717 pr_cont("\n");
718
719 if (netif_msg_pktdata(adapter) &&
720 tx_buffer->skb)
721 print_hex_dump(KERN_INFO, "",
722 DUMP_PREFIX_ADDRESS, 16, 1,
723 tx_buffer->skb->data,
724 dma_unmap_len(tx_buffer, len),
725 true);
726 }
dcd79aeb
TI		 727 }
728 }
729
730 /* Print RX Rings Summary */
731rx_ring_summary:
732 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 733 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 734 for (n = 0; n < adapter->num_rx_queues; n++) {
735 rx_ring = adapter->rx_ring[n];
c7689578
JP		 736 pr_info("%5d %5X %5X\n",
737 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 738 }
739
740 /* Print RX Rings */
741 if (!netif_msg_rx_status(adapter))
e90dd264 742 return;
dcd79aeb
TI		 743
744 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
745
39ac868a
JH		 746 /* Receive Descriptor Formats
747 *
748 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 749 * 63 1 0
750 * +-----------------------------------------------------+
751 * 0 | Packet Buffer Address [63:1] |A0/NSE|
752 * +----------------------------------------------+------+
753 * 8 | Header Buffer Address [63:1] | DD |
754 * +-----------------------------------------------------+
755 *
756 *
39ac868a 757 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 758 *
759 * 63 48 47 32 31 30 21 20 16 15 4 3 0
760 * +------------------------------------------------------+
39ac868a
JH		 761 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
762 * | Packet | IP | | | | Type | Type |
763 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 764 * +------------------------------------------------------+
765 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
766 * +------------------------------------------------------+
767 * 63 48 47 32 31 20 19 0
39ac868a
JH		 768 *
769 * 82599+ Advanced Receive Descriptor (Read) Format
770 * 63 1 0
771 * +-----------------------------------------------------+
772 * 0 | Packet Buffer Address [63:1] |A0/NSE|
773 * +----------------------------------------------+------+
774 * 8 | Header Buffer Address [63:1] | DD |
775 * +-----------------------------------------------------+
776 *
777 *
778 * 82599+ Advanced Receive Descriptor (Write-Back) Format
779 *
780 * 63 48 47 32 31 30 21 20 17 16 4 3 0
781 * +------------------------------------------------------+
782 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
783 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
784 * |/ Flow Dir Flt ID | | | | | |
785 * +------------------------------------------------------+
786 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
787 * +------------------------------------------------------+
788 * 63 48 47 32 31 20 19 0
dcd79aeb 789 */
39ac868a 790
dcd79aeb
TI		 791 for (n = 0; n < adapter->num_rx_queues; n++) {
792 rx_ring = adapter->rx_ring[n];
c7689578
JP		 793 pr_info("------------------------------------\n");
794 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
795 pr_info("------------------------------------\n");
8ad88e37
JH		 796 pr_info("%s%s%s",
797 "R [desc] [ PktBuf A0] ",
798 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 799 "<-- Adv Rx Read format\n");
8ad88e37
JH		 800 pr_info("%s%s%s",
801 "RWB[desc] [PcsmIpSHl PtRs] ",
802 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 803 "<-- Adv Rx Write-Back format\n");
804
805 for (i = 0; i < rx_ring->count; i++) {
806 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 807 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 808 u0 = (struct my_u0 *)rx_desc;
809 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
810 if (staterr & IXGBE_RXD_STAT_DD) {
811 /* Descriptor Done */
c7689578 812 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 813 "%016llX ---------------- %p", i,
814 le64_to_cpu(u0->a),
815 le64_to_cpu(u0->b),
816 rx_buffer_info->skb);
817 } else {
c7689578 818 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 819 "%016llX %016llX %p", i,
820 le64_to_cpu(u0->a),
821 le64_to_cpu(u0->b),
822 (u64)rx_buffer_info->dma,
823 rx_buffer_info->skb);
824
9c50c035
ET		 825 if (netif_msg_pktdata(adapter) &&
826 rx_buffer_info->dma) {
dcd79aeb
TI		 827 print_hex_dump(KERN_INFO, "",
828 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 829 page_address(rx_buffer_info->page) +
830 rx_buffer_info->page_offset,
f800326d 831 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 832 }
833 }
834
835 if (i == rx_ring->next_to_use)
c7689578 836 pr_cont(" NTU\n");
dcd79aeb 837 else if (i == rx_ring->next_to_clean)
c7689578 838 pr_cont(" NTC\n");
dcd79aeb 839 else
c7689578 840 pr_cont("\n");
dcd79aeb
TI		 841
842 }
843 }
dcd79aeb
TI		 844}
845
5eba3699
AV		 846static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
847{
848 u32 ctrl_ext;
849
850 /* Let firmware take over control of h/w */
851 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
852 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 853 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 854}
855
856static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
857{
858 u32 ctrl_ext;
859
860 /* Let firmware know the driver has taken over */
861 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 863 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 864}
9a799d71 865
49ce9c2c 866/**
e8e26350
PW		 867 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
868 * @adapter: pointer to adapter struct
869 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
870 * @queue: queue to map the corresponding interrupt to
871 * @msix_vector: the vector to map to the corresponding queue
872 *
873 */
874static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 875 u8 queue, u8 msix_vector)
9a799d71
AK		 876{
877 u32 ivar, index;
e8e26350
PW		 878 struct ixgbe_hw *hw = &adapter->hw;
879 switch (hw->mac.type) {
880 case ixgbe_mac_82598EB:
881 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
882 if (direction == -1)
883 direction = 0;
884 index = (((direction * 64) + queue) >> 2) & 0x1F;
885 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
886 ivar &= ~(0xFF << (8 * (queue & 0x3)));
887 ivar |= (msix_vector << (8 * (queue & 0x3)));
888 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
889 break;
890 case ixgbe_mac_82599EB:
b93a2226 891 case ixgbe_mac_X540:
9a75a1ac
DS		 892 case ixgbe_mac_X550:
893 case ixgbe_mac_X550EM_x:
49425dfc 894 case ixgbe_mac_x550em_a:
e8e26350
PW		 895 if (direction == -1) {
896 /* other causes */
897 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
898 index = ((queue & 1) * 8);
899 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
900 ivar &= ~(0xFF << index);
901 ivar |= (msix_vector << index);
902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
903 break;
904 } else {
905 /* tx or rx causes */
906 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
907 index = ((16 * (queue & 1)) + (8 * direction));
908 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
909 ivar &= ~(0xFF << index);
910 ivar |= (msix_vector << index);
911 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
912 break;
913 }
914 default:
915 break;
916 }
9a799d71
AK		 917}
918
fe49f04a 919static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 920 u64 qmask)
fe49f04a
AD		 921{
922 u32 mask;
923
bd508178
AD		 924 switch (adapter->hw.mac.type) {
925 case ixgbe_mac_82598EB:
fe49f04a
AD		 926 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
927 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 928 break;
929 case ixgbe_mac_82599EB:
b93a2226 930 case ixgbe_mac_X540:
9a75a1ac
DS		 931 case ixgbe_mac_X550:
932 case ixgbe_mac_X550EM_x:
49425dfc 933 case ixgbe_mac_x550em_a:
fe49f04a
AD		 934 mask = (qmask & 0xFFFFFFFF);
935 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
936 mask = (qmask >> 32);
937 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 938 break;
939 default:
940 break;
fe49f04a
AD		 941 }
942}
943
729739b7
AD		 944void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
945 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 946{
729739b7
AD		 947 if (tx_buffer->skb) {
948 dev_kfree_skb_any(tx_buffer->skb);
949 if (dma_unmap_len(tx_buffer, len))
d3d00239 950 dma_unmap_single(ring->dev,
729739b7
AD		 951 dma_unmap_addr(tx_buffer, dma),
952 dma_unmap_len(tx_buffer, len),
953 DMA_TO_DEVICE);
954 } else if (dma_unmap_len(tx_buffer, len)) {
955 dma_unmap_page(ring->dev,
956 dma_unmap_addr(tx_buffer, dma),
957 dma_unmap_len(tx_buffer, len),
958 DMA_TO_DEVICE);
e5a43549 959 }
729739b7
AD		 960 tx_buffer->next_to_watch = NULL;
961 tx_buffer->skb = NULL;
962 dma_unmap_len_set(tx_buffer, len, 0);
963 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 964}
965
943561d3 966static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 967{
968 struct ixgbe_hw *hw = &adapter->hw;
969 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 970 int i;
943561d3 971 u32 data;
c84d324c 972
943561d3
AD		 973 if ((hw->fc.current_mode != ixgbe_fc_full) &&
974 (hw->fc.current_mode != ixgbe_fc_rx_pause))
975 return;
c84d324c 976
943561d3
AD		 977 switch (hw->mac.type) {
978 case ixgbe_mac_82598EB:
979 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
980 break;
981 default:
982 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
983 }
984 hwstats->lxoffrxc += data;
c84d324c 985
943561d3
AD		 986 /* refill credits (no tx hang) if we received xoff */
987 if (!data)
c84d324c 988 return;
943561d3
AD		 989
990 for (i = 0; i < adapter->num_tx_queues; i++)
991 clear_bit(__IXGBE_HANG_CHECK_ARMED,
992 &adapter->tx_ring[i]->state);
993}
994
995static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
996{
997 struct ixgbe_hw *hw = &adapter->hw;
998 struct ixgbe_hw_stats *hwstats = &adapter->stats;
999 u32 xoff[8] = {0};
2afaa00d 1000 u8 tc;
943561d3
AD		 1001 int i;
1002 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
1003
1004 if (adapter->ixgbe_ieee_pfc)
1005 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
1006
1007 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
1008 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 1009 return;
943561d3 1010 }
c84d324c
JF		 1011
1012 /* update stats for each tc, only valid with PFC enabled */
1013 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 1014 u32 pxoffrxc;
1015
c84d324c
JF		 1016 switch (hw->mac.type) {
1017 case ixgbe_mac_82598EB:
2afaa00d 1018 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 1019 break;
c84d324c 1020 default:
2afaa00d 1021 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 1022 }
2afaa00d
PN		 1023 hwstats->pxoffrxc[i] += pxoffrxc;
1024 /* Get the TC for given UP */
1025 tc = netdev_get_prio_tc_map(adapter->netdev, i);
1026 xoff[tc] += pxoffrxc;
c84d324c
JF		 1027 }
1028
1029 /* disarm tx queues that have received xoff frames */
1030 for (i = 0; i < adapter->num_tx_queues; i++) {
1031 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1032
2afaa00d 1033 tc = tx_ring->dcb_tc;
c84d324c
JF		 1034 if (xoff[tc])
1035 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1036 }
26f23d82
YZ		 1037}
1038
c84d324c 1039static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1040{
7d7ce682 1041 return ring->stats.packets;
c84d324c
JF		 1042}
1043
1044static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1045{
2a47fa45
JF		 1046 struct ixgbe_adapter *adapter;
1047 struct ixgbe_hw *hw;
1048 u32 head, tail;
1049
1050 if (ring->l2_accel_priv)
1051 adapter = ring->l2_accel_priv->real_adapter;
1052 else
1053 adapter = netdev_priv(ring->netdev);
e01c31a5 1054
2a47fa45
JF		 1055 hw = &adapter->hw;
1056 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1057 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1058
1059 if (head != tail)
1060 return (head < tail) ?
1061 tail - head : (tail + ring->count - head);
1062
1063 return 0;
1064}
1065
1066static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1067{
1068 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1069 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1070 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1071
7d637bcc 1072 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1073
1074 /*
1075 * Check for a hung queue, but be thorough. This verifies
1076 * that a transmit has been completed since the previous
1077 * check AND there is at least one packet pending. The
1078 * ARMED bit is set to indicate a potential hang. The
1079 * bit is cleared if a pause frame is received to remove
1080 * false hang detection due to PFC or 802.3x frames. By
1081 * requiring this to fail twice we avoid races with
1082 * pfc clearing the ARMED bit and conditions where we
1083 * run the check_tx_hang logic with a transmit completion
1084 * pending but without time to complete it yet.
1085 */
e90dd264 1086 if (tx_done_old == tx_done && tx_pending)
c84d324c 1087 /* make sure it is true for two checks in a row */
e90dd264
MR		 1088 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1089 &tx_ring->state);
1090 /* update completed stats and continue */
1091 tx_ring->tx_stats.tx_done_old = tx_done;
1092 /* reset the countdown */
1093 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1094
e90dd264 1095 return false;
9a799d71
AK		 1096}
1097
c83c6cbd
AD		 1098/**
1099 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1100 * @adapter: driver private struct
1101 **/
1102static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1103{
1104
1105 /* Do the reset outside of interrupt context */
1106 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
57ca2a4f 1107 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
12ff3f3b 1108 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1109 ixgbe_service_event_schedule(adapter);
1110 }
1111}
e01c31a5 1112
c04f90e5
RP		 1113/**
1114 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1115 **/
1116static int ixgbe_tx_maxrate(struct net_device *netdev,
1117 int queue_index, u32 maxrate)
1118{
1119 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1120 struct ixgbe_hw *hw = &adapter->hw;
1121 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1122
1123 if (!maxrate)
1124 return 0;
1125
1126 /* Calculate the rate factor values to set */
1127 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1128 bcnrc_val /= maxrate;
1129
1130 /* clear everything but the rate factor */
1131 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1132 IXGBE_RTTBCNRC_RF_DEC_MASK;
1133
1134 /* enable the rate scheduler */
1135 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1136
1137 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1138 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1139
1140 return 0;
1141}
1142
9a799d71
AK		 1143/**
1144 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1145 * @q_vector: structure containing interrupt and ring information
e01c31a5 1146 * @tx_ring: tx ring to clean
8220bbc1 1147 * @napi_budget: Used to determine if we are in netpoll
9a799d71 1148 **/
fe49f04a 1149static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
a3a8749d 1150 struct ixgbe_ring *tx_ring, int napi_budget)
9a799d71 1151{
fe49f04a 1152 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1153 struct ixgbe_tx_buffer *tx_buffer;
1154 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1155 unsigned int total_bytes = 0, total_packets = 0;
59224555 1156 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1157 unsigned int i = tx_ring->next_to_clean;
1158
1159 if (test_bit(__IXGBE_DOWN, &adapter->state))
1160 return true;
9a799d71 1161
d3d00239 1162 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1163 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1164 i -= tx_ring->count;
12207e49 1165
729739b7 1166 do {
d3d00239
AD		 1167 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1168
1169 /* if next_to_watch is not set then there is no work pending */
1170 if (!eop_desc)
1171 break;
1172
7f83a9e6 1173 /* prevent any other reads prior to eop_desc */
7e63bf49 1174 read_barrier_depends();
7f83a9e6 1175
d3d00239
AD		 1176 /* if DD is not set pending work has not been completed */
1177 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1178 break;
8ad494b0 1179
d3d00239
AD		 1180 /* clear next_to_watch to prevent false hangs */
1181 tx_buffer->next_to_watch = NULL;
8ad494b0 1182
091a6246
AD		 1183 /* update the statistics for this packet */
1184 total_bytes += tx_buffer->bytecount;
1185 total_packets += tx_buffer->gso_segs;
1186
fd0db0ed 1187 /* free the skb */
a3a8749d 1188 napi_consume_skb(tx_buffer->skb, napi_budget);
fd0db0ed 1189
729739b7
AD		 1190 /* unmap skb header data */
1191 dma_unmap_single(tx_ring->dev,
1192 dma_unmap_addr(tx_buffer, dma),
1193 dma_unmap_len(tx_buffer, len),
1194 DMA_TO_DEVICE);
1195
fd0db0ed
AD		 1196 /* clear tx_buffer data */
1197 tx_buffer->skb = NULL;
729739b7 1198 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1199
729739b7
AD		 1200 /* unmap remaining buffers */
1201 while (tx_desc != eop_desc) {
d3d00239
AD		 1202 tx_buffer++;
1203 tx_desc++;
8ad494b0 1204 i++;
729739b7
AD		 1205 if (unlikely(!i)) {
1206 i -= tx_ring->count;
d3d00239 1207 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1208 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1209 }
e01c31a5 1210
729739b7
AD		 1211 /* unmap any remaining paged data */
1212 if (dma_unmap_len(tx_buffer, len)) {
1213 dma_unmap_page(tx_ring->dev,
1214 dma_unmap_addr(tx_buffer, dma),
1215 dma_unmap_len(tx_buffer, len),
1216 DMA_TO_DEVICE);
1217 dma_unmap_len_set(tx_buffer, len, 0);
1218 }
1219 }
1220
1221 /* move us one more past the eop_desc for start of next pkt */
1222 tx_buffer++;
1223 tx_desc++;
1224 i++;
1225 if (unlikely(!i)) {
1226 i -= tx_ring->count;
1227 tx_buffer = tx_ring->tx_buffer_info;
1228 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1229 }
1230
1231 /* issue prefetch for next Tx descriptor */
1232 prefetch(tx_desc);
12207e49 1233
729739b7
AD		 1234 /* update budget accounting */
1235 budget--;
1236 } while (likely(budget));
1237
1238 i += tx_ring->count;
9a799d71 1239 tx_ring->next_to_clean = i;
d3d00239 1240 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1241 tx_ring->stats.bytes += total_bytes;
bd198058 1242 tx_ring->stats.packets += total_packets;
d3d00239 1243 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1244 q_vector->tx.total_bytes += total_bytes;
1245 q_vector->tx.total_packets += total_packets;
b953799e 1246
c84d324c
JF		 1247 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1248 /* schedule immediate reset if we believe we hung */
1249 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1250 e_err(drv, "Detected Tx Unit Hang\n"
1251 " Tx Queue <%d>\n"
1252 " TDH, TDT <%x>, <%x>\n"
1253 " next_to_use <%x>\n"
1254 " next_to_clean <%x>\n"
1255 "tx_buffer_info[next_to_clean]\n"
1256 " time_stamp <%lx>\n"
1257 " jiffies <%lx>\n",
1258 tx_ring->queue_index,
1259 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1260 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1261 tx_ring->next_to_use, i,
1262 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1263
1264 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1265
1266 e_info(probe,
1267 "tx hang %d detected on queue %d, resetting adapter\n",
1268 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1269
b953799e 1270 /* schedule immediate reset if we believe we hung */
c83c6cbd 1271 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1272
1273 /* the adapter is about to reset, no point in enabling stuff */
59224555 1274 return true;
b953799e 1275 }
9a799d71 1276
b2d96e0a
AD		 1277 netdev_tx_completed_queue(txring_txq(tx_ring),
1278 total_packets, total_bytes);
1279
e092be60 1280#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1281 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1282 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1283 /* Make sure that anybody stopping the queue after this
1284 * sees the new next_to_clean.
1285 */
1286 smp_mb();
729739b7
AD		 1287 if (__netif_subqueue_stopped(tx_ring->netdev,
1288 tx_ring->queue_index)
1289 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1290 netif_wake_subqueue(tx_ring->netdev,
1291 tx_ring->queue_index);
5b7da515 1292 ++tx_ring->tx_stats.restart_queue;
30eba97a 1293 }
e092be60 1294 }
9a799d71 1295
59224555 1296 return !!budget;
9a799d71
AK		 1297}
1298
5dd2d332 1299#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1300static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1301 struct ixgbe_ring *tx_ring,
33cf09c9 1302 int cpu)
bd0362dd 1303{
33cf09c9 1304 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1305 u32 txctrl = 0;
bdda1a61 1306 u16 reg_offset;
33cf09c9 1307
9de7605e
MR		 1308 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1309 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1310
33cf09c9
AD		 1311 switch (hw->mac.type) {
1312 case ixgbe_mac_82598EB:
bdda1a61 1313 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1314 break;
1315 case ixgbe_mac_82599EB:
b93a2226 1316 case ixgbe_mac_X540:
bdda1a61
AD		 1317 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1318 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1319 break;
1320 default:
bdda1a61
AD		 1321 /* for unknown hardware do not write register */
1322 return;
bd0362dd 1323 }
bdda1a61
AD		 1324
1325 /*
1326 * We can enable relaxed ordering for reads, but not writes when
1327 * DCA is enabled. This is due to a known issue in some chipsets
1328 * which will cause the DCA tag to be cleared.
1329 */
1330 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1331 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1332 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1333
1334 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1335}
1336
bdda1a61
AD		 1337static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1338 struct ixgbe_ring *rx_ring,
33cf09c9 1339 int cpu)
bd0362dd 1340{
33cf09c9 1341 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1342 u32 rxctrl = 0;
bdda1a61
AD		 1343 u8 reg_idx = rx_ring->reg_idx;
1344
9de7605e
MR		 1345 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1346 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1347
1348 switch (hw->mac.type) {
33cf09c9 1349 case ixgbe_mac_82599EB:
b93a2226 1350 case ixgbe_mac_X540:
bdda1a61 1351 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1352 break;
1353 default:
1354 break;
1355 }
bdda1a61
AD		 1356
1357 /*
1358 * We can enable relaxed ordering for reads, but not writes when
1359 * DCA is enabled. This is due to a known issue in some chipsets
1360 * which will cause the DCA tag to be cleared.
1361 */
1362 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1363 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1364 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1365
1366 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1367}
1368
1369static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1370{
1371 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1372 struct ixgbe_ring *ring;
bd0362dd 1373 int cpu = get_cpu();
bd0362dd 1374
33cf09c9
AD		 1375 if (q_vector->cpu == cpu)
1376 goto out_no_update;
1377
a557928e 1378 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1379 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1380
a557928e 1381 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1382 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1383
1384 q_vector->cpu = cpu;
1385out_no_update:
bd0362dd
JC		 1386 put_cpu();
1387}
1388
1389static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1390{
1391 int i;
1392
e35ec126 1393 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1394 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1396 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1397 else
1398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1399 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1400
49c7ffbe 1401 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1402 adapter->q_vector[i]->cpu = -1;
1403 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1404 }
1405}
1406
1407static int __ixgbe_notify_dca(struct device *dev, void *data)
1408{
c60fbb00 1409 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1410 unsigned long event = *(unsigned long *)data;
1411
2a72c31e 1412 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1413 return 0;
1414
bd0362dd
JC		 1415 switch (event) {
1416 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1417 /* if we're already enabled, don't do it again */
1418 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1419 break;
652f093f 1420 if (dca_add_requester(dev) == 0) {
96b0e0f6 1421 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1422 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1423 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1424 break;
1425 }
1426 /* Fall Through since DCA is disabled. */
1427 case DCA_PROVIDER_REMOVE:
1428 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1429 dca_remove_requester(dev);
1430 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1431 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1432 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1433 }
1434 break;
1435 }
1436
652f093f 1437 return 0;
bd0362dd 1438}
67a74ee2 1439
bdda1a61 1440#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1441
1442#define IXGBE_RSS_L4_TYPES_MASK \
1443 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1444 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1445 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1446 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1447
8a0da21b
AD		 1448static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1449 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1450 struct sk_buff *skb)
1451{
7edda4b8
FD		 1452 u16 rss_type;
1453
1454 if (!(ring->netdev->features & NETIF_F_RXHASH))
1455 return;
1456
1457 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1458 IXGBE_RXDADV_RSSTYPE_MASK;
1459
1460 if (!rss_type)
1461 return;
1462
1463 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1464 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1465 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1466}
1467
f800326d 1468#ifdef IXGBE_FCOE
ff886dfc
AD		 1469/**
1470 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1471 * @ring: structure containing ring specific data
ff886dfc
AD		 1472 * @rx_desc: advanced rx descriptor
1473 *
1474 * Returns : true if it is FCoE pkt
1475 */
57efd44c 1476static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1477 union ixgbe_adv_rx_desc *rx_desc)
1478{
1479 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1480
57efd44c 1481 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1482 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1483 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1484 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1485}
1486
f800326d 1487#endif /* IXGBE_FCOE */
e59bd25d
AV		 1488/**
1489 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1490 * @ring: structure containing ring specific data
1491 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1492 * @skb: skb currently being received and modified
1493 **/
8a0da21b 1494static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1495 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1496 struct sk_buff *skb)
9a799d71 1497{
3f207800 1498 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
3f207800
DS		 1499 bool encap_pkt = false;
1500
8a0da21b 1501 skb_checksum_none_assert(skb);
9a799d71 1502
712744be 1503 /* Rx csum disabled */
8a0da21b 1504 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1505 return;
e59bd25d 1506
a21d0822
ET		 1507 /* check for VXLAN and Geneve packets */
1508 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
3f207800
DS		 1509 encap_pkt = true;
1510 skb->encapsulation = 1;
3f207800
DS		 1511 }
1512
e59bd25d 1513 /* if IP and error */
f56e0cb1
AD		 1514 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1515 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1516 ring->rx_stats.csum_err++;
9a799d71
AK		 1517 return;
1518 }
e59bd25d 1519
f56e0cb1 1520 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1521 return;
1522
f56e0cb1 1523 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1524 /*
1525 * 82599 errata, UDP frames with a 0 checksum can be marked as
1526 * checksum errors.
1527 */
8a0da21b
AD		 1528 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1529 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1530 return;
1531
8a0da21b 1532 ring->rx_stats.csum_err++;
e59bd25d
AV		 1533 return;
1534 }
1535
9a799d71 1536 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1537 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1538 if (encap_pkt) {
1539 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1540 return;
1541
1542 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
d469251b 1543 skb->ip_summed = CHECKSUM_NONE;
3f207800
DS		 1544 return;
1545 }
1546 /* If we checked the outer header let the stack know */
1547 skb->csum_level = 1;
1548 }
9a799d71
AK		 1549}
1550
f990b79b
AD		 1551static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1552 struct ixgbe_rx_buffer *bi)
1553{
1554 struct page *page = bi->page;
18cb652a 1555 dma_addr_t dma;
f990b79b 1556
f800326d 1557 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1558 if (likely(page))
f990b79b
AD		 1559 return true;
1560
f800326d 1561 /* alloc new page for storage */
18cb652a
AD		 1562 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1563 if (unlikely(!page)) {
1564 rx_ring->rx_stats.alloc_rx_page_failed++;
1565 return false;
f990b79b
AD		 1566 }
1567
f800326d
AD		 1568 /* map page for use */
1569 dma = dma_map_page(rx_ring->dev, page, 0,
1570 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1571
1572 /*
1573 * if mapping failed free memory back to system since
1574 * there isn't much point in holding memory we can't use
1575 */
1576 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1577 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1578
f990b79b
AD		 1579 rx_ring->rx_stats.alloc_rx_page_failed++;
1580 return false;
1581 }
1582
f800326d 1583 bi->dma = dma;
18cb652a 1584 bi->page = page;
afaa9459 1585 bi->page_offset = 0;
f800326d 1586
f990b79b
AD		 1587 return true;
1588}
1589
9a799d71 1590/**
f990b79b 1591 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1592 * @rx_ring: ring to place buffers on
1593 * @cleaned_count: number of buffers to replace
9a799d71 1594 **/
fc77dc3c 1595void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1596{
9a799d71 1597 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1598 struct ixgbe_rx_buffer *bi;
d5f398ed 1599 u16 i = rx_ring->next_to_use;
9a799d71 1600
f800326d
AD		 1601 /* nothing to do */
1602 if (!cleaned_count)
fc77dc3c
AD		 1603 return;
1604
e4f74028 1605 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1606 bi = &rx_ring->rx_buffer_info[i];
1607 i -= rx_ring->count;
9a799d71 1608
f800326d
AD		 1609 do {
1610 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1611 break;
d5f398ed 1612
f800326d
AD		 1613 /*
1614 * Refresh the desc even if buffer_addrs didn't change
1615 * because each write-back erases this info.
1616 */
1617 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1618
f990b79b
AD		 1619 rx_desc++;
1620 bi++;
9a799d71 1621 i++;
f990b79b 1622 if (unlikely(!i)) {
e4f74028 1623 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1624 bi = rx_ring->rx_buffer_info;
1625 i -= rx_ring->count;
1626 }
1627
18cb652a
AD		 1628 /* clear the status bits for the next_to_use descriptor */
1629 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1630
1631 cleaned_count--;
1632 } while (cleaned_count);
7c6e0a43 1633
f990b79b
AD		 1634 i += rx_ring->count;
1635
ad435ec6
AD		 1636 if (rx_ring->next_to_use != i) {
1637 rx_ring->next_to_use = i;
1638
1639 /* update next to alloc since we have filled the ring */
1640 rx_ring->next_to_alloc = i;
1641
1642 /* Force memory writes to complete before letting h/w
1643 * know there are new descriptors to fetch. (Only
1644 * applicable for weak-ordered memory model archs,
1645 * such as IA-64).
1646 */
1647 wmb();
1648 writel(i, rx_ring->tail);
1649 }
9a799d71
AK		 1650}
1651
1d2024f6
AD		 1652static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1653 struct sk_buff *skb)
1654{
f800326d 1655 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1656
1657 /* set gso_size to avoid messing up TCP MSS */
1658 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1659 IXGBE_CB(skb)->append_cnt);
96be80ab 1660 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1661}
1662
1663static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1664 struct sk_buff *skb)
1665{
1666 /* if append_cnt is 0 then frame is not RSC */
1667 if (!IXGBE_CB(skb)->append_cnt)
1668 return;
1669
1670 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1671 rx_ring->rx_stats.rsc_flush++;
1672
1673 ixgbe_set_rsc_gso_size(rx_ring, skb);
1674
1675 /* gso_size is computed using append_cnt so always clear it last */
1676 IXGBE_CB(skb)->append_cnt = 0;
1677}
1678
8a0da21b
AD		 1679/**
1680 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1681 * @rx_ring: rx descriptor ring packet is being transacted on
1682 * @rx_desc: pointer to the EOP Rx descriptor
1683 * @skb: pointer to current skb being populated
f8212f97 1684 *
8a0da21b
AD		 1685 * This function checks the ring, descriptor, and packet information in
1686 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1687 * other fields within the skb.
f8212f97 1688 **/
8a0da21b
AD		 1689static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1690 union ixgbe_adv_rx_desc *rx_desc,
1691 struct sk_buff *skb)
f8212f97 1692{
43e95f11 1693 struct net_device *dev = rx_ring->netdev;
a9763f3c 1694 u32 flags = rx_ring->q_vector->adapter->flags;
43e95f11 1695
8a0da21b
AD		 1696 ixgbe_update_rsc_stats(rx_ring, skb);
1697
1698 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1699
8a0da21b
AD		 1700 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1701
a9763f3c
MR		 1702 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1703 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1704
f646968f 1705 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1706 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1707 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1708 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1709 }
1710
8a0da21b 1711 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1712
43e95f11 1713 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1714}
1715
8a0da21b
AD		 1716static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1717 struct sk_buff *skb)
aa80175a 1718{
93f93a44 1719 skb_mark_napi_id(skb, &q_vector->napi);
b4640030 1720 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1721 netif_receive_skb(skb);
8a0da21b 1722 else
856f606e 1723 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1724}
43634e82 1725
f800326d
AD		 1726/**
1727 * ixgbe_is_non_eop - process handling of non-EOP buffers
1728 * @rx_ring: Rx ring being processed
1729 * @rx_desc: Rx descriptor for current buffer
1730 * @skb: Current socket buffer containing buffer in progress
1731 *
1732 * This function updates next to clean. If the buffer is an EOP buffer
1733 * this function exits returning false, otherwise it will place the
1734 * sk_buff in the next buffer to be chained and return true indicating
1735 * that this is in fact a non-EOP buffer.
1736 **/
1737static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1738 union ixgbe_adv_rx_desc *rx_desc,
1739 struct sk_buff *skb)
1740{
1741 u32 ntc = rx_ring->next_to_clean + 1;
1742
1743 /* fetch, update, and store next to clean */
1744 ntc = (ntc < rx_ring->count) ? ntc : 0;
1745 rx_ring->next_to_clean = ntc;
1746
1747 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1748
5a02cbd1
AD		 1749 /* update RSC append count if present */
1750 if (ring_is_rsc_enabled(rx_ring)) {
1751 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1752 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1753
1754 if (unlikely(rsc_enabled)) {
1755 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1756
1757 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1758 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1759
5a02cbd1
AD		 1760 /* update ntc based on RSC value */
1761 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1762 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1763 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1764 }
f800326d
AD		 1765 }
1766
5a02cbd1
AD		 1767 /* if we are the last buffer then there is nothing else to do */
1768 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1769 return false;
1770
f800326d
AD		 1771 /* place skb in next buffer to be received */
1772 rx_ring->rx_buffer_info[ntc].skb = skb;
1773 rx_ring->rx_stats.non_eop_descs++;
1774
1775 return true;
1776}
1777
19861ce2
AD		 1778/**
1779 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1780 * @rx_ring: rx descriptor ring packet is being transacted on
1781 * @skb: pointer to current skb being adjusted
1782 *
1783 * This function is an ixgbe specific version of __pskb_pull_tail. The
1784 * main difference between this version and the original function is that
1785 * this function can make several assumptions about the state of things
1786 * that allow for significant optimizations versus the standard function.
1787 * As a result we can do things like drop a frag and maintain an accurate
1788 * truesize for the skb.
1789 */
1790static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1791 struct sk_buff *skb)
1792{
1793 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1794 unsigned char *va;
1795 unsigned int pull_len;
1796
1797 /*
1798 * it is valid to use page_address instead of kmap since we are
1799 * working with pages allocated out of the lomem pool per
1800 * alloc_page(GFP_ATOMIC)
1801 */
1802 va = skb_frag_address(frag);
1803
1804 /*
1805 * we need the header to contain the greater of either ETH_HLEN or
1806 * 60 bytes if the skb->len is less than 60 for skb_pad.
1807 */
8496e338 1808 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1809
1810 /* align pull length to size of long to optimize memcpy performance */
1811 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1812
1813 /* update all of the pointers */
1814 skb_frag_size_sub(frag, pull_len);
1815 frag->page_offset += pull_len;
1816 skb->data_len -= pull_len;
1817 skb->tail += pull_len;
19861ce2
AD		 1818}
1819
42073d91
AD		 1820/**
1821 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1822 * @rx_ring: rx descriptor ring packet is being transacted on
1823 * @skb: pointer to current skb being updated
1824 *
1825 * This function provides a basic DMA sync up for the first fragment of an
1826 * skb. The reason for doing this is that the first fragment cannot be
1827 * unmapped until we have reached the end of packet descriptor for a buffer
1828 * chain.
1829 */
1830static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1831 struct sk_buff *skb)
1832{
1833 /* if the page was released unmap it, else just sync our portion */
1834 if (unlikely(IXGBE_CB(skb)->page_released)) {
1835 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1836 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1837 IXGBE_CB(skb)->page_released = false;
1838 } else {
1839 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1840
1841 dma_sync_single_range_for_cpu(rx_ring->dev,
1842 IXGBE_CB(skb)->dma,
1843 frag->page_offset,
1844 ixgbe_rx_bufsz(rx_ring),
1845 DMA_FROM_DEVICE);
1846 }
1847 IXGBE_CB(skb)->dma = 0;
1848}
1849
f800326d
AD		 1850/**
1851 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1852 * @rx_ring: rx descriptor ring packet is being transacted on
1853 * @rx_desc: pointer to the EOP Rx descriptor
1854 * @skb: pointer to current skb being fixed
1855 *
1856 * Check for corrupted packet headers caused by senders on the local L2
1857 * embedded NIC switch not setting up their Tx Descriptors right. These
1858 * should be very rare.
1859 *
1860 * Also address the case where we are pulling data in on pages only
1861 * and as such no data is present in the skb header.
1862 *
1863 * In addition if skb is not at least 60 bytes we need to pad it so that
1864 * it is large enough to qualify as a valid Ethernet frame.
1865 *
1866 * Returns true if an error was encountered and skb was freed.
1867 **/
1868static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1869 union ixgbe_adv_rx_desc *rx_desc,
1870 struct sk_buff *skb)
1871{
f800326d 1872 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1873
1874 /* verify that the packet does not have any known errors */
1875 if (unlikely(ixgbe_test_staterr(rx_desc,
1876 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1877 !(netdev->features & NETIF_F_RXALL))) {
1878 dev_kfree_skb_any(skb);
1879 return true;
1880 }
1881
19861ce2 1882 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1883 if (skb_is_nonlinear(skb))
1884 ixgbe_pull_tail(rx_ring, skb);
f800326d 1885
57efd44c
AD		 1886#ifdef IXGBE_FCOE
1887 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1888 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1889 return false;
1890
1891#endif
a94d9e22
AD		 1892 /* if eth_skb_pad returns an error the skb was freed */
1893 if (eth_skb_pad(skb))
1894 return true;
f800326d
AD		 1895
1896 return false;
1897}
1898
f800326d
AD		 1899/**
1900 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1901 * @rx_ring: rx descriptor ring to store buffers on
1902 * @old_buff: donor buffer to have page reused
1903 *
0549ae20 1904 * Synchronizes page for reuse by the adapter
f800326d
AD		 1905 **/
1906static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1907 struct ixgbe_rx_buffer *old_buff)
1908{
1909 struct ixgbe_rx_buffer *new_buff;
1910 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1911
1912 new_buff = &rx_ring->rx_buffer_info[nta];
1913
1914 /* update, and store next to alloc */
1915 nta++;
1916 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1917
1918 /* transfer page from old buffer to new buffer */
18cb652a 1919 *new_buff = *old_buff;
f800326d
AD		 1920
1921 /* sync the buffer for use by the device */
1922 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1923 new_buff->page_offset,
1924 ixgbe_rx_bufsz(rx_ring),
f800326d 1925 DMA_FROM_DEVICE);
f800326d
AD		 1926}
1927
18cb652a
AD		 1928static inline bool ixgbe_page_is_reserved(struct page *page)
1929{
2f064f34 1930 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1931}
1932
f800326d
AD		 1933/**
1934 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1935 * @rx_ring: rx descriptor ring to transact packets on
1936 * @rx_buffer: buffer containing page to add
1937 * @rx_desc: descriptor containing length of buffer written by hardware
1938 * @skb: sk_buff to place the data into
1939 *
0549ae20
AD		 1940 * This function will add the data contained in rx_buffer->page to the skb.
1941 * This is done either through a direct copy if the data in the buffer is
1942 * less than the skb header size, otherwise it will just attach the page as
1943 * a frag to the skb.
1944 *
1945 * The function will then update the page offset if necessary and return
1946 * true if the buffer can be reused by the adapter.
f800326d 1947 **/
0549ae20 1948static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1949 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1950 union ixgbe_adv_rx_desc *rx_desc,
1951 struct sk_buff *skb)
f800326d 1952{
0549ae20
AD		 1953 struct page *page = rx_buffer->page;
1954 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1955#if (PAGE_SIZE < 8192)
0549ae20 1956 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1957#else
1958 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1959 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1960 ixgbe_rx_bufsz(rx_ring);
1961#endif
0549ae20 1962
cf3fe7ac
AD		 1963 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1964 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1965
1966 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1967
18cb652a
AD		 1968 /* page is not reserved, we can reuse buffer as-is */
1969 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1970 return true;
1971
1972 /* this page cannot be reused so discard it */
18cb652a 1973 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1974 return false;
1975 }
1976
0549ae20
AD		 1977 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1978 rx_buffer->page_offset, size, truesize);
1979
09816fbe 1980 /* avoid re-using remote pages */
18cb652a 1981 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1982 return false;
1983
1984#if (PAGE_SIZE < 8192)
1985 /* if we are only owner of page we can reuse it */
1986 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1987 return false;
1988
1989 /* flip page offset to other buffer */
1990 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1991#else
1992 /* move offset up to the next cache line */
1993 rx_buffer->page_offset += truesize;
1994
1995 if (rx_buffer->page_offset > last_offset)
1996 return false;
09816fbe 1997#endif
0549ae20 1998
18cb652a
AD		 1999 /* Even if we own the page, we are not allowed to use atomic_set()
2000 * This would break get_page_unless_zero() users.
2001 */
fe896d18 2002 page_ref_inc(page);
18cb652a 2003
0549ae20 2004 return true;
f800326d
AD		 2005}
2006
18806c9e
AD		 2007static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
2008 union ixgbe_adv_rx_desc *rx_desc)
2009{
2010 struct ixgbe_rx_buffer *rx_buffer;
2011 struct sk_buff *skb;
2012 struct page *page;
2013
2014 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2015 page = rx_buffer->page;
2016 prefetchw(page);
2017
2018 skb = rx_buffer->skb;
2019
2020 if (likely(!skb)) {
2021 void *page_addr = page_address(page) +
2022 rx_buffer->page_offset;
2023
2024 /* prefetch first cache line of first page */
2025 prefetch(page_addr);
2026#if L1_CACHE_BYTES < 128
2027 prefetch(page_addr + L1_CACHE_BYTES);
2028#endif
2029
2030 /* allocate a skb to store the frags */
67fd893e
AD		 2031 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
2032 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 2033 if (unlikely(!skb)) {
2034 rx_ring->rx_stats.alloc_rx_buff_failed++;
2035 return NULL;
2036 }
2037
2038 /*
2039 * we will be copying header into skb->data in
2040 * pskb_may_pull so it is in our interest to prefetch
2041 * it now to avoid a possible cache miss
2042 */
2043 prefetchw(skb->data);
2044
2045 /*
2046 * Delay unmapping of the first packet. It carries the
2047 * header information, HW may still access the header
2048 * after the writeback. Only unmap it when EOP is
2049 * reached
2050 */
2051 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2052 goto dma_sync;
2053
2054 IXGBE_CB(skb)->dma = rx_buffer->dma;
2055 } else {
2056 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2057 ixgbe_dma_sync_frag(rx_ring, skb);
2058
2059dma_sync:
2060 /* we are reusing so sync this buffer for CPU use */
2061 dma_sync_single_range_for_cpu(rx_ring->dev,
2062 rx_buffer->dma,
2063 rx_buffer->page_offset,
2064 ixgbe_rx_bufsz(rx_ring),
2065 DMA_FROM_DEVICE);
18cb652a
AD		 2066
2067 rx_buffer->skb = NULL;
18806c9e
AD		 2068 }
2069
2070 /* pull page into skb */
2071 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2072 /* hand second half of page back to the ring */
2073 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2074 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2075 /* the page has been released from the ring */
2076 IXGBE_CB(skb)->page_released = true;
2077 } else {
2078 /* we are not reusing the buffer so unmap it */
2079 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2080 ixgbe_rx_pg_size(rx_ring),
2081 DMA_FROM_DEVICE);
2082 }
2083
2084 /* clear contents of buffer_info */
18806c9e
AD		 2085 rx_buffer->page = NULL;
2086
2087 return skb;
f800326d
AD		 2088}
2089
2090/**
2091 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2092 * @q_vector: structure containing interrupt and ring information
2093 * @rx_ring: rx descriptor ring to transact packets on
2094 * @budget: Total limit on number of packets to process
2095 *
2096 * This function provides a "bounce buffer" approach to Rx interrupt
2097 * processing. The advantage to this is that on systems that have
2098 * expensive overhead for IOMMU access this provides a means of avoiding
2099 * it by maintaining the mapping of the page to the syste.
2100 *
5a85e737 2101 * Returns amount of work completed
f800326d 2102 **/
5a85e737 2103static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2104 struct ixgbe_ring *rx_ring,
f4de00ed 2105 const int budget)
9a799d71 2106{
d2f4fbe2 2107 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2108#ifdef IXGBE_FCOE
f800326d 2109 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2110 int ddp_bytes;
2111 unsigned int mss = 0;
3d8fd385 2112#endif /* IXGBE_FCOE */
f800326d 2113 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2114
fdabfc8a 2115 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2116 union ixgbe_adv_rx_desc *rx_desc;
2117 struct sk_buff *skb;
f800326d
AD		 2118
2119 /* return some buffers to hardware, one at a time is too slow */
2120 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2121 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2122 cleaned_count = 0;
2123 }
2124
18806c9e 2125 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2126
124b74c1 2127 if (!rx_desc->wb.upper.status_error)
f800326d 2128 break;
9a799d71 2129
124b74c1 2130 /* This memory barrier is needed to keep us from reading
f800326d 2131 * any other fields out of the rx_desc until we know the
124b74c1 2132 * descriptor has been written back
f800326d 2133 */
124b74c1 2134 dma_rmb();
9a799d71 2135
18806c9e
AD		 2136 /* retrieve a buffer from the ring */
2137 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2138
18806c9e
AD		 2139 /* exit if we failed to retrieve a buffer */
2140 if (!skb)
2141 break;
9a799d71 2142
9a799d71 2143 cleaned_count++;
f8212f97 2144
f800326d
AD		 2145 /* place incomplete frames back on ring for completion */
2146 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2147 continue;
c267fc16 2148
f800326d
AD		 2149 /* verify the packet layout is correct */
2150 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2151 continue;
9a799d71 2152
d2f4fbe2
AV		 2153 /* probably a little skewed due to removing CRC */
2154 total_rx_bytes += skb->len;
d2f4fbe2 2155
8a0da21b
AD		 2156 /* populate checksum, timestamp, VLAN, and protocol */
2157 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2158
332d4a7d
YZ		 2159#ifdef IXGBE_FCOE
2160 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2161 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2162 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2163 /* include DDPed FCoE data */
2164 if (ddp_bytes > 0) {
2165 if (!mss) {
2166 mss = rx_ring->netdev->mtu -
2167 sizeof(struct fcoe_hdr) -
2168 sizeof(struct fc_frame_header) -
2169 sizeof(struct fcoe_crc_eof);
2170 if (mss > 512)
2171 mss &= ~511;
2172 }
2173 total_rx_bytes += ddp_bytes;
2174 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2175 mss);
2176 }
63d635b2
AD		 2177 if (!ddp_bytes) {
2178 dev_kfree_skb_any(skb);
f800326d 2179 continue;
63d635b2 2180 }
3d8fd385 2181 }
f800326d 2182
332d4a7d 2183#endif /* IXGBE_FCOE */
8a0da21b 2184 ixgbe_rx_skb(q_vector, skb);
9a799d71 2185
f800326d 2186 /* update budget accounting */
f4de00ed 2187 total_rx_packets++;
fdabfc8a 2188 }
9a799d71 2189
c267fc16
AD		 2190 u64_stats_update_begin(&rx_ring->syncp);
2191 rx_ring->stats.packets += total_rx_packets;
2192 rx_ring->stats.bytes += total_rx_bytes;
2193 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2194 q_vector->rx.total_packets += total_rx_packets;
2195 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2196
5a85e737 2197 return total_rx_packets;
9a799d71
AK		 2198}
2199
e0d1095a 2200#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2201/* must be called with local_bh_disable()d */
2202static int ixgbe_low_latency_recv(struct napi_struct *napi)
2203{
2204 struct ixgbe_q_vector *q_vector =
2205 container_of(napi, struct ixgbe_q_vector, napi);
2206 struct ixgbe_adapter *adapter = q_vector->adapter;
2207 struct ixgbe_ring *ring;
2208 int found = 0;
2209
2210 if (test_bit(__IXGBE_DOWN, &adapter->state))
2211 return LL_FLUSH_FAILED;
2212
2213 if (!ixgbe_qv_lock_poll(q_vector))
2214 return LL_FLUSH_BUSY;
2215
2216 ixgbe_for_each_ring(ring, q_vector->rx) {
2217 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2218#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2219 if (found)
2220 ring->stats.cleaned += found;
2221 else
2222 ring->stats.misses++;
2223#endif
5a85e737
ET		 2224 if (found)
2225 break;
2226 }
2227
2228 ixgbe_qv_unlock_poll(q_vector);
2229
2230 return found;
2231}
e0d1095a 2232#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2233
9a799d71
AK		 2234/**
2235 * ixgbe_configure_msix - Configure MSI-X hardware
2236 * @adapter: board private structure
2237 *
2238 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2239 * interrupts.
2240 **/
2241static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2242{
021230d4 2243 struct ixgbe_q_vector *q_vector;
49c7ffbe 2244 int v_idx;
021230d4 2245 u32 mask;
9a799d71 2246
8e34d1aa
AD		 2247 /* Populate MSIX to EITR Select */
2248 if (adapter->num_vfs > 32) {
b4f47a48 2249 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
8e34d1aa
AD		 2250 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2251 }
2252
4df10466
JB		 2253 /*
2254 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2255 * corresponding register.
2256 */
49c7ffbe 2257 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2258 struct ixgbe_ring *ring;
7a921c93 2259 q_vector = adapter->q_vector[v_idx];
021230d4 2260
a557928e 2261 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2262 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2263
a557928e 2264 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2265 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2266
fe49f04a 2267 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2268 }
2269
bd508178
AD		 2270 switch (adapter->hw.mac.type) {
2271 case ixgbe_mac_82598EB:
e8e26350 2272 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2273 v_idx);
bd508178
AD		 2274 break;
2275 case ixgbe_mac_82599EB:
b93a2226 2276 case ixgbe_mac_X540:
9a75a1ac
DS		 2277 case ixgbe_mac_X550:
2278 case ixgbe_mac_X550EM_x:
49425dfc 2279 case ixgbe_mac_x550em_a:
e8e26350 2280 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2281 break;
bd508178
AD		 2282 default:
2283 break;
2284 }
021230d4
AV		 2285 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2286
41fb9248 2287 /* set up to autoclear timer, and the vectors */
021230d4 2288 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2289 mask &= ~(IXGBE_EIMS_OTHER |
2290 IXGBE_EIMS_MAILBOX |
2291 IXGBE_EIMS_LSC);
2292
021230d4 2293 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2294}
2295
f494e8fa
AV		 2296enum latency_range {
2297 lowest_latency = 0,
2298 low_latency = 1,
2299 bulk_latency = 2,
2300 latency_invalid = 255
2301};
2302
2303/**
2304 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2305 * @q_vector: structure containing interrupt and ring information
2306 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2307 *
2308 * Stores a new ITR value based on packets and byte
2309 * counts during the last interrupt. The advantage of per interrupt
2310 * computation is faster updates and more accurate ITR for the current
2311 * traffic pattern. Constants in this function were computed
2312 * based on theoretical maximum wire speed and thresholds were set based
2313 * on testing data as well as attempting to minimize response time
2314 * while increasing bulk throughput.
2315 * this functionality is controlled by the InterruptThrottleRate module
2316 * parameter (see ixgbe_param.c)
2317 **/
bd198058
AD		 2318static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2319 struct ixgbe_ring_container *ring_container)
f494e8fa 2320{
bd198058
AD		 2321 int bytes = ring_container->total_bytes;
2322 int packets = ring_container->total_packets;
2323 u32 timepassed_us;
621bd70e 2324 u64 bytes_perint;
bd198058 2325 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2326
2327 if (packets == 0)
bd198058 2328 return;
f494e8fa
AV		 2329
2330 /* simple throttlerate management
621bd70e
AD		 2331 * 0-10MB/s lowest (100000 ints/s)
2332 * 10-20MB/s low (20000 ints/s)
8ac34f10 2333 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2334 */
2335 /* what was last interrupt timeslice? */
d5bf4f67 2336 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2337 if (timepassed_us == 0)
2338 return;
2339
f494e8fa
AV		 2340 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2341
2342 switch (itr_setting) {
2343 case lowest_latency:
621bd70e 2344 if (bytes_perint > 10)
bd198058 2345 itr_setting = low_latency;
f494e8fa
AV		 2346 break;
2347 case low_latency:
621bd70e 2348 if (bytes_perint > 20)
bd198058 2349 itr_setting = bulk_latency;
621bd70e 2350 else if (bytes_perint <= 10)
bd198058 2351 itr_setting = lowest_latency;
f494e8fa
AV		 2352 break;
2353 case bulk_latency:
621bd70e 2354 if (bytes_perint <= 20)
bd198058 2355 itr_setting = low_latency;
f494e8fa
AV		 2356 break;
2357 }
2358
bd198058
AD		 2359 /* clear work counters since we have the values we need */
2360 ring_container->total_bytes = 0;
2361 ring_container->total_packets = 0;
2362
2363 /* write updated itr to ring container */
2364 ring_container->itr = itr_setting;
f494e8fa
AV		 2365}
2366
509ee935
JB		 2367/**
2368 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2369 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2370 *
2371 * This function is made to be called by ethtool and by the driver
2372 * when it needs to update EITR registers at runtime. Hardware
2373 * specific quirks/differences are taken care of here.
2374 */
fe49f04a 2375void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2376{
fe49f04a 2377 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2378 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2379 int v_idx = q_vector->v_idx;
5d967eb7 2380 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2381
bd508178
AD		 2382 switch (adapter->hw.mac.type) {
2383 case ixgbe_mac_82598EB:
509ee935
JB		 2384 /* must write high and low 16 bits to reset counter */
2385 itr_reg |= (itr_reg << 16);
bd508178
AD		 2386 break;
2387 case ixgbe_mac_82599EB:
b93a2226 2388 case ixgbe_mac_X540:
9a75a1ac
DS		 2389 case ixgbe_mac_X550:
2390 case ixgbe_mac_X550EM_x:
49425dfc 2391 case ixgbe_mac_x550em_a:
509ee935
JB		 2392 /*
2393 * set the WDIS bit to not clear the timer bits and cause an
2394 * immediate assertion of the interrupt
2395 */
2396 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2397 break;
2398 default:
2399 break;
509ee935
JB		 2400 }
2401 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2402}
2403
bd198058 2404static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2405{
d5bf4f67 2406 u32 new_itr = q_vector->itr;
bd198058 2407 u8 current_itr;
f494e8fa 2408
bd198058
AD		 2409 ixgbe_update_itr(q_vector, &q_vector->tx);
2410 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2411
08c8833b 2412 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2413
2414 switch (current_itr) {
2415 /* counts and packets in update_itr are dependent on these numbers */
2416 case lowest_latency:
d5bf4f67 2417 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2418 break;
2419 case low_latency:
d5bf4f67 2420 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2421 break;
2422 case bulk_latency:
8ac34f10 2423 new_itr = IXGBE_12K_ITR;
f494e8fa 2424 break;
bd198058
AD		 2425 default:
2426 break;
f494e8fa
AV		 2427 }
2428
d5bf4f67 2429 if (new_itr != q_vector->itr) {
fe49f04a 2430 /* do an exponential smoothing */
d5bf4f67
ET		 2431 new_itr = (10 * new_itr * q_vector->itr) /
2432 ((9 * new_itr) + q_vector->itr);
509ee935 2433
bd198058 2434 /* save the algorithm value here */
5d967eb7 2435 q_vector->itr = new_itr;
fe49f04a
AD		 2436
2437 ixgbe_write_eitr(q_vector);
f494e8fa 2438 }
f494e8fa
AV		 2439}
2440
119fc60a 2441/**
de88eeeb 2442 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2443 * @adapter: pointer to adapter
119fc60a 2444 **/
f0f9778d 2445static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2446{
119fc60a
MC		 2447 struct ixgbe_hw *hw = &adapter->hw;
2448 u32 eicr = adapter->interrupt_event;
2449
f0f9778d 2450 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2451 return;
2452
f0f9778d
AD		 2453 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2454 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2455 return;
2456
2457 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2458
7ca647bd 2459 switch (hw->device_id) {
f0f9778d
AD		 2460 case IXGBE_DEV_ID_82599_T3_LOM:
2461 /*
2462 * Since the warning interrupt is for both ports
2463 * we don't have to check if:
2464 * - This interrupt wasn't for our port.
2465 * - We may have missed the interrupt so always have to
2466 * check if we got a LSC
2467 */
9a900eca 2468 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2469 !(eicr & IXGBE_EICR_LSC))
2470 return;
2471
2472 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2473 u32 speed;
f0f9778d 2474 bool link_up = false;
7ca647bd 2475
3d292265 2476 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2477
f0f9778d
AD		 2478 if (link_up)
2479 return;
2480 }
2481
2482 /* Check if this is not due to overtemp */
2483 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2484 return;
2485
2486 break;
7ca647bd 2487 default:
597f22d6
DS		 2488 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2489 return;
9a900eca 2490 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2491 return;
7ca647bd 2492 break;
119fc60a 2493 }
f44e751b 2494 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2495
2496 adapter->interrupt_event = 0;
119fc60a
MC		 2497}
2498
0befdb3e
JB		 2499static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2500{
2501 struct ixgbe_hw *hw = &adapter->hw;
2502
2503 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2504 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2505 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2506 /* write to clear the interrupt */
9a900eca 2507 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2508 }
2509}
cf8280ee 2510
4f51bf70
JK		 2511static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2512{
9a900eca
DS		 2513 struct ixgbe_hw *hw = &adapter->hw;
2514
4f51bf70
JK		 2515 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2516 return;
2517
2518 switch (adapter->hw.mac.type) {
2519 case ixgbe_mac_82599EB:
2520 /*
2521 * Need to check link state so complete overtemp check
2522 * on service task
2523 */
9a900eca
DS		 2524 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2525 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2526 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2527 adapter->interrupt_event = eicr;
2528 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2529 ixgbe_service_event_schedule(adapter);
2530 return;
2531 }
2532 return;
2533 case ixgbe_mac_X540:
2534 if (!(eicr & IXGBE_EICR_TS))
2535 return;
2536 break;
2537 default:
2538 return;
2539 }
2540
f44e751b 2541 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2542}
2543
45788d2a
DS		 2544static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2545{
2546 switch (hw->mac.type) {
2547 case ixgbe_mac_82598EB:
2548 if (hw->phy.type == ixgbe_phy_nl)
2549 return true;
2550 return false;
2551 case ixgbe_mac_82599EB:
2552 case ixgbe_mac_X550EM_x:
49425dfc 2553 case ixgbe_mac_x550em_a:
45788d2a
DS		 2554 switch (hw->mac.ops.get_media_type(hw)) {
2555 case ixgbe_media_type_fiber:
2556 case ixgbe_media_type_fiber_qsfp:
2557 return true;
2558 default:
2559 return false;
2560 }
2561 default:
2562 return false;
2563 }
2564}
2565
e8e26350
PW		 2566static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2567{
2568 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2569 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2570
4ccc650c
DS		 2571 if (!ixgbe_is_sfp(hw))
2572 return;
2573
2574 /* Later MAC's use different SDP */
2575 if (hw->mac.type >= ixgbe_mac_X540)
2576 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2577
2578 if (eicr & eicr_mask) {
73c4b7cd 2579 /* Clear the interrupt */
4ccc650c 2580 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2581 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2582 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2583 adapter->sfp_poll_time = 0;
7086400d
AD		 2584 ixgbe_service_event_schedule(adapter);
2585 }
73c4b7cd
AD		 2586 }
2587
4ccc650c
DS		 2588 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2589 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2590 /* Clear the interrupt */
9a900eca 2591 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2592 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2593 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2594 ixgbe_service_event_schedule(adapter);
2595 }
e8e26350
PW		 2596 }
2597}
2598
cf8280ee
JB		 2599static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2600{
2601 struct ixgbe_hw *hw = &adapter->hw;
2602
2603 adapter->lsc_int++;
2604 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2605 adapter->link_check_timeout = jiffies;
2606 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2607 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2608 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2609 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2610 }
2611}
2612
fe49f04a
AD		 2613static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2614 u64 qmask)
2615{
2616 u32 mask;
bd508178 2617 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2618
bd508178
AD		 2619 switch (hw->mac.type) {
2620 case ixgbe_mac_82598EB:
fe49f04a 2621 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2622 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2623 break;
2624 case ixgbe_mac_82599EB:
b93a2226 2625 case ixgbe_mac_X540:
9a75a1ac
DS		 2626 case ixgbe_mac_X550:
2627 case ixgbe_mac_X550EM_x:
49425dfc 2628 case ixgbe_mac_x550em_a:
fe49f04a 2629 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2630 if (mask)
2631 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2632 mask = (qmask >> 32);
bd508178
AD		 2633 if (mask)
2634 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2635 break;
2636 default:
2637 break;
fe49f04a
AD		 2638 }
2639 /* skip the flush */
2640}
2641
2642static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2643 u64 qmask)
fe49f04a
AD		 2644{
2645 u32 mask;
bd508178 2646 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2647
bd508178
AD		 2648 switch (hw->mac.type) {
2649 case ixgbe_mac_82598EB:
fe49f04a 2650 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2651 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2652 break;
2653 case ixgbe_mac_82599EB:
b93a2226 2654 case ixgbe_mac_X540:
9a75a1ac
DS		 2655 case ixgbe_mac_X550:
2656 case ixgbe_mac_X550EM_x:
49425dfc 2657 case ixgbe_mac_x550em_a:
fe49f04a 2658 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2659 if (mask)
2660 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2661 mask = (qmask >> 32);
bd508178
AD		 2662 if (mask)
2663 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2664 break;
2665 default:
2666 break;
fe49f04a
AD		 2667 }
2668 /* skip the flush */
2669}
2670
021230d4 2671/**
2c4af694
AD		 2672 * ixgbe_irq_enable - Enable default interrupt generation settings
2673 * @adapter: board private structure
021230d4 2674 **/
2c4af694
AD		 2675static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2676 bool flush)
9a799d71 2677{
9a900eca 2678 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2679 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2680
2c4af694
AD		 2681 /* don't reenable LSC while waiting for link */
2682 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2683 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2684
2c4af694 2685 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2686 switch (adapter->hw.mac.type) {
2687 case ixgbe_mac_82599EB:
9a900eca 2688 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2689 break;
2690 case ixgbe_mac_X540:
9a75a1ac
DS		 2691 case ixgbe_mac_X550:
2692 case ixgbe_mac_X550EM_x:
49425dfc 2693 case ixgbe_mac_x550em_a:
4f51bf70
JK		 2694 mask |= IXGBE_EIMS_TS;
2695 break;
2696 default:
2697 break;
2698 }
2c4af694 2699 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2700 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2701 switch (adapter->hw.mac.type) {
2702 case ixgbe_mac_82599EB:
9a900eca
DS		 2703 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2704 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2705 /* fall through */
858bc081 2706 case ixgbe_mac_X540:
9a75a1ac
DS		 2707 case ixgbe_mac_X550:
2708 case ixgbe_mac_X550EM_x:
49425dfc
MR		 2709 case ixgbe_mac_x550em_a:
2710 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
2d40cd17 2711 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
49425dfc 2712 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
cbd45ec7 2713 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2714 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2715 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2716 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2717 mask |= IXGBE_EIMS_MAILBOX;
2718 break;
2719 default:
2720 break;
9a799d71 2721 }
db0677fa 2722
2c4af694
AD		 2723 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2724 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2725 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2726
2c4af694
AD		 2727 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2728 if (queues)
2729 ixgbe_irq_enable_queues(adapter, ~0);
2730 if (flush)
2731 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2732}
2733
2c4af694 2734static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2735{
a65151ba 2736 struct ixgbe_adapter *adapter = data;
9a799d71 2737 struct ixgbe_hw *hw = &adapter->hw;
54037505 2738 u32 eicr;
91281fd3 2739
54037505
DS		 2740 /*
2741 * Workaround for Silicon errata. Use clear-by-write instead
2742 * of clear-by-read. Reading with EICS will return the
2743 * interrupt causes without clearing, which later be done
2744 * with the write to EICR.
2745 */
2746 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2747
2748 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2749 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2750 * the bits are high when ixgbe_msix_other is called. There is a race
2751 * condition otherwise which results in possible performance loss
2752 * especially if the ixgbe_msix_other interrupt is triggering
2753 * consistently (as it would when PPS is turned on for the X540 device)
2754 */
2755 eicr &= 0xFFFF0000;
2756
54037505 2757 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2758
cf8280ee
JB		 2759 if (eicr & IXGBE_EICR_LSC)
2760 ixgbe_check_lsc(adapter);
f0848276 2761
1cdd1ec8
GR		 2762 if (eicr & IXGBE_EICR_MAILBOX)
2763 ixgbe_msg_task(adapter);
efe3d3c8 2764
bd508178
AD		 2765 switch (hw->mac.type) {
2766 case ixgbe_mac_82599EB:
b93a2226 2767 case ixgbe_mac_X540:
9a75a1ac
DS		 2768 case ixgbe_mac_X550:
2769 case ixgbe_mac_X550EM_x:
49425dfc 2770 case ixgbe_mac_x550em_a:
597f22d6
DS		 2771 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2772 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2773 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2774 ixgbe_service_event_schedule(adapter);
2775 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2776 IXGBE_EICR_GPI_SDP0_X540);
2777 }
d773ce2d
DS		 2778 if (eicr & IXGBE_EICR_ECC) {
2779 e_info(link, "Received ECC Err, initiating reset\n");
57ca2a4f 2780 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
d773ce2d
DS		 2781 ixgbe_service_event_schedule(adapter);
2782 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2783 }
c4cf55e5
PWJ		 2784 /* Handle Flow Director Full threshold interrupt */
2785 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2786 int reinit_count = 0;
c4cf55e5 2787 int i;
c4cf55e5 2788 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2789 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2790 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2791 &ring->state))
2792 reinit_count++;
2793 }
2794 if (reinit_count) {
2795 /* no more flow director interrupts until after init */
2796 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2797 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2798 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2799 }
2800 }
f0f9778d 2801 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2802 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2803 break;
2804 default:
2805 break;
c4cf55e5 2806 }
f0848276 2807
bd508178 2808 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2809
db0677fa 2810 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2811 ixgbe_ptp_check_pps_event(adapter);
efe3d3c8 2812
7086400d 2813 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2814 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2815 ixgbe_irq_enable(adapter, false, false);
f0848276 2816
9a799d71 2817 return IRQ_HANDLED;
f0848276 2818}
91281fd3 2819
4ff7fb12 2820static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2821{
021230d4 2822 struct ixgbe_q_vector *q_vector = data;
91281fd3 2823
9b471446 2824 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2825
4ff7fb12 2826 if (q_vector->rx.ring || q_vector->tx.ring)
ef2662b2 2827 napi_schedule_irqoff(&q_vector->napi);
91281fd3 2828
9a799d71 2829 return IRQ_HANDLED;
91281fd3
AD		 2830}
2831
eb01b975
AD		 2832/**
2833 * ixgbe_poll - NAPI Rx polling callback
2834 * @napi: structure for representing this polling device
2835 * @budget: how many packets driver is allowed to clean
2836 *
2837 * This function is used for legacy and MSI, NAPI mode
2838 **/
8af3c33f 2839int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2840{
2841 struct ixgbe_q_vector *q_vector =
2842 container_of(napi, struct ixgbe_q_vector, napi);
2843 struct ixgbe_adapter *adapter = q_vector->adapter;
2844 struct ixgbe_ring *ring;
32b3e08f 2845 int per_ring_budget, work_done = 0;
eb01b975
AD		 2846 bool clean_complete = true;
2847
2848#ifdef CONFIG_IXGBE_DCA
2849 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2850 ixgbe_update_dca(q_vector);
2851#endif
2852
8220bbc1
AD		 2853 ixgbe_for_each_ring(ring, q_vector->tx) {
2854 if (!ixgbe_clean_tx_irq(q_vector, ring, budget))
2855 clean_complete = false;
2856 }
eb01b975 2857
5d6002b7
AD		 2858 /* Exit if we are called by netpoll or busy polling is active */
2859 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
5a85e737
ET		 2860 return budget;
2861
eb01b975
AD		 2862 /* attempt to distribute budget to each queue fairly, but don't allow
2863 * the budget to go below 1 because we'll exit polling */
2864 if (q_vector->rx.count > 1)
2865 per_ring_budget = max(budget/q_vector->rx.count, 1);
2866 else
2867 per_ring_budget = budget;
2868
32b3e08f
JB		 2869 ixgbe_for_each_ring(ring, q_vector->rx) {
2870 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2871 per_ring_budget);
2872
2873 work_done += cleaned;
8220bbc1
AD		 2874 if (cleaned >= per_ring_budget)
2875 clean_complete = false;
32b3e08f 2876 }
eb01b975 2877
5a85e737 2878 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2879 /* If all work not completed, return budget and keep polling */
2880 if (!clean_complete)
2881 return budget;
2882
2883 /* all work done, exit the polling mode */
32b3e08f 2884 napi_complete_done(napi, work_done);
eb01b975
AD		 2885 if (adapter->rx_itr_setting & 1)
2886 ixgbe_set_itr(q_vector);
2887 if (!test_bit(__IXGBE_DOWN, &adapter->state))
b4f47a48 2888 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx));
eb01b975 2889
4b732cd4 2890 return min(work_done, budget - 1);
eb01b975
AD		 2891}
2892
021230d4
AV		 2893/**
2894 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2895 * @adapter: board private structure
2896 *
2897 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2898 * interrupts from the kernel.
2899 **/
2900static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2901{
2902 struct net_device *netdev = adapter->netdev;
207867f5 2903 int vector, err;
e8e9f696 2904 int ri = 0, ti = 0;
021230d4 2905
49c7ffbe 2906 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2907 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2908 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2909
4ff7fb12 2910 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2911 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2912 "%s-%s-%d", netdev->name, "TxRx", ri++);
2913 ti++;
2914 } else if (q_vector->rx.ring) {
9fe93afd 2915 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2916 "%s-%s-%d", netdev->name, "rx", ri++);
2917 } else if (q_vector->tx.ring) {
9fe93afd 2918 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2919 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2920 } else {
2921 /* skip this unused q_vector */
2922 continue;
32aa77a4 2923 }
207867f5
AD		 2924 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2925 q_vector->name, q_vector);
9a799d71 2926 if (err) {
396e799c 2927 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2928 "Error: %d\n", err);
021230d4 2929 goto free_queue_irqs;
9a799d71 2930 }
207867f5
AD		 2931 /* If Flow Director is enabled, set interrupt affinity */
2932 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2933 /* assign the mask for this irq */
2934 irq_set_affinity_hint(entry->vector,
de88eeeb 2935 &q_vector->affinity_mask);
207867f5 2936 }
9a799d71
AK		 2937 }
2938
021230d4 2939 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2940 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2941 if (err) {
de88eeeb 2942 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2943 goto free_queue_irqs;
9a799d71
AK		 2944 }
2945
9a799d71
AK		 2946 return 0;
2947
021230d4 2948free_queue_irqs:
207867f5
AD		 2949 while (vector) {
2950 vector--;
2951 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2952 NULL);
2953 free_irq(adapter->msix_entries[vector].vector,
2954 adapter->q_vector[vector]);
2955 }
021230d4
AV		 2956 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2957 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2958 kfree(adapter->msix_entries);
2959 adapter->msix_entries = NULL;
9a799d71
AK		 2960 return err;
2961}
2962
2963/**
021230d4 2964 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2965 * @irq: interrupt number
2966 * @data: pointer to a network interface device structure
9a799d71
AK		 2967 **/
2968static irqreturn_t ixgbe_intr(int irq, void *data)
2969{
a65151ba 2970 struct ixgbe_adapter *adapter = data;
9a799d71 2971 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2972 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2973 u32 eicr;
2974
54037505 2975 /*
24ddd967 2976 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2977 * before the read of EICR.
2978 */
2979 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2980
021230d4 2981 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2982 * therefore no explicit interrupt disable is necessary */
021230d4 2983 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2984 if (!eicr) {
6af3b9eb
ET		 2985 /*
2986 * shared interrupt alert!
f47cf66e 2987 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2988 * have disabled interrupts due to EIAM
2989 * finish the workaround of silicon errata on 82598. Unmask
2990 * the interrupt that we masked before the EICR read.
2991 */
2992 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2993 ixgbe_irq_enable(adapter, true, true);
9a799d71 2994 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2995 }
9a799d71 2996
cf8280ee
JB		 2997 if (eicr & IXGBE_EICR_LSC)
2998 ixgbe_check_lsc(adapter);
021230d4 2999
bd508178
AD		 3000 switch (hw->mac.type) {
3001 case ixgbe_mac_82599EB:
e8e26350 3002 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 3003 /* Fall through */
3004 case ixgbe_mac_X540:
9a75a1ac
DS		 3005 case ixgbe_mac_X550:
3006 case ixgbe_mac_X550EM_x:
49425dfc 3007 case ixgbe_mac_x550em_a:
d773ce2d
DS		 3008 if (eicr & IXGBE_EICR_ECC) {
3009 e_info(link, "Received ECC Err, initiating reset\n");
57ca2a4f 3010 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
d773ce2d
DS		 3011 ixgbe_service_event_schedule(adapter);
3012 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3013 }
4f51bf70 3014 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 3015 break;
3016 default:
3017 break;
3018 }
e8e26350 3019
0befdb3e 3020 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 3021 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 3022 ixgbe_ptp_check_pps_event(adapter);
0befdb3e 3023
b9f6ed2b 3024 /* would disable interrupts here but EIAM disabled it */
ef2662b2 3025 napi_schedule_irqoff(&q_vector->napi);
9a799d71 3026
6af3b9eb
ET		 3027 /*
3028 * re-enable link(maybe) and non-queue interrupts, no flush.
3029 * ixgbe_poll will re-enable the queue interrupts
3030 */
6af3b9eb
ET		 3031 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3032 ixgbe_irq_enable(adapter, false, false);
3033
9a799d71
AK		 3034 return IRQ_HANDLED;
3035}
3036
3037/**
3038 * ixgbe_request_irq - initialize interrupts
3039 * @adapter: board private structure
3040 *
3041 * Attempts to configure interrupts using the best available
3042 * capabilities of the hardware and kernel.
3043 **/
021230d4 3044static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 3045{
3046 struct net_device *netdev = adapter->netdev;
021230d4 3047 int err;
9a799d71 3048
4cc6df29 3049 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 3050 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 3051 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 3052 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 3053 netdev->name, adapter);
4cc6df29 3054 else
a0607fd3 3055 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 3056 netdev->name, adapter);
9a799d71 3057
de88eeeb 3058 if (err)
396e799c 3059 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 3060
9a799d71
AK		 3061 return err;
3062}
3063
3064static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3065{
49c7ffbe 3066 int vector;
9a799d71 3067
49c7ffbe
AD		 3068 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3069 free_irq(adapter->pdev->irq, adapter);
3070 return;
3071 }
4cc6df29 3072
1fa71252
MR		 3073 if (!adapter->msix_entries)
3074 return;
3075
49c7ffbe
AD		 3076 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3077 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3078 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3079
49c7ffbe
AD		 3080 /* free only the irqs that were actually requested */
3081 if (!q_vector->rx.ring && !q_vector->tx.ring)
3082 continue;
207867f5 3083
49c7ffbe
AD		 3084 /* clear the affinity_mask in the IRQ descriptor */
3085 irq_set_affinity_hint(entry->vector, NULL);
3086
3087 free_irq(entry->vector, q_vector);
9a799d71 3088 }
49c7ffbe 3089
90c6f877 3090 free_irq(adapter->msix_entries[vector].vector, adapter);
9a799d71
AK		 3091}
3092
22d5a71b
JB		 3093/**
3094 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3095 * @adapter: board private structure
3096 **/
3097static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3098{
bd508178
AD		 3099 switch (adapter->hw.mac.type) {
3100 case ixgbe_mac_82598EB:
835462fc 3101 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3102 break;
3103 case ixgbe_mac_82599EB:
b93a2226 3104 case ixgbe_mac_X540:
9a75a1ac
DS		 3105 case ixgbe_mac_X550:
3106 case ixgbe_mac_X550EM_x:
49425dfc 3107 case ixgbe_mac_x550em_a:
835462fc
NS		 3108 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3109 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3110 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3111 break;
3112 default:
3113 break;
22d5a71b
JB		 3114 }
3115 IXGBE_WRITE_FLUSH(&adapter->hw);
3116 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3117 int vector;
3118
3119 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3120 synchronize_irq(adapter->msix_entries[vector].vector);
3121
3122 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3123 } else {
3124 synchronize_irq(adapter->pdev->irq);
3125 }
3126}
3127
9a799d71
AK		 3128/**
3129 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3130 *
3131 **/
3132static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3133{
d5bf4f67 3134 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3135
d5bf4f67 3136 ixgbe_write_eitr(q_vector);
9a799d71 3137
e8e26350
PW		 3138 ixgbe_set_ivar(adapter, 0, 0, 0);
3139 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3140
396e799c 3141 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3142}
3143
43e69bf0
AD		 3144/**
3145 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3146 * @adapter: board private structure
3147 * @ring: structure containing ring specific data
3148 *
3149 * Configure the Tx descriptor ring after a reset.
3150 **/
84418e3b
AD		 3151void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3152 struct ixgbe_ring *ring)
43e69bf0
AD		 3153{
3154 struct ixgbe_hw *hw = &adapter->hw;
3155 u64 tdba = ring->dma;
2f1860b8 3156 int wait_loop = 10;
b88c6de2 3157 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3158 u8 reg_idx = ring->reg_idx;
43e69bf0 3159
2f1860b8 3160 /* disable queue to avoid issues while updating state */
b88c6de2 3161 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3162 IXGBE_WRITE_FLUSH(hw);
3163
43e69bf0 3164 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3165 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3166 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3167 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3168 ring->count * sizeof(union ixgbe_adv_tx_desc));
3169 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3170 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3171 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3172
b88c6de2
AD		 3173 /*
3174 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3175 * higher than 1 when:
3176 * - ITR is 0 as it could cause false TX hangs
3177 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3178 *
3179 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3180 * to or less than the number of on chip descriptors, which is
3181 * currently 40.
3182 */
67da097e 3183 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b4f47a48 3184 txdctl |= 1u << 16; /* WTHRESH = 1 */
b88c6de2 3185 else
b4f47a48 3186 txdctl |= 8u << 16; /* WTHRESH = 8 */
b88c6de2 3187
e954b374
AD		 3188 /*
3189 * Setting PTHRESH to 32 both improves performance
3190 * and avoids a TX hang with DFP enabled
3191 */
b4f47a48 3192 txdctl |= (1u << 8) | /* HTHRESH = 1 */
b88c6de2 3193 32; /* PTHRESH = 32 */
2f1860b8
AD		 3194
3195 /* reinitialize flowdirector state */
39cb681b 3196 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3197 ring->atr_sample_rate = adapter->atr_sample_rate;
3198 ring->atr_count = 0;
3199 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3200 } else {
3201 ring->atr_sample_rate = 0;
3202 }
2f1860b8 3203
fd786b7b
AD		 3204 /* initialize XPS */
3205 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3206 struct ixgbe_q_vector *q_vector = ring->q_vector;
3207
3208 if (q_vector)
2a47fa45 3209 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3210 &q_vector->affinity_mask,
3211 ring->queue_index);
3212 }
3213
c84d324c
JF		 3214 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3215
2f1860b8 3216 /* enable queue */
2f1860b8
AD		 3217 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3218
3219 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3220 if (hw->mac.type == ixgbe_mac_82598EB &&
3221 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3222 return;
3223
3224 /* poll to verify queue is enabled */
3225 do {
032b4325 3226 usleep_range(1000, 2000);
2f1860b8
AD		 3227 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3228 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3229 if (!wait_loop)
a55defd8 3230 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3231}
3232
120ff942
AD		 3233static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3234{
3235 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3236 u32 rttdcs, mtqc;
8b1c0b24 3237 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3238
3239 if (hw->mac.type == ixgbe_mac_82598EB)
3240 return;
3241
3242 /* disable the arbiter while setting MTQC */
3243 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3244 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3245 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3246
3247 /* set transmit pool layout */
671c0adb
AD		 3248 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3249 mtqc = IXGBE_MTQC_VT_ENA;
3250 if (tcs > 4)
3251 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3252 else if (tcs > 1)
3253 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
e24fcf28
AD		 3254 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3255 IXGBE_82599_VMDQ_4Q_MASK)
671c0adb
AD		 3256 mtqc |= IXGBE_MTQC_32VF;
3257 else
3258 mtqc |= IXGBE_MTQC_64VF;
3259 } else {
3260 if (tcs > 4)
3261 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3262 else if (tcs > 1)
3263 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3264 else
671c0adb
AD		 3265 mtqc = IXGBE_MTQC_64Q_1PB;
3266 }
120ff942 3267
671c0adb 3268 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3269
671c0adb
AD		 3270 /* Enable Security TX Buffer IFG for multiple pb */
3271 if (tcs) {
3272 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3273 sectx |= IXGBE_SECTX_DCB;
3274 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3275 }
3276
3277 /* re-enable the arbiter */
3278 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3279 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3280}
3281
9a799d71 3282/**
3a581073 3283 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3284 * @adapter: board private structure
3285 *
3286 * Configure the Tx unit of the MAC after a reset.
3287 **/
3288static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3289{
2f1860b8
AD		 3290 struct ixgbe_hw *hw = &adapter->hw;
3291 u32 dmatxctl;
43e69bf0 3292 u32 i;
9a799d71 3293
2f1860b8
AD		 3294 ixgbe_setup_mtqc(adapter);
3295
3296 if (hw->mac.type != ixgbe_mac_82598EB) {
3297 /* DMATXCTL.EN must be before Tx queues are enabled */
3298 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3299 dmatxctl |= IXGBE_DMATXCTL_TE;
3300 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3301 }
3302
9a799d71 3303 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3304 for (i = 0; i < adapter->num_tx_queues; i++)
3305 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3306}
3307
3ebe8fde
AD		 3308static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3309 struct ixgbe_ring *ring)
3310{
3311 struct ixgbe_hw *hw = &adapter->hw;
3312 u8 reg_idx = ring->reg_idx;
3313 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3314
3315 srrctl |= IXGBE_SRRCTL_DROP_EN;
3316
3317 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3318}
3319
3320static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3321 struct ixgbe_ring *ring)
3322{
3323 struct ixgbe_hw *hw = &adapter->hw;
3324 u8 reg_idx = ring->reg_idx;
3325 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3326
3327 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3328
3329 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3330}
3331
3332#ifdef CONFIG_IXGBE_DCB
3333void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3334#else
3335static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3336#endif
3337{
3338 int i;
3339 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3340
3341 if (adapter->ixgbe_ieee_pfc)
3342 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3343
3344 /*
3345 * We should set the drop enable bit if:
3346 * SR-IOV is enabled
3347 * or
3348 * Number of Rx queues > 1 and flow control is disabled
3349 *
3350 * This allows us to avoid head of line blocking for security
3351 * and performance reasons.
3352 */
3353 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3354 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3355 for (i = 0; i < adapter->num_rx_queues; i++)
3356 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3357 } else {
3358 for (i = 0; i < adapter->num_rx_queues; i++)
3359 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3360 }
3361}
3362
e8e26350 3363#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3364
a6616b42 3365static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3366 struct ixgbe_ring *rx_ring)
cc41ac7c 3367{
45e9baa5 3368 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3369 u32 srrctl;
bf29ee6c 3370 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3371
45e9baa5
AD		 3372 if (hw->mac.type == ixgbe_mac_82598EB) {
3373 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3374
45e9baa5
AD		 3375 /*
3376 * if VMDq is not active we must program one srrctl register
3377 * per RSS queue since we have enabled RDRXCTL.MVMEN
3378 */
3379 reg_idx &= mask;
3380 }
cc41ac7c 3381
45e9baa5
AD		 3382 /* configure header buffer length, needed for RSC */
3383 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3384
45e9baa5 3385 /* configure the packet buffer length */
f800326d 3386 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3387
3388 /* configure descriptor type */
f800326d 3389 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3390
45e9baa5 3391 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3392}
9a799d71 3393
dfaf891d 3394/**
a897a2ad 3395 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3396 * @adapter: device handle
3397 *
3398 * - 82598/82599/X540: 128
3399 * - X550(non-SRIOV mode): 512
3400 * - X550(SRIOV mode): 64
3401 */
7f276efb 3402u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3403{
3404 if (adapter->hw.mac.type < ixgbe_mac_X550)
3405 return 128;
3406 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3407 return 64;
3408 else
3409 return 512;
3410}
3411
3412/**
a897a2ad 3413 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3414 * @adapter: device handle
3415 *
3416 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3417 */
1c7cf078 3418void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3419{
dfaf891d 3420 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3421 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3422 u32 reta = 0;
dfaf891d
VZ		 3423 u32 indices_multi;
3424 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3425
0f9b232b 3426 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3427 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3428 * indices.
3429 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3430 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3431 */
3432 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3433 indices_multi = 0x11;
3434 else
3435 indices_multi = 0x1;
3436
dfaf891d
VZ		 3437 /* Write redirection table to HW */
3438 for (i = 0; i < reta_entries; i++) {
3439 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3440 if ((i & 3) == 3) {
3441 if (i < 128)
3442 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3443 else
3444 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3445 reta);
dfaf891d 3446 reta = 0;
0f9b232b
DS		 3447 }
3448 }
3449}
3450
dfaf891d 3451/**
a897a2ad 3452 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3453 * @adapter: device handle
3454 *
3455 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3456 */
3457static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3458{
dfaf891d 3459 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3460 struct ixgbe_hw *hw = &adapter->hw;
3461 u32 vfreta = 0;
dfaf891d
VZ		 3462 unsigned int pf_pool = adapter->num_vfs;
3463
3464 /* Write redirection table to HW */
3465 for (i = 0; i < reta_entries; i++) {
3466 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3467 if ((i & 3) == 3) {
3468 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3469 vfreta);
3470 vfreta = 0;
3471 }
3472 }
3473}
3474
3475static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3476{
3477 struct ixgbe_hw *hw = &adapter->hw;
3478 u32 i, j;
3479 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3480 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3481
e24fcf28 3482 /* Program table for at least 4 queues w/ SR-IOV so that VFs can
dfaf891d
VZ		 3483 * make full use of any rings they may have. We will use the
3484 * PSRTYPE register to control how many rings we use within the PF.
3485 */
e24fcf28
AD		 3486 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3487 rss_i = 4;
dfaf891d
VZ		 3488
3489 /* Fill out hash function seeds */
3490 for (i = 0; i < 10; i++)
3491 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3492
3493 /* Fill out redirection table */
3494 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3495
3496 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3497 if (j == rss_i)
3498 j = 0;
3499
3500 adapter->rss_indir_tbl[i] = j;
3501 }
3502
3503 ixgbe_store_reta(adapter);
3504}
3505
3506static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3507{
3508 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3509 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3510 unsigned int pf_pool = adapter->num_vfs;
3511 int i, j;
3512
3513 /* Fill out hash function seeds */
3514 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3515 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3516 adapter->rss_key[i]);
0f9b232b
DS		 3517
3518 /* Fill out the redirection table */
3519 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3520 if (j == rss_i)
05abb126 3521 j = 0;
dfaf891d
VZ		 3522
3523 adapter->rss_indir_tbl[i] = j;
05abb126 3524 }
dfaf891d
VZ		 3525
3526 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3527}
3528
3529static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3530{
3531 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3532 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3533 u32 rxcsum;
0cefafad 3534
05abb126
AD		 3535 /* Disable indicating checksum in descriptor, enables RSS hash */
3536 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3537 rxcsum |= IXGBE_RXCSUM_PCSD;
3538 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3539
671c0adb 3540 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3541 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3542 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3543 } else {
671c0adb
AD		 3544 u8 tcs = netdev_get_num_tc(adapter->netdev);
3545
3546 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3547 if (tcs > 4)
3548 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3549 else if (tcs > 1)
3550 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
e24fcf28
AD		 3551 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3552 IXGBE_82599_VMDQ_4Q_MASK)
671c0adb 3553 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3554 else
671c0adb
AD		 3555 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3556 } else {
3557 if (tcs > 4)
8b1c0b24 3558 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3559 else if (tcs > 1)
3560 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3561 else
3562 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3563 }
0cefafad
JB		 3564 }
3565
05abb126 3566 /* Perform hash on these packet types */
d1b849b9
DS		 3567 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3568 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3569 IXGBE_MRQC_RSS_FIELD_IPV6 |
3570 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3571
ef6afc0c 3572 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3573 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3574 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3575 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3576
dfaf891d 3577 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3578 if ((hw->mac.type >= ixgbe_mac_X550) &&
3579 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3580 unsigned int pf_pool = adapter->num_vfs;
3581
3582 /* Enable VF RSS mode */
3583 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3584 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3585
3586 /* Setup RSS through the VF registers */
dfaf891d 3587 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3588 vfmrqc = IXGBE_MRQC_RSSEN;
3589 vfmrqc |= rss_field;
3590 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3591 } else {
dfaf891d 3592 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3593 mrqc |= rss_field;
3594 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3595 }
0cefafad
JB		 3596}
3597
bb5a9ad2
NS		 3598/**
3599 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3600 * @adapter: address of board private structure
3601 * @index: index of ring to set
bb5a9ad2 3602 **/
082757af 3603static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3604 struct ixgbe_ring *ring)
bb5a9ad2 3605{
bb5a9ad2 3606 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3607 u32 rscctrl;
bf29ee6c 3608 u8 reg_idx = ring->reg_idx;
7367096a 3609
7d637bcc 3610 if (!ring_is_rsc_enabled(ring))
7367096a 3611 return;
bb5a9ad2 3612
7367096a 3613 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3614 rscctrl |= IXGBE_RSCCTL_RSCEN;
3615 /*
3616 * we must limit the number of descriptors so that the
3617 * total size of max desc * buf_len is not greater
642c680e 3618 * than 65536
bb5a9ad2 3619 */
f800326d 3620 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3621 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3622}
3623
9e10e045
AD		 3624#define IXGBE_MAX_RX_DESC_POLL 10
3625static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3626 struct ixgbe_ring *ring)
3627{
3628 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3629 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3630 u32 rxdctl;
bf29ee6c 3631 u8 reg_idx = ring->reg_idx;
9e10e045 3632
b0483c8f
MR		 3633 if (ixgbe_removed(hw->hw_addr))
3634 return;
9e10e045
AD		 3635 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3636 if (hw->mac.type == ixgbe_mac_82598EB &&
3637 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3638 return;
3639
3640 do {
032b4325 3641 usleep_range(1000, 2000);
9e10e045
AD		 3642 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3643 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3644
3645 if (!wait_loop) {
3646 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3647 "the polling period\n", reg_idx);
3648 }
3649}
3650
2d39d576
YZ		 3651void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3652 struct ixgbe_ring *ring)
3653{
3654 struct ixgbe_hw *hw = &adapter->hw;
3655 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3656 u32 rxdctl;
3657 u8 reg_idx = ring->reg_idx;
3658
b0483c8f
MR		 3659 if (ixgbe_removed(hw->hw_addr))
3660 return;
2d39d576
YZ		 3661 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3662 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3663
3664 /* write value back with RXDCTL.ENABLE bit cleared */
3665 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3666
3667 if (hw->mac.type == ixgbe_mac_82598EB &&
3668 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3669 return;
3670
3671 /* the hardware may take up to 100us to really disable the rx queue */
3672 do {
3673 udelay(10);
3674 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3675 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3676
3677 if (!wait_loop) {
3678 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3679 "the polling period\n", reg_idx);
3680 }
3681}
3682
84418e3b
AD		 3683void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3684 struct ixgbe_ring *ring)
acd37177
AD		 3685{
3686 struct ixgbe_hw *hw = &adapter->hw;
3687 u64 rdba = ring->dma;
9e10e045 3688 u32 rxdctl;
bf29ee6c 3689 u8 reg_idx = ring->reg_idx;
acd37177 3690
9e10e045
AD		 3691 /* disable queue to avoid issues while updating state */
3692 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3693 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3694
acd37177
AD		 3695 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3696 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3697 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3698 ring->count * sizeof(union ixgbe_adv_rx_desc));
8b75451b
NP		 3699 /* Force flushing of IXGBE_RDLEN to prevent MDD */
3700 IXGBE_WRITE_FLUSH(hw);
3701
acd37177
AD		 3702 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3703 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3704 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3705
3706 ixgbe_configure_srrctl(adapter, ring);
3707 ixgbe_configure_rscctl(adapter, ring);
3708
3709 if (hw->mac.type == ixgbe_mac_82598EB) {
3710 /*
3711 * enable cache line friendly hardware writes:
3712 * PTHRESH=32 descriptors (half the internal cache),
3713 * this also removes ugly rx_no_buffer_count increment
3714 * HTHRESH=4 descriptors (to minimize latency on fetch)
3715 * WTHRESH=8 burst writeback up to two cache lines
3716 */
3717 rxdctl &= ~0x3FFFFF;
3718 rxdctl |= 0x080420;
3719 }
3720
3721 /* enable receive descriptor ring */
3722 rxdctl |= IXGBE_RXDCTL_ENABLE;
3723 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3724
3725 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3726 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3727}
3728
48654521
AD		 3729static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3730{
3731 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3732 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3733 u16 pool;
48654521
AD		 3734
3735 /* PSRTYPE must be initialized in non 82598 adapters */
3736 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3737 IXGBE_PSRTYPE_UDPHDR |
3738 IXGBE_PSRTYPE_IPV4HDR |
48654521 3739 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3740 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3741
3742 if (hw->mac.type == ixgbe_mac_82598EB)
3743 return;
3744
fbe7ca7f 3745 if (rss_i > 3)
b4f47a48 3746 psrtype |= 2u << 29;
fbe7ca7f 3747 else if (rss_i > 1)
b4f47a48 3748 psrtype |= 1u << 29;
48654521 3749
2a47fa45
JF		 3750 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3751 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3752}
3753
f5b4a52e
AD		 3754static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3755{
3756 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3757 u32 reg_offset, vf_shift;
435b19f6 3758 u32 gcr_ext, vmdctl;
de4c7f65 3759 int i;
f5b4a52e
AD		 3760
3761 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3762 return;
3763
3764 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3765 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3766 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3767 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3768 vmdctl |= IXGBE_VT_CTL_REPLEN;
3769 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3770
1d9c0bfd
AD		 3771 vf_shift = VMDQ_P(0) % 32;
3772 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3773
3774 /* Enable only the PF's pool for Tx/Rx */
11f2b494 3775 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
435b19f6 3776 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
11f2b494 3777 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
435b19f6 3778 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3779 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3780 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3781
3782 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3783 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e 3784
16369564
AD		 3785 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3786 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
3787
f5b4a52e
AD		 3788 /*
3789 * Set up VF register offsets for selected VT Mode,
3790 * i.e. 32 or 64 VFs for SR-IOV
3791 */
73079ea0
AD		 3792 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3793 case IXGBE_82599_VMDQ_8Q_MASK:
3794 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3795 break;
3796 case IXGBE_82599_VMDQ_4Q_MASK:
3797 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3798 break;
3799 default:
3800 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3801 break;
3802 }
3803
f5b4a52e
AD		 3804 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3805
de4c7f65 3806 for (i = 0; i < adapter->num_vfs; i++) {
77f192af
ET		 3807 /* configure spoof checking */
3808 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
3809 adapter->vfinfo[i].spoofchk_enabled);
e65ce0d3
VZ		 3810
3811 /* Enable/Disable RSS query feature */
3812 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3813 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3814 }
f5b4a52e
AD		 3815}
3816
477de6ed 3817static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3818{
9a799d71
AK		 3819 struct ixgbe_hw *hw = &adapter->hw;
3820 struct net_device *netdev = adapter->netdev;
3821 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3822 struct ixgbe_ring *rx_ring;
3823 int i;
3824 u32 mhadd, hlreg0;
48654521 3825
63f39bd1 3826#ifdef IXGBE_FCOE
477de6ed
AD		 3827 /* adjust max frame to be able to do baby jumbo for FCoE */
3828 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3829 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3830 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3831
477de6ed 3832#endif /* IXGBE_FCOE */
872844dd
AD		 3833
3834 /* adjust max frame to be at least the size of a standard frame */
3835 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3836 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3837
477de6ed
AD		 3838 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3839 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3840 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3841 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3842
3843 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3844 }
3845
3846 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3847 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3848 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3849 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3850
0cefafad
JB		 3851 /*
3852 * Setup the HW Rx Head and Tail Descriptor Pointers and
3853 * the Base and Length of the Rx Descriptor Ring
3854 */
9a799d71 3855 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3856 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3857 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3858 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3859 else
7d637bcc 3860 clear_ring_rsc_enabled(rx_ring);
477de6ed 3861 }
477de6ed
AD		 3862}
3863
7367096a
AD		 3864static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3865{
3866 struct ixgbe_hw *hw = &adapter->hw;
3867 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3868
3869 switch (hw->mac.type) {
3870 case ixgbe_mac_82598EB:
3871 /*
3872 * For VMDq support of different descriptor types or
3873 * buffer sizes through the use of multiple SRRCTL
3874 * registers, RDRXCTL.MVMEN must be set to 1
3875 *
3876 * also, the manual doesn't mention it clearly but DCA hints
3877 * will only use queue 0's tags unless this bit is set. Side
3878 * effects of setting this bit are only that SRRCTL must be
3879 * fully programmed [0..15]
3880 */
3881 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3882 break;
052a1a72
MR		 3883 case ixgbe_mac_X550:
3884 case ixgbe_mac_X550EM_x:
49425dfc 3885 case ixgbe_mac_x550em_a:
f961ddae
MR		 3886 if (adapter->num_vfs)
3887 rdrxctl |= IXGBE_RDRXCTL_PSP;
3888 /* fall through for older HW */
7367096a 3889 case ixgbe_mac_82599EB:
b93a2226 3890 case ixgbe_mac_X540:
7367096a
AD		 3891 /* Disable RSC for ACK packets */
3892 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3893 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3894 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3895 /* hardware requires some bits to be set by default */
3896 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3897 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3898 break;
3899 default:
3900 /* We should do nothing since we don't know this hardware */
3901 return;
3902 }
3903
3904 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3905}
3906
477de6ed
AD		 3907/**
3908 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3909 * @adapter: board private structure
3910 *
3911 * Configure the Rx unit of the MAC after a reset.
3912 **/
3913static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3914{
3915 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3916 int i;
6dcc28b9 3917 u32 rxctrl, rfctl;
477de6ed
AD		 3918
3919 /* disable receives while setting up the descriptors */
1f9ac57c 3920 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3921
3922 ixgbe_setup_psrtype(adapter);
7367096a 3923 ixgbe_setup_rdrxctl(adapter);
477de6ed 3924
6dcc28b9
JK		 3925 /* RSC Setup */
3926 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3927 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3928 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3929 rfctl |= IXGBE_RFCTL_RSC_DIS;
a21d0822
ET		 3930
3931 /* disable NFS filtering */
3932 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
6dcc28b9
JK		 3933 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3934
9e10e045 3935 /* Program registers for the distribution of queues */
f5b4a52e 3936 ixgbe_setup_mrqc(adapter);
f5b4a52e 3937
477de6ed
AD		 3938 /* set_rx_buffer_len must be called before ring initialization */
3939 ixgbe_set_rx_buffer_len(adapter);
3940
3941 /*
3942 * Setup the HW Rx Head and Tail Descriptor Pointers and
3943 * the Base and Length of the Rx Descriptor Ring
3944 */
9e10e045
AD		 3945 for (i = 0; i < adapter->num_rx_queues; i++)
3946 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3947
1f9ac57c 3948 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3949 /* disable drop enable for 82598 parts */
3950 if (hw->mac.type == ixgbe_mac_82598EB)
3951 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3952
3953 /* enable all receives */
3954 rxctrl |= IXGBE_RXCTRL_RXEN;
3955 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3956}
3957
80d5c368
PM		 3958static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3959 __be16 proto, u16 vid)
068c89b0
DS		 3960{
3961 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3962 struct ixgbe_hw *hw = &adapter->hw;
3963
3964 /* add VID to filter table */
18be4fce
AD		 3965 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3966 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
3967
f62bbb5e 3968 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3969
3970 return 0;
068c89b0
DS		 3971}
3972
e1d0a2af
AD		 3973static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
3974{
3975 u32 vlvf;
3976 int idx;
3977
3978 /* short cut the special case */
3979 if (vlan == 0)
3980 return 0;
3981
3982 /* Search for the vlan id in the VLVF entries */
3983 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
3984 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
3985 if ((vlvf & VLAN_VID_MASK) == vlan)
3986 break;
3987 }
3988
3989 return idx;
3990}
3991
3992void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
3993{
3994 struct ixgbe_hw *hw = &adapter->hw;
3995 u32 bits, word;
3996 int idx;
3997
3998 idx = ixgbe_find_vlvf_entry(hw, vid);
3999 if (!idx)
4000 return;
4001
4002 /* See if any other pools are set for this VLAN filter
4003 * entry other than the PF.
4004 */
4005 word = idx * 2 + (VMDQ_P(0) / 32);
b4f47a48 4006 bits = ~BIT(VMDQ_P(0) % 32);
e1d0a2af
AD		 4007 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4008
4009 /* Disable the filter so this falls into the default pool. */
4010 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4011 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4012 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4013 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4014 }
4015}
4016
80d5c368
PM		 4017static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4018 __be16 proto, u16 vid)
068c89b0
DS		 4019{
4020 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4021 struct ixgbe_hw *hw = &adapter->hw;
4022
068c89b0 4023 /* remove VID from filter table */
18be4fce 4024 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
e1d0a2af
AD		 4025 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4026
f62bbb5e 4027 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 4028
4029 return 0;
068c89b0
DS		 4030}
4031
f62bbb5e
JG		 4032/**
4033 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4034 * @adapter: driver data
4035 */
4036static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4037{
4038 struct ixgbe_hw *hw = &adapter->hw;
4039 u32 vlnctrl;
5f6c0181
JB		 4040 int i, j;
4041
4042 switch (hw->mac.type) {
4043 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4044 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4045 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4046 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4047 break;
4048 case ixgbe_mac_82599EB:
b93a2226 4049 case ixgbe_mac_X540:
9a75a1ac
DS		 4050 case ixgbe_mac_X550:
4051 case ixgbe_mac_X550EM_x:
49425dfc 4052 case ixgbe_mac_x550em_a:
5f6c0181 4053 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4054 struct ixgbe_ring *ring = adapter->rx_ring[i];
4055
4056 if (ring->l2_accel_priv)
4057 continue;
4058 j = ring->reg_idx;
5f6c0181
JB		 4059 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4060 vlnctrl &= ~IXGBE_RXDCTL_VME;
4061 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4062 }
4063 break;
4064 default:
4065 break;
4066 }
4067}
4068
4069/**
f62bbb5e 4070 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 4071 * @adapter: driver data
4072 */
f62bbb5e 4073static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 4074{
4075 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 4076 u32 vlnctrl;
5f6c0181
JB		 4077 int i, j;
4078
4079 switch (hw->mac.type) {
4080 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4081 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4082 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4083 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4084 break;
4085 case ixgbe_mac_82599EB:
b93a2226 4086 case ixgbe_mac_X540:
9a75a1ac
DS		 4087 case ixgbe_mac_X550:
4088 case ixgbe_mac_X550EM_x:
49425dfc 4089 case ixgbe_mac_x550em_a:
5f6c0181 4090 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4091 struct ixgbe_ring *ring = adapter->rx_ring[i];
4092
4093 if (ring->l2_accel_priv)
4094 continue;
4095 j = ring->reg_idx;
5f6c0181
JB		 4096 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4097 vlnctrl |= IXGBE_RXDCTL_VME;
4098 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4099 }
4100 break;
4101 default:
4102 break;
4103 }
4104}
4105
16369564
AD		 4106static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4107{
4108 struct ixgbe_hw *hw = &adapter->hw;
4109 u32 vlnctrl, i;
4110
f60439bc
AD		 4111 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4112
691e4121
ET		 4113 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4114 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4115 vlnctrl |= IXGBE_VLNCTRL_VFE;
4116 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4117 } else {
f60439bc 4118 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
16369564
AD		 4119 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4120 return;
4121 }
4122
691e4121
ET		 4123 /* Nothing to do for 82598 */
4124 if (hw->mac.type == ixgbe_mac_82598EB)
4125 return;
4126
16369564
AD		 4127 /* We are already in VLAN promisc, nothing to do */
4128 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4129 return;
4130
4131 /* Set flag so we don't redo unnecessary work */
4132 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4133
4134 /* Add PF to all active pools */
4135 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4136 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4137 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4138
b4f47a48 4139 vlvfb |= BIT(VMDQ_P(0) % 32);
16369564
AD		 4140 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4141 }
4142
4143 /* Set all bits in the VLAN filter table array */
4144 for (i = hw->mac.vft_size; i--;)
4145 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4146}
4147
4148#define VFTA_BLOCK_SIZE 8
4149static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4150{
4151 struct ixgbe_hw *hw = &adapter->hw;
4152 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4153 u32 vid_start = vfta_offset * 32;
4154 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4155 u32 i, vid, word, bits;
4156
4157 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4158 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4159
4160 /* pull VLAN ID from VLVF */
4161 vid = vlvf & VLAN_VID_MASK;
4162
4163 /* only concern outselves with a certain range */
4164 if (vid < vid_start || vid >= vid_end)
4165 continue;
4166
4167 if (vlvf) {
4168 /* record VLAN ID in VFTA */
b4f47a48 4169 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16369564
AD		 4170
4171 /* if PF is part of this then continue */
4172 if (test_bit(vid, adapter->active_vlans))
4173 continue;
4174 }
4175
4176 /* remove PF from the pool */
4177 word = i * 2 + VMDQ_P(0) / 32;
b4f47a48 4178 bits = ~BIT(VMDQ_P(0) % 32);
16369564
AD		 4179 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4180 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4181 }
4182
4183 /* extract values from active_vlans and write back to VFTA */
4184 for (i = VFTA_BLOCK_SIZE; i--;) {
4185 vid = (vfta_offset + i) * 32;
4186 word = vid / BITS_PER_LONG;
4187 bits = vid % BITS_PER_LONG;
4188
4189 vfta[i] |= adapter->active_vlans[word] >> bits;
4190
4191 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4192 }
4193}
4194
4195static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4196{
4197 struct ixgbe_hw *hw = &adapter->hw;
4198 u32 vlnctrl, i;
4199
f60439bc
AD		 4200 /* Set VLAN filtering to enabled */
4201 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4202 vlnctrl |= IXGBE_VLNCTRL_VFE;
4203 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4204
691e4121
ET		 4205 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4206 hw->mac.type == ixgbe_mac_82598EB)
16369564 4207 return;
16369564
AD		 4208
4209 /* We are not in VLAN promisc, nothing to do */
4210 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4211 return;
4212
4213 /* Set flag so we don't redo unnecessary work */
4214 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4215
4216 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4217 ixgbe_scrub_vfta(adapter, i);
4218}
4219
9a799d71
AK		 4220static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4221{
06bb1c39 4222 u16 vid = 1;
9a799d71 4223
80d5c368 4224 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e 4225
06bb1c39 4226 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 4227 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 4228}
4229
b335e75b
JK		 4230/**
4231 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4232 * @netdev: network interface device structure
4233 *
4234 * Writes multicast address list to the MTA hash table.
4235 * Returns: -ENOMEM on failure
4236 * 0 on no addresses written
4237 * X on writing X addresses to MTA
4238 **/
4239static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4240{
4241 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4242 struct ixgbe_hw *hw = &adapter->hw;
4243
4244 if (!netif_running(netdev))
4245 return 0;
4246
4247 if (hw->mac.ops.update_mc_addr_list)
4248 hw->mac.ops.update_mc_addr_list(hw, netdev);
4249 else
4250 return -ENOMEM;
4251
4252#ifdef CONFIG_PCI_IOV
5d7daa35 4253 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4254#endif
4255
4256 return netdev_mc_count(netdev);
4257}
4258
5d7daa35
JK		 4259#ifdef CONFIG_PCI_IOV
4260void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4261{
c9f53e63 4262 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4263 struct ixgbe_hw *hw = &adapter->hw;
4264 int i;
c9f53e63
AD		 4265
4266 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4267 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4268
4269 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4270 hw->mac.ops.set_rar(hw, i,
4271 mac_table->addr,
4272 mac_table->pool,
5d7daa35
JK		 4273 IXGBE_RAH_AV);
4274 else
4275 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4276 }
4277}
5d7daa35 4278
c9f53e63 4279#endif
5d7daa35
JK		 4280static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4281{
c9f53e63 4282 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4283 struct ixgbe_hw *hw = &adapter->hw;
4284 int i;
5d7daa35 4285
c9f53e63
AD		 4286 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4287 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4288 continue;
4289
4290 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4291
4292 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4293 hw->mac.ops.set_rar(hw, i,
4294 mac_table->addr,
4295 mac_table->pool,
4296 IXGBE_RAH_AV);
4297 else
4298 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4299 }
4300}
4301
4302static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4303{
c9f53e63 4304 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4305 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4306 int i;
5d7daa35 4307
c9f53e63
AD		 4308 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4309 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4310 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
5d7daa35 4311 }
c9f53e63 4312
5d7daa35
JK		 4313 ixgbe_sync_mac_table(adapter);
4314}
4315
c9f53e63 4316static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
5d7daa35 4317{
c9f53e63 4318 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4319 struct ixgbe_hw *hw = &adapter->hw;
4320 int i, count = 0;
4321
c9f53e63
AD		 4322 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4323 /* do not count default RAR as available */
4324 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4325 continue;
4326
4327 /* only count unused and addresses that belong to us */
4328 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4329 if (mac_table->pool != pool)
4330 continue;
4331 }
4332
4333 count++;
5d7daa35 4334 }
c9f53e63 4335
5d7daa35
JK		 4336 return count;
4337}
4338
4339/* this function destroys the first RAR entry */
c9f53e63 4340static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
5d7daa35 4341{
c9f53e63 4342 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4343 struct ixgbe_hw *hw = &adapter->hw;
4344
c9f53e63
AD		 4345 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4346 mac_table->pool = VMDQ_P(0);
4347
4348 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4349
4350 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
5d7daa35
JK		 4351 IXGBE_RAH_AV);
4352}
4353
c9f53e63
AD		 4354int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4355 const u8 *addr, u16 pool)
5d7daa35 4356{
c9f53e63 4357 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4358 struct ixgbe_hw *hw = &adapter->hw;
4359 int i;
4360
4361 if (is_zero_ether_addr(addr))
4362 return -EINVAL;
4363
c9f53e63
AD		 4364 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4365 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
5d7daa35 4366 continue;
c9f53e63
AD		 4367
4368 ether_addr_copy(mac_table->addr, addr);
4369 mac_table->pool = pool;
4370
4371 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4372 IXGBE_MAC_STATE_IN_USE;
4373
5d7daa35 4374 ixgbe_sync_mac_table(adapter);
c9f53e63 4375
5d7daa35
JK		 4376 return i;
4377 }
c9f53e63 4378
5d7daa35
JK		 4379 return -ENOMEM;
4380}
4381
c9f53e63
AD		 4382int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4383 const u8 *addr, u16 pool)
5d7daa35 4384{
c9f53e63 4385 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4386 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4387 int i;
5d7daa35
JK		 4388
4389 if (is_zero_ether_addr(addr))
4390 return -EINVAL;
4391
c9f53e63
AD		 4392 /* search table for addr, if found clear IN_USE flag and sync */
4393 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4394 /* we can only delete an entry if it is in use */
4395 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4396 continue;
4397 /* we only care about entries that belong to the given pool */
4398 if (mac_table->pool != pool)
4399 continue;
4400 /* we only care about a specific MAC address */
4401 if (!ether_addr_equal(addr, mac_table->addr))
4402 continue;
4403
4404 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4405 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4406
4407 ixgbe_sync_mac_table(adapter);
4408
4409 return 0;
5d7daa35 4410 }
c9f53e63 4411
5d7daa35
JK		 4412 return -ENOMEM;
4413}
2850062a
AD		 4414/**
4415 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4416 * @netdev: network interface device structure
4417 *
4418 * Writes unicast address list to the RAR table.
4419 * Returns: -ENOMEM on failure/insufficient address space
4420 * 0 on no addresses written
4421 * X on writing X addresses to the RAR table
4422 **/
5d7daa35 4423static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4424{
4425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4426 int count = 0;
4427
4428 /* return ENOMEM indicating insufficient memory for addresses */
c9f53e63 4429 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
2850062a
AD		 4430 return -ENOMEM;
4431
95447461 4432 if (!netdev_uc_empty(netdev)) {
2850062a 4433 struct netdev_hw_addr *ha;
2850062a 4434 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4435 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4436 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4437 count++;
4438 }
4439 }
2850062a
AD		 4440 return count;
4441}
4442
0f079d22
AD		 4443static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4444{
4445 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4446 int ret;
4447
4448 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4449
4450 return min_t(int, ret, 0);
4451}
4452
4453static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4454{
4455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4456
4457 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4458
4459 return 0;
4460}
4461
9a799d71 4462/**
2c5645cf 4463 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4464 * @netdev: network interface device structure
4465 *
2c5645cf
CL		 4466 * The set_rx_method entry point is called whenever the unicast/multicast
4467 * address list or the network interface flags are updated. This routine is
4468 * responsible for configuring the hardware for proper unicast, multicast and
4469 * promiscuous mode.
9a799d71 4470 **/
7f870475 4471void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4472{
4473 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4474 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4475 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
0c5a6166 4476 netdev_features_t features = netdev->features;
2850062a 4477 int count;
9a799d71
AK		 4478
4479 /* Check for Promiscuous and All Multicast modes */
9a799d71
AK		 4480 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4481
f5dc442b 4482 /* set all bits that we expect to always be set */
3f2d1c0f 4483 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4484 fctrl |= IXGBE_FCTRL_BAM;
4485 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4486 fctrl |= IXGBE_FCTRL_PMCF;
4487
2850062a
AD		 4488 /* clear the bits we are changing the status of */
4489 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
9a799d71 4490 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4491 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4492 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4493 vmolr |= IXGBE_VMOLR_MPE;
0c5a6166 4494 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
9a799d71 4495 } else {
746b9f02
PM		 4496 if (netdev->flags & IFF_ALLMULTI) {
4497 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4498 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4499 }
e433ea1f 4500 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4501 }
4502
4503 /*
4504 * Write addresses to available RAR registers, if there is not
4505 * sufficient space to store all the addresses then enable
4506 * unicast promiscuous mode
4507 */
0f079d22 4508 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
9dcb373c
JF		 4509 fctrl |= IXGBE_FCTRL_UPE;
4510 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4511 }
4512
cf78959c
ET		 4513 /* Write addresses to the MTA, if the attempt fails
4514 * then we should just turn on promiscuous mode so
4515 * that we can at least receive multicast traffic
4516 */
b335e75b
JK		 4517 count = ixgbe_write_mc_addr_list(netdev);
4518 if (count < 0) {
4519 fctrl |= IXGBE_FCTRL_MPE;
4520 vmolr |= IXGBE_VMOLR_MPE;
4521 } else if (count) {
4522 vmolr |= IXGBE_VMOLR_ROMPE;
4523 }
1d9c0bfd
AD		 4524
4525 if (hw->mac.type != ixgbe_mac_82598EB) {
4526 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4527 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4528 IXGBE_VMOLR_ROPE);
1d9c0bfd 4529 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4530 }
4531
3f2d1c0f 4532 /* This is useful for sniffing bad packets. */
0c5a6166 4533 if (features & NETIF_F_RXALL) {
3f2d1c0f
BG		 4534 /* UPE and MPE will be handled by normal PROMISC logic
4535 * in e1000e_set_rx_mode */
4536 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4537 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4538 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4539
4540 fctrl &= ~(IXGBE_FCTRL_DPF);
4541 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4542 }
4543
2850062a 4544 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4545
0c5a6166 4546 if (features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4547 ixgbe_vlan_strip_enable(adapter);
4548 else
4549 ixgbe_vlan_strip_disable(adapter);
0c5a6166
AD		 4550
4551 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4552 ixgbe_vlan_promisc_disable(adapter);
4553 else
4554 ixgbe_vlan_promisc_enable(adapter);
9a799d71
AK		 4555}
4556
021230d4
AV		 4557static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4558{
4559 int q_idx;
021230d4 4560
5a85e737
ET		 4561 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4562 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4563 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4564 }
021230d4
AV		 4565}
4566
4567static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4568{
4569 int q_idx;
021230d4 4570
5a85e737 4571 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4572 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4573 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4574 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4575 usleep_range(1000, 20000);
5a85e737
ET		 4576 }
4577 }
021230d4
AV		 4578}
4579
a21d0822 4580static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask)
67359c3c 4581{
a21d0822
ET		 4582 struct ixgbe_hw *hw = &adapter->hw;
4583 u32 vxlanctrl;
4584
4585 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE |
4586 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)))
4587 return;
4588
4589 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) && ~mask;
4590 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl);
4591
4592 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK)
67359c3c 4593 adapter->vxlan_port = 0;
a21d0822
ET		 4594
4595 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK)
4596 adapter->geneve_port = 0;
67359c3c
MR		 4597}
4598
7a6b6f51 4599#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4600/**
2f90b865
AD		 4601 * ixgbe_configure_dcb - Configure DCB hardware
4602 * @adapter: ixgbe adapter struct
4603 *
4604 * This is called by the driver on open to configure the DCB hardware.
4605 * This is also called by the gennetlink interface when reconfiguring
4606 * the DCB state.
4607 */
4608static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4609{
4610 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4611 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4612
67ebd791
AD		 4613 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4614 if (hw->mac.type == ixgbe_mac_82598EB)
4615 netif_set_gso_max_size(adapter->netdev, 65536);
4616 return;
4617 }
4618
4619 if (hw->mac.type == ixgbe_mac_82598EB)
4620 netif_set_gso_max_size(adapter->netdev, 32768);
4621
971060b1 4622#ifdef IXGBE_FCOE
b120818e
JF		 4623 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4624 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4625#endif
b120818e
JF		 4626
4627 /* reconfigure the hardware */
4628 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4629 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4630 DCB_TX_CONFIG);
4631 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4632 DCB_RX_CONFIG);
4633 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4634 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4635 ixgbe_dcb_hw_ets(&adapter->hw,
4636 adapter->ixgbe_ieee_ets,
4637 max_frame);
4638 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4639 adapter->ixgbe_ieee_pfc->pfc_en,
4640 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4641 }
8187cd48
JF		 4642
4643 /* Enable RSS Hash per TC */
4644 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4645 u32 msb = 0;
4646 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4647
d411a936
AD		 4648 while (rss_i) {
4649 msb++;
4650 rss_i >>= 1;
4651 }
8187cd48 4652
4ae63730
AD		 4653 /* write msb to all 8 TCs in one write */
4654 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4655 }
2f90b865 4656}
9da712d2
JF		 4657#endif
4658
4659/* Additional bittime to account for IXGBE framing */
4660#define IXGBE_ETH_FRAMING 20
4661
49ce9c2c 4662/**
9da712d2
JF		 4663 * ixgbe_hpbthresh - calculate high water mark for flow control
4664 *
4665 * @adapter: board private structure to calculate for
49ce9c2c 4666 * @pb: packet buffer to calculate
9da712d2
JF		 4667 */
4668static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4669{
4670 struct ixgbe_hw *hw = &adapter->hw;
4671 struct net_device *dev = adapter->netdev;
4672 int link, tc, kb, marker;
4673 u32 dv_id, rx_pba;
4674
4675 /* Calculate max LAN frame size */
4676 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4677
4678#ifdef IXGBE_FCOE
4679 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4680 if ((dev->features & NETIF_F_FCOE_MTU) &&
4681 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4682 (pb == ixgbe_fcoe_get_tc(adapter)))
4683 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4684#endif
e5776620 4685
9da712d2
JF		 4686 /* Calculate delay value for device */
4687 switch (hw->mac.type) {
4688 case ixgbe_mac_X540:
9a75a1ac
DS		 4689 case ixgbe_mac_X550:
4690 case ixgbe_mac_X550EM_x:
49425dfc 4691 case ixgbe_mac_x550em_a:
9da712d2
JF		 4692 dv_id = IXGBE_DV_X540(link, tc);
4693 break;
4694 default:
4695 dv_id = IXGBE_DV(link, tc);
4696 break;
4697 }
4698
4699 /* Loopback switch introduces additional latency */
4700 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4701 dv_id += IXGBE_B2BT(tc);
4702
4703 /* Delay value is calculated in bit times convert to KB */
4704 kb = IXGBE_BT2KB(dv_id);
4705 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4706
4707 marker = rx_pba - kb;
4708
4709 /* It is possible that the packet buffer is not large enough
4710 * to provide required headroom. In this case throw an error
4711 * to user and a do the best we can.
4712 */
4713 if (marker < 0) {
4714 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4715 "headroom to support flow control."
4716 "Decrease MTU or number of traffic classes\n", pb);
4717 marker = tc + 1;
4718 }
4719
4720 return marker;
4721}
4722
49ce9c2c 4723/**
9da712d2
JF		 4724 * ixgbe_lpbthresh - calculate low water mark for for flow control
4725 *
4726 * @adapter: board private structure to calculate for
49ce9c2c 4727 * @pb: packet buffer to calculate
9da712d2 4728 */
e5776620 4729static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4730{
4731 struct ixgbe_hw *hw = &adapter->hw;
4732 struct net_device *dev = adapter->netdev;
4733 int tc;
4734 u32 dv_id;
4735
4736 /* Calculate max LAN frame size */
4737 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4738
e5776620
JK		 4739#ifdef IXGBE_FCOE
4740 /* FCoE traffic class uses FCOE jumbo frames */
4741 if ((dev->features & NETIF_F_FCOE_MTU) &&
4742 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4743 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4744 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4745#endif
4746
9da712d2
JF		 4747 /* Calculate delay value for device */
4748 switch (hw->mac.type) {
4749 case ixgbe_mac_X540:
9a75a1ac
DS		 4750 case ixgbe_mac_X550:
4751 case ixgbe_mac_X550EM_x:
49425dfc 4752 case ixgbe_mac_x550em_a:
9da712d2
JF		 4753 dv_id = IXGBE_LOW_DV_X540(tc);
4754 break;
4755 default:
4756 dv_id = IXGBE_LOW_DV(tc);
4757 break;
4758 }
4759
4760 /* Delay value is calculated in bit times convert to KB */
4761 return IXGBE_BT2KB(dv_id);
4762}
4763
4764/*
4765 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4766 */
4767static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4768{
4769 struct ixgbe_hw *hw = &adapter->hw;
4770 int num_tc = netdev_get_num_tc(adapter->netdev);
4771 int i;
4772
4773 if (!num_tc)
4774 num_tc = 1;
4775
9da712d2
JF		 4776 for (i = 0; i < num_tc; i++) {
4777 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4778 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4779
4780 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4781 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4782 hw->fc.low_water[i] = 0;
9da712d2 4783 }
e5776620
JK		 4784
4785 for (; i < MAX_TRAFFIC_CLASS; i++)
4786 hw->fc.high_water[i] = 0;
9da712d2
JF		 4787}
4788
80605c65
JF		 4789static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4790{
80605c65 4791 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4792 int hdrm;
4793 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4794
4795 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4796 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4797 hdrm = 32 << adapter->fdir_pballoc;
4798 else
4799 hdrm = 0;
80605c65 4800
f7e1027f 4801 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4802 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4803}
4804
e4911d57
AD		 4805static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4806{
4807 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4808 struct hlist_node *node2;
e4911d57
AD		 4809 struct ixgbe_fdir_filter *filter;
4810
4811 spin_lock(&adapter->fdir_perfect_lock);
4812
4813 if (!hlist_empty(&adapter->fdir_filter_list))
4814 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4815
b67bfe0d 4816 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4817 &adapter->fdir_filter_list, fdir_node) {
4818 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4819 &filter->filter,
4820 filter->sw_idx,
4821 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4822 IXGBE_FDIR_DROP_QUEUE :
4823 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4824 }
4825
4826 spin_unlock(&adapter->fdir_perfect_lock);
4827}
4828
2a47fa45
JF		 4829static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4830 struct ixgbe_adapter *adapter)
4831{
4832 struct ixgbe_hw *hw = &adapter->hw;
4833 u32 vmolr;
4834
4835 /* No unicast promiscuous support for VMDQ devices. */
4836 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4837 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4838
4839 /* clear the affected bit */
4840 vmolr &= ~IXGBE_VMOLR_MPE;
4841
4842 if (dev->flags & IFF_ALLMULTI) {
4843 vmolr |= IXGBE_VMOLR_MPE;
4844 } else {
4845 vmolr |= IXGBE_VMOLR_ROMPE;
4846 hw->mac.ops.update_mc_addr_list(hw, dev);
4847 }
5d7daa35 4848 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4849 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4850}
4851
2a47fa45
JF		 4852static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4853{
4854 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4855 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4856 struct ixgbe_hw *hw = &adapter->hw;
4857 u16 pool = vadapter->pool;
4858 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4859 IXGBE_PSRTYPE_UDPHDR |
4860 IXGBE_PSRTYPE_IPV4HDR |
4861 IXGBE_PSRTYPE_L2HDR |
4862 IXGBE_PSRTYPE_IPV6HDR;
4863
4864 if (hw->mac.type == ixgbe_mac_82598EB)
4865 return;
4866
4867 if (rss_i > 3)
b4f47a48 4868 psrtype |= 2u << 29;
2a47fa45 4869 else if (rss_i > 1)
b4f47a48 4870 psrtype |= 1u << 29;
2a47fa45
JF		 4871
4872 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4873}
4874
4875/**
4876 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4877 * @rx_ring: ring to free buffers from
4878 **/
4879static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4880{
4881 struct device *dev = rx_ring->dev;
4882 unsigned long size;
4883 u16 i;
4884
4885 /* ring already cleared, nothing to do */
4886 if (!rx_ring->rx_buffer_info)
4887 return;
4888
4889 /* Free all the Rx ring sk_buffs */
4890 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4891 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4892
2a47fa45
JF		 4893 if (rx_buffer->skb) {
4894 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4895 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4896 dma_unmap_page(dev,
4897 IXGBE_CB(skb)->dma,
4898 ixgbe_rx_bufsz(rx_ring),
4899 DMA_FROM_DEVICE);
2a47fa45 4900 dev_kfree_skb(skb);
4d2fcfbc 4901 rx_buffer->skb = NULL;
2a47fa45 4902 }
18cb652a
AD		 4903
4904 if (!rx_buffer->page)
4905 continue;
4906
4907 dma_unmap_page(dev, rx_buffer->dma,
4908 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4909 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4910
2a47fa45
JF		 4911 rx_buffer->page = NULL;
4912 }
4913
4914 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4915 memset(rx_ring->rx_buffer_info, 0, size);
4916
4917 /* Zero out the descriptor ring */
4918 memset(rx_ring->desc, 0, rx_ring->size);
4919
4920 rx_ring->next_to_alloc = 0;
4921 rx_ring->next_to_clean = 0;
4922 rx_ring->next_to_use = 0;
4923}
4924
4925static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4926 struct ixgbe_ring *rx_ring)
4927{
4928 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4929 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4930
4931 /* shutdown specific queue receive and wait for dma to settle */
4932 ixgbe_disable_rx_queue(adapter, rx_ring);
4933 usleep_range(10000, 20000);
b4f47a48 4934 ixgbe_irq_disable_queues(adapter, BIT_ULL(index));
2a47fa45
JF		 4935 ixgbe_clean_rx_ring(rx_ring);
4936 rx_ring->l2_accel_priv = NULL;
4937}
4938
ae72c8d0
JF		 4939static int ixgbe_fwd_ring_down(struct net_device *vdev,
4940 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4941{
4942 struct ixgbe_adapter *adapter = accel->real_adapter;
4943 unsigned int rxbase = accel->rx_base_queue;
4944 unsigned int txbase = accel->tx_base_queue;
4945 int i;
4946
4947 netif_tx_stop_all_queues(vdev);
4948
4949 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4950 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4951 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4952 }
4953
4954 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4955 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4956 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4957 }
4958
4959
4960 return 0;
4961}
4962
4963static int ixgbe_fwd_ring_up(struct net_device *vdev,
4964 struct ixgbe_fwd_adapter *accel)
4965{
4966 struct ixgbe_adapter *adapter = accel->real_adapter;
4967 unsigned int rxbase, txbase, queues;
4968 int i, baseq, err = 0;
4969
4970 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4971 return 0;
4972
4973 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4974 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4975 accel->pool, adapter->num_rx_pools,
4976 baseq, baseq + adapter->num_rx_queues_per_pool,
4977 adapter->fwd_bitmask);
4978
4979 accel->netdev = vdev;
4980 accel->rx_base_queue = rxbase = baseq;
4981 accel->tx_base_queue = txbase = baseq;
4982
4983 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4984 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4985
4986 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4987 adapter->rx_ring[rxbase + i]->netdev = vdev;
4988 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4989 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4990 }
4991
4992 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4993 adapter->tx_ring[txbase + i]->netdev = vdev;
4994 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4995 }
4996
4997 queues = min_t(unsigned int,
4998 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4999 err = netif_set_real_num_tx_queues(vdev, queues);
5000 if (err)
5001 goto fwd_queue_err;
5002
2a47fa45
JF		 5003 err = netif_set_real_num_rx_queues(vdev, queues);
5004 if (err)
5005 goto fwd_queue_err;
5006
5007 if (is_valid_ether_addr(vdev->dev_addr))
5008 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
5009
5010 ixgbe_fwd_psrtype(accel);
5011 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
5012 return err;
5013fwd_queue_err:
5014 ixgbe_fwd_ring_down(vdev, accel);
5015 return err;
5016}
5017
1cd127fc 5018static int ixgbe_upper_dev_walk(struct net_device *upper, void *data)
2a47fa45 5019{
1cd127fc
DA		 5020 if (netif_is_macvlan(upper)) {
5021 struct macvlan_dev *dfwd = netdev_priv(upper);
5022 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
2a47fa45 5023
1cd127fc
DA		 5024 if (dfwd->fwd_priv)
5025 ixgbe_fwd_ring_up(upper, vadapter);
2a47fa45 5026 }
1cd127fc
DA		 5027
5028 return 0;
5029}
5030
5031static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5032{
5033 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5034 ixgbe_upper_dev_walk, NULL);
2a47fa45
JF		 5035}
5036
9a799d71
AK		 5037static void ixgbe_configure(struct ixgbe_adapter *adapter)
5038{
d2f5e7f3
AS		 5039 struct ixgbe_hw *hw = &adapter->hw;
5040
80605c65 5041 ixgbe_configure_pb(adapter);
7a6b6f51 5042#ifdef CONFIG_IXGBE_DCB
67ebd791 5043 ixgbe_configure_dcb(adapter);
2f90b865 5044#endif
b35d4d42
AD		 5045 /*
5046 * We must restore virtualization before VLANs or else
5047 * the VLVF registers will not be populated
5048 */
5049 ixgbe_configure_virtualization(adapter);
9a799d71 5050
4c1d7b4b 5051 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 5052 ixgbe_restore_vlan(adapter);
5053
d2f5e7f3
AS		 5054 switch (hw->mac.type) {
5055 case ixgbe_mac_82599EB:
5056 case ixgbe_mac_X540:
5057 hw->mac.ops.disable_rx_buff(hw);
5058 break;
5059 default:
5060 break;
5061 }
5062
c4cf55e5 5063 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 5064 ixgbe_init_fdir_signature_82599(&adapter->hw,
5065 adapter->fdir_pballoc);
e4911d57
AD		 5066 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5067 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5068 adapter->fdir_pballoc);
5069 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 5070 }
4c1d7b4b 5071
d2f5e7f3
AS		 5072 switch (hw->mac.type) {
5073 case ixgbe_mac_82599EB:
5074 case ixgbe_mac_X540:
5075 hw->mac.ops.enable_rx_buff(hw);
5076 break;
5077 default:
5078 break;
5079 }
5080
9de7605e
MR		 5081#ifdef CONFIG_IXGBE_DCA
5082 /* configure DCA */
5083 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5084 ixgbe_setup_dca(adapter);
5085#endif /* CONFIG_IXGBE_DCA */
5086
7c8ae65a
AD		 5087#ifdef IXGBE_FCOE
5088 /* configure FCoE L2 filters, redirection table, and Rx control */
5089 ixgbe_configure_fcoe(adapter);
5090
5091#endif /* IXGBE_FCOE */
9a799d71
AK		 5092 ixgbe_configure_tx(adapter);
5093 ixgbe_configure_rx(adapter);
2a47fa45 5094 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 5095}
5096
0ecc061d 5097/**
e8e26350
PW		 5098 * ixgbe_sfp_link_config - set up SFP+ link
5099 * @adapter: pointer to private adapter struct
5100 **/
5101static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5102{
7086400d 5103 /*
52f33af8 5104 * We are assuming the worst case scenario here, and that
7086400d
AD		 5105 * is that an SFP was inserted/removed after the reset
5106 * but before SFP detection was enabled. As such the best
5107 * solution is to just start searching as soon as we start
5108 */
5109 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5110 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 5111
7086400d 5112 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 5113 adapter->sfp_poll_time = 0;
e8e26350
PW		 5114}
5115
5116/**
5117 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 5118 * @hw: pointer to private hardware struct
5119 *
5120 * Returns 0 on success, negative on failure
5121 **/
e8e26350 5122static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 5123{
3d292265
JH		 5124 u32 speed;
5125 bool autoneg, link_up = false;
a1e869de 5126 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 5127
5128 if (hw->mac.ops.check_link)
3d292265 5129 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 5130
5131 if (ret)
e90dd264 5132 return ret;
0ecc061d 5133
3d292265
JH		 5134 speed = hw->phy.autoneg_advertised;
5135 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5136 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5137 &autoneg);
0ecc061d 5138 if (ret)
e90dd264 5139 return ret;
0ecc061d 5140
8620a103 5141 if (hw->mac.ops.setup_link)
fd0326f2 5142 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 5143
0ecc061d
PWJ		 5144 return ret;
5145}
5146
a34bcfff 5147static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 5148{
9a799d71 5149 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5150 u32 gpie = 0;
9a799d71 5151
9b471446 5152 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 5153 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5154 IXGBE_GPIE_OCD;
5155 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 5156 /*
5157 * use EIAM to auto-mask when MSI-X interrupt is asserted
5158 * this saves a register write for every interrupt
5159 */
5160 switch (hw->mac.type) {
5161 case ixgbe_mac_82598EB:
5162 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5163 break;
9b471446 5164 case ixgbe_mac_82599EB:
b93a2226 5165 case ixgbe_mac_X540:
9a75a1ac
DS		 5166 case ixgbe_mac_X550:
5167 case ixgbe_mac_X550EM_x:
49425dfc 5168 case ixgbe_mac_x550em_a:
b93a2226 5169 default:
9b471446
JB		 5170 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5171 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5172 break;
5173 }
5174 } else {
021230d4
AV		 5175 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5176 * specifically only auto mask tx and rx interrupts */
5177 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5178 }
9a799d71 5179
a34bcfff
AD		 5180 /* XXX: to interrupt immediately for EICS writes, enable this */
5181 /* gpie |= IXGBE_GPIE_EIMEN; */
5182
5183 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5184 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 5185
5186 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5187 case IXGBE_82599_VMDQ_8Q_MASK:
5188 gpie |= IXGBE_GPIE_VTMODE_16;
5189 break;
5190 case IXGBE_82599_VMDQ_4Q_MASK:
5191 gpie |= IXGBE_GPIE_VTMODE_32;
5192 break;
5193 default:
5194 gpie |= IXGBE_GPIE_VTMODE_64;
5195 break;
5196 }
119fc60a
MC		 5197 }
5198
5fdd31f9 5199 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 5200 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5201 switch (adapter->hw.mac.type) {
5202 case ixgbe_mac_82599EB:
9a900eca 5203 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 5204 break;
f3df98ec
DS		 5205 default:
5206 break;
5207 }
5208 }
5fdd31f9 5209
a34bcfff
AD		 5210 /* Enable fan failure interrupt */
5211 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 5212 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 5213
a023bbd0
DS		 5214 switch (hw->mac.type) {
5215 case ixgbe_mac_82599EB:
5216 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5217 break;
5218 case ixgbe_mac_X550EM_x:
49425dfc 5219 case ixgbe_mac_x550em_a:
a023bbd0
DS		 5220 gpie |= IXGBE_SDP0_GPIEN_X540;
5221 break;
5222 default:
5223 break;
2698b208 5224 }
a34bcfff
AD		 5225
5226 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5227}
5228
c7ccde0f 5229static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 5230{
5231 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5232 int err;
a34bcfff
AD		 5233 u32 ctrl_ext;
5234
5235 ixgbe_get_hw_control(adapter);
5236 ixgbe_setup_gpie(adapter);
e8e26350 5237
9a799d71
AK		 5238 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5239 ixgbe_configure_msix(adapter);
5240 else
5241 ixgbe_configure_msi_and_legacy(adapter);
5242
ec74a471
ET		 5243 /* enable the optics for 82599 SFP+ fiber */
5244 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 5245 hw->mac.ops.enable_tx_laser(hw);
5246
961fac88
DS		 5247 if (hw->phy.ops.set_phy_power)
5248 hw->phy.ops.set_phy_power(hw, true);
5249
4e857c58 5250 smp_mb__before_atomic();
9a799d71 5251 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 5252 ixgbe_napi_enable_all(adapter);
5253
73c4b7cd
AD		 5254 if (ixgbe_is_sfp(hw)) {
5255 ixgbe_sfp_link_config(adapter);
5256 } else {
5257 err = ixgbe_non_sfp_link_config(hw);
5258 if (err)
5259 e_err(probe, "link_config FAILED %d\n", err);
5260 }
5261
021230d4
AV		 5262 /* clear any pending interrupts, may auto mask */
5263 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 5264 ixgbe_irq_enable(adapter, true, true);
9a799d71 5265
bf069c97
DS		 5266 /*
5267 * If this adapter has a fan, check to see if we had a failure
5268 * before we enabled the interrupt.
5269 */
5270 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5271 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5272 if (esdp & IXGBE_ESDP_SDP1)
396e799c 5273 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 5274 }
5275
9a799d71
AK		 5276 /* bring the link up in the watchdog, this could race with our first
5277 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 5278 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5279 adapter->link_check_timeout = jiffies;
7086400d 5280 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 5281
5282 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5283 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5284 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5285 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5286}
5287
d4f80882
AV		 5288void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5289{
5290 WARN_ON(in_interrupt());
7086400d 5291 /* put off any impending NetWatchDogTimeout */
860e9538 5292 netif_trans_update(adapter->netdev);
7086400d 5293
d4f80882 5294 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5295 usleep_range(1000, 2000);
d4f80882 5296 ixgbe_down(adapter);
5809a1ae
GR		 5297 /*
5298 * If SR-IOV enabled then wait a bit before bringing the adapter
5299 * back up to give the VFs time to respond to the reset. The
5300 * two second wait is based upon the watchdog timer cycle in
5301 * the VF driver.
5302 */
5303 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5304 msleep(2000);
d4f80882
AV		 5305 ixgbe_up(adapter);
5306 clear_bit(__IXGBE_RESETTING, &adapter->state);
5307}
5308
c7ccde0f 5309void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5310{
5311 /* hardware has been reset, we need to reload some things */
5312 ixgbe_configure(adapter);
5313
c7ccde0f 5314 ixgbe_up_complete(adapter);
9a799d71
AK		 5315}
5316
5317void ixgbe_reset(struct ixgbe_adapter *adapter)
5318{
c44ade9e 5319 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5320 struct net_device *netdev = adapter->netdev;
8ca783ab
DS		 5321 int err;
5322
b0483c8f
MR		 5323 if (ixgbe_removed(hw->hw_addr))
5324 return;
7086400d
AD		 5325 /* lock SFP init bit to prevent race conditions with the watchdog */
5326 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5327 usleep_range(1000, 2000);
5328
5329 /* clear all SFP and link config related flags while holding SFP_INIT */
5330 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5331 IXGBE_FLAG2_SFP_NEEDS_RESET);
5332 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5333
8ca783ab 5334 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5335 switch (err) {
5336 case 0:
5337 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5338 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5339 break;
5340 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5341 e_dev_err("master disable timed out\n");
da4dd0f7 5342 break;
794caeb2
PWJ		 5343 case IXGBE_ERR_EEPROM_VERSION:
5344 /* We are running on a pre-production device, log a warning */
849c4542 5345 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5346 "Please be aware there may be issues associated with "
849c4542
ET		 5347 "your hardware. If you are experiencing problems "
5348 "please contact your Intel or hardware "
5349 "representative who provided you with this "
5350 "hardware.\n");
794caeb2 5351 break;
da4dd0f7 5352 default:
849c4542 5353 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5354 }
9a799d71 5355
7086400d 5356 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
0f079d22
AD		 5357
5358 /* flush entries out of MAC table */
5d7daa35 5359 ixgbe_flush_sw_mac_table(adapter);
0f079d22
AD		 5360 __dev_uc_unsync(netdev, NULL);
5361
5362 /* do not flush user set addresses */
c9f53e63 5363 ixgbe_mac_set_default_filter(adapter);
7fa7c9dc
AD		 5364
5365 /* update SAN MAC vmdq pool selection */
5366 if (hw->mac.san_mac_rar_index)
5367 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5368
8fecf67c 5369 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5370 ixgbe_ptp_reset(adapter);
961fac88
DS		 5371
5372 if (hw->phy.ops.set_phy_power) {
5373 if (!netif_running(adapter->netdev) && !adapter->wol)
5374 hw->phy.ops.set_phy_power(hw, false);
5375 else
5376 hw->phy.ops.set_phy_power(hw, true);
5377 }
9a799d71
AK		 5378}
5379
9a799d71
AK		 5380/**
5381 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5382 * @tx_ring: ring to be cleaned
5383 **/
b6ec895e 5384static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5385{
5386 struct ixgbe_tx_buffer *tx_buffer_info;
5387 unsigned long size;
b6ec895e 5388 u16 i;
9a799d71 5389
84418e3b
AD		 5390 /* ring already cleared, nothing to do */
5391 if (!tx_ring->tx_buffer_info)
5392 return;
9a799d71 5393
84418e3b 5394 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5395 for (i = 0; i < tx_ring->count; i++) {
5396 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5397 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5398 }
5399
dad8a3b3
JF		 5400 netdev_tx_reset_queue(txring_txq(tx_ring));
5401
9a799d71
AK		 5402 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5403 memset(tx_ring->tx_buffer_info, 0, size);
5404
5405 /* Zero out the descriptor ring */
5406 memset(tx_ring->desc, 0, tx_ring->size);
5407
5408 tx_ring->next_to_use = 0;
5409 tx_ring->next_to_clean = 0;
9a799d71
AK		 5410}
5411
5412/**
021230d4 5413 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5414 * @adapter: board private structure
5415 **/
021230d4 5416static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5417{
5418 int i;
5419
021230d4 5420 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5421 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5422}
5423
5424/**
021230d4 5425 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5426 * @adapter: board private structure
5427 **/
021230d4 5428static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5429{
5430 int i;
5431
021230d4 5432 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5433 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5434}
5435
e4911d57
AD		 5436static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5437{
b67bfe0d 5438 struct hlist_node *node2;
e4911d57
AD		 5439 struct ixgbe_fdir_filter *filter;
5440
5441 spin_lock(&adapter->fdir_perfect_lock);
5442
b67bfe0d 5443 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5444 &adapter->fdir_filter_list, fdir_node) {
5445 hlist_del(&filter->fdir_node);
5446 kfree(filter);
5447 }
5448 adapter->fdir_filter_count = 0;
5449
5450 spin_unlock(&adapter->fdir_perfect_lock);
5451}
5452
1cd127fc
DA		 5453static int ixgbe_disable_macvlan(struct net_device *upper, void *data)
5454{
5455 if (netif_is_macvlan(upper)) {
5456 struct macvlan_dev *vlan = netdev_priv(upper);
5457
5458 if (vlan->fwd_priv) {
5459 netif_tx_stop_all_queues(upper);
5460 netif_carrier_off(upper);
5461 netif_tx_disable(upper);
5462 }
5463 }
5464
5465 return 0;
5466}
5467
9a799d71
AK		 5468void ixgbe_down(struct ixgbe_adapter *adapter)
5469{
5470 struct net_device *netdev = adapter->netdev;
7f821875 5471 struct ixgbe_hw *hw = &adapter->hw;
bf29ee6c 5472 int i;
9a799d71
AK		 5473
5474 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5475 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5476 return; /* do nothing if already down */
9a799d71
AK		 5477
5478 /* disable receives */
1f9ac57c 5479 hw->mac.ops.disable_rx(hw);
9a799d71 5480
2d39d576
YZ		 5481 /* disable all enabled rx queues */
5482 for (i = 0; i < adapter->num_rx_queues; i++)
5483 /* this call also flushes the previous write */
5484 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5485
032b4325 5486 usleep_range(10000, 20000);
9a799d71 5487
7f821875
JB		 5488 netif_tx_stop_all_queues(netdev);
5489
7086400d 5490 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5491 netif_carrier_off(netdev);
5492 netif_tx_disable(netdev);
5493
2a47fa45 5494 /* disable any upper devices */
1cd127fc
DA		 5495 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5496 ixgbe_disable_macvlan, NULL);
2a47fa45 5497
c0dfb90e
JF		 5498 ixgbe_irq_disable(adapter);
5499
5500 ixgbe_napi_disable_all(adapter);
5501
57ca2a4f
ET		 5502 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
5503 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7086400d
AD		 5504 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5505
5506 del_timer_sync(&adapter->service_timer);
5507
34cecbbf 5508 if (adapter->num_vfs) {
8e34d1aa
AD		 5509 /* Clear EITR Select mapping */
5510 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5511
5512 /* Mark all the VFs as inactive */
5513 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5514 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5515
34cecbbf
AD		 5516 /* ping all the active vfs to let them know we are going down */
5517 ixgbe_ping_all_vfs(adapter);
5518
5519 /* Disable all VFTE/VFRE TX/RX */
5520 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5521 }
5522
7f821875
JB		 5523 /* disable transmits in the hardware now that interrupts are off */
5524 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5525 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5526 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5527 }
34cecbbf 5528
9a75a1ac 5529 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5530 switch (hw->mac.type) {
5531 case ixgbe_mac_82599EB:
b93a2226 5532 case ixgbe_mac_X540:
9a75a1ac
DS		 5533 case ixgbe_mac_X550:
5534 case ixgbe_mac_X550EM_x:
49425dfc 5535 case ixgbe_mac_x550em_a:
88512539 5536 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5537 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5538 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5539 break;
5540 default:
5541 break;
5542 }
7f821875 5543
6f4a0e45
PL		 5544 if (!pci_channel_offline(adapter->pdev))
5545 ixgbe_reset(adapter);
c6ecf39a 5546
ec74a471
ET		 5547 /* power down the optics for 82599 SFP+ fiber */
5548 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5549 hw->mac.ops.disable_tx_laser(hw);
5550
9a799d71
AK		 5551 ixgbe_clean_all_tx_rings(adapter);
5552 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 5553}
5554
9a799d71
AK		 5555/**
5556 * ixgbe_tx_timeout - Respond to a Tx Hang
5557 * @netdev: network interface device structure
5558 **/
5559static void ixgbe_tx_timeout(struct net_device *netdev)
5560{
5561 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5562
5563 /* Do the reset outside of interrupt context */
c83c6cbd 5564 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5565}
5566
8829009d
UK		 5567#ifdef CONFIG_IXGBE_DCB
5568static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
5569{
5570 struct ixgbe_hw *hw = &adapter->hw;
5571 struct tc_configuration *tc;
5572 int j;
5573
5574 switch (hw->mac.type) {
5575 case ixgbe_mac_82598EB:
5576 case ixgbe_mac_82599EB:
5577 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5578 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5579 break;
5580 case ixgbe_mac_X540:
5581 case ixgbe_mac_X550:
5582 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5583 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5584 break;
5585 case ixgbe_mac_X550EM_x:
5586 case ixgbe_mac_x550em_a:
5587 default:
5588 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
5589 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
5590 break;
5591 }
5592
5593 /* Configure DCB traffic classes */
5594 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5595 tc = &adapter->dcb_cfg.tc_config[j];
5596 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5597 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5598 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5599 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5600 tc->dcb_pfc = pfc_disabled;
5601 }
5602
5603 /* Initialize default user to priority mapping, UPx->TC0 */
5604 tc = &adapter->dcb_cfg.tc_config[0];
5605 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5606 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5607
5608 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5609 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5610 adapter->dcb_cfg.pfc_mode_enable = false;
5611 adapter->dcb_set_bitmap = 0x00;
5612 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
5613 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5614 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5615 sizeof(adapter->temp_dcb_cfg));
5616}
5617#endif
5618
9a799d71
AK		 5619/**
5620 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5621 * @adapter: board private structure to initialize
5622 *
5623 * ixgbe_sw_init initializes the Adapter private data structure.
5624 * Fields are initialized based on PCI device information and
5625 * OS network device settings (MTU size).
5626 **/
55570b6f
ET		 5627static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
5628 const struct ixgbe_info *ii)
9a799d71
AK		 5629{
5630 struct ixgbe_hw *hw = &adapter->hw;
5631 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5632 unsigned int rss, fdir;
cb6d0f5e 5633 u32 fwsm;
1cdaaf54 5634 int i;
021230d4 5635
c44ade9e
JB		 5636 /* PCI config space info */
5637
5638 hw->vendor_id = pdev->vendor;
5639 hw->device_id = pdev->device;
5640 hw->revision_id = pdev->revision;
5641 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5642 hw->subsystem_device_id = pdev->subsystem_device;
5643
55570b6f
ET		 5644 /* get_invariants needs the device IDs */
5645 ii->get_invariants(hw);
5646
8fc3bb6d 5647 /* Set common capability flags and settings */
0f9b232b 5648 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5649 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 5650 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 5651 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5652 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5653 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5654 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5655 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5656#ifdef CONFIG_IXGBE_DCA
5657 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5658#endif
8829009d
UK		 5659#ifdef CONFIG_IXGBE_DCB
5660 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
5661 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
5662#endif
8fc3bb6d
ET		 5663#ifdef IXGBE_FCOE
5664 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5665 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5666#ifdef CONFIG_IXGBE_DCB
5667 /* Default traffic class to use for FCoE */
5668 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5669#endif /* CONFIG_IXGBE_DCB */
5670#endif /* IXGBE_FCOE */
5671
b82b17d9 5672 /* initialize static ixgbe jump table entries */
1cdaaf54
AN		 5673 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
5674 GFP_KERNEL);
5675 if (!adapter->jump_tables[0])
5676 return -ENOMEM;
5677 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
5678
5679 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
5680 adapter->jump_tables[i] = NULL;
b82b17d9 5681
5d7daa35
JK		 5682 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5683 hw->mac.num_rar_entries,
5684 GFP_ATOMIC);
530fd82a
AD		 5685 if (!adapter->mac_table)
5686 return -ENOMEM;
5d7daa35 5687
8fc3bb6d 5688 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5689 switch (hw->mac.type) {
5690 case ixgbe_mac_82598EB:
8fc3bb6d 5691 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 5692
bf069c97
DS		 5693 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5694 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5695
49c7ffbe 5696 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5697 adapter->ring_feature[RING_F_FDIR].limit = 0;
5698 adapter->atr_sample_rate = 0;
5699 adapter->fdir_pballoc = 0;
5700#ifdef IXGBE_FCOE
5701 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5702 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5703#ifdef CONFIG_IXGBE_DCB
5704 adapter->fcoe.up = 0;
5705#endif /* IXGBE_DCB */
5706#endif /* IXGBE_FCOE */
5707 break;
5708 case ixgbe_mac_82599EB:
5709 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5710 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5711 break;
b93a2226 5712 case ixgbe_mac_X540:
9a900eca 5713 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5714 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5715 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5716 break;
49425dfc 5717 case ixgbe_mac_x550em_a:
a21d0822
ET		 5718 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE;
5719 /* fall through */
5720 case ixgbe_mac_X550EM_x:
8829009d
UK		 5721#ifdef CONFIG_IXGBE_DCB
5722 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
5723#endif
5724#ifdef IXGBE_FCOE
5725 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5726#ifdef CONFIG_IXGBE_DCB
5727 adapter->fcoe.up = 0;
5728#endif /* IXGBE_DCB */
5729#endif /* IXGBE_FCOE */
5730 /* Fall Through */
9a75a1ac
DS		 5731 case ixgbe_mac_X550:
5732#ifdef CONFIG_IXGBE_DCA
5733 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c 5734#endif
67359c3c 5735 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac 5736 break;
bd508178
AD		 5737 default:
5738 break;
f8212f97 5739 }
2f90b865 5740
7c8ae65a
AD		 5741#ifdef IXGBE_FCOE
5742 /* FCoE support exists, always init the FCoE lock */
5743 spin_lock_init(&adapter->fcoe.lock);
5744
5745#endif
1fc5f038
AD		 5746 /* n-tuple support exists, always init our spinlock */
5747 spin_lock_init(&adapter->fdir_perfect_lock);
5748
7a6b6f51 5749#ifdef CONFIG_IXGBE_DCB
8829009d 5750 ixgbe_init_dcb(adapter);
2f90b865 5751#endif
9a799d71
AK		 5752
5753 /* default flow control settings */
cd7664f6 5754 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5755 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5756 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5757 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5758 hw->fc.send_xon = true;
73d80953 5759 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5760
99d74487 5761#ifdef CONFIG_PCI_IOV
170e8543
JK		 5762 if (max_vfs > 0)
5763 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5764
99d74487 5765 /* assign number of SR-IOV VFs */
170e8543 5766 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5767 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5768 adapter->num_vfs = 0;
5769 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5770 } else {
5771 adapter->num_vfs = max_vfs;
5772 }
5773 }
5774#endif /* CONFIG_PCI_IOV */
99d74487 5775
30efa5a3 5776 /* enable itr by default in dynamic mode */
f7554a2b 5777 adapter->rx_itr_setting = 1;
f7554a2b 5778 adapter->tx_itr_setting = 1;
30efa5a3 5779
30efa5a3
JB		 5780 /* set default ring sizes */
5781 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5782 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5783
bd198058 5784 /* set default work limits */
59224555 5785 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5786
9a799d71 5787 /* initialize eeprom parameters */
c44ade9e 5788 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5789 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5790 return -EIO;
5791 }
5792
2a47fa45
JF		 5793 /* PF holds first pool slot */
5794 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5795 set_bit(__IXGBE_DOWN, &adapter->state);
5796
5797 return 0;
5798}
5799
5800/**
5801 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5802 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5803 *
5804 * Return 0 on success, negative on failure
5805 **/
b6ec895e 5806int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5807{
b6ec895e 5808 struct device *dev = tx_ring->dev;
de88eeeb 5809 int orig_node = dev_to_node(dev);
ca8dfe25 5810 int ring_node = -1;
9a799d71
AK		 5811 int size;
5812
3a581073 5813 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5814
5815 if (tx_ring->q_vector)
ca8dfe25 5816 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5817
ca8dfe25 5818 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5819 if (!tx_ring->tx_buffer_info)
89bf67f1 5820 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5821 if (!tx_ring->tx_buffer_info)
5822 goto err;
9a799d71 5823
827da44c
JS		 5824 u64_stats_init(&tx_ring->syncp);
5825
9a799d71 5826 /* round up to nearest 4K */
12207e49 5827 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5828 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5829
ca8dfe25 5830 set_dev_node(dev, ring_node);
de88eeeb
AD		 5831 tx_ring->desc = dma_alloc_coherent(dev,
5832 tx_ring->size,
5833 &tx_ring->dma,
5834 GFP_KERNEL);
5835 set_dev_node(dev, orig_node);
5836 if (!tx_ring->desc)
5837 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5838 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5839 if (!tx_ring->desc)
5840 goto err;
9a799d71 5841
3a581073
JB		 5842 tx_ring->next_to_use = 0;
5843 tx_ring->next_to_clean = 0;
9a799d71 5844 return 0;
e01c31a5
JB		 5845
5846err:
5847 vfree(tx_ring->tx_buffer_info);
5848 tx_ring->tx_buffer_info = NULL;
b6ec895e 5849 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5850 return -ENOMEM;
9a799d71
AK		 5851}
5852
69888674
AD		 5853/**
5854 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5855 * @adapter: board private structure
5856 *
5857 * If this function returns with an error, then it's possible one or
5858 * more of the rings is populated (while the rest are not). It is the
5859 * callers duty to clean those orphaned rings.
5860 *
5861 * Return 0 on success, negative on failure
5862 **/
5863static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5864{
5865 int i, err = 0;
5866
5867 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5868 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5869 if (!err)
5870 continue;
de3d5b94 5871
396e799c 5872 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5873 goto err_setup_tx;
69888674
AD		 5874 }
5875
de3d5b94
AD		 5876 return 0;
5877err_setup_tx:
5878 /* rewind the index freeing the rings as we go */
5879 while (i--)
5880 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5881 return err;
5882}
5883
9a799d71
AK		 5884/**
5885 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5886 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5887 *
5888 * Returns 0 on success, negative on failure
5889 **/
b6ec895e 5890int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5891{
b6ec895e 5892 struct device *dev = rx_ring->dev;
de88eeeb 5893 int orig_node = dev_to_node(dev);
ca8dfe25 5894 int ring_node = -1;
021230d4 5895 int size;
9a799d71 5896
3a581073 5897 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5898
5899 if (rx_ring->q_vector)
ca8dfe25 5900 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5901
ca8dfe25 5902 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5903 if (!rx_ring->rx_buffer_info)
89bf67f1 5904 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5905 if (!rx_ring->rx_buffer_info)
5906 goto err;
9a799d71 5907
827da44c
JS		 5908 u64_stats_init(&rx_ring->syncp);
5909
9a799d71 5910 /* Round up to nearest 4K */
3a581073
JB		 5911 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5912 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5913
ca8dfe25 5914 set_dev_node(dev, ring_node);
de88eeeb
AD		 5915 rx_ring->desc = dma_alloc_coherent(dev,
5916 rx_ring->size,
5917 &rx_ring->dma,
5918 GFP_KERNEL);
5919 set_dev_node(dev, orig_node);
5920 if (!rx_ring->desc)
5921 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5922 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5923 if (!rx_ring->desc)
5924 goto err;
9a799d71 5925
3a581073
JB		 5926 rx_ring->next_to_clean = 0;
5927 rx_ring->next_to_use = 0;
9a799d71
AK		 5928
5929 return 0;
b6ec895e
AD		 5930err:
5931 vfree(rx_ring->rx_buffer_info);
5932 rx_ring->rx_buffer_info = NULL;
5933 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5934 return -ENOMEM;
9a799d71
AK		 5935}
5936
69888674
AD		 5937/**
5938 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5939 * @adapter: board private structure
5940 *
5941 * If this function returns with an error, then it's possible one or
5942 * more of the rings is populated (while the rest are not). It is the
5943 * callers duty to clean those orphaned rings.
5944 *
5945 * Return 0 on success, negative on failure
5946 **/
69888674
AD		 5947static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5948{
5949 int i, err = 0;
5950
5951 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5952 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5953 if (!err)
5954 continue;
de3d5b94 5955
396e799c 5956 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5957 goto err_setup_rx;
69888674
AD		 5958 }
5959
7c8ae65a
AD		 5960#ifdef IXGBE_FCOE
5961 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5962 if (!err)
5963#endif
5964 return 0;
de3d5b94
AD		 5965err_setup_rx:
5966 /* rewind the index freeing the rings as we go */
5967 while (i--)
5968 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5969 return err;
5970}
5971
9a799d71
AK		 5972/**
5973 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5974 * @tx_ring: Tx descriptor ring for a specific queue
5975 *
5976 * Free all transmit software resources
5977 **/
b6ec895e 5978void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5979{
b6ec895e 5980 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5981
5982 vfree(tx_ring->tx_buffer_info);
5983 tx_ring->tx_buffer_info = NULL;
5984
b6ec895e
AD		 5985 /* if not set, then don't free */
5986 if (!tx_ring->desc)
5987 return;
5988
5989 dma_free_coherent(tx_ring->dev, tx_ring->size,
5990 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5991
5992 tx_ring->desc = NULL;
5993}
5994
5995/**
5996 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5997 * @adapter: board private structure
5998 *
5999 * Free all transmit software resources
6000 **/
6001static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6002{
6003 int i;
6004
6005 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 6006 if (adapter->tx_ring[i]->desc)
b6ec895e 6007 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 6008}
6009
6010/**
b4617240 6011 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 6012 * @rx_ring: ring to clean the resources from
6013 *
6014 * Free all receive software resources
6015 **/
b6ec895e 6016void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 6017{
b6ec895e 6018 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 6019
6020 vfree(rx_ring->rx_buffer_info);
6021 rx_ring->rx_buffer_info = NULL;
6022
b6ec895e
AD		 6023 /* if not set, then don't free */
6024 if (!rx_ring->desc)
6025 return;
6026
6027 dma_free_coherent(rx_ring->dev, rx_ring->size,
6028 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 6029
6030 rx_ring->desc = NULL;
6031}
6032
6033/**
6034 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6035 * @adapter: board private structure
6036 *
6037 * Free all receive software resources
6038 **/
6039static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6040{
6041 int i;
6042
7c8ae65a
AD		 6043#ifdef IXGBE_FCOE
6044 ixgbe_free_fcoe_ddp_resources(adapter);
6045
6046#endif
9a799d71 6047 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 6048 if (adapter->rx_ring[i]->desc)
b6ec895e 6049 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 6050}
6051
9a799d71
AK		 6052/**
6053 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6054 * @netdev: network interface device structure
6055 * @new_mtu: new value for maximum frame size
6056 *
6057 * Returns 0 on success, negative on failure
6058 **/
6059static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6060{
6061 struct ixgbe_adapter *adapter = netdev_priv(netdev);
655309e9
AD		 6062
6063 /*
872844dd
AD		 6064 * For 82599EB we cannot allow legacy VFs to enable their receive
6065 * paths when MTU greater than 1500 is configured. So display a
6066 * warning that legacy VFs will be disabled.
655309e9
AD		 6067 */
6068 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6069 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
91c527a5 6070 (new_mtu > ETH_DATA_LEN))
872844dd 6071 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 6072
396e799c 6073 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 6074
021230d4 6075 /* must set new MTU before calling down or up */
9a799d71
AK		 6076 netdev->mtu = new_mtu;
6077
d4f80882
AV		 6078 if (netif_running(netdev))
6079 ixgbe_reinit_locked(adapter);
9a799d71
AK		 6080
6081 return 0;
6082}
6083
6084/**
6085 * ixgbe_open - Called when a network interface is made active
6086 * @netdev: network interface device structure
6087 *
6088 * Returns 0 on success, negative value on failure
6089 *
6090 * The open entry point is called when a network interface is made
6091 * active by the system (IFF_UP). At this point all resources needed
6092 * for transmit and receive operations are allocated, the interrupt
6093 * handler is registered with the OS, the watchdog timer is started,
6094 * and the stack is notified that the interface is ready.
6095 **/
6c211fe1 6096int ixgbe_open(struct net_device *netdev)
9a799d71
AK		 6097{
6098 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 6099 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 6100 int err, queues;
4bebfaa5
AK		 6101
6102 /* disallow open during test */
6103 if (test_bit(__IXGBE_TESTING, &adapter->state))
6104 return -EBUSY;
9a799d71 6105
54386467
JB		 6106 netif_carrier_off(netdev);
6107
9a799d71
AK		 6108 /* allocate transmit descriptors */
6109 err = ixgbe_setup_all_tx_resources(adapter);
6110 if (err)
6111 goto err_setup_tx;
6112
9a799d71
AK		 6113 /* allocate receive descriptors */
6114 err = ixgbe_setup_all_rx_resources(adapter);
6115 if (err)
6116 goto err_setup_rx;
6117
6118 ixgbe_configure(adapter);
6119
021230d4 6120 err = ixgbe_request_irq(adapter);
9a799d71
AK		 6121 if (err)
6122 goto err_req_irq;
6123
ac802f5d 6124 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 6125 if (adapter->num_rx_pools > 1)
6126 queues = adapter->num_rx_queues_per_pool;
6127 else
6128 queues = adapter->num_tx_queues;
6129
6130 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 6131 if (err)
6132 goto err_set_queues;
6133
2a47fa45
JF		 6134 if (adapter->num_rx_pools > 1 &&
6135 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6136 queues = IXGBE_MAX_L2A_QUEUES;
6137 else
6138 queues = adapter->num_rx_queues;
6139 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 6140 if (err)
6141 goto err_set_queues;
6142
1a71ab24 6143 ixgbe_ptp_init(adapter);
1a71ab24 6144
c7ccde0f 6145 ixgbe_up_complete(adapter);
9a799d71 6146
a21d0822 6147 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK);
b3a49557 6148 udp_tunnel_get_rx_info(netdev);
67359c3c 6149
9a799d71
AK		 6150 return 0;
6151
ac802f5d
AD		 6152err_set_queues:
6153 ixgbe_free_irq(adapter);
9a799d71 6154err_req_irq:
a20a1199 6155 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 6156 if (hw->phy.ops.set_phy_power && !adapter->wol)
6157 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 6158err_setup_rx:
a20a1199 6159 ixgbe_free_all_tx_resources(adapter);
de3d5b94 6160err_setup_tx:
9a799d71
AK		 6161 ixgbe_reset(adapter);
6162
6163 return err;
6164}
6165
a0cccce2
JK		 6166static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6167{
6168 ixgbe_ptp_suspend(adapter);
6169
6ac74394
DS		 6170 if (adapter->hw.phy.ops.enter_lplu) {
6171 adapter->hw.phy.reset_disable = true;
6172 ixgbe_down(adapter);
6173 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6174 adapter->hw.phy.reset_disable = false;
6175 } else {
6176 ixgbe_down(adapter);
6177 }
6178
a0cccce2
JK		 6179 ixgbe_free_irq(adapter);
6180
6181 ixgbe_free_all_tx_resources(adapter);
6182 ixgbe_free_all_rx_resources(adapter);
6183}
6184
9a799d71
AK		 6185/**
6186 * ixgbe_close - Disables a network interface
6187 * @netdev: network interface device structure
6188 *
6189 * Returns 0, this is not allowed to fail
6190 *
6191 * The close entry point is called when an interface is de-activated
6192 * by the OS. The hardware is still under the drivers control, but
6193 * needs to be disabled. A global MAC reset is issued to stop the
6194 * hardware, and all transmit and receive resources are freed.
6195 **/
6c211fe1 6196int ixgbe_close(struct net_device *netdev)
9a799d71
AK		 6197{
6198 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 6199
1a71ab24 6200 ixgbe_ptp_stop(adapter);
1a71ab24 6201
a0cccce2 6202 ixgbe_close_suspend(adapter);
9a799d71 6203
e4911d57
AD		 6204 ixgbe_fdir_filter_exit(adapter);
6205
5eba3699 6206 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6207
6208 return 0;
6209}
6210
b3c8b4ba
AD		 6211#ifdef CONFIG_PM
6212static int ixgbe_resume(struct pci_dev *pdev)
6213{
c60fbb00
AD		 6214 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6215 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 6216 u32 err;
6217
0391bbe3 6218 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 6219 pci_set_power_state(pdev, PCI_D0);
6220 pci_restore_state(pdev);
656ab817
DS		 6221 /*
6222 * pci_restore_state clears dev->state_saved so call
6223 * pci_save_state to restore it.
6224 */
6225 pci_save_state(pdev);
9ce77666 6226
6227 err = pci_enable_device_mem(pdev);
b3c8b4ba 6228 if (err) {
849c4542 6229 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 6230 return err;
6231 }
4e857c58 6232 smp_mb__before_atomic();
41c62843 6233 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 6234 pci_set_master(pdev);
6235
dd4d8ca6 6236 pci_wake_from_d3(pdev, false);
b3c8b4ba 6237
b3c8b4ba
AD		 6238 ixgbe_reset(adapter);
6239
495dce12
WJP		 6240 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6241
ac802f5d
AD		 6242 rtnl_lock();
6243 err = ixgbe_init_interrupt_scheme(adapter);
6244 if (!err && netif_running(netdev))
c60fbb00 6245 err = ixgbe_open(netdev);
ac802f5d
AD		 6246
6247 rtnl_unlock();
6248
6249 if (err)
6250 return err;
b3c8b4ba
AD		 6251
6252 netif_device_attach(netdev);
6253
6254 return 0;
6255}
b3c8b4ba 6256#endif /* CONFIG_PM */
9d8d05ae
RW		 6257
6258static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 6259{
c60fbb00
AD		 6260 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6261 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 6262 struct ixgbe_hw *hw = &adapter->hw;
6263 u32 ctrl, fctrl;
6264 u32 wufc = adapter->wol;
b3c8b4ba
AD		 6265#ifdef CONFIG_PM
6266 int retval = 0;
6267#endif
6268
6269 netif_device_detach(netdev);
6270
499ab5cc 6271 rtnl_lock();
a0cccce2
JK		 6272 if (netif_running(netdev))
6273 ixgbe_close_suspend(adapter);
499ab5cc 6274 rtnl_unlock();
b3c8b4ba 6275
5f5ae6fc
AD		 6276 ixgbe_clear_interrupt_scheme(adapter);
6277
b3c8b4ba
AD		 6278#ifdef CONFIG_PM
6279 retval = pci_save_state(pdev);
6280 if (retval)
6281 return retval;
4df10466 6282
b3c8b4ba 6283#endif
f4f1040a
JK		 6284 if (hw->mac.ops.stop_link_on_d3)
6285 hw->mac.ops.stop_link_on_d3(hw);
6286
e8e26350
PW		 6287 if (wufc) {
6288 ixgbe_set_rx_mode(netdev);
b3c8b4ba 6289
ec74a471
ET		 6290 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6291 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 6292 hw->mac.ops.enable_tx_laser(hw);
6293
e8e26350
PW		 6294 /* turn on all-multi mode if wake on multicast is enabled */
6295 if (wufc & IXGBE_WUFC_MC) {
6296 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6297 fctrl |= IXGBE_FCTRL_MPE;
6298 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6299 }
6300
6301 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6302 ctrl |= IXGBE_CTRL_GIO_DIS;
6303 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6304
6305 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6306 } else {
6307 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6308 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6309 }
6310
bd508178
AD		 6311 switch (hw->mac.type) {
6312 case ixgbe_mac_82598EB:
dd4d8ca6 6313 pci_wake_from_d3(pdev, false);
bd508178
AD		 6314 break;
6315 case ixgbe_mac_82599EB:
b93a2226 6316 case ixgbe_mac_X540:
9a75a1ac
DS		 6317 case ixgbe_mac_X550:
6318 case ixgbe_mac_X550EM_x:
49425dfc 6319 case ixgbe_mac_x550em_a:
bd508178
AD		 6320 pci_wake_from_d3(pdev, !!wufc);
6321 break;
6322 default:
6323 break;
6324 }
b3c8b4ba 6325
9d8d05ae 6326 *enable_wake = !!wufc;
961fac88
DS		 6327 if (hw->phy.ops.set_phy_power && !*enable_wake)
6328 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6329
b3c8b4ba
AD		 6330 ixgbe_release_hw_control(adapter);
6331
41c62843
MR		 6332 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6333 pci_disable_device(pdev);
b3c8b4ba 6334
9d8d05ae
RW		 6335 return 0;
6336}
6337
6338#ifdef CONFIG_PM
6339static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6340{
6341 int retval;
6342 bool wake;
6343
6344 retval = __ixgbe_shutdown(pdev, &wake);
6345 if (retval)
6346 return retval;
6347
6348 if (wake) {
6349 pci_prepare_to_sleep(pdev);
6350 } else {
6351 pci_wake_from_d3(pdev, false);
6352 pci_set_power_state(pdev, PCI_D3hot);
6353 }
b3c8b4ba
AD		 6354
6355 return 0;
6356}
9d8d05ae 6357#endif /* CONFIG_PM */
b3c8b4ba
AD		 6358
6359static void ixgbe_shutdown(struct pci_dev *pdev)
6360{
9d8d05ae
RW		 6361 bool wake;
6362
6363 __ixgbe_shutdown(pdev, &wake);
6364
6365 if (system_state == SYSTEM_POWER_OFF) {
6366 pci_wake_from_d3(pdev, wake);
6367 pci_set_power_state(pdev, PCI_D3hot);
6368 }
b3c8b4ba
AD		 6369}
6370
9a799d71
AK		 6371/**
6372 * ixgbe_update_stats - Update the board statistics counters.
6373 * @adapter: board private structure
6374 **/
6375void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6376{
2d86f139 6377 struct net_device *netdev = adapter->netdev;
9a799d71 6378 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6379 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6380 u64 total_mpc = 0;
6381 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6382 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6383 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6384 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6385
d08935c2
DS		 6386 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6387 test_bit(__IXGBE_RESETTING, &adapter->state))
6388 return;
6389
94b982b2 6390 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6391 u64 rsc_count = 0;
94b982b2 6392 u64 rsc_flush = 0;
94b982b2 6393 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6394 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6395 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6396 }
6397 adapter->rsc_total_count = rsc_count;
6398 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6399 }
6400
5b7da515
AD		 6401 for (i = 0; i < adapter->num_rx_queues; i++) {
6402 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6403 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6404 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6405 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6406 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6407 bytes += rx_ring->stats.bytes;
6408 packets += rx_ring->stats.packets;
6409 }
6410 adapter->non_eop_descs = non_eop_descs;
6411 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6412 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6413 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6414 netdev->stats.rx_bytes = bytes;
6415 netdev->stats.rx_packets = packets;
6416
6417 bytes = 0;
6418 packets = 0;
7ca3bc58 6419 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6420 for (i = 0; i < adapter->num_tx_queues; i++) {
6421 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6422 restart_queue += tx_ring->tx_stats.restart_queue;
6423 tx_busy += tx_ring->tx_stats.tx_busy;
6424 bytes += tx_ring->stats.bytes;
6425 packets += tx_ring->stats.packets;
6426 }
eb985f09 6427 adapter->restart_queue = restart_queue;
5b7da515
AD		 6428 adapter->tx_busy = tx_busy;
6429 netdev->stats.tx_bytes = bytes;
6430 netdev->stats.tx_packets = packets;
7ca3bc58 6431
7ca647bd 6432 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6433
6434 /* 8 register reads */
6f11eef7
AV		 6435 for (i = 0; i < 8; i++) {
6436 /* for packet buffers not used, the register should read 0 */
6437 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6438 missed_rx += mpc;
7ca647bd
JP		 6439 hwstats->mpc[i] += mpc;
6440 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6441 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6442 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6443 switch (hw->mac.type) {
6444 case ixgbe_mac_82598EB:
1a70db4b
ET		 6445 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6446 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6447 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6448 hwstats->pxonrxc[i] +=
6449 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6450 break;
6451 case ixgbe_mac_82599EB:
b93a2226 6452 case ixgbe_mac_X540:
9a75a1ac
DS		 6453 case ixgbe_mac_X550:
6454 case ixgbe_mac_X550EM_x:
49425dfc 6455 case ixgbe_mac_x550em_a:
bd508178
AD		 6456 hwstats->pxonrxc[i] +=
6457 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6458 break;
6459 default:
6460 break;
e8e26350 6461 }
6f11eef7 6462 }
1a70db4b
ET		 6463
6464 /*16 register reads */
6465 for (i = 0; i < 16; i++) {
6466 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6467 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6468 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6469 (hw->mac.type == ixgbe_mac_X540) ||
6470 (hw->mac.type == ixgbe_mac_X550) ||
49425dfc
MR		 6471 (hw->mac.type == ixgbe_mac_X550EM_x) ||
6472 (hw->mac.type == ixgbe_mac_x550em_a)) {
1a70db4b
ET		 6473 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6474 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6475 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6476 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6477 }
6478 }
6479
7ca647bd 6480 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6481 /* work around hardware counting issue */
7ca647bd 6482 hwstats->gprc -= missed_rx;
6f11eef7 6483
c84d324c
JF		 6484 ixgbe_update_xoff_received(adapter);
6485
6f11eef7 6486 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6487 switch (hw->mac.type) {
6488 case ixgbe_mac_82598EB:
6489 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6490 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6491 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6492 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6493 break;
b93a2226 6494 case ixgbe_mac_X540:
9a75a1ac
DS		 6495 case ixgbe_mac_X550:
6496 case ixgbe_mac_X550EM_x:
49425dfc 6497 case ixgbe_mac_x550em_a:
9a75a1ac 6498 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6499 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6500 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6501 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6502 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6503 case ixgbe_mac_82599EB:
a4d4f629
AD		 6504 for (i = 0; i < 16; i++)
6505 adapter->hw_rx_no_dma_resources +=
6506 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6507 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6508 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6509 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6510 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6511 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6512 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6513 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6514 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6515 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6516#ifdef IXGBE_FCOE
7ca647bd
JP		 6517 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6518 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6519 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6520 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6521 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6522 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6523 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6524 if (adapter->fcoe.ddp_pool) {
6525 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6526 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6527 unsigned int cpu;
6528 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6529 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6530 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6531 noddp += ddp_pool->noddp;
6532 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6533 }
5a1ee270
AD		 6534 hwstats->fcoe_noddp = noddp;
6535 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6536 }
6d45522c 6537#endif /* IXGBE_FCOE */
bd508178
AD		 6538 break;
6539 default:
6540 break;
e8e26350 6541 }
9a799d71 6542 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6543 hwstats->bprc += bprc;
6544 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6545 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6546 hwstats->mprc -= bprc;
6547 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6548 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6549 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6550 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6551 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6552 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6553 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6554 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6555 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6556 hwstats->lxontxc += lxon;
6f11eef7 6557 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6558 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6559 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6560 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6561 /*
6562 * 82598 errata - tx of flow control packets is included in tx counters
6563 */
6564 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6565 hwstats->gptc -= xon_off_tot;
6566 hwstats->mptc -= xon_off_tot;
6567 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6568 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6569 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6570 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6571 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6572 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6573 hwstats->ptc64 -= xon_off_tot;
6574 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6575 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6576 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6577 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6578 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6579 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6580
6581 /* Fill out the OS statistics structure */
7ca647bd 6582 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6583
6584 /* Rx Errors */
7ca647bd 6585 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6586 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6587 netdev->stats.rx_length_errors = hwstats->rlec;
6588 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6589 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6590}
6591
6592/**
d034acf1 6593 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6594 * @adapter: pointer to the device adapter structure
9a799d71 6595 **/
d034acf1 6596static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6597{
cf8280ee 6598 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6599 int i;
cf8280ee 6600
d034acf1
AD		 6601 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6602 return;
6603
6604 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6605
d034acf1 6606 /* if interface is down do nothing */
fe49f04a 6607 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6608 return;
6609
6610 /* do nothing if we are not using signature filters */
6611 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6612 return;
6613
6614 adapter->fdir_overflow++;
6615
93c52dd0
AD		 6616 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6617 for (i = 0; i < adapter->num_tx_queues; i++)
6618 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6619 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6620 /* re-enable flow director interrupts */
6621 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6622 } else {
6623 e_err(probe, "failed to finish FDIR re-initialization, "
6624 "ignored adding FDIR ATR filters\n");
6625 }
93c52dd0
AD		 6626}
6627
6628/**
6629 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6630 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6631 *
6632 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6633 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6634 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6635 * determine if a hang has occurred.
93c52dd0
AD		 6636 */
6637static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6638{
cf8280ee 6639 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6640 u64 eics = 0;
6641 int i;
cf8280ee 6642
09f40aed 6643 /* If we're down, removing or resetting, just bail */
93c52dd0 6644 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6645 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6646 test_bit(__IXGBE_RESETTING, &adapter->state))
6647 return;
22d5a71b 6648
93c52dd0
AD		 6649 /* Force detection of hung controller */
6650 if (netif_carrier_ok(adapter->netdev)) {
6651 for (i = 0; i < adapter->num_tx_queues; i++)
6652 set_check_for_tx_hang(adapter->tx_ring[i]);
6653 }
22d5a71b 6654
fe49f04a
AD		 6655 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6656 /*
6657 * for legacy and MSI interrupts don't set any bits
6658 * that are enabled for EIAM, because this operation
6659 * would set *both* EIMS and EICS for any bit in EIAM
6660 */
6661 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6662 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6663 } else {
6664 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6665 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6666 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6667 if (qv->rx.ring || qv->tx.ring)
b4f47a48 6668 eics |= BIT_ULL(i);
93c52dd0 6669 }
cf8280ee 6670 }
9a799d71 6671
93c52dd0 6672 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6673 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6674}
6675
e8e26350 6676/**
93c52dd0 6677 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6678 * @adapter: pointer to the device adapter structure
6679 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6680 **/
93c52dd0 6681static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6682{
e8e26350 6683 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6684 u32 link_speed = adapter->link_speed;
6685 bool link_up = adapter->link_up;
041441d0 6686 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6687
93c52dd0
AD		 6688 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6689 return;
6690
6691 if (hw->mac.ops.check_link) {
6692 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6693 } else {
93c52dd0
AD		 6694 /* always assume link is up, if no check link function */
6695 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6696 link_up = true;
c4cf55e5 6697 }
041441d0
AD		 6698
6699 if (adapter->ixgbe_ieee_pfc)
6700 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6701
3ebe8fde 6702 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6703 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6704 ixgbe_set_rx_drop_en(adapter);
6705 }
93c52dd0
AD		 6706
6707 if (link_up ||
6708 time_after(jiffies, (adapter->link_check_timeout +
6709 IXGBE_TRY_LINK_TIMEOUT))) {
6710 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6711 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6712 IXGBE_WRITE_FLUSH(hw);
6713 }
6714
6715 adapter->link_up = link_up;
6716 adapter->link_speed = link_speed;
e8e26350
PW		 6717}
6718
107d3018
AD		 6719static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6720{
6721#ifdef CONFIG_IXGBE_DCB
6722 struct net_device *netdev = adapter->netdev;
6723 struct dcb_app app = {
6724 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6725 .protocol = 0,
6726 };
6727 u8 up = 0;
6728
6729 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6730 up = dcb_ieee_getapp_mask(netdev, &app);
6731
6732 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6733#endif
6734}
6735
1cd127fc
DA		 6736static int ixgbe_enable_macvlan(struct net_device *upper, void *data)
6737{
6738 if (netif_is_macvlan(upper)) {
6739 struct macvlan_dev *vlan = netdev_priv(upper);
6740
6741 if (vlan->fwd_priv)
6742 netif_tx_wake_all_queues(upper);
6743 }
6744
6745 return 0;
6746}
6747
e8e26350 6748/**
93c52dd0
AD		 6749 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6750 * print link up message
49ce9c2c 6751 * @adapter: pointer to the device adapter structure
e8e26350 6752 **/
93c52dd0 6753static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6754{
93c52dd0 6755 struct net_device *netdev = adapter->netdev;
e8e26350 6756 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0 6757 u32 link_speed = adapter->link_speed;
454adb00 6758 const char *speed_str;
93c52dd0 6759 bool flow_rx, flow_tx;
e8e26350 6760
93c52dd0
AD		 6761 /* only continue if link was previously down */
6762 if (netif_carrier_ok(netdev))
a985b6c3 6763 return;
63d6e1d8 6764
93c52dd0 6765 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6766
93c52dd0
AD		 6767 switch (hw->mac.type) {
6768 case ixgbe_mac_82598EB: {
6769 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6770 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6771 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6772 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6773 }
6774 break;
6775 case ixgbe_mac_X540:
9a75a1ac
DS		 6776 case ixgbe_mac_X550:
6777 case ixgbe_mac_X550EM_x:
49425dfc 6778 case ixgbe_mac_x550em_a:
93c52dd0
AD		 6779 case ixgbe_mac_82599EB: {
6780 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6781 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6782 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6783 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6784 }
6785 break;
6786 default:
6787 flow_tx = false;
6788 flow_rx = false;
6789 break;
e8e26350 6790 }
3a6a4eda 6791
6cb562d6
JK		 6792 adapter->last_rx_ptp_check = jiffies;
6793
8fecf67c 6794 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6795 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6796
454adb00
MR		 6797 switch (link_speed) {
6798 case IXGBE_LINK_SPEED_10GB_FULL:
6799 speed_str = "10 Gbps";
6800 break;
6801 case IXGBE_LINK_SPEED_2_5GB_FULL:
6802 speed_str = "2.5 Gbps";
6803 break;
6804 case IXGBE_LINK_SPEED_1GB_FULL:
6805 speed_str = "1 Gbps";
6806 break;
6807 case IXGBE_LINK_SPEED_100_FULL:
6808 speed_str = "100 Mbps";
6809 break;
6810 default:
6811 speed_str = "unknown speed";
6812 break;
6813 }
6814 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6815 ((flow_rx && flow_tx) ? "RX/TX" :
6816 (flow_rx ? "RX" :
6817 (flow_tx ? "TX" : "None"))));
e8e26350 6818
93c52dd0 6819 netif_carrier_on(netdev);
93c52dd0 6820 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6821
cdc04dcc
ET		 6822 /* enable transmits */
6823 netif_tx_wake_all_queues(adapter->netdev);
6824
6825 /* enable any upper devices */
6826 rtnl_lock();
1cd127fc
DA		 6827 netdev_walk_all_upper_dev_rcu(adapter->netdev,
6828 ixgbe_enable_macvlan, NULL);
cdc04dcc
ET		 6829 rtnl_unlock();
6830
107d3018
AD		 6831 /* update the default user priority for VFs */
6832 ixgbe_update_default_up(adapter);
6833
befa2af7
AD		 6834 /* ping all the active vfs to let them know link has changed */
6835 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6836}
6837
c4cf55e5 6838/**
93c52dd0
AD		 6839 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6840 * print link down message
49ce9c2c 6841 * @adapter: pointer to the adapter structure
c4cf55e5 6842 **/
581330ba 6843static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6844{
cf8280ee 6845 struct net_device *netdev = adapter->netdev;
c4cf55e5 6846 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6847
93c52dd0
AD		 6848 adapter->link_up = false;
6849 adapter->link_speed = 0;
cf8280ee 6850
93c52dd0
AD		 6851 /* only continue if link was up previously */
6852 if (!netif_carrier_ok(netdev))
6853 return;
264857b8 6854
93c52dd0
AD		 6855 /* poll for SFP+ cable when link is down */
6856 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6857 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6858
8fecf67c 6859 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6860 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6861
93c52dd0
AD		 6862 e_info(drv, "NIC Link is Down\n");
6863 netif_carrier_off(netdev);
befa2af7
AD		 6864
6865 /* ping all the active vfs to let them know link has changed */
6866 ixgbe_ping_all_vfs(adapter);
93c52dd0 6867}
e8e26350 6868
07923c17
ET		 6869static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6870{
6871 int i;
6872
6873 for (i = 0; i < adapter->num_tx_queues; i++) {
6874 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6875
6876 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6877 return true;
6878 }
6879
6880 return false;
6881}
6882
6883static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6884{
6885 struct ixgbe_hw *hw = &adapter->hw;
6886 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6887 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6888
6889 int i, j;
6890
6891 if (!adapter->num_vfs)
6892 return false;
6893
9a75a1ac
DS		 6894 /* resetting the PF is only needed for MAC before X550 */
6895 if (hw->mac.type >= ixgbe_mac_X550)
6896 return false;
6897
07923c17
ET		 6898 for (i = 0; i < adapter->num_vfs; i++) {
6899 for (j = 0; j < q_per_pool; j++) {
6900 u32 h, t;
6901
6902 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6903 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6904
6905 if (h != t)
6906 return true;
6907 }
6908 }
6909
6910 return false;
6911}
6912
93c52dd0
AD		 6913/**
6914 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6915 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6916 **/
6917static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6918{
93c52dd0 6919 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6920 if (ixgbe_ring_tx_pending(adapter) ||
6921 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6922 /* We've lost link, so the controller stops DMA,
6923 * but we've got queued Tx work that's never going
6924 * to get done, so reset controller to flush Tx.
6925 * (Do the reset outside of interrupt context).
6926 */
12ff3f3b 6927 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
57ca2a4f 6928 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
bc59fcda 6929 }
c4cf55e5 6930 }
c4cf55e5
PWJ		 6931}
6932
9079e416
ET		 6933#ifdef CONFIG_PCI_IOV
6934static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6935 struct pci_dev *vfdev)
6936{
6937 if (!pci_wait_for_pending_transaction(vfdev))
6938 e_dev_warn("Issuing VFLR with pending transactions\n");
6939
6940 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6941 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6942
6943 msleep(100);
6944}
6945
6946static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6947{
6948 struct ixgbe_hw *hw = &adapter->hw;
6949 struct pci_dev *pdev = adapter->pdev;
988d1307 6950 unsigned int vf;
9079e416 6951 u32 gpc;
9079e416
ET		 6952
6953 if (!(netif_carrier_ok(adapter->netdev)))
6954 return;
6955
6956 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6957 if (gpc) /* If incrementing then no need for the check below */
6958 return;
6959 /* Check to see if a bad DMA write target from an errant or
6960 * malicious VF has caused a PCIe error. If so then we can
6961 * issue a VFLR to the offending VF(s) and then resume without
6962 * requesting a full slot reset.
6963 */
6964
6965 if (!pdev)
6966 return;
6967
9079e416 6968 /* check status reg for all VFs owned by this PF */
988d1307
MR		 6969 for (vf = 0; vf < adapter->num_vfs; ++vf) {
6970 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
6971 u16 status_reg;
9079e416 6972
988d1307
MR		 6973 if (!vfdev)
6974 continue;
6975 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6976 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
6977 status_reg & PCI_STATUS_REC_MASTER_ABORT)
6978 ixgbe_issue_vf_flr(adapter, vfdev);
9079e416
ET		 6979 }
6980}
6981
a985b6c3
GR		 6982static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6983{
6984 u32 ssvpc;
6985
0584d999
GR		 6986 /* Do not perform spoof check for 82598 or if not in IOV mode */
6987 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6988 adapter->num_vfs == 0)
a985b6c3
GR		 6989 return;
6990
6991 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6992
6993 /*
6994 * ssvpc register is cleared on read, if zero then no
6995 * spoofed packets in the last interval.
6996 */
6997 if (!ssvpc)
6998 return;
6999
d6ea0754 7000 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 7001}
9079e416
ET		 7002#else
7003static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7004{
7005}
7006
7007static void
7008ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7009{
7010}
7011#endif /* CONFIG_PCI_IOV */
7012
a985b6c3 7013
93c52dd0
AD		 7014/**
7015 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 7016 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 7017 **/
7018static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7019{
09f40aed 7020 /* if interface is down, removing or resetting, do nothing */
7edebf9a 7021 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7022 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 7023 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 7024 return;
7025
7026 ixgbe_watchdog_update_link(adapter);
7027
7028 if (adapter->link_up)
7029 ixgbe_watchdog_link_is_up(adapter);
7030 else
7031 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 7032
9079e416 7033 ixgbe_check_for_bad_vf(adapter);
a985b6c3 7034 ixgbe_spoof_check(adapter);
9a799d71 7035 ixgbe_update_stats(adapter);
93c52dd0
AD		 7036
7037 ixgbe_watchdog_flush_tx(adapter);
9a799d71 7038}
10eec955 7039
cf8280ee 7040/**
7086400d 7041 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 7042 * @adapter: the ixgbe adapter structure
cf8280ee 7043 **/
7086400d 7044static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 7045{
cf8280ee 7046 struct ixgbe_hw *hw = &adapter->hw;
7086400d 7047 s32 err;
cf8280ee 7048
7086400d
AD		 7049 /* not searching for SFP so there is nothing to do here */
7050 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7051 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7052 return;
10eec955 7053
58e7cd24
MR		 7054 if (adapter->sfp_poll_time &&
7055 time_after(adapter->sfp_poll_time, jiffies))
7056 return; /* If not yet time to poll for SFP */
7057
7086400d
AD		 7058 /* someone else is in init, wait until next service event */
7059 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7060 return;
cf8280ee 7061
58e7cd24
MR		 7062 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7063
7086400d
AD		 7064 err = hw->phy.ops.identify_sfp(hw);
7065 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7066 goto sfp_out;
264857b8 7067
7086400d
AD		 7068 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7069 /* If no cable is present, then we need to reset
7070 * the next time we find a good cable. */
7071 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 7072 }
9a799d71 7073
7086400d
AD		 7074 /* exit on error */
7075 if (err)
7076 goto sfp_out;
e8e26350 7077
7086400d
AD		 7078 /* exit if reset not needed */
7079 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7080 goto sfp_out;
9a799d71 7081
7086400d 7082 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 7083
7086400d
AD		 7084 /*
7085 * A module may be identified correctly, but the EEPROM may not have
7086 * support for that module. setup_sfp() will fail in that case, so
7087 * we should not allow that module to load.
7088 */
7089 if (hw->mac.type == ixgbe_mac_82598EB)
7090 err = hw->phy.ops.reset(hw);
7091 else
7092 err = hw->mac.ops.setup_sfp(hw);
7093
7094 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7095 goto sfp_out;
7096
7097 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7098 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7099
7100sfp_out:
7101 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7102
7103 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7104 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7105 e_dev_err("failed to initialize because an unsupported "
7106 "SFP+ module type was detected.\n");
7107 e_dev_err("Reload the driver after installing a "
7108 "supported module.\n");
7109 unregister_netdev(adapter->netdev);
bc59fcda 7110 }
7086400d 7111}
bc59fcda 7112
7086400d
AD		 7113/**
7114 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 7115 * @adapter: the ixgbe adapter structure
7086400d
AD		 7116 **/
7117static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7118{
7119 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 7120 u32 speed;
7121 bool autoneg = false;
7086400d
AD		 7122
7123 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7124 return;
7125
7126 /* someone else is in init, wait until next service event */
7127 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7128 return;
7129
7130 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7131
3d292265 7132 speed = hw->phy.autoneg_advertised;
ed33ff66 7133 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 7134 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 7135
7136 /* setup the highest link when no autoneg */
7137 if (!autoneg) {
7138 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7139 speed = IXGBE_LINK_SPEED_10GB_FULL;
7140 }
7141 }
7142
7086400d 7143 if (hw->mac.ops.setup_link)
fd0326f2 7144 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 7145
7146 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7147 adapter->link_check_timeout = jiffies;
7148 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7149}
7150
7151/**
7152 * ixgbe_service_timer - Timer Call-back
7153 * @data: pointer to adapter cast into an unsigned long
7154 **/
7155static void ixgbe_service_timer(unsigned long data)
7156{
7157 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7158 unsigned long next_event_offset;
7159
6bb78cfb
AD		 7160 /* poll faster when waiting for link */
7161 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7162 next_event_offset = HZ / 10;
7163 else
7164 next_event_offset = HZ * 2;
83c61fa9 7165
7086400d
AD		 7166 /* Reset the timer */
7167 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7168
9079e416 7169 ixgbe_service_event_schedule(adapter);
7086400d
AD		 7170}
7171
597f22d6
DS		 7172static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7173{
7174 struct ixgbe_hw *hw = &adapter->hw;
7175 u32 status;
7176
7177 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7178 return;
7179
7180 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7181
7182 if (!hw->phy.ops.handle_lasi)
7183 return;
7184
7185 status = hw->phy.ops.handle_lasi(&adapter->hw);
7186 if (status != IXGBE_ERR_OVERTEMP)
7187 return;
7188
7189 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7190}
7191
c83c6cbd
AD		 7192static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7193{
57ca2a4f 7194 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
c83c6cbd
AD		 7195 return;
7196
09f40aed 7197 /* If we're already down, removing or resetting, just bail */
c83c6cbd 7198 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7199 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 7200 test_bit(__IXGBE_RESETTING, &adapter->state))
7201 return;
7202
7203 ixgbe_dump(adapter);
7204 netdev_err(adapter->netdev, "Reset adapter\n");
7205 adapter->tx_timeout_count++;
7206
8f4c5c9f 7207 rtnl_lock();
c83c6cbd 7208 ixgbe_reinit_locked(adapter);
8f4c5c9f 7209 rtnl_unlock();
c83c6cbd
AD		 7210}
7211
7086400d
AD		 7212/**
7213 * ixgbe_service_task - manages and runs subtasks
7214 * @work: pointer to work_struct containing our data
7215 **/
7216static void ixgbe_service_task(struct work_struct *work)
7217{
7218 struct ixgbe_adapter *adapter = container_of(work,
7219 struct ixgbe_adapter,
7220 service_task);
b0483c8f
MR		 7221 if (ixgbe_removed(adapter->hw.hw_addr)) {
7222 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7223 rtnl_lock();
7224 ixgbe_down(adapter);
7225 rtnl_unlock();
7226 }
7227 ixgbe_service_event_complete(adapter);
7228 return;
7229 }
a21d0822 7230 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) {
b3a49557 7231 rtnl_lock();
a21d0822 7232 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
b3a49557
AD		 7233 udp_tunnel_get_rx_info(adapter->netdev);
7234 rtnl_unlock();
67359c3c 7235 }
c83c6cbd 7236 ixgbe_reset_subtask(adapter);
597f22d6 7237 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 7238 ixgbe_sfp_detection_subtask(adapter);
7239 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 7240 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 7241 ixgbe_watchdog_subtask(adapter);
d034acf1 7242 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 7243 ixgbe_check_hang_subtask(adapter);
891dc082 7244
8fecf67c 7245 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 7246 ixgbe_ptp_overflow_check(adapter);
7247 ixgbe_ptp_rx_hang(adapter);
7248 }
7086400d
AD		 7249
7250 ixgbe_service_event_complete(adapter);
9a799d71
AK		 7251}
7252
fd0db0ed
AD		 7253static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7254 struct ixgbe_tx_buffer *first,
244e27ad 7255 u8 *hdr_len)
897ab156 7256{
b83e3010 7257 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
fd0db0ed 7258 struct sk_buff *skb = first->skb;
b83e3010
AD		 7259 union {
7260 struct iphdr *v4;
7261 struct ipv6hdr *v6;
7262 unsigned char *hdr;
7263 } ip;
7264 union {
7265 struct tcphdr *tcp;
7266 unsigned char *hdr;
7267 } l4;
7268 u32 paylen, l4_offset;
2049e1f6 7269 int err;
9a799d71 7270
8f4fbb9b
AD		 7271 if (skb->ip_summed != CHECKSUM_PARTIAL)
7272 return 0;
7273
897ab156
AD		 7274 if (!skb_is_gso(skb))
7275 return 0;
9a799d71 7276
2049e1f6
FR		 7277 err = skb_cow_head(skb, 0);
7278 if (err < 0)
7279 return err;
9a799d71 7280
b83e3010
AD		 7281 ip.hdr = skb_network_header(skb);
7282 l4.hdr = skb_checksum_start(skb);
7283
897ab156
AD		 7284 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7285 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7286
b83e3010
AD		 7287 /* initialize outer IP header fields */
7288 if (ip.v4->version == 4) {
7289 /* IP header will have to cancel out any data that
7290 * is not a part of the outer IP header
7291 */
7292 ip.v4->check = csum_fold(csum_add(lco_csum(skb),
7293 csum_unfold(l4.tcp->check)));
897ab156 7294 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
b83e3010
AD		 7295
7296 ip.v4->tot_len = 0;
244e27ad
AD		 7297 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7298 IXGBE_TX_FLAGS_CSUM |
7299 IXGBE_TX_FLAGS_IPV4;
b83e3010
AD		 7300 } else {
7301 ip.v6->payload_len = 0;
244e27ad
AD		 7302 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7303 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 7304 }
7305
b83e3010
AD		 7306 /* determine offset of inner transport header */
7307 l4_offset = l4.hdr - skb->data;
7308
7309 /* compute length of segmentation header */
7310 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
7311
7312 /* remove payload length from inner checksum */
7313 paylen = skb->len - l4_offset;
7314 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
897ab156 7315
091a6246
AD		 7316 /* update gso size and bytecount with header size */
7317 first->gso_segs = skb_shinfo(skb)->gso_segs;
7318 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7319
c44f5f51 7320 /* mss_l4len_id: use 0 as index for TSO */
b83e3010 7321 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
897ab156 7322 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 7323
7324 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
b83e3010
AD		 7325 vlan_macip_lens = l4.hdr - ip.hdr;
7326 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7327 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 7328
7329 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 7330 mss_l4len_idx);
897ab156
AD		 7331
7332 return 1;
7333}
7334
49763de0
AD		 7335static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
7336{
7337 unsigned int offset = 0;
7338
7339 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
7340
7341 return offset == skb_checksum_start_offset(skb);
7342}
7343
244e27ad
AD		 7344static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7345 struct ixgbe_tx_buffer *first)
7ca647bd 7346{
fd0db0ed 7347 struct sk_buff *skb = first->skb;
897ab156 7348 u32 vlan_macip_lens = 0;
897ab156 7349 u32 type_tucmd = 0;
7ca647bd 7350
897ab156 7351 if (skb->ip_summed != CHECKSUM_PARTIAL) {
49763de0
AD		 7352csum_failed:
7353 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
7354 IXGBE_TX_FLAGS_CC)))
472148c3 7355 return;
49763de0
AD		 7356 goto no_csum;
7357 }
897ab156 7358
49763de0
AD		 7359 switch (skb->csum_offset) {
7360 case offsetof(struct tcphdr, check):
7361 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7362 /* fall through */
7363 case offsetof(struct udphdr, check):
7364 break;
7365 case offsetof(struct sctphdr, checksum):
7366 /* validate that this is actually an SCTP request */
7367 if (((first->protocol == htons(ETH_P_IP)) &&
7368 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
7369 ((first->protocol == htons(ETH_P_IPV6)) &&
7370 ixgbe_ipv6_csum_is_sctp(skb))) {
7371 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
897ab156 7372 break;
7ca647bd 7373 }
49763de0
AD		 7374 /* fall through */
7375 default:
7376 skb_checksum_help(skb);
7377 goto csum_failed;
7ca647bd
JP		 7378 }
7379
49763de0
AD		 7380 /* update TX checksum flag */
7381 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7382 vlan_macip_lens = skb_checksum_start_offset(skb) -
7383 skb_network_offset(skb);
36a92d71 7384no_csum:
244e27ad 7385 /* vlan_macip_lens: MACLEN, VLAN tag */
49763de0 7386 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7387 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7388
49763de0 7389 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0);
9a799d71
AK		 7390}
7391
472148c3
AD		 7392#define IXGBE_SET_FLAG(_input, _flag, _result) \
7393 ((_flag <= _result) ? \
7394 ((u32)(_input & _flag) * (_result / _flag)) : \
7395 ((u32)(_input & _flag) / (_flag / _result)))
7396
7397static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7398{
d3d00239 7399 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7400 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7401 IXGBE_ADVTXD_DCMD_DEXT |
7402 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7403
d3d00239 7404 /* set HW vlan bit if vlan is present */
472148c3
AD		 7405 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7406 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7407
d3d00239 7408 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7409 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7410 IXGBE_ADVTXD_DCMD_TSE);
7411
7412 /* set timestamp bit if present */
7413 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7414 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7415
62748b7b 7416 /* insert frame checksum */
472148c3 7417 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7418
d3d00239
AD		 7419 return cmd_type;
7420}
9a799d71 7421
729739b7
AD		 7422static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7423 u32 tx_flags, unsigned int paylen)
d3d00239 7424{
472148c3 7425 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7426
d3d00239 7427 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7428 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7429 IXGBE_TX_FLAGS_CSUM,
7430 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7431
93f5b3c1 7432 /* enble IPv4 checksum for TSO */
472148c3
AD		 7433 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7434 IXGBE_TX_FLAGS_IPV4,
7435 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7436
7f9643fd
AD		 7437 /*
7438 * Check Context must be set if Tx switch is enabled, which it
7439 * always is for case where virtual functions are running
7440 */
472148c3
AD		 7441 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7442 IXGBE_TX_FLAGS_CC,
7443 IXGBE_ADVTXD_CC);
7f9643fd 7444
472148c3 7445 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7446}
44df32c5 7447
2367a173
DB		 7448static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7449{
7450 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7451
7452 /* Herbert's original patch had:
7453 * smp_mb__after_netif_stop_queue();
7454 * but since that doesn't exist yet, just open code it.
7455 */
7456 smp_mb();
7457
7458 /* We need to check again in a case another CPU has just
7459 * made room available.
7460 */
7461 if (likely(ixgbe_desc_unused(tx_ring) < size))
7462 return -EBUSY;
7463
7464 /* A reprieve! - use start_queue because it doesn't call schedule */
7465 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7466 ++tx_ring->tx_stats.restart_queue;
7467 return 0;
7468}
7469
7470static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7471{
7472 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7473 return 0;
7474
7475 return __ixgbe_maybe_stop_tx(tx_ring, size);
7476}
7477
d3d00239
AD		 7478#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7479 IXGBE_TXD_CMD_RS)
7480
7481static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7482 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7483 const u8 hdr_len)
7484{
fd0db0ed 7485 struct sk_buff *skb = first->skb;
729739b7 7486 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7487 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7488 struct skb_frag_struct *frag;
7489 dma_addr_t dma;
7490 unsigned int data_len, size;
244e27ad 7491 u32 tx_flags = first->tx_flags;
472148c3 7492 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7493 u16 i = tx_ring->next_to_use;
d3d00239 7494
729739b7
AD		 7495 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7496
ec718254
AD		 7497 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7498
7499 size = skb_headlen(skb);
7500 data_len = skb->data_len;
729739b7 7501
d3d00239
AD		 7502#ifdef IXGBE_FCOE
7503 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7504 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7505 size -= sizeof(struct fcoe_crc_eof) - data_len;
7506 data_len = 0;
729739b7
AD		 7507 } else {
7508 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7509 }
7510 }
44df32c5 7511
d3d00239 7512#endif
729739b7 7513 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7514
ec718254 7515 tx_buffer = first;
9a799d71 7516
ec718254
AD		 7517 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7518 if (dma_mapping_error(tx_ring->dev, dma))
7519 goto dma_error;
7520
7521 /* record length, and DMA address */
7522 dma_unmap_len_set(tx_buffer, len, size);
7523 dma_unmap_addr_set(tx_buffer, dma, dma);
7524
7525 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7526
729739b7 7527 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7528 tx_desc->read.cmd_type_len =
472148c3 7529 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7530
d3d00239 7531 i++;
729739b7 7532 tx_desc++;
d3d00239 7533 if (i == tx_ring->count) {
e4f74028 7534 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7535 i = 0;
7536 }
ec718254 7537 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7538
7539 dma += IXGBE_MAX_DATA_PER_TXD;
7540 size -= IXGBE_MAX_DATA_PER_TXD;
7541
7542 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7543 }
e5a43549 7544
729739b7
AD		 7545 if (likely(!data_len))
7546 break;
9a799d71 7547
472148c3 7548 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7549
729739b7
AD		 7550 i++;
7551 tx_desc++;
7552 if (i == tx_ring->count) {
7553 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7554 i = 0;
7555 }
ec718254 7556 tx_desc->read.olinfo_status = 0;
9a799d71 7557
d3d00239 7558#ifdef IXGBE_FCOE
9e903e08 7559 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7560#else
9e903e08 7561 size = skb_frag_size(frag);
d3d00239
AD		 7562#endif
7563 data_len -= size;
9a799d71 7564
729739b7
AD		 7565 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7566 DMA_TO_DEVICE);
9a799d71 7567
729739b7 7568 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7569 }
9a799d71 7570
729739b7 7571 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7572 cmd_type |= size | IXGBE_TXD_CMD;
7573 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7574
091a6246 7575 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7576
d3d00239
AD		 7577 /* set the timestamp */
7578 first->time_stamp = jiffies;
9a799d71
AK		 7579
7580 /*
729739b7
AD		 7581 * Force memory writes to complete before letting h/w know there
7582 * are new descriptors to fetch. (Only applicable for weak-ordered
7583 * memory model archs, such as IA-64).
7584 *
7585 * We also need this memory barrier to make certain all of the
7586 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7587 */
7588 wmb();
7589
d3d00239
AD		 7590 /* set next_to_watch value indicating a packet is present */
7591 first->next_to_watch = tx_desc;
7592
729739b7
AD		 7593 i++;
7594 if (i == tx_ring->count)
7595 i = 0;
7596
7597 tx_ring->next_to_use = i;
7598
2367a173
DB		 7599 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7600
7601 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7602 writel(i, tx_ring->tail);
7603
7604 /* we need this if more than one processor can write to our tail
7605 * at a time, it synchronizes IO on IA64/Altix systems
7606 */
7607 mmiowb();
9c938cdd 7608 }
2367a173 7609
d3d00239
AD		 7610 return;
7611dma_error:
729739b7 7612 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7613
7614 /* clear dma mappings for failed tx_buffer_info map */
7615 for (;;) {
729739b7
AD		 7616 tx_buffer = &tx_ring->tx_buffer_info[i];
7617 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7618 if (tx_buffer == first)
d3d00239
AD		 7619 break;
7620 if (i == 0)
7621 i = tx_ring->count;
7622 i--;
7623 }
7624
d3d00239 7625 tx_ring->next_to_use = i;
9a799d71
AK		 7626}
7627
fd0db0ed 7628static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7629 struct ixgbe_tx_buffer *first)
69830529
AD		 7630{
7631 struct ixgbe_q_vector *q_vector = ring->q_vector;
7632 union ixgbe_atr_hash_dword input = { .dword = 0 };
7633 union ixgbe_atr_hash_dword common = { .dword = 0 };
7634 union {
7635 unsigned char *network;
7636 struct iphdr *ipv4;
7637 struct ipv6hdr *ipv6;
7638 } hdr;
ee9e0f0b 7639 struct tcphdr *th;
e2873d43 7640 unsigned int hlen;
67359c3c 7641 struct sk_buff *skb;
905e4a41 7642 __be16 vlan_id;
e2873d43 7643 int l4_proto;
c4cf55e5 7644
69830529
AD		 7645 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7646 if (!q_vector)
7647 return;
7648
7649 /* do nothing if sampling is disabled */
7650 if (!ring->atr_sample_rate)
d3ead241 7651 return;
c4cf55e5 7652
69830529 7653 ring->atr_count++;
c4cf55e5 7654
e2873d43
AD		 7655 /* currently only IPv4/IPv6 with TCP is supported */
7656 if ((first->protocol != htons(ETH_P_IP)) &&
7657 (first->protocol != htons(ETH_P_IPV6)))
7658 return;
7659
69830529 7660 /* snag network header to get L4 type and address */
67359c3c
MR		 7661 skb = first->skb;
7662 hdr.network = skb_network_header(skb);
9f12df90
AD		 7663 if (skb->encapsulation &&
7664 first->protocol == htons(ETH_P_IP) &&
52028821 7665 hdr.ipv4->protocol == IPPROTO_UDP) {
67359c3c 7666 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7667
9f12df90
AD		 7668 /* verify the port is recognized as VXLAN */
7669 if (adapter->vxlan_port &&
e2873d43 7670 udp_hdr(skb)->dest == adapter->vxlan_port)
9f12df90 7671 hdr.network = skb_inner_network_header(skb);
a21d0822
ET		 7672
7673 if (adapter->geneve_port &&
7674 udp_hdr(skb)->dest == adapter->geneve_port)
7675 hdr.network = skb_inner_network_header(skb);
e19dcdeb
MR		 7676 }
7677
7678 /* Currently only IPv4/IPv6 with TCP is supported */
7679 switch (hdr.ipv4->version) {
7680 case IPVERSION:
e2873d43
AD		 7681 /* access ihl as u8 to avoid unaligned access on ia64 */
7682 hlen = (hdr.network[0] & 0x0F) << 2;
7683 l4_proto = hdr.ipv4->protocol;
e19dcdeb
MR		 7684 break;
7685 case 6:
e2873d43
AD		 7686 hlen = hdr.network - skb->data;
7687 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
7688 hlen -= hdr.network - skb->data;
e19dcdeb
MR		 7689 break;
7690 default:
7691 return;
67359c3c 7692 }
c4cf55e5 7693
e2873d43
AD		 7694 if (l4_proto != IPPROTO_TCP)
7695 return;
7696
7697 th = (struct tcphdr *)(hdr.network + hlen);
7698
7699 /* skip this packet since the socket is closing */
7700 if (th->fin)
69830529
AD		 7701 return;
7702
7703 /* sample on all syn packets or once every atr sample count */
7704 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7705 return;
7706
7707 /* reset sample count */
7708 ring->atr_count = 0;
7709
244e27ad 7710 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7711
7712 /*
7713 * src and dst are inverted, think how the receiver sees them
7714 *
7715 * The input is broken into two sections, a non-compressed section
7716 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7717 * is XORed together and stored in the compressed dword.
7718 */
7719 input.formatted.vlan_id = vlan_id;
7720
7721 /*
7722 * since src port and flex bytes occupy the same word XOR them together
7723 * and write the value to source port portion of compressed dword
7724 */
244e27ad 7725 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7726 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7727 else
244e27ad 7728 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7729 common.port.dst ^= th->source;
7730
e19dcdeb
MR		 7731 switch (hdr.ipv4->version) {
7732 case IPVERSION:
69830529
AD		 7733 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7734 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
e19dcdeb
MR		 7735 break;
7736 case 6:
69830529
AD		 7737 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7738 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7739 hdr.ipv6->saddr.s6_addr32[1] ^
7740 hdr.ipv6->saddr.s6_addr32[2] ^
7741 hdr.ipv6->saddr.s6_addr32[3] ^
7742 hdr.ipv6->daddr.s6_addr32[0] ^
7743 hdr.ipv6->daddr.s6_addr32[1] ^
7744 hdr.ipv6->daddr.s6_addr32[2] ^
7745 hdr.ipv6->daddr.s6_addr32[3];
e19dcdeb
MR		 7746 break;
7747 default:
7748 break;
69830529 7749 }
c4cf55e5 7750
9f12df90 7751 if (hdr.network != skb_network_header(skb))
67359c3c 7752 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
67359c3c 7753
c4cf55e5 7754 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7755 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7756 input, common, ring->queue_index);
c4cf55e5
PWJ		 7757}
7758
f663dd9a 7759static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7760 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7761{
f663dd9a
JW		 7762 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7763#ifdef IXGBE_FCOE
97488bd1
AD		 7764 struct ixgbe_adapter *adapter;
7765 struct ixgbe_ring_feature *f;
7766 int txq;
f663dd9a
JW		 7767#endif
7768
7769 if (fwd_adapter)
7770 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7771
7772#ifdef IXGBE_FCOE
5e09a105 7773
97488bd1
AD		 7774 /*
7775 * only execute the code below if protocol is FCoE
7776 * or FIP and we have FCoE enabled on the adapter
7777 */
7778 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7779 case htons(ETH_P_FCOE):
7780 case htons(ETH_P_FIP):
97488bd1 7781 adapter = netdev_priv(dev);
c087663e 7782
97488bd1
AD		 7783 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7784 break;
7785 default:
99932d4f 7786 return fallback(dev, skb);
97488bd1 7787 }
c087663e 7788
97488bd1 7789 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7790
97488bd1
AD		 7791 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7792 smp_processor_id();
56075a98 7793
97488bd1
AD		 7794 while (txq >= f->indices)
7795 txq -= f->indices;
c4cf55e5 7796
97488bd1 7797 return txq + f->offset;
f663dd9a 7798#else
99932d4f 7799 return fallback(dev, skb);
f663dd9a 7800#endif
09a3b1f8
SH		 7801}
7802
fc77dc3c 7803netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7804 struct ixgbe_adapter *adapter,
7805 struct ixgbe_ring *tx_ring)
9a799d71 7806{
d3d00239 7807 struct ixgbe_tx_buffer *first;
5f715823 7808 int tso;
d3d00239 7809 u32 tx_flags = 0;
a535c30e 7810 unsigned short f;
a535c30e 7811 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7812 __be16 protocol = skb->protocol;
63544e9c 7813 u8 hdr_len = 0;
5e09a105 7814
a535c30e
AD		 7815 /*
7816 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7817 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7818 * + 2 desc gap to keep tail from touching head,
7819 * + 1 desc for context descriptor,
7820 * otherwise try next time
7821 */
a535c30e
AD		 7822 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7823 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7824
a535c30e
AD		 7825 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7826 tx_ring->tx_stats.tx_busy++;
7827 return NETDEV_TX_BUSY;
7828 }
7829
fd0db0ed
AD		 7830 /* record the location of the first descriptor for this packet */
7831 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7832 first->skb = skb;
091a6246
AD		 7833 first->bytecount = skb->len;
7834 first->gso_segs = 1;
fd0db0ed 7835
66f32a8b 7836 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7837 if (skb_vlan_tag_present(skb)) {
7838 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7839 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7840 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7841 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7842 struct vlan_hdr *vhdr, _vhdr;
7843 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7844 if (!vhdr)
7845 goto out_drop;
7846
9e0c5648
AD		 7847 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7848 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7849 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7850 }
0213668f 7851 protocol = vlan_get_protocol(skb);
66f32a8b 7852
d5234933
MR		 7853 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7854 adapter->ptp_clock &&
7855 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7856 &adapter->state)) {
3a6a4eda
JK		 7857 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7858 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7859
7860 /* schedule check for Tx timestamp */
7861 adapter->ptp_tx_skb = skb_get(skb);
7862 adapter->ptp_tx_start = jiffies;
7863 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7864 }
3a6a4eda 7865
ff29a86e
JK		 7866 skb_tx_timestamp(skb);
7867
9e0c5648
AD		 7868#ifdef CONFIG_PCI_IOV
7869 /*
7870 * Use the l2switch_enable flag - would be false if the DMA
7871 * Tx switch had been disabled.
7872 */
7873 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7874 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7875
7876#endif
32701dc2 7877 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7878 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7879 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7880 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7881 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7882 tx_flags |= (skb->priority & 0x7) <<
7883 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7884 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7885 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7886
7887 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7888 goto out_drop;
7889 vhdr = (struct vlan_ethhdr *)skb->data;
7890 vhdr->h_vlan_TCI = htons(tx_flags >>
7891 IXGBE_TX_FLAGS_VLAN_SHIFT);
7892 } else {
7893 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7894 }
9a799d71 7895 }
eacd73f7 7896
244e27ad
AD		 7897 /* record initial flags and protocol */
7898 first->tx_flags = tx_flags;
7899 first->protocol = protocol;
7900
eacd73f7 7901#ifdef IXGBE_FCOE
66f32a8b 7902 /* setup tx offload for FCoE */
a1108ffd 7903 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7904 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7905 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7906 if (tso < 0)
7907 goto out_drop;
9a799d71 7908
66f32a8b 7909 goto xmit_fcoe;
eacd73f7 7910 }
9a799d71 7911
66f32a8b 7912#endif /* IXGBE_FCOE */
244e27ad 7913 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7914 if (tso < 0)
897ab156 7915 goto out_drop;
244e27ad
AD		 7916 else if (!tso)
7917 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7918
7919 /* add the ATR filter if ATR is on */
7920 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7921 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7922
7923#ifdef IXGBE_FCOE
7924xmit_fcoe:
7925#endif /* IXGBE_FCOE */
244e27ad 7926 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7927
9a799d71 7928 return NETDEV_TX_OK;
897ab156
AD		 7929
7930out_drop:
fd0db0ed
AD		 7931 dev_kfree_skb_any(first->skb);
7932 first->skb = NULL;
7933
897ab156 7934 return NETDEV_TX_OK;
9a799d71
AK		 7935}
7936
2a47fa45
JF		 7937static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7938 struct net_device *netdev,
7939 struct ixgbe_ring *ring)
84418e3b
AD		 7940{
7941 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7942 struct ixgbe_ring *tx_ring;
7943
a50c29dd
AD		 7944 /*
7945 * The minimum packet size for olinfo paylen is 17 so pad the skb
7946 * in order to meet this minimum size requirement.
7947 */
a94d9e22
AD		 7948 if (skb_put_padto(skb, 17))
7949 return NETDEV_TX_OK;
a50c29dd 7950
2a47fa45
JF		 7951 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7952
fc77dc3c 7953 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7954}
7955
2a47fa45
JF		 7956static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7957 struct net_device *netdev)
7958{
7959 return __ixgbe_xmit_frame(skb, netdev, NULL);
7960}
7961
9a799d71
AK		 7962/**
7963 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7964 * @netdev: network interface device structure
7965 * @p: pointer to an address structure
7966 *
7967 * Returns 0 on success, negative on failure
7968 **/
7969static int ixgbe_set_mac(struct net_device *netdev, void *p)
7970{
7971 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7972 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7973 struct sockaddr *addr = p;
7974
7975 if (!is_valid_ether_addr(addr->sa_data))
7976 return -EADDRNOTAVAIL;
7977
7978 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7979 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7980
c9f53e63
AD		 7981 ixgbe_mac_set_default_filter(adapter);
7982
7983 return 0;
9a799d71
AK		 7984}
7985
6b73e10d
BH		 7986static int
7987ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7988{
7989 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7990 struct ixgbe_hw *hw = &adapter->hw;
7991 u16 value;
7992 int rc;
7993
7994 if (prtad != hw->phy.mdio.prtad)
7995 return -EINVAL;
7996 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7997 if (!rc)
7998 rc = value;
7999 return rc;
8000}
8001
8002static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8003 u16 addr, u16 value)
8004{
8005 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8006 struct ixgbe_hw *hw = &adapter->hw;
8007
8008 if (prtad != hw->phy.mdio.prtad)
8009 return -EINVAL;
8010 return hw->phy.ops.write_reg(hw, addr, devad, value);
8011}
8012
8013static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8014{
8015 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8016
3a6a4eda 8017 switch (cmd) {
3a6a4eda 8018 case SIOCSHWTSTAMP:
93501d48
JK		 8019 return ixgbe_ptp_set_ts_config(adapter, req);
8020 case SIOCGHWTSTAMP:
8021 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 8022 default:
8023 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8024 }
6b73e10d
BH		 8025}
8026
0365e6e4
PW		 8027/**
8028 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 8029 * netdev->dev_addrs
0365e6e4
PW		 8030 * @netdev: network interface device structure
8031 *
8032 * Returns non-zero on failure
8033 **/
8034static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8035{
8036 int err = 0;
8037 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 8038 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 8039
7fa7c9dc 8040 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 8041 rtnl_lock();
7fa7c9dc 8042 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 8043 rtnl_unlock();
7fa7c9dc
AD		 8044
8045 /* update SAN MAC vmdq pool selection */
8046 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 8047 }
8048 return err;
8049}
8050
8051/**
8052 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 8053 * netdev->dev_addrs
0365e6e4
PW		 8054 * @netdev: network interface device structure
8055 *
8056 * Returns non-zero on failure
8057 **/
8058static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8059{
8060 int err = 0;
8061 struct ixgbe_adapter *adapter = netdev_priv(dev);
8062 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8063
8064 if (is_valid_ether_addr(mac->san_addr)) {
8065 rtnl_lock();
8066 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8067 rtnl_unlock();
8068 }
8069 return err;
8070}
8071
9a799d71
AK		 8072#ifdef CONFIG_NET_POLL_CONTROLLER
8073/*
8074 * Polling 'interrupt' - used by things like netconsole to send skbs
8075 * without having to re-enable interrupts. It's not called while
8076 * the interrupt routine is executing.
8077 */
8078static void ixgbe_netpoll(struct net_device *netdev)
8079{
8080 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 8081 int i;
9a799d71 8082
1a647bd2
AD		 8083 /* if interface is down do nothing */
8084 if (test_bit(__IXGBE_DOWN, &adapter->state))
8085 return;
8086
856f606e
AD		 8087 /* loop through and schedule all active queues */
8088 for (i = 0; i < adapter->num_q_vectors; i++)
8089 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 8090}
9a799d71 8091
581330ba 8092#endif
de1036b1
ED		 8093static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
8094 struct rtnl_link_stats64 *stats)
8095{
8096 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8097 int i;
8098
1a51502b 8099 rcu_read_lock();
de1036b1 8100 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 8101 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 8102 u64 bytes, packets;
8103 unsigned int start;
8104
1a51502b
ED		 8105 if (ring) {
8106 do {
57a7744e 8107 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 8108 packets = ring->stats.packets;
8109 bytes = ring->stats.bytes;
57a7744e 8110 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 8111 stats->rx_packets += packets;
8112 stats->rx_bytes += bytes;
8113 }
de1036b1 8114 }
1ac9ad13
ED		 8115
8116 for (i = 0; i < adapter->num_tx_queues; i++) {
8117 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
8118 u64 bytes, packets;
8119 unsigned int start;
8120
8121 if (ring) {
8122 do {
57a7744e 8123 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 8124 packets = ring->stats.packets;
8125 bytes = ring->stats.bytes;
57a7744e 8126 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 8127 stats->tx_packets += packets;
8128 stats->tx_bytes += bytes;
8129 }
8130 }
1a51502b 8131 rcu_read_unlock();
de1036b1
ED		 8132 /* following stats updated by ixgbe_watchdog_task() */
8133 stats->multicast = netdev->stats.multicast;
8134 stats->rx_errors = netdev->stats.rx_errors;
8135 stats->rx_length_errors = netdev->stats.rx_length_errors;
8136 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8137 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8138 return stats;
8139}
8140
8af3c33f 8141#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 8142/**
8143 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8144 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 8145 * @tc: number of traffic classes currently enabled
8146 *
8147 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8148 * 802.1Q priority maps to a packet buffer that exists.
8149 */
8150static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8151{
8152 struct ixgbe_hw *hw = &adapter->hw;
8153 u32 reg, rsave;
8154 int i;
8155
8156 /* 82598 have a static priority to TC mapping that can not
8157 * be changed so no validation is needed.
8158 */
8159 if (hw->mac.type == ixgbe_mac_82598EB)
8160 return;
8161
8162 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8163 rsave = reg;
8164
8165 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8166 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8167
8168 /* If up2tc is out of bounds default to zero */
8169 if (up2tc > tc)
8170 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8171 }
8172
8173 if (reg != rsave)
8174 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8175
8176 return;
8177}
8178
02debdc9
AD		 8179/**
8180 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8181 * @adapter: Pointer to adapter struct
8182 *
8183 * Populate the netdev user priority to tc map
8184 */
8185static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8186{
8187 struct net_device *dev = adapter->netdev;
8188 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8189 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8190 u8 prio;
8191
8192 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8193 u8 tc = 0;
8194
8195 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8196 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8197 else if (ets)
8198 tc = ets->prio_tc[prio];
8199
8200 netdev_set_prio_tc_map(dev, prio, tc);
8201 }
8202}
8203
cca73c59 8204#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 8205/**
8206 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 8207 *
8208 * @netdev: net device to configure
8209 * @tc: number of traffic classes to enable
8210 */
8211int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8212{
8b1c0b24
JF		 8213 struct ixgbe_adapter *adapter = netdev_priv(dev);
8214 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 8215 bool pools;
8b1c0b24 8216
8b1c0b24 8217 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 8218 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8219 return -EINVAL;
8220
8221 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 8222 return -EINVAL;
8223
2a47fa45
JF		 8224 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8225 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8226 return -EBUSY;
8227
8b1c0b24 8228 /* Hardware has to reinitialize queues and interrupts to
52f33af8 8229 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 8230 * hardware is not flexible enough to do this dynamically.
8231 */
8232 if (netif_running(dev))
8233 ixgbe_close(dev);
bf4d67d9
AD		 8234 else
8235 ixgbe_reset(adapter);
8236
8b1c0b24
JF		 8237 ixgbe_clear_interrupt_scheme(adapter);
8238
cca73c59 8239#ifdef CONFIG_IXGBE_DCB
e7589eab 8240 if (tc) {
8b1c0b24 8241 netdev_set_num_tc(dev, tc);
02debdc9
AD		 8242 ixgbe_set_prio_tc_map(adapter);
8243
e7589eab 8244 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 8245
943561d3
AD		 8246 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8247 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 8248 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 8249 }
e7589eab 8250 } else {
8b1c0b24 8251 netdev_reset_tc(dev);
02debdc9 8252
943561d3
AD		 8253 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8254 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 8255
8256 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 8257
8258 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8259 adapter->dcb_cfg.pfc_mode_enable = false;
8260 }
8261
8b1c0b24 8262 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 8263
8264#endif /* CONFIG_IXGBE_DCB */
8265 ixgbe_init_interrupt_scheme(adapter);
8266
8b1c0b24 8267 if (netif_running(dev))
cca73c59 8268 return ixgbe_open(dev);
8b1c0b24
JF		 8269
8270 return 0;
8271}
de1036b1 8272
b82b17d9
JF		 8273static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
8274 struct tc_cls_u32_offload *cls)
8275{
1ecedc92 8276 u32 hdl = cls->knode.handle;
176621c9 8277 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
1ecedc92
AN		 8278 u32 loc = cls->knode.handle & 0xfffff;
8279 int err = 0, i, j;
8280 struct ixgbe_jump_table *jump = NULL;
8281
8282 if (loc > IXGBE_MAX_HW_ENTRIES)
8283 return -EINVAL;
b82b17d9 8284
176621c9
SS		 8285 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
8286 return -EINVAL;
8287
1ecedc92
AN		 8288 /* Clear this filter in the link data it is associated with */
8289 if (uhtid != 0x800) {
8290 jump = adapter->jump_tables[uhtid];
12746fd2
AN		 8291 if (!jump)
8292 return -EINVAL;
8293 if (!test_bit(loc - 1, jump->child_loc_map))
8294 return -EINVAL;
8295 clear_bit(loc - 1, jump->child_loc_map);
1ecedc92
AN		 8296 }
8297
8298 /* Check if the filter being deleted is a link */
8299 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
8300 jump = adapter->jump_tables[i];
8301 if (jump && jump->link_hdl == hdl) {
8302 /* Delete filters in the hardware in the child hash
8303 * table associated with this link
8304 */
8305 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
8306 if (!test_bit(j, jump->child_loc_map))
8307 continue;
8308 spin_lock(&adapter->fdir_perfect_lock);
8309 err = ixgbe_update_ethtool_fdir_entry(adapter,
8310 NULL,
8311 j + 1);
8312 spin_unlock(&adapter->fdir_perfect_lock);
8313 clear_bit(j, jump->child_loc_map);
8314 }
8315 /* Remove resources for this link */
8316 kfree(jump->input);
8317 kfree(jump->mask);
8318 kfree(jump);
8319 adapter->jump_tables[i] = NULL;
8320 return err;
8321 }
8322 }
176621c9 8323
b82b17d9 8324 spin_lock(&adapter->fdir_perfect_lock);
176621c9 8325 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
b82b17d9
JF		 8326 spin_unlock(&adapter->fdir_perfect_lock);
8327 return err;
8328}
8329
db956ae8
JF		 8330static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
8331 __be16 protocol,
8332 struct tc_cls_u32_offload *cls)
8333{
176621c9
SS		 8334 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8335
8336 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8337 return -EINVAL;
8338
db956ae8
JF		 8339 /* This ixgbe devices do not support hash tables at the moment
8340 * so abort when given hash tables.
8341 */
8342 if (cls->hnode.divisor > 0)
8343 return -EINVAL;
8344
176621c9 8345 set_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 8346 return 0;
8347}
8348
8349static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
8350 struct tc_cls_u32_offload *cls)
8351{
176621c9
SS		 8352 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8353
8354 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8355 return -EINVAL;
8356
8357 clear_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 8358 return 0;
8359}
8360
947f8a45 8361#ifdef CONFIG_NET_CLS_ACT
1cd127fc
DA		 8362struct upper_walk_data {
8363 struct ixgbe_adapter *adapter;
8364 u64 action;
8365 int ifindex;
8366 u8 queue;
8367};
8368
8369static int get_macvlan_queue(struct net_device *upper, void *_data)
8370{
8371 if (netif_is_macvlan(upper)) {
8372 struct macvlan_dev *dfwd = netdev_priv(upper);
8373 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
8374 struct upper_walk_data *data = _data;
8375 struct ixgbe_adapter *adapter = data->adapter;
8376 int ifindex = data->ifindex;
8377
8378 if (vadapter && vadapter->netdev->ifindex == ifindex) {
8379 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
8380 data->action = data->queue;
8381 return 1;
8382 }
8383 }
8384
8385 return 0;
8386}
8387
947f8a45
SS		 8388static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
8389 u8 *queue, u64 *action)
8390{
8391 unsigned int num_vfs = adapter->num_vfs, vf;
1cd127fc 8392 struct upper_walk_data data;
947f8a45 8393 struct net_device *upper;
947f8a45
SS		 8394
8395 /* redirect to a SRIOV VF */
8396 for (vf = 0; vf < num_vfs; ++vf) {
8397 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
8398 if (upper->ifindex == ifindex) {
8399 if (adapter->num_rx_pools > 1)
8400 *queue = vf * 2;
8401 else
8402 *queue = vf * adapter->num_rx_queues_per_pool;
8403
8404 *action = vf + 1;
8405 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
8406 return 0;
8407 }
8408 }
8409
8410 /* redirect to a offloaded macvlan netdev */
1cd127fc
DA		 8411 data.adapter = adapter;
8412 data.ifindex = ifindex;
8413 data.action = 0;
8414 data.queue = 0;
8415 if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
8416 get_macvlan_queue, &data)) {
8417 *action = data.action;
8418 *queue = data.queue;
8419
8420 return 0;
947f8a45
SS		 8421 }
8422
8423 return -EINVAL;
8424}
8425
8426static int parse_tc_actions(struct ixgbe_adapter *adapter,
8427 struct tcf_exts *exts, u64 *action, u8 *queue)
8428{
8429 const struct tc_action *a;
22dc13c8 8430 LIST_HEAD(actions);
947f8a45
SS		 8431 int err;
8432
8433 if (tc_no_actions(exts))
8434 return -EINVAL;
8435
22dc13c8
WC		 8436 tcf_exts_to_list(exts, &actions);
8437 list_for_each_entry(a, &actions, list) {
947f8a45
SS		 8438
8439 /* Drop action */
8440 if (is_tcf_gact_shot(a)) {
8441 *action = IXGBE_FDIR_DROP_QUEUE;
8442 *queue = IXGBE_FDIR_DROP_QUEUE;
8443 return 0;
8444 }
8445
8446 /* Redirect to a VF or a offloaded macvlan */
5724b8b5 8447 if (is_tcf_mirred_egress_redirect(a)) {
947f8a45
SS		 8448 int ifindex = tcf_mirred_ifindex(a);
8449
8450 err = handle_redirect_action(adapter, ifindex, queue,
8451 action);
8452 if (err == 0)
8453 return err;
8454 }
8455 }
8456
8457 return -EINVAL;
8458}
8459#else
8460static int parse_tc_actions(struct ixgbe_adapter *adapter,
8461 struct tcf_exts *exts, u64 *action, u8 *queue)
8462{
8463 return -EINVAL;
8464}
8465#endif /* CONFIG_NET_CLS_ACT */
8466
1cdaaf54
AN		 8467static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
8468 union ixgbe_atr_input *mask,
8469 struct tc_cls_u32_offload *cls,
8470 struct ixgbe_mat_field *field_ptr,
8471 struct ixgbe_nexthdr *nexthdr)
8472{
8473 int i, j, off;
8474 __be32 val, m;
8475 bool found_entry = false, found_jump_field = false;
8476
8477 for (i = 0; i < cls->knode.sel->nkeys; i++) {
8478 off = cls->knode.sel->keys[i].off;
8479 val = cls->knode.sel->keys[i].val;
8480 m = cls->knode.sel->keys[i].mask;
8481
8482 for (j = 0; field_ptr[j].val; j++) {
8483 if (field_ptr[j].off == off) {
8484 field_ptr[j].val(input, mask, val, m);
8485 input->filter.formatted.flow_type |=
8486 field_ptr[j].type;
8487 found_entry = true;
8488 break;
8489 }
8490 }
8491 if (nexthdr) {
8492 if (nexthdr->off == cls->knode.sel->keys[i].off &&
8493 nexthdr->val == cls->knode.sel->keys[i].val &&
8494 nexthdr->mask == cls->knode.sel->keys[i].mask)
8495 found_jump_field = true;
8496 else
8497 continue;
8498 }
8499 }
8500
8501 if (nexthdr && !found_jump_field)
8502 return -EINVAL;
8503
8504 if (!found_entry)
8505 return 0;
8506
8507 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
8508 IXGBE_ATR_L4TYPE_MASK;
8509
8510 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
8511 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
8512
8513 return 0;
8514}
8515
b82b17d9
JF		 8516static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
8517 __be16 protocol,
8518 struct tc_cls_u32_offload *cls)
8519{
8520 u32 loc = cls->knode.handle & 0xfffff;
8521 struct ixgbe_hw *hw = &adapter->hw;
8522 struct ixgbe_mat_field *field_ptr;
1cdaaf54
AN		 8523 struct ixgbe_fdir_filter *input = NULL;
8524 union ixgbe_atr_input *mask = NULL;
8525 struct ixgbe_jump_table *jump = NULL;
8526 int i, err = -EINVAL;
b82b17d9 8527 u8 queue;
176621c9 8528 u32 uhtid, link_uhtid;
b82b17d9 8529
176621c9
SS		 8530 uhtid = TC_U32_USERHTID(cls->knode.handle);
8531 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
b82b17d9 8532
176621c9 8533 /* At the moment cls_u32 jumps to network layer and skips past
b82b17d9
JF		 8534 * L2 headers. The canonical method to match L2 frames is to use
8535 * negative values. However this is error prone at best but really
8536 * just broken because there is no way to "know" what sort of hdr
176621c9 8537 * is in front of the network layer. Fix cls_u32 to support L2
b82b17d9
JF		 8538 * headers when needed.
8539 */
8540 if (protocol != htons(ETH_P_IP))
1cdaaf54 8541 return err;
b82b17d9
JF		 8542
8543 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
8544 e_err(drv, "Location out of range\n");
1cdaaf54 8545 return err;
b82b17d9
JF		 8546 }
8547
8548 /* cls u32 is a graph starting at root node 0x800. The driver tracks
8549 * links and also the fields used to advance the parser across each
8550 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
8551 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
8552 * To add support for new nodes update ixgbe_model.h parse structures
8553 * this function _should_ be generic try not to hardcode values here.
8554 */
176621c9 8555 if (uhtid == 0x800) {
1cdaaf54 8556 field_ptr = (adapter->jump_tables[0])->mat;
b82b17d9 8557 } else {
176621c9 8558 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
1cdaaf54
AN		 8559 return err;
8560 if (!adapter->jump_tables[uhtid])
8561 return err;
8562 field_ptr = (adapter->jump_tables[uhtid])->mat;
b82b17d9
JF		 8563 }
8564
8565 if (!field_ptr)
1cdaaf54 8566 return err;
b82b17d9 8567
1cdaaf54
AN		 8568 /* At this point we know the field_ptr is valid and need to either
8569 * build cls_u32 link or attach filter. Because adding a link to
8570 * a handle that does not exist is invalid and the same for adding
8571 * rules to handles that don't exist.
8572 */
b82b17d9 8573
1cdaaf54
AN		 8574 if (link_uhtid) {
8575 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
b82b17d9 8576
1cdaaf54
AN		 8577 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
8578 return err;
8579
8580 if (!test_bit(link_uhtid - 1, &adapter->tables))
8581 return err;
8582
1ecedc92
AN		 8583 /* Multiple filters as links to the same hash table are not
8584 * supported. To add a new filter with the same next header
8585 * but different match/jump conditions, create a new hash table
8586 * and link to it.
8587 */
8588 if (adapter->jump_tables[link_uhtid] &&
8589 (adapter->jump_tables[link_uhtid])->link_hdl) {
8590 e_err(drv, "Link filter exists for link: %x\n",
8591 link_uhtid);
8592 return err;
8593 }
8594
1cdaaf54
AN		 8595 for (i = 0; nexthdr[i].jump; i++) {
8596 if (nexthdr[i].o != cls->knode.sel->offoff ||
8597 nexthdr[i].s != cls->knode.sel->offshift ||
8598 nexthdr[i].m != cls->knode.sel->offmask)
8599 return err;
8600
8601 jump = kzalloc(sizeof(*jump), GFP_KERNEL);
8602 if (!jump)
8603 return -ENOMEM;
8604 input = kzalloc(sizeof(*input), GFP_KERNEL);
8605 if (!input) {
8606 err = -ENOMEM;
8607 goto free_jump;
8608 }
8609 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
8610 if (!mask) {
8611 err = -ENOMEM;
12746fd2 8612 goto free_input;
1cdaaf54
AN		 8613 }
8614 jump->input = input;
8615 jump->mask = mask;
1ecedc92
AN		 8616 jump->link_hdl = cls->knode.handle;
8617
1cdaaf54
AN		 8618 err = ixgbe_clsu32_build_input(input, mask, cls,
8619 field_ptr, &nexthdr[i]);
8620 if (!err) {
8621 jump->mat = nexthdr[i].jump;
8622 adapter->jump_tables[link_uhtid] = jump;
b82b17d9
JF		 8623 break;
8624 }
8625 }
1cdaaf54 8626 return 0;
b82b17d9
JF		 8627 }
8628
1cdaaf54
AN		 8629 input = kzalloc(sizeof(*input), GFP_KERNEL);
8630 if (!input)
8631 return -ENOMEM;
8632 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
8633 if (!mask) {
8634 err = -ENOMEM;
12746fd2 8635 goto free_input;
1cdaaf54 8636 }
b82b17d9 8637
1cdaaf54
AN		 8638 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
8639 if ((adapter->jump_tables[uhtid])->input)
8640 memcpy(input, (adapter->jump_tables[uhtid])->input,
8641 sizeof(*input));
8642 if ((adapter->jump_tables[uhtid])->mask)
8643 memcpy(mask, (adapter->jump_tables[uhtid])->mask,
8644 sizeof(*mask));
12746fd2
AN		 8645
8646 /* Lookup in all child hash tables if this location is already
8647 * filled with a filter
8648 */
8649 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
8650 struct ixgbe_jump_table *link = adapter->jump_tables[i];
8651
8652 if (link && (test_bit(loc - 1, link->child_loc_map))) {
8653 e_err(drv, "Filter exists in location: %x\n",
8654 loc);
8655 err = -EINVAL;
8656 goto err_out;
8657 }
8658 }
1cdaaf54
AN		 8659 }
8660 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
8661 if (err)
b82b17d9
JF		 8662 goto err_out;
8663
947f8a45
SS		 8664 err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
8665 &queue);
8666 if (err < 0)
b82b17d9 8667 goto err_out;
b82b17d9 8668
b82b17d9
JF		 8669 input->sw_idx = loc;
8670
8671 spin_lock(&adapter->fdir_perfect_lock);
8672
8673 if (hlist_empty(&adapter->fdir_filter_list)) {
1cdaaf54
AN		 8674 memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
8675 err = ixgbe_fdir_set_input_mask_82599(hw, mask);
b82b17d9
JF		 8676 if (err)
8677 goto err_out_w_lock;
1cdaaf54 8678 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
b82b17d9
JF		 8679 err = -EINVAL;
8680 goto err_out_w_lock;
8681 }
8682
1cdaaf54 8683 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
b82b17d9
JF		 8684 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
8685 input->sw_idx, queue);
8686 if (!err)
8687 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
8688 spin_unlock(&adapter->fdir_perfect_lock);
8689
12746fd2
AN		 8690 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
8691 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
1ecedc92 8692
1cdaaf54 8693 kfree(mask);
b82b17d9
JF		 8694 return err;
8695err_out_w_lock:
8696 spin_unlock(&adapter->fdir_perfect_lock);
8697err_out:
1ecedc92 8698 kfree(mask);
12746fd2
AN		 8699free_input:
8700 kfree(input);
1cdaaf54
AN		 8701free_jump:
8702 kfree(jump);
8703 return err;
b82b17d9
JF		 8704}
8705
6e2a60b5
ET		 8706static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
8707 struct tc_to_netdev *tc)
e4c6734e 8708{
b82b17d9
JF		 8709 struct ixgbe_adapter *adapter = netdev_priv(dev);
8710
8711 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
8712 tc->type == TC_SETUP_CLSU32) {
b82b17d9
JF		 8713 switch (tc->cls_u32->command) {
8714 case TC_CLSU32_NEW_KNODE:
8715 case TC_CLSU32_REPLACE_KNODE:
8716 return ixgbe_configure_clsu32(adapter,
8717 proto, tc->cls_u32);
8718 case TC_CLSU32_DELETE_KNODE:
8719 return ixgbe_delete_clsu32(adapter, tc->cls_u32);
db956ae8
JF		 8720 case TC_CLSU32_NEW_HNODE:
8721 case TC_CLSU32_REPLACE_HNODE:
8722 return ixgbe_configure_clsu32_add_hnode(adapter, proto,
8723 tc->cls_u32);
8724 case TC_CLSU32_DELETE_HNODE:
8725 return ixgbe_configure_clsu32_del_hnode(adapter,
8726 tc->cls_u32);
b82b17d9
JF		 8727 default:
8728 return -EINVAL;
8729 }
8730 }
8731
5eb4dce3 8732 if (tc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 8733 return -EINVAL;
8734
16e5cc64 8735 return ixgbe_setup_tc(dev, tc->tc);
e4c6734e
JF		 8736}
8737
da36b647
GR		 8738#ifdef CONFIG_PCI_IOV
8739void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8740{
8741 struct net_device *netdev = adapter->netdev;
8742
8743 rtnl_lock();
da36b647 8744 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 8745 rtnl_unlock();
8746}
8747
8748#endif
082757af
DS		 8749void ixgbe_do_reset(struct net_device *netdev)
8750{
8751 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8752
8753 if (netif_running(netdev))
8754 ixgbe_reinit_locked(adapter);
8755 else
8756 ixgbe_reset(adapter);
8757}
8758
c8f44aff 8759static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 8760 netdev_features_t features)
082757af
DS		 8761{
8762 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8763
082757af 8764 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 8765 if (!(features & NETIF_F_RXCSUM))
8766 features &= ~NETIF_F_LRO;
082757af 8767
567d2de2
AD		 8768 /* Turn off LRO if not RSC capable */
8769 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8770 features &= ~NETIF_F_LRO;
8e2813f5 8771
567d2de2 8772 return features;
082757af
DS		 8773}
8774
c8f44aff 8775static int ixgbe_set_features(struct net_device *netdev,
567d2de2 8776 netdev_features_t features)
082757af
DS		 8777{
8778 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 8779 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 8780 bool need_reset = false;
8781
082757af 8782 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 8783 if (!(features & NETIF_F_LRO)) {
8784 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 8785 need_reset = true;
567d2de2
AD		 8786 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8787 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8788 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8789 if (adapter->rx_itr_setting == 1 ||
8790 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8791 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8792 need_reset = true;
8793 } else if ((changed ^ features) & NETIF_F_LRO) {
8794 e_info(probe, "rx-usecs set too low, "
8795 "disabling RSC\n");
082757af
DS		 8796 }
8797 }
8798
8799 /*
b82b17d9
JF		 8800 * Check if Flow Director n-tuple support or hw_tc support was
8801 * enabled or disabled. If the state changed, we need to reset.
082757af 8802 */
b82b17d9 8803 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
567d2de2 8804 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8805 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8806 need_reset = true;
8807
567d2de2
AD		 8808 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8809 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
b82b17d9 8810 } else {
39cb681b
AD		 8811 /* turn off perfect filters, enable ATR and reset */
8812 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8813 need_reset = true;
8814
8815 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8816
8817 /* We cannot enable ATR if SR-IOV is enabled */
b82b17d9
JF		 8818 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
8819 /* We cannot enable ATR if we have 2 or more tcs */
8820 (netdev_get_num_tc(netdev) > 1) ||
8821 /* We cannot enable ATR if RSS is disabled */
8822 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
8823 /* A sample rate of 0 indicates ATR disabled */
8824 (!adapter->atr_sample_rate))
8825 ; /* do nothing not supported */
8826 else /* otherwise supported and set the flag */
8827 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 8828 }
8829
3f2d1c0f
BG		 8830 if (changed & NETIF_F_RXALL)
8831 need_reset = true;
8832
567d2de2 8833 netdev->features = features;
67359c3c 8834
67359c3c 8835 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
a21d0822
ET		 8836 if (features & NETIF_F_RXCSUM) {
8837 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
8838 } else {
8839 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK;
8840
8841 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
8842 }
8843 }
8844
8845 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) {
8846 if (features & NETIF_F_RXCSUM) {
8847 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
8848 } else {
8849 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK;
8850
8851 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
8852 }
67359c3c 8853 }
67359c3c 8854
082757af
DS		 8855 if (need_reset)
8856 ixgbe_do_reset(netdev);
0c5a6166
AD		 8857 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
8858 NETIF_F_HW_VLAN_CTAG_FILTER))
8859 ixgbe_set_rx_mode(netdev);
082757af
DS		 8860
8861 return 0;
082757af
DS		 8862}
8863
3f207800 8864/**
a21d0822 8865 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports
3f207800 8866 * @dev: The port's netdev
e5de25dc 8867 * @ti: Tunnel endpoint information
3f207800 8868 **/
a21d0822
ET		 8869static void ixgbe_add_udp_tunnel_port(struct net_device *dev,
8870 struct udp_tunnel_info *ti)
3f207800
DS		 8871{
8872 struct ixgbe_adapter *adapter = netdev_priv(dev);
8873 struct ixgbe_hw *hw = &adapter->hw;
b3a49557 8874 __be16 port = ti->port;
a21d0822
ET		 8875 u32 port_shift = 0;
8876 u32 reg;
67359c3c 8877
b3a49557
AD		 8878 if (ti->sa_family != AF_INET)
8879 return;
8880
a21d0822
ET		 8881 switch (ti->type) {
8882 case UDP_TUNNEL_TYPE_VXLAN:
8883 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8884 return;
3f207800 8885
a21d0822
ET		 8886 if (adapter->vxlan_port == port)
8887 return;
8888
8889 if (adapter->vxlan_port) {
8890 netdev_info(dev,
8891 "VXLAN port %d set, not adding port %d\n",
8892 ntohs(adapter->vxlan_port),
8893 ntohs(port));
8894 return;
8895 }
8896
8897 adapter->vxlan_port = port;
8898 break;
8899 case UDP_TUNNEL_TYPE_GENEVE:
8900 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))
8901 return;
8902
8903 if (adapter->geneve_port == port)
8904 return;
8905
8906 if (adapter->geneve_port) {
8907 netdev_info(dev,
8908 "GENEVE port %d set, not adding port %d\n",
8909 ntohs(adapter->geneve_port),
8910 ntohs(port));
8911 return;
8912 }
3f207800 8913
a21d0822
ET		 8914 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT;
8915 adapter->geneve_port = port;
8916 break;
8917 default:
3f207800
DS		 8918 return;
8919 }
8920
a21d0822
ET		 8921 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift;
8922 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg);
3f207800
DS		 8923}
8924
8925/**
a21d0822 8926 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports
3f207800 8927 * @dev: The port's netdev
e5de25dc 8928 * @ti: Tunnel endpoint information
3f207800 8929 **/
a21d0822
ET		 8930static void ixgbe_del_udp_tunnel_port(struct net_device *dev,
8931 struct udp_tunnel_info *ti)
3f207800
DS		 8932{
8933 struct ixgbe_adapter *adapter = netdev_priv(dev);
a21d0822 8934 u32 port_mask;
3f207800 8935
a21d0822
ET		 8936 if (ti->type != UDP_TUNNEL_TYPE_VXLAN &&
8937 ti->type != UDP_TUNNEL_TYPE_GENEVE)
67359c3c
MR		 8938 return;
8939
b3a49557 8940 if (ti->sa_family != AF_INET)
3f207800
DS		 8941 return;
8942
a21d0822
ET		 8943 switch (ti->type) {
8944 case UDP_TUNNEL_TYPE_VXLAN:
8945 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8946 return;
b3a49557 8947
a21d0822
ET		 8948 if (adapter->vxlan_port != ti->port) {
8949 netdev_info(dev, "VXLAN port %d not found\n",
8950 ntohs(ti->port));
8951 return;
8952 }
8953
8954 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK;
8955 break;
8956 case UDP_TUNNEL_TYPE_GENEVE:
8957 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))
8958 return;
8959
8960 if (adapter->geneve_port != ti->port) {
8961 netdev_info(dev, "GENEVE port %d not found\n",
8962 ntohs(ti->port));
8963 return;
8964 }
8965
8966 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK;
8967 break;
8968 default:
3f207800
DS		 8969 return;
8970 }
8971
a21d0822
ET		 8972 ixgbe_clear_udp_tunnel_port(adapter, port_mask);
8973 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
3f207800
DS		 8974}
8975
edc7d573 8976static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8977 struct net_device *dev,
f6f6424b 8978 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8979 u16 flags)
8980{
bcfd3432 8981 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8982 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2f9be166
AD		 8983 struct ixgbe_adapter *adapter = netdev_priv(dev);
8984 u16 pool = VMDQ_P(0);
8985
8986 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
bcfd3432 8987 return -ENOMEM;
0f4b0add
JF		 8988 }
8989
f6f6424b 8990 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8991}
8992
219efe97
DS		 8993/**
8994 * ixgbe_configure_bridge_mode - set various bridge modes
8995 * @adapter - the private structure
8996 * @mode - requested bridge mode
8997 *
8998 * Configure some settings require for various bridge modes.
8999 **/
9000static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9001 __u16 mode)
9002{
6d4c96ad
DS		 9003 struct ixgbe_hw *hw = &adapter->hw;
9004 unsigned int p, num_pools;
9005 u32 vmdctl;
9006
219efe97
DS		 9007 switch (mode) {
9008 case BRIDGE_MODE_VEPA:
6d4c96ad 9009 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 9010 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 9011
9012 /* must enable Rx switching replication to allow multicast
9013 * packet reception on all VFs, and to enable source address
9014 * pruning.
9015 */
9016 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9017 vmdctl |= IXGBE_VT_CTL_REPLEN;
9018 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9019
9020 /* enable Rx source address pruning. Note, this requires
9021 * replication to be enabled or else it does nothing.
9022 */
9023 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9024 for (p = 0; p < num_pools; p++) {
9025 if (hw->mac.ops.set_source_address_pruning)
9026 hw->mac.ops.set_source_address_pruning(hw,
9027 true,
9028 p);
9029 }
219efe97
DS		 9030 break;
9031 case BRIDGE_MODE_VEB:
6d4c96ad 9032 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 9033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
9034 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 9035
9036 /* disable Rx switching replication unless we have SR-IOV
9037 * virtual functions
9038 */
9039 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9040 if (!adapter->num_vfs)
9041 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
9042 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9043
9044 /* disable Rx source address pruning, since we don't expect to
9045 * be receiving external loopback of our transmitted frames.
9046 */
9047 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9048 for (p = 0; p < num_pools; p++) {
9049 if (hw->mac.ops.set_source_address_pruning)
9050 hw->mac.ops.set_source_address_pruning(hw,
9051 false,
9052 p);
9053 }
219efe97
DS		 9054 break;
9055 default:
9056 return -EINVAL;
9057 }
9058
9059 adapter->bridge_mode = mode;
9060
9061 e_info(drv, "enabling bridge mode: %s\n",
9062 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
9063
9064 return 0;
9065}
9066
815cccbf 9067static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 9068 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 9069{
9070 struct ixgbe_adapter *adapter = netdev_priv(dev);
9071 struct nlattr *attr, *br_spec;
9072 int rem;
9073
9074 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9075 return -EOPNOTSUPP;
9076
9077 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 9078 if (!br_spec)
9079 return -EINVAL;
815cccbf
JF		 9080
9081 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 9082 int status;
815cccbf 9083 __u16 mode;
815cccbf
JF		 9084
9085 if (nla_type(attr) != IFLA_BRIDGE_MODE)
9086 continue;
9087
b7c1a314
TG		 9088 if (nla_len(attr) < sizeof(mode))
9089 return -EINVAL;
9090
815cccbf 9091 mode = nla_get_u16(attr);
219efe97
DS		 9092 status = ixgbe_configure_bridge_mode(adapter, mode);
9093 if (status)
9094 return status;
aa2bacb6
DS		 9095
9096 break;
815cccbf
JF		 9097 }
9098
9099 return 0;
9100}
9101
9102static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 9103 struct net_device *dev,
46c264da 9104 u32 filter_mask, int nlflags)
815cccbf
JF		 9105{
9106 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 9107
9108 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9109 return 0;
9110
aa2bacb6 9111 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 9112 adapter->bridge_mode, 0, 0, nlflags,
9113 filter_mask, NULL);
815cccbf
JF		 9114}
9115
2a47fa45
JF		 9116static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
9117{
9118 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
9119 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 9120 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 9121 unsigned int limit;
2a47fa45
JF		 9122 int pool, err;
9123
aac2f1bf
JK		 9124 /* Hardware has a limited number of available pools. Each VF, and the
9125 * PF require a pool. Check to ensure we don't attempt to use more
9126 * then the available number of pools.
9127 */
9128 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
9129 return ERR_PTR(-EINVAL);
9130
219354d4
JF		 9131#ifdef CONFIG_RPS
9132 if (vdev->num_rx_queues != vdev->num_tx_queues) {
9133 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
9134 vdev->name);
9135 return ERR_PTR(-EINVAL);
9136 }
9137#endif
2a47fa45 9138 /* Check for hardware restriction on number of rx/tx queues */
219354d4 9139 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 9140 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
9141 netdev_info(pdev,
9142 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
9143 pdev->name);
9144 return ERR_PTR(-EINVAL);
9145 }
9146
9147 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
9148 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
9149 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
9150 return ERR_PTR(-EBUSY);
9151
bc52f951 9152 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 9153 if (!fwd_adapter)
9154 return ERR_PTR(-ENOMEM);
9155
9156 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
9157 adapter->num_rx_pools++;
9158 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 9159 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 9160
9161 /* Enable VMDq flag so device will be set in VM mode */
9162 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 9163 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 9164 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 9165
9166 /* Force reinit of ring allocation with VMDQ enabled */
9167 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
9168 if (err)
9169 goto fwd_add_err;
9170 fwd_adapter->pool = pool;
9171 fwd_adapter->real_adapter = adapter;
a3b8cb1f
ET		 9172
9173 if (netif_running(pdev)) {
9174 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
9175 if (err)
9176 goto fwd_add_err;
9177 netif_tx_start_all_queues(vdev);
9178 }
9179
2a47fa45
JF		 9180 return fwd_adapter;
9181fwd_add_err:
9182 /* unwind counter and free adapter struct */
9183 netdev_info(pdev,
9184 "%s: dfwd hardware acceleration failed\n", vdev->name);
9185 clear_bit(pool, &adapter->fwd_bitmask);
9186 adapter->num_rx_pools--;
9187 kfree(fwd_adapter);
9188 return ERR_PTR(err);
9189}
9190
9191static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
9192{
9193 struct ixgbe_fwd_adapter *fwd_adapter = priv;
9194 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 9195 unsigned int limit;
2a47fa45
JF		 9196
9197 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
9198 adapter->num_rx_pools--;
9199
51f3773b
JF		 9200 limit = find_last_bit(&adapter->fwd_bitmask, 32);
9201 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 9202 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
9203 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
9204 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
9205 fwd_adapter->pool, adapter->num_rx_pools,
9206 fwd_adapter->rx_base_queue,
9207 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
9208 adapter->fwd_bitmask);
9209 kfree(fwd_adapter);
9210}
9211
b83e3010
AD		 9212#define IXGBE_MAX_MAC_HDR_LEN 127
9213#define IXGBE_MAX_NETWORK_HDR_LEN 511
9214
f467bc06
MR		 9215static netdev_features_t
9216ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
9217 netdev_features_t features)
9218{
b83e3010
AD		 9219 unsigned int network_hdr_len, mac_hdr_len;
9220
9221 /* Make certain the headers can be described by a context descriptor */
9222 mac_hdr_len = skb_network_header(skb) - skb->data;
9223 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
9224 return features & ~(NETIF_F_HW_CSUM |
9225 NETIF_F_SCTP_CRC |
9226 NETIF_F_HW_VLAN_CTAG_TX |
9227 NETIF_F_TSO |
9228 NETIF_F_TSO6);
9229
9230 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
9231 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
9232 return features & ~(NETIF_F_HW_CSUM |
9233 NETIF_F_SCTP_CRC |
9234 NETIF_F_TSO |
9235 NETIF_F_TSO6);
9236
9237 /* We can only support IPV4 TSO in tunnels if we can mangle the
9238 * inner IP ID field, so strip TSO if MANGLEID is not supported.
9239 */
9240 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
9241 features &= ~NETIF_F_TSO;
f467bc06
MR		 9242
9243 return features;
9244}
9245
0edc3527 9246static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 9247 .ndo_open = ixgbe_open,
0edc3527 9248 .ndo_stop = ixgbe_close,
00829823 9249 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 9250 .ndo_select_queue = ixgbe_select_queue,
581330ba 9251 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 9252 .ndo_validate_addr = eth_validate_addr,
9253 .ndo_set_mac_address = ixgbe_set_mac,
9254 .ndo_change_mtu = ixgbe_change_mtu,
9255 .ndo_tx_timeout = ixgbe_tx_timeout,
c04f90e5 9256 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
0edc3527
SH		 9257 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
9258 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 9259 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 9260 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
9261 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 9262 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 9263 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 9264 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 9265 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 9266 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 9267 .ndo_get_stats64 = ixgbe_get_stats64,
e4c6734e 9268 .ndo_setup_tc = __ixgbe_setup_tc,
0edc3527
SH		 9269#ifdef CONFIG_NET_POLL_CONTROLLER
9270 .ndo_poll_controller = ixgbe_netpoll,
9271#endif
e0d1095a 9272#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 9273 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 9274#endif
332d4a7d
YZ		 9275#ifdef IXGBE_FCOE
9276 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 9277 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 9278 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 9279 .ndo_fcoe_enable = ixgbe_fcoe_enable,
9280 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 9281 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 9282 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 9283#endif /* IXGBE_FCOE */
082757af
DS		 9284 .ndo_set_features = ixgbe_set_features,
9285 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 9286 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 9287 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
9288 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 9289 .ndo_dfwd_add_station = ixgbe_fwd_add,
9290 .ndo_dfwd_del_station = ixgbe_fwd_del,
a21d0822
ET		 9291 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port,
9292 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port,
f467bc06 9293 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 9294};
9295
e027d1ae
JK		 9296/**
9297 * ixgbe_enumerate_functions - Get the number of ports this device has
9298 * @adapter: adapter structure
9299 *
9300 * This function enumerates the phsyical functions co-located on a single slot,
9301 * in order to determine how many ports a device has. This is most useful in
9302 * determining the required GT/s of PCIe bandwidth necessary for optimal
9303 * performance.
9304 **/
9305static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
9306{
caafb95d 9307 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 9308 int physfns = 0;
9309
f1f96579
JK		 9310 /* Some cards can not use the generic count PCIe functions method,
9311 * because they are behind a parent switch, so we hardcode these with
9312 * the correct number of functions.
e027d1ae 9313 */
8818970d 9314 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 9315 physfns = 4;
8818970d
JK		 9316
9317 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
9318 /* don't count virtual functions */
caafb95d
JK		 9319 if (entry->is_virtfn)
9320 continue;
9321
9322 /* When the devices on the bus don't all match our device ID,
9323 * we can't reliably determine the correct number of
9324 * functions. This can occur if a function has been direct
9325 * attached to a virtual machine using VT-d, for example. In
9326 * this case, simply return -1 to indicate this.
9327 */
9328 if ((entry->vendor != pdev->vendor) ||
9329 (entry->device != pdev->device))
9330 return -1;
9331
9332 physfns++;
e027d1ae
JK		 9333 }
9334
9335 return physfns;
9336}
9337
8e2813f5
JK		 9338/**
9339 * ixgbe_wol_supported - Check whether device supports WoL
740234f0 9340 * @adapter: the adapter private structure
8e2813f5
JK		 9341 * @device_id: the device ID
9342 * @subdev_id: the subsystem device ID
9343 *
9344 * This function is used by probe and ethtool to determine
9345 * which devices have WoL support
9346 *
9347 **/
740234f0
ET		 9348bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
9349 u16 subdevice_id)
8e2813f5
JK		 9350{
9351 struct ixgbe_hw *hw = &adapter->hw;
9352 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8e2813f5 9353
740234f0
ET		 9354 /* WOL not supported on 82598 */
9355 if (hw->mac.type == ixgbe_mac_82598EB)
9356 return false;
9357
9358 /* check eeprom to see if WOL is enabled for X540 and newer */
9359 if (hw->mac.type >= ixgbe_mac_X540) {
9360 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
9361 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
9362 (hw->bus.func == 0)))
9363 return true;
9364 }
9365
9366 /* WOL is determined based on device IDs for 82599 MACs */
8e2813f5
JK		 9367 switch (device_id) {
9368 case IXGBE_DEV_ID_82599_SFP:
9369 /* Only these subdevices could supports WOL */
9370 switch (subdevice_id) {
9371 case IXGBE_SUBDEV_ID_82599_560FLR:
00103a6c
ET		 9372 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
9373 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
9374 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
8e2813f5
JK		 9375 /* only support first port */
9376 if (hw->bus.func != 0)
9377 break;
5700ff26 9378 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 9379 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 9380 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 9381 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
00103a6c
ET		 9382 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
9383 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
9384 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
740234f0 9385 return true;
8e2813f5
JK		 9386 }
9387 break;
5daebbb0 9388 case IXGBE_DEV_ID_82599EN_SFP:
740234f0 9389 /* Only these subdevices support WOL */
5daebbb0
DS		 9390 switch (subdevice_id) {
9391 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
740234f0 9392 return true;
5daebbb0
DS		 9393 }
9394 break;
8e2813f5
JK		 9395 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
9396 /* All except this subdevice support WOL */
9397 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
740234f0 9398 return true;
8e2813f5
JK		 9399 break;
9400 case IXGBE_DEV_ID_82599_KX4:
740234f0
ET		 9401 return true;
9402 default:
8e2813f5
JK		 9403 break;
9404 }
9405
740234f0 9406 return false;
8e2813f5
JK		 9407}
9408
9a799d71
AK		 9409/**
9410 * ixgbe_probe - Device Initialization Routine
9411 * @pdev: PCI device information struct
9412 * @ent: entry in ixgbe_pci_tbl
9413 *
9414 * Returns 0 on success, negative on failure
9415 *
9416 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
9417 * The OS initialization, configuring of the adapter private structure,
9418 * and a hardware reset occur.
9419 **/
1dd06ae8 9420static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 9421{
9422 struct net_device *netdev;
9423 struct ixgbe_adapter *adapter = NULL;
9424 struct ixgbe_hw *hw;
9425 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 9426 int i, err, pci_using_dac, expected_gts;
d3cb9869 9427 unsigned int indices = MAX_TX_QUEUES;
289700db 9428 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 9429 bool disable_dev = false;
eacd73f7
YZ		 9430#ifdef IXGBE_FCOE
9431 u16 device_caps;
9432#endif
289700db 9433 u32 eec;
9a799d71 9434
bded64a7
AG		 9435 /* Catch broken hardware that put the wrong VF device ID in
9436 * the PCIe SR-IOV capability.
9437 */
9438 if (pdev->is_virtfn) {
9439 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
9440 pci_name(pdev), pdev->vendor, pdev->device);
9441 return -EINVAL;
9442 }
9443
9ce77666 9444 err = pci_enable_device_mem(pdev);
9a799d71
AK		 9445 if (err)
9446 return err;
9447
f5f2eda8 9448 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 9449 pci_using_dac = 1;
9450 } else {
f5f2eda8 9451 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 9452 if (err) {
f5f2eda8
RK		 9453 dev_err(&pdev->dev,
9454 "No usable DMA configuration, aborting\n");
9455 goto err_dma;
9a799d71
AK		 9456 }
9457 pci_using_dac = 0;
9458 }
9459
56d766d6 9460 err = pci_request_mem_regions(pdev, ixgbe_driver_name);
9a799d71 9461 if (err) {
b8bc0421
DC		 9462 dev_err(&pdev->dev,
9463 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 9464 goto err_pci_reg;
9465 }
9466
19d5afd4 9467 pci_enable_pcie_error_reporting(pdev);
6fabd715 9468
9a799d71 9469 pci_set_master(pdev);
fb3b27bc 9470 pci_save_state(pdev);
9a799d71 9471
d3cb9869 9472 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 9473#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 9474 /* 8 TC w/ 4 queues per TC */
9475 indices = 4 * MAX_TRAFFIC_CLASS;
9476#else
9477 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 9478#endif
d3cb9869 9479 }
e901acd6 9480
c85a2618 9481 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 9482 if (!netdev) {
9483 err = -ENOMEM;
9484 goto err_alloc_etherdev;
9485 }
9486
9a799d71
AK		 9487 SET_NETDEV_DEV(netdev, &pdev->dev);
9488
9a799d71
AK		 9489 adapter = netdev_priv(netdev);
9490
9491 adapter->netdev = netdev;
9492 adapter->pdev = pdev;
9493 hw = &adapter->hw;
9494 hw->back = adapter;
b3f4d599 9495 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 9496
05857980 9497 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 9498 pci_resource_len(pdev, 0));
2a1a091c 9499 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 9500 if (!hw->hw_addr) {
9501 err = -EIO;
9502 goto err_ioremap;
9503 }
9504
0edc3527 9505 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 9506 ixgbe_set_ethtool_ops(netdev);
9a799d71 9507 netdev->watchdog_timeo = 5 * HZ;
339de30f 9508 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 9509
9a799d71 9510 /* Setup hw api */
37689010 9511 hw->mac.ops = *ii->mac_ops;
021230d4 9512 hw->mac.type = ii->mac;
9a900eca 9513 hw->mvals = ii->mvals;
b71f6c40
ET		 9514 if (ii->link_ops)
9515 hw->link.ops = *ii->link_ops;
9a799d71 9516
c44ade9e 9517 /* EEPROM */
37689010 9518 hw->eeprom.ops = *ii->eeprom_ops;
9a900eca 9519 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 9520 if (ixgbe_removed(hw->hw_addr)) {
9521 err = -EIO;
9522 goto err_ioremap;
9523 }
c44ade9e 9524 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
b4f47a48 9525 if (!(eec & BIT(8)))
c44ade9e
JB		 9526 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
9527
9528 /* PHY */
37689010 9529 hw->phy.ops = *ii->phy_ops;
c4900be0 9530 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 9531 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
9532 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
9533 hw->phy.mdio.mmds = 0;
9534 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9535 hw->phy.mdio.dev = netdev;
9536 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
9537 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 9538
9a799d71 9539 /* setup the private structure */
55570b6f 9540 err = ixgbe_sw_init(adapter, ii);
9a799d71
AK		 9541 if (err)
9542 goto err_sw_init;
9543
dbd15b8f
DS		 9544 /* Make sure the SWFW semaphore is in a valid state */
9545 if (hw->mac.ops.init_swfw_sync)
9546 hw->mac.ops.init_swfw_sync(hw);
9547
e86bff0e 9548 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 9549 switch (adapter->hw.mac.type) {
9550 case ixgbe_mac_82599EB:
9551 case ixgbe_mac_X540:
9a75a1ac
DS		 9552 case ixgbe_mac_X550:
9553 case ixgbe_mac_X550EM_x:
49425dfc 9554 case ixgbe_mac_x550em_a:
e86bff0e 9555 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 9556 break;
9557 default:
9558 break;
9559 }
e86bff0e 9560
bf069c97
DS		 9561 /*
9562 * If there is a fan on this device and it has failed log the
9563 * failure.
9564 */
9565 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
9566 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
9567 if (esdp & IXGBE_ESDP_SDP1)
396e799c 9568 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 9569 }
9570
8ef78adc
PWJ		 9571 if (allow_unsupported_sfp)
9572 hw->allow_unsupported_sfp = allow_unsupported_sfp;
9573
c44ade9e 9574 /* reset_hw fills in the perm_addr as well */
119fc60a 9575 hw->phy.reset_if_overtemp = true;
c44ade9e 9576 err = hw->mac.ops.reset_hw(hw);
119fc60a 9577 hw->phy.reset_if_overtemp = false;
29a8dca1 9578 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 9579 err = 0;
9580 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 9581 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
9582 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 9583 goto err_sw_init;
9584 } else if (err) {
849c4542 9585 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 9586 goto err_sw_init;
9587 }
9588
99d74487 9589#ifdef CONFIG_PCI_IOV
60a1a680
GR		 9590 /* SR-IOV not supported on the 82598 */
9591 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9592 goto skip_sriov;
9593 /* Mailbox */
9594 ixgbe_init_mbx_params_pf(hw);
37689010 9595 hw->mbx.ops = ii->mbx_ops;
dcc23e3a 9596 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 9597 ixgbe_enable_sriov(adapter);
60a1a680 9598skip_sriov:
1cdd1ec8 9599
99d74487 9600#endif
396e799c 9601 netdev->features = NETIF_F_SG |
082757af
DS		 9602 NETIF_F_TSO |
9603 NETIF_F_TSO6 |
082757af 9604 NETIF_F_RXHASH |
49763de0 9605 NETIF_F_RXCSUM |
b83e3010
AD		 9606 NETIF_F_HW_CSUM;
9607
9608#define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
9609 NETIF_F_GSO_GRE_CSUM | \
7e13318d 9610 NETIF_F_GSO_IPXIP4 | \
bf2d1df3 9611 NETIF_F_GSO_IPXIP6 | \
b83e3010
AD		 9612 NETIF_F_GSO_UDP_TUNNEL | \
9613 NETIF_F_GSO_UDP_TUNNEL_CSUM)
9614
9615 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
9616 netdev->features |= NETIF_F_GSO_PARTIAL |
9617 IXGBE_GSO_PARTIAL_FEATURES;
ad31c402 9618
49763de0 9619 if (hw->mac.type >= ixgbe_mac_82599EB)
53692b1d 9620 netdev->features |= NETIF_F_SCTP_CRC;
49763de0
AD		 9621
9622 /* copy netdev features into list of user selectable features */
b83e3010 9623 netdev->hw_features |= netdev->features |
3d951822 9624 NETIF_F_HW_VLAN_CTAG_FILTER |
b83e3010
AD		 9625 NETIF_F_HW_VLAN_CTAG_RX |
9626 NETIF_F_HW_VLAN_CTAG_TX |
9627 NETIF_F_RXALL |
49763de0
AD		 9628 NETIF_F_HW_L2FW_DOFFLOAD;
9629
9630 if (hw->mac.type >= ixgbe_mac_82599EB)
9631 netdev->hw_features |= NETIF_F_NTUPLE |
b82b17d9 9632 NETIF_F_HW_TC;
45a5ead0 9633
b83e3010
AD		 9634 if (pci_using_dac)
9635 netdev->features |= NETIF_F_HIGHDMA;
9636
5eee87cd
AD		 9637 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
9638 netdev->hw_enc_features |= netdev->vlan_features;
9639 netdev->mpls_features |= NETIF_F_HW_CSUM;
9640
b83e3010
AD		 9641 /* set this bit last since it cannot be part of vlan_features */
9642 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
9643 NETIF_F_HW_VLAN_CTAG_RX |
9644 NETIF_F_HW_VLAN_CTAG_TX;
ad31c402 9645
01789349 9646 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 9647 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 9648
91c527a5
JW		 9649 /* MTU range: 68 - 9710 */
9650 netdev->min_mtu = ETH_MIN_MTU;
9651 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
9652
7a6b6f51 9653#ifdef CONFIG_IXGBE_DCB
8829009d
UK		 9654 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
9655 netdev->dcbnl_ops = &dcbnl_ops;
2f90b865
AD		 9656#endif
9657
eacd73f7 9658#ifdef IXGBE_FCOE
0d551589 9659 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 9660 unsigned int fcoe_l;
9661
eacd73f7
YZ		 9662 if (hw->mac.ops.get_device_caps) {
9663 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 9664 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
9665 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 9666 }
7c8ae65a 9667
d3cb9869
AD		 9668
9669 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
9670 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 9671
a58915c7
AD		 9672 netdev->features |= NETIF_F_FSO |
9673 NETIF_F_FCOE_CRC;
9674
7c8ae65a
AD		 9675 netdev->vlan_features |= NETIF_F_FSO |
9676 NETIF_F_FCOE_CRC |
9677 NETIF_F_FCOE_MTU;
5e09d7f6 9678 }
eacd73f7 9679#endif /* IXGBE_FCOE */
9a799d71 9680
082757af
DS		 9681 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9682 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 9683 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 9684 netdev->features |= NETIF_F_LRO;
9685
9a799d71 9686 /* make sure the EEPROM is good */
c44ade9e 9687 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 9688 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 9689 err = -EIO;
35937c05 9690 goto err_sw_init;
9a799d71
AK		 9691 }
9692
c7374b5a
SV		 9693 eth_platform_get_mac_address(&adapter->pdev->dev,
9694 adapter->hw.mac.perm_addr);
c762dff2 9695
9a799d71 9696 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 9697
aaeb6cdf 9698 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 9699 e_dev_err("invalid MAC address\n");
9a799d71 9700 err = -EIO;
35937c05 9701 goto err_sw_init;
9a799d71
AK		 9702 }
9703
56768045
TD		 9704 /* Set hw->mac.addr to permanent MAC address */
9705 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
c9f53e63 9706 ixgbe_mac_set_default_filter(adapter);
5d7daa35 9707
7086400d 9708 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 9709 (unsigned long) adapter);
9a799d71 9710
58cf663f
MR		 9711 if (ixgbe_removed(hw->hw_addr)) {
9712 err = -EIO;
9713 goto err_sw_init;
9714 }
7086400d 9715 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 9716 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 9717 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 9718
021230d4
AV		 9719 err = ixgbe_init_interrupt_scheme(adapter);
9720 if (err)
9721 goto err_sw_init;
9a799d71 9722
8e2813f5 9723 /* WOL not supported for all devices */
c23f5b6b 9724 adapter->wol = 0;
8e2813f5 9725 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 9726 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 9727 pdev->subsystem_device);
6b92b0ba 9728 if (hw->wol_enabled)
9417c464 9729 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 9730
e8e26350
PW		 9731 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9732
15e5209f
ET		 9733 /* save off EEPROM version number */
9734 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
9735 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
9736
04f165ef 9737 /* pick up the PCI bus settings for reporting later */
e027d1ae 9738 if (ixgbe_pcie_from_parent(hw))
b8e82001 9739 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 9740 else
9741 hw->mac.ops.get_bus_info(hw);
04f165ef 9742
e027d1ae
JK		 9743 /* calculate the expected PCIe bandwidth required for optimal
9744 * performance. Note that some older parts will never have enough
9745 * bandwidth due to being older generation PCIe parts. We clamp these
9746 * parts to ensure no warning is displayed if it can't be fixed.
9747 */
9748 switch (hw->mac.type) {
9749 case ixgbe_mac_82598EB:
9750 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
9751 break;
9752 default:
9753 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
9754 break;
0c254d86 9755 }
caafb95d
JK		 9756
9757 /* don't check link if we failed to enumerate functions */
9758 if (expected_gts > 0)
9759 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 9760
339de30f 9761 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 9762 if (err)
339de30f 9763 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 9764 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
9765 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
9766 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 9767 part_str);
6a2aae5a
JK		 9768 else
9769 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
9770 hw->mac.type, hw->phy.type, part_str);
9771
9772 e_dev_info("%pM\n", netdev->dev_addr);
9773
9a799d71 9774 /* reset the hardware with the new settings */
794caeb2 9775 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 9776 if (err == IXGBE_ERR_EEPROM_VERSION) {
9777 /* We are running on a pre-production device, log a warning */
849c4542
ET		 9778 e_dev_warn("This device is a pre-production adapter/LOM. "
9779 "Please be aware there may be issues associated "
9780 "with your hardware. If you are experiencing "
9781 "problems please contact your Intel or hardware "
9782 "representative who provided you with this "
9783 "hardware.\n");
794caeb2 9784 }
9a799d71
AK		 9785 strcpy(netdev->name, "eth%d");
9786 err = register_netdev(netdev);
9787 if (err)
9788 goto err_register;
9789
0fb6a55c
ET		 9790 pci_set_drvdata(pdev, adapter);
9791
ec74a471
ET		 9792 /* power down the optics for 82599 SFP+ fiber */
9793 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 9794 hw->mac.ops.disable_tx_laser(hw);
9795
54386467
JB		 9796 /* carrier off reporting is important to ethtool even BEFORE open */
9797 netif_carrier_off(netdev);
9798
5dd2d332 9799#ifdef CONFIG_IXGBE_DCA
652f093f 9800 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 9801 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 9802 ixgbe_setup_dca(adapter);
9803 }
9804#endif
1cdd1ec8 9805 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 9806 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 9807 for (i = 0; i < adapter->num_vfs; i++)
9808 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9809 }
9810
2466dd9c
JK		 9811 /* firmware requires driver version to be 0xFFFFFFFF
9812 * since os does not support feature
9813 */
9612de92 9814 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 9815 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9816 0xFF);
9612de92 9817
0365e6e4
PW		 9818 /* add san mac addr to netdev */
9819 ixgbe_add_sanmac_netdev(netdev);
9a799d71 9820
ea81875a 9821 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 9822
1210982b 9823#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 9824 if (ixgbe_sysfs_init(adapter))
9825 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 9826#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9827
00949167 9828 ixgbe_dbg_adapter_init(adapter);
00949167 9829
d1a35ee2
ET		 9830 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9831 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 9832 hw->mac.ops.setup_link(hw,
9833 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9834 true);
9835
9a799d71
AK		 9836 return 0;
9837
9838err_register:
5eba3699 9839 ixgbe_release_hw_control(adapter);
7a921c93 9840 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 9841err_sw_init:
99d74487 9842 ixgbe_disable_sriov(adapter);
7086400d 9843 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 9844 iounmap(adapter->io_addr);
1cdaaf54 9845 kfree(adapter->jump_tables[0]);
5d7daa35 9846 kfree(adapter->mac_table);
9a799d71 9847err_ioremap:
b5b2ffc0 9848 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9849 free_netdev(netdev);
9850err_alloc_etherdev:
56d766d6 9851 pci_release_mem_regions(pdev);
9a799d71
AK		 9852err_pci_reg:
9853err_dma:
b5b2ffc0 9854 if (!adapter || disable_dev)
41c62843 9855 pci_disable_device(pdev);
9a799d71
AK		 9856 return err;
9857}
9858
9859/**
9860 * ixgbe_remove - Device Removal Routine
9861 * @pdev: PCI device information struct
9862 *
9863 * ixgbe_remove is called by the PCI subsystem to alert the driver
9864 * that it should release a PCI device. The could be caused by a
9865 * Hot-Plug event, or because the driver is going to be removed from
9866 * memory.
9867 **/
9f9a12f8 9868static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 9869{
c60fbb00 9870 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 9871 struct net_device *netdev;
b5b2ffc0 9872 bool disable_dev;
1cdaaf54 9873 int i;
9a799d71 9874
0fb6a55c
ET		 9875 /* if !adapter then we already cleaned up in probe */
9876 if (!adapter)
9877 return;
9878
9879 netdev = adapter->netdev;
00949167 9880 ixgbe_dbg_adapter_exit(adapter);
00949167 9881
09f40aed 9882 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 9883 cancel_work_sync(&adapter->service_task);
9a799d71 9884
3a6a4eda 9885
5dd2d332 9886#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9887 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9888 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9889 dca_remove_requester(&pdev->dev);
9de7605e
MR		 9890 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9891 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 9892 }
9893
9894#endif
1210982b 9895#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9896 ixgbe_sysfs_exit(adapter);
1210982b 9897#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9898
0365e6e4
PW		 9899 /* remove the added san mac */
9900 ixgbe_del_sanmac_netdev(netdev);
9901
da36b647 9902#ifdef CONFIG_PCI_IOV
7837e286 9903 ixgbe_disable_sriov(adapter);
da36b647 9904#endif
6b010e9b
AW		 9905 if (netdev->reg_state == NETREG_REGISTERED)
9906 unregister_netdev(netdev);
9907
7a921c93 9908 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9909
021230d4 9910 ixgbe_release_hw_control(adapter);
9a799d71 9911
2b1588c3
AD		 9912#ifdef CONFIG_DCB
9913 kfree(adapter->ixgbe_ieee_pfc);
9914 kfree(adapter->ixgbe_ieee_ets);
9915
9916#endif
2a1a091c 9917 iounmap(adapter->io_addr);
56d766d6 9918 pci_release_mem_regions(pdev);
9a799d71 9919
849c4542 9920 e_dev_info("complete\n");
021230d4 9921
1cdaaf54
AN		 9922 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
9923 if (adapter->jump_tables[i]) {
9924 kfree(adapter->jump_tables[i]->input);
9925 kfree(adapter->jump_tables[i]->mask);
9926 }
9927 kfree(adapter->jump_tables[i]);
9928 }
9929
5d7daa35 9930 kfree(adapter->mac_table);
b5b2ffc0 9931 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9932 free_netdev(netdev);
9933
19d5afd4 9934 pci_disable_pcie_error_reporting(pdev);
6fabd715 9935
b5b2ffc0 9936 if (disable_dev)
41c62843 9937 pci_disable_device(pdev);
9a799d71
AK		 9938}
9939
9940/**
9941 * ixgbe_io_error_detected - called when PCI error is detected
9942 * @pdev: Pointer to PCI device
9943 * @state: The current pci connection state
9944 *
9945 * This function is called after a PCI bus error affecting
9946 * this device has been detected.
9947 */
9948static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9949 pci_channel_state_t state)
9a799d71 9950{
c60fbb00
AD		 9951 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9952 struct net_device *netdev = adapter->netdev;
9a799d71 9953
83c61fa9 9954#ifdef CONFIG_PCI_IOV
14438464 9955 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9956 struct pci_dev *bdev, *vfdev;
9957 u32 dw0, dw1, dw2, dw3;
9958 int vf, pos;
9959 u16 req_id, pf_func;
9960
9961 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9962 adapter->num_vfs == 0)
9963 goto skip_bad_vf_detection;
9964
9965 bdev = pdev->bus->self;
62f87c0e 9966 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9967 bdev = bdev->bus->self;
9968
9969 if (!bdev)
9970 goto skip_bad_vf_detection;
9971
9972 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9973 if (!pos)
9974 goto skip_bad_vf_detection;
9975
14438464
MR		 9976 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9977 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9978 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9979 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9980 if (ixgbe_removed(hw->hw_addr))
9981 goto skip_bad_vf_detection;
83c61fa9
GR		 9982
9983 req_id = dw1 >> 16;
9984 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9985 if (!(req_id & 0x0080))
9986 goto skip_bad_vf_detection;
9987
9988 pf_func = req_id & 0x01;
9989 if ((pf_func & 1) == (pdev->devfn & 1)) {
9990 unsigned int device_id;
9991
9992 vf = (req_id & 0x7F) >> 1;
9993 e_dev_err("VF %d has caused a PCIe error\n", vf);
9994 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9995 "%8.8x\tdw3: %8.8x\n",
9996 dw0, dw1, dw2, dw3);
9997 switch (adapter->hw.mac.type) {
9998 case ixgbe_mac_82599EB:
9999 device_id = IXGBE_82599_VF_DEVICE_ID;
10000 break;
10001 case ixgbe_mac_X540:
10002 device_id = IXGBE_X540_VF_DEVICE_ID;
10003 break;
9a75a1ac
DS		 10004 case ixgbe_mac_X550:
10005 device_id = IXGBE_DEV_ID_X550_VF;
10006 break;
10007 case ixgbe_mac_X550EM_x:
10008 device_id = IXGBE_DEV_ID_X550EM_X_VF;
10009 break;
49425dfc
MR		 10010 case ixgbe_mac_x550em_a:
10011 device_id = IXGBE_DEV_ID_X550EM_A_VF;
10012 break;
83c61fa9
GR		 10013 default:
10014 device_id = 0;
10015 break;
10016 }
10017
10018 /* Find the pci device of the offending VF */
36e90319 10019 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 10020 while (vfdev) {
10021 if (vfdev->devfn == (req_id & 0xFF))
10022 break;
36e90319 10023 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 10024 device_id, vfdev);
10025 }
10026 /*
10027 * There's a slim chance the VF could have been hot plugged,
10028 * so if it is no longer present we don't need to issue the
10029 * VFLR. Just clean up the AER in that case.
10030 */
10031 if (vfdev) {
9079e416 10032 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 10033 /* Free device reference count */
10034 pci_dev_put(vfdev);
83c61fa9
GR		 10035 }
10036
10037 pci_cleanup_aer_uncorrect_error_status(pdev);
10038 }
10039
10040 /*
10041 * Even though the error may have occurred on the other port
10042 * we still need to increment the vf error reference count for
10043 * both ports because the I/O resume function will be called
10044 * for both of them.
10045 */
10046 adapter->vferr_refcount++;
10047
10048 return PCI_ERS_RESULT_RECOVERED;
10049
10050skip_bad_vf_detection:
10051#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 10052 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
10053 return PCI_ERS_RESULT_DISCONNECT;
10054
41c62843 10055 rtnl_lock();
9a799d71
AK		 10056 netif_device_detach(netdev);
10057
41c62843
MR		 10058 if (state == pci_channel_io_perm_failure) {
10059 rtnl_unlock();
3044b8d1 10060 return PCI_ERS_RESULT_DISCONNECT;
41c62843 10061 }
3044b8d1 10062
9a799d71
AK		 10063 if (netif_running(netdev))
10064 ixgbe_down(adapter);
41c62843
MR		 10065
10066 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
10067 pci_disable_device(pdev);
10068 rtnl_unlock();
9a799d71 10069
b4617240 10070 /* Request a slot reset. */
9a799d71
AK		 10071 return PCI_ERS_RESULT_NEED_RESET;
10072}
10073
10074/**
10075 * ixgbe_io_slot_reset - called after the pci bus has been reset.
10076 * @pdev: Pointer to PCI device
10077 *
10078 * Restart the card from scratch, as if from a cold-boot.
10079 */
10080static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
10081{
c60fbb00 10082 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 10083 pci_ers_result_t result;
10084 int err;
9a799d71 10085
9ce77666 10086 if (pci_enable_device_mem(pdev)) {
396e799c 10087 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 10088 result = PCI_ERS_RESULT_DISCONNECT;
10089 } else {
4e857c58 10090 smp_mb__before_atomic();
41c62843 10091 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 10092 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 10093 pci_set_master(pdev);
10094 pci_restore_state(pdev);
c0e1f68b 10095 pci_save_state(pdev);
9a799d71 10096
dd4d8ca6 10097 pci_wake_from_d3(pdev, false);
9a799d71 10098
6fabd715 10099 ixgbe_reset(adapter);
88512539 10100 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 10101 result = PCI_ERS_RESULT_RECOVERED;
10102 }
10103
10104 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10105 if (err) {
849c4542
ET		 10106 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
10107 "failed 0x%0x\n", err);
6fabd715
PWJ		 10108 /* non-fatal, continue */
10109 }
9a799d71 10110
6fabd715 10111 return result;
9a799d71
AK		 10112}
10113
10114/**
10115 * ixgbe_io_resume - called when traffic can start flowing again.
10116 * @pdev: Pointer to PCI device
10117 *
10118 * This callback is called when the error recovery driver tells us that
10119 * its OK to resume normal operation.
10120 */
10121static void ixgbe_io_resume(struct pci_dev *pdev)
10122{
c60fbb00
AD		 10123 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
10124 struct net_device *netdev = adapter->netdev;
9a799d71 10125
83c61fa9
GR		 10126#ifdef CONFIG_PCI_IOV
10127 if (adapter->vferr_refcount) {
10128 e_info(drv, "Resuming after VF err\n");
10129 adapter->vferr_refcount--;
10130 return;
10131 }
10132
10133#endif
c7ccde0f
AD		 10134 if (netif_running(netdev))
10135 ixgbe_up(adapter);
9a799d71
AK		 10136
10137 netif_device_attach(netdev);
9a799d71
AK		 10138}
10139
3646f0e5 10140static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 10141 .error_detected = ixgbe_io_error_detected,
10142 .slot_reset = ixgbe_io_slot_reset,
10143 .resume = ixgbe_io_resume,
10144};
10145
10146static struct pci_driver ixgbe_driver = {
10147 .name = ixgbe_driver_name,
10148 .id_table = ixgbe_pci_tbl,
10149 .probe = ixgbe_probe,
9f9a12f8 10150 .remove = ixgbe_remove,
9a799d71
AK		 10151#ifdef CONFIG_PM
10152 .suspend = ixgbe_suspend,
10153 .resume = ixgbe_resume,
10154#endif
10155 .shutdown = ixgbe_shutdown,
da36b647 10156 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 10157 .err_handler = &ixgbe_err_handler
10158};
10159
10160/**
10161 * ixgbe_init_module - Driver Registration Routine
10162 *
10163 * ixgbe_init_module is the first routine called when the driver is
10164 * loaded. All it does is register with the PCI subsystem.
10165 **/
10166static int __init ixgbe_init_module(void)
10167{
10168 int ret;
c7689578 10169 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 10170 pr_info("%s\n", ixgbe_copyright);
9a799d71 10171
780484d8
MR		 10172 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
10173 if (!ixgbe_wq) {
10174 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
10175 return -ENOMEM;
10176 }
10177
00949167 10178 ixgbe_dbg_init();
00949167 10179
f01fc1a8
JK		 10180 ret = pci_register_driver(&ixgbe_driver);
10181 if (ret) {
6b836879 10182 destroy_workqueue(ixgbe_wq);
f01fc1a8 10183 ixgbe_dbg_exit();
f01fc1a8
JK		 10184 return ret;
10185 }
10186
5dd2d332 10187#ifdef CONFIG_IXGBE_DCA
bd0362dd 10188 dca_register_notify(&dca_notifier);
bd0362dd 10189#endif
5dd2d332 10190
f01fc1a8 10191 return 0;
9a799d71 10192}
b4617240 10193
9a799d71
AK		 10194module_init(ixgbe_init_module);
10195
10196/**
10197 * ixgbe_exit_module - Driver Exit Cleanup Routine
10198 *
10199 * ixgbe_exit_module is called just before the driver is removed
10200 * from memory.
10201 **/
10202static void __exit ixgbe_exit_module(void)
10203{
5dd2d332 10204#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 10205 dca_unregister_notify(&dca_notifier);
10206#endif
9a799d71 10207 pci_unregister_driver(&ixgbe_driver);
00949167 10208
00949167 10209 ixgbe_dbg_exit();
780484d8
MR		 10210 if (ixgbe_wq) {
10211 destroy_workqueue(ixgbe_wq);
10212 ixgbe_wq = NULL;
10213 }
9a799d71 10214}
bd0362dd 10215
5dd2d332 10216#ifdef CONFIG_IXGBE_DCA
bd0362dd 10217static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 10218 void *p)
bd0362dd
JC		 10219{
10220 int ret_val;
10221
10222 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 10223 __ixgbe_notify_dca);
bd0362dd
JC		 10224
10225 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
10226}
b453368d 10227
5dd2d332 10228#endif /* CONFIG_IXGBE_DCA */
849c4542 10229
9a799d71
AK		 10230module_exit(ixgbe_exit_module);
10231
10232/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)