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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
37689010 | 4 | Copyright(c) 1999 - 2016 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/types.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/vmalloc.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/in.h> | |
a6b7a407 | 36 | #include <linux/interrupt.h> |
9a799d71 AK |
37 | #include <linux/ip.h> |
38 | #include <linux/tcp.h> | |
897ab156 | 39 | #include <linux/sctp.h> |
60127865 | 40 | #include <linux/pkt_sched.h> |
9a799d71 | 41 | #include <linux/ipv6.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
9a799d71 AK |
43 | #include <net/checksum.h> |
44 | #include <net/ip6_checksum.h> | |
c762dff2 | 45 | #include <linux/etherdevice.h> |
9a799d71 | 46 | #include <linux/ethtool.h> |
01789349 | 47 | #include <linux/if.h> |
9a799d71 | 48 | #include <linux/if_vlan.h> |
2a47fa45 | 49 | #include <linux/if_macvlan.h> |
815cccbf | 50 | #include <linux/if_bridge.h> |
70c71606 | 51 | #include <linux/prefetch.h> |
92470808 JF |
52 | #include <linux/bpf.h> |
53 | #include <linux/bpf_trace.h> | |
54 | #include <linux/atomic.h> | |
eacd73f7 | 55 | #include <scsi/fc/fc_fcoe.h> |
b3a49557 | 56 | #include <net/udp_tunnel.h> |
b82b17d9 JF |
57 | #include <net/pkt_cls.h> |
58 | #include <net/tc_act/tc_gact.h> | |
947f8a45 | 59 | #include <net/tc_act/tc_mirred.h> |
9f3c7504 | 60 | #include <net/vxlan.h> |
2a20525b | 61 | #include <net/mpls.h> |
9a799d71 AK |
62 | |
63 | #include "ixgbe.h" | |
64 | #include "ixgbe_common.h" | |
ee5f784a | 65 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 66 | #include "ixgbe_sriov.h" |
b82b17d9 | 67 | #include "ixgbe_model.h" |
9a799d71 AK |
68 | |
69 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 70 | static const char ixgbe_driver_string[] = |
e8e9f696 | 71 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
8af3c33f | 72 | #ifdef IXGBE_FCOE |
ea81875a NP |
73 | char ixgbe_default_device_descr[] = |
74 | "Intel(R) 10 Gigabit Network Connection"; | |
8af3c33f JK |
75 | #else |
76 | static char ixgbe_default_device_descr[] = | |
77 | "Intel(R) 10 Gigabit Network Connection"; | |
78 | #endif | |
1733284d | 79 | #define DRV_VERSION "5.0.0-k" |
9c8eb720 | 80 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 81 | static const char ixgbe_copyright[] = |
49425dfc | 82 | "Copyright (c) 1999-2016 Intel Corporation."; |
9a799d71 | 83 | |
f44e751b DS |
84 | static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; |
85 | ||
9a799d71 | 86 | static const struct ixgbe_info *ixgbe_info_tbl[] = { |
6a14ee0c DS |
87 | [board_82598] = &ixgbe_82598_info, |
88 | [board_82599] = &ixgbe_82599_info, | |
89 | [board_X540] = &ixgbe_X540_info, | |
90 | [board_X550] = &ixgbe_X550_info, | |
91 | [board_X550EM_x] = &ixgbe_X550EM_x_info, | |
8dc963e1 | 92 | [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, |
49425dfc | 93 | [board_x550em_a] = &ixgbe_x550em_a_info, |
b3eb4e18 | 94 | [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, |
9a799d71 AK |
95 | }; |
96 | ||
97 | /* ixgbe_pci_tbl - PCI Device ID Table | |
98 | * | |
99 | * Wildcard entries (PCI_ANY_ID) should come last | |
100 | * Last entry must be all 0s | |
101 | * | |
102 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
103 | * Class, Class Mask, private data (not used) } | |
104 | */ | |
9baa3c34 | 105 | static const struct pci_device_id ixgbe_pci_tbl[] = { |
54239c67 AD |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
112 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
114 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
115 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
116 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
117 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
118 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
119 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
120 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
121 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
122 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
123 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
124 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
125 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
126 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
127 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
128 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
129 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
130 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
131 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
8f58332b | 132 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, |
7d145282 | 133 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 134 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
df376f0d | 135 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, |
6a14ee0c | 136 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, |
a711ad89 | 137 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, |
6a14ee0c | 138 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, |
18e01ee7 | 139 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, |
6a14ee0c | 140 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, |
deda562a | 141 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, |
018d7146 | 142 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, |
8dc963e1 | 143 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, |
f572b2c4 MR |
144 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, |
145 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, | |
49425dfc | 146 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, |
200157c2 MR |
147 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, |
148 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, | |
92ed8430 | 149 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, |
2d40cd17 | 150 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, |
b3eb4e18 MR |
151 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, |
152 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, | |
9a799d71 AK |
153 | /* required last entry */ |
154 | {0, } | |
155 | }; | |
156 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
157 | ||
5dd2d332 | 158 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 159 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 160 | void *p); |
bd0362dd JC |
161 | static struct notifier_block dca_notifier = { |
162 | .notifier_call = ixgbe_notify_dca, | |
163 | .next = NULL, | |
164 | .priority = 0 | |
165 | }; | |
166 | #endif | |
167 | ||
1cdd1ec8 GR |
168 | #ifdef CONFIG_PCI_IOV |
169 | static unsigned int max_vfs; | |
170 | module_param(max_vfs, uint, 0); | |
e8e9f696 | 171 | MODULE_PARM_DESC(max_vfs, |
170e8543 | 172 | "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); |
1cdd1ec8 GR |
173 | #endif /* CONFIG_PCI_IOV */ |
174 | ||
8ef78adc PWJ |
175 | static unsigned int allow_unsupported_sfp; |
176 | module_param(allow_unsupported_sfp, uint, 0); | |
177 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
178 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
179 | ||
b3f4d599 | 180 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
181 | static int debug = -1; | |
182 | module_param(debug, int, 0); | |
183 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
184 | ||
9a799d71 AK |
185 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
186 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
187 | MODULE_LICENSE("GPL"); | |
188 | MODULE_VERSION(DRV_VERSION); | |
189 | ||
780484d8 MR |
190 | static struct workqueue_struct *ixgbe_wq; |
191 | ||
14438464 | 192 | static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); |
b3eb4e18 | 193 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); |
14438464 | 194 | |
b8e82001 JK |
195 | static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, |
196 | u32 reg, u16 *value) | |
197 | { | |
b8e82001 JK |
198 | struct pci_dev *parent_dev; |
199 | struct pci_bus *parent_bus; | |
200 | ||
201 | parent_bus = adapter->pdev->bus->parent; | |
202 | if (!parent_bus) | |
203 | return -1; | |
204 | ||
205 | parent_dev = parent_bus->self; | |
206 | if (!parent_dev) | |
207 | return -1; | |
208 | ||
c0798edf | 209 | if (!pci_is_pcie(parent_dev)) |
b8e82001 JK |
210 | return -1; |
211 | ||
c0798edf | 212 | pcie_capability_read_word(parent_dev, reg, value); |
14438464 MR |
213 | if (*value == IXGBE_FAILED_READ_CFG_WORD && |
214 | ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) | |
215 | return -1; | |
b8e82001 JK |
216 | return 0; |
217 | } | |
218 | ||
219 | static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) | |
220 | { | |
221 | struct ixgbe_hw *hw = &adapter->hw; | |
222 | u16 link_status = 0; | |
223 | int err; | |
224 | ||
225 | hw->bus.type = ixgbe_bus_type_pci_express; | |
226 | ||
227 | /* Get the negotiated link width and speed from PCI config space of the | |
228 | * parent, as this device is behind a switch | |
229 | */ | |
230 | err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); | |
231 | ||
232 | /* assume caller will handle error case */ | |
233 | if (err) | |
234 | return err; | |
235 | ||
236 | hw->bus.width = ixgbe_convert_bus_width(link_status); | |
237 | hw->bus.speed = ixgbe_convert_bus_speed(link_status); | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
e027d1ae JK |
242 | /** |
243 | * ixgbe_check_from_parent - Determine whether PCIe info should come from parent | |
244 | * @hw: hw specific details | |
245 | * | |
246 | * This function is used by probe to determine whether a device's PCI-Express | |
247 | * bandwidth details should be gathered from the parent bus instead of from the | |
248 | * device. Used to ensure that various locations all have the correct device ID | |
249 | * checks. | |
250 | */ | |
251 | static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) | |
252 | { | |
253 | switch (hw->device_id) { | |
254 | case IXGBE_DEV_ID_82599_SFP_SF_QP: | |
8f58332b | 255 | case IXGBE_DEV_ID_82599_QSFP_SF_QP: |
e027d1ae JK |
256 | return true; |
257 | default: | |
258 | return false; | |
259 | } | |
260 | } | |
261 | ||
262 | static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, | |
263 | int expected_gts) | |
264 | { | |
f9328bc6 | 265 | struct ixgbe_hw *hw = &adapter->hw; |
e027d1ae JK |
266 | int max_gts = 0; |
267 | enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; | |
268 | enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; | |
269 | struct pci_dev *pdev; | |
270 | ||
f9328bc6 DS |
271 | /* Some devices are not connected over PCIe and thus do not negotiate |
272 | * speed. These devices do not have valid bus info, and thus any report | |
273 | * we generate may not be correct. | |
274 | */ | |
275 | if (hw->bus.type == ixgbe_bus_type_internal) | |
276 | return; | |
277 | ||
56d1392f | 278 | /* determine whether to use the parent device */ |
e027d1ae JK |
279 | if (ixgbe_pcie_from_parent(&adapter->hw)) |
280 | pdev = adapter->pdev->bus->parent->self; | |
281 | else | |
282 | pdev = adapter->pdev; | |
283 | ||
284 | if (pcie_get_minimum_link(pdev, &speed, &width) || | |
285 | speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { | |
286 | e_dev_warn("Unable to determine PCI Express bandwidth.\n"); | |
287 | return; | |
288 | } | |
289 | ||
290 | switch (speed) { | |
291 | case PCIE_SPEED_2_5GT: | |
292 | /* 8b/10b encoding reduces max throughput by 20% */ | |
293 | max_gts = 2 * width; | |
294 | break; | |
295 | case PCIE_SPEED_5_0GT: | |
296 | /* 8b/10b encoding reduces max throughput by 20% */ | |
297 | max_gts = 4 * width; | |
298 | break; | |
299 | case PCIE_SPEED_8_0GT: | |
9f0a433c | 300 | /* 128b/130b encoding reduces throughput by less than 2% */ |
e027d1ae JK |
301 | max_gts = 8 * width; |
302 | break; | |
303 | default: | |
304 | e_dev_warn("Unable to determine PCI Express bandwidth.\n"); | |
305 | return; | |
306 | } | |
307 | ||
308 | e_dev_info("PCI Express bandwidth of %dGT/s available\n", | |
309 | max_gts); | |
310 | e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", | |
311 | (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : | |
312 | speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : | |
313 | speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : | |
314 | "Unknown"), | |
315 | width, | |
316 | (speed == PCIE_SPEED_2_5GT ? "20%" : | |
317 | speed == PCIE_SPEED_5_0GT ? "20%" : | |
9f0a433c | 318 | speed == PCIE_SPEED_8_0GT ? "<2%" : |
e027d1ae JK |
319 | "Unknown")); |
320 | ||
321 | if (max_gts < expected_gts) { | |
322 | e_dev_warn("This is not sufficient for optimal performance of this card.\n"); | |
323 | e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", | |
324 | expected_gts); | |
325 | e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); | |
326 | } | |
327 | } | |
328 | ||
7086400d AD |
329 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
330 | { | |
331 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
09f40aed | 332 | !test_bit(__IXGBE_REMOVING, &adapter->state) && |
7086400d | 333 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) |
780484d8 | 334 | queue_work(ixgbe_wq, &adapter->service_task); |
7086400d AD |
335 | } |
336 | ||
2a1a091c MR |
337 | static void ixgbe_remove_adapter(struct ixgbe_hw *hw) |
338 | { | |
339 | struct ixgbe_adapter *adapter = hw->back; | |
340 | ||
341 | if (!hw->hw_addr) | |
342 | return; | |
343 | hw->hw_addr = NULL; | |
344 | e_dev_err("Adapter removed\n"); | |
58cf663f MR |
345 | if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) |
346 | ixgbe_service_event_schedule(adapter); | |
2a1a091c MR |
347 | } |
348 | ||
f8e2472f | 349 | static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) |
2a1a091c MR |
350 | { |
351 | u32 value; | |
352 | ||
353 | /* The following check not only optimizes a bit by not | |
354 | * performing a read on the status register when the | |
355 | * register just read was a status register read that | |
356 | * returned IXGBE_FAILED_READ_REG. It also blocks any | |
357 | * potential recursion. | |
358 | */ | |
359 | if (reg == IXGBE_STATUS) { | |
360 | ixgbe_remove_adapter(hw); | |
361 | return; | |
362 | } | |
363 | value = ixgbe_read_reg(hw, IXGBE_STATUS); | |
364 | if (value == IXGBE_FAILED_READ_REG) | |
365 | ixgbe_remove_adapter(hw); | |
366 | } | |
367 | ||
f8e2472f MR |
368 | /** |
369 | * ixgbe_read_reg - Read from device register | |
370 | * @hw: hw specific details | |
371 | * @reg: offset of register to read | |
372 | * | |
373 | * Returns : value read or IXGBE_FAILED_READ_REG if removed | |
374 | * | |
375 | * This function is used to read device registers. It checks for device | |
376 | * removal by confirming any read that returns all ones by checking the | |
377 | * status register value for all ones. This function avoids reading from | |
378 | * the hardware if a removal was previously detected in which case it | |
379 | * returns IXGBE_FAILED_READ_REG (all ones). | |
380 | */ | |
381 | u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) | |
382 | { | |
383 | u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); | |
384 | u32 value; | |
385 | ||
386 | if (ixgbe_removed(reg_addr)) | |
387 | return IXGBE_FAILED_READ_REG; | |
2f2219be MR |
388 | if (unlikely(hw->phy.nw_mng_if_sel & |
389 | IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M)) { | |
390 | struct ixgbe_adapter *adapter; | |
391 | int i; | |
392 | ||
393 | for (i = 0; i < 200; ++i) { | |
394 | value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); | |
395 | if (likely(!value)) | |
396 | goto writes_completed; | |
397 | if (value == IXGBE_FAILED_READ_REG) { | |
398 | ixgbe_remove_adapter(hw); | |
399 | return IXGBE_FAILED_READ_REG; | |
400 | } | |
401 | udelay(5); | |
402 | } | |
403 | ||
404 | adapter = hw->back; | |
405 | e_warn(hw, "register writes incomplete %08x\n", value); | |
406 | } | |
407 | ||
408 | writes_completed: | |
f8e2472f MR |
409 | value = readl(reg_addr + reg); |
410 | if (unlikely(value == IXGBE_FAILED_READ_REG)) | |
411 | ixgbe_check_remove(hw, reg); | |
412 | return value; | |
413 | } | |
414 | ||
14438464 MR |
415 | static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) |
416 | { | |
417 | u16 value; | |
418 | ||
419 | pci_read_config_word(pdev, PCI_VENDOR_ID, &value); | |
420 | if (value == IXGBE_FAILED_READ_CFG_WORD) { | |
421 | ixgbe_remove_adapter(hw); | |
422 | return true; | |
423 | } | |
424 | return false; | |
425 | } | |
426 | ||
427 | u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) | |
428 | { | |
429 | struct ixgbe_adapter *adapter = hw->back; | |
430 | u16 value; | |
431 | ||
432 | if (ixgbe_removed(hw->hw_addr)) | |
433 | return IXGBE_FAILED_READ_CFG_WORD; | |
434 | pci_read_config_word(adapter->pdev, reg, &value); | |
435 | if (value == IXGBE_FAILED_READ_CFG_WORD && | |
436 | ixgbe_check_cfg_remove(hw, adapter->pdev)) | |
437 | return IXGBE_FAILED_READ_CFG_WORD; | |
438 | return value; | |
439 | } | |
440 | ||
441 | #ifdef CONFIG_PCI_IOV | |
442 | static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) | |
443 | { | |
444 | struct ixgbe_adapter *adapter = hw->back; | |
445 | u32 value; | |
446 | ||
447 | if (ixgbe_removed(hw->hw_addr)) | |
448 | return IXGBE_FAILED_READ_CFG_DWORD; | |
449 | pci_read_config_dword(adapter->pdev, reg, &value); | |
450 | if (value == IXGBE_FAILED_READ_CFG_DWORD && | |
451 | ixgbe_check_cfg_remove(hw, adapter->pdev)) | |
452 | return IXGBE_FAILED_READ_CFG_DWORD; | |
453 | return value; | |
454 | } | |
455 | #endif /* CONFIG_PCI_IOV */ | |
456 | ||
ed19231c JK |
457 | void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) |
458 | { | |
459 | struct ixgbe_adapter *adapter = hw->back; | |
460 | ||
461 | if (ixgbe_removed(hw->hw_addr)) | |
462 | return; | |
463 | pci_write_config_word(adapter->pdev, reg, value); | |
464 | } | |
465 | ||
7086400d AD |
466 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) |
467 | { | |
468 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
469 | ||
52f33af8 | 470 | /* flush memory to make sure state is correct before next watchdog */ |
4e857c58 | 471 | smp_mb__before_atomic(); |
7086400d AD |
472 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); |
473 | } | |
474 | ||
dcd79aeb TI |
475 | struct ixgbe_reg_info { |
476 | u32 ofs; | |
477 | char *name; | |
478 | }; | |
479 | ||
480 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
481 | ||
482 | /* General Registers */ | |
483 | {IXGBE_CTRL, "CTRL"}, | |
484 | {IXGBE_STATUS, "STATUS"}, | |
485 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
486 | ||
487 | /* Interrupt Registers */ | |
488 | {IXGBE_EICR, "EICR"}, | |
489 | ||
490 | /* RX Registers */ | |
491 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
492 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
493 | {IXGBE_RDLEN(0), "RDLEN"}, | |
494 | {IXGBE_RDH(0), "RDH"}, | |
495 | {IXGBE_RDT(0), "RDT"}, | |
496 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
497 | {IXGBE_RDBAL(0), "RDBAL"}, | |
498 | {IXGBE_RDBAH(0), "RDBAH"}, | |
499 | ||
500 | /* TX Registers */ | |
501 | {IXGBE_TDBAL(0), "TDBAL"}, | |
502 | {IXGBE_TDBAH(0), "TDBAH"}, | |
503 | {IXGBE_TDLEN(0), "TDLEN"}, | |
504 | {IXGBE_TDH(0), "TDH"}, | |
505 | {IXGBE_TDT(0), "TDT"}, | |
506 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
507 | ||
508 | /* List Terminator */ | |
ca8dfe25 | 509 | { .name = NULL } |
dcd79aeb TI |
510 | }; |
511 | ||
512 | ||
513 | /* | |
514 | * ixgbe_regdump - register printout routine | |
515 | */ | |
516 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
517 | { | |
332f2358 | 518 | int i; |
dcd79aeb TI |
519 | char rname[16]; |
520 | u32 regs[64]; | |
521 | ||
522 | switch (reginfo->ofs) { | |
523 | case IXGBE_SRRCTL(0): | |
524 | for (i = 0; i < 64; i++) | |
525 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
526 | break; | |
527 | case IXGBE_DCA_RXCTRL(0): | |
528 | for (i = 0; i < 64; i++) | |
529 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
530 | break; | |
531 | case IXGBE_RDLEN(0): | |
532 | for (i = 0; i < 64; i++) | |
533 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
534 | break; | |
535 | case IXGBE_RDH(0): | |
536 | for (i = 0; i < 64; i++) | |
537 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
538 | break; | |
539 | case IXGBE_RDT(0): | |
540 | for (i = 0; i < 64; i++) | |
541 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
542 | break; | |
543 | case IXGBE_RXDCTL(0): | |
544 | for (i = 0; i < 64; i++) | |
545 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
546 | break; | |
547 | case IXGBE_RDBAL(0): | |
548 | for (i = 0; i < 64; i++) | |
549 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
550 | break; | |
551 | case IXGBE_RDBAH(0): | |
552 | for (i = 0; i < 64; i++) | |
553 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
554 | break; | |
555 | case IXGBE_TDBAL(0): | |
556 | for (i = 0; i < 64; i++) | |
557 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
558 | break; | |
559 | case IXGBE_TDBAH(0): | |
560 | for (i = 0; i < 64; i++) | |
561 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
562 | break; | |
563 | case IXGBE_TDLEN(0): | |
564 | for (i = 0; i < 64; i++) | |
565 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
566 | break; | |
567 | case IXGBE_TDH(0): | |
568 | for (i = 0; i < 64; i++) | |
569 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
570 | break; | |
571 | case IXGBE_TDT(0): | |
572 | for (i = 0; i < 64; i++) | |
573 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
574 | break; | |
575 | case IXGBE_TXDCTL(0): | |
576 | for (i = 0; i < 64; i++) | |
577 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
578 | break; | |
579 | default: | |
332f2358 JP |
580 | pr_info("%-15s %08x\n", |
581 | reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); | |
dcd79aeb TI |
582 | return; |
583 | } | |
584 | ||
332f2358 JP |
585 | i = 0; |
586 | while (i < 64) { | |
587 | int j; | |
588 | char buf[9 * 8 + 1]; | |
589 | char *p = buf; | |
590 | ||
591 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); | |
dcd79aeb | 592 | for (j = 0; j < 8; j++) |
332f2358 JP |
593 | p += sprintf(p, " %08x", regs[i++]); |
594 | pr_err("%-15s%s\n", rname, buf); | |
dcd79aeb TI |
595 | } |
596 | ||
597 | } | |
598 | ||
33fdc82f JF |
599 | static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) |
600 | { | |
601 | struct ixgbe_tx_buffer *tx_buffer; | |
602 | ||
603 | tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; | |
604 | pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", | |
605 | n, ring->next_to_use, ring->next_to_clean, | |
606 | (u64)dma_unmap_addr(tx_buffer, dma), | |
607 | dma_unmap_len(tx_buffer, len), | |
608 | tx_buffer->next_to_watch, | |
609 | (u64)tx_buffer->time_stamp); | |
610 | } | |
611 | ||
dcd79aeb TI |
612 | /* |
613 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
614 | */ | |
615 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
616 | { | |
617 | struct net_device *netdev = adapter->netdev; | |
618 | struct ixgbe_hw *hw = &adapter->hw; | |
619 | struct ixgbe_reg_info *reginfo; | |
620 | int n = 0; | |
33fdc82f | 621 | struct ixgbe_ring *ring; |
729739b7 | 622 | struct ixgbe_tx_buffer *tx_buffer; |
dcd79aeb TI |
623 | union ixgbe_adv_tx_desc *tx_desc; |
624 | struct my_u0 { u64 a; u64 b; } *u0; | |
625 | struct ixgbe_ring *rx_ring; | |
626 | union ixgbe_adv_rx_desc *rx_desc; | |
627 | struct ixgbe_rx_buffer *rx_buffer_info; | |
dcd79aeb TI |
628 | int i = 0; |
629 | ||
630 | if (!netif_msg_hw(adapter)) | |
631 | return; | |
632 | ||
633 | /* Print netdevice Info */ | |
634 | if (netdev) { | |
635 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 636 | pr_info("Device Name state " |
4a7c9726 TK |
637 | "trans_start\n"); |
638 | pr_info("%-15s %016lX %016lX\n", | |
c7689578 JP |
639 | netdev->name, |
640 | netdev->state, | |
4a7c9726 | 641 | dev_trans_start(netdev)); |
dcd79aeb TI |
642 | } |
643 | ||
644 | /* Print Registers */ | |
645 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 646 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
647 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
648 | reginfo->name; reginfo++) { | |
649 | ixgbe_regdump(hw, reginfo); | |
650 | } | |
651 | ||
652 | /* Print TX Ring Summary */ | |
653 | if (!netdev || !netif_running(netdev)) | |
e90dd264 | 654 | return; |
dcd79aeb TI |
655 | |
656 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
8ad88e37 JH |
657 | pr_info(" %s %s %s %s\n", |
658 | "Queue [NTU] [NTC] [bi(ntc)->dma ]", | |
659 | "leng", "ntw", "timestamp"); | |
dcd79aeb | 660 | for (n = 0; n < adapter->num_tx_queues; n++) { |
33fdc82f JF |
661 | ring = adapter->tx_ring[n]; |
662 | ixgbe_print_buffer(ring, n); | |
663 | } | |
664 | ||
665 | for (n = 0; n < adapter->num_xdp_queues; n++) { | |
666 | ring = adapter->xdp_ring[n]; | |
667 | ixgbe_print_buffer(ring, n); | |
dcd79aeb TI |
668 | } |
669 | ||
670 | /* Print TX Rings */ | |
671 | if (!netif_msg_tx_done(adapter)) | |
672 | goto rx_ring_summary; | |
673 | ||
674 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
675 | ||
676 | /* Transmit Descriptor Formats | |
677 | * | |
39ac868a | 678 | * 82598 Advanced Transmit Descriptor |
dcd79aeb TI |
679 | * +--------------------------------------------------------------+ |
680 | * 0 | Buffer Address [63:0] | | |
681 | * +--------------------------------------------------------------+ | |
39ac868a | 682 | * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | |
dcd79aeb TI |
683 | * +--------------------------------------------------------------+ |
684 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
39ac868a JH |
685 | * |
686 | * 82598 Advanced Transmit Descriptor (Write-Back Format) | |
687 | * +--------------------------------------------------------------+ | |
688 | * 0 | RSV [63:0] | | |
689 | * +--------------------------------------------------------------+ | |
690 | * 8 | RSV | STA | NXTSEQ | | |
691 | * +--------------------------------------------------------------+ | |
692 | * 63 36 35 32 31 0 | |
693 | * | |
694 | * 82599+ Advanced Transmit Descriptor | |
695 | * +--------------------------------------------------------------+ | |
696 | * 0 | Buffer Address [63:0] | | |
697 | * +--------------------------------------------------------------+ | |
698 | * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | | |
699 | * +--------------------------------------------------------------+ | |
700 | * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 | |
701 | * | |
702 | * 82599+ Advanced Transmit Descriptor (Write-Back Format) | |
703 | * +--------------------------------------------------------------+ | |
704 | * 0 | RSV [63:0] | | |
705 | * +--------------------------------------------------------------+ | |
706 | * 8 | RSV | STA | RSV | | |
707 | * +--------------------------------------------------------------+ | |
708 | * 63 36 35 32 31 0 | |
dcd79aeb TI |
709 | */ |
710 | ||
711 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
33fdc82f | 712 | ring = adapter->tx_ring[n]; |
c7689578 | 713 | pr_info("------------------------------------\n"); |
33fdc82f | 714 | pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); |
c7689578 | 715 | pr_info("------------------------------------\n"); |
8ad88e37 JH |
716 | pr_info("%s%s %s %s %s %s\n", |
717 | "T [desc] [address 63:0 ] ", | |
718 | "[PlPOIdStDDt Ln] [bi->dma ] ", | |
719 | "leng", "ntw", "timestamp", "bi->skb"); | |
dcd79aeb | 720 | |
33fdc82f JF |
721 | for (i = 0; ring->desc && (i < ring->count); i++) { |
722 | tx_desc = IXGBE_TX_DESC(ring, i); | |
723 | tx_buffer = &ring->tx_buffer_info[i]; | |
dcd79aeb | 724 | u0 = (struct my_u0 *)tx_desc; |
8ad88e37 | 725 | if (dma_unmap_len(tx_buffer, len) > 0) { |
332f2358 JP |
726 | const char *ring_desc; |
727 | ||
33fdc82f JF |
728 | if (i == ring->next_to_use && |
729 | i == ring->next_to_clean) | |
332f2358 | 730 | ring_desc = " NTC/U"; |
33fdc82f | 731 | else if (i == ring->next_to_use) |
332f2358 | 732 | ring_desc = " NTU"; |
33fdc82f | 733 | else if (i == ring->next_to_clean) |
332f2358 JP |
734 | ring_desc = " NTC"; |
735 | else | |
736 | ring_desc = ""; | |
737 | pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", | |
8ad88e37 JH |
738 | i, |
739 | le64_to_cpu(u0->a), | |
740 | le64_to_cpu(u0->b), | |
741 | (u64)dma_unmap_addr(tx_buffer, dma), | |
729739b7 | 742 | dma_unmap_len(tx_buffer, len), |
8ad88e37 JH |
743 | tx_buffer->next_to_watch, |
744 | (u64)tx_buffer->time_stamp, | |
332f2358 JP |
745 | tx_buffer->skb, |
746 | ring_desc); | |
8ad88e37 JH |
747 | |
748 | if (netif_msg_pktdata(adapter) && | |
749 | tx_buffer->skb) | |
750 | print_hex_dump(KERN_INFO, "", | |
751 | DUMP_PREFIX_ADDRESS, 16, 1, | |
752 | tx_buffer->skb->data, | |
753 | dma_unmap_len(tx_buffer, len), | |
754 | true); | |
755 | } | |
dcd79aeb TI |
756 | } |
757 | } | |
758 | ||
759 | /* Print RX Rings Summary */ | |
760 | rx_ring_summary: | |
761 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 762 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
763 | for (n = 0; n < adapter->num_rx_queues; n++) { |
764 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
765 | pr_info("%5d %5X %5X\n", |
766 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
767 | } |
768 | ||
769 | /* Print RX Rings */ | |
770 | if (!netif_msg_rx_status(adapter)) | |
e90dd264 | 771 | return; |
dcd79aeb TI |
772 | |
773 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
774 | ||
39ac868a JH |
775 | /* Receive Descriptor Formats |
776 | * | |
777 | * 82598 Advanced Receive Descriptor (Read) Format | |
dcd79aeb TI |
778 | * 63 1 0 |
779 | * +-----------------------------------------------------+ | |
780 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
781 | * +----------------------------------------------+------+ | |
782 | * 8 | Header Buffer Address [63:1] | DD | | |
783 | * +-----------------------------------------------------+ | |
784 | * | |
785 | * | |
39ac868a | 786 | * 82598 Advanced Receive Descriptor (Write-Back) Format |
dcd79aeb TI |
787 | * |
788 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
789 | * +------------------------------------------------------+ | |
39ac868a JH |
790 | * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | |
791 | * | Packet | IP | | | | Type | Type | | |
792 | * | Checksum | Ident | | | | | | | |
dcd79aeb TI |
793 | * +------------------------------------------------------+ |
794 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
795 | * +------------------------------------------------------+ | |
796 | * 63 48 47 32 31 20 19 0 | |
39ac868a JH |
797 | * |
798 | * 82599+ Advanced Receive Descriptor (Read) Format | |
799 | * 63 1 0 | |
800 | * +-----------------------------------------------------+ | |
801 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
802 | * +----------------------------------------------+------+ | |
803 | * 8 | Header Buffer Address [63:1] | DD | | |
804 | * +-----------------------------------------------------+ | |
805 | * | |
806 | * | |
807 | * 82599+ Advanced Receive Descriptor (Write-Back) Format | |
808 | * | |
809 | * 63 48 47 32 31 30 21 20 17 16 4 3 0 | |
810 | * +------------------------------------------------------+ | |
811 | * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | | |
812 | * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | | |
813 | * |/ Flow Dir Flt ID | | | | | | | |
814 | * +------------------------------------------------------+ | |
815 | * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | | |
816 | * +------------------------------------------------------+ | |
817 | * 63 48 47 32 31 20 19 0 | |
dcd79aeb | 818 | */ |
39ac868a | 819 | |
dcd79aeb TI |
820 | for (n = 0; n < adapter->num_rx_queues; n++) { |
821 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
822 | pr_info("------------------------------------\n"); |
823 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
824 | pr_info("------------------------------------\n"); | |
332f2358 | 825 | pr_info("%s%s%s\n", |
8ad88e37 JH |
826 | "R [desc] [ PktBuf A0] ", |
827 | "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", | |
332f2358 JP |
828 | "<-- Adv Rx Read format"); |
829 | pr_info("%s%s%s\n", | |
8ad88e37 JH |
830 | "RWB[desc] [PcsmIpSHl PtRs] ", |
831 | "[vl er S cks ln] ---------------- [bi->skb ] ", | |
332f2358 | 832 | "<-- Adv Rx Write-Back format"); |
dcd79aeb TI |
833 | |
834 | for (i = 0; i < rx_ring->count; i++) { | |
332f2358 JP |
835 | const char *ring_desc; |
836 | ||
837 | if (i == rx_ring->next_to_use) | |
838 | ring_desc = " NTU"; | |
839 | else if (i == rx_ring->next_to_clean) | |
840 | ring_desc = " NTC"; | |
841 | else | |
842 | ring_desc = ""; | |
843 | ||
dcd79aeb | 844 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
e4f74028 | 845 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb | 846 | u0 = (struct my_u0 *)rx_desc; |
18a8cc98 | 847 | if (rx_desc->wb.upper.length) { |
dcd79aeb | 848 | /* Descriptor Done */ |
332f2358 JP |
849 | pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", |
850 | i, | |
dcd79aeb TI |
851 | le64_to_cpu(u0->a), |
852 | le64_to_cpu(u0->b), | |
332f2358 JP |
853 | rx_buffer_info->skb, |
854 | ring_desc); | |
dcd79aeb | 855 | } else { |
332f2358 JP |
856 | pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", |
857 | i, | |
dcd79aeb TI |
858 | le64_to_cpu(u0->a), |
859 | le64_to_cpu(u0->b), | |
860 | (u64)rx_buffer_info->dma, | |
332f2358 JP |
861 | rx_buffer_info->skb, |
862 | ring_desc); | |
dcd79aeb | 863 | |
9c50c035 ET |
864 | if (netif_msg_pktdata(adapter) && |
865 | rx_buffer_info->dma) { | |
dcd79aeb TI |
866 | print_hex_dump(KERN_INFO, "", |
867 | DUMP_PREFIX_ADDRESS, 16, 1, | |
9c50c035 ET |
868 | page_address(rx_buffer_info->page) + |
869 | rx_buffer_info->page_offset, | |
f800326d | 870 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
871 | } |
872 | } | |
dcd79aeb TI |
873 | } |
874 | } | |
dcd79aeb TI |
875 | } |
876 | ||
5eba3699 AV |
877 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
878 | { | |
879 | u32 ctrl_ext; | |
880 | ||
881 | /* Let firmware take over control of h/w */ | |
882 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
883 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 884 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
885 | } |
886 | ||
887 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
888 | { | |
889 | u32 ctrl_ext; | |
890 | ||
891 | /* Let firmware know the driver has taken over */ | |
892 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
893 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 894 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 895 | } |
9a799d71 | 896 | |
49ce9c2c | 897 | /** |
e8e26350 PW |
898 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors |
899 | * @adapter: pointer to adapter struct | |
900 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
901 | * @queue: queue to map the corresponding interrupt to | |
902 | * @msix_vector: the vector to map to the corresponding queue | |
903 | * | |
904 | */ | |
905 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 906 | u8 queue, u8 msix_vector) |
9a799d71 AK |
907 | { |
908 | u32 ivar, index; | |
e8e26350 PW |
909 | struct ixgbe_hw *hw = &adapter->hw; |
910 | switch (hw->mac.type) { | |
911 | case ixgbe_mac_82598EB: | |
912 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
913 | if (direction == -1) | |
914 | direction = 0; | |
915 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
916 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
917 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
918 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
919 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
920 | break; | |
921 | case ixgbe_mac_82599EB: | |
b93a2226 | 922 | case ixgbe_mac_X540: |
9a75a1ac DS |
923 | case ixgbe_mac_X550: |
924 | case ixgbe_mac_X550EM_x: | |
49425dfc | 925 | case ixgbe_mac_x550em_a: |
e8e26350 PW |
926 | if (direction == -1) { |
927 | /* other causes */ | |
928 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
929 | index = ((queue & 1) * 8); | |
930 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
931 | ivar &= ~(0xFF << index); | |
932 | ivar |= (msix_vector << index); | |
933 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
934 | break; | |
935 | } else { | |
936 | /* tx or rx causes */ | |
937 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
938 | index = ((16 * (queue & 1)) + (8 * direction)); | |
939 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
940 | ivar &= ~(0xFF << index); | |
941 | ivar |= (msix_vector << index); | |
942 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
943 | break; | |
944 | } | |
945 | default: | |
946 | break; | |
947 | } | |
9a799d71 AK |
948 | } |
949 | ||
fe49f04a | 950 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 951 | u64 qmask) |
fe49f04a AD |
952 | { |
953 | u32 mask; | |
954 | ||
bd508178 AD |
955 | switch (adapter->hw.mac.type) { |
956 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
957 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
958 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
959 | break; |
960 | case ixgbe_mac_82599EB: | |
b93a2226 | 961 | case ixgbe_mac_X540: |
9a75a1ac DS |
962 | case ixgbe_mac_X550: |
963 | case ixgbe_mac_X550EM_x: | |
49425dfc | 964 | case ixgbe_mac_x550em_a: |
fe49f04a AD |
965 | mask = (qmask & 0xFFFFFFFF); |
966 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
967 | mask = (qmask >> 32); | |
968 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
969 | break; |
970 | default: | |
971 | break; | |
fe49f04a AD |
972 | } |
973 | } | |
974 | ||
943561d3 | 975 | static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) |
c84d324c JF |
976 | { |
977 | struct ixgbe_hw *hw = &adapter->hw; | |
978 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
c84d324c | 979 | int i; |
943561d3 | 980 | u32 data; |
c84d324c | 981 | |
943561d3 AD |
982 | if ((hw->fc.current_mode != ixgbe_fc_full) && |
983 | (hw->fc.current_mode != ixgbe_fc_rx_pause)) | |
984 | return; | |
c84d324c | 985 | |
943561d3 AD |
986 | switch (hw->mac.type) { |
987 | case ixgbe_mac_82598EB: | |
988 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
989 | break; | |
990 | default: | |
991 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
992 | } | |
993 | hwstats->lxoffrxc += data; | |
c84d324c | 994 | |
943561d3 AD |
995 | /* refill credits (no tx hang) if we received xoff */ |
996 | if (!data) | |
c84d324c | 997 | return; |
943561d3 AD |
998 | |
999 | for (i = 0; i < adapter->num_tx_queues; i++) | |
1000 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
1001 | &adapter->tx_ring[i]->state); | |
33fdc82f JF |
1002 | |
1003 | for (i = 0; i < adapter->num_xdp_queues; i++) | |
1004 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
1005 | &adapter->xdp_ring[i]->state); | |
943561d3 AD |
1006 | } |
1007 | ||
1008 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
1009 | { | |
1010 | struct ixgbe_hw *hw = &adapter->hw; | |
1011 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
1012 | u32 xoff[8] = {0}; | |
2afaa00d | 1013 | u8 tc; |
943561d3 AD |
1014 | int i; |
1015 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
1016 | ||
1017 | if (adapter->ixgbe_ieee_pfc) | |
1018 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
1019 | ||
1020 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { | |
1021 | ixgbe_update_xoff_rx_lfc(adapter); | |
c84d324c | 1022 | return; |
943561d3 | 1023 | } |
c84d324c JF |
1024 | |
1025 | /* update stats for each tc, only valid with PFC enabled */ | |
1026 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
2afaa00d PN |
1027 | u32 pxoffrxc; |
1028 | ||
c84d324c JF |
1029 | switch (hw->mac.type) { |
1030 | case ixgbe_mac_82598EB: | |
2afaa00d | 1031 | pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); |
bd508178 | 1032 | break; |
c84d324c | 1033 | default: |
2afaa00d | 1034 | pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); |
26f23d82 | 1035 | } |
2afaa00d PN |
1036 | hwstats->pxoffrxc[i] += pxoffrxc; |
1037 | /* Get the TC for given UP */ | |
1038 | tc = netdev_get_prio_tc_map(adapter->netdev, i); | |
1039 | xoff[tc] += pxoffrxc; | |
c84d324c JF |
1040 | } |
1041 | ||
1042 | /* disarm tx queues that have received xoff frames */ | |
1043 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1044 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
c84d324c | 1045 | |
2afaa00d | 1046 | tc = tx_ring->dcb_tc; |
c84d324c JF |
1047 | if (xoff[tc]) |
1048 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 1049 | } |
33fdc82f JF |
1050 | |
1051 | for (i = 0; i < adapter->num_xdp_queues; i++) { | |
1052 | struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; | |
1053 | ||
1054 | tc = xdp_ring->dcb_tc; | |
1055 | if (xoff[tc]) | |
1056 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); | |
1057 | } | |
26f23d82 YZ |
1058 | } |
1059 | ||
c84d324c | 1060 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 1061 | { |
7d7ce682 | 1062 | return ring->stats.packets; |
c84d324c JF |
1063 | } |
1064 | ||
1065 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
1066 | { | |
2a47fa45 JF |
1067 | struct ixgbe_adapter *adapter; |
1068 | struct ixgbe_hw *hw; | |
1069 | u32 head, tail; | |
1070 | ||
1071 | if (ring->l2_accel_priv) | |
1072 | adapter = ring->l2_accel_priv->real_adapter; | |
1073 | else | |
1074 | adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 1075 | |
2a47fa45 JF |
1076 | hw = &adapter->hw; |
1077 | head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); | |
1078 | tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
c84d324c JF |
1079 | |
1080 | if (head != tail) | |
1081 | return (head < tail) ? | |
1082 | tail - head : (tail + ring->count - head); | |
1083 | ||
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
1088 | { | |
1089 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
1090 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
1091 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
c84d324c | 1092 | |
7d637bcc | 1093 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
1094 | |
1095 | /* | |
1096 | * Check for a hung queue, but be thorough. This verifies | |
1097 | * that a transmit has been completed since the previous | |
1098 | * check AND there is at least one packet pending. The | |
1099 | * ARMED bit is set to indicate a potential hang. The | |
1100 | * bit is cleared if a pause frame is received to remove | |
1101 | * false hang detection due to PFC or 802.3x frames. By | |
1102 | * requiring this to fail twice we avoid races with | |
1103 | * pfc clearing the ARMED bit and conditions where we | |
1104 | * run the check_tx_hang logic with a transmit completion | |
1105 | * pending but without time to complete it yet. | |
1106 | */ | |
e90dd264 | 1107 | if (tx_done_old == tx_done && tx_pending) |
c84d324c | 1108 | /* make sure it is true for two checks in a row */ |
e90dd264 MR |
1109 | return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, |
1110 | &tx_ring->state); | |
1111 | /* update completed stats and continue */ | |
1112 | tx_ring->tx_stats.tx_done_old = tx_done; | |
1113 | /* reset the countdown */ | |
1114 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 | 1115 | |
e90dd264 | 1116 | return false; |
9a799d71 AK |
1117 | } |
1118 | ||
c83c6cbd AD |
1119 | /** |
1120 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
1121 | * @adapter: driver private struct | |
1122 | **/ | |
1123 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
1124 | { | |
1125 | ||
1126 | /* Do the reset outside of interrupt context */ | |
1127 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
57ca2a4f | 1128 | set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); |
12ff3f3b | 1129 | e_warn(drv, "initiating reset due to tx timeout\n"); |
c83c6cbd AD |
1130 | ixgbe_service_event_schedule(adapter); |
1131 | } | |
1132 | } | |
e01c31a5 | 1133 | |
c04f90e5 RP |
1134 | /** |
1135 | * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate | |
1136 | **/ | |
1137 | static int ixgbe_tx_maxrate(struct net_device *netdev, | |
1138 | int queue_index, u32 maxrate) | |
1139 | { | |
1140 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1141 | struct ixgbe_hw *hw = &adapter->hw; | |
1142 | u32 bcnrc_val = ixgbe_link_mbps(adapter); | |
1143 | ||
1144 | if (!maxrate) | |
1145 | return 0; | |
1146 | ||
1147 | /* Calculate the rate factor values to set */ | |
1148 | bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; | |
1149 | bcnrc_val /= maxrate; | |
1150 | ||
1151 | /* clear everything but the rate factor */ | |
1152 | bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | | |
1153 | IXGBE_RTTBCNRC_RF_DEC_MASK; | |
1154 | ||
1155 | /* enable the rate scheduler */ | |
1156 | bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; | |
1157 | ||
1158 | IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); | |
1159 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
9a799d71 AK |
1164 | /** |
1165 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 1166 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 1167 | * @tx_ring: tx ring to clean |
8220bbc1 | 1168 | * @napi_budget: Used to determine if we are in netpoll |
9a799d71 | 1169 | **/ |
fe49f04a | 1170 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
a3a8749d | 1171 | struct ixgbe_ring *tx_ring, int napi_budget) |
9a799d71 | 1172 | { |
fe49f04a | 1173 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
1174 | struct ixgbe_tx_buffer *tx_buffer; |
1175 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 1176 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 1177 | unsigned int budget = q_vector->tx.work_limit; |
729739b7 AD |
1178 | unsigned int i = tx_ring->next_to_clean; |
1179 | ||
1180 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
1181 | return true; | |
9a799d71 | 1182 | |
d3d00239 | 1183 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 1184 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 1185 | i -= tx_ring->count; |
12207e49 | 1186 | |
729739b7 | 1187 | do { |
d3d00239 AD |
1188 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
1189 | ||
1190 | /* if next_to_watch is not set then there is no work pending */ | |
1191 | if (!eop_desc) | |
1192 | break; | |
1193 | ||
7f83a9e6 | 1194 | /* prevent any other reads prior to eop_desc */ |
7e63bf49 | 1195 | read_barrier_depends(); |
7f83a9e6 | 1196 | |
d3d00239 AD |
1197 | /* if DD is not set pending work has not been completed */ |
1198 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
1199 | break; | |
8ad494b0 | 1200 | |
d3d00239 AD |
1201 | /* clear next_to_watch to prevent false hangs */ |
1202 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 1203 | |
091a6246 AD |
1204 | /* update the statistics for this packet */ |
1205 | total_bytes += tx_buffer->bytecount; | |
1206 | total_packets += tx_buffer->gso_segs; | |
1207 | ||
fd0db0ed | 1208 | /* free the skb */ |
33fdc82f JF |
1209 | if (ring_is_xdp(tx_ring)) |
1210 | page_frag_free(tx_buffer->data); | |
1211 | else | |
1212 | napi_consume_skb(tx_buffer->skb, napi_budget); | |
fd0db0ed | 1213 | |
729739b7 AD |
1214 | /* unmap skb header data */ |
1215 | dma_unmap_single(tx_ring->dev, | |
1216 | dma_unmap_addr(tx_buffer, dma), | |
1217 | dma_unmap_len(tx_buffer, len), | |
1218 | DMA_TO_DEVICE); | |
1219 | ||
fd0db0ed | 1220 | /* clear tx_buffer data */ |
729739b7 | 1221 | dma_unmap_len_set(tx_buffer, len, 0); |
fd0db0ed | 1222 | |
729739b7 AD |
1223 | /* unmap remaining buffers */ |
1224 | while (tx_desc != eop_desc) { | |
d3d00239 AD |
1225 | tx_buffer++; |
1226 | tx_desc++; | |
8ad494b0 | 1227 | i++; |
729739b7 AD |
1228 | if (unlikely(!i)) { |
1229 | i -= tx_ring->count; | |
d3d00239 | 1230 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 1231 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 1232 | } |
e01c31a5 | 1233 | |
729739b7 AD |
1234 | /* unmap any remaining paged data */ |
1235 | if (dma_unmap_len(tx_buffer, len)) { | |
1236 | dma_unmap_page(tx_ring->dev, | |
1237 | dma_unmap_addr(tx_buffer, dma), | |
1238 | dma_unmap_len(tx_buffer, len), | |
1239 | DMA_TO_DEVICE); | |
1240 | dma_unmap_len_set(tx_buffer, len, 0); | |
1241 | } | |
1242 | } | |
1243 | ||
1244 | /* move us one more past the eop_desc for start of next pkt */ | |
1245 | tx_buffer++; | |
1246 | tx_desc++; | |
1247 | i++; | |
1248 | if (unlikely(!i)) { | |
1249 | i -= tx_ring->count; | |
1250 | tx_buffer = tx_ring->tx_buffer_info; | |
1251 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
1252 | } | |
1253 | ||
1254 | /* issue prefetch for next Tx descriptor */ | |
1255 | prefetch(tx_desc); | |
12207e49 | 1256 | |
729739b7 AD |
1257 | /* update budget accounting */ |
1258 | budget--; | |
1259 | } while (likely(budget)); | |
1260 | ||
1261 | i += tx_ring->count; | |
9a799d71 | 1262 | tx_ring->next_to_clean = i; |
d3d00239 | 1263 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 1264 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 1265 | tx_ring->stats.packets += total_packets; |
d3d00239 | 1266 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
1267 | q_vector->tx.total_bytes += total_bytes; |
1268 | q_vector->tx.total_packets += total_packets; | |
b953799e | 1269 | |
c84d324c JF |
1270 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
1271 | /* schedule immediate reset if we believe we hung */ | |
1272 | struct ixgbe_hw *hw = &adapter->hw; | |
33fdc82f | 1273 | e_err(drv, "Detected Tx Unit Hang %s\n" |
c84d324c JF |
1274 | " Tx Queue <%d>\n" |
1275 | " TDH, TDT <%x>, <%x>\n" | |
1276 | " next_to_use <%x>\n" | |
1277 | " next_to_clean <%x>\n" | |
1278 | "tx_buffer_info[next_to_clean]\n" | |
1279 | " time_stamp <%lx>\n" | |
1280 | " jiffies <%lx>\n", | |
33fdc82f | 1281 | ring_is_xdp(tx_ring) ? "(XDP)" : "", |
c84d324c JF |
1282 | tx_ring->queue_index, |
1283 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
1284 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
1285 | tx_ring->next_to_use, i, |
1286 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c | 1287 | |
33fdc82f JF |
1288 | if (!ring_is_xdp(tx_ring)) |
1289 | netif_stop_subqueue(tx_ring->netdev, | |
1290 | tx_ring->queue_index); | |
c84d324c JF |
1291 | |
1292 | e_info(probe, | |
1293 | "tx hang %d detected on queue %d, resetting adapter\n", | |
1294 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
1295 | ||
b953799e | 1296 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 1297 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
1298 | |
1299 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 1300 | return true; |
b953799e | 1301 | } |
9a799d71 | 1302 | |
33fdc82f JF |
1303 | if (ring_is_xdp(tx_ring)) |
1304 | return !!budget; | |
1305 | ||
b2d96e0a AD |
1306 | netdev_tx_completed_queue(txring_txq(tx_ring), |
1307 | total_packets, total_bytes); | |
1308 | ||
e092be60 | 1309 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 1310 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 1311 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
1312 | /* Make sure that anybody stopping the queue after this |
1313 | * sees the new next_to_clean. | |
1314 | */ | |
1315 | smp_mb(); | |
729739b7 AD |
1316 | if (__netif_subqueue_stopped(tx_ring->netdev, |
1317 | tx_ring->queue_index) | |
1318 | && !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1319 | netif_wake_subqueue(tx_ring->netdev, | |
1320 | tx_ring->queue_index); | |
5b7da515 | 1321 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 1322 | } |
e092be60 | 1323 | } |
9a799d71 | 1324 | |
59224555 | 1325 | return !!budget; |
9a799d71 AK |
1326 | } |
1327 | ||
5dd2d332 | 1328 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
1329 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
1330 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 1331 | int cpu) |
bd0362dd | 1332 | { |
33cf09c9 | 1333 | struct ixgbe_hw *hw = &adapter->hw; |
9de7605e | 1334 | u32 txctrl = 0; |
bdda1a61 | 1335 | u16 reg_offset; |
33cf09c9 | 1336 | |
9de7605e MR |
1337 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1338 | txctrl = dca3_get_tag(tx_ring->dev, cpu); | |
1339 | ||
33cf09c9 AD |
1340 | switch (hw->mac.type) { |
1341 | case ixgbe_mac_82598EB: | |
bdda1a61 | 1342 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
1343 | break; |
1344 | case ixgbe_mac_82599EB: | |
b93a2226 | 1345 | case ixgbe_mac_X540: |
bdda1a61 AD |
1346 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
1347 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
1348 | break; |
1349 | default: | |
bdda1a61 AD |
1350 | /* for unknown hardware do not write register */ |
1351 | return; | |
bd0362dd | 1352 | } |
bdda1a61 AD |
1353 | |
1354 | /* | |
1355 | * We can enable relaxed ordering for reads, but not writes when | |
1356 | * DCA is enabled. This is due to a known issue in some chipsets | |
1357 | * which will cause the DCA tag to be cleared. | |
1358 | */ | |
1359 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
1360 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
1361 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
1362 | ||
1363 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
1364 | } |
1365 | ||
bdda1a61 AD |
1366 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
1367 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 1368 | int cpu) |
bd0362dd | 1369 | { |
33cf09c9 | 1370 | struct ixgbe_hw *hw = &adapter->hw; |
9de7605e | 1371 | u32 rxctrl = 0; |
bdda1a61 AD |
1372 | u8 reg_idx = rx_ring->reg_idx; |
1373 | ||
9de7605e MR |
1374 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1375 | rxctrl = dca3_get_tag(rx_ring->dev, cpu); | |
33cf09c9 AD |
1376 | |
1377 | switch (hw->mac.type) { | |
33cf09c9 | 1378 | case ixgbe_mac_82599EB: |
b93a2226 | 1379 | case ixgbe_mac_X540: |
bdda1a61 | 1380 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
1381 | break; |
1382 | default: | |
1383 | break; | |
1384 | } | |
bdda1a61 AD |
1385 | |
1386 | /* | |
1387 | * We can enable relaxed ordering for reads, but not writes when | |
1388 | * DCA is enabled. This is due to a known issue in some chipsets | |
1389 | * which will cause the DCA tag to be cleared. | |
1390 | */ | |
1391 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
9de7605e | 1392 | IXGBE_DCA_RXCTRL_DATA_DCA_EN | |
bdda1a61 AD |
1393 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
1394 | ||
1395 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
1396 | } |
1397 | ||
1398 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
1399 | { | |
1400 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 1401 | struct ixgbe_ring *ring; |
bd0362dd | 1402 | int cpu = get_cpu(); |
bd0362dd | 1403 | |
33cf09c9 AD |
1404 | if (q_vector->cpu == cpu) |
1405 | goto out_no_update; | |
1406 | ||
a557928e | 1407 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 1408 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 1409 | |
a557928e | 1410 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 1411 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
1412 | |
1413 | q_vector->cpu = cpu; | |
1414 | out_no_update: | |
bd0362dd JC |
1415 | put_cpu(); |
1416 | } | |
1417 | ||
1418 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
1419 | { | |
1420 | int i; | |
1421 | ||
e35ec126 | 1422 | /* always use CB2 mode, difference is masked in the CB driver */ |
9de7605e MR |
1423 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1424 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, | |
1425 | IXGBE_DCA_CTRL_DCA_MODE_CB2); | |
1426 | else | |
1427 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, | |
1428 | IXGBE_DCA_CTRL_DCA_DISABLE); | |
e35ec126 | 1429 | |
49c7ffbe | 1430 | for (i = 0; i < adapter->num_q_vectors; i++) { |
33cf09c9 AD |
1431 | adapter->q_vector[i]->cpu = -1; |
1432 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1433 | } |
1434 | } | |
1435 | ||
1436 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1437 | { | |
c60fbb00 | 1438 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1439 | unsigned long event = *(unsigned long *)data; |
1440 | ||
2a72c31e | 1441 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
1442 | return 0; |
1443 | ||
bd0362dd JC |
1444 | switch (event) { |
1445 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1446 | /* if we're already enabled, don't do it again */ |
1447 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1448 | break; | |
652f093f | 1449 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1450 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
9de7605e MR |
1451 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, |
1452 | IXGBE_DCA_CTRL_DCA_MODE_CB2); | |
bd0362dd JC |
1453 | break; |
1454 | } | |
93df9465 | 1455 | /* fall through - DCA is disabled. */ |
bd0362dd JC |
1456 | case DCA_PROVIDER_REMOVE: |
1457 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1458 | dca_remove_requester(dev); | |
1459 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
9de7605e MR |
1460 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, |
1461 | IXGBE_DCA_CTRL_DCA_DISABLE); | |
bd0362dd JC |
1462 | } |
1463 | break; | |
1464 | } | |
1465 | ||
652f093f | 1466 | return 0; |
bd0362dd | 1467 | } |
67a74ee2 | 1468 | |
bdda1a61 | 1469 | #endif /* CONFIG_IXGBE_DCA */ |
7edda4b8 FD |
1470 | |
1471 | #define IXGBE_RSS_L4_TYPES_MASK \ | |
1472 | ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ | |
1473 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ | |
1474 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ | |
1475 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) | |
1476 | ||
8a0da21b AD |
1477 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
1478 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
1479 | struct sk_buff *skb) |
1480 | { | |
7edda4b8 FD |
1481 | u16 rss_type; |
1482 | ||
1483 | if (!(ring->netdev->features & NETIF_F_RXHASH)) | |
1484 | return; | |
1485 | ||
1486 | rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & | |
1487 | IXGBE_RXDADV_RSSTYPE_MASK; | |
1488 | ||
1489 | if (!rss_type) | |
1490 | return; | |
1491 | ||
1492 | skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), | |
1493 | (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? | |
1494 | PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); | |
67a74ee2 ET |
1495 | } |
1496 | ||
f800326d | 1497 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1498 | /** |
1499 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
57efd44c | 1500 | * @ring: structure containing ring specific data |
ff886dfc AD |
1501 | * @rx_desc: advanced rx descriptor |
1502 | * | |
1503 | * Returns : true if it is FCoE pkt | |
1504 | */ | |
57efd44c | 1505 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, |
ff886dfc AD |
1506 | union ixgbe_adv_rx_desc *rx_desc) |
1507 | { | |
1508 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1509 | ||
57efd44c | 1510 | return test_bit(__IXGBE_RX_FCOE, &ring->state) && |
ff886dfc AD |
1511 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == |
1512 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1513 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1514 | } | |
1515 | ||
f800326d | 1516 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1517 | /** |
1518 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1519 | * @ring: structure containing ring specific data |
1520 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1521 | * @skb: skb currently being received and modified |
1522 | **/ | |
8a0da21b | 1523 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1524 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1525 | struct sk_buff *skb) |
9a799d71 | 1526 | { |
3f207800 | 1527 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
3f207800 DS |
1528 | bool encap_pkt = false; |
1529 | ||
8a0da21b | 1530 | skb_checksum_none_assert(skb); |
9a799d71 | 1531 | |
712744be | 1532 | /* Rx csum disabled */ |
8a0da21b | 1533 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1534 | return; |
e59bd25d | 1535 | |
a21d0822 ET |
1536 | /* check for VXLAN and Geneve packets */ |
1537 | if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { | |
3f207800 DS |
1538 | encap_pkt = true; |
1539 | skb->encapsulation = 1; | |
3f207800 DS |
1540 | } |
1541 | ||
e59bd25d | 1542 | /* if IP and error */ |
f56e0cb1 AD |
1543 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1544 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1545 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1546 | return; |
1547 | } | |
e59bd25d | 1548 | |
f56e0cb1 | 1549 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1550 | return; |
1551 | ||
f56e0cb1 | 1552 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
8bae1b2b DS |
1553 | /* |
1554 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1555 | * checksum errors. | |
1556 | */ | |
8a0da21b AD |
1557 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1558 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1559 | return; |
1560 | ||
8a0da21b | 1561 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1562 | return; |
1563 | } | |
1564 | ||
9a799d71 | 1565 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1566 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
3f207800 DS |
1567 | if (encap_pkt) { |
1568 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) | |
1569 | return; | |
1570 | ||
1571 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { | |
d469251b | 1572 | skb->ip_summed = CHECKSUM_NONE; |
3f207800 DS |
1573 | return; |
1574 | } | |
1575 | /* If we checked the outer header let the stack know */ | |
1576 | skb->csum_level = 1; | |
1577 | } | |
9a799d71 AK |
1578 | } |
1579 | ||
2de6aa3a AD |
1580 | static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) |
1581 | { | |
1582 | return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; | |
1583 | } | |
1584 | ||
f990b79b AD |
1585 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1586 | struct ixgbe_rx_buffer *bi) | |
1587 | { | |
1588 | struct page *page = bi->page; | |
18cb652a | 1589 | dma_addr_t dma; |
f990b79b | 1590 | |
f800326d | 1591 | /* since we are recycling buffers we should seldom need to alloc */ |
18cb652a | 1592 | if (likely(page)) |
f990b79b AD |
1593 | return true; |
1594 | ||
f800326d | 1595 | /* alloc new page for storage */ |
18cb652a AD |
1596 | page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); |
1597 | if (unlikely(!page)) { | |
1598 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1599 | return false; | |
f990b79b AD |
1600 | } |
1601 | ||
f800326d | 1602 | /* map page for use */ |
f3213d93 AD |
1603 | dma = dma_map_page_attrs(rx_ring->dev, page, 0, |
1604 | ixgbe_rx_pg_size(rx_ring), | |
1605 | DMA_FROM_DEVICE, | |
1606 | IXGBE_RX_DMA_ATTR); | |
f800326d AD |
1607 | |
1608 | /* | |
1609 | * if mapping failed free memory back to system since | |
1610 | * there isn't much point in holding memory we can't use | |
1611 | */ | |
1612 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
dd411ec4 | 1613 | __free_pages(page, ixgbe_rx_pg_order(rx_ring)); |
f990b79b | 1614 | |
f990b79b AD |
1615 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1616 | return false; | |
1617 | } | |
1618 | ||
f800326d | 1619 | bi->dma = dma; |
18cb652a | 1620 | bi->page = page; |
2de6aa3a | 1621 | bi->page_offset = ixgbe_rx_offset(rx_ring); |
1b56cf49 | 1622 | bi->pagecnt_bias = 1; |
f800326d | 1623 | |
f990b79b AD |
1624 | return true; |
1625 | } | |
1626 | ||
9a799d71 | 1627 | /** |
f990b79b | 1628 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1629 | * @rx_ring: ring to place buffers on |
1630 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1631 | **/ |
fc77dc3c | 1632 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1633 | { |
9a799d71 | 1634 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1635 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1636 | u16 i = rx_ring->next_to_use; |
4f4542bf | 1637 | u16 bufsz; |
9a799d71 | 1638 | |
f800326d AD |
1639 | /* nothing to do */ |
1640 | if (!cleaned_count) | |
fc77dc3c AD |
1641 | return; |
1642 | ||
e4f74028 | 1643 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1644 | bi = &rx_ring->rx_buffer_info[i]; |
1645 | i -= rx_ring->count; | |
9a799d71 | 1646 | |
4f4542bf AD |
1647 | bufsz = ixgbe_rx_bufsz(rx_ring); |
1648 | ||
f800326d AD |
1649 | do { |
1650 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1651 | break; |
d5f398ed | 1652 | |
f3213d93 AD |
1653 | /* sync the buffer for use by the device */ |
1654 | dma_sync_single_range_for_device(rx_ring->dev, bi->dma, | |
4f4542bf | 1655 | bi->page_offset, bufsz, |
f3213d93 AD |
1656 | DMA_FROM_DEVICE); |
1657 | ||
f800326d AD |
1658 | /* |
1659 | * Refresh the desc even if buffer_addrs didn't change | |
1660 | * because each write-back erases this info. | |
1661 | */ | |
1662 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1663 | |
f990b79b AD |
1664 | rx_desc++; |
1665 | bi++; | |
9a799d71 | 1666 | i++; |
f990b79b | 1667 | if (unlikely(!i)) { |
e4f74028 | 1668 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1669 | bi = rx_ring->rx_buffer_info; |
1670 | i -= rx_ring->count; | |
1671 | } | |
1672 | ||
c3630cc4 AD |
1673 | /* clear the length for the next_to_use descriptor */ |
1674 | rx_desc->wb.upper.length = 0; | |
f800326d AD |
1675 | |
1676 | cleaned_count--; | |
1677 | } while (cleaned_count); | |
7c6e0a43 | 1678 | |
f990b79b AD |
1679 | i += rx_ring->count; |
1680 | ||
ad435ec6 AD |
1681 | if (rx_ring->next_to_use != i) { |
1682 | rx_ring->next_to_use = i; | |
1683 | ||
1684 | /* update next to alloc since we have filled the ring */ | |
1685 | rx_ring->next_to_alloc = i; | |
1686 | ||
1687 | /* Force memory writes to complete before letting h/w | |
1688 | * know there are new descriptors to fetch. (Only | |
1689 | * applicable for weak-ordered memory model archs, | |
1690 | * such as IA-64). | |
1691 | */ | |
1692 | wmb(); | |
1693 | writel(i, rx_ring->tail); | |
1694 | } | |
9a799d71 AK |
1695 | } |
1696 | ||
1d2024f6 AD |
1697 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1698 | struct sk_buff *skb) | |
1699 | { | |
f800326d | 1700 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1701 | |
1702 | /* set gso_size to avoid messing up TCP MSS */ | |
1703 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1704 | IXGBE_CB(skb)->append_cnt); | |
96be80ab | 1705 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; |
1d2024f6 AD |
1706 | } |
1707 | ||
1708 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1709 | struct sk_buff *skb) | |
1710 | { | |
1711 | /* if append_cnt is 0 then frame is not RSC */ | |
1712 | if (!IXGBE_CB(skb)->append_cnt) | |
1713 | return; | |
1714 | ||
1715 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1716 | rx_ring->rx_stats.rsc_flush++; | |
1717 | ||
1718 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1719 | ||
1720 | /* gso_size is computed using append_cnt so always clear it last */ | |
1721 | IXGBE_CB(skb)->append_cnt = 0; | |
1722 | } | |
1723 | ||
8a0da21b AD |
1724 | /** |
1725 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1726 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1727 | * @rx_desc: pointer to the EOP Rx descriptor | |
1728 | * @skb: pointer to current skb being populated | |
f8212f97 | 1729 | * |
8a0da21b AD |
1730 | * This function checks the ring, descriptor, and packet information in |
1731 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1732 | * other fields within the skb. | |
f8212f97 | 1733 | **/ |
8a0da21b AD |
1734 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1735 | union ixgbe_adv_rx_desc *rx_desc, | |
1736 | struct sk_buff *skb) | |
f8212f97 | 1737 | { |
43e95f11 | 1738 | struct net_device *dev = rx_ring->netdev; |
a9763f3c | 1739 | u32 flags = rx_ring->q_vector->adapter->flags; |
43e95f11 | 1740 | |
8a0da21b AD |
1741 | ixgbe_update_rsc_stats(rx_ring, skb); |
1742 | ||
1743 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1744 | |
8a0da21b AD |
1745 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1746 | ||
a9763f3c MR |
1747 | if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) |
1748 | ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); | |
3a6a4eda | 1749 | |
f646968f | 1750 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
43e95f11 | 1751 | ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { |
8a0da21b | 1752 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); |
86a9bad3 | 1753 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); |
f8212f97 AD |
1754 | } |
1755 | ||
8a0da21b | 1756 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1757 | |
43e95f11 | 1758 | skb->protocol = eth_type_trans(skb, dev); |
f8212f97 AD |
1759 | } |
1760 | ||
8a0da21b AD |
1761 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1762 | struct sk_buff *skb) | |
aa80175a | 1763 | { |
3ffc1af5 | 1764 | napi_gro_receive(&q_vector->napi, skb); |
aa80175a | 1765 | } |
43634e82 | 1766 | |
f800326d AD |
1767 | /** |
1768 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1769 | * @rx_ring: Rx ring being processed | |
1770 | * @rx_desc: Rx descriptor for current buffer | |
1771 | * @skb: Current socket buffer containing buffer in progress | |
1772 | * | |
1773 | * This function updates next to clean. If the buffer is an EOP buffer | |
1774 | * this function exits returning false, otherwise it will place the | |
1775 | * sk_buff in the next buffer to be chained and return true indicating | |
1776 | * that this is in fact a non-EOP buffer. | |
1777 | **/ | |
1778 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1779 | union ixgbe_adv_rx_desc *rx_desc, | |
1780 | struct sk_buff *skb) | |
1781 | { | |
1782 | u32 ntc = rx_ring->next_to_clean + 1; | |
1783 | ||
1784 | /* fetch, update, and store next to clean */ | |
1785 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1786 | rx_ring->next_to_clean = ntc; | |
1787 | ||
1788 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1789 | ||
5a02cbd1 AD |
1790 | /* update RSC append count if present */ |
1791 | if (ring_is_rsc_enabled(rx_ring)) { | |
1792 | __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1793 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1794 | ||
1795 | if (unlikely(rsc_enabled)) { | |
1796 | u32 rsc_cnt = le32_to_cpu(rsc_enabled); | |
1797 | ||
1798 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1799 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
f800326d | 1800 | |
5a02cbd1 AD |
1801 | /* update ntc based on RSC value */ |
1802 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1803 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1804 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1805 | } | |
f800326d AD |
1806 | } |
1807 | ||
5a02cbd1 AD |
1808 | /* if we are the last buffer then there is nothing else to do */ |
1809 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1810 | return false; | |
1811 | ||
f800326d AD |
1812 | /* place skb in next buffer to be received */ |
1813 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1814 | rx_ring->rx_stats.non_eop_descs++; | |
1815 | ||
1816 | return true; | |
1817 | } | |
1818 | ||
19861ce2 AD |
1819 | /** |
1820 | * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail | |
1821 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1822 | * @skb: pointer to current skb being adjusted | |
1823 | * | |
1824 | * This function is an ixgbe specific version of __pskb_pull_tail. The | |
1825 | * main difference between this version and the original function is that | |
1826 | * this function can make several assumptions about the state of things | |
1827 | * that allow for significant optimizations versus the standard function. | |
1828 | * As a result we can do things like drop a frag and maintain an accurate | |
1829 | * truesize for the skb. | |
1830 | */ | |
1831 | static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, | |
1832 | struct sk_buff *skb) | |
1833 | { | |
1834 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1835 | unsigned char *va; | |
1836 | unsigned int pull_len; | |
1837 | ||
1838 | /* | |
1839 | * it is valid to use page_address instead of kmap since we are | |
1840 | * working with pages allocated out of the lomem pool per | |
1841 | * alloc_page(GFP_ATOMIC) | |
1842 | */ | |
1843 | va = skb_frag_address(frag); | |
1844 | ||
1845 | /* | |
1846 | * we need the header to contain the greater of either ETH_HLEN or | |
1847 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1848 | */ | |
8496e338 | 1849 | pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); |
19861ce2 AD |
1850 | |
1851 | /* align pull length to size of long to optimize memcpy performance */ | |
1852 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1853 | ||
1854 | /* update all of the pointers */ | |
1855 | skb_frag_size_sub(frag, pull_len); | |
1856 | frag->page_offset += pull_len; | |
1857 | skb->data_len -= pull_len; | |
1858 | skb->tail += pull_len; | |
19861ce2 AD |
1859 | } |
1860 | ||
42073d91 AD |
1861 | /** |
1862 | * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB | |
1863 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1864 | * @skb: pointer to current skb being updated | |
1865 | * | |
1866 | * This function provides a basic DMA sync up for the first fragment of an | |
1867 | * skb. The reason for doing this is that the first fragment cannot be | |
1868 | * unmapped until we have reached the end of packet descriptor for a buffer | |
1869 | * chain. | |
1870 | */ | |
1871 | static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, | |
1872 | struct sk_buff *skb) | |
1873 | { | |
1874 | /* if the page was released unmap it, else just sync our portion */ | |
1875 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
f3213d93 AD |
1876 | dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, |
1877 | ixgbe_rx_pg_size(rx_ring), | |
1878 | DMA_FROM_DEVICE, | |
1879 | IXGBE_RX_DMA_ATTR); | |
42073d91 AD |
1880 | } else { |
1881 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1882 | ||
1883 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1884 | IXGBE_CB(skb)->dma, | |
1885 | frag->page_offset, | |
f215af8c | 1886 | skb_frag_size(frag), |
42073d91 AD |
1887 | DMA_FROM_DEVICE); |
1888 | } | |
42073d91 AD |
1889 | } |
1890 | ||
f800326d AD |
1891 | /** |
1892 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1893 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1894 | * @rx_desc: pointer to the EOP Rx descriptor | |
1895 | * @skb: pointer to current skb being fixed | |
1896 | * | |
92470808 JF |
1897 | * Check if the skb is valid in the XDP case it will be an error pointer. |
1898 | * Return true in this case to abort processing and advance to next | |
1899 | * descriptor. | |
1900 | * | |
f800326d AD |
1901 | * Check for corrupted packet headers caused by senders on the local L2 |
1902 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1903 | * should be very rare. | |
1904 | * | |
1905 | * Also address the case where we are pulling data in on pages only | |
1906 | * and as such no data is present in the skb header. | |
1907 | * | |
1908 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1909 | * it is large enough to qualify as a valid Ethernet frame. | |
1910 | * | |
1911 | * Returns true if an error was encountered and skb was freed. | |
1912 | **/ | |
1913 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1914 | union ixgbe_adv_rx_desc *rx_desc, | |
1915 | struct sk_buff *skb) | |
1916 | { | |
f800326d | 1917 | struct net_device *netdev = rx_ring->netdev; |
f800326d | 1918 | |
92470808 JF |
1919 | /* XDP packets use error pointer so abort at this point */ |
1920 | if (IS_ERR(skb)) | |
1921 | return true; | |
1922 | ||
f800326d AD |
1923 | /* verify that the packet does not have any known errors */ |
1924 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1925 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1926 | !(netdev->features & NETIF_F_RXALL))) { | |
1927 | dev_kfree_skb_any(skb); | |
1928 | return true; | |
1929 | } | |
1930 | ||
19861ce2 | 1931 | /* place header in linear portion of buffer */ |
6f429223 | 1932 | if (!skb_headlen(skb)) |
cf3fe7ac | 1933 | ixgbe_pull_tail(rx_ring, skb); |
f800326d | 1934 | |
57efd44c AD |
1935 | #ifdef IXGBE_FCOE |
1936 | /* do not attempt to pad FCoE Frames as this will disrupt DDP */ | |
1937 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) | |
1938 | return false; | |
1939 | ||
1940 | #endif | |
a94d9e22 AD |
1941 | /* if eth_skb_pad returns an error the skb was freed */ |
1942 | if (eth_skb_pad(skb)) | |
1943 | return true; | |
f800326d AD |
1944 | |
1945 | return false; | |
1946 | } | |
1947 | ||
f800326d AD |
1948 | /** |
1949 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1950 | * @rx_ring: rx descriptor ring to store buffers on | |
1951 | * @old_buff: donor buffer to have page reused | |
1952 | * | |
0549ae20 | 1953 | * Synchronizes page for reuse by the adapter |
f800326d AD |
1954 | **/ |
1955 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1956 | struct ixgbe_rx_buffer *old_buff) | |
1957 | { | |
1958 | struct ixgbe_rx_buffer *new_buff; | |
1959 | u16 nta = rx_ring->next_to_alloc; | |
f800326d AD |
1960 | |
1961 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1962 | ||
1963 | /* update, and store next to alloc */ | |
1964 | nta++; | |
1965 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1966 | ||
3fd21876 AD |
1967 | /* Transfer page from old buffer to new buffer. |
1968 | * Move each member individually to avoid possible store | |
1969 | * forwarding stalls and unnecessary copy of skb. | |
1970 | */ | |
1971 | new_buff->dma = old_buff->dma; | |
1972 | new_buff->page = old_buff->page; | |
1973 | new_buff->page_offset = old_buff->page_offset; | |
1974 | new_buff->pagecnt_bias = old_buff->pagecnt_bias; | |
f800326d AD |
1975 | } |
1976 | ||
18cb652a AD |
1977 | static inline bool ixgbe_page_is_reserved(struct page *page) |
1978 | { | |
2f064f34 | 1979 | return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); |
18cb652a AD |
1980 | } |
1981 | ||
3fd21876 | 1982 | static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) |
af43da0d | 1983 | { |
3fd21876 AD |
1984 | unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; |
1985 | struct page *page = rx_buffer->page; | |
1b56cf49 | 1986 | |
af43da0d AD |
1987 | /* avoid re-using remote pages */ |
1988 | if (unlikely(ixgbe_page_is_reserved(page))) | |
1989 | return false; | |
1990 | ||
1991 | #if (PAGE_SIZE < 8192) | |
1992 | /* if we are only owner of page we can reuse it */ | |
3fd21876 | 1993 | if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) |
af43da0d | 1994 | return false; |
af43da0d | 1995 | #else |
3fd21876 AD |
1996 | /* The last offset is a bit aggressive in that we assume the |
1997 | * worst case of FCoE being enabled and using a 3K buffer. | |
1998 | * However this should have minimal impact as the 1K extra is | |
1999 | * still less than one buffer in size. | |
2000 | */ | |
2001 | #define IXGBE_LAST_OFFSET \ | |
2002 | (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) | |
2003 | if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) | |
af43da0d AD |
2004 | return false; |
2005 | #endif | |
2006 | ||
1b56cf49 AD |
2007 | /* If we have drained the page fragment pool we need to update |
2008 | * the pagecnt_bias and page count so that we fully restock the | |
2009 | * number of references the driver holds. | |
af43da0d | 2010 | */ |
3fd21876 | 2011 | if (unlikely(!pagecnt_bias)) { |
1b56cf49 AD |
2012 | page_ref_add(page, USHRT_MAX); |
2013 | rx_buffer->pagecnt_bias = USHRT_MAX; | |
2014 | } | |
af43da0d AD |
2015 | |
2016 | return true; | |
2017 | } | |
2018 | ||
f800326d AD |
2019 | /** |
2020 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
2021 | * @rx_ring: rx descriptor ring to transact packets on | |
2022 | * @rx_buffer: buffer containing page to add | |
2023 | * @rx_desc: descriptor containing length of buffer written by hardware | |
2024 | * @skb: sk_buff to place the data into | |
2025 | * | |
0549ae20 AD |
2026 | * This function will add the data contained in rx_buffer->page to the skb. |
2027 | * This is done either through a direct copy if the data in the buffer is | |
2028 | * less than the skb header size, otherwise it will just attach the page as | |
2029 | * a frag to the skb. | |
2030 | * | |
2031 | * The function will then update the page offset if necessary and return | |
2032 | * true if the buffer can be reused by the adapter. | |
f800326d | 2033 | **/ |
3fd21876 | 2034 | static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, |
f800326d | 2035 | struct ixgbe_rx_buffer *rx_buffer, |
3fd21876 AD |
2036 | struct sk_buff *skb, |
2037 | unsigned int size) | |
f800326d | 2038 | { |
09816fbe | 2039 | #if (PAGE_SIZE < 8192) |
4f4542bf | 2040 | unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; |
09816fbe | 2041 | #else |
2de6aa3a AD |
2042 | unsigned int truesize = ring_uses_build_skb(rx_ring) ? |
2043 | SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : | |
2044 | SKB_DATA_ALIGN(size); | |
09816fbe | 2045 | #endif |
3fd21876 | 2046 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, |
0549ae20 | 2047 | rx_buffer->page_offset, size, truesize); |
3fd21876 AD |
2048 | #if (PAGE_SIZE < 8192) |
2049 | rx_buffer->page_offset ^= truesize; | |
2050 | #else | |
2051 | rx_buffer->page_offset += truesize; | |
2052 | #endif | |
f800326d AD |
2053 | } |
2054 | ||
3fd21876 AD |
2055 | static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, |
2056 | union ixgbe_adv_rx_desc *rx_desc, | |
2057 | struct sk_buff **skb, | |
2058 | const unsigned int size) | |
18806c9e AD |
2059 | { |
2060 | struct ixgbe_rx_buffer *rx_buffer; | |
18806c9e AD |
2061 | |
2062 | rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; | |
3fd21876 AD |
2063 | prefetchw(rx_buffer->page); |
2064 | *skb = rx_buffer->skb; | |
18806c9e | 2065 | |
3fd21876 AD |
2066 | /* Delay unmapping of the first packet. It carries the header |
2067 | * information, HW may still access the header after the writeback. | |
2068 | * Only unmap it when EOP is reached | |
2069 | */ | |
2070 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { | |
2071 | if (!*skb) | |
2072 | goto skip_sync; | |
18806c9e | 2073 | } else { |
3fd21876 AD |
2074 | if (*skb) |
2075 | ixgbe_dma_sync_frag(rx_ring, *skb); | |
2076 | } | |
18806c9e | 2077 | |
3fd21876 AD |
2078 | /* we are reusing so sync this buffer for CPU use */ |
2079 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
2080 | rx_buffer->dma, | |
2081 | rx_buffer->page_offset, | |
2082 | size, | |
2083 | DMA_FROM_DEVICE); | |
2084 | skip_sync: | |
2085 | rx_buffer->pagecnt_bias--; | |
18cb652a | 2086 | |
3fd21876 AD |
2087 | return rx_buffer; |
2088 | } | |
18806c9e | 2089 | |
3fd21876 AD |
2090 | static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, |
2091 | struct ixgbe_rx_buffer *rx_buffer, | |
2092 | struct sk_buff *skb) | |
2093 | { | |
2094 | if (ixgbe_can_reuse_rx_page(rx_buffer)) { | |
18806c9e AD |
2095 | /* hand second half of page back to the ring */ |
2096 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
18806c9e | 2097 | } else { |
92470808 | 2098 | if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { |
1b56cf49 AD |
2099 | /* the page has been released from the ring */ |
2100 | IXGBE_CB(skb)->page_released = true; | |
2101 | } else { | |
2102 | /* we are not reusing the buffer so unmap it */ | |
2103 | dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, | |
2104 | ixgbe_rx_pg_size(rx_ring), | |
2105 | DMA_FROM_DEVICE, | |
2106 | IXGBE_RX_DMA_ATTR); | |
2107 | } | |
3fd21876 | 2108 | __page_frag_cache_drain(rx_buffer->page, |
1b56cf49 | 2109 | rx_buffer->pagecnt_bias); |
18806c9e AD |
2110 | } |
2111 | ||
3fd21876 | 2112 | /* clear contents of rx_buffer */ |
18806c9e | 2113 | rx_buffer->page = NULL; |
3fd21876 AD |
2114 | rx_buffer->skb = NULL; |
2115 | } | |
2116 | ||
2117 | static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, | |
2118 | struct ixgbe_rx_buffer *rx_buffer, | |
92470808 JF |
2119 | struct xdp_buff *xdp, |
2120 | union ixgbe_adv_rx_desc *rx_desc) | |
3fd21876 | 2121 | { |
92470808 | 2122 | unsigned int size = xdp->data_end - xdp->data; |
3fd21876 AD |
2123 | #if (PAGE_SIZE < 8192) |
2124 | unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; | |
2125 | #else | |
92470808 JF |
2126 | unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - |
2127 | xdp->data_hard_start); | |
3fd21876 AD |
2128 | #endif |
2129 | struct sk_buff *skb; | |
2130 | ||
2131 | /* prefetch first cache line of first page */ | |
92470808 | 2132 | prefetch(xdp->data); |
3fd21876 | 2133 | #if L1_CACHE_BYTES < 128 |
92470808 | 2134 | prefetch(xdp->data + L1_CACHE_BYTES); |
3fd21876 AD |
2135 | #endif |
2136 | ||
2137 | /* allocate a skb to store the frags */ | |
2138 | skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); | |
2139 | if (unlikely(!skb)) | |
2140 | return NULL; | |
2141 | ||
2142 | if (size > IXGBE_RX_HDR_SIZE) { | |
2143 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) | |
2144 | IXGBE_CB(skb)->dma = rx_buffer->dma; | |
2145 | ||
2146 | skb_add_rx_frag(skb, 0, rx_buffer->page, | |
92470808 | 2147 | xdp->data - page_address(rx_buffer->page), |
3fd21876 AD |
2148 | size, truesize); |
2149 | #if (PAGE_SIZE < 8192) | |
2150 | rx_buffer->page_offset ^= truesize; | |
2151 | #else | |
2152 | rx_buffer->page_offset += truesize; | |
2153 | #endif | |
2154 | } else { | |
92470808 JF |
2155 | memcpy(__skb_put(skb, size), |
2156 | xdp->data, ALIGN(size, sizeof(long))); | |
3fd21876 AD |
2157 | rx_buffer->pagecnt_bias++; |
2158 | } | |
18806c9e AD |
2159 | |
2160 | return skb; | |
f800326d AD |
2161 | } |
2162 | ||
6f429223 AD |
2163 | static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, |
2164 | struct ixgbe_rx_buffer *rx_buffer, | |
92470808 JF |
2165 | struct xdp_buff *xdp, |
2166 | union ixgbe_adv_rx_desc *rx_desc) | |
6f429223 | 2167 | { |
6f429223 AD |
2168 | #if (PAGE_SIZE < 8192) |
2169 | unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; | |
2170 | #else | |
2171 | unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + | |
92470808 JF |
2172 | SKB_DATA_ALIGN(xdp->data_end - |
2173 | xdp->data_hard_start); | |
6f429223 AD |
2174 | #endif |
2175 | struct sk_buff *skb; | |
2176 | ||
2177 | /* prefetch first cache line of first page */ | |
92470808 | 2178 | prefetch(xdp->data); |
6f429223 | 2179 | #if L1_CACHE_BYTES < 128 |
92470808 | 2180 | prefetch(xdp->data + L1_CACHE_BYTES); |
6f429223 AD |
2181 | #endif |
2182 | ||
92470808 JF |
2183 | /* build an skb to around the page buffer */ |
2184 | skb = build_skb(xdp->data_hard_start, truesize); | |
6f429223 AD |
2185 | if (unlikely(!skb)) |
2186 | return NULL; | |
2187 | ||
2188 | /* update pointers within the skb to store the data */ | |
92470808 JF |
2189 | skb_reserve(skb, xdp->data - xdp->data_hard_start); |
2190 | __skb_put(skb, xdp->data_end - xdp->data); | |
6f429223 AD |
2191 | |
2192 | /* record DMA address if this is the start of a chain of buffers */ | |
2193 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) | |
2194 | IXGBE_CB(skb)->dma = rx_buffer->dma; | |
2195 | ||
2196 | /* update buffer offset */ | |
2197 | #if (PAGE_SIZE < 8192) | |
2198 | rx_buffer->page_offset ^= truesize; | |
2199 | #else | |
2200 | rx_buffer->page_offset += truesize; | |
2201 | #endif | |
2202 | ||
2203 | return skb; | |
2204 | } | |
2205 | ||
92470808 JF |
2206 | #define IXGBE_XDP_PASS 0 |
2207 | #define IXGBE_XDP_CONSUMED 1 | |
33fdc82f | 2208 | #define IXGBE_XDP_TX 2 |
92470808 | 2209 | |
33fdc82f JF |
2210 | static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, |
2211 | struct xdp_buff *xdp); | |
2212 | ||
2213 | static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, | |
2214 | struct ixgbe_ring *rx_ring, | |
92470808 JF |
2215 | struct xdp_buff *xdp) |
2216 | { | |
2217 | int result = IXGBE_XDP_PASS; | |
2218 | struct bpf_prog *xdp_prog; | |
2219 | u32 act; | |
2220 | ||
2221 | rcu_read_lock(); | |
2222 | xdp_prog = READ_ONCE(rx_ring->xdp_prog); | |
2223 | ||
2224 | if (!xdp_prog) | |
2225 | goto xdp_out; | |
2226 | ||
2227 | act = bpf_prog_run_xdp(xdp_prog, xdp); | |
2228 | switch (act) { | |
2229 | case XDP_PASS: | |
2230 | break; | |
33fdc82f JF |
2231 | case XDP_TX: |
2232 | result = ixgbe_xmit_xdp_ring(adapter, xdp); | |
2233 | break; | |
92470808 JF |
2234 | default: |
2235 | bpf_warn_invalid_xdp_action(act); | |
93df9465 | 2236 | /* fallthrough */ |
92470808 JF |
2237 | case XDP_ABORTED: |
2238 | trace_xdp_exception(rx_ring->netdev, xdp_prog, act); | |
2239 | /* fallthrough -- handle aborts by dropping packet */ | |
2240 | case XDP_DROP: | |
2241 | result = IXGBE_XDP_CONSUMED; | |
2242 | break; | |
2243 | } | |
2244 | xdp_out: | |
2245 | rcu_read_unlock(); | |
2246 | return ERR_PTR(-result); | |
2247 | } | |
2248 | ||
33fdc82f JF |
2249 | static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, |
2250 | struct ixgbe_rx_buffer *rx_buffer, | |
2251 | unsigned int size) | |
2252 | { | |
2253 | #if (PAGE_SIZE < 8192) | |
2254 | unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; | |
2255 | ||
2256 | rx_buffer->page_offset ^= truesize; | |
2257 | #else | |
2258 | unsigned int truesize = ring_uses_build_skb(rx_ring) ? | |
2259 | SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : | |
2260 | SKB_DATA_ALIGN(size); | |
2261 | ||
2262 | rx_buffer->page_offset += truesize; | |
2263 | #endif | |
2264 | } | |
2265 | ||
f800326d AD |
2266 | /** |
2267 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
2268 | * @q_vector: structure containing interrupt and ring information | |
2269 | * @rx_ring: rx descriptor ring to transact packets on | |
2270 | * @budget: Total limit on number of packets to process | |
2271 | * | |
2272 | * This function provides a "bounce buffer" approach to Rx interrupt | |
2273 | * processing. The advantage to this is that on systems that have | |
2274 | * expensive overhead for IOMMU access this provides a means of avoiding | |
2275 | * it by maintaining the mapping of the page to the syste. | |
2276 | * | |
5a85e737 | 2277 | * Returns amount of work completed |
f800326d | 2278 | **/ |
5a85e737 | 2279 | static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 2280 | struct ixgbe_ring *rx_ring, |
f4de00ed | 2281 | const int budget) |
9a799d71 | 2282 | { |
d2f4fbe2 | 2283 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
f800326d | 2284 | struct ixgbe_adapter *adapter = q_vector->adapter; |
33fdc82f | 2285 | #ifdef IXGBE_FCOE |
4ffdf91a MR |
2286 | int ddp_bytes; |
2287 | unsigned int mss = 0; | |
3d8fd385 | 2288 | #endif /* IXGBE_FCOE */ |
f800326d | 2289 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
7379f97a | 2290 | bool xdp_xmit = false; |
9a799d71 | 2291 | |
fdabfc8a | 2292 | while (likely(total_rx_packets < budget)) { |
f800326d | 2293 | union ixgbe_adv_rx_desc *rx_desc; |
3fd21876 | 2294 | struct ixgbe_rx_buffer *rx_buffer; |
f800326d | 2295 | struct sk_buff *skb; |
92470808 | 2296 | struct xdp_buff xdp; |
3fd21876 | 2297 | unsigned int size; |
f800326d AD |
2298 | |
2299 | /* return some buffers to hardware, one at a time is too slow */ | |
2300 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
2301 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
2302 | cleaned_count = 0; | |
2303 | } | |
2304 | ||
18806c9e | 2305 | rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); |
3fd21876 AD |
2306 | size = le16_to_cpu(rx_desc->wb.upper.length); |
2307 | if (!size) | |
f800326d | 2308 | break; |
9a799d71 | 2309 | |
124b74c1 | 2310 | /* This memory barrier is needed to keep us from reading |
f800326d | 2311 | * any other fields out of the rx_desc until we know the |
124b74c1 | 2312 | * descriptor has been written back |
f800326d | 2313 | */ |
124b74c1 | 2314 | dma_rmb(); |
9a799d71 | 2315 | |
3fd21876 AD |
2316 | rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); |
2317 | ||
18806c9e | 2318 | /* retrieve a buffer from the ring */ |
92470808 JF |
2319 | if (!skb) { |
2320 | xdp.data = page_address(rx_buffer->page) + | |
2321 | rx_buffer->page_offset; | |
2322 | xdp.data_hard_start = xdp.data - | |
2323 | ixgbe_rx_offset(rx_ring); | |
2324 | xdp.data_end = xdp.data + size; | |
2325 | ||
33fdc82f | 2326 | skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); |
92470808 JF |
2327 | } |
2328 | ||
2329 | if (IS_ERR(skb)) { | |
7379f97a JF |
2330 | if (PTR_ERR(skb) == -IXGBE_XDP_TX) { |
2331 | xdp_xmit = true; | |
33fdc82f | 2332 | ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); |
7379f97a | 2333 | } else { |
33fdc82f | 2334 | rx_buffer->pagecnt_bias++; |
7379f97a | 2335 | } |
92470808 JF |
2336 | total_rx_packets++; |
2337 | total_rx_bytes += size; | |
92470808 | 2338 | } else if (skb) { |
3fd21876 | 2339 | ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); |
92470808 | 2340 | } else if (ring_uses_build_skb(rx_ring)) { |
6f429223 | 2341 | skb = ixgbe_build_skb(rx_ring, rx_buffer, |
92470808 JF |
2342 | &xdp, rx_desc); |
2343 | } else { | |
3fd21876 | 2344 | skb = ixgbe_construct_skb(rx_ring, rx_buffer, |
92470808 JF |
2345 | &xdp, rx_desc); |
2346 | } | |
f800326d | 2347 | |
18806c9e | 2348 | /* exit if we failed to retrieve a buffer */ |
3fd21876 AD |
2349 | if (!skb) { |
2350 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
2351 | rx_buffer->pagecnt_bias++; | |
18806c9e | 2352 | break; |
3fd21876 | 2353 | } |
9a799d71 | 2354 | |
3fd21876 | 2355 | ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); |
9a799d71 | 2356 | cleaned_count++; |
f8212f97 | 2357 | |
f800326d AD |
2358 | /* place incomplete frames back on ring for completion */ |
2359 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
2360 | continue; | |
c267fc16 | 2361 | |
f800326d AD |
2362 | /* verify the packet layout is correct */ |
2363 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
2364 | continue; | |
9a799d71 | 2365 | |
d2f4fbe2 AV |
2366 | /* probably a little skewed due to removing CRC */ |
2367 | total_rx_bytes += skb->len; | |
d2f4fbe2 | 2368 | |
8a0da21b AD |
2369 | /* populate checksum, timestamp, VLAN, and protocol */ |
2370 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
2371 | ||
332d4a7d YZ |
2372 | #ifdef IXGBE_FCOE |
2373 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
57efd44c | 2374 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { |
f56e0cb1 | 2375 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
4ffdf91a MR |
2376 | /* include DDPed FCoE data */ |
2377 | if (ddp_bytes > 0) { | |
2378 | if (!mss) { | |
2379 | mss = rx_ring->netdev->mtu - | |
2380 | sizeof(struct fcoe_hdr) - | |
2381 | sizeof(struct fc_frame_header) - | |
2382 | sizeof(struct fcoe_crc_eof); | |
2383 | if (mss > 512) | |
2384 | mss &= ~511; | |
2385 | } | |
2386 | total_rx_bytes += ddp_bytes; | |
2387 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, | |
2388 | mss); | |
2389 | } | |
63d635b2 AD |
2390 | if (!ddp_bytes) { |
2391 | dev_kfree_skb_any(skb); | |
f800326d | 2392 | continue; |
63d635b2 | 2393 | } |
3d8fd385 | 2394 | } |
f800326d | 2395 | |
332d4a7d | 2396 | #endif /* IXGBE_FCOE */ |
8a0da21b | 2397 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 2398 | |
f800326d | 2399 | /* update budget accounting */ |
f4de00ed | 2400 | total_rx_packets++; |
fdabfc8a | 2401 | } |
9a799d71 | 2402 | |
7379f97a JF |
2403 | if (xdp_xmit) { |
2404 | struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; | |
2405 | ||
2406 | /* Force memory writes to complete before letting h/w | |
2407 | * know there are new descriptors to fetch. | |
2408 | */ | |
2409 | wmb(); | |
2410 | writel(ring->next_to_use, ring->tail); | |
2411 | } | |
2412 | ||
c267fc16 AD |
2413 | u64_stats_update_begin(&rx_ring->syncp); |
2414 | rx_ring->stats.packets += total_rx_packets; | |
2415 | rx_ring->stats.bytes += total_rx_bytes; | |
2416 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
2417 | q_vector->rx.total_packets += total_rx_packets; |
2418 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 2419 | |
5a85e737 | 2420 | return total_rx_packets; |
9a799d71 AK |
2421 | } |
2422 | ||
9a799d71 AK |
2423 | /** |
2424 | * ixgbe_configure_msix - Configure MSI-X hardware | |
2425 | * @adapter: board private structure | |
2426 | * | |
2427 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
2428 | * interrupts. | |
2429 | **/ | |
2430 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
2431 | { | |
021230d4 | 2432 | struct ixgbe_q_vector *q_vector; |
49c7ffbe | 2433 | int v_idx; |
021230d4 | 2434 | u32 mask; |
9a799d71 | 2435 | |
8e34d1aa AD |
2436 | /* Populate MSIX to EITR Select */ |
2437 | if (adapter->num_vfs > 32) { | |
b4f47a48 | 2438 | u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; |
8e34d1aa AD |
2439 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); |
2440 | } | |
2441 | ||
4df10466 JB |
2442 | /* |
2443 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
2444 | * corresponding register. |
2445 | */ | |
49c7ffbe | 2446 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { |
efe3d3c8 | 2447 | struct ixgbe_ring *ring; |
7a921c93 | 2448 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 2449 | |
a557928e | 2450 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
2451 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
2452 | ||
a557928e | 2453 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
2454 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
2455 | ||
fe49f04a | 2456 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
2457 | } |
2458 | ||
bd508178 AD |
2459 | switch (adapter->hw.mac.type) { |
2460 | case ixgbe_mac_82598EB: | |
e8e26350 | 2461 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 2462 | v_idx); |
bd508178 AD |
2463 | break; |
2464 | case ixgbe_mac_82599EB: | |
b93a2226 | 2465 | case ixgbe_mac_X540: |
9a75a1ac DS |
2466 | case ixgbe_mac_X550: |
2467 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2468 | case ixgbe_mac_x550em_a: |
e8e26350 | 2469 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 2470 | break; |
bd508178 AD |
2471 | default: |
2472 | break; | |
2473 | } | |
021230d4 AV |
2474 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
2475 | ||
41fb9248 | 2476 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 2477 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
2478 | mask &= ~(IXGBE_EIMS_OTHER | |
2479 | IXGBE_EIMS_MAILBOX | | |
2480 | IXGBE_EIMS_LSC); | |
2481 | ||
021230d4 | 2482 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
2483 | } |
2484 | ||
f494e8fa AV |
2485 | enum latency_range { |
2486 | lowest_latency = 0, | |
2487 | low_latency = 1, | |
2488 | bulk_latency = 2, | |
2489 | latency_invalid = 255 | |
2490 | }; | |
2491 | ||
2492 | /** | |
2493 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
2494 | * @q_vector: structure containing interrupt and ring information |
2495 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
2496 | * |
2497 | * Stores a new ITR value based on packets and byte | |
2498 | * counts during the last interrupt. The advantage of per interrupt | |
2499 | * computation is faster updates and more accurate ITR for the current | |
2500 | * traffic pattern. Constants in this function were computed | |
2501 | * based on theoretical maximum wire speed and thresholds were set based | |
2502 | * on testing data as well as attempting to minimize response time | |
2503 | * while increasing bulk throughput. | |
2504 | * this functionality is controlled by the InterruptThrottleRate module | |
2505 | * parameter (see ixgbe_param.c) | |
2506 | **/ | |
bd198058 AD |
2507 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
2508 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 2509 | { |
bd198058 AD |
2510 | int bytes = ring_container->total_bytes; |
2511 | int packets = ring_container->total_packets; | |
2512 | u32 timepassed_us; | |
621bd70e | 2513 | u64 bytes_perint; |
bd198058 | 2514 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
2515 | |
2516 | if (packets == 0) | |
bd198058 | 2517 | return; |
f494e8fa AV |
2518 | |
2519 | /* simple throttlerate management | |
621bd70e AD |
2520 | * 0-10MB/s lowest (100000 ints/s) |
2521 | * 10-20MB/s low (20000 ints/s) | |
8ac34f10 | 2522 | * 20-1249MB/s bulk (12000 ints/s) |
f494e8fa AV |
2523 | */ |
2524 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 2525 | timepassed_us = q_vector->itr >> 2; |
bdbeefe8 DS |
2526 | if (timepassed_us == 0) |
2527 | return; | |
2528 | ||
f494e8fa AV |
2529 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
2530 | ||
2531 | switch (itr_setting) { | |
2532 | case lowest_latency: | |
621bd70e | 2533 | if (bytes_perint > 10) |
bd198058 | 2534 | itr_setting = low_latency; |
f494e8fa AV |
2535 | break; |
2536 | case low_latency: | |
621bd70e | 2537 | if (bytes_perint > 20) |
bd198058 | 2538 | itr_setting = bulk_latency; |
621bd70e | 2539 | else if (bytes_perint <= 10) |
bd198058 | 2540 | itr_setting = lowest_latency; |
f494e8fa AV |
2541 | break; |
2542 | case bulk_latency: | |
621bd70e | 2543 | if (bytes_perint <= 20) |
bd198058 | 2544 | itr_setting = low_latency; |
f494e8fa AV |
2545 | break; |
2546 | } | |
2547 | ||
bd198058 AD |
2548 | /* clear work counters since we have the values we need */ |
2549 | ring_container->total_bytes = 0; | |
2550 | ring_container->total_packets = 0; | |
2551 | ||
2552 | /* write updated itr to ring container */ | |
2553 | ring_container->itr = itr_setting; | |
f494e8fa AV |
2554 | } |
2555 | ||
509ee935 JB |
2556 | /** |
2557 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 2558 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
2559 | * |
2560 | * This function is made to be called by ethtool and by the driver | |
2561 | * when it needs to update EITR registers at runtime. Hardware | |
2562 | * specific quirks/differences are taken care of here. | |
2563 | */ | |
fe49f04a | 2564 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 2565 | { |
fe49f04a | 2566 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 2567 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2568 | int v_idx = q_vector->v_idx; |
5d967eb7 | 2569 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 2570 | |
bd508178 AD |
2571 | switch (adapter->hw.mac.type) { |
2572 | case ixgbe_mac_82598EB: | |
509ee935 JB |
2573 | /* must write high and low 16 bits to reset counter */ |
2574 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
2575 | break; |
2576 | case ixgbe_mac_82599EB: | |
b93a2226 | 2577 | case ixgbe_mac_X540: |
9a75a1ac DS |
2578 | case ixgbe_mac_X550: |
2579 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2580 | case ixgbe_mac_x550em_a: |
509ee935 JB |
2581 | /* |
2582 | * set the WDIS bit to not clear the timer bits and cause an | |
2583 | * immediate assertion of the interrupt | |
2584 | */ | |
2585 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
2586 | break; |
2587 | default: | |
2588 | break; | |
509ee935 JB |
2589 | } |
2590 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
2591 | } | |
2592 | ||
bd198058 | 2593 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 2594 | { |
d5bf4f67 | 2595 | u32 new_itr = q_vector->itr; |
bd198058 | 2596 | u8 current_itr; |
f494e8fa | 2597 | |
bd198058 AD |
2598 | ixgbe_update_itr(q_vector, &q_vector->tx); |
2599 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 2600 | |
08c8833b | 2601 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
2602 | |
2603 | switch (current_itr) { | |
2604 | /* counts and packets in update_itr are dependent on these numbers */ | |
2605 | case lowest_latency: | |
d5bf4f67 | 2606 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
2607 | break; |
2608 | case low_latency: | |
d5bf4f67 | 2609 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
2610 | break; |
2611 | case bulk_latency: | |
8ac34f10 | 2612 | new_itr = IXGBE_12K_ITR; |
f494e8fa | 2613 | break; |
bd198058 AD |
2614 | default: |
2615 | break; | |
f494e8fa AV |
2616 | } |
2617 | ||
d5bf4f67 | 2618 | if (new_itr != q_vector->itr) { |
fe49f04a | 2619 | /* do an exponential smoothing */ |
d5bf4f67 ET |
2620 | new_itr = (10 * new_itr * q_vector->itr) / |
2621 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 2622 | |
bd198058 | 2623 | /* save the algorithm value here */ |
5d967eb7 | 2624 | q_vector->itr = new_itr; |
fe49f04a AD |
2625 | |
2626 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2627 | } |
f494e8fa AV |
2628 | } |
2629 | ||
119fc60a | 2630 | /** |
de88eeeb | 2631 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 2632 | * @adapter: pointer to adapter |
119fc60a | 2633 | **/ |
f0f9778d | 2634 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 2635 | { |
119fc60a MC |
2636 | struct ixgbe_hw *hw = &adapter->hw; |
2637 | u32 eicr = adapter->interrupt_event; | |
b3eb4e18 | 2638 | s32 rc; |
119fc60a | 2639 | |
f0f9778d | 2640 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
2641 | return; |
2642 | ||
22cb4fff | 2643 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) |
f0f9778d AD |
2644 | return; |
2645 | ||
2646 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2647 | ||
7ca647bd | 2648 | switch (hw->device_id) { |
f0f9778d AD |
2649 | case IXGBE_DEV_ID_82599_T3_LOM: |
2650 | /* | |
2651 | * Since the warning interrupt is for both ports | |
2652 | * we don't have to check if: | |
2653 | * - This interrupt wasn't for our port. | |
2654 | * - We may have missed the interrupt so always have to | |
2655 | * check if we got a LSC | |
2656 | */ | |
9a900eca | 2657 | if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && |
f0f9778d AD |
2658 | !(eicr & IXGBE_EICR_LSC)) |
2659 | return; | |
2660 | ||
2661 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
3d292265 | 2662 | u32 speed; |
f0f9778d | 2663 | bool link_up = false; |
7ca647bd | 2664 | |
3d292265 | 2665 | hw->mac.ops.check_link(hw, &speed, &link_up, false); |
7ca647bd | 2666 | |
f0f9778d AD |
2667 | if (link_up) |
2668 | return; | |
2669 | } | |
2670 | ||
2671 | /* Check if this is not due to overtemp */ | |
2672 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2673 | return; | |
2674 | ||
2675 | break; | |
b3eb4e18 MR |
2676 | case IXGBE_DEV_ID_X550EM_A_1G_T: |
2677 | case IXGBE_DEV_ID_X550EM_A_1G_T_L: | |
2678 | rc = hw->phy.ops.check_overtemp(hw); | |
2679 | if (rc != IXGBE_ERR_OVERTEMP) | |
2680 | return; | |
2681 | break; | |
7ca647bd | 2682 | default: |
597f22d6 DS |
2683 | if (adapter->hw.mac.type >= ixgbe_mac_X540) |
2684 | return; | |
9a900eca | 2685 | if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) |
119fc60a | 2686 | return; |
7ca647bd | 2687 | break; |
119fc60a | 2688 | } |
f44e751b | 2689 | e_crit(drv, "%s\n", ixgbe_overheat_msg); |
f0f9778d AD |
2690 | |
2691 | adapter->interrupt_event = 0; | |
119fc60a MC |
2692 | } |
2693 | ||
0befdb3e JB |
2694 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2695 | { | |
2696 | struct ixgbe_hw *hw = &adapter->hw; | |
2697 | ||
2698 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
9a900eca | 2699 | (eicr & IXGBE_EICR_GPI_SDP1(hw))) { |
396e799c | 2700 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e | 2701 | /* write to clear the interrupt */ |
9a900eca | 2702 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); |
0befdb3e JB |
2703 | } |
2704 | } | |
cf8280ee | 2705 | |
4f51bf70 JK |
2706 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2707 | { | |
9a900eca DS |
2708 | struct ixgbe_hw *hw = &adapter->hw; |
2709 | ||
4f51bf70 JK |
2710 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) |
2711 | return; | |
2712 | ||
2713 | switch (adapter->hw.mac.type) { | |
2714 | case ixgbe_mac_82599EB: | |
2715 | /* | |
2716 | * Need to check link state so complete overtemp check | |
2717 | * on service task | |
2718 | */ | |
9a900eca DS |
2719 | if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || |
2720 | (eicr & IXGBE_EICR_LSC)) && | |
4f51bf70 JK |
2721 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { |
2722 | adapter->interrupt_event = eicr; | |
2723 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2724 | ixgbe_service_event_schedule(adapter); | |
2725 | return; | |
2726 | } | |
2727 | return; | |
b3eb4e18 MR |
2728 | case ixgbe_mac_x550em_a: |
2729 | if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { | |
2730 | adapter->interrupt_event = eicr; | |
2731 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2732 | ixgbe_service_event_schedule(adapter); | |
2733 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, | |
2734 | IXGBE_EICR_GPI_SDP0_X550EM_a); | |
2735 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, | |
2736 | IXGBE_EICR_GPI_SDP0_X550EM_a); | |
2737 | } | |
2738 | return; | |
2739 | case ixgbe_mac_X550: | |
4f51bf70 JK |
2740 | case ixgbe_mac_X540: |
2741 | if (!(eicr & IXGBE_EICR_TS)) | |
2742 | return; | |
2743 | break; | |
2744 | default: | |
2745 | return; | |
2746 | } | |
2747 | ||
f44e751b | 2748 | e_crit(drv, "%s\n", ixgbe_overheat_msg); |
4f51bf70 JK |
2749 | } |
2750 | ||
45788d2a DS |
2751 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2752 | { | |
2753 | switch (hw->mac.type) { | |
2754 | case ixgbe_mac_82598EB: | |
2755 | if (hw->phy.type == ixgbe_phy_nl) | |
2756 | return true; | |
2757 | return false; | |
2758 | case ixgbe_mac_82599EB: | |
2759 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2760 | case ixgbe_mac_x550em_a: |
45788d2a DS |
2761 | switch (hw->mac.ops.get_media_type(hw)) { |
2762 | case ixgbe_media_type_fiber: | |
2763 | case ixgbe_media_type_fiber_qsfp: | |
2764 | return true; | |
2765 | default: | |
2766 | return false; | |
2767 | } | |
2768 | default: | |
2769 | return false; | |
2770 | } | |
2771 | } | |
2772 | ||
e8e26350 PW |
2773 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2774 | { | |
2775 | struct ixgbe_hw *hw = &adapter->hw; | |
4ccc650c | 2776 | u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); |
e8e26350 | 2777 | |
4ccc650c DS |
2778 | if (!ixgbe_is_sfp(hw)) |
2779 | return; | |
2780 | ||
2781 | /* Later MAC's use different SDP */ | |
2782 | if (hw->mac.type >= ixgbe_mac_X540) | |
2783 | eicr_mask = IXGBE_EICR_GPI_SDP0_X540; | |
2784 | ||
2785 | if (eicr & eicr_mask) { | |
73c4b7cd | 2786 | /* Clear the interrupt */ |
4ccc650c | 2787 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); |
7086400d AD |
2788 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2789 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
58e7cd24 | 2790 | adapter->sfp_poll_time = 0; |
7086400d AD |
2791 | ixgbe_service_event_schedule(adapter); |
2792 | } | |
73c4b7cd AD |
2793 | } |
2794 | ||
4ccc650c DS |
2795 | if (adapter->hw.mac.type == ixgbe_mac_82599EB && |
2796 | (eicr & IXGBE_EICR_GPI_SDP1(hw))) { | |
e8e26350 | 2797 | /* Clear the interrupt */ |
9a900eca | 2798 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); |
7086400d AD |
2799 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2800 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2801 | ixgbe_service_event_schedule(adapter); | |
2802 | } | |
e8e26350 PW |
2803 | } |
2804 | } | |
2805 | ||
cf8280ee JB |
2806 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2807 | { | |
2808 | struct ixgbe_hw *hw = &adapter->hw; | |
2809 | ||
2810 | adapter->lsc_int++; | |
2811 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2812 | adapter->link_check_timeout = jiffies; | |
2813 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2814 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2815 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2816 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2817 | } |
2818 | } | |
2819 | ||
fe49f04a AD |
2820 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2821 | u64 qmask) | |
2822 | { | |
2823 | u32 mask; | |
bd508178 | 2824 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2825 | |
bd508178 AD |
2826 | switch (hw->mac.type) { |
2827 | case ixgbe_mac_82598EB: | |
fe49f04a | 2828 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2829 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2830 | break; | |
2831 | case ixgbe_mac_82599EB: | |
b93a2226 | 2832 | case ixgbe_mac_X540: |
9a75a1ac DS |
2833 | case ixgbe_mac_X550: |
2834 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2835 | case ixgbe_mac_x550em_a: |
fe49f04a | 2836 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2837 | if (mask) |
2838 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2839 | mask = (qmask >> 32); |
bd508178 AD |
2840 | if (mask) |
2841 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2842 | break; | |
2843 | default: | |
2844 | break; | |
fe49f04a AD |
2845 | } |
2846 | /* skip the flush */ | |
2847 | } | |
2848 | ||
2849 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2850 | u64 qmask) |
fe49f04a AD |
2851 | { |
2852 | u32 mask; | |
bd508178 | 2853 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2854 | |
bd508178 AD |
2855 | switch (hw->mac.type) { |
2856 | case ixgbe_mac_82598EB: | |
fe49f04a | 2857 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2858 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2859 | break; | |
2860 | case ixgbe_mac_82599EB: | |
b93a2226 | 2861 | case ixgbe_mac_X540: |
9a75a1ac DS |
2862 | case ixgbe_mac_X550: |
2863 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2864 | case ixgbe_mac_x550em_a: |
fe49f04a | 2865 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2866 | if (mask) |
2867 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2868 | mask = (qmask >> 32); |
bd508178 AD |
2869 | if (mask) |
2870 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2871 | break; | |
2872 | default: | |
2873 | break; | |
fe49f04a AD |
2874 | } |
2875 | /* skip the flush */ | |
2876 | } | |
2877 | ||
021230d4 | 2878 | /** |
2c4af694 AD |
2879 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2880 | * @adapter: board private structure | |
021230d4 | 2881 | **/ |
2c4af694 AD |
2882 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2883 | bool flush) | |
9a799d71 | 2884 | { |
9a900eca | 2885 | struct ixgbe_hw *hw = &adapter->hw; |
2c4af694 | 2886 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2887 | |
2c4af694 AD |
2888 | /* don't reenable LSC while waiting for link */ |
2889 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2890 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2891 | |
2c4af694 | 2892 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2893 | switch (adapter->hw.mac.type) { |
2894 | case ixgbe_mac_82599EB: | |
9a900eca | 2895 | mask |= IXGBE_EIMS_GPI_SDP0(hw); |
4f51bf70 JK |
2896 | break; |
2897 | case ixgbe_mac_X540: | |
9a75a1ac DS |
2898 | case ixgbe_mac_X550: |
2899 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2900 | case ixgbe_mac_x550em_a: |
4f51bf70 JK |
2901 | mask |= IXGBE_EIMS_TS; |
2902 | break; | |
2903 | default: | |
2904 | break; | |
2905 | } | |
2c4af694 | 2906 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
9a900eca | 2907 | mask |= IXGBE_EIMS_GPI_SDP1(hw); |
2c4af694 AD |
2908 | switch (adapter->hw.mac.type) { |
2909 | case ixgbe_mac_82599EB: | |
9a900eca DS |
2910 | mask |= IXGBE_EIMS_GPI_SDP1(hw); |
2911 | mask |= IXGBE_EIMS_GPI_SDP2(hw); | |
9a75a1ac | 2912 | /* fall through */ |
858bc081 | 2913 | case ixgbe_mac_X540: |
9a75a1ac DS |
2914 | case ixgbe_mac_X550: |
2915 | case ixgbe_mac_X550EM_x: | |
49425dfc MR |
2916 | case ixgbe_mac_x550em_a: |
2917 | if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || | |
2d40cd17 | 2918 | adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || |
49425dfc | 2919 | adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) |
cbd45ec7 | 2920 | mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); |
597f22d6 DS |
2921 | if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) |
2922 | mask |= IXGBE_EICR_GPI_SDP0_X540; | |
858bc081 | 2923 | mask |= IXGBE_EIMS_ECC; |
2c4af694 AD |
2924 | mask |= IXGBE_EIMS_MAILBOX; |
2925 | break; | |
2926 | default: | |
2927 | break; | |
9a799d71 | 2928 | } |
db0677fa | 2929 | |
2c4af694 AD |
2930 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2931 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2932 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2933 | |
2c4af694 AD |
2934 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2935 | if (queues) | |
2936 | ixgbe_irq_enable_queues(adapter, ~0); | |
2937 | if (flush) | |
2938 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2939 | } |
2940 | ||
2c4af694 | 2941 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2942 | { |
a65151ba | 2943 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2944 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2945 | u32 eicr; |
91281fd3 | 2946 | |
54037505 DS |
2947 | /* |
2948 | * Workaround for Silicon errata. Use clear-by-write instead | |
2949 | * of clear-by-read. Reading with EICS will return the | |
2950 | * interrupt causes without clearing, which later be done | |
2951 | * with the write to EICR. | |
2952 | */ | |
2953 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
d87d8307 JK |
2954 | |
2955 | /* The lower 16bits of the EICR register are for the queue interrupts | |
dbedd44e | 2956 | * which should be masked here in order to not accidentally clear them if |
d87d8307 JK |
2957 | * the bits are high when ixgbe_msix_other is called. There is a race |
2958 | * condition otherwise which results in possible performance loss | |
2959 | * especially if the ixgbe_msix_other interrupt is triggering | |
2960 | * consistently (as it would when PPS is turned on for the X540 device) | |
2961 | */ | |
2962 | eicr &= 0xFFFF0000; | |
2963 | ||
54037505 | 2964 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); |
33cf09c9 | 2965 | |
cf8280ee JB |
2966 | if (eicr & IXGBE_EICR_LSC) |
2967 | ixgbe_check_lsc(adapter); | |
f0848276 | 2968 | |
1cdd1ec8 GR |
2969 | if (eicr & IXGBE_EICR_MAILBOX) |
2970 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2971 | |
bd508178 AD |
2972 | switch (hw->mac.type) { |
2973 | case ixgbe_mac_82599EB: | |
b93a2226 | 2974 | case ixgbe_mac_X540: |
9a75a1ac DS |
2975 | case ixgbe_mac_X550: |
2976 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2977 | case ixgbe_mac_x550em_a: |
597f22d6 DS |
2978 | if (hw->phy.type == ixgbe_phy_x550em_ext_t && |
2979 | (eicr & IXGBE_EICR_GPI_SDP0_X540)) { | |
2980 | adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; | |
2981 | ixgbe_service_event_schedule(adapter); | |
2982 | IXGBE_WRITE_REG(hw, IXGBE_EICR, | |
2983 | IXGBE_EICR_GPI_SDP0_X540); | |
2984 | } | |
d773ce2d DS |
2985 | if (eicr & IXGBE_EICR_ECC) { |
2986 | e_info(link, "Received ECC Err, initiating reset\n"); | |
57ca2a4f | 2987 | set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); |
d773ce2d DS |
2988 | ixgbe_service_event_schedule(adapter); |
2989 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); | |
2990 | } | |
c4cf55e5 PWJ |
2991 | /* Handle Flow Director Full threshold interrupt */ |
2992 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2993 | int reinit_count = 0; |
c4cf55e5 | 2994 | int i; |
c4cf55e5 | 2995 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2996 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2997 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2998 | &ring->state)) |
2999 | reinit_count++; | |
3000 | } | |
3001 | if (reinit_count) { | |
3002 | /* no more flow director interrupts until after init */ | |
3003 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
3004 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
3005 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
3006 | } |
3007 | } | |
f0f9778d | 3008 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 3009 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
3010 | break; |
3011 | default: | |
3012 | break; | |
c4cf55e5 | 3013 | } |
f0848276 | 3014 | |
bd508178 | 3015 | ixgbe_check_fan_failure(adapter, eicr); |
db0677fa | 3016 | |
db0677fa | 3017 | if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) |
a9763f3c | 3018 | ixgbe_ptp_check_pps_event(adapter); |
efe3d3c8 | 3019 | |
7086400d | 3020 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 3021 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 3022 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 3023 | |
9a799d71 | 3024 | return IRQ_HANDLED; |
f0848276 | 3025 | } |
91281fd3 | 3026 | |
4ff7fb12 | 3027 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 3028 | { |
021230d4 | 3029 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 3030 | |
9b471446 | 3031 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 3032 | |
4ff7fb12 | 3033 | if (q_vector->rx.ring || q_vector->tx.ring) |
ef2662b2 | 3034 | napi_schedule_irqoff(&q_vector->napi); |
91281fd3 | 3035 | |
9a799d71 | 3036 | return IRQ_HANDLED; |
91281fd3 AD |
3037 | } |
3038 | ||
eb01b975 AD |
3039 | /** |
3040 | * ixgbe_poll - NAPI Rx polling callback | |
3041 | * @napi: structure for representing this polling device | |
3042 | * @budget: how many packets driver is allowed to clean | |
3043 | * | |
3044 | * This function is used for legacy and MSI, NAPI mode | |
3045 | **/ | |
8af3c33f | 3046 | int ixgbe_poll(struct napi_struct *napi, int budget) |
eb01b975 AD |
3047 | { |
3048 | struct ixgbe_q_vector *q_vector = | |
3049 | container_of(napi, struct ixgbe_q_vector, napi); | |
3050 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3051 | struct ixgbe_ring *ring; | |
32b3e08f | 3052 | int per_ring_budget, work_done = 0; |
eb01b975 AD |
3053 | bool clean_complete = true; |
3054 | ||
3055 | #ifdef CONFIG_IXGBE_DCA | |
3056 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
3057 | ixgbe_update_dca(q_vector); | |
3058 | #endif | |
3059 | ||
8220bbc1 AD |
3060 | ixgbe_for_each_ring(ring, q_vector->tx) { |
3061 | if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) | |
3062 | clean_complete = false; | |
3063 | } | |
eb01b975 | 3064 | |
3ffc1af5 ED |
3065 | /* Exit if we are called by netpoll */ |
3066 | if (budget <= 0) | |
5a85e737 ET |
3067 | return budget; |
3068 | ||
eb01b975 AD |
3069 | /* attempt to distribute budget to each queue fairly, but don't allow |
3070 | * the budget to go below 1 because we'll exit polling */ | |
3071 | if (q_vector->rx.count > 1) | |
3072 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
3073 | else | |
3074 | per_ring_budget = budget; | |
3075 | ||
32b3e08f JB |
3076 | ixgbe_for_each_ring(ring, q_vector->rx) { |
3077 | int cleaned = ixgbe_clean_rx_irq(q_vector, ring, | |
3078 | per_ring_budget); | |
3079 | ||
3080 | work_done += cleaned; | |
8220bbc1 AD |
3081 | if (cleaned >= per_ring_budget) |
3082 | clean_complete = false; | |
32b3e08f | 3083 | } |
eb01b975 AD |
3084 | |
3085 | /* If all work not completed, return budget and keep polling */ | |
3086 | if (!clean_complete) | |
3087 | return budget; | |
3088 | ||
3089 | /* all work done, exit the polling mode */ | |
32b3e08f | 3090 | napi_complete_done(napi, work_done); |
eb01b975 AD |
3091 | if (adapter->rx_itr_setting & 1) |
3092 | ixgbe_set_itr(q_vector); | |
3093 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
b4f47a48 | 3094 | ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); |
eb01b975 | 3095 | |
4b732cd4 | 3096 | return min(work_done, budget - 1); |
eb01b975 AD |
3097 | } |
3098 | ||
021230d4 AV |
3099 | /** |
3100 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
3101 | * @adapter: board private structure | |
3102 | * | |
3103 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
3104 | * interrupts from the kernel. | |
3105 | **/ | |
3106 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
3107 | { | |
3108 | struct net_device *netdev = adapter->netdev; | |
e61e4c8b | 3109 | unsigned int ri = 0, ti = 0; |
207867f5 | 3110 | int vector, err; |
021230d4 | 3111 | |
49c7ffbe | 3112 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
d0759ebb | 3113 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 3114 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 3115 | |
4ff7fb12 | 3116 | if (q_vector->tx.ring && q_vector->rx.ring) { |
e61e4c8b TN |
3117 | snprintf(q_vector->name, sizeof(q_vector->name), |
3118 | "%s-TxRx-%u", netdev->name, ri++); | |
4ff7fb12 AD |
3119 | ti++; |
3120 | } else if (q_vector->rx.ring) { | |
e61e4c8b TN |
3121 | snprintf(q_vector->name, sizeof(q_vector->name), |
3122 | "%s-rx-%u", netdev->name, ri++); | |
4ff7fb12 | 3123 | } else if (q_vector->tx.ring) { |
e61e4c8b TN |
3124 | snprintf(q_vector->name, sizeof(q_vector->name), |
3125 | "%s-tx-%u", netdev->name, ti++); | |
d0759ebb AD |
3126 | } else { |
3127 | /* skip this unused q_vector */ | |
3128 | continue; | |
32aa77a4 | 3129 | } |
207867f5 AD |
3130 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
3131 | q_vector->name, q_vector); | |
9a799d71 | 3132 | if (err) { |
396e799c | 3133 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 3134 | "Error: %d\n", err); |
021230d4 | 3135 | goto free_queue_irqs; |
9a799d71 | 3136 | } |
207867f5 AD |
3137 | /* If Flow Director is enabled, set interrupt affinity */ |
3138 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
3139 | /* assign the mask for this irq */ | |
3140 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 3141 | &q_vector->affinity_mask); |
207867f5 | 3142 | } |
9a799d71 AK |
3143 | } |
3144 | ||
021230d4 | 3145 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 3146 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 3147 | if (err) { |
de88eeeb | 3148 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 3149 | goto free_queue_irqs; |
9a799d71 AK |
3150 | } |
3151 | ||
9a799d71 AK |
3152 | return 0; |
3153 | ||
021230d4 | 3154 | free_queue_irqs: |
207867f5 AD |
3155 | while (vector) { |
3156 | vector--; | |
3157 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
3158 | NULL); | |
3159 | free_irq(adapter->msix_entries[vector].vector, | |
3160 | adapter->q_vector[vector]); | |
3161 | } | |
021230d4 AV |
3162 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
3163 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
3164 | kfree(adapter->msix_entries); |
3165 | adapter->msix_entries = NULL; | |
9a799d71 AK |
3166 | return err; |
3167 | } | |
3168 | ||
3169 | /** | |
021230d4 | 3170 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
3171 | * @irq: interrupt number |
3172 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
3173 | **/ |
3174 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
3175 | { | |
a65151ba | 3176 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 3177 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 3178 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
3179 | u32 eicr; |
3180 | ||
54037505 | 3181 | /* |
24ddd967 | 3182 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
3183 | * before the read of EICR. |
3184 | */ | |
3185 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
3186 | ||
021230d4 | 3187 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 3188 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 3189 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 3190 | if (!eicr) { |
6af3b9eb ET |
3191 | /* |
3192 | * shared interrupt alert! | |
f47cf66e | 3193 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
3194 | * have disabled interrupts due to EIAM |
3195 | * finish the workaround of silicon errata on 82598. Unmask | |
3196 | * the interrupt that we masked before the EICR read. | |
3197 | */ | |
3198 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
3199 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 3200 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 3201 | } |
9a799d71 | 3202 | |
cf8280ee JB |
3203 | if (eicr & IXGBE_EICR_LSC) |
3204 | ixgbe_check_lsc(adapter); | |
021230d4 | 3205 | |
bd508178 AD |
3206 | switch (hw->mac.type) { |
3207 | case ixgbe_mac_82599EB: | |
e8e26350 | 3208 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
3209 | /* Fall through */ |
3210 | case ixgbe_mac_X540: | |
9a75a1ac DS |
3211 | case ixgbe_mac_X550: |
3212 | case ixgbe_mac_X550EM_x: | |
49425dfc | 3213 | case ixgbe_mac_x550em_a: |
d773ce2d DS |
3214 | if (eicr & IXGBE_EICR_ECC) { |
3215 | e_info(link, "Received ECC Err, initiating reset\n"); | |
57ca2a4f | 3216 | set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); |
d773ce2d DS |
3217 | ixgbe_service_event_schedule(adapter); |
3218 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); | |
3219 | } | |
4f51bf70 | 3220 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
3221 | break; |
3222 | default: | |
3223 | break; | |
3224 | } | |
e8e26350 | 3225 | |
0befdb3e | 3226 | ixgbe_check_fan_failure(adapter, eicr); |
db0677fa | 3227 | if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) |
a9763f3c | 3228 | ixgbe_ptp_check_pps_event(adapter); |
0befdb3e | 3229 | |
b9f6ed2b | 3230 | /* would disable interrupts here but EIAM disabled it */ |
ef2662b2 | 3231 | napi_schedule_irqoff(&q_vector->napi); |
9a799d71 | 3232 | |
6af3b9eb ET |
3233 | /* |
3234 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
3235 | * ixgbe_poll will re-enable the queue interrupts | |
3236 | */ | |
6af3b9eb ET |
3237 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
3238 | ixgbe_irq_enable(adapter, false, false); | |
3239 | ||
9a799d71 AK |
3240 | return IRQ_HANDLED; |
3241 | } | |
3242 | ||
3243 | /** | |
3244 | * ixgbe_request_irq - initialize interrupts | |
3245 | * @adapter: board private structure | |
3246 | * | |
3247 | * Attempts to configure interrupts using the best available | |
3248 | * capabilities of the hardware and kernel. | |
3249 | **/ | |
021230d4 | 3250 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3251 | { |
3252 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 3253 | int err; |
9a799d71 | 3254 | |
4cc6df29 | 3255 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 3256 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 3257 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 3258 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 3259 | netdev->name, adapter); |
4cc6df29 | 3260 | else |
a0607fd3 | 3261 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 3262 | netdev->name, adapter); |
9a799d71 | 3263 | |
de88eeeb | 3264 | if (err) |
396e799c | 3265 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 3266 | |
9a799d71 AK |
3267 | return err; |
3268 | } | |
3269 | ||
3270 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
3271 | { | |
49c7ffbe | 3272 | int vector; |
9a799d71 | 3273 | |
49c7ffbe AD |
3274 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
3275 | free_irq(adapter->pdev->irq, adapter); | |
3276 | return; | |
3277 | } | |
4cc6df29 | 3278 | |
1fa71252 MR |
3279 | if (!adapter->msix_entries) |
3280 | return; | |
3281 | ||
49c7ffbe AD |
3282 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
3283 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; | |
3284 | struct msix_entry *entry = &adapter->msix_entries[vector]; | |
894ff7cf | 3285 | |
49c7ffbe AD |
3286 | /* free only the irqs that were actually requested */ |
3287 | if (!q_vector->rx.ring && !q_vector->tx.ring) | |
3288 | continue; | |
207867f5 | 3289 | |
49c7ffbe AD |
3290 | /* clear the affinity_mask in the IRQ descriptor */ |
3291 | irq_set_affinity_hint(entry->vector, NULL); | |
3292 | ||
3293 | free_irq(entry->vector, q_vector); | |
9a799d71 | 3294 | } |
49c7ffbe | 3295 | |
90c6f877 | 3296 | free_irq(adapter->msix_entries[vector].vector, adapter); |
9a799d71 AK |
3297 | } |
3298 | ||
22d5a71b JB |
3299 | /** |
3300 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
3301 | * @adapter: board private structure | |
3302 | **/ | |
3303 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
3304 | { | |
bd508178 AD |
3305 | switch (adapter->hw.mac.type) { |
3306 | case ixgbe_mac_82598EB: | |
835462fc | 3307 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
3308 | break; |
3309 | case ixgbe_mac_82599EB: | |
b93a2226 | 3310 | case ixgbe_mac_X540: |
9a75a1ac DS |
3311 | case ixgbe_mac_X550: |
3312 | case ixgbe_mac_X550EM_x: | |
49425dfc | 3313 | case ixgbe_mac_x550em_a: |
835462fc NS |
3314 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
3315 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 3316 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
3317 | break; |
3318 | default: | |
3319 | break; | |
22d5a71b JB |
3320 | } |
3321 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
3322 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
49c7ffbe AD |
3323 | int vector; |
3324 | ||
3325 | for (vector = 0; vector < adapter->num_q_vectors; vector++) | |
3326 | synchronize_irq(adapter->msix_entries[vector].vector); | |
3327 | ||
3328 | synchronize_irq(adapter->msix_entries[vector++].vector); | |
22d5a71b JB |
3329 | } else { |
3330 | synchronize_irq(adapter->pdev->irq); | |
3331 | } | |
3332 | } | |
3333 | ||
9a799d71 AK |
3334 | /** |
3335 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
3336 | * | |
3337 | **/ | |
3338 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
3339 | { | |
d5bf4f67 | 3340 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 3341 | |
d5bf4f67 | 3342 | ixgbe_write_eitr(q_vector); |
9a799d71 | 3343 | |
e8e26350 PW |
3344 | ixgbe_set_ivar(adapter, 0, 0, 0); |
3345 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 3346 | |
396e799c | 3347 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
3348 | } |
3349 | ||
43e69bf0 AD |
3350 | /** |
3351 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
3352 | * @adapter: board private structure | |
3353 | * @ring: structure containing ring specific data | |
3354 | * | |
3355 | * Configure the Tx descriptor ring after a reset. | |
3356 | **/ | |
84418e3b AD |
3357 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
3358 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
3359 | { |
3360 | struct ixgbe_hw *hw = &adapter->hw; | |
3361 | u64 tdba = ring->dma; | |
2f1860b8 | 3362 | int wait_loop = 10; |
b88c6de2 | 3363 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 3364 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 3365 | |
2f1860b8 | 3366 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 3367 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
3368 | IXGBE_WRITE_FLUSH(hw); |
3369 | ||
43e69bf0 | 3370 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 3371 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
3372 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
3373 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
3374 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
3375 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
3376 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
2a1a091c | 3377 | ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 3378 | |
b88c6de2 AD |
3379 | /* |
3380 | * set WTHRESH to encourage burst writeback, it should not be set | |
67da097e ET |
3381 | * higher than 1 when: |
3382 | * - ITR is 0 as it could cause false TX hangs | |
3383 | * - ITR is set to > 100k int/sec and BQL is enabled | |
b88c6de2 AD |
3384 | * |
3385 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
3386 | * to or less than the number of on chip descriptors, which is | |
3387 | * currently 40. | |
3388 | */ | |
67da097e | 3389 | if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) |
b4f47a48 | 3390 | txdctl |= 1u << 16; /* WTHRESH = 1 */ |
b88c6de2 | 3391 | else |
b4f47a48 | 3392 | txdctl |= 8u << 16; /* WTHRESH = 8 */ |
b88c6de2 | 3393 | |
e954b374 AD |
3394 | /* |
3395 | * Setting PTHRESH to 32 both improves performance | |
3396 | * and avoids a TX hang with DFP enabled | |
3397 | */ | |
b4f47a48 | 3398 | txdctl |= (1u << 8) | /* HTHRESH = 1 */ |
b88c6de2 | 3399 | 32; /* PTHRESH = 32 */ |
2f1860b8 AD |
3400 | |
3401 | /* reinitialize flowdirector state */ | |
39cb681b | 3402 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
ee9e0f0b AD |
3403 | ring->atr_sample_rate = adapter->atr_sample_rate; |
3404 | ring->atr_count = 0; | |
3405 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
3406 | } else { | |
3407 | ring->atr_sample_rate = 0; | |
3408 | } | |
2f1860b8 | 3409 | |
fd786b7b AD |
3410 | /* initialize XPS */ |
3411 | if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { | |
3412 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
3413 | ||
3414 | if (q_vector) | |
2a47fa45 | 3415 | netif_set_xps_queue(ring->netdev, |
fd786b7b AD |
3416 | &q_vector->affinity_mask, |
3417 | ring->queue_index); | |
3418 | } | |
3419 | ||
c84d324c JF |
3420 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
3421 | ||
ffed21bc AD |
3422 | /* reinitialize tx_buffer_info */ |
3423 | memset(ring->tx_buffer_info, 0, | |
3424 | sizeof(struct ixgbe_tx_buffer) * ring->count); | |
3425 | ||
2f1860b8 | 3426 | /* enable queue */ |
2f1860b8 AD |
3427 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
3428 | ||
3429 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
3430 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3431 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3432 | return; | |
3433 | ||
3434 | /* poll to verify queue is enabled */ | |
3435 | do { | |
032b4325 | 3436 | usleep_range(1000, 2000); |
2f1860b8 AD |
3437 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
3438 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
3439 | if (!wait_loop) | |
a55defd8 | 3440 | hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); |
43e69bf0 AD |
3441 | } |
3442 | ||
120ff942 AD |
3443 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
3444 | { | |
3445 | struct ixgbe_hw *hw = &adapter->hw; | |
671c0adb | 3446 | u32 rttdcs, mtqc; |
8b1c0b24 | 3447 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
3448 | |
3449 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3450 | return; | |
3451 | ||
3452 | /* disable the arbiter while setting MTQC */ | |
3453 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
3454 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
3455 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
3456 | ||
3457 | /* set transmit pool layout */ | |
671c0adb AD |
3458 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
3459 | mtqc = IXGBE_MTQC_VT_ENA; | |
3460 | if (tcs > 4) | |
3461 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
3462 | else if (tcs > 1) | |
3463 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
e24fcf28 AD |
3464 | else if (adapter->ring_feature[RING_F_VMDQ].mask == |
3465 | IXGBE_82599_VMDQ_4Q_MASK) | |
671c0adb AD |
3466 | mtqc |= IXGBE_MTQC_32VF; |
3467 | else | |
3468 | mtqc |= IXGBE_MTQC_64VF; | |
3469 | } else { | |
3470 | if (tcs > 4) | |
3471 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
3472 | else if (tcs > 1) | |
3473 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
8b1c0b24 | 3474 | else |
671c0adb AD |
3475 | mtqc = IXGBE_MTQC_64Q_1PB; |
3476 | } | |
120ff942 | 3477 | |
671c0adb | 3478 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); |
120ff942 | 3479 | |
671c0adb AD |
3480 | /* Enable Security TX Buffer IFG for multiple pb */ |
3481 | if (tcs) { | |
3482 | u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
3483 | sectx |= IXGBE_SECTX_DCB; | |
3484 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); | |
120ff942 AD |
3485 | } |
3486 | ||
3487 | /* re-enable the arbiter */ | |
3488 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
3489 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
3490 | } | |
3491 | ||
9a799d71 | 3492 | /** |
3a581073 | 3493 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
3494 | * @adapter: board private structure |
3495 | * | |
3496 | * Configure the Tx unit of the MAC after a reset. | |
3497 | **/ | |
3498 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
3499 | { | |
2f1860b8 AD |
3500 | struct ixgbe_hw *hw = &adapter->hw; |
3501 | u32 dmatxctl; | |
43e69bf0 | 3502 | u32 i; |
9a799d71 | 3503 | |
2f1860b8 AD |
3504 | ixgbe_setup_mtqc(adapter); |
3505 | ||
3506 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3507 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
3508 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
3509 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
3510 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
3511 | } | |
3512 | ||
9a799d71 | 3513 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
3514 | for (i = 0; i < adapter->num_tx_queues; i++) |
3515 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
33fdc82f JF |
3516 | for (i = 0; i < adapter->num_xdp_queues; i++) |
3517 | ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); | |
9a799d71 AK |
3518 | } |
3519 | ||
3ebe8fde AD |
3520 | static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, |
3521 | struct ixgbe_ring *ring) | |
3522 | { | |
3523 | struct ixgbe_hw *hw = &adapter->hw; | |
3524 | u8 reg_idx = ring->reg_idx; | |
3525 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
3526 | ||
3527 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
3528 | ||
3529 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
3530 | } | |
3531 | ||
3532 | static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, | |
3533 | struct ixgbe_ring *ring) | |
3534 | { | |
3535 | struct ixgbe_hw *hw = &adapter->hw; | |
3536 | u8 reg_idx = ring->reg_idx; | |
3537 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
3538 | ||
3539 | srrctl &= ~IXGBE_SRRCTL_DROP_EN; | |
3540 | ||
3541 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
3542 | } | |
3543 | ||
3544 | #ifdef CONFIG_IXGBE_DCB | |
3545 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
3546 | #else | |
3547 | static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
3548 | #endif | |
3549 | { | |
3550 | int i; | |
3551 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
3552 | ||
3553 | if (adapter->ixgbe_ieee_pfc) | |
3554 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
3555 | ||
3556 | /* | |
3557 | * We should set the drop enable bit if: | |
3558 | * SR-IOV is enabled | |
3559 | * or | |
3560 | * Number of Rx queues > 1 and flow control is disabled | |
3561 | * | |
3562 | * This allows us to avoid head of line blocking for security | |
3563 | * and performance reasons. | |
3564 | */ | |
3565 | if (adapter->num_vfs || (adapter->num_rx_queues > 1 && | |
3566 | !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { | |
3567 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3568 | ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); | |
3569 | } else { | |
3570 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3571 | ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); | |
3572 | } | |
3573 | } | |
3574 | ||
e8e26350 | 3575 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 3576 | |
a6616b42 | 3577 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 3578 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 3579 | { |
45e9baa5 | 3580 | struct ixgbe_hw *hw = &adapter->hw; |
cc41ac7c | 3581 | u32 srrctl; |
bf29ee6c | 3582 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 3583 | |
45e9baa5 AD |
3584 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3585 | u16 mask = adapter->ring_feature[RING_F_RSS].mask; | |
cc41ac7c | 3586 | |
45e9baa5 AD |
3587 | /* |
3588 | * if VMDq is not active we must program one srrctl register | |
3589 | * per RSS queue since we have enabled RDRXCTL.MVMEN | |
3590 | */ | |
3591 | reg_idx &= mask; | |
3592 | } | |
cc41ac7c | 3593 | |
45e9baa5 AD |
3594 | /* configure header buffer length, needed for RSC */ |
3595 | srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; | |
afafd5b0 | 3596 | |
45e9baa5 | 3597 | /* configure the packet buffer length */ |
2de6aa3a AD |
3598 | if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) |
3599 | srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
3600 | else | |
3601 | srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
45e9baa5 AD |
3602 | |
3603 | /* configure descriptor type */ | |
f800326d | 3604 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 3605 | |
45e9baa5 | 3606 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 3607 | } |
9a799d71 | 3608 | |
dfaf891d | 3609 | /** |
a897a2ad | 3610 | * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries |
dfaf891d VZ |
3611 | * @adapter: device handle |
3612 | * | |
3613 | * - 82598/82599/X540: 128 | |
3614 | * - X550(non-SRIOV mode): 512 | |
3615 | * - X550(SRIOV mode): 64 | |
3616 | */ | |
7f276efb | 3617 | u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) |
dfaf891d VZ |
3618 | { |
3619 | if (adapter->hw.mac.type < ixgbe_mac_X550) | |
3620 | return 128; | |
3621 | else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3622 | return 64; | |
3623 | else | |
3624 | return 512; | |
3625 | } | |
3626 | ||
d3aa9c9f PA |
3627 | /** |
3628 | * ixgbe_store_key - Write the RSS key to HW | |
3629 | * @adapter: device handle | |
3630 | * | |
3631 | * Write the RSS key stored in adapter.rss_key to HW. | |
3632 | */ | |
3633 | void ixgbe_store_key(struct ixgbe_adapter *adapter) | |
3634 | { | |
3635 | struct ixgbe_hw *hw = &adapter->hw; | |
3636 | int i; | |
3637 | ||
3638 | for (i = 0; i < 10; i++) | |
3639 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); | |
3640 | } | |
3641 | ||
3dfbfc7e TN |
3642 | /** |
3643 | * ixgbe_init_rss_key - Initialize adapter RSS key | |
3644 | * @adapter: device handle | |
3645 | * | |
3646 | * Allocates and initializes the RSS key if it is not allocated. | |
3647 | **/ | |
3648 | static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) | |
3649 | { | |
3650 | u32 *rss_key; | |
3651 | ||
3652 | if (!adapter->rss_key) { | |
3653 | rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); | |
3654 | if (unlikely(!rss_key)) | |
3655 | return -ENOMEM; | |
3656 | ||
3657 | netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); | |
3658 | adapter->rss_key = rss_key; | |
3659 | } | |
3660 | ||
3661 | return 0; | |
3662 | } | |
3663 | ||
dfaf891d | 3664 | /** |
a897a2ad | 3665 | * ixgbe_store_reta - Write the RETA table to HW |
dfaf891d VZ |
3666 | * @adapter: device handle |
3667 | * | |
3668 | * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. | |
3669 | */ | |
1c7cf078 | 3670 | void ixgbe_store_reta(struct ixgbe_adapter *adapter) |
0cefafad | 3671 | { |
dfaf891d | 3672 | u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); |
05abb126 | 3673 | struct ixgbe_hw *hw = &adapter->hw; |
d1b849b9 | 3674 | u32 reta = 0; |
dfaf891d VZ |
3675 | u32 indices_multi; |
3676 | u8 *indir_tbl = adapter->rss_indir_tbl; | |
05abb126 | 3677 | |
0f9b232b | 3678 | /* Fill out the redirection table as follows: |
dfaf891d VZ |
3679 | * - 82598: 8 bit wide entries containing pair of 4 bit RSS |
3680 | * indices. | |
3681 | * - 82599/X540: 8 bit wide entries containing 4 bit RSS index | |
3682 | * - X550: 8 bit wide entries containing 6 bit RSS index | |
0f9b232b DS |
3683 | */ |
3684 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3685 | indices_multi = 0x11; | |
3686 | else | |
3687 | indices_multi = 0x1; | |
3688 | ||
dfaf891d VZ |
3689 | /* Write redirection table to HW */ |
3690 | for (i = 0; i < reta_entries; i++) { | |
3691 | reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; | |
0f9b232b DS |
3692 | if ((i & 3) == 3) { |
3693 | if (i < 128) | |
3694 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
3695 | else | |
3696 | IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), | |
3697 | reta); | |
dfaf891d | 3698 | reta = 0; |
0f9b232b DS |
3699 | } |
3700 | } | |
3701 | } | |
3702 | ||
dfaf891d | 3703 | /** |
a897a2ad | 3704 | * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) |
dfaf891d VZ |
3705 | * @adapter: device handle |
3706 | * | |
3707 | * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. | |
3708 | */ | |
3709 | static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) | |
0f9b232b | 3710 | { |
dfaf891d | 3711 | u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); |
0f9b232b DS |
3712 | struct ixgbe_hw *hw = &adapter->hw; |
3713 | u32 vfreta = 0; | |
dfaf891d VZ |
3714 | unsigned int pf_pool = adapter->num_vfs; |
3715 | ||
3716 | /* Write redirection table to HW */ | |
3717 | for (i = 0; i < reta_entries; i++) { | |
3718 | vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; | |
3719 | if ((i & 3) == 3) { | |
3720 | IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), | |
3721 | vfreta); | |
3722 | vfreta = 0; | |
3723 | } | |
3724 | } | |
3725 | } | |
3726 | ||
3727 | static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) | |
3728 | { | |
dfaf891d VZ |
3729 | u32 i, j; |
3730 | u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); | |
3731 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; | |
3732 | ||
e24fcf28 | 3733 | /* Program table for at least 4 queues w/ SR-IOV so that VFs can |
dfaf891d VZ |
3734 | * make full use of any rings they may have. We will use the |
3735 | * PSRTYPE register to control how many rings we use within the PF. | |
3736 | */ | |
e24fcf28 AD |
3737 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) |
3738 | rss_i = 4; | |
dfaf891d VZ |
3739 | |
3740 | /* Fill out hash function seeds */ | |
d3aa9c9f | 3741 | ixgbe_store_key(adapter); |
dfaf891d VZ |
3742 | |
3743 | /* Fill out redirection table */ | |
3744 | memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); | |
3745 | ||
3746 | for (i = 0, j = 0; i < reta_entries; i++, j++) { | |
3747 | if (j == rss_i) | |
3748 | j = 0; | |
3749 | ||
3750 | adapter->rss_indir_tbl[i] = j; | |
3751 | } | |
3752 | ||
3753 | ixgbe_store_reta(adapter); | |
3754 | } | |
3755 | ||
3756 | static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) | |
3757 | { | |
3758 | struct ixgbe_hw *hw = &adapter->hw; | |
0f9b232b DS |
3759 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; |
3760 | unsigned int pf_pool = adapter->num_vfs; | |
3761 | int i, j; | |
3762 | ||
3763 | /* Fill out hash function seeds */ | |
3764 | for (i = 0; i < 10; i++) | |
dfaf891d | 3765 | IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), |
3dfbfc7e | 3766 | *(adapter->rss_key + i)); |
0f9b232b DS |
3767 | |
3768 | /* Fill out the redirection table */ | |
3769 | for (i = 0, j = 0; i < 64; i++, j++) { | |
671c0adb | 3770 | if (j == rss_i) |
05abb126 | 3771 | j = 0; |
dfaf891d VZ |
3772 | |
3773 | adapter->rss_indir_tbl[i] = j; | |
05abb126 | 3774 | } |
dfaf891d VZ |
3775 | |
3776 | ixgbe_store_vfreta(adapter); | |
d1b849b9 DS |
3777 | } |
3778 | ||
3779 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) | |
3780 | { | |
3781 | struct ixgbe_hw *hw = &adapter->hw; | |
0f9b232b | 3782 | u32 mrqc = 0, rss_field = 0, vfmrqc = 0; |
d1b849b9 | 3783 | u32 rxcsum; |
0cefafad | 3784 | |
05abb126 AD |
3785 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
3786 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
3787 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
3788 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
3789 | ||
671c0adb | 3790 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
fbe7ca7f | 3791 | if (adapter->ring_feature[RING_F_RSS].mask) |
671c0adb | 3792 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 | 3793 | } else { |
671c0adb AD |
3794 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
3795 | ||
3796 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3797 | if (tcs > 4) | |
3798 | mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ | |
3799 | else if (tcs > 1) | |
3800 | mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ | |
e24fcf28 AD |
3801 | else if (adapter->ring_feature[RING_F_VMDQ].mask == |
3802 | IXGBE_82599_VMDQ_4Q_MASK) | |
671c0adb | 3803 | mrqc = IXGBE_MRQC_VMDQRSS32EN; |
8b1c0b24 | 3804 | else |
671c0adb | 3805 | mrqc = IXGBE_MRQC_VMDQRSS64EN; |
e6b41c88 ET |
3806 | |
3807 | /* Enable L3/L4 for Tx Switched packets */ | |
3808 | mrqc |= IXGBE_MRQC_L3L4TXSWEN; | |
671c0adb AD |
3809 | } else { |
3810 | if (tcs > 4) | |
8b1c0b24 | 3811 | mrqc = IXGBE_MRQC_RTRSS8TCEN; |
671c0adb AD |
3812 | else if (tcs > 1) |
3813 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
3814 | else | |
3815 | mrqc = IXGBE_MRQC_RSSEN; | |
8b1c0b24 | 3816 | } |
0cefafad JB |
3817 | } |
3818 | ||
05abb126 | 3819 | /* Perform hash on these packet types */ |
d1b849b9 DS |
3820 | rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
3821 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | | |
3822 | IXGBE_MRQC_RSS_FIELD_IPV6 | | |
3823 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
05abb126 | 3824 | |
ef6afc0c | 3825 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) |
d1b849b9 | 3826 | rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; |
ef6afc0c | 3827 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) |
d1b849b9 | 3828 | rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; |
ef6afc0c | 3829 | |
0f9b232b DS |
3830 | if ((hw->mac.type >= ixgbe_mac_X550) && |
3831 | (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { | |
3832 | unsigned int pf_pool = adapter->num_vfs; | |
3833 | ||
3834 | /* Enable VF RSS mode */ | |
3835 | mrqc |= IXGBE_MRQC_MULTIPLE_RSS; | |
3836 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
3837 | ||
3838 | /* Setup RSS through the VF registers */ | |
dfaf891d | 3839 | ixgbe_setup_vfreta(adapter); |
0f9b232b DS |
3840 | vfmrqc = IXGBE_MRQC_RSSEN; |
3841 | vfmrqc |= rss_field; | |
3842 | IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); | |
3843 | } else { | |
dfaf891d | 3844 | ixgbe_setup_reta(adapter); |
0f9b232b DS |
3845 | mrqc |= rss_field; |
3846 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
3847 | } | |
0cefafad JB |
3848 | } |
3849 | ||
bb5a9ad2 NS |
3850 | /** |
3851 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
3852 | * @adapter: address of board private structure | |
3853 | * @index: index of ring to set | |
bb5a9ad2 | 3854 | **/ |
082757af | 3855 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 3856 | struct ixgbe_ring *ring) |
bb5a9ad2 | 3857 | { |
bb5a9ad2 | 3858 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 3859 | u32 rscctrl; |
bf29ee6c | 3860 | u8 reg_idx = ring->reg_idx; |
7367096a | 3861 | |
7d637bcc | 3862 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 3863 | return; |
bb5a9ad2 | 3864 | |
7367096a | 3865 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
3866 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
3867 | /* | |
3868 | * we must limit the number of descriptors so that the | |
3869 | * total size of max desc * buf_len is not greater | |
642c680e | 3870 | * than 65536 |
bb5a9ad2 | 3871 | */ |
f800326d | 3872 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; |
7367096a | 3873 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
3874 | } |
3875 | ||
9e10e045 AD |
3876 | #define IXGBE_MAX_RX_DESC_POLL 10 |
3877 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
3878 | struct ixgbe_ring *ring) | |
3879 | { | |
3880 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
3881 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
3882 | u32 rxdctl; | |
bf29ee6c | 3883 | u8 reg_idx = ring->reg_idx; |
9e10e045 | 3884 | |
b0483c8f MR |
3885 | if (ixgbe_removed(hw->hw_addr)) |
3886 | return; | |
9e10e045 AD |
3887 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ |
3888 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3889 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3890 | return; | |
3891 | ||
3892 | do { | |
032b4325 | 3893 | usleep_range(1000, 2000); |
9e10e045 AD |
3894 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3895 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3896 | ||
3897 | if (!wait_loop) { | |
3898 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
3899 | "the polling period\n", reg_idx); | |
3900 | } | |
3901 | } | |
3902 | ||
2d39d576 YZ |
3903 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
3904 | struct ixgbe_ring *ring) | |
3905 | { | |
3906 | struct ixgbe_hw *hw = &adapter->hw; | |
3907 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
3908 | u32 rxdctl; | |
3909 | u8 reg_idx = ring->reg_idx; | |
3910 | ||
b0483c8f MR |
3911 | if (ixgbe_removed(hw->hw_addr)) |
3912 | return; | |
2d39d576 YZ |
3913 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3914 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
3915 | ||
3916 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
3917 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3918 | ||
3919 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3920 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3921 | return; | |
3922 | ||
3923 | /* the hardware may take up to 100us to really disable the rx queue */ | |
3924 | do { | |
3925 | udelay(10); | |
3926 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3927 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3928 | ||
3929 | if (!wait_loop) { | |
3930 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
3931 | "the polling period\n", reg_idx); | |
3932 | } | |
3933 | } | |
3934 | ||
84418e3b AD |
3935 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
3936 | struct ixgbe_ring *ring) | |
acd37177 AD |
3937 | { |
3938 | struct ixgbe_hw *hw = &adapter->hw; | |
c3630cc4 | 3939 | union ixgbe_adv_rx_desc *rx_desc; |
acd37177 | 3940 | u64 rdba = ring->dma; |
9e10e045 | 3941 | u32 rxdctl; |
bf29ee6c | 3942 | u8 reg_idx = ring->reg_idx; |
acd37177 | 3943 | |
9e10e045 AD |
3944 | /* disable queue to avoid issues while updating state */ |
3945 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 3946 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3947 | |
acd37177 AD |
3948 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3949 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3950 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3951 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
8b75451b NP |
3952 | /* Force flushing of IXGBE_RDLEN to prevent MDD */ |
3953 | IXGBE_WRITE_FLUSH(hw); | |
3954 | ||
acd37177 AD |
3955 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); |
3956 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
2a1a091c | 3957 | ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3958 | |
3959 | ixgbe_configure_srrctl(adapter, ring); | |
3960 | ixgbe_configure_rscctl(adapter, ring); | |
3961 | ||
3962 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
3963 | /* | |
3964 | * enable cache line friendly hardware writes: | |
3965 | * PTHRESH=32 descriptors (half the internal cache), | |
3966 | * this also removes ugly rx_no_buffer_count increment | |
3967 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3968 | * WTHRESH=8 burst writeback up to two cache lines | |
3969 | */ | |
3970 | rxdctl &= ~0x3FFFFF; | |
3971 | rxdctl |= 0x080420; | |
2de6aa3a AD |
3972 | #if (PAGE_SIZE < 8192) |
3973 | } else { | |
3974 | rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | | |
3975 | IXGBE_RXDCTL_RLPML_EN); | |
3976 | ||
3977 | /* Limit the maximum frame size so we don't overrun the skb */ | |
3978 | if (ring_uses_build_skb(ring) && | |
3979 | !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) | |
541ea69a | 3980 | rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | |
2de6aa3a AD |
3981 | IXGBE_RXDCTL_RLPML_EN; |
3982 | #endif | |
9e10e045 AD |
3983 | } |
3984 | ||
ffed21bc AD |
3985 | /* initialize rx_buffer_info */ |
3986 | memset(ring->rx_buffer_info, 0, | |
3987 | sizeof(struct ixgbe_rx_buffer) * ring->count); | |
3988 | ||
c3630cc4 AD |
3989 | /* initialize Rx descriptor 0 */ |
3990 | rx_desc = IXGBE_RX_DESC(ring, 0); | |
3991 | rx_desc->wb.upper.length = 0; | |
3992 | ||
9e10e045 AD |
3993 | /* enable receive descriptor ring */ |
3994 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3995 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3996 | ||
3997 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 3998 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
3999 | } |
4000 | ||
48654521 AD |
4001 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
4002 | { | |
4003 | struct ixgbe_hw *hw = &adapter->hw; | |
fbe7ca7f | 4004 | int rss_i = adapter->ring_feature[RING_F_RSS].indices; |
2a47fa45 | 4005 | u16 pool; |
48654521 AD |
4006 | |
4007 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
4008 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
4009 | IXGBE_PSRTYPE_UDPHDR | |
4010 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 4011 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 4012 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
4013 | |
4014 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4015 | return; | |
4016 | ||
fbe7ca7f | 4017 | if (rss_i > 3) |
b4f47a48 | 4018 | psrtype |= 2u << 29; |
fbe7ca7f | 4019 | else if (rss_i > 1) |
b4f47a48 | 4020 | psrtype |= 1u << 29; |
48654521 | 4021 | |
2a47fa45 JF |
4022 | for_each_set_bit(pool, &adapter->fwd_bitmask, 32) |
4023 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); | |
48654521 AD |
4024 | } |
4025 | ||
f5b4a52e AD |
4026 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
4027 | { | |
4028 | struct ixgbe_hw *hw = &adapter->hw; | |
f5b4a52e | 4029 | u32 reg_offset, vf_shift; |
435b19f6 | 4030 | u32 gcr_ext, vmdctl; |
de4c7f65 | 4031 | int i; |
f5b4a52e AD |
4032 | |
4033 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
4034 | return; | |
4035 | ||
4036 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
435b19f6 AD |
4037 | vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; |
4038 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
1d9c0bfd | 4039 | vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; |
435b19f6 AD |
4040 | vmdctl |= IXGBE_VT_CTL_REPLEN; |
4041 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
f5b4a52e | 4042 | |
1d9c0bfd AD |
4043 | vf_shift = VMDQ_P(0) % 32; |
4044 | reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; | |
f5b4a52e AD |
4045 | |
4046 | /* Enable only the PF's pool for Tx/Rx */ | |
11f2b494 | 4047 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); |
435b19f6 | 4048 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); |
11f2b494 | 4049 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); |
435b19f6 | 4050 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); |
aa2bacb6 | 4051 | if (adapter->bridge_mode == BRIDGE_MODE_VEB) |
9b735984 | 4052 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); |
f5b4a52e AD |
4053 | |
4054 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
1d9c0bfd | 4055 | hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); |
f5b4a52e | 4056 | |
16369564 AD |
4057 | /* clear VLAN promisc flag so VFTA will be updated if necessary */ |
4058 | adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; | |
4059 | ||
f5b4a52e AD |
4060 | /* |
4061 | * Set up VF register offsets for selected VT Mode, | |
4062 | * i.e. 32 or 64 VFs for SR-IOV | |
4063 | */ | |
73079ea0 AD |
4064 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { |
4065 | case IXGBE_82599_VMDQ_8Q_MASK: | |
4066 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; | |
4067 | break; | |
4068 | case IXGBE_82599_VMDQ_4Q_MASK: | |
4069 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; | |
4070 | break; | |
4071 | default: | |
4072 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; | |
4073 | break; | |
4074 | } | |
4075 | ||
f5b4a52e AD |
4076 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); |
4077 | ||
de4c7f65 | 4078 | for (i = 0; i < adapter->num_vfs; i++) { |
77f192af ET |
4079 | /* configure spoof checking */ |
4080 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, | |
4081 | adapter->vfinfo[i].spoofchk_enabled); | |
e65ce0d3 VZ |
4082 | |
4083 | /* Enable/Disable RSS query feature */ | |
4084 | ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, | |
4085 | adapter->vfinfo[i].rss_query_enabled); | |
de4c7f65 | 4086 | } |
f5b4a52e AD |
4087 | } |
4088 | ||
477de6ed | 4089 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 4090 | { |
9a799d71 AK |
4091 | struct ixgbe_hw *hw = &adapter->hw; |
4092 | struct net_device *netdev = adapter->netdev; | |
4093 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
4094 | struct ixgbe_ring *rx_ring; |
4095 | int i; | |
4096 | u32 mhadd, hlreg0; | |
48654521 | 4097 | |
63f39bd1 | 4098 | #ifdef IXGBE_FCOE |
477de6ed AD |
4099 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
4100 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
4101 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
4102 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 4103 | |
477de6ed | 4104 | #endif /* IXGBE_FCOE */ |
872844dd AD |
4105 | |
4106 | /* adjust max frame to be at least the size of a standard frame */ | |
4107 | if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) | |
4108 | max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); | |
4109 | ||
477de6ed AD |
4110 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
4111 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
4112 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
4113 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
4114 | ||
4115 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
4116 | } | |
4117 | ||
4118 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
4119 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
4120 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
4121 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 4122 | |
0cefafad JB |
4123 | /* |
4124 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
4125 | * the Base and Length of the Rx Descriptor Ring | |
4126 | */ | |
9a799d71 | 4127 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 4128 | rx_ring = adapter->rx_ring[i]; |
4f4542bf AD |
4129 | |
4130 | clear_ring_rsc_enabled(rx_ring); | |
4131 | clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); | |
2de6aa3a | 4132 | clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); |
4f4542bf | 4133 | |
7d637bcc AD |
4134 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
4135 | set_ring_rsc_enabled(rx_ring); | |
4f4542bf AD |
4136 | |
4137 | if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) | |
4138 | set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); | |
2de6aa3a | 4139 | |
6f429223 | 4140 | clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); |
2de6aa3a AD |
4141 | if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) |
4142 | continue; | |
4143 | ||
4144 | set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); | |
4145 | ||
4146 | #if (PAGE_SIZE < 8192) | |
4147 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
4148 | set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); | |
4149 | ||
541ea69a AD |
4150 | if (IXGBE_2K_TOO_SMALL_WITH_PADDING || |
4151 | (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) | |
2de6aa3a AD |
4152 | set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); |
4153 | #endif | |
477de6ed | 4154 | } |
477de6ed AD |
4155 | } |
4156 | ||
7367096a AD |
4157 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
4158 | { | |
4159 | struct ixgbe_hw *hw = &adapter->hw; | |
4160 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
4161 | ||
4162 | switch (hw->mac.type) { | |
4163 | case ixgbe_mac_82598EB: | |
4164 | /* | |
4165 | * For VMDq support of different descriptor types or | |
4166 | * buffer sizes through the use of multiple SRRCTL | |
4167 | * registers, RDRXCTL.MVMEN must be set to 1 | |
4168 | * | |
4169 | * also, the manual doesn't mention it clearly but DCA hints | |
4170 | * will only use queue 0's tags unless this bit is set. Side | |
4171 | * effects of setting this bit are only that SRRCTL must be | |
4172 | * fully programmed [0..15] | |
4173 | */ | |
4174 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
4175 | break; | |
052a1a72 MR |
4176 | case ixgbe_mac_X550: |
4177 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4178 | case ixgbe_mac_x550em_a: |
f961ddae MR |
4179 | if (adapter->num_vfs) |
4180 | rdrxctl |= IXGBE_RDRXCTL_PSP; | |
93df9465 | 4181 | /* fall through */ |
7367096a | 4182 | case ixgbe_mac_82599EB: |
b93a2226 | 4183 | case ixgbe_mac_X540: |
7367096a AD |
4184 | /* Disable RSC for ACK packets */ |
4185 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
4186 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
4187 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
4188 | /* hardware requires some bits to be set by default */ | |
4189 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
4190 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
4191 | break; | |
4192 | default: | |
4193 | /* We should do nothing since we don't know this hardware */ | |
4194 | return; | |
4195 | } | |
4196 | ||
4197 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
4198 | } | |
4199 | ||
477de6ed AD |
4200 | /** |
4201 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
4202 | * @adapter: board private structure | |
4203 | * | |
4204 | * Configure the Rx unit of the MAC after a reset. | |
4205 | **/ | |
4206 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
4207 | { | |
4208 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed | 4209 | int i; |
6dcc28b9 | 4210 | u32 rxctrl, rfctl; |
477de6ed AD |
4211 | |
4212 | /* disable receives while setting up the descriptors */ | |
1f9ac57c | 4213 | hw->mac.ops.disable_rx(hw); |
477de6ed AD |
4214 | |
4215 | ixgbe_setup_psrtype(adapter); | |
7367096a | 4216 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 4217 | |
6dcc28b9 JK |
4218 | /* RSC Setup */ |
4219 | rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); | |
4220 | rfctl &= ~IXGBE_RFCTL_RSC_DIS; | |
4221 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) | |
4222 | rfctl |= IXGBE_RFCTL_RSC_DIS; | |
a21d0822 ET |
4223 | |
4224 | /* disable NFS filtering */ | |
4225 | rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); | |
6dcc28b9 JK |
4226 | IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); |
4227 | ||
9e10e045 | 4228 | /* Program registers for the distribution of queues */ |
f5b4a52e | 4229 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 4230 | |
477de6ed AD |
4231 | /* set_rx_buffer_len must be called before ring initialization */ |
4232 | ixgbe_set_rx_buffer_len(adapter); | |
4233 | ||
4234 | /* | |
4235 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
4236 | * the Base and Length of the Rx Descriptor Ring | |
4237 | */ | |
9e10e045 AD |
4238 | for (i = 0; i < adapter->num_rx_queues; i++) |
4239 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 4240 | |
1f9ac57c | 4241 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
9e10e045 AD |
4242 | /* disable drop enable for 82598 parts */ |
4243 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4244 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
4245 | ||
4246 | /* enable all receives */ | |
4247 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
4248 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
4249 | } |
4250 | ||
80d5c368 PM |
4251 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, |
4252 | __be16 proto, u16 vid) | |
068c89b0 DS |
4253 | { |
4254 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4255 | struct ixgbe_hw *hw = &adapter->hw; | |
4256 | ||
4257 | /* add VID to filter table */ | |
18be4fce AD |
4258 | if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) |
4259 | hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); | |
4260 | ||
f62bbb5e | 4261 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
4262 | |
4263 | return 0; | |
068c89b0 DS |
4264 | } |
4265 | ||
e1d0a2af AD |
4266 | static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) |
4267 | { | |
4268 | u32 vlvf; | |
4269 | int idx; | |
4270 | ||
4271 | /* short cut the special case */ | |
4272 | if (vlan == 0) | |
4273 | return 0; | |
4274 | ||
4275 | /* Search for the vlan id in the VLVF entries */ | |
4276 | for (idx = IXGBE_VLVF_ENTRIES; --idx;) { | |
4277 | vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); | |
4278 | if ((vlvf & VLAN_VID_MASK) == vlan) | |
4279 | break; | |
4280 | } | |
4281 | ||
4282 | return idx; | |
4283 | } | |
4284 | ||
4285 | void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) | |
4286 | { | |
4287 | struct ixgbe_hw *hw = &adapter->hw; | |
4288 | u32 bits, word; | |
4289 | int idx; | |
4290 | ||
4291 | idx = ixgbe_find_vlvf_entry(hw, vid); | |
4292 | if (!idx) | |
4293 | return; | |
4294 | ||
4295 | /* See if any other pools are set for this VLAN filter | |
4296 | * entry other than the PF. | |
4297 | */ | |
4298 | word = idx * 2 + (VMDQ_P(0) / 32); | |
b4f47a48 | 4299 | bits = ~BIT(VMDQ_P(0) % 32); |
e1d0a2af AD |
4300 | bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); |
4301 | ||
4302 | /* Disable the filter so this falls into the default pool. */ | |
4303 | if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { | |
4304 | if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) | |
4305 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); | |
4306 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); | |
4307 | } | |
4308 | } | |
4309 | ||
80d5c368 PM |
4310 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, |
4311 | __be16 proto, u16 vid) | |
068c89b0 DS |
4312 | { |
4313 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4314 | struct ixgbe_hw *hw = &adapter->hw; | |
4315 | ||
068c89b0 | 4316 | /* remove VID from filter table */ |
18be4fce | 4317 | if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) |
e1d0a2af AD |
4318 | hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); |
4319 | ||
f62bbb5e | 4320 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
4321 | |
4322 | return 0; | |
068c89b0 DS |
4323 | } |
4324 | ||
f62bbb5e JG |
4325 | /** |
4326 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
4327 | * @adapter: driver data | |
4328 | */ | |
4329 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
4330 | { | |
4331 | struct ixgbe_hw *hw = &adapter->hw; | |
4332 | u32 vlnctrl; | |
5f6c0181 JB |
4333 | int i, j; |
4334 | ||
4335 | switch (hw->mac.type) { | |
4336 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
4337 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
4338 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
4339 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
4340 | break; | |
4341 | case ixgbe_mac_82599EB: | |
b93a2226 | 4342 | case ixgbe_mac_X540: |
9a75a1ac DS |
4343 | case ixgbe_mac_X550: |
4344 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4345 | case ixgbe_mac_x550em_a: |
5f6c0181 | 4346 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2a47fa45 JF |
4347 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
4348 | ||
4349 | if (ring->l2_accel_priv) | |
4350 | continue; | |
4351 | j = ring->reg_idx; | |
5f6c0181 JB |
4352 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
4353 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
4354 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
4355 | } | |
4356 | break; | |
4357 | default: | |
4358 | break; | |
4359 | } | |
4360 | } | |
4361 | ||
4362 | /** | |
f62bbb5e | 4363 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
4364 | * @adapter: driver data |
4365 | */ | |
f62bbb5e | 4366 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
4367 | { |
4368 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 4369 | u32 vlnctrl; |
5f6c0181 JB |
4370 | int i, j; |
4371 | ||
4372 | switch (hw->mac.type) { | |
4373 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
4374 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
4375 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
4376 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
4377 | break; | |
4378 | case ixgbe_mac_82599EB: | |
b93a2226 | 4379 | case ixgbe_mac_X540: |
9a75a1ac DS |
4380 | case ixgbe_mac_X550: |
4381 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4382 | case ixgbe_mac_x550em_a: |
5f6c0181 | 4383 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2a47fa45 JF |
4384 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
4385 | ||
4386 | if (ring->l2_accel_priv) | |
4387 | continue; | |
4388 | j = ring->reg_idx; | |
5f6c0181 JB |
4389 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
4390 | vlnctrl |= IXGBE_RXDCTL_VME; | |
4391 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
4392 | } | |
4393 | break; | |
4394 | default: | |
4395 | break; | |
4396 | } | |
4397 | } | |
4398 | ||
16369564 AD |
4399 | static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) |
4400 | { | |
4401 | struct ixgbe_hw *hw = &adapter->hw; | |
4402 | u32 vlnctrl, i; | |
4403 | ||
f60439bc AD |
4404 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
4405 | ||
691e4121 ET |
4406 | if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { |
4407 | /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ | |
4408 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
4409 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
4410 | } else { | |
f60439bc | 4411 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
16369564 AD |
4412 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
4413 | return; | |
4414 | } | |
4415 | ||
691e4121 ET |
4416 | /* Nothing to do for 82598 */ |
4417 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4418 | return; | |
4419 | ||
16369564 AD |
4420 | /* We are already in VLAN promisc, nothing to do */ |
4421 | if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) | |
4422 | return; | |
4423 | ||
4424 | /* Set flag so we don't redo unnecessary work */ | |
4425 | adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; | |
4426 | ||
4427 | /* Add PF to all active pools */ | |
4428 | for (i = IXGBE_VLVF_ENTRIES; --i;) { | |
4429 | u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); | |
4430 | u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); | |
4431 | ||
b4f47a48 | 4432 | vlvfb |= BIT(VMDQ_P(0) % 32); |
16369564 AD |
4433 | IXGBE_WRITE_REG(hw, reg_offset, vlvfb); |
4434 | } | |
4435 | ||
4436 | /* Set all bits in the VLAN filter table array */ | |
4437 | for (i = hw->mac.vft_size; i--;) | |
4438 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); | |
4439 | } | |
4440 | ||
4441 | #define VFTA_BLOCK_SIZE 8 | |
4442 | static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) | |
4443 | { | |
4444 | struct ixgbe_hw *hw = &adapter->hw; | |
4445 | u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; | |
4446 | u32 vid_start = vfta_offset * 32; | |
4447 | u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); | |
4448 | u32 i, vid, word, bits; | |
4449 | ||
4450 | for (i = IXGBE_VLVF_ENTRIES; --i;) { | |
4451 | u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); | |
4452 | ||
4453 | /* pull VLAN ID from VLVF */ | |
4454 | vid = vlvf & VLAN_VID_MASK; | |
4455 | ||
4456 | /* only concern outselves with a certain range */ | |
4457 | if (vid < vid_start || vid >= vid_end) | |
4458 | continue; | |
4459 | ||
4460 | if (vlvf) { | |
4461 | /* record VLAN ID in VFTA */ | |
b4f47a48 | 4462 | vfta[(vid - vid_start) / 32] |= BIT(vid % 32); |
16369564 AD |
4463 | |
4464 | /* if PF is part of this then continue */ | |
4465 | if (test_bit(vid, adapter->active_vlans)) | |
4466 | continue; | |
4467 | } | |
4468 | ||
4469 | /* remove PF from the pool */ | |
4470 | word = i * 2 + VMDQ_P(0) / 32; | |
b4f47a48 | 4471 | bits = ~BIT(VMDQ_P(0) % 32); |
16369564 AD |
4472 | bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); |
4473 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); | |
4474 | } | |
4475 | ||
4476 | /* extract values from active_vlans and write back to VFTA */ | |
4477 | for (i = VFTA_BLOCK_SIZE; i--;) { | |
4478 | vid = (vfta_offset + i) * 32; | |
4479 | word = vid / BITS_PER_LONG; | |
4480 | bits = vid % BITS_PER_LONG; | |
4481 | ||
4482 | vfta[i] |= adapter->active_vlans[word] >> bits; | |
4483 | ||
4484 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); | |
4485 | } | |
4486 | } | |
4487 | ||
4488 | static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) | |
4489 | { | |
4490 | struct ixgbe_hw *hw = &adapter->hw; | |
4491 | u32 vlnctrl, i; | |
4492 | ||
f60439bc AD |
4493 | /* Set VLAN filtering to enabled */ |
4494 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
4495 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
4496 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
4497 | ||
691e4121 ET |
4498 | if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || |
4499 | hw->mac.type == ixgbe_mac_82598EB) | |
16369564 | 4500 | return; |
16369564 AD |
4501 | |
4502 | /* We are not in VLAN promisc, nothing to do */ | |
4503 | if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) | |
4504 | return; | |
4505 | ||
4506 | /* Set flag so we don't redo unnecessary work */ | |
4507 | adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; | |
4508 | ||
4509 | for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) | |
4510 | ixgbe_scrub_vfta(adapter, i); | |
4511 | } | |
4512 | ||
9a799d71 AK |
4513 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
4514 | { | |
06bb1c39 | 4515 | u16 vid = 1; |
9a799d71 | 4516 | |
80d5c368 | 4517 | ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); |
f62bbb5e | 4518 | |
06bb1c39 | 4519 | for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) |
80d5c368 | 4520 | ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); |
9a799d71 AK |
4521 | } |
4522 | ||
b335e75b JK |
4523 | /** |
4524 | * ixgbe_write_mc_addr_list - write multicast addresses to MTA | |
4525 | * @netdev: network interface device structure | |
4526 | * | |
4527 | * Writes multicast address list to the MTA hash table. | |
4528 | * Returns: -ENOMEM on failure | |
4529 | * 0 on no addresses written | |
4530 | * X on writing X addresses to MTA | |
4531 | **/ | |
4532 | static int ixgbe_write_mc_addr_list(struct net_device *netdev) | |
4533 | { | |
4534 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4535 | struct ixgbe_hw *hw = &adapter->hw; | |
4536 | ||
4537 | if (!netif_running(netdev)) | |
4538 | return 0; | |
4539 | ||
4540 | if (hw->mac.ops.update_mc_addr_list) | |
4541 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
4542 | else | |
4543 | return -ENOMEM; | |
4544 | ||
4545 | #ifdef CONFIG_PCI_IOV | |
5d7daa35 | 4546 | ixgbe_restore_vf_multicasts(adapter); |
b335e75b JK |
4547 | #endif |
4548 | ||
4549 | return netdev_mc_count(netdev); | |
4550 | } | |
4551 | ||
5d7daa35 JK |
4552 | #ifdef CONFIG_PCI_IOV |
4553 | void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) | |
4554 | { | |
c9f53e63 | 4555 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4556 | struct ixgbe_hw *hw = &adapter->hw; |
4557 | int i; | |
c9f53e63 AD |
4558 | |
4559 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { | |
4560 | mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; | |
4561 | ||
4562 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) | |
4563 | hw->mac.ops.set_rar(hw, i, | |
4564 | mac_table->addr, | |
4565 | mac_table->pool, | |
5d7daa35 JK |
4566 | IXGBE_RAH_AV); |
4567 | else | |
4568 | hw->mac.ops.clear_rar(hw, i); | |
5d7daa35 JK |
4569 | } |
4570 | } | |
5d7daa35 | 4571 | |
c9f53e63 | 4572 | #endif |
5d7daa35 JK |
4573 | static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) |
4574 | { | |
c9f53e63 | 4575 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4576 | struct ixgbe_hw *hw = &adapter->hw; |
4577 | int i; | |
5d7daa35 | 4578 | |
c9f53e63 AD |
4579 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4580 | if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) | |
4581 | continue; | |
4582 | ||
4583 | mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; | |
4584 | ||
4585 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) | |
4586 | hw->mac.ops.set_rar(hw, i, | |
4587 | mac_table->addr, | |
4588 | mac_table->pool, | |
4589 | IXGBE_RAH_AV); | |
4590 | else | |
4591 | hw->mac.ops.clear_rar(hw, i); | |
5d7daa35 JK |
4592 | } |
4593 | } | |
4594 | ||
4595 | static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) | |
4596 | { | |
c9f53e63 | 4597 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 | 4598 | struct ixgbe_hw *hw = &adapter->hw; |
c9f53e63 | 4599 | int i; |
5d7daa35 | 4600 | |
c9f53e63 AD |
4601 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4602 | mac_table->state |= IXGBE_MAC_STATE_MODIFIED; | |
4603 | mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; | |
5d7daa35 | 4604 | } |
c9f53e63 | 4605 | |
5d7daa35 JK |
4606 | ixgbe_sync_mac_table(adapter); |
4607 | } | |
4608 | ||
c9f53e63 | 4609 | static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) |
5d7daa35 | 4610 | { |
c9f53e63 | 4611 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4612 | struct ixgbe_hw *hw = &adapter->hw; |
4613 | int i, count = 0; | |
4614 | ||
c9f53e63 AD |
4615 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4616 | /* do not count default RAR as available */ | |
4617 | if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) | |
4618 | continue; | |
4619 | ||
4620 | /* only count unused and addresses that belong to us */ | |
4621 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { | |
4622 | if (mac_table->pool != pool) | |
4623 | continue; | |
4624 | } | |
4625 | ||
4626 | count++; | |
5d7daa35 | 4627 | } |
c9f53e63 | 4628 | |
5d7daa35 JK |
4629 | return count; |
4630 | } | |
4631 | ||
4632 | /* this function destroys the first RAR entry */ | |
c9f53e63 | 4633 | static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) |
5d7daa35 | 4634 | { |
c9f53e63 | 4635 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4636 | struct ixgbe_hw *hw = &adapter->hw; |
4637 | ||
c9f53e63 AD |
4638 | memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); |
4639 | mac_table->pool = VMDQ_P(0); | |
4640 | ||
4641 | mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; | |
4642 | ||
4643 | hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, | |
5d7daa35 JK |
4644 | IXGBE_RAH_AV); |
4645 | } | |
4646 | ||
c9f53e63 AD |
4647 | int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, |
4648 | const u8 *addr, u16 pool) | |
5d7daa35 | 4649 | { |
c9f53e63 | 4650 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4651 | struct ixgbe_hw *hw = &adapter->hw; |
4652 | int i; | |
4653 | ||
4654 | if (is_zero_ether_addr(addr)) | |
4655 | return -EINVAL; | |
4656 | ||
c9f53e63 AD |
4657 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4658 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) | |
5d7daa35 | 4659 | continue; |
c9f53e63 AD |
4660 | |
4661 | ether_addr_copy(mac_table->addr, addr); | |
4662 | mac_table->pool = pool; | |
4663 | ||
4664 | mac_table->state |= IXGBE_MAC_STATE_MODIFIED | | |
4665 | IXGBE_MAC_STATE_IN_USE; | |
4666 | ||
5d7daa35 | 4667 | ixgbe_sync_mac_table(adapter); |
c9f53e63 | 4668 | |
5d7daa35 JK |
4669 | return i; |
4670 | } | |
c9f53e63 | 4671 | |
5d7daa35 JK |
4672 | return -ENOMEM; |
4673 | } | |
4674 | ||
c9f53e63 AD |
4675 | int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, |
4676 | const u8 *addr, u16 pool) | |
5d7daa35 | 4677 | { |
c9f53e63 | 4678 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 | 4679 | struct ixgbe_hw *hw = &adapter->hw; |
c9f53e63 | 4680 | int i; |
5d7daa35 JK |
4681 | |
4682 | if (is_zero_ether_addr(addr)) | |
4683 | return -EINVAL; | |
4684 | ||
c9f53e63 AD |
4685 | /* search table for addr, if found clear IN_USE flag and sync */ |
4686 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { | |
4687 | /* we can only delete an entry if it is in use */ | |
4688 | if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) | |
4689 | continue; | |
4690 | /* we only care about entries that belong to the given pool */ | |
4691 | if (mac_table->pool != pool) | |
4692 | continue; | |
4693 | /* we only care about a specific MAC address */ | |
4694 | if (!ether_addr_equal(addr, mac_table->addr)) | |
4695 | continue; | |
4696 | ||
4697 | mac_table->state |= IXGBE_MAC_STATE_MODIFIED; | |
4698 | mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; | |
4699 | ||
4700 | ixgbe_sync_mac_table(adapter); | |
4701 | ||
4702 | return 0; | |
5d7daa35 | 4703 | } |
c9f53e63 | 4704 | |
5d7daa35 JK |
4705 | return -ENOMEM; |
4706 | } | |
2850062a AD |
4707 | /** |
4708 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
4709 | * @netdev: network interface device structure | |
4710 | * | |
4711 | * Writes unicast address list to the RAR table. | |
4712 | * Returns: -ENOMEM on failure/insufficient address space | |
4713 | * 0 on no addresses written | |
4714 | * X on writing X addresses to the RAR table | |
4715 | **/ | |
5d7daa35 | 4716 | static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) |
2850062a AD |
4717 | { |
4718 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2850062a AD |
4719 | int count = 0; |
4720 | ||
4721 | /* return ENOMEM indicating insufficient memory for addresses */ | |
c9f53e63 | 4722 | if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn)) |
2850062a AD |
4723 | return -ENOMEM; |
4724 | ||
95447461 | 4725 | if (!netdev_uc_empty(netdev)) { |
2850062a | 4726 | struct netdev_hw_addr *ha; |
2850062a | 4727 | netdev_for_each_uc_addr(ha, netdev) { |
5d7daa35 JK |
4728 | ixgbe_del_mac_filter(adapter, ha->addr, vfn); |
4729 | ixgbe_add_mac_filter(adapter, ha->addr, vfn); | |
2850062a AD |
4730 | count++; |
4731 | } | |
4732 | } | |
2850062a AD |
4733 | return count; |
4734 | } | |
4735 | ||
0f079d22 AD |
4736 | static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) |
4737 | { | |
4738 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4739 | int ret; | |
4740 | ||
4741 | ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); | |
4742 | ||
4743 | return min_t(int, ret, 0); | |
4744 | } | |
4745 | ||
4746 | static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) | |
4747 | { | |
4748 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4749 | ||
4750 | ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); | |
4751 | ||
4752 | return 0; | |
4753 | } | |
4754 | ||
9a799d71 | 4755 | /** |
2c5645cf | 4756 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
4757 | * @netdev: network interface device structure |
4758 | * | |
2c5645cf CL |
4759 | * The set_rx_method entry point is called whenever the unicast/multicast |
4760 | * address list or the network interface flags are updated. This routine is | |
4761 | * responsible for configuring the hardware for proper unicast, multicast and | |
4762 | * promiscuous mode. | |
9a799d71 | 4763 | **/ |
7f870475 | 4764 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
4765 | { |
4766 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4767 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a | 4768 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
0c5a6166 | 4769 | netdev_features_t features = netdev->features; |
2850062a | 4770 | int count; |
9a799d71 AK |
4771 | |
4772 | /* Check for Promiscuous and All Multicast modes */ | |
9a799d71 AK |
4773 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
4774 | ||
f5dc442b | 4775 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 4776 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
4777 | fctrl |= IXGBE_FCTRL_BAM; |
4778 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
4779 | fctrl |= IXGBE_FCTRL_PMCF; | |
4780 | ||
2850062a AD |
4781 | /* clear the bits we are changing the status of */ |
4782 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
9a799d71 | 4783 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 4784 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 4785 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
b335e75b | 4786 | vmolr |= IXGBE_VMOLR_MPE; |
0c5a6166 | 4787 | features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; |
9a799d71 | 4788 | } else { |
746b9f02 PM |
4789 | if (netdev->flags & IFF_ALLMULTI) { |
4790 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a | 4791 | vmolr |= IXGBE_VMOLR_MPE; |
746b9f02 | 4792 | } |
e433ea1f | 4793 | hw->addr_ctrl.user_set_promisc = false; |
9dcb373c JF |
4794 | } |
4795 | ||
4796 | /* | |
4797 | * Write addresses to available RAR registers, if there is not | |
4798 | * sufficient space to store all the addresses then enable | |
4799 | * unicast promiscuous mode | |
4800 | */ | |
0f079d22 | 4801 | if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { |
9dcb373c JF |
4802 | fctrl |= IXGBE_FCTRL_UPE; |
4803 | vmolr |= IXGBE_VMOLR_ROPE; | |
9a799d71 AK |
4804 | } |
4805 | ||
cf78959c ET |
4806 | /* Write addresses to the MTA, if the attempt fails |
4807 | * then we should just turn on promiscuous mode so | |
4808 | * that we can at least receive multicast traffic | |
4809 | */ | |
b335e75b JK |
4810 | count = ixgbe_write_mc_addr_list(netdev); |
4811 | if (count < 0) { | |
4812 | fctrl |= IXGBE_FCTRL_MPE; | |
4813 | vmolr |= IXGBE_VMOLR_MPE; | |
4814 | } else if (count) { | |
4815 | vmolr |= IXGBE_VMOLR_ROMPE; | |
4816 | } | |
1d9c0bfd AD |
4817 | |
4818 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
4819 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & | |
2850062a AD |
4820 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | |
4821 | IXGBE_VMOLR_ROPE); | |
1d9c0bfd | 4822 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); |
2850062a AD |
4823 | } |
4824 | ||
3f2d1c0f | 4825 | /* This is useful for sniffing bad packets. */ |
0c5a6166 | 4826 | if (features & NETIF_F_RXALL) { |
3f2d1c0f BG |
4827 | /* UPE and MPE will be handled by normal PROMISC logic |
4828 | * in e1000e_set_rx_mode */ | |
4829 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
4830 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
4831 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
4832 | ||
4833 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
4834 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
4835 | } | |
4836 | ||
2850062a | 4837 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e | 4838 | |
0c5a6166 | 4839 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
f62bbb5e JG |
4840 | ixgbe_vlan_strip_enable(adapter); |
4841 | else | |
4842 | ixgbe_vlan_strip_disable(adapter); | |
0c5a6166 AD |
4843 | |
4844 | if (features & NETIF_F_HW_VLAN_CTAG_FILTER) | |
4845 | ixgbe_vlan_promisc_disable(adapter); | |
4846 | else | |
4847 | ixgbe_vlan_promisc_enable(adapter); | |
9a799d71 AK |
4848 | } |
4849 | ||
021230d4 AV |
4850 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
4851 | { | |
4852 | int q_idx; | |
021230d4 | 4853 | |
3ffc1af5 | 4854 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) |
49c7ffbe | 4855 | napi_enable(&adapter->q_vector[q_idx]->napi); |
021230d4 AV |
4856 | } |
4857 | ||
4858 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
4859 | { | |
4860 | int q_idx; | |
021230d4 | 4861 | |
3ffc1af5 | 4862 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) |
49c7ffbe | 4863 | napi_disable(&adapter->q_vector[q_idx]->napi); |
021230d4 AV |
4864 | } |
4865 | ||
a21d0822 | 4866 | static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) |
67359c3c | 4867 | { |
a21d0822 ET |
4868 | struct ixgbe_hw *hw = &adapter->hw; |
4869 | u32 vxlanctrl; | |
4870 | ||
4871 | if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | | |
4872 | IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) | |
4873 | return; | |
4874 | ||
4875 | vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) && ~mask; | |
4876 | IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); | |
4877 | ||
4878 | if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) | |
67359c3c | 4879 | adapter->vxlan_port = 0; |
a21d0822 ET |
4880 | |
4881 | if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) | |
4882 | adapter->geneve_port = 0; | |
67359c3c MR |
4883 | } |
4884 | ||
7a6b6f51 | 4885 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c | 4886 | /** |
2f90b865 AD |
4887 | * ixgbe_configure_dcb - Configure DCB hardware |
4888 | * @adapter: ixgbe adapter struct | |
4889 | * | |
4890 | * This is called by the driver on open to configure the DCB hardware. | |
4891 | * This is also called by the gennetlink interface when reconfiguring | |
4892 | * the DCB state. | |
4893 | */ | |
4894 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
4895 | { | |
4896 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 4897 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 4898 | |
67ebd791 AD |
4899 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
4900 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4901 | netif_set_gso_max_size(adapter->netdev, 65536); | |
4902 | return; | |
4903 | } | |
4904 | ||
4905 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4906 | netif_set_gso_max_size(adapter->netdev, 32768); | |
4907 | ||
971060b1 | 4908 | #ifdef IXGBE_FCOE |
b120818e JF |
4909 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
4910 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 4911 | #endif |
b120818e JF |
4912 | |
4913 | /* reconfigure the hardware */ | |
4914 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
4915 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
4916 | DCB_TX_CONFIG); | |
4917 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
4918 | DCB_RX_CONFIG); | |
4919 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
4920 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
4921 | ixgbe_dcb_hw_ets(&adapter->hw, | |
4922 | adapter->ixgbe_ieee_ets, | |
4923 | max_frame); | |
4924 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
4925 | adapter->ixgbe_ieee_pfc->pfc_en, | |
4926 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 4927 | } |
8187cd48 JF |
4928 | |
4929 | /* Enable RSS Hash per TC */ | |
4930 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
4ae63730 AD |
4931 | u32 msb = 0; |
4932 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; | |
8187cd48 | 4933 | |
d411a936 AD |
4934 | while (rss_i) { |
4935 | msb++; | |
4936 | rss_i >>= 1; | |
4937 | } | |
8187cd48 | 4938 | |
4ae63730 AD |
4939 | /* write msb to all 8 TCs in one write */ |
4940 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); | |
8187cd48 | 4941 | } |
2f90b865 | 4942 | } |
9da712d2 JF |
4943 | #endif |
4944 | ||
4945 | /* Additional bittime to account for IXGBE framing */ | |
4946 | #define IXGBE_ETH_FRAMING 20 | |
4947 | ||
49ce9c2c | 4948 | /** |
9da712d2 JF |
4949 | * ixgbe_hpbthresh - calculate high water mark for flow control |
4950 | * | |
4951 | * @adapter: board private structure to calculate for | |
49ce9c2c | 4952 | * @pb: packet buffer to calculate |
9da712d2 JF |
4953 | */ |
4954 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
4955 | { | |
4956 | struct ixgbe_hw *hw = &adapter->hw; | |
4957 | struct net_device *dev = adapter->netdev; | |
4958 | int link, tc, kb, marker; | |
4959 | u32 dv_id, rx_pba; | |
4960 | ||
4961 | /* Calculate max LAN frame size */ | |
4962 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
4963 | ||
4964 | #ifdef IXGBE_FCOE | |
4965 | /* FCoE traffic class uses FCOE jumbo frames */ | |
800bd607 AD |
4966 | if ((dev->features & NETIF_F_FCOE_MTU) && |
4967 | (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
4968 | (pb == ixgbe_fcoe_get_tc(adapter))) | |
4969 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9da712d2 | 4970 | #endif |
e5776620 | 4971 | |
9da712d2 JF |
4972 | /* Calculate delay value for device */ |
4973 | switch (hw->mac.type) { | |
4974 | case ixgbe_mac_X540: | |
9a75a1ac DS |
4975 | case ixgbe_mac_X550: |
4976 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4977 | case ixgbe_mac_x550em_a: |
9da712d2 JF |
4978 | dv_id = IXGBE_DV_X540(link, tc); |
4979 | break; | |
4980 | default: | |
4981 | dv_id = IXGBE_DV(link, tc); | |
4982 | break; | |
4983 | } | |
4984 | ||
4985 | /* Loopback switch introduces additional latency */ | |
4986 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4987 | dv_id += IXGBE_B2BT(tc); | |
4988 | ||
4989 | /* Delay value is calculated in bit times convert to KB */ | |
4990 | kb = IXGBE_BT2KB(dv_id); | |
4991 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
4992 | ||
4993 | marker = rx_pba - kb; | |
4994 | ||
4995 | /* It is possible that the packet buffer is not large enough | |
4996 | * to provide required headroom. In this case throw an error | |
4997 | * to user and a do the best we can. | |
4998 | */ | |
4999 | if (marker < 0) { | |
5000 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
5001 | "headroom to support flow control." | |
5002 | "Decrease MTU or number of traffic classes\n", pb); | |
5003 | marker = tc + 1; | |
5004 | } | |
5005 | ||
5006 | return marker; | |
5007 | } | |
5008 | ||
49ce9c2c | 5009 | /** |
9da712d2 JF |
5010 | * ixgbe_lpbthresh - calculate low water mark for for flow control |
5011 | * | |
5012 | * @adapter: board private structure to calculate for | |
49ce9c2c | 5013 | * @pb: packet buffer to calculate |
9da712d2 | 5014 | */ |
e5776620 | 5015 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) |
9da712d2 JF |
5016 | { |
5017 | struct ixgbe_hw *hw = &adapter->hw; | |
5018 | struct net_device *dev = adapter->netdev; | |
5019 | int tc; | |
5020 | u32 dv_id; | |
5021 | ||
5022 | /* Calculate max LAN frame size */ | |
5023 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
5024 | ||
e5776620 JK |
5025 | #ifdef IXGBE_FCOE |
5026 | /* FCoE traffic class uses FCOE jumbo frames */ | |
5027 | if ((dev->features & NETIF_F_FCOE_MTU) && | |
5028 | (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
5029 | (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) | |
5030 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
5031 | #endif | |
5032 | ||
9da712d2 JF |
5033 | /* Calculate delay value for device */ |
5034 | switch (hw->mac.type) { | |
5035 | case ixgbe_mac_X540: | |
9a75a1ac DS |
5036 | case ixgbe_mac_X550: |
5037 | case ixgbe_mac_X550EM_x: | |
49425dfc | 5038 | case ixgbe_mac_x550em_a: |
9da712d2 JF |
5039 | dv_id = IXGBE_LOW_DV_X540(tc); |
5040 | break; | |
5041 | default: | |
5042 | dv_id = IXGBE_LOW_DV(tc); | |
5043 | break; | |
5044 | } | |
5045 | ||
5046 | /* Delay value is calculated in bit times convert to KB */ | |
5047 | return IXGBE_BT2KB(dv_id); | |
5048 | } | |
5049 | ||
5050 | /* | |
5051 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
5052 | */ | |
5053 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
5054 | { | |
5055 | struct ixgbe_hw *hw = &adapter->hw; | |
5056 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
5057 | int i; | |
5058 | ||
5059 | if (!num_tc) | |
5060 | num_tc = 1; | |
5061 | ||
9da712d2 JF |
5062 | for (i = 0; i < num_tc; i++) { |
5063 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
e5776620 | 5064 | hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); |
9da712d2 JF |
5065 | |
5066 | /* Low water marks must not be larger than high water marks */ | |
e5776620 JK |
5067 | if (hw->fc.low_water[i] > hw->fc.high_water[i]) |
5068 | hw->fc.low_water[i] = 0; | |
9da712d2 | 5069 | } |
e5776620 JK |
5070 | |
5071 | for (; i < MAX_TRAFFIC_CLASS; i++) | |
5072 | hw->fc.high_water[i] = 0; | |
9da712d2 JF |
5073 | } |
5074 | ||
80605c65 JF |
5075 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
5076 | { | |
80605c65 | 5077 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
5078 | int hdrm; |
5079 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
5080 | |
5081 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
5082 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
5083 | hdrm = 32 << adapter->fdir_pballoc; |
5084 | else | |
5085 | hdrm = 0; | |
80605c65 | 5086 | |
f7e1027f | 5087 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 5088 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
5089 | } |
5090 | ||
e4911d57 AD |
5091 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
5092 | { | |
5093 | struct ixgbe_hw *hw = &adapter->hw; | |
b67bfe0d | 5094 | struct hlist_node *node2; |
e4911d57 AD |
5095 | struct ixgbe_fdir_filter *filter; |
5096 | ||
5097 | spin_lock(&adapter->fdir_perfect_lock); | |
5098 | ||
5099 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
5100 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
5101 | ||
b67bfe0d | 5102 | hlist_for_each_entry_safe(filter, node2, |
e4911d57 AD |
5103 | &adapter->fdir_filter_list, fdir_node) { |
5104 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
5105 | &filter->filter, |
5106 | filter->sw_idx, | |
5107 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
5108 | IXGBE_FDIR_DROP_QUEUE : | |
5109 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
5110 | } |
5111 | ||
5112 | spin_unlock(&adapter->fdir_perfect_lock); | |
5113 | } | |
5114 | ||
2a47fa45 JF |
5115 | static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, |
5116 | struct ixgbe_adapter *adapter) | |
5117 | { | |
5118 | struct ixgbe_hw *hw = &adapter->hw; | |
5119 | u32 vmolr; | |
5120 | ||
5121 | /* No unicast promiscuous support for VMDQ devices. */ | |
5122 | vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); | |
5123 | vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); | |
5124 | ||
5125 | /* clear the affected bit */ | |
5126 | vmolr &= ~IXGBE_VMOLR_MPE; | |
5127 | ||
5128 | if (dev->flags & IFF_ALLMULTI) { | |
5129 | vmolr |= IXGBE_VMOLR_MPE; | |
5130 | } else { | |
5131 | vmolr |= IXGBE_VMOLR_ROMPE; | |
5132 | hw->mac.ops.update_mc_addr_list(hw, dev); | |
5133 | } | |
5d7daa35 | 5134 | ixgbe_write_uc_addr_list(adapter->netdev, pool); |
2a47fa45 JF |
5135 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); |
5136 | } | |
5137 | ||
2a47fa45 JF |
5138 | static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) |
5139 | { | |
5140 | struct ixgbe_adapter *adapter = vadapter->real_adapter; | |
219354d4 | 5141 | int rss_i = adapter->num_rx_queues_per_pool; |
2a47fa45 JF |
5142 | struct ixgbe_hw *hw = &adapter->hw; |
5143 | u16 pool = vadapter->pool; | |
5144 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
5145 | IXGBE_PSRTYPE_UDPHDR | | |
5146 | IXGBE_PSRTYPE_IPV4HDR | | |
5147 | IXGBE_PSRTYPE_L2HDR | | |
5148 | IXGBE_PSRTYPE_IPV6HDR; | |
5149 | ||
5150 | if (hw->mac.type == ixgbe_mac_82598EB) | |
5151 | return; | |
5152 | ||
5153 | if (rss_i > 3) | |
b4f47a48 | 5154 | psrtype |= 2u << 29; |
2a47fa45 | 5155 | else if (rss_i > 1) |
b4f47a48 | 5156 | psrtype |= 1u << 29; |
2a47fa45 JF |
5157 | |
5158 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); | |
5159 | } | |
5160 | ||
5161 | /** | |
5162 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
5163 | * @rx_ring: ring to free buffers from | |
5164 | **/ | |
5165 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) | |
5166 | { | |
ffed21bc AD |
5167 | u16 i = rx_ring->next_to_clean; |
5168 | struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; | |
2a47fa45 JF |
5169 | |
5170 | /* Free all the Rx ring sk_buffs */ | |
ffed21bc | 5171 | while (i != rx_ring->next_to_alloc) { |
2a47fa45 JF |
5172 | if (rx_buffer->skb) { |
5173 | struct sk_buff *skb = rx_buffer->skb; | |
18cb652a | 5174 | if (IXGBE_CB(skb)->page_released) |
ffed21bc | 5175 | dma_unmap_page_attrs(rx_ring->dev, |
f3213d93 AD |
5176 | IXGBE_CB(skb)->dma, |
5177 | ixgbe_rx_pg_size(rx_ring), | |
5178 | DMA_FROM_DEVICE, | |
5179 | IXGBE_RX_DMA_ATTR); | |
2a47fa45 JF |
5180 | dev_kfree_skb(skb); |
5181 | } | |
18cb652a | 5182 | |
f3213d93 AD |
5183 | /* Invalidate cache lines that may have been written to by |
5184 | * device so that we avoid corrupting memory. | |
5185 | */ | |
5186 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
5187 | rx_buffer->dma, | |
5188 | rx_buffer->page_offset, | |
5189 | ixgbe_rx_bufsz(rx_ring), | |
5190 | DMA_FROM_DEVICE); | |
5191 | ||
5192 | /* free resources associated with mapping */ | |
ffed21bc | 5193 | dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, |
f3213d93 AD |
5194 | ixgbe_rx_pg_size(rx_ring), |
5195 | DMA_FROM_DEVICE, | |
5196 | IXGBE_RX_DMA_ATTR); | |
1b56cf49 AD |
5197 | __page_frag_cache_drain(rx_buffer->page, |
5198 | rx_buffer->pagecnt_bias); | |
18cb652a | 5199 | |
ffed21bc AD |
5200 | i++; |
5201 | rx_buffer++; | |
5202 | if (i == rx_ring->count) { | |
5203 | i = 0; | |
5204 | rx_buffer = rx_ring->rx_buffer_info; | |
5205 | } | |
2a47fa45 JF |
5206 | } |
5207 | ||
2a47fa45 JF |
5208 | rx_ring->next_to_alloc = 0; |
5209 | rx_ring->next_to_clean = 0; | |
5210 | rx_ring->next_to_use = 0; | |
5211 | } | |
5212 | ||
5213 | static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, | |
5214 | struct ixgbe_ring *rx_ring) | |
5215 | { | |
5216 | struct ixgbe_adapter *adapter = vadapter->real_adapter; | |
5217 | int index = rx_ring->queue_index + vadapter->rx_base_queue; | |
5218 | ||
5219 | /* shutdown specific queue receive and wait for dma to settle */ | |
5220 | ixgbe_disable_rx_queue(adapter, rx_ring); | |
5221 | usleep_range(10000, 20000); | |
b4f47a48 | 5222 | ixgbe_irq_disable_queues(adapter, BIT_ULL(index)); |
2a47fa45 JF |
5223 | ixgbe_clean_rx_ring(rx_ring); |
5224 | rx_ring->l2_accel_priv = NULL; | |
5225 | } | |
5226 | ||
ae72c8d0 JF |
5227 | static int ixgbe_fwd_ring_down(struct net_device *vdev, |
5228 | struct ixgbe_fwd_adapter *accel) | |
2a47fa45 JF |
5229 | { |
5230 | struct ixgbe_adapter *adapter = accel->real_adapter; | |
5231 | unsigned int rxbase = accel->rx_base_queue; | |
5232 | unsigned int txbase = accel->tx_base_queue; | |
5233 | int i; | |
5234 | ||
5235 | netif_tx_stop_all_queues(vdev); | |
5236 | ||
5237 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
5238 | ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); | |
5239 | adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; | |
5240 | } | |
5241 | ||
5242 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
5243 | adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; | |
5244 | adapter->tx_ring[txbase + i]->netdev = adapter->netdev; | |
5245 | } | |
5246 | ||
5247 | ||
5248 | return 0; | |
5249 | } | |
5250 | ||
5251 | static int ixgbe_fwd_ring_up(struct net_device *vdev, | |
5252 | struct ixgbe_fwd_adapter *accel) | |
5253 | { | |
5254 | struct ixgbe_adapter *adapter = accel->real_adapter; | |
5255 | unsigned int rxbase, txbase, queues; | |
5256 | int i, baseq, err = 0; | |
5257 | ||
5258 | if (!test_bit(accel->pool, &adapter->fwd_bitmask)) | |
5259 | return 0; | |
5260 | ||
5261 | baseq = accel->pool * adapter->num_rx_queues_per_pool; | |
5262 | netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", | |
5263 | accel->pool, adapter->num_rx_pools, | |
5264 | baseq, baseq + adapter->num_rx_queues_per_pool, | |
5265 | adapter->fwd_bitmask); | |
5266 | ||
5267 | accel->netdev = vdev; | |
5268 | accel->rx_base_queue = rxbase = baseq; | |
5269 | accel->tx_base_queue = txbase = baseq; | |
5270 | ||
5271 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) | |
5272 | ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); | |
5273 | ||
5274 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
5275 | adapter->rx_ring[rxbase + i]->netdev = vdev; | |
5276 | adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; | |
5277 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); | |
5278 | } | |
5279 | ||
5280 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
5281 | adapter->tx_ring[txbase + i]->netdev = vdev; | |
5282 | adapter->tx_ring[txbase + i]->l2_accel_priv = accel; | |
5283 | } | |
5284 | ||
5285 | queues = min_t(unsigned int, | |
5286 | adapter->num_rx_queues_per_pool, vdev->num_tx_queues); | |
5287 | err = netif_set_real_num_tx_queues(vdev, queues); | |
5288 | if (err) | |
5289 | goto fwd_queue_err; | |
5290 | ||
2a47fa45 JF |
5291 | err = netif_set_real_num_rx_queues(vdev, queues); |
5292 | if (err) | |
5293 | goto fwd_queue_err; | |
5294 | ||
5295 | if (is_valid_ether_addr(vdev->dev_addr)) | |
5296 | ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); | |
5297 | ||
5298 | ixgbe_fwd_psrtype(accel); | |
5299 | ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); | |
5300 | return err; | |
5301 | fwd_queue_err: | |
5302 | ixgbe_fwd_ring_down(vdev, accel); | |
5303 | return err; | |
5304 | } | |
5305 | ||
1cd127fc | 5306 | static int ixgbe_upper_dev_walk(struct net_device *upper, void *data) |
2a47fa45 | 5307 | { |
1cd127fc DA |
5308 | if (netif_is_macvlan(upper)) { |
5309 | struct macvlan_dev *dfwd = netdev_priv(upper); | |
5310 | struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; | |
2a47fa45 | 5311 | |
1cd127fc DA |
5312 | if (dfwd->fwd_priv) |
5313 | ixgbe_fwd_ring_up(upper, vadapter); | |
2a47fa45 | 5314 | } |
1cd127fc DA |
5315 | |
5316 | return 0; | |
5317 | } | |
5318 | ||
5319 | static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) | |
5320 | { | |
5321 | netdev_walk_all_upper_dev_rcu(adapter->netdev, | |
5322 | ixgbe_upper_dev_walk, NULL); | |
2a47fa45 JF |
5323 | } |
5324 | ||
9a799d71 AK |
5325 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
5326 | { | |
d2f5e7f3 AS |
5327 | struct ixgbe_hw *hw = &adapter->hw; |
5328 | ||
80605c65 | 5329 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 5330 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 5331 | ixgbe_configure_dcb(adapter); |
2f90b865 | 5332 | #endif |
b35d4d42 AD |
5333 | /* |
5334 | * We must restore virtualization before VLANs or else | |
5335 | * the VLVF registers will not be populated | |
5336 | */ | |
5337 | ixgbe_configure_virtualization(adapter); | |
9a799d71 | 5338 | |
4c1d7b4b | 5339 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
5340 | ixgbe_restore_vlan(adapter); |
5341 | ||
d2f5e7f3 AS |
5342 | switch (hw->mac.type) { |
5343 | case ixgbe_mac_82599EB: | |
5344 | case ixgbe_mac_X540: | |
5345 | hw->mac.ops.disable_rx_buff(hw); | |
5346 | break; | |
5347 | default: | |
5348 | break; | |
5349 | } | |
5350 | ||
c4cf55e5 | 5351 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
5352 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
5353 | adapter->fdir_pballoc); | |
e4911d57 AD |
5354 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
5355 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
5356 | adapter->fdir_pballoc); | |
5357 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 5358 | } |
4c1d7b4b | 5359 | |
d2f5e7f3 AS |
5360 | switch (hw->mac.type) { |
5361 | case ixgbe_mac_82599EB: | |
5362 | case ixgbe_mac_X540: | |
5363 | hw->mac.ops.enable_rx_buff(hw); | |
5364 | break; | |
5365 | default: | |
5366 | break; | |
5367 | } | |
5368 | ||
9de7605e MR |
5369 | #ifdef CONFIG_IXGBE_DCA |
5370 | /* configure DCA */ | |
5371 | if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) | |
5372 | ixgbe_setup_dca(adapter); | |
5373 | #endif /* CONFIG_IXGBE_DCA */ | |
5374 | ||
7c8ae65a AD |
5375 | #ifdef IXGBE_FCOE |
5376 | /* configure FCoE L2 filters, redirection table, and Rx control */ | |
5377 | ixgbe_configure_fcoe(adapter); | |
5378 | ||
5379 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
5380 | ixgbe_configure_tx(adapter); |
5381 | ixgbe_configure_rx(adapter); | |
2a47fa45 | 5382 | ixgbe_configure_dfwd(adapter); |
9a799d71 AK |
5383 | } |
5384 | ||
0ecc061d | 5385 | /** |
e8e26350 PW |
5386 | * ixgbe_sfp_link_config - set up SFP+ link |
5387 | * @adapter: pointer to private adapter struct | |
5388 | **/ | |
5389 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
5390 | { | |
7086400d | 5391 | /* |
52f33af8 | 5392 | * We are assuming the worst case scenario here, and that |
7086400d AD |
5393 | * is that an SFP was inserted/removed after the reset |
5394 | * but before SFP detection was enabled. As such the best | |
5395 | * solution is to just start searching as soon as we start | |
5396 | */ | |
5397 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
5398 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 5399 | |
7086400d | 5400 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
58e7cd24 | 5401 | adapter->sfp_poll_time = 0; |
e8e26350 PW |
5402 | } |
5403 | ||
5404 | /** | |
5405 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
5406 | * @hw: pointer to private hardware struct |
5407 | * | |
5408 | * Returns 0 on success, negative on failure | |
5409 | **/ | |
e8e26350 | 5410 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d | 5411 | { |
3d292265 JH |
5412 | u32 speed; |
5413 | bool autoneg, link_up = false; | |
a1e869de | 5414 | int ret = IXGBE_ERR_LINK_SETUP; |
0ecc061d PWJ |
5415 | |
5416 | if (hw->mac.ops.check_link) | |
3d292265 | 5417 | ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); |
0ecc061d PWJ |
5418 | |
5419 | if (ret) | |
e90dd264 | 5420 | return ret; |
0ecc061d | 5421 | |
3d292265 JH |
5422 | speed = hw->phy.autoneg_advertised; |
5423 | if ((!speed) && (hw->mac.ops.get_link_capabilities)) | |
5424 | ret = hw->mac.ops.get_link_capabilities(hw, &speed, | |
5425 | &autoneg); | |
0ecc061d | 5426 | if (ret) |
e90dd264 | 5427 | return ret; |
0ecc061d | 5428 | |
8620a103 | 5429 | if (hw->mac.ops.setup_link) |
fd0326f2 | 5430 | ret = hw->mac.ops.setup_link(hw, speed, link_up); |
e90dd264 | 5431 | |
0ecc061d PWJ |
5432 | return ret; |
5433 | } | |
5434 | ||
a34bcfff | 5435 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 5436 | { |
9a799d71 | 5437 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 5438 | u32 gpie = 0; |
9a799d71 | 5439 | |
9b471446 | 5440 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
5441 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
5442 | IXGBE_GPIE_OCD; | |
5443 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
5444 | /* |
5445 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
5446 | * this saves a register write for every interrupt | |
5447 | */ | |
5448 | switch (hw->mac.type) { | |
5449 | case ixgbe_mac_82598EB: | |
5450 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
5451 | break; | |
9b471446 | 5452 | case ixgbe_mac_82599EB: |
b93a2226 | 5453 | case ixgbe_mac_X540: |
9a75a1ac DS |
5454 | case ixgbe_mac_X550: |
5455 | case ixgbe_mac_X550EM_x: | |
49425dfc | 5456 | case ixgbe_mac_x550em_a: |
b93a2226 | 5457 | default: |
9b471446 JB |
5458 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
5459 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
5460 | break; | |
5461 | } | |
5462 | } else { | |
021230d4 AV |
5463 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
5464 | * specifically only auto mask tx and rx interrupts */ | |
5465 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
5466 | } | |
9a799d71 | 5467 | |
a34bcfff AD |
5468 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
5469 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
5470 | ||
5471 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
5472 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
73079ea0 AD |
5473 | |
5474 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { | |
5475 | case IXGBE_82599_VMDQ_8Q_MASK: | |
5476 | gpie |= IXGBE_GPIE_VTMODE_16; | |
5477 | break; | |
5478 | case IXGBE_82599_VMDQ_4Q_MASK: | |
5479 | gpie |= IXGBE_GPIE_VTMODE_32; | |
5480 | break; | |
5481 | default: | |
5482 | gpie |= IXGBE_GPIE_VTMODE_64; | |
5483 | break; | |
5484 | } | |
119fc60a MC |
5485 | } |
5486 | ||
5fdd31f9 | 5487 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
5488 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
5489 | switch (adapter->hw.mac.type) { | |
5490 | case ixgbe_mac_82599EB: | |
9a900eca | 5491 | gpie |= IXGBE_SDP0_GPIEN_8259X; |
f3df98ec | 5492 | break; |
f3df98ec DS |
5493 | default: |
5494 | break; | |
5495 | } | |
5496 | } | |
5fdd31f9 | 5497 | |
a34bcfff AD |
5498 | /* Enable fan failure interrupt */ |
5499 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
9a900eca | 5500 | gpie |= IXGBE_SDP1_GPIEN(hw); |
0befdb3e | 5501 | |
a023bbd0 DS |
5502 | switch (hw->mac.type) { |
5503 | case ixgbe_mac_82599EB: | |
5504 | gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; | |
5505 | break; | |
5506 | case ixgbe_mac_X550EM_x: | |
49425dfc | 5507 | case ixgbe_mac_x550em_a: |
a023bbd0 DS |
5508 | gpie |= IXGBE_SDP0_GPIEN_X540; |
5509 | break; | |
5510 | default: | |
5511 | break; | |
2698b208 | 5512 | } |
a34bcfff AD |
5513 | |
5514 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
5515 | } | |
5516 | ||
c7ccde0f | 5517 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
5518 | { |
5519 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 5520 | int err; |
a34bcfff AD |
5521 | u32 ctrl_ext; |
5522 | ||
5523 | ixgbe_get_hw_control(adapter); | |
5524 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 5525 | |
9a799d71 AK |
5526 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
5527 | ixgbe_configure_msix(adapter); | |
5528 | else | |
5529 | ixgbe_configure_msi_and_legacy(adapter); | |
5530 | ||
ec74a471 ET |
5531 | /* enable the optics for 82599 SFP+ fiber */ |
5532 | if (hw->mac.ops.enable_tx_laser) | |
61fac744 PW |
5533 | hw->mac.ops.enable_tx_laser(hw); |
5534 | ||
961fac88 DS |
5535 | if (hw->phy.ops.set_phy_power) |
5536 | hw->phy.ops.set_phy_power(hw, true); | |
5537 | ||
4e857c58 | 5538 | smp_mb__before_atomic(); |
9a799d71 | 5539 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
5540 | ixgbe_napi_enable_all(adapter); |
5541 | ||
73c4b7cd AD |
5542 | if (ixgbe_is_sfp(hw)) { |
5543 | ixgbe_sfp_link_config(adapter); | |
5544 | } else { | |
5545 | err = ixgbe_non_sfp_link_config(hw); | |
5546 | if (err) | |
5547 | e_err(probe, "link_config FAILED %d\n", err); | |
5548 | } | |
5549 | ||
021230d4 AV |
5550 | /* clear any pending interrupts, may auto mask */ |
5551 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 5552 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 5553 | |
bf069c97 DS |
5554 | /* |
5555 | * If this adapter has a fan, check to see if we had a failure | |
5556 | * before we enabled the interrupt. | |
5557 | */ | |
5558 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
5559 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
5560 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 5561 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
5562 | } |
5563 | ||
9a799d71 AK |
5564 | /* bring the link up in the watchdog, this could race with our first |
5565 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
5566 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
5567 | adapter->link_check_timeout = jiffies; | |
7086400d | 5568 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
5569 | |
5570 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
5571 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
5572 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
5573 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
5574 | } |
5575 | ||
d4f80882 AV |
5576 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
5577 | { | |
5578 | WARN_ON(in_interrupt()); | |
7086400d | 5579 | /* put off any impending NetWatchDogTimeout */ |
860e9538 | 5580 | netif_trans_update(adapter->netdev); |
7086400d | 5581 | |
d4f80882 | 5582 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 5583 | usleep_range(1000, 2000); |
b3eb4e18 MR |
5584 | if (adapter->hw.phy.type == ixgbe_phy_fw) |
5585 | ixgbe_watchdog_link_is_down(adapter); | |
d4f80882 | 5586 | ixgbe_down(adapter); |
5809a1ae GR |
5587 | /* |
5588 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
5589 | * back up to give the VFs time to respond to the reset. The | |
5590 | * two second wait is based upon the watchdog timer cycle in | |
5591 | * the VF driver. | |
5592 | */ | |
5593 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
5594 | msleep(2000); | |
d4f80882 AV |
5595 | ixgbe_up(adapter); |
5596 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
5597 | } | |
5598 | ||
c7ccde0f | 5599 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5600 | { |
5601 | /* hardware has been reset, we need to reload some things */ | |
5602 | ixgbe_configure(adapter); | |
5603 | ||
c7ccde0f | 5604 | ixgbe_up_complete(adapter); |
9a799d71 AK |
5605 | } |
5606 | ||
5607 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
5608 | { | |
c44ade9e | 5609 | struct ixgbe_hw *hw = &adapter->hw; |
5d7daa35 | 5610 | struct net_device *netdev = adapter->netdev; |
8ca783ab DS |
5611 | int err; |
5612 | ||
b0483c8f MR |
5613 | if (ixgbe_removed(hw->hw_addr)) |
5614 | return; | |
7086400d AD |
5615 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
5616 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5617 | usleep_range(1000, 2000); | |
5618 | ||
5619 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
5620 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
5621 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
5622 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
5623 | ||
8ca783ab | 5624 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
5625 | switch (err) { |
5626 | case 0: | |
5627 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 5628 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
5629 | break; |
5630 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 5631 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 5632 | break; |
794caeb2 PWJ |
5633 | case IXGBE_ERR_EEPROM_VERSION: |
5634 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 5635 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 5636 | "Please be aware there may be issues associated with " |
849c4542 ET |
5637 | "your hardware. If you are experiencing problems " |
5638 | "please contact your Intel or hardware " | |
5639 | "representative who provided you with this " | |
5640 | "hardware.\n"); | |
794caeb2 | 5641 | break; |
da4dd0f7 | 5642 | default: |
849c4542 | 5643 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 5644 | } |
9a799d71 | 5645 | |
7086400d | 5646 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
0f079d22 AD |
5647 | |
5648 | /* flush entries out of MAC table */ | |
5d7daa35 | 5649 | ixgbe_flush_sw_mac_table(adapter); |
0f079d22 AD |
5650 | __dev_uc_unsync(netdev, NULL); |
5651 | ||
5652 | /* do not flush user set addresses */ | |
c9f53e63 | 5653 | ixgbe_mac_set_default_filter(adapter); |
7fa7c9dc AD |
5654 | |
5655 | /* update SAN MAC vmdq pool selection */ | |
5656 | if (hw->mac.san_mac_rar_index) | |
5657 | hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); | |
1a71ab24 | 5658 | |
8fecf67c | 5659 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) |
1a71ab24 | 5660 | ixgbe_ptp_reset(adapter); |
961fac88 DS |
5661 | |
5662 | if (hw->phy.ops.set_phy_power) { | |
5663 | if (!netif_running(adapter->netdev) && !adapter->wol) | |
5664 | hw->phy.ops.set_phy_power(hw, false); | |
5665 | else | |
5666 | hw->phy.ops.set_phy_power(hw, true); | |
5667 | } | |
9a799d71 AK |
5668 | } |
5669 | ||
9a799d71 AK |
5670 | /** |
5671 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
5672 | * @tx_ring: ring to be cleaned |
5673 | **/ | |
b6ec895e | 5674 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 | 5675 | { |
ffed21bc AD |
5676 | u16 i = tx_ring->next_to_clean; |
5677 | struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; | |
9a799d71 | 5678 | |
ffed21bc AD |
5679 | while (i != tx_ring->next_to_use) { |
5680 | union ixgbe_adv_tx_desc *eop_desc, *tx_desc; | |
9a799d71 | 5681 | |
ffed21bc | 5682 | /* Free all the Tx ring sk_buffs */ |
33fdc82f JF |
5683 | if (ring_is_xdp(tx_ring)) |
5684 | page_frag_free(tx_buffer->data); | |
5685 | else | |
5686 | dev_kfree_skb_any(tx_buffer->skb); | |
9a799d71 | 5687 | |
ffed21bc AD |
5688 | /* unmap skb header data */ |
5689 | dma_unmap_single(tx_ring->dev, | |
5690 | dma_unmap_addr(tx_buffer, dma), | |
5691 | dma_unmap_len(tx_buffer, len), | |
5692 | DMA_TO_DEVICE); | |
dad8a3b3 | 5693 | |
ffed21bc AD |
5694 | /* check for eop_desc to determine the end of the packet */ |
5695 | eop_desc = tx_buffer->next_to_watch; | |
5696 | tx_desc = IXGBE_TX_DESC(tx_ring, i); | |
5697 | ||
5698 | /* unmap remaining buffers */ | |
5699 | while (tx_desc != eop_desc) { | |
5700 | tx_buffer++; | |
5701 | tx_desc++; | |
5702 | i++; | |
5703 | if (unlikely(i == tx_ring->count)) { | |
5704 | i = 0; | |
5705 | tx_buffer = tx_ring->tx_buffer_info; | |
5706 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
5707 | } | |
9a799d71 | 5708 | |
ffed21bc AD |
5709 | /* unmap any remaining paged data */ |
5710 | if (dma_unmap_len(tx_buffer, len)) | |
5711 | dma_unmap_page(tx_ring->dev, | |
5712 | dma_unmap_addr(tx_buffer, dma), | |
5713 | dma_unmap_len(tx_buffer, len), | |
5714 | DMA_TO_DEVICE); | |
5715 | } | |
9a799d71 | 5716 | |
ffed21bc AD |
5717 | /* move us one more past the eop_desc for start of next pkt */ |
5718 | tx_buffer++; | |
5719 | i++; | |
5720 | if (unlikely(i == tx_ring->count)) { | |
5721 | i = 0; | |
5722 | tx_buffer = tx_ring->tx_buffer_info; | |
5723 | } | |
5724 | } | |
5725 | ||
5726 | /* reset BQL for queue */ | |
33fdc82f JF |
5727 | if (!ring_is_xdp(tx_ring)) |
5728 | netdev_tx_reset_queue(txring_txq(tx_ring)); | |
ffed21bc AD |
5729 | |
5730 | /* reset next_to_use and next_to_clean */ | |
9a799d71 AK |
5731 | tx_ring->next_to_use = 0; |
5732 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
5733 | } |
5734 | ||
5735 | /** | |
021230d4 | 5736 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
5737 | * @adapter: board private structure |
5738 | **/ | |
021230d4 | 5739 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5740 | { |
5741 | int i; | |
5742 | ||
021230d4 | 5743 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 5744 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
5745 | } |
5746 | ||
5747 | /** | |
021230d4 | 5748 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
5749 | * @adapter: board private structure |
5750 | **/ | |
021230d4 | 5751 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5752 | { |
5753 | int i; | |
5754 | ||
021230d4 | 5755 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 5756 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
33fdc82f JF |
5757 | for (i = 0; i < adapter->num_xdp_queues; i++) |
5758 | ixgbe_clean_tx_ring(adapter->xdp_ring[i]); | |
9a799d71 AK |
5759 | } |
5760 | ||
e4911d57 AD |
5761 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
5762 | { | |
b67bfe0d | 5763 | struct hlist_node *node2; |
e4911d57 AD |
5764 | struct ixgbe_fdir_filter *filter; |
5765 | ||
5766 | spin_lock(&adapter->fdir_perfect_lock); | |
5767 | ||
b67bfe0d | 5768 | hlist_for_each_entry_safe(filter, node2, |
e4911d57 AD |
5769 | &adapter->fdir_filter_list, fdir_node) { |
5770 | hlist_del(&filter->fdir_node); | |
5771 | kfree(filter); | |
5772 | } | |
5773 | adapter->fdir_filter_count = 0; | |
5774 | ||
5775 | spin_unlock(&adapter->fdir_perfect_lock); | |
5776 | } | |
5777 | ||
1cd127fc DA |
5778 | static int ixgbe_disable_macvlan(struct net_device *upper, void *data) |
5779 | { | |
5780 | if (netif_is_macvlan(upper)) { | |
5781 | struct macvlan_dev *vlan = netdev_priv(upper); | |
5782 | ||
5783 | if (vlan->fwd_priv) { | |
5784 | netif_tx_stop_all_queues(upper); | |
5785 | netif_carrier_off(upper); | |
5786 | netif_tx_disable(upper); | |
5787 | } | |
5788 | } | |
5789 | ||
5790 | return 0; | |
5791 | } | |
5792 | ||
9a799d71 AK |
5793 | void ixgbe_down(struct ixgbe_adapter *adapter) |
5794 | { | |
5795 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 5796 | struct ixgbe_hw *hw = &adapter->hw; |
bf29ee6c | 5797 | int i; |
9a799d71 AK |
5798 | |
5799 | /* signal that we are down to the interrupt handler */ | |
c3049c8f MR |
5800 | if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) |
5801 | return; /* do nothing if already down */ | |
9a799d71 AK |
5802 | |
5803 | /* disable receives */ | |
1f9ac57c | 5804 | hw->mac.ops.disable_rx(hw); |
9a799d71 | 5805 | |
2d39d576 YZ |
5806 | /* disable all enabled rx queues */ |
5807 | for (i = 0; i < adapter->num_rx_queues; i++) | |
5808 | /* this call also flushes the previous write */ | |
5809 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
5810 | ||
032b4325 | 5811 | usleep_range(10000, 20000); |
9a799d71 | 5812 | |
7f821875 JB |
5813 | netif_tx_stop_all_queues(netdev); |
5814 | ||
7086400d | 5815 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
5816 | netif_carrier_off(netdev); |
5817 | netif_tx_disable(netdev); | |
5818 | ||
2a47fa45 | 5819 | /* disable any upper devices */ |
1cd127fc DA |
5820 | netdev_walk_all_upper_dev_rcu(adapter->netdev, |
5821 | ixgbe_disable_macvlan, NULL); | |
2a47fa45 | 5822 | |
c0dfb90e JF |
5823 | ixgbe_irq_disable(adapter); |
5824 | ||
5825 | ixgbe_napi_disable_all(adapter); | |
5826 | ||
57ca2a4f ET |
5827 | clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); |
5828 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
7086400d AD |
5829 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
5830 | ||
5831 | del_timer_sync(&adapter->service_timer); | |
5832 | ||
34cecbbf | 5833 | if (adapter->num_vfs) { |
8e34d1aa AD |
5834 | /* Clear EITR Select mapping */ |
5835 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
5836 | |
5837 | /* Mark all the VFs as inactive */ | |
5838 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 5839 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 5840 | |
34cecbbf AD |
5841 | /* ping all the active vfs to let them know we are going down */ |
5842 | ixgbe_ping_all_vfs(adapter); | |
5843 | ||
5844 | /* Disable all VFTE/VFRE TX/RX */ | |
5845 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
5846 | } |
5847 | ||
7f821875 JB |
5848 | /* disable transmits in the hardware now that interrupts are off */ |
5849 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 5850 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 5851 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 5852 | } |
33fdc82f JF |
5853 | for (i = 0; i < adapter->num_xdp_queues; i++) { |
5854 | u8 reg_idx = adapter->xdp_ring[i]->reg_idx; | |
5855 | ||
5856 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); | |
5857 | } | |
34cecbbf | 5858 | |
9a75a1ac | 5859 | /* Disable the Tx DMA engine on 82599 and later MAC */ |
bd508178 AD |
5860 | switch (hw->mac.type) { |
5861 | case ixgbe_mac_82599EB: | |
b93a2226 | 5862 | case ixgbe_mac_X540: |
9a75a1ac DS |
5863 | case ixgbe_mac_X550: |
5864 | case ixgbe_mac_X550EM_x: | |
49425dfc | 5865 | case ixgbe_mac_x550em_a: |
88512539 | 5866 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
5867 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
5868 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
5869 | break; |
5870 | default: | |
5871 | break; | |
5872 | } | |
7f821875 | 5873 | |
6f4a0e45 PL |
5874 | if (!pci_channel_offline(adapter->pdev)) |
5875 | ixgbe_reset(adapter); | |
c6ecf39a | 5876 | |
ec74a471 ET |
5877 | /* power down the optics for 82599 SFP+ fiber */ |
5878 | if (hw->mac.ops.disable_tx_laser) | |
c6ecf39a DS |
5879 | hw->mac.ops.disable_tx_laser(hw); |
5880 | ||
9a799d71 AK |
5881 | ixgbe_clean_all_tx_rings(adapter); |
5882 | ixgbe_clean_all_rx_rings(adapter); | |
9a799d71 AK |
5883 | } |
5884 | ||
b3eb4e18 MR |
5885 | /** |
5886 | * ixgbe_eee_capable - helper function to determine EEE support on X550 | |
5887 | * @adapter: board private structure | |
5888 | */ | |
5889 | static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) | |
5890 | { | |
5891 | struct ixgbe_hw *hw = &adapter->hw; | |
5892 | ||
5893 | switch (hw->device_id) { | |
5894 | case IXGBE_DEV_ID_X550EM_A_1G_T: | |
5895 | case IXGBE_DEV_ID_X550EM_A_1G_T_L: | |
5896 | if (!hw->phy.eee_speeds_supported) | |
5897 | break; | |
5898 | adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; | |
5899 | if (!hw->phy.eee_speeds_advertised) | |
5900 | break; | |
5901 | adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; | |
5902 | break; | |
5903 | default: | |
5904 | adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; | |
5905 | adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; | |
5906 | break; | |
5907 | } | |
5908 | } | |
5909 | ||
9a799d71 AK |
5910 | /** |
5911 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
5912 | * @netdev: network interface device structure | |
5913 | **/ | |
5914 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
5915 | { | |
5916 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5917 | ||
5918 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 5919 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
5920 | } |
5921 | ||
8829009d UK |
5922 | #ifdef CONFIG_IXGBE_DCB |
5923 | static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) | |
5924 | { | |
5925 | struct ixgbe_hw *hw = &adapter->hw; | |
5926 | struct tc_configuration *tc; | |
5927 | int j; | |
5928 | ||
5929 | switch (hw->mac.type) { | |
5930 | case ixgbe_mac_82598EB: | |
5931 | case ixgbe_mac_82599EB: | |
5932 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
5933 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
5934 | break; | |
5935 | case ixgbe_mac_X540: | |
5936 | case ixgbe_mac_X550: | |
5937 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; | |
5938 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
5939 | break; | |
5940 | case ixgbe_mac_X550EM_x: | |
5941 | case ixgbe_mac_x550em_a: | |
5942 | default: | |
5943 | adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; | |
5944 | adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; | |
5945 | break; | |
5946 | } | |
5947 | ||
5948 | /* Configure DCB traffic classes */ | |
5949 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
5950 | tc = &adapter->dcb_cfg.tc_config[j]; | |
5951 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
5952 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
5953 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
5954 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
5955 | tc->dcb_pfc = pfc_disabled; | |
5956 | } | |
5957 | ||
5958 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
5959 | tc = &adapter->dcb_cfg.tc_config[0]; | |
5960 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
5961 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
5962 | ||
5963 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
5964 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
5965 | adapter->dcb_cfg.pfc_mode_enable = false; | |
5966 | adapter->dcb_set_bitmap = 0x00; | |
5967 | if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) | |
5968 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; | |
5969 | memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, | |
5970 | sizeof(adapter->temp_dcb_cfg)); | |
5971 | } | |
5972 | #endif | |
5973 | ||
9a799d71 AK |
5974 | /** |
5975 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
5976 | * @adapter: board private structure to initialize | |
5977 | * | |
5978 | * ixgbe_sw_init initializes the Adapter private data structure. | |
5979 | * Fields are initialized based on PCI device information and | |
5980 | * OS network device settings (MTU size). | |
5981 | **/ | |
55570b6f ET |
5982 | static int ixgbe_sw_init(struct ixgbe_adapter *adapter, |
5983 | const struct ixgbe_info *ii) | |
9a799d71 AK |
5984 | { |
5985 | struct ixgbe_hw *hw = &adapter->hw; | |
5986 | struct pci_dev *pdev = adapter->pdev; | |
d3cb9869 | 5987 | unsigned int rss, fdir; |
cb6d0f5e | 5988 | u32 fwsm; |
1cdaaf54 | 5989 | int i; |
021230d4 | 5990 | |
c44ade9e JB |
5991 | /* PCI config space info */ |
5992 | ||
5993 | hw->vendor_id = pdev->vendor; | |
5994 | hw->device_id = pdev->device; | |
5995 | hw->revision_id = pdev->revision; | |
5996 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
5997 | hw->subsystem_device_id = pdev->subsystem_device; | |
5998 | ||
55570b6f ET |
5999 | /* get_invariants needs the device IDs */ |
6000 | ii->get_invariants(hw); | |
6001 | ||
8fc3bb6d | 6002 | /* Set common capability flags and settings */ |
0f9b232b | 6003 | rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); |
c087663e | 6004 | adapter->ring_feature[RING_F_RSS].limit = rss; |
8fc3bb6d | 6005 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
8fc3bb6d ET |
6006 | adapter->max_q_vectors = MAX_Q_VECTORS_82599; |
6007 | adapter->atr_sample_rate = 20; | |
d3cb9869 AD |
6008 | fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); |
6009 | adapter->ring_feature[RING_F_FDIR].limit = fdir; | |
8fc3bb6d ET |
6010 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
6011 | #ifdef CONFIG_IXGBE_DCA | |
6012 | adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; | |
6013 | #endif | |
8829009d UK |
6014 | #ifdef CONFIG_IXGBE_DCB |
6015 | adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; | |
6016 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
6017 | #endif | |
8fc3bb6d ET |
6018 | #ifdef IXGBE_FCOE |
6019 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; | |
6020 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
6021 | #ifdef CONFIG_IXGBE_DCB | |
6022 | /* Default traffic class to use for FCoE */ | |
6023 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; | |
6024 | #endif /* CONFIG_IXGBE_DCB */ | |
6025 | #endif /* IXGBE_FCOE */ | |
6026 | ||
b82b17d9 | 6027 | /* initialize static ixgbe jump table entries */ |
1cdaaf54 AN |
6028 | adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), |
6029 | GFP_KERNEL); | |
6030 | if (!adapter->jump_tables[0]) | |
6031 | return -ENOMEM; | |
6032 | adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; | |
6033 | ||
6034 | for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) | |
6035 | adapter->jump_tables[i] = NULL; | |
b82b17d9 | 6036 | |
5d7daa35 JK |
6037 | adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * |
6038 | hw->mac.num_rar_entries, | |
6039 | GFP_ATOMIC); | |
530fd82a AD |
6040 | if (!adapter->mac_table) |
6041 | return -ENOMEM; | |
5d7daa35 | 6042 | |
3dfbfc7e TN |
6043 | if (ixgbe_init_rss_key(adapter)) |
6044 | return -ENOMEM; | |
6045 | ||
8fc3bb6d | 6046 | /* Set MAC specific capability flags and exceptions */ |
bd508178 AD |
6047 | switch (hw->mac.type) { |
6048 | case ixgbe_mac_82598EB: | |
8fc3bb6d | 6049 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; |
8fc3bb6d | 6050 | |
bf069c97 DS |
6051 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
6052 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
8fc3bb6d | 6053 | |
49c7ffbe | 6054 | adapter->max_q_vectors = MAX_Q_VECTORS_82598; |
8fc3bb6d ET |
6055 | adapter->ring_feature[RING_F_FDIR].limit = 0; |
6056 | adapter->atr_sample_rate = 0; | |
6057 | adapter->fdir_pballoc = 0; | |
6058 | #ifdef IXGBE_FCOE | |
6059 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
6060 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
6061 | #ifdef CONFIG_IXGBE_DCB | |
6062 | adapter->fcoe.up = 0; | |
6063 | #endif /* IXGBE_DCB */ | |
6064 | #endif /* IXGBE_FCOE */ | |
6065 | break; | |
6066 | case ixgbe_mac_82599EB: | |
6067 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) | |
6068 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
bd508178 | 6069 | break; |
b93a2226 | 6070 | case ixgbe_mac_X540: |
9a900eca | 6071 | fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); |
cb6d0f5e JK |
6072 | if (fwsm & IXGBE_FWSM_TS_ENABLED) |
6073 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
bd508178 | 6074 | break; |
49425dfc | 6075 | case ixgbe_mac_x550em_a: |
a21d0822 | 6076 | adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; |
b3eb4e18 MR |
6077 | switch (hw->device_id) { |
6078 | case IXGBE_DEV_ID_X550EM_A_1G_T: | |
6079 | case IXGBE_DEV_ID_X550EM_A_1G_T_L: | |
6080 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
6081 | break; | |
6082 | default: | |
6083 | break; | |
6084 | } | |
a21d0822 ET |
6085 | /* fall through */ |
6086 | case ixgbe_mac_X550EM_x: | |
8829009d UK |
6087 | #ifdef CONFIG_IXGBE_DCB |
6088 | adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; | |
6089 | #endif | |
6090 | #ifdef IXGBE_FCOE | |
6091 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
6092 | #ifdef CONFIG_IXGBE_DCB | |
6093 | adapter->fcoe.up = 0; | |
6094 | #endif /* IXGBE_DCB */ | |
6095 | #endif /* IXGBE_FCOE */ | |
6096 | /* Fall Through */ | |
9a75a1ac | 6097 | case ixgbe_mac_X550: |
b3eb4e18 MR |
6098 | if (hw->mac.type == ixgbe_mac_X550) |
6099 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
9a75a1ac DS |
6100 | #ifdef CONFIG_IXGBE_DCA |
6101 | adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; | |
67359c3c | 6102 | #endif |
67359c3c | 6103 | adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; |
9a75a1ac | 6104 | break; |
bd508178 AD |
6105 | default: |
6106 | break; | |
f8212f97 | 6107 | } |
2f90b865 | 6108 | |
7c8ae65a AD |
6109 | #ifdef IXGBE_FCOE |
6110 | /* FCoE support exists, always init the FCoE lock */ | |
6111 | spin_lock_init(&adapter->fcoe.lock); | |
6112 | ||
6113 | #endif | |
1fc5f038 AD |
6114 | /* n-tuple support exists, always init our spinlock */ |
6115 | spin_lock_init(&adapter->fdir_perfect_lock); | |
6116 | ||
7a6b6f51 | 6117 | #ifdef CONFIG_IXGBE_DCB |
8829009d | 6118 | ixgbe_init_dcb(adapter); |
2f90b865 | 6119 | #endif |
9a799d71 AK |
6120 | |
6121 | /* default flow control settings */ | |
cd7664f6 | 6122 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 6123 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
9da712d2 | 6124 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
6125 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
6126 | hw->fc.send_xon = true; | |
73d80953 | 6127 | hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); |
9a799d71 | 6128 | |
99d74487 | 6129 | #ifdef CONFIG_PCI_IOV |
170e8543 JK |
6130 | if (max_vfs > 0) |
6131 | e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); | |
6132 | ||
99d74487 | 6133 | /* assign number of SR-IOV VFs */ |
170e8543 | 6134 | if (hw->mac.type != ixgbe_mac_82598EB) { |
dcc23e3a | 6135 | if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { |
5c11f00d | 6136 | max_vfs = 0; |
170e8543 | 6137 | e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); |
170e8543 JK |
6138 | } |
6139 | } | |
6140 | #endif /* CONFIG_PCI_IOV */ | |
99d74487 | 6141 | |
30efa5a3 | 6142 | /* enable itr by default in dynamic mode */ |
f7554a2b | 6143 | adapter->rx_itr_setting = 1; |
f7554a2b | 6144 | adapter->tx_itr_setting = 1; |
30efa5a3 | 6145 | |
30efa5a3 JB |
6146 | /* set default ring sizes */ |
6147 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
6148 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
6149 | ||
bd198058 | 6150 | /* set default work limits */ |
59224555 | 6151 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 6152 | |
9a799d71 | 6153 | /* initialize eeprom parameters */ |
c44ade9e | 6154 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 6155 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
6156 | return -EIO; |
6157 | } | |
6158 | ||
2a47fa45 JF |
6159 | /* PF holds first pool slot */ |
6160 | set_bit(0, &adapter->fwd_bitmask); | |
9a799d71 AK |
6161 | set_bit(__IXGBE_DOWN, &adapter->state); |
6162 | ||
6163 | return 0; | |
6164 | } | |
6165 | ||
6166 | /** | |
6167 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 6168 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
6169 | * |
6170 | * Return 0 on success, negative on failure | |
6171 | **/ | |
b6ec895e | 6172 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 6173 | { |
b6ec895e | 6174 | struct device *dev = tx_ring->dev; |
de88eeeb | 6175 | int orig_node = dev_to_node(dev); |
ca8dfe25 | 6176 | int ring_node = -1; |
9a799d71 AK |
6177 | int size; |
6178 | ||
3a581073 | 6179 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
6180 | |
6181 | if (tx_ring->q_vector) | |
ca8dfe25 | 6182 | ring_node = tx_ring->q_vector->numa_node; |
de88eeeb | 6183 | |
ffed21bc | 6184 | tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); |
1a6c14a2 | 6185 | if (!tx_ring->tx_buffer_info) |
ffed21bc | 6186 | tx_ring->tx_buffer_info = vmalloc(size); |
e01c31a5 JB |
6187 | if (!tx_ring->tx_buffer_info) |
6188 | goto err; | |
9a799d71 AK |
6189 | |
6190 | /* round up to nearest 4K */ | |
12207e49 | 6191 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 6192 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 6193 | |
ca8dfe25 | 6194 | set_dev_node(dev, ring_node); |
de88eeeb AD |
6195 | tx_ring->desc = dma_alloc_coherent(dev, |
6196 | tx_ring->size, | |
6197 | &tx_ring->dma, | |
6198 | GFP_KERNEL); | |
6199 | set_dev_node(dev, orig_node); | |
6200 | if (!tx_ring->desc) | |
6201 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
6202 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
6203 | if (!tx_ring->desc) |
6204 | goto err; | |
9a799d71 | 6205 | |
3a581073 JB |
6206 | tx_ring->next_to_use = 0; |
6207 | tx_ring->next_to_clean = 0; | |
9a799d71 | 6208 | return 0; |
e01c31a5 JB |
6209 | |
6210 | err: | |
6211 | vfree(tx_ring->tx_buffer_info); | |
6212 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 6213 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 6214 | return -ENOMEM; |
9a799d71 AK |
6215 | } |
6216 | ||
69888674 AD |
6217 | /** |
6218 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
6219 | * @adapter: board private structure | |
6220 | * | |
6221 | * If this function returns with an error, then it's possible one or | |
6222 | * more of the rings is populated (while the rest are not). It is the | |
6223 | * callers duty to clean those orphaned rings. | |
6224 | * | |
6225 | * Return 0 on success, negative on failure | |
6226 | **/ | |
6227 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
6228 | { | |
33fdc82f | 6229 | int i, j = 0, err = 0; |
69888674 AD |
6230 | |
6231 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 6232 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
6233 | if (!err) |
6234 | continue; | |
de3d5b94 | 6235 | |
396e799c | 6236 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
de3d5b94 | 6237 | goto err_setup_tx; |
69888674 | 6238 | } |
33fdc82f JF |
6239 | for (j = 0; j < adapter->num_xdp_queues; j++) { |
6240 | err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); | |
6241 | if (!err) | |
6242 | continue; | |
6243 | ||
6244 | e_err(probe, "Allocation for Tx Queue %u failed\n", j); | |
6245 | goto err_setup_tx; | |
6246 | } | |
69888674 | 6247 | |
de3d5b94 AD |
6248 | return 0; |
6249 | err_setup_tx: | |
6250 | /* rewind the index freeing the rings as we go */ | |
33fdc82f JF |
6251 | while (j--) |
6252 | ixgbe_free_tx_resources(adapter->xdp_ring[j]); | |
de3d5b94 AD |
6253 | while (i--) |
6254 | ixgbe_free_tx_resources(adapter->tx_ring[i]); | |
69888674 AD |
6255 | return err; |
6256 | } | |
6257 | ||
9a799d71 AK |
6258 | /** |
6259 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 6260 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
6261 | * |
6262 | * Returns 0 on success, negative on failure | |
6263 | **/ | |
92470808 JF |
6264 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, |
6265 | struct ixgbe_ring *rx_ring) | |
9a799d71 | 6266 | { |
b6ec895e | 6267 | struct device *dev = rx_ring->dev; |
de88eeeb | 6268 | int orig_node = dev_to_node(dev); |
ca8dfe25 | 6269 | int ring_node = -1; |
021230d4 | 6270 | int size; |
9a799d71 | 6271 | |
3a581073 | 6272 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
6273 | |
6274 | if (rx_ring->q_vector) | |
ca8dfe25 | 6275 | ring_node = rx_ring->q_vector->numa_node; |
de88eeeb | 6276 | |
ffed21bc | 6277 | rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); |
1a6c14a2 | 6278 | if (!rx_ring->rx_buffer_info) |
ffed21bc | 6279 | rx_ring->rx_buffer_info = vmalloc(size); |
b6ec895e AD |
6280 | if (!rx_ring->rx_buffer_info) |
6281 | goto err; | |
9a799d71 | 6282 | |
9a799d71 | 6283 | /* Round up to nearest 4K */ |
3a581073 JB |
6284 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
6285 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 6286 | |
ca8dfe25 | 6287 | set_dev_node(dev, ring_node); |
de88eeeb AD |
6288 | rx_ring->desc = dma_alloc_coherent(dev, |
6289 | rx_ring->size, | |
6290 | &rx_ring->dma, | |
6291 | GFP_KERNEL); | |
6292 | set_dev_node(dev, orig_node); | |
6293 | if (!rx_ring->desc) | |
6294 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
6295 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
6296 | if (!rx_ring->desc) |
6297 | goto err; | |
9a799d71 | 6298 | |
3a581073 JB |
6299 | rx_ring->next_to_clean = 0; |
6300 | rx_ring->next_to_use = 0; | |
9a799d71 | 6301 | |
92470808 JF |
6302 | rx_ring->xdp_prog = adapter->xdp_prog; |
6303 | ||
9a799d71 | 6304 | return 0; |
b6ec895e AD |
6305 | err: |
6306 | vfree(rx_ring->rx_buffer_info); | |
6307 | rx_ring->rx_buffer_info = NULL; | |
6308 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 6309 | return -ENOMEM; |
9a799d71 AK |
6310 | } |
6311 | ||
69888674 AD |
6312 | /** |
6313 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
6314 | * @adapter: board private structure | |
6315 | * | |
6316 | * If this function returns with an error, then it's possible one or | |
6317 | * more of the rings is populated (while the rest are not). It is the | |
6318 | * callers duty to clean those orphaned rings. | |
6319 | * | |
6320 | * Return 0 on success, negative on failure | |
6321 | **/ | |
69888674 AD |
6322 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
6323 | { | |
6324 | int i, err = 0; | |
6325 | ||
6326 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
92470808 | 6327 | err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); |
69888674 AD |
6328 | if (!err) |
6329 | continue; | |
de3d5b94 | 6330 | |
396e799c | 6331 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
de3d5b94 | 6332 | goto err_setup_rx; |
69888674 AD |
6333 | } |
6334 | ||
7c8ae65a AD |
6335 | #ifdef IXGBE_FCOE |
6336 | err = ixgbe_setup_fcoe_ddp_resources(adapter); | |
6337 | if (!err) | |
6338 | #endif | |
6339 | return 0; | |
de3d5b94 AD |
6340 | err_setup_rx: |
6341 | /* rewind the index freeing the rings as we go */ | |
6342 | while (i--) | |
6343 | ixgbe_free_rx_resources(adapter->rx_ring[i]); | |
69888674 AD |
6344 | return err; |
6345 | } | |
6346 | ||
9a799d71 AK |
6347 | /** |
6348 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
6349 | * @tx_ring: Tx descriptor ring for a specific queue |
6350 | * | |
6351 | * Free all transmit software resources | |
6352 | **/ | |
b6ec895e | 6353 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 6354 | { |
b6ec895e | 6355 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
6356 | |
6357 | vfree(tx_ring->tx_buffer_info); | |
6358 | tx_ring->tx_buffer_info = NULL; | |
6359 | ||
b6ec895e AD |
6360 | /* if not set, then don't free */ |
6361 | if (!tx_ring->desc) | |
6362 | return; | |
6363 | ||
6364 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
6365 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
6366 | |
6367 | tx_ring->desc = NULL; | |
6368 | } | |
6369 | ||
6370 | /** | |
6371 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
6372 | * @adapter: board private structure | |
6373 | * | |
6374 | * Free all transmit software resources | |
6375 | **/ | |
6376 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
6377 | { | |
6378 | int i; | |
6379 | ||
6380 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 6381 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 6382 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
33fdc82f JF |
6383 | for (i = 0; i < adapter->num_xdp_queues; i++) |
6384 | if (adapter->xdp_ring[i]->desc) | |
6385 | ixgbe_free_tx_resources(adapter->xdp_ring[i]); | |
9a799d71 AK |
6386 | } |
6387 | ||
6388 | /** | |
b4617240 | 6389 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
6390 | * @rx_ring: ring to clean the resources from |
6391 | * | |
6392 | * Free all receive software resources | |
6393 | **/ | |
b6ec895e | 6394 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 6395 | { |
b6ec895e | 6396 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 | 6397 | |
92470808 | 6398 | rx_ring->xdp_prog = NULL; |
9a799d71 AK |
6399 | vfree(rx_ring->rx_buffer_info); |
6400 | rx_ring->rx_buffer_info = NULL; | |
6401 | ||
b6ec895e AD |
6402 | /* if not set, then don't free */ |
6403 | if (!rx_ring->desc) | |
6404 | return; | |
6405 | ||
6406 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
6407 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
6408 | |
6409 | rx_ring->desc = NULL; | |
6410 | } | |
6411 | ||
6412 | /** | |
6413 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
6414 | * @adapter: board private structure | |
6415 | * | |
6416 | * Free all receive software resources | |
6417 | **/ | |
6418 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
6419 | { | |
6420 | int i; | |
6421 | ||
7c8ae65a AD |
6422 | #ifdef IXGBE_FCOE |
6423 | ixgbe_free_fcoe_ddp_resources(adapter); | |
6424 | ||
6425 | #endif | |
9a799d71 | 6426 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 6427 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 6428 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
6429 | } |
6430 | ||
9a799d71 AK |
6431 | /** |
6432 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
6433 | * @netdev: network interface device structure | |
6434 | * @new_mtu: new value for maximum frame size | |
6435 | * | |
6436 | * Returns 0 on success, negative on failure | |
6437 | **/ | |
6438 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
6439 | { | |
6440 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
655309e9 AD |
6441 | |
6442 | /* | |
872844dd AD |
6443 | * For 82599EB we cannot allow legacy VFs to enable their receive |
6444 | * paths when MTU greater than 1500 is configured. So display a | |
6445 | * warning that legacy VFs will be disabled. | |
655309e9 AD |
6446 | */ |
6447 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
6448 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
91c527a5 | 6449 | (new_mtu > ETH_DATA_LEN)) |
872844dd | 6450 | e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); |
9a799d71 | 6451 | |
396e799c | 6452 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 6453 | |
021230d4 | 6454 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
6455 | netdev->mtu = new_mtu; |
6456 | ||
d4f80882 AV |
6457 | if (netif_running(netdev)) |
6458 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
6459 | |
6460 | return 0; | |
6461 | } | |
6462 | ||
6463 | /** | |
6464 | * ixgbe_open - Called when a network interface is made active | |
6465 | * @netdev: network interface device structure | |
6466 | * | |
6467 | * Returns 0 on success, negative value on failure | |
6468 | * | |
6469 | * The open entry point is called when a network interface is made | |
6470 | * active by the system (IFF_UP). At this point all resources needed | |
6471 | * for transmit and receive operations are allocated, the interrupt | |
6472 | * handler is registered with the OS, the watchdog timer is started, | |
6473 | * and the stack is notified that the interface is ready. | |
6474 | **/ | |
6c211fe1 | 6475 | int ixgbe_open(struct net_device *netdev) |
9a799d71 AK |
6476 | { |
6477 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
961fac88 | 6478 | struct ixgbe_hw *hw = &adapter->hw; |
2a47fa45 | 6479 | int err, queues; |
4bebfaa5 AK |
6480 | |
6481 | /* disallow open during test */ | |
6482 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
6483 | return -EBUSY; | |
9a799d71 | 6484 | |
54386467 JB |
6485 | netif_carrier_off(netdev); |
6486 | ||
9a799d71 AK |
6487 | /* allocate transmit descriptors */ |
6488 | err = ixgbe_setup_all_tx_resources(adapter); | |
6489 | if (err) | |
6490 | goto err_setup_tx; | |
6491 | ||
9a799d71 AK |
6492 | /* allocate receive descriptors */ |
6493 | err = ixgbe_setup_all_rx_resources(adapter); | |
6494 | if (err) | |
6495 | goto err_setup_rx; | |
6496 | ||
6497 | ixgbe_configure(adapter); | |
6498 | ||
021230d4 | 6499 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
6500 | if (err) |
6501 | goto err_req_irq; | |
6502 | ||
ac802f5d | 6503 | /* Notify the stack of the actual queue counts. */ |
2a47fa45 JF |
6504 | if (adapter->num_rx_pools > 1) |
6505 | queues = adapter->num_rx_queues_per_pool; | |
6506 | else | |
6507 | queues = adapter->num_tx_queues; | |
6508 | ||
6509 | err = netif_set_real_num_tx_queues(netdev, queues); | |
ac802f5d AD |
6510 | if (err) |
6511 | goto err_set_queues; | |
6512 | ||
2a47fa45 JF |
6513 | if (adapter->num_rx_pools > 1 && |
6514 | adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) | |
6515 | queues = IXGBE_MAX_L2A_QUEUES; | |
6516 | else | |
6517 | queues = adapter->num_rx_queues; | |
6518 | err = netif_set_real_num_rx_queues(netdev, queues); | |
ac802f5d AD |
6519 | if (err) |
6520 | goto err_set_queues; | |
6521 | ||
1a71ab24 | 6522 | ixgbe_ptp_init(adapter); |
1a71ab24 | 6523 | |
c7ccde0f | 6524 | ixgbe_up_complete(adapter); |
9a799d71 | 6525 | |
a21d0822 | 6526 | ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); |
b3a49557 | 6527 | udp_tunnel_get_rx_info(netdev); |
67359c3c | 6528 | |
9a799d71 AK |
6529 | return 0; |
6530 | ||
ac802f5d AD |
6531 | err_set_queues: |
6532 | ixgbe_free_irq(adapter); | |
9a799d71 | 6533 | err_req_irq: |
a20a1199 | 6534 | ixgbe_free_all_rx_resources(adapter); |
961fac88 DS |
6535 | if (hw->phy.ops.set_phy_power && !adapter->wol) |
6536 | hw->phy.ops.set_phy_power(&adapter->hw, false); | |
de3d5b94 | 6537 | err_setup_rx: |
a20a1199 | 6538 | ixgbe_free_all_tx_resources(adapter); |
de3d5b94 | 6539 | err_setup_tx: |
9a799d71 AK |
6540 | ixgbe_reset(adapter); |
6541 | ||
6542 | return err; | |
6543 | } | |
6544 | ||
a0cccce2 JK |
6545 | static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) |
6546 | { | |
6547 | ixgbe_ptp_suspend(adapter); | |
6548 | ||
6ac74394 DS |
6549 | if (adapter->hw.phy.ops.enter_lplu) { |
6550 | adapter->hw.phy.reset_disable = true; | |
6551 | ixgbe_down(adapter); | |
6552 | adapter->hw.phy.ops.enter_lplu(&adapter->hw); | |
6553 | adapter->hw.phy.reset_disable = false; | |
6554 | } else { | |
6555 | ixgbe_down(adapter); | |
6556 | } | |
6557 | ||
a0cccce2 JK |
6558 | ixgbe_free_irq(adapter); |
6559 | ||
6560 | ixgbe_free_all_tx_resources(adapter); | |
6561 | ixgbe_free_all_rx_resources(adapter); | |
6562 | } | |
6563 | ||
9a799d71 AK |
6564 | /** |
6565 | * ixgbe_close - Disables a network interface | |
6566 | * @netdev: network interface device structure | |
6567 | * | |
6568 | * Returns 0, this is not allowed to fail | |
6569 | * | |
6570 | * The close entry point is called when an interface is de-activated | |
6571 | * by the OS. The hardware is still under the drivers control, but | |
6572 | * needs to be disabled. A global MAC reset is issued to stop the | |
6573 | * hardware, and all transmit and receive resources are freed. | |
6574 | **/ | |
6c211fe1 | 6575 | int ixgbe_close(struct net_device *netdev) |
9a799d71 AK |
6576 | { |
6577 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 | 6578 | |
1a71ab24 | 6579 | ixgbe_ptp_stop(adapter); |
1a71ab24 | 6580 | |
f7f37e7f ET |
6581 | if (netif_device_present(netdev)) |
6582 | ixgbe_close_suspend(adapter); | |
9a799d71 | 6583 | |
e4911d57 AD |
6584 | ixgbe_fdir_filter_exit(adapter); |
6585 | ||
5eba3699 | 6586 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
6587 | |
6588 | return 0; | |
6589 | } | |
6590 | ||
b3c8b4ba AD |
6591 | #ifdef CONFIG_PM |
6592 | static int ixgbe_resume(struct pci_dev *pdev) | |
6593 | { | |
c60fbb00 AD |
6594 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6595 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
6596 | u32 err; |
6597 | ||
0391bbe3 | 6598 | adapter->hw.hw_addr = adapter->io_addr; |
b3c8b4ba AD |
6599 | pci_set_power_state(pdev, PCI_D0); |
6600 | pci_restore_state(pdev); | |
656ab817 DS |
6601 | /* |
6602 | * pci_restore_state clears dev->state_saved so call | |
6603 | * pci_save_state to restore it. | |
6604 | */ | |
6605 | pci_save_state(pdev); | |
9ce77666 | 6606 | |
6607 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 6608 | if (err) { |
849c4542 | 6609 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
6610 | return err; |
6611 | } | |
4e857c58 | 6612 | smp_mb__before_atomic(); |
41c62843 | 6613 | clear_bit(__IXGBE_DISABLED, &adapter->state); |
b3c8b4ba AD |
6614 | pci_set_master(pdev); |
6615 | ||
dd4d8ca6 | 6616 | pci_wake_from_d3(pdev, false); |
b3c8b4ba | 6617 | |
b3c8b4ba AD |
6618 | ixgbe_reset(adapter); |
6619 | ||
495dce12 WJP |
6620 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6621 | ||
ac802f5d AD |
6622 | rtnl_lock(); |
6623 | err = ixgbe_init_interrupt_scheme(adapter); | |
6624 | if (!err && netif_running(netdev)) | |
c60fbb00 | 6625 | err = ixgbe_open(netdev); |
ac802f5d | 6626 | |
ac802f5d | 6627 | |
f7f37e7f ET |
6628 | if (!err) |
6629 | netif_device_attach(netdev); | |
6630 | rtnl_unlock(); | |
b3c8b4ba | 6631 | |
f7f37e7f | 6632 | return err; |
b3c8b4ba | 6633 | } |
b3c8b4ba | 6634 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
6635 | |
6636 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 6637 | { |
c60fbb00 AD |
6638 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6639 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
6640 | struct ixgbe_hw *hw = &adapter->hw; |
6641 | u32 ctrl, fctrl; | |
6642 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
6643 | #ifdef CONFIG_PM |
6644 | int retval = 0; | |
6645 | #endif | |
6646 | ||
f7f37e7f | 6647 | rtnl_lock(); |
b3c8b4ba AD |
6648 | netif_device_detach(netdev); |
6649 | ||
a0cccce2 JK |
6650 | if (netif_running(netdev)) |
6651 | ixgbe_close_suspend(adapter); | |
b3c8b4ba | 6652 | |
5f5ae6fc | 6653 | ixgbe_clear_interrupt_scheme(adapter); |
f7f37e7f | 6654 | rtnl_unlock(); |
5f5ae6fc | 6655 | |
b3c8b4ba AD |
6656 | #ifdef CONFIG_PM |
6657 | retval = pci_save_state(pdev); | |
6658 | if (retval) | |
6659 | return retval; | |
4df10466 | 6660 | |
b3c8b4ba | 6661 | #endif |
f4f1040a JK |
6662 | if (hw->mac.ops.stop_link_on_d3) |
6663 | hw->mac.ops.stop_link_on_d3(hw); | |
6664 | ||
e8e26350 PW |
6665 | if (wufc) { |
6666 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 6667 | |
ec74a471 ET |
6668 | /* enable the optics for 82599 SFP+ fiber as we can WoL */ |
6669 | if (hw->mac.ops.enable_tx_laser) | |
c509e754 DS |
6670 | hw->mac.ops.enable_tx_laser(hw); |
6671 | ||
e8e26350 PW |
6672 | /* turn on all-multi mode if wake on multicast is enabled */ |
6673 | if (wufc & IXGBE_WUFC_MC) { | |
6674 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
6675 | fctrl |= IXGBE_FCTRL_MPE; | |
6676 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
6677 | } | |
6678 | ||
6679 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
6680 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
6681 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
6682 | ||
6683 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
6684 | } else { | |
6685 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
6686 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
6687 | } | |
6688 | ||
bd508178 AD |
6689 | switch (hw->mac.type) { |
6690 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 6691 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
6692 | break; |
6693 | case ixgbe_mac_82599EB: | |
b93a2226 | 6694 | case ixgbe_mac_X540: |
9a75a1ac DS |
6695 | case ixgbe_mac_X550: |
6696 | case ixgbe_mac_X550EM_x: | |
49425dfc | 6697 | case ixgbe_mac_x550em_a: |
bd508178 AD |
6698 | pci_wake_from_d3(pdev, !!wufc); |
6699 | break; | |
6700 | default: | |
6701 | break; | |
6702 | } | |
b3c8b4ba | 6703 | |
9d8d05ae | 6704 | *enable_wake = !!wufc; |
961fac88 DS |
6705 | if (hw->phy.ops.set_phy_power && !*enable_wake) |
6706 | hw->phy.ops.set_phy_power(hw, false); | |
9d8d05ae | 6707 | |
b3c8b4ba AD |
6708 | ixgbe_release_hw_control(adapter); |
6709 | ||
41c62843 MR |
6710 | if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) |
6711 | pci_disable_device(pdev); | |
b3c8b4ba | 6712 | |
9d8d05ae RW |
6713 | return 0; |
6714 | } | |
6715 | ||
6716 | #ifdef CONFIG_PM | |
6717 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
6718 | { | |
6719 | int retval; | |
6720 | bool wake; | |
6721 | ||
6722 | retval = __ixgbe_shutdown(pdev, &wake); | |
6723 | if (retval) | |
6724 | return retval; | |
6725 | ||
6726 | if (wake) { | |
6727 | pci_prepare_to_sleep(pdev); | |
6728 | } else { | |
6729 | pci_wake_from_d3(pdev, false); | |
6730 | pci_set_power_state(pdev, PCI_D3hot); | |
6731 | } | |
b3c8b4ba AD |
6732 | |
6733 | return 0; | |
6734 | } | |
9d8d05ae | 6735 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
6736 | |
6737 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
6738 | { | |
9d8d05ae RW |
6739 | bool wake; |
6740 | ||
6741 | __ixgbe_shutdown(pdev, &wake); | |
6742 | ||
6743 | if (system_state == SYSTEM_POWER_OFF) { | |
6744 | pci_wake_from_d3(pdev, wake); | |
6745 | pci_set_power_state(pdev, PCI_D3hot); | |
6746 | } | |
b3c8b4ba AD |
6747 | } |
6748 | ||
9a799d71 AK |
6749 | /** |
6750 | * ixgbe_update_stats - Update the board statistics counters. | |
6751 | * @adapter: board private structure | |
6752 | **/ | |
6753 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
6754 | { | |
2d86f139 | 6755 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 6756 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 6757 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
6758 | u64 total_mpc = 0; |
6759 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
6760 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
6761 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 6762 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
9a799d71 | 6763 | |
d08935c2 DS |
6764 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
6765 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
6766 | return; | |
6767 | ||
94b982b2 | 6768 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 6769 | u64 rsc_count = 0; |
94b982b2 | 6770 | u64 rsc_flush = 0; |
94b982b2 | 6771 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
6772 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
6773 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
6774 | } |
6775 | adapter->rsc_total_count = rsc_count; | |
6776 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
6777 | } |
6778 | ||
5b7da515 AD |
6779 | for (i = 0; i < adapter->num_rx_queues; i++) { |
6780 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
6781 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
6782 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
6783 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 6784 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
6785 | bytes += rx_ring->stats.bytes; |
6786 | packets += rx_ring->stats.packets; | |
6787 | } | |
6788 | adapter->non_eop_descs = non_eop_descs; | |
6789 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
6790 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 6791 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
6792 | netdev->stats.rx_bytes = bytes; |
6793 | netdev->stats.rx_packets = packets; | |
6794 | ||
6795 | bytes = 0; | |
6796 | packets = 0; | |
7ca3bc58 | 6797 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
6798 | for (i = 0; i < adapter->num_tx_queues; i++) { |
6799 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
6800 | restart_queue += tx_ring->tx_stats.restart_queue; | |
6801 | tx_busy += tx_ring->tx_stats.tx_busy; | |
6802 | bytes += tx_ring->stats.bytes; | |
6803 | packets += tx_ring->stats.packets; | |
6804 | } | |
33fdc82f JF |
6805 | for (i = 0; i < adapter->num_xdp_queues; i++) { |
6806 | struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; | |
6807 | ||
6808 | restart_queue += xdp_ring->tx_stats.restart_queue; | |
6809 | tx_busy += xdp_ring->tx_stats.tx_busy; | |
6810 | bytes += xdp_ring->stats.bytes; | |
6811 | packets += xdp_ring->stats.packets; | |
6812 | } | |
eb985f09 | 6813 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
6814 | adapter->tx_busy = tx_busy; |
6815 | netdev->stats.tx_bytes = bytes; | |
6816 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 6817 | |
7ca647bd | 6818 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
6819 | |
6820 | /* 8 register reads */ | |
6f11eef7 AV |
6821 | for (i = 0; i < 8; i++) { |
6822 | /* for packet buffers not used, the register should read 0 */ | |
6823 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
6824 | missed_rx += mpc; | |
7ca647bd JP |
6825 | hwstats->mpc[i] += mpc; |
6826 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
6827 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
6828 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
6829 | switch (hw->mac.type) { |
6830 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
6831 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
6832 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
6833 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
6834 | hwstats->pxonrxc[i] += |
6835 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
6836 | break; |
6837 | case ixgbe_mac_82599EB: | |
b93a2226 | 6838 | case ixgbe_mac_X540: |
9a75a1ac DS |
6839 | case ixgbe_mac_X550: |
6840 | case ixgbe_mac_X550EM_x: | |
49425dfc | 6841 | case ixgbe_mac_x550em_a: |
bd508178 AD |
6842 | hwstats->pxonrxc[i] += |
6843 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
6844 | break; |
6845 | default: | |
6846 | break; | |
e8e26350 | 6847 | } |
6f11eef7 | 6848 | } |
1a70db4b ET |
6849 | |
6850 | /*16 register reads */ | |
6851 | for (i = 0; i < 16; i++) { | |
6852 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
6853 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
6854 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
9a75a1ac DS |
6855 | (hw->mac.type == ixgbe_mac_X540) || |
6856 | (hw->mac.type == ixgbe_mac_X550) || | |
49425dfc MR |
6857 | (hw->mac.type == ixgbe_mac_X550EM_x) || |
6858 | (hw->mac.type == ixgbe_mac_x550em_a)) { | |
1a70db4b ET |
6859 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); |
6860 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
6861 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
6862 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
6863 | } | |
6864 | } | |
6865 | ||
7ca647bd | 6866 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 6867 | /* work around hardware counting issue */ |
7ca647bd | 6868 | hwstats->gprc -= missed_rx; |
6f11eef7 | 6869 | |
c84d324c JF |
6870 | ixgbe_update_xoff_received(adapter); |
6871 | ||
6f11eef7 | 6872 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
6873 | switch (hw->mac.type) { |
6874 | case ixgbe_mac_82598EB: | |
6875 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
6876 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
6877 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
6878 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
6879 | break; | |
b93a2226 | 6880 | case ixgbe_mac_X540: |
9a75a1ac DS |
6881 | case ixgbe_mac_X550: |
6882 | case ixgbe_mac_X550EM_x: | |
49425dfc | 6883 | case ixgbe_mac_x550em_a: |
9a75a1ac | 6884 | /* OS2BMC stats are X540 and later */ |
58f6bcf9 ET |
6885 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); |
6886 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
6887 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
6888 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
93df9465 | 6889 | /* fall through */ |
58f6bcf9 | 6890 | case ixgbe_mac_82599EB: |
a4d4f629 AD |
6891 | for (i = 0; i < 16; i++) |
6892 | adapter->hw_rx_no_dma_resources += | |
6893 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
7ca647bd | 6894 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 6895 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 6896 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 6897 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 6898 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 6899 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 6900 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
6901 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
6902 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 6903 | #ifdef IXGBE_FCOE |
7ca647bd JP |
6904 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
6905 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
6906 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
6907 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
6908 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
6909 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc | 6910 | /* Add up per cpu counters for total ddp aloc fail */ |
5a1ee270 AD |
6911 | if (adapter->fcoe.ddp_pool) { |
6912 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
6913 | struct ixgbe_fcoe_ddp_pool *ddp_pool; | |
6914 | unsigned int cpu; | |
6915 | u64 noddp = 0, noddp_ext_buff = 0; | |
7b859ebc | 6916 | for_each_possible_cpu(cpu) { |
5a1ee270 AD |
6917 | ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); |
6918 | noddp += ddp_pool->noddp; | |
6919 | noddp_ext_buff += ddp_pool->noddp_ext_buff; | |
7b859ebc | 6920 | } |
5a1ee270 AD |
6921 | hwstats->fcoe_noddp = noddp; |
6922 | hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; | |
7b859ebc | 6923 | } |
6d45522c | 6924 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
6925 | break; |
6926 | default: | |
6927 | break; | |
e8e26350 | 6928 | } |
9a799d71 | 6929 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
6930 | hwstats->bprc += bprc; |
6931 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 6932 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
6933 | hwstats->mprc -= bprc; |
6934 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
6935 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
6936 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
6937 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
6938 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
6939 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
6940 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
6941 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 6942 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 6943 | hwstats->lxontxc += lxon; |
6f11eef7 | 6944 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 6945 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
6946 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
6947 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
6948 | /* |
6949 | * 82598 errata - tx of flow control packets is included in tx counters | |
6950 | */ | |
6951 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
6952 | hwstats->gptc -= xon_off_tot; |
6953 | hwstats->mptc -= xon_off_tot; | |
6954 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
6955 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
6956 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
6957 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
6958 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
6959 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6960 | hwstats->ptc64 -= xon_off_tot; | |
6961 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
6962 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
6963 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
6964 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
6965 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
6966 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
6967 | |
6968 | /* Fill out the OS statistics structure */ | |
7ca647bd | 6969 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
6970 | |
6971 | /* Rx Errors */ | |
7ca647bd | 6972 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 6973 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
6974 | netdev->stats.rx_length_errors = hwstats->rlec; |
6975 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 6976 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
6977 | } |
6978 | ||
6979 | /** | |
d034acf1 | 6980 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
49ce9c2c | 6981 | * @adapter: pointer to the device adapter structure |
9a799d71 | 6982 | **/ |
d034acf1 | 6983 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 6984 | { |
cf8280ee | 6985 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 6986 | int i; |
cf8280ee | 6987 | |
d034acf1 AD |
6988 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
6989 | return; | |
6990 | ||
6991 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 6992 | |
d034acf1 | 6993 | /* if interface is down do nothing */ |
fe49f04a | 6994 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
6995 | return; |
6996 | ||
6997 | /* do nothing if we are not using signature filters */ | |
6998 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
6999 | return; | |
7000 | ||
7001 | adapter->fdir_overflow++; | |
7002 | ||
93c52dd0 AD |
7003 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
7004 | for (i = 0; i < adapter->num_tx_queues; i++) | |
7005 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
e7cf745b | 7006 | &(adapter->tx_ring[i]->state)); |
33fdc82f JF |
7007 | for (i = 0; i < adapter->num_xdp_queues; i++) |
7008 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
7009 | &adapter->xdp_ring[i]->state); | |
d034acf1 AD |
7010 | /* re-enable flow director interrupts */ |
7011 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
7012 | } else { |
7013 | e_err(probe, "failed to finish FDIR re-initialization, " | |
7014 | "ignored adding FDIR ATR filters\n"); | |
7015 | } | |
93c52dd0 AD |
7016 | } |
7017 | ||
7018 | /** | |
7019 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
49ce9c2c | 7020 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
7021 | * |
7022 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 7023 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 7024 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 7025 | * determine if a hang has occurred. |
93c52dd0 AD |
7026 | */ |
7027 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 7028 | { |
cf8280ee | 7029 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
7030 | u64 eics = 0; |
7031 | int i; | |
cf8280ee | 7032 | |
09f40aed | 7033 | /* If we're down, removing or resetting, just bail */ |
93c52dd0 | 7034 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
09f40aed | 7035 | test_bit(__IXGBE_REMOVING, &adapter->state) || |
93c52dd0 AD |
7036 | test_bit(__IXGBE_RESETTING, &adapter->state)) |
7037 | return; | |
22d5a71b | 7038 | |
93c52dd0 AD |
7039 | /* Force detection of hung controller */ |
7040 | if (netif_carrier_ok(adapter->netdev)) { | |
7041 | for (i = 0; i < adapter->num_tx_queues; i++) | |
7042 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
33fdc82f JF |
7043 | for (i = 0; i < adapter->num_xdp_queues; i++) |
7044 | set_check_for_tx_hang(adapter->xdp_ring[i]); | |
93c52dd0 | 7045 | } |
22d5a71b | 7046 | |
fe49f04a AD |
7047 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
7048 | /* | |
7049 | * for legacy and MSI interrupts don't set any bits | |
7050 | * that are enabled for EIAM, because this operation | |
7051 | * would set *both* EIMS and EICS for any bit in EIAM | |
7052 | */ | |
7053 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
7054 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
7055 | } else { |
7056 | /* get one bit for every active tx/rx interrupt vector */ | |
49c7ffbe | 7057 | for (i = 0; i < adapter->num_q_vectors; i++) { |
93c52dd0 | 7058 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; |
efe3d3c8 | 7059 | if (qv->rx.ring || qv->tx.ring) |
b4f47a48 | 7060 | eics |= BIT_ULL(i); |
93c52dd0 | 7061 | } |
cf8280ee | 7062 | } |
9a799d71 | 7063 | |
93c52dd0 | 7064 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a | 7065 | ixgbe_irq_rearm_queues(adapter, eics); |
cf8280ee JB |
7066 | } |
7067 | ||
e8e26350 | 7068 | /** |
93c52dd0 | 7069 | * ixgbe_watchdog_update_link - update the link status |
49ce9c2c BH |
7070 | * @adapter: pointer to the device adapter structure |
7071 | * @link_speed: pointer to a u32 to store the link_speed | |
e8e26350 | 7072 | **/ |
93c52dd0 | 7073 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 7074 | { |
e8e26350 | 7075 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
7076 | u32 link_speed = adapter->link_speed; |
7077 | bool link_up = adapter->link_up; | |
041441d0 | 7078 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; |
e8e26350 | 7079 | |
93c52dd0 AD |
7080 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
7081 | return; | |
7082 | ||
7083 | if (hw->mac.ops.check_link) { | |
7084 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 7085 | } else { |
93c52dd0 AD |
7086 | /* always assume link is up, if no check link function */ |
7087 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
7088 | link_up = true; | |
c4cf55e5 | 7089 | } |
041441d0 AD |
7090 | |
7091 | if (adapter->ixgbe_ieee_pfc) | |
7092 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
7093 | ||
3ebe8fde | 7094 | if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { |
041441d0 | 7095 | hw->mac.ops.fc_enable(hw); |
3ebe8fde AD |
7096 | ixgbe_set_rx_drop_en(adapter); |
7097 | } | |
93c52dd0 AD |
7098 | |
7099 | if (link_up || | |
7100 | time_after(jiffies, (adapter->link_check_timeout + | |
7101 | IXGBE_TRY_LINK_TIMEOUT))) { | |
7102 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
7103 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
7104 | IXGBE_WRITE_FLUSH(hw); | |
7105 | } | |
7106 | ||
7107 | adapter->link_up = link_up; | |
7108 | adapter->link_speed = link_speed; | |
e8e26350 PW |
7109 | } |
7110 | ||
107d3018 AD |
7111 | static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) |
7112 | { | |
7113 | #ifdef CONFIG_IXGBE_DCB | |
7114 | struct net_device *netdev = adapter->netdev; | |
7115 | struct dcb_app app = { | |
7116 | .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, | |
7117 | .protocol = 0, | |
7118 | }; | |
7119 | u8 up = 0; | |
7120 | ||
7121 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) | |
7122 | up = dcb_ieee_getapp_mask(netdev, &app); | |
7123 | ||
7124 | adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; | |
7125 | #endif | |
7126 | } | |
7127 | ||
1cd127fc DA |
7128 | static int ixgbe_enable_macvlan(struct net_device *upper, void *data) |
7129 | { | |
7130 | if (netif_is_macvlan(upper)) { | |
7131 | struct macvlan_dev *vlan = netdev_priv(upper); | |
7132 | ||
7133 | if (vlan->fwd_priv) | |
7134 | netif_tx_wake_all_queues(upper); | |
7135 | } | |
7136 | ||
7137 | return 0; | |
7138 | } | |
7139 | ||
e8e26350 | 7140 | /** |
93c52dd0 AD |
7141 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
7142 | * print link up message | |
49ce9c2c | 7143 | * @adapter: pointer to the device adapter structure |
e8e26350 | 7144 | **/ |
93c52dd0 | 7145 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 7146 | { |
93c52dd0 | 7147 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 7148 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 | 7149 | u32 link_speed = adapter->link_speed; |
454adb00 | 7150 | const char *speed_str; |
93c52dd0 | 7151 | bool flow_rx, flow_tx; |
e8e26350 | 7152 | |
93c52dd0 AD |
7153 | /* only continue if link was previously down */ |
7154 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 7155 | return; |
63d6e1d8 | 7156 | |
93c52dd0 | 7157 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 7158 | |
93c52dd0 AD |
7159 | switch (hw->mac.type) { |
7160 | case ixgbe_mac_82598EB: { | |
7161 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
7162 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
7163 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
7164 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
7165 | } | |
7166 | break; | |
7167 | case ixgbe_mac_X540: | |
9a75a1ac DS |
7168 | case ixgbe_mac_X550: |
7169 | case ixgbe_mac_X550EM_x: | |
49425dfc | 7170 | case ixgbe_mac_x550em_a: |
93c52dd0 AD |
7171 | case ixgbe_mac_82599EB: { |
7172 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
7173 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
7174 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
7175 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
7176 | } | |
7177 | break; | |
7178 | default: | |
7179 | flow_tx = false; | |
7180 | flow_rx = false; | |
7181 | break; | |
e8e26350 | 7182 | } |
3a6a4eda | 7183 | |
6cb562d6 JK |
7184 | adapter->last_rx_ptp_check = jiffies; |
7185 | ||
8fecf67c | 7186 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) |
1a71ab24 | 7187 | ixgbe_ptp_start_cyclecounter(adapter); |
3a6a4eda | 7188 | |
454adb00 MR |
7189 | switch (link_speed) { |
7190 | case IXGBE_LINK_SPEED_10GB_FULL: | |
7191 | speed_str = "10 Gbps"; | |
7192 | break; | |
7193 | case IXGBE_LINK_SPEED_2_5GB_FULL: | |
7194 | speed_str = "2.5 Gbps"; | |
7195 | break; | |
7196 | case IXGBE_LINK_SPEED_1GB_FULL: | |
7197 | speed_str = "1 Gbps"; | |
7198 | break; | |
7199 | case IXGBE_LINK_SPEED_100_FULL: | |
7200 | speed_str = "100 Mbps"; | |
7201 | break; | |
b3eb4e18 MR |
7202 | case IXGBE_LINK_SPEED_10_FULL: |
7203 | speed_str = "10 Mbps"; | |
7204 | break; | |
454adb00 MR |
7205 | default: |
7206 | speed_str = "unknown speed"; | |
7207 | break; | |
7208 | } | |
7209 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, | |
93c52dd0 AD |
7210 | ((flow_rx && flow_tx) ? "RX/TX" : |
7211 | (flow_rx ? "RX" : | |
7212 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 7213 | |
93c52dd0 | 7214 | netif_carrier_on(netdev); |
93c52dd0 | 7215 | ixgbe_check_vf_rate_limit(adapter); |
befa2af7 | 7216 | |
cdc04dcc ET |
7217 | /* enable transmits */ |
7218 | netif_tx_wake_all_queues(adapter->netdev); | |
7219 | ||
7220 | /* enable any upper devices */ | |
7221 | rtnl_lock(); | |
1cd127fc DA |
7222 | netdev_walk_all_upper_dev_rcu(adapter->netdev, |
7223 | ixgbe_enable_macvlan, NULL); | |
cdc04dcc ET |
7224 | rtnl_unlock(); |
7225 | ||
107d3018 AD |
7226 | /* update the default user priority for VFs */ |
7227 | ixgbe_update_default_up(adapter); | |
7228 | ||
befa2af7 AD |
7229 | /* ping all the active vfs to let them know link has changed */ |
7230 | ixgbe_ping_all_vfs(adapter); | |
e8e26350 PW |
7231 | } |
7232 | ||
c4cf55e5 | 7233 | /** |
93c52dd0 AD |
7234 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
7235 | * print link down message | |
49ce9c2c | 7236 | * @adapter: pointer to the adapter structure |
c4cf55e5 | 7237 | **/ |
581330ba | 7238 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) |
c4cf55e5 | 7239 | { |
cf8280ee | 7240 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 7241 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 7242 | |
93c52dd0 AD |
7243 | adapter->link_up = false; |
7244 | adapter->link_speed = 0; | |
cf8280ee | 7245 | |
93c52dd0 AD |
7246 | /* only continue if link was up previously */ |
7247 | if (!netif_carrier_ok(netdev)) | |
7248 | return; | |
264857b8 | 7249 | |
93c52dd0 AD |
7250 | /* poll for SFP+ cable when link is down */ |
7251 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
7252 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 7253 | |
8fecf67c | 7254 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) |
1a71ab24 | 7255 | ixgbe_ptp_start_cyclecounter(adapter); |
3a6a4eda | 7256 | |
93c52dd0 AD |
7257 | e_info(drv, "NIC Link is Down\n"); |
7258 | netif_carrier_off(netdev); | |
befa2af7 AD |
7259 | |
7260 | /* ping all the active vfs to let them know link has changed */ | |
7261 | ixgbe_ping_all_vfs(adapter); | |
93c52dd0 | 7262 | } |
e8e26350 | 7263 | |
07923c17 ET |
7264 | static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) |
7265 | { | |
7266 | int i; | |
7267 | ||
7268 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
7269 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
7270 | ||
7271 | if (tx_ring->next_to_use != tx_ring->next_to_clean) | |
7272 | return true; | |
7273 | } | |
7274 | ||
33fdc82f JF |
7275 | for (i = 0; i < adapter->num_xdp_queues; i++) { |
7276 | struct ixgbe_ring *ring = adapter->xdp_ring[i]; | |
7277 | ||
7278 | if (ring->next_to_use != ring->next_to_clean) | |
7279 | return true; | |
7280 | } | |
7281 | ||
07923c17 ET |
7282 | return false; |
7283 | } | |
7284 | ||
7285 | static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) | |
7286 | { | |
7287 | struct ixgbe_hw *hw = &adapter->hw; | |
7288 | struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; | |
7289 | u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); | |
7290 | ||
7291 | int i, j; | |
7292 | ||
7293 | if (!adapter->num_vfs) | |
7294 | return false; | |
7295 | ||
9a75a1ac DS |
7296 | /* resetting the PF is only needed for MAC before X550 */ |
7297 | if (hw->mac.type >= ixgbe_mac_X550) | |
7298 | return false; | |
7299 | ||
07923c17 ET |
7300 | for (i = 0; i < adapter->num_vfs; i++) { |
7301 | for (j = 0; j < q_per_pool; j++) { | |
7302 | u32 h, t; | |
7303 | ||
7304 | h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); | |
7305 | t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); | |
7306 | ||
7307 | if (h != t) | |
7308 | return true; | |
7309 | } | |
7310 | } | |
7311 | ||
7312 | return false; | |
7313 | } | |
7314 | ||
93c52dd0 AD |
7315 | /** |
7316 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
49ce9c2c | 7317 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
7318 | **/ |
7319 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
7320 | { | |
93c52dd0 | 7321 | if (!netif_carrier_ok(adapter->netdev)) { |
07923c17 ET |
7322 | if (ixgbe_ring_tx_pending(adapter) || |
7323 | ixgbe_vf_tx_pending(adapter)) { | |
bc59fcda NS |
7324 | /* We've lost link, so the controller stops DMA, |
7325 | * but we've got queued Tx work that's never going | |
7326 | * to get done, so reset controller to flush Tx. | |
7327 | * (Do the reset outside of interrupt context). | |
7328 | */ | |
12ff3f3b | 7329 | e_warn(drv, "initiating reset to clear Tx work after link loss\n"); |
57ca2a4f | 7330 | set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); |
bc59fcda | 7331 | } |
c4cf55e5 | 7332 | } |
c4cf55e5 PWJ |
7333 | } |
7334 | ||
9079e416 | 7335 | #ifdef CONFIG_PCI_IOV |
9079e416 ET |
7336 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) |
7337 | { | |
7338 | struct ixgbe_hw *hw = &adapter->hw; | |
7339 | struct pci_dev *pdev = adapter->pdev; | |
988d1307 | 7340 | unsigned int vf; |
9079e416 | 7341 | u32 gpc; |
9079e416 ET |
7342 | |
7343 | if (!(netif_carrier_ok(adapter->netdev))) | |
7344 | return; | |
7345 | ||
7346 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
7347 | if (gpc) /* If incrementing then no need for the check below */ | |
7348 | return; | |
7349 | /* Check to see if a bad DMA write target from an errant or | |
7350 | * malicious VF has caused a PCIe error. If so then we can | |
7351 | * issue a VFLR to the offending VF(s) and then resume without | |
7352 | * requesting a full slot reset. | |
7353 | */ | |
7354 | ||
7355 | if (!pdev) | |
7356 | return; | |
7357 | ||
9079e416 | 7358 | /* check status reg for all VFs owned by this PF */ |
988d1307 MR |
7359 | for (vf = 0; vf < adapter->num_vfs; ++vf) { |
7360 | struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; | |
7361 | u16 status_reg; | |
9079e416 | 7362 | |
988d1307 MR |
7363 | if (!vfdev) |
7364 | continue; | |
7365 | pci_read_config_word(vfdev, PCI_STATUS, &status_reg); | |
7366 | if (status_reg != IXGBE_FAILED_READ_CFG_WORD && | |
7367 | status_reg & PCI_STATUS_REC_MASTER_ABORT) | |
63af8f7a | 7368 | pcie_flr(vfdev); |
9079e416 ET |
7369 | } |
7370 | } | |
7371 | ||
a985b6c3 GR |
7372 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
7373 | { | |
7374 | u32 ssvpc; | |
7375 | ||
0584d999 GR |
7376 | /* Do not perform spoof check for 82598 or if not in IOV mode */ |
7377 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
7378 | adapter->num_vfs == 0) | |
a985b6c3 GR |
7379 | return; |
7380 | ||
7381 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
7382 | ||
7383 | /* | |
7384 | * ssvpc register is cleared on read, if zero then no | |
7385 | * spoofed packets in the last interval. | |
7386 | */ | |
7387 | if (!ssvpc) | |
7388 | return; | |
7389 | ||
d6ea0754 | 7390 | e_warn(drv, "%u Spoofed packets detected\n", ssvpc); |
a985b6c3 | 7391 | } |
9079e416 ET |
7392 | #else |
7393 | static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) | |
7394 | { | |
7395 | } | |
7396 | ||
7397 | static void | |
7398 | ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) | |
7399 | { | |
7400 | } | |
7401 | #endif /* CONFIG_PCI_IOV */ | |
7402 | ||
a985b6c3 | 7403 | |
93c52dd0 AD |
7404 | /** |
7405 | * ixgbe_watchdog_subtask - check and bring link up | |
49ce9c2c | 7406 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
7407 | **/ |
7408 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
7409 | { | |
09f40aed | 7410 | /* if interface is down, removing or resetting, do nothing */ |
7edebf9a | 7411 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
09f40aed | 7412 | test_bit(__IXGBE_REMOVING, &adapter->state) || |
7edebf9a | 7413 | test_bit(__IXGBE_RESETTING, &adapter->state)) |
93c52dd0 AD |
7414 | return; |
7415 | ||
7416 | ixgbe_watchdog_update_link(adapter); | |
7417 | ||
7418 | if (adapter->link_up) | |
7419 | ixgbe_watchdog_link_is_up(adapter); | |
7420 | else | |
7421 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 7422 | |
9079e416 | 7423 | ixgbe_check_for_bad_vf(adapter); |
a985b6c3 | 7424 | ixgbe_spoof_check(adapter); |
9a799d71 | 7425 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
7426 | |
7427 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 7428 | } |
10eec955 | 7429 | |
cf8280ee | 7430 | /** |
7086400d | 7431 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
49ce9c2c | 7432 | * @adapter: the ixgbe adapter structure |
cf8280ee | 7433 | **/ |
7086400d | 7434 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 7435 | { |
cf8280ee | 7436 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 7437 | s32 err; |
cf8280ee | 7438 | |
7086400d AD |
7439 | /* not searching for SFP so there is nothing to do here */ |
7440 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
7441 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
7442 | return; | |
10eec955 | 7443 | |
58e7cd24 MR |
7444 | if (adapter->sfp_poll_time && |
7445 | time_after(adapter->sfp_poll_time, jiffies)) | |
7446 | return; /* If not yet time to poll for SFP */ | |
7447 | ||
7086400d AD |
7448 | /* someone else is in init, wait until next service event */ |
7449 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
7450 | return; | |
cf8280ee | 7451 | |
58e7cd24 MR |
7452 | adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; |
7453 | ||
7086400d AD |
7454 | err = hw->phy.ops.identify_sfp(hw); |
7455 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
7456 | goto sfp_out; | |
264857b8 | 7457 | |
7086400d AD |
7458 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
7459 | /* If no cable is present, then we need to reset | |
7460 | * the next time we find a good cable. */ | |
7461 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 7462 | } |
9a799d71 | 7463 | |
7086400d AD |
7464 | /* exit on error */ |
7465 | if (err) | |
7466 | goto sfp_out; | |
e8e26350 | 7467 | |
7086400d AD |
7468 | /* exit if reset not needed */ |
7469 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
7470 | goto sfp_out; | |
9a799d71 | 7471 | |
7086400d | 7472 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 7473 | |
7086400d AD |
7474 | /* |
7475 | * A module may be identified correctly, but the EEPROM may not have | |
7476 | * support for that module. setup_sfp() will fail in that case, so | |
7477 | * we should not allow that module to load. | |
7478 | */ | |
7479 | if (hw->mac.type == ixgbe_mac_82598EB) | |
7480 | err = hw->phy.ops.reset(hw); | |
7481 | else | |
7482 | err = hw->mac.ops.setup_sfp(hw); | |
7483 | ||
7484 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
7485 | goto sfp_out; | |
7486 | ||
7487 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
7488 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
7489 | ||
7490 | sfp_out: | |
7491 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
7492 | ||
7493 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
7494 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
7495 | e_dev_err("failed to initialize because an unsupported " | |
7496 | "SFP+ module type was detected.\n"); | |
7497 | e_dev_err("Reload the driver after installing a " | |
7498 | "supported module.\n"); | |
7499 | unregister_netdev(adapter->netdev); | |
bc59fcda | 7500 | } |
7086400d | 7501 | } |
bc59fcda | 7502 | |
7086400d AD |
7503 | /** |
7504 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
49ce9c2c | 7505 | * @adapter: the ixgbe adapter structure |
7086400d AD |
7506 | **/ |
7507 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
7508 | { | |
7509 | struct ixgbe_hw *hw = &adapter->hw; | |
3d292265 JH |
7510 | u32 speed; |
7511 | bool autoneg = false; | |
7086400d AD |
7512 | |
7513 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
7514 | return; | |
7515 | ||
7516 | /* someone else is in init, wait until next service event */ | |
7517 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
7518 | return; | |
7519 | ||
7520 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
7521 | ||
3d292265 | 7522 | speed = hw->phy.autoneg_advertised; |
ed33ff66 | 7523 | if ((!speed) && (hw->mac.ops.get_link_capabilities)) { |
3d292265 | 7524 | hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); |
ed33ff66 ET |
7525 | |
7526 | /* setup the highest link when no autoneg */ | |
7527 | if (!autoneg) { | |
7528 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
7529 | speed = IXGBE_LINK_SPEED_10GB_FULL; | |
7530 | } | |
7531 | } | |
7532 | ||
7086400d | 7533 | if (hw->mac.ops.setup_link) |
fd0326f2 | 7534 | hw->mac.ops.setup_link(hw, speed, true); |
7086400d AD |
7535 | |
7536 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
7537 | adapter->link_check_timeout = jiffies; | |
7538 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
7539 | } | |
7540 | ||
7541 | /** | |
7542 | * ixgbe_service_timer - Timer Call-back | |
7543 | * @data: pointer to adapter cast into an unsigned long | |
7544 | **/ | |
7545 | static void ixgbe_service_timer(unsigned long data) | |
7546 | { | |
7547 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
7548 | unsigned long next_event_offset; | |
7549 | ||
6bb78cfb AD |
7550 | /* poll faster when waiting for link */ |
7551 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
7552 | next_event_offset = HZ / 10; | |
7553 | else | |
7554 | next_event_offset = HZ * 2; | |
83c61fa9 | 7555 | |
7086400d AD |
7556 | /* Reset the timer */ |
7557 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
7558 | ||
9079e416 | 7559 | ixgbe_service_event_schedule(adapter); |
7086400d AD |
7560 | } |
7561 | ||
597f22d6 DS |
7562 | static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) |
7563 | { | |
7564 | struct ixgbe_hw *hw = &adapter->hw; | |
7565 | u32 status; | |
7566 | ||
7567 | if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) | |
7568 | return; | |
7569 | ||
7570 | adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; | |
7571 | ||
7572 | if (!hw->phy.ops.handle_lasi) | |
7573 | return; | |
7574 | ||
7575 | status = hw->phy.ops.handle_lasi(&adapter->hw); | |
7576 | if (status != IXGBE_ERR_OVERTEMP) | |
7577 | return; | |
7578 | ||
7579 | e_crit(drv, "%s\n", ixgbe_overheat_msg); | |
7580 | } | |
7581 | ||
c83c6cbd AD |
7582 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
7583 | { | |
57ca2a4f | 7584 | if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) |
c83c6cbd AD |
7585 | return; |
7586 | ||
09f40aed | 7587 | /* If we're already down, removing or resetting, just bail */ |
c83c6cbd | 7588 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
09f40aed | 7589 | test_bit(__IXGBE_REMOVING, &adapter->state) || |
c83c6cbd AD |
7590 | test_bit(__IXGBE_RESETTING, &adapter->state)) |
7591 | return; | |
7592 | ||
7593 | ixgbe_dump(adapter); | |
7594 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
7595 | adapter->tx_timeout_count++; | |
7596 | ||
8f4c5c9f | 7597 | rtnl_lock(); |
c83c6cbd | 7598 | ixgbe_reinit_locked(adapter); |
8f4c5c9f | 7599 | rtnl_unlock(); |
c83c6cbd AD |
7600 | } |
7601 | ||
7086400d AD |
7602 | /** |
7603 | * ixgbe_service_task - manages and runs subtasks | |
7604 | * @work: pointer to work_struct containing our data | |
7605 | **/ | |
7606 | static void ixgbe_service_task(struct work_struct *work) | |
7607 | { | |
7608 | struct ixgbe_adapter *adapter = container_of(work, | |
7609 | struct ixgbe_adapter, | |
7610 | service_task); | |
b0483c8f MR |
7611 | if (ixgbe_removed(adapter->hw.hw_addr)) { |
7612 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
7613 | rtnl_lock(); | |
7614 | ixgbe_down(adapter); | |
7615 | rtnl_unlock(); | |
7616 | } | |
7617 | ixgbe_service_event_complete(adapter); | |
7618 | return; | |
7619 | } | |
a21d0822 | 7620 | if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { |
b3a49557 | 7621 | rtnl_lock(); |
a21d0822 | 7622 | adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; |
b3a49557 AD |
7623 | udp_tunnel_get_rx_info(adapter->netdev); |
7624 | rtnl_unlock(); | |
67359c3c | 7625 | } |
c83c6cbd | 7626 | ixgbe_reset_subtask(adapter); |
597f22d6 | 7627 | ixgbe_phy_interrupt_subtask(adapter); |
7086400d AD |
7628 | ixgbe_sfp_detection_subtask(adapter); |
7629 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 7630 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 7631 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 7632 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 7633 | ixgbe_check_hang_subtask(adapter); |
891dc082 | 7634 | |
8fecf67c | 7635 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { |
891dc082 JK |
7636 | ixgbe_ptp_overflow_check(adapter); |
7637 | ixgbe_ptp_rx_hang(adapter); | |
7638 | } | |
7086400d AD |
7639 | |
7640 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
7641 | } |
7642 | ||
fd0db0ed AD |
7643 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
7644 | struct ixgbe_tx_buffer *first, | |
244e27ad | 7645 | u8 *hdr_len) |
897ab156 | 7646 | { |
b83e3010 | 7647 | u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; |
fd0db0ed | 7648 | struct sk_buff *skb = first->skb; |
b83e3010 AD |
7649 | union { |
7650 | struct iphdr *v4; | |
7651 | struct ipv6hdr *v6; | |
7652 | unsigned char *hdr; | |
7653 | } ip; | |
7654 | union { | |
7655 | struct tcphdr *tcp; | |
7656 | unsigned char *hdr; | |
7657 | } l4; | |
7658 | u32 paylen, l4_offset; | |
2049e1f6 | 7659 | int err; |
9a799d71 | 7660 | |
8f4fbb9b AD |
7661 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
7662 | return 0; | |
7663 | ||
897ab156 AD |
7664 | if (!skb_is_gso(skb)) |
7665 | return 0; | |
9a799d71 | 7666 | |
2049e1f6 FR |
7667 | err = skb_cow_head(skb, 0); |
7668 | if (err < 0) | |
7669 | return err; | |
9a799d71 | 7670 | |
2a20525b SP |
7671 | if (eth_p_mpls(first->protocol)) |
7672 | ip.hdr = skb_inner_network_header(skb); | |
7673 | else | |
7674 | ip.hdr = skb_network_header(skb); | |
b83e3010 AD |
7675 | l4.hdr = skb_checksum_start(skb); |
7676 | ||
897ab156 AD |
7677 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
7678 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
7679 | ||
b83e3010 AD |
7680 | /* initialize outer IP header fields */ |
7681 | if (ip.v4->version == 4) { | |
c54cdc31 AD |
7682 | unsigned char *csum_start = skb_checksum_start(skb); |
7683 | unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); | |
7684 | ||
b83e3010 AD |
7685 | /* IP header will have to cancel out any data that |
7686 | * is not a part of the outer IP header | |
7687 | */ | |
c54cdc31 AD |
7688 | ip.v4->check = csum_fold(csum_partial(trans_start, |
7689 | csum_start - trans_start, | |
7690 | 0)); | |
897ab156 | 7691 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; |
b83e3010 AD |
7692 | |
7693 | ip.v4->tot_len = 0; | |
244e27ad AD |
7694 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
7695 | IXGBE_TX_FLAGS_CSUM | | |
7696 | IXGBE_TX_FLAGS_IPV4; | |
b83e3010 AD |
7697 | } else { |
7698 | ip.v6->payload_len = 0; | |
244e27ad AD |
7699 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
7700 | IXGBE_TX_FLAGS_CSUM; | |
897ab156 AD |
7701 | } |
7702 | ||
b83e3010 AD |
7703 | /* determine offset of inner transport header */ |
7704 | l4_offset = l4.hdr - skb->data; | |
7705 | ||
7706 | /* compute length of segmentation header */ | |
7707 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
7708 | ||
7709 | /* remove payload length from inner checksum */ | |
7710 | paylen = skb->len - l4_offset; | |
7711 | csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); | |
897ab156 | 7712 | |
091a6246 AD |
7713 | /* update gso size and bytecount with header size */ |
7714 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
7715 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
7716 | ||
c44f5f51 | 7717 | /* mss_l4len_id: use 0 as index for TSO */ |
b83e3010 | 7718 | mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; |
897ab156 | 7719 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; |
897ab156 AD |
7720 | |
7721 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
b83e3010 AD |
7722 | vlan_macip_lens = l4.hdr - ip.hdr; |
7723 | vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
244e27ad | 7724 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
897ab156 AD |
7725 | |
7726 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
244e27ad | 7727 | mss_l4len_idx); |
897ab156 AD |
7728 | |
7729 | return 1; | |
7730 | } | |
7731 | ||
49763de0 AD |
7732 | static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) |
7733 | { | |
7734 | unsigned int offset = 0; | |
7735 | ||
7736 | ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); | |
7737 | ||
7738 | return offset == skb_checksum_start_offset(skb); | |
7739 | } | |
7740 | ||
244e27ad AD |
7741 | static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, |
7742 | struct ixgbe_tx_buffer *first) | |
7ca647bd | 7743 | { |
fd0db0ed | 7744 | struct sk_buff *skb = first->skb; |
897ab156 | 7745 | u32 vlan_macip_lens = 0; |
897ab156 | 7746 | u32 type_tucmd = 0; |
7ca647bd | 7747 | |
897ab156 | 7748 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
49763de0 AD |
7749 | csum_failed: |
7750 | if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | | |
7751 | IXGBE_TX_FLAGS_CC))) | |
472148c3 | 7752 | return; |
49763de0 AD |
7753 | goto no_csum; |
7754 | } | |
897ab156 | 7755 | |
49763de0 AD |
7756 | switch (skb->csum_offset) { |
7757 | case offsetof(struct tcphdr, check): | |
7758 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
7759 | /* fall through */ | |
7760 | case offsetof(struct udphdr, check): | |
7761 | break; | |
7762 | case offsetof(struct sctphdr, checksum): | |
7763 | /* validate that this is actually an SCTP request */ | |
7764 | if (((first->protocol == htons(ETH_P_IP)) && | |
7765 | (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || | |
7766 | ((first->protocol == htons(ETH_P_IPV6)) && | |
7767 | ixgbe_ipv6_csum_is_sctp(skb))) { | |
7768 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
897ab156 | 7769 | break; |
7ca647bd | 7770 | } |
49763de0 AD |
7771 | /* fall through */ |
7772 | default: | |
7773 | skb_checksum_help(skb); | |
7774 | goto csum_failed; | |
7ca647bd JP |
7775 | } |
7776 | ||
49763de0 AD |
7777 | /* update TX checksum flag */ |
7778 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7779 | vlan_macip_lens = skb_checksum_start_offset(skb) - | |
7780 | skb_network_offset(skb); | |
36a92d71 | 7781 | no_csum: |
244e27ad | 7782 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
49763de0 | 7783 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
244e27ad | 7784 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
9a799d71 | 7785 | |
49763de0 | 7786 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0); |
9a799d71 AK |
7787 | } |
7788 | ||
472148c3 AD |
7789 | #define IXGBE_SET_FLAG(_input, _flag, _result) \ |
7790 | ((_flag <= _result) ? \ | |
7791 | ((u32)(_input & _flag) * (_result / _flag)) : \ | |
7792 | ((u32)(_input & _flag) / (_flag / _result))) | |
7793 | ||
7794 | static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) | |
9a799d71 | 7795 | { |
d3d00239 | 7796 | /* set type for advanced descriptor with frame checksum insertion */ |
472148c3 AD |
7797 | u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | |
7798 | IXGBE_ADVTXD_DCMD_DEXT | | |
7799 | IXGBE_ADVTXD_DCMD_IFCS; | |
9a799d71 | 7800 | |
d3d00239 | 7801 | /* set HW vlan bit if vlan is present */ |
472148c3 AD |
7802 | cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, |
7803 | IXGBE_ADVTXD_DCMD_VLE); | |
3a6a4eda | 7804 | |
d3d00239 | 7805 | /* set segmentation enable bits for TSO/FSO */ |
472148c3 AD |
7806 | cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, |
7807 | IXGBE_ADVTXD_DCMD_TSE); | |
7808 | ||
7809 | /* set timestamp bit if present */ | |
7810 | cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, | |
7811 | IXGBE_ADVTXD_MAC_TSTAMP); | |
eacd73f7 | 7812 | |
62748b7b | 7813 | /* insert frame checksum */ |
472148c3 | 7814 | cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); |
62748b7b | 7815 | |
d3d00239 AD |
7816 | return cmd_type; |
7817 | } | |
9a799d71 | 7818 | |
729739b7 AD |
7819 | static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
7820 | u32 tx_flags, unsigned int paylen) | |
d3d00239 | 7821 | { |
472148c3 | 7822 | u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; |
9a799d71 | 7823 | |
d3d00239 | 7824 | /* enable L4 checksum for TSO and TX checksum offload */ |
472148c3 AD |
7825 | olinfo_status |= IXGBE_SET_FLAG(tx_flags, |
7826 | IXGBE_TX_FLAGS_CSUM, | |
7827 | IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 7828 | |
93f5b3c1 | 7829 | /* enble IPv4 checksum for TSO */ |
472148c3 AD |
7830 | olinfo_status |= IXGBE_SET_FLAG(tx_flags, |
7831 | IXGBE_TX_FLAGS_IPV4, | |
7832 | IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 7833 | |
7f9643fd AD |
7834 | /* |
7835 | * Check Context must be set if Tx switch is enabled, which it | |
7836 | * always is for case where virtual functions are running | |
7837 | */ | |
472148c3 AD |
7838 | olinfo_status |= IXGBE_SET_FLAG(tx_flags, |
7839 | IXGBE_TX_FLAGS_CC, | |
7840 | IXGBE_ADVTXD_CC); | |
7f9643fd | 7841 | |
472148c3 | 7842 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
d3d00239 | 7843 | } |
44df32c5 | 7844 | |
2367a173 DB |
7845 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
7846 | { | |
7847 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
7848 | ||
7849 | /* Herbert's original patch had: | |
7850 | * smp_mb__after_netif_stop_queue(); | |
7851 | * but since that doesn't exist yet, just open code it. | |
7852 | */ | |
7853 | smp_mb(); | |
7854 | ||
7855 | /* We need to check again in a case another CPU has just | |
7856 | * made room available. | |
7857 | */ | |
7858 | if (likely(ixgbe_desc_unused(tx_ring) < size)) | |
7859 | return -EBUSY; | |
7860 | ||
7861 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
7862 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
7863 | ++tx_ring->tx_stats.restart_queue; | |
7864 | return 0; | |
7865 | } | |
7866 | ||
7867 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) | |
7868 | { | |
7869 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) | |
7870 | return 0; | |
7871 | ||
7872 | return __ixgbe_maybe_stop_tx(tx_ring, size); | |
7873 | } | |
7874 | ||
d3d00239 AD |
7875 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
7876 | IXGBE_TXD_CMD_RS) | |
7877 | ||
7878 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 | 7879 | struct ixgbe_tx_buffer *first, |
d3d00239 AD |
7880 | const u8 hdr_len) |
7881 | { | |
fd0db0ed | 7882 | struct sk_buff *skb = first->skb; |
729739b7 | 7883 | struct ixgbe_tx_buffer *tx_buffer; |
d3d00239 | 7884 | union ixgbe_adv_tx_desc *tx_desc; |
ec718254 AD |
7885 | struct skb_frag_struct *frag; |
7886 | dma_addr_t dma; | |
7887 | unsigned int data_len, size; | |
244e27ad | 7888 | u32 tx_flags = first->tx_flags; |
472148c3 | 7889 | u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); |
d3d00239 | 7890 | u16 i = tx_ring->next_to_use; |
d3d00239 | 7891 | |
729739b7 AD |
7892 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
7893 | ||
ec718254 AD |
7894 | ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); |
7895 | ||
7896 | size = skb_headlen(skb); | |
7897 | data_len = skb->data_len; | |
729739b7 | 7898 | |
d3d00239 AD |
7899 | #ifdef IXGBE_FCOE |
7900 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
729739b7 | 7901 | if (data_len < sizeof(struct fcoe_crc_eof)) { |
d3d00239 AD |
7902 | size -= sizeof(struct fcoe_crc_eof) - data_len; |
7903 | data_len = 0; | |
729739b7 AD |
7904 | } else { |
7905 | data_len -= sizeof(struct fcoe_crc_eof); | |
9a799d71 AK |
7906 | } |
7907 | } | |
44df32c5 | 7908 | |
d3d00239 | 7909 | #endif |
729739b7 | 7910 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
8ad494b0 | 7911 | |
ec718254 | 7912 | tx_buffer = first; |
9a799d71 | 7913 | |
ec718254 AD |
7914 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { |
7915 | if (dma_mapping_error(tx_ring->dev, dma)) | |
7916 | goto dma_error; | |
7917 | ||
7918 | /* record length, and DMA address */ | |
7919 | dma_unmap_len_set(tx_buffer, len, size); | |
7920 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
7921 | ||
7922 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
e5a43549 | 7923 | |
729739b7 | 7924 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
d3d00239 | 7925 | tx_desc->read.cmd_type_len = |
472148c3 | 7926 | cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); |
e5a43549 | 7927 | |
d3d00239 | 7928 | i++; |
729739b7 | 7929 | tx_desc++; |
d3d00239 | 7930 | if (i == tx_ring->count) { |
e4f74028 | 7931 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
7932 | i = 0; |
7933 | } | |
ec718254 | 7934 | tx_desc->read.olinfo_status = 0; |
729739b7 AD |
7935 | |
7936 | dma += IXGBE_MAX_DATA_PER_TXD; | |
7937 | size -= IXGBE_MAX_DATA_PER_TXD; | |
7938 | ||
7939 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
d3d00239 | 7940 | } |
e5a43549 | 7941 | |
729739b7 AD |
7942 | if (likely(!data_len)) |
7943 | break; | |
9a799d71 | 7944 | |
472148c3 | 7945 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); |
9a799d71 | 7946 | |
729739b7 AD |
7947 | i++; |
7948 | tx_desc++; | |
7949 | if (i == tx_ring->count) { | |
7950 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
7951 | i = 0; | |
7952 | } | |
ec718254 | 7953 | tx_desc->read.olinfo_status = 0; |
9a799d71 | 7954 | |
d3d00239 | 7955 | #ifdef IXGBE_FCOE |
9e903e08 | 7956 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 7957 | #else |
9e903e08 | 7958 | size = skb_frag_size(frag); |
d3d00239 AD |
7959 | #endif |
7960 | data_len -= size; | |
9a799d71 | 7961 | |
729739b7 AD |
7962 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
7963 | DMA_TO_DEVICE); | |
9a799d71 | 7964 | |
729739b7 | 7965 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
729739b7 | 7966 | } |
9a799d71 | 7967 | |
729739b7 | 7968 | /* write last descriptor with RS and EOP bits */ |
472148c3 AD |
7969 | cmd_type |= size | IXGBE_TXD_CMD; |
7970 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); | |
eacd73f7 | 7971 | |
091a6246 | 7972 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
b2d96e0a | 7973 | |
d3d00239 AD |
7974 | /* set the timestamp */ |
7975 | first->time_stamp = jiffies; | |
9a799d71 AK |
7976 | |
7977 | /* | |
729739b7 AD |
7978 | * Force memory writes to complete before letting h/w know there |
7979 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
7980 | * memory model archs, such as IA-64). | |
7981 | * | |
7982 | * We also need this memory barrier to make certain all of the | |
7983 | * status bits have been updated before next_to_watch is written. | |
9a799d71 AK |
7984 | */ |
7985 | wmb(); | |
7986 | ||
d3d00239 AD |
7987 | /* set next_to_watch value indicating a packet is present */ |
7988 | first->next_to_watch = tx_desc; | |
7989 | ||
729739b7 AD |
7990 | i++; |
7991 | if (i == tx_ring->count) | |
7992 | i = 0; | |
7993 | ||
7994 | tx_ring->next_to_use = i; | |
7995 | ||
2367a173 DB |
7996 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); |
7997 | ||
7998 | if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { | |
ad435ec6 AD |
7999 | writel(i, tx_ring->tail); |
8000 | ||
8001 | /* we need this if more than one processor can write to our tail | |
8002 | * at a time, it synchronizes IO on IA64/Altix systems | |
8003 | */ | |
8004 | mmiowb(); | |
9c938cdd | 8005 | } |
2367a173 | 8006 | |
d3d00239 AD |
8007 | return; |
8008 | dma_error: | |
729739b7 | 8009 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
ffed21bc | 8010 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
d3d00239 AD |
8011 | |
8012 | /* clear dma mappings for failed tx_buffer_info map */ | |
ffed21bc AD |
8013 | while (tx_buffer != first) { |
8014 | if (dma_unmap_len(tx_buffer, len)) | |
8015 | dma_unmap_page(tx_ring->dev, | |
8016 | dma_unmap_addr(tx_buffer, dma), | |
8017 | dma_unmap_len(tx_buffer, len), | |
8018 | DMA_TO_DEVICE); | |
8019 | dma_unmap_len_set(tx_buffer, len, 0); | |
8020 | ||
8021 | if (i--) | |
8022 | i += tx_ring->count; | |
729739b7 | 8023 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
d3d00239 AD |
8024 | } |
8025 | ||
ffed21bc AD |
8026 | if (dma_unmap_len(tx_buffer, len)) |
8027 | dma_unmap_single(tx_ring->dev, | |
8028 | dma_unmap_addr(tx_buffer, dma), | |
8029 | dma_unmap_len(tx_buffer, len), | |
8030 | DMA_TO_DEVICE); | |
8031 | dma_unmap_len_set(tx_buffer, len, 0); | |
8032 | ||
8033 | dev_kfree_skb_any(first->skb); | |
8034 | first->skb = NULL; | |
8035 | ||
d3d00239 | 8036 | tx_ring->next_to_use = i; |
9a799d71 AK |
8037 | } |
8038 | ||
fd0db0ed | 8039 | static void ixgbe_atr(struct ixgbe_ring *ring, |
244e27ad | 8040 | struct ixgbe_tx_buffer *first) |
69830529 AD |
8041 | { |
8042 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
8043 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
8044 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
8045 | union { | |
8046 | unsigned char *network; | |
8047 | struct iphdr *ipv4; | |
8048 | struct ipv6hdr *ipv6; | |
8049 | } hdr; | |
ee9e0f0b | 8050 | struct tcphdr *th; |
e2873d43 | 8051 | unsigned int hlen; |
67359c3c | 8052 | struct sk_buff *skb; |
905e4a41 | 8053 | __be16 vlan_id; |
e2873d43 | 8054 | int l4_proto; |
c4cf55e5 | 8055 | |
69830529 AD |
8056 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
8057 | if (!q_vector) | |
8058 | return; | |
8059 | ||
8060 | /* do nothing if sampling is disabled */ | |
8061 | if (!ring->atr_sample_rate) | |
d3ead241 | 8062 | return; |
c4cf55e5 | 8063 | |
69830529 | 8064 | ring->atr_count++; |
c4cf55e5 | 8065 | |
e2873d43 AD |
8066 | /* currently only IPv4/IPv6 with TCP is supported */ |
8067 | if ((first->protocol != htons(ETH_P_IP)) && | |
8068 | (first->protocol != htons(ETH_P_IPV6))) | |
8069 | return; | |
8070 | ||
69830529 | 8071 | /* snag network header to get L4 type and address */ |
67359c3c MR |
8072 | skb = first->skb; |
8073 | hdr.network = skb_network_header(skb); | |
9f3c7504 SV |
8074 | if (unlikely(hdr.network <= skb->data)) |
8075 | return; | |
9f12df90 AD |
8076 | if (skb->encapsulation && |
8077 | first->protocol == htons(ETH_P_IP) && | |
52028821 | 8078 | hdr.ipv4->protocol == IPPROTO_UDP) { |
67359c3c | 8079 | struct ixgbe_adapter *adapter = q_vector->adapter; |
69830529 | 8080 | |
9f3c7504 SV |
8081 | if (unlikely(skb_tail_pointer(skb) < hdr.network + |
8082 | VXLAN_HEADROOM)) | |
8083 | return; | |
8084 | ||
9f12df90 AD |
8085 | /* verify the port is recognized as VXLAN */ |
8086 | if (adapter->vxlan_port && | |
e2873d43 | 8087 | udp_hdr(skb)->dest == adapter->vxlan_port) |
9f12df90 | 8088 | hdr.network = skb_inner_network_header(skb); |
a21d0822 ET |
8089 | |
8090 | if (adapter->geneve_port && | |
8091 | udp_hdr(skb)->dest == adapter->geneve_port) | |
8092 | hdr.network = skb_inner_network_header(skb); | |
e19dcdeb MR |
8093 | } |
8094 | ||
9f3c7504 SV |
8095 | /* Make sure we have at least [minimum IPv4 header + TCP] |
8096 | * or [IPv6 header] bytes | |
8097 | */ | |
8098 | if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) | |
8099 | return; | |
8100 | ||
e19dcdeb MR |
8101 | /* Currently only IPv4/IPv6 with TCP is supported */ |
8102 | switch (hdr.ipv4->version) { | |
8103 | case IPVERSION: | |
e2873d43 AD |
8104 | /* access ihl as u8 to avoid unaligned access on ia64 */ |
8105 | hlen = (hdr.network[0] & 0x0F) << 2; | |
8106 | l4_proto = hdr.ipv4->protocol; | |
e19dcdeb MR |
8107 | break; |
8108 | case 6: | |
e2873d43 AD |
8109 | hlen = hdr.network - skb->data; |
8110 | l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); | |
8111 | hlen -= hdr.network - skb->data; | |
e19dcdeb MR |
8112 | break; |
8113 | default: | |
8114 | return; | |
67359c3c | 8115 | } |
c4cf55e5 | 8116 | |
e2873d43 AD |
8117 | if (l4_proto != IPPROTO_TCP) |
8118 | return; | |
8119 | ||
9f3c7504 SV |
8120 | if (unlikely(skb_tail_pointer(skb) < hdr.network + |
8121 | hlen + sizeof(struct tcphdr))) | |
8122 | return; | |
8123 | ||
e2873d43 AD |
8124 | th = (struct tcphdr *)(hdr.network + hlen); |
8125 | ||
8126 | /* skip this packet since the socket is closing */ | |
8127 | if (th->fin) | |
69830529 AD |
8128 | return; |
8129 | ||
8130 | /* sample on all syn packets or once every atr sample count */ | |
8131 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
8132 | return; | |
8133 | ||
8134 | /* reset sample count */ | |
8135 | ring->atr_count = 0; | |
8136 | ||
244e27ad | 8137 | vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); |
69830529 AD |
8138 | |
8139 | /* | |
8140 | * src and dst are inverted, think how the receiver sees them | |
8141 | * | |
8142 | * The input is broken into two sections, a non-compressed section | |
8143 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
8144 | * is XORed together and stored in the compressed dword. | |
8145 | */ | |
8146 | input.formatted.vlan_id = vlan_id; | |
8147 | ||
8148 | /* | |
8149 | * since src port and flex bytes occupy the same word XOR them together | |
8150 | * and write the value to source port portion of compressed dword | |
8151 | */ | |
244e27ad | 8152 | if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
a1108ffd | 8153 | common.port.src ^= th->dest ^ htons(ETH_P_8021Q); |
69830529 | 8154 | else |
244e27ad | 8155 | common.port.src ^= th->dest ^ first->protocol; |
69830529 AD |
8156 | common.port.dst ^= th->source; |
8157 | ||
e19dcdeb MR |
8158 | switch (hdr.ipv4->version) { |
8159 | case IPVERSION: | |
69830529 AD |
8160 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; |
8161 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
e19dcdeb MR |
8162 | break; |
8163 | case 6: | |
69830529 AD |
8164 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; |
8165 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
8166 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
8167 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
8168 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
8169 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
8170 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
8171 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
8172 | hdr.ipv6->daddr.s6_addr32[3]; | |
e19dcdeb MR |
8173 | break; |
8174 | default: | |
8175 | break; | |
69830529 | 8176 | } |
c4cf55e5 | 8177 | |
9f12df90 | 8178 | if (hdr.network != skb_network_header(skb)) |
67359c3c | 8179 | input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; |
67359c3c | 8180 | |
c4cf55e5 | 8181 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ |
69830529 AD |
8182 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
8183 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
8184 | } |
8185 | ||
f663dd9a | 8186 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 8187 | void *accel_priv, select_queue_fallback_t fallback) |
09a3b1f8 | 8188 | { |
f663dd9a JW |
8189 | struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; |
8190 | #ifdef IXGBE_FCOE | |
97488bd1 AD |
8191 | struct ixgbe_adapter *adapter; |
8192 | struct ixgbe_ring_feature *f; | |
8193 | int txq; | |
f663dd9a JW |
8194 | #endif |
8195 | ||
8196 | if (fwd_adapter) | |
8197 | return skb->queue_mapping + fwd_adapter->tx_base_queue; | |
8198 | ||
8199 | #ifdef IXGBE_FCOE | |
5e09a105 | 8200 | |
97488bd1 AD |
8201 | /* |
8202 | * only execute the code below if protocol is FCoE | |
8203 | * or FIP and we have FCoE enabled on the adapter | |
8204 | */ | |
8205 | switch (vlan_get_protocol(skb)) { | |
a1108ffd JP |
8206 | case htons(ETH_P_FCOE): |
8207 | case htons(ETH_P_FIP): | |
97488bd1 | 8208 | adapter = netdev_priv(dev); |
c087663e | 8209 | |
97488bd1 AD |
8210 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) |
8211 | break; | |
93df9465 | 8212 | /* fall through */ |
97488bd1 | 8213 | default: |
99932d4f | 8214 | return fallback(dev, skb); |
97488bd1 | 8215 | } |
c087663e | 8216 | |
97488bd1 | 8217 | f = &adapter->ring_feature[RING_F_FCOE]; |
c087663e | 8218 | |
97488bd1 AD |
8219 | txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
8220 | smp_processor_id(); | |
56075a98 | 8221 | |
97488bd1 AD |
8222 | while (txq >= f->indices) |
8223 | txq -= f->indices; | |
c4cf55e5 | 8224 | |
97488bd1 | 8225 | return txq + f->offset; |
f663dd9a | 8226 | #else |
99932d4f | 8227 | return fallback(dev, skb); |
f663dd9a | 8228 | #endif |
09a3b1f8 SH |
8229 | } |
8230 | ||
33fdc82f JF |
8231 | static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, |
8232 | struct xdp_buff *xdp) | |
8233 | { | |
8234 | struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; | |
8235 | struct ixgbe_tx_buffer *tx_buffer; | |
8236 | union ixgbe_adv_tx_desc *tx_desc; | |
8237 | u32 len, cmd_type; | |
8238 | dma_addr_t dma; | |
8239 | u16 i; | |
8240 | ||
8241 | len = xdp->data_end - xdp->data; | |
8242 | ||
8243 | if (unlikely(!ixgbe_desc_unused(ring))) | |
8244 | return IXGBE_XDP_CONSUMED; | |
8245 | ||
8246 | dma = dma_map_single(ring->dev, xdp->data, len, DMA_TO_DEVICE); | |
8247 | if (dma_mapping_error(ring->dev, dma)) | |
8248 | return IXGBE_XDP_CONSUMED; | |
8249 | ||
8250 | /* record the location of the first descriptor for this packet */ | |
8251 | tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; | |
8252 | tx_buffer->bytecount = len; | |
8253 | tx_buffer->gso_segs = 1; | |
8254 | tx_buffer->protocol = 0; | |
8255 | ||
8256 | i = ring->next_to_use; | |
8257 | tx_desc = IXGBE_TX_DESC(ring, i); | |
8258 | ||
8259 | dma_unmap_len_set(tx_buffer, len, len); | |
8260 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
8261 | tx_buffer->data = xdp->data; | |
8262 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
8263 | ||
8264 | /* put descriptor type bits */ | |
8265 | cmd_type = IXGBE_ADVTXD_DTYP_DATA | | |
8266 | IXGBE_ADVTXD_DCMD_DEXT | | |
8267 | IXGBE_ADVTXD_DCMD_IFCS; | |
8268 | cmd_type |= len | IXGBE_TXD_CMD; | |
8269 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); | |
8270 | tx_desc->read.olinfo_status = | |
8271 | cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); | |
8272 | ||
7379f97a JF |
8273 | /* Avoid any potential race with xdp_xmit and cleanup */ |
8274 | smp_wmb(); | |
33fdc82f JF |
8275 | |
8276 | /* set next_to_watch value indicating a packet is present */ | |
8277 | i++; | |
8278 | if (i == ring->count) | |
8279 | i = 0; | |
8280 | ||
8281 | tx_buffer->next_to_watch = tx_desc; | |
8282 | ring->next_to_use = i; | |
8283 | ||
33fdc82f JF |
8284 | return IXGBE_XDP_TX; |
8285 | } | |
8286 | ||
fc77dc3c | 8287 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
8288 | struct ixgbe_adapter *adapter, |
8289 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 8290 | { |
d3d00239 | 8291 | struct ixgbe_tx_buffer *first; |
5f715823 | 8292 | int tso; |
d3d00239 | 8293 | u32 tx_flags = 0; |
a535c30e | 8294 | unsigned short f; |
a535c30e | 8295 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 8296 | __be16 protocol = skb->protocol; |
63544e9c | 8297 | u8 hdr_len = 0; |
5e09a105 | 8298 | |
a535c30e AD |
8299 | /* |
8300 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 8301 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
8302 | * + 2 desc gap to keep tail from touching head, |
8303 | * + 1 desc for context descriptor, | |
8304 | * otherwise try next time | |
8305 | */ | |
a535c30e AD |
8306 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) |
8307 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
7f66162b | 8308 | |
a535c30e AD |
8309 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { |
8310 | tx_ring->tx_stats.tx_busy++; | |
8311 | return NETDEV_TX_BUSY; | |
8312 | } | |
8313 | ||
fd0db0ed AD |
8314 | /* record the location of the first descriptor for this packet */ |
8315 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
8316 | first->skb = skb; | |
091a6246 AD |
8317 | first->bytecount = skb->len; |
8318 | first->gso_segs = 1; | |
fd0db0ed | 8319 | |
66f32a8b | 8320 | /* if we have a HW VLAN tag being added default to the HW one */ |
df8a39de JP |
8321 | if (skb_vlan_tag_present(skb)) { |
8322 | tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
8323 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; |
8324 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
a1108ffd | 8325 | } else if (protocol == htons(ETH_P_8021Q)) { |
66f32a8b AD |
8326 | struct vlan_hdr *vhdr, _vhdr; |
8327 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
8328 | if (!vhdr) | |
8329 | goto out_drop; | |
8330 | ||
9e0c5648 AD |
8331 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
8332 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
8333 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
8334 | } | |
0213668f | 8335 | protocol = vlan_get_protocol(skb); |
66f32a8b | 8336 | |
d5234933 MR |
8337 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
8338 | adapter->ptp_clock && | |
8339 | !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, | |
8340 | &adapter->state)) { | |
3a6a4eda JK |
8341 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
8342 | tx_flags |= IXGBE_TX_FLAGS_TSTAMP; | |
891dc082 JK |
8343 | |
8344 | /* schedule check for Tx timestamp */ | |
8345 | adapter->ptp_tx_skb = skb_get(skb); | |
8346 | adapter->ptp_tx_start = jiffies; | |
8347 | schedule_work(&adapter->ptp_tx_work); | |
3a6a4eda | 8348 | } |
3a6a4eda | 8349 | |
ff29a86e JK |
8350 | skb_tx_timestamp(skb); |
8351 | ||
9e0c5648 AD |
8352 | #ifdef CONFIG_PCI_IOV |
8353 | /* | |
8354 | * Use the l2switch_enable flag - would be false if the DMA | |
8355 | * Tx switch had been disabled. | |
8356 | */ | |
8357 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
472148c3 | 8358 | tx_flags |= IXGBE_TX_FLAGS_CC; |
9e0c5648 AD |
8359 | |
8360 | #endif | |
32701dc2 | 8361 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 8362 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
8363 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
8364 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 8365 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
8366 | tx_flags |= (skb->priority & 0x7) << |
8367 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
8368 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
8369 | struct vlan_ethhdr *vhdr; | |
2049e1f6 FR |
8370 | |
8371 | if (skb_cow_head(skb, 0)) | |
66f32a8b AD |
8372 | goto out_drop; |
8373 | vhdr = (struct vlan_ethhdr *)skb->data; | |
8374 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
8375 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
8376 | } else { | |
8377 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 8378 | } |
9a799d71 | 8379 | } |
eacd73f7 | 8380 | |
244e27ad AD |
8381 | /* record initial flags and protocol */ |
8382 | first->tx_flags = tx_flags; | |
8383 | first->protocol = protocol; | |
8384 | ||
eacd73f7 | 8385 | #ifdef IXGBE_FCOE |
66f32a8b | 8386 | /* setup tx offload for FCoE */ |
a1108ffd | 8387 | if ((protocol == htons(ETH_P_FCOE)) && |
a58915c7 | 8388 | (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { |
244e27ad | 8389 | tso = ixgbe_fso(tx_ring, first, &hdr_len); |
897ab156 AD |
8390 | if (tso < 0) |
8391 | goto out_drop; | |
9a799d71 | 8392 | |
66f32a8b | 8393 | goto xmit_fcoe; |
eacd73f7 | 8394 | } |
9a799d71 | 8395 | |
66f32a8b | 8396 | #endif /* IXGBE_FCOE */ |
244e27ad | 8397 | tso = ixgbe_tso(tx_ring, first, &hdr_len); |
66f32a8b | 8398 | if (tso < 0) |
897ab156 | 8399 | goto out_drop; |
244e27ad AD |
8400 | else if (!tso) |
8401 | ixgbe_tx_csum(tx_ring, first); | |
66f32a8b AD |
8402 | |
8403 | /* add the ATR filter if ATR is on */ | |
8404 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
244e27ad | 8405 | ixgbe_atr(tx_ring, first); |
66f32a8b AD |
8406 | |
8407 | #ifdef IXGBE_FCOE | |
8408 | xmit_fcoe: | |
8409 | #endif /* IXGBE_FCOE */ | |
244e27ad | 8410 | ixgbe_tx_map(tx_ring, first, hdr_len); |
d3d00239 | 8411 | |
9a799d71 | 8412 | return NETDEV_TX_OK; |
897ab156 AD |
8413 | |
8414 | out_drop: | |
fd0db0ed AD |
8415 | dev_kfree_skb_any(first->skb); |
8416 | first->skb = NULL; | |
8417 | ||
897ab156 | 8418 | return NETDEV_TX_OK; |
9a799d71 AK |
8419 | } |
8420 | ||
2a47fa45 JF |
8421 | static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, |
8422 | struct net_device *netdev, | |
8423 | struct ixgbe_ring *ring) | |
84418e3b AD |
8424 | { |
8425 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8426 | struct ixgbe_ring *tx_ring; | |
8427 | ||
a50c29dd AD |
8428 | /* |
8429 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
8430 | * in order to meet this minimum size requirement. | |
8431 | */ | |
a94d9e22 AD |
8432 | if (skb_put_padto(skb, 17)) |
8433 | return NETDEV_TX_OK; | |
a50c29dd | 8434 | |
2a47fa45 JF |
8435 | tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; |
8436 | ||
fc77dc3c | 8437 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
8438 | } |
8439 | ||
2a47fa45 JF |
8440 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
8441 | struct net_device *netdev) | |
8442 | { | |
8443 | return __ixgbe_xmit_frame(skb, netdev, NULL); | |
8444 | } | |
8445 | ||
9a799d71 AK |
8446 | /** |
8447 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
8448 | * @netdev: network interface device structure | |
8449 | * @p: pointer to an address structure | |
8450 | * | |
8451 | * Returns 0 on success, negative on failure | |
8452 | **/ | |
8453 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
8454 | { | |
8455 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 8456 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
8457 | struct sockaddr *addr = p; |
8458 | ||
8459 | if (!is_valid_ether_addr(addr->sa_data)) | |
8460 | return -EADDRNOTAVAIL; | |
8461 | ||
8462 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 8463 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 8464 | |
c9f53e63 AD |
8465 | ixgbe_mac_set_default_filter(adapter); |
8466 | ||
8467 | return 0; | |
9a799d71 AK |
8468 | } |
8469 | ||
6b73e10d BH |
8470 | static int |
8471 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
8472 | { | |
8473 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8474 | struct ixgbe_hw *hw = &adapter->hw; | |
8475 | u16 value; | |
8476 | int rc; | |
8477 | ||
8478 | if (prtad != hw->phy.mdio.prtad) | |
8479 | return -EINVAL; | |
8480 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
8481 | if (!rc) | |
8482 | rc = value; | |
8483 | return rc; | |
8484 | } | |
8485 | ||
8486 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
8487 | u16 addr, u16 value) | |
8488 | { | |
8489 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8490 | struct ixgbe_hw *hw = &adapter->hw; | |
8491 | ||
8492 | if (prtad != hw->phy.mdio.prtad) | |
8493 | return -EINVAL; | |
8494 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
8495 | } | |
8496 | ||
8497 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
8498 | { | |
8499 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8500 | ||
3a6a4eda | 8501 | switch (cmd) { |
3a6a4eda | 8502 | case SIOCSHWTSTAMP: |
93501d48 JK |
8503 | return ixgbe_ptp_set_ts_config(adapter, req); |
8504 | case SIOCGHWTSTAMP: | |
8505 | return ixgbe_ptp_get_ts_config(adapter, req); | |
3a6a4eda JK |
8506 | default: |
8507 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
8508 | } | |
6b73e10d BH |
8509 | } |
8510 | ||
0365e6e4 PW |
8511 | /** |
8512 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 8513 | * netdev->dev_addrs |
0365e6e4 PW |
8514 | * @netdev: network interface device structure |
8515 | * | |
8516 | * Returns non-zero on failure | |
8517 | **/ | |
8518 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
8519 | { | |
8520 | int err = 0; | |
8521 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7fa7c9dc | 8522 | struct ixgbe_hw *hw = &adapter->hw; |
0365e6e4 | 8523 | |
7fa7c9dc | 8524 | if (is_valid_ether_addr(hw->mac.san_addr)) { |
0365e6e4 | 8525 | rtnl_lock(); |
7fa7c9dc | 8526 | err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); |
0365e6e4 | 8527 | rtnl_unlock(); |
7fa7c9dc AD |
8528 | |
8529 | /* update SAN MAC vmdq pool selection */ | |
8530 | hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); | |
0365e6e4 PW |
8531 | } |
8532 | return err; | |
8533 | } | |
8534 | ||
8535 | /** | |
8536 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 8537 | * netdev->dev_addrs |
0365e6e4 PW |
8538 | * @netdev: network interface device structure |
8539 | * | |
8540 | * Returns non-zero on failure | |
8541 | **/ | |
8542 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
8543 | { | |
8544 | int err = 0; | |
8545 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
8546 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
8547 | ||
8548 | if (is_valid_ether_addr(mac->san_addr)) { | |
8549 | rtnl_lock(); | |
8550 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
8551 | rtnl_unlock(); | |
8552 | } | |
8553 | return err; | |
8554 | } | |
8555 | ||
9a799d71 AK |
8556 | #ifdef CONFIG_NET_POLL_CONTROLLER |
8557 | /* | |
8558 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
8559 | * without having to re-enable interrupts. It's not called while | |
8560 | * the interrupt routine is executing. | |
8561 | */ | |
8562 | static void ixgbe_netpoll(struct net_device *netdev) | |
8563 | { | |
8564 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 8565 | int i; |
9a799d71 | 8566 | |
1a647bd2 AD |
8567 | /* if interface is down do nothing */ |
8568 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
8569 | return; | |
8570 | ||
856f606e AD |
8571 | /* loop through and schedule all active queues */ |
8572 | for (i = 0; i < adapter->num_q_vectors; i++) | |
8573 | ixgbe_msix_clean_rings(0, adapter->q_vector[i]); | |
9a799d71 | 8574 | } |
9a799d71 | 8575 | |
581330ba | 8576 | #endif |
bc1f4470 | 8577 | |
33fdc82f JF |
8578 | static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, |
8579 | struct ixgbe_ring *ring) | |
8580 | { | |
8581 | u64 bytes, packets; | |
8582 | unsigned int start; | |
8583 | ||
8584 | if (ring) { | |
8585 | do { | |
8586 | start = u64_stats_fetch_begin_irq(&ring->syncp); | |
8587 | packets = ring->stats.packets; | |
8588 | bytes = ring->stats.bytes; | |
8589 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); | |
8590 | stats->tx_packets += packets; | |
8591 | stats->tx_bytes += bytes; | |
8592 | } | |
8593 | } | |
8594 | ||
bc1f4470 | 8595 | static void ixgbe_get_stats64(struct net_device *netdev, |
8596 | struct rtnl_link_stats64 *stats) | |
de1036b1 ED |
8597 | { |
8598 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8599 | int i; | |
8600 | ||
1a51502b | 8601 | rcu_read_lock(); |
de1036b1 | 8602 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 8603 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
8604 | u64 bytes, packets; |
8605 | unsigned int start; | |
8606 | ||
1a51502b ED |
8607 | if (ring) { |
8608 | do { | |
57a7744e | 8609 | start = u64_stats_fetch_begin_irq(&ring->syncp); |
1a51502b ED |
8610 | packets = ring->stats.packets; |
8611 | bytes = ring->stats.bytes; | |
57a7744e | 8612 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); |
1a51502b ED |
8613 | stats->rx_packets += packets; |
8614 | stats->rx_bytes += bytes; | |
8615 | } | |
de1036b1 | 8616 | } |
1ac9ad13 ED |
8617 | |
8618 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
8619 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
1ac9ad13 | 8620 | |
33fdc82f JF |
8621 | ixgbe_get_ring_stats64(stats, ring); |
8622 | } | |
8623 | for (i = 0; i < adapter->num_xdp_queues; i++) { | |
8624 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->xdp_ring[i]); | |
8625 | ||
8626 | ixgbe_get_ring_stats64(stats, ring); | |
1ac9ad13 | 8627 | } |
1a51502b | 8628 | rcu_read_unlock(); |
bc1f4470 | 8629 | |
de1036b1 ED |
8630 | /* following stats updated by ixgbe_watchdog_task() */ |
8631 | stats->multicast = netdev->stats.multicast; | |
8632 | stats->rx_errors = netdev->stats.rx_errors; | |
8633 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
8634 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
8635 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
de1036b1 ED |
8636 | } |
8637 | ||
8af3c33f | 8638 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c BH |
8639 | /** |
8640 | * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. | |
8641 | * @adapter: pointer to ixgbe_adapter | |
8b1c0b24 JF |
8642 | * @tc: number of traffic classes currently enabled |
8643 | * | |
8644 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
8645 | * 802.1Q priority maps to a packet buffer that exists. | |
8646 | */ | |
8647 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
8648 | { | |
8649 | struct ixgbe_hw *hw = &adapter->hw; | |
8650 | u32 reg, rsave; | |
8651 | int i; | |
8652 | ||
8653 | /* 82598 have a static priority to TC mapping that can not | |
8654 | * be changed so no validation is needed. | |
8655 | */ | |
8656 | if (hw->mac.type == ixgbe_mac_82598EB) | |
8657 | return; | |
8658 | ||
8659 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
8660 | rsave = reg; | |
8661 | ||
8662 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
8663 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
8664 | ||
8665 | /* If up2tc is out of bounds default to zero */ | |
8666 | if (up2tc > tc) | |
8667 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
8668 | } | |
8669 | ||
8670 | if (reg != rsave) | |
8671 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
8672 | ||
8673 | return; | |
8674 | } | |
8675 | ||
02debdc9 AD |
8676 | /** |
8677 | * ixgbe_set_prio_tc_map - Configure netdev prio tc map | |
8678 | * @adapter: Pointer to adapter struct | |
8679 | * | |
8680 | * Populate the netdev user priority to tc map | |
8681 | */ | |
8682 | static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) | |
8683 | { | |
8684 | struct net_device *dev = adapter->netdev; | |
8685 | struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; | |
8686 | struct ieee_ets *ets = adapter->ixgbe_ieee_ets; | |
8687 | u8 prio; | |
8688 | ||
8689 | for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { | |
8690 | u8 tc = 0; | |
8691 | ||
8692 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) | |
8693 | tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); | |
8694 | else if (ets) | |
8695 | tc = ets->prio_tc[prio]; | |
8696 | ||
8697 | netdev_set_prio_tc_map(dev, prio, tc); | |
8698 | } | |
8699 | } | |
8700 | ||
cca73c59 | 8701 | #endif /* CONFIG_IXGBE_DCB */ |
49ce9c2c BH |
8702 | /** |
8703 | * ixgbe_setup_tc - configure net_device for multiple traffic classes | |
8b1c0b24 JF |
8704 | * |
8705 | * @netdev: net device to configure | |
8706 | * @tc: number of traffic classes to enable | |
8707 | */ | |
8708 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
8709 | { | |
8b1c0b24 JF |
8710 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
8711 | struct ixgbe_hw *hw = &adapter->hw; | |
2a47fa45 | 8712 | bool pools; |
8b1c0b24 | 8713 | |
8b1c0b24 | 8714 | /* Hardware supports up to 8 traffic classes */ |
7e3f5c88 ET |
8715 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) |
8716 | return -EINVAL; | |
8717 | ||
8718 | if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) | |
8b1c0b24 JF |
8719 | return -EINVAL; |
8720 | ||
2a47fa45 JF |
8721 | pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); |
8722 | if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) | |
8723 | return -EBUSY; | |
8724 | ||
8b1c0b24 | 8725 | /* Hardware has to reinitialize queues and interrupts to |
52f33af8 | 8726 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
8727 | * hardware is not flexible enough to do this dynamically. |
8728 | */ | |
8729 | if (netif_running(dev)) | |
8730 | ixgbe_close(dev); | |
bf4d67d9 AD |
8731 | else |
8732 | ixgbe_reset(adapter); | |
8733 | ||
8b1c0b24 JF |
8734 | ixgbe_clear_interrupt_scheme(adapter); |
8735 | ||
cca73c59 | 8736 | #ifdef CONFIG_IXGBE_DCB |
e7589eab | 8737 | if (tc) { |
8b1c0b24 | 8738 | netdev_set_num_tc(dev, tc); |
02debdc9 AD |
8739 | ixgbe_set_prio_tc_map(adapter); |
8740 | ||
e7589eab | 8741 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
e7589eab | 8742 | |
943561d3 AD |
8743 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
8744 | adapter->last_lfc_mode = adapter->hw.fc.requested_mode; | |
e7589eab | 8745 | adapter->hw.fc.requested_mode = ixgbe_fc_none; |
943561d3 | 8746 | } |
e7589eab | 8747 | } else { |
8b1c0b24 | 8748 | netdev_reset_tc(dev); |
02debdc9 | 8749 | |
943561d3 AD |
8750 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
8751 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; | |
e7589eab JF |
8752 | |
8753 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
e7589eab JF |
8754 | |
8755 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
8756 | adapter->dcb_cfg.pfc_mode_enable = false; | |
8757 | } | |
8758 | ||
8b1c0b24 | 8759 | ixgbe_validate_rtr(adapter, tc); |
cca73c59 AD |
8760 | |
8761 | #endif /* CONFIG_IXGBE_DCB */ | |
8762 | ixgbe_init_interrupt_scheme(adapter); | |
8763 | ||
8b1c0b24 | 8764 | if (netif_running(dev)) |
cca73c59 | 8765 | return ixgbe_open(dev); |
8b1c0b24 JF |
8766 | |
8767 | return 0; | |
8768 | } | |
de1036b1 | 8769 | |
b82b17d9 JF |
8770 | static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, |
8771 | struct tc_cls_u32_offload *cls) | |
8772 | { | |
1ecedc92 | 8773 | u32 hdl = cls->knode.handle; |
176621c9 | 8774 | u32 uhtid = TC_U32_USERHTID(cls->knode.handle); |
1ecedc92 AN |
8775 | u32 loc = cls->knode.handle & 0xfffff; |
8776 | int err = 0, i, j; | |
8777 | struct ixgbe_jump_table *jump = NULL; | |
8778 | ||
8779 | if (loc > IXGBE_MAX_HW_ENTRIES) | |
8780 | return -EINVAL; | |
b82b17d9 | 8781 | |
176621c9 SS |
8782 | if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) |
8783 | return -EINVAL; | |
8784 | ||
1ecedc92 AN |
8785 | /* Clear this filter in the link data it is associated with */ |
8786 | if (uhtid != 0x800) { | |
8787 | jump = adapter->jump_tables[uhtid]; | |
12746fd2 AN |
8788 | if (!jump) |
8789 | return -EINVAL; | |
8790 | if (!test_bit(loc - 1, jump->child_loc_map)) | |
8791 | return -EINVAL; | |
8792 | clear_bit(loc - 1, jump->child_loc_map); | |
1ecedc92 AN |
8793 | } |
8794 | ||
8795 | /* Check if the filter being deleted is a link */ | |
8796 | for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { | |
8797 | jump = adapter->jump_tables[i]; | |
8798 | if (jump && jump->link_hdl == hdl) { | |
8799 | /* Delete filters in the hardware in the child hash | |
8800 | * table associated with this link | |
8801 | */ | |
8802 | for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { | |
8803 | if (!test_bit(j, jump->child_loc_map)) | |
8804 | continue; | |
8805 | spin_lock(&adapter->fdir_perfect_lock); | |
8806 | err = ixgbe_update_ethtool_fdir_entry(adapter, | |
8807 | NULL, | |
8808 | j + 1); | |
8809 | spin_unlock(&adapter->fdir_perfect_lock); | |
8810 | clear_bit(j, jump->child_loc_map); | |
8811 | } | |
8812 | /* Remove resources for this link */ | |
8813 | kfree(jump->input); | |
8814 | kfree(jump->mask); | |
8815 | kfree(jump); | |
8816 | adapter->jump_tables[i] = NULL; | |
8817 | return err; | |
8818 | } | |
8819 | } | |
176621c9 | 8820 | |
b82b17d9 | 8821 | spin_lock(&adapter->fdir_perfect_lock); |
176621c9 | 8822 | err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); |
b82b17d9 JF |
8823 | spin_unlock(&adapter->fdir_perfect_lock); |
8824 | return err; | |
8825 | } | |
8826 | ||
db956ae8 JF |
8827 | static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, |
8828 | __be16 protocol, | |
8829 | struct tc_cls_u32_offload *cls) | |
8830 | { | |
176621c9 SS |
8831 | u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); |
8832 | ||
8833 | if (uhtid >= IXGBE_MAX_LINK_HANDLE) | |
8834 | return -EINVAL; | |
8835 | ||
db956ae8 JF |
8836 | /* This ixgbe devices do not support hash tables at the moment |
8837 | * so abort when given hash tables. | |
8838 | */ | |
8839 | if (cls->hnode.divisor > 0) | |
8840 | return -EINVAL; | |
8841 | ||
176621c9 | 8842 | set_bit(uhtid - 1, &adapter->tables); |
db956ae8 JF |
8843 | return 0; |
8844 | } | |
8845 | ||
8846 | static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, | |
8847 | struct tc_cls_u32_offload *cls) | |
8848 | { | |
176621c9 SS |
8849 | u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); |
8850 | ||
8851 | if (uhtid >= IXGBE_MAX_LINK_HANDLE) | |
8852 | return -EINVAL; | |
8853 | ||
8854 | clear_bit(uhtid - 1, &adapter->tables); | |
db956ae8 JF |
8855 | return 0; |
8856 | } | |
8857 | ||
947f8a45 | 8858 | #ifdef CONFIG_NET_CLS_ACT |
1cd127fc DA |
8859 | struct upper_walk_data { |
8860 | struct ixgbe_adapter *adapter; | |
8861 | u64 action; | |
8862 | int ifindex; | |
8863 | u8 queue; | |
8864 | }; | |
8865 | ||
8866 | static int get_macvlan_queue(struct net_device *upper, void *_data) | |
8867 | { | |
8868 | if (netif_is_macvlan(upper)) { | |
8869 | struct macvlan_dev *dfwd = netdev_priv(upper); | |
8870 | struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; | |
8871 | struct upper_walk_data *data = _data; | |
8872 | struct ixgbe_adapter *adapter = data->adapter; | |
8873 | int ifindex = data->ifindex; | |
8874 | ||
8875 | if (vadapter && vadapter->netdev->ifindex == ifindex) { | |
8876 | data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; | |
8877 | data->action = data->queue; | |
8878 | return 1; | |
8879 | } | |
8880 | } | |
8881 | ||
8882 | return 0; | |
8883 | } | |
8884 | ||
947f8a45 SS |
8885 | static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, |
8886 | u8 *queue, u64 *action) | |
8887 | { | |
8888 | unsigned int num_vfs = adapter->num_vfs, vf; | |
1cd127fc | 8889 | struct upper_walk_data data; |
947f8a45 | 8890 | struct net_device *upper; |
947f8a45 SS |
8891 | |
8892 | /* redirect to a SRIOV VF */ | |
8893 | for (vf = 0; vf < num_vfs; ++vf) { | |
8894 | upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); | |
8895 | if (upper->ifindex == ifindex) { | |
8896 | if (adapter->num_rx_pools > 1) | |
8897 | *queue = vf * 2; | |
8898 | else | |
8899 | *queue = vf * adapter->num_rx_queues_per_pool; | |
8900 | ||
8901 | *action = vf + 1; | |
8902 | *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; | |
8903 | return 0; | |
8904 | } | |
8905 | } | |
8906 | ||
8907 | /* redirect to a offloaded macvlan netdev */ | |
1cd127fc DA |
8908 | data.adapter = adapter; |
8909 | data.ifindex = ifindex; | |
8910 | data.action = 0; | |
8911 | data.queue = 0; | |
8912 | if (netdev_walk_all_upper_dev_rcu(adapter->netdev, | |
8913 | get_macvlan_queue, &data)) { | |
8914 | *action = data.action; | |
8915 | *queue = data.queue; | |
8916 | ||
8917 | return 0; | |
947f8a45 SS |
8918 | } |
8919 | ||
8920 | return -EINVAL; | |
8921 | } | |
8922 | ||
8923 | static int parse_tc_actions(struct ixgbe_adapter *adapter, | |
8924 | struct tcf_exts *exts, u64 *action, u8 *queue) | |
8925 | { | |
8926 | const struct tc_action *a; | |
22dc13c8 | 8927 | LIST_HEAD(actions); |
947f8a45 SS |
8928 | int err; |
8929 | ||
8930 | if (tc_no_actions(exts)) | |
8931 | return -EINVAL; | |
8932 | ||
22dc13c8 WC |
8933 | tcf_exts_to_list(exts, &actions); |
8934 | list_for_each_entry(a, &actions, list) { | |
947f8a45 SS |
8935 | |
8936 | /* Drop action */ | |
8937 | if (is_tcf_gact_shot(a)) { | |
8938 | *action = IXGBE_FDIR_DROP_QUEUE; | |
8939 | *queue = IXGBE_FDIR_DROP_QUEUE; | |
8940 | return 0; | |
8941 | } | |
8942 | ||
8943 | /* Redirect to a VF or a offloaded macvlan */ | |
5724b8b5 | 8944 | if (is_tcf_mirred_egress_redirect(a)) { |
947f8a45 SS |
8945 | int ifindex = tcf_mirred_ifindex(a); |
8946 | ||
8947 | err = handle_redirect_action(adapter, ifindex, queue, | |
8948 | action); | |
8949 | if (err == 0) | |
8950 | return err; | |
8951 | } | |
8952 | } | |
8953 | ||
8954 | return -EINVAL; | |
8955 | } | |
8956 | #else | |
8957 | static int parse_tc_actions(struct ixgbe_adapter *adapter, | |
8958 | struct tcf_exts *exts, u64 *action, u8 *queue) | |
8959 | { | |
8960 | return -EINVAL; | |
8961 | } | |
8962 | #endif /* CONFIG_NET_CLS_ACT */ | |
8963 | ||
1cdaaf54 AN |
8964 | static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, |
8965 | union ixgbe_atr_input *mask, | |
8966 | struct tc_cls_u32_offload *cls, | |
8967 | struct ixgbe_mat_field *field_ptr, | |
8968 | struct ixgbe_nexthdr *nexthdr) | |
8969 | { | |
8970 | int i, j, off; | |
8971 | __be32 val, m; | |
8972 | bool found_entry = false, found_jump_field = false; | |
8973 | ||
8974 | for (i = 0; i < cls->knode.sel->nkeys; i++) { | |
8975 | off = cls->knode.sel->keys[i].off; | |
8976 | val = cls->knode.sel->keys[i].val; | |
8977 | m = cls->knode.sel->keys[i].mask; | |
8978 | ||
8979 | for (j = 0; field_ptr[j].val; j++) { | |
8980 | if (field_ptr[j].off == off) { | |
8981 | field_ptr[j].val(input, mask, val, m); | |
8982 | input->filter.formatted.flow_type |= | |
8983 | field_ptr[j].type; | |
8984 | found_entry = true; | |
8985 | break; | |
8986 | } | |
8987 | } | |
8988 | if (nexthdr) { | |
8989 | if (nexthdr->off == cls->knode.sel->keys[i].off && | |
8990 | nexthdr->val == cls->knode.sel->keys[i].val && | |
8991 | nexthdr->mask == cls->knode.sel->keys[i].mask) | |
8992 | found_jump_field = true; | |
8993 | else | |
8994 | continue; | |
8995 | } | |
8996 | } | |
8997 | ||
8998 | if (nexthdr && !found_jump_field) | |
8999 | return -EINVAL; | |
9000 | ||
9001 | if (!found_entry) | |
9002 | return 0; | |
9003 | ||
9004 | mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | | |
9005 | IXGBE_ATR_L4TYPE_MASK; | |
9006 | ||
9007 | if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) | |
9008 | mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; | |
9009 | ||
9010 | return 0; | |
9011 | } | |
9012 | ||
b82b17d9 JF |
9013 | static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, |
9014 | __be16 protocol, | |
9015 | struct tc_cls_u32_offload *cls) | |
9016 | { | |
9017 | u32 loc = cls->knode.handle & 0xfffff; | |
9018 | struct ixgbe_hw *hw = &adapter->hw; | |
9019 | struct ixgbe_mat_field *field_ptr; | |
1cdaaf54 AN |
9020 | struct ixgbe_fdir_filter *input = NULL; |
9021 | union ixgbe_atr_input *mask = NULL; | |
9022 | struct ixgbe_jump_table *jump = NULL; | |
9023 | int i, err = -EINVAL; | |
b82b17d9 | 9024 | u8 queue; |
176621c9 | 9025 | u32 uhtid, link_uhtid; |
b82b17d9 | 9026 | |
176621c9 SS |
9027 | uhtid = TC_U32_USERHTID(cls->knode.handle); |
9028 | link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); | |
b82b17d9 | 9029 | |
176621c9 | 9030 | /* At the moment cls_u32 jumps to network layer and skips past |
b82b17d9 JF |
9031 | * L2 headers. The canonical method to match L2 frames is to use |
9032 | * negative values. However this is error prone at best but really | |
9033 | * just broken because there is no way to "know" what sort of hdr | |
176621c9 | 9034 | * is in front of the network layer. Fix cls_u32 to support L2 |
b82b17d9 JF |
9035 | * headers when needed. |
9036 | */ | |
9037 | if (protocol != htons(ETH_P_IP)) | |
1cdaaf54 | 9038 | return err; |
b82b17d9 JF |
9039 | |
9040 | if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { | |
9041 | e_err(drv, "Location out of range\n"); | |
1cdaaf54 | 9042 | return err; |
b82b17d9 JF |
9043 | } |
9044 | ||
9045 | /* cls u32 is a graph starting at root node 0x800. The driver tracks | |
9046 | * links and also the fields used to advance the parser across each | |
9047 | * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map | |
9048 | * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h | |
9049 | * To add support for new nodes update ixgbe_model.h parse structures | |
9050 | * this function _should_ be generic try not to hardcode values here. | |
9051 | */ | |
176621c9 | 9052 | if (uhtid == 0x800) { |
1cdaaf54 | 9053 | field_ptr = (adapter->jump_tables[0])->mat; |
b82b17d9 | 9054 | } else { |
176621c9 | 9055 | if (uhtid >= IXGBE_MAX_LINK_HANDLE) |
1cdaaf54 AN |
9056 | return err; |
9057 | if (!adapter->jump_tables[uhtid]) | |
9058 | return err; | |
9059 | field_ptr = (adapter->jump_tables[uhtid])->mat; | |
b82b17d9 JF |
9060 | } |
9061 | ||
9062 | if (!field_ptr) | |
1cdaaf54 | 9063 | return err; |
b82b17d9 | 9064 | |
1cdaaf54 AN |
9065 | /* At this point we know the field_ptr is valid and need to either |
9066 | * build cls_u32 link or attach filter. Because adding a link to | |
9067 | * a handle that does not exist is invalid and the same for adding | |
9068 | * rules to handles that don't exist. | |
9069 | */ | |
b82b17d9 | 9070 | |
1cdaaf54 AN |
9071 | if (link_uhtid) { |
9072 | struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; | |
b82b17d9 | 9073 | |
1cdaaf54 AN |
9074 | if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) |
9075 | return err; | |
9076 | ||
9077 | if (!test_bit(link_uhtid - 1, &adapter->tables)) | |
9078 | return err; | |
9079 | ||
1ecedc92 AN |
9080 | /* Multiple filters as links to the same hash table are not |
9081 | * supported. To add a new filter with the same next header | |
9082 | * but different match/jump conditions, create a new hash table | |
9083 | * and link to it. | |
9084 | */ | |
9085 | if (adapter->jump_tables[link_uhtid] && | |
9086 | (adapter->jump_tables[link_uhtid])->link_hdl) { | |
9087 | e_err(drv, "Link filter exists for link: %x\n", | |
9088 | link_uhtid); | |
9089 | return err; | |
9090 | } | |
9091 | ||
1cdaaf54 AN |
9092 | for (i = 0; nexthdr[i].jump; i++) { |
9093 | if (nexthdr[i].o != cls->knode.sel->offoff || | |
9094 | nexthdr[i].s != cls->knode.sel->offshift || | |
9095 | nexthdr[i].m != cls->knode.sel->offmask) | |
9096 | return err; | |
9097 | ||
9098 | jump = kzalloc(sizeof(*jump), GFP_KERNEL); | |
9099 | if (!jump) | |
9100 | return -ENOMEM; | |
9101 | input = kzalloc(sizeof(*input), GFP_KERNEL); | |
9102 | if (!input) { | |
9103 | err = -ENOMEM; | |
9104 | goto free_jump; | |
9105 | } | |
9106 | mask = kzalloc(sizeof(*mask), GFP_KERNEL); | |
9107 | if (!mask) { | |
9108 | err = -ENOMEM; | |
12746fd2 | 9109 | goto free_input; |
1cdaaf54 AN |
9110 | } |
9111 | jump->input = input; | |
9112 | jump->mask = mask; | |
1ecedc92 AN |
9113 | jump->link_hdl = cls->knode.handle; |
9114 | ||
1cdaaf54 AN |
9115 | err = ixgbe_clsu32_build_input(input, mask, cls, |
9116 | field_ptr, &nexthdr[i]); | |
9117 | if (!err) { | |
9118 | jump->mat = nexthdr[i].jump; | |
9119 | adapter->jump_tables[link_uhtid] = jump; | |
b82b17d9 JF |
9120 | break; |
9121 | } | |
9122 | } | |
1cdaaf54 | 9123 | return 0; |
b82b17d9 JF |
9124 | } |
9125 | ||
1cdaaf54 AN |
9126 | input = kzalloc(sizeof(*input), GFP_KERNEL); |
9127 | if (!input) | |
9128 | return -ENOMEM; | |
9129 | mask = kzalloc(sizeof(*mask), GFP_KERNEL); | |
9130 | if (!mask) { | |
9131 | err = -ENOMEM; | |
12746fd2 | 9132 | goto free_input; |
1cdaaf54 | 9133 | } |
b82b17d9 | 9134 | |
1cdaaf54 AN |
9135 | if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { |
9136 | if ((adapter->jump_tables[uhtid])->input) | |
9137 | memcpy(input, (adapter->jump_tables[uhtid])->input, | |
9138 | sizeof(*input)); | |
9139 | if ((adapter->jump_tables[uhtid])->mask) | |
9140 | memcpy(mask, (adapter->jump_tables[uhtid])->mask, | |
9141 | sizeof(*mask)); | |
12746fd2 AN |
9142 | |
9143 | /* Lookup in all child hash tables if this location is already | |
9144 | * filled with a filter | |
9145 | */ | |
9146 | for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { | |
9147 | struct ixgbe_jump_table *link = adapter->jump_tables[i]; | |
9148 | ||
9149 | if (link && (test_bit(loc - 1, link->child_loc_map))) { | |
9150 | e_err(drv, "Filter exists in location: %x\n", | |
9151 | loc); | |
9152 | err = -EINVAL; | |
9153 | goto err_out; | |
9154 | } | |
9155 | } | |
1cdaaf54 AN |
9156 | } |
9157 | err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); | |
9158 | if (err) | |
b82b17d9 JF |
9159 | goto err_out; |
9160 | ||
947f8a45 SS |
9161 | err = parse_tc_actions(adapter, cls->knode.exts, &input->action, |
9162 | &queue); | |
9163 | if (err < 0) | |
b82b17d9 | 9164 | goto err_out; |
b82b17d9 | 9165 | |
b82b17d9 JF |
9166 | input->sw_idx = loc; |
9167 | ||
9168 | spin_lock(&adapter->fdir_perfect_lock); | |
9169 | ||
9170 | if (hlist_empty(&adapter->fdir_filter_list)) { | |
1cdaaf54 AN |
9171 | memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); |
9172 | err = ixgbe_fdir_set_input_mask_82599(hw, mask); | |
b82b17d9 JF |
9173 | if (err) |
9174 | goto err_out_w_lock; | |
1cdaaf54 | 9175 | } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { |
b82b17d9 JF |
9176 | err = -EINVAL; |
9177 | goto err_out_w_lock; | |
9178 | } | |
9179 | ||
1cdaaf54 | 9180 | ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); |
b82b17d9 JF |
9181 | err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, |
9182 | input->sw_idx, queue); | |
9183 | if (!err) | |
9184 | ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); | |
9185 | spin_unlock(&adapter->fdir_perfect_lock); | |
9186 | ||
12746fd2 AN |
9187 | if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) |
9188 | set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); | |
1ecedc92 | 9189 | |
1cdaaf54 | 9190 | kfree(mask); |
b82b17d9 JF |
9191 | return err; |
9192 | err_out_w_lock: | |
9193 | spin_unlock(&adapter->fdir_perfect_lock); | |
9194 | err_out: | |
1ecedc92 | 9195 | kfree(mask); |
12746fd2 AN |
9196 | free_input: |
9197 | kfree(input); | |
1cdaaf54 AN |
9198 | free_jump: |
9199 | kfree(jump); | |
9200 | return err; | |
b82b17d9 JF |
9201 | } |
9202 | ||
6e2a60b5 ET |
9203 | static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto, |
9204 | struct tc_to_netdev *tc) | |
e4c6734e | 9205 | { |
b82b17d9 JF |
9206 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
9207 | ||
9208 | if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) && | |
9209 | tc->type == TC_SETUP_CLSU32) { | |
b82b17d9 JF |
9210 | switch (tc->cls_u32->command) { |
9211 | case TC_CLSU32_NEW_KNODE: | |
9212 | case TC_CLSU32_REPLACE_KNODE: | |
9213 | return ixgbe_configure_clsu32(adapter, | |
9214 | proto, tc->cls_u32); | |
9215 | case TC_CLSU32_DELETE_KNODE: | |
9216 | return ixgbe_delete_clsu32(adapter, tc->cls_u32); | |
db956ae8 JF |
9217 | case TC_CLSU32_NEW_HNODE: |
9218 | case TC_CLSU32_REPLACE_HNODE: | |
9219 | return ixgbe_configure_clsu32_add_hnode(adapter, proto, | |
9220 | tc->cls_u32); | |
9221 | case TC_CLSU32_DELETE_HNODE: | |
9222 | return ixgbe_configure_clsu32_del_hnode(adapter, | |
9223 | tc->cls_u32); | |
b82b17d9 JF |
9224 | default: |
9225 | return -EINVAL; | |
9226 | } | |
9227 | } | |
9228 | ||
5eb4dce3 | 9229 | if (tc->type != TC_SETUP_MQPRIO) |
e4c6734e JF |
9230 | return -EINVAL; |
9231 | ||
56f36acd AN |
9232 | tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; |
9233 | ||
9234 | return ixgbe_setup_tc(dev, tc->mqprio->num_tc); | |
e4c6734e JF |
9235 | } |
9236 | ||
da36b647 GR |
9237 | #ifdef CONFIG_PCI_IOV |
9238 | void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) | |
9239 | { | |
9240 | struct net_device *netdev = adapter->netdev; | |
9241 | ||
9242 | rtnl_lock(); | |
da36b647 | 9243 | ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); |
da36b647 GR |
9244 | rtnl_unlock(); |
9245 | } | |
9246 | ||
9247 | #endif | |
082757af DS |
9248 | void ixgbe_do_reset(struct net_device *netdev) |
9249 | { | |
9250 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9251 | ||
9252 | if (netif_running(netdev)) | |
9253 | ixgbe_reinit_locked(adapter); | |
9254 | else | |
9255 | ixgbe_reset(adapter); | |
9256 | } | |
9257 | ||
c8f44aff | 9258 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
567d2de2 | 9259 | netdev_features_t features) |
082757af DS |
9260 | { |
9261 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9262 | ||
082757af | 9263 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ |
567d2de2 AD |
9264 | if (!(features & NETIF_F_RXCSUM)) |
9265 | features &= ~NETIF_F_LRO; | |
082757af | 9266 | |
567d2de2 AD |
9267 | /* Turn off LRO if not RSC capable */ |
9268 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) | |
9269 | features &= ~NETIF_F_LRO; | |
8e2813f5 | 9270 | |
567d2de2 | 9271 | return features; |
082757af DS |
9272 | } |
9273 | ||
c8f44aff | 9274 | static int ixgbe_set_features(struct net_device *netdev, |
567d2de2 | 9275 | netdev_features_t features) |
082757af DS |
9276 | { |
9277 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
567d2de2 | 9278 | netdev_features_t changed = netdev->features ^ features; |
082757af DS |
9279 | bool need_reset = false; |
9280 | ||
082757af | 9281 | /* Make sure RSC matches LRO, reset if change */ |
567d2de2 AD |
9282 | if (!(features & NETIF_F_LRO)) { |
9283 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
082757af | 9284 | need_reset = true; |
567d2de2 AD |
9285 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; |
9286 | } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && | |
9287 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
9288 | if (adapter->rx_itr_setting == 1 || | |
9289 | adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { | |
9290 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
9291 | need_reset = true; | |
9292 | } else if ((changed ^ features) & NETIF_F_LRO) { | |
9293 | e_info(probe, "rx-usecs set too low, " | |
9294 | "disabling RSC\n"); | |
082757af DS |
9295 | } |
9296 | } | |
9297 | ||
9298 | /* | |
b82b17d9 JF |
9299 | * Check if Flow Director n-tuple support or hw_tc support was |
9300 | * enabled or disabled. If the state changed, we need to reset. | |
082757af | 9301 | */ |
b82b17d9 | 9302 | if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { |
567d2de2 | 9303 | /* turn off ATR, enable perfect filters and reset */ |
39cb681b AD |
9304 | if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) |
9305 | need_reset = true; | |
9306 | ||
567d2de2 AD |
9307 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
9308 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
b82b17d9 | 9309 | } else { |
39cb681b AD |
9310 | /* turn off perfect filters, enable ATR and reset */ |
9311 | if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
9312 | need_reset = true; | |
9313 | ||
9314 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
9315 | ||
9316 | /* We cannot enable ATR if SR-IOV is enabled */ | |
b82b17d9 JF |
9317 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || |
9318 | /* We cannot enable ATR if we have 2 or more tcs */ | |
9319 | (netdev_get_num_tc(netdev) > 1) || | |
9320 | /* We cannot enable ATR if RSS is disabled */ | |
9321 | (adapter->ring_feature[RING_F_RSS].limit <= 1) || | |
9322 | /* A sample rate of 0 indicates ATR disabled */ | |
9323 | (!adapter->atr_sample_rate)) | |
9324 | ; /* do nothing not supported */ | |
9325 | else /* otherwise supported and set the flag */ | |
9326 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
082757af DS |
9327 | } |
9328 | ||
3f2d1c0f BG |
9329 | if (changed & NETIF_F_RXALL) |
9330 | need_reset = true; | |
9331 | ||
567d2de2 | 9332 | netdev->features = features; |
67359c3c | 9333 | |
67359c3c | 9334 | if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { |
a21d0822 ET |
9335 | if (features & NETIF_F_RXCSUM) { |
9336 | adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; | |
9337 | } else { | |
9338 | u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; | |
9339 | ||
9340 | ixgbe_clear_udp_tunnel_port(adapter, port_mask); | |
9341 | } | |
9342 | } | |
9343 | ||
9344 | if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { | |
9345 | if (features & NETIF_F_RXCSUM) { | |
9346 | adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; | |
9347 | } else { | |
9348 | u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; | |
9349 | ||
9350 | ixgbe_clear_udp_tunnel_port(adapter, port_mask); | |
9351 | } | |
67359c3c | 9352 | } |
67359c3c | 9353 | |
082757af DS |
9354 | if (need_reset) |
9355 | ixgbe_do_reset(netdev); | |
0c5a6166 AD |
9356 | else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | |
9357 | NETIF_F_HW_VLAN_CTAG_FILTER)) | |
9358 | ixgbe_set_rx_mode(netdev); | |
082757af DS |
9359 | |
9360 | return 0; | |
082757af DS |
9361 | } |
9362 | ||
3f207800 | 9363 | /** |
a21d0822 | 9364 | * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports |
3f207800 | 9365 | * @dev: The port's netdev |
e5de25dc | 9366 | * @ti: Tunnel endpoint information |
3f207800 | 9367 | **/ |
a21d0822 ET |
9368 | static void ixgbe_add_udp_tunnel_port(struct net_device *dev, |
9369 | struct udp_tunnel_info *ti) | |
3f207800 DS |
9370 | { |
9371 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
9372 | struct ixgbe_hw *hw = &adapter->hw; | |
b3a49557 | 9373 | __be16 port = ti->port; |
a21d0822 ET |
9374 | u32 port_shift = 0; |
9375 | u32 reg; | |
67359c3c | 9376 | |
b3a49557 AD |
9377 | if (ti->sa_family != AF_INET) |
9378 | return; | |
9379 | ||
a21d0822 ET |
9380 | switch (ti->type) { |
9381 | case UDP_TUNNEL_TYPE_VXLAN: | |
9382 | if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) | |
9383 | return; | |
3f207800 | 9384 | |
a21d0822 ET |
9385 | if (adapter->vxlan_port == port) |
9386 | return; | |
9387 | ||
9388 | if (adapter->vxlan_port) { | |
9389 | netdev_info(dev, | |
9390 | "VXLAN port %d set, not adding port %d\n", | |
9391 | ntohs(adapter->vxlan_port), | |
9392 | ntohs(port)); | |
9393 | return; | |
9394 | } | |
9395 | ||
9396 | adapter->vxlan_port = port; | |
9397 | break; | |
9398 | case UDP_TUNNEL_TYPE_GENEVE: | |
9399 | if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) | |
9400 | return; | |
9401 | ||
9402 | if (adapter->geneve_port == port) | |
9403 | return; | |
9404 | ||
9405 | if (adapter->geneve_port) { | |
9406 | netdev_info(dev, | |
9407 | "GENEVE port %d set, not adding port %d\n", | |
9408 | ntohs(adapter->geneve_port), | |
9409 | ntohs(port)); | |
9410 | return; | |
9411 | } | |
3f207800 | 9412 | |
a21d0822 ET |
9413 | port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; |
9414 | adapter->geneve_port = port; | |
9415 | break; | |
9416 | default: | |
3f207800 DS |
9417 | return; |
9418 | } | |
9419 | ||
a21d0822 ET |
9420 | reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; |
9421 | IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); | |
3f207800 DS |
9422 | } |
9423 | ||
9424 | /** | |
a21d0822 | 9425 | * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports |
3f207800 | 9426 | * @dev: The port's netdev |
e5de25dc | 9427 | * @ti: Tunnel endpoint information |
3f207800 | 9428 | **/ |
a21d0822 ET |
9429 | static void ixgbe_del_udp_tunnel_port(struct net_device *dev, |
9430 | struct udp_tunnel_info *ti) | |
3f207800 DS |
9431 | { |
9432 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
a21d0822 | 9433 | u32 port_mask; |
3f207800 | 9434 | |
a21d0822 ET |
9435 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN && |
9436 | ti->type != UDP_TUNNEL_TYPE_GENEVE) | |
67359c3c MR |
9437 | return; |
9438 | ||
b3a49557 | 9439 | if (ti->sa_family != AF_INET) |
3f207800 DS |
9440 | return; |
9441 | ||
a21d0822 ET |
9442 | switch (ti->type) { |
9443 | case UDP_TUNNEL_TYPE_VXLAN: | |
9444 | if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) | |
9445 | return; | |
b3a49557 | 9446 | |
a21d0822 ET |
9447 | if (adapter->vxlan_port != ti->port) { |
9448 | netdev_info(dev, "VXLAN port %d not found\n", | |
9449 | ntohs(ti->port)); | |
9450 | return; | |
9451 | } | |
9452 | ||
9453 | port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; | |
9454 | break; | |
9455 | case UDP_TUNNEL_TYPE_GENEVE: | |
9456 | if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) | |
9457 | return; | |
9458 | ||
9459 | if (adapter->geneve_port != ti->port) { | |
9460 | netdev_info(dev, "GENEVE port %d not found\n", | |
9461 | ntohs(ti->port)); | |
9462 | return; | |
9463 | } | |
9464 | ||
9465 | port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; | |
9466 | break; | |
9467 | default: | |
3f207800 DS |
9468 | return; |
9469 | } | |
9470 | ||
a21d0822 ET |
9471 | ixgbe_clear_udp_tunnel_port(adapter, port_mask); |
9472 | adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; | |
3f207800 DS |
9473 | } |
9474 | ||
edc7d573 | 9475 | static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], |
0f4b0add | 9476 | struct net_device *dev, |
f6f6424b | 9477 | const unsigned char *addr, u16 vid, |
0f4b0add JF |
9478 | u16 flags) |
9479 | { | |
bcfd3432 | 9480 | /* guarantee we can provide a unique filter for the unicast address */ |
46acc460 | 9481 | if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { |
2f9be166 AD |
9482 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
9483 | u16 pool = VMDQ_P(0); | |
9484 | ||
9485 | if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) | |
bcfd3432 | 9486 | return -ENOMEM; |
0f4b0add JF |
9487 | } |
9488 | ||
f6f6424b | 9489 | return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); |
0f4b0add JF |
9490 | } |
9491 | ||
219efe97 DS |
9492 | /** |
9493 | * ixgbe_configure_bridge_mode - set various bridge modes | |
9494 | * @adapter - the private structure | |
9495 | * @mode - requested bridge mode | |
9496 | * | |
9497 | * Configure some settings require for various bridge modes. | |
9498 | **/ | |
9499 | static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, | |
9500 | __u16 mode) | |
9501 | { | |
6d4c96ad DS |
9502 | struct ixgbe_hw *hw = &adapter->hw; |
9503 | unsigned int p, num_pools; | |
9504 | u32 vmdctl; | |
9505 | ||
219efe97 DS |
9506 | switch (mode) { |
9507 | case BRIDGE_MODE_VEPA: | |
6d4c96ad | 9508 | /* disable Tx loopback, rely on switch hairpin mode */ |
219efe97 | 9509 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); |
6d4c96ad DS |
9510 | |
9511 | /* must enable Rx switching replication to allow multicast | |
9512 | * packet reception on all VFs, and to enable source address | |
9513 | * pruning. | |
9514 | */ | |
9515 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); | |
9516 | vmdctl |= IXGBE_VT_CTL_REPLEN; | |
9517 | IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); | |
9518 | ||
9519 | /* enable Rx source address pruning. Note, this requires | |
9520 | * replication to be enabled or else it does nothing. | |
9521 | */ | |
9522 | num_pools = adapter->num_vfs + adapter->num_rx_pools; | |
9523 | for (p = 0; p < num_pools; p++) { | |
9524 | if (hw->mac.ops.set_source_address_pruning) | |
9525 | hw->mac.ops.set_source_address_pruning(hw, | |
9526 | true, | |
9527 | p); | |
9528 | } | |
219efe97 DS |
9529 | break; |
9530 | case BRIDGE_MODE_VEB: | |
6d4c96ad | 9531 | /* enable Tx loopback for internal VF/PF communication */ |
219efe97 DS |
9532 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, |
9533 | IXGBE_PFDTXGSWC_VT_LBEN); | |
6d4c96ad DS |
9534 | |
9535 | /* disable Rx switching replication unless we have SR-IOV | |
9536 | * virtual functions | |
9537 | */ | |
9538 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); | |
9539 | if (!adapter->num_vfs) | |
9540 | vmdctl &= ~IXGBE_VT_CTL_REPLEN; | |
9541 | IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); | |
9542 | ||
9543 | /* disable Rx source address pruning, since we don't expect to | |
9544 | * be receiving external loopback of our transmitted frames. | |
9545 | */ | |
9546 | num_pools = adapter->num_vfs + adapter->num_rx_pools; | |
9547 | for (p = 0; p < num_pools; p++) { | |
9548 | if (hw->mac.ops.set_source_address_pruning) | |
9549 | hw->mac.ops.set_source_address_pruning(hw, | |
9550 | false, | |
9551 | p); | |
9552 | } | |
219efe97 DS |
9553 | break; |
9554 | default: | |
9555 | return -EINVAL; | |
9556 | } | |
9557 | ||
9558 | adapter->bridge_mode = mode; | |
9559 | ||
9560 | e_info(drv, "enabling bridge mode: %s\n", | |
9561 | mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); | |
9562 | ||
9563 | return 0; | |
9564 | } | |
9565 | ||
815cccbf | 9566 | static int ixgbe_ndo_bridge_setlink(struct net_device *dev, |
add511b3 | 9567 | struct nlmsghdr *nlh, u16 flags) |
815cccbf JF |
9568 | { |
9569 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
9570 | struct nlattr *attr, *br_spec; | |
9571 | int rem; | |
9572 | ||
9573 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
9574 | return -EOPNOTSUPP; | |
9575 | ||
9576 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
4ea85e83 TG |
9577 | if (!br_spec) |
9578 | return -EINVAL; | |
815cccbf JF |
9579 | |
9580 | nla_for_each_nested(attr, br_spec, rem) { | |
a1e869de | 9581 | int status; |
815cccbf | 9582 | __u16 mode; |
815cccbf JF |
9583 | |
9584 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
9585 | continue; | |
9586 | ||
b7c1a314 TG |
9587 | if (nla_len(attr) < sizeof(mode)) |
9588 | return -EINVAL; | |
9589 | ||
815cccbf | 9590 | mode = nla_get_u16(attr); |
219efe97 DS |
9591 | status = ixgbe_configure_bridge_mode(adapter, mode); |
9592 | if (status) | |
9593 | return status; | |
aa2bacb6 DS |
9594 | |
9595 | break; | |
815cccbf JF |
9596 | } |
9597 | ||
9598 | return 0; | |
9599 | } | |
9600 | ||
9601 | static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, | |
6cbdceeb | 9602 | struct net_device *dev, |
46c264da | 9603 | u32 filter_mask, int nlflags) |
815cccbf JF |
9604 | { |
9605 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
815cccbf JF |
9606 | |
9607 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
9608 | return 0; | |
9609 | ||
aa2bacb6 | 9610 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, |
7d4f8d87 SF |
9611 | adapter->bridge_mode, 0, 0, nlflags, |
9612 | filter_mask, NULL); | |
815cccbf JF |
9613 | } |
9614 | ||
2a47fa45 JF |
9615 | static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) |
9616 | { | |
9617 | struct ixgbe_fwd_adapter *fwd_adapter = NULL; | |
9618 | struct ixgbe_adapter *adapter = netdev_priv(pdev); | |
aac2f1bf | 9619 | int used_pools = adapter->num_vfs + adapter->num_rx_pools; |
51f3773b | 9620 | unsigned int limit; |
2a47fa45 JF |
9621 | int pool, err; |
9622 | ||
aac2f1bf JK |
9623 | /* Hardware has a limited number of available pools. Each VF, and the |
9624 | * PF require a pool. Check to ensure we don't attempt to use more | |
9625 | * then the available number of pools. | |
9626 | */ | |
9627 | if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) | |
9628 | return ERR_PTR(-EINVAL); | |
9629 | ||
219354d4 JF |
9630 | #ifdef CONFIG_RPS |
9631 | if (vdev->num_rx_queues != vdev->num_tx_queues) { | |
9632 | netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", | |
9633 | vdev->name); | |
9634 | return ERR_PTR(-EINVAL); | |
9635 | } | |
9636 | #endif | |
2a47fa45 | 9637 | /* Check for hardware restriction on number of rx/tx queues */ |
219354d4 | 9638 | if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || |
2a47fa45 JF |
9639 | vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { |
9640 | netdev_info(pdev, | |
9641 | "%s: Supports RX/TX Queue counts 1,2, and 4\n", | |
9642 | pdev->name); | |
9643 | return ERR_PTR(-EINVAL); | |
9644 | } | |
9645 | ||
9646 | if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && | |
9647 | adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || | |
9648 | (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) | |
9649 | return ERR_PTR(-EBUSY); | |
9650 | ||
bc52f951 | 9651 | fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); |
2a47fa45 JF |
9652 | if (!fwd_adapter) |
9653 | return ERR_PTR(-ENOMEM); | |
9654 | ||
9655 | pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); | |
9656 | adapter->num_rx_pools++; | |
9657 | set_bit(pool, &adapter->fwd_bitmask); | |
51f3773b | 9658 | limit = find_last_bit(&adapter->fwd_bitmask, 32); |
2a47fa45 JF |
9659 | |
9660 | /* Enable VMDq flag so device will be set in VM mode */ | |
9661 | adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; | |
51f3773b | 9662 | adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; |
219354d4 | 9663 | adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; |
2a47fa45 JF |
9664 | |
9665 | /* Force reinit of ring allocation with VMDQ enabled */ | |
9666 | err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); | |
9667 | if (err) | |
9668 | goto fwd_add_err; | |
9669 | fwd_adapter->pool = pool; | |
9670 | fwd_adapter->real_adapter = adapter; | |
a3b8cb1f ET |
9671 | |
9672 | if (netif_running(pdev)) { | |
9673 | err = ixgbe_fwd_ring_up(vdev, fwd_adapter); | |
9674 | if (err) | |
9675 | goto fwd_add_err; | |
9676 | netif_tx_start_all_queues(vdev); | |
9677 | } | |
9678 | ||
2a47fa45 JF |
9679 | return fwd_adapter; |
9680 | fwd_add_err: | |
9681 | /* unwind counter and free adapter struct */ | |
9682 | netdev_info(pdev, | |
9683 | "%s: dfwd hardware acceleration failed\n", vdev->name); | |
9684 | clear_bit(pool, &adapter->fwd_bitmask); | |
9685 | adapter->num_rx_pools--; | |
9686 | kfree(fwd_adapter); | |
9687 | return ERR_PTR(err); | |
9688 | } | |
9689 | ||
9690 | static void ixgbe_fwd_del(struct net_device *pdev, void *priv) | |
9691 | { | |
9692 | struct ixgbe_fwd_adapter *fwd_adapter = priv; | |
9693 | struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; | |
51f3773b | 9694 | unsigned int limit; |
2a47fa45 JF |
9695 | |
9696 | clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); | |
9697 | adapter->num_rx_pools--; | |
9698 | ||
51f3773b JF |
9699 | limit = find_last_bit(&adapter->fwd_bitmask, 32); |
9700 | adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; | |
2a47fa45 JF |
9701 | ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); |
9702 | ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); | |
9703 | netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", | |
9704 | fwd_adapter->pool, adapter->num_rx_pools, | |
9705 | fwd_adapter->rx_base_queue, | |
9706 | fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, | |
9707 | adapter->fwd_bitmask); | |
9708 | kfree(fwd_adapter); | |
9709 | } | |
9710 | ||
b83e3010 AD |
9711 | #define IXGBE_MAX_MAC_HDR_LEN 127 |
9712 | #define IXGBE_MAX_NETWORK_HDR_LEN 511 | |
9713 | ||
f467bc06 MR |
9714 | static netdev_features_t |
9715 | ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, | |
9716 | netdev_features_t features) | |
9717 | { | |
b83e3010 AD |
9718 | unsigned int network_hdr_len, mac_hdr_len; |
9719 | ||
9720 | /* Make certain the headers can be described by a context descriptor */ | |
9721 | mac_hdr_len = skb_network_header(skb) - skb->data; | |
9722 | if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) | |
9723 | return features & ~(NETIF_F_HW_CSUM | | |
9724 | NETIF_F_SCTP_CRC | | |
9725 | NETIF_F_HW_VLAN_CTAG_TX | | |
9726 | NETIF_F_TSO | | |
9727 | NETIF_F_TSO6); | |
9728 | ||
9729 | network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); | |
9730 | if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) | |
9731 | return features & ~(NETIF_F_HW_CSUM | | |
9732 | NETIF_F_SCTP_CRC | | |
9733 | NETIF_F_TSO | | |
9734 | NETIF_F_TSO6); | |
9735 | ||
9736 | /* We can only support IPV4 TSO in tunnels if we can mangle the | |
9737 | * inner IP ID field, so strip TSO if MANGLEID is not supported. | |
9738 | */ | |
9739 | if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) | |
9740 | features &= ~NETIF_F_TSO; | |
f467bc06 MR |
9741 | |
9742 | return features; | |
9743 | } | |
9744 | ||
92470808 JF |
9745 | static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) |
9746 | { | |
9747 | int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
9748 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
9749 | struct bpf_prog *old_prog; | |
9750 | ||
9751 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
9752 | return -EINVAL; | |
9753 | ||
9754 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
9755 | return -EINVAL; | |
9756 | ||
9757 | /* verify ixgbe ring attributes are sufficient for XDP */ | |
9758 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
9759 | struct ixgbe_ring *ring = adapter->rx_ring[i]; | |
9760 | ||
9761 | if (ring_is_rsc_enabled(ring)) | |
9762 | return -EINVAL; | |
9763 | ||
9764 | if (frame_size > ixgbe_rx_bufsz(ring)) | |
9765 | return -EINVAL; | |
9766 | } | |
9767 | ||
33fdc82f JF |
9768 | if (nr_cpu_ids > MAX_XDP_QUEUES) |
9769 | return -ENOMEM; | |
9770 | ||
92470808 | 9771 | old_prog = xchg(&adapter->xdp_prog, prog); |
33fdc82f JF |
9772 | |
9773 | /* If transitioning XDP modes reconfigure rings */ | |
9774 | if (!!prog != !!old_prog) { | |
9775 | int err = ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); | |
9776 | ||
9777 | if (err) { | |
9778 | rcu_assign_pointer(adapter->xdp_prog, old_prog); | |
9779 | return -EINVAL; | |
9780 | } | |
9781 | } else { | |
9782 | for (i = 0; i < adapter->num_rx_queues; i++) | |
9783 | xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog); | |
9784 | } | |
92470808 JF |
9785 | |
9786 | if (old_prog) | |
9787 | bpf_prog_put(old_prog); | |
9788 | ||
9789 | return 0; | |
9790 | } | |
9791 | ||
9792 | static int ixgbe_xdp(struct net_device *dev, struct netdev_xdp *xdp) | |
9793 | { | |
9794 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
9795 | ||
9796 | switch (xdp->command) { | |
9797 | case XDP_SETUP_PROG: | |
9798 | return ixgbe_xdp_setup(dev, xdp->prog); | |
9799 | case XDP_QUERY_PROG: | |
9800 | xdp->prog_attached = !!(adapter->xdp_prog); | |
9801 | return 0; | |
9802 | default: | |
9803 | return -EINVAL; | |
9804 | } | |
9805 | } | |
9806 | ||
0edc3527 | 9807 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 9808 | .ndo_open = ixgbe_open, |
0edc3527 | 9809 | .ndo_stop = ixgbe_close, |
00829823 | 9810 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 9811 | .ndo_select_queue = ixgbe_select_queue, |
581330ba | 9812 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
9813 | .ndo_validate_addr = eth_validate_addr, |
9814 | .ndo_set_mac_address = ixgbe_set_mac, | |
9815 | .ndo_change_mtu = ixgbe_change_mtu, | |
9816 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
c04f90e5 | 9817 | .ndo_set_tx_maxrate = ixgbe_tx_maxrate, |
0edc3527 SH |
9818 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
9819 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 9820 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
9821 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
9822 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
ed616689 | 9823 | .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, |
581330ba | 9824 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
e65ce0d3 | 9825 | .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, |
54011e4d | 9826 | .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, |
7f01648a | 9827 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 9828 | .ndo_get_stats64 = ixgbe_get_stats64, |
e4c6734e | 9829 | .ndo_setup_tc = __ixgbe_setup_tc, |
0edc3527 SH |
9830 | #ifdef CONFIG_NET_POLL_CONTROLLER |
9831 | .ndo_poll_controller = ixgbe_netpoll, | |
9832 | #endif | |
332d4a7d YZ |
9833 | #ifdef IXGBE_FCOE |
9834 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 9835 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 9836 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
9837 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
9838 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 9839 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 9840 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 9841 | #endif /* IXGBE_FCOE */ |
082757af DS |
9842 | .ndo_set_features = ixgbe_set_features, |
9843 | .ndo_fix_features = ixgbe_fix_features, | |
0f4b0add | 9844 | .ndo_fdb_add = ixgbe_ndo_fdb_add, |
815cccbf JF |
9845 | .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, |
9846 | .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, | |
2a47fa45 JF |
9847 | .ndo_dfwd_add_station = ixgbe_fwd_add, |
9848 | .ndo_dfwd_del_station = ixgbe_fwd_del, | |
a21d0822 ET |
9849 | .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, |
9850 | .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, | |
f467bc06 | 9851 | .ndo_features_check = ixgbe_features_check, |
92470808 | 9852 | .ndo_xdp = ixgbe_xdp, |
0edc3527 SH |
9853 | }; |
9854 | ||
e027d1ae JK |
9855 | /** |
9856 | * ixgbe_enumerate_functions - Get the number of ports this device has | |
9857 | * @adapter: adapter structure | |
9858 | * | |
9859 | * This function enumerates the phsyical functions co-located on a single slot, | |
9860 | * in order to determine how many ports a device has. This is most useful in | |
9861 | * determining the required GT/s of PCIe bandwidth necessary for optimal | |
9862 | * performance. | |
9863 | **/ | |
9864 | static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) | |
9865 | { | |
caafb95d | 9866 | struct pci_dev *entry, *pdev = adapter->pdev; |
e027d1ae JK |
9867 | int physfns = 0; |
9868 | ||
f1f96579 JK |
9869 | /* Some cards can not use the generic count PCIe functions method, |
9870 | * because they are behind a parent switch, so we hardcode these with | |
9871 | * the correct number of functions. | |
e027d1ae | 9872 | */ |
8818970d | 9873 | if (ixgbe_pcie_from_parent(&adapter->hw)) |
e027d1ae | 9874 | physfns = 4; |
8818970d JK |
9875 | |
9876 | list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { | |
9877 | /* don't count virtual functions */ | |
caafb95d JK |
9878 | if (entry->is_virtfn) |
9879 | continue; | |
9880 | ||
9881 | /* When the devices on the bus don't all match our device ID, | |
9882 | * we can't reliably determine the correct number of | |
9883 | * functions. This can occur if a function has been direct | |
9884 | * attached to a virtual machine using VT-d, for example. In | |
9885 | * this case, simply return -1 to indicate this. | |
9886 | */ | |
9887 | if ((entry->vendor != pdev->vendor) || | |
9888 | (entry->device != pdev->device)) | |
9889 | return -1; | |
9890 | ||
9891 | physfns++; | |
e027d1ae JK |
9892 | } |
9893 | ||
9894 | return physfns; | |
9895 | } | |
9896 | ||
8e2813f5 JK |
9897 | /** |
9898 | * ixgbe_wol_supported - Check whether device supports WoL | |
740234f0 | 9899 | * @adapter: the adapter private structure |
8e2813f5 JK |
9900 | * @device_id: the device ID |
9901 | * @subdev_id: the subsystem device ID | |
9902 | * | |
9903 | * This function is used by probe and ethtool to determine | |
9904 | * which devices have WoL support | |
9905 | * | |
9906 | **/ | |
740234f0 ET |
9907 | bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, |
9908 | u16 subdevice_id) | |
8e2813f5 JK |
9909 | { |
9910 | struct ixgbe_hw *hw = &adapter->hw; | |
9911 | u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
8e2813f5 | 9912 | |
740234f0 ET |
9913 | /* WOL not supported on 82598 */ |
9914 | if (hw->mac.type == ixgbe_mac_82598EB) | |
9915 | return false; | |
9916 | ||
9917 | /* check eeprom to see if WOL is enabled for X540 and newer */ | |
9918 | if (hw->mac.type >= ixgbe_mac_X540) { | |
9919 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
9920 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
9921 | (hw->bus.func == 0))) | |
9922 | return true; | |
9923 | } | |
9924 | ||
9925 | /* WOL is determined based on device IDs for 82599 MACs */ | |
8e2813f5 JK |
9926 | switch (device_id) { |
9927 | case IXGBE_DEV_ID_82599_SFP: | |
9928 | /* Only these subdevices could supports WOL */ | |
9929 | switch (subdevice_id) { | |
9930 | case IXGBE_SUBDEV_ID_82599_560FLR: | |
00103a6c ET |
9931 | case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: |
9932 | case IXGBE_SUBDEV_ID_82599_SFP_WOL0: | |
9933 | case IXGBE_SUBDEV_ID_82599_SFP_2OCP: | |
8e2813f5 JK |
9934 | /* only support first port */ |
9935 | if (hw->bus.func != 0) | |
9936 | break; | |
93df9465 | 9937 | /* fall through */ |
5700ff26 | 9938 | case IXGBE_SUBDEV_ID_82599_SP_560FLR: |
8e2813f5 | 9939 | case IXGBE_SUBDEV_ID_82599_SFP: |
b6dfd939 | 9940 | case IXGBE_SUBDEV_ID_82599_RNDC: |
f8a06c2c | 9941 | case IXGBE_SUBDEV_ID_82599_ECNA_DP: |
00103a6c ET |
9942 | case IXGBE_SUBDEV_ID_82599_SFP_1OCP: |
9943 | case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: | |
9944 | case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: | |
740234f0 | 9945 | return true; |
8e2813f5 JK |
9946 | } |
9947 | break; | |
5daebbb0 | 9948 | case IXGBE_DEV_ID_82599EN_SFP: |
740234f0 | 9949 | /* Only these subdevices support WOL */ |
5daebbb0 DS |
9950 | switch (subdevice_id) { |
9951 | case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: | |
740234f0 | 9952 | return true; |
5daebbb0 DS |
9953 | } |
9954 | break; | |
8e2813f5 JK |
9955 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
9956 | /* All except this subdevice support WOL */ | |
9957 | if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) | |
740234f0 | 9958 | return true; |
8e2813f5 JK |
9959 | break; |
9960 | case IXGBE_DEV_ID_82599_KX4: | |
740234f0 ET |
9961 | return true; |
9962 | default: | |
8e2813f5 JK |
9963 | break; |
9964 | } | |
9965 | ||
740234f0 | 9966 | return false; |
8e2813f5 JK |
9967 | } |
9968 | ||
9a799d71 AK |
9969 | /** |
9970 | * ixgbe_probe - Device Initialization Routine | |
9971 | * @pdev: PCI device information struct | |
9972 | * @ent: entry in ixgbe_pci_tbl | |
9973 | * | |
9974 | * Returns 0 on success, negative on failure | |
9975 | * | |
9976 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
9977 | * The OS initialization, configuring of the adapter private structure, | |
9978 | * and a hardware reset occur. | |
9979 | **/ | |
1dd06ae8 | 9980 | static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
9a799d71 AK |
9981 | { |
9982 | struct net_device *netdev; | |
9983 | struct ixgbe_adapter *adapter = NULL; | |
9984 | struct ixgbe_hw *hw; | |
9985 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
e027d1ae | 9986 | int i, err, pci_using_dac, expected_gts; |
d3cb9869 | 9987 | unsigned int indices = MAX_TX_QUEUES; |
289700db | 9988 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
b5b2ffc0 | 9989 | bool disable_dev = false; |
eacd73f7 YZ |
9990 | #ifdef IXGBE_FCOE |
9991 | u16 device_caps; | |
9992 | #endif | |
289700db | 9993 | u32 eec; |
9a799d71 | 9994 | |
bded64a7 AG |
9995 | /* Catch broken hardware that put the wrong VF device ID in |
9996 | * the PCIe SR-IOV capability. | |
9997 | */ | |
9998 | if (pdev->is_virtfn) { | |
9999 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
10000 | pci_name(pdev), pdev->vendor, pdev->device); | |
10001 | return -EINVAL; | |
10002 | } | |
10003 | ||
9ce77666 | 10004 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
10005 | if (err) |
10006 | return err; | |
10007 | ||
f5f2eda8 | 10008 | if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { |
9a799d71 AK |
10009 | pci_using_dac = 1; |
10010 | } else { | |
f5f2eda8 | 10011 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 10012 | if (err) { |
f5f2eda8 RK |
10013 | dev_err(&pdev->dev, |
10014 | "No usable DMA configuration, aborting\n"); | |
10015 | goto err_dma; | |
9a799d71 AK |
10016 | } |
10017 | pci_using_dac = 0; | |
10018 | } | |
10019 | ||
56d766d6 | 10020 | err = pci_request_mem_regions(pdev, ixgbe_driver_name); |
9a799d71 | 10021 | if (err) { |
b8bc0421 DC |
10022 | dev_err(&pdev->dev, |
10023 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
10024 | goto err_pci_reg; |
10025 | } | |
10026 | ||
19d5afd4 | 10027 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 10028 | |
9a799d71 | 10029 | pci_set_master(pdev); |
fb3b27bc | 10030 | pci_save_state(pdev); |
9a799d71 | 10031 | |
d3cb9869 | 10032 | if (ii->mac == ixgbe_mac_82598EB) { |
e901acd6 | 10033 | #ifdef CONFIG_IXGBE_DCB |
d3cb9869 AD |
10034 | /* 8 TC w/ 4 queues per TC */ |
10035 | indices = 4 * MAX_TRAFFIC_CLASS; | |
10036 | #else | |
10037 | indices = IXGBE_MAX_RSS_INDICES; | |
e901acd6 | 10038 | #endif |
d3cb9869 | 10039 | } |
e901acd6 | 10040 | |
c85a2618 | 10041 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
10042 | if (!netdev) { |
10043 | err = -ENOMEM; | |
10044 | goto err_alloc_etherdev; | |
10045 | } | |
10046 | ||
9a799d71 AK |
10047 | SET_NETDEV_DEV(netdev, &pdev->dev); |
10048 | ||
9a799d71 AK |
10049 | adapter = netdev_priv(netdev); |
10050 | ||
10051 | adapter->netdev = netdev; | |
10052 | adapter->pdev = pdev; | |
10053 | hw = &adapter->hw; | |
10054 | hw->back = adapter; | |
b3f4d599 | 10055 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9a799d71 | 10056 | |
05857980 | 10057 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 10058 | pci_resource_len(pdev, 0)); |
2a1a091c | 10059 | adapter->io_addr = hw->hw_addr; |
9a799d71 AK |
10060 | if (!hw->hw_addr) { |
10061 | err = -EIO; | |
10062 | goto err_ioremap; | |
10063 | } | |
10064 | ||
0edc3527 | 10065 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 10066 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 10067 | netdev->watchdog_timeo = 5 * HZ; |
339de30f | 10068 | strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); |
9a799d71 | 10069 | |
9a799d71 | 10070 | /* Setup hw api */ |
37689010 | 10071 | hw->mac.ops = *ii->mac_ops; |
021230d4 | 10072 | hw->mac.type = ii->mac; |
9a900eca | 10073 | hw->mvals = ii->mvals; |
b71f6c40 ET |
10074 | if (ii->link_ops) |
10075 | hw->link.ops = *ii->link_ops; | |
9a799d71 | 10076 | |
c44ade9e | 10077 | /* EEPROM */ |
37689010 | 10078 | hw->eeprom.ops = *ii->eeprom_ops; |
9a900eca | 10079 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
58cf663f MR |
10080 | if (ixgbe_removed(hw->hw_addr)) { |
10081 | err = -EIO; | |
10082 | goto err_ioremap; | |
10083 | } | |
c44ade9e | 10084 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ |
b4f47a48 | 10085 | if (!(eec & BIT(8))) |
c44ade9e JB |
10086 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; |
10087 | ||
10088 | /* PHY */ | |
37689010 | 10089 | hw->phy.ops = *ii->phy_ops; |
c4900be0 | 10090 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
10091 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
10092 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
10093 | hw->phy.mdio.mmds = 0; | |
10094 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
10095 | hw->phy.mdio.dev = netdev; | |
10096 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
10097 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 10098 | |
9a799d71 | 10099 | /* setup the private structure */ |
55570b6f | 10100 | err = ixgbe_sw_init(adapter, ii); |
9a799d71 AK |
10101 | if (err) |
10102 | goto err_sw_init; | |
10103 | ||
dbd15b8f DS |
10104 | /* Make sure the SWFW semaphore is in a valid state */ |
10105 | if (hw->mac.ops.init_swfw_sync) | |
10106 | hw->mac.ops.init_swfw_sync(hw); | |
10107 | ||
e86bff0e | 10108 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
10109 | switch (adapter->hw.mac.type) { |
10110 | case ixgbe_mac_82599EB: | |
10111 | case ixgbe_mac_X540: | |
9a75a1ac DS |
10112 | case ixgbe_mac_X550: |
10113 | case ixgbe_mac_X550EM_x: | |
49425dfc | 10114 | case ixgbe_mac_x550em_a: |
e86bff0e | 10115 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
10116 | break; |
10117 | default: | |
10118 | break; | |
10119 | } | |
e86bff0e | 10120 | |
bf069c97 DS |
10121 | /* |
10122 | * If there is a fan on this device and it has failed log the | |
10123 | * failure. | |
10124 | */ | |
10125 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
10126 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
10127 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 10128 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
10129 | } |
10130 | ||
8ef78adc PWJ |
10131 | if (allow_unsupported_sfp) |
10132 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
10133 | ||
c44ade9e | 10134 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 10135 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 10136 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 10137 | hw->phy.reset_if_overtemp = false; |
b3eb4e18 | 10138 | ixgbe_set_eee_capable(adapter); |
29a8dca1 | 10139 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
8ca783ab DS |
10140 | err = 0; |
10141 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
1b1bf31a DS |
10142 | e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); |
10143 | e_dev_err("Reload the driver after installing a supported module.\n"); | |
04f165ef PW |
10144 | goto err_sw_init; |
10145 | } else if (err) { | |
849c4542 | 10146 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
10147 | goto err_sw_init; |
10148 | } | |
10149 | ||
99d74487 | 10150 | #ifdef CONFIG_PCI_IOV |
60a1a680 GR |
10151 | /* SR-IOV not supported on the 82598 */ |
10152 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
10153 | goto skip_sriov; | |
10154 | /* Mailbox */ | |
10155 | ixgbe_init_mbx_params_pf(hw); | |
37689010 | 10156 | hw->mbx.ops = ii->mbx_ops; |
dcc23e3a | 10157 | pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); |
5c11f00d | 10158 | ixgbe_enable_sriov(adapter, max_vfs); |
60a1a680 | 10159 | skip_sriov: |
1cdd1ec8 | 10160 | |
99d74487 | 10161 | #endif |
396e799c | 10162 | netdev->features = NETIF_F_SG | |
082757af DS |
10163 | NETIF_F_TSO | |
10164 | NETIF_F_TSO6 | | |
082757af | 10165 | NETIF_F_RXHASH | |
49763de0 | 10166 | NETIF_F_RXCSUM | |
b83e3010 AD |
10167 | NETIF_F_HW_CSUM; |
10168 | ||
10169 | #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ | |
10170 | NETIF_F_GSO_GRE_CSUM | \ | |
7e13318d | 10171 | NETIF_F_GSO_IPXIP4 | \ |
bf2d1df3 | 10172 | NETIF_F_GSO_IPXIP6 | \ |
b83e3010 AD |
10173 | NETIF_F_GSO_UDP_TUNNEL | \ |
10174 | NETIF_F_GSO_UDP_TUNNEL_CSUM) | |
10175 | ||
10176 | netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; | |
10177 | netdev->features |= NETIF_F_GSO_PARTIAL | | |
10178 | IXGBE_GSO_PARTIAL_FEATURES; | |
ad31c402 | 10179 | |
49763de0 | 10180 | if (hw->mac.type >= ixgbe_mac_82599EB) |
53692b1d | 10181 | netdev->features |= NETIF_F_SCTP_CRC; |
49763de0 AD |
10182 | |
10183 | /* copy netdev features into list of user selectable features */ | |
b83e3010 | 10184 | netdev->hw_features |= netdev->features | |
3d951822 | 10185 | NETIF_F_HW_VLAN_CTAG_FILTER | |
b83e3010 AD |
10186 | NETIF_F_HW_VLAN_CTAG_RX | |
10187 | NETIF_F_HW_VLAN_CTAG_TX | | |
10188 | NETIF_F_RXALL | | |
49763de0 AD |
10189 | NETIF_F_HW_L2FW_DOFFLOAD; |
10190 | ||
10191 | if (hw->mac.type >= ixgbe_mac_82599EB) | |
10192 | netdev->hw_features |= NETIF_F_NTUPLE | | |
b82b17d9 | 10193 | NETIF_F_HW_TC; |
45a5ead0 | 10194 | |
b83e3010 AD |
10195 | if (pci_using_dac) |
10196 | netdev->features |= NETIF_F_HIGHDMA; | |
10197 | ||
5eee87cd AD |
10198 | netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; |
10199 | netdev->hw_enc_features |= netdev->vlan_features; | |
2a20525b SP |
10200 | netdev->mpls_features |= NETIF_F_SG | |
10201 | NETIF_F_TSO | | |
10202 | NETIF_F_TSO6 | | |
10203 | NETIF_F_HW_CSUM; | |
10204 | netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; | |
5eee87cd | 10205 | |
b83e3010 AD |
10206 | /* set this bit last since it cannot be part of vlan_features */ |
10207 | netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | | |
10208 | NETIF_F_HW_VLAN_CTAG_RX | | |
10209 | NETIF_F_HW_VLAN_CTAG_TX; | |
ad31c402 | 10210 | |
01789349 | 10211 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 10212 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 10213 | |
91c527a5 JW |
10214 | /* MTU range: 68 - 9710 */ |
10215 | netdev->min_mtu = ETH_MIN_MTU; | |
10216 | netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); | |
10217 | ||
7a6b6f51 | 10218 | #ifdef CONFIG_IXGBE_DCB |
8829009d | 10219 | if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) |
3f40c74c | 10220 | netdev->dcbnl_ops = &ixgbe_dcbnl_ops; |
2f90b865 AD |
10221 | #endif |
10222 | ||
eacd73f7 | 10223 | #ifdef IXGBE_FCOE |
0d551589 | 10224 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
d3cb9869 AD |
10225 | unsigned int fcoe_l; |
10226 | ||
eacd73f7 YZ |
10227 | if (hw->mac.ops.get_device_caps) { |
10228 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
10229 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
10230 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 | 10231 | } |
7c8ae65a | 10232 | |
d3cb9869 AD |
10233 | |
10234 | fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); | |
10235 | adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; | |
7c8ae65a | 10236 | |
a58915c7 AD |
10237 | netdev->features |= NETIF_F_FSO | |
10238 | NETIF_F_FCOE_CRC; | |
10239 | ||
7c8ae65a AD |
10240 | netdev->vlan_features |= NETIF_F_FSO | |
10241 | NETIF_F_FCOE_CRC | | |
10242 | NETIF_F_FCOE_MTU; | |
5e09d7f6 | 10243 | } |
eacd73f7 | 10244 | #endif /* IXGBE_FCOE */ |
9a799d71 | 10245 | |
082757af DS |
10246 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
10247 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 10248 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
10249 | netdev->features |= NETIF_F_LRO; |
10250 | ||
9a799d71 | 10251 | /* make sure the EEPROM is good */ |
c44ade9e | 10252 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 10253 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 | 10254 | err = -EIO; |
35937c05 | 10255 | goto err_sw_init; |
9a799d71 AK |
10256 | } |
10257 | ||
c7374b5a SV |
10258 | eth_platform_get_mac_address(&adapter->pdev->dev, |
10259 | adapter->hw.mac.perm_addr); | |
c762dff2 | 10260 | |
9a799d71 | 10261 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); |
9a799d71 | 10262 | |
aaeb6cdf | 10263 | if (!is_valid_ether_addr(netdev->dev_addr)) { |
849c4542 | 10264 | e_dev_err("invalid MAC address\n"); |
9a799d71 | 10265 | err = -EIO; |
35937c05 | 10266 | goto err_sw_init; |
9a799d71 AK |
10267 | } |
10268 | ||
56768045 TD |
10269 | /* Set hw->mac.addr to permanent MAC address */ |
10270 | ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); | |
c9f53e63 | 10271 | ixgbe_mac_set_default_filter(adapter); |
5d7daa35 | 10272 | |
7086400d | 10273 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
581330ba | 10274 | (unsigned long) adapter); |
9a799d71 | 10275 | |
58cf663f MR |
10276 | if (ixgbe_removed(hw->hw_addr)) { |
10277 | err = -EIO; | |
10278 | goto err_sw_init; | |
10279 | } | |
7086400d | 10280 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
58cf663f | 10281 | set_bit(__IXGBE_SERVICE_INITED, &adapter->state); |
7086400d | 10282 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); |
9a799d71 | 10283 | |
021230d4 AV |
10284 | err = ixgbe_init_interrupt_scheme(adapter); |
10285 | if (err) | |
10286 | goto err_sw_init; | |
9a799d71 | 10287 | |
b09457e7 LS |
10288 | for (i = 0; i < adapter->num_rx_queues; i++) |
10289 | u64_stats_init(&adapter->rx_ring[i]->syncp); | |
10290 | for (i = 0; i < adapter->num_tx_queues; i++) | |
10291 | u64_stats_init(&adapter->tx_ring[i]->syncp); | |
33fdc82f JF |
10292 | for (i = 0; i < adapter->num_xdp_queues; i++) |
10293 | u64_stats_init(&adapter->xdp_ring[i]->syncp); | |
10294 | ||
8e2813f5 | 10295 | /* WOL not supported for all devices */ |
c23f5b6b | 10296 | adapter->wol = 0; |
8e2813f5 | 10297 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); |
6b92b0ba | 10298 | hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, |
b8f83638 | 10299 | pdev->subsystem_device); |
6b92b0ba | 10300 | if (hw->wol_enabled) |
9417c464 | 10301 | adapter->wol = IXGBE_WUFC_MAG; |
c23f5b6b | 10302 | |
e8e26350 PW |
10303 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
10304 | ||
15e5209f ET |
10305 | /* save off EEPROM version number */ |
10306 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
10307 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
10308 | ||
04f165ef | 10309 | /* pick up the PCI bus settings for reporting later */ |
e027d1ae | 10310 | if (ixgbe_pcie_from_parent(hw)) |
b8e82001 | 10311 | ixgbe_get_parent_bus_info(adapter); |
f9328bc6 DS |
10312 | else |
10313 | hw->mac.ops.get_bus_info(hw); | |
04f165ef | 10314 | |
e027d1ae JK |
10315 | /* calculate the expected PCIe bandwidth required for optimal |
10316 | * performance. Note that some older parts will never have enough | |
10317 | * bandwidth due to being older generation PCIe parts. We clamp these | |
10318 | * parts to ensure no warning is displayed if it can't be fixed. | |
10319 | */ | |
10320 | switch (hw->mac.type) { | |
10321 | case ixgbe_mac_82598EB: | |
10322 | expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); | |
10323 | break; | |
10324 | default: | |
10325 | expected_gts = ixgbe_enumerate_functions(adapter) * 10; | |
10326 | break; | |
0c254d86 | 10327 | } |
caafb95d JK |
10328 | |
10329 | /* don't check link if we failed to enumerate functions */ | |
10330 | if (expected_gts > 0) | |
10331 | ixgbe_check_minimum_link(adapter, expected_gts); | |
0c254d86 | 10332 | |
339de30f | 10333 | err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); |
6a2aae5a | 10334 | if (err) |
339de30f | 10335 | strlcpy(part_str, "Unknown", sizeof(part_str)); |
6a2aae5a JK |
10336 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
10337 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", | |
10338 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
e7cf745b | 10339 | part_str); |
6a2aae5a JK |
10340 | else |
10341 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", | |
10342 | hw->mac.type, hw->phy.type, part_str); | |
10343 | ||
10344 | e_dev_info("%pM\n", netdev->dev_addr); | |
10345 | ||
9a799d71 | 10346 | /* reset the hardware with the new settings */ |
794caeb2 | 10347 | err = hw->mac.ops.start_hw(hw); |
794caeb2 PWJ |
10348 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
10349 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
10350 | e_dev_warn("This device is a pre-production adapter/LOM. " |
10351 | "Please be aware there may be issues associated " | |
10352 | "with your hardware. If you are experiencing " | |
10353 | "problems please contact your Intel or hardware " | |
10354 | "representative who provided you with this " | |
10355 | "hardware.\n"); | |
794caeb2 | 10356 | } |
9a799d71 AK |
10357 | strcpy(netdev->name, "eth%d"); |
10358 | err = register_netdev(netdev); | |
10359 | if (err) | |
10360 | goto err_register; | |
10361 | ||
0fb6a55c ET |
10362 | pci_set_drvdata(pdev, adapter); |
10363 | ||
ec74a471 ET |
10364 | /* power down the optics for 82599 SFP+ fiber */ |
10365 | if (hw->mac.ops.disable_tx_laser) | |
93d3ce8f ET |
10366 | hw->mac.ops.disable_tx_laser(hw); |
10367 | ||
54386467 JB |
10368 | /* carrier off reporting is important to ethtool even BEFORE open */ |
10369 | netif_carrier_off(netdev); | |
10370 | ||
5dd2d332 | 10371 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 10372 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 10373 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
10374 | ixgbe_setup_dca(adapter); |
10375 | } | |
10376 | #endif | |
1cdd1ec8 | 10377 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 10378 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
10379 | for (i = 0; i < adapter->num_vfs; i++) |
10380 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
10381 | } | |
10382 | ||
2466dd9c JK |
10383 | /* firmware requires driver version to be 0xFFFFFFFF |
10384 | * since os does not support feature | |
10385 | */ | |
9612de92 | 10386 | if (hw->mac.ops.set_fw_drv_ver) |
cb8e0514 TN |
10387 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, |
10388 | sizeof(ixgbe_driver_version) - 1, | |
10389 | ixgbe_driver_version); | |
9612de92 | 10390 | |
0365e6e4 PW |
10391 | /* add san mac addr to netdev */ |
10392 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 10393 | |
ea81875a | 10394 | e_dev_info("%s\n", ixgbe_default_device_descr); |
3ca8bc6d | 10395 | |
1210982b | 10396 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d DS |
10397 | if (ixgbe_sysfs_init(adapter)) |
10398 | e_err(probe, "failed to allocate sysfs resources\n"); | |
1210982b | 10399 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 10400 | |
00949167 | 10401 | ixgbe_dbg_adapter_init(adapter); |
00949167 | 10402 | |
d1a35ee2 ET |
10403 | /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ |
10404 | if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) | |
0b2679d6 DS |
10405 | hw->mac.ops.setup_link(hw, |
10406 | IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, | |
10407 | true); | |
10408 | ||
9a799d71 AK |
10409 | return 0; |
10410 | ||
10411 | err_register: | |
5eba3699 | 10412 | ixgbe_release_hw_control(adapter); |
7a921c93 | 10413 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 | 10414 | err_sw_init: |
99d74487 | 10415 | ixgbe_disable_sriov(adapter); |
7086400d | 10416 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
2a1a091c | 10417 | iounmap(adapter->io_addr); |
1cdaaf54 | 10418 | kfree(adapter->jump_tables[0]); |
5d7daa35 | 10419 | kfree(adapter->mac_table); |
3dfbfc7e | 10420 | kfree(adapter->rss_key); |
9a799d71 | 10421 | err_ioremap: |
b5b2ffc0 | 10422 | disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); |
9a799d71 AK |
10423 | free_netdev(netdev); |
10424 | err_alloc_etherdev: | |
56d766d6 | 10425 | pci_release_mem_regions(pdev); |
9a799d71 AK |
10426 | err_pci_reg: |
10427 | err_dma: | |
b5b2ffc0 | 10428 | if (!adapter || disable_dev) |
41c62843 | 10429 | pci_disable_device(pdev); |
9a799d71 AK |
10430 | return err; |
10431 | } | |
10432 | ||
10433 | /** | |
10434 | * ixgbe_remove - Device Removal Routine | |
10435 | * @pdev: PCI device information struct | |
10436 | * | |
10437 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
10438 | * that it should release a PCI device. The could be caused by a | |
10439 | * Hot-Plug event, or because the driver is going to be removed from | |
10440 | * memory. | |
10441 | **/ | |
9f9a12f8 | 10442 | static void ixgbe_remove(struct pci_dev *pdev) |
9a799d71 | 10443 | { |
c60fbb00 | 10444 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
0fb6a55c | 10445 | struct net_device *netdev; |
b5b2ffc0 | 10446 | bool disable_dev; |
1cdaaf54 | 10447 | int i; |
9a799d71 | 10448 | |
0fb6a55c ET |
10449 | /* if !adapter then we already cleaned up in probe */ |
10450 | if (!adapter) | |
10451 | return; | |
10452 | ||
10453 | netdev = adapter->netdev; | |
00949167 | 10454 | ixgbe_dbg_adapter_exit(adapter); |
00949167 | 10455 | |
09f40aed | 10456 | set_bit(__IXGBE_REMOVING, &adapter->state); |
7086400d | 10457 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 10458 | |
3a6a4eda | 10459 | |
5dd2d332 | 10460 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
10461 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
10462 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
10463 | dca_remove_requester(&pdev->dev); | |
9de7605e MR |
10464 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, |
10465 | IXGBE_DCA_CTRL_DCA_DISABLE); | |
bd0362dd JC |
10466 | } |
10467 | ||
10468 | #endif | |
1210982b | 10469 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d | 10470 | ixgbe_sysfs_exit(adapter); |
1210982b | 10471 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 10472 | |
0365e6e4 PW |
10473 | /* remove the added san mac */ |
10474 | ixgbe_del_sanmac_netdev(netdev); | |
10475 | ||
da36b647 | 10476 | #ifdef CONFIG_PCI_IOV |
7837e286 | 10477 | ixgbe_disable_sriov(adapter); |
da36b647 | 10478 | #endif |
6b010e9b AW |
10479 | if (netdev->reg_state == NETREG_REGISTERED) |
10480 | unregister_netdev(netdev); | |
10481 | ||
7a921c93 | 10482 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 10483 | |
021230d4 | 10484 | ixgbe_release_hw_control(adapter); |
9a799d71 | 10485 | |
2b1588c3 AD |
10486 | #ifdef CONFIG_DCB |
10487 | kfree(adapter->ixgbe_ieee_pfc); | |
10488 | kfree(adapter->ixgbe_ieee_ets); | |
10489 | ||
10490 | #endif | |
2a1a091c | 10491 | iounmap(adapter->io_addr); |
56d766d6 | 10492 | pci_release_mem_regions(pdev); |
9a799d71 | 10493 | |
849c4542 | 10494 | e_dev_info("complete\n"); |
021230d4 | 10495 | |
1cdaaf54 AN |
10496 | for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { |
10497 | if (adapter->jump_tables[i]) { | |
10498 | kfree(adapter->jump_tables[i]->input); | |
10499 | kfree(adapter->jump_tables[i]->mask); | |
10500 | } | |
10501 | kfree(adapter->jump_tables[i]); | |
10502 | } | |
10503 | ||
5d7daa35 | 10504 | kfree(adapter->mac_table); |
3dfbfc7e | 10505 | kfree(adapter->rss_key); |
b5b2ffc0 | 10506 | disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); |
9a799d71 AK |
10507 | free_netdev(netdev); |
10508 | ||
19d5afd4 | 10509 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 10510 | |
b5b2ffc0 | 10511 | if (disable_dev) |
41c62843 | 10512 | pci_disable_device(pdev); |
9a799d71 AK |
10513 | } |
10514 | ||
10515 | /** | |
10516 | * ixgbe_io_error_detected - called when PCI error is detected | |
10517 | * @pdev: Pointer to PCI device | |
10518 | * @state: The current pci connection state | |
10519 | * | |
10520 | * This function is called after a PCI bus error affecting | |
10521 | * this device has been detected. | |
10522 | */ | |
10523 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 10524 | pci_channel_state_t state) |
9a799d71 | 10525 | { |
c60fbb00 AD |
10526 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
10527 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 10528 | |
83c61fa9 | 10529 | #ifdef CONFIG_PCI_IOV |
14438464 | 10530 | struct ixgbe_hw *hw = &adapter->hw; |
83c61fa9 GR |
10531 | struct pci_dev *bdev, *vfdev; |
10532 | u32 dw0, dw1, dw2, dw3; | |
10533 | int vf, pos; | |
10534 | u16 req_id, pf_func; | |
10535 | ||
10536 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
10537 | adapter->num_vfs == 0) | |
10538 | goto skip_bad_vf_detection; | |
10539 | ||
10540 | bdev = pdev->bus->self; | |
62f87c0e | 10541 | while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) |
83c61fa9 GR |
10542 | bdev = bdev->bus->self; |
10543 | ||
10544 | if (!bdev) | |
10545 | goto skip_bad_vf_detection; | |
10546 | ||
10547 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
10548 | if (!pos) | |
10549 | goto skip_bad_vf_detection; | |
10550 | ||
14438464 MR |
10551 | dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); |
10552 | dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); | |
10553 | dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); | |
10554 | dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); | |
10555 | if (ixgbe_removed(hw->hw_addr)) | |
10556 | goto skip_bad_vf_detection; | |
83c61fa9 GR |
10557 | |
10558 | req_id = dw1 >> 16; | |
10559 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
10560 | if (!(req_id & 0x0080)) | |
10561 | goto skip_bad_vf_detection; | |
10562 | ||
10563 | pf_func = req_id & 0x01; | |
10564 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
10565 | unsigned int device_id; | |
10566 | ||
10567 | vf = (req_id & 0x7F) >> 1; | |
10568 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
10569 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
10570 | "%8.8x\tdw3: %8.8x\n", | |
10571 | dw0, dw1, dw2, dw3); | |
10572 | switch (adapter->hw.mac.type) { | |
10573 | case ixgbe_mac_82599EB: | |
10574 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
10575 | break; | |
10576 | case ixgbe_mac_X540: | |
10577 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
10578 | break; | |
9a75a1ac DS |
10579 | case ixgbe_mac_X550: |
10580 | device_id = IXGBE_DEV_ID_X550_VF; | |
10581 | break; | |
10582 | case ixgbe_mac_X550EM_x: | |
10583 | device_id = IXGBE_DEV_ID_X550EM_X_VF; | |
10584 | break; | |
49425dfc MR |
10585 | case ixgbe_mac_x550em_a: |
10586 | device_id = IXGBE_DEV_ID_X550EM_A_VF; | |
10587 | break; | |
83c61fa9 GR |
10588 | default: |
10589 | device_id = 0; | |
10590 | break; | |
10591 | } | |
10592 | ||
10593 | /* Find the pci device of the offending VF */ | |
36e90319 | 10594 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); |
83c61fa9 GR |
10595 | while (vfdev) { |
10596 | if (vfdev->devfn == (req_id & 0xFF)) | |
10597 | break; | |
36e90319 | 10598 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
83c61fa9 GR |
10599 | device_id, vfdev); |
10600 | } | |
10601 | /* | |
10602 | * There's a slim chance the VF could have been hot plugged, | |
10603 | * so if it is no longer present we don't need to issue the | |
10604 | * VFLR. Just clean up the AER in that case. | |
10605 | */ | |
10606 | if (vfdev) { | |
63af8f7a | 10607 | pcie_flr(vfdev); |
b4fafbe9 GR |
10608 | /* Free device reference count */ |
10609 | pci_dev_put(vfdev); | |
83c61fa9 GR |
10610 | } |
10611 | ||
10612 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
10613 | } | |
10614 | ||
10615 | /* | |
10616 | * Even though the error may have occurred on the other port | |
10617 | * we still need to increment the vf error reference count for | |
10618 | * both ports because the I/O resume function will be called | |
10619 | * for both of them. | |
10620 | */ | |
10621 | adapter->vferr_refcount++; | |
10622 | ||
10623 | return PCI_ERS_RESULT_RECOVERED; | |
10624 | ||
10625 | skip_bad_vf_detection: | |
10626 | #endif /* CONFIG_PCI_IOV */ | |
58cf663f MR |
10627 | if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) |
10628 | return PCI_ERS_RESULT_DISCONNECT; | |
10629 | ||
41c62843 | 10630 | rtnl_lock(); |
9a799d71 AK |
10631 | netif_device_detach(netdev); |
10632 | ||
41c62843 MR |
10633 | if (state == pci_channel_io_perm_failure) { |
10634 | rtnl_unlock(); | |
3044b8d1 | 10635 | return PCI_ERS_RESULT_DISCONNECT; |
41c62843 | 10636 | } |
3044b8d1 | 10637 | |
9a799d71 | 10638 | if (netif_running(netdev)) |
126db13f | 10639 | ixgbe_close_suspend(adapter); |
41c62843 MR |
10640 | |
10641 | if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) | |
10642 | pci_disable_device(pdev); | |
10643 | rtnl_unlock(); | |
9a799d71 | 10644 | |
b4617240 | 10645 | /* Request a slot reset. */ |
9a799d71 AK |
10646 | return PCI_ERS_RESULT_NEED_RESET; |
10647 | } | |
10648 | ||
10649 | /** | |
10650 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
10651 | * @pdev: Pointer to PCI device | |
10652 | * | |
10653 | * Restart the card from scratch, as if from a cold-boot. | |
10654 | */ | |
10655 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
10656 | { | |
c60fbb00 | 10657 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
10658 | pci_ers_result_t result; |
10659 | int err; | |
9a799d71 | 10660 | |
9ce77666 | 10661 | if (pci_enable_device_mem(pdev)) { |
396e799c | 10662 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
10663 | result = PCI_ERS_RESULT_DISCONNECT; |
10664 | } else { | |
4e857c58 | 10665 | smp_mb__before_atomic(); |
41c62843 | 10666 | clear_bit(__IXGBE_DISABLED, &adapter->state); |
0391bbe3 | 10667 | adapter->hw.hw_addr = adapter->io_addr; |
6fabd715 PWJ |
10668 | pci_set_master(pdev); |
10669 | pci_restore_state(pdev); | |
c0e1f68b | 10670 | pci_save_state(pdev); |
9a799d71 | 10671 | |
dd4d8ca6 | 10672 | pci_wake_from_d3(pdev, false); |
9a799d71 | 10673 | |
6fabd715 | 10674 | ixgbe_reset(adapter); |
88512539 | 10675 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
10676 | result = PCI_ERS_RESULT_RECOVERED; |
10677 | } | |
10678 | ||
10679 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
10680 | if (err) { | |
849c4542 ET |
10681 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
10682 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
10683 | /* non-fatal, continue */ |
10684 | } | |
9a799d71 | 10685 | |
6fabd715 | 10686 | return result; |
9a799d71 AK |
10687 | } |
10688 | ||
10689 | /** | |
10690 | * ixgbe_io_resume - called when traffic can start flowing again. | |
10691 | * @pdev: Pointer to PCI device | |
10692 | * | |
10693 | * This callback is called when the error recovery driver tells us that | |
10694 | * its OK to resume normal operation. | |
10695 | */ | |
10696 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
10697 | { | |
c60fbb00 AD |
10698 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
10699 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 10700 | |
83c61fa9 GR |
10701 | #ifdef CONFIG_PCI_IOV |
10702 | if (adapter->vferr_refcount) { | |
10703 | e_info(drv, "Resuming after VF err\n"); | |
10704 | adapter->vferr_refcount--; | |
10705 | return; | |
10706 | } | |
10707 | ||
10708 | #endif | |
126db13f | 10709 | rtnl_lock(); |
c7ccde0f | 10710 | if (netif_running(netdev)) |
126db13f | 10711 | ixgbe_open(netdev); |
9a799d71 AK |
10712 | |
10713 | netif_device_attach(netdev); | |
126db13f | 10714 | rtnl_unlock(); |
9a799d71 AK |
10715 | } |
10716 | ||
3646f0e5 | 10717 | static const struct pci_error_handlers ixgbe_err_handler = { |
9a799d71 AK |
10718 | .error_detected = ixgbe_io_error_detected, |
10719 | .slot_reset = ixgbe_io_slot_reset, | |
10720 | .resume = ixgbe_io_resume, | |
10721 | }; | |
10722 | ||
10723 | static struct pci_driver ixgbe_driver = { | |
10724 | .name = ixgbe_driver_name, | |
10725 | .id_table = ixgbe_pci_tbl, | |
10726 | .probe = ixgbe_probe, | |
9f9a12f8 | 10727 | .remove = ixgbe_remove, |
9a799d71 AK |
10728 | #ifdef CONFIG_PM |
10729 | .suspend = ixgbe_suspend, | |
10730 | .resume = ixgbe_resume, | |
10731 | #endif | |
10732 | .shutdown = ixgbe_shutdown, | |
da36b647 | 10733 | .sriov_configure = ixgbe_pci_sriov_configure, |
9a799d71 AK |
10734 | .err_handler = &ixgbe_err_handler |
10735 | }; | |
10736 | ||
10737 | /** | |
10738 | * ixgbe_init_module - Driver Registration Routine | |
10739 | * | |
10740 | * ixgbe_init_module is the first routine called when the driver is | |
10741 | * loaded. All it does is register with the PCI subsystem. | |
10742 | **/ | |
10743 | static int __init ixgbe_init_module(void) | |
10744 | { | |
10745 | int ret; | |
c7689578 | 10746 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 10747 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 10748 | |
780484d8 MR |
10749 | ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); |
10750 | if (!ixgbe_wq) { | |
10751 | pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); | |
10752 | return -ENOMEM; | |
10753 | } | |
10754 | ||
00949167 | 10755 | ixgbe_dbg_init(); |
00949167 | 10756 | |
f01fc1a8 JK |
10757 | ret = pci_register_driver(&ixgbe_driver); |
10758 | if (ret) { | |
6b836879 | 10759 | destroy_workqueue(ixgbe_wq); |
f01fc1a8 | 10760 | ixgbe_dbg_exit(); |
f01fc1a8 JK |
10761 | return ret; |
10762 | } | |
10763 | ||
5dd2d332 | 10764 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 10765 | dca_register_notify(&dca_notifier); |
bd0362dd | 10766 | #endif |
5dd2d332 | 10767 | |
f01fc1a8 | 10768 | return 0; |
9a799d71 | 10769 | } |
b4617240 | 10770 | |
9a799d71 AK |
10771 | module_init(ixgbe_init_module); |
10772 | ||
10773 | /** | |
10774 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
10775 | * | |
10776 | * ixgbe_exit_module is called just before the driver is removed | |
10777 | * from memory. | |
10778 | **/ | |
10779 | static void __exit ixgbe_exit_module(void) | |
10780 | { | |
5dd2d332 | 10781 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
10782 | dca_unregister_notify(&dca_notifier); |
10783 | #endif | |
9a799d71 | 10784 | pci_unregister_driver(&ixgbe_driver); |
00949167 | 10785 | |
00949167 | 10786 | ixgbe_dbg_exit(); |
780484d8 MR |
10787 | if (ixgbe_wq) { |
10788 | destroy_workqueue(ixgbe_wq); | |
10789 | ixgbe_wq = NULL; | |
10790 | } | |
9a799d71 | 10791 | } |
bd0362dd | 10792 | |
5dd2d332 | 10793 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 10794 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 10795 | void *p) |
bd0362dd JC |
10796 | { |
10797 | int ret_val; | |
10798 | ||
10799 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 10800 | __ixgbe_notify_dca); |
bd0362dd JC |
10801 | |
10802 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
10803 | } | |
b453368d | 10804 | |
5dd2d332 | 10805 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 10806 | |
9a799d71 AK |
10807 | module_exit(ixgbe_exit_module); |
10808 | ||
10809 | /* ixgbe_main.c */ |