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bridge: Use is_link_local() in store_group_addr()
[linux-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
815cccbf 47#include <linux/if_bridge.h>
70c71606 48#include <linux/prefetch.h>
eacd73f7 49#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 50
51#include "ixgbe.h"
52#include "ixgbe_common.h"
ee5f784a 53#include "ixgbe_dcb_82599.h"
1cdd1ec8 54#include "ixgbe_sriov.h"
9a799d71
AK		 55
56char ixgbe_driver_name[] = "ixgbe";
9c8eb720 57static const char ixgbe_driver_string[] =
e8e9f696 58 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 59#ifdef IXGBE_FCOE
ea81875a
NP		 60char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 62#else
63static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65#endif
75e3d3c6 66#define MAJ 3
eef4560f
DS		 67#define MIN 9
68#define BUILD 15
75e3d3c6 69#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 70 __stringify(BUILD) "-k"
9c8eb720 71const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 72static const char ixgbe_copyright[] =
94971820 73 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 74
75static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 76 [board_82598] = &ixgbe_82598_info,
e8e26350 77 [board_82599] = &ixgbe_82599_info,
fe15e8e1 78 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 79};
80
81/* ixgbe_pci_tbl - PCI Device ID Table
82 *
83 * Wildcard entries (PCI_ANY_ID) should come last
84 * Last entry must be all 0s
85 *
86 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
87 * Class, Class Mask, private data (not used) }
88 */
a3aa1884 89static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 119 /* required last entry */
120 {0, }
121};
122MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
123
5dd2d332 124#ifdef CONFIG_IXGBE_DCA
bd0362dd 125static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 126 void *p);
bd0362dd
JC		 127static struct notifier_block dca_notifier = {
128 .notifier_call = ixgbe_notify_dca,
129 .next = NULL,
130 .priority = 0
131};
132#endif
133
1cdd1ec8
GR		 134#ifdef CONFIG_PCI_IOV
135static unsigned int max_vfs;
136module_param(max_vfs, uint, 0);
e8e9f696 137MODULE_PARM_DESC(max_vfs,
6b42a9c5 138 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 139#endif /* CONFIG_PCI_IOV */
140
8ef78adc
PWJ		 141static unsigned int allow_unsupported_sfp;
142module_param(allow_unsupported_sfp, uint, 0);
143MODULE_PARM_DESC(allow_unsupported_sfp,
144 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
145
b3f4d599 146#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
147static int debug = -1;
148module_param(debug, int, 0);
149MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
150
9a799d71
AK		 151MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
152MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
153MODULE_LICENSE("GPL");
154MODULE_VERSION(DRV_VERSION);
155
7086400d
AD		 156static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
157{
158 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
159 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
160 schedule_work(&adapter->service_task);
161}
162
163static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
164{
165 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
166
52f33af8 167 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 168 smp_mb__before_clear_bit();
169 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
170}
171
dcd79aeb
TI		 172struct ixgbe_reg_info {
173 u32 ofs;
174 char *name;
175};
176
177static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
178
179 /* General Registers */
180 {IXGBE_CTRL, "CTRL"},
181 {IXGBE_STATUS, "STATUS"},
182 {IXGBE_CTRL_EXT, "CTRL_EXT"},
183
184 /* Interrupt Registers */
185 {IXGBE_EICR, "EICR"},
186
187 /* RX Registers */
188 {IXGBE_SRRCTL(0), "SRRCTL"},
189 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
190 {IXGBE_RDLEN(0), "RDLEN"},
191 {IXGBE_RDH(0), "RDH"},
192 {IXGBE_RDT(0), "RDT"},
193 {IXGBE_RXDCTL(0), "RXDCTL"},
194 {IXGBE_RDBAL(0), "RDBAL"},
195 {IXGBE_RDBAH(0), "RDBAH"},
196
197 /* TX Registers */
198 {IXGBE_TDBAL(0), "TDBAL"},
199 {IXGBE_TDBAH(0), "TDBAH"},
200 {IXGBE_TDLEN(0), "TDLEN"},
201 {IXGBE_TDH(0), "TDH"},
202 {IXGBE_TDT(0), "TDT"},
203 {IXGBE_TXDCTL(0), "TXDCTL"},
204
205 /* List Terminator */
206 {}
207};
208
209
210/*
211 * ixgbe_regdump - register printout routine
212 */
213static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
214{
215 int i = 0, j = 0;
216 char rname[16];
217 u32 regs[64];
218
219 switch (reginfo->ofs) {
220 case IXGBE_SRRCTL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
223 break;
224 case IXGBE_DCA_RXCTRL(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
227 break;
228 case IXGBE_RDLEN(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
231 break;
232 case IXGBE_RDH(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
235 break;
236 case IXGBE_RDT(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
239 break;
240 case IXGBE_RXDCTL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
243 break;
244 case IXGBE_RDBAL(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
247 break;
248 case IXGBE_RDBAH(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
251 break;
252 case IXGBE_TDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
255 break;
256 case IXGBE_TDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
259 break;
260 case IXGBE_TDLEN(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
263 break;
264 case IXGBE_TDH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
267 break;
268 case IXGBE_TDT(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
271 break;
272 case IXGBE_TXDCTL(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
275 break;
276 default:
c7689578 277 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 278 IXGBE_READ_REG(hw, reginfo->ofs));
279 return;
280 }
281
282 for (i = 0; i < 8; i++) {
283 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 284 pr_err("%-15s", rname);
dcd79aeb 285 for (j = 0; j < 8; j++)
c7689578
JP		 286 pr_cont(" %08x", regs[i*8+j]);
287 pr_cont("\n");
dcd79aeb
TI		 288 }
289
290}
291
292/*
293 * ixgbe_dump - Print registers, tx-rings and rx-rings
294 */
295static void ixgbe_dump(struct ixgbe_adapter *adapter)
296{
297 struct net_device *netdev = adapter->netdev;
298 struct ixgbe_hw *hw = &adapter->hw;
299 struct ixgbe_reg_info *reginfo;
300 int n = 0;
301 struct ixgbe_ring *tx_ring;
729739b7 302 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 303 union ixgbe_adv_tx_desc *tx_desc;
304 struct my_u0 { u64 a; u64 b; } *u0;
305 struct ixgbe_ring *rx_ring;
306 union ixgbe_adv_rx_desc *rx_desc;
307 struct ixgbe_rx_buffer *rx_buffer_info;
308 u32 staterr;
309 int i = 0;
310
311 if (!netif_msg_hw(adapter))
312 return;
313
314 /* Print netdevice Info */
315 if (netdev) {
316 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 317 pr_info("Device Name state "
dcd79aeb 318 "trans_start last_rx\n");
c7689578
JP		 319 pr_info("%-15s %016lX %016lX %016lX\n",
320 netdev->name,
321 netdev->state,
322 netdev->trans_start,
323 netdev->last_rx);
dcd79aeb
TI		 324 }
325
326 /* Print Registers */
327 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 328 pr_info(" Register Name Value\n");
dcd79aeb
TI		 329 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
330 reginfo->name; reginfo++) {
331 ixgbe_regdump(hw, reginfo);
332 }
333
334 /* Print TX Ring Summary */
335 if (!netdev || !netif_running(netdev))
336 goto exit;
337
338 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 339 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 340 for (n = 0; n < adapter->num_tx_queues; n++) {
341 tx_ring = adapter->tx_ring[n];
729739b7 342 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 343 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 344 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 345 (u64)dma_unmap_addr(tx_buffer, dma),
346 dma_unmap_len(tx_buffer, len),
347 tx_buffer->next_to_watch,
348 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 349 }
350
351 /* Print TX Rings */
352 if (!netif_msg_tx_done(adapter))
353 goto rx_ring_summary;
354
355 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
356
357 /* Transmit Descriptor Formats
358 *
39ac868a 359 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 360 * +--------------------------------------------------------------+
361 * 0 | Buffer Address [63:0] |
362 * +--------------------------------------------------------------+
39ac868a 363 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 364 * +--------------------------------------------------------------+
365 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 366 *
367 * 82598 Advanced Transmit Descriptor (Write-Back Format)
368 * +--------------------------------------------------------------+
369 * 0 | RSV [63:0] |
370 * +--------------------------------------------------------------+
371 * 8 | RSV | STA | NXTSEQ |
372 * +--------------------------------------------------------------+
373 * 63 36 35 32 31 0
374 *
375 * 82599+ Advanced Transmit Descriptor
376 * +--------------------------------------------------------------+
377 * 0 | Buffer Address [63:0] |
378 * +--------------------------------------------------------------+
379 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
380 * +--------------------------------------------------------------+
381 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
382 *
383 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
384 * +--------------------------------------------------------------+
385 * 0 | RSV [63:0] |
386 * +--------------------------------------------------------------+
387 * 8 | RSV | STA | RSV |
388 * +--------------------------------------------------------------+
389 * 63 36 35 32 31 0
dcd79aeb
TI		 390 */
391
392 for (n = 0; n < adapter->num_tx_queues; n++) {
393 tx_ring = adapter->tx_ring[n];
c7689578
JP		 394 pr_info("------------------------------------\n");
395 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
396 pr_info("------------------------------------\n");
397 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 398 "[PlPOIdStDDt Ln] [bi->dma ] "
399 "leng ntw timestamp bi->skb\n");
400
401 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 402 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 403 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 404 u0 = (struct my_u0 *)tx_desc;
c7689578 405 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 406 " %04X %p %016llX %p", i,
dcd79aeb
TI		 407 le64_to_cpu(u0->a),
408 le64_to_cpu(u0->b),
729739b7
AD		 409 (u64)dma_unmap_addr(tx_buffer, dma),
410 dma_unmap_len(tx_buffer, len),
411 tx_buffer->next_to_watch,
412 (u64)tx_buffer->time_stamp,
413 tx_buffer->skb);
dcd79aeb
TI		 414 if (i == tx_ring->next_to_use &&
415 i == tx_ring->next_to_clean)
c7689578 416 pr_cont(" NTC/U\n");
dcd79aeb 417 else if (i == tx_ring->next_to_use)
c7689578 418 pr_cont(" NTU\n");
dcd79aeb 419 else if (i == tx_ring->next_to_clean)
c7689578 420 pr_cont(" NTC\n");
dcd79aeb 421 else
c7689578 422 pr_cont("\n");
dcd79aeb
TI		 423
424 if (netif_msg_pktdata(adapter) &&
9c50c035 425 tx_buffer->skb)
dcd79aeb
TI		 426 print_hex_dump(KERN_INFO, "",
427 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035 428 tx_buffer->skb->data,
729739b7
AD		 429 dma_unmap_len(tx_buffer, len),
430 true);
dcd79aeb
TI		 431 }
432 }
433
434 /* Print RX Rings Summary */
435rx_ring_summary:
436 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 437 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 438 for (n = 0; n < adapter->num_rx_queues; n++) {
439 rx_ring = adapter->rx_ring[n];
c7689578
JP		 440 pr_info("%5d %5X %5X\n",
441 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 442 }
443
444 /* Print RX Rings */
445 if (!netif_msg_rx_status(adapter))
446 goto exit;
447
448 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
449
39ac868a
JH		 450 /* Receive Descriptor Formats
451 *
452 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 453 * 63 1 0
454 * +-----------------------------------------------------+
455 * 0 | Packet Buffer Address [63:1] |A0/NSE|
456 * +----------------------------------------------+------+
457 * 8 | Header Buffer Address [63:1] | DD |
458 * +-----------------------------------------------------+
459 *
460 *
39ac868a 461 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 462 *
463 * 63 48 47 32 31 30 21 20 16 15 4 3 0
464 * +------------------------------------------------------+
39ac868a
JH		 465 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
466 * | Packet | IP | | | | Type | Type |
467 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 468 * +------------------------------------------------------+
469 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
470 * +------------------------------------------------------+
471 * 63 48 47 32 31 20 19 0
39ac868a
JH		 472 *
473 * 82599+ Advanced Receive Descriptor (Read) Format
474 * 63 1 0
475 * +-----------------------------------------------------+
476 * 0 | Packet Buffer Address [63:1] |A0/NSE|
477 * +----------------------------------------------+------+
478 * 8 | Header Buffer Address [63:1] | DD |
479 * +-----------------------------------------------------+
480 *
481 *
482 * 82599+ Advanced Receive Descriptor (Write-Back) Format
483 *
484 * 63 48 47 32 31 30 21 20 17 16 4 3 0
485 * +------------------------------------------------------+
486 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
487 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
488 * |/ Flow Dir Flt ID | | | | | |
489 * +------------------------------------------------------+
490 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
491 * +------------------------------------------------------+
492 * 63 48 47 32 31 20 19 0
dcd79aeb 493 */
39ac868a 494
dcd79aeb
TI		 495 for (n = 0; n < adapter->num_rx_queues; n++) {
496 rx_ring = adapter->rx_ring[n];
c7689578
JP		 497 pr_info("------------------------------------\n");
498 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
499 pr_info("------------------------------------\n");
500 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 501 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
502 "<-- Adv Rx Read format\n");
c7689578 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 504 "[vl er S cks ln] ---------------- [bi->skb] "
505 "<-- Adv Rx Write-Back format\n");
506
507 for (i = 0; i < rx_ring->count; i++) {
508 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 509 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 510 u0 = (struct my_u0 *)rx_desc;
511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512 if (staterr & IXGBE_RXD_STAT_DD) {
513 /* Descriptor Done */
c7689578 514 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 515 "%016llX ---------------- %p", i,
516 le64_to_cpu(u0->a),
517 le64_to_cpu(u0->b),
518 rx_buffer_info->skb);
519 } else {
c7689578 520 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 521 "%016llX %016llX %p", i,
522 le64_to_cpu(u0->a),
523 le64_to_cpu(u0->b),
524 (u64)rx_buffer_info->dma,
525 rx_buffer_info->skb);
526
9c50c035
ET		 527 if (netif_msg_pktdata(adapter) &&
528 rx_buffer_info->dma) {
dcd79aeb
TI		 529 print_hex_dump(KERN_INFO, "",
530 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 531 page_address(rx_buffer_info->page) +
532 rx_buffer_info->page_offset,
f800326d 533 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 534 }
535 }
536
537 if (i == rx_ring->next_to_use)
c7689578 538 pr_cont(" NTU\n");
dcd79aeb 539 else if (i == rx_ring->next_to_clean)
c7689578 540 pr_cont(" NTC\n");
dcd79aeb 541 else
c7689578 542 pr_cont("\n");
dcd79aeb
TI		 543
544 }
545 }
546
547exit:
548 return;
549}
550
5eba3699
AV		 551static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
552{
553 u32 ctrl_ext;
554
555 /* Let firmware take over control of h/w */
556 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
557 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 558 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 559}
560
561static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
562{
563 u32 ctrl_ext;
564
565 /* Let firmware know the driver has taken over */
566 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 568 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 569}
9a799d71 570
49ce9c2c 571/**
e8e26350
PW		 572 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
573 * @adapter: pointer to adapter struct
574 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
575 * @queue: queue to map the corresponding interrupt to
576 * @msix_vector: the vector to map to the corresponding queue
577 *
578 */
579static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 580 u8 queue, u8 msix_vector)
9a799d71
AK		 581{
582 u32 ivar, index;
e8e26350
PW		 583 struct ixgbe_hw *hw = &adapter->hw;
584 switch (hw->mac.type) {
585 case ixgbe_mac_82598EB:
586 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
587 if (direction == -1)
588 direction = 0;
589 index = (((direction * 64) + queue) >> 2) & 0x1F;
590 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
591 ivar &= ~(0xFF << (8 * (queue & 0x3)));
592 ivar |= (msix_vector << (8 * (queue & 0x3)));
593 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
594 break;
595 case ixgbe_mac_82599EB:
b93a2226 596 case ixgbe_mac_X540:
e8e26350
PW		 597 if (direction == -1) {
598 /* other causes */
599 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
600 index = ((queue & 1) * 8);
601 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
602 ivar &= ~(0xFF << index);
603 ivar |= (msix_vector << index);
604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
605 break;
606 } else {
607 /* tx or rx causes */
608 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
609 index = ((16 * (queue & 1)) + (8 * direction));
610 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
611 ivar &= ~(0xFF << index);
612 ivar |= (msix_vector << index);
613 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
614 break;
615 }
616 default:
617 break;
618 }
9a799d71
AK		 619}
620
fe49f04a 621static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 622 u64 qmask)
fe49f04a
AD		 623{
624 u32 mask;
625
bd508178
AD		 626 switch (adapter->hw.mac.type) {
627 case ixgbe_mac_82598EB:
fe49f04a
AD		 628 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 630 break;
631 case ixgbe_mac_82599EB:
b93a2226 632 case ixgbe_mac_X540:
fe49f04a
AD		 633 mask = (qmask & 0xFFFFFFFF);
634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
635 mask = (qmask >> 32);
636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 637 break;
638 default:
639 break;
fe49f04a
AD		 640 }
641}
642
729739b7
AD		 643void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
644 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 645{
729739b7
AD		 646 if (tx_buffer->skb) {
647 dev_kfree_skb_any(tx_buffer->skb);
648 if (dma_unmap_len(tx_buffer, len))
d3d00239 649 dma_unmap_single(ring->dev,
729739b7
AD		 650 dma_unmap_addr(tx_buffer, dma),
651 dma_unmap_len(tx_buffer, len),
652 DMA_TO_DEVICE);
653 } else if (dma_unmap_len(tx_buffer, len)) {
654 dma_unmap_page(ring->dev,
655 dma_unmap_addr(tx_buffer, dma),
656 dma_unmap_len(tx_buffer, len),
657 DMA_TO_DEVICE);
e5a43549 658 }
729739b7
AD		 659 tx_buffer->next_to_watch = NULL;
660 tx_buffer->skb = NULL;
661 dma_unmap_len_set(tx_buffer, len, 0);
662 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 663}
664
943561d3 665static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 666{
667 struct ixgbe_hw *hw = &adapter->hw;
668 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 669 int i;
943561d3 670 u32 data;
c84d324c 671
943561d3
AD		 672 if ((hw->fc.current_mode != ixgbe_fc_full) &&
673 (hw->fc.current_mode != ixgbe_fc_rx_pause))
674 return;
c84d324c 675
943561d3
AD		 676 switch (hw->mac.type) {
677 case ixgbe_mac_82598EB:
678 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
679 break;
680 default:
681 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
682 }
683 hwstats->lxoffrxc += data;
c84d324c 684
943561d3
AD		 685 /* refill credits (no tx hang) if we received xoff */
686 if (!data)
c84d324c 687 return;
943561d3
AD		 688
689 for (i = 0; i < adapter->num_tx_queues; i++)
690 clear_bit(__IXGBE_HANG_CHECK_ARMED,
691 &adapter->tx_ring[i]->state);
692}
693
694static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
695{
696 struct ixgbe_hw *hw = &adapter->hw;
697 struct ixgbe_hw_stats *hwstats = &adapter->stats;
698 u32 xoff[8] = {0};
699 int i;
700 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
701
702 if (adapter->ixgbe_ieee_pfc)
703 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
704
705 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
706 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 707 return;
943561d3 708 }
c84d324c
JF		 709
710 /* update stats for each tc, only valid with PFC enabled */
711 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
712 switch (hw->mac.type) {
713 case ixgbe_mac_82598EB:
714 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 715 break;
c84d324c
JF		 716 default:
717 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 718 }
c84d324c
JF		 719 hwstats->pxoffrxc[i] += xoff[i];
720 }
721
722 /* disarm tx queues that have received xoff frames */
723 for (i = 0; i < adapter->num_tx_queues; i++) {
724 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 725 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 726
727 if (xoff[tc])
728 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 729 }
26f23d82
YZ		 730}
731
c84d324c 732static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 733{
7d7ce682 734 return ring->stats.packets;
c84d324c
JF		 735}
736
737static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
738{
739 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 740 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 741
c84d324c
JF		 742 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
743 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
744
745 if (head != tail)
746 return (head < tail) ?
747 tail - head : (tail + ring->count - head);
748
749 return 0;
750}
751
752static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
753{
754 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
755 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
756 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
757 bool ret = false;
758
7d637bcc 759 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 760
761 /*
762 * Check for a hung queue, but be thorough. This verifies
763 * that a transmit has been completed since the previous
764 * check AND there is at least one packet pending. The
765 * ARMED bit is set to indicate a potential hang. The
766 * bit is cleared if a pause frame is received to remove
767 * false hang detection due to PFC or 802.3x frames. By
768 * requiring this to fail twice we avoid races with
769 * pfc clearing the ARMED bit and conditions where we
770 * run the check_tx_hang logic with a transmit completion
771 * pending but without time to complete it yet.
772 */
773 if ((tx_done_old == tx_done) && tx_pending) {
774 /* make sure it is true for two checks in a row */
775 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
776 &tx_ring->state);
777 } else {
778 /* update completed stats and continue */
779 tx_ring->tx_stats.tx_done_old = tx_done;
780 /* reset the countdown */
781 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 782 }
783
c84d324c 784 return ret;
9a799d71
AK		 785}
786
c83c6cbd
AD		 787/**
788 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
789 * @adapter: driver private struct
790 **/
791static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
792{
793
794 /* Do the reset outside of interrupt context */
795 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
796 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
797 ixgbe_service_event_schedule(adapter);
798 }
799}
e01c31a5 800
9a799d71
AK		 801/**
802 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 803 * @q_vector: structure containing interrupt and ring information
e01c31a5 804 * @tx_ring: tx ring to clean
9a799d71 805 **/
fe49f04a 806static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 807 struct ixgbe_ring *tx_ring)
9a799d71 808{
fe49f04a 809 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 810 struct ixgbe_tx_buffer *tx_buffer;
811 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 812 unsigned int total_bytes = 0, total_packets = 0;
59224555 813 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 814 unsigned int i = tx_ring->next_to_clean;
815
816 if (test_bit(__IXGBE_DOWN, &adapter->state))
817 return true;
9a799d71 818
d3d00239 819 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 820 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 821 i -= tx_ring->count;
12207e49 822
729739b7 823 do {
d3d00239
AD		 824 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
825
826 /* if next_to_watch is not set then there is no work pending */
827 if (!eop_desc)
828 break;
829
7f83a9e6
AD		 830 /* prevent any other reads prior to eop_desc */
831 rmb();
832
d3d00239
AD		 833 /* if DD is not set pending work has not been completed */
834 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
835 break;
8ad494b0 836
d3d00239
AD		 837 /* clear next_to_watch to prevent false hangs */
838 tx_buffer->next_to_watch = NULL;
8ad494b0 839
091a6246
AD		 840 /* update the statistics for this packet */
841 total_bytes += tx_buffer->bytecount;
842 total_packets += tx_buffer->gso_segs;
843
0ede4a60
JK		 844 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
845 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
0ede4a60 846
fd0db0ed
AD		 847 /* free the skb */
848 dev_kfree_skb_any(tx_buffer->skb);
849
729739b7
AD		 850 /* unmap skb header data */
851 dma_unmap_single(tx_ring->dev,
852 dma_unmap_addr(tx_buffer, dma),
853 dma_unmap_len(tx_buffer, len),
854 DMA_TO_DEVICE);
855
fd0db0ed
AD		 856 /* clear tx_buffer data */
857 tx_buffer->skb = NULL;
729739b7 858 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 859
729739b7
AD		 860 /* unmap remaining buffers */
861 while (tx_desc != eop_desc) {
d3d00239
AD		 862 tx_buffer++;
863 tx_desc++;
8ad494b0 864 i++;
729739b7
AD		 865 if (unlikely(!i)) {
866 i -= tx_ring->count;
d3d00239 867 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 868 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 869 }
e01c31a5 870
729739b7
AD		 871 /* unmap any remaining paged data */
872 if (dma_unmap_len(tx_buffer, len)) {
873 dma_unmap_page(tx_ring->dev,
874 dma_unmap_addr(tx_buffer, dma),
875 dma_unmap_len(tx_buffer, len),
876 DMA_TO_DEVICE);
877 dma_unmap_len_set(tx_buffer, len, 0);
878 }
879 }
880
881 /* move us one more past the eop_desc for start of next pkt */
882 tx_buffer++;
883 tx_desc++;
884 i++;
885 if (unlikely(!i)) {
886 i -= tx_ring->count;
887 tx_buffer = tx_ring->tx_buffer_info;
888 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
889 }
890
891 /* issue prefetch for next Tx descriptor */
892 prefetch(tx_desc);
12207e49 893
729739b7
AD		 894 /* update budget accounting */
895 budget--;
896 } while (likely(budget));
897
898 i += tx_ring->count;
9a799d71 899 tx_ring->next_to_clean = i;
d3d00239 900 u64_stats_update_begin(&tx_ring->syncp);
b953799e 901 tx_ring->stats.bytes += total_bytes;
bd198058 902 tx_ring->stats.packets += total_packets;
d3d00239 903 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 904 q_vector->tx.total_bytes += total_bytes;
905 q_vector->tx.total_packets += total_packets;
b953799e 906
c84d324c
JF		 907 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
908 /* schedule immediate reset if we believe we hung */
909 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 910 e_err(drv, "Detected Tx Unit Hang\n"
911 " Tx Queue <%d>\n"
912 " TDH, TDT <%x>, <%x>\n"
913 " next_to_use <%x>\n"
914 " next_to_clean <%x>\n"
915 "tx_buffer_info[next_to_clean]\n"
916 " time_stamp <%lx>\n"
917 " jiffies <%lx>\n",
918 tx_ring->queue_index,
919 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
920 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 921 tx_ring->next_to_use, i,
922 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 923
924 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
925
926 e_info(probe,
927 "tx hang %d detected on queue %d, resetting adapter\n",
928 adapter->tx_timeout_count + 1, tx_ring->queue_index);
929
b953799e 930 /* schedule immediate reset if we believe we hung */
c83c6cbd 931 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 932
933 /* the adapter is about to reset, no point in enabling stuff */
59224555 934 return true;
b953799e 935 }
9a799d71 936
b2d96e0a
AD		 937 netdev_tx_completed_queue(txring_txq(tx_ring),
938 total_packets, total_bytes);
939
e092be60 940#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 941 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 942 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 943 /* Make sure that anybody stopping the queue after this
944 * sees the new next_to_clean.
945 */
946 smp_mb();
729739b7
AD		 947 if (__netif_subqueue_stopped(tx_ring->netdev,
948 tx_ring->queue_index)
949 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
950 netif_wake_subqueue(tx_ring->netdev,
951 tx_ring->queue_index);
5b7da515 952 ++tx_ring->tx_stats.restart_queue;
30eba97a 953 }
e092be60 954 }
9a799d71 955
59224555 956 return !!budget;
9a799d71
AK		 957}
958
5dd2d332 959#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 960static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
961 struct ixgbe_ring *tx_ring,
33cf09c9 962 int cpu)
bd0362dd 963{
33cf09c9 964 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 965 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
966 u16 reg_offset;
33cf09c9 967
33cf09c9
AD		 968 switch (hw->mac.type) {
969 case ixgbe_mac_82598EB:
bdda1a61 970 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 971 break;
972 case ixgbe_mac_82599EB:
b93a2226 973 case ixgbe_mac_X540:
bdda1a61
AD		 974 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
975 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 976 break;
977 default:
bdda1a61
AD		 978 /* for unknown hardware do not write register */
979 return;
bd0362dd 980 }
bdda1a61
AD		 981
982 /*
983 * We can enable relaxed ordering for reads, but not writes when
984 * DCA is enabled. This is due to a known issue in some chipsets
985 * which will cause the DCA tag to be cleared.
986 */
987 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
988 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
989 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
990
991 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 992}
993
bdda1a61
AD		 994static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
995 struct ixgbe_ring *rx_ring,
33cf09c9 996 int cpu)
bd0362dd 997{
33cf09c9 998 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 999 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1000 u8 reg_idx = rx_ring->reg_idx;
1001
33cf09c9
AD		 1002
1003 switch (hw->mac.type) {
33cf09c9 1004 case ixgbe_mac_82599EB:
b93a2226 1005 case ixgbe_mac_X540:
bdda1a61 1006 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1007 break;
1008 default:
1009 break;
1010 }
bdda1a61
AD		 1011
1012 /*
1013 * We can enable relaxed ordering for reads, but not writes when
1014 * DCA is enabled. This is due to a known issue in some chipsets
1015 * which will cause the DCA tag to be cleared.
1016 */
1017 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1018 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1019 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1020
1021 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1022}
1023
1024static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1025{
1026 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1027 struct ixgbe_ring *ring;
bd0362dd 1028 int cpu = get_cpu();
bd0362dd 1029
33cf09c9
AD		 1030 if (q_vector->cpu == cpu)
1031 goto out_no_update;
1032
a557928e 1033 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1034 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1035
a557928e 1036 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1037 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1038
1039 q_vector->cpu = cpu;
1040out_no_update:
bd0362dd
JC		 1041 put_cpu();
1042}
1043
1044static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1045{
1046 int i;
1047
1048 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1049 return;
1050
e35ec126
AD		 1051 /* always use CB2 mode, difference is masked in the CB driver */
1052 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1053
49c7ffbe 1054 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1055 adapter->q_vector[i]->cpu = -1;
1056 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1057 }
1058}
1059
1060static int __ixgbe_notify_dca(struct device *dev, void *data)
1061{
c60fbb00 1062 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1063 unsigned long event = *(unsigned long *)data;
1064
2a72c31e 1065 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1066 return 0;
1067
bd0362dd
JC		 1068 switch (event) {
1069 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1070 /* if we're already enabled, don't do it again */
1071 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1072 break;
652f093f 1073 if (dca_add_requester(dev) == 0) {
96b0e0f6 1074 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1075 ixgbe_setup_dca(adapter);
1076 break;
1077 }
1078 /* Fall Through since DCA is disabled. */
1079 case DCA_PROVIDER_REMOVE:
1080 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1081 dca_remove_requester(dev);
1082 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1083 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1084 }
1085 break;
1086 }
1087
652f093f 1088 return 0;
bd0362dd 1089}
67a74ee2 1090
bdda1a61 1091#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1092static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1093 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1094 struct sk_buff *skb)
1095{
8a0da21b
AD		 1096 if (ring->netdev->features & NETIF_F_RXHASH)
1097 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1098}
1099
f800326d 1100#ifdef IXGBE_FCOE
ff886dfc
AD		 1101/**
1102 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1103 * @ring: structure containing ring specific data
ff886dfc
AD		 1104 * @rx_desc: advanced rx descriptor
1105 *
1106 * Returns : true if it is FCoE pkt
1107 */
57efd44c 1108static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1109 union ixgbe_adv_rx_desc *rx_desc)
1110{
1111 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1112
57efd44c 1113 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1114 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1115 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1116 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1117}
1118
f800326d 1119#endif /* IXGBE_FCOE */
e59bd25d
AV		 1120/**
1121 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1122 * @ring: structure containing ring specific data
1123 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1124 * @skb: skb currently being received and modified
1125 **/
8a0da21b 1126static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1127 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1128 struct sk_buff *skb)
9a799d71 1129{
8a0da21b 1130 skb_checksum_none_assert(skb);
9a799d71 1131
712744be 1132 /* Rx csum disabled */
8a0da21b 1133 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1134 return;
e59bd25d
AV		 1135
1136 /* if IP and error */
f56e0cb1
AD		 1137 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1138 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1139 ring->rx_stats.csum_err++;
9a799d71
AK		 1140 return;
1141 }
e59bd25d 1142
f56e0cb1 1143 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1144 return;
1145
f56e0cb1 1146 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1147 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1148
1149 /*
1150 * 82599 errata, UDP frames with a 0 checksum can be marked as
1151 * checksum errors.
1152 */
8a0da21b
AD		 1153 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1154 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1155 return;
1156
8a0da21b 1157 ring->rx_stats.csum_err++;
e59bd25d
AV		 1158 return;
1159 }
1160
9a799d71 1161 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1162 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1163}
1164
84ea2591 1165static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1166{
f56e0cb1 1167 rx_ring->next_to_use = val;
f800326d
AD		 1168
1169 /* update next to alloc since we have filled the ring */
1170 rx_ring->next_to_alloc = val;
e8e26350
PW		 1171 /*
1172 * Force memory writes to complete before letting h/w
1173 * know there are new descriptors to fetch. (Only
1174 * applicable for weak-ordered memory model archs,
1175 * such as IA-64).
1176 */
1177 wmb();
84ea2591 1178 writel(val, rx_ring->tail);
e8e26350
PW		 1179}
1180
f990b79b
AD		 1181static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1182 struct ixgbe_rx_buffer *bi)
1183{
1184 struct page *page = bi->page;
f800326d 1185 dma_addr_t dma = bi->dma;
f990b79b 1186
f800326d
AD		 1187 /* since we are recycling buffers we should seldom need to alloc */
1188 if (likely(dma))
f990b79b
AD		 1189 return true;
1190
f800326d
AD		 1191 /* alloc new page for storage */
1192 if (likely(!page)) {
0614002b
MG		 1193 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1194 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1195 if (unlikely(!page)) {
1196 rx_ring->rx_stats.alloc_rx_page_failed++;
1197 return false;
1198 }
f800326d 1199 bi->page = page;
f990b79b
AD		 1200 }
1201
f800326d
AD		 1202 /* map page for use */
1203 dma = dma_map_page(rx_ring->dev, page, 0,
1204 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1205
1206 /*
1207 * if mapping failed free memory back to system since
1208 * there isn't much point in holding memory we can't use
1209 */
1210 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1211 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1212 bi->page = NULL;
f990b79b 1213
f990b79b
AD		 1214 rx_ring->rx_stats.alloc_rx_page_failed++;
1215 return false;
1216 }
1217
f800326d 1218 bi->dma = dma;
afaa9459 1219 bi->page_offset = 0;
f800326d 1220
f990b79b
AD		 1221 return true;
1222}
1223
9a799d71 1224/**
f990b79b 1225 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1226 * @rx_ring: ring to place buffers on
1227 * @cleaned_count: number of buffers to replace
9a799d71 1228 **/
fc77dc3c 1229void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1230{
9a799d71 1231 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1232 struct ixgbe_rx_buffer *bi;
d5f398ed 1233 u16 i = rx_ring->next_to_use;
9a799d71 1234
f800326d
AD		 1235 /* nothing to do */
1236 if (!cleaned_count)
fc77dc3c
AD		 1237 return;
1238
e4f74028 1239 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1240 bi = &rx_ring->rx_buffer_info[i];
1241 i -= rx_ring->count;
9a799d71 1242
f800326d
AD		 1243 do {
1244 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1245 break;
d5f398ed 1246
f800326d
AD		 1247 /*
1248 * Refresh the desc even if buffer_addrs didn't change
1249 * because each write-back erases this info.
1250 */
1251 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1252
f990b79b
AD		 1253 rx_desc++;
1254 bi++;
9a799d71 1255 i++;
f990b79b 1256 if (unlikely(!i)) {
e4f74028 1257 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1258 bi = rx_ring->rx_buffer_info;
1259 i -= rx_ring->count;
1260 }
1261
1262 /* clear the hdr_addr for the next_to_use descriptor */
1263 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1264
1265 cleaned_count--;
1266 } while (cleaned_count);
7c6e0a43 1267
f990b79b
AD		 1268 i += rx_ring->count;
1269
f56e0cb1 1270 if (rx_ring->next_to_use != i)
84ea2591 1271 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1272}
1273
1d2024f6
AD		 1274/**
1275 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1276 * @data: pointer to the start of the headers
1277 * @max_len: total length of section to find headers in
1278 *
1279 * This function is meant to determine the length of headers that will
1280 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1281 * motivation of doing this is to only perform one pull for IPv4 TCP
1282 * packets so that we can do basic things like calculating the gso_size
1283 * based on the average data per packet.
1284 **/
1285static unsigned int ixgbe_get_headlen(unsigned char *data,
1286 unsigned int max_len)
1287{
1288 union {
1289 unsigned char *network;
1290 /* l2 headers */
1291 struct ethhdr *eth;
1292 struct vlan_hdr *vlan;
1293 /* l3 headers */
1294 struct iphdr *ipv4;
a048b40e 1295 struct ipv6hdr *ipv6;
1d2024f6
AD		 1296 } hdr;
1297 __be16 protocol;
1298 u8 nexthdr = 0; /* default to not TCP */
1299 u8 hlen;
1300
1301 /* this should never happen, but better safe than sorry */
1302 if (max_len < ETH_HLEN)
1303 return max_len;
1304
1305 /* initialize network frame pointer */
1306 hdr.network = data;
1307
1308 /* set first protocol and move network header forward */
1309 protocol = hdr.eth->h_proto;
1310 hdr.network += ETH_HLEN;
1311
1312 /* handle any vlan tag if present */
1313 if (protocol == __constant_htons(ETH_P_8021Q)) {
1314 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1315 return max_len;
1316
1317 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1318 hdr.network += VLAN_HLEN;
1319 }
1320
1321 /* handle L3 protocols */
1322 if (protocol == __constant_htons(ETH_P_IP)) {
1323 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1324 return max_len;
1325
1326 /* access ihl as a u8 to avoid unaligned access on ia64 */
1327 hlen = (hdr.network[0] & 0x0F) << 2;
1328
1329 /* verify hlen meets minimum size requirements */
1330 if (hlen < sizeof(struct iphdr))
1331 return hdr.network - data;
1332
1333 /* record next protocol */
1334 nexthdr = hdr.ipv4->protocol;
1335 hdr.network += hlen;
a048b40e
AD		 1336 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1337 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1338 return max_len;
1339
1340 /* record next protocol */
1341 nexthdr = hdr.ipv6->nexthdr;
1342 hdr.network += sizeof(struct ipv6hdr);
f800326d 1343#ifdef IXGBE_FCOE
1d2024f6
AD		 1344 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1345 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1346 return max_len;
1347 hdr.network += FCOE_HEADER_LEN;
1348#endif
1349 } else {
1350 return hdr.network - data;
1351 }
1352
a048b40e 1353 /* finally sort out TCP/UDP */
1d2024f6
AD		 1354 if (nexthdr == IPPROTO_TCP) {
1355 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1356 return max_len;
1357
1358 /* access doff as a u8 to avoid unaligned access on ia64 */
1359 hlen = (hdr.network[12] & 0xF0) >> 2;
1360
1361 /* verify hlen meets minimum size requirements */
1362 if (hlen < sizeof(struct tcphdr))
1363 return hdr.network - data;
1364
1365 hdr.network += hlen;
a048b40e
AD		 1366 } else if (nexthdr == IPPROTO_UDP) {
1367 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1368 return max_len;
1369
1370 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1371 }
1372
1373 /*
1374 * If everything has gone correctly hdr.network should be the
1375 * data section of the packet and will be the end of the header.
1376 * If not then it probably represents the end of the last recognized
1377 * header.
1378 */
1379 if ((hdr.network - data) < max_len)
1380 return hdr.network - data;
1381 else
1382 return max_len;
1383}
1384
1d2024f6
AD		 1385static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1386 struct sk_buff *skb)
1387{
f800326d 1388 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1389
1390 /* set gso_size to avoid messing up TCP MSS */
1391 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1392 IXGBE_CB(skb)->append_cnt);
1393}
1394
1395static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1396 struct sk_buff *skb)
1397{
1398 /* if append_cnt is 0 then frame is not RSC */
1399 if (!IXGBE_CB(skb)->append_cnt)
1400 return;
1401
1402 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1403 rx_ring->rx_stats.rsc_flush++;
1404
1405 ixgbe_set_rsc_gso_size(rx_ring, skb);
1406
1407 /* gso_size is computed using append_cnt so always clear it last */
1408 IXGBE_CB(skb)->append_cnt = 0;
1409}
1410
8a0da21b
AD		 1411/**
1412 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1413 * @rx_ring: rx descriptor ring packet is being transacted on
1414 * @rx_desc: pointer to the EOP Rx descriptor
1415 * @skb: pointer to current skb being populated
f8212f97 1416 *
8a0da21b
AD		 1417 * This function checks the ring, descriptor, and packet information in
1418 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1419 * other fields within the skb.
f8212f97 1420 **/
8a0da21b
AD		 1421static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1422 union ixgbe_adv_rx_desc *rx_desc,
1423 struct sk_buff *skb)
f8212f97 1424{
43e95f11
JF		 1425 struct net_device *dev = rx_ring->netdev;
1426
8a0da21b
AD		 1427 ixgbe_update_rsc_stats(rx_ring, skb);
1428
1429 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1430
8a0da21b
AD		 1431 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1432
1d1a79b5 1433 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda 1434
43e95f11
JF		 1435 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1436 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1437 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1438 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1439 }
1440
8a0da21b 1441 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1442
43e95f11 1443 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1444}
1445
8a0da21b
AD		 1446static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1447 struct sk_buff *skb)
aa80175a 1448{
8a0da21b
AD		 1449 struct ixgbe_adapter *adapter = q_vector->adapter;
1450
1451 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1452 napi_gro_receive(&q_vector->napi, skb);
1453 else
1454 netif_rx(skb);
aa80175a 1455}
43634e82 1456
f800326d
AD		 1457/**
1458 * ixgbe_is_non_eop - process handling of non-EOP buffers
1459 * @rx_ring: Rx ring being processed
1460 * @rx_desc: Rx descriptor for current buffer
1461 * @skb: Current socket buffer containing buffer in progress
1462 *
1463 * This function updates next to clean. If the buffer is an EOP buffer
1464 * this function exits returning false, otherwise it will place the
1465 * sk_buff in the next buffer to be chained and return true indicating
1466 * that this is in fact a non-EOP buffer.
1467 **/
1468static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1469 union ixgbe_adv_rx_desc *rx_desc,
1470 struct sk_buff *skb)
1471{
1472 u32 ntc = rx_ring->next_to_clean + 1;
1473
1474 /* fetch, update, and store next to clean */
1475 ntc = (ntc < rx_ring->count) ? ntc : 0;
1476 rx_ring->next_to_clean = ntc;
1477
1478 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1479
5a02cbd1
AD		 1480 /* update RSC append count if present */
1481 if (ring_is_rsc_enabled(rx_ring)) {
1482 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1483 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1484
1485 if (unlikely(rsc_enabled)) {
1486 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1487
1488 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1489 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1490
5a02cbd1
AD		 1491 /* update ntc based on RSC value */
1492 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1493 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1494 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1495 }
f800326d
AD		 1496 }
1497
5a02cbd1
AD		 1498 /* if we are the last buffer then there is nothing else to do */
1499 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1500 return false;
1501
f800326d
AD		 1502 /* place skb in next buffer to be received */
1503 rx_ring->rx_buffer_info[ntc].skb = skb;
1504 rx_ring->rx_stats.non_eop_descs++;
1505
1506 return true;
1507}
1508
19861ce2
AD		 1509/**
1510 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1511 * @rx_ring: rx descriptor ring packet is being transacted on
1512 * @skb: pointer to current skb being adjusted
1513 *
1514 * This function is an ixgbe specific version of __pskb_pull_tail. The
1515 * main difference between this version and the original function is that
1516 * this function can make several assumptions about the state of things
1517 * that allow for significant optimizations versus the standard function.
1518 * As a result we can do things like drop a frag and maintain an accurate
1519 * truesize for the skb.
1520 */
1521static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1522 struct sk_buff *skb)
1523{
1524 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1525 unsigned char *va;
1526 unsigned int pull_len;
1527
1528 /*
1529 * it is valid to use page_address instead of kmap since we are
1530 * working with pages allocated out of the lomem pool per
1531 * alloc_page(GFP_ATOMIC)
1532 */
1533 va = skb_frag_address(frag);
1534
1535 /*
1536 * we need the header to contain the greater of either ETH_HLEN or
1537 * 60 bytes if the skb->len is less than 60 for skb_pad.
1538 */
cf3fe7ac 1539 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1540
1541 /* align pull length to size of long to optimize memcpy performance */
1542 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1543
1544 /* update all of the pointers */
1545 skb_frag_size_sub(frag, pull_len);
1546 frag->page_offset += pull_len;
1547 skb->data_len -= pull_len;
1548 skb->tail += pull_len;
19861ce2
AD		 1549}
1550
42073d91
AD		 1551/**
1552 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1553 * @rx_ring: rx descriptor ring packet is being transacted on
1554 * @skb: pointer to current skb being updated
1555 *
1556 * This function provides a basic DMA sync up for the first fragment of an
1557 * skb. The reason for doing this is that the first fragment cannot be
1558 * unmapped until we have reached the end of packet descriptor for a buffer
1559 * chain.
1560 */
1561static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1562 struct sk_buff *skb)
1563{
1564 /* if the page was released unmap it, else just sync our portion */
1565 if (unlikely(IXGBE_CB(skb)->page_released)) {
1566 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1567 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1568 IXGBE_CB(skb)->page_released = false;
1569 } else {
1570 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1571
1572 dma_sync_single_range_for_cpu(rx_ring->dev,
1573 IXGBE_CB(skb)->dma,
1574 frag->page_offset,
1575 ixgbe_rx_bufsz(rx_ring),
1576 DMA_FROM_DEVICE);
1577 }
1578 IXGBE_CB(skb)->dma = 0;
1579}
1580
f800326d
AD		 1581/**
1582 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1583 * @rx_ring: rx descriptor ring packet is being transacted on
1584 * @rx_desc: pointer to the EOP Rx descriptor
1585 * @skb: pointer to current skb being fixed
1586 *
1587 * Check for corrupted packet headers caused by senders on the local L2
1588 * embedded NIC switch not setting up their Tx Descriptors right. These
1589 * should be very rare.
1590 *
1591 * Also address the case where we are pulling data in on pages only
1592 * and as such no data is present in the skb header.
1593 *
1594 * In addition if skb is not at least 60 bytes we need to pad it so that
1595 * it is large enough to qualify as a valid Ethernet frame.
1596 *
1597 * Returns true if an error was encountered and skb was freed.
1598 **/
1599static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1600 union ixgbe_adv_rx_desc *rx_desc,
1601 struct sk_buff *skb)
1602{
f800326d 1603 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1604
1605 /* verify that the packet does not have any known errors */
1606 if (unlikely(ixgbe_test_staterr(rx_desc,
1607 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1608 !(netdev->features & NETIF_F_RXALL))) {
1609 dev_kfree_skb_any(skb);
1610 return true;
1611 }
1612
19861ce2 1613 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1614 if (skb_is_nonlinear(skb))
1615 ixgbe_pull_tail(rx_ring, skb);
f800326d 1616
57efd44c
AD		 1617#ifdef IXGBE_FCOE
1618 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1619 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1620 return false;
1621
1622#endif
f800326d
AD		 1623 /* if skb_pad returns an error the skb was freed */
1624 if (unlikely(skb->len < 60)) {
1625 int pad_len = 60 - skb->len;
1626
1627 if (skb_pad(skb, pad_len))
1628 return true;
1629 __skb_put(skb, pad_len);
1630 }
1631
1632 return false;
1633}
1634
f800326d
AD		 1635/**
1636 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1637 * @rx_ring: rx descriptor ring to store buffers on
1638 * @old_buff: donor buffer to have page reused
1639 *
0549ae20 1640 * Synchronizes page for reuse by the adapter
f800326d
AD		 1641 **/
1642static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1643 struct ixgbe_rx_buffer *old_buff)
1644{
1645 struct ixgbe_rx_buffer *new_buff;
1646 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1647
1648 new_buff = &rx_ring->rx_buffer_info[nta];
1649
1650 /* update, and store next to alloc */
1651 nta++;
1652 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1653
1654 /* transfer page from old buffer to new buffer */
1655 new_buff->page = old_buff->page;
1656 new_buff->dma = old_buff->dma;
0549ae20 1657 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1658
1659 /* sync the buffer for use by the device */
1660 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1661 new_buff->page_offset,
1662 ixgbe_rx_bufsz(rx_ring),
f800326d 1663 DMA_FROM_DEVICE);
f800326d
AD		 1664}
1665
1666/**
1667 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1668 * @rx_ring: rx descriptor ring to transact packets on
1669 * @rx_buffer: buffer containing page to add
1670 * @rx_desc: descriptor containing length of buffer written by hardware
1671 * @skb: sk_buff to place the data into
1672 *
0549ae20
AD		 1673 * This function will add the data contained in rx_buffer->page to the skb.
1674 * This is done either through a direct copy if the data in the buffer is
1675 * less than the skb header size, otherwise it will just attach the page as
1676 * a frag to the skb.
1677 *
1678 * The function will then update the page offset if necessary and return
1679 * true if the buffer can be reused by the adapter.
f800326d 1680 **/
0549ae20 1681static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1682 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1683 union ixgbe_adv_rx_desc *rx_desc,
1684 struct sk_buff *skb)
f800326d 1685{
0549ae20
AD		 1686 struct page *page = rx_buffer->page;
1687 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1688#if (PAGE_SIZE < 8192)
0549ae20 1689 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1690#else
1691 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1692 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1693 ixgbe_rx_bufsz(rx_ring);
1694#endif
0549ae20 1695
cf3fe7ac
AD		 1696 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1697 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1698
1699 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1700
1701 /* we can reuse buffer as-is, just make sure it is local */
1702 if (likely(page_to_nid(page) == numa_node_id()))
1703 return true;
1704
1705 /* this page cannot be reused so discard it */
1706 put_page(page);
1707 return false;
1708 }
1709
0549ae20
AD		 1710 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1711 rx_buffer->page_offset, size, truesize);
1712
09816fbe
AD		 1713 /* avoid re-using remote pages */
1714 if (unlikely(page_to_nid(page) != numa_node_id()))
1715 return false;
1716
1717#if (PAGE_SIZE < 8192)
1718 /* if we are only owner of page we can reuse it */
1719 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1720 return false;
1721
1722 /* flip page offset to other buffer */
1723 rx_buffer->page_offset ^= truesize;
1724
09816fbe
AD		 1725 /*
1726 * since we are the only owner of the page and we need to
1727 * increment it, just set the value to 2 in order to avoid
1728 * an unecessary locked operation
1729 */
1730 atomic_set(&page->_count, 2);
1731#else
1732 /* move offset up to the next cache line */
1733 rx_buffer->page_offset += truesize;
1734
1735 if (rx_buffer->page_offset > last_offset)
1736 return false;
1737
0549ae20
AD		 1738 /* bump ref count on page before it is given to the stack */
1739 get_page(page);
09816fbe 1740#endif
0549ae20
AD		 1741
1742 return true;
f800326d
AD		 1743}
1744
18806c9e
AD		 1745static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1746 union ixgbe_adv_rx_desc *rx_desc)
1747{
1748 struct ixgbe_rx_buffer *rx_buffer;
1749 struct sk_buff *skb;
1750 struct page *page;
1751
1752 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1753 page = rx_buffer->page;
1754 prefetchw(page);
1755
1756 skb = rx_buffer->skb;
1757
1758 if (likely(!skb)) {
1759 void *page_addr = page_address(page) +
1760 rx_buffer->page_offset;
1761
1762 /* prefetch first cache line of first page */
1763 prefetch(page_addr);
1764#if L1_CACHE_BYTES < 128
1765 prefetch(page_addr + L1_CACHE_BYTES);
1766#endif
1767
1768 /* allocate a skb to store the frags */
1769 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1770 IXGBE_RX_HDR_SIZE);
1771 if (unlikely(!skb)) {
1772 rx_ring->rx_stats.alloc_rx_buff_failed++;
1773 return NULL;
1774 }
1775
1776 /*
1777 * we will be copying header into skb->data in
1778 * pskb_may_pull so it is in our interest to prefetch
1779 * it now to avoid a possible cache miss
1780 */
1781 prefetchw(skb->data);
1782
1783 /*
1784 * Delay unmapping of the first packet. It carries the
1785 * header information, HW may still access the header
1786 * after the writeback. Only unmap it when EOP is
1787 * reached
1788 */
1789 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1790 goto dma_sync;
1791
1792 IXGBE_CB(skb)->dma = rx_buffer->dma;
1793 } else {
1794 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1795 ixgbe_dma_sync_frag(rx_ring, skb);
1796
1797dma_sync:
1798 /* we are reusing so sync this buffer for CPU use */
1799 dma_sync_single_range_for_cpu(rx_ring->dev,
1800 rx_buffer->dma,
1801 rx_buffer->page_offset,
1802 ixgbe_rx_bufsz(rx_ring),
1803 DMA_FROM_DEVICE);
1804 }
1805
1806 /* pull page into skb */
1807 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1808 /* hand second half of page back to the ring */
1809 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1810 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1811 /* the page has been released from the ring */
1812 IXGBE_CB(skb)->page_released = true;
1813 } else {
1814 /* we are not reusing the buffer so unmap it */
1815 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1816 ixgbe_rx_pg_size(rx_ring),
1817 DMA_FROM_DEVICE);
1818 }
1819
1820 /* clear contents of buffer_info */
1821 rx_buffer->skb = NULL;
1822 rx_buffer->dma = 0;
1823 rx_buffer->page = NULL;
1824
1825 return skb;
f800326d
AD		 1826}
1827
1828/**
1829 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1830 * @q_vector: structure containing interrupt and ring information
1831 * @rx_ring: rx descriptor ring to transact packets on
1832 * @budget: Total limit on number of packets to process
1833 *
1834 * This function provides a "bounce buffer" approach to Rx interrupt
1835 * processing. The advantage to this is that on systems that have
1836 * expensive overhead for IOMMU access this provides a means of avoiding
1837 * it by maintaining the mapping of the page to the syste.
1838 *
1839 * Returns true if all work is completed without reaching budget
1840 **/
4ff7fb12 1841static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1842 struct ixgbe_ring *rx_ring,
f4de00ed 1843 const int budget)
9a799d71 1844{
d2f4fbe2 1845 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1846#ifdef IXGBE_FCOE
f800326d 1847 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1848 int ddp_bytes;
1849 unsigned int mss = 0;
3d8fd385 1850#endif /* IXGBE_FCOE */
f800326d 1851 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1852
f800326d 1853 do {
f800326d
AD		 1854 union ixgbe_adv_rx_desc *rx_desc;
1855 struct sk_buff *skb;
f800326d
AD		 1856
1857 /* return some buffers to hardware, one at a time is too slow */
1858 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1859 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1860 cleaned_count = 0;
1861 }
1862
18806c9e 1863 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 1864
1865 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1866 break;
9a799d71 1867
f800326d
AD		 1868 /*
1869 * This memory barrier is needed to keep us from reading
1870 * any other fields out of the rx_desc until we know the
1871 * RXD_STAT_DD bit is set
1872 */
1873 rmb();
9a799d71 1874
18806c9e
AD		 1875 /* retrieve a buffer from the ring */
1876 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 1877
18806c9e
AD		 1878 /* exit if we failed to retrieve a buffer */
1879 if (!skb)
1880 break;
9a799d71 1881
9a799d71 1882 cleaned_count++;
f8212f97 1883
f800326d
AD		 1884 /* place incomplete frames back on ring for completion */
1885 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1886 continue;
c267fc16 1887
f800326d
AD		 1888 /* verify the packet layout is correct */
1889 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1890 continue;
9a799d71 1891
d2f4fbe2
AV		 1892 /* probably a little skewed due to removing CRC */
1893 total_rx_bytes += skb->len;
d2f4fbe2 1894
8a0da21b
AD		 1895 /* populate checksum, timestamp, VLAN, and protocol */
1896 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1897
332d4a7d
YZ		 1898#ifdef IXGBE_FCOE
1899 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1900 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1901 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 1902 /* include DDPed FCoE data */
1903 if (ddp_bytes > 0) {
1904 if (!mss) {
1905 mss = rx_ring->netdev->mtu -
1906 sizeof(struct fcoe_hdr) -
1907 sizeof(struct fc_frame_header) -
1908 sizeof(struct fcoe_crc_eof);
1909 if (mss > 512)
1910 mss &= ~511;
1911 }
1912 total_rx_bytes += ddp_bytes;
1913 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1914 mss);
1915 }
63d635b2
AD		 1916 if (!ddp_bytes) {
1917 dev_kfree_skb_any(skb);
f800326d 1918 continue;
63d635b2 1919 }
3d8fd385 1920 }
f800326d 1921
332d4a7d 1922#endif /* IXGBE_FCOE */
8a0da21b 1923 ixgbe_rx_skb(q_vector, skb);
9a799d71 1924
f800326d 1925 /* update budget accounting */
f4de00ed
AD		 1926 total_rx_packets++;
1927 } while (likely(total_rx_packets < budget));
9a799d71 1928
c267fc16
AD		 1929 u64_stats_update_begin(&rx_ring->syncp);
1930 rx_ring->stats.packets += total_rx_packets;
1931 rx_ring->stats.bytes += total_rx_bytes;
1932 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1933 q_vector->rx.total_packets += total_rx_packets;
1934 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1935
f800326d
AD		 1936 if (cleaned_count)
1937 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1938
f4de00ed 1939 return (total_rx_packets < budget);
9a799d71
AK		 1940}
1941
9a799d71
AK		 1942/**
1943 * ixgbe_configure_msix - Configure MSI-X hardware
1944 * @adapter: board private structure
1945 *
1946 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1947 * interrupts.
1948 **/
1949static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1950{
021230d4 1951 struct ixgbe_q_vector *q_vector;
49c7ffbe 1952 int v_idx;
021230d4 1953 u32 mask;
9a799d71 1954
8e34d1aa
AD		 1955 /* Populate MSIX to EITR Select */
1956 if (adapter->num_vfs > 32) {
1957 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1958 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1959 }
1960
4df10466
JB		 1961 /*
1962 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1963 * corresponding register.
1964 */
49c7ffbe 1965 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1966 struct ixgbe_ring *ring;
7a921c93 1967 q_vector = adapter->q_vector[v_idx];
021230d4 1968
a557928e 1969 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1970 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1971
a557928e 1972 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1973 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1974
fe49f04a 1975 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1976 }
1977
bd508178
AD		 1978 switch (adapter->hw.mac.type) {
1979 case ixgbe_mac_82598EB:
e8e26350 1980 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1981 v_idx);
bd508178
AD		 1982 break;
1983 case ixgbe_mac_82599EB:
b93a2226 1984 case ixgbe_mac_X540:
e8e26350 1985 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1986 break;
bd508178
AD		 1987 default:
1988 break;
1989 }
021230d4
AV		 1990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1991
41fb9248 1992 /* set up to autoclear timer, and the vectors */
021230d4 1993 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1994 mask &= ~(IXGBE_EIMS_OTHER |
1995 IXGBE_EIMS_MAILBOX |
1996 IXGBE_EIMS_LSC);
1997
021230d4 1998 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1999}
2000
f494e8fa
AV		 2001enum latency_range {
2002 lowest_latency = 0,
2003 low_latency = 1,
2004 bulk_latency = 2,
2005 latency_invalid = 255
2006};
2007
2008/**
2009 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2010 * @q_vector: structure containing interrupt and ring information
2011 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2012 *
2013 * Stores a new ITR value based on packets and byte
2014 * counts during the last interrupt. The advantage of per interrupt
2015 * computation is faster updates and more accurate ITR for the current
2016 * traffic pattern. Constants in this function were computed
2017 * based on theoretical maximum wire speed and thresholds were set based
2018 * on testing data as well as attempting to minimize response time
2019 * while increasing bulk throughput.
2020 * this functionality is controlled by the InterruptThrottleRate module
2021 * parameter (see ixgbe_param.c)
2022 **/
bd198058
AD		 2023static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2024 struct ixgbe_ring_container *ring_container)
f494e8fa 2025{
bd198058
AD		 2026 int bytes = ring_container->total_bytes;
2027 int packets = ring_container->total_packets;
2028 u32 timepassed_us;
621bd70e 2029 u64 bytes_perint;
bd198058 2030 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2031
2032 if (packets == 0)
bd198058 2033 return;
f494e8fa
AV		 2034
2035 /* simple throttlerate management
621bd70e
AD		 2036 * 0-10MB/s lowest (100000 ints/s)
2037 * 10-20MB/s low (20000 ints/s)
2038 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2039 */
2040 /* what was last interrupt timeslice? */
d5bf4f67 2041 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 2042 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2043
2044 switch (itr_setting) {
2045 case lowest_latency:
621bd70e 2046 if (bytes_perint > 10)
bd198058 2047 itr_setting = low_latency;
f494e8fa
AV		 2048 break;
2049 case low_latency:
621bd70e 2050 if (bytes_perint > 20)
bd198058 2051 itr_setting = bulk_latency;
621bd70e 2052 else if (bytes_perint <= 10)
bd198058 2053 itr_setting = lowest_latency;
f494e8fa
AV		 2054 break;
2055 case bulk_latency:
621bd70e 2056 if (bytes_perint <= 20)
bd198058 2057 itr_setting = low_latency;
f494e8fa
AV		 2058 break;
2059 }
2060
bd198058
AD		 2061 /* clear work counters since we have the values we need */
2062 ring_container->total_bytes = 0;
2063 ring_container->total_packets = 0;
2064
2065 /* write updated itr to ring container */
2066 ring_container->itr = itr_setting;
f494e8fa
AV		 2067}
2068
509ee935
JB		 2069/**
2070 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2071 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2072 *
2073 * This function is made to be called by ethtool and by the driver
2074 * when it needs to update EITR registers at runtime. Hardware
2075 * specific quirks/differences are taken care of here.
2076 */
fe49f04a 2077void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2078{
fe49f04a 2079 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2080 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2081 int v_idx = q_vector->v_idx;
5d967eb7 2082 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2083
bd508178
AD		 2084 switch (adapter->hw.mac.type) {
2085 case ixgbe_mac_82598EB:
509ee935
JB		 2086 /* must write high and low 16 bits to reset counter */
2087 itr_reg |= (itr_reg << 16);
bd508178
AD		 2088 break;
2089 case ixgbe_mac_82599EB:
b93a2226 2090 case ixgbe_mac_X540:
509ee935
JB		 2091 /*
2092 * set the WDIS bit to not clear the timer bits and cause an
2093 * immediate assertion of the interrupt
2094 */
2095 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2096 break;
2097 default:
2098 break;
509ee935
JB		 2099 }
2100 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2101}
2102
bd198058 2103static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2104{
d5bf4f67 2105 u32 new_itr = q_vector->itr;
bd198058 2106 u8 current_itr;
f494e8fa 2107
bd198058
AD		 2108 ixgbe_update_itr(q_vector, &q_vector->tx);
2109 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2110
08c8833b 2111 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2112
2113 switch (current_itr) {
2114 /* counts and packets in update_itr are dependent on these numbers */
2115 case lowest_latency:
d5bf4f67 2116 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2117 break;
2118 case low_latency:
d5bf4f67 2119 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2120 break;
2121 case bulk_latency:
d5bf4f67 2122 new_itr = IXGBE_8K_ITR;
f494e8fa 2123 break;
bd198058
AD		 2124 default:
2125 break;
f494e8fa
AV		 2126 }
2127
d5bf4f67 2128 if (new_itr != q_vector->itr) {
fe49f04a 2129 /* do an exponential smoothing */
d5bf4f67
ET		 2130 new_itr = (10 * new_itr * q_vector->itr) /
2131 ((9 * new_itr) + q_vector->itr);
509ee935 2132
bd198058 2133 /* save the algorithm value here */
5d967eb7 2134 q_vector->itr = new_itr;
fe49f04a
AD		 2135
2136 ixgbe_write_eitr(q_vector);
f494e8fa 2137 }
f494e8fa
AV		 2138}
2139
119fc60a 2140/**
de88eeeb 2141 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2142 * @adapter: pointer to adapter
119fc60a 2143 **/
f0f9778d 2144static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2145{
119fc60a
MC		 2146 struct ixgbe_hw *hw = &adapter->hw;
2147 u32 eicr = adapter->interrupt_event;
2148
f0f9778d 2149 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2150 return;
2151
f0f9778d
AD		 2152 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2153 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2154 return;
2155
2156 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2157
7ca647bd 2158 switch (hw->device_id) {
f0f9778d
AD		 2159 case IXGBE_DEV_ID_82599_T3_LOM:
2160 /*
2161 * Since the warning interrupt is for both ports
2162 * we don't have to check if:
2163 * - This interrupt wasn't for our port.
2164 * - We may have missed the interrupt so always have to
2165 * check if we got a LSC
2166 */
2167 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2168 !(eicr & IXGBE_EICR_LSC))
2169 return;
2170
2171 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2172 u32 autoneg;
2173 bool link_up = false;
7ca647bd 2174
7ca647bd
JP		 2175 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2176
f0f9778d
AD		 2177 if (link_up)
2178 return;
2179 }
2180
2181 /* Check if this is not due to overtemp */
2182 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2183 return;
2184
2185 break;
7ca647bd
JP		 2186 default:
2187 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2188 return;
7ca647bd 2189 break;
119fc60a 2190 }
7ca647bd
JP		 2191 e_crit(drv,
2192 "Network adapter has been stopped because it has over heated. "
2193 "Restart the computer. If the problem persists, "
2194 "power off the system and replace the adapter\n");
f0f9778d
AD		 2195
2196 adapter->interrupt_event = 0;
119fc60a
MC		 2197}
2198
0befdb3e
JB		 2199static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2200{
2201 struct ixgbe_hw *hw = &adapter->hw;
2202
2203 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2204 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2205 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2206 /* write to clear the interrupt */
2207 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2208 }
2209}
cf8280ee 2210
4f51bf70
JK		 2211static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2212{
2213 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2214 return;
2215
2216 switch (adapter->hw.mac.type) {
2217 case ixgbe_mac_82599EB:
2218 /*
2219 * Need to check link state so complete overtemp check
2220 * on service task
2221 */
2222 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2223 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2224 adapter->interrupt_event = eicr;
2225 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2226 ixgbe_service_event_schedule(adapter);
2227 return;
2228 }
2229 return;
2230 case ixgbe_mac_X540:
2231 if (!(eicr & IXGBE_EICR_TS))
2232 return;
2233 break;
2234 default:
2235 return;
2236 }
2237
2238 e_crit(drv,
2239 "Network adapter has been stopped because it has over heated. "
2240 "Restart the computer. If the problem persists, "
2241 "power off the system and replace the adapter\n");
2242}
2243
e8e26350
PW		 2244static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2245{
2246 struct ixgbe_hw *hw = &adapter->hw;
2247
73c4b7cd
AD		 2248 if (eicr & IXGBE_EICR_GPI_SDP2) {
2249 /* Clear the interrupt */
2250 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2251 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2252 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2253 ixgbe_service_event_schedule(adapter);
2254 }
73c4b7cd
AD		 2255 }
2256
e8e26350
PW		 2257 if (eicr & IXGBE_EICR_GPI_SDP1) {
2258 /* Clear the interrupt */
2259 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2260 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2261 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2262 ixgbe_service_event_schedule(adapter);
2263 }
e8e26350
PW		 2264 }
2265}
2266
cf8280ee
JB		 2267static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2268{
2269 struct ixgbe_hw *hw = &adapter->hw;
2270
2271 adapter->lsc_int++;
2272 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2273 adapter->link_check_timeout = jiffies;
2274 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2275 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2276 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2277 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2278 }
2279}
2280
fe49f04a
AD		 2281static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2282 u64 qmask)
2283{
2284 u32 mask;
bd508178 2285 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2286
bd508178
AD		 2287 switch (hw->mac.type) {
2288 case ixgbe_mac_82598EB:
fe49f04a 2289 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2290 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2291 break;
2292 case ixgbe_mac_82599EB:
b93a2226 2293 case ixgbe_mac_X540:
fe49f04a 2294 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2295 if (mask)
2296 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2297 mask = (qmask >> 32);
bd508178
AD		 2298 if (mask)
2299 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2300 break;
2301 default:
2302 break;
fe49f04a
AD		 2303 }
2304 /* skip the flush */
2305}
2306
2307static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2308 u64 qmask)
fe49f04a
AD		 2309{
2310 u32 mask;
bd508178 2311 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2312
bd508178
AD		 2313 switch (hw->mac.type) {
2314 case ixgbe_mac_82598EB:
fe49f04a 2315 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2316 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2317 break;
2318 case ixgbe_mac_82599EB:
b93a2226 2319 case ixgbe_mac_X540:
fe49f04a 2320 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2321 if (mask)
2322 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2323 mask = (qmask >> 32);
bd508178
AD		 2324 if (mask)
2325 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2326 break;
2327 default:
2328 break;
fe49f04a
AD		 2329 }
2330 /* skip the flush */
2331}
2332
021230d4 2333/**
2c4af694
AD		 2334 * ixgbe_irq_enable - Enable default interrupt generation settings
2335 * @adapter: board private structure
021230d4 2336 **/
2c4af694
AD		 2337static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2338 bool flush)
9a799d71 2339{
2c4af694 2340 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2341
2c4af694
AD		 2342 /* don't reenable LSC while waiting for link */
2343 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2344 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2345
2c4af694 2346 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2347 switch (adapter->hw.mac.type) {
2348 case ixgbe_mac_82599EB:
2349 mask |= IXGBE_EIMS_GPI_SDP0;
2350 break;
2351 case ixgbe_mac_X540:
2352 mask |= IXGBE_EIMS_TS;
2353 break;
2354 default:
2355 break;
2356 }
2c4af694
AD		 2357 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2358 mask |= IXGBE_EIMS_GPI_SDP1;
2359 switch (adapter->hw.mac.type) {
2360 case ixgbe_mac_82599EB:
2c4af694
AD		 2361 mask |= IXGBE_EIMS_GPI_SDP1;
2362 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2363 case ixgbe_mac_X540:
2364 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2365 mask |= IXGBE_EIMS_MAILBOX;
2366 break;
2367 default:
2368 break;
9a799d71 2369 }
db0677fa 2370
db0677fa
JK		 2371 if (adapter->hw.mac.type == ixgbe_mac_X540)
2372 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2373
2c4af694
AD		 2374 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2375 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2376 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2377
2c4af694
AD		 2378 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2379 if (queues)
2380 ixgbe_irq_enable_queues(adapter, ~0);
2381 if (flush)
2382 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2383}
2384
2c4af694 2385static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2386{
a65151ba 2387 struct ixgbe_adapter *adapter = data;
9a799d71 2388 struct ixgbe_hw *hw = &adapter->hw;
54037505 2389 u32 eicr;
91281fd3 2390
54037505
DS		 2391 /*
2392 * Workaround for Silicon errata. Use clear-by-write instead
2393 * of clear-by-read. Reading with EICS will return the
2394 * interrupt causes without clearing, which later be done
2395 * with the write to EICR.
2396 */
2397 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2398 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2399
cf8280ee
JB		 2400 if (eicr & IXGBE_EICR_LSC)
2401 ixgbe_check_lsc(adapter);
f0848276 2402
1cdd1ec8
GR		 2403 if (eicr & IXGBE_EICR_MAILBOX)
2404 ixgbe_msg_task(adapter);
efe3d3c8 2405
bd508178
AD		 2406 switch (hw->mac.type) {
2407 case ixgbe_mac_82599EB:
b93a2226 2408 case ixgbe_mac_X540:
2c4af694
AD		 2409 if (eicr & IXGBE_EICR_ECC)
2410 e_info(link, "Received unrecoverable ECC Err, please "
2411 "reboot\n");
c4cf55e5
PWJ		 2412 /* Handle Flow Director Full threshold interrupt */
2413 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2414 int reinit_count = 0;
c4cf55e5 2415 int i;
c4cf55e5 2416 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2417 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2418 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2419 &ring->state))
2420 reinit_count++;
2421 }
2422 if (reinit_count) {
2423 /* no more flow director interrupts until after init */
2424 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2425 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2426 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2427 }
2428 }
f0f9778d 2429 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2430 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2431 break;
2432 default:
2433 break;
c4cf55e5 2434 }
f0848276 2435
bd508178 2436 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2437
db0677fa
JK		 2438 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2439 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2440
7086400d 2441 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2442 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2443 ixgbe_irq_enable(adapter, false, false);
f0848276 2444
9a799d71 2445 return IRQ_HANDLED;
f0848276 2446}
91281fd3 2447
4ff7fb12 2448static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2449{
021230d4 2450 struct ixgbe_q_vector *q_vector = data;
91281fd3 2451
9b471446 2452 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2453
4ff7fb12
AD		 2454 if (q_vector->rx.ring || q_vector->tx.ring)
2455 napi_schedule(&q_vector->napi);
91281fd3 2456
9a799d71 2457 return IRQ_HANDLED;
91281fd3
AD		 2458}
2459
eb01b975
AD		 2460/**
2461 * ixgbe_poll - NAPI Rx polling callback
2462 * @napi: structure for representing this polling device
2463 * @budget: how many packets driver is allowed to clean
2464 *
2465 * This function is used for legacy and MSI, NAPI mode
2466 **/
8af3c33f 2467int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2468{
2469 struct ixgbe_q_vector *q_vector =
2470 container_of(napi, struct ixgbe_q_vector, napi);
2471 struct ixgbe_adapter *adapter = q_vector->adapter;
2472 struct ixgbe_ring *ring;
2473 int per_ring_budget;
2474 bool clean_complete = true;
2475
2476#ifdef CONFIG_IXGBE_DCA
2477 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2478 ixgbe_update_dca(q_vector);
2479#endif
2480
2481 ixgbe_for_each_ring(ring, q_vector->tx)
2482 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2483
2484 /* attempt to distribute budget to each queue fairly, but don't allow
2485 * the budget to go below 1 because we'll exit polling */
2486 if (q_vector->rx.count > 1)
2487 per_ring_budget = max(budget/q_vector->rx.count, 1);
2488 else
2489 per_ring_budget = budget;
2490
2491 ixgbe_for_each_ring(ring, q_vector->rx)
2492 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2493 per_ring_budget);
2494
2495 /* If all work not completed, return budget and keep polling */
2496 if (!clean_complete)
2497 return budget;
2498
2499 /* all work done, exit the polling mode */
2500 napi_complete(napi);
2501 if (adapter->rx_itr_setting & 1)
2502 ixgbe_set_itr(q_vector);
2503 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2504 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2505
2506 return 0;
2507}
2508
021230d4
AV		 2509/**
2510 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2511 * @adapter: board private structure
2512 *
2513 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2514 * interrupts from the kernel.
2515 **/
2516static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2517{
2518 struct net_device *netdev = adapter->netdev;
207867f5 2519 int vector, err;
e8e9f696 2520 int ri = 0, ti = 0;
021230d4 2521
49c7ffbe 2522 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2523 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2524 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2525
4ff7fb12 2526 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2527 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2528 "%s-%s-%d", netdev->name, "TxRx", ri++);
2529 ti++;
2530 } else if (q_vector->rx.ring) {
9fe93afd 2531 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2532 "%s-%s-%d", netdev->name, "rx", ri++);
2533 } else if (q_vector->tx.ring) {
9fe93afd 2534 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2535 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2536 } else {
2537 /* skip this unused q_vector */
2538 continue;
32aa77a4 2539 }
207867f5
AD		 2540 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2541 q_vector->name, q_vector);
9a799d71 2542 if (err) {
396e799c 2543 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2544 "Error: %d\n", err);
021230d4 2545 goto free_queue_irqs;
9a799d71 2546 }
207867f5
AD		 2547 /* If Flow Director is enabled, set interrupt affinity */
2548 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2549 /* assign the mask for this irq */
2550 irq_set_affinity_hint(entry->vector,
de88eeeb 2551 &q_vector->affinity_mask);
207867f5 2552 }
9a799d71
AK		 2553 }
2554
021230d4 2555 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2556 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2557 if (err) {
de88eeeb 2558 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2559 goto free_queue_irqs;
9a799d71
AK		 2560 }
2561
9a799d71
AK		 2562 return 0;
2563
021230d4 2564free_queue_irqs:
207867f5
AD		 2565 while (vector) {
2566 vector--;
2567 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2568 NULL);
2569 free_irq(adapter->msix_entries[vector].vector,
2570 adapter->q_vector[vector]);
2571 }
021230d4
AV		 2572 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2573 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2574 kfree(adapter->msix_entries);
2575 adapter->msix_entries = NULL;
9a799d71
AK		 2576 return err;
2577}
2578
2579/**
021230d4 2580 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2581 * @irq: interrupt number
2582 * @data: pointer to a network interface device structure
9a799d71
AK		 2583 **/
2584static irqreturn_t ixgbe_intr(int irq, void *data)
2585{
a65151ba 2586 struct ixgbe_adapter *adapter = data;
9a799d71 2587 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2588 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2589 u32 eicr;
2590
54037505 2591 /*
24ddd967 2592 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2593 * before the read of EICR.
2594 */
2595 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2596
021230d4 2597 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2598 * therefore no explicit interrupt disable is necessary */
021230d4 2599 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2600 if (!eicr) {
6af3b9eb
ET		 2601 /*
2602 * shared interrupt alert!
f47cf66e 2603 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2604 * have disabled interrupts due to EIAM
2605 * finish the workaround of silicon errata on 82598. Unmask
2606 * the interrupt that we masked before the EICR read.
2607 */
2608 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2609 ixgbe_irq_enable(adapter, true, true);
9a799d71 2610 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2611 }
9a799d71 2612
cf8280ee
JB		 2613 if (eicr & IXGBE_EICR_LSC)
2614 ixgbe_check_lsc(adapter);
021230d4 2615
bd508178
AD		 2616 switch (hw->mac.type) {
2617 case ixgbe_mac_82599EB:
e8e26350 2618 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2619 /* Fall through */
2620 case ixgbe_mac_X540:
2621 if (eicr & IXGBE_EICR_ECC)
2622 e_info(link, "Received unrecoverable ECC err, please "
2623 "reboot\n");
4f51bf70 2624 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2625 break;
2626 default:
2627 break;
2628 }
e8e26350 2629
0befdb3e 2630 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2631 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2632 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2633
b9f6ed2b
AD		 2634 /* would disable interrupts here but EIAM disabled it */
2635 napi_schedule(&q_vector->napi);
9a799d71 2636
6af3b9eb
ET		 2637 /*
2638 * re-enable link(maybe) and non-queue interrupts, no flush.
2639 * ixgbe_poll will re-enable the queue interrupts
2640 */
6af3b9eb
ET		 2641 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2642 ixgbe_irq_enable(adapter, false, false);
2643
9a799d71
AK		 2644 return IRQ_HANDLED;
2645}
2646
2647/**
2648 * ixgbe_request_irq - initialize interrupts
2649 * @adapter: board private structure
2650 *
2651 * Attempts to configure interrupts using the best available
2652 * capabilities of the hardware and kernel.
2653 **/
021230d4 2654static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2655{
2656 struct net_device *netdev = adapter->netdev;
021230d4 2657 int err;
9a799d71 2658
4cc6df29 2659 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2660 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2661 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2662 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2663 netdev->name, adapter);
4cc6df29 2664 else
a0607fd3 2665 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2666 netdev->name, adapter);
9a799d71 2667
de88eeeb 2668 if (err)
396e799c 2669 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2670
9a799d71
AK		 2671 return err;
2672}
2673
2674static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2675{
49c7ffbe 2676 int vector;
9a799d71 2677
49c7ffbe
AD		 2678 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2679 free_irq(adapter->pdev->irq, adapter);
2680 return;
2681 }
4cc6df29 2682
49c7ffbe
AD		 2683 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2684 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2685 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2686
49c7ffbe
AD		 2687 /* free only the irqs that were actually requested */
2688 if (!q_vector->rx.ring && !q_vector->tx.ring)
2689 continue;
207867f5 2690
49c7ffbe
AD		 2691 /* clear the affinity_mask in the IRQ descriptor */
2692 irq_set_affinity_hint(entry->vector, NULL);
2693
2694 free_irq(entry->vector, q_vector);
9a799d71 2695 }
49c7ffbe
AD		 2696
2697 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2698}
2699
22d5a71b
JB		 2700/**
2701 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2702 * @adapter: board private structure
2703 **/
2704static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2705{
bd508178
AD		 2706 switch (adapter->hw.mac.type) {
2707 case ixgbe_mac_82598EB:
835462fc 2708 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2709 break;
2710 case ixgbe_mac_82599EB:
b93a2226 2711 case ixgbe_mac_X540:
835462fc
NS		 2712 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2713 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2714 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2715 break;
2716 default:
2717 break;
22d5a71b
JB		 2718 }
2719 IXGBE_WRITE_FLUSH(&adapter->hw);
2720 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2721 int vector;
2722
2723 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2724 synchronize_irq(adapter->msix_entries[vector].vector);
2725
2726 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2727 } else {
2728 synchronize_irq(adapter->pdev->irq);
2729 }
2730}
2731
9a799d71
AK		 2732/**
2733 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2734 *
2735 **/
2736static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2737{
d5bf4f67 2738 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2739
d5bf4f67 2740 ixgbe_write_eitr(q_vector);
9a799d71 2741
e8e26350
PW		 2742 ixgbe_set_ivar(adapter, 0, 0, 0);
2743 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2744
396e799c 2745 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2746}
2747
43e69bf0
AD		 2748/**
2749 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2750 * @adapter: board private structure
2751 * @ring: structure containing ring specific data
2752 *
2753 * Configure the Tx descriptor ring after a reset.
2754 **/
84418e3b
AD		 2755void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2756 struct ixgbe_ring *ring)
43e69bf0
AD		 2757{
2758 struct ixgbe_hw *hw = &adapter->hw;
2759 u64 tdba = ring->dma;
2f1860b8 2760 int wait_loop = 10;
b88c6de2 2761 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2762 u8 reg_idx = ring->reg_idx;
43e69bf0 2763
2f1860b8 2764 /* disable queue to avoid issues while updating state */
b88c6de2 2765 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2766 IXGBE_WRITE_FLUSH(hw);
2767
43e69bf0 2768 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2769 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2770 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2771 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2772 ring->count * sizeof(union ixgbe_adv_tx_desc));
2773 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2774 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2775 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2776
b88c6de2
AD		 2777 /*
2778 * set WTHRESH to encourage burst writeback, it should not be set
2779 * higher than 1 when ITR is 0 as it could cause false TX hangs
2780 *
2781 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2782 * to or less than the number of on chip descriptors, which is
2783 * currently 40.
2784 */
e954b374 2785 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2786 txdctl |= (1 << 16); /* WTHRESH = 1 */
2787 else
2788 txdctl |= (8 << 16); /* WTHRESH = 8 */
2789
e954b374
AD		 2790 /*
2791 * Setting PTHRESH to 32 both improves performance
2792 * and avoids a TX hang with DFP enabled
2793 */
b88c6de2
AD		 2794 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2795 32; /* PTHRESH = 32 */
2f1860b8
AD		 2796
2797 /* reinitialize flowdirector state */
39cb681b 2798 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2799 ring->atr_sample_rate = adapter->atr_sample_rate;
2800 ring->atr_count = 0;
2801 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2802 } else {
2803 ring->atr_sample_rate = 0;
2804 }
2f1860b8 2805
c84d324c
JF		 2806 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2807
2f1860b8 2808 /* enable queue */
2f1860b8
AD		 2809 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2810
2811 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2812 if (hw->mac.type == ixgbe_mac_82598EB &&
2813 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2814 return;
2815
2816 /* poll to verify queue is enabled */
2817 do {
032b4325 2818 usleep_range(1000, 2000);
2f1860b8
AD		 2819 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2820 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2821 if (!wait_loop)
2822 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2823}
2824
120ff942
AD		 2825static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2826{
2827 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2828 u32 rttdcs, mtqc;
8b1c0b24 2829 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2830
2831 if (hw->mac.type == ixgbe_mac_82598EB)
2832 return;
2833
2834 /* disable the arbiter while setting MTQC */
2835 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2836 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2837 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2838
2839 /* set transmit pool layout */
671c0adb
AD		 2840 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2841 mtqc = IXGBE_MTQC_VT_ENA;
2842 if (tcs > 4)
2843 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2844 else if (tcs > 1)
2845 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2846 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2847 mtqc |= IXGBE_MTQC_32VF;
2848 else
2849 mtqc |= IXGBE_MTQC_64VF;
2850 } else {
2851 if (tcs > 4)
2852 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2853 else if (tcs > 1)
2854 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2855 else
671c0adb
AD		 2856 mtqc = IXGBE_MTQC_64Q_1PB;
2857 }
120ff942 2858
671c0adb 2859 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2860
671c0adb
AD		 2861 /* Enable Security TX Buffer IFG for multiple pb */
2862 if (tcs) {
2863 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2864 sectx |= IXGBE_SECTX_DCB;
2865 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2866 }
2867
2868 /* re-enable the arbiter */
2869 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2870 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2871}
2872
9a799d71 2873/**
3a581073 2874 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2875 * @adapter: board private structure
2876 *
2877 * Configure the Tx unit of the MAC after a reset.
2878 **/
2879static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2880{
2f1860b8
AD		 2881 struct ixgbe_hw *hw = &adapter->hw;
2882 u32 dmatxctl;
43e69bf0 2883 u32 i;
9a799d71 2884
2f1860b8
AD		 2885 ixgbe_setup_mtqc(adapter);
2886
2887 if (hw->mac.type != ixgbe_mac_82598EB) {
2888 /* DMATXCTL.EN must be before Tx queues are enabled */
2889 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2890 dmatxctl |= IXGBE_DMATXCTL_TE;
2891 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2892 }
2893
9a799d71 2894 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2895 for (i = 0; i < adapter->num_tx_queues; i++)
2896 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2897}
2898
3ebe8fde
AD		 2899static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2900 struct ixgbe_ring *ring)
2901{
2902 struct ixgbe_hw *hw = &adapter->hw;
2903 u8 reg_idx = ring->reg_idx;
2904 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2905
2906 srrctl |= IXGBE_SRRCTL_DROP_EN;
2907
2908 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2909}
2910
2911static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2912 struct ixgbe_ring *ring)
2913{
2914 struct ixgbe_hw *hw = &adapter->hw;
2915 u8 reg_idx = ring->reg_idx;
2916 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2917
2918 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2919
2920 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2921}
2922
2923#ifdef CONFIG_IXGBE_DCB
2924void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2925#else
2926static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2927#endif
2928{
2929 int i;
2930 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2931
2932 if (adapter->ixgbe_ieee_pfc)
2933 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2934
2935 /*
2936 * We should set the drop enable bit if:
2937 * SR-IOV is enabled
2938 * or
2939 * Number of Rx queues > 1 and flow control is disabled
2940 *
2941 * This allows us to avoid head of line blocking for security
2942 * and performance reasons.
2943 */
2944 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2945 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2946 for (i = 0; i < adapter->num_rx_queues; i++)
2947 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2948 } else {
2949 for (i = 0; i < adapter->num_rx_queues; i++)
2950 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2951 }
2952}
2953
e8e26350 2954#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2955
a6616b42 2956static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2957 struct ixgbe_ring *rx_ring)
cc41ac7c 2958{
45e9baa5 2959 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2960 u32 srrctl;
bf29ee6c 2961 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2962
45e9baa5
AD		 2963 if (hw->mac.type == ixgbe_mac_82598EB) {
2964 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2965
45e9baa5
AD		 2966 /*
2967 * if VMDq is not active we must program one srrctl register
2968 * per RSS queue since we have enabled RDRXCTL.MVMEN
2969 */
2970 reg_idx &= mask;
2971 }
cc41ac7c 2972
45e9baa5
AD		 2973 /* configure header buffer length, needed for RSC */
2974 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2975
45e9baa5 2976 /* configure the packet buffer length */
f800326d 2977 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 2978
2979 /* configure descriptor type */
f800326d 2980 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2981
45e9baa5 2982 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2983}
9a799d71 2984
05abb126 2985static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2986{
05abb126
AD		 2987 struct ixgbe_hw *hw = &adapter->hw;
2988 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2989 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2990 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2991 u32 mrqc = 0, reta = 0;
2992 u32 rxcsum;
2993 int i, j;
671c0adb
AD		 2994 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2995
671c0adb
AD		 2996 /*
2997 * Program table for at least 2 queues w/ SR-IOV so that VFs can
2998 * make full use of any rings they may have. We will use the
2999 * PSRTYPE register to control how many rings we use within the PF.
3000 */
3001 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3002 rss_i = 2;
0cefafad 3003
05abb126
AD		 3004 /* Fill out hash function seeds */
3005 for (i = 0; i < 10; i++)
3006 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3007
3008 /* Fill out redirection table */
3009 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3010 if (j == rss_i)
05abb126
AD		 3011 j = 0;
3012 /* reta = 4-byte sliding window of
3013 * 0x00..(indices-1)(indices-1)00..etc. */
3014 reta = (reta << 8) | (j * 0x11);
3015 if ((i & 3) == 3)
3016 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3017 }
0cefafad 3018
05abb126
AD		 3019 /* Disable indicating checksum in descriptor, enables RSS hash */
3020 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3021 rxcsum |= IXGBE_RXCSUM_PCSD;
3022 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3023
671c0adb 3024 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3025 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3026 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3027 } else {
671c0adb
AD		 3028 u8 tcs = netdev_get_num_tc(adapter->netdev);
3029
3030 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3031 if (tcs > 4)
3032 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3033 else if (tcs > 1)
3034 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3035 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3036 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3037 else
671c0adb
AD		 3038 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3039 } else {
3040 if (tcs > 4)
8b1c0b24 3041 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3042 else if (tcs > 1)
3043 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3044 else
3045 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3046 }
0cefafad
JB		 3047 }
3048
05abb126 3049 /* Perform hash on these packet types */
671c0adb
AD		 3050 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3051 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3052 IXGBE_MRQC_RSS_FIELD_IPV6 |
3053 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3054
ef6afc0c
AD		 3055 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3056 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3057 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3058 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3059
05abb126 3060 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3061}
3062
bb5a9ad2
NS		 3063/**
3064 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3065 * @adapter: address of board private structure
3066 * @index: index of ring to set
bb5a9ad2 3067 **/
082757af 3068static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3069 struct ixgbe_ring *ring)
bb5a9ad2 3070{
bb5a9ad2 3071 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3072 u32 rscctrl;
bf29ee6c 3073 u8 reg_idx = ring->reg_idx;
7367096a 3074
7d637bcc 3075 if (!ring_is_rsc_enabled(ring))
7367096a 3076 return;
bb5a9ad2 3077
7367096a 3078 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3079 rscctrl |= IXGBE_RSCCTL_RSCEN;
3080 /*
3081 * we must limit the number of descriptors so that the
3082 * total size of max desc * buf_len is not greater
642c680e 3083 * than 65536
bb5a9ad2 3084 */
f800326d 3085 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3086 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3087}
3088
9e10e045
AD		 3089#define IXGBE_MAX_RX_DESC_POLL 10
3090static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3091 struct ixgbe_ring *ring)
3092{
3093 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3094 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3095 u32 rxdctl;
bf29ee6c 3096 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3097
3098 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3099 if (hw->mac.type == ixgbe_mac_82598EB &&
3100 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3101 return;
3102
3103 do {
032b4325 3104 usleep_range(1000, 2000);
9e10e045
AD		 3105 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3106 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3107
3108 if (!wait_loop) {
3109 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3110 "the polling period\n", reg_idx);
3111 }
3112}
3113
2d39d576
YZ		 3114void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3115 struct ixgbe_ring *ring)
3116{
3117 struct ixgbe_hw *hw = &adapter->hw;
3118 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3119 u32 rxdctl;
3120 u8 reg_idx = ring->reg_idx;
3121
3122 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3123 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3124
3125 /* write value back with RXDCTL.ENABLE bit cleared */
3126 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3127
3128 if (hw->mac.type == ixgbe_mac_82598EB &&
3129 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3130 return;
3131
3132 /* the hardware may take up to 100us to really disable the rx queue */
3133 do {
3134 udelay(10);
3135 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3136 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3137
3138 if (!wait_loop) {
3139 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3140 "the polling period\n", reg_idx);
3141 }
3142}
3143
84418e3b
AD		 3144void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3145 struct ixgbe_ring *ring)
acd37177
AD		 3146{
3147 struct ixgbe_hw *hw = &adapter->hw;
3148 u64 rdba = ring->dma;
9e10e045 3149 u32 rxdctl;
bf29ee6c 3150 u8 reg_idx = ring->reg_idx;
acd37177 3151
9e10e045
AD		 3152 /* disable queue to avoid issues while updating state */
3153 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3154 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3155
acd37177
AD		 3156 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3157 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3158 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3159 ring->count * sizeof(union ixgbe_adv_rx_desc));
3160 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3161 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3162 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3163
3164 ixgbe_configure_srrctl(adapter, ring);
3165 ixgbe_configure_rscctl(adapter, ring);
3166
e9f98072
GR		 3167 /* If operating in IOV mode set RLPML for X540 */
3168 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3169 hw->mac.type == ixgbe_mac_X540) {
3170 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3171 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3172 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3173 }
3174
9e10e045
AD		 3175 if (hw->mac.type == ixgbe_mac_82598EB) {
3176 /*
3177 * enable cache line friendly hardware writes:
3178 * PTHRESH=32 descriptors (half the internal cache),
3179 * this also removes ugly rx_no_buffer_count increment
3180 * HTHRESH=4 descriptors (to minimize latency on fetch)
3181 * WTHRESH=8 burst writeback up to two cache lines
3182 */
3183 rxdctl &= ~0x3FFFFF;
3184 rxdctl |= 0x080420;
3185 }
3186
3187 /* enable receive descriptor ring */
3188 rxdctl |= IXGBE_RXDCTL_ENABLE;
3189 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3190
3191 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3192 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3193}
3194
48654521
AD		 3195static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3196{
3197 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3198 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3199 int p;
3200
3201 /* PSRTYPE must be initialized in non 82598 adapters */
3202 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3203 IXGBE_PSRTYPE_UDPHDR |
3204 IXGBE_PSRTYPE_IPV4HDR |
48654521 3205 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3206 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3207
3208 if (hw->mac.type == ixgbe_mac_82598EB)
3209 return;
3210
fbe7ca7f
AD		 3211 if (rss_i > 3)
3212 psrtype |= 2 << 29;
3213 else if (rss_i > 1)
3214 psrtype |= 1 << 29;
48654521
AD		 3215
3216 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3217 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3218 psrtype);
3219}
3220
f5b4a52e
AD		 3221static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3222{
3223 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3224 u32 reg_offset, vf_shift;
435b19f6 3225 u32 gcr_ext, vmdctl;
de4c7f65 3226 int i;
f5b4a52e
AD		 3227
3228 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3229 return;
3230
3231 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3232 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3233 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3234 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3235 vmdctl |= IXGBE_VT_CTL_REPLEN;
3236 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3237
1d9c0bfd
AD		 3238 vf_shift = VMDQ_P(0) % 32;
3239 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3240
3241 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3242 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3243 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3244 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3245 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
f5b4a52e
AD		 3246
3247 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3248 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3249
3250 /*
3251 * Set up VF register offsets for selected VT Mode,
3252 * i.e. 32 or 64 VFs for SR-IOV
3253 */
73079ea0
AD		 3254 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3255 case IXGBE_82599_VMDQ_8Q_MASK:
3256 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3257 break;
3258 case IXGBE_82599_VMDQ_4Q_MASK:
3259 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3260 break;
3261 default:
3262 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3263 break;
3264 }
3265
f5b4a52e
AD		 3266 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3267
435b19f6 3268
a985b6c3 3269 /* Enable MAC Anti-Spoofing */
435b19f6 3270 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3271 adapter->num_vfs);
de4c7f65
GR		 3272 /* For VFs that have spoof checking turned off */
3273 for (i = 0; i < adapter->num_vfs; i++) {
3274 if (!adapter->vfinfo[i].spoofchk_enabled)
3275 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3276 }
f5b4a52e
AD		 3277}
3278
477de6ed 3279static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3280{
9a799d71
AK		 3281 struct ixgbe_hw *hw = &adapter->hw;
3282 struct net_device *netdev = adapter->netdev;
3283 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3284 struct ixgbe_ring *rx_ring;
3285 int i;
3286 u32 mhadd, hlreg0;
48654521 3287
63f39bd1 3288#ifdef IXGBE_FCOE
477de6ed
AD		 3289 /* adjust max frame to be able to do baby jumbo for FCoE */
3290 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3291 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3292 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3293
477de6ed 3294#endif /* IXGBE_FCOE */
872844dd
AD		 3295
3296 /* adjust max frame to be at least the size of a standard frame */
3297 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3298 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3299
477de6ed
AD		 3300 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3301 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3302 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3303 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3304
3305 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3306 }
3307
3308 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3309 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3310 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3311 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3312
0cefafad
JB		 3313 /*
3314 * Setup the HW Rx Head and Tail Descriptor Pointers and
3315 * the Base and Length of the Rx Descriptor Ring
3316 */
9a799d71 3317 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3318 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3319 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3320 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3321 else
7d637bcc 3322 clear_ring_rsc_enabled(rx_ring);
477de6ed 3323 }
477de6ed
AD		 3324}
3325
7367096a
AD		 3326static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3327{
3328 struct ixgbe_hw *hw = &adapter->hw;
3329 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3330
3331 switch (hw->mac.type) {
3332 case ixgbe_mac_82598EB:
3333 /*
3334 * For VMDq support of different descriptor types or
3335 * buffer sizes through the use of multiple SRRCTL
3336 * registers, RDRXCTL.MVMEN must be set to 1
3337 *
3338 * also, the manual doesn't mention it clearly but DCA hints
3339 * will only use queue 0's tags unless this bit is set. Side
3340 * effects of setting this bit are only that SRRCTL must be
3341 * fully programmed [0..15]
3342 */
3343 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3344 break;
3345 case ixgbe_mac_82599EB:
b93a2226 3346 case ixgbe_mac_X540:
7367096a
AD		 3347 /* Disable RSC for ACK packets */
3348 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3349 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3350 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3351 /* hardware requires some bits to be set by default */
3352 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3353 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3354 break;
3355 default:
3356 /* We should do nothing since we don't know this hardware */
3357 return;
3358 }
3359
3360 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3361}
3362
477de6ed
AD		 3363/**
3364 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3365 * @adapter: board private structure
3366 *
3367 * Configure the Rx unit of the MAC after a reset.
3368 **/
3369static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3370{
3371 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3372 int i;
3373 u32 rxctrl;
477de6ed
AD		 3374
3375 /* disable receives while setting up the descriptors */
3376 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3377 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3378
3379 ixgbe_setup_psrtype(adapter);
7367096a 3380 ixgbe_setup_rdrxctl(adapter);
477de6ed 3381
9e10e045 3382 /* Program registers for the distribution of queues */
f5b4a52e 3383 ixgbe_setup_mrqc(adapter);
f5b4a52e 3384
477de6ed
AD		 3385 /* set_rx_buffer_len must be called before ring initialization */
3386 ixgbe_set_rx_buffer_len(adapter);
3387
3388 /*
3389 * Setup the HW Rx Head and Tail Descriptor Pointers and
3390 * the Base and Length of the Rx Descriptor Ring
3391 */
9e10e045
AD		 3392 for (i = 0; i < adapter->num_rx_queues; i++)
3393 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3394
9e10e045
AD		 3395 /* disable drop enable for 82598 parts */
3396 if (hw->mac.type == ixgbe_mac_82598EB)
3397 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3398
3399 /* enable all receives */
3400 rxctrl |= IXGBE_RXCTRL_RXEN;
3401 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3402}
3403
8e586137 3404static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3405{
3406 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3407 struct ixgbe_hw *hw = &adapter->hw;
3408
3409 /* add VID to filter table */
1d9c0bfd 3410 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3411 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3412
3413 return 0;
068c89b0
DS		 3414}
3415
8e586137 3416static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3417{
3418 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3419 struct ixgbe_hw *hw = &adapter->hw;
3420
068c89b0 3421 /* remove VID from filter table */
1d9c0bfd 3422 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3423 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3424
3425 return 0;
068c89b0
DS		 3426}
3427
5f6c0181
JB		 3428/**
3429 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3430 * @adapter: driver data
3431 */
3432static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3433{
3434 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3435 u32 vlnctrl;
3436
3437 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3438 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3439 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3440}
3441
3442/**
3443 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3444 * @adapter: driver data
3445 */
3446static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3447{
3448 struct ixgbe_hw *hw = &adapter->hw;
3449 u32 vlnctrl;
3450
3451 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3452 vlnctrl |= IXGBE_VLNCTRL_VFE;
3453 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3454 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3455}
3456
3457/**
3458 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3459 * @adapter: driver data
3460 */
3461static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3462{
3463 struct ixgbe_hw *hw = &adapter->hw;
3464 u32 vlnctrl;
5f6c0181
JB		 3465 int i, j;
3466
3467 switch (hw->mac.type) {
3468 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3469 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3470 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3471 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3472 break;
3473 case ixgbe_mac_82599EB:
b93a2226 3474 case ixgbe_mac_X540:
5f6c0181
JB		 3475 for (i = 0; i < adapter->num_rx_queues; i++) {
3476 j = adapter->rx_ring[i]->reg_idx;
3477 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3478 vlnctrl &= ~IXGBE_RXDCTL_VME;
3479 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3480 }
3481 break;
3482 default:
3483 break;
3484 }
3485}
3486
3487/**
f62bbb5e 3488 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3489 * @adapter: driver data
3490 */
f62bbb5e 3491static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3492{
3493 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3494 u32 vlnctrl;
5f6c0181
JB		 3495 int i, j;
3496
3497 switch (hw->mac.type) {
3498 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3499 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3500 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3501 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3502 break;
3503 case ixgbe_mac_82599EB:
b93a2226 3504 case ixgbe_mac_X540:
5f6c0181
JB		 3505 for (i = 0; i < adapter->num_rx_queues; i++) {
3506 j = adapter->rx_ring[i]->reg_idx;
3507 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3508 vlnctrl |= IXGBE_RXDCTL_VME;
3509 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3510 }
3511 break;
3512 default:
3513 break;
3514 }
3515}
3516
9a799d71
AK		 3517static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3518{
f62bbb5e 3519 u16 vid;
9a799d71 3520
f62bbb5e
JG		 3521 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3522
3523 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3524 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3525}
3526
2850062a
AD		 3527/**
3528 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3529 * @netdev: network interface device structure
3530 *
3531 * Writes unicast address list to the RAR table.
3532 * Returns: -ENOMEM on failure/insufficient address space
3533 * 0 on no addresses written
3534 * X on writing X addresses to the RAR table
3535 **/
3536static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3537{
3538 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3539 struct ixgbe_hw *hw = &adapter->hw;
95447461 3540 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3541 int count = 0;
3542
95447461
JF		 3543 /* In SR-IOV mode significantly less RAR entries are available */
3544 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3545 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3546
2850062a
AD		 3547 /* return ENOMEM indicating insufficient memory for addresses */
3548 if (netdev_uc_count(netdev) > rar_entries)
3549 return -ENOMEM;
3550
95447461 3551 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3552 struct netdev_hw_addr *ha;
3553 /* return error if we do not support writing to RAR table */
3554 if (!hw->mac.ops.set_rar)
3555 return -ENOMEM;
3556
3557 netdev_for_each_uc_addr(ha, netdev) {
3558 if (!rar_entries)
3559 break;
3560 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3561 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3562 count++;
3563 }
3564 }
3565 /* write the addresses in reverse order to avoid write combining */
3566 for (; rar_entries > 0 ; rar_entries--)
3567 hw->mac.ops.clear_rar(hw, rar_entries);
3568
3569 return count;
3570}
3571
9a799d71 3572/**
2c5645cf 3573 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3574 * @netdev: network interface device structure
3575 *
2c5645cf
CL		 3576 * The set_rx_method entry point is called whenever the unicast/multicast
3577 * address list or the network interface flags are updated. This routine is
3578 * responsible for configuring the hardware for proper unicast, multicast and
3579 * promiscuous mode.
9a799d71 3580 **/
7f870475 3581void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3582{
3583 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3584 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3585 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3586 int count;
9a799d71
AK		 3587
3588 /* Check for Promiscuous and All Multicast modes */
3589
3590 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3591
f5dc442b 3592 /* set all bits that we expect to always be set */
3f2d1c0f 3593 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3594 fctrl |= IXGBE_FCTRL_BAM;
3595 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3596 fctrl |= IXGBE_FCTRL_PMCF;
3597
2850062a
AD		 3598 /* clear the bits we are changing the status of */
3599 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3600
9a799d71 3601 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3602 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3603 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3604 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3605 /* don't hardware filter vlans in promisc mode */
3606 ixgbe_vlan_filter_disable(adapter);
9a799d71 3607 } else {
746b9f02
PM		 3608 if (netdev->flags & IFF_ALLMULTI) {
3609 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3610 vmolr |= IXGBE_VMOLR_MPE;
3611 } else {
3612 /*
3613 * Write addresses to the MTA, if the attempt fails
25985edc 3614 * then we should just turn on promiscuous mode so
2850062a
AD		 3615 * that we can at least receive multicast traffic
3616 */
3617 hw->mac.ops.update_mc_addr_list(hw, netdev);
3618 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3619 }
5f6c0181 3620 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3621 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3622 }
3623
3624 /*
3625 * Write addresses to available RAR registers, if there is not
3626 * sufficient space to store all the addresses then enable
3627 * unicast promiscuous mode
3628 */
3629 count = ixgbe_write_uc_addr_list(netdev);
3630 if (count < 0) {
3631 fctrl |= IXGBE_FCTRL_UPE;
3632 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3633 }
3634
1d9c0bfd 3635 if (adapter->num_vfs)
1cdd1ec8 3636 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3637
3638 if (hw->mac.type != ixgbe_mac_82598EB) {
3639 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3640 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3641 IXGBE_VMOLR_ROPE);
1d9c0bfd 3642 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3643 }
3644
3f2d1c0f
BG		 3645 /* This is useful for sniffing bad packets. */
3646 if (adapter->netdev->features & NETIF_F_RXALL) {
3647 /* UPE and MPE will be handled by normal PROMISC logic
3648 * in e1000e_set_rx_mode */
3649 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3650 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3651 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3652
3653 fctrl &= ~(IXGBE_FCTRL_DPF);
3654 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3655 }
3656
2850062a 3657 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3658
3659 if (netdev->features & NETIF_F_HW_VLAN_RX)
3660 ixgbe_vlan_strip_enable(adapter);
3661 else
3662 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3663}
3664
021230d4
AV		 3665static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3666{
3667 int q_idx;
021230d4 3668
49c7ffbe
AD		 3669 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3670 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3671}
3672
3673static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3674{
3675 int q_idx;
021230d4 3676
49c7ffbe
AD		 3677 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3678 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3679}
3680
7a6b6f51 3681#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3682/**
2f90b865
AD		 3683 * ixgbe_configure_dcb - Configure DCB hardware
3684 * @adapter: ixgbe adapter struct
3685 *
3686 * This is called by the driver on open to configure the DCB hardware.
3687 * This is also called by the gennetlink interface when reconfiguring
3688 * the DCB state.
3689 */
3690static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3691{
3692 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3693 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3694
67ebd791
AD		 3695 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3696 if (hw->mac.type == ixgbe_mac_82598EB)
3697 netif_set_gso_max_size(adapter->netdev, 65536);
3698 return;
3699 }
3700
3701 if (hw->mac.type == ixgbe_mac_82598EB)
3702 netif_set_gso_max_size(adapter->netdev, 32768);
3703
971060b1 3704#ifdef IXGBE_FCOE
b120818e
JF		 3705 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3706 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3707#endif
b120818e
JF		 3708
3709 /* reconfigure the hardware */
3710 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3711 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3712 DCB_TX_CONFIG);
3713 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3714 DCB_RX_CONFIG);
3715 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3716 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3717 ixgbe_dcb_hw_ets(&adapter->hw,
3718 adapter->ixgbe_ieee_ets,
3719 max_frame);
3720 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3721 adapter->ixgbe_ieee_pfc->pfc_en,
3722 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3723 }
8187cd48
JF		 3724
3725 /* Enable RSS Hash per TC */
3726 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3727 u32 msb = 0;
3728 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3729
d411a936
AD		 3730 while (rss_i) {
3731 msb++;
3732 rss_i >>= 1;
3733 }
8187cd48 3734
4ae63730
AD		 3735 /* write msb to all 8 TCs in one write */
3736 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3737 }
2f90b865 3738}
9da712d2
JF		 3739#endif
3740
3741/* Additional bittime to account for IXGBE framing */
3742#define IXGBE_ETH_FRAMING 20
3743
49ce9c2c 3744/**
9da712d2
JF		 3745 * ixgbe_hpbthresh - calculate high water mark for flow control
3746 *
3747 * @adapter: board private structure to calculate for
49ce9c2c 3748 * @pb: packet buffer to calculate
9da712d2
JF		 3749 */
3750static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3751{
3752 struct ixgbe_hw *hw = &adapter->hw;
3753 struct net_device *dev = adapter->netdev;
3754 int link, tc, kb, marker;
3755 u32 dv_id, rx_pba;
3756
3757 /* Calculate max LAN frame size */
3758 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3759
3760#ifdef IXGBE_FCOE
3761 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3762 if ((dev->features & NETIF_F_FCOE_MTU) &&
3763 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3764 (pb == ixgbe_fcoe_get_tc(adapter)))
3765 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3766
3767#endif
9da712d2
JF		 3768 /* Calculate delay value for device */
3769 switch (hw->mac.type) {
3770 case ixgbe_mac_X540:
3771 dv_id = IXGBE_DV_X540(link, tc);
3772 break;
3773 default:
3774 dv_id = IXGBE_DV(link, tc);
3775 break;
3776 }
3777
3778 /* Loopback switch introduces additional latency */
3779 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3780 dv_id += IXGBE_B2BT(tc);
3781
3782 /* Delay value is calculated in bit times convert to KB */
3783 kb = IXGBE_BT2KB(dv_id);
3784 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3785
3786 marker = rx_pba - kb;
3787
3788 /* It is possible that the packet buffer is not large enough
3789 * to provide required headroom. In this case throw an error
3790 * to user and a do the best we can.
3791 */
3792 if (marker < 0) {
3793 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3794 "headroom to support flow control."
3795 "Decrease MTU or number of traffic classes\n", pb);
3796 marker = tc + 1;
3797 }
3798
3799 return marker;
3800}
3801
49ce9c2c 3802/**
9da712d2
JF		 3803 * ixgbe_lpbthresh - calculate low water mark for for flow control
3804 *
3805 * @adapter: board private structure to calculate for
49ce9c2c 3806 * @pb: packet buffer to calculate
9da712d2
JF		 3807 */
3808static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3809{
3810 struct ixgbe_hw *hw = &adapter->hw;
3811 struct net_device *dev = adapter->netdev;
3812 int tc;
3813 u32 dv_id;
3814
3815 /* Calculate max LAN frame size */
3816 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3817
3818 /* Calculate delay value for device */
3819 switch (hw->mac.type) {
3820 case ixgbe_mac_X540:
3821 dv_id = IXGBE_LOW_DV_X540(tc);
3822 break;
3823 default:
3824 dv_id = IXGBE_LOW_DV(tc);
3825 break;
3826 }
3827
3828 /* Delay value is calculated in bit times convert to KB */
3829 return IXGBE_BT2KB(dv_id);
3830}
3831
3832/*
3833 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3834 */
3835static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3836{
3837 struct ixgbe_hw *hw = &adapter->hw;
3838 int num_tc = netdev_get_num_tc(adapter->netdev);
3839 int i;
3840
3841 if (!num_tc)
3842 num_tc = 1;
3843
3844 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3845
3846 for (i = 0; i < num_tc; i++) {
3847 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3848
3849 /* Low water marks must not be larger than high water marks */
3850 if (hw->fc.low_water > hw->fc.high_water[i])
3851 hw->fc.low_water = 0;
3852 }
3853}
3854
80605c65
JF		 3855static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3856{
80605c65 3857 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3858 int hdrm;
3859 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3860
3861 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3862 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3863 hdrm = 32 << adapter->fdir_pballoc;
3864 else
3865 hdrm = 0;
80605c65 3866
f7e1027f 3867 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3868 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3869}
3870
e4911d57
AD		 3871static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3872{
3873 struct ixgbe_hw *hw = &adapter->hw;
3874 struct hlist_node *node, *node2;
3875 struct ixgbe_fdir_filter *filter;
3876
3877 spin_lock(&adapter->fdir_perfect_lock);
3878
3879 if (!hlist_empty(&adapter->fdir_filter_list))
3880 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3881
3882 hlist_for_each_entry_safe(filter, node, node2,
3883 &adapter->fdir_filter_list, fdir_node) {
3884 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3885 &filter->filter,
3886 filter->sw_idx,
3887 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3888 IXGBE_FDIR_DROP_QUEUE :
3889 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3890 }
3891
3892 spin_unlock(&adapter->fdir_perfect_lock);
3893}
3894
9a799d71
AK		 3895static void ixgbe_configure(struct ixgbe_adapter *adapter)
3896{
d2f5e7f3
AS		 3897 struct ixgbe_hw *hw = &adapter->hw;
3898
80605c65 3899 ixgbe_configure_pb(adapter);
7a6b6f51 3900#ifdef CONFIG_IXGBE_DCB
67ebd791 3901 ixgbe_configure_dcb(adapter);
2f90b865 3902#endif
b35d4d42
AD		 3903 /*
3904 * We must restore virtualization before VLANs or else
3905 * the VLVF registers will not be populated
3906 */
3907 ixgbe_configure_virtualization(adapter);
9a799d71 3908
4c1d7b4b 3909 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3910 ixgbe_restore_vlan(adapter);
3911
d2f5e7f3
AS		 3912 switch (hw->mac.type) {
3913 case ixgbe_mac_82599EB:
3914 case ixgbe_mac_X540:
3915 hw->mac.ops.disable_rx_buff(hw);
3916 break;
3917 default:
3918 break;
3919 }
3920
c4cf55e5 3921 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3922 ixgbe_init_fdir_signature_82599(&adapter->hw,
3923 adapter->fdir_pballoc);
e4911d57
AD		 3924 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3925 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3926 adapter->fdir_pballoc);
3927 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3928 }
4c1d7b4b 3929
d2f5e7f3
AS		 3930 switch (hw->mac.type) {
3931 case ixgbe_mac_82599EB:
3932 case ixgbe_mac_X540:
3933 hw->mac.ops.enable_rx_buff(hw);
3934 break;
3935 default:
3936 break;
3937 }
3938
7c8ae65a
AD		 3939#ifdef IXGBE_FCOE
3940 /* configure FCoE L2 filters, redirection table, and Rx control */
3941 ixgbe_configure_fcoe(adapter);
3942
3943#endif /* IXGBE_FCOE */
9a799d71
AK		 3944 ixgbe_configure_tx(adapter);
3945 ixgbe_configure_rx(adapter);
9a799d71
AK		 3946}
3947
e8e26350
PW		 3948static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3949{
3950 switch (hw->phy.type) {
3951 case ixgbe_phy_sfp_avago:
3952 case ixgbe_phy_sfp_ftl:
3953 case ixgbe_phy_sfp_intel:
3954 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3955 case ixgbe_phy_sfp_passive_tyco:
3956 case ixgbe_phy_sfp_passive_unknown:
3957 case ixgbe_phy_sfp_active_unknown:
3958 case ixgbe_phy_sfp_ftl_active:
e8e26350 3959 return true;
8917b447
AD		 3960 case ixgbe_phy_nl:
3961 if (hw->mac.type == ixgbe_mac_82598EB)
3962 return true;
e8e26350
PW		 3963 default:
3964 return false;
3965 }
3966}
3967
0ecc061d 3968/**
e8e26350
PW		 3969 * ixgbe_sfp_link_config - set up SFP+ link
3970 * @adapter: pointer to private adapter struct
3971 **/
3972static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3973{
7086400d 3974 /*
52f33af8 3975 * We are assuming the worst case scenario here, and that
7086400d
AD		 3976 * is that an SFP was inserted/removed after the reset
3977 * but before SFP detection was enabled. As such the best
3978 * solution is to just start searching as soon as we start
3979 */
3980 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3981 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3982
7086400d 3983 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3984}
3985
3986/**
3987 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3988 * @hw: pointer to private hardware struct
3989 *
3990 * Returns 0 on success, negative on failure
3991 **/
e8e26350 3992static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3993{
3994 u32 autoneg;
8620a103 3995 bool negotiation, link_up = false;
0ecc061d
PWJ		 3996 u32 ret = IXGBE_ERR_LINK_SETUP;
3997
3998 if (hw->mac.ops.check_link)
3999 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
4000
4001 if (ret)
4002 goto link_cfg_out;
4003
0b0c2b31
ET		 4004 autoneg = hw->phy.autoneg_advertised;
4005 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 4006 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
4007 &negotiation);
0ecc061d
PWJ		 4008 if (ret)
4009 goto link_cfg_out;
4010
8620a103
MC		 4011 if (hw->mac.ops.setup_link)
4012 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 4013link_cfg_out:
4014 return ret;
4015}
4016
a34bcfff 4017static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4018{
9a799d71 4019 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4020 u32 gpie = 0;
9a799d71 4021
9b471446 4022 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4023 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4024 IXGBE_GPIE_OCD;
4025 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4026 /*
4027 * use EIAM to auto-mask when MSI-X interrupt is asserted
4028 * this saves a register write for every interrupt
4029 */
4030 switch (hw->mac.type) {
4031 case ixgbe_mac_82598EB:
4032 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4033 break;
9b471446 4034 case ixgbe_mac_82599EB:
b93a2226
DS		 4035 case ixgbe_mac_X540:
4036 default:
9b471446
JB		 4037 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4038 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4039 break;
4040 }
4041 } else {
021230d4
AV		 4042 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4043 * specifically only auto mask tx and rx interrupts */
4044 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4045 }
9a799d71 4046
a34bcfff
AD		 4047 /* XXX: to interrupt immediately for EICS writes, enable this */
4048 /* gpie |= IXGBE_GPIE_EIMEN; */
4049
4050 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4051 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4052
4053 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4054 case IXGBE_82599_VMDQ_8Q_MASK:
4055 gpie |= IXGBE_GPIE_VTMODE_16;
4056 break;
4057 case IXGBE_82599_VMDQ_4Q_MASK:
4058 gpie |= IXGBE_GPIE_VTMODE_32;
4059 break;
4060 default:
4061 gpie |= IXGBE_GPIE_VTMODE_64;
4062 break;
4063 }
119fc60a
MC		 4064 }
4065
5fdd31f9 4066 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4067 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4068 switch (adapter->hw.mac.type) {
4069 case ixgbe_mac_82599EB:
4070 gpie |= IXGBE_SDP0_GPIEN;
4071 break;
4072 case ixgbe_mac_X540:
4073 gpie |= IXGBE_EIMS_TS;
4074 break;
4075 default:
4076 break;
4077 }
4078 }
5fdd31f9 4079
a34bcfff
AD		 4080 /* Enable fan failure interrupt */
4081 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4082 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4083
2698b208 4084 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4085 gpie |= IXGBE_SDP1_GPIEN;
4086 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4087 }
a34bcfff
AD		 4088
4089 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4090}
4091
c7ccde0f 4092static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4093{
4094 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4095 int err;
a34bcfff
AD		 4096 u32 ctrl_ext;
4097
4098 ixgbe_get_hw_control(adapter);
4099 ixgbe_setup_gpie(adapter);
e8e26350 4100
9a799d71
AK		 4101 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4102 ixgbe_configure_msix(adapter);
4103 else
4104 ixgbe_configure_msi_and_legacy(adapter);
4105
ec74a471
ET		 4106 /* enable the optics for 82599 SFP+ fiber */
4107 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4108 hw->mac.ops.enable_tx_laser(hw);
4109
9a799d71 4110 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4111 ixgbe_napi_enable_all(adapter);
4112
73c4b7cd
AD		 4113 if (ixgbe_is_sfp(hw)) {
4114 ixgbe_sfp_link_config(adapter);
4115 } else {
4116 err = ixgbe_non_sfp_link_config(hw);
4117 if (err)
4118 e_err(probe, "link_config FAILED %d\n", err);
4119 }
4120
021230d4
AV		 4121 /* clear any pending interrupts, may auto mask */
4122 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4123 ixgbe_irq_enable(adapter, true, true);
9a799d71 4124
bf069c97
DS		 4125 /*
4126 * If this adapter has a fan, check to see if we had a failure
4127 * before we enabled the interrupt.
4128 */
4129 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4130 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4131 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4132 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4133 }
4134
1da100bb 4135 /* enable transmits */
477de6ed 4136 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4137
9a799d71
AK		 4138 /* bring the link up in the watchdog, this could race with our first
4139 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4140 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4141 adapter->link_check_timeout = jiffies;
7086400d 4142 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4143
4144 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4145 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4146 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4147 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4148}
4149
d4f80882
AV		 4150void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4151{
4152 WARN_ON(in_interrupt());
7086400d
AD		 4153 /* put off any impending NetWatchDogTimeout */
4154 adapter->netdev->trans_start = jiffies;
4155
d4f80882 4156 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4157 usleep_range(1000, 2000);
d4f80882 4158 ixgbe_down(adapter);
5809a1ae
GR		 4159 /*
4160 * If SR-IOV enabled then wait a bit before bringing the adapter
4161 * back up to give the VFs time to respond to the reset. The
4162 * two second wait is based upon the watchdog timer cycle in
4163 * the VF driver.
4164 */
4165 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4166 msleep(2000);
d4f80882
AV		 4167 ixgbe_up(adapter);
4168 clear_bit(__IXGBE_RESETTING, &adapter->state);
4169}
4170
c7ccde0f 4171void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4172{
4173 /* hardware has been reset, we need to reload some things */
4174 ixgbe_configure(adapter);
4175
c7ccde0f 4176 ixgbe_up_complete(adapter);
9a799d71
AK		 4177}
4178
4179void ixgbe_reset(struct ixgbe_adapter *adapter)
4180{
c44ade9e 4181 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4182 int err;
4183
7086400d
AD		 4184 /* lock SFP init bit to prevent race conditions with the watchdog */
4185 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4186 usleep_range(1000, 2000);
4187
4188 /* clear all SFP and link config related flags while holding SFP_INIT */
4189 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4190 IXGBE_FLAG2_SFP_NEEDS_RESET);
4191 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4192
8ca783ab 4193 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4194 switch (err) {
4195 case 0:
4196 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4197 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4198 break;
4199 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4200 e_dev_err("master disable timed out\n");
da4dd0f7 4201 break;
794caeb2
PWJ		 4202 case IXGBE_ERR_EEPROM_VERSION:
4203 /* We are running on a pre-production device, log a warning */
849c4542 4204 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4205 "Please be aware there may be issues associated with "
849c4542
ET		 4206 "your hardware. If you are experiencing problems "
4207 "please contact your Intel or hardware "
4208 "representative who provided you with this "
4209 "hardware.\n");
794caeb2 4210 break;
da4dd0f7 4211 default:
849c4542 4212 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4213 }
9a799d71 4214
7086400d
AD		 4215 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4216
9a799d71 4217 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4218 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4219
4220 /* update SAN MAC vmdq pool selection */
4221 if (hw->mac.san_mac_rar_index)
4222 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4223
1a71ab24
JK		 4224 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4225 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4226}
4227
9a799d71
AK		 4228/**
4229 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4230 * @rx_ring: ring to free buffers from
4231 **/
b6ec895e 4232static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4233{
b6ec895e 4234 struct device *dev = rx_ring->dev;
9a799d71 4235 unsigned long size;
b6ec895e 4236 u16 i;
9a799d71 4237
84418e3b
AD		 4238 /* ring already cleared, nothing to do */
4239 if (!rx_ring->rx_buffer_info)
4240 return;
9a799d71 4241
84418e3b 4242 /* Free all the Rx ring sk_buffs */
9a799d71 4243 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4244 struct ixgbe_rx_buffer *rx_buffer;
4245
4246 rx_buffer = &rx_ring->rx_buffer_info[i];
4247 if (rx_buffer->skb) {
4248 struct sk_buff *skb = rx_buffer->skb;
4249 if (IXGBE_CB(skb)->page_released) {
4250 dma_unmap_page(dev,
4251 IXGBE_CB(skb)->dma,
4252 ixgbe_rx_bufsz(rx_ring),
4253 DMA_FROM_DEVICE);
4254 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4255 }
4256 dev_kfree_skb(skb);
9a799d71 4257 }
f800326d
AD		 4258 rx_buffer->skb = NULL;
4259 if (rx_buffer->dma)
4260 dma_unmap_page(dev, rx_buffer->dma,
4261 ixgbe_rx_pg_size(rx_ring),
4262 DMA_FROM_DEVICE);
4263 rx_buffer->dma = 0;
4264 if (rx_buffer->page)
dd411ec4
AD		 4265 __free_pages(rx_buffer->page,
4266 ixgbe_rx_pg_order(rx_ring));
f800326d 4267 rx_buffer->page = NULL;
9a799d71
AK		 4268 }
4269
4270 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4271 memset(rx_ring->rx_buffer_info, 0, size);
4272
4273 /* Zero out the descriptor ring */
4274 memset(rx_ring->desc, 0, rx_ring->size);
4275
f800326d 4276 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4277 rx_ring->next_to_clean = 0;
4278 rx_ring->next_to_use = 0;
9a799d71
AK		 4279}
4280
4281/**
4282 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4283 * @tx_ring: ring to be cleaned
4284 **/
b6ec895e 4285static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4286{
4287 struct ixgbe_tx_buffer *tx_buffer_info;
4288 unsigned long size;
b6ec895e 4289 u16 i;
9a799d71 4290
84418e3b
AD		 4291 /* ring already cleared, nothing to do */
4292 if (!tx_ring->tx_buffer_info)
4293 return;
9a799d71 4294
84418e3b 4295 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4296 for (i = 0; i < tx_ring->count; i++) {
4297 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4298 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4299 }
4300
dad8a3b3
JF		 4301 netdev_tx_reset_queue(txring_txq(tx_ring));
4302
9a799d71
AK		 4303 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4304 memset(tx_ring->tx_buffer_info, 0, size);
4305
4306 /* Zero out the descriptor ring */
4307 memset(tx_ring->desc, 0, tx_ring->size);
4308
4309 tx_ring->next_to_use = 0;
4310 tx_ring->next_to_clean = 0;
9a799d71
AK		 4311}
4312
4313/**
021230d4 4314 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4315 * @adapter: board private structure
4316 **/
021230d4 4317static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4318{
4319 int i;
4320
021230d4 4321 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4322 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4323}
4324
4325/**
021230d4 4326 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4327 * @adapter: board private structure
4328 **/
021230d4 4329static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4330{
4331 int i;
4332
021230d4 4333 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4334 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4335}
4336
e4911d57
AD		 4337static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4338{
4339 struct hlist_node *node, *node2;
4340 struct ixgbe_fdir_filter *filter;
4341
4342 spin_lock(&adapter->fdir_perfect_lock);
4343
4344 hlist_for_each_entry_safe(filter, node, node2,
4345 &adapter->fdir_filter_list, fdir_node) {
4346 hlist_del(&filter->fdir_node);
4347 kfree(filter);
4348 }
4349 adapter->fdir_filter_count = 0;
4350
4351 spin_unlock(&adapter->fdir_perfect_lock);
4352}
4353
9a799d71
AK		 4354void ixgbe_down(struct ixgbe_adapter *adapter)
4355{
4356 struct net_device *netdev = adapter->netdev;
7f821875 4357 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4358 u32 rxctrl;
bf29ee6c 4359 int i;
9a799d71
AK		 4360
4361 /* signal that we are down to the interrupt handler */
4362 set_bit(__IXGBE_DOWN, &adapter->state);
4363
4364 /* disable receives */
7f821875
JB		 4365 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4366 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4367
2d39d576
YZ		 4368 /* disable all enabled rx queues */
4369 for (i = 0; i < adapter->num_rx_queues; i++)
4370 /* this call also flushes the previous write */
4371 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4372
032b4325 4373 usleep_range(10000, 20000);
9a799d71 4374
7f821875
JB		 4375 netif_tx_stop_all_queues(netdev);
4376
7086400d 4377 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4378 netif_carrier_off(netdev);
4379 netif_tx_disable(netdev);
4380
4381 ixgbe_irq_disable(adapter);
4382
4383 ixgbe_napi_disable_all(adapter);
4384
d034acf1
AD		 4385 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4386 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4387 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4388
4389 del_timer_sync(&adapter->service_timer);
4390
34cecbbf 4391 if (adapter->num_vfs) {
8e34d1aa
AD		 4392 /* Clear EITR Select mapping */
4393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4394
4395 /* Mark all the VFs as inactive */
4396 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4397 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4398
34cecbbf
AD		 4399 /* ping all the active vfs to let them know we are going down */
4400 ixgbe_ping_all_vfs(adapter);
4401
4402 /* Disable all VFTE/VFRE TX/RX */
4403 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4404 }
4405
7f821875
JB		 4406 /* disable transmits in the hardware now that interrupts are off */
4407 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4408 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4409 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4410 }
34cecbbf
AD		 4411
4412 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4413 switch (hw->mac.type) {
4414 case ixgbe_mac_82599EB:
b93a2226 4415 case ixgbe_mac_X540:
88512539 4416 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4417 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4418 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4419 break;
4420 default:
4421 break;
4422 }
7f821875 4423
6f4a0e45
PL		 4424 if (!pci_channel_offline(adapter->pdev))
4425 ixgbe_reset(adapter);
c6ecf39a 4426
ec74a471
ET		 4427 /* power down the optics for 82599 SFP+ fiber */
4428 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4429 hw->mac.ops.disable_tx_laser(hw);
4430
9a799d71
AK		 4431 ixgbe_clean_all_tx_rings(adapter);
4432 ixgbe_clean_all_rx_rings(adapter);
4433
5dd2d332 4434#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4435 /* since we reset the hardware DCA settings were cleared */
e35ec126 4436 ixgbe_setup_dca(adapter);
96b0e0f6 4437#endif
9a799d71
AK		 4438}
4439
9a799d71
AK		 4440/**
4441 * ixgbe_tx_timeout - Respond to a Tx Hang
4442 * @netdev: network interface device structure
4443 **/
4444static void ixgbe_tx_timeout(struct net_device *netdev)
4445{
4446 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4447
4448 /* Do the reset outside of interrupt context */
c83c6cbd 4449 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4450}
4451
9a799d71
AK		 4452/**
4453 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4454 * @adapter: board private structure to initialize
4455 *
4456 * ixgbe_sw_init initializes the Adapter private data structure.
4457 * Fields are initialized based on PCI device information and
4458 * OS network device settings (MTU size).
4459 **/
4460static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4461{
4462 struct ixgbe_hw *hw = &adapter->hw;
4463 struct pci_dev *pdev = adapter->pdev;
021230d4 4464 unsigned int rss;
7a6b6f51 4465#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4466 int j;
4467 struct tc_configuration *tc;
4468#endif
021230d4 4469
c44ade9e
JB		 4470 /* PCI config space info */
4471
4472 hw->vendor_id = pdev->vendor;
4473 hw->device_id = pdev->device;
4474 hw->revision_id = pdev->revision;
4475 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4476 hw->subsystem_device_id = pdev->subsystem_device;
4477
021230d4 4478 /* Set capability flags */
3ed69d7e 4479 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4480 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4481 switch (hw->mac.type) {
4482 case ixgbe_mac_82598EB:
bf069c97
DS		 4483 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4484 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4485 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4486 break;
b93a2226 4487 case ixgbe_mac_X540:
4f51bf70
JK		 4488 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4489 case ixgbe_mac_82599EB:
49c7ffbe 4490 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4491 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4492 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4493 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4494 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509 4495 /* Flow Director hash filters enabled */
45b9f509 4496 adapter->atr_sample_rate = 20;
c087663e 4497 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4498 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4499 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4500#ifdef IXGBE_FCOE
0d551589
YZ		 4501 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4502 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4503#ifdef CONFIG_IXGBE_DCB
6ee16520 4504 /* Default traffic class to use for FCoE */
56075a98 4505 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4506#endif
eacd73f7 4507#endif /* IXGBE_FCOE */
bd508178
AD		 4508 break;
4509 default:
4510 break;
f8212f97 4511 }
2f90b865 4512
7c8ae65a
AD		 4513#ifdef IXGBE_FCOE
4514 /* FCoE support exists, always init the FCoE lock */
4515 spin_lock_init(&adapter->fcoe.lock);
4516
4517#endif
1fc5f038
AD		 4518 /* n-tuple support exists, always init our spinlock */
4519 spin_lock_init(&adapter->fdir_perfect_lock);
4520
7a6b6f51 4521#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4522 switch (hw->mac.type) {
4523 case ixgbe_mac_X540:
4524 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4525 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4526 break;
4527 default:
4528 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4529 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4530 break;
4531 }
4532
2f90b865
AD		 4533 /* Configure DCB traffic classes */
4534 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4535 tc = &adapter->dcb_cfg.tc_config[j];
4536 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4537 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4538 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4539 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4540 tc->dcb_pfc = pfc_disabled;
4541 }
4de2a022
JF		 4542
4543 /* Initialize default user to priority mapping, UPx->TC0 */
4544 tc = &adapter->dcb_cfg.tc_config[0];
4545 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4546 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4547
2f90b865
AD		 4548 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4549 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4550 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4551 adapter->dcb_set_bitmap = 0x00;
3032309b 4552 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4553 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4554 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4555
4556#endif
9a799d71
AK		 4557
4558 /* default flow control settings */
cd7664f6 4559 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4560 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4561 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4562 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4563 hw->fc.send_xon = true;
71fd570b 4564 hw->fc.disable_fc_autoneg = false;
9a799d71 4565
99d74487
AD		 4566#ifdef CONFIG_PCI_IOV
4567 /* assign number of SR-IOV VFs */
4568 if (hw->mac.type != ixgbe_mac_82598EB)
4569 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4570
4571#endif
30efa5a3 4572 /* enable itr by default in dynamic mode */
f7554a2b 4573 adapter->rx_itr_setting = 1;
f7554a2b 4574 adapter->tx_itr_setting = 1;
30efa5a3 4575
30efa5a3
JB		 4576 /* set default ring sizes */
4577 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4578 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4579
bd198058 4580 /* set default work limits */
59224555 4581 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4582
9a799d71 4583 /* initialize eeprom parameters */
c44ade9e 4584 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4585 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4586 return -EIO;
4587 }
4588
9a799d71
AK		 4589 set_bit(__IXGBE_DOWN, &adapter->state);
4590
4591 return 0;
4592}
4593
4594/**
4595 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4596 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4597 *
4598 * Return 0 on success, negative on failure
4599 **/
b6ec895e 4600int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4601{
b6ec895e 4602 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4603 int orig_node = dev_to_node(dev);
4604 int numa_node = -1;
9a799d71
AK		 4605 int size;
4606
3a581073 4607 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4608
4609 if (tx_ring->q_vector)
4610 numa_node = tx_ring->q_vector->numa_node;
4611
4612 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4613 if (!tx_ring->tx_buffer_info)
89bf67f1 4614 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4615 if (!tx_ring->tx_buffer_info)
4616 goto err;
9a799d71
AK		 4617
4618 /* round up to nearest 4K */
12207e49 4619 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4620 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4621
de88eeeb
AD		 4622 set_dev_node(dev, numa_node);
4623 tx_ring->desc = dma_alloc_coherent(dev,
4624 tx_ring->size,
4625 &tx_ring->dma,
4626 GFP_KERNEL);
4627 set_dev_node(dev, orig_node);
4628 if (!tx_ring->desc)
4629 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4630 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4631 if (!tx_ring->desc)
4632 goto err;
9a799d71 4633
3a581073
JB		 4634 tx_ring->next_to_use = 0;
4635 tx_ring->next_to_clean = 0;
9a799d71 4636 return 0;
e01c31a5
JB		 4637
4638err:
4639 vfree(tx_ring->tx_buffer_info);
4640 tx_ring->tx_buffer_info = NULL;
b6ec895e 4641 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4642 return -ENOMEM;
9a799d71
AK		 4643}
4644
69888674
AD		 4645/**
4646 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4647 * @adapter: board private structure
4648 *
4649 * If this function returns with an error, then it's possible one or
4650 * more of the rings is populated (while the rest are not). It is the
4651 * callers duty to clean those orphaned rings.
4652 *
4653 * Return 0 on success, negative on failure
4654 **/
4655static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4656{
4657 int i, err = 0;
4658
4659 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4660 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4661 if (!err)
4662 continue;
de3d5b94 4663
396e799c 4664 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4665 goto err_setup_tx;
69888674
AD		 4666 }
4667
de3d5b94
AD		 4668 return 0;
4669err_setup_tx:
4670 /* rewind the index freeing the rings as we go */
4671 while (i--)
4672 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4673 return err;
4674}
4675
9a799d71
AK		 4676/**
4677 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4678 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4679 *
4680 * Returns 0 on success, negative on failure
4681 **/
b6ec895e 4682int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4683{
b6ec895e 4684 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4685 int orig_node = dev_to_node(dev);
4686 int numa_node = -1;
021230d4 4687 int size;
9a799d71 4688
3a581073 4689 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4690
4691 if (rx_ring->q_vector)
4692 numa_node = rx_ring->q_vector->numa_node;
4693
4694 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4695 if (!rx_ring->rx_buffer_info)
89bf67f1 4696 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4697 if (!rx_ring->rx_buffer_info)
4698 goto err;
9a799d71 4699
9a799d71 4700 /* Round up to nearest 4K */
3a581073
JB		 4701 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4702 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4703
de88eeeb
AD		 4704 set_dev_node(dev, numa_node);
4705 rx_ring->desc = dma_alloc_coherent(dev,
4706 rx_ring->size,
4707 &rx_ring->dma,
4708 GFP_KERNEL);
4709 set_dev_node(dev, orig_node);
4710 if (!rx_ring->desc)
4711 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4712 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4713 if (!rx_ring->desc)
4714 goto err;
9a799d71 4715
3a581073
JB		 4716 rx_ring->next_to_clean = 0;
4717 rx_ring->next_to_use = 0;
9a799d71
AK		 4718
4719 return 0;
b6ec895e
AD		 4720err:
4721 vfree(rx_ring->rx_buffer_info);
4722 rx_ring->rx_buffer_info = NULL;
4723 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4724 return -ENOMEM;
9a799d71
AK		 4725}
4726
69888674
AD		 4727/**
4728 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4729 * @adapter: board private structure
4730 *
4731 * If this function returns with an error, then it's possible one or
4732 * more of the rings is populated (while the rest are not). It is the
4733 * callers duty to clean those orphaned rings.
4734 *
4735 * Return 0 on success, negative on failure
4736 **/
69888674
AD		 4737static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4738{
4739 int i, err = 0;
4740
4741 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4742 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4743 if (!err)
4744 continue;
de3d5b94 4745
396e799c 4746 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4747 goto err_setup_rx;
69888674
AD		 4748 }
4749
7c8ae65a
AD		 4750#ifdef IXGBE_FCOE
4751 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4752 if (!err)
4753#endif
4754 return 0;
de3d5b94
AD		 4755err_setup_rx:
4756 /* rewind the index freeing the rings as we go */
4757 while (i--)
4758 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4759 return err;
4760}
4761
9a799d71
AK		 4762/**
4763 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4764 * @tx_ring: Tx descriptor ring for a specific queue
4765 *
4766 * Free all transmit software resources
4767 **/
b6ec895e 4768void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4769{
b6ec895e 4770 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4771
4772 vfree(tx_ring->tx_buffer_info);
4773 tx_ring->tx_buffer_info = NULL;
4774
b6ec895e
AD		 4775 /* if not set, then don't free */
4776 if (!tx_ring->desc)
4777 return;
4778
4779 dma_free_coherent(tx_ring->dev, tx_ring->size,
4780 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4781
4782 tx_ring->desc = NULL;
4783}
4784
4785/**
4786 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4787 * @adapter: board private structure
4788 *
4789 * Free all transmit software resources
4790 **/
4791static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4792{
4793 int i;
4794
4795 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4796 if (adapter->tx_ring[i]->desc)
b6ec895e 4797 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4798}
4799
4800/**
b4617240 4801 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4802 * @rx_ring: ring to clean the resources from
4803 *
4804 * Free all receive software resources
4805 **/
b6ec895e 4806void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4807{
b6ec895e 4808 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4809
4810 vfree(rx_ring->rx_buffer_info);
4811 rx_ring->rx_buffer_info = NULL;
4812
b6ec895e
AD		 4813 /* if not set, then don't free */
4814 if (!rx_ring->desc)
4815 return;
4816
4817 dma_free_coherent(rx_ring->dev, rx_ring->size,
4818 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4819
4820 rx_ring->desc = NULL;
4821}
4822
4823/**
4824 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4825 * @adapter: board private structure
4826 *
4827 * Free all receive software resources
4828 **/
4829static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4830{
4831 int i;
4832
7c8ae65a
AD		 4833#ifdef IXGBE_FCOE
4834 ixgbe_free_fcoe_ddp_resources(adapter);
4835
4836#endif
9a799d71 4837 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4838 if (adapter->rx_ring[i]->desc)
b6ec895e 4839 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4840}
4841
9a799d71
AK		 4842/**
4843 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4844 * @netdev: network interface device structure
4845 * @new_mtu: new value for maximum frame size
4846 *
4847 * Returns 0 on success, negative on failure
4848 **/
4849static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4850{
4851 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4852 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4853
42c783c5 4854 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4855 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4856 return -EINVAL;
4857
4858 /*
872844dd
AD		 4859 * For 82599EB we cannot allow legacy VFs to enable their receive
4860 * paths when MTU greater than 1500 is configured. So display a
4861 * warning that legacy VFs will be disabled.
655309e9
AD		 4862 */
4863 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4864 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4865 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
872844dd 4866 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 4867
396e799c 4868 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4869
021230d4 4870 /* must set new MTU before calling down or up */
9a799d71
AK		 4871 netdev->mtu = new_mtu;
4872
d4f80882
AV		 4873 if (netif_running(netdev))
4874 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4875
4876 return 0;
4877}
4878
4879/**
4880 * ixgbe_open - Called when a network interface is made active
4881 * @netdev: network interface device structure
4882 *
4883 * Returns 0 on success, negative value on failure
4884 *
4885 * The open entry point is called when a network interface is made
4886 * active by the system (IFF_UP). At this point all resources needed
4887 * for transmit and receive operations are allocated, the interrupt
4888 * handler is registered with the OS, the watchdog timer is started,
4889 * and the stack is notified that the interface is ready.
4890 **/
4891static int ixgbe_open(struct net_device *netdev)
4892{
4893 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4894 int err;
4bebfaa5
AK		 4895
4896 /* disallow open during test */
4897 if (test_bit(__IXGBE_TESTING, &adapter->state))
4898 return -EBUSY;
9a799d71 4899
54386467
JB		 4900 netif_carrier_off(netdev);
4901
9a799d71
AK		 4902 /* allocate transmit descriptors */
4903 err = ixgbe_setup_all_tx_resources(adapter);
4904 if (err)
4905 goto err_setup_tx;
4906
9a799d71
AK		 4907 /* allocate receive descriptors */
4908 err = ixgbe_setup_all_rx_resources(adapter);
4909 if (err)
4910 goto err_setup_rx;
4911
4912 ixgbe_configure(adapter);
4913
021230d4 4914 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4915 if (err)
4916 goto err_req_irq;
4917
ac802f5d
AD		 4918 /* Notify the stack of the actual queue counts. */
4919 err = netif_set_real_num_tx_queues(netdev,
4920 adapter->num_rx_pools > 1 ? 1 :
4921 adapter->num_tx_queues);
4922 if (err)
4923 goto err_set_queues;
4924
4925
4926 err = netif_set_real_num_rx_queues(netdev,
4927 adapter->num_rx_pools > 1 ? 1 :
4928 adapter->num_rx_queues);
4929 if (err)
4930 goto err_set_queues;
4931
1a71ab24 4932 ixgbe_ptp_init(adapter);
1a71ab24 4933
c7ccde0f 4934 ixgbe_up_complete(adapter);
9a799d71
AK		 4935
4936 return 0;
4937
ac802f5d
AD		 4938err_set_queues:
4939 ixgbe_free_irq(adapter);
9a799d71 4940err_req_irq:
a20a1199 4941 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4942err_setup_rx:
a20a1199 4943 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4944err_setup_tx:
9a799d71
AK		 4945 ixgbe_reset(adapter);
4946
4947 return err;
4948}
4949
4950/**
4951 * ixgbe_close - Disables a network interface
4952 * @netdev: network interface device structure
4953 *
4954 * Returns 0, this is not allowed to fail
4955 *
4956 * The close entry point is called when an interface is de-activated
4957 * by the OS. The hardware is still under the drivers control, but
4958 * needs to be disabled. A global MAC reset is issued to stop the
4959 * hardware, and all transmit and receive resources are freed.
4960 **/
4961static int ixgbe_close(struct net_device *netdev)
4962{
4963 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 4964
1a71ab24 4965 ixgbe_ptp_stop(adapter);
1a71ab24 4966
9a799d71
AK		 4967 ixgbe_down(adapter);
4968 ixgbe_free_irq(adapter);
4969
e4911d57
AD		 4970 ixgbe_fdir_filter_exit(adapter);
4971
9a799d71
AK		 4972 ixgbe_free_all_tx_resources(adapter);
4973 ixgbe_free_all_rx_resources(adapter);
4974
5eba3699 4975 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4976
4977 return 0;
4978}
4979
b3c8b4ba
AD		 4980#ifdef CONFIG_PM
4981static int ixgbe_resume(struct pci_dev *pdev)
4982{
c60fbb00
AD		 4983 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4984 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4985 u32 err;
4986
4987 pci_set_power_state(pdev, PCI_D0);
4988 pci_restore_state(pdev);
656ab817
DS		 4989 /*
4990 * pci_restore_state clears dev->state_saved so call
4991 * pci_save_state to restore it.
4992 */
4993 pci_save_state(pdev);
9ce77666 4994
4995 err = pci_enable_device_mem(pdev);
b3c8b4ba 4996 if (err) {
849c4542 4997 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 4998 return err;
4999 }
5000 pci_set_master(pdev);
5001
dd4d8ca6 5002 pci_wake_from_d3(pdev, false);
b3c8b4ba 5003
b3c8b4ba
AD		 5004 ixgbe_reset(adapter);
5005
495dce12
WJP		 5006 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5007
ac802f5d
AD		 5008 rtnl_lock();
5009 err = ixgbe_init_interrupt_scheme(adapter);
5010 if (!err && netif_running(netdev))
c60fbb00 5011 err = ixgbe_open(netdev);
ac802f5d
AD		 5012
5013 rtnl_unlock();
5014
5015 if (err)
5016 return err;
b3c8b4ba
AD		 5017
5018 netif_device_attach(netdev);
5019
5020 return 0;
5021}
b3c8b4ba 5022#endif /* CONFIG_PM */
9d8d05ae
RW		 5023
5024static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5025{
c60fbb00
AD		 5026 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5027 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5028 struct ixgbe_hw *hw = &adapter->hw;
5029 u32 ctrl, fctrl;
5030 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5031#ifdef CONFIG_PM
5032 int retval = 0;
5033#endif
5034
5035 netif_device_detach(netdev);
5036
5037 if (netif_running(netdev)) {
ab6039a7 5038 rtnl_lock();
b3c8b4ba
AD		 5039 ixgbe_down(adapter);
5040 ixgbe_free_irq(adapter);
5041 ixgbe_free_all_tx_resources(adapter);
5042 ixgbe_free_all_rx_resources(adapter);
ab6039a7 5043 rtnl_unlock();
b3c8b4ba 5044 }
b3c8b4ba 5045
5f5ae6fc
AD		 5046 ixgbe_clear_interrupt_scheme(adapter);
5047
b3c8b4ba
AD		 5048#ifdef CONFIG_PM
5049 retval = pci_save_state(pdev);
5050 if (retval)
5051 return retval;
4df10466 5052
b3c8b4ba 5053#endif
e8e26350
PW		 5054 if (wufc) {
5055 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5056
ec74a471
ET		 5057 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5058 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5059 hw->mac.ops.enable_tx_laser(hw);
5060
e8e26350
PW		 5061 /* turn on all-multi mode if wake on multicast is enabled */
5062 if (wufc & IXGBE_WUFC_MC) {
5063 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5064 fctrl |= IXGBE_FCTRL_MPE;
5065 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5066 }
5067
5068 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5069 ctrl |= IXGBE_CTRL_GIO_DIS;
5070 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5071
5072 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5073 } else {
5074 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5075 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5076 }
5077
bd508178
AD		 5078 switch (hw->mac.type) {
5079 case ixgbe_mac_82598EB:
dd4d8ca6 5080 pci_wake_from_d3(pdev, false);
bd508178
AD		 5081 break;
5082 case ixgbe_mac_82599EB:
b93a2226 5083 case ixgbe_mac_X540:
bd508178
AD		 5084 pci_wake_from_d3(pdev, !!wufc);
5085 break;
5086 default:
5087 break;
5088 }
b3c8b4ba 5089
9d8d05ae
RW		 5090 *enable_wake = !!wufc;
5091
b3c8b4ba
AD		 5092 ixgbe_release_hw_control(adapter);
5093
5094 pci_disable_device(pdev);
5095
9d8d05ae
RW		 5096 return 0;
5097}
5098
5099#ifdef CONFIG_PM
5100static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5101{
5102 int retval;
5103 bool wake;
5104
5105 retval = __ixgbe_shutdown(pdev, &wake);
5106 if (retval)
5107 return retval;
5108
5109 if (wake) {
5110 pci_prepare_to_sleep(pdev);
5111 } else {
5112 pci_wake_from_d3(pdev, false);
5113 pci_set_power_state(pdev, PCI_D3hot);
5114 }
b3c8b4ba
AD		 5115
5116 return 0;
5117}
9d8d05ae 5118#endif /* CONFIG_PM */
b3c8b4ba
AD		 5119
5120static void ixgbe_shutdown(struct pci_dev *pdev)
5121{
9d8d05ae
RW		 5122 bool wake;
5123
5124 __ixgbe_shutdown(pdev, &wake);
5125
5126 if (system_state == SYSTEM_POWER_OFF) {
5127 pci_wake_from_d3(pdev, wake);
5128 pci_set_power_state(pdev, PCI_D3hot);
5129 }
b3c8b4ba
AD		 5130}
5131
9a799d71
AK		 5132/**
5133 * ixgbe_update_stats - Update the board statistics counters.
5134 * @adapter: board private structure
5135 **/
5136void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5137{
2d86f139 5138 struct net_device *netdev = adapter->netdev;
9a799d71 5139 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5140 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5141 u64 total_mpc = 0;
5142 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5143 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5144 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5145 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5146
d08935c2
DS		 5147 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5148 test_bit(__IXGBE_RESETTING, &adapter->state))
5149 return;
5150
94b982b2 5151 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5152 u64 rsc_count = 0;
94b982b2 5153 u64 rsc_flush = 0;
94b982b2 5154 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5155 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5156 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5157 }
5158 adapter->rsc_total_count = rsc_count;
5159 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5160 }
5161
5b7da515
AD		 5162 for (i = 0; i < adapter->num_rx_queues; i++) {
5163 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5164 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5165 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5166 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5167 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5168 bytes += rx_ring->stats.bytes;
5169 packets += rx_ring->stats.packets;
5170 }
5171 adapter->non_eop_descs = non_eop_descs;
5172 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5173 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5174 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5175 netdev->stats.rx_bytes = bytes;
5176 netdev->stats.rx_packets = packets;
5177
5178 bytes = 0;
5179 packets = 0;
7ca3bc58 5180 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5181 for (i = 0; i < adapter->num_tx_queues; i++) {
5182 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5183 restart_queue += tx_ring->tx_stats.restart_queue;
5184 tx_busy += tx_ring->tx_stats.tx_busy;
5185 bytes += tx_ring->stats.bytes;
5186 packets += tx_ring->stats.packets;
5187 }
eb985f09 5188 adapter->restart_queue = restart_queue;
5b7da515
AD		 5189 adapter->tx_busy = tx_busy;
5190 netdev->stats.tx_bytes = bytes;
5191 netdev->stats.tx_packets = packets;
7ca3bc58 5192
7ca647bd 5193 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5194
5195 /* 8 register reads */
6f11eef7
AV		 5196 for (i = 0; i < 8; i++) {
5197 /* for packet buffers not used, the register should read 0 */
5198 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5199 missed_rx += mpc;
7ca647bd
JP		 5200 hwstats->mpc[i] += mpc;
5201 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5202 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5203 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5204 switch (hw->mac.type) {
5205 case ixgbe_mac_82598EB:
1a70db4b
ET		 5206 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5207 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5208 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5209 hwstats->pxonrxc[i] +=
5210 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5211 break;
5212 case ixgbe_mac_82599EB:
b93a2226 5213 case ixgbe_mac_X540:
bd508178
AD		 5214 hwstats->pxonrxc[i] +=
5215 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5216 break;
5217 default:
5218 break;
e8e26350 5219 }
6f11eef7 5220 }
1a70db4b
ET		 5221
5222 /*16 register reads */
5223 for (i = 0; i < 16; i++) {
5224 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5225 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5226 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5227 (hw->mac.type == ixgbe_mac_X540)) {
5228 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5229 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5230 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5231 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5232 }
5233 }
5234
7ca647bd 5235 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5236 /* work around hardware counting issue */
7ca647bd 5237 hwstats->gprc -= missed_rx;
6f11eef7 5238
c84d324c
JF		 5239 ixgbe_update_xoff_received(adapter);
5240
6f11eef7 5241 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5242 switch (hw->mac.type) {
5243 case ixgbe_mac_82598EB:
5244 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5245 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5246 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5247 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5248 break;
b93a2226 5249 case ixgbe_mac_X540:
58f6bcf9
ET		 5250 /* OS2BMC stats are X540 only*/
5251 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5252 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5253 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5254 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5255 case ixgbe_mac_82599EB:
a4d4f629
AD		 5256 for (i = 0; i < 16; i++)
5257 adapter->hw_rx_no_dma_resources +=
5258 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5259 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5260 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5261 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5262 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5263 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5264 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5265 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5266 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5267 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5268#ifdef IXGBE_FCOE
7ca647bd
JP		 5269 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5270 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5271 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5272 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5273 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5274 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5275 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5276 if (adapter->fcoe.ddp_pool) {
5277 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5278 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5279 unsigned int cpu;
5280 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5281 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5282 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5283 noddp += ddp_pool->noddp;
5284 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5285 }
5a1ee270
AD		 5286 hwstats->fcoe_noddp = noddp;
5287 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5288 }
6d45522c 5289#endif /* IXGBE_FCOE */
bd508178
AD		 5290 break;
5291 default:
5292 break;
e8e26350 5293 }
9a799d71 5294 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5295 hwstats->bprc += bprc;
5296 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5297 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5298 hwstats->mprc -= bprc;
5299 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5300 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5301 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5302 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5303 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5304 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5305 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5306 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5307 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5308 hwstats->lxontxc += lxon;
6f11eef7 5309 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5310 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5311 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5312 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5313 /*
5314 * 82598 errata - tx of flow control packets is included in tx counters
5315 */
5316 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5317 hwstats->gptc -= xon_off_tot;
5318 hwstats->mptc -= xon_off_tot;
5319 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5320 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5321 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5322 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5323 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5324 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5325 hwstats->ptc64 -= xon_off_tot;
5326 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5327 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5328 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5329 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5330 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5331 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5332
5333 /* Fill out the OS statistics structure */
7ca647bd 5334 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5335
5336 /* Rx Errors */
7ca647bd 5337 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5338 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5339 netdev->stats.rx_length_errors = hwstats->rlec;
5340 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5341 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5342}
5343
5344/**
d034acf1 5345 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5346 * @adapter: pointer to the device adapter structure
9a799d71 5347 **/
d034acf1 5348static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5349{
cf8280ee 5350 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5351 int i;
cf8280ee 5352
d034acf1
AD		 5353 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5354 return;
5355
5356 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5357
d034acf1 5358 /* if interface is down do nothing */
fe49f04a 5359 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5360 return;
5361
5362 /* do nothing if we are not using signature filters */
5363 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5364 return;
5365
5366 adapter->fdir_overflow++;
5367
93c52dd0
AD		 5368 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5369 for (i = 0; i < adapter->num_tx_queues; i++)
5370 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5371 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5372 /* re-enable flow director interrupts */
5373 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5374 } else {
5375 e_err(probe, "failed to finish FDIR re-initialization, "
5376 "ignored adding FDIR ATR filters\n");
5377 }
93c52dd0
AD		 5378}
5379
5380/**
5381 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5382 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5383 *
5384 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5385 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5386 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5387 * determine if a hang has occurred.
93c52dd0
AD		 5388 */
5389static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5390{
cf8280ee 5391 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5392 u64 eics = 0;
5393 int i;
cf8280ee 5394
93c52dd0
AD		 5395 /* If we're down or resetting, just bail */
5396 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5397 test_bit(__IXGBE_RESETTING, &adapter->state))
5398 return;
22d5a71b 5399
93c52dd0
AD		 5400 /* Force detection of hung controller */
5401 if (netif_carrier_ok(adapter->netdev)) {
5402 for (i = 0; i < adapter->num_tx_queues; i++)
5403 set_check_for_tx_hang(adapter->tx_ring[i]);
5404 }
22d5a71b 5405
fe49f04a
AD		 5406 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5407 /*
5408 * for legacy and MSI interrupts don't set any bits
5409 * that are enabled for EIAM, because this operation
5410 * would set *both* EIMS and EICS for any bit in EIAM
5411 */
5412 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5413 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5414 } else {
5415 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5416 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5417 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5418 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5419 eics |= ((u64)1 << i);
5420 }
cf8280ee 5421 }
9a799d71 5422
93c52dd0 5423 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5424 ixgbe_irq_rearm_queues(adapter, eics);
5425
cf8280ee
JB		 5426}
5427
e8e26350 5428/**
93c52dd0 5429 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5430 * @adapter: pointer to the device adapter structure
5431 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5432 **/
93c52dd0 5433static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5434{
e8e26350 5435 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5436 u32 link_speed = adapter->link_speed;
5437 bool link_up = adapter->link_up;
041441d0 5438 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5439
93c52dd0
AD		 5440 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5441 return;
5442
5443 if (hw->mac.ops.check_link) {
5444 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5445 } else {
93c52dd0
AD		 5446 /* always assume link is up, if no check link function */
5447 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5448 link_up = true;
c4cf55e5 5449 }
041441d0
AD		 5450
5451 if (adapter->ixgbe_ieee_pfc)
5452 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5453
3ebe8fde 5454 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5455 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5456 ixgbe_set_rx_drop_en(adapter);
5457 }
93c52dd0
AD		 5458
5459 if (link_up ||
5460 time_after(jiffies, (adapter->link_check_timeout +
5461 IXGBE_TRY_LINK_TIMEOUT))) {
5462 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5463 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5464 IXGBE_WRITE_FLUSH(hw);
5465 }
5466
5467 adapter->link_up = link_up;
5468 adapter->link_speed = link_speed;
e8e26350
PW		 5469}
5470
107d3018
AD		 5471static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5472{
5473#ifdef CONFIG_IXGBE_DCB
5474 struct net_device *netdev = adapter->netdev;
5475 struct dcb_app app = {
5476 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5477 .protocol = 0,
5478 };
5479 u8 up = 0;
5480
5481 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5482 up = dcb_ieee_getapp_mask(netdev, &app);
5483
5484 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5485#endif
5486}
5487
e8e26350 5488/**
93c52dd0
AD		 5489 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5490 * print link up message
49ce9c2c 5491 * @adapter: pointer to the device adapter structure
e8e26350 5492 **/
93c52dd0 5493static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5494{
93c52dd0 5495 struct net_device *netdev = adapter->netdev;
e8e26350 5496 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5497 u32 link_speed = adapter->link_speed;
5498 bool flow_rx, flow_tx;
e8e26350 5499
93c52dd0
AD		 5500 /* only continue if link was previously down */
5501 if (netif_carrier_ok(netdev))
a985b6c3 5502 return;
63d6e1d8 5503
93c52dd0 5504 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5505
93c52dd0
AD		 5506 switch (hw->mac.type) {
5507 case ixgbe_mac_82598EB: {
5508 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5509 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5510 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5511 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5512 }
5513 break;
5514 case ixgbe_mac_X540:
5515 case ixgbe_mac_82599EB: {
5516 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5517 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5518 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5519 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5520 }
5521 break;
5522 default:
5523 flow_tx = false;
5524 flow_rx = false;
5525 break;
e8e26350 5526 }
3a6a4eda 5527
1a71ab24
JK		 5528 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5529 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5530
93c52dd0
AD		 5531 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5532 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5533 "10 Gbps" :
5534 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5535 "1 Gbps" :
5536 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5537 "100 Mbps" :
5538 "unknown speed"))),
5539 ((flow_rx && flow_tx) ? "RX/TX" :
5540 (flow_rx ? "RX" :
5541 (flow_tx ? "TX" : "None"))));
e8e26350 5542
93c52dd0 5543 netif_carrier_on(netdev);
93c52dd0 5544 ixgbe_check_vf_rate_limit(adapter);
befa2af7 5545
107d3018
AD		 5546 /* update the default user priority for VFs */
5547 ixgbe_update_default_up(adapter);
5548
befa2af7
AD		 5549 /* ping all the active vfs to let them know link has changed */
5550 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5551}
5552
c4cf55e5 5553/**
93c52dd0
AD		 5554 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5555 * print link down message
49ce9c2c 5556 * @adapter: pointer to the adapter structure
c4cf55e5 5557 **/
581330ba 5558static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5559{
cf8280ee 5560 struct net_device *netdev = adapter->netdev;
c4cf55e5 5561 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5562
93c52dd0
AD		 5563 adapter->link_up = false;
5564 adapter->link_speed = 0;
cf8280ee 5565
93c52dd0
AD		 5566 /* only continue if link was up previously */
5567 if (!netif_carrier_ok(netdev))
5568 return;
264857b8 5569
93c52dd0
AD		 5570 /* poll for SFP+ cable when link is down */
5571 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5572 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5573
1a71ab24
JK		 5574 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5575 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5576
93c52dd0
AD		 5577 e_info(drv, "NIC Link is Down\n");
5578 netif_carrier_off(netdev);
befa2af7
AD		 5579
5580 /* ping all the active vfs to let them know link has changed */
5581 ixgbe_ping_all_vfs(adapter);
93c52dd0 5582}
e8e26350 5583
93c52dd0
AD		 5584/**
5585 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5586 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5587 **/
5588static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5589{
c4cf55e5 5590 int i;
93c52dd0 5591 int some_tx_pending = 0;
c4cf55e5 5592
93c52dd0 5593 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5594 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5595 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5596 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5597 some_tx_pending = 1;
5598 break;
5599 }
5600 }
5601
5602 if (some_tx_pending) {
5603 /* We've lost link, so the controller stops DMA,
5604 * but we've got queued Tx work that's never going
5605 * to get done, so reset controller to flush Tx.
5606 * (Do the reset outside of interrupt context).
5607 */
c83c6cbd 5608 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5609 }
c4cf55e5 5610 }
c4cf55e5
PWJ		 5611}
5612
a985b6c3
GR		 5613static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5614{
5615 u32 ssvpc;
5616
0584d999
GR		 5617 /* Do not perform spoof check for 82598 or if not in IOV mode */
5618 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5619 adapter->num_vfs == 0)
a985b6c3
GR		 5620 return;
5621
5622 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5623
5624 /*
5625 * ssvpc register is cleared on read, if zero then no
5626 * spoofed packets in the last interval.
5627 */
5628 if (!ssvpc)
5629 return;
5630
d6ea0754 5631 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 5632}
5633
93c52dd0
AD		 5634/**
5635 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5636 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5637 **/
5638static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5639{
5640 /* if interface is down do nothing */
7edebf9a
ET		 5641 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5642 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5643 return;
5644
5645 ixgbe_watchdog_update_link(adapter);
5646
5647 if (adapter->link_up)
5648 ixgbe_watchdog_link_is_up(adapter);
5649 else
5650 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5651
a985b6c3 5652 ixgbe_spoof_check(adapter);
9a799d71 5653 ixgbe_update_stats(adapter);
93c52dd0
AD		 5654
5655 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5656}
10eec955 5657
cf8280ee 5658/**
7086400d 5659 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5660 * @adapter: the ixgbe adapter structure
cf8280ee 5661 **/
7086400d 5662static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5663{
cf8280ee 5664 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5665 s32 err;
cf8280ee 5666
7086400d
AD		 5667 /* not searching for SFP so there is nothing to do here */
5668 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5669 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5670 return;
10eec955 5671
7086400d
AD		 5672 /* someone else is in init, wait until next service event */
5673 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5674 return;
cf8280ee 5675
7086400d
AD		 5676 err = hw->phy.ops.identify_sfp(hw);
5677 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5678 goto sfp_out;
264857b8 5679
7086400d
AD		 5680 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5681 /* If no cable is present, then we need to reset
5682 * the next time we find a good cable. */
5683 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5684 }
9a799d71 5685
7086400d
AD		 5686 /* exit on error */
5687 if (err)
5688 goto sfp_out;
e8e26350 5689
7086400d
AD		 5690 /* exit if reset not needed */
5691 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5692 goto sfp_out;
9a799d71 5693
7086400d 5694 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5695
7086400d
AD		 5696 /*
5697 * A module may be identified correctly, but the EEPROM may not have
5698 * support for that module. setup_sfp() will fail in that case, so
5699 * we should not allow that module to load.
5700 */
5701 if (hw->mac.type == ixgbe_mac_82598EB)
5702 err = hw->phy.ops.reset(hw);
5703 else
5704 err = hw->mac.ops.setup_sfp(hw);
5705
5706 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5707 goto sfp_out;
5708
5709 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5710 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5711
5712sfp_out:
5713 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5714
5715 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5716 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5717 e_dev_err("failed to initialize because an unsupported "
5718 "SFP+ module type was detected.\n");
5719 e_dev_err("Reload the driver after installing a "
5720 "supported module.\n");
5721 unregister_netdev(adapter->netdev);
bc59fcda 5722 }
7086400d 5723}
bc59fcda 5724
7086400d
AD		 5725/**
5726 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5727 * @adapter: the ixgbe adapter structure
7086400d
AD		 5728 **/
5729static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5730{
5731 struct ixgbe_hw *hw = &adapter->hw;
5732 u32 autoneg;
5733 bool negotiation;
5734
5735 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5736 return;
5737
5738 /* someone else is in init, wait until next service event */
5739 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5740 return;
5741
5742 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5743
5744 autoneg = hw->phy.autoneg_advertised;
5745 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5746 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5747 if (hw->mac.ops.setup_link)
5748 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5749
5750 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5751 adapter->link_check_timeout = jiffies;
5752 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5753}
5754
83c61fa9
GR		 5755#ifdef CONFIG_PCI_IOV
5756static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5757{
5758 int vf;
5759 struct ixgbe_hw *hw = &adapter->hw;
5760 struct net_device *netdev = adapter->netdev;
5761 u32 gpc;
5762 u32 ciaa, ciad;
5763
5764 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5765 if (gpc) /* If incrementing then no need for the check below */
5766 return;
5767 /*
5768 * Check to see if a bad DMA write target from an errant or
5769 * malicious VF has caused a PCIe error. If so then we can
5770 * issue a VFLR to the offending VF(s) and then resume without
5771 * requesting a full slot reset.
5772 */
5773
5774 for (vf = 0; vf < adapter->num_vfs; vf++) {
5775 ciaa = (vf << 16) | 0x80000000;
5776 /* 32 bit read so align, we really want status at offset 6 */
5777 ciaa |= PCI_COMMAND;
5778 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5779 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5780 ciaa &= 0x7FFFFFFF;
5781 /* disable debug mode asap after reading data */
5782 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5783 /* Get the upper 16 bits which will be the PCI status reg */
5784 ciad >>= 16;
5785 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5786 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5787 /* Issue VFLR */
5788 ciaa = (vf << 16) | 0x80000000;
5789 ciaa |= 0xA8;
5790 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5791 ciad = 0x00008000; /* VFLR */
5792 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5793 ciaa &= 0x7FFFFFFF;
5794 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5795 }
5796 }
5797}
5798
5799#endif
7086400d
AD		 5800/**
5801 * ixgbe_service_timer - Timer Call-back
5802 * @data: pointer to adapter cast into an unsigned long
5803 **/
5804static void ixgbe_service_timer(unsigned long data)
5805{
5806 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5807 unsigned long next_event_offset;
83c61fa9 5808 bool ready = true;
7086400d 5809
6bb78cfb
AD		 5810 /* poll faster when waiting for link */
5811 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5812 next_event_offset = HZ / 10;
5813 else
5814 next_event_offset = HZ * 2;
83c61fa9 5815
6bb78cfb 5816#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5817 /*
5818 * don't bother with SR-IOV VF DMA hang check if there are
5819 * no VFs or the link is down
5820 */
5821 if (!adapter->num_vfs ||
6bb78cfb 5822 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5823 goto normal_timer_service;
83c61fa9
GR		 5824
5825 /* If we have VFs allocated then we must check for DMA hangs */
5826 ixgbe_check_for_bad_vf(adapter);
5827 next_event_offset = HZ / 50;
5828 adapter->timer_event_accumulator++;
5829
6bb78cfb 5830 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5831 adapter->timer_event_accumulator = 0;
7086400d 5832 else
6bb78cfb 5833 ready = false;
7086400d 5834
6bb78cfb 5835normal_timer_service:
83c61fa9 5836#endif
7086400d
AD		 5837 /* Reset the timer */
5838 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5839
83c61fa9
GR		 5840 if (ready)
5841 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5842}
5843
c83c6cbd
AD		 5844static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5845{
5846 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5847 return;
5848
5849 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5850
5851 /* If we're already down or resetting, just bail */
5852 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5853 test_bit(__IXGBE_RESETTING, &adapter->state))
5854 return;
5855
5856 ixgbe_dump(adapter);
5857 netdev_err(adapter->netdev, "Reset adapter\n");
5858 adapter->tx_timeout_count++;
5859
5860 ixgbe_reinit_locked(adapter);
5861}
5862
7086400d
AD		 5863/**
5864 * ixgbe_service_task - manages and runs subtasks
5865 * @work: pointer to work_struct containing our data
5866 **/
5867static void ixgbe_service_task(struct work_struct *work)
5868{
5869 struct ixgbe_adapter *adapter = container_of(work,
5870 struct ixgbe_adapter,
5871 service_task);
5872
c83c6cbd 5873 ixgbe_reset_subtask(adapter);
7086400d
AD		 5874 ixgbe_sfp_detection_subtask(adapter);
5875 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5876 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5877 ixgbe_watchdog_subtask(adapter);
d034acf1 5878 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5879 ixgbe_check_hang_subtask(adapter);
3a6a4eda 5880 ixgbe_ptp_overflow_check(adapter);
7086400d
AD		 5881
5882 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5883}
5884
fd0db0ed
AD		 5885static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5886 struct ixgbe_tx_buffer *first,
244e27ad 5887 u8 *hdr_len)
897ab156 5888{
fd0db0ed 5889 struct sk_buff *skb = first->skb;
897ab156
AD		 5890 u32 vlan_macip_lens, type_tucmd;
5891 u32 mss_l4len_idx, l4len;
9a799d71 5892
897ab156
AD		 5893 if (!skb_is_gso(skb))
5894 return 0;
9a799d71 5895
897ab156 5896 if (skb_header_cloned(skb)) {
244e27ad 5897 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5898 if (err)
5899 return err;
9a799d71 5900 }
9a799d71 5901
897ab156
AD		 5902 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5903 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5904
244e27ad 5905 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5906 struct iphdr *iph = ip_hdr(skb);
5907 iph->tot_len = 0;
5908 iph->check = 0;
5909 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5910 iph->daddr, 0,
5911 IPPROTO_TCP,
5912 0);
5913 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5914 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5915 IXGBE_TX_FLAGS_CSUM |
5916 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5917 } else if (skb_is_gso_v6(skb)) {
5918 ipv6_hdr(skb)->payload_len = 0;
5919 tcp_hdr(skb)->check =
5920 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5921 &ipv6_hdr(skb)->daddr,
5922 0, IPPROTO_TCP, 0);
244e27ad
AD		 5923 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5924 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5925 }
5926
091a6246 5927 /* compute header lengths */
897ab156
AD		 5928 l4len = tcp_hdrlen(skb);
5929 *hdr_len = skb_transport_offset(skb) + l4len;
5930
091a6246
AD		 5931 /* update gso size and bytecount with header size */
5932 first->gso_segs = skb_shinfo(skb)->gso_segs;
5933 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5934
897ab156
AD		 5935 /* mss_l4len_id: use 1 as index for TSO */
5936 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5937 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5938 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5939
5940 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5941 vlan_macip_lens = skb_network_header_len(skb);
5942 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5943 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5944
5945 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5946 mss_l4len_idx);
897ab156
AD		 5947
5948 return 1;
5949}
5950
244e27ad
AD		 5951static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5952 struct ixgbe_tx_buffer *first)
7ca647bd 5953{
fd0db0ed 5954 struct sk_buff *skb = first->skb;
897ab156
AD		 5955 u32 vlan_macip_lens = 0;
5956 u32 mss_l4len_idx = 0;
5957 u32 type_tucmd = 0;
7ca647bd 5958
897ab156 5959 if (skb->ip_summed != CHECKSUM_PARTIAL) {
62748b7b
AD		 5960 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) {
5961 if (unlikely(skb->no_fcs))
5962 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS;
5963 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5964 return;
5965 }
897ab156
AD		 5966 } else {
5967 u8 l4_hdr = 0;
244e27ad 5968 switch (first->protocol) {
897ab156
AD		 5969 case __constant_htons(ETH_P_IP):
5970 vlan_macip_lens |= skb_network_header_len(skb);
5971 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5972 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5973 break;
897ab156
AD		 5974 case __constant_htons(ETH_P_IPV6):
5975 vlan_macip_lens |= skb_network_header_len(skb);
5976 l4_hdr = ipv6_hdr(skb)->nexthdr;
5977 break;
5978 default:
5979 if (unlikely(net_ratelimit())) {
5980 dev_warn(tx_ring->dev,
5981 "partial checksum but proto=%x!\n",
244e27ad 5982 first->protocol);
897ab156 5983 }
7ca647bd
JP		 5984 break;
5985 }
897ab156
AD		 5986
5987 switch (l4_hdr) {
7ca647bd 5988 case IPPROTO_TCP:
897ab156
AD		 5989 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5990 mss_l4len_idx = tcp_hdrlen(skb) <<
5991 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 5992 break;
5993 case IPPROTO_SCTP:
897ab156
AD		 5994 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5995 mss_l4len_idx = sizeof(struct sctphdr) <<
5996 IXGBE_ADVTXD_L4LEN_SHIFT;
5997 break;
5998 case IPPROTO_UDP:
5999 mss_l4len_idx = sizeof(struct udphdr) <<
6000 IXGBE_ADVTXD_L4LEN_SHIFT;
6001 break;
6002 default:
6003 if (unlikely(net_ratelimit())) {
6004 dev_warn(tx_ring->dev,
6005 "partial checksum but l4 proto=%x!\n",
244e27ad 6006 l4_hdr);
897ab156 6007 }
7ca647bd
JP		 6008 break;
6009 }
244e27ad
AD		 6010
6011 /* update TX checksum flag */
6012 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6013 }
6014
244e27ad 6015 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6016 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6017 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6018
897ab156
AD		 6019 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6020 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6021}
6022
d3d00239 6023static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6024{
d3d00239
AD		 6025 /* set type for advanced descriptor with frame checksum insertion */
6026 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
d3d00239 6027 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6028
d3d00239 6029 /* set HW vlan bit if vlan is present */
66f32a8b 6030 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6031 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6032
3a6a4eda
JK		 6033 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
6034 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
3a6a4eda 6035
d3d00239
AD		 6036 /* set segmentation enable bits for TSO/FSO */
6037#ifdef IXGBE_FCOE
93f5b3c1 6038 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 6039#else
6040 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6041#endif
6042 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6043
62748b7b
AD		 6044 /* insert frame checksum */
6045 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS))
6046 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS);
6047
d3d00239
AD		 6048 return cmd_type;
6049}
9a799d71 6050
729739b7
AD		 6051static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6052 u32 tx_flags, unsigned int paylen)
d3d00239 6053{
93f5b3c1 6054 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 6055
d3d00239
AD		 6056 /* enable L4 checksum for TSO and TX checksum offload */
6057 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6058 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6059
93f5b3c1
AD		 6060 /* enble IPv4 checksum for TSO */
6061 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6062 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6063
93f5b3c1
AD		 6064 /* use index 1 context for TSO/FSO/FCOE */
6065#ifdef IXGBE_FCOE
6066 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6067#else
6068 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 6069#endif
93f5b3c1
AD		 6070 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6071
7f9643fd
AD		 6072 /*
6073 * Check Context must be set if Tx switch is enabled, which it
6074 * always is for case where virtual functions are running
6075 */
93f5b3c1
AD		 6076#ifdef IXGBE_FCOE
6077 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6078#else
7f9643fd 6079 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 6080#endif
7f9643fd
AD		 6081 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6082
729739b7 6083 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 6084}
44df32c5 6085
d3d00239
AD		 6086#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6087 IXGBE_TXD_CMD_RS)
6088
6089static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6090 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6091 const u8 hdr_len)
6092{
729739b7 6093 dma_addr_t dma;
fd0db0ed 6094 struct sk_buff *skb = first->skb;
729739b7 6095 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6096 union ixgbe_adv_tx_desc *tx_desc;
729739b7 6097 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 6098 unsigned int data_len = skb->data_len;
6099 unsigned int size = skb_headlen(skb);
729739b7 6100 unsigned int paylen = skb->len - hdr_len;
244e27ad 6101 u32 tx_flags = first->tx_flags;
729739b7 6102 __le32 cmd_type;
d3d00239 6103 u16 i = tx_ring->next_to_use;
d3d00239 6104
729739b7
AD		 6105 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6106
6107 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6108 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6109
d3d00239
AD		 6110#ifdef IXGBE_FCOE
6111 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6112 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6113 size -= sizeof(struct fcoe_crc_eof) - data_len;
6114 data_len = 0;
729739b7
AD		 6115 } else {
6116 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6117 }
6118 }
44df32c5 6119
d3d00239 6120#endif
729739b7
AD		 6121 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6122 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6123 goto dma_error;
8ad494b0 6124
729739b7
AD		 6125 /* record length, and DMA address */
6126 dma_unmap_len_set(first, len, size);
6127 dma_unmap_addr_set(first, dma, dma);
9a799d71 6128
729739b7 6129 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6130
d3d00239 6131 for (;;) {
729739b7 6132 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6133 tx_desc->read.cmd_type_len =
6134 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6135
d3d00239 6136 i++;
729739b7 6137 tx_desc++;
d3d00239 6138 if (i == tx_ring->count) {
e4f74028 6139 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6140 i = 0;
6141 }
729739b7
AD		 6142
6143 dma += IXGBE_MAX_DATA_PER_TXD;
6144 size -= IXGBE_MAX_DATA_PER_TXD;
6145
6146 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6147 tx_desc->read.olinfo_status = 0;
d3d00239 6148 }
e5a43549 6149
729739b7
AD		 6150 if (likely(!data_len))
6151 break;
9a799d71 6152
d3d00239 6153 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6154
729739b7
AD		 6155 i++;
6156 tx_desc++;
6157 if (i == tx_ring->count) {
6158 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6159 i = 0;
6160 }
9a799d71 6161
d3d00239 6162#ifdef IXGBE_FCOE
9e903e08 6163 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6164#else
9e903e08 6165 size = skb_frag_size(frag);
d3d00239
AD		 6166#endif
6167 data_len -= size;
9a799d71 6168
729739b7
AD		 6169 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6170 DMA_TO_DEVICE);
6171 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6172 goto dma_error;
9a799d71 6173
729739b7
AD		 6174 tx_buffer = &tx_ring->tx_buffer_info[i];
6175 dma_unmap_len_set(tx_buffer, len, size);
6176 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6177
729739b7
AD		 6178 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6179 tx_desc->read.olinfo_status = 0;
9a799d71 6180
729739b7
AD		 6181 frag++;
6182 }
9a799d71 6183
729739b7
AD		 6184 /* write last descriptor with RS and EOP bits */
6185 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6186 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6187
091a6246 6188 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6189
d3d00239
AD		 6190 /* set the timestamp */
6191 first->time_stamp = jiffies;
9a799d71
AK		 6192
6193 /*
729739b7
AD		 6194 * Force memory writes to complete before letting h/w know there
6195 * are new descriptors to fetch. (Only applicable for weak-ordered
6196 * memory model archs, such as IA-64).
6197 *
6198 * We also need this memory barrier to make certain all of the
6199 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6200 */
6201 wmb();
6202
d3d00239
AD		 6203 /* set next_to_watch value indicating a packet is present */
6204 first->next_to_watch = tx_desc;
6205
729739b7
AD		 6206 i++;
6207 if (i == tx_ring->count)
6208 i = 0;
6209
6210 tx_ring->next_to_use = i;
6211
d3d00239 6212 /* notify HW of packet */
84ea2591 6213 writel(i, tx_ring->tail);
d3d00239
AD		 6214
6215 return;
6216dma_error:
729739b7 6217 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6218
6219 /* clear dma mappings for failed tx_buffer_info map */
6220 for (;;) {
729739b7
AD		 6221 tx_buffer = &tx_ring->tx_buffer_info[i];
6222 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6223 if (tx_buffer == first)
d3d00239
AD		 6224 break;
6225 if (i == 0)
6226 i = tx_ring->count;
6227 i--;
6228 }
6229
d3d00239 6230 tx_ring->next_to_use = i;
9a799d71
AK		 6231}
6232
fd0db0ed 6233static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6234 struct ixgbe_tx_buffer *first)
69830529
AD		 6235{
6236 struct ixgbe_q_vector *q_vector = ring->q_vector;
6237 union ixgbe_atr_hash_dword input = { .dword = 0 };
6238 union ixgbe_atr_hash_dword common = { .dword = 0 };
6239 union {
6240 unsigned char *network;
6241 struct iphdr *ipv4;
6242 struct ipv6hdr *ipv6;
6243 } hdr;
ee9e0f0b 6244 struct tcphdr *th;
905e4a41 6245 __be16 vlan_id;
c4cf55e5 6246
69830529
AD		 6247 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6248 if (!q_vector)
6249 return;
6250
6251 /* do nothing if sampling is disabled */
6252 if (!ring->atr_sample_rate)
d3ead241 6253 return;
c4cf55e5 6254
69830529 6255 ring->atr_count++;
c4cf55e5 6256
69830529 6257 /* snag network header to get L4 type and address */
fd0db0ed 6258 hdr.network = skb_network_header(first->skb);
69830529
AD		 6259
6260 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6261 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6262 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6263 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6264 hdr.ipv4->protocol != IPPROTO_TCP))
6265 return;
ee9e0f0b 6266
fd0db0ed 6267 th = tcp_hdr(first->skb);
c4cf55e5 6268
66f32a8b
AD		 6269 /* skip this packet since it is invalid or the socket is closing */
6270 if (!th || th->fin)
69830529
AD		 6271 return;
6272
6273 /* sample on all syn packets or once every atr sample count */
6274 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6275 return;
6276
6277 /* reset sample count */
6278 ring->atr_count = 0;
6279
244e27ad 6280 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6281
6282 /*
6283 * src and dst are inverted, think how the receiver sees them
6284 *
6285 * The input is broken into two sections, a non-compressed section
6286 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6287 * is XORed together and stored in the compressed dword.
6288 */
6289 input.formatted.vlan_id = vlan_id;
6290
6291 /*
6292 * since src port and flex bytes occupy the same word XOR them together
6293 * and write the value to source port portion of compressed dword
6294 */
244e27ad 6295 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6296 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6297 else
244e27ad 6298 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6299 common.port.dst ^= th->source;
6300
244e27ad 6301 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6302 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6303 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6304 } else {
6305 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6306 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6307 hdr.ipv6->saddr.s6_addr32[1] ^
6308 hdr.ipv6->saddr.s6_addr32[2] ^
6309 hdr.ipv6->saddr.s6_addr32[3] ^
6310 hdr.ipv6->daddr.s6_addr32[0] ^
6311 hdr.ipv6->daddr.s6_addr32[1] ^
6312 hdr.ipv6->daddr.s6_addr32[2] ^
6313 hdr.ipv6->daddr.s6_addr32[3];
6314 }
c4cf55e5
PWJ		 6315
6316 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6317 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6318 input, common, ring->queue_index);
c4cf55e5
PWJ		 6319}
6320
63544e9c 6321static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6322{
fc77dc3c 6323 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6324 /* Herbert's original patch had:
6325 * smp_mb__after_netif_stop_queue();
6326 * but since that doesn't exist yet, just open code it. */
6327 smp_mb();
6328
6329 /* We need to check again in a case another CPU has just
6330 * made room available. */
7d4987de 6331 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6332 return -EBUSY;
6333
6334 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6335 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6336 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6337 return 0;
6338}
6339
82d4e46e 6340static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6341{
7d4987de 6342 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6343 return 0;
fc77dc3c 6344 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6345}
6346
09a3b1f8
SH		 6347static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6348{
6349 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6350 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6351 smp_processor_id();
56075a98 6352#ifdef IXGBE_FCOE
6440752c 6353 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6354
e5b64635
JF		 6355 if (((protocol == htons(ETH_P_FCOE)) ||
6356 (protocol == htons(ETH_P_FIP))) &&
6357 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6358 struct ixgbe_ring_feature *f;
6359
6360 f = &adapter->ring_feature[RING_F_FCOE];
6361
6362 while (txq >= f->indices)
6363 txq -= f->indices;
e4b317e9 6364 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6365
e5b64635 6366 return txq;
56075a98
JF		 6367 }
6368#endif
6369
fdd3d631
KK		 6370 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6371 while (unlikely(txq >= dev->real_num_tx_queues))
6372 txq -= dev->real_num_tx_queues;
5f715823 6373 return txq;
fdd3d631 6374 }
c4cf55e5 6375
09a3b1f8
SH		 6376 return skb_tx_hash(dev, skb);
6377}
6378
fc77dc3c 6379netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6380 struct ixgbe_adapter *adapter,
6381 struct ixgbe_ring *tx_ring)
9a799d71 6382{
d3d00239 6383 struct ixgbe_tx_buffer *first;
5f715823 6384 int tso;
d3d00239 6385 u32 tx_flags = 0;
a535c30e
AD		 6386#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6387 unsigned short f;
6388#endif
a535c30e 6389 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6390 __be16 protocol = skb->protocol;
63544e9c 6391 u8 hdr_len = 0;
5e09a105 6392
a535c30e
AD		 6393 /*
6394 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6395 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6396 * + 2 desc gap to keep tail from touching head,
6397 * + 1 desc for context descriptor,
6398 * otherwise try next time
6399 */
6400#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6401 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6402 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6403#else
6404 count += skb_shinfo(skb)->nr_frags;
6405#endif
6406 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6407 tx_ring->tx_stats.tx_busy++;
6408 return NETDEV_TX_BUSY;
6409 }
6410
fd0db0ed
AD		 6411 /* record the location of the first descriptor for this packet */
6412 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6413 first->skb = skb;
091a6246
AD		 6414 first->bytecount = skb->len;
6415 first->gso_segs = 1;
fd0db0ed 6416
66f32a8b 6417 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6418 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6419 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6420 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6421 /* else if it is a SW VLAN check the next protocol and store the tag */
6422 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6423 struct vlan_hdr *vhdr, _vhdr;
6424 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6425 if (!vhdr)
6426 goto out_drop;
6427
6428 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6429 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6430 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6431 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6432 }
6433
aa7bd467
JK		 6434 skb_tx_timestamp(skb);
6435
3a6a4eda
JK		 6436 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6437 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6438 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6439 }
3a6a4eda 6440
9e0c5648
AD		 6441#ifdef CONFIG_PCI_IOV
6442 /*
6443 * Use the l2switch_enable flag - would be false if the DMA
6444 * Tx switch had been disabled.
6445 */
6446 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6447 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6448
6449#endif
32701dc2 6450 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6451 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6452 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6453 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6454 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6455 tx_flags |= (skb->priority & 0x7) <<
6456 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6457 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6458 struct vlan_ethhdr *vhdr;
6459 if (skb_header_cloned(skb) &&
6460 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6461 goto out_drop;
6462 vhdr = (struct vlan_ethhdr *)skb->data;
6463 vhdr->h_vlan_TCI = htons(tx_flags >>
6464 IXGBE_TX_FLAGS_VLAN_SHIFT);
6465 } else {
6466 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6467 }
9a799d71 6468 }
eacd73f7 6469
244e27ad
AD		 6470 /* record initial flags and protocol */
6471 first->tx_flags = tx_flags;
6472 first->protocol = protocol;
6473
eacd73f7 6474#ifdef IXGBE_FCOE
66f32a8b
AD		 6475 /* setup tx offload for FCoE */
6476 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6477 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6478 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6479 if (tso < 0)
6480 goto out_drop;
9a799d71 6481
66f32a8b 6482 goto xmit_fcoe;
eacd73f7 6483 }
9a799d71 6484
66f32a8b 6485#endif /* IXGBE_FCOE */
244e27ad 6486 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6487 if (tso < 0)
897ab156 6488 goto out_drop;
244e27ad
AD		 6489 else if (!tso)
6490 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6491
6492 /* add the ATR filter if ATR is on */
6493 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6494 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6495
6496#ifdef IXGBE_FCOE
6497xmit_fcoe:
6498#endif /* IXGBE_FCOE */
244e27ad 6499 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6500
6501 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6502
6503 return NETDEV_TX_OK;
897ab156
AD		 6504
6505out_drop:
fd0db0ed
AD		 6506 dev_kfree_skb_any(first->skb);
6507 first->skb = NULL;
6508
897ab156 6509 return NETDEV_TX_OK;
9a799d71
AK		 6510}
6511
a50c29dd
AD		 6512static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6513 struct net_device *netdev)
84418e3b
AD		 6514{
6515 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6516 struct ixgbe_ring *tx_ring;
6517
a50c29dd
AD		 6518 /*
6519 * The minimum packet size for olinfo paylen is 17 so pad the skb
6520 * in order to meet this minimum size requirement.
6521 */
f73332fc
SH		 6522 if (unlikely(skb->len < 17)) {
6523 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6524 return NETDEV_TX_OK;
6525 skb->len = 17;
71a49f77 6526 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 6527 }
6528
84418e3b 6529 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6530 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6531}
6532
9a799d71
AK		 6533/**
6534 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6535 * @netdev: network interface device structure
6536 * @p: pointer to an address structure
6537 *
6538 * Returns 0 on success, negative on failure
6539 **/
6540static int ixgbe_set_mac(struct net_device *netdev, void *p)
6541{
6542 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6543 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6544 struct sockaddr *addr = p;
6545
6546 if (!is_valid_ether_addr(addr->sa_data))
6547 return -EADDRNOTAVAIL;
6548
6549 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6550 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6551
1d9c0bfd 6552 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6553
6554 return 0;
6555}
6556
6b73e10d
BH		 6557static int
6558ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6559{
6560 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6561 struct ixgbe_hw *hw = &adapter->hw;
6562 u16 value;
6563 int rc;
6564
6565 if (prtad != hw->phy.mdio.prtad)
6566 return -EINVAL;
6567 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6568 if (!rc)
6569 rc = value;
6570 return rc;
6571}
6572
6573static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6574 u16 addr, u16 value)
6575{
6576 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6577 struct ixgbe_hw *hw = &adapter->hw;
6578
6579 if (prtad != hw->phy.mdio.prtad)
6580 return -EINVAL;
6581 return hw->phy.ops.write_reg(hw, addr, devad, value);
6582}
6583
6584static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6585{
6586 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6587
3a6a4eda 6588 switch (cmd) {
3a6a4eda
JK		 6589 case SIOCSHWTSTAMP:
6590 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
3a6a4eda
JK		 6591 default:
6592 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6593 }
6b73e10d
BH		 6594}
6595
0365e6e4
PW		 6596/**
6597 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6598 * netdev->dev_addrs
0365e6e4
PW		 6599 * @netdev: network interface device structure
6600 *
6601 * Returns non-zero on failure
6602 **/
6603static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6604{
6605 int err = 0;
6606 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6607 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6608
7fa7c9dc 6609 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6610 rtnl_lock();
7fa7c9dc 6611 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6612 rtnl_unlock();
7fa7c9dc
AD		 6613
6614 /* update SAN MAC vmdq pool selection */
6615 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6616 }
6617 return err;
6618}
6619
6620/**
6621 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6622 * netdev->dev_addrs
0365e6e4
PW		 6623 * @netdev: network interface device structure
6624 *
6625 * Returns non-zero on failure
6626 **/
6627static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6628{
6629 int err = 0;
6630 struct ixgbe_adapter *adapter = netdev_priv(dev);
6631 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6632
6633 if (is_valid_ether_addr(mac->san_addr)) {
6634 rtnl_lock();
6635 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6636 rtnl_unlock();
6637 }
6638 return err;
6639}
6640
9a799d71
AK		 6641#ifdef CONFIG_NET_POLL_CONTROLLER
6642/*
6643 * Polling 'interrupt' - used by things like netconsole to send skbs
6644 * without having to re-enable interrupts. It's not called while
6645 * the interrupt routine is executing.
6646 */
6647static void ixgbe_netpoll(struct net_device *netdev)
6648{
6649 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6650 int i;
9a799d71 6651
1a647bd2
AD		 6652 /* if interface is down do nothing */
6653 if (test_bit(__IXGBE_DOWN, &adapter->state))
6654 return;
6655
9a799d71 6656 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6657 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6658 for (i = 0; i < adapter->num_q_vectors; i++)
6659 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6660 } else {
6661 ixgbe_intr(adapter->pdev->irq, netdev);
6662 }
9a799d71 6663 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6664}
9a799d71 6665
581330ba 6666#endif
de1036b1
ED		 6667static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6668 struct rtnl_link_stats64 *stats)
6669{
6670 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6671 int i;
6672
1a51502b 6673 rcu_read_lock();
de1036b1 6674 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6675 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6676 u64 bytes, packets;
6677 unsigned int start;
6678
1a51502b
ED		 6679 if (ring) {
6680 do {
6681 start = u64_stats_fetch_begin_bh(&ring->syncp);
6682 packets = ring->stats.packets;
6683 bytes = ring->stats.bytes;
6684 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6685 stats->rx_packets += packets;
6686 stats->rx_bytes += bytes;
6687 }
de1036b1 6688 }
1ac9ad13
ED		 6689
6690 for (i = 0; i < adapter->num_tx_queues; i++) {
6691 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6692 u64 bytes, packets;
6693 unsigned int start;
6694
6695 if (ring) {
6696 do {
6697 start = u64_stats_fetch_begin_bh(&ring->syncp);
6698 packets = ring->stats.packets;
6699 bytes = ring->stats.bytes;
6700 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6701 stats->tx_packets += packets;
6702 stats->tx_bytes += bytes;
6703 }
6704 }
1a51502b 6705 rcu_read_unlock();
de1036b1
ED		 6706 /* following stats updated by ixgbe_watchdog_task() */
6707 stats->multicast = netdev->stats.multicast;
6708 stats->rx_errors = netdev->stats.rx_errors;
6709 stats->rx_length_errors = netdev->stats.rx_length_errors;
6710 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6711 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6712 return stats;
6713}
6714
8af3c33f 6715#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6716/**
6717 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6718 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6719 * @tc: number of traffic classes currently enabled
6720 *
6721 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6722 * 802.1Q priority maps to a packet buffer that exists.
6723 */
6724static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6725{
6726 struct ixgbe_hw *hw = &adapter->hw;
6727 u32 reg, rsave;
6728 int i;
6729
6730 /* 82598 have a static priority to TC mapping that can not
6731 * be changed so no validation is needed.
6732 */
6733 if (hw->mac.type == ixgbe_mac_82598EB)
6734 return;
6735
6736 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6737 rsave = reg;
6738
6739 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6740 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6741
6742 /* If up2tc is out of bounds default to zero */
6743 if (up2tc > tc)
6744 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6745 }
6746
6747 if (reg != rsave)
6748 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6749
6750 return;
6751}
6752
02debdc9
AD		 6753/**
6754 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6755 * @adapter: Pointer to adapter struct
6756 *
6757 * Populate the netdev user priority to tc map
6758 */
6759static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6760{
6761 struct net_device *dev = adapter->netdev;
6762 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6763 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6764 u8 prio;
6765
6766 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6767 u8 tc = 0;
6768
6769 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6770 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6771 else if (ets)
6772 tc = ets->prio_tc[prio];
6773
6774 netdev_set_prio_tc_map(dev, prio, tc);
6775 }
6776}
6777
49ce9c2c
BH		 6778/**
6779 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6780 *
6781 * @netdev: net device to configure
6782 * @tc: number of traffic classes to enable
6783 */
6784int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6785{
8b1c0b24
JF		 6786 struct ixgbe_adapter *adapter = netdev_priv(dev);
6787 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6788
8b1c0b24 6789 /* Hardware supports up to 8 traffic classes */
4de2a022 6790 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6791 (hw->mac.type == ixgbe_mac_82598EB &&
6792 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6793 return -EINVAL;
6794
6795 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6796 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6797 * hardware is not flexible enough to do this dynamically.
6798 */
6799 if (netif_running(dev))
6800 ixgbe_close(dev);
6801 ixgbe_clear_interrupt_scheme(adapter);
6802
e7589eab 6803 if (tc) {
8b1c0b24 6804 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6805 ixgbe_set_prio_tc_map(adapter);
6806
e7589eab 6807 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6808
943561d3
AD		 6809 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6810 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6811 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6812 }
e7589eab 6813 } else {
8b1c0b24 6814 netdev_reset_tc(dev);
02debdc9 6815
943561d3
AD		 6816 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6817 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6818
6819 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6820
6821 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6822 adapter->dcb_cfg.pfc_mode_enable = false;
6823 }
6824
8b1c0b24
JF		 6825 ixgbe_init_interrupt_scheme(adapter);
6826 ixgbe_validate_rtr(adapter, tc);
6827 if (netif_running(dev))
6828 ixgbe_open(dev);
6829
6830 return 0;
6831}
de1036b1 6832
8af3c33f 6833#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6834void ixgbe_do_reset(struct net_device *netdev)
6835{
6836 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6837
6838 if (netif_running(netdev))
6839 ixgbe_reinit_locked(adapter);
6840 else
6841 ixgbe_reset(adapter);
6842}
6843
c8f44aff 6844static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6845 netdev_features_t features)
082757af
DS		 6846{
6847 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6848
082757af 6849 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6850 if (!(features & NETIF_F_RXCSUM))
6851 features &= ~NETIF_F_LRO;
082757af 6852
567d2de2
AD		 6853 /* Turn off LRO if not RSC capable */
6854 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6855 features &= ~NETIF_F_LRO;
8e2813f5 6856
567d2de2 6857 return features;
082757af
DS		 6858}
6859
c8f44aff 6860static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6861 netdev_features_t features)
082757af
DS		 6862{
6863 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6864 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6865 bool need_reset = false;
6866
082757af 6867 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6868 if (!(features & NETIF_F_LRO)) {
6869 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6870 need_reset = true;
567d2de2
AD		 6871 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6872 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6873 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6874 if (adapter->rx_itr_setting == 1 ||
6875 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6876 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6877 need_reset = true;
6878 } else if ((changed ^ features) & NETIF_F_LRO) {
6879 e_info(probe, "rx-usecs set too low, "
6880 "disabling RSC\n");
082757af
DS		 6881 }
6882 }
6883
6884 /*
6885 * Check if Flow Director n-tuple support was enabled or disabled. If
6886 * the state changed, we need to reset.
6887 */
39cb681b
AD		 6888 switch (features & NETIF_F_NTUPLE) {
6889 case NETIF_F_NTUPLE:
567d2de2 6890 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 6891 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6892 need_reset = true;
6893
567d2de2
AD		 6894 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6895 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 6896 break;
6897 default:
6898 /* turn off perfect filters, enable ATR and reset */
6899 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6900 need_reset = true;
6901
6902 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6903
6904 /* We cannot enable ATR if SR-IOV is enabled */
6905 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6906 break;
6907
6908 /* We cannot enable ATR if we have 2 or more traffic classes */
6909 if (netdev_get_num_tc(netdev) > 1)
6910 break;
6911
6912 /* We cannot enable ATR if RSS is disabled */
6913 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6914 break;
6915
6916 /* A sample rate of 0 indicates ATR disabled */
6917 if (!adapter->atr_sample_rate)
6918 break;
6919
6920 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6921 break;
082757af
DS		 6922 }
6923
146d4cc9
JF		 6924 if (features & NETIF_F_HW_VLAN_RX)
6925 ixgbe_vlan_strip_enable(adapter);
6926 else
6927 ixgbe_vlan_strip_disable(adapter);
6928
3f2d1c0f
BG		 6929 if (changed & NETIF_F_RXALL)
6930 need_reset = true;
6931
567d2de2 6932 netdev->features = features;
082757af
DS		 6933 if (need_reset)
6934 ixgbe_do_reset(netdev);
6935
6936 return 0;
082757af
DS		 6937}
6938
edc7d573 6939static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 6940 struct net_device *dev,
6b6e2725 6941 const unsigned char *addr,
0f4b0add
JF		 6942 u16 flags)
6943{
6944 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 6945 int err;
6946
6947 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6948 return -EOPNOTSUPP;
0f4b0add
JF		 6949
6950 if (ndm->ndm_state & NUD_PERMANENT) {
6951 pr_info("%s: FDB only supports static addresses\n",
6952 ixgbe_driver_name);
6953 return -EINVAL;
6954 }
6955
b3343a2a 6956 if (is_unicast_ether_addr(addr) || is_link_local(addr)) {
95447461
JF		 6957 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6958
6959 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 6960 err = dev_uc_add_excl(dev, addr);
0f4b0add 6961 else
95447461
JF		 6962 err = -ENOMEM;
6963 } else if (is_multicast_ether_addr(addr)) {
6964 err = dev_mc_add_excl(dev, addr);
6965 } else {
6966 err = -EINVAL;
0f4b0add
JF		 6967 }
6968
6969 /* Only return duplicate errors if NLM_F_EXCL is set */
6970 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6971 err = 0;
6972
6973 return err;
6974}
6975
6976static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6977 struct net_device *dev,
6b6e2725 6978 const unsigned char *addr)
0f4b0add
JF		 6979{
6980 struct ixgbe_adapter *adapter = netdev_priv(dev);
6981 int err = -EOPNOTSUPP;
6982
6983 if (ndm->ndm_state & NUD_PERMANENT) {
6984 pr_info("%s: FDB only supports static addresses\n",
6985 ixgbe_driver_name);
6986 return -EINVAL;
6987 }
6988
6989 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6990 if (is_unicast_ether_addr(addr))
6991 err = dev_uc_del(dev, addr);
6992 else if (is_multicast_ether_addr(addr))
6993 err = dev_mc_del(dev, addr);
6994 else
6995 err = -EINVAL;
6996 }
6997
6998 return err;
6999}
7000
7001static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7002 struct netlink_callback *cb,
7003 struct net_device *dev,
7004 int idx)
7005{
7006 struct ixgbe_adapter *adapter = netdev_priv(dev);
7007
7008 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7009 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7010
7011 return idx;
7012}
7013
815cccbf
JF		 7014static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7015 struct nlmsghdr *nlh)
7016{
7017 struct ixgbe_adapter *adapter = netdev_priv(dev);
7018 struct nlattr *attr, *br_spec;
7019 int rem;
7020
7021 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7022 return -EOPNOTSUPP;
7023
7024 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7025
7026 nla_for_each_nested(attr, br_spec, rem) {
7027 __u16 mode;
7028 u32 reg = 0;
7029
7030 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7031 continue;
7032
7033 mode = nla_get_u16(attr);
7034 if (mode == BRIDGE_MODE_VEPA)
7035 reg = 0;
7036 else if (mode == BRIDGE_MODE_VEB)
7037 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7038 else
7039 return -EINVAL;
7040
7041 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7042
7043 e_info(drv, "enabling bridge mode: %s\n",
7044 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7045 }
7046
7047 return 0;
7048}
7049
7050static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7051 struct net_device *dev)
7052{
7053 struct ixgbe_adapter *adapter = netdev_priv(dev);
7054 u16 mode;
7055
7056 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7057 return 0;
7058
7059 if (IXGBE_READ_REG(&adapter->hw, IXGBE_PFDTXGSWC) & 1)
7060 mode = BRIDGE_MODE_VEB;
7061 else
7062 mode = BRIDGE_MODE_VEPA;
7063
7064 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7065}
7066
0edc3527 7067static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7068 .ndo_open = ixgbe_open,
0edc3527 7069 .ndo_stop = ixgbe_close,
00829823 7070 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7071 .ndo_select_queue = ixgbe_select_queue,
581330ba 7072 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7073 .ndo_validate_addr = eth_validate_addr,
7074 .ndo_set_mac_address = ixgbe_set_mac,
7075 .ndo_change_mtu = ixgbe_change_mtu,
7076 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7077 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7078 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7079 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7080 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7081 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7082 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7083 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7084 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7085 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7086#ifdef CONFIG_IXGBE_DCB
24095aa3 7087 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7088#endif
0edc3527
SH		 7089#ifdef CONFIG_NET_POLL_CONTROLLER
7090 .ndo_poll_controller = ixgbe_netpoll,
7091#endif
332d4a7d
YZ		 7092#ifdef IXGBE_FCOE
7093 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7094 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7095 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7096 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7097 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7098 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7099 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7100#endif /* IXGBE_FCOE */
082757af
DS		 7101 .ndo_set_features = ixgbe_set_features,
7102 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 7103 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7104 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7105 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
815cccbf
JF		 7106 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7107 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
0edc3527
SH		 7108};
7109
8e2813f5
JK		 7110/**
7111 * ixgbe_wol_supported - Check whether device supports WoL
7112 * @hw: hw specific details
7113 * @device_id: the device ID
7114 * @subdev_id: the subsystem device ID
7115 *
7116 * This function is used by probe and ethtool to determine
7117 * which devices have WoL support
7118 *
7119 **/
7120int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7121 u16 subdevice_id)
7122{
7123 struct ixgbe_hw *hw = &adapter->hw;
7124 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7125 int is_wol_supported = 0;
7126
7127 switch (device_id) {
7128 case IXGBE_DEV_ID_82599_SFP:
7129 /* Only these subdevices could supports WOL */
7130 switch (subdevice_id) {
7131 case IXGBE_SUBDEV_ID_82599_560FLR:
7132 /* only support first port */
7133 if (hw->bus.func != 0)
7134 break;
7135 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7136 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7137 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8e2813f5
JK		 7138 is_wol_supported = 1;
7139 break;
7140 }
7141 break;
7142 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7143 /* All except this subdevice support WOL */
7144 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7145 is_wol_supported = 1;
7146 break;
7147 case IXGBE_DEV_ID_82599_KX4:
7148 is_wol_supported = 1;
7149 break;
7150 case IXGBE_DEV_ID_X540T:
df376f0d 7151 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7152 /* check eeprom to see if enabled wol */
7153 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7154 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7155 (hw->bus.func == 0))) {
7156 is_wol_supported = 1;
7157 }
7158 break;
7159 }
7160
7161 return is_wol_supported;
7162}
7163
9a799d71
AK		 7164/**
7165 * ixgbe_probe - Device Initialization Routine
7166 * @pdev: PCI device information struct
7167 * @ent: entry in ixgbe_pci_tbl
7168 *
7169 * Returns 0 on success, negative on failure
7170 *
7171 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7172 * The OS initialization, configuring of the adapter private structure,
7173 * and a hardware reset occur.
7174 **/
7175static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7176 const struct pci_device_id *ent)
9a799d71
AK		 7177{
7178 struct net_device *netdev;
7179 struct ixgbe_adapter *adapter = NULL;
7180 struct ixgbe_hw *hw;
7181 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7182 static int cards_found;
7183 int i, err, pci_using_dac;
289700db 7184 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7185 unsigned int indices = num_possible_cpus();
3f4a6f00 7186 unsigned int dcb_max = 0;
eacd73f7
YZ		 7187#ifdef IXGBE_FCOE
7188 u16 device_caps;
7189#endif
289700db 7190 u32 eec;
9a799d71 7191
bded64a7
AG		 7192 /* Catch broken hardware that put the wrong VF device ID in
7193 * the PCIe SR-IOV capability.
7194 */
7195 if (pdev->is_virtfn) {
7196 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7197 pci_name(pdev), pdev->vendor, pdev->device);
7198 return -EINVAL;
7199 }
7200
9ce77666 7201 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7202 if (err)
7203 return err;
7204
1b507730
NN		 7205 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7206 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7207 pci_using_dac = 1;
7208 } else {
1b507730 7209 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7210 if (err) {
1b507730
NN		 7211 err = dma_set_coherent_mask(&pdev->dev,
7212 DMA_BIT_MASK(32));
9a799d71 7213 if (err) {
b8bc0421
DC		 7214 dev_err(&pdev->dev,
7215 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7216 goto err_dma;
7217 }
7218 }
7219 pci_using_dac = 0;
7220 }
7221
9ce77666 7222 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7223 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7224 if (err) {
b8bc0421
DC		 7225 dev_err(&pdev->dev,
7226 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7227 goto err_pci_reg;
7228 }
7229
19d5afd4 7230 pci_enable_pcie_error_reporting(pdev);
6fabd715 7231
9a799d71 7232 pci_set_master(pdev);
fb3b27bc 7233 pci_save_state(pdev);
9a799d71 7234
e901acd6 7235#ifdef CONFIG_IXGBE_DCB
3f4a6f00
JF		 7236 if (ii->mac == ixgbe_mac_82598EB)
7237 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7238 IXGBE_MAX_RSS_INDICES);
7239 else
7240 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7241 IXGBE_MAX_FDIR_INDICES);
e901acd6
JF		 7242#endif
7243
c85a2618
JF		 7244 if (ii->mac == ixgbe_mac_82598EB)
7245 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7246 else
7247 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7248
e901acd6 7249#ifdef IXGBE_FCOE
c85a2618
JF		 7250 indices += min_t(unsigned int, num_possible_cpus(),
7251 IXGBE_MAX_FCOE_INDICES);
7252#endif
3f4a6f00 7253 indices = max_t(unsigned int, dcb_max, indices);
c85a2618 7254 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7255 if (!netdev) {
7256 err = -ENOMEM;
7257 goto err_alloc_etherdev;
7258 }
7259
9a799d71
AK		 7260 SET_NETDEV_DEV(netdev, &pdev->dev);
7261
9a799d71 7262 adapter = netdev_priv(netdev);
c60fbb00 7263 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7264
7265 adapter->netdev = netdev;
7266 adapter->pdev = pdev;
7267 hw = &adapter->hw;
7268 hw->back = adapter;
b3f4d599 7269 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7270
05857980 7271 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7272 pci_resource_len(pdev, 0));
9a799d71
AK		 7273 if (!hw->hw_addr) {
7274 err = -EIO;
7275 goto err_ioremap;
7276 }
7277
0edc3527 7278 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7279 ixgbe_set_ethtool_ops(netdev);
9a799d71 7280 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7281 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7282
9a799d71
AK		 7283 adapter->bd_number = cards_found;
7284
9a799d71
AK		 7285 /* Setup hw api */
7286 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7287 hw->mac.type = ii->mac;
9a799d71 7288
c44ade9e
JB		 7289 /* EEPROM */
7290 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7291 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7292 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7293 if (!(eec & (1 << 8)))
7294 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7295
7296 /* PHY */
7297 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7298 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7299 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7300 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7301 hw->phy.mdio.mmds = 0;
7302 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7303 hw->phy.mdio.dev = netdev;
7304 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7305 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7306
8ca783ab 7307 ii->get_invariants(hw);
9a799d71
AK		 7308
7309 /* setup the private structure */
7310 err = ixgbe_sw_init(adapter);
7311 if (err)
7312 goto err_sw_init;
7313
e86bff0e 7314 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7315 switch (adapter->hw.mac.type) {
7316 case ixgbe_mac_82599EB:
7317 case ixgbe_mac_X540:
e86bff0e 7318 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7319 break;
7320 default:
7321 break;
7322 }
e86bff0e 7323
bf069c97
DS		 7324 /*
7325 * If there is a fan on this device and it has failed log the
7326 * failure.
7327 */
7328 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7329 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7330 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7331 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7332 }
7333
8ef78adc
PWJ		 7334 if (allow_unsupported_sfp)
7335 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7336
c44ade9e 7337 /* reset_hw fills in the perm_addr as well */
119fc60a 7338 hw->phy.reset_if_overtemp = true;
c44ade9e 7339 err = hw->mac.ops.reset_hw(hw);
119fc60a 7340 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7341 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7342 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7343 err = 0;
7344 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7345 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7346 "module type was detected.\n");
7347 e_dev_err("Reload the driver after installing a supported "
7348 "module.\n");
04f165ef
PW		 7349 goto err_sw_init;
7350 } else if (err) {
849c4542 7351 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7352 goto err_sw_init;
7353 }
7354
99d74487
AD		 7355#ifdef CONFIG_PCI_IOV
7356 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8 7357
99d74487 7358#endif
396e799c 7359 netdev->features = NETIF_F_SG |
e8e9f696 7360 NETIF_F_IP_CSUM |
082757af 7361 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7362 NETIF_F_HW_VLAN_TX |
7363 NETIF_F_HW_VLAN_RX |
082757af
DS		 7364 NETIF_F_HW_VLAN_FILTER |
7365 NETIF_F_TSO |
7366 NETIF_F_TSO6 |
082757af
DS		 7367 NETIF_F_RXHASH |
7368 NETIF_F_RXCSUM;
9a799d71 7369
082757af 7370 netdev->hw_features = netdev->features;
ad31c402 7371
58be7666
DS		 7372 switch (adapter->hw.mac.type) {
7373 case ixgbe_mac_82599EB:
7374 case ixgbe_mac_X540:
45a5ead0 7375 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7376 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7377 NETIF_F_NTUPLE;
58be7666
DS		 7378 break;
7379 default:
7380 break;
7381 }
45a5ead0 7382
3f2d1c0f
BG		 7383 netdev->hw_features |= NETIF_F_RXALL;
7384
ad31c402
JK		 7385 netdev->vlan_features |= NETIF_F_TSO;
7386 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7387 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7388 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7389 netdev->vlan_features |= NETIF_F_SG;
7390
01789349 7391 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7392 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7393
7a6b6f51 7394#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7395 netdev->dcbnl_ops = &dcbnl_ops;
7396#endif
7397
eacd73f7 7398#ifdef IXGBE_FCOE
0d551589 7399 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7400 if (hw->mac.ops.get_device_caps) {
7401 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7402 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7403 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7404 }
7c8ae65a
AD		 7405
7406 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7407
a58915c7
AD		 7408 netdev->features |= NETIF_F_FSO |
7409 NETIF_F_FCOE_CRC;
7410
7c8ae65a
AD		 7411 netdev->vlan_features |= NETIF_F_FSO |
7412 NETIF_F_FCOE_CRC |
7413 NETIF_F_FCOE_MTU;
5e09d7f6 7414 }
eacd73f7 7415#endif /* IXGBE_FCOE */
7b872a55 7416 if (pci_using_dac) {
9a799d71 7417 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7418 netdev->vlan_features |= NETIF_F_HIGHDMA;
7419 }
9a799d71 7420
082757af
DS		 7421 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7422 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7423 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7424 netdev->features |= NETIF_F_LRO;
7425
9a799d71 7426 /* make sure the EEPROM is good */
c44ade9e 7427 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7428 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7429 err = -EIO;
35937c05 7430 goto err_sw_init;
9a799d71
AK		 7431 }
7432
7433 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7434 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7435
c44ade9e 7436 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7437 e_dev_err("invalid MAC address\n");
9a799d71 7438 err = -EIO;
35937c05 7439 goto err_sw_init;
9a799d71
AK		 7440 }
7441
7086400d 7442 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7443 (unsigned long) adapter);
9a799d71 7444
7086400d
AD		 7445 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7446 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7447
021230d4
AV		 7448 err = ixgbe_init_interrupt_scheme(adapter);
7449 if (err)
7450 goto err_sw_init;
9a799d71 7451
8e2813f5 7452 /* WOL not supported for all devices */
c23f5b6b 7453 adapter->wol = 0;
8e2813f5
JK		 7454 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7455 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7456 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7457
e8e26350
PW		 7458 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7459
15e5209f
ET		 7460 /* save off EEPROM version number */
7461 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7462 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7463
04f165ef
PW		 7464 /* pick up the PCI bus settings for reporting later */
7465 hw->mac.ops.get_bus_info(hw);
7466
9a799d71 7467 /* print bus type/speed/width info */
849c4542 7468 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7469 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7470 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7471 "Unknown"),
7472 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7473 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7474 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7475 "Unknown"),
7476 netdev->dev_addr);
289700db
DS		 7477
7478 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7479 if (err)
9fe93afd 7480 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7481 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7482 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7483 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7484 part_str);
e8e26350 7485 else
289700db
DS		 7486 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7487 hw->mac.type, hw->phy.type, part_str);
9a799d71 7488
e8e26350 7489 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7490 e_dev_warn("PCI-Express bandwidth available for this card is "
7491 "not sufficient for optimal performance.\n");
7492 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7493 "is required.\n");
0c254d86
AK		 7494 }
7495
9a799d71 7496 /* reset the hardware with the new settings */
794caeb2 7497 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7498 if (err == IXGBE_ERR_EEPROM_VERSION) {
7499 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7500 e_dev_warn("This device is a pre-production adapter/LOM. "
7501 "Please be aware there may be issues associated "
7502 "with your hardware. If you are experiencing "
7503 "problems please contact your Intel or hardware "
7504 "representative who provided you with this "
7505 "hardware.\n");
794caeb2 7506 }
9a799d71
AK		 7507 strcpy(netdev->name, "eth%d");
7508 err = register_netdev(netdev);
7509 if (err)
7510 goto err_register;
7511
ec74a471
ET		 7512 /* power down the optics for 82599 SFP+ fiber */
7513 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 7514 hw->mac.ops.disable_tx_laser(hw);
7515
54386467
JB		 7516 /* carrier off reporting is important to ethtool even BEFORE open */
7517 netif_carrier_off(netdev);
7518
5dd2d332 7519#ifdef CONFIG_IXGBE_DCA
652f093f 7520 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7521 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7522 ixgbe_setup_dca(adapter);
7523 }
7524#endif
1cdd1ec8 7525 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7526 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7527 for (i = 0; i < adapter->num_vfs; i++)
7528 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7529 }
7530
2466dd9c
JK		 7531 /* firmware requires driver version to be 0xFFFFFFFF
7532 * since os does not support feature
7533 */
9612de92 7534 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7535 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7536 0xFF);
9612de92 7537
0365e6e4
PW		 7538 /* add san mac addr to netdev */
7539 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7540
ea81875a 7541 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7542 cards_found++;
3ca8bc6d 7543
1210982b 7544#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7545 if (ixgbe_sysfs_init(adapter))
7546 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7547#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7548
00949167
CS		 7549#ifdef CONFIG_DEBUG_FS
7550 ixgbe_dbg_adapter_init(adapter);
7551#endif /* CONFIG_DEBUG_FS */
7552
9a799d71
AK		 7553 return 0;
7554
7555err_register:
5eba3699 7556 ixgbe_release_hw_control(adapter);
7a921c93 7557 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7558err_sw_init:
99d74487 7559 ixgbe_disable_sriov(adapter);
7086400d 7560 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7561 iounmap(hw->hw_addr);
7562err_ioremap:
7563 free_netdev(netdev);
7564err_alloc_etherdev:
e8e9f696
JP		 7565 pci_release_selected_regions(pdev,
7566 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7567err_pci_reg:
7568err_dma:
7569 pci_disable_device(pdev);
7570 return err;
7571}
7572
7573/**
7574 * ixgbe_remove - Device Removal Routine
7575 * @pdev: PCI device information struct
7576 *
7577 * ixgbe_remove is called by the PCI subsystem to alert the driver
7578 * that it should release a PCI device. The could be caused by a
7579 * Hot-Plug event, or because the driver is going to be removed from
7580 * memory.
7581 **/
7582static void __devexit ixgbe_remove(struct pci_dev *pdev)
7583{
c60fbb00
AD		 7584 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7585 struct net_device *netdev = adapter->netdev;
9a799d71 7586
00949167
CS		 7587#ifdef CONFIG_DEBUG_FS
7588 ixgbe_dbg_adapter_exit(adapter);
7589#endif /*CONFIG_DEBUG_FS */
7590
9a799d71 7591 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7592 cancel_work_sync(&adapter->service_task);
9a799d71 7593
3a6a4eda 7594
5dd2d332 7595#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7596 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7597 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7598 dca_remove_requester(&pdev->dev);
7599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7600 }
7601
7602#endif
1210982b 7603#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7604 ixgbe_sysfs_exit(adapter);
1210982b 7605#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7606
0365e6e4
PW		 7607 /* remove the added san mac */
7608 ixgbe_del_sanmac_netdev(netdev);
7609
c4900be0
DS		 7610 if (netdev->reg_state == NETREG_REGISTERED)
7611 unregister_netdev(netdev);
9a799d71 7612
9297127b 7613 ixgbe_disable_sriov(adapter);
1cdd1ec8 7614
7a921c93 7615 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7616
021230d4 7617 ixgbe_release_hw_control(adapter);
9a799d71 7618
2b1588c3
AD		 7619#ifdef CONFIG_DCB
7620 kfree(adapter->ixgbe_ieee_pfc);
7621 kfree(adapter->ixgbe_ieee_ets);
7622
7623#endif
9a799d71 7624 iounmap(adapter->hw.hw_addr);
9ce77666 7625 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7626 IORESOURCE_MEM));
9a799d71 7627
849c4542 7628 e_dev_info("complete\n");
021230d4 7629
9a799d71
AK		 7630 free_netdev(netdev);
7631
19d5afd4 7632 pci_disable_pcie_error_reporting(pdev);
6fabd715 7633
9a799d71
AK		 7634 pci_disable_device(pdev);
7635}
7636
7637/**
7638 * ixgbe_io_error_detected - called when PCI error is detected
7639 * @pdev: Pointer to PCI device
7640 * @state: The current pci connection state
7641 *
7642 * This function is called after a PCI bus error affecting
7643 * this device has been detected.
7644 */
7645static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7646 pci_channel_state_t state)
9a799d71 7647{
c60fbb00
AD		 7648 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7649 struct net_device *netdev = adapter->netdev;
9a799d71 7650
83c61fa9
GR		 7651#ifdef CONFIG_PCI_IOV
7652 struct pci_dev *bdev, *vfdev;
7653 u32 dw0, dw1, dw2, dw3;
7654 int vf, pos;
7655 u16 req_id, pf_func;
7656
7657 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7658 adapter->num_vfs == 0)
7659 goto skip_bad_vf_detection;
7660
7661 bdev = pdev->bus->self;
62f87c0e 7662 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 7663 bdev = bdev->bus->self;
7664
7665 if (!bdev)
7666 goto skip_bad_vf_detection;
7667
7668 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7669 if (!pos)
7670 goto skip_bad_vf_detection;
7671
7672 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7673 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7674 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7675 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7676
7677 req_id = dw1 >> 16;
7678 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7679 if (!(req_id & 0x0080))
7680 goto skip_bad_vf_detection;
7681
7682 pf_func = req_id & 0x01;
7683 if ((pf_func & 1) == (pdev->devfn & 1)) {
7684 unsigned int device_id;
7685
7686 vf = (req_id & 0x7F) >> 1;
7687 e_dev_err("VF %d has caused a PCIe error\n", vf);
7688 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7689 "%8.8x\tdw3: %8.8x\n",
7690 dw0, dw1, dw2, dw3);
7691 switch (adapter->hw.mac.type) {
7692 case ixgbe_mac_82599EB:
7693 device_id = IXGBE_82599_VF_DEVICE_ID;
7694 break;
7695 case ixgbe_mac_X540:
7696 device_id = IXGBE_X540_VF_DEVICE_ID;
7697 break;
7698 default:
7699 device_id = 0;
7700 break;
7701 }
7702
7703 /* Find the pci device of the offending VF */
36e90319 7704 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7705 while (vfdev) {
7706 if (vfdev->devfn == (req_id & 0xFF))
7707 break;
36e90319 7708 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7709 device_id, vfdev);
7710 }
7711 /*
7712 * There's a slim chance the VF could have been hot plugged,
7713 * so if it is no longer present we don't need to issue the
7714 * VFLR. Just clean up the AER in that case.
7715 */
7716 if (vfdev) {
7717 e_dev_err("Issuing VFLR to VF %d\n", vf);
7718 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7719 }
7720
7721 pci_cleanup_aer_uncorrect_error_status(pdev);
7722 }
7723
7724 /*
7725 * Even though the error may have occurred on the other port
7726 * we still need to increment the vf error reference count for
7727 * both ports because the I/O resume function will be called
7728 * for both of them.
7729 */
7730 adapter->vferr_refcount++;
7731
7732 return PCI_ERS_RESULT_RECOVERED;
7733
7734skip_bad_vf_detection:
7735#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7736 netif_device_detach(netdev);
7737
3044b8d1
BL		 7738 if (state == pci_channel_io_perm_failure)
7739 return PCI_ERS_RESULT_DISCONNECT;
7740
9a799d71
AK		 7741 if (netif_running(netdev))
7742 ixgbe_down(adapter);
7743 pci_disable_device(pdev);
7744
b4617240 7745 /* Request a slot reset. */
9a799d71
AK		 7746 return PCI_ERS_RESULT_NEED_RESET;
7747}
7748
7749/**
7750 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7751 * @pdev: Pointer to PCI device
7752 *
7753 * Restart the card from scratch, as if from a cold-boot.
7754 */
7755static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7756{
c60fbb00 7757 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7758 pci_ers_result_t result;
7759 int err;
9a799d71 7760
9ce77666 7761 if (pci_enable_device_mem(pdev)) {
396e799c 7762 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7763 result = PCI_ERS_RESULT_DISCONNECT;
7764 } else {
7765 pci_set_master(pdev);
7766 pci_restore_state(pdev);
c0e1f68b 7767 pci_save_state(pdev);
9a799d71 7768
dd4d8ca6 7769 pci_wake_from_d3(pdev, false);
9a799d71 7770
6fabd715 7771 ixgbe_reset(adapter);
88512539 7772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7773 result = PCI_ERS_RESULT_RECOVERED;
7774 }
7775
7776 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7777 if (err) {
849c4542
ET		 7778 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7779 "failed 0x%0x\n", err);
6fabd715
PWJ		 7780 /* non-fatal, continue */
7781 }
9a799d71 7782
6fabd715 7783 return result;
9a799d71
AK		 7784}
7785
7786/**
7787 * ixgbe_io_resume - called when traffic can start flowing again.
7788 * @pdev: Pointer to PCI device
7789 *
7790 * This callback is called when the error recovery driver tells us that
7791 * its OK to resume normal operation.
7792 */
7793static void ixgbe_io_resume(struct pci_dev *pdev)
7794{
c60fbb00
AD		 7795 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7796 struct net_device *netdev = adapter->netdev;
9a799d71 7797
83c61fa9
GR		 7798#ifdef CONFIG_PCI_IOV
7799 if (adapter->vferr_refcount) {
7800 e_info(drv, "Resuming after VF err\n");
7801 adapter->vferr_refcount--;
7802 return;
7803 }
7804
7805#endif
c7ccde0f
AD		 7806 if (netif_running(netdev))
7807 ixgbe_up(adapter);
9a799d71
AK		 7808
7809 netif_device_attach(netdev);
9a799d71
AK		 7810}
7811
3646f0e5 7812static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 7813 .error_detected = ixgbe_io_error_detected,
7814 .slot_reset = ixgbe_io_slot_reset,
7815 .resume = ixgbe_io_resume,
7816};
7817
7818static struct pci_driver ixgbe_driver = {
7819 .name = ixgbe_driver_name,
7820 .id_table = ixgbe_pci_tbl,
7821 .probe = ixgbe_probe,
7822 .remove = __devexit_p(ixgbe_remove),
7823#ifdef CONFIG_PM
7824 .suspend = ixgbe_suspend,
7825 .resume = ixgbe_resume,
7826#endif
7827 .shutdown = ixgbe_shutdown,
7828 .err_handler = &ixgbe_err_handler
7829};
7830
7831/**
7832 * ixgbe_init_module - Driver Registration Routine
7833 *
7834 * ixgbe_init_module is the first routine called when the driver is
7835 * loaded. All it does is register with the PCI subsystem.
7836 **/
7837static int __init ixgbe_init_module(void)
7838{
7839 int ret;
c7689578 7840 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7841 pr_info("%s\n", ixgbe_copyright);
9a799d71 7842
00949167
CS		 7843#ifdef CONFIG_DEBUG_FS
7844 ixgbe_dbg_init();
7845#endif /* CONFIG_DEBUG_FS */
7846
5dd2d332 7847#ifdef CONFIG_IXGBE_DCA
bd0362dd 7848 dca_register_notify(&dca_notifier);
bd0362dd 7849#endif
5dd2d332 7850
9a799d71
AK		 7851 ret = pci_register_driver(&ixgbe_driver);
7852 return ret;
7853}
b4617240 7854
9a799d71
AK		 7855module_init(ixgbe_init_module);
7856
7857/**
7858 * ixgbe_exit_module - Driver Exit Cleanup Routine
7859 *
7860 * ixgbe_exit_module is called just before the driver is removed
7861 * from memory.
7862 **/
7863static void __exit ixgbe_exit_module(void)
7864{
5dd2d332 7865#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7866 dca_unregister_notify(&dca_notifier);
7867#endif
9a799d71 7868 pci_unregister_driver(&ixgbe_driver);
00949167
CS		 7869
7870#ifdef CONFIG_DEBUG_FS
7871 ixgbe_dbg_exit();
7872#endif /* CONFIG_DEBUG_FS */
7873
1a51502b 7874 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7875}
bd0362dd 7876
5dd2d332 7877#ifdef CONFIG_IXGBE_DCA
bd0362dd 7878static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7879 void *p)
bd0362dd
JC		 7880{
7881 int ret_val;
7882
7883 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7884 __ixgbe_notify_dca);
bd0362dd
JC		 7885
7886 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7887}
b453368d 7888
5dd2d332 7889#endif /* CONFIG_IXGBE_DCA */
849c4542 7890
9a799d71
AK		 7891module_exit(ixgbe_exit_module);
7892
7893/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)