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ixgbe: fixup hard dependencies on supporting 8 traffic classes
[linux-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 58#define MAJ 3
a38a104d 59#define MIN 4
c89c7112 60#define BUILD 8
75e3d3c6 61#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 62 __stringify(BUILD) "-k"
9c8eb720 63const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 64static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 66
67static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 68 [board_82598] = &ixgbe_82598_info,
e8e26350 69 [board_82599] = &ixgbe_82599_info,
fe15e8e1 70 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 71};
72
73/* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
a3aa1884 81static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9a799d71
AK		 109 /* required last entry */
110 {0, }
111};
112MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
113
5dd2d332 114#ifdef CONFIG_IXGBE_DCA
bd0362dd 115static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 116 void *p);
bd0362dd
JC		 117static struct notifier_block dca_notifier = {
118 .notifier_call = ixgbe_notify_dca,
119 .next = NULL,
120 .priority = 0
121};
122#endif
123
1cdd1ec8
GR		 124#ifdef CONFIG_PCI_IOV
125static unsigned int max_vfs;
126module_param(max_vfs, uint, 0);
e8e9f696
JP		 127MODULE_PARM_DESC(max_vfs,
128 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 129#endif /* CONFIG_PCI_IOV */
130
9a799d71
AK		 131MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
132MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
133MODULE_LICENSE("GPL");
134MODULE_VERSION(DRV_VERSION);
135
136#define DEFAULT_DEBUG_LEVEL_SHIFT 3
137
7086400d
AD		 138static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
139{
140 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
141 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
142 schedule_work(&adapter->service_task);
143}
144
145static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
146{
147 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
148
149 /* flush memory to make sure state is correct before next watchog */
150 smp_mb__before_clear_bit();
151 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
152}
153
dcd79aeb
TI		 154struct ixgbe_reg_info {
155 u32 ofs;
156 char *name;
157};
158
159static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
160
161 /* General Registers */
162 {IXGBE_CTRL, "CTRL"},
163 {IXGBE_STATUS, "STATUS"},
164 {IXGBE_CTRL_EXT, "CTRL_EXT"},
165
166 /* Interrupt Registers */
167 {IXGBE_EICR, "EICR"},
168
169 /* RX Registers */
170 {IXGBE_SRRCTL(0), "SRRCTL"},
171 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
172 {IXGBE_RDLEN(0), "RDLEN"},
173 {IXGBE_RDH(0), "RDH"},
174 {IXGBE_RDT(0), "RDT"},
175 {IXGBE_RXDCTL(0), "RXDCTL"},
176 {IXGBE_RDBAL(0), "RDBAL"},
177 {IXGBE_RDBAH(0), "RDBAH"},
178
179 /* TX Registers */
180 {IXGBE_TDBAL(0), "TDBAL"},
181 {IXGBE_TDBAH(0), "TDBAH"},
182 {IXGBE_TDLEN(0), "TDLEN"},
183 {IXGBE_TDH(0), "TDH"},
184 {IXGBE_TDT(0), "TDT"},
185 {IXGBE_TXDCTL(0), "TXDCTL"},
186
187 /* List Terminator */
188 {}
189};
190
191
192/*
193 * ixgbe_regdump - register printout routine
194 */
195static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
196{
197 int i = 0, j = 0;
198 char rname[16];
199 u32 regs[64];
200
201 switch (reginfo->ofs) {
202 case IXGBE_SRRCTL(0):
203 for (i = 0; i < 64; i++)
204 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
205 break;
206 case IXGBE_DCA_RXCTRL(0):
207 for (i = 0; i < 64; i++)
208 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
209 break;
210 case IXGBE_RDLEN(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
213 break;
214 case IXGBE_RDH(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
217 break;
218 case IXGBE_RDT(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
221 break;
222 case IXGBE_RXDCTL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
225 break;
226 case IXGBE_RDBAL(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
229 break;
230 case IXGBE_RDBAH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
233 break;
234 case IXGBE_TDBAL(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
237 break;
238 case IXGBE_TDBAH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
241 break;
242 case IXGBE_TDLEN(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
245 break;
246 case IXGBE_TDH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
249 break;
250 case IXGBE_TDT(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
253 break;
254 case IXGBE_TXDCTL(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
257 break;
258 default:
c7689578 259 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 260 IXGBE_READ_REG(hw, reginfo->ofs));
261 return;
262 }
263
264 for (i = 0; i < 8; i++) {
265 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 266 pr_err("%-15s", rname);
dcd79aeb 267 for (j = 0; j < 8; j++)
c7689578
JP		 268 pr_cont(" %08x", regs[i*8+j]);
269 pr_cont("\n");
dcd79aeb
TI		 270 }
271
272}
273
274/*
275 * ixgbe_dump - Print registers, tx-rings and rx-rings
276 */
277static void ixgbe_dump(struct ixgbe_adapter *adapter)
278{
279 struct net_device *netdev = adapter->netdev;
280 struct ixgbe_hw *hw = &adapter->hw;
281 struct ixgbe_reg_info *reginfo;
282 int n = 0;
283 struct ixgbe_ring *tx_ring;
284 struct ixgbe_tx_buffer *tx_buffer_info;
285 union ixgbe_adv_tx_desc *tx_desc;
286 struct my_u0 { u64 a; u64 b; } *u0;
287 struct ixgbe_ring *rx_ring;
288 union ixgbe_adv_rx_desc *rx_desc;
289 struct ixgbe_rx_buffer *rx_buffer_info;
290 u32 staterr;
291 int i = 0;
292
293 if (!netif_msg_hw(adapter))
294 return;
295
296 /* Print netdevice Info */
297 if (netdev) {
298 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 299 pr_info("Device Name state "
dcd79aeb 300 "trans_start last_rx\n");
c7689578
JP		 301 pr_info("%-15s %016lX %016lX %016lX\n",
302 netdev->name,
303 netdev->state,
304 netdev->trans_start,
305 netdev->last_rx);
dcd79aeb
TI		 306 }
307
308 /* Print Registers */
309 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 310 pr_info(" Register Name Value\n");
dcd79aeb
TI		 311 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
312 reginfo->name; reginfo++) {
313 ixgbe_regdump(hw, reginfo);
314 }
315
316 /* Print TX Ring Summary */
317 if (!netdev || !netif_running(netdev))
318 goto exit;
319
320 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 321 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 322 for (n = 0; n < adapter->num_tx_queues; n++) {
323 tx_ring = adapter->tx_ring[n];
324 tx_buffer_info =
325 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 326 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 327 n, tx_ring->next_to_use, tx_ring->next_to_clean,
328 (u64)tx_buffer_info->dma,
329 tx_buffer_info->length,
330 tx_buffer_info->next_to_watch,
331 (u64)tx_buffer_info->time_stamp);
332 }
333
334 /* Print TX Rings */
335 if (!netif_msg_tx_done(adapter))
336 goto rx_ring_summary;
337
338 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
339
340 /* Transmit Descriptor Formats
341 *
342 * Advanced Transmit Descriptor
343 * +--------------------------------------------------------------+
344 * 0 | Buffer Address [63:0] |
345 * +--------------------------------------------------------------+
346 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
347 * +--------------------------------------------------------------+
348 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
349 */
350
351 for (n = 0; n < adapter->num_tx_queues; n++) {
352 tx_ring = adapter->tx_ring[n];
c7689578
JP		 353 pr_info("------------------------------------\n");
354 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
355 pr_info("------------------------------------\n");
356 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 357 "[PlPOIdStDDt Ln] [bi->dma ] "
358 "leng ntw timestamp bi->skb\n");
359
360 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 361 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 362 tx_buffer_info = &tx_ring->tx_buffer_info[i];
363 u0 = (struct my_u0 *)tx_desc;
c7689578 364 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 365 " %04X %p %016llX %p", i,
dcd79aeb
TI		 366 le64_to_cpu(u0->a),
367 le64_to_cpu(u0->b),
368 (u64)tx_buffer_info->dma,
369 tx_buffer_info->length,
370 tx_buffer_info->next_to_watch,
371 (u64)tx_buffer_info->time_stamp,
372 tx_buffer_info->skb);
373 if (i == tx_ring->next_to_use &&
374 i == tx_ring->next_to_clean)
c7689578 375 pr_cont(" NTC/U\n");
dcd79aeb 376 else if (i == tx_ring->next_to_use)
c7689578 377 pr_cont(" NTU\n");
dcd79aeb 378 else if (i == tx_ring->next_to_clean)
c7689578 379 pr_cont(" NTC\n");
dcd79aeb 380 else
c7689578 381 pr_cont("\n");
dcd79aeb
TI		 382
383 if (netif_msg_pktdata(adapter) &&
384 tx_buffer_info->dma != 0)
385 print_hex_dump(KERN_INFO, "",
386 DUMP_PREFIX_ADDRESS, 16, 1,
387 phys_to_virt(tx_buffer_info->dma),
388 tx_buffer_info->length, true);
389 }
390 }
391
392 /* Print RX Rings Summary */
393rx_ring_summary:
394 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 395 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 396 for (n = 0; n < adapter->num_rx_queues; n++) {
397 rx_ring = adapter->rx_ring[n];
c7689578
JP		 398 pr_info("%5d %5X %5X\n",
399 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 400 }
401
402 /* Print RX Rings */
403 if (!netif_msg_rx_status(adapter))
404 goto exit;
405
406 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
407
408 /* Advanced Receive Descriptor (Read) Format
409 * 63 1 0
410 * +-----------------------------------------------------+
411 * 0 | Packet Buffer Address [63:1] |A0/NSE|
412 * +----------------------------------------------+------+
413 * 8 | Header Buffer Address [63:1] | DD |
414 * +-----------------------------------------------------+
415 *
416 *
417 * Advanced Receive Descriptor (Write-Back) Format
418 *
419 * 63 48 47 32 31 30 21 20 16 15 4 3 0
420 * +------------------------------------------------------+
421 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
422 * | Checksum Ident | | | | Type | Type |
423 * +------------------------------------------------------+
424 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
425 * +------------------------------------------------------+
426 * 63 48 47 32 31 20 19 0
427 */
428 for (n = 0; n < adapter->num_rx_queues; n++) {
429 rx_ring = adapter->rx_ring[n];
c7689578
JP		 430 pr_info("------------------------------------\n");
431 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
432 pr_info("------------------------------------\n");
433 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 434 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
435 "<-- Adv Rx Read format\n");
c7689578 436 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 437 "[vl er S cks ln] ---------------- [bi->skb] "
438 "<-- Adv Rx Write-Back format\n");
439
440 for (i = 0; i < rx_ring->count; i++) {
441 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 442 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 443 u0 = (struct my_u0 *)rx_desc;
444 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
445 if (staterr & IXGBE_RXD_STAT_DD) {
446 /* Descriptor Done */
c7689578 447 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 448 "%016llX ---------------- %p", i,
449 le64_to_cpu(u0->a),
450 le64_to_cpu(u0->b),
451 rx_buffer_info->skb);
452 } else {
c7689578 453 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 454 "%016llX %016llX %p", i,
455 le64_to_cpu(u0->a),
456 le64_to_cpu(u0->b),
457 (u64)rx_buffer_info->dma,
458 rx_buffer_info->skb);
459
460 if (netif_msg_pktdata(adapter)) {
461 print_hex_dump(KERN_INFO, "",
462 DUMP_PREFIX_ADDRESS, 16, 1,
463 phys_to_virt(rx_buffer_info->dma),
464 rx_ring->rx_buf_len, true);
465
466 if (rx_ring->rx_buf_len
919e78a6 467 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 468 print_hex_dump(KERN_INFO, "",
469 DUMP_PREFIX_ADDRESS, 16, 1,
470 phys_to_virt(
471 rx_buffer_info->page_dma +
472 rx_buffer_info->page_offset
473 ),
474 PAGE_SIZE/2, true);
475 }
476 }
477
478 if (i == rx_ring->next_to_use)
c7689578 479 pr_cont(" NTU\n");
dcd79aeb 480 else if (i == rx_ring->next_to_clean)
c7689578 481 pr_cont(" NTC\n");
dcd79aeb 482 else
c7689578 483 pr_cont("\n");
dcd79aeb
TI		 484
485 }
486 }
487
488exit:
489 return;
490}
491
5eba3699
AV		 492static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
493{
494 u32 ctrl_ext;
495
496 /* Let firmware take over control of h/w */
497 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
498 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 499 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 500}
501
502static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
503{
504 u32 ctrl_ext;
505
506 /* Let firmware know the driver has taken over */
507 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 509 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 510}
9a799d71 511
e8e26350
PW		 512/*
513 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
514 * @adapter: pointer to adapter struct
515 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
516 * @queue: queue to map the corresponding interrupt to
517 * @msix_vector: the vector to map to the corresponding queue
518 *
519 */
520static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 521 u8 queue, u8 msix_vector)
9a799d71
AK		 522{
523 u32 ivar, index;
e8e26350
PW		 524 struct ixgbe_hw *hw = &adapter->hw;
525 switch (hw->mac.type) {
526 case ixgbe_mac_82598EB:
527 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
528 if (direction == -1)
529 direction = 0;
530 index = (((direction * 64) + queue) >> 2) & 0x1F;
531 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
532 ivar &= ~(0xFF << (8 * (queue & 0x3)));
533 ivar |= (msix_vector << (8 * (queue & 0x3)));
534 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
535 break;
536 case ixgbe_mac_82599EB:
b93a2226 537 case ixgbe_mac_X540:
e8e26350
PW		 538 if (direction == -1) {
539 /* other causes */
540 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
541 index = ((queue & 1) * 8);
542 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
543 ivar &= ~(0xFF << index);
544 ivar |= (msix_vector << index);
545 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
546 break;
547 } else {
548 /* tx or rx causes */
549 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
550 index = ((16 * (queue & 1)) + (8 * direction));
551 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
552 ivar &= ~(0xFF << index);
553 ivar |= (msix_vector << index);
554 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
555 break;
556 }
557 default:
558 break;
559 }
9a799d71
AK		 560}
561
fe49f04a 562static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 563 u64 qmask)
fe49f04a
AD		 564{
565 u32 mask;
566
bd508178
AD		 567 switch (adapter->hw.mac.type) {
568 case ixgbe_mac_82598EB:
fe49f04a
AD		 569 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 571 break;
572 case ixgbe_mac_82599EB:
b93a2226 573 case ixgbe_mac_X540:
fe49f04a
AD		 574 mask = (qmask & 0xFFFFFFFF);
575 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
576 mask = (qmask >> 32);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 578 break;
579 default:
580 break;
fe49f04a
AD		 581 }
582}
583
d3d00239
AD		 584static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
585 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 586{
d3d00239
AD		 587 if (tx_buffer->dma) {
588 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
589 dma_unmap_page(ring->dev,
590 tx_buffer->dma,
591 tx_buffer->length,
592 DMA_TO_DEVICE);
e5a43549 593 else
d3d00239
AD		 594 dma_unmap_single(ring->dev,
595 tx_buffer->dma,
596 tx_buffer->length,
597 DMA_TO_DEVICE);
e5a43549 598 }
d3d00239
AD		 599 tx_buffer->dma = 0;
600}
601
602void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
603 struct ixgbe_tx_buffer *tx_buffer_info)
604{
605 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
606 if (tx_buffer_info->skb)
9a799d71 607 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 608 tx_buffer_info->skb = NULL;
9a799d71
AK		 609 /* tx_buffer_info must be completely set up in the transmit path */
610}
611
c84d324c
JF		 612static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
613{
614 struct ixgbe_hw *hw = &adapter->hw;
615 struct ixgbe_hw_stats *hwstats = &adapter->stats;
616 u32 data = 0;
617 u32 xoff[8] = {0};
618 int i;
619
620 if ((hw->fc.current_mode == ixgbe_fc_full) ||
621 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
622 switch (hw->mac.type) {
623 case ixgbe_mac_82598EB:
624 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 625 break;
626 default:
c84d324c
JF		 627 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
628 }
629 hwstats->lxoffrxc += data;
630
631 /* refill credits (no tx hang) if we received xoff */
632 if (!data)
633 return;
634
635 for (i = 0; i < adapter->num_tx_queues; i++)
636 clear_bit(__IXGBE_HANG_CHECK_ARMED,
637 &adapter->tx_ring[i]->state);
638 return;
639 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
640 return;
641
642 /* update stats for each tc, only valid with PFC enabled */
643 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
644 switch (hw->mac.type) {
645 case ixgbe_mac_82598EB:
646 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 647 break;
c84d324c
JF		 648 default:
649 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 650 }
c84d324c
JF		 651 hwstats->pxoffrxc[i] += xoff[i];
652 }
653
654 /* disarm tx queues that have received xoff frames */
655 for (i = 0; i < adapter->num_tx_queues; i++) {
656 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 657 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 658
659 if (xoff[tc])
660 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 661 }
26f23d82
YZ		 662}
663
c84d324c 664static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 665{
c84d324c
JF		 666 return ring->tx_stats.completed;
667}
668
669static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
670{
671 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 672 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 673
c84d324c
JF		 674 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
675 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
676
677 if (head != tail)
678 return (head < tail) ?
679 tail - head : (tail + ring->count - head);
680
681 return 0;
682}
683
684static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
685{
686 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
687 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
688 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
689 bool ret = false;
690
7d637bcc 691 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 692
693 /*
694 * Check for a hung queue, but be thorough. This verifies
695 * that a transmit has been completed since the previous
696 * check AND there is at least one packet pending. The
697 * ARMED bit is set to indicate a potential hang. The
698 * bit is cleared if a pause frame is received to remove
699 * false hang detection due to PFC or 802.3x frames. By
700 * requiring this to fail twice we avoid races with
701 * pfc clearing the ARMED bit and conditions where we
702 * run the check_tx_hang logic with a transmit completion
703 * pending but without time to complete it yet.
704 */
705 if ((tx_done_old == tx_done) && tx_pending) {
706 /* make sure it is true for two checks in a row */
707 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
708 &tx_ring->state);
709 } else {
710 /* update completed stats and continue */
711 tx_ring->tx_stats.tx_done_old = tx_done;
712 /* reset the countdown */
713 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 714 }
715
c84d324c 716 return ret;
9a799d71
AK		 717}
718
c83c6cbd
AD		 719/**
720 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
721 * @adapter: driver private struct
722 **/
723static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
724{
725
726 /* Do the reset outside of interrupt context */
727 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
728 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
729 ixgbe_service_event_schedule(adapter);
730 }
731}
e01c31a5 732
9a799d71
AK		 733/**
734 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 735 * @q_vector: structure containing interrupt and ring information
e01c31a5 736 * @tx_ring: tx ring to clean
9a799d71 737 **/
fe49f04a 738static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 739 struct ixgbe_ring *tx_ring)
9a799d71 740{
fe49f04a 741 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 742 struct ixgbe_tx_buffer *tx_buffer;
743 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 744 unsigned int total_bytes = 0, total_packets = 0;
59224555 745 unsigned int budget = q_vector->tx.work_limit;
d3d00239 746 u16 i = tx_ring->next_to_clean;
9a799d71 747
d3d00239
AD		 748 tx_buffer = &tx_ring->tx_buffer_info[i];
749 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
12207e49 750
30065e63 751 for (; budget; budget--) {
d3d00239
AD		 752 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
753
754 /* if next_to_watch is not set then there is no work pending */
755 if (!eop_desc)
756 break;
757
758 /* if DD is not set pending work has not been completed */
759 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
760 break;
8ad494b0 761
d3d00239
AD		 762 /* count the packet as being completed */
763 tx_ring->tx_stats.completed++;
764
765 /* clear next_to_watch to prevent false hangs */
766 tx_buffer->next_to_watch = NULL;
8ad494b0 767
d3d00239
AD		 768 /* prevent any other reads prior to eop_desc being verified */
769 rmb();
770
771 do {
772 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 773 tx_desc->wb.status = 0;
d3d00239
AD		 774 if (likely(tx_desc == eop_desc)) {
775 eop_desc = NULL;
776 dev_kfree_skb_any(tx_buffer->skb);
777 tx_buffer->skb = NULL;
778
779 total_bytes += tx_buffer->bytecount;
780 total_packets += tx_buffer->gso_segs;
781 }
9a799d71 782
d3d00239
AD		 783 tx_buffer++;
784 tx_desc++;
8ad494b0 785 i++;
d3d00239 786 if (unlikely(i == tx_ring->count)) {
8ad494b0 787 i = 0;
e01c31a5 788
d3d00239
AD		 789 tx_buffer = tx_ring->tx_buffer_info;
790 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
e092be60 791 }
e01c31a5 792
d3d00239 793 } while (eop_desc);
12207e49
PWJ		 794 }
795
9a799d71 796 tx_ring->next_to_clean = i;
d3d00239 797 u64_stats_update_begin(&tx_ring->syncp);
b953799e 798 tx_ring->stats.bytes += total_bytes;
bd198058 799 tx_ring->stats.packets += total_packets;
d3d00239 800 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 801 q_vector->tx.total_bytes += total_bytes;
802 q_vector->tx.total_packets += total_packets;
b953799e 803
c84d324c
JF		 804 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
805 /* schedule immediate reset if we believe we hung */
806 struct ixgbe_hw *hw = &adapter->hw;
d3d00239 807 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
c84d324c
JF		 808 e_err(drv, "Detected Tx Unit Hang\n"
809 " Tx Queue <%d>\n"
810 " TDH, TDT <%x>, <%x>\n"
811 " next_to_use <%x>\n"
812 " next_to_clean <%x>\n"
813 "tx_buffer_info[next_to_clean]\n"
814 " time_stamp <%lx>\n"
815 " jiffies <%lx>\n",
816 tx_ring->queue_index,
817 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
818 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 819 tx_ring->next_to_use, i,
820 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 821
822 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
823
824 e_info(probe,
825 "tx hang %d detected on queue %d, resetting adapter\n",
826 adapter->tx_timeout_count + 1, tx_ring->queue_index);
827
b953799e 828 /* schedule immediate reset if we believe we hung */
c83c6cbd 829 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 830
831 /* the adapter is about to reset, no point in enabling stuff */
59224555 832 return true;
b953799e 833 }
9a799d71 834
e092be60 835#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 836 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 837 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 838 /* Make sure that anybody stopping the queue after this
839 * sees the new next_to_clean.
840 */
841 smp_mb();
fc77dc3c 842 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 843 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 844 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 845 ++tx_ring->tx_stats.restart_queue;
30eba97a 846 }
e092be60 847 }
9a799d71 848
59224555 849 return !!budget;
9a799d71
AK		 850}
851
5dd2d332 852#ifdef CONFIG_IXGBE_DCA
bd0362dd 853static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 854 struct ixgbe_ring *rx_ring,
855 int cpu)
bd0362dd 856{
33cf09c9 857 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 858 u32 rxctrl;
33cf09c9
AD		 859 u8 reg_idx = rx_ring->reg_idx;
860
861 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
862 switch (hw->mac.type) {
863 case ixgbe_mac_82598EB:
864 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
263a84e7 865 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 866 break;
867 case ixgbe_mac_82599EB:
b93a2226 868 case ixgbe_mac_X540:
33cf09c9 869 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
263a84e7 870 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
33cf09c9
AD		 871 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
872 break;
873 default:
874 break;
bd0362dd 875 }
33cf09c9
AD		 876 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
877 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
878 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 879 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 880}
881
882static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 883 struct ixgbe_ring *tx_ring,
884 int cpu)
bd0362dd 885{
33cf09c9 886 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 887 u32 txctrl;
33cf09c9
AD		 888 u8 reg_idx = tx_ring->reg_idx;
889
890 switch (hw->mac.type) {
891 case ixgbe_mac_82598EB:
892 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
893 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
263a84e7 894 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
33cf09c9 895 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 896 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
897 break;
898 case ixgbe_mac_82599EB:
b93a2226 899 case ixgbe_mac_X540:
33cf09c9
AD		 900 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
901 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
263a84e7 902 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
33cf09c9
AD		 903 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
904 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 905 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
906 break;
907 default:
908 break;
909 }
910}
911
912static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
913{
914 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 915 struct ixgbe_ring *ring;
bd0362dd 916 int cpu = get_cpu();
bd0362dd 917
33cf09c9
AD		 918 if (q_vector->cpu == cpu)
919 goto out_no_update;
920
efe3d3c8
AD		 921 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
922 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 923
efe3d3c8
AD		 924 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
925 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 926
927 q_vector->cpu = cpu;
928out_no_update:
bd0362dd
JC		 929 put_cpu();
930}
931
932static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
933{
33cf09c9 934 int num_q_vectors;
bd0362dd
JC		 935 int i;
936
937 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
938 return;
939
e35ec126
AD		 940 /* always use CB2 mode, difference is masked in the CB driver */
941 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
942
33cf09c9
AD		 943 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
944 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
945 else
946 num_q_vectors = 1;
947
948 for (i = 0; i < num_q_vectors; i++) {
949 adapter->q_vector[i]->cpu = -1;
950 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 951 }
952}
953
954static int __ixgbe_notify_dca(struct device *dev, void *data)
955{
c60fbb00 956 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 957 unsigned long event = *(unsigned long *)data;
958
2a72c31e 959 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 960 return 0;
961
bd0362dd
JC		 962 switch (event) {
963 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 964 /* if we're already enabled, don't do it again */
965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
966 break;
652f093f 967 if (dca_add_requester(dev) == 0) {
96b0e0f6 968 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 969 ixgbe_setup_dca(adapter);
970 break;
971 }
972 /* Fall Through since DCA is disabled. */
973 case DCA_PROVIDER_REMOVE:
974 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
975 dca_remove_requester(dev);
976 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
977 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
978 }
979 break;
980 }
981
652f093f 982 return 0;
bd0362dd 983}
5dd2d332 984#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 985
986static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
987 struct sk_buff *skb)
988{
989 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
990}
991
ff886dfc
AD		 992/**
993 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
994 * @adapter: address of board private structure
995 * @rx_desc: advanced rx descriptor
996 *
997 * Returns : true if it is FCoE pkt
998 */
999static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1000 union ixgbe_adv_rx_desc *rx_desc)
1001{
1002 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1003
1004 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1005 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1006 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1007 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1008}
1009
9a799d71
AK		 1010/**
1011 * ixgbe_receive_skb - Send a completed packet up the stack
1012 * @adapter: board private structure
1013 * @skb: packet to send up
177db6ff
MC		 1014 * @status: hardware indication of status of receive
1015 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1016 * @rx_desc: rx descriptor
9a799d71 1017 **/
78b6f4ce 1018static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1019 struct sk_buff *skb, u8 status,
1020 struct ixgbe_ring *ring,
1021 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1022{
78b6f4ce
HX		 1023 struct ixgbe_adapter *adapter = q_vector->adapter;
1024 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1025 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1026 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1027
f62bbb5e
JG		 1028 if (is_vlan && (tag & VLAN_VID_MASK))
1029 __vlan_hwaccel_put_tag(skb, tag);
1030
1031 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1032 napi_gro_receive(napi, skb);
1033 else
1034 netif_rx(skb);
9a799d71
AK		 1035}
1036
e59bd25d
AV		 1037/**
1038 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1039 * @adapter: address of board private structure
1040 * @status_err: hardware indication of status of receive
1041 * @skb: skb currently being received and modified
ff886dfc 1042 * @status_err: status error value of last descriptor in packet
e59bd25d 1043 **/
9a799d71 1044static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1045 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1046 struct sk_buff *skb,
1047 u32 status_err)
9a799d71 1048{
ff886dfc 1049 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1050
712744be
JB		 1051 /* Rx csum disabled */
1052 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1053 return;
e59bd25d
AV		 1054
1055 /* if IP and error */
1056 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1057 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1058 adapter->hw_csum_rx_error++;
1059 return;
1060 }
e59bd25d
AV		 1061
1062 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1063 return;
1064
1065 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1066 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1067
1068 /*
1069 * 82599 errata, UDP frames with a 0 checksum can be marked as
1070 * checksum errors.
1071 */
1072 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1073 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1074 return;
1075
e59bd25d
AV		 1076 adapter->hw_csum_rx_error++;
1077 return;
1078 }
1079
9a799d71 1080 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1081 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1082}
1083
84ea2591 1084static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1085{
1086 /*
1087 * Force memory writes to complete before letting h/w
1088 * know there are new descriptors to fetch. (Only
1089 * applicable for weak-ordered memory model archs,
1090 * such as IA-64).
1091 */
1092 wmb();
84ea2591 1093 writel(val, rx_ring->tail);
e8e26350
PW		 1094}
1095
9a799d71
AK		 1096/**
1097 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1098 * @rx_ring: ring to place buffers on
1099 * @cleaned_count: number of buffers to replace
9a799d71 1100 **/
fc77dc3c 1101void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1102{
9a799d71 1103 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1104 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1105 struct sk_buff *skb;
1106 u16 i = rx_ring->next_to_use;
9a799d71 1107
fc77dc3c
AD		 1108 /* do nothing if no valid netdev defined */
1109 if (!rx_ring->netdev)
1110 return;
1111
9a799d71 1112 while (cleaned_count--) {
31f05a2d 1113 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1114 bi = &rx_ring->rx_buffer_info[i];
1115 skb = bi->skb;
9a799d71 1116
d5f398ed 1117 if (!skb) {
fc77dc3c 1118 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1119 rx_ring->rx_buf_len);
9a799d71 1120 if (!skb) {
5b7da515 1121 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1122 goto no_buffers;
1123 }
d716a7d8
AD		 1124 /* initialize queue mapping */
1125 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1126 bi->skb = skb;
d716a7d8 1127 }
9a799d71 1128
d716a7d8 1129 if (!bi->dma) {
b6ec895e 1130 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1131 skb->data,
e8e9f696 1132 rx_ring->rx_buf_len,
1b507730 1133 DMA_FROM_DEVICE);
b6ec895e 1134 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1135 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1136 bi->dma = 0;
1137 goto no_buffers;
1138 }
9a799d71 1139 }
d5f398ed 1140
7d637bcc 1141 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1142 if (!bi->page) {
fc77dc3c 1143 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1144 if (!bi->page) {
5b7da515 1145 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1146 goto no_buffers;
1147 }
1148 }
1149
1150 if (!bi->page_dma) {
1151 /* use a half page if we're re-using */
1152 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1153 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1154 bi->page,
1155 bi->page_offset,
1156 PAGE_SIZE / 2,
1157 DMA_FROM_DEVICE);
b6ec895e 1158 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1159 bi->page_dma)) {
5b7da515 1160 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1161 bi->page_dma = 0;
1162 goto no_buffers;
1163 }
1164 }
1165
1166 /* Refresh the desc even if buffer_addrs didn't change
1167 * because each write-back erases this info. */
3a581073
JB		 1168 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1169 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1170 } else {
3a581073 1171 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1172 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1173 }
1174
1175 i++;
1176 if (i == rx_ring->count)
1177 i = 0;
9a799d71 1178 }
7c6e0a43 1179
9a799d71
AK		 1180no_buffers:
1181 if (rx_ring->next_to_use != i) {
1182 rx_ring->next_to_use = i;
84ea2591 1183 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1184 }
1185}
1186
c267fc16 1187static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1188{
c267fc16
AD		 1189 /* HW will not DMA in data larger than the given buffer, even if it
1190 * parses the (NFS, of course) header to be larger. In that case, it
1191 * fills the header buffer and spills the rest into the page.
1192 */
1193 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1194 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1195 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1196 if (hlen > IXGBE_RX_HDR_SIZE)
1197 hlen = IXGBE_RX_HDR_SIZE;
1198 return hlen;
7c6e0a43
JB		 1199}
1200
f8212f97
AD		 1201/**
1202 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1203 * @skb: pointer to the last skb in the rsc queue
1204 *
1205 * This function changes a queue full of hw rsc buffers into a completed
1206 * packet. It uses the ->prev pointers to find the first packet and then
1207 * turns it into the frag list owner.
1208 **/
aa80175a 1209static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1210{
1211 unsigned int frag_list_size = 0;
aa80175a 1212 unsigned int skb_cnt = 1;
f8212f97
AD		 1213
1214 while (skb->prev) {
1215 struct sk_buff *prev = skb->prev;
1216 frag_list_size += skb->len;
1217 skb->prev = NULL;
1218 skb = prev;
aa80175a 1219 skb_cnt++;
f8212f97
AD		 1220 }
1221
1222 skb_shinfo(skb)->frag_list = skb->next;
1223 skb->next = NULL;
1224 skb->len += frag_list_size;
1225 skb->data_len += frag_list_size;
1226 skb->truesize += frag_list_size;
aa80175a
AD		 1227 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1228
f8212f97
AD		 1229 return skb;
1230}
1231
aa80175a
AD		 1232static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1233{
1234 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1235 IXGBE_RXDADV_RSCCNT_MASK);
1236}
43634e82 1237
4ff7fb12 1238static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1239 struct ixgbe_ring *rx_ring,
4ff7fb12 1240 int budget)
9a799d71 1241{
78b6f4ce 1242 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1243 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1244 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1245 struct sk_buff *skb;
d2f4fbe2 1246 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1247 const int current_node = numa_node_id();
3d8fd385
YZ		 1248#ifdef IXGBE_FCOE
1249 int ddp_bytes = 0;
1250#endif /* IXGBE_FCOE */
c267fc16
AD		 1251 u32 staterr;
1252 u16 i;
1253 u16 cleaned_count = 0;
aa80175a 1254 bool pkt_is_rsc = false;
9a799d71
AK		 1255
1256 i = rx_ring->next_to_clean;
31f05a2d 1257 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1258 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1259
1260 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1261 u32 upper_len = 0;
9a799d71 1262
3c945e5b 1263 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1264
c267fc16
AD		 1265 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1266
9a799d71 1267 skb = rx_buffer_info->skb;
9a799d71 1268 rx_buffer_info->skb = NULL;
c267fc16 1269 prefetch(skb->data);
9a799d71 1270
c267fc16 1271 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1272 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16 1273
b811ce91
JB		 1274 /* linear means we are building an skb from multiple pages */
1275 if (!skb_is_nonlinear(skb)) {
c267fc16 1276 u16 hlen;
aa80175a 1277 if (pkt_is_rsc &&
c267fc16
AD		 1278 !(staterr & IXGBE_RXD_STAT_EOP) &&
1279 !skb->prev) {
43634e82
MC		 1280 /*
1281 * When HWRSC is enabled, delay unmapping
1282 * of the first packet. It carries the
1283 * header information, HW may still
1284 * access the header after the writeback.
1285 * Only unmap it when EOP is reached
1286 */
e8171aaa 1287 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1288 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1289 } else {
b6ec895e 1290 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1291 rx_buffer_info->dma,
1292 rx_ring->rx_buf_len,
1293 DMA_FROM_DEVICE);
e8171aaa 1294 }
4f57ca6e 1295 rx_buffer_info->dma = 0;
c267fc16
AD		 1296
1297 if (ring_is_ps_enabled(rx_ring)) {
1298 hlen = ixgbe_get_hlen(rx_desc);
1299 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1300 } else {
1301 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1302 }
1303
1304 skb_put(skb, hlen);
1305 } else {
1306 /* assume packet split since header is unmapped */
1307 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1308 }
1309
1310 if (upper_len) {
b6ec895e
AD		 1311 dma_unmap_page(rx_ring->dev,
1312 rx_buffer_info->page_dma,
1313 PAGE_SIZE / 2,
1314 DMA_FROM_DEVICE);
9a799d71
AK		 1315 rx_buffer_info->page_dma = 0;
1316 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1317 rx_buffer_info->page,
1318 rx_buffer_info->page_offset,
1319 upper_len);
762f4c57 1320
c267fc16
AD		 1321 if ((page_count(rx_buffer_info->page) == 1) &&
1322 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1323 get_page(rx_buffer_info->page);
c267fc16
AD		 1324 else
1325 rx_buffer_info->page = NULL;
9a799d71
AK		 1326
1327 skb->len += upper_len;
1328 skb->data_len += upper_len;
1329 skb->truesize += upper_len;
1330 }
1331
1332 i++;
1333 if (i == rx_ring->count)
1334 i = 0;
9a799d71 1335
31f05a2d 1336 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1337 prefetch(next_rxd);
9a799d71 1338 cleaned_count++;
f8212f97 1339
aa80175a 1340 if (pkt_is_rsc) {
f8212f97
AD		 1341 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1342 IXGBE_RXDADV_NEXTP_SHIFT;
1343 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1344 } else {
1345 next_buffer = &rx_ring->rx_buffer_info[i];
1346 }
1347
c267fc16 1348 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1349 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1350 rx_buffer_info->skb = next_buffer->skb;
1351 rx_buffer_info->dma = next_buffer->dma;
1352 next_buffer->skb = skb;
1353 next_buffer->dma = 0;
1354 } else {
1355 skb->next = next_buffer->skb;
1356 skb->next->prev = skb;
1357 }
5b7da515 1358 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1359 goto next_desc;
1360 }
1361
aa80175a
AD		 1362 if (skb->prev) {
1363 skb = ixgbe_transform_rsc_queue(skb);
1364 /* if we got here without RSC the packet is invalid */
1365 if (!pkt_is_rsc) {
1366 __pskb_trim(skb, 0);
1367 rx_buffer_info->skb = skb;
1368 goto next_desc;
1369 }
1370 }
c267fc16
AD		 1371
1372 if (ring_is_rsc_enabled(rx_ring)) {
1373 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1374 dma_unmap_single(rx_ring->dev,
1375 IXGBE_RSC_CB(skb)->dma,
1376 rx_ring->rx_buf_len,
1377 DMA_FROM_DEVICE);
1378 IXGBE_RSC_CB(skb)->dma = 0;
1379 IXGBE_RSC_CB(skb)->delay_unmap = false;
1380 }
aa80175a
AD		 1381 }
1382 if (pkt_is_rsc) {
c267fc16
AD		 1383 if (ring_is_ps_enabled(rx_ring))
1384 rx_ring->rx_stats.rsc_count +=
aa80175a 1385 skb_shinfo(skb)->nr_frags;
c267fc16 1386 else
aa80175a
AD		 1387 rx_ring->rx_stats.rsc_count +=
1388 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1389 rx_ring->rx_stats.rsc_flush++;
1390 }
1391
1392 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1393 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1394 dev_kfree_skb_any(skb);
9a799d71
AK		 1395 goto next_desc;
1396 }
1397
ff886dfc 1398 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1399 if (adapter->netdev->features & NETIF_F_RXHASH)
1400 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1401
1402 /* probably a little skewed due to removing CRC */
1403 total_rx_bytes += skb->len;
1404 total_rx_packets++;
1405
fc77dc3c 1406 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1407#ifdef IXGBE_FCOE
1408 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1409 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1410 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1411 staterr);
63d635b2
AD		 1412 if (!ddp_bytes) {
1413 dev_kfree_skb_any(skb);
332d4a7d 1414 goto next_desc;
63d635b2 1415 }
3d8fd385 1416 }
332d4a7d 1417#endif /* IXGBE_FCOE */
fdaff1ce 1418 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71 1419
4ff7fb12 1420 budget--;
9a799d71
AK		 1421next_desc:
1422 rx_desc->wb.upper.status_error = 0;
1423
4ff7fb12 1424 if (!budget)
c267fc16
AD		 1425 break;
1426
9a799d71
AK		 1427 /* return some buffers to hardware, one at a time is too slow */
1428 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1429 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1430 cleaned_count = 0;
1431 }
1432
1433 /* use prefetched values */
1434 rx_desc = next_rxd;
9a799d71 1435 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1436 }
1437
9a799d71 1438 rx_ring->next_to_clean = i;
7d4987de 1439 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1440
1441 if (cleaned_count)
fc77dc3c 1442 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1443
3d8fd385
YZ		 1444#ifdef IXGBE_FCOE
1445 /* include DDPed FCoE data */
1446 if (ddp_bytes > 0) {
1447 unsigned int mss;
1448
fc77dc3c 1449 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1450 sizeof(struct fc_frame_header) -
1451 sizeof(struct fcoe_crc_eof);
1452 if (mss > 512)
1453 mss &= ~511;
1454 total_rx_bytes += ddp_bytes;
1455 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1456 }
1457#endif /* IXGBE_FCOE */
1458
c267fc16
AD		 1459 u64_stats_update_begin(&rx_ring->syncp);
1460 rx_ring->stats.packets += total_rx_packets;
1461 rx_ring->stats.bytes += total_rx_bytes;
1462 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1463 q_vector->rx.total_packets += total_rx_packets;
1464 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1465
1466 return !!budget;
9a799d71
AK		 1467}
1468
9a799d71
AK		 1469/**
1470 * ixgbe_configure_msix - Configure MSI-X hardware
1471 * @adapter: board private structure
1472 *
1473 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1474 * interrupts.
1475 **/
1476static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1477{
021230d4 1478 struct ixgbe_q_vector *q_vector;
efe3d3c8 1479 int q_vectors, v_idx;
021230d4 1480 u32 mask;
9a799d71 1481
021230d4 1482 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1483
8e34d1aa
AD		 1484 /* Populate MSIX to EITR Select */
1485 if (adapter->num_vfs > 32) {
1486 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1487 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1488 }
1489
4df10466
JB		 1490 /*
1491 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1492 * corresponding register.
1493 */
1494 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1495 struct ixgbe_ring *ring;
7a921c93 1496 q_vector = adapter->q_vector[v_idx];
021230d4 1497
efe3d3c8
AD		 1498 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1499 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1500
1501 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1502 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1503
d5bf4f67
ET		 1504 if (q_vector->tx.ring && !q_vector->rx.ring) {
1505 /* tx only vector */
1506 if (adapter->tx_itr_setting == 1)
1507 q_vector->itr = IXGBE_10K_ITR;
1508 else
1509 q_vector->itr = adapter->tx_itr_setting;
1510 } else {
1511 /* rx or rx/tx vector */
1512 if (adapter->rx_itr_setting == 1)
1513 q_vector->itr = IXGBE_20K_ITR;
1514 else
1515 q_vector->itr = adapter->rx_itr_setting;
1516 }
021230d4 1517
fe49f04a 1518 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1519 }
1520
bd508178
AD		 1521 switch (adapter->hw.mac.type) {
1522 case ixgbe_mac_82598EB:
e8e26350 1523 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1524 v_idx);
bd508178
AD		 1525 break;
1526 case ixgbe_mac_82599EB:
b93a2226 1527 case ixgbe_mac_X540:
e8e26350 1528 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1529 break;
bd508178
AD		 1530 default:
1531 break;
1532 }
021230d4
AV		 1533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1534
41fb9248 1535 /* set up to autoclear timer, and the vectors */
021230d4 1536 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1537 mask &= ~(IXGBE_EIMS_OTHER |
1538 IXGBE_EIMS_MAILBOX |
1539 IXGBE_EIMS_LSC);
1540
021230d4 1541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1542}
1543
f494e8fa
AV		 1544enum latency_range {
1545 lowest_latency = 0,
1546 low_latency = 1,
1547 bulk_latency = 2,
1548 latency_invalid = 255
1549};
1550
1551/**
1552 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1553 * @q_vector: structure containing interrupt and ring information
1554 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1555 *
1556 * Stores a new ITR value based on packets and byte
1557 * counts during the last interrupt. The advantage of per interrupt
1558 * computation is faster updates and more accurate ITR for the current
1559 * traffic pattern. Constants in this function were computed
1560 * based on theoretical maximum wire speed and thresholds were set based
1561 * on testing data as well as attempting to minimize response time
1562 * while increasing bulk throughput.
1563 * this functionality is controlled by the InterruptThrottleRate module
1564 * parameter (see ixgbe_param.c)
1565 **/
bd198058
AD		 1566static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1567 struct ixgbe_ring_container *ring_container)
f494e8fa 1568{
f494e8fa 1569 u64 bytes_perint;
bd198058
AD		 1570 struct ixgbe_adapter *adapter = q_vector->adapter;
1571 int bytes = ring_container->total_bytes;
1572 int packets = ring_container->total_packets;
1573 u32 timepassed_us;
1574 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1575
1576 if (packets == 0)
bd198058 1577 return;
f494e8fa
AV		 1578
1579 /* simple throttlerate management
1580 * 0-20MB/s lowest (100000 ints/s)
1581 * 20-100MB/s low (20000 ints/s)
1582 * 100-1249MB/s bulk (8000 ints/s)
1583 */
1584 /* what was last interrupt timeslice? */
d5bf4f67 1585 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1586 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1587
1588 switch (itr_setting) {
1589 case lowest_latency:
1590 if (bytes_perint > adapter->eitr_low)
bd198058 1591 itr_setting = low_latency;
f494e8fa
AV		 1592 break;
1593 case low_latency:
1594 if (bytes_perint > adapter->eitr_high)
bd198058 1595 itr_setting = bulk_latency;
f494e8fa 1596 else if (bytes_perint <= adapter->eitr_low)
bd198058 1597 itr_setting = lowest_latency;
f494e8fa
AV		 1598 break;
1599 case bulk_latency:
1600 if (bytes_perint <= adapter->eitr_high)
bd198058 1601 itr_setting = low_latency;
f494e8fa
AV		 1602 break;
1603 }
1604
bd198058
AD		 1605 /* clear work counters since we have the values we need */
1606 ring_container->total_bytes = 0;
1607 ring_container->total_packets = 0;
1608
1609 /* write updated itr to ring container */
1610 ring_container->itr = itr_setting;
f494e8fa
AV		 1611}
1612
509ee935
JB		 1613/**
1614 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1615 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1616 *
1617 * This function is made to be called by ethtool and by the driver
1618 * when it needs to update EITR registers at runtime. Hardware
1619 * specific quirks/differences are taken care of here.
1620 */
fe49f04a 1621void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1622{
fe49f04a 1623 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1624 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1625 int v_idx = q_vector->v_idx;
d5bf4f67 1626 u32 itr_reg = q_vector->itr;
fe49f04a 1627
bd508178
AD		 1628 switch (adapter->hw.mac.type) {
1629 case ixgbe_mac_82598EB:
509ee935
JB		 1630 /* must write high and low 16 bits to reset counter */
1631 itr_reg |= (itr_reg << 16);
bd508178
AD		 1632 break;
1633 case ixgbe_mac_82599EB:
b93a2226 1634 case ixgbe_mac_X540:
509ee935
JB		 1635 /*
1636 * set the WDIS bit to not clear the timer bits and cause an
1637 * immediate assertion of the interrupt
1638 */
1639 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1640 break;
1641 default:
1642 break;
509ee935
JB		 1643 }
1644 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1645}
1646
bd198058 1647static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1648{
d5bf4f67 1649 u32 new_itr = q_vector->itr;
bd198058 1650 u8 current_itr;
f494e8fa 1651
bd198058
AD		 1652 ixgbe_update_itr(q_vector, &q_vector->tx);
1653 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1654
08c8833b 1655 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1656
1657 switch (current_itr) {
1658 /* counts and packets in update_itr are dependent on these numbers */
1659 case lowest_latency:
d5bf4f67 1660 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1661 break;
1662 case low_latency:
d5bf4f67 1663 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1664 break;
1665 case bulk_latency:
d5bf4f67 1666 new_itr = IXGBE_8K_ITR;
f494e8fa 1667 break;
bd198058
AD		 1668 default:
1669 break;
f494e8fa
AV		 1670 }
1671
d5bf4f67 1672 if (new_itr != q_vector->itr) {
fe49f04a 1673 /* do an exponential smoothing */
d5bf4f67
ET		 1674 new_itr = (10 * new_itr * q_vector->itr) /
1675 ((9 * new_itr) + q_vector->itr);
509ee935 1676
bd198058 1677 /* save the algorithm value here */
d5bf4f67 1678 q_vector->itr = new_itr & IXGBE_MAX_EITR;
fe49f04a
AD		 1679
1680 ixgbe_write_eitr(q_vector);
f494e8fa 1681 }
f494e8fa
AV		 1682}
1683
119fc60a 1684/**
f0f9778d
AD		 1685 * ixgbe_check_overtemp_subtask - check for over tempurature
1686 * @adapter: pointer to adapter
119fc60a 1687 **/
f0f9778d 1688static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1689{
119fc60a
MC		 1690 struct ixgbe_hw *hw = &adapter->hw;
1691 u32 eicr = adapter->interrupt_event;
1692
f0f9778d 1693 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1694 return;
1695
f0f9778d
AD		 1696 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1697 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1698 return;
1699
1700 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1701
7ca647bd 1702 switch (hw->device_id) {
f0f9778d
AD		 1703 case IXGBE_DEV_ID_82599_T3_LOM:
1704 /*
1705 * Since the warning interrupt is for both ports
1706 * we don't have to check if:
1707 * - This interrupt wasn't for our port.
1708 * - We may have missed the interrupt so always have to
1709 * check if we got a LSC
1710 */
1711 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1712 !(eicr & IXGBE_EICR_LSC))
1713 return;
1714
1715 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1716 u32 autoneg;
1717 bool link_up = false;
7ca647bd 1718
7ca647bd
JP		 1719 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1720
f0f9778d
AD		 1721 if (link_up)
1722 return;
1723 }
1724
1725 /* Check if this is not due to overtemp */
1726 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1727 return;
1728
1729 break;
7ca647bd
JP		 1730 default:
1731 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1732 return;
7ca647bd 1733 break;
119fc60a 1734 }
7ca647bd
JP		 1735 e_crit(drv,
1736 "Network adapter has been stopped because it has over heated. "
1737 "Restart the computer. If the problem persists, "
1738 "power off the system and replace the adapter\n");
f0f9778d
AD		 1739
1740 adapter->interrupt_event = 0;
119fc60a
MC		 1741}
1742
0befdb3e
JB		 1743static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1744{
1745 struct ixgbe_hw *hw = &adapter->hw;
1746
1747 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1748 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1749 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1750 /* write to clear the interrupt */
1751 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1752 }
1753}
cf8280ee 1754
4f51bf70
JK		 1755static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1756{
1757 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1758 return;
1759
1760 switch (adapter->hw.mac.type) {
1761 case ixgbe_mac_82599EB:
1762 /*
1763 * Need to check link state so complete overtemp check
1764 * on service task
1765 */
1766 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1767 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1768 adapter->interrupt_event = eicr;
1769 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1770 ixgbe_service_event_schedule(adapter);
1771 return;
1772 }
1773 return;
1774 case ixgbe_mac_X540:
1775 if (!(eicr & IXGBE_EICR_TS))
1776 return;
1777 break;
1778 default:
1779 return;
1780 }
1781
1782 e_crit(drv,
1783 "Network adapter has been stopped because it has over heated. "
1784 "Restart the computer. If the problem persists, "
1785 "power off the system and replace the adapter\n");
1786}
1787
e8e26350
PW		 1788static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1789{
1790 struct ixgbe_hw *hw = &adapter->hw;
1791
73c4b7cd
AD		 1792 if (eicr & IXGBE_EICR_GPI_SDP2) {
1793 /* Clear the interrupt */
1794 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1795 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1796 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1797 ixgbe_service_event_schedule(adapter);
1798 }
73c4b7cd
AD		 1799 }
1800
e8e26350
PW		 1801 if (eicr & IXGBE_EICR_GPI_SDP1) {
1802 /* Clear the interrupt */
1803 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1804 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1805 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1806 ixgbe_service_event_schedule(adapter);
1807 }
e8e26350
PW		 1808 }
1809}
1810
cf8280ee
JB		 1811static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1812{
1813 struct ixgbe_hw *hw = &adapter->hw;
1814
1815 adapter->lsc_int++;
1816 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1817 adapter->link_check_timeout = jiffies;
1818 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1819 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1820 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1821 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1822 }
1823}
1824
fe49f04a
AD		 1825static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1826 u64 qmask)
1827{
1828 u32 mask;
bd508178 1829 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1830
bd508178
AD		 1831 switch (hw->mac.type) {
1832 case ixgbe_mac_82598EB:
fe49f04a 1833 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1834 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1835 break;
1836 case ixgbe_mac_82599EB:
b93a2226 1837 case ixgbe_mac_X540:
fe49f04a 1838 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1839 if (mask)
1840 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1841 mask = (qmask >> 32);
bd508178
AD		 1842 if (mask)
1843 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1844 break;
1845 default:
1846 break;
fe49f04a
AD		 1847 }
1848 /* skip the flush */
1849}
1850
1851static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1852 u64 qmask)
fe49f04a
AD		 1853{
1854 u32 mask;
bd508178 1855 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1856
bd508178
AD		 1857 switch (hw->mac.type) {
1858 case ixgbe_mac_82598EB:
fe49f04a 1859 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1860 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1861 break;
1862 case ixgbe_mac_82599EB:
b93a2226 1863 case ixgbe_mac_X540:
fe49f04a 1864 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1865 if (mask)
1866 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1867 mask = (qmask >> 32);
bd508178
AD		 1868 if (mask)
1869 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1870 break;
1871 default:
1872 break;
fe49f04a
AD		 1873 }
1874 /* skip the flush */
1875}
1876
021230d4 1877/**
2c4af694
AD		 1878 * ixgbe_irq_enable - Enable default interrupt generation settings
1879 * @adapter: board private structure
021230d4 1880 **/
2c4af694
AD		 1881static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1882 bool flush)
9a799d71 1883{
2c4af694 1884 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 1885
2c4af694
AD		 1886 /* don't reenable LSC while waiting for link */
1887 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1888 mask &= ~IXGBE_EIMS_LSC;
9a799d71 1889
2c4af694 1890 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 1891 switch (adapter->hw.mac.type) {
1892 case ixgbe_mac_82599EB:
1893 mask |= IXGBE_EIMS_GPI_SDP0;
1894 break;
1895 case ixgbe_mac_X540:
1896 mask |= IXGBE_EIMS_TS;
1897 break;
1898 default:
1899 break;
1900 }
2c4af694
AD		 1901 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1902 mask |= IXGBE_EIMS_GPI_SDP1;
1903 switch (adapter->hw.mac.type) {
1904 case ixgbe_mac_82599EB:
2c4af694
AD		 1905 mask |= IXGBE_EIMS_GPI_SDP1;
1906 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 1907 case ixgbe_mac_X540:
1908 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 1909 mask |= IXGBE_EIMS_MAILBOX;
1910 break;
1911 default:
1912 break;
9a799d71 1913 }
2c4af694
AD		 1914 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1915 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1916 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 1917
2c4af694
AD		 1918 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1919 if (queues)
1920 ixgbe_irq_enable_queues(adapter, ~0);
1921 if (flush)
1922 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1923}
1924
2c4af694 1925static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 1926{
a65151ba 1927 struct ixgbe_adapter *adapter = data;
9a799d71 1928 struct ixgbe_hw *hw = &adapter->hw;
54037505 1929 u32 eicr;
91281fd3 1930
54037505
DS		 1931 /*
1932 * Workaround for Silicon errata. Use clear-by-write instead
1933 * of clear-by-read. Reading with EICS will return the
1934 * interrupt causes without clearing, which later be done
1935 * with the write to EICR.
1936 */
1937 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1938 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 1939
cf8280ee
JB		 1940 if (eicr & IXGBE_EICR_LSC)
1941 ixgbe_check_lsc(adapter);
f0848276 1942
1cdd1ec8
GR		 1943 if (eicr & IXGBE_EICR_MAILBOX)
1944 ixgbe_msg_task(adapter);
efe3d3c8 1945
bd508178
AD		 1946 switch (hw->mac.type) {
1947 case ixgbe_mac_82599EB:
b93a2226 1948 case ixgbe_mac_X540:
2c4af694
AD		 1949 if (eicr & IXGBE_EICR_ECC)
1950 e_info(link, "Received unrecoverable ECC Err, please "
1951 "reboot\n");
c4cf55e5
PWJ		 1952 /* Handle Flow Director Full threshold interrupt */
1953 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1954 int reinit_count = 0;
c4cf55e5 1955 int i;
c4cf55e5 1956 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1957 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1958 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1959 &ring->state))
1960 reinit_count++;
1961 }
1962 if (reinit_count) {
1963 /* no more flow director interrupts until after init */
1964 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 1965 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1966 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1967 }
1968 }
f0f9778d 1969 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 1970 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 1971 break;
1972 default:
1973 break;
c4cf55e5 1974 }
f0848276 1975
bd508178 1976 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 1977
7086400d 1978 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1979 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 1980 ixgbe_irq_enable(adapter, false, false);
f0848276 1981
9a799d71 1982 return IRQ_HANDLED;
f0848276 1983}
91281fd3 1984
4ff7fb12 1985static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 1986{
021230d4 1987 struct ixgbe_q_vector *q_vector = data;
91281fd3 1988
9b471446 1989 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1990
4ff7fb12
AD		 1991 if (q_vector->rx.ring || q_vector->tx.ring)
1992 napi_schedule(&q_vector->napi);
91281fd3 1993
9a799d71 1994 return IRQ_HANDLED;
91281fd3
AD		 1995}
1996
021230d4 1997static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 1998 int r_idx)
021230d4 1999{
7a921c93 2000 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2001 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2002
2274543f 2003 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2004 rx_ring->next = q_vector->rx.ring;
2005 q_vector->rx.ring = rx_ring;
2006 q_vector->rx.count++;
021230d4
AV		 2007}
2008
2009static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2010 int t_idx)
021230d4 2011{
7a921c93 2012 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2013 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2014
2274543f 2015 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2016 tx_ring->next = q_vector->tx.ring;
2017 q_vector->tx.ring = tx_ring;
2018 q_vector->tx.count++;
bd198058 2019 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2020}
2021
9a799d71 2022/**
021230d4
AV		 2023 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2024 * @adapter: board private structure to initialize
9a799d71 2025 *
021230d4
AV		 2026 * This function maps descriptor rings to the queue-specific vectors
2027 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2028 * one vector per ring/queue, but on a constrained vector budget, we
2029 * group the rings as "efficiently" as possible. You would add new
2030 * mapping configurations in here.
9a799d71 2031 **/
4cc6df29 2032static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2033{
4cc6df29
AD		 2034 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2035 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2036 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
021230d4 2037 int v_start = 0;
021230d4 2038
4cc6df29 2039 /* only one q_vector if MSI-X is disabled. */
021230d4 2040 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
4cc6df29 2041 q_vectors = 1;
d0759ebb 2042
021230d4 2043 /*
4cc6df29
AD		 2044 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2045 * group them so there are multiple queues per vector.
2046 *
2047 * Re-adjusting *qpv takes care of the remainder.
021230d4 2048 */
4cc6df29
AD		 2049 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2050 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2051 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
021230d4 2052 map_vector_to_rxq(adapter, v_start, rxr_idx);
021230d4 2053 }
9a799d71 2054
021230d4 2055 /*
4cc6df29
AD		 2056 * If there are not enough q_vectors for each ring to have it's own
2057 * vector then we must pair up Rx/Tx on a each vector
021230d4 2058 */
4cc6df29
AD		 2059 if ((v_start + txr_remaining) > q_vectors)
2060 v_start = 0;
2061
2062 for (; v_start < q_vectors && txr_remaining; v_start++) {
2063 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2064 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2065 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2066 }
021230d4
AV		 2067}
2068
2069/**
2070 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2071 * @adapter: board private structure
2072 *
2073 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2074 * interrupts from the kernel.
2075 **/
2076static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2077{
2078 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2079 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2080 int vector, err;
e8e9f696 2081 int ri = 0, ti = 0;
021230d4 2082
021230d4 2083 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2084 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2085 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2086
4ff7fb12 2087 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2088 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2089 "%s-%s-%d", netdev->name, "TxRx", ri++);
2090 ti++;
2091 } else if (q_vector->rx.ring) {
9fe93afd 2092 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2093 "%s-%s-%d", netdev->name, "rx", ri++);
2094 } else if (q_vector->tx.ring) {
9fe93afd 2095 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2096 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2097 } else {
2098 /* skip this unused q_vector */
2099 continue;
32aa77a4 2100 }
207867f5
AD		 2101 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2102 q_vector->name, q_vector);
9a799d71 2103 if (err) {
396e799c 2104 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2105 "Error: %d\n", err);
021230d4 2106 goto free_queue_irqs;
9a799d71 2107 }
207867f5
AD		 2108 /* If Flow Director is enabled, set interrupt affinity */
2109 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2110 /* assign the mask for this irq */
2111 irq_set_affinity_hint(entry->vector,
2112 q_vector->affinity_mask);
2113 }
9a799d71
AK		 2114 }
2115
021230d4 2116 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2117 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2118 if (err) {
396e799c 2119 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2120 goto free_queue_irqs;
9a799d71
AK		 2121 }
2122
9a799d71
AK		 2123 return 0;
2124
021230d4 2125free_queue_irqs:
207867f5
AD		 2126 while (vector) {
2127 vector--;
2128 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2129 NULL);
2130 free_irq(adapter->msix_entries[vector].vector,
2131 adapter->q_vector[vector]);
2132 }
021230d4
AV		 2133 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2134 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2135 kfree(adapter->msix_entries);
2136 adapter->msix_entries = NULL;
9a799d71
AK		 2137 return err;
2138}
2139
2140/**
021230d4 2141 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2142 * @irq: interrupt number
2143 * @data: pointer to a network interface device structure
9a799d71
AK		 2144 **/
2145static irqreturn_t ixgbe_intr(int irq, void *data)
2146{
a65151ba 2147 struct ixgbe_adapter *adapter = data;
9a799d71 2148 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2149 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2150 u32 eicr;
2151
54037505 2152 /*
6af3b9eb 2153 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2154 * before the read of EICR.
2155 */
2156 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2157
021230d4
AV		 2158 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2159 * therefore no explict interrupt disable is necessary */
2160 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2161 if (!eicr) {
6af3b9eb
ET		 2162 /*
2163 * shared interrupt alert!
f47cf66e 2164 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2165 * have disabled interrupts due to EIAM
2166 * finish the workaround of silicon errata on 82598. Unmask
2167 * the interrupt that we masked before the EICR read.
2168 */
2169 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2170 ixgbe_irq_enable(adapter, true, true);
9a799d71 2171 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2172 }
9a799d71 2173
cf8280ee
JB		 2174 if (eicr & IXGBE_EICR_LSC)
2175 ixgbe_check_lsc(adapter);
021230d4 2176
bd508178
AD		 2177 switch (hw->mac.type) {
2178 case ixgbe_mac_82599EB:
e8e26350 2179 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2180 /* Fall through */
2181 case ixgbe_mac_X540:
2182 if (eicr & IXGBE_EICR_ECC)
2183 e_info(link, "Received unrecoverable ECC err, please "
2184 "reboot\n");
4f51bf70 2185 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2186 break;
2187 default:
2188 break;
2189 }
e8e26350 2190
0befdb3e
JB		 2191 ixgbe_check_fan_failure(adapter, eicr);
2192
7a921c93 2193 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2194 /* would disable interrupts here but EIAM disabled it */
7a921c93 2195 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2196 }
2197
6af3b9eb
ET		 2198 /*
2199 * re-enable link(maybe) and non-queue interrupts, no flush.
2200 * ixgbe_poll will re-enable the queue interrupts
2201 */
2202
2203 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2204 ixgbe_irq_enable(adapter, false, false);
2205
9a799d71
AK		 2206 return IRQ_HANDLED;
2207}
2208
021230d4
AV		 2209static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2210{
efe3d3c8
AD		 2211 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2212 int i;
2213
2214 /* legacy and MSI only use one vector */
2215 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2216 q_vectors = 1;
2217
2218 for (i = 0; i < adapter->num_rx_queues; i++) {
2219 adapter->rx_ring[i]->q_vector = NULL;
2220 adapter->rx_ring[i]->next = NULL;
2221 }
2222 for (i = 0; i < adapter->num_tx_queues; i++) {
2223 adapter->tx_ring[i]->q_vector = NULL;
2224 adapter->tx_ring[i]->next = NULL;
2225 }
021230d4
AV		 2226
2227 for (i = 0; i < q_vectors; i++) {
7a921c93 2228 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2229 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2230 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2231 }
2232}
2233
9a799d71
AK		 2234/**
2235 * ixgbe_request_irq - initialize interrupts
2236 * @adapter: board private structure
2237 *
2238 * Attempts to configure interrupts using the best available
2239 * capabilities of the hardware and kernel.
2240 **/
021230d4 2241static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2242{
2243 struct net_device *netdev = adapter->netdev;
021230d4 2244 int err;
9a799d71 2245
4cc6df29
AD		 2246 /* map all of the rings to the q_vectors */
2247 ixgbe_map_rings_to_vectors(adapter);
2248
2249 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2250 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2251 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2252 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2253 netdev->name, adapter);
4cc6df29 2254 else
a0607fd3 2255 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2256 netdev->name, adapter);
9a799d71 2257
4cc6df29 2258 if (err) {
396e799c 2259 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2260
4cc6df29
AD		 2261 /* place q_vectors and rings back into a known good state */
2262 ixgbe_reset_q_vectors(adapter);
2263 }
2264
9a799d71
AK		 2265 return err;
2266}
2267
2268static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2269{
9a799d71 2270 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2271 int i, q_vectors;
9a799d71 2272
021230d4 2273 q_vectors = adapter->num_msix_vectors;
021230d4 2274 i = q_vectors - 1;
a65151ba 2275 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2276 i--;
4cc6df29 2277
021230d4 2278 for (; i >= 0; i--) {
894ff7cf 2279 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2280 if (!adapter->q_vector[i]->rx.ring &&
2281 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2282 continue;
2283
207867f5
AD		 2284 /* clear the affinity_mask in the IRQ descriptor */
2285 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2286 NULL);
2287
021230d4 2288 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2289 adapter->q_vector[i]);
021230d4 2290 }
021230d4 2291 } else {
a65151ba 2292 free_irq(adapter->pdev->irq, adapter);
9a799d71 2293 }
207867f5
AD		 2294
2295 /* clear q_vector state information */
2296 ixgbe_reset_q_vectors(adapter);
9a799d71
AK		 2297}
2298
22d5a71b
JB		 2299/**
2300 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2301 * @adapter: board private structure
2302 **/
2303static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2304{
bd508178
AD		 2305 switch (adapter->hw.mac.type) {
2306 case ixgbe_mac_82598EB:
835462fc 2307 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2308 break;
2309 case ixgbe_mac_82599EB:
b93a2226 2310 case ixgbe_mac_X540:
835462fc
NS		 2311 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2312 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2313 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2314 break;
2315 default:
2316 break;
22d5a71b
JB		 2317 }
2318 IXGBE_WRITE_FLUSH(&adapter->hw);
2319 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2320 int i;
2321 for (i = 0; i < adapter->num_msix_vectors; i++)
2322 synchronize_irq(adapter->msix_entries[i].vector);
2323 } else {
2324 synchronize_irq(adapter->pdev->irq);
2325 }
2326}
2327
9a799d71
AK		 2328/**
2329 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2330 *
2331 **/
2332static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2333{
d5bf4f67 2334 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2335
d5bf4f67
ET		 2336 /* rx/tx vector */
2337 if (adapter->rx_itr_setting == 1)
2338 q_vector->itr = IXGBE_20K_ITR;
2339 else
2340 q_vector->itr = adapter->rx_itr_setting;
2341
2342 ixgbe_write_eitr(q_vector);
9a799d71 2343
e8e26350
PW		 2344 ixgbe_set_ivar(adapter, 0, 0, 0);
2345 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2346
396e799c 2347 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2348}
2349
43e69bf0
AD		 2350/**
2351 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2352 * @adapter: board private structure
2353 * @ring: structure containing ring specific data
2354 *
2355 * Configure the Tx descriptor ring after a reset.
2356 **/
84418e3b
AD		 2357void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2358 struct ixgbe_ring *ring)
43e69bf0
AD		 2359{
2360 struct ixgbe_hw *hw = &adapter->hw;
2361 u64 tdba = ring->dma;
2f1860b8 2362 int wait_loop = 10;
b88c6de2 2363 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2364 u8 reg_idx = ring->reg_idx;
43e69bf0 2365
2f1860b8 2366 /* disable queue to avoid issues while updating state */
b88c6de2 2367 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2368 IXGBE_WRITE_FLUSH(hw);
2369
43e69bf0 2370 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2371 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2372 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2373 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2374 ring->count * sizeof(union ixgbe_adv_tx_desc));
2375 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2376 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2377 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2378
b88c6de2
AD		 2379 /*
2380 * set WTHRESH to encourage burst writeback, it should not be set
2381 * higher than 1 when ITR is 0 as it could cause false TX hangs
2382 *
2383 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2384 * to or less than the number of on chip descriptors, which is
2385 * currently 40.
2386 */
2387 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2388 txdctl |= (1 << 16); /* WTHRESH = 1 */
2389 else
2390 txdctl |= (8 << 16); /* WTHRESH = 8 */
2391
2392 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2393 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2394 32; /* PTHRESH = 32 */
2f1860b8
AD		 2395
2396 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2397 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2398 adapter->atr_sample_rate) {
2399 ring->atr_sample_rate = adapter->atr_sample_rate;
2400 ring->atr_count = 0;
2401 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2402 } else {
2403 ring->atr_sample_rate = 0;
2404 }
2f1860b8 2405
c84d324c
JF		 2406 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2407
2f1860b8 2408 /* enable queue */
2f1860b8
AD		 2409 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2410
2411 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2412 if (hw->mac.type == ixgbe_mac_82598EB &&
2413 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2414 return;
2415
2416 /* poll to verify queue is enabled */
2417 do {
032b4325 2418 usleep_range(1000, 2000);
2f1860b8
AD		 2419 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2420 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2421 if (!wait_loop)
2422 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2423}
2424
120ff942
AD		 2425static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2426{
2427 struct ixgbe_hw *hw = &adapter->hw;
2428 u32 rttdcs;
72a32f1f 2429 u32 reg;
8b1c0b24 2430 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2431
2432 if (hw->mac.type == ixgbe_mac_82598EB)
2433 return;
2434
2435 /* disable the arbiter while setting MTQC */
2436 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2437 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2438 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2439
2440 /* set transmit pool layout */
8b1c0b24 2441 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2442 case (IXGBE_FLAG_SRIOV_ENABLED):
2443 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2444 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2445 break;
8b1c0b24
JF		 2446 default:
2447 if (!tcs)
2448 reg = IXGBE_MTQC_64Q_1PB;
2449 else if (tcs <= 4)
2450 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2451 else
2452 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2453
8b1c0b24 2454 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2455
8b1c0b24
JF		 2456 /* Enable Security TX Buffer IFG for multiple pb */
2457 if (tcs) {
2458 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2459 reg |= IXGBE_SECTX_DCB;
2460 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2461 }
120ff942
AD		 2462 break;
2463 }
2464
2465 /* re-enable the arbiter */
2466 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2467 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2468}
2469
9a799d71 2470/**
3a581073 2471 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2472 * @adapter: board private structure
2473 *
2474 * Configure the Tx unit of the MAC after a reset.
2475 **/
2476static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2477{
2f1860b8
AD		 2478 struct ixgbe_hw *hw = &adapter->hw;
2479 u32 dmatxctl;
43e69bf0 2480 u32 i;
9a799d71 2481
2f1860b8
AD		 2482 ixgbe_setup_mtqc(adapter);
2483
2484 if (hw->mac.type != ixgbe_mac_82598EB) {
2485 /* DMATXCTL.EN must be before Tx queues are enabled */
2486 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2487 dmatxctl |= IXGBE_DMATXCTL_TE;
2488 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2489 }
2490
9a799d71 2491 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2492 for (i = 0; i < adapter->num_tx_queues; i++)
2493 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2494}
2495
e8e26350 2496#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2497
a6616b42 2498static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2499 struct ixgbe_ring *rx_ring)
cc41ac7c 2500{
cc41ac7c 2501 u32 srrctl;
bf29ee6c 2502 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2503
bd508178
AD		 2504 switch (adapter->hw.mac.type) {
2505 case ixgbe_mac_82598EB: {
2506 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2507 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2508 reg_idx = reg_idx & mask;
cc41ac7c 2509 }
bd508178
AD		 2510 break;
2511 case ixgbe_mac_82599EB:
b93a2226 2512 case ixgbe_mac_X540:
bd508178
AD		 2513 default:
2514 break;
2515 }
2516
bf29ee6c 2517 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2518
2519 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2520 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2521 if (adapter->num_vfs)
2522 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2523
afafd5b0
AD		 2524 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2525 IXGBE_SRRCTL_BSIZEHDR_MASK;
2526
7d637bcc 2527 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2528#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2529 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2530#else
2531 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2532#endif
cc41ac7c 2533 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2534 } else {
afafd5b0
AD		 2535 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2536 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2537 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2538 }
e8e26350 2539
bf29ee6c 2540 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2541}
9a799d71 2542
05abb126 2543static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2544{
05abb126
AD		 2545 struct ixgbe_hw *hw = &adapter->hw;
2546 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2547 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2548 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2549 u32 mrqc = 0, reta = 0;
2550 u32 rxcsum;
2551 int i, j;
8b1c0b24 2552 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2553 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2554
2555 if (tcs)
2556 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2557
05abb126
AD		 2558 /* Fill out hash function seeds */
2559 for (i = 0; i < 10; i++)
2560 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2561
2562 /* Fill out redirection table */
2563 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2564 if (j == maxq)
05abb126
AD		 2565 j = 0;
2566 /* reta = 4-byte sliding window of
2567 * 0x00..(indices-1)(indices-1)00..etc. */
2568 reta = (reta << 8) | (j * 0x11);
2569 if ((i & 3) == 3)
2570 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2571 }
0cefafad 2572
05abb126
AD		 2573 /* Disable indicating checksum in descriptor, enables RSS hash */
2574 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2575 rxcsum |= IXGBE_RXCSUM_PCSD;
2576 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2577
8b1c0b24
JF		 2578 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2579 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2580 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2581 } else {
2582 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2583 | IXGBE_FLAG_SRIOV_ENABLED);
2584
2585 switch (mask) {
2586 case (IXGBE_FLAG_RSS_ENABLED):
2587 if (!tcs)
2588 mrqc = IXGBE_MRQC_RSSEN;
2589 else if (tcs <= 4)
2590 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2591 else
2592 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2593 break;
2594 case (IXGBE_FLAG_SRIOV_ENABLED):
2595 mrqc = IXGBE_MRQC_VMDQEN;
2596 break;
2597 default:
2598 break;
2599 }
0cefafad
JB		 2600 }
2601
05abb126
AD		 2602 /* Perform hash on these packet types */
2603 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2604 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2605 | IXGBE_MRQC_RSS_FIELD_IPV6
2606 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2607
2608 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2609}
2610
bb5a9ad2
NS		 2611/**
2612 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2613 * @adapter: address of board private structure
2614 * @index: index of ring to set
bb5a9ad2 2615 **/
082757af 2616static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2617 struct ixgbe_ring *ring)
bb5a9ad2 2618{
bb5a9ad2 2619 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2620 u32 rscctrl;
edd2ea55 2621 int rx_buf_len;
bf29ee6c 2622 u8 reg_idx = ring->reg_idx;
7367096a 2623
7d637bcc 2624 if (!ring_is_rsc_enabled(ring))
7367096a 2625 return;
bb5a9ad2 2626
7367096a
AD		 2627 rx_buf_len = ring->rx_buf_len;
2628 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2629 rscctrl |= IXGBE_RSCCTL_RSCEN;
2630 /*
2631 * we must limit the number of descriptors so that the
2632 * total size of max desc * buf_len is not greater
2633 * than 65535
2634 */
7d637bcc 2635 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2636#if (MAX_SKB_FRAGS > 16)
2637 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2638#elif (MAX_SKB_FRAGS > 8)
2639 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2640#elif (MAX_SKB_FRAGS > 4)
2641 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2642#else
2643 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2644#endif
2645 } else {
919e78a6 2646 if (rx_buf_len < IXGBE_RXBUFFER_4K)
bb5a9ad2 2647 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
919e78a6 2648 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2649 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2650 else
2651 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2652 }
7367096a 2653 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2654}
2655
9e10e045
AD		 2656/**
2657 * ixgbe_set_uta - Set unicast filter table address
2658 * @adapter: board private structure
2659 *
2660 * The unicast table address is a register array of 32-bit registers.
2661 * The table is meant to be used in a way similar to how the MTA is used
2662 * however due to certain limitations in the hardware it is necessary to
2663 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2664 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2665 **/
2666static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2667{
2668 struct ixgbe_hw *hw = &adapter->hw;
2669 int i;
2670
2671 /* The UTA table only exists on 82599 hardware and newer */
2672 if (hw->mac.type < ixgbe_mac_82599EB)
2673 return;
2674
2675 /* we only need to do this if VMDq is enabled */
2676 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2677 return;
2678
2679 for (i = 0; i < 128; i++)
2680 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2681}
2682
2683#define IXGBE_MAX_RX_DESC_POLL 10
2684static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2685 struct ixgbe_ring *ring)
2686{
2687 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2688 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2689 u32 rxdctl;
bf29ee6c 2690 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2691
2692 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2693 if (hw->mac.type == ixgbe_mac_82598EB &&
2694 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2695 return;
2696
2697 do {
032b4325 2698 usleep_range(1000, 2000);
9e10e045
AD		 2699 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2700 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2701
2702 if (!wait_loop) {
2703 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2704 "the polling period\n", reg_idx);
2705 }
2706}
2707
2d39d576
YZ		 2708void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2709 struct ixgbe_ring *ring)
2710{
2711 struct ixgbe_hw *hw = &adapter->hw;
2712 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2713 u32 rxdctl;
2714 u8 reg_idx = ring->reg_idx;
2715
2716 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2717 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2718
2719 /* write value back with RXDCTL.ENABLE bit cleared */
2720 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2721
2722 if (hw->mac.type == ixgbe_mac_82598EB &&
2723 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2724 return;
2725
2726 /* the hardware may take up to 100us to really disable the rx queue */
2727 do {
2728 udelay(10);
2729 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2730 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2731
2732 if (!wait_loop) {
2733 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2734 "the polling period\n", reg_idx);
2735 }
2736}
2737
84418e3b
AD		 2738void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2739 struct ixgbe_ring *ring)
acd37177
AD		 2740{
2741 struct ixgbe_hw *hw = &adapter->hw;
2742 u64 rdba = ring->dma;
9e10e045 2743 u32 rxdctl;
bf29ee6c 2744 u8 reg_idx = ring->reg_idx;
acd37177 2745
9e10e045
AD		 2746 /* disable queue to avoid issues while updating state */
2747 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2748 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2749
acd37177
AD		 2750 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2751 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2752 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2753 ring->count * sizeof(union ixgbe_adv_rx_desc));
2754 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2755 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2756 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2757
2758 ixgbe_configure_srrctl(adapter, ring);
2759 ixgbe_configure_rscctl(adapter, ring);
2760
e9f98072
GR		 2761 /* If operating in IOV mode set RLPML for X540 */
2762 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2763 hw->mac.type == ixgbe_mac_X540) {
2764 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2765 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2766 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2767 }
2768
9e10e045
AD		 2769 if (hw->mac.type == ixgbe_mac_82598EB) {
2770 /*
2771 * enable cache line friendly hardware writes:
2772 * PTHRESH=32 descriptors (half the internal cache),
2773 * this also removes ugly rx_no_buffer_count increment
2774 * HTHRESH=4 descriptors (to minimize latency on fetch)
2775 * WTHRESH=8 burst writeback up to two cache lines
2776 */
2777 rxdctl &= ~0x3FFFFF;
2778 rxdctl |= 0x080420;
2779 }
2780
2781 /* enable receive descriptor ring */
2782 rxdctl |= IXGBE_RXDCTL_ENABLE;
2783 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2784
2785 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2786 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2787}
2788
48654521
AD		 2789static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2790{
2791 struct ixgbe_hw *hw = &adapter->hw;
2792 int p;
2793
2794 /* PSRTYPE must be initialized in non 82598 adapters */
2795 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2796 IXGBE_PSRTYPE_UDPHDR |
2797 IXGBE_PSRTYPE_IPV4HDR |
48654521 2798 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2799 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2800
2801 if (hw->mac.type == ixgbe_mac_82598EB)
2802 return;
2803
2804 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2805 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2806
2807 for (p = 0; p < adapter->num_rx_pools; p++)
2808 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2809 psrtype);
2810}
2811
f5b4a52e
AD		 2812static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2813{
2814 struct ixgbe_hw *hw = &adapter->hw;
2815 u32 gcr_ext;
2816 u32 vt_reg_bits;
2817 u32 reg_offset, vf_shift;
2818 u32 vmdctl;
2819
2820 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2821 return;
2822
2823 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2824 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2825 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2826 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2827
2828 vf_shift = adapter->num_vfs % 32;
2829 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2830
2831 /* Enable only the PF's pool for Tx/Rx */
2832 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2833 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2834 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2835 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2836 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2837
2838 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2839 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2840
2841 /*
2842 * Set up VF register offsets for selected VT Mode,
2843 * i.e. 32 or 64 VFs for SR-IOV
2844 */
2845 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2846 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2847 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2848 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2849
2850 /* enable Tx loopback for VF/PF communication */
2851 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 2852 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 2853 hw->mac.ops.set_mac_anti_spoofing(hw,
2854 (adapter->antispoofing_enabled =
2855 (adapter->num_vfs != 0)),
a985b6c3 2856 adapter->num_vfs);
f5b4a52e
AD		 2857}
2858
477de6ed 2859static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2860{
9a799d71
AK		 2861 struct ixgbe_hw *hw = &adapter->hw;
2862 struct net_device *netdev = adapter->netdev;
2863 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2864 int rx_buf_len;
477de6ed
AD		 2865 struct ixgbe_ring *rx_ring;
2866 int i;
2867 u32 mhadd, hlreg0;
48654521 2868
9a799d71 2869 /* Decide whether to use packet split mode or not */
a124339a
DS		 2870 /* On by default */
2871 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2872
1cdd1ec8 2873 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 2874 if (adapter->num_vfs)
2875 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2876
2877 /* Disable packet split due to 82599 erratum #45 */
2878 if (hw->mac.type == ixgbe_mac_82599EB)
2879 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 2880
63f39bd1 2881#ifdef IXGBE_FCOE
477de6ed
AD		 2882 /* adjust max frame to be able to do baby jumbo for FCoE */
2883 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2884 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2885 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2886
477de6ed
AD		 2887#endif /* IXGBE_FCOE */
2888 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2889 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2890 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2891 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2892
2893 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2894 }
2895
919e78a6
AD		 2896 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2897 max_frame += VLAN_HLEN;
2898
2899 /* Set the RX buffer length according to the mode */
2900 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2901 rx_buf_len = IXGBE_RX_HDR_SIZE;
2902 } else {
2903 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2904 (netdev->mtu <= ETH_DATA_LEN))
2905 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2906 /*
2907 * Make best use of allocation by using all but 1K of a
2908 * power of 2 allocation that will be used for skb->head.
2909 */
2910 else if (max_frame <= IXGBE_RXBUFFER_3K)
2911 rx_buf_len = IXGBE_RXBUFFER_3K;
2912 else if (max_frame <= IXGBE_RXBUFFER_7K)
2913 rx_buf_len = IXGBE_RXBUFFER_7K;
2914 else if (max_frame <= IXGBE_RXBUFFER_15K)
2915 rx_buf_len = IXGBE_RXBUFFER_15K;
2916 else
2917 rx_buf_len = IXGBE_MAX_RXBUFFER;
2918 }
2919
477de6ed
AD		 2920 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2921 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2922 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2923 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2924
0cefafad
JB		 2925 /*
2926 * Setup the HW Rx Head and Tail Descriptor Pointers and
2927 * the Base and Length of the Rx Descriptor Ring
2928 */
9a799d71 2929 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2930 rx_ring = adapter->rx_ring[i];
a6616b42 2931 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2932
6e455b89 2933 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 2934 set_ring_ps_enabled(rx_ring);
2935 else
2936 clear_ring_ps_enabled(rx_ring);
2937
2938 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2939 set_ring_rsc_enabled(rx_ring);
1b3ff02e 2940 else
7d637bcc 2941 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 2942
63f39bd1 2943#ifdef IXGBE_FCOE
e8e9f696 2944 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2945 struct ixgbe_ring_feature *f;
2946 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 2947 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 2948 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 2949 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2950 rx_ring->rx_buf_len =
e8e9f696 2951 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 2952 } else if (!ring_is_rsc_enabled(rx_ring) &&
2953 !ring_is_ps_enabled(rx_ring)) {
2954 rx_ring->rx_buf_len =
2955 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2956 }
63f39bd1 2957 }
63f39bd1 2958#endif /* IXGBE_FCOE */
477de6ed 2959 }
477de6ed
AD		 2960}
2961
7367096a
AD		 2962static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2963{
2964 struct ixgbe_hw *hw = &adapter->hw;
2965 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2966
2967 switch (hw->mac.type) {
2968 case ixgbe_mac_82598EB:
2969 /*
2970 * For VMDq support of different descriptor types or
2971 * buffer sizes through the use of multiple SRRCTL
2972 * registers, RDRXCTL.MVMEN must be set to 1
2973 *
2974 * also, the manual doesn't mention it clearly but DCA hints
2975 * will only use queue 0's tags unless this bit is set. Side
2976 * effects of setting this bit are only that SRRCTL must be
2977 * fully programmed [0..15]
2978 */
2979 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2980 break;
2981 case ixgbe_mac_82599EB:
b93a2226 2982 case ixgbe_mac_X540:
7367096a
AD		 2983 /* Disable RSC for ACK packets */
2984 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2985 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2986 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2987 /* hardware requires some bits to be set by default */
2988 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2989 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2990 break;
2991 default:
2992 /* We should do nothing since we don't know this hardware */
2993 return;
2994 }
2995
2996 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2997}
2998
477de6ed
AD		 2999/**
3000 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3001 * @adapter: board private structure
3002 *
3003 * Configure the Rx unit of the MAC after a reset.
3004 **/
3005static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3006{
3007 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3008 int i;
3009 u32 rxctrl;
477de6ed
AD		 3010
3011 /* disable receives while setting up the descriptors */
3012 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3013 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3014
3015 ixgbe_setup_psrtype(adapter);
7367096a 3016 ixgbe_setup_rdrxctl(adapter);
477de6ed 3017
9e10e045 3018 /* Program registers for the distribution of queues */
f5b4a52e 3019 ixgbe_setup_mrqc(adapter);
f5b4a52e 3020
9e10e045
AD		 3021 ixgbe_set_uta(adapter);
3022
477de6ed
AD		 3023 /* set_rx_buffer_len must be called before ring initialization */
3024 ixgbe_set_rx_buffer_len(adapter);
3025
3026 /*
3027 * Setup the HW Rx Head and Tail Descriptor Pointers and
3028 * the Base and Length of the Rx Descriptor Ring
3029 */
9e10e045
AD		 3030 for (i = 0; i < adapter->num_rx_queues; i++)
3031 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3032
9e10e045
AD		 3033 /* disable drop enable for 82598 parts */
3034 if (hw->mac.type == ixgbe_mac_82598EB)
3035 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3036
3037 /* enable all receives */
3038 rxctrl |= IXGBE_RXCTRL_RXEN;
3039 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3040}
3041
068c89b0
DS		 3042static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3043{
3044 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3045 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3046 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3047
3048 /* add VID to filter table */
1ada1b1b 3049 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3050 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3051}
3052
3053static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3054{
3055 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3056 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3057 int pool_ndx = adapter->num_vfs;
068c89b0 3058
068c89b0 3059 /* remove VID from filter table */
1ada1b1b 3060 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3061 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3062}
3063
5f6c0181
JB		 3064/**
3065 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3066 * @adapter: driver data
3067 */
3068static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3069{
3070 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3071 u32 vlnctrl;
3072
3073 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3074 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3075 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3076}
3077
3078/**
3079 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3080 * @adapter: driver data
3081 */
3082static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3083{
3084 struct ixgbe_hw *hw = &adapter->hw;
3085 u32 vlnctrl;
3086
3087 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3088 vlnctrl |= IXGBE_VLNCTRL_VFE;
3089 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3090 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3091}
3092
3093/**
3094 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3095 * @adapter: driver data
3096 */
3097static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3098{
3099 struct ixgbe_hw *hw = &adapter->hw;
3100 u32 vlnctrl;
5f6c0181
JB		 3101 int i, j;
3102
3103 switch (hw->mac.type) {
3104 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3105 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3106 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3107 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3108 break;
3109 case ixgbe_mac_82599EB:
b93a2226 3110 case ixgbe_mac_X540:
5f6c0181
JB		 3111 for (i = 0; i < adapter->num_rx_queues; i++) {
3112 j = adapter->rx_ring[i]->reg_idx;
3113 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3114 vlnctrl &= ~IXGBE_RXDCTL_VME;
3115 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3116 }
3117 break;
3118 default:
3119 break;
3120 }
3121}
3122
3123/**
f62bbb5e 3124 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3125 * @adapter: driver data
3126 */
f62bbb5e 3127static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3128{
3129 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3130 u32 vlnctrl;
5f6c0181
JB		 3131 int i, j;
3132
3133 switch (hw->mac.type) {
3134 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3135 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3136 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3137 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3138 break;
3139 case ixgbe_mac_82599EB:
b93a2226 3140 case ixgbe_mac_X540:
5f6c0181
JB		 3141 for (i = 0; i < adapter->num_rx_queues; i++) {
3142 j = adapter->rx_ring[i]->reg_idx;
3143 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3144 vlnctrl |= IXGBE_RXDCTL_VME;
3145 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3146 }
3147 break;
3148 default:
3149 break;
3150 }
3151}
3152
9a799d71
AK		 3153static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3154{
f62bbb5e 3155 u16 vid;
9a799d71 3156
f62bbb5e
JG		 3157 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3158
3159 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3160 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3161}
3162
2850062a
AD		 3163/**
3164 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3165 * @netdev: network interface device structure
3166 *
3167 * Writes unicast address list to the RAR table.
3168 * Returns: -ENOMEM on failure/insufficient address space
3169 * 0 on no addresses written
3170 * X on writing X addresses to the RAR table
3171 **/
3172static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3173{
3174 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3175 struct ixgbe_hw *hw = &adapter->hw;
3176 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3177 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3178 int count = 0;
3179
3180 /* return ENOMEM indicating insufficient memory for addresses */
3181 if (netdev_uc_count(netdev) > rar_entries)
3182 return -ENOMEM;
3183
3184 if (!netdev_uc_empty(netdev) && rar_entries) {
3185 struct netdev_hw_addr *ha;
3186 /* return error if we do not support writing to RAR table */
3187 if (!hw->mac.ops.set_rar)
3188 return -ENOMEM;
3189
3190 netdev_for_each_uc_addr(ha, netdev) {
3191 if (!rar_entries)
3192 break;
3193 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3194 vfn, IXGBE_RAH_AV);
3195 count++;
3196 }
3197 }
3198 /* write the addresses in reverse order to avoid write combining */
3199 for (; rar_entries > 0 ; rar_entries--)
3200 hw->mac.ops.clear_rar(hw, rar_entries);
3201
3202 return count;
3203}
3204
9a799d71 3205/**
2c5645cf 3206 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3207 * @netdev: network interface device structure
3208 *
2c5645cf
CL		 3209 * The set_rx_method entry point is called whenever the unicast/multicast
3210 * address list or the network interface flags are updated. This routine is
3211 * responsible for configuring the hardware for proper unicast, multicast and
3212 * promiscuous mode.
9a799d71 3213 **/
7f870475 3214void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3215{
3216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3217 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3218 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3219 int count;
9a799d71
AK		 3220
3221 /* Check for Promiscuous and All Multicast modes */
3222
3223 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3224
f5dc442b
AD		 3225 /* set all bits that we expect to always be set */
3226 fctrl |= IXGBE_FCTRL_BAM;
3227 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3228 fctrl |= IXGBE_FCTRL_PMCF;
3229
2850062a
AD		 3230 /* clear the bits we are changing the status of */
3231 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3232
9a799d71 3233 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3234 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3235 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3236 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3237 /* don't hardware filter vlans in promisc mode */
3238 ixgbe_vlan_filter_disable(adapter);
9a799d71 3239 } else {
746b9f02
PM		 3240 if (netdev->flags & IFF_ALLMULTI) {
3241 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3242 vmolr |= IXGBE_VMOLR_MPE;
3243 } else {
3244 /*
3245 * Write addresses to the MTA, if the attempt fails
25985edc 3246 * then we should just turn on promiscuous mode so
2850062a
AD		 3247 * that we can at least receive multicast traffic
3248 */
3249 hw->mac.ops.update_mc_addr_list(hw, netdev);
3250 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3251 }
5f6c0181 3252 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3253 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3254 /*
3255 * Write addresses to available RAR registers, if there is not
3256 * sufficient space to store all the addresses then enable
25985edc 3257 * unicast promiscuous mode
2850062a
AD		 3258 */
3259 count = ixgbe_write_uc_addr_list(netdev);
3260 if (count < 0) {
3261 fctrl |= IXGBE_FCTRL_UPE;
3262 vmolr |= IXGBE_VMOLR_ROPE;
3263 }
9a799d71
AK		 3264 }
3265
2850062a 3266 if (adapter->num_vfs) {
1cdd1ec8 3267 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3268 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3269 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3270 IXGBE_VMOLR_ROPE);
3271 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3272 }
3273
3274 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3275
3276 if (netdev->features & NETIF_F_HW_VLAN_RX)
3277 ixgbe_vlan_strip_enable(adapter);
3278 else
3279 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3280}
3281
021230d4
AV		 3282static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3283{
3284 int q_idx;
3285 struct ixgbe_q_vector *q_vector;
3286 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3287
3288 /* legacy and MSI only use one vector */
3289 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3290 q_vectors = 1;
3291
3292 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3293 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3294 napi_enable(&q_vector->napi);
021230d4
AV		 3295 }
3296}
3297
3298static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3299{
3300 int q_idx;
3301 struct ixgbe_q_vector *q_vector;
3302 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3303
3304 /* legacy and MSI only use one vector */
3305 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3306 q_vectors = 1;
3307
3308 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3309 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3310 napi_disable(&q_vector->napi);
3311 }
3312}
3313
7a6b6f51 3314#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3315/*
3316 * ixgbe_configure_dcb - Configure DCB hardware
3317 * @adapter: ixgbe adapter struct
3318 *
3319 * This is called by the driver on open to configure the DCB hardware.
3320 * This is also called by the gennetlink interface when reconfiguring
3321 * the DCB state.
3322 */
3323static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3324{
3325 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3326 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3327
67ebd791
AD		 3328 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3329 if (hw->mac.type == ixgbe_mac_82598EB)
3330 netif_set_gso_max_size(adapter->netdev, 65536);
3331 return;
3332 }
3333
3334 if (hw->mac.type == ixgbe_mac_82598EB)
3335 netif_set_gso_max_size(adapter->netdev, 32768);
3336
2f90b865 3337
2f90b865 3338 /* Enable VLAN tag insert/strip */
f62bbb5e 3339 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3340
2f90b865 3341 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3342
3343 /* reconfigure the hardware */
6f70f6ac 3344 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
971060b1 3345#ifdef IXGBE_FCOE
c27931da
JF		 3346 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3347 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3348#endif
3349 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3350 DCB_TX_CONFIG);
3351 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3352 DCB_RX_CONFIG);
3353 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3354 } else {
3355 struct net_device *dev = adapter->netdev;
3356
4c09f3a0
JF		 3357 if (adapter->ixgbe_ieee_ets) {
3358 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
3359 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3360
3361 ixgbe_dcb_hw_ets(&adapter->hw, ets, max_frame);
3362 }
3363
3364 if (adapter->ixgbe_ieee_pfc) {
3365 struct ieee_pfc *pfc = adapter->ixgbe_ieee_pfc;
32701dc2 3366 u8 *prio_tc = adapter->ixgbe_ieee_ets->prio_tc;
4c09f3a0 3367
32701dc2
JF		 3368 ixgbe_dcb_hw_pfc_config(&adapter->hw, pfc->pfc_en,
3369 prio_tc);
4c09f3a0 3370 }
c27931da 3371 }
8187cd48
JF		 3372
3373 /* Enable RSS Hash per TC */
3374 if (hw->mac.type != ixgbe_mac_82598EB) {
3375 int i;
3376 u32 reg = 0;
3377
3378 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3379 u8 msb = 0;
3380 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3381
3382 while (cnt >>= 1)
3383 msb++;
3384
3385 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3386 }
3387 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3388 }
2f90b865 3389}
9da712d2
JF		 3390#endif
3391
3392/* Additional bittime to account for IXGBE framing */
3393#define IXGBE_ETH_FRAMING 20
3394
3395/*
3396 * ixgbe_hpbthresh - calculate high water mark for flow control
3397 *
3398 * @adapter: board private structure to calculate for
3399 * @pb - packet buffer to calculate
3400 */
3401static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3402{
3403 struct ixgbe_hw *hw = &adapter->hw;
3404 struct net_device *dev = adapter->netdev;
3405 int link, tc, kb, marker;
3406 u32 dv_id, rx_pba;
3407
3408 /* Calculate max LAN frame size */
3409 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3410
3411#ifdef IXGBE_FCOE
3412 /* FCoE traffic class uses FCOE jumbo frames */
3413 if (dev->features & NETIF_F_FCOE_MTU) {
3414 int fcoe_pb = 0;
2f90b865 3415
9da712d2
JF		 3416#ifdef CONFIG_IXGBE_DCB
3417 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3418
3419#endif
3420 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3421 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3422 }
2f90b865 3423#endif
80605c65 3424
9da712d2
JF		 3425 /* Calculate delay value for device */
3426 switch (hw->mac.type) {
3427 case ixgbe_mac_X540:
3428 dv_id = IXGBE_DV_X540(link, tc);
3429 break;
3430 default:
3431 dv_id = IXGBE_DV(link, tc);
3432 break;
3433 }
3434
3435 /* Loopback switch introduces additional latency */
3436 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3437 dv_id += IXGBE_B2BT(tc);
3438
3439 /* Delay value is calculated in bit times convert to KB */
3440 kb = IXGBE_BT2KB(dv_id);
3441 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3442
3443 marker = rx_pba - kb;
3444
3445 /* It is possible that the packet buffer is not large enough
3446 * to provide required headroom. In this case throw an error
3447 * to user and a do the best we can.
3448 */
3449 if (marker < 0) {
3450 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3451 "headroom to support flow control."
3452 "Decrease MTU or number of traffic classes\n", pb);
3453 marker = tc + 1;
3454 }
3455
3456 return marker;
3457}
3458
3459/*
3460 * ixgbe_lpbthresh - calculate low water mark for for flow control
3461 *
3462 * @adapter: board private structure to calculate for
3463 * @pb - packet buffer to calculate
3464 */
3465static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3466{
3467 struct ixgbe_hw *hw = &adapter->hw;
3468 struct net_device *dev = adapter->netdev;
3469 int tc;
3470 u32 dv_id;
3471
3472 /* Calculate max LAN frame size */
3473 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3474
3475 /* Calculate delay value for device */
3476 switch (hw->mac.type) {
3477 case ixgbe_mac_X540:
3478 dv_id = IXGBE_LOW_DV_X540(tc);
3479 break;
3480 default:
3481 dv_id = IXGBE_LOW_DV(tc);
3482 break;
3483 }
3484
3485 /* Delay value is calculated in bit times convert to KB */
3486 return IXGBE_BT2KB(dv_id);
3487}
3488
3489/*
3490 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3491 */
3492static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3493{
3494 struct ixgbe_hw *hw = &adapter->hw;
3495 int num_tc = netdev_get_num_tc(adapter->netdev);
3496 int i;
3497
3498 if (!num_tc)
3499 num_tc = 1;
3500
3501 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3502
3503 for (i = 0; i < num_tc; i++) {
3504 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3505
3506 /* Low water marks must not be larger than high water marks */
3507 if (hw->fc.low_water > hw->fc.high_water[i])
3508 hw->fc.low_water = 0;
3509 }
3510}
3511
80605c65
JF		 3512static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3513{
80605c65 3514 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3515 int hdrm;
3516 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3517
3518 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3519 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3520 hdrm = 32 << adapter->fdir_pballoc;
3521 else
3522 hdrm = 0;
80605c65 3523
f7e1027f 3524 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3525 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3526}
3527
e4911d57
AD		 3528static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3529{
3530 struct ixgbe_hw *hw = &adapter->hw;
3531 struct hlist_node *node, *node2;
3532 struct ixgbe_fdir_filter *filter;
3533
3534 spin_lock(&adapter->fdir_perfect_lock);
3535
3536 if (!hlist_empty(&adapter->fdir_filter_list))
3537 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3538
3539 hlist_for_each_entry_safe(filter, node, node2,
3540 &adapter->fdir_filter_list, fdir_node) {
3541 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3542 &filter->filter,
3543 filter->sw_idx,
3544 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3545 IXGBE_FDIR_DROP_QUEUE :
3546 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3547 }
3548
3549 spin_unlock(&adapter->fdir_perfect_lock);
3550}
3551
9a799d71
AK		 3552static void ixgbe_configure(struct ixgbe_adapter *adapter)
3553{
80605c65 3554 ixgbe_configure_pb(adapter);
7a6b6f51 3555#ifdef CONFIG_IXGBE_DCB
67ebd791 3556 ixgbe_configure_dcb(adapter);
2f90b865 3557#endif
9a799d71 3558
4c1d7b4b 3559 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3560 ixgbe_restore_vlan(adapter);
3561
eacd73f7
YZ		 3562#ifdef IXGBE_FCOE
3563 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3564 ixgbe_configure_fcoe(adapter);
3565
3566#endif /* IXGBE_FCOE */
c4cf55e5 3567 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3568 ixgbe_init_fdir_signature_82599(&adapter->hw,
3569 adapter->fdir_pballoc);
e4911d57
AD		 3570 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3571 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3572 adapter->fdir_pballoc);
3573 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3574 }
4c1d7b4b 3575
933d41f1 3576 ixgbe_configure_virtualization(adapter);
c4cf55e5 3577
9a799d71
AK		 3578 ixgbe_configure_tx(adapter);
3579 ixgbe_configure_rx(adapter);
9a799d71
AK		 3580}
3581
e8e26350
PW		 3582static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3583{
3584 switch (hw->phy.type) {
3585 case ixgbe_phy_sfp_avago:
3586 case ixgbe_phy_sfp_ftl:
3587 case ixgbe_phy_sfp_intel:
3588 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3589 case ixgbe_phy_sfp_passive_tyco:
3590 case ixgbe_phy_sfp_passive_unknown:
3591 case ixgbe_phy_sfp_active_unknown:
3592 case ixgbe_phy_sfp_ftl_active:
e8e26350 3593 return true;
8917b447
AD		 3594 case ixgbe_phy_nl:
3595 if (hw->mac.type == ixgbe_mac_82598EB)
3596 return true;
e8e26350
PW		 3597 default:
3598 return false;
3599 }
3600}
3601
0ecc061d 3602/**
e8e26350
PW		 3603 * ixgbe_sfp_link_config - set up SFP+ link
3604 * @adapter: pointer to private adapter struct
3605 **/
3606static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3607{
7086400d
AD		 3608 /*
3609 * We are assuming the worst case scenerio here, and that
3610 * is that an SFP was inserted/removed after the reset
3611 * but before SFP detection was enabled. As such the best
3612 * solution is to just start searching as soon as we start
3613 */
3614 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3615 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3616
7086400d 3617 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3618}
3619
3620/**
3621 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3622 * @hw: pointer to private hardware struct
3623 *
3624 * Returns 0 on success, negative on failure
3625 **/
e8e26350 3626static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3627{
3628 u32 autoneg;
8620a103 3629 bool negotiation, link_up = false;
0ecc061d
PWJ		 3630 u32 ret = IXGBE_ERR_LINK_SETUP;
3631
3632 if (hw->mac.ops.check_link)
3633 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3634
3635 if (ret)
3636 goto link_cfg_out;
3637
0b0c2b31
ET		 3638 autoneg = hw->phy.autoneg_advertised;
3639 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3640 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3641 &negotiation);
0ecc061d
PWJ		 3642 if (ret)
3643 goto link_cfg_out;
3644
8620a103
MC		 3645 if (hw->mac.ops.setup_link)
3646 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3647link_cfg_out:
3648 return ret;
3649}
3650
a34bcfff 3651static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3652{
9a799d71 3653 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3654 u32 gpie = 0;
9a799d71 3655
9b471446 3656 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3657 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3658 IXGBE_GPIE_OCD;
3659 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3660 /*
3661 * use EIAM to auto-mask when MSI-X interrupt is asserted
3662 * this saves a register write for every interrupt
3663 */
3664 switch (hw->mac.type) {
3665 case ixgbe_mac_82598EB:
3666 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3667 break;
9b471446 3668 case ixgbe_mac_82599EB:
b93a2226
DS		 3669 case ixgbe_mac_X540:
3670 default:
9b471446
JB		 3671 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3672 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3673 break;
3674 }
3675 } else {
021230d4
AV		 3676 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3677 * specifically only auto mask tx and rx interrupts */
3678 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3679 }
9a799d71 3680
a34bcfff
AD		 3681 /* XXX: to interrupt immediately for EICS writes, enable this */
3682 /* gpie |= IXGBE_GPIE_EIMEN; */
3683
3684 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3685 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3686 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3687 }
3688
5fdd31f9 3689 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3690 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3691 switch (adapter->hw.mac.type) {
3692 case ixgbe_mac_82599EB:
3693 gpie |= IXGBE_SDP0_GPIEN;
3694 break;
3695 case ixgbe_mac_X540:
3696 gpie |= IXGBE_EIMS_TS;
3697 break;
3698 default:
3699 break;
3700 }
3701 }
5fdd31f9 3702
a34bcfff
AD		 3703 /* Enable fan failure interrupt */
3704 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3705 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3706
2698b208 3707 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3708 gpie |= IXGBE_SDP1_GPIEN;
3709 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3710 }
a34bcfff
AD		 3711
3712 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3713}
3714
c7ccde0f 3715static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3716{
3717 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3718 int err;
a34bcfff
AD		 3719 u32 ctrl_ext;
3720
3721 ixgbe_get_hw_control(adapter);
3722 ixgbe_setup_gpie(adapter);
e8e26350 3723
9a799d71
AK		 3724 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3725 ixgbe_configure_msix(adapter);
3726 else
3727 ixgbe_configure_msi_and_legacy(adapter);
3728
c6ecf39a
DS		 3729 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3730 if (hw->mac.ops.enable_tx_laser &&
3731 ((hw->phy.multispeed_fiber) ||
9f911707 3732 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3733 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3734 hw->mac.ops.enable_tx_laser(hw);
3735
9a799d71 3736 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3737 ixgbe_napi_enable_all(adapter);
3738
73c4b7cd
AD		 3739 if (ixgbe_is_sfp(hw)) {
3740 ixgbe_sfp_link_config(adapter);
3741 } else {
3742 err = ixgbe_non_sfp_link_config(hw);
3743 if (err)
3744 e_err(probe, "link_config FAILED %d\n", err);
3745 }
3746
021230d4
AV		 3747 /* clear any pending interrupts, may auto mask */
3748 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3749 ixgbe_irq_enable(adapter, true, true);
9a799d71 3750
bf069c97
DS		 3751 /*
3752 * If this adapter has a fan, check to see if we had a failure
3753 * before we enabled the interrupt.
3754 */
3755 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3756 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3757 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3758 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3759 }
3760
1da100bb 3761 /* enable transmits */
477de6ed 3762 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3763
9a799d71
AK		 3764 /* bring the link up in the watchdog, this could race with our first
3765 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3766 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3767 adapter->link_check_timeout = jiffies;
7086400d 3768 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3769
3770 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3771 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3772 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3773 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3774}
3775
d4f80882
AV		 3776void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3777{
3778 WARN_ON(in_interrupt());
7086400d
AD		 3779 /* put off any impending NetWatchDogTimeout */
3780 adapter->netdev->trans_start = jiffies;
3781
d4f80882 3782 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3783 usleep_range(1000, 2000);
d4f80882 3784 ixgbe_down(adapter);
5809a1ae
GR		 3785 /*
3786 * If SR-IOV enabled then wait a bit before bringing the adapter
3787 * back up to give the VFs time to respond to the reset. The
3788 * two second wait is based upon the watchdog timer cycle in
3789 * the VF driver.
3790 */
3791 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3792 msleep(2000);
d4f80882
AV		 3793 ixgbe_up(adapter);
3794 clear_bit(__IXGBE_RESETTING, &adapter->state);
3795}
3796
c7ccde0f 3797void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 3798{
3799 /* hardware has been reset, we need to reload some things */
3800 ixgbe_configure(adapter);
3801
c7ccde0f 3802 ixgbe_up_complete(adapter);
9a799d71
AK		 3803}
3804
3805void ixgbe_reset(struct ixgbe_adapter *adapter)
3806{
c44ade9e 3807 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3808 int err;
3809
7086400d
AD		 3810 /* lock SFP init bit to prevent race conditions with the watchdog */
3811 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3812 usleep_range(1000, 2000);
3813
3814 /* clear all SFP and link config related flags while holding SFP_INIT */
3815 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3816 IXGBE_FLAG2_SFP_NEEDS_RESET);
3817 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3818
8ca783ab 3819 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3820 switch (err) {
3821 case 0:
3822 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3823 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3824 break;
3825 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3826 e_dev_err("master disable timed out\n");
da4dd0f7 3827 break;
794caeb2
PWJ		 3828 case IXGBE_ERR_EEPROM_VERSION:
3829 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3830 e_dev_warn("This device is a pre-production adapter/LOM. "
3831 "Please be aware there may be issuesassociated with "
3832 "your hardware. If you are experiencing problems "
3833 "please contact your Intel or hardware "
3834 "representative who provided you with this "
3835 "hardware.\n");
794caeb2 3836 break;
da4dd0f7 3837 default:
849c4542 3838 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3839 }
9a799d71 3840
7086400d
AD		 3841 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3842
9a799d71 3843 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3844 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3845 IXGBE_RAH_AV);
9a799d71
AK		 3846}
3847
9a799d71
AK		 3848/**
3849 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3850 * @rx_ring: ring to free buffers from
3851 **/
b6ec895e 3852static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3853{
b6ec895e 3854 struct device *dev = rx_ring->dev;
9a799d71 3855 unsigned long size;
b6ec895e 3856 u16 i;
9a799d71 3857
84418e3b
AD		 3858 /* ring already cleared, nothing to do */
3859 if (!rx_ring->rx_buffer_info)
3860 return;
9a799d71 3861
84418e3b 3862 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3863 for (i = 0; i < rx_ring->count; i++) {
3864 struct ixgbe_rx_buffer *rx_buffer_info;
3865
3866 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3867 if (rx_buffer_info->dma) {
b6ec895e 3868 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3869 rx_ring->rx_buf_len,
1b507730 3870 DMA_FROM_DEVICE);
9a799d71
AK		 3871 rx_buffer_info->dma = 0;
3872 }
3873 if (rx_buffer_info->skb) {
f8212f97 3874 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3875 rx_buffer_info->skb = NULL;
f8212f97
AD		 3876 do {
3877 struct sk_buff *this = skb;
e8171aaa 3878 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3879 dma_unmap_single(dev,
1b507730 3880 IXGBE_RSC_CB(this)->dma,
e8e9f696 3881 rx_ring->rx_buf_len,
1b507730 3882 DMA_FROM_DEVICE);
fd3686a8 3883 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3884 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3885 }
f8212f97
AD		 3886 skb = skb->prev;
3887 dev_kfree_skb(this);
3888 } while (skb);
9a799d71
AK		 3889 }
3890 if (!rx_buffer_info->page)
3891 continue;
4f57ca6e 3892 if (rx_buffer_info->page_dma) {
b6ec895e 3893 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3894 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3895 rx_buffer_info->page_dma = 0;
3896 }
9a799d71
AK		 3897 put_page(rx_buffer_info->page);
3898 rx_buffer_info->page = NULL;
762f4c57 3899 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3900 }
3901
3902 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3903 memset(rx_ring->rx_buffer_info, 0, size);
3904
3905 /* Zero out the descriptor ring */
3906 memset(rx_ring->desc, 0, rx_ring->size);
3907
3908 rx_ring->next_to_clean = 0;
3909 rx_ring->next_to_use = 0;
9a799d71
AK		 3910}
3911
3912/**
3913 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3914 * @tx_ring: ring to be cleaned
3915 **/
b6ec895e 3916static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3917{
3918 struct ixgbe_tx_buffer *tx_buffer_info;
3919 unsigned long size;
b6ec895e 3920 u16 i;
9a799d71 3921
84418e3b
AD		 3922 /* ring already cleared, nothing to do */
3923 if (!tx_ring->tx_buffer_info)
3924 return;
9a799d71 3925
84418e3b 3926 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3927 for (i = 0; i < tx_ring->count; i++) {
3928 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3929 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3930 }
3931
3932 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3933 memset(tx_ring->tx_buffer_info, 0, size);
3934
3935 /* Zero out the descriptor ring */
3936 memset(tx_ring->desc, 0, tx_ring->size);
3937
3938 tx_ring->next_to_use = 0;
3939 tx_ring->next_to_clean = 0;
9a799d71
AK		 3940}
3941
3942/**
021230d4 3943 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3944 * @adapter: board private structure
3945 **/
021230d4 3946static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3947{
3948 int i;
3949
021230d4 3950 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3951 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3952}
3953
3954/**
021230d4 3955 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3956 * @adapter: board private structure
3957 **/
021230d4 3958static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3959{
3960 int i;
3961
021230d4 3962 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3963 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3964}
3965
e4911d57
AD		 3966static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3967{
3968 struct hlist_node *node, *node2;
3969 struct ixgbe_fdir_filter *filter;
3970
3971 spin_lock(&adapter->fdir_perfect_lock);
3972
3973 hlist_for_each_entry_safe(filter, node, node2,
3974 &adapter->fdir_filter_list, fdir_node) {
3975 hlist_del(&filter->fdir_node);
3976 kfree(filter);
3977 }
3978 adapter->fdir_filter_count = 0;
3979
3980 spin_unlock(&adapter->fdir_perfect_lock);
3981}
3982
9a799d71
AK		 3983void ixgbe_down(struct ixgbe_adapter *adapter)
3984{
3985 struct net_device *netdev = adapter->netdev;
7f821875 3986 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3987 u32 rxctrl;
bf29ee6c 3988 int i;
9a799d71
AK		 3989
3990 /* signal that we are down to the interrupt handler */
3991 set_bit(__IXGBE_DOWN, &adapter->state);
3992
3993 /* disable receives */
7f821875
JB		 3994 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3995 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3996
2d39d576
YZ		 3997 /* disable all enabled rx queues */
3998 for (i = 0; i < adapter->num_rx_queues; i++)
3999 /* this call also flushes the previous write */
4000 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4001
032b4325 4002 usleep_range(10000, 20000);
9a799d71 4003
7f821875
JB		 4004 netif_tx_stop_all_queues(netdev);
4005
7086400d 4006 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4007 netif_carrier_off(netdev);
4008 netif_tx_disable(netdev);
4009
4010 ixgbe_irq_disable(adapter);
4011
4012 ixgbe_napi_disable_all(adapter);
4013
d034acf1
AD		 4014 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4015 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4016 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4017
4018 del_timer_sync(&adapter->service_timer);
4019
34cecbbf 4020 if (adapter->num_vfs) {
8e34d1aa
AD		 4021 /* Clear EITR Select mapping */
4022 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4023
4024 /* Mark all the VFs as inactive */
4025 for (i = 0 ; i < adapter->num_vfs; i++)
4026 adapter->vfinfo[i].clear_to_send = 0;
34cecbbf 4027
34cecbbf
AD		 4028 /* ping all the active vfs to let them know we are going down */
4029 ixgbe_ping_all_vfs(adapter);
4030
4031 /* Disable all VFTE/VFRE TX/RX */
4032 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4033 }
4034
7f821875
JB		 4035 /* disable transmits in the hardware now that interrupts are off */
4036 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4037 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4038 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4039 }
34cecbbf
AD		 4040
4041 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4042 switch (hw->mac.type) {
4043 case ixgbe_mac_82599EB:
b93a2226 4044 case ixgbe_mac_X540:
88512539 4045 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4046 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4047 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4048 break;
4049 default:
4050 break;
4051 }
7f821875 4052
6f4a0e45
PL		 4053 if (!pci_channel_offline(adapter->pdev))
4054 ixgbe_reset(adapter);
c6ecf39a
DS		 4055
4056 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4057 if (hw->mac.ops.disable_tx_laser &&
4058 ((hw->phy.multispeed_fiber) ||
9f911707 4059 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4060 (hw->mac.type == ixgbe_mac_82599EB))))
4061 hw->mac.ops.disable_tx_laser(hw);
4062
9a799d71
AK		 4063 ixgbe_clean_all_tx_rings(adapter);
4064 ixgbe_clean_all_rx_rings(adapter);
4065
5dd2d332 4066#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4067 /* since we reset the hardware DCA settings were cleared */
e35ec126 4068 ixgbe_setup_dca(adapter);
96b0e0f6 4069#endif
9a799d71
AK		 4070}
4071
9a799d71 4072/**
021230d4
AV		 4073 * ixgbe_poll - NAPI Rx polling callback
4074 * @napi: structure for representing this polling device
4075 * @budget: how many packets driver is allowed to clean
4076 *
4077 * This function is used for legacy and MSI, NAPI mode
9a799d71 4078 **/
021230d4 4079static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4080{
9a1a69ad 4081 struct ixgbe_q_vector *q_vector =
e8e9f696 4082 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4083 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4084 struct ixgbe_ring *ring;
4085 int per_ring_budget;
4086 bool clean_complete = true;
9a799d71 4087
5dd2d332 4088#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4089 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4090 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4091#endif
4092
4ff7fb12
AD		 4093 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4094 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4095
4ff7fb12
AD		 4096 /* attempt to distribute budget to each queue fairly, but don't allow
4097 * the budget to go below 1 because we'll exit polling */
4098 if (q_vector->rx.count > 1)
4099 per_ring_budget = max(budget/q_vector->rx.count, 1);
4100 else
4101 per_ring_budget = budget;
d2c7ddd6 4102
4ff7fb12
AD		 4103 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4104 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4105 per_ring_budget);
4106
4107 /* If all work not completed, return budget and keep polling */
4108 if (!clean_complete)
4109 return budget;
4110
4111 /* all work done, exit the polling mode */
4112 napi_complete(napi);
4113 if (adapter->rx_itr_setting & 1)
4114 ixgbe_set_itr(q_vector);
4115 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4116 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4117
4118 return 0;
9a799d71
AK		 4119}
4120
4121/**
4122 * ixgbe_tx_timeout - Respond to a Tx Hang
4123 * @netdev: network interface device structure
4124 **/
4125static void ixgbe_tx_timeout(struct net_device *netdev)
4126{
4127 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4128
4129 /* Do the reset outside of interrupt context */
c83c6cbd 4130 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4131}
4132
4df10466
JB		 4133/**
4134 * ixgbe_set_rss_queues: Allocate queues for RSS
4135 * @adapter: board private structure to initialize
4136 *
4137 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4138 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4139 *
4140 **/
bc97114d
PWJ		 4141static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4142{
4143 bool ret = false;
0cefafad 4144 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4145
4146 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4147 f->mask = 0xF;
4148 adapter->num_rx_queues = f->indices;
4149 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4150 ret = true;
4151 } else {
bc97114d 4152 ret = false;
b9804972
JB		 4153 }
4154
bc97114d
PWJ		 4155 return ret;
4156}
4157
c4cf55e5
PWJ		 4158/**
4159 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4160 * @adapter: board private structure to initialize
4161 *
4162 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4163 * to the original CPU that initiated the Tx session. This runs in addition
4164 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4165 * Rx load across CPUs using RSS.
4166 *
4167 **/
e8e9f696 4168static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4169{
4170 bool ret = false;
4171 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4172
4173 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4174 f_fdir->mask = 0;
4175
4176 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4177 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4178 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4179 adapter->num_tx_queues = f_fdir->indices;
4180 adapter->num_rx_queues = f_fdir->indices;
4181 ret = true;
4182 } else {
4183 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4184 }
4185 return ret;
4186}
4187
0331a832
YZ		 4188#ifdef IXGBE_FCOE
4189/**
4190 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4191 * @adapter: board private structure to initialize
4192 *
4193 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4194 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4195 * rx queues out of the max number of rx queues, instead, it is used as the
4196 * index of the first rx queue used by FCoE.
4197 *
4198 **/
4199static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4200{
0331a832
YZ		 4201 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4202
e5b64635
JF		 4203 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4204 return false;
4205
e901acd6 4206 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4207
e901acd6
JF		 4208 adapter->num_rx_queues = 1;
4209 adapter->num_tx_queues = 1;
e5b64635 4210
e901acd6
JF		 4211 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4212 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4213 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4214 ixgbe_set_fdir_queues(adapter);
4215 else
4216 ixgbe_set_rss_queues(adapter);
e5b64635 4217 }
03ecf91a 4218
e901acd6
JF		 4219 /* adding FCoE rx rings to the end */
4220 f->mask = adapter->num_rx_queues;
4221 adapter->num_rx_queues += f->indices;
4222 adapter->num_tx_queues += f->indices;
0331a832 4223
e5b64635
JF		 4224 return true;
4225}
4226#endif /* IXGBE_FCOE */
4227
e901acd6
JF		 4228/* Artificial max queue cap per traffic class in DCB mode */
4229#define DCB_QUEUE_CAP 8
4230
e5b64635
JF		 4231#ifdef CONFIG_IXGBE_DCB
4232static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4233{
e901acd6
JF		 4234 int per_tc_q, q, i, offset = 0;
4235 struct net_device *dev = adapter->netdev;
4236 int tcs = netdev_get_num_tc(dev);
e5b64635 4237
e901acd6
JF		 4238 if (!tcs)
4239 return false;
e5b64635 4240
e901acd6
JF		 4241 /* Map queue offset and counts onto allocated tx queues */
4242 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4243 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4244
8b1c0b24 4245 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4246 netdev_set_tc_queue(dev, i, q, offset);
4247 offset += q;
0331a832
YZ		 4248 }
4249
e901acd6
JF		 4250 adapter->num_tx_queues = q * tcs;
4251 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4252
4253#ifdef IXGBE_FCOE
e901acd6
JF		 4254 /* FCoE enabled queues require special configuration indexed
4255 * by feature specific indices and mask. Here we map FCoE
4256 * indices onto the DCB queue pairs allowing FCoE to own
4257 * configuration later.
e5b64635 4258 */
e901acd6
JF		 4259 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4260 int tc;
4261 struct ixgbe_ring_feature *f =
4262 &adapter->ring_feature[RING_F_FCOE];
4263
4264 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4265 f->indices = dev->tc_to_txq[tc].count;
4266 f->mask = dev->tc_to_txq[tc].offset;
4267 }
e5b64635
JF		 4268#endif
4269
e901acd6 4270 return true;
0331a832 4271}
e5b64635 4272#endif
0331a832 4273
1cdd1ec8
GR		 4274/**
4275 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4276 * @adapter: board private structure to initialize
4277 *
4278 * IOV doesn't actually use anything, so just NAK the
4279 * request for now and let the other queue routines
4280 * figure out what to do.
4281 */
4282static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4283{
4284 return false;
4285}
4286
4df10466 4287/*
25985edc 4288 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4289 * @adapter: board private structure to initialize
4290 *
4291 * This is the top level queue allocation routine. The order here is very
4292 * important, starting with the "most" number of features turned on at once,
4293 * and ending with the smallest set of features. This way large combinations
4294 * can be allocated if they're turned on, and smaller combinations are the
4295 * fallthrough conditions.
4296 *
4297 **/
847f53ff 4298static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4299{
1cdd1ec8
GR		 4300 /* Start with base case */
4301 adapter->num_rx_queues = 1;
4302 adapter->num_tx_queues = 1;
4303 adapter->num_rx_pools = adapter->num_rx_queues;
4304 adapter->num_rx_queues_per_pool = 1;
4305
4306 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4307 goto done;
1cdd1ec8 4308
bc97114d
PWJ		 4309#ifdef CONFIG_IXGBE_DCB
4310 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4311 goto done;
bc97114d
PWJ		 4312
4313#endif
e5b64635
JF		 4314#ifdef IXGBE_FCOE
4315 if (ixgbe_set_fcoe_queues(adapter))
4316 goto done;
4317
4318#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4319 if (ixgbe_set_fdir_queues(adapter))
4320 goto done;
4321
bc97114d 4322 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4323 goto done;
4324
4325 /* fallback to base case */
4326 adapter->num_rx_queues = 1;
4327 adapter->num_tx_queues = 1;
4328
4329done:
847f53ff 4330 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4331 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4332 return netif_set_real_num_rx_queues(adapter->netdev,
4333 adapter->num_rx_queues);
b9804972
JB		 4334}
4335
021230d4 4336static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4337 int vectors)
021230d4
AV		 4338{
4339 int err, vector_threshold;
4340
4341 /* We'll want at least 3 (vector_threshold):
4342 * 1) TxQ[0] Cleanup
4343 * 2) RxQ[0] Cleanup
4344 * 3) Other (Link Status Change, etc.)
4345 * 4) TCP Timer (optional)
4346 */
4347 vector_threshold = MIN_MSIX_COUNT;
4348
4349 /* The more we get, the more we will assign to Tx/Rx Cleanup
4350 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4351 * Right now, we simply care about how many we'll get; we'll
4352 * set them up later while requesting irq's.
4353 */
4354 while (vectors >= vector_threshold) {
4355 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4356 vectors);
021230d4
AV		 4357 if (!err) /* Success in acquiring all requested vectors. */
4358 break;
4359 else if (err < 0)
4360 vectors = 0; /* Nasty failure, quit now */
4361 else /* err == number of vectors we should try again with */
4362 vectors = err;
4363 }
4364
4365 if (vectors < vector_threshold) {
4366 /* Can't allocate enough MSI-X interrupts? Oh well.
4367 * This just means we'll go with either a single MSI
4368 * vector or fall back to legacy interrupts.
4369 */
849c4542
ET		 4370 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4371 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4372 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4373 kfree(adapter->msix_entries);
4374 adapter->msix_entries = NULL;
021230d4
AV		 4375 } else {
4376 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4377 /*
4378 * Adjust for only the vectors we'll use, which is minimum
4379 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4380 * vectors we were allocated.
4381 */
4382 adapter->num_msix_vectors = min(vectors,
e8e9f696 4383 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4384 }
4385}
4386
021230d4 4387/**
bc97114d 4388 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4389 * @adapter: board private structure to initialize
4390 *
bc97114d
PWJ		 4391 * Cache the descriptor ring offsets for RSS to the assigned rings.
4392 *
021230d4 4393 **/
bc97114d 4394static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4395{
bc97114d 4396 int i;
bc97114d 4397
9d6b758f
AD		 4398 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4399 return false;
bc97114d 4400
9d6b758f
AD		 4401 for (i = 0; i < adapter->num_rx_queues; i++)
4402 adapter->rx_ring[i]->reg_idx = i;
4403 for (i = 0; i < adapter->num_tx_queues; i++)
4404 adapter->tx_ring[i]->reg_idx = i;
4405
4406 return true;
bc97114d
PWJ		 4407}
4408
4409#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4410
4411/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4412static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4413 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4414{
4415 struct net_device *dev = adapter->netdev;
4416 struct ixgbe_hw *hw = &adapter->hw;
4417 u8 num_tcs = netdev_get_num_tc(dev);
4418
4419 *tx = 0;
4420 *rx = 0;
4421
4422 switch (hw->mac.type) {
4423 case ixgbe_mac_82598EB:
aba70d5e
JF		 4424 *tx = tc << 2;
4425 *rx = tc << 3;
e5b64635
JF		 4426 break;
4427 case ixgbe_mac_82599EB:
4428 case ixgbe_mac_X540:
4fa2e0e1 4429 if (num_tcs > 4) {
e5b64635
JF		 4430 if (tc < 3) {
4431 *tx = tc << 5;
4432 *rx = tc << 4;
4433 } else if (tc < 5) {
4434 *tx = ((tc + 2) << 4);
4435 *rx = tc << 4;
4436 } else if (tc < num_tcs) {
4437 *tx = ((tc + 8) << 3);
4438 *rx = tc << 4;
4439 }
4fa2e0e1 4440 } else {
e5b64635
JF		 4441 *rx = tc << 5;
4442 switch (tc) {
4443 case 0:
4444 *tx = 0;
4445 break;
4446 case 1:
4447 *tx = 64;
4448 break;
4449 case 2:
4450 *tx = 96;
4451 break;
4452 case 3:
4453 *tx = 112;
4454 break;
4455 default:
4456 break;
4457 }
4458 }
4459 break;
4460 default:
4461 break;
4462 }
4463}
4464
bc97114d
PWJ		 4465/**
4466 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4467 * @adapter: board private structure to initialize
4468 *
4469 * Cache the descriptor ring offsets for DCB to the assigned rings.
4470 *
4471 **/
4472static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4473{
e5b64635
JF		 4474 struct net_device *dev = adapter->netdev;
4475 int i, j, k;
4476 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4477
8b1c0b24 4478 if (!num_tcs)
bd508178 4479 return false;
f92ef202 4480
e5b64635
JF		 4481 for (i = 0, k = 0; i < num_tcs; i++) {
4482 unsigned int tx_s, rx_s;
4483 u16 count = dev->tc_to_txq[i].count;
4484
4485 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4486 for (j = 0; j < count; j++, k++) {
4487 adapter->tx_ring[k]->reg_idx = tx_s + j;
4488 adapter->rx_ring[k]->reg_idx = rx_s + j;
4489 adapter->tx_ring[k]->dcb_tc = i;
4490 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4491 }
021230d4 4492 }
e5b64635
JF		 4493
4494 return true;
bc97114d
PWJ		 4495}
4496#endif
4497
c4cf55e5
PWJ		 4498/**
4499 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4500 * @adapter: board private structure to initialize
4501 *
4502 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4503 *
4504 **/
e8e9f696 4505static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4506{
4507 int i;
4508 bool ret = false;
4509
03ecf91a
AD		 4510 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4511 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4512 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4513 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4514 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4515 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4516 ret = true;
4517 }
4518
4519 return ret;
4520}
4521
0331a832
YZ		 4522#ifdef IXGBE_FCOE
4523/**
4524 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4525 * @adapter: board private structure to initialize
4526 *
4527 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4528 *
4529 */
4530static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4531{
0331a832 4532 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4533 int i;
4534 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4535
4536 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4537 return false;
0331a832 4538
bf29ee6c 4539 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4540 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4541 ixgbe_cache_ring_fdir(adapter);
4542 else
4543 ixgbe_cache_ring_rss(adapter);
8faa2a78 4544
bf29ee6c
AD		 4545 fcoe_rx_i = f->mask;
4546 fcoe_tx_i = f->mask;
0331a832 4547 }
bf29ee6c
AD		 4548 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4549 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4550 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4551 }
4552 return true;
0331a832
YZ		 4553}
4554
4555#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4556/**
4557 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4558 * @adapter: board private structure to initialize
4559 *
4560 * SR-IOV doesn't use any descriptor rings but changes the default if
4561 * no other mapping is used.
4562 *
4563 */
4564static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4565{
4a0b9ca0
PW		 4566 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4567 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4568 if (adapter->num_vfs)
4569 return true;
4570 else
4571 return false;
4572}
4573
bc97114d
PWJ		 4574/**
4575 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4576 * @adapter: board private structure to initialize
4577 *
4578 * Once we know the feature-set enabled for the device, we'll cache
4579 * the register offset the descriptor ring is assigned to.
4580 *
4581 * Note, the order the various feature calls is important. It must start with
4582 * the "most" features enabled at the same time, then trickle down to the
4583 * least amount of features turned on at once.
4584 **/
4585static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4586{
4587 /* start with default case */
4a0b9ca0
PW		 4588 adapter->rx_ring[0]->reg_idx = 0;
4589 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4590
1cdd1ec8
GR		 4591 if (ixgbe_cache_ring_sriov(adapter))
4592 return;
4593
e5b64635
JF		 4594#ifdef CONFIG_IXGBE_DCB
4595 if (ixgbe_cache_ring_dcb(adapter))
4596 return;
4597#endif
4598
0331a832
YZ		 4599#ifdef IXGBE_FCOE
4600 if (ixgbe_cache_ring_fcoe(adapter))
4601 return;
0331a832 4602#endif /* IXGBE_FCOE */
bc97114d 4603
c4cf55e5
PWJ		 4604 if (ixgbe_cache_ring_fdir(adapter))
4605 return;
4606
bc97114d
PWJ		 4607 if (ixgbe_cache_ring_rss(adapter))
4608 return;
021230d4
AV		 4609}
4610
9a799d71
AK		 4611/**
4612 * ixgbe_alloc_queues - Allocate memory for all rings
4613 * @adapter: board private structure to initialize
4614 *
4615 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4616 * number of queues at compile-time. The polling_netdev array is
4617 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4618 **/
2f90b865 4619static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4620{
e2ddeba9 4621 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4622
e2ddeba9
ED		 4623 if (nid < 0 || !node_online(nid))
4624 nid = first_online_node;
4625
4626 for (; tx < adapter->num_tx_queues; tx++) {
4627 struct ixgbe_ring *ring;
4628
4629 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4630 if (!ring)
e2ddeba9 4631 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4632 if (!ring)
e2ddeba9 4633 goto err_allocation;
4a0b9ca0 4634 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4635 ring->queue_index = tx;
4636 ring->numa_node = nid;
b6ec895e 4637 ring->dev = &adapter->pdev->dev;
fc77dc3c 4638 ring->netdev = adapter->netdev;
4a0b9ca0 4639
e2ddeba9 4640 adapter->tx_ring[tx] = ring;
021230d4 4641 }
b9804972 4642
e2ddeba9
ED		 4643 for (; rx < adapter->num_rx_queues; rx++) {
4644 struct ixgbe_ring *ring;
4a0b9ca0 4645
e2ddeba9 4646 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4647 if (!ring)
e2ddeba9 4648 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4649 if (!ring)
e2ddeba9
ED		 4650 goto err_allocation;
4651 ring->count = adapter->rx_ring_count;
4652 ring->queue_index = rx;
4653 ring->numa_node = nid;
b6ec895e 4654 ring->dev = &adapter->pdev->dev;
fc77dc3c 4655 ring->netdev = adapter->netdev;
4a0b9ca0 4656
e2ddeba9 4657 adapter->rx_ring[rx] = ring;
021230d4
AV		 4658 }
4659
4660 ixgbe_cache_ring_register(adapter);
4661
4662 return 0;
4663
e2ddeba9
ED		 4664err_allocation:
4665 while (tx)
4666 kfree(adapter->tx_ring[--tx]);
4667
4668 while (rx)
4669 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4670 return -ENOMEM;
4671}
4672
4673/**
4674 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4675 * @adapter: board private structure to initialize
4676 *
4677 * Attempt to configure the interrupts using the best available
4678 * capabilities of the hardware and the kernel.
4679 **/
feea6a57 4680static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4681{
8be0e467 4682 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4683 int err = 0;
4684 int vector, v_budget;
4685
4686 /*
4687 * It's easy to be greedy for MSI-X vectors, but it really
4688 * doesn't do us much good if we have a lot more vectors
4689 * than CPU's. So let's be conservative and only ask for
342bde1b 4690 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4691 */
4692 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4693 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4694
4695 /*
4696 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4697 * hw.mac->max_msix_vectors vectors. With features
4698 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4699 * descriptor queues supported by our device. Thus, we cap it off in
4700 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4701 */
8be0e467 4702 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4703
4704 /* A failure in MSI-X entry allocation isn't fatal, but it does
4705 * mean we disable MSI-X capabilities of the adapter. */
4706 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4707 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4708 if (adapter->msix_entries) {
4709 for (vector = 0; vector < v_budget; vector++)
4710 adapter->msix_entries[vector].entry = vector;
021230d4 4711
7a921c93 4712 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4713
7a921c93
AD		 4714 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4715 goto out;
4716 }
26d27844 4717
7a921c93
AD		 4718 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4719 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4720 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4721 e_err(probe,
03ecf91a 4722 "ATR is not supported while multiple "
45b9f509
AD		 4723 "queues are disabled. Disabling Flow Director\n");
4724 }
c4cf55e5 4725 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4726 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4727 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4728 ixgbe_disable_sriov(adapter);
4729
847f53ff
BH		 4730 err = ixgbe_set_num_queues(adapter);
4731 if (err)
4732 return err;
021230d4 4733
021230d4
AV		 4734 err = pci_enable_msi(adapter->pdev);
4735 if (!err) {
4736 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4737 } else {
849c4542
ET		 4738 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4739 "Unable to allocate MSI interrupt, "
4740 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4741 /* reset err */
4742 err = 0;
4743 }
4744
4745out:
021230d4
AV		 4746 return err;
4747}
4748
7a921c93
AD		 4749/**
4750 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4751 * @adapter: board private structure to initialize
4752 *
4753 * We allocate one q_vector per queue interrupt. If allocation fails we
4754 * return -ENOMEM.
4755 **/
4756static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4757{
4ff7fb12 4758 int v_idx, num_q_vectors;
7a921c93 4759 struct ixgbe_q_vector *q_vector;
7a921c93 4760
4ff7fb12 4761 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4762 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4763 else
7a921c93 4764 num_q_vectors = 1;
7a921c93 4765
4ff7fb12 4766 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4767 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4768 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4769 if (!q_vector)
4770 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4771 GFP_KERNEL);
7a921c93
AD		 4772 if (!q_vector)
4773 goto err_out;
4ff7fb12 4774
7a921c93 4775 q_vector->adapter = adapter;
4ff7fb12
AD		 4776 q_vector->v_idx = v_idx;
4777
207867f5
AD		 4778 /* Allocate the affinity_hint cpumask, configure the mask */
4779 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4780 goto err_out;
4781 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4ff7fb12
AD		 4782 netif_napi_add(adapter->netdev, &q_vector->napi,
4783 ixgbe_poll, 64);
4784 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 4785 }
4786
4787 return 0;
4788
4789err_out:
4ff7fb12
AD		 4790 while (v_idx) {
4791 v_idx--;
4792 q_vector = adapter->q_vector[v_idx];
7a921c93 4793 netif_napi_del(&q_vector->napi);
207867f5 4794 free_cpumask_var(q_vector->affinity_mask);
7a921c93 4795 kfree(q_vector);
4ff7fb12 4796 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 4797 }
4798 return -ENOMEM;
4799}
4800
4801/**
4802 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4803 * @adapter: board private structure to initialize
4804 *
4805 * This function frees the memory allocated to the q_vectors. In addition if
4806 * NAPI is enabled it will delete any references to the NAPI struct prior
4807 * to freeing the q_vector.
4808 **/
4809static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4810{
207867f5 4811 int v_idx, num_q_vectors;
7a921c93 4812
91281fd3 4813 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4814 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4815 else
7a921c93 4816 num_q_vectors = 1;
7a921c93 4817
207867f5
AD		 4818 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4819 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4820 adapter->q_vector[v_idx] = NULL;
91281fd3 4821 netif_napi_del(&q_vector->napi);
207867f5 4822 free_cpumask_var(q_vector->affinity_mask);
7a921c93
AD		 4823 kfree(q_vector);
4824 }
4825}
4826
7b25cdba 4827static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4828{
4829 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4830 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4831 pci_disable_msix(adapter->pdev);
4832 kfree(adapter->msix_entries);
4833 adapter->msix_entries = NULL;
4834 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4835 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4836 pci_disable_msi(adapter->pdev);
4837 }
021230d4
AV		 4838}
4839
4840/**
4841 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4842 * @adapter: board private structure to initialize
4843 *
4844 * We determine which interrupt scheme to use based on...
4845 * - Kernel support (MSI, MSI-X)
4846 * - which can be user-defined (via MODULE_PARAM)
4847 * - Hardware queue count (num_*_queues)
4848 * - defined by miscellaneous hardware support/features (RSS, etc.)
4849 **/
2f90b865 4850int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4851{
4852 int err;
4853
4854 /* Number of supported queues */
847f53ff
BH		 4855 err = ixgbe_set_num_queues(adapter);
4856 if (err)
4857 return err;
021230d4 4858
021230d4
AV		 4859 err = ixgbe_set_interrupt_capability(adapter);
4860 if (err) {
849c4542 4861 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4862 goto err_set_interrupt;
9a799d71
AK		 4863 }
4864
7a921c93
AD		 4865 err = ixgbe_alloc_q_vectors(adapter);
4866 if (err) {
849c4542 4867 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4868 goto err_alloc_q_vectors;
4869 }
4870
4871 err = ixgbe_alloc_queues(adapter);
4872 if (err) {
849c4542 4873 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4874 goto err_alloc_queues;
4875 }
4876
849c4542 4877 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4878 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4879 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4880
4881 set_bit(__IXGBE_DOWN, &adapter->state);
4882
9a799d71 4883 return 0;
021230d4 4884
7a921c93
AD		 4885err_alloc_queues:
4886 ixgbe_free_q_vectors(adapter);
4887err_alloc_q_vectors:
4888 ixgbe_reset_interrupt_capability(adapter);
021230d4 4889err_set_interrupt:
7a921c93
AD		 4890 return err;
4891}
4892
4893/**
4894 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4895 * @adapter: board private structure to clear interrupt scheme on
4896 *
4897 * We go through and clear interrupt specific resources and reset the structure
4898 * to pre-load conditions
4899 **/
4900void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4901{
4a0b9ca0
PW		 4902 int i;
4903
4904 for (i = 0; i < adapter->num_tx_queues; i++) {
4905 kfree(adapter->tx_ring[i]);
4906 adapter->tx_ring[i] = NULL;
4907 }
4908 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4909 struct ixgbe_ring *ring = adapter->rx_ring[i];
4910
4911 /* ixgbe_get_stats64() might access this ring, we must wait
4912 * a grace period before freeing it.
4913 */
bcec8b65 4914 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 4915 adapter->rx_ring[i] = NULL;
4916 }
7a921c93 4917
b8eb3a10
DS		 4918 adapter->num_tx_queues = 0;
4919 adapter->num_rx_queues = 0;
4920
7a921c93
AD		 4921 ixgbe_free_q_vectors(adapter);
4922 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4923}
4924
4925/**
4926 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4927 * @adapter: board private structure to initialize
4928 *
4929 * ixgbe_sw_init initializes the Adapter private data structure.
4930 * Fields are initialized based on PCI device information and
4931 * OS network device settings (MTU size).
4932 **/
4933static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4934{
4935 struct ixgbe_hw *hw = &adapter->hw;
4936 struct pci_dev *pdev = adapter->pdev;
021230d4 4937 unsigned int rss;
7a6b6f51 4938#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4939 int j;
4940 struct tc_configuration *tc;
4941#endif
021230d4 4942
c44ade9e
JB		 4943 /* PCI config space info */
4944
4945 hw->vendor_id = pdev->vendor;
4946 hw->device_id = pdev->device;
4947 hw->revision_id = pdev->revision;
4948 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4949 hw->subsystem_device_id = pdev->subsystem_device;
4950
021230d4
AV		 4951 /* Set capability flags */
4952 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4953 adapter->ring_feature[RING_F_RSS].indices = rss;
4954 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 4955 switch (hw->mac.type) {
4956 case ixgbe_mac_82598EB:
bf069c97
DS		 4957 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4958 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4959 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 4960 break;
b93a2226 4961 case ixgbe_mac_X540:
4f51bf70
JK		 4962 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4963 case ixgbe_mac_82599EB:
e8e26350 4964 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4965 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4966 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4967 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4968 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4969 /* Flow Director hash filters enabled */
4970 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4971 adapter->atr_sample_rate = 20;
c4cf55e5 4972 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4973 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4974 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4975#ifdef IXGBE_FCOE
0d551589
YZ		 4976 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4977 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4978 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4979#ifdef CONFIG_IXGBE_DCB
6ee16520 4980 /* Default traffic class to use for FCoE */
56075a98 4981 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4982#endif
eacd73f7 4983#endif /* IXGBE_FCOE */
bd508178
AD		 4984 break;
4985 default:
4986 break;
f8212f97 4987 }
2f90b865 4988
1fc5f038
AD		 4989 /* n-tuple support exists, always init our spinlock */
4990 spin_lock_init(&adapter->fdir_perfect_lock);
4991
7a6b6f51 4992#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4993 /* Configure DCB traffic classes */
4994 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4995 tc = &adapter->dcb_cfg.tc_config[j];
4996 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4997 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
32701dc2 4998 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 1 << j;
2f90b865
AD		 4999 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5000 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
32701dc2 5001 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 1 << j;
2f90b865
AD		 5002 tc->dcb_pfc = pfc_disabled;
5003 }
5004 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5005 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5006 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5007 adapter->dcb_set_bitmap = 0x00;
3032309b 5008 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5009 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5010 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5011
5012#endif
9a799d71
AK		 5013
5014 /* default flow control settings */
cd7664f6 5015 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5016 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5017#ifdef CONFIG_DCB
5018 adapter->last_lfc_mode = hw->fc.current_mode;
5019#endif
9da712d2 5020 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5021 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5022 hw->fc.send_xon = true;
71fd570b 5023 hw->fc.disable_fc_autoneg = false;
9a799d71 5024
30efa5a3 5025 /* enable itr by default in dynamic mode */
f7554a2b 5026 adapter->rx_itr_setting = 1;
f7554a2b 5027 adapter->tx_itr_setting = 1;
30efa5a3
JB		 5028
5029 /* set defaults for eitr in MegaBytes */
5030 adapter->eitr_low = 10;
5031 adapter->eitr_high = 20;
5032
5033 /* set default ring sizes */
5034 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5035 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5036
bd198058 5037 /* set default work limits */
59224555 5038 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5039
9a799d71 5040 /* initialize eeprom parameters */
c44ade9e 5041 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5042 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5043 return -EIO;
5044 }
5045
021230d4 5046 /* enable rx csum by default */
9a799d71
AK		 5047 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5048
1a6c14a2
JB		 5049 /* get assigned NUMA node */
5050 adapter->node = dev_to_node(&pdev->dev);
5051
9a799d71
AK		 5052 set_bit(__IXGBE_DOWN, &adapter->state);
5053
5054 return 0;
5055}
5056
5057/**
5058 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5059 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5060 *
5061 * Return 0 on success, negative on failure
5062 **/
b6ec895e 5063int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5064{
b6ec895e 5065 struct device *dev = tx_ring->dev;
9a799d71
AK		 5066 int size;
5067
3a581073 5068 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5069 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5070 if (!tx_ring->tx_buffer_info)
89bf67f1 5071 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5072 if (!tx_ring->tx_buffer_info)
5073 goto err;
9a799d71
AK		 5074
5075 /* round up to nearest 4K */
12207e49 5076 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5077 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5078
b6ec895e 5079 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5080 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5081 if (!tx_ring->desc)
5082 goto err;
9a799d71 5083
3a581073
JB		 5084 tx_ring->next_to_use = 0;
5085 tx_ring->next_to_clean = 0;
9a799d71 5086 return 0;
e01c31a5
JB		 5087
5088err:
5089 vfree(tx_ring->tx_buffer_info);
5090 tx_ring->tx_buffer_info = NULL;
b6ec895e 5091 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5092 return -ENOMEM;
9a799d71
AK		 5093}
5094
69888674
AD		 5095/**
5096 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5097 * @adapter: board private structure
5098 *
5099 * If this function returns with an error, then it's possible one or
5100 * more of the rings is populated (while the rest are not). It is the
5101 * callers duty to clean those orphaned rings.
5102 *
5103 * Return 0 on success, negative on failure
5104 **/
5105static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5106{
5107 int i, err = 0;
5108
5109 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5110 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5111 if (!err)
5112 continue;
396e799c 5113 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5114 break;
5115 }
5116
5117 return err;
5118}
5119
9a799d71
AK		 5120/**
5121 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5122 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5123 *
5124 * Returns 0 on success, negative on failure
5125 **/
b6ec895e 5126int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5127{
b6ec895e 5128 struct device *dev = rx_ring->dev;
021230d4 5129 int size;
9a799d71 5130
3a581073 5131 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5132 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5133 if (!rx_ring->rx_buffer_info)
89bf67f1 5134 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5135 if (!rx_ring->rx_buffer_info)
5136 goto err;
9a799d71 5137
9a799d71 5138 /* Round up to nearest 4K */
3a581073
JB		 5139 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5140 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5141
b6ec895e 5142 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5143 &rx_ring->dma, GFP_KERNEL);
9a799d71 5144
b6ec895e
AD		 5145 if (!rx_ring->desc)
5146 goto err;
9a799d71 5147
3a581073
JB		 5148 rx_ring->next_to_clean = 0;
5149 rx_ring->next_to_use = 0;
9a799d71
AK		 5150
5151 return 0;
b6ec895e
AD		 5152err:
5153 vfree(rx_ring->rx_buffer_info);
5154 rx_ring->rx_buffer_info = NULL;
5155 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5156 return -ENOMEM;
9a799d71
AK		 5157}
5158
69888674
AD		 5159/**
5160 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5161 * @adapter: board private structure
5162 *
5163 * If this function returns with an error, then it's possible one or
5164 * more of the rings is populated (while the rest are not). It is the
5165 * callers duty to clean those orphaned rings.
5166 *
5167 * Return 0 on success, negative on failure
5168 **/
69888674
AD		 5169static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5170{
5171 int i, err = 0;
5172
5173 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5174 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5175 if (!err)
5176 continue;
396e799c 5177 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5178 break;
5179 }
5180
5181 return err;
5182}
5183
9a799d71
AK		 5184/**
5185 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5186 * @tx_ring: Tx descriptor ring for a specific queue
5187 *
5188 * Free all transmit software resources
5189 **/
b6ec895e 5190void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5191{
b6ec895e 5192 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5193
5194 vfree(tx_ring->tx_buffer_info);
5195 tx_ring->tx_buffer_info = NULL;
5196
b6ec895e
AD		 5197 /* if not set, then don't free */
5198 if (!tx_ring->desc)
5199 return;
5200
5201 dma_free_coherent(tx_ring->dev, tx_ring->size,
5202 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5203
5204 tx_ring->desc = NULL;
5205}
5206
5207/**
5208 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5209 * @adapter: board private structure
5210 *
5211 * Free all transmit software resources
5212 **/
5213static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5214{
5215 int i;
5216
5217 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5218 if (adapter->tx_ring[i]->desc)
b6ec895e 5219 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5220}
5221
5222/**
b4617240 5223 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5224 * @rx_ring: ring to clean the resources from
5225 *
5226 * Free all receive software resources
5227 **/
b6ec895e 5228void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5229{
b6ec895e 5230 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5231
5232 vfree(rx_ring->rx_buffer_info);
5233 rx_ring->rx_buffer_info = NULL;
5234
b6ec895e
AD		 5235 /* if not set, then don't free */
5236 if (!rx_ring->desc)
5237 return;
5238
5239 dma_free_coherent(rx_ring->dev, rx_ring->size,
5240 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5241
5242 rx_ring->desc = NULL;
5243}
5244
5245/**
5246 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5247 * @adapter: board private structure
5248 *
5249 * Free all receive software resources
5250 **/
5251static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5252{
5253 int i;
5254
5255 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5256 if (adapter->rx_ring[i]->desc)
b6ec895e 5257 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5258}
5259
9a799d71
AK		 5260/**
5261 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5262 * @netdev: network interface device structure
5263 * @new_mtu: new value for maximum frame size
5264 *
5265 * Returns 0 on success, negative on failure
5266 **/
5267static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5268{
5269 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5270 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5271 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5272
42c783c5 5273 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5274 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5275 hw->mac.type != ixgbe_mac_X540) {
5276 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5277 return -EINVAL;
5278 } else {
5279 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5280 return -EINVAL;
5281 }
9a799d71 5282
396e799c 5283 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5284 /* must set new MTU before calling down or up */
9a799d71
AK		 5285 netdev->mtu = new_mtu;
5286
d4f80882
AV		 5287 if (netif_running(netdev))
5288 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5289
5290 return 0;
5291}
5292
5293/**
5294 * ixgbe_open - Called when a network interface is made active
5295 * @netdev: network interface device structure
5296 *
5297 * Returns 0 on success, negative value on failure
5298 *
5299 * The open entry point is called when a network interface is made
5300 * active by the system (IFF_UP). At this point all resources needed
5301 * for transmit and receive operations are allocated, the interrupt
5302 * handler is registered with the OS, the watchdog timer is started,
5303 * and the stack is notified that the interface is ready.
5304 **/
5305static int ixgbe_open(struct net_device *netdev)
5306{
5307 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5308 int err;
4bebfaa5
AK		 5309
5310 /* disallow open during test */
5311 if (test_bit(__IXGBE_TESTING, &adapter->state))
5312 return -EBUSY;
9a799d71 5313
54386467
JB		 5314 netif_carrier_off(netdev);
5315
9a799d71
AK		 5316 /* allocate transmit descriptors */
5317 err = ixgbe_setup_all_tx_resources(adapter);
5318 if (err)
5319 goto err_setup_tx;
5320
9a799d71
AK		 5321 /* allocate receive descriptors */
5322 err = ixgbe_setup_all_rx_resources(adapter);
5323 if (err)
5324 goto err_setup_rx;
5325
5326 ixgbe_configure(adapter);
5327
021230d4 5328 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5329 if (err)
5330 goto err_req_irq;
5331
c7ccde0f 5332 ixgbe_up_complete(adapter);
9a799d71
AK		 5333
5334 return 0;
5335
9a799d71 5336err_req_irq:
9a799d71 5337err_setup_rx:
a20a1199 5338 ixgbe_free_all_rx_resources(adapter);
9a799d71 5339err_setup_tx:
a20a1199 5340 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5341 ixgbe_reset(adapter);
5342
5343 return err;
5344}
5345
5346/**
5347 * ixgbe_close - Disables a network interface
5348 * @netdev: network interface device structure
5349 *
5350 * Returns 0, this is not allowed to fail
5351 *
5352 * The close entry point is called when an interface is de-activated
5353 * by the OS. The hardware is still under the drivers control, but
5354 * needs to be disabled. A global MAC reset is issued to stop the
5355 * hardware, and all transmit and receive resources are freed.
5356 **/
5357static int ixgbe_close(struct net_device *netdev)
5358{
5359 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5360
5361 ixgbe_down(adapter);
5362 ixgbe_free_irq(adapter);
5363
e4911d57
AD		 5364 ixgbe_fdir_filter_exit(adapter);
5365
9a799d71
AK		 5366 ixgbe_free_all_tx_resources(adapter);
5367 ixgbe_free_all_rx_resources(adapter);
5368
5eba3699 5369 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5370
5371 return 0;
5372}
5373
b3c8b4ba
AD		 5374#ifdef CONFIG_PM
5375static int ixgbe_resume(struct pci_dev *pdev)
5376{
c60fbb00
AD		 5377 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5378 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5379 u32 err;
5380
5381 pci_set_power_state(pdev, PCI_D0);
5382 pci_restore_state(pdev);
656ab817
DS		 5383 /*
5384 * pci_restore_state clears dev->state_saved so call
5385 * pci_save_state to restore it.
5386 */
5387 pci_save_state(pdev);
9ce77666 5388
5389 err = pci_enable_device_mem(pdev);
b3c8b4ba 5390 if (err) {
849c4542 5391 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5392 return err;
5393 }
5394 pci_set_master(pdev);
5395
dd4d8ca6 5396 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5397
5398 err = ixgbe_init_interrupt_scheme(adapter);
5399 if (err) {
849c4542 5400 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5401 return err;
5402 }
5403
b3c8b4ba
AD		 5404 ixgbe_reset(adapter);
5405
495dce12
WJP		 5406 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5407
b3c8b4ba 5408 if (netif_running(netdev)) {
c60fbb00 5409 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5410 if (err)
5411 return err;
5412 }
5413
5414 netif_device_attach(netdev);
5415
5416 return 0;
5417}
b3c8b4ba 5418#endif /* CONFIG_PM */
9d8d05ae
RW		 5419
5420static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5421{
c60fbb00
AD		 5422 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5423 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5424 struct ixgbe_hw *hw = &adapter->hw;
5425 u32 ctrl, fctrl;
5426 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5427#ifdef CONFIG_PM
5428 int retval = 0;
5429#endif
5430
5431 netif_device_detach(netdev);
5432
5433 if (netif_running(netdev)) {
5434 ixgbe_down(adapter);
5435 ixgbe_free_irq(adapter);
5436 ixgbe_free_all_tx_resources(adapter);
5437 ixgbe_free_all_rx_resources(adapter);
5438 }
b3c8b4ba 5439
5f5ae6fc 5440 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5441#ifdef CONFIG_DCB
5442 kfree(adapter->ixgbe_ieee_pfc);
5443 kfree(adapter->ixgbe_ieee_ets);
5444#endif
5f5ae6fc 5445
b3c8b4ba
AD		 5446#ifdef CONFIG_PM
5447 retval = pci_save_state(pdev);
5448 if (retval)
5449 return retval;
4df10466 5450
b3c8b4ba 5451#endif
e8e26350
PW		 5452 if (wufc) {
5453 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5454
e8e26350
PW		 5455 /* turn on all-multi mode if wake on multicast is enabled */
5456 if (wufc & IXGBE_WUFC_MC) {
5457 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5458 fctrl |= IXGBE_FCTRL_MPE;
5459 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5460 }
5461
5462 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5463 ctrl |= IXGBE_CTRL_GIO_DIS;
5464 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5465
5466 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5467 } else {
5468 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5469 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5470 }
5471
bd508178
AD		 5472 switch (hw->mac.type) {
5473 case ixgbe_mac_82598EB:
dd4d8ca6 5474 pci_wake_from_d3(pdev, false);
bd508178
AD		 5475 break;
5476 case ixgbe_mac_82599EB:
b93a2226 5477 case ixgbe_mac_X540:
bd508178
AD		 5478 pci_wake_from_d3(pdev, !!wufc);
5479 break;
5480 default:
5481 break;
5482 }
b3c8b4ba 5483
9d8d05ae
RW		 5484 *enable_wake = !!wufc;
5485
b3c8b4ba
AD		 5486 ixgbe_release_hw_control(adapter);
5487
5488 pci_disable_device(pdev);
5489
9d8d05ae
RW		 5490 return 0;
5491}
5492
5493#ifdef CONFIG_PM
5494static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5495{
5496 int retval;
5497 bool wake;
5498
5499 retval = __ixgbe_shutdown(pdev, &wake);
5500 if (retval)
5501 return retval;
5502
5503 if (wake) {
5504 pci_prepare_to_sleep(pdev);
5505 } else {
5506 pci_wake_from_d3(pdev, false);
5507 pci_set_power_state(pdev, PCI_D3hot);
5508 }
b3c8b4ba
AD		 5509
5510 return 0;
5511}
9d8d05ae 5512#endif /* CONFIG_PM */
b3c8b4ba
AD		 5513
5514static void ixgbe_shutdown(struct pci_dev *pdev)
5515{
9d8d05ae
RW		 5516 bool wake;
5517
5518 __ixgbe_shutdown(pdev, &wake);
5519
5520 if (system_state == SYSTEM_POWER_OFF) {
5521 pci_wake_from_d3(pdev, wake);
5522 pci_set_power_state(pdev, PCI_D3hot);
5523 }
b3c8b4ba
AD		 5524}
5525
9a799d71
AK		 5526/**
5527 * ixgbe_update_stats - Update the board statistics counters.
5528 * @adapter: board private structure
5529 **/
5530void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5531{
2d86f139 5532 struct net_device *netdev = adapter->netdev;
9a799d71 5533 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5534 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5535 u64 total_mpc = 0;
5536 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5537 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5538 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5539 u64 bytes = 0, packets = 0;
9a799d71 5540
d08935c2
DS		 5541 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5542 test_bit(__IXGBE_RESETTING, &adapter->state))
5543 return;
5544
94b982b2 5545 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5546 u64 rsc_count = 0;
94b982b2 5547 u64 rsc_flush = 0;
d51019a4
PW		 5548 for (i = 0; i < 16; i++)
5549 adapter->hw_rx_no_dma_resources +=
7ca647bd 5550 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5551 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5552 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5553 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5554 }
5555 adapter->rsc_total_count = rsc_count;
5556 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5557 }
5558
5b7da515
AD		 5559 for (i = 0; i < adapter->num_rx_queues; i++) {
5560 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5561 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5562 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5563 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5564 bytes += rx_ring->stats.bytes;
5565 packets += rx_ring->stats.packets;
5566 }
5567 adapter->non_eop_descs = non_eop_descs;
5568 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5569 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5570 netdev->stats.rx_bytes = bytes;
5571 netdev->stats.rx_packets = packets;
5572
5573 bytes = 0;
5574 packets = 0;
7ca3bc58 5575 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5576 for (i = 0; i < adapter->num_tx_queues; i++) {
5577 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5578 restart_queue += tx_ring->tx_stats.restart_queue;
5579 tx_busy += tx_ring->tx_stats.tx_busy;
5580 bytes += tx_ring->stats.bytes;
5581 packets += tx_ring->stats.packets;
5582 }
eb985f09 5583 adapter->restart_queue = restart_queue;
5b7da515
AD		 5584 adapter->tx_busy = tx_busy;
5585 netdev->stats.tx_bytes = bytes;
5586 netdev->stats.tx_packets = packets;
7ca3bc58 5587
7ca647bd 5588 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5589
5590 /* 8 register reads */
6f11eef7
AV		 5591 for (i = 0; i < 8; i++) {
5592 /* for packet buffers not used, the register should read 0 */
5593 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5594 missed_rx += mpc;
7ca647bd
JP		 5595 hwstats->mpc[i] += mpc;
5596 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5597 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5598 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5599 switch (hw->mac.type) {
5600 case ixgbe_mac_82598EB:
1a70db4b
ET		 5601 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5602 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5603 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5604 hwstats->pxonrxc[i] +=
5605 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5606 break;
5607 case ixgbe_mac_82599EB:
b93a2226 5608 case ixgbe_mac_X540:
bd508178
AD		 5609 hwstats->pxonrxc[i] +=
5610 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5611 break;
5612 default:
5613 break;
e8e26350 5614 }
6f11eef7 5615 }
1a70db4b
ET		 5616
5617 /*16 register reads */
5618 for (i = 0; i < 16; i++) {
5619 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5620 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5621 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5622 (hw->mac.type == ixgbe_mac_X540)) {
5623 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5624 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5625 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5626 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5627 }
5628 }
5629
7ca647bd 5630 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5631 /* work around hardware counting issue */
7ca647bd 5632 hwstats->gprc -= missed_rx;
6f11eef7 5633
c84d324c
JF		 5634 ixgbe_update_xoff_received(adapter);
5635
6f11eef7 5636 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5637 switch (hw->mac.type) {
5638 case ixgbe_mac_82598EB:
5639 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5640 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5641 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5642 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5643 break;
b93a2226 5644 case ixgbe_mac_X540:
58f6bcf9
ET		 5645 /* OS2BMC stats are X540 only*/
5646 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5647 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5648 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5649 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5650 case ixgbe_mac_82599EB:
7ca647bd 5651 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5652 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5653 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5654 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5655 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5656 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5657 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5658 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5659 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5660#ifdef IXGBE_FCOE
7ca647bd
JP		 5661 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5662 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5663 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5664 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5665 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5666 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5667#endif /* IXGBE_FCOE */
bd508178
AD		 5668 break;
5669 default:
5670 break;
e8e26350 5671 }
9a799d71 5672 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5673 hwstats->bprc += bprc;
5674 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5675 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5676 hwstats->mprc -= bprc;
5677 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5678 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5679 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5680 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5681 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5682 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5683 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5684 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5685 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5686 hwstats->lxontxc += lxon;
6f11eef7 5687 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5688 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5689 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5690 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5691 /*
5692 * 82598 errata - tx of flow control packets is included in tx counters
5693 */
5694 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5695 hwstats->gptc -= xon_off_tot;
5696 hwstats->mptc -= xon_off_tot;
5697 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5698 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5699 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5700 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5701 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5702 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5703 hwstats->ptc64 -= xon_off_tot;
5704 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5705 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5706 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5707 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5708 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5709 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5710
5711 /* Fill out the OS statistics structure */
7ca647bd 5712 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5713
5714 /* Rx Errors */
7ca647bd 5715 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5716 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5717 netdev->stats.rx_length_errors = hwstats->rlec;
5718 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5719 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5720}
5721
5722/**
d034acf1
AD		 5723 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5724 * @adapter - pointer to the device adapter structure
9a799d71 5725 **/
d034acf1 5726static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5727{
cf8280ee 5728 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5729 int i;
cf8280ee 5730
d034acf1
AD		 5731 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5732 return;
5733
5734 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5735
d034acf1 5736 /* if interface is down do nothing */
fe49f04a 5737 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5738 return;
5739
5740 /* do nothing if we are not using signature filters */
5741 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5742 return;
5743
5744 adapter->fdir_overflow++;
5745
93c52dd0
AD		 5746 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5747 for (i = 0; i < adapter->num_tx_queues; i++)
5748 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5749 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5750 /* re-enable flow director interrupts */
5751 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5752 } else {
5753 e_err(probe, "failed to finish FDIR re-initialization, "
5754 "ignored adding FDIR ATR filters\n");
5755 }
93c52dd0
AD		 5756}
5757
5758/**
5759 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5760 * @adapter - pointer to the device adapter structure
5761 *
5762 * This function serves two purposes. First it strobes the interrupt lines
5763 * in order to make certain interrupts are occuring. Secondly it sets the
5764 * bits needed to check for TX hangs. As a result we should immediately
5765 * determine if a hang has occured.
5766 */
5767static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5768{
cf8280ee 5769 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5770 u64 eics = 0;
5771 int i;
cf8280ee 5772
93c52dd0
AD		 5773 /* If we're down or resetting, just bail */
5774 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5775 test_bit(__IXGBE_RESETTING, &adapter->state))
5776 return;
22d5a71b 5777
93c52dd0
AD		 5778 /* Force detection of hung controller */
5779 if (netif_carrier_ok(adapter->netdev)) {
5780 for (i = 0; i < adapter->num_tx_queues; i++)
5781 set_check_for_tx_hang(adapter->tx_ring[i]);
5782 }
22d5a71b 5783
fe49f04a
AD		 5784 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5785 /*
5786 * for legacy and MSI interrupts don't set any bits
5787 * that are enabled for EIAM, because this operation
5788 * would set *both* EIMS and EICS for any bit in EIAM
5789 */
5790 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5791 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5792 } else {
5793 /* get one bit for every active tx/rx interrupt vector */
5794 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5795 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5796 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5797 eics |= ((u64)1 << i);
5798 }
cf8280ee 5799 }
9a799d71 5800
93c52dd0 5801 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5802 ixgbe_irq_rearm_queues(adapter, eics);
5803
cf8280ee
JB		 5804}
5805
e8e26350 5806/**
93c52dd0
AD		 5807 * ixgbe_watchdog_update_link - update the link status
5808 * @adapter - pointer to the device adapter structure
5809 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5810 **/
93c52dd0 5811static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5812{
e8e26350 5813 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5814 u32 link_speed = adapter->link_speed;
5815 bool link_up = adapter->link_up;
c4cf55e5 5816 int i;
e8e26350 5817
93c52dd0
AD		 5818 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5819 return;
5820
5821 if (hw->mac.ops.check_link) {
5822 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5823 } else {
93c52dd0
AD		 5824 /* always assume link is up, if no check link function */
5825 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5826 link_up = true;
c4cf55e5 5827 }
93c52dd0
AD		 5828 if (link_up) {
5829 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5830 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5831 hw->mac.ops.fc_enable(hw, i);
5832 } else {
5833 hw->mac.ops.fc_enable(hw, 0);
5834 }
5835 }
5836
5837 if (link_up ||
5838 time_after(jiffies, (adapter->link_check_timeout +
5839 IXGBE_TRY_LINK_TIMEOUT))) {
5840 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5841 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5842 IXGBE_WRITE_FLUSH(hw);
5843 }
5844
5845 adapter->link_up = link_up;
5846 adapter->link_speed = link_speed;
e8e26350
PW		 5847}
5848
5849/**
93c52dd0
AD		 5850 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5851 * print link up message
5852 * @adapter - pointer to the device adapter structure
e8e26350 5853 **/
93c52dd0 5854static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5855{
93c52dd0 5856 struct net_device *netdev = adapter->netdev;
e8e26350 5857 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5858 u32 link_speed = adapter->link_speed;
5859 bool flow_rx, flow_tx;
e8e26350 5860
93c52dd0
AD		 5861 /* only continue if link was previously down */
5862 if (netif_carrier_ok(netdev))
a985b6c3 5863 return;
63d6e1d8 5864
93c52dd0 5865 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5866
93c52dd0
AD		 5867 switch (hw->mac.type) {
5868 case ixgbe_mac_82598EB: {
5869 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5870 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5871 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5872 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5873 }
5874 break;
5875 case ixgbe_mac_X540:
5876 case ixgbe_mac_82599EB: {
5877 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5878 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5879 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5880 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5881 }
5882 break;
5883 default:
5884 flow_tx = false;
5885 flow_rx = false;
5886 break;
e8e26350 5887 }
93c52dd0
AD		 5888 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5889 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5890 "10 Gbps" :
5891 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5892 "1 Gbps" :
5893 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5894 "100 Mbps" :
5895 "unknown speed"))),
5896 ((flow_rx && flow_tx) ? "RX/TX" :
5897 (flow_rx ? "RX" :
5898 (flow_tx ? "TX" : "None"))));
e8e26350 5899
93c52dd0 5900 netif_carrier_on(netdev);
93c52dd0 5901 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5902}
5903
c4cf55e5 5904/**
93c52dd0
AD		 5905 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5906 * print link down message
5907 * @adapter - pointer to the adapter structure
c4cf55e5 5908 **/
93c52dd0 5909static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 5910{
cf8280ee 5911 struct net_device *netdev = adapter->netdev;
c4cf55e5 5912 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5913
93c52dd0
AD		 5914 adapter->link_up = false;
5915 adapter->link_speed = 0;
cf8280ee 5916
93c52dd0
AD		 5917 /* only continue if link was up previously */
5918 if (!netif_carrier_ok(netdev))
5919 return;
264857b8 5920
93c52dd0
AD		 5921 /* poll for SFP+ cable when link is down */
5922 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5923 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5924
93c52dd0
AD		 5925 e_info(drv, "NIC Link is Down\n");
5926 netif_carrier_off(netdev);
5927}
e8e26350 5928
93c52dd0
AD		 5929/**
5930 * ixgbe_watchdog_flush_tx - flush queues on link down
5931 * @adapter - pointer to the device adapter structure
5932 **/
5933static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5934{
c4cf55e5 5935 int i;
93c52dd0 5936 int some_tx_pending = 0;
c4cf55e5 5937
93c52dd0 5938 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5939 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5940 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5941 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5942 some_tx_pending = 1;
5943 break;
5944 }
5945 }
5946
5947 if (some_tx_pending) {
5948 /* We've lost link, so the controller stops DMA,
5949 * but we've got queued Tx work that's never going
5950 * to get done, so reset controller to flush Tx.
5951 * (Do the reset outside of interrupt context).
5952 */
c83c6cbd 5953 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5954 }
c4cf55e5 5955 }
c4cf55e5
PWJ		 5956}
5957
a985b6c3
GR		 5958static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5959{
5960 u32 ssvpc;
5961
5962 /* Do not perform spoof check for 82598 */
5963 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5964 return;
5965
5966 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5967
5968 /*
5969 * ssvpc register is cleared on read, if zero then no
5970 * spoofed packets in the last interval.
5971 */
5972 if (!ssvpc)
5973 return;
5974
5975 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5976}
5977
93c52dd0
AD		 5978/**
5979 * ixgbe_watchdog_subtask - check and bring link up
5980 * @adapter - pointer to the device adapter structure
5981 **/
5982static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5983{
5984 /* if interface is down do nothing */
7edebf9a
ET		 5985 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5986 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5987 return;
5988
5989 ixgbe_watchdog_update_link(adapter);
5990
5991 if (adapter->link_up)
5992 ixgbe_watchdog_link_is_up(adapter);
5993 else
5994 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5995
a985b6c3 5996 ixgbe_spoof_check(adapter);
9a799d71 5997 ixgbe_update_stats(adapter);
93c52dd0
AD		 5998
5999 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6000}
10eec955 6001
cf8280ee 6002/**
7086400d
AD		 6003 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6004 * @adapter - the ixgbe adapter structure
cf8280ee 6005 **/
7086400d 6006static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6007{
cf8280ee 6008 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6009 s32 err;
cf8280ee 6010
7086400d
AD		 6011 /* not searching for SFP so there is nothing to do here */
6012 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6013 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6014 return;
10eec955 6015
7086400d
AD		 6016 /* someone else is in init, wait until next service event */
6017 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6018 return;
cf8280ee 6019
7086400d
AD		 6020 err = hw->phy.ops.identify_sfp(hw);
6021 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6022 goto sfp_out;
264857b8 6023
7086400d
AD		 6024 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6025 /* If no cable is present, then we need to reset
6026 * the next time we find a good cable. */
6027 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6028 }
9a799d71 6029
7086400d
AD		 6030 /* exit on error */
6031 if (err)
6032 goto sfp_out;
e8e26350 6033
7086400d
AD		 6034 /* exit if reset not needed */
6035 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6036 goto sfp_out;
9a799d71 6037
7086400d 6038 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6039
7086400d
AD		 6040 /*
6041 * A module may be identified correctly, but the EEPROM may not have
6042 * support for that module. setup_sfp() will fail in that case, so
6043 * we should not allow that module to load.
6044 */
6045 if (hw->mac.type == ixgbe_mac_82598EB)
6046 err = hw->phy.ops.reset(hw);
6047 else
6048 err = hw->mac.ops.setup_sfp(hw);
6049
6050 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6051 goto sfp_out;
6052
6053 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6054 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6055
6056sfp_out:
6057 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6058
6059 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6060 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6061 e_dev_err("failed to initialize because an unsupported "
6062 "SFP+ module type was detected.\n");
6063 e_dev_err("Reload the driver after installing a "
6064 "supported module.\n");
6065 unregister_netdev(adapter->netdev);
bc59fcda 6066 }
7086400d 6067}
bc59fcda 6068
7086400d
AD		 6069/**
6070 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6071 * @adapter - the ixgbe adapter structure
6072 **/
6073static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6074{
6075 struct ixgbe_hw *hw = &adapter->hw;
6076 u32 autoneg;
6077 bool negotiation;
6078
6079 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6080 return;
6081
6082 /* someone else is in init, wait until next service event */
6083 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6084 return;
6085
6086 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6087
6088 autoneg = hw->phy.autoneg_advertised;
6089 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6090 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6091 hw->mac.autotry_restart = false;
6092 if (hw->mac.ops.setup_link)
6093 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6094
6095 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6096 adapter->link_check_timeout = jiffies;
6097 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6098}
6099
6100/**
6101 * ixgbe_service_timer - Timer Call-back
6102 * @data: pointer to adapter cast into an unsigned long
6103 **/
6104static void ixgbe_service_timer(unsigned long data)
6105{
6106 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6107 unsigned long next_event_offset;
6108
6109 /* poll faster when waiting for link */
6110 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6111 next_event_offset = HZ / 10;
6112 else
6113 next_event_offset = HZ * 2;
6114
6115 /* Reset the timer */
6116 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6117
6118 ixgbe_service_event_schedule(adapter);
6119}
6120
c83c6cbd
AD		 6121static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6122{
6123 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6124 return;
6125
6126 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6127
6128 /* If we're already down or resetting, just bail */
6129 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6130 test_bit(__IXGBE_RESETTING, &adapter->state))
6131 return;
6132
6133 ixgbe_dump(adapter);
6134 netdev_err(adapter->netdev, "Reset adapter\n");
6135 adapter->tx_timeout_count++;
6136
6137 ixgbe_reinit_locked(adapter);
6138}
6139
7086400d
AD		 6140/**
6141 * ixgbe_service_task - manages and runs subtasks
6142 * @work: pointer to work_struct containing our data
6143 **/
6144static void ixgbe_service_task(struct work_struct *work)
6145{
6146 struct ixgbe_adapter *adapter = container_of(work,
6147 struct ixgbe_adapter,
6148 service_task);
6149
c83c6cbd 6150 ixgbe_reset_subtask(adapter);
7086400d
AD		 6151 ixgbe_sfp_detection_subtask(adapter);
6152 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6153 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6154 ixgbe_watchdog_subtask(adapter);
d034acf1 6155 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6156 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6157
6158 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6159}
6160
897ab156
AD		 6161void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6162 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6163{
6164 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6165 u16 i = tx_ring->next_to_use;
9a799d71 6166
897ab156 6167 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6168
897ab156
AD		 6169 i++;
6170 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6171
897ab156
AD		 6172 /* set bits to identify this as an advanced context descriptor */
6173 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6174
897ab156
AD		 6175 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6176 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6177 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6178 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6179}
9a799d71 6180
897ab156
AD		 6181static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6182 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6183{
6184 int err;
6185 u32 vlan_macip_lens, type_tucmd;
6186 u32 mss_l4len_idx, l4len;
9a799d71 6187
897ab156
AD		 6188 if (!skb_is_gso(skb))
6189 return 0;
9a799d71 6190
897ab156
AD		 6191 if (skb_header_cloned(skb)) {
6192 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6193 if (err)
6194 return err;
9a799d71 6195 }
9a799d71 6196
897ab156
AD		 6197 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6198 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6199
6200 if (protocol == __constant_htons(ETH_P_IP)) {
6201 struct iphdr *iph = ip_hdr(skb);
6202 iph->tot_len = 0;
6203 iph->check = 0;
6204 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6205 iph->daddr, 0,
6206 IPPROTO_TCP,
6207 0);
6208 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6209 } else if (skb_is_gso_v6(skb)) {
6210 ipv6_hdr(skb)->payload_len = 0;
6211 tcp_hdr(skb)->check =
6212 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6213 &ipv6_hdr(skb)->daddr,
6214 0, IPPROTO_TCP, 0);
6215 }
6216
6217 l4len = tcp_hdrlen(skb);
6218 *hdr_len = skb_transport_offset(skb) + l4len;
6219
6220 /* mss_l4len_id: use 1 as index for TSO */
6221 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6222 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6223 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6224
6225 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6226 vlan_macip_lens = skb_network_header_len(skb);
6227 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6228 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6229
6230 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6231 mss_l4len_idx);
6232
6233 return 1;
6234}
6235
6236static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6237 struct sk_buff *skb, u32 tx_flags,
6238 __be16 protocol)
7ca647bd 6239{
897ab156
AD		 6240 u32 vlan_macip_lens = 0;
6241 u32 mss_l4len_idx = 0;
6242 u32 type_tucmd = 0;
7ca647bd 6243
897ab156 6244 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6245 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6246 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6247 return false;
6248 } else {
6249 u8 l4_hdr = 0;
6250 switch (protocol) {
6251 case __constant_htons(ETH_P_IP):
6252 vlan_macip_lens |= skb_network_header_len(skb);
6253 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6254 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6255 break;
897ab156
AD		 6256 case __constant_htons(ETH_P_IPV6):
6257 vlan_macip_lens |= skb_network_header_len(skb);
6258 l4_hdr = ipv6_hdr(skb)->nexthdr;
6259 break;
6260 default:
6261 if (unlikely(net_ratelimit())) {
6262 dev_warn(tx_ring->dev,
6263 "partial checksum but proto=%x!\n",
6264 skb->protocol);
6265 }
7ca647bd
JP		 6266 break;
6267 }
897ab156
AD		 6268
6269 switch (l4_hdr) {
7ca647bd 6270 case IPPROTO_TCP:
897ab156
AD		 6271 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6272 mss_l4len_idx = tcp_hdrlen(skb) <<
6273 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6274 break;
6275 case IPPROTO_SCTP:
897ab156
AD		 6276 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6277 mss_l4len_idx = sizeof(struct sctphdr) <<
6278 IXGBE_ADVTXD_L4LEN_SHIFT;
6279 break;
6280 case IPPROTO_UDP:
6281 mss_l4len_idx = sizeof(struct udphdr) <<
6282 IXGBE_ADVTXD_L4LEN_SHIFT;
6283 break;
6284 default:
6285 if (unlikely(net_ratelimit())) {
6286 dev_warn(tx_ring->dev,
6287 "partial checksum but l4 proto=%x!\n",
6288 skb->protocol);
6289 }
7ca647bd
JP		 6290 break;
6291 }
7ca647bd
JP		 6292 }
6293
897ab156
AD		 6294 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6295 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6296
897ab156
AD		 6297 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6298 type_tucmd, mss_l4len_idx);
9a799d71 6299
897ab156 6300 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6301}
6302
d3d00239 6303static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6304{
d3d00239
AD		 6305 /* set type for advanced descriptor with frame checksum insertion */
6306 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6307 IXGBE_ADVTXD_DCMD_IFCS |
6308 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6309
d3d00239 6310 /* set HW vlan bit if vlan is present */
66f32a8b 6311 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6312 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6313
d3d00239
AD		 6314 /* set segmentation enable bits for TSO/FSO */
6315#ifdef IXGBE_FCOE
6316 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6317#else
6318 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6319#endif
6320 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6321
d3d00239
AD		 6322 return cmd_type;
6323}
9a799d71 6324
d3d00239
AD		 6325static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6326{
6327 __le32 olinfo_status =
6328 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6329
d3d00239
AD		 6330 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6331 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6332 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6333 /* enble IPv4 checksum for TSO */
6334 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6335 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6336 }
6337
d3d00239
AD		 6338 /* enable L4 checksum for TSO and TX checksum offload */
6339 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6340 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6341
d3d00239
AD		 6342#ifdef IXGBE_FCOE
6343 /* use index 1 context for FCOE/FSO */
6344 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6345 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6346 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6347
d3d00239 6348#endif
7f9643fd
AD		 6349 /*
6350 * Check Context must be set if Tx switch is enabled, which it
6351 * always is for case where virtual functions are running
6352 */
6353 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6354 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6355
d3d00239
AD		 6356 return olinfo_status;
6357}
44df32c5 6358
d3d00239
AD		 6359#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6360 IXGBE_TXD_CMD_RS)
6361
6362static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6363 struct sk_buff *skb,
6364 struct ixgbe_tx_buffer *first,
6365 u32 tx_flags,
6366 const u8 hdr_len)
6367{
6368 struct device *dev = tx_ring->dev;
6369 struct ixgbe_tx_buffer *tx_buffer_info;
6370 union ixgbe_adv_tx_desc *tx_desc;
6371 dma_addr_t dma;
6372 __le32 cmd_type, olinfo_status;
6373 struct skb_frag_struct *frag;
6374 unsigned int f = 0;
6375 unsigned int data_len = skb->data_len;
6376 unsigned int size = skb_headlen(skb);
6377 u32 offset = 0;
6378 u32 paylen = skb->len - hdr_len;
6379 u16 i = tx_ring->next_to_use;
6380 u16 gso_segs;
6381
6382#ifdef IXGBE_FCOE
6383 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6384 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6385 data_len -= sizeof(struct fcoe_crc_eof);
6386 } else {
6387 size -= sizeof(struct fcoe_crc_eof) - data_len;
6388 data_len = 0;
9a799d71
AK		 6389 }
6390 }
44df32c5 6391
d3d00239
AD		 6392#endif
6393 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6394 if (dma_mapping_error(dev, dma))
6395 goto dma_error;
8ad494b0 6396
d3d00239
AD		 6397 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6398 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6399
d3d00239 6400 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
e5a43549 6401
d3d00239
AD		 6402 for (;;) {
6403 while (size > IXGBE_MAX_DATA_PER_TXD) {
6404 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6405 tx_desc->read.cmd_type_len =
6406 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6407 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6408
d3d00239
AD		 6409 offset += IXGBE_MAX_DATA_PER_TXD;
6410 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6411
d3d00239
AD		 6412 tx_desc++;
6413 i++;
6414 if (i == tx_ring->count) {
6415 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6416 i = 0;
6417 }
6418 }
e5a43549 6419
e5a43549 6420 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6421 tx_buffer_info->length = offset + size;
6422 tx_buffer_info->tx_flags = tx_flags;
6423 tx_buffer_info->dma = dma;
9a799d71 6424
d3d00239
AD		 6425 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6426 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6427 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6428
d3d00239
AD		 6429 if (!data_len)
6430 break;
9a799d71 6431
d3d00239
AD		 6432 frag = &skb_shinfo(skb)->frags[f];
6433#ifdef IXGBE_FCOE
6434 size = min_t(unsigned int, data_len, frag->size);
6435#else
6436 size = frag->size;
6437#endif
6438 data_len -= size;
6439 f++;
9a799d71 6440
d3d00239
AD		 6441 offset = 0;
6442 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6443
877749bf 6444 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6445 if (dma_mapping_error(dev, dma))
6446 goto dma_error;
9a799d71 6447
d3d00239
AD		 6448 tx_desc++;
6449 i++;
6450 if (i == tx_ring->count) {
6451 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6452 i = 0;
6453 }
6454 }
9a799d71 6455
d3d00239 6456 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6457
d3d00239
AD		 6458 i++;
6459 if (i == tx_ring->count)
6460 i = 0;
9a799d71 6461
d3d00239 6462 tx_ring->next_to_use = i;
eacd73f7 6463
d3d00239
AD		 6464 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6465 gso_segs = skb_shinfo(skb)->gso_segs;
6466#ifdef IXGBE_FCOE
6467 /* adjust for FCoE Sequence Offload */
6468 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6469 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6470 skb_shinfo(skb)->gso_size);
6471#endif /* IXGBE_FCOE */
6472 else
6473 gso_segs = 1;
9a799d71 6474
d3d00239
AD		 6475 /* multiply data chunks by size of headers */
6476 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6477 tx_buffer_info->gso_segs = gso_segs;
6478 tx_buffer_info->skb = skb;
9a799d71 6479
d3d00239
AD		 6480 /* set the timestamp */
6481 first->time_stamp = jiffies;
9a799d71
AK		 6482
6483 /*
6484 * Force memory writes to complete before letting h/w
6485 * know there are new descriptors to fetch. (Only
6486 * applicable for weak-ordered memory model archs,
6487 * such as IA-64).
6488 */
6489 wmb();
6490
d3d00239
AD		 6491 /* set next_to_watch value indicating a packet is present */
6492 first->next_to_watch = tx_desc;
6493
6494 /* notify HW of packet */
84ea2591 6495 writel(i, tx_ring->tail);
d3d00239
AD		 6496
6497 return;
6498dma_error:
6499 dev_err(dev, "TX DMA map failed\n");
6500
6501 /* clear dma mappings for failed tx_buffer_info map */
6502 for (;;) {
6503 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6504 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6505 if (tx_buffer_info == first)
6506 break;
6507 if (i == 0)
6508 i = tx_ring->count;
6509 i--;
6510 }
6511
6512 dev_kfree_skb_any(skb);
6513
6514 tx_ring->next_to_use = i;
9a799d71
AK		 6515}
6516
69830529
AD		 6517static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6518 u32 tx_flags, __be16 protocol)
6519{
6520 struct ixgbe_q_vector *q_vector = ring->q_vector;
6521 union ixgbe_atr_hash_dword input = { .dword = 0 };
6522 union ixgbe_atr_hash_dword common = { .dword = 0 };
6523 union {
6524 unsigned char *network;
6525 struct iphdr *ipv4;
6526 struct ipv6hdr *ipv6;
6527 } hdr;
ee9e0f0b 6528 struct tcphdr *th;
905e4a41 6529 __be16 vlan_id;
c4cf55e5 6530
69830529
AD		 6531 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6532 if (!q_vector)
6533 return;
6534
6535 /* do nothing if sampling is disabled */
6536 if (!ring->atr_sample_rate)
d3ead241 6537 return;
c4cf55e5 6538
69830529 6539 ring->atr_count++;
c4cf55e5 6540
69830529
AD		 6541 /* snag network header to get L4 type and address */
6542 hdr.network = skb_network_header(skb);
6543
6544 /* Currently only IPv4/IPv6 with TCP is supported */
6545 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6546 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6547 (protocol != __constant_htons(ETH_P_IP) ||
6548 hdr.ipv4->protocol != IPPROTO_TCP))
6549 return;
ee9e0f0b
AD		 6550
6551 th = tcp_hdr(skb);
c4cf55e5 6552
66f32a8b
AD		 6553 /* skip this packet since it is invalid or the socket is closing */
6554 if (!th || th->fin)
69830529
AD		 6555 return;
6556
6557 /* sample on all syn packets or once every atr sample count */
6558 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6559 return;
6560
6561 /* reset sample count */
6562 ring->atr_count = 0;
6563
6564 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6565
6566 /*
6567 * src and dst are inverted, think how the receiver sees them
6568 *
6569 * The input is broken into two sections, a non-compressed section
6570 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6571 * is XORed together and stored in the compressed dword.
6572 */
6573 input.formatted.vlan_id = vlan_id;
6574
6575 /*
6576 * since src port and flex bytes occupy the same word XOR them together
6577 * and write the value to source port portion of compressed dword
6578 */
66f32a8b 6579 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6580 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6581 else
6582 common.port.src ^= th->dest ^ protocol;
6583 common.port.dst ^= th->source;
6584
6585 if (protocol == __constant_htons(ETH_P_IP)) {
6586 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6587 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6588 } else {
6589 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6590 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6591 hdr.ipv6->saddr.s6_addr32[1] ^
6592 hdr.ipv6->saddr.s6_addr32[2] ^
6593 hdr.ipv6->saddr.s6_addr32[3] ^
6594 hdr.ipv6->daddr.s6_addr32[0] ^
6595 hdr.ipv6->daddr.s6_addr32[1] ^
6596 hdr.ipv6->daddr.s6_addr32[2] ^
6597 hdr.ipv6->daddr.s6_addr32[3];
6598 }
c4cf55e5
PWJ		 6599
6600 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6601 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6602 input, common, ring->queue_index);
c4cf55e5
PWJ		 6603}
6604
63544e9c 6605static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6606{
fc77dc3c 6607 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6608 /* Herbert's original patch had:
6609 * smp_mb__after_netif_stop_queue();
6610 * but since that doesn't exist yet, just open code it. */
6611 smp_mb();
6612
6613 /* We need to check again in a case another CPU has just
6614 * made room available. */
7d4987de 6615 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6616 return -EBUSY;
6617
6618 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6619 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6620 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6621 return 0;
6622}
6623
82d4e46e 6624static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6625{
7d4987de 6626 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6627 return 0;
fc77dc3c 6628 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6629}
6630
09a3b1f8
SH		 6631static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6632{
6633 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6634 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6635 smp_processor_id();
56075a98 6636#ifdef IXGBE_FCOE
6440752c 6637 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6638
e5b64635
JF		 6639 if (((protocol == htons(ETH_P_FCOE)) ||
6640 (protocol == htons(ETH_P_FIP))) &&
6641 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6642 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6643 txq += adapter->ring_feature[RING_F_FCOE].mask;
6644 return txq;
56075a98
JF		 6645 }
6646#endif
6647
fdd3d631
KK		 6648 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6649 while (unlikely(txq >= dev->real_num_tx_queues))
6650 txq -= dev->real_num_tx_queues;
5f715823 6651 return txq;
fdd3d631 6652 }
c4cf55e5 6653
09a3b1f8
SH		 6654 return skb_tx_hash(dev, skb);
6655}
6656
fc77dc3c 6657netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6658 struct ixgbe_adapter *adapter,
6659 struct ixgbe_ring *tx_ring)
9a799d71 6660{
d3d00239 6661 struct ixgbe_tx_buffer *first;
5f715823 6662 int tso;
d3d00239 6663 u32 tx_flags = 0;
a535c30e
AD		 6664#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6665 unsigned short f;
6666#endif
a535c30e 6667 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6668 __be16 protocol = skb->protocol;
63544e9c 6669 u8 hdr_len = 0;
5e09a105 6670
a535c30e
AD		 6671 /*
6672 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6673 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6674 * + 2 desc gap to keep tail from touching head,
6675 * + 1 desc for context descriptor,
6676 * otherwise try next time
6677 */
6678#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6679 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6680 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6681#else
6682 count += skb_shinfo(skb)->nr_frags;
6683#endif
6684 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6685 tx_ring->tx_stats.tx_busy++;
6686 return NETDEV_TX_BUSY;
6687 }
6688
7f9643fd
AD		 6689#ifdef CONFIG_PCI_IOV
6690 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6691 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6692
6693#endif
66f32a8b 6694 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6695 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6696 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6697 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6698 /* else if it is a SW VLAN check the next protocol and store the tag */
6699 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6700 struct vlan_hdr *vhdr, _vhdr;
6701 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6702 if (!vhdr)
6703 goto out_drop;
6704
6705 protocol = vhdr->h_vlan_encapsulated_proto;
6706 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6707 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6708 }
6709
32701dc2 6710 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6711 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6712 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6713 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6714 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6715 tx_flags |= (skb->priority & 0x7) <<
6716 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6717 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6718 struct vlan_ethhdr *vhdr;
6719 if (skb_header_cloned(skb) &&
6720 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6721 goto out_drop;
6722 vhdr = (struct vlan_ethhdr *)skb->data;
6723 vhdr->h_vlan_TCI = htons(tx_flags >>
6724 IXGBE_TX_FLAGS_VLAN_SHIFT);
6725 } else {
6726 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6727 }
9a799d71 6728 }
eacd73f7 6729
a535c30e 6730 /* record the location of the first descriptor for this packet */
d3d00239 6731 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 6732
eacd73f7 6733#ifdef IXGBE_FCOE
66f32a8b
AD		 6734 /* setup tx offload for FCoE */
6735 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6736 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 6737 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6738 if (tso < 0)
6739 goto out_drop;
6740 else if (tso)
66f32a8b
AD		 6741 tx_flags |= IXGBE_TX_FLAGS_FSO |
6742 IXGBE_TX_FLAGS_FCOE;
6743 else
6744 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6745
66f32a8b 6746 goto xmit_fcoe;
eacd73f7 6747 }
9a799d71 6748
66f32a8b
AD		 6749#endif /* IXGBE_FCOE */
6750 /* setup IPv4/IPv6 offloads */
6751 if (protocol == __constant_htons(ETH_P_IP))
6752 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 6753
66f32a8b
AD		 6754 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6755 if (tso < 0)
897ab156 6756 goto out_drop;
66f32a8b
AD		 6757 else if (tso)
6758 tx_flags |= IXGBE_TX_FLAGS_TSO;
6759 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6760 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6761
6762 /* add the ATR filter if ATR is on */
6763 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6764 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6765
6766#ifdef IXGBE_FCOE
6767xmit_fcoe:
6768#endif /* IXGBE_FCOE */
d3d00239
AD		 6769 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6770
6771 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6772
6773 return NETDEV_TX_OK;
897ab156
AD		 6774
6775out_drop:
6776 dev_kfree_skb_any(skb);
6777 return NETDEV_TX_OK;
9a799d71
AK		 6778}
6779
84418e3b
AD		 6780static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6781{
6782 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6783 struct ixgbe_ring *tx_ring;
6784
6785 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6786 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6787}
6788
9a799d71
AK		 6789/**
6790 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6791 * @netdev: network interface device structure
6792 * @p: pointer to an address structure
6793 *
6794 * Returns 0 on success, negative on failure
6795 **/
6796static int ixgbe_set_mac(struct net_device *netdev, void *p)
6797{
6798 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6799 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6800 struct sockaddr *addr = p;
6801
6802 if (!is_valid_ether_addr(addr->sa_data))
6803 return -EADDRNOTAVAIL;
6804
6805 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6806 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6807
1cdd1ec8
GR		 6808 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6809 IXGBE_RAH_AV);
9a799d71
AK		 6810
6811 return 0;
6812}
6813
6b73e10d
BH		 6814static int
6815ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6816{
6817 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6818 struct ixgbe_hw *hw = &adapter->hw;
6819 u16 value;
6820 int rc;
6821
6822 if (prtad != hw->phy.mdio.prtad)
6823 return -EINVAL;
6824 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6825 if (!rc)
6826 rc = value;
6827 return rc;
6828}
6829
6830static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6831 u16 addr, u16 value)
6832{
6833 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6834 struct ixgbe_hw *hw = &adapter->hw;
6835
6836 if (prtad != hw->phy.mdio.prtad)
6837 return -EINVAL;
6838 return hw->phy.ops.write_reg(hw, addr, devad, value);
6839}
6840
6841static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6842{
6843 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6844
6845 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6846}
6847
0365e6e4
PW		 6848/**
6849 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6850 * netdev->dev_addrs
0365e6e4
PW		 6851 * @netdev: network interface device structure
6852 *
6853 * Returns non-zero on failure
6854 **/
6855static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6856{
6857 int err = 0;
6858 struct ixgbe_adapter *adapter = netdev_priv(dev);
6859 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6860
6861 if (is_valid_ether_addr(mac->san_addr)) {
6862 rtnl_lock();
6863 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6864 rtnl_unlock();
6865 }
6866 return err;
6867}
6868
6869/**
6870 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6871 * netdev->dev_addrs
0365e6e4
PW		 6872 * @netdev: network interface device structure
6873 *
6874 * Returns non-zero on failure
6875 **/
6876static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6877{
6878 int err = 0;
6879 struct ixgbe_adapter *adapter = netdev_priv(dev);
6880 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6881
6882 if (is_valid_ether_addr(mac->san_addr)) {
6883 rtnl_lock();
6884 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6885 rtnl_unlock();
6886 }
6887 return err;
6888}
6889
9a799d71
AK		 6890#ifdef CONFIG_NET_POLL_CONTROLLER
6891/*
6892 * Polling 'interrupt' - used by things like netconsole to send skbs
6893 * without having to re-enable interrupts. It's not called while
6894 * the interrupt routine is executing.
6895 */
6896static void ixgbe_netpoll(struct net_device *netdev)
6897{
6898 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6899 int i;
9a799d71 6900
1a647bd2
AD		 6901 /* if interface is down do nothing */
6902 if (test_bit(__IXGBE_DOWN, &adapter->state))
6903 return;
6904
9a799d71 6905 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6906 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6907 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6908 for (i = 0; i < num_q_vectors; i++) {
6909 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 6910 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 6911 }
6912 } else {
6913 ixgbe_intr(adapter->pdev->irq, netdev);
6914 }
9a799d71 6915 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6916}
6917#endif
6918
de1036b1
ED		 6919static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6920 struct rtnl_link_stats64 *stats)
6921{
6922 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6923 int i;
6924
1a51502b 6925 rcu_read_lock();
de1036b1 6926 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6927 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6928 u64 bytes, packets;
6929 unsigned int start;
6930
1a51502b
ED		 6931 if (ring) {
6932 do {
6933 start = u64_stats_fetch_begin_bh(&ring->syncp);
6934 packets = ring->stats.packets;
6935 bytes = ring->stats.bytes;
6936 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6937 stats->rx_packets += packets;
6938 stats->rx_bytes += bytes;
6939 }
de1036b1 6940 }
1ac9ad13
ED		 6941
6942 for (i = 0; i < adapter->num_tx_queues; i++) {
6943 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6944 u64 bytes, packets;
6945 unsigned int start;
6946
6947 if (ring) {
6948 do {
6949 start = u64_stats_fetch_begin_bh(&ring->syncp);
6950 packets = ring->stats.packets;
6951 bytes = ring->stats.bytes;
6952 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6953 stats->tx_packets += packets;
6954 stats->tx_bytes += bytes;
6955 }
6956 }
1a51502b 6957 rcu_read_unlock();
de1036b1
ED		 6958 /* following stats updated by ixgbe_watchdog_task() */
6959 stats->multicast = netdev->stats.multicast;
6960 stats->rx_errors = netdev->stats.rx_errors;
6961 stats->rx_length_errors = netdev->stats.rx_length_errors;
6962 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6963 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6964 return stats;
6965}
6966
8b1c0b24
JF		 6967/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6968 * #adapter: pointer to ixgbe_adapter
6969 * @tc: number of traffic classes currently enabled
6970 *
6971 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6972 * 802.1Q priority maps to a packet buffer that exists.
6973 */
6974static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6975{
6976 struct ixgbe_hw *hw = &adapter->hw;
6977 u32 reg, rsave;
6978 int i;
6979
6980 /* 82598 have a static priority to TC mapping that can not
6981 * be changed so no validation is needed.
6982 */
6983 if (hw->mac.type == ixgbe_mac_82598EB)
6984 return;
6985
6986 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6987 rsave = reg;
6988
6989 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6990 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6991
6992 /* If up2tc is out of bounds default to zero */
6993 if (up2tc > tc)
6994 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6995 }
6996
6997 if (reg != rsave)
6998 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6999
7000 return;
7001}
7002
7003
7004/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7005 * classes.
7006 *
7007 * @netdev: net device to configure
7008 * @tc: number of traffic classes to enable
7009 */
7010int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7011{
8b1c0b24
JF		 7012 struct ixgbe_adapter *adapter = netdev_priv(dev);
7013 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7014
e7589eab
JF		 7015 /* Multiple traffic classes requires multiple queues */
7016 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7017 e_err(drv, "Enable failed, needs MSI-X\n");
7018 return -EINVAL;
7019 }
8b1c0b24
JF		 7020
7021 /* Hardware supports up to 8 traffic classes */
7022 if (tc > MAX_TRAFFIC_CLASS ||
7023 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7024 return -EINVAL;
7025
7026 /* Hardware has to reinitialize queues and interrupts to
7027 * match packet buffer alignment. Unfortunantly, the
7028 * hardware is not flexible enough to do this dynamically.
7029 */
7030 if (netif_running(dev))
7031 ixgbe_close(dev);
7032 ixgbe_clear_interrupt_scheme(adapter);
7033
e7589eab 7034 if (tc) {
8b1c0b24 7035 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7036 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7037
7038 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7039 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7040
7041 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7042 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7043 } else {
8b1c0b24
JF		 7044 netdev_reset_tc(dev);
7045
e7589eab
JF		 7046 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7047
7048 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7049 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7050
7051 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7052 adapter->dcb_cfg.pfc_mode_enable = false;
7053 }
7054
8b1c0b24
JF		 7055 ixgbe_init_interrupt_scheme(adapter);
7056 ixgbe_validate_rtr(adapter, tc);
7057 if (netif_running(dev))
7058 ixgbe_open(dev);
7059
7060 return 0;
7061}
de1036b1 7062
082757af
DS		 7063void ixgbe_do_reset(struct net_device *netdev)
7064{
7065 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7066
7067 if (netif_running(netdev))
7068 ixgbe_reinit_locked(adapter);
7069 else
7070 ixgbe_reset(adapter);
7071}
7072
7073static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7074{
7075 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7076
7077#ifdef CONFIG_DCB
7078 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7079 data &= ~NETIF_F_HW_VLAN_RX;
7080#endif
7081
7082 /* return error if RXHASH is being enabled when RSS is not supported */
7083 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7084 data &= ~NETIF_F_RXHASH;
7085
7086 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7087 if (!(data & NETIF_F_RXCSUM))
7088 data &= ~NETIF_F_LRO;
7089
7090 /* Turn off LRO if not RSC capable or invalid ITR settings */
7091 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7092 data &= ~NETIF_F_LRO;
7093 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7094 (adapter->rx_itr_setting != 1 &&
7095 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7096 data &= ~NETIF_F_LRO;
7097 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7098 }
7099
7100 return data;
7101}
7102
7103static int ixgbe_set_features(struct net_device *netdev, u32 data)
7104{
7105 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7106 bool need_reset = false;
7107
7108 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7109 if (!(data & NETIF_F_RXCSUM))
7110 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7111 else
7112 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7113
7114 /* Make sure RSC matches LRO, reset if change */
7115 if (!!(data & NETIF_F_LRO) !=
7116 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7117 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7118 switch (adapter->hw.mac.type) {
7119 case ixgbe_mac_X540:
7120 case ixgbe_mac_82599EB:
7121 need_reset = true;
7122 break;
7123 default:
7124 break;
7125 }
7126 }
7127
7128 /*
7129 * Check if Flow Director n-tuple support was enabled or disabled. If
7130 * the state changed, we need to reset.
7131 */
7132 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7133 /* turn off ATR, enable perfect filters and reset */
7134 if (data & NETIF_F_NTUPLE) {
7135 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7136 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7137 need_reset = true;
7138 }
7139 } else if (!(data & NETIF_F_NTUPLE)) {
7140 /* turn off Flow Director, set ATR and reset */
7141 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7142 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7143 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7144 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7145 need_reset = true;
7146 }
7147
7148 if (need_reset)
7149 ixgbe_do_reset(netdev);
7150
7151 return 0;
7152
7153}
7154
0edc3527 7155static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7156 .ndo_open = ixgbe_open,
0edc3527 7157 .ndo_stop = ixgbe_close,
00829823 7158 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7159 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7160 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7161 .ndo_validate_addr = eth_validate_addr,
7162 .ndo_set_mac_address = ixgbe_set_mac,
7163 .ndo_change_mtu = ixgbe_change_mtu,
7164 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7165 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7166 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7167 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7168 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7169 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7170 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7171 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7172 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7173 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7174#ifdef CONFIG_NET_POLL_CONTROLLER
7175 .ndo_poll_controller = ixgbe_netpoll,
7176#endif
332d4a7d
YZ		 7177#ifdef IXGBE_FCOE
7178 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7179 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7180 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7181 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7182 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7183 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7184#endif /* IXGBE_FCOE */
082757af
DS		 7185 .ndo_set_features = ixgbe_set_features,
7186 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7187};
7188
1cdd1ec8
GR		 7189static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7190 const struct ixgbe_info *ii)
7191{
7192#ifdef CONFIG_PCI_IOV
7193 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7194
c6bda30a 7195 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7196 return;
7197
7198 /* The 82599 supports up to 64 VFs per physical function
7199 * but this implementation limits allocation to 63 so that
7200 * basic networking resources are still available to the
7201 * physical function
7202 */
7203 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7204 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7205#endif /* CONFIG_PCI_IOV */
7206}
7207
9a799d71
AK		 7208/**
7209 * ixgbe_probe - Device Initialization Routine
7210 * @pdev: PCI device information struct
7211 * @ent: entry in ixgbe_pci_tbl
7212 *
7213 * Returns 0 on success, negative on failure
7214 *
7215 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7216 * The OS initialization, configuring of the adapter private structure,
7217 * and a hardware reset occur.
7218 **/
7219static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7220 const struct pci_device_id *ent)
9a799d71
AK		 7221{
7222 struct net_device *netdev;
7223 struct ixgbe_adapter *adapter = NULL;
7224 struct ixgbe_hw *hw;
7225 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7226 static int cards_found;
7227 int i, err, pci_using_dac;
289700db 7228 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7229 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7230#ifdef IXGBE_FCOE
7231 u16 device_caps;
7232#endif
289700db 7233 u32 eec;
c23f5b6b 7234 u16 wol_cap;
9a799d71 7235
bded64a7
AG		 7236 /* Catch broken hardware that put the wrong VF device ID in
7237 * the PCIe SR-IOV capability.
7238 */
7239 if (pdev->is_virtfn) {
7240 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7241 pci_name(pdev), pdev->vendor, pdev->device);
7242 return -EINVAL;
7243 }
7244
9ce77666 7245 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7246 if (err)
7247 return err;
7248
1b507730
NN		 7249 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7250 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7251 pci_using_dac = 1;
7252 } else {
1b507730 7253 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7254 if (err) {
1b507730
NN		 7255 err = dma_set_coherent_mask(&pdev->dev,
7256 DMA_BIT_MASK(32));
9a799d71 7257 if (err) {
b8bc0421
DC		 7258 dev_err(&pdev->dev,
7259 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7260 goto err_dma;
7261 }
7262 }
7263 pci_using_dac = 0;
7264 }
7265
9ce77666 7266 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7267 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7268 if (err) {
b8bc0421
DC		 7269 dev_err(&pdev->dev,
7270 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7271 goto err_pci_reg;
7272 }
7273
19d5afd4 7274 pci_enable_pcie_error_reporting(pdev);
6fabd715 7275
9a799d71 7276 pci_set_master(pdev);
fb3b27bc 7277 pci_save_state(pdev);
9a799d71 7278
e901acd6
JF		 7279#ifdef CONFIG_IXGBE_DCB
7280 indices *= MAX_TRAFFIC_CLASS;
7281#endif
7282
c85a2618
JF		 7283 if (ii->mac == ixgbe_mac_82598EB)
7284 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7285 else
7286 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7287
e901acd6 7288#ifdef IXGBE_FCOE
c85a2618
JF		 7289 indices += min_t(unsigned int, num_possible_cpus(),
7290 IXGBE_MAX_FCOE_INDICES);
7291#endif
c85a2618 7292 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7293 if (!netdev) {
7294 err = -ENOMEM;
7295 goto err_alloc_etherdev;
7296 }
7297
9a799d71
AK		 7298 SET_NETDEV_DEV(netdev, &pdev->dev);
7299
9a799d71 7300 adapter = netdev_priv(netdev);
c60fbb00 7301 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7302
7303 adapter->netdev = netdev;
7304 adapter->pdev = pdev;
7305 hw = &adapter->hw;
7306 hw->back = adapter;
7307 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7308
05857980 7309 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7310 pci_resource_len(pdev, 0));
9a799d71
AK		 7311 if (!hw->hw_addr) {
7312 err = -EIO;
7313 goto err_ioremap;
7314 }
7315
7316 for (i = 1; i <= 5; i++) {
7317 if (pci_resource_len(pdev, i) == 0)
7318 continue;
7319 }
7320
0edc3527 7321 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7322 ixgbe_set_ethtool_ops(netdev);
9a799d71 7323 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7324 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7325
9a799d71
AK		 7326 adapter->bd_number = cards_found;
7327
9a799d71
AK		 7328 /* Setup hw api */
7329 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7330 hw->mac.type = ii->mac;
9a799d71 7331
c44ade9e
JB		 7332 /* EEPROM */
7333 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7334 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7335 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7336 if (!(eec & (1 << 8)))
7337 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7338
7339 /* PHY */
7340 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7341 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7342 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7343 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7344 hw->phy.mdio.mmds = 0;
7345 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7346 hw->phy.mdio.dev = netdev;
7347 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7348 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7349
8ca783ab 7350 ii->get_invariants(hw);
9a799d71
AK		 7351
7352 /* setup the private structure */
7353 err = ixgbe_sw_init(adapter);
7354 if (err)
7355 goto err_sw_init;
7356
e86bff0e 7357 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7358 switch (adapter->hw.mac.type) {
7359 case ixgbe_mac_82599EB:
7360 case ixgbe_mac_X540:
e86bff0e 7361 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7362 break;
7363 default:
7364 break;
7365 }
e86bff0e 7366
bf069c97
DS		 7367 /*
7368 * If there is a fan on this device and it has failed log the
7369 * failure.
7370 */
7371 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7372 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7373 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7374 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7375 }
7376
c44ade9e 7377 /* reset_hw fills in the perm_addr as well */
119fc60a 7378 hw->phy.reset_if_overtemp = true;
c44ade9e 7379 err = hw->mac.ops.reset_hw(hw);
119fc60a 7380 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7381 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7382 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7383 err = 0;
7384 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7385 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7386 "module type was detected.\n");
7387 e_dev_err("Reload the driver after installing a supported "
7388 "module.\n");
04f165ef
PW		 7389 goto err_sw_init;
7390 } else if (err) {
849c4542 7391 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7392 goto err_sw_init;
7393 }
7394
1cdd1ec8
GR		 7395 ixgbe_probe_vf(adapter, ii);
7396
396e799c 7397 netdev->features = NETIF_F_SG |
e8e9f696 7398 NETIF_F_IP_CSUM |
082757af 7399 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7400 NETIF_F_HW_VLAN_TX |
7401 NETIF_F_HW_VLAN_RX |
082757af
DS		 7402 NETIF_F_HW_VLAN_FILTER |
7403 NETIF_F_TSO |
7404 NETIF_F_TSO6 |
082757af
DS		 7405 NETIF_F_RXHASH |
7406 NETIF_F_RXCSUM;
9a799d71 7407
082757af 7408 netdev->hw_features = netdev->features;
ad31c402 7409
58be7666
DS		 7410 switch (adapter->hw.mac.type) {
7411 case ixgbe_mac_82599EB:
7412 case ixgbe_mac_X540:
45a5ead0 7413 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7414 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7415 NETIF_F_NTUPLE;
58be7666
DS		 7416 break;
7417 default:
7418 break;
7419 }
45a5ead0 7420
ad31c402
JK		 7421 netdev->vlan_features |= NETIF_F_TSO;
7422 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7423 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7424 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7425 netdev->vlan_features |= NETIF_F_SG;
7426
01789349
JP		 7427 netdev->priv_flags |= IFF_UNICAST_FLT;
7428
1cdd1ec8
GR		 7429 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7430 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7431 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7432
7a6b6f51 7433#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7434 netdev->dcbnl_ops = &dcbnl_ops;
7435#endif
7436
eacd73f7 7437#ifdef IXGBE_FCOE
0d551589 7438 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7439 if (hw->mac.ops.get_device_caps) {
7440 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7441 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7442 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7443 }
7444 }
5e09d7f6
YZ		 7445 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7446 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7447 netdev->vlan_features |= NETIF_F_FSO;
7448 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7449 }
eacd73f7 7450#endif /* IXGBE_FCOE */
7b872a55 7451 if (pci_using_dac) {
9a799d71 7452 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7453 netdev->vlan_features |= NETIF_F_HIGHDMA;
7454 }
9a799d71 7455
082757af
DS		 7456 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7457 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7458 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7459 netdev->features |= NETIF_F_LRO;
7460
9a799d71 7461 /* make sure the EEPROM is good */
c44ade9e 7462 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7463 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7464 err = -EIO;
7465 goto err_eeprom;
7466 }
7467
7468 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7469 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7470
c44ade9e 7471 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7472 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7473 err = -EIO;
7474 goto err_eeprom;
7475 }
7476
c6ecf39a
DS		 7477 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7478 if (hw->mac.ops.disable_tx_laser &&
7479 ((hw->phy.multispeed_fiber) ||
9f911707 7480 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7481 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7482 hw->mac.ops.disable_tx_laser(hw);
7483
7086400d
AD		 7484 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7485 (unsigned long) adapter);
9a799d71 7486
7086400d
AD		 7487 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7488 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7489
021230d4
AV		 7490 err = ixgbe_init_interrupt_scheme(adapter);
7491 if (err)
7492 goto err_sw_init;
9a799d71 7493
082757af
DS		 7494 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7495 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7496 netdev->features &= ~NETIF_F_RXHASH;
082757af 7497 }
67a74ee2 7498
c23f5b6b
ET		 7499 /* WOL not supported for all but the following */
7500 adapter->wol = 0;
e8e26350 7501 switch (pdev->device) {
0b077fea
DS		 7502 case IXGBE_DEV_ID_82599_SFP:
7503 /* Only this subdevice supports WOL */
7504 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
9417c464 7505 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7506 break;
50d6c681
AD		 7507 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7508 /* All except this subdevice support WOL */
0b077fea 7509 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7510 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7511 break;
e8e26350 7512 case IXGBE_DEV_ID_82599_KX4:
9417c464 7513 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7514 break;
c23f5b6b
ET		 7515 case IXGBE_DEV_ID_X540T:
7516 /* Check eeprom to see if it is enabled */
7517 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7518 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7519
7520 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7521 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7522 (hw->bus.func == 0)))
7523 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7524 break;
7525 }
e8e26350
PW		 7526 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7527
04f165ef
PW		 7528 /* pick up the PCI bus settings for reporting later */
7529 hw->mac.ops.get_bus_info(hw);
7530
9a799d71 7531 /* print bus type/speed/width info */
849c4542 7532 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7533 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7534 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7535 "Unknown"),
7536 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7537 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7538 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7539 "Unknown"),
7540 netdev->dev_addr);
289700db
DS		 7541
7542 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7543 if (err)
9fe93afd 7544 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7545 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7546 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7547 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7548 part_str);
e8e26350 7549 else
289700db
DS		 7550 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7551 hw->mac.type, hw->phy.type, part_str);
9a799d71 7552
e8e26350 7553 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7554 e_dev_warn("PCI-Express bandwidth available for this card is "
7555 "not sufficient for optimal performance.\n");
7556 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7557 "is required.\n");
0c254d86
AK		 7558 }
7559
34b0368c
PWJ		 7560 /* save off EEPROM version number */
7561 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7562
9a799d71 7563 /* reset the hardware with the new settings */
794caeb2 7564 err = hw->mac.ops.start_hw(hw);
c44ade9e 7565
794caeb2
PWJ		 7566 if (err == IXGBE_ERR_EEPROM_VERSION) {
7567 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7568 e_dev_warn("This device is a pre-production adapter/LOM. "
7569 "Please be aware there may be issues associated "
7570 "with your hardware. If you are experiencing "
7571 "problems please contact your Intel or hardware "
7572 "representative who provided you with this "
7573 "hardware.\n");
794caeb2 7574 }
9a799d71
AK		 7575 strcpy(netdev->name, "eth%d");
7576 err = register_netdev(netdev);
7577 if (err)
7578 goto err_register;
7579
54386467
JB		 7580 /* carrier off reporting is important to ethtool even BEFORE open */
7581 netif_carrier_off(netdev);
7582
5dd2d332 7583#ifdef CONFIG_IXGBE_DCA
652f093f 7584 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7585 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7586 ixgbe_setup_dca(adapter);
7587 }
7588#endif
1cdd1ec8 7589 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7590 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7591 for (i = 0; i < adapter->num_vfs; i++)
7592 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7593 }
7594
2466dd9c
JK		 7595 /* firmware requires driver version to be 0xFFFFFFFF
7596 * since os does not support feature
7597 */
9612de92 7598 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7599 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7600 0xFF);
9612de92 7601
0365e6e4
PW		 7602 /* add san mac addr to netdev */
7603 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7604
849c4542 7605 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7606 cards_found++;
7607 return 0;
7608
7609err_register:
5eba3699 7610 ixgbe_release_hw_control(adapter);
7a921c93 7611 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7612err_sw_init:
7613err_eeprom:
1cdd1ec8
GR		 7614 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7615 ixgbe_disable_sriov(adapter);
7086400d 7616 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7617 iounmap(hw->hw_addr);
7618err_ioremap:
7619 free_netdev(netdev);
7620err_alloc_etherdev:
e8e9f696
JP		 7621 pci_release_selected_regions(pdev,
7622 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7623err_pci_reg:
7624err_dma:
7625 pci_disable_device(pdev);
7626 return err;
7627}
7628
7629/**
7630 * ixgbe_remove - Device Removal Routine
7631 * @pdev: PCI device information struct
7632 *
7633 * ixgbe_remove is called by the PCI subsystem to alert the driver
7634 * that it should release a PCI device. The could be caused by a
7635 * Hot-Plug event, or because the driver is going to be removed from
7636 * memory.
7637 **/
7638static void __devexit ixgbe_remove(struct pci_dev *pdev)
7639{
c60fbb00
AD		 7640 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7641 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7642
7643 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7644 cancel_work_sync(&adapter->service_task);
9a799d71 7645
5dd2d332 7646#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7647 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7648 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7649 dca_remove_requester(&pdev->dev);
7650 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7651 }
7652
7653#endif
332d4a7d
YZ		 7654#ifdef IXGBE_FCOE
7655 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7656 ixgbe_cleanup_fcoe(adapter);
7657
7658#endif /* IXGBE_FCOE */
0365e6e4
PW		 7659
7660 /* remove the added san mac */
7661 ixgbe_del_sanmac_netdev(netdev);
7662
c4900be0
DS		 7663 if (netdev->reg_state == NETREG_REGISTERED)
7664 unregister_netdev(netdev);
9a799d71 7665
c6bda30a
GR		 7666 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7667 if (!(ixgbe_check_vf_assignment(adapter)))
7668 ixgbe_disable_sriov(adapter);
7669 else
7670 e_dev_warn("Unloading driver while VFs are assigned "
7671 "- VFs will not be deallocated\n");
7672 }
1cdd1ec8 7673
7a921c93 7674 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7675
021230d4 7676 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7677
7678 iounmap(adapter->hw.hw_addr);
9ce77666 7679 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7680 IORESOURCE_MEM));
9a799d71 7681
849c4542 7682 e_dev_info("complete\n");
021230d4 7683
9a799d71
AK		 7684 free_netdev(netdev);
7685
19d5afd4 7686 pci_disable_pcie_error_reporting(pdev);
6fabd715 7687
9a799d71
AK		 7688 pci_disable_device(pdev);
7689}
7690
7691/**
7692 * ixgbe_io_error_detected - called when PCI error is detected
7693 * @pdev: Pointer to PCI device
7694 * @state: The current pci connection state
7695 *
7696 * This function is called after a PCI bus error affecting
7697 * this device has been detected.
7698 */
7699static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7700 pci_channel_state_t state)
9a799d71 7701{
c60fbb00
AD		 7702 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7703 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7704
7705 netif_device_detach(netdev);
7706
3044b8d1
BL		 7707 if (state == pci_channel_io_perm_failure)
7708 return PCI_ERS_RESULT_DISCONNECT;
7709
9a799d71
AK		 7710 if (netif_running(netdev))
7711 ixgbe_down(adapter);
7712 pci_disable_device(pdev);
7713
b4617240 7714 /* Request a slot reset. */
9a799d71
AK		 7715 return PCI_ERS_RESULT_NEED_RESET;
7716}
7717
7718/**
7719 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7720 * @pdev: Pointer to PCI device
7721 *
7722 * Restart the card from scratch, as if from a cold-boot.
7723 */
7724static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7725{
c60fbb00 7726 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7727 pci_ers_result_t result;
7728 int err;
9a799d71 7729
9ce77666 7730 if (pci_enable_device_mem(pdev)) {
396e799c 7731 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7732 result = PCI_ERS_RESULT_DISCONNECT;
7733 } else {
7734 pci_set_master(pdev);
7735 pci_restore_state(pdev);
c0e1f68b 7736 pci_save_state(pdev);
9a799d71 7737
dd4d8ca6 7738 pci_wake_from_d3(pdev, false);
9a799d71 7739
6fabd715 7740 ixgbe_reset(adapter);
88512539 7741 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7742 result = PCI_ERS_RESULT_RECOVERED;
7743 }
7744
7745 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7746 if (err) {
849c4542
ET		 7747 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7748 "failed 0x%0x\n", err);
6fabd715
PWJ		 7749 /* non-fatal, continue */
7750 }
9a799d71 7751
6fabd715 7752 return result;
9a799d71
AK		 7753}
7754
7755/**
7756 * ixgbe_io_resume - called when traffic can start flowing again.
7757 * @pdev: Pointer to PCI device
7758 *
7759 * This callback is called when the error recovery driver tells us that
7760 * its OK to resume normal operation.
7761 */
7762static void ixgbe_io_resume(struct pci_dev *pdev)
7763{
c60fbb00
AD		 7764 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7765 struct net_device *netdev = adapter->netdev;
9a799d71 7766
c7ccde0f
AD		 7767 if (netif_running(netdev))
7768 ixgbe_up(adapter);
9a799d71
AK		 7769
7770 netif_device_attach(netdev);
9a799d71
AK		 7771}
7772
7773static struct pci_error_handlers ixgbe_err_handler = {
7774 .error_detected = ixgbe_io_error_detected,
7775 .slot_reset = ixgbe_io_slot_reset,
7776 .resume = ixgbe_io_resume,
7777};
7778
7779static struct pci_driver ixgbe_driver = {
7780 .name = ixgbe_driver_name,
7781 .id_table = ixgbe_pci_tbl,
7782 .probe = ixgbe_probe,
7783 .remove = __devexit_p(ixgbe_remove),
7784#ifdef CONFIG_PM
7785 .suspend = ixgbe_suspend,
7786 .resume = ixgbe_resume,
7787#endif
7788 .shutdown = ixgbe_shutdown,
7789 .err_handler = &ixgbe_err_handler
7790};
7791
7792/**
7793 * ixgbe_init_module - Driver Registration Routine
7794 *
7795 * ixgbe_init_module is the first routine called when the driver is
7796 * loaded. All it does is register with the PCI subsystem.
7797 **/
7798static int __init ixgbe_init_module(void)
7799{
7800 int ret;
c7689578 7801 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7802 pr_info("%s\n", ixgbe_copyright);
9a799d71 7803
5dd2d332 7804#ifdef CONFIG_IXGBE_DCA
bd0362dd 7805 dca_register_notify(&dca_notifier);
bd0362dd 7806#endif
5dd2d332 7807
9a799d71
AK		 7808 ret = pci_register_driver(&ixgbe_driver);
7809 return ret;
7810}
b4617240 7811
9a799d71
AK		 7812module_init(ixgbe_init_module);
7813
7814/**
7815 * ixgbe_exit_module - Driver Exit Cleanup Routine
7816 *
7817 * ixgbe_exit_module is called just before the driver is removed
7818 * from memory.
7819 **/
7820static void __exit ixgbe_exit_module(void)
7821{
5dd2d332 7822#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7823 dca_unregister_notify(&dca_notifier);
7824#endif
9a799d71 7825 pci_unregister_driver(&ixgbe_driver);
1a51502b 7826 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7827}
bd0362dd 7828
5dd2d332 7829#ifdef CONFIG_IXGBE_DCA
bd0362dd 7830static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7831 void *p)
bd0362dd
JC		 7832{
7833 int ret_val;
7834
7835 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7836 __ixgbe_notify_dca);
bd0362dd
JC		 7837
7838 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7839}
b453368d 7840
5dd2d332 7841#endif /* CONFIG_IXGBE_DCA */
849c4542 7842
9a799d71
AK		 7843module_exit(ixgbe_exit_module);
7844
7845/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)