[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_dcb_82599.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2013 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _DCB_82599_CONFIG_H_
#define _DCB_82599_CONFIG_H_

/* DCB register definitions */
#define IXGBE_RTTDCS_TDPAC      0x00000001 /* 0 Round Robin,
					    * 1 WSP - Weighted Strict Priority
					    */
#define IXGBE_RTTDCS_VMPAC      0x00000002 /* 0 Round Robin,
					    * 1 WRR - Weighted Round Robin
					    */
#define IXGBE_RTTDCS_TDRM       0x00000010 /* Transmit Recycle Mode */
#define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
#define IXGBE_RTTDCS_BDPM       0x00400000 /* Bypass Data Pipe - must clear! */
#define IXGBE_RTTDCS_BPBFSM     0x00800000 /* Bypass PB Free Space - must
					     * clear!
					     */
#define IXGBE_RTTDCS_SPEED_CHG  0x80000000 /* Link speed change */

/* Receive UP2TC mapping */
#define IXGBE_RTRUP2TC_UP_SHIFT 3
#define IXGBE_RTRUP2TC_UP_MASK	7
/* Transmit UP2TC mapping */
#define IXGBE_RTTUP2TC_UP_SHIFT 3

#define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
#define IXGBE_RTRPT4C_BWG_SHIFT 9  /* Offset to BWG index */
#define IXGBE_RTRPT4C_GSP       0x40000000 /* GSP enable bit */
#define IXGBE_RTRPT4C_LSP       0x80000000 /* LSP enable bit */

#define IXGBE_RDRXCTL_MPBEN     0x00000010 /* DMA config for multiple packet
					    * buffers enable
					    */
#define IXGBE_RDRXCTL_MCEN      0x00000040 /* DMA config for multiple cores
					    * (RSS) enable
					    */

/* RTRPCS Bit Masks */
#define IXGBE_RTRPCS_RRM        0x00000002 /* Receive Recycle Mode enable */
/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
#define IXGBE_RTRPCS_RAC        0x00000004
#define IXGBE_RTRPCS_ARBDIS     0x00000040 /* Arbitration disable bit */

/* RTTDT2C Bit Masks */
#define IXGBE_RTTDT2C_MCL_SHIFT 12
#define IXGBE_RTTDT2C_BWG_SHIFT 9
#define IXGBE_RTTDT2C_GSP       0x40000000
#define IXGBE_RTTDT2C_LSP       0x80000000

#define IXGBE_RTTPT2C_MCL_SHIFT 12
#define IXGBE_RTTPT2C_BWG_SHIFT 9
#define IXGBE_RTTPT2C_GSP       0x40000000
#define IXGBE_RTTPT2C_LSP       0x80000000

/* RTTPCS Bit Masks */
#define IXGBE_RTTPCS_TPPAC      0x00000020 /* 0 Round Robin,
					    * 1 SP - Strict Priority
					    */
#define IXGBE_RTTPCS_ARBDIS     0x00000040 /* Arbiter disable */
#define IXGBE_RTTPCS_TPRM       0x00000100 /* Transmit Recycle Mode enable */
#define IXGBE_RTTPCS_ARBD_SHIFT 22
#define IXGBE_RTTPCS_ARBD_DCB   0x4        /* Arbitration delay in DCB mode */

/* SECTXMINIFG DCB */
#define IXGBE_SECTX_DCB		0x00001F00 /* DCB TX Buffer IFG */


/* DCB hardware-specific driver APIs */

/* DCB PFC functions */
s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc);

/* DCB hw initialization */
s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
					u16 *refill,
					u16 *max,
					u8 *bwg_id,
					u8 *prio_type,
					u8 *prio_tc);

s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
						u16 *refill,
						u16 *max,
						u8 *bwg_id,
						u8 *prio_type);

s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
						u16 *refill,
						u16 *max,
						u8 *bwg_id,
						u8 *prio_type,
						u8 *prio_tc);

s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
			      u16 *max, u8 *bwg_id, u8 *prio_type,
			      u8 *prio_tc);

#endif /* _DCB_82599_CONFIG_H */
Commit	Line	Data
235ea828 PW	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
434c5e39	4	Copyright(c) 1999 - 2013 Intel Corporation.
235ea828 PW	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
b89aae71	23	Linux NICS <linux.nics@intel.com>
235ea828 PW	24	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	26
	27	*******************************************************************************/
	28
	29	#ifndef _DCB_82599_CONFIG_H_
	30	#define _DCB_82599_CONFIG_H_
	31
	32	/* DCB register definitions */
	33	#define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin,
e7cf745b JK	34	* 1 WSP - Weighted Strict Priority
e7cf745b JK	35	*/
235ea828	36	#define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin,
e7cf745b JK	37	* 1 WRR - Weighted Round Robin
e7cf745b JK	38	*/
235ea828 PW	39	#define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */
	40	#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
	41	#define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */
	42	#define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must
e7cf745b JK	43	* clear!
e7cf745b JK	44	*/
235ea828 PW	45	#define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */
	46
	47	/* Receive UP2TC mapping */
	48	#define IXGBE_RTRUP2TC_UP_SHIFT 3
e8915beb	49	#define IXGBE_RTRUP2TC_UP_MASK 7
235ea828 PW	50	/* Transmit UP2TC mapping */
	51	#define IXGBE_RTTUP2TC_UP_SHIFT 3
	52
	53	#define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
	54	#define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */
	55	#define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */
	56	#define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */
	57
	58	#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet
e7cf745b JK	59	* buffers enable
e7cf745b JK	60	*/
235ea828	61	#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores
e7cf745b JK	62	* (RSS) enable
e7cf745b JK	63	*/
235ea828 PW	64
	65	/* RTRPCS Bit Masks */
	66	#define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */
	67	/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
	68	#define IXGBE_RTRPCS_RAC 0x00000004
	69	#define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */
	70
	71	/* RTTDT2C Bit Masks */
	72	#define IXGBE_RTTDT2C_MCL_SHIFT 12
	73	#define IXGBE_RTTDT2C_BWG_SHIFT 9
	74	#define IXGBE_RTTDT2C_GSP 0x40000000
	75	#define IXGBE_RTTDT2C_LSP 0x80000000
	76
	77	#define IXGBE_RTTPT2C_MCL_SHIFT 12
	78	#define IXGBE_RTTPT2C_BWG_SHIFT 9
	79	#define IXGBE_RTTPT2C_GSP 0x40000000
	80	#define IXGBE_RTTPT2C_LSP 0x80000000
	81
	82	/* RTTPCS Bit Masks */
	83	#define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin,
e7cf745b JK	84	* 1 SP - Strict Priority
e7cf745b JK	85	*/
235ea828 PW	86	#define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */
	87	#define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */
	88	#define IXGBE_RTTPCS_ARBD_SHIFT 22
	89	#define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */
	90
9806307a JF	91	/* SECTXMINIFG DCB */
	92	#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer IFG */
	93
235ea828 PW	94
	95	/* DCB hardware-specific driver APIs */
	96
	97	/* DCB PFC functions */
32701dc2	98	s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw hw, u8 pfc_en, u8 prio_tc);
235ea828	99
235ea828	100	/* DCB hw initialization */
55320cb5 JF	101	s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
	102	u16 *refill,
	103	u16 *max,
	104	u8 *bwg_id,
17049d30 JF	105	u8 *prio_type,
17049d30 JF	106	u8 *prio_tc);
55320cb5 JF	107
	108	s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
	109	u16 *refill,
	110	u16 *max,
	111	u8 *bwg_id,
	112	u8 *prio_type);
	113
	114	s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
	115	u16 *refill,
	116	u16 *max,
	117	u8 *bwg_id,
17049d30 JF	118	u8 *prio_type,
17049d30 JF	119	u8 *prio_tc);
55320cb5	120
80605c65	121	s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw hw, u8 pfc_en, u16 refill,
17049d30 JF	122	u16 max, u8 bwg_id, u8 *prio_type,
17049d30 JF	123	u8 *prio_tc);
235ea828 PW	124
235ea828 PW	125	#endif /* _DCB_82599_CONFIG_H */