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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
afdc71e4 | 4 | Copyright(c) 1999 - 2016 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #ifndef _IXGBE_COMMON_H_ | |
30 | #define _IXGBE_COMMON_H_ | |
31 | ||
32 | #include "ixgbe_type.h" | |
32f75466 | 33 | #include "ixgbe.h" |
9a799d71 | 34 | |
71161302 | 35 | u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw); |
c44ade9e JB |
36 | s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw); |
37 | s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw); | |
38 | s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw); | |
7184b7cf | 39 | s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw); |
c44ade9e | 40 | s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw); |
289700db | 41 | s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, |
e7cf745b | 42 | u32 pba_num_size); |
c44ade9e | 43 | s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr); |
ef1889d5 JK |
44 | enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status); |
45 | enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status); | |
c44ade9e | 46 | s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw); |
11afc1b1 | 47 | void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw); |
c44ade9e JB |
48 | s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw); |
49 | ||
50 | s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index); | |
51 | s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index); | |
52 | ||
53 | s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw); | |
11afc1b1 | 54 | s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data); |
68c7005d ET |
55 | s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, |
56 | u16 words, u16 *data); | |
21ce849b | 57 | s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data); |
68c7005d ET |
58 | s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, |
59 | u16 words, u16 *data); | |
eb9c3e3e | 60 | s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data); |
68c7005d ET |
61 | s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, |
62 | u16 words, u16 *data); | |
c44ade9e | 63 | s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, |
e7cf745b | 64 | u16 *data); |
68c7005d ET |
65 | s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, |
66 | u16 words, u16 *data); | |
735c35af | 67 | s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw); |
c44ade9e | 68 | s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, |
e7cf745b | 69 | u16 *checksum_val); |
c44ade9e JB |
70 | s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw); |
71 | ||
72 | s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, | |
e7cf745b | 73 | u32 enable_addr); |
c44ade9e JB |
74 | s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index); |
75 | s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw); | |
2853eb89 JP |
76 | s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, |
77 | struct net_device *netdev); | |
c44ade9e JB |
78 | s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw); |
79 | s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw); | |
d2f5e7f3 AS |
80 | s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw); |
81 | s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw); | |
11afc1b1 | 82 | s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval); |
041441d0 | 83 | s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw); |
afdc71e4 | 84 | s32 ixgbe_setup_fc_generic(struct ixgbe_hw *); |
73d80953 | 85 | bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw); |
786e9a5f | 86 | void ixgbe_fc_autoneg(struct ixgbe_hw *hw); |
9a799d71 | 87 | |
030eaece DS |
88 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask); |
89 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask); | |
21ce849b MC |
90 | s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr); |
91 | s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq); | |
7fa7c9dc | 92 | s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq); |
21ce849b MC |
93 | s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq); |
94 | s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw); | |
95 | s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, | |
b6488b66 | 96 | u32 vind, bool vlan_on, bool vlvf_bypass); |
21ce849b MC |
97 | s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw); |
98 | s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, | |
e7cf745b JK |
99 | ixgbe_link_speed *speed, |
100 | bool *link_up, bool link_up_wait_to_complete); | |
a391f1d5 | 101 | s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, |
e7cf745b | 102 | u16 *wwpn_prefix); |
429d6a3b DS |
103 | |
104 | s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val); | |
105 | s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked); | |
106 | ||
87c12017 PW |
107 | s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index); |
108 | s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index); | |
77f192af | 109 | void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf); |
a985b6c3 | 110 | void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf); |
b776d104 | 111 | s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps); |
9612de92 ET |
112 | s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, |
113 | u8 build, u8 ver); | |
5cffde30 MR |
114 | s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *, u32 length, |
115 | u32 timeout, bool return_data); | |
ff9d1a5a | 116 | void ixgbe_clear_tx_pending(struct ixgbe_hw *hw); |
bd8069ac | 117 | bool ixgbe_mng_present(struct ixgbe_hw *hw); |
7155d051 | 118 | bool ixgbe_mng_enabled(struct ixgbe_hw *hw); |
87c12017 | 119 | |
80605c65 JF |
120 | void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, |
121 | u32 headroom, int strategy); | |
122 | ||
9a900eca DS |
123 | extern const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT]; |
124 | ||
e1ea9158 DS |
125 | #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8 |
126 | #define IXGBE_EMC_INTERNAL_DATA 0x00 | |
127 | #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20 | |
128 | #define IXGBE_EMC_DIODE1_DATA 0x01 | |
129 | #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19 | |
130 | #define IXGBE_EMC_DIODE2_DATA 0x23 | |
131 | #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A | |
132 | #define IXGBE_EMC_DIODE3_DATA 0x2A | |
133 | #define IXGBE_EMC_DIODE3_THERM_LIMIT 0x30 | |
134 | ||
135 | s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw); | |
136 | s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw); | |
1f9ac57c DS |
137 | void ixgbe_disable_rx_generic(struct ixgbe_hw *hw); |
138 | void ixgbe_enable_rx_generic(struct ixgbe_hw *hw); | |
6d373a1b MR |
139 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, |
140 | ixgbe_link_speed speed, | |
141 | bool autoneg_wait_to_complete); | |
142 | void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, | |
143 | ixgbe_link_speed speed); | |
e1ea9158 | 144 | |
2a1a091c | 145 | #define IXGBE_FAILED_READ_REG 0xffffffffU |
14438464 MR |
146 | #define IXGBE_FAILED_READ_CFG_DWORD 0xffffffffU |
147 | #define IXGBE_FAILED_READ_CFG_WORD 0xffffU | |
148 | ||
149 | u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg); | |
ed19231c | 150 | void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value); |
2a1a091c MR |
151 | |
152 | static inline bool ixgbe_removed(void __iomem *addr) | |
153 | { | |
154 | return unlikely(!addr); | |
155 | } | |
156 | ||
84227bcd MR |
157 | static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value) |
158 | { | |
b12babd4 MR |
159 | u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); |
160 | ||
161 | if (ixgbe_removed(reg_addr)) | |
162 | return; | |
163 | writel(value, reg_addr + reg); | |
84227bcd MR |
164 | } |
165 | #define IXGBE_WRITE_REG(a, reg, value) ixgbe_write_reg((a), (reg), (value)) | |
9a799d71 | 166 | |
11afc1b1 | 167 | #ifndef writeq |
84227bcd MR |
168 | #define writeq writeq |
169 | static inline void writeq(u64 val, void __iomem *addr) | |
170 | { | |
171 | writel((u32)val, addr); | |
172 | writel((u32)(val >> 32), addr + 4); | |
173 | } | |
11afc1b1 PW |
174 | #endif |
175 | ||
84227bcd MR |
176 | static inline void ixgbe_write_reg64(struct ixgbe_hw *hw, u32 reg, u64 value) |
177 | { | |
b12babd4 MR |
178 | u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); |
179 | ||
180 | if (ixgbe_removed(reg_addr)) | |
181 | return; | |
182 | writeq(value, reg_addr + reg); | |
84227bcd MR |
183 | } |
184 | #define IXGBE_WRITE_REG64(a, reg, value) ixgbe_write_reg64((a), (reg), (value)) | |
11afc1b1 | 185 | |
f8e2472f | 186 | u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg); |
84227bcd | 187 | #define IXGBE_READ_REG(a, reg) ixgbe_read_reg((a), (reg)) |
9a799d71 | 188 | |
84227bcd MR |
189 | #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) \ |
190 | ixgbe_write_reg((a), (reg) + ((offset) << 2), (value)) | |
9a799d71 | 191 | |
84227bcd MR |
192 | #define IXGBE_READ_REG_ARRAY(a, reg, offset) \ |
193 | ixgbe_read_reg((a), (reg) + ((offset) << 2)) | |
9a799d71 | 194 | |
84227bcd | 195 | #define IXGBE_WRITE_FLUSH(a) ixgbe_read_reg((a), IXGBE_STATUS) |
9a799d71 | 196 | |
be0c27b4 MR |
197 | #define ixgbe_hw_to_netdev(hw) (((struct ixgbe_adapter *)(hw)->back)->netdev) |
198 | ||
9a799d71 | 199 | #define hw_dbg(hw, format, arg...) \ |
be0c27b4 MR |
200 | netdev_dbg(ixgbe_hw_to_netdev(hw), format, ## arg) |
201 | #define hw_err(hw, format, arg...) \ | |
202 | netdev_err(ixgbe_hw_to_netdev(hw), format, ## arg) | |
849c4542 ET |
203 | #define e_dev_info(format, arg...) \ |
204 | dev_info(&adapter->pdev->dev, format, ## arg) | |
205 | #define e_dev_warn(format, arg...) \ | |
206 | dev_warn(&adapter->pdev->dev, format, ## arg) | |
207 | #define e_dev_err(format, arg...) \ | |
208 | dev_err(&adapter->pdev->dev, format, ## arg) | |
209 | #define e_dev_notice(format, arg...) \ | |
210 | dev_notice(&adapter->pdev->dev, format, ## arg) | |
396e799c ET |
211 | #define e_info(msglvl, format, arg...) \ |
212 | netif_info(adapter, msglvl, adapter->netdev, format, ## arg) | |
213 | #define e_err(msglvl, format, arg...) \ | |
214 | netif_err(adapter, msglvl, adapter->netdev, format, ## arg) | |
215 | #define e_warn(msglvl, format, arg...) \ | |
216 | netif_warn(adapter, msglvl, adapter->netdev, format, ## arg) | |
217 | #define e_crit(msglvl, format, arg...) \ | |
218 | netif_crit(adapter, msglvl, adapter->netdev, format, ## arg) | |
9a799d71 | 219 | #endif /* IXGBE_COMMON */ |