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ixgbe: Fix incorrect logic for fixed fiber eeprom write
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
096a58fd 34#include "ixgbe_mbx.h"
11afc1b1
PW		 35
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
e09ad236 41#define IXGBE_82599_RX_PB_SIZE 512
11afc1b1 42
5d5b7c39
ET		 43static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
5d5b7c39 48 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 49static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
cd7e1f0b 51 bool autoneg_wait_to_complete);
f4f1040a 52static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
5d5b7c39
ET		 53static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
8620a103 56 ixgbe_link_speed speed,
8620a103 57 bool autoneg_wait_to_complete);
8620a103
MC		 58static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
59 ixgbe_link_speed speed,
8620a103 60 bool autoneg_wait_to_complete);
794caeb2 61static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
8f58332b
DS		 62static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
63 u8 dev_addr, u8 *data);
64static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
65 u8 dev_addr, u8 data);
11afc1b1 66
0b2679d6
DS		 67static bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
68{
69 u32 fwsm, manc, factps;
70
71 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
72 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
73 return false;
74
75 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
76 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
77 return false;
78
79 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
80 if (factps & IXGBE_FACTPS_MNGCG)
81 return false;
82
83 return true;
84}
85
7b25cdba 86static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 87{
88 struct ixgbe_mac_info *mac = &hw->mac;
c6ecf39a 89
0b2679d6
DS		 90 /* enable the laser control functions for SFP+ fiber
91 * and MNG not enabled
92 */
93 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
94 !hw->mng_fw_enabled) {
61fac744
PW		 95 mac->ops.disable_tx_laser =
96 &ixgbe_disable_tx_laser_multispeed_fiber;
97 mac->ops.enable_tx_laser =
98 &ixgbe_enable_tx_laser_multispeed_fiber;
1097cd17 99 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
11afc1b1 100 } else {
61fac744
PW		 101 mac->ops.disable_tx_laser = NULL;
102 mac->ops.enable_tx_laser = NULL;
1097cd17 103 mac->ops.flap_tx_laser = NULL;
c6ecf39a
DS		 104 }
105
106 if (hw->phy.multispeed_fiber) {
107 /* Set up dual speed SFP+ support */
108 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
109 } else {
cd7e1f0b
DS		 110 if ((mac->ops.get_media_type(hw) ==
111 ixgbe_media_type_backplane) &&
112 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
0fa6d832
ET		 113 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
114 !ixgbe_verify_lesm_fw_enabled_82599(hw))
cd7e1f0b
DS		 115 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
116 else
117 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 118 }
119}
120
7b25cdba 121static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 122{
123 s32 ret_val = 0;
124 u16 list_offset, data_offset, data_value;
d7bbcd32 125 bool got_lock = false;
11afc1b1
PW		 126
127 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
128 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 129
130 hw->phy.ops.reset = NULL;
131
11afc1b1
PW		 132 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
133 &data_offset);
11afc1b1
PW		 134 if (ret_val != 0)
135 goto setup_sfp_out;
136
aa5aec88 137 /* PHY config will finish before releasing the semaphore */
5e655105
DS		 138 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
139 IXGBE_GSSR_MAC_CSR_SM);
aa5aec88
PWJ		 140 if (ret_val != 0) {
141 ret_val = IXGBE_ERR_SWFW_SYNC;
142 goto setup_sfp_out;
143 }
144
be0c27b4
MR		 145 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
146 goto setup_sfp_err;
11afc1b1
PW		 147 while (data_value != 0xffff) {
148 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
149 IXGBE_WRITE_FLUSH(hw);
be0c27b4
MR		 150 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
151 goto setup_sfp_err;
11afc1b1 152 }
aa5aec88
PWJ		 153
154 /* Release the semaphore */
6d980c3e 155 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
032b4325
DS		 156 /*
157 * Delay obtaining semaphore again to allow FW access,
158 * semaphore_delay is in ms usleep_range needs us.
159 */
160 usleep_range(hw->eeprom.semaphore_delay * 1000,
161 hw->eeprom.semaphore_delay * 2000);
a7f5a5fc 162
d7bbcd32
DS		 163 /* Need SW/FW semaphore around AUTOC writes if LESM on,
164 * likewise reset_pipeline requires lock as it also writes
165 * AUTOC.
166 */
167 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
168 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
169 IXGBE_GSSR_MAC_CSR_SM);
170 if (ret_val)
171 goto setup_sfp_out;
172
173 got_lock = true;
174 }
175
176 /* Restart DSP and set SFI mode */
5e82f2f0
ET		 177 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((hw->mac.orig_autoc) |
178 IXGBE_AUTOC_LMS_10G_SERIAL));
179 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
d7bbcd32
DS		 180 ret_val = ixgbe_reset_pipeline_82599(hw);
181
182 if (got_lock) {
183 hw->mac.ops.release_swfw_sync(hw,
184 IXGBE_GSSR_MAC_CSR_SM);
185 got_lock = false;
a7f5a5fc 186 }
d7bbcd32
DS		 187
188 if (ret_val) {
189 hw_dbg(hw, " sfp module setup not complete\n");
a7f5a5fc
DS		 190 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
191 goto setup_sfp_out;
192 }
11afc1b1
PW		 193 }
194
195setup_sfp_out:
196 return ret_val;
be0c27b4
MR		 197
198setup_sfp_err:
199 /* Release the semaphore */
200 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
201 /* Delay obtaining semaphore again to allow FW access,
202 * semaphore_delay is in ms usleep_range needs us.
203 */
204 usleep_range(hw->eeprom.semaphore_delay * 1000,
205 hw->eeprom.semaphore_delay * 2000);
206 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
207 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
11afc1b1
PW		 208}
209
11afc1b1
PW		 210static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
211{
212 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 213
04f165ef 214 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 215
04f165ef
PW		 216 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
217 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
218 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
219 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
220 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
21ce849b 221 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
11afc1b1 222
04f165ef
PW		 223 return 0;
224}
11afc1b1 225
04f165ef
PW		 226/**
227 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
228 * @hw: pointer to hardware structure
229 *
230 * Initialize any function pointers that were not able to be
231 * set during get_invariants because the PHY/SFP type was
232 * not known. Perform the SFP init if necessary.
233 *
234 **/
7b25cdba 235static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 236{
237 struct ixgbe_mac_info *mac = &hw->mac;
238 struct ixgbe_phy_info *phy = &hw->phy;
239 s32 ret_val = 0;
8f58332b
DS		 240 u32 esdp;
241
242 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
243 /* Store flag indicating I2C bus access control unit. */
244 hw->phy.qsfp_shared_i2c_bus = true;
245
246 /* Initialize access to QSFP+ I2C bus */
247 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
248 esdp |= IXGBE_ESDP_SDP0_DIR;
249 esdp &= ~IXGBE_ESDP_SDP1_DIR;
250 esdp &= ~IXGBE_ESDP_SDP0;
251 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
252 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
253 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
254 IXGBE_WRITE_FLUSH(hw);
255
256 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
257 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
258 }
11afc1b1 259
04f165ef
PW		 260 /* Identify the PHY or SFP module */
261 ret_val = phy->ops.identify(hw);
262
263 /* Setup function pointers based on detected SFP module and speeds */
264 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 265
266 /* If copper media, overwrite with copper function pointers */
267 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
268 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1 269 mac->ops.get_link_capabilities =
a391f1d5 270 &ixgbe_get_copper_link_capabilities_generic;
11afc1b1
PW		 271 }
272
04f165ef 273 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 274 switch (hw->phy.type) {
275 case ixgbe_phy_tn:
276 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
b57e35bd 277 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
11afc1b1 278 phy->ops.get_firmware_version =
04f165ef 279 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 280 break;
281 default:
282 break;
283 }
284
11afc1b1
PW		 285 return ret_val;
286}
287
288/**
289 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
290 * @hw: pointer to hardware structure
291 * @speed: pointer to link speed
3d292265 292 * @autoneg: true when autoneg or autotry is enabled
11afc1b1
PW		 293 *
294 * Determines the link capabilities by reading the AUTOC register.
295 **/
7b25cdba
DS		 296static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
297 ixgbe_link_speed *speed,
3d292265 298 bool *autoneg)
11afc1b1
PW		 299{
300 s32 status = 0;
1eb99d5a 301 u32 autoc = 0;
11afc1b1 302
cb836a97
DS		 303 /* Determine 1G link capabilities off of SFP+ type */
304 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
a49fda3e 305 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
345be204
DS		 306 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
307 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
a49fda3e
JK		 308 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
309 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
cb836a97 310 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3d292265 311 *autoneg = true;
cb836a97
DS		 312 goto out;
313 }
314
1eb99d5a
PW		 315 /*
316 * Determine link capabilities based on the stored value of AUTOC,
317 * which represents EEPROM defaults. If AUTOC value has not been
318 * stored, use the current register value.
319 */
320 if (hw->mac.orig_link_settings_stored)
321 autoc = hw->mac.orig_autoc;
322 else
323 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
324
325 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 326 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
327 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3d292265 328 *autoneg = false;
11afc1b1
PW		 329 break;
330
331 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
332 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3d292265 333 *autoneg = false;
11afc1b1
PW		 334 break;
335
336 case IXGBE_AUTOC_LMS_1G_AN:
337 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3d292265 338 *autoneg = true;
11afc1b1
PW		 339 break;
340
341 case IXGBE_AUTOC_LMS_10G_SERIAL:
342 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3d292265 343 *autoneg = false;
11afc1b1
PW		 344 break;
345
346 case IXGBE_AUTOC_LMS_KX4_KX_KR:
347 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
348 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 349 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 350 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 351 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 352 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 353 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1 354 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
3d292265 355 *autoneg = true;
11afc1b1
PW		 356 break;
357
358 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
359 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 360 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 361 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 362 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 363 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 364 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1 365 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
3d292265 366 *autoneg = true;
11afc1b1
PW		 367 break;
368
369 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
370 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
3d292265 371 *autoneg = false;
11afc1b1
PW		 372 break;
373
374 default:
375 status = IXGBE_ERR_LINK_SETUP;
376 goto out;
377 break;
378 }
379
380 if (hw->phy.multispeed_fiber) {
381 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
61aaf9e8
ET		 382 IXGBE_LINK_SPEED_1GB_FULL;
383
384 /* QSFP must not enable auto-negotiation */
385 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
386 *autoneg = false;
387 else
388 *autoneg = true;
11afc1b1
PW		 389 }
390
391out:
392 return status;
393}
394
11afc1b1
PW		 395/**
396 * ixgbe_get_media_type_82599 - Get media type
397 * @hw: pointer to hardware structure
398 *
399 * Returns the media type (fiber, copper, backplane)
400 **/
7b25cdba 401static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 402{
403 enum ixgbe_media_type media_type;
404
405 /* Detect if there is a copper PHY attached. */
21cc5b4f
ET		 406 switch (hw->phy.type) {
407 case ixgbe_phy_cu_unknown:
408 case ixgbe_phy_tn:
11afc1b1
PW		 409 media_type = ixgbe_media_type_copper;
410 goto out;
21cc5b4f
ET		 411 default:
412 break;
11afc1b1
PW		 413 }
414
415 switch (hw->device_id) {
11afc1b1 416 case IXGBE_DEV_ID_82599_KX4:
dbfec662 417 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 418 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 419 case IXGBE_DEV_ID_82599_KR:
dbffcb21 420 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
1fcf03e6 421 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 422 /* Default device ID is mezzanine card KX/KX4 */
423 media_type = ixgbe_media_type_backplane;
424 break;
425 case IXGBE_DEV_ID_82599_SFP:
dbffcb21 426 case IXGBE_DEV_ID_82599_SFP_FCOE:
38ad1c8e 427 case IXGBE_DEV_ID_82599_SFP_EM:
4c40ef02 428 case IXGBE_DEV_ID_82599_SFP_SF2:
9e791e4a 429 case IXGBE_DEV_ID_82599_SFP_SF_QP:
7d145282 430 case IXGBE_DEV_ID_82599EN_SFP:
11afc1b1
PW		 431 media_type = ixgbe_media_type_fiber;
432 break;
8911184f 433 case IXGBE_DEV_ID_82599_CX4:
6b1be199 434 media_type = ixgbe_media_type_cx4;
8911184f 435 break;
21cc5b4f
ET		 436 case IXGBE_DEV_ID_82599_T3_LOM:
437 media_type = ixgbe_media_type_copper;
438 break;
4f6290cf
DS		 439 case IXGBE_DEV_ID_82599_LS:
440 media_type = ixgbe_media_type_fiber_lco;
441 break;
8f58332b
DS		 442 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
443 media_type = ixgbe_media_type_fiber_qsfp;
444 break;
11afc1b1
PW		 445 default:
446 media_type = ixgbe_media_type_unknown;
447 break;
448 }
449out:
450 return media_type;
451}
452
f4f1040a
JK		 453/**
454 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
455 * @hw: pointer to hardware structure
456 *
457 * Disables link, should be called during D3 power down sequence.
458 *
459 */
460static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
461{
462 u32 autoc2_reg;
463
464 if (!hw->mng_fw_enabled && !hw->wol_enabled) {
465 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
466 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
467 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
468 }
469}
470
11afc1b1 471/**
8620a103 472 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 473 * @hw: pointer to hardware structure
8620a103 474 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 475 *
476 * Configures link settings based on values in the ixgbe_hw struct.
477 * Restarts the link. Performs autonegotiation if needed.
478 **/
5d5b7c39 479static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
8620a103 480 bool autoneg_wait_to_complete)
11afc1b1
PW		 481{
482 u32 autoc_reg;
483 u32 links_reg;
484 u32 i;
485 s32 status = 0;
d7bbcd32
DS		 486 bool got_lock = false;
487
488 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
489 status = hw->mac.ops.acquire_swfw_sync(hw,
490 IXGBE_GSSR_MAC_CSR_SM);
491 if (status)
492 goto out;
493
494 got_lock = true;
495 }
11afc1b1
PW		 496
497 /* Restart link */
d7bbcd32
DS		 498 ixgbe_reset_pipeline_82599(hw);
499
500 if (got_lock)
501 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
11afc1b1
PW		 502
503 /* Only poll for autoneg to complete if specified to do so */
8620a103 504 if (autoneg_wait_to_complete) {
d7bbcd32 505 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
11afc1b1
PW		 506 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
507 IXGBE_AUTOC_LMS_KX4_KX_KR ||
508 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
509 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
510 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
511 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
512 links_reg = 0; /* Just in case Autoneg time = 0 */
513 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
514 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
515 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
516 break;
517 msleep(100);
518 }
519 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
520 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
521 hw_dbg(hw, "Autoneg did not complete.\n");
522 }
523 }
524 }
525
11afc1b1
PW		 526 /* Add delay to filter out noises during initial link setup */
527 msleep(50);
528
d7bbcd32 529out:
11afc1b1
PW		 530 return status;
531}
532
8c7bea32
ET		 533/**
534 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
535 * @hw: pointer to hardware structure
536 *
537 * The base drivers may require better control over SFP+ module
538 * PHY states. This includes selectively shutting down the Tx
539 * laser on the PHY, effectively halting physical link.
540 **/
5d5b7c39 541static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 542{
543 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
544
545 /* Disable tx laser; allow 100us to go dark per spec */
546 esdp_reg |= IXGBE_ESDP_SDP3;
547 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
548 IXGBE_WRITE_FLUSH(hw);
549 udelay(100);
550}
551
552/**
553 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
554 * @hw: pointer to hardware structure
555 *
556 * The base drivers may require better control over SFP+ module
557 * PHY states. This includes selectively turning on the Tx
558 * laser on the PHY, effectively starting physical link.
559 **/
5d5b7c39 560static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 561{
562 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
563
564 /* Enable tx laser; allow 100ms to light up */
565 esdp_reg &= ~IXGBE_ESDP_SDP3;
566 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
567 IXGBE_WRITE_FLUSH(hw);
568 msleep(100);
569}
570
1097cd17
MC		 571/**
572 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
573 * @hw: pointer to hardware structure
574 *
575 * When the driver changes the link speeds that it can support,
576 * it sets autotry_restart to true to indicate that we need to
577 * initiate a new autotry session with the link partner. To do
578 * so, we set the speed then disable and re-enable the tx laser, to
579 * alert the link partner that it also needs to restart autotry on its
580 * end. This is consistent with true clause 37 autoneg, which also
581 * involves a loss of signal.
582 **/
5d5b7c39 583static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
1097cd17 584{
1097cd17 585 if (hw->mac.autotry_restart) {
61fac744
PW		 586 ixgbe_disable_tx_laser_multispeed_fiber(hw);
587 ixgbe_enable_tx_laser_multispeed_fiber(hw);
1097cd17
MC		 588 hw->mac.autotry_restart = false;
589 }
590}
591
4e8e1bca
DS		 592/**
593 * ixgbe_set_fiber_fixed_speed - Set module link speed for fixed fiber
594 * @hw: pointer to hardware structure
595 * @speed: link speed to set
596 *
597 * We set the module speed differently for fixed fiber. For other
598 * multi-speed devices we don't have an error value so here if we
599 * detect an error we just log it and exit.
600 */
601static void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw,
602 ixgbe_link_speed speed)
603{
604 s32 status;
605 u8 rs, eeprom_data;
606
607 switch (speed) {
608 case IXGBE_LINK_SPEED_10GB_FULL:
609 /* one bit mask same as setting on */
610 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
611 break;
612 case IXGBE_LINK_SPEED_1GB_FULL:
613 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
614 break;
615 default:
616 hw_dbg(hw, "Invalid fixed module speed\n");
617 return;
618 }
619
620 /* Set RS0 */
621 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
622 IXGBE_I2C_EEPROM_DEV_ADDR2,
623 &eeprom_data);
624 if (status) {
625 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
626 goto out;
627 }
628
d3cec927 629 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4e8e1bca
DS		 630
631 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
632 IXGBE_I2C_EEPROM_DEV_ADDR2,
633 eeprom_data);
634 if (status) {
635 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
636 goto out;
637 }
638
639 /* Set RS1 */
640 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
641 IXGBE_I2C_EEPROM_DEV_ADDR2,
642 &eeprom_data);
643 if (status) {
644 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n");
645 goto out;
646 }
647
648 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
649
650 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
651 IXGBE_I2C_EEPROM_DEV_ADDR2,
652 eeprom_data);
653 if (status) {
654 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n");
655 goto out;
656 }
657out:
658 return;
659}
660
11afc1b1 661/**
8620a103 662 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 663 * @hw: pointer to hardware structure
664 * @speed: new link speed
11afc1b1
PW		 665 * @autoneg_wait_to_complete: true when waiting for completion is needed
666 *
667 * Set the link speed in the AUTOC register and restarts link.
668 **/
b32c8dcc 669static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
8620a103 670 ixgbe_link_speed speed,
8620a103 671 bool autoneg_wait_to_complete)
11afc1b1
PW		 672{
673 s32 status = 0;
037c6d0a 674 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
11afc1b1
PW		 675 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
676 u32 speedcnt = 0;
677 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
037c6d0a 678 u32 i = 0;
11afc1b1 679 bool link_up = false;
fd0326f2 680 bool autoneg = false;
11afc1b1
PW		 681
682 /* Mask off requested but non-supported speeds */
037c6d0a 683 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
3d292265 684 &autoneg);
037c6d0a
ET		 685 if (status != 0)
686 return status;
687
688 speed &= link_speed;
11afc1b1
PW		 689
690 /*
691 * Try each speed one by one, highest priority first. We do this in
692 * software because 10gb fiber doesn't support speed autonegotiation.
693 */
694 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
695 speedcnt++;
696 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
697
50ac58ba 698 /* If we already have link at this speed, just jump out */
037c6d0a
ET		 699 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
700 false);
701 if (status != 0)
702 return status;
50ac58ba 703
037c6d0a 704 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
50ac58ba
PWJ		 705 goto out;
706
707 /* Set the module link speed */
61aaf9e8
ET		 708 switch (hw->phy.media_type) {
709 case ixgbe_media_type_fiber:
4e8e1bca
DS		 710 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
711 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
712 IXGBE_WRITE_FLUSH(hw);
61aaf9e8
ET		 713 break;
714 case ixgbe_media_type_fiber_qsfp:
715 /* QSFP module automatically detects MAC link speed */
716 break;
717 default:
718 hw_dbg(hw, "Unexpected media type.\n");
719 break;
4e8e1bca 720 }
11afc1b1 721
50ac58ba
PWJ		 722 /* Allow module to change analog characteristics (1G->10G) */
723 msleep(40);
11afc1b1 724
8620a103 725 status = ixgbe_setup_mac_link_82599(hw,
037c6d0a 726 IXGBE_LINK_SPEED_10GB_FULL,
037c6d0a 727 autoneg_wait_to_complete);
50ac58ba 728 if (status != 0)
c3c74327 729 return status;
50ac58ba
PWJ		 730
731 /* Flap the tx laser if it has not already been done */
0b2679d6
DS		 732 if (hw->mac.ops.flap_tx_laser)
733 hw->mac.ops.flap_tx_laser(hw);
50ac58ba 734
cd7e1f0b
DS		 735 /*
736 * Wait for the controller to acquire link. Per IEEE 802.3ap,
737 * Section 73.10.2, we may have to wait up to 500ms if KR is
738 * attempted. 82599 uses the same timing for 10g SFI.
739 */
50ac58ba
PWJ		 740 for (i = 0; i < 5; i++) {
741 /* Wait for the link partner to also set speed */
742 msleep(100);
743
744 /* If we have link, just jump out */
037c6d0a
ET		 745 status = hw->mac.ops.check_link(hw, &link_speed,
746 &link_up, false);
747 if (status != 0)
748 return status;
749
50ac58ba
PWJ		 750 if (link_up)
751 goto out;
752 }
11afc1b1
PW		 753 }
754
755 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
756 speedcnt++;
757 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
758 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
759
50ac58ba 760 /* If we already have link at this speed, just jump out */
037c6d0a
ET		 761 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
762 false);
763 if (status != 0)
764 return status;
50ac58ba 765
037c6d0a 766 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
50ac58ba
PWJ		 767 goto out;
768
769 /* Set the module link speed */
61aaf9e8
ET		 770 switch (hw->phy.media_type) {
771 case ixgbe_media_type_fiber_fixed:
4e8e1bca
DS		 772 ixgbe_set_fiber_fixed_speed(hw,
773 IXGBE_LINK_SPEED_1GB_FULL);
61aaf9e8
ET		 774 break;
775 case ixgbe_media_type_fiber:
4e8e1bca
DS		 776 esdp_reg &= ~IXGBE_ESDP_SDP5;
777 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
778 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
779 IXGBE_WRITE_FLUSH(hw);
61aaf9e8
ET		 780 break;
781 case ixgbe_media_type_fiber_qsfp:
782 /* QSFP module automatically detects MAC link speed */
783 break;
784 default:
785 hw_dbg(hw, "Unexpected media type.\n");
786 break;
4e8e1bca 787 }
11afc1b1 788
50ac58ba
PWJ		 789 /* Allow module to change analog characteristics (10G->1G) */
790 msleep(40);
11afc1b1 791
8620a103 792 status = ixgbe_setup_mac_link_82599(hw,
037c6d0a 793 IXGBE_LINK_SPEED_1GB_FULL,
037c6d0a 794 autoneg_wait_to_complete);
50ac58ba 795 if (status != 0)
c3c74327 796 return status;
50ac58ba
PWJ		 797
798 /* Flap the tx laser if it has not already been done */
0b2679d6
DS		 799 if (hw->mac.ops.flap_tx_laser)
800 hw->mac.ops.flap_tx_laser(hw);
50ac58ba
PWJ		 801
802 /* Wait for the link partner to also set speed */
803 msleep(100);
11afc1b1
PW		 804
805 /* If we have link, just jump out */
037c6d0a
ET		 806 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
807 false);
808 if (status != 0)
809 return status;
810
11afc1b1
PW		 811 if (link_up)
812 goto out;
813 }
814
815 /*
816 * We didn't get link. Configure back to the highest speed we tried,
817 * (if there was more than one). We call ourselves back with just the
818 * single highest speed that the user requested.
819 */
820 if (speedcnt > 1)
8620a103
MC		 821 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
822 highest_link_speed,
8620a103 823 autoneg_wait_to_complete);
11afc1b1
PW		 824
825out:
c3c74327
MC		 826 /* Set autoneg_advertised value based on input link speed */
827 hw->phy.autoneg_advertised = 0;
828
829 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
830 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
831
832 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
833 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
834
11afc1b1
PW		 835 return status;
836}
837
cd7e1f0b
DS		 838/**
839 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
840 * @hw: pointer to hardware structure
841 * @speed: new link speed
cd7e1f0b
DS		 842 * @autoneg_wait_to_complete: true when waiting for completion is needed
843 *
844 * Implements the Intel SmartSpeed algorithm.
845 **/
846static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
fd0326f2 847 ixgbe_link_speed speed,
cd7e1f0b
DS		 848 bool autoneg_wait_to_complete)
849{
850 s32 status = 0;
037c6d0a 851 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
cd7e1f0b
DS		 852 s32 i, j;
853 bool link_up = false;
854 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
cd7e1f0b
DS		 855
856 /* Set autoneg_advertised value based on input link speed */
857 hw->phy.autoneg_advertised = 0;
858
859 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
860 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
861
862 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
863 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
864
865 if (speed & IXGBE_LINK_SPEED_100_FULL)
866 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
867
868 /*
869 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
870 * autoneg advertisement if link is unable to be established at the
871 * highest negotiated rate. This can sometimes happen due to integrity
872 * issues with the physical media connection.
873 */
874
875 /* First, try to get link with full advertisement */
876 hw->phy.smart_speed_active = false;
877 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
fd0326f2 878 status = ixgbe_setup_mac_link_82599(hw, speed,
cd7e1f0b 879 autoneg_wait_to_complete);
037c6d0a 880 if (status != 0)
cd7e1f0b
DS		 881 goto out;
882
883 /*
884 * Wait for the controller to acquire link. Per IEEE 802.3ap,
885 * Section 73.10.2, we may have to wait up to 500ms if KR is
886 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
887 * Table 9 in the AN MAS.
888 */
889 for (i = 0; i < 5; i++) {
890 mdelay(100);
891
892 /* If we have link, just jump out */
037c6d0a
ET		 893 status = hw->mac.ops.check_link(hw, &link_speed,
894 &link_up, false);
895 if (status != 0)
896 goto out;
897
cd7e1f0b
DS		 898 if (link_up)
899 goto out;
900 }
901 }
902
903 /*
904 * We didn't get link. If we advertised KR plus one of KX4/KX
905 * (or BX4/BX), then disable KR and try again.
906 */
907 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
908 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
909 goto out;
910
911 /* Turn SmartSpeed on to disable KR support */
912 hw->phy.smart_speed_active = true;
fd0326f2 913 status = ixgbe_setup_mac_link_82599(hw, speed,
cd7e1f0b 914 autoneg_wait_to_complete);
037c6d0a 915 if (status != 0)
cd7e1f0b
DS		 916 goto out;
917
918 /*
919 * Wait for the controller to acquire link. 600ms will allow for
920 * the AN link_fail_inhibit_timer as well for multiple cycles of
921 * parallel detect, both 10g and 1g. This allows for the maximum
922 * connect attempts as defined in the AN MAS table 73-7.
923 */
924 for (i = 0; i < 6; i++) {
925 mdelay(100);
926
927 /* If we have link, just jump out */
037c6d0a
ET		 928 status = hw->mac.ops.check_link(hw, &link_speed,
929 &link_up, false);
930 if (status != 0)
931 goto out;
932
cd7e1f0b
DS		 933 if (link_up)
934 goto out;
935 }
936
937 /* We didn't get link. Turn SmartSpeed back off. */
938 hw->phy.smart_speed_active = false;
fd0326f2 939 status = ixgbe_setup_mac_link_82599(hw, speed,
cd7e1f0b
DS		 940 autoneg_wait_to_complete);
941
942out:
c4ee6a53 943 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
037c6d0a 944 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
849c4542 945 "the maximum advertised\n");
cd7e1f0b
DS		 946 return status;
947}
948
11afc1b1 949/**
8620a103 950 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 951 * @hw: pointer to hardware structure
952 * @speed: new link speed
11afc1b1
PW		 953 * @autoneg_wait_to_complete: true when waiting for completion is needed
954 *
955 * Set the link speed in the AUTOC register and restarts link.
956 **/
5d5b7c39 957static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
fd0326f2
JH		 958 ixgbe_link_speed speed,
959 bool autoneg_wait_to_complete)
11afc1b1
PW		 960{
961 s32 status = 0;
5e82f2f0 962 u32 autoc, pma_pmd_1g, link_mode, start_autoc;
11afc1b1 963 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1eb99d5a 964 u32 orig_autoc = 0;
11afc1b1
PW		 965 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
966 u32 links_reg;
967 u32 i;
968 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
d7bbcd32 969 bool got_lock = false;
fd0326f2 970 bool autoneg = false;
11afc1b1
PW		 971
972 /* Check to see if speed passed in is supported. */
9cdcf098
DS		 973 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
974 &autoneg);
0b0c2b31
ET		 975 if (status != 0)
976 goto out;
977
11afc1b1
PW		 978 speed &= link_capabilities;
979
50ac58ba
PWJ		 980 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
981 status = IXGBE_ERR_LINK_SETUP;
982 goto out;
983 }
984
1eb99d5a
PW		 985 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
986 if (hw->mac.orig_link_settings_stored)
5e82f2f0 987 autoc = hw->mac.orig_autoc;
1eb99d5a 988 else
5e82f2f0
ET		 989 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
990
991 orig_autoc = autoc;
992 start_autoc = hw->mac.cached_autoc;
993 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
994 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1eb99d5a 995
50ac58ba
PWJ		 996 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
997 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
998 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 999 /* Set KX4/KX/KR support according to speed requested */
1000 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
55461ddb 1001 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1eb99d5a 1002 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 1003 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 1004 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
1005 (hw->phy.smart_speed_active == false))
11afc1b1 1006 autoc |= IXGBE_AUTOC_KR_SUPP;
55461ddb 1007 }
11afc1b1
PW		 1008 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1009 autoc |= IXGBE_AUTOC_KX_SUPP;
1010 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
1011 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1012 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
1013 /* Switch from 1G SFI to 10G SFI if requested */
1014 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
1015 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
1016 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1017 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1018 }
1019 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1020 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1021 /* Switch from 10G SFI to 1G SFI if requested */
1022 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1023 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1024 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1025 if (autoneg)
1026 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1027 else
1028 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1029 }
1030 }
1031
50ac58ba 1032 if (autoc != start_autoc) {
d7bbcd32
DS		 1033 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
1034 * likewise reset_pipeline requires us to hold this lock as
1035 * it also writes to AUTOC.
1036 */
1037 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1038 status = hw->mac.ops.acquire_swfw_sync(hw,
1039 IXGBE_GSSR_MAC_CSR_SM);
1040 if (status != 0)
1041 goto out;
1042
1043 got_lock = true;
1044 }
1045
11afc1b1 1046 /* Restart link */
11afc1b1 1047 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
5e82f2f0 1048 hw->mac.cached_autoc = autoc;
d7bbcd32
DS		 1049 ixgbe_reset_pipeline_82599(hw);
1050
1051 if (got_lock)
1052 hw->mac.ops.release_swfw_sync(hw,
1053 IXGBE_GSSR_MAC_CSR_SM);
11afc1b1
PW		 1054
1055 /* Only poll for autoneg to complete if specified to do so */
1056 if (autoneg_wait_to_complete) {
1057 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1058 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1059 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1060 links_reg = 0; /*Just in case Autoneg time=0*/
1061 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1062 links_reg =
1063 IXGBE_READ_REG(hw, IXGBE_LINKS);
1064 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1065 break;
1066 msleep(100);
1067 }
1068 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1069 status =
1070 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1071 hw_dbg(hw, "Autoneg did not "
1072 "complete.\n");
1073 }
1074 }
1075 }
1076
11afc1b1
PW		 1077 /* Add delay to filter out noises during initial link setup */
1078 msleep(50);
1079 }
1080
50ac58ba 1081out:
11afc1b1
PW		 1082 return status;
1083}
1084
1085/**
8620a103 1086 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 1087 * @hw: pointer to hardware structure
1088 * @speed: new link speed
11afc1b1
PW		 1089 * @autoneg_wait_to_complete: true if waiting is needed to complete
1090 *
1091 * Restarts link on PHY and MAC based on settings passed in.
1092 **/
8620a103
MC		 1093static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1094 ixgbe_link_speed speed,
8620a103 1095 bool autoneg_wait_to_complete)
11afc1b1
PW		 1096{
1097 s32 status;
1098
1099 /* Setup the PHY according to input speed */
99b76642 1100 status = hw->phy.ops.setup_link_speed(hw, speed,
11afc1b1
PW		 1101 autoneg_wait_to_complete);
1102 /* Set up MAC */
8620a103 1103 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 1104
1105 return status;
1106}
1107
1108/**
1109 * ixgbe_reset_hw_82599 - Perform hardware reset
1110 * @hw: pointer to hardware structure
1111 *
1112 * Resets the hardware by resetting the transmit and receive units, masks
1113 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1114 * reset.
1115 **/
7b25cdba 1116static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1 1117{
8132b54e
AD		 1118 ixgbe_link_speed link_speed;
1119 s32 status;
5e82f2f0 1120 u32 ctrl, i, autoc2;
0b2679d6 1121 u32 curr_lms;
8132b54e 1122 bool link_up = false;
11afc1b1
PW		 1123
1124 /* Call adapter stop to disable tx/rx and clear interrupts */
ff9d1a5a
ET		 1125 status = hw->mac.ops.stop_adapter(hw);
1126 if (status != 0)
1127 goto reset_hw_out;
1128
1129 /* flush pending Tx transactions */
1130 ixgbe_clear_tx_pending(hw);
11afc1b1 1131
553b4497 1132 /* PHY ops must be identified and initialized prior to reset */
04f165ef 1133
037c6d0a 1134 /* Identify PHY and related function pointers */
553b4497 1135 status = hw->phy.ops.init(hw);
04f165ef 1136
553b4497
PW		 1137 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1138 goto reset_hw_out;
04f165ef 1139
553b4497
PW		 1140 /* Setup SFP module if there is one present. */
1141 if (hw->phy.sfp_setup_needed) {
1142 status = hw->mac.ops.setup_sfp(hw);
1143 hw->phy.sfp_setup_needed = false;
04f165ef 1144 }
11afc1b1 1145
037c6d0a
ET		 1146 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1147 goto reset_hw_out;
1148
553b4497
PW		 1149 /* Reset PHY */
1150 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1151 hw->phy.ops.reset(hw);
1152
5e82f2f0
ET		 1153 /* remember AUTOC from before we reset */
1154 if (hw->mac.cached_autoc)
1155 curr_lms = hw->mac.cached_autoc & IXGBE_AUTOC_LMS_MASK;
1156 else
1157 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) &
1158 IXGBE_AUTOC_LMS_MASK;
0b2679d6 1159
a4297dc2 1160mac_reset_top:
11afc1b1 1161 /*
8132b54e
AD		 1162 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1163 * If link reset is used when link is up, it might reset the PHY when
1164 * mng is using it. If link is down or the flag to force full link
1165 * reset is set, then perform link reset.
11afc1b1 1166 */
8132b54e
AD		 1167 ctrl = IXGBE_CTRL_LNK_RST;
1168 if (!hw->force_full_reset) {
1169 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1170 if (link_up)
1171 ctrl = IXGBE_CTRL_RST;
1172 }
1173
1174 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1175 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
11afc1b1
PW		 1176 IXGBE_WRITE_FLUSH(hw);
1177
1178 /* Poll for reset bit to self-clear indicating reset is complete */
1179 for (i = 0; i < 10; i++) {
1180 udelay(1);
1181 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
8132b54e 1182 if (!(ctrl & IXGBE_CTRL_RST_MASK))
11afc1b1
PW		 1183 break;
1184 }
8132b54e
AD		 1185
1186 if (ctrl & IXGBE_CTRL_RST_MASK) {
11afc1b1
PW		 1187 status = IXGBE_ERR_RESET_FAILED;
1188 hw_dbg(hw, "Reset polling failed to complete.\n");
1189 }
11afc1b1 1190
8132b54e
AD		 1191 msleep(50);
1192
a4297dc2
ET		 1193 /*
1194 * Double resets are required for recovery from certain error
1195 * conditions. Between resets, it is necessary to stall to allow time
8132b54e 1196 * for any pending HW events to complete.
a4297dc2
ET		 1197 */
1198 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1199 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 1200 goto mac_reset_top;
1201 }
1202
11afc1b1
PW		 1203 /*
1204 * Store the original AUTOC/AUTOC2 values if they have not been
1205 * stored off yet. Otherwise restore the stored original
1206 * values since the reset operation sets back to defaults.
1207 */
5e82f2f0 1208 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
11afc1b1 1209 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
46d5cedd
ET		 1210
1211 /* Enable link if disabled in NVM */
1212 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1213 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1214 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1215 IXGBE_WRITE_FLUSH(hw);
1216 }
1217
11afc1b1 1218 if (hw->mac.orig_link_settings_stored == false) {
5e82f2f0 1219 hw->mac.orig_autoc = hw->mac.cached_autoc;
11afc1b1
PW		 1220 hw->mac.orig_autoc2 = autoc2;
1221 hw->mac.orig_link_settings_stored = true;
4df10466 1222 } else {
0b2679d6
DS		 1223
1224 /* If MNG FW is running on a multi-speed device that
1225 * doesn't autoneg with out driver support we need to
1226 * leave LMS in the state it was before we MAC reset.
b8f83638
DS		 1227 * Likewise if we support WoL we don't want change the
1228 * LMS state either.
0b2679d6 1229 */
b8f83638 1230 if ((hw->phy.multispeed_fiber && hw->mng_fw_enabled) ||
6b92b0ba 1231 hw->wol_enabled)
0b2679d6
DS		 1232 hw->mac.orig_autoc =
1233 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1234 curr_lms;
1235
5e82f2f0 1236 if (hw->mac.cached_autoc != hw->mac.orig_autoc) {
d7bbcd32
DS		 1237 /* Need SW/FW semaphore around AUTOC writes if LESM is
1238 * on, likewise reset_pipeline requires us to hold
1239 * this lock as it also writes to AUTOC.
1240 */
1241 bool got_lock = false;
1242 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1243 status = hw->mac.ops.acquire_swfw_sync(hw,
1244 IXGBE_GSSR_MAC_CSR_SM);
1245 if (status)
1246 goto reset_hw_out;
1247
1248 got_lock = true;
1249 }
1250
1251 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
5e82f2f0 1252 hw->mac.cached_autoc = hw->mac.orig_autoc;
d7bbcd32
DS		 1253 ixgbe_reset_pipeline_82599(hw);
1254
1255 if (got_lock)
1256 hw->mac.ops.release_swfw_sync(hw,
1257 IXGBE_GSSR_MAC_CSR_SM);
1258 }
11afc1b1
PW		 1259
1260 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1261 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1262 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1263 autoc2 |= (hw->mac.orig_autoc2 &
1264 IXGBE_AUTOC2_UPPER_MASK);
1265 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1266 }
1267 }
1268
278675d8
ET		 1269 /* Store the permanent mac address */
1270 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1271
aca6bee7
WJP		 1272 /*
1273 * Store MAC address from RAR0, clear receive address registers, and
1274 * clear the multicast table. Also reset num_rar_entries to 128,
1275 * since we modify this value when programming the SAN MAC address.
1276 */
1277 hw->mac.num_rar_entries = 128;
1278 hw->mac.ops.init_rx_addrs(hw);
1279
0365e6e4
PW		 1280 /* Store the permanent SAN mac address */
1281 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1282
aca6bee7 1283 /* Add the SAN MAC address to the RAR only if it's a valid address */
f8ebc683 1284 if (is_valid_ether_addr(hw->mac.san_addr)) {
aca6bee7
WJP		 1285 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1286 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1287
7fa7c9dc
AD		 1288 /* Save the SAN MAC RAR index */
1289 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1290
aca6bee7
WJP		 1291 /* Reserve the last RAR for the SAN MAC address */
1292 hw->mac.num_rar_entries--;
1293 }
1294
383ff34b
YZ		 1295 /* Store the alternative WWNN/WWPN prefix */
1296 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1297 &hw->mac.wwpn_prefix);
1298
04f165ef 1299reset_hw_out:
11afc1b1
PW		 1300 return status;
1301}
1302
ffff4772
PWJ		 1303/**
1304 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1305 * @hw: pointer to hardware structure
1306 **/
1307s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1308{
1309 int i;
1310 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1311 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1312
1313 /*
1314 * Before starting reinitialization process,
1315 * FDIRCMD.CMD must be zero.
1316 */
1317 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1318 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1319 IXGBE_FDIRCMD_CMD_MASK))
1320 break;
1321 udelay(10);
1322 }
1323 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
905e4a41 1324 hw_dbg(hw, "Flow Director previous command isn't complete, "
d6dbee86 1325 "aborting table re-initialization.\n");
ffff4772
PWJ		 1326 return IXGBE_ERR_FDIR_REINIT_FAILED;
1327 }
1328
1329 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1330 IXGBE_WRITE_FLUSH(hw);
1331 /*
1332 * 82599 adapters flow director init flow cannot be restarted,
1333 * Workaround 82599 silicon errata by performing the following steps
1334 * before re-writing the FDIRCTRL control register with the same value.
1335 * - write 1 to bit 8 of FDIRCMD register &
1336 * - write 0 to bit 8 of FDIRCMD register
1337 */
1338 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1339 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1340 IXGBE_FDIRCMD_CLEARHT));
1341 IXGBE_WRITE_FLUSH(hw);
1342 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1343 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1344 ~IXGBE_FDIRCMD_CLEARHT));
1345 IXGBE_WRITE_FLUSH(hw);
1346 /*
1347 * Clear FDIR Hash register to clear any leftover hashes
1348 * waiting to be programmed.
1349 */
1350 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1351 IXGBE_WRITE_FLUSH(hw);
1352
1353 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1354 IXGBE_WRITE_FLUSH(hw);
1355
1356 /* Poll init-done after we write FDIRCTRL register */
1357 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1358 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1359 IXGBE_FDIRCTRL_INIT_DONE)
1360 break;
4a97df0b 1361 usleep_range(1000, 2000);
ffff4772
PWJ		 1362 }
1363 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1364 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1365 return IXGBE_ERR_FDIR_REINIT_FAILED;
1366 }
1367
1368 /* Clear FDIR statistics registers (read to clear) */
1369 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1370 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1371 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1372 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1373 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1374
1375 return 0;
1376}
1377
ffff4772 1378/**
c04f6ca8 1379 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
ffff4772 1380 * @hw: pointer to hardware structure
c04f6ca8 1381 * @fdirctrl: value to write to flow director control register
ffff4772 1382 **/
c04f6ca8 1383static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
ffff4772 1384{
ffff4772
PWJ		 1385 int i;
1386
ffff4772 1387 /* Prime the keys for hashing */
905e4a41
AD		 1388 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1389 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
ffff4772
PWJ		 1390
1391 /*
1392 * Poll init-done after we write the register. Estimated times:
1393 * 10G: PBALLOC = 11b, timing is 60us
1394 * 1G: PBALLOC = 11b, timing is 600us
1395 * 100M: PBALLOC = 11b, timing is 6ms
1396 *
1397 * Multiple these timings by 4 if under full Rx load
1398 *
1399 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1400 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1401 * this might not finish in our poll time, but we can live with that
1402 * for now.
1403 */
ffff4772
PWJ		 1404 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1405 IXGBE_WRITE_FLUSH(hw);
1406 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1407 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1408 IXGBE_FDIRCTRL_INIT_DONE)
1409 break;
032b4325 1410 usleep_range(1000, 2000);
ffff4772 1411 }
ffff4772 1412
c04f6ca8
AD		 1413 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1414 hw_dbg(hw, "Flow Director poll time exceeded!\n");
ffff4772
PWJ		 1415}
1416
ffff4772 1417/**
c04f6ca8
AD		 1418 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1419 * @hw: pointer to hardware structure
1420 * @fdirctrl: value to write to flow director control register, initially
1421 * contains just the value of the Rx packet buffer allocation
ffff4772 1422 **/
c04f6ca8 1423s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
ffff4772 1424{
c04f6ca8
AD		 1425 /*
1426 * Continue setup of fdirctrl register bits:
1427 * Move the flexible bytes to use the ethertype - shift 6 words
1428 * Set the maximum length per hash bucket to 0xA filters
1429 * Send interrupt when 64 filters are left
1430 */
1431 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1432 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1433 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
ffff4772 1434
c04f6ca8
AD		 1435 /* write hashes and fdirctrl register, poll for completion */
1436 ixgbe_fdir_enable_82599(hw, fdirctrl);
ffff4772 1437
c04f6ca8
AD		 1438 return 0;
1439}
ffff4772 1440
c04f6ca8
AD		 1441/**
1442 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1443 * @hw: pointer to hardware structure
1444 * @fdirctrl: value to write to flow director control register, initially
1445 * contains just the value of the Rx packet buffer allocation
1446 **/
1447s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1448{
ffff4772 1449 /*
c04f6ca8
AD		 1450 * Continue setup of fdirctrl register bits:
1451 * Turn perfect match filtering on
1452 * Report hash in RSS field of Rx wb descriptor
1453 * Initialize the drop queue
1454 * Move the flexible bytes to use the ethertype - shift 6 words
1455 * Set the maximum length per hash bucket to 0xA filters
1456 * Send interrupt when 64 (0x4 * 16) filters are left
ffff4772 1457 */
c04f6ca8
AD		 1458 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1459 IXGBE_FDIRCTRL_REPORT_STATUS |
1460 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1461 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1462 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1463 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
ffff4772 1464
c04f6ca8
AD		 1465 /* write hashes and fdirctrl register, poll for completion */
1466 ixgbe_fdir_enable_82599(hw, fdirctrl);
905e4a41 1467
c04f6ca8 1468 return 0;
ffff4772
PWJ		 1469}
1470
69830529
AD		 1471/*
1472 * These defines allow us to quickly generate all of the necessary instructions
1473 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1474 * for values 0 through 15
1475 */
1476#define IXGBE_ATR_COMMON_HASH_KEY \
1477 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1478#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1479do { \
1480 u32 n = (_n); \
1481 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1482 common_hash ^= lo_hash_dword >> n; \
1483 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1484 bucket_hash ^= lo_hash_dword >> n; \
1485 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1486 sig_hash ^= lo_hash_dword << (16 - n); \
1487 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1488 common_hash ^= hi_hash_dword >> n; \
1489 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1490 bucket_hash ^= hi_hash_dword >> n; \
1491 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1492 sig_hash ^= hi_hash_dword << (16 - n); \
1493} while (0);
1494
1495/**
1496 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1497 * @stream: input bitstream to compute the hash on
1498 *
1499 * This function is almost identical to the function above but contains
1500 * several optomizations such as unwinding all of the loops, letting the
1501 * compiler work out all of the conditional ifs since the keys are static
1502 * defines, and computing two keys at once since the hashed dword stream
1503 * will be the same for both keys.
1504 **/
1505static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1506 union ixgbe_atr_hash_dword common)
1507{
1508 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1509 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1510
1511 /* record the flow_vm_vlan bits as they are a key part to the hash */
1512 flow_vm_vlan = ntohl(input.dword);
1513
1514 /* generate common hash dword */
1515 hi_hash_dword = ntohl(common.dword);
1516
1517 /* low dword is word swapped version of common */
1518 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1519
1520 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1521 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1522
1523 /* Process bits 0 and 16 */
1524 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1525
1526 /*
1527 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1528 * delay this because bit 0 of the stream should not be processed
1529 * so we do not add the vlan until after bit 0 was processed
1530 */
1531 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1532
1533 /* Process remaining 30 bit of the key */
1534 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1535 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1536 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1537 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1538 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1539 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1540 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1541 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1542 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1543 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1544 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1545 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1546 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1547 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1548 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1549
1550 /* combine common_hash result with signature and bucket hashes */
1551 bucket_hash ^= common_hash;
1552 bucket_hash &= IXGBE_ATR_HASH_MASK;
1553
1554 sig_hash ^= common_hash << 16;
1555 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1556
1557 /* return completed signature hash */
1558 return sig_hash ^ bucket_hash;
1559}
1560
ffff4772
PWJ		 1561/**
1562 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1563 * @hw: pointer to hardware structure
69830529
AD		 1564 * @input: unique input dword
1565 * @common: compressed common input dword
ffff4772
PWJ		 1566 * @queue: queue index to direct traffic to
1567 **/
1568s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 1569 union ixgbe_atr_hash_dword input,
1570 union ixgbe_atr_hash_dword common,
ffff4772
PWJ		 1571 u8 queue)
1572{
1573 u64 fdirhashcmd;
905e4a41 1574 u32 fdircmd;
ffff4772
PWJ		 1575
1576 /*
905e4a41
AD		 1577 * Get the flow_type in order to program FDIRCMD properly
1578 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
ffff4772 1579 */
69830529 1580 switch (input.formatted.flow_type) {
905e4a41
AD		 1581 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1582 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1583 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1584 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1585 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1586 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
ffff4772
PWJ		 1587 break;
1588 default:
905e4a41 1589 hw_dbg(hw, " Error on flow type input\n");
ffff4772
PWJ		 1590 return IXGBE_ERR_CONFIG;
1591 }
1592
905e4a41
AD		 1593 /* configure FDIRCMD register */
1594 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1595 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
69830529 1596 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
905e4a41
AD		 1597 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1598
1599 /*
1600 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1601 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1602 */
1603 fdirhashcmd = (u64)fdircmd << 32;
69830529 1604 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
ffff4772
PWJ		 1605 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1606
69830529
AD		 1607 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1608
ffff4772
PWJ		 1609 return 0;
1610}
1611
c04f6ca8
AD		 1612#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1613do { \
1614 u32 n = (_n); \
1615 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1616 bucket_hash ^= lo_hash_dword >> n; \
1617 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1618 bucket_hash ^= hi_hash_dword >> n; \
1619} while (0);
1620
1621/**
1622 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1623 * @atr_input: input bitstream to compute the hash on
1624 * @input_mask: mask for the input bitstream
1625 *
1626 * This function serves two main purposes. First it applys the input_mask
1627 * to the atr_input resulting in a cleaned up atr_input data stream.
1628 * Secondly it computes the hash and stores it in the bkt_hash field at
1629 * the end of the input byte stream. This way it will be available for
1630 * future use without needing to recompute the hash.
1631 **/
1632void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1633 union ixgbe_atr_input *input_mask)
1634{
1635
1636 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1637 u32 bucket_hash = 0;
1638
1639 /* Apply masks to input data */
1640 input->dword_stream[0] &= input_mask->dword_stream[0];
1641 input->dword_stream[1] &= input_mask->dword_stream[1];
1642 input->dword_stream[2] &= input_mask->dword_stream[2];
1643 input->dword_stream[3] &= input_mask->dword_stream[3];
1644 input->dword_stream[4] &= input_mask->dword_stream[4];
1645 input->dword_stream[5] &= input_mask->dword_stream[5];
1646 input->dword_stream[6] &= input_mask->dword_stream[6];
1647 input->dword_stream[7] &= input_mask->dword_stream[7];
1648 input->dword_stream[8] &= input_mask->dword_stream[8];
1649 input->dword_stream[9] &= input_mask->dword_stream[9];
1650 input->dword_stream[10] &= input_mask->dword_stream[10];
1651
1652 /* record the flow_vm_vlan bits as they are a key part to the hash */
1653 flow_vm_vlan = ntohl(input->dword_stream[0]);
1654
1655 /* generate common hash dword */
1656 hi_hash_dword = ntohl(input->dword_stream[1] ^
1657 input->dword_stream[2] ^
1658 input->dword_stream[3] ^
1659 input->dword_stream[4] ^
1660 input->dword_stream[5] ^
1661 input->dword_stream[6] ^
1662 input->dword_stream[7] ^
1663 input->dword_stream[8] ^
1664 input->dword_stream[9] ^
1665 input->dword_stream[10]);
1666
1667 /* low dword is word swapped version of common */
1668 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1669
1670 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1671 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1672
1673 /* Process bits 0 and 16 */
1674 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1675
1676 /*
1677 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1678 * delay this because bit 0 of the stream should not be processed
1679 * so we do not add the vlan until after bit 0 was processed
1680 */
1681 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1682
1683 /* Process remaining 30 bit of the key */
1684 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1685 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1686 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1687 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1688 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1689 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1690 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1691 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1692 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1693 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1694 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1695 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1696 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1697 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1698 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1699
1700 /*
1701 * Limit hash to 13 bits since max bucket count is 8K.
1702 * Store result at the end of the input stream.
1703 */
1704 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1705}
1706
45b9f509
AD		 1707/**
1708 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1709 * @input_mask: mask to be bit swapped
1710 *
1711 * The source and destination port masks for flow director are bit swapped
1712 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1713 * generate a correctly swapped value we need to bit swap the mask and that
1714 * is what is accomplished by this function.
1715 **/
c04f6ca8 1716static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
45b9f509 1717{
c04f6ca8 1718 u32 mask = ntohs(input_mask->formatted.dst_port);
45b9f509 1719 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
c04f6ca8 1720 mask |= ntohs(input_mask->formatted.src_port);
45b9f509
AD		 1721 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1722 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1723 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1724 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1725}
1726
1727/*
1728 * These two macros are meant to address the fact that we have registers
1729 * that are either all or in part big-endian. As a result on big-endian
1730 * systems we will end up byte swapping the value to little-endian before
1731 * it is byte swapped again and written to the hardware in the original
1732 * big-endian format.
1733 */
1734#define IXGBE_STORE_AS_BE32(_value) \
1735 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1736 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1737
1738#define IXGBE_WRITE_REG_BE32(a, reg, value) \
1739 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1740
1741#define IXGBE_STORE_AS_BE16(_value) \
c04f6ca8 1742 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
45b9f509 1743
c04f6ca8
AD		 1744s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1745 union ixgbe_atr_input *input_mask)
ffff4772 1746{
c04f6ca8
AD		 1747 /* mask IPv6 since it is currently not supported */
1748 u32 fdirm = IXGBE_FDIRM_DIPv6;
1749 u32 fdirtcpm;
ffff4772 1750
9a713e7c 1751 /*
45b9f509
AD		 1752 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1753 * are zero, then assume a full mask for that field. Also assume that
1754 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1755 * cannot be masked out in this implementation.
9a713e7c
PW		 1756 *
1757 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1758 * point in time.
1759 */
45b9f509 1760
c04f6ca8
AD		 1761 /* verify bucket hash is cleared on hash generation */
1762 if (input_mask->formatted.bkt_hash)
1763 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1764
1765 /* Program FDIRM and verify partial masks */
1766 switch (input_mask->formatted.vm_pool & 0x7F) {
1767 case 0x0:
1768 fdirm |= IXGBE_FDIRM_POOL;
1769 case 0x7F:
9a713e7c 1770 break;
c04f6ca8
AD		 1771 default:
1772 hw_dbg(hw, " Error on vm pool mask\n");
1773 return IXGBE_ERR_CONFIG;
1774 }
1775
1776 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1777 case 0x0:
1778 fdirm |= IXGBE_FDIRM_L4P;
1779 if (input_mask->formatted.dst_port ||
1780 input_mask->formatted.src_port) {
1781 hw_dbg(hw, " Error on src/dst port mask\n");
1782 return IXGBE_ERR_CONFIG;
1783 }
1784 case IXGBE_ATR_L4TYPE_MASK:
9a713e7c 1785 break;
c04f6ca8
AD		 1786 default:
1787 hw_dbg(hw, " Error on flow type mask\n");
1788 return IXGBE_ERR_CONFIG;
1789 }
1790
1791 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
45b9f509 1792 case 0x0000:
c04f6ca8
AD		 1793 /* mask VLAN ID, fall through to mask VLAN priority */
1794 fdirm |= IXGBE_FDIRM_VLANID;
1795 case 0x0FFF:
1796 /* mask VLAN priority */
1797 fdirm |= IXGBE_FDIRM_VLANP;
1798 break;
1799 case 0xE000:
1800 /* mask VLAN ID only, fall through */
1801 fdirm |= IXGBE_FDIRM_VLANID;
1802 case 0xEFFF:
1803 /* no VLAN fields masked */
9a713e7c 1804 break;
45b9f509
AD		 1805 default:
1806 hw_dbg(hw, " Error on VLAN mask\n");
1807 return IXGBE_ERR_CONFIG;
9a713e7c
PW		 1808 }
1809
c04f6ca8
AD		 1810 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1811 case 0x0000:
1812 /* Mask Flex Bytes, fall through */
1813 fdirm |= IXGBE_FDIRM_FLEX;
1814 case 0xFFFF:
1815 break;
1816 default:
1817 hw_dbg(hw, " Error on flexible byte mask\n");
1818 return IXGBE_ERR_CONFIG;
45b9f509 1819 }
9a713e7c
PW		 1820
1821 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
9a713e7c 1822 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
ffff4772 1823
45b9f509 1824 /* store the TCP/UDP port masks, bit reversed from port layout */
c04f6ca8 1825 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
45b9f509
AD		 1826
1827 /* write both the same so that UDP and TCP use the same mask */
1828 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1829 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1830
1831 /* store source and destination IP masks (big-enian) */
1832 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
c04f6ca8 1833 ~input_mask->formatted.src_ip[0]);
45b9f509 1834 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
c04f6ca8 1835 ~input_mask->formatted.dst_ip[0]);
45b9f509 1836
c04f6ca8
AD		 1837 return 0;
1838}
45b9f509 1839
c04f6ca8
AD		 1840s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1841 union ixgbe_atr_input *input,
1842 u16 soft_id, u8 queue)
1843{
1844 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1845
1846 /* currently IPv6 is not supported, must be programmed with 0 */
1847 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1848 input->formatted.src_ip[0]);
1849 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1850 input->formatted.src_ip[1]);
1851 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1852 input->formatted.src_ip[2]);
1853
1854 /* record the source address (big-endian) */
1855 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1856
1857 /* record the first 32 bits of the destination address (big-endian) */
1858 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
45b9f509
AD		 1859
1860 /* record source and destination port (little-endian)*/
1861 fdirport = ntohs(input->formatted.dst_port);
1862 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1863 fdirport |= ntohs(input->formatted.src_port);
1864 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1865
c04f6ca8
AD		 1866 /* record vlan (little-endian) and flex_bytes(big-endian) */
1867 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1868 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1869 fdirvlan |= ntohs(input->formatted.vlan_id);
1870 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
45b9f509 1871
c04f6ca8
AD		 1872 /* configure FDIRHASH register */
1873 fdirhash = input->formatted.bkt_hash;
1874 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1875 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1876
1877 /*
1878 * flush all previous writes to make certain registers are
1879 * programmed prior to issuing the command
1880 */
1881 IXGBE_WRITE_FLUSH(hw);
45b9f509
AD		 1882
1883 /* configure FDIRCMD register */
1884 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1885 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
c04f6ca8
AD		 1886 if (queue == IXGBE_FDIR_DROP_QUEUE)
1887 fdircmd |= IXGBE_FDIRCMD_DROP;
45b9f509
AD		 1888 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1889 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
c04f6ca8 1890 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
45b9f509 1891
ffff4772
PWJ		 1892 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1893
1894 return 0;
1895}
45b9f509 1896
c04f6ca8
AD		 1897s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1898 union ixgbe_atr_input *input,
1899 u16 soft_id)
1900{
1901 u32 fdirhash;
1902 u32 fdircmd = 0;
1903 u32 retry_count;
1904 s32 err = 0;
1905
1906 /* configure FDIRHASH register */
1907 fdirhash = input->formatted.bkt_hash;
1908 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1909 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1910
1911 /* flush hash to HW */
1912 IXGBE_WRITE_FLUSH(hw);
1913
1914 /* Query if filter is present */
1915 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1916
1917 for (retry_count = 10; retry_count; retry_count--) {
1918 /* allow 10us for query to process */
1919 udelay(10);
1920 /* verify query completed successfully */
1921 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1922 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1923 break;
1924 }
1925
1926 if (!retry_count)
1927 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1928
1929 /* if filter exists in hardware then remove it */
1930 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1931 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1932 IXGBE_WRITE_FLUSH(hw);
1933 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1934 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1935 }
1936
1937 return err;
1938}
1939
11afc1b1
PW		 1940/**
1941 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1942 * @hw: pointer to hardware structure
1943 * @reg: analog register to read
1944 * @val: read value
1945 *
1946 * Performs read operation to Omer analog register specified.
1947 **/
7b25cdba 1948static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 1949{
1950 u32 core_ctl;
1951
1952 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1953 (reg << 8));
1954 IXGBE_WRITE_FLUSH(hw);
1955 udelay(10);
1956 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1957 *val = (u8)core_ctl;
1958
1959 return 0;
1960}
1961
1962/**
1963 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1964 * @hw: pointer to hardware structure
1965 * @reg: atlas register to write
1966 * @val: value to write
1967 *
1968 * Performs write operation to Omer analog register specified.
1969 **/
7b25cdba 1970static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 1971{
1972 u32 core_ctl;
1973
1974 core_ctl = (reg << 8) | val;
1975 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1976 IXGBE_WRITE_FLUSH(hw);
1977 udelay(10);
1978
1979 return 0;
1980}
1981
1982/**
1983 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1984 * @hw: pointer to hardware structure
1985 *
7184b7cf
ET		 1986 * Starts the hardware using the generic start_hw function
1987 * and the generation start_hw function.
1988 * Then performs revision-specific operations, if any.
11afc1b1 1989 **/
7b25cdba 1990static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1 1991{
7184b7cf 1992 s32 ret_val = 0;
11afc1b1 1993
794caeb2 1994 ret_val = ixgbe_start_hw_generic(hw);
7184b7cf
ET		 1995 if (ret_val != 0)
1996 goto out;
11afc1b1 1997
7184b7cf
ET		 1998 ret_val = ixgbe_start_hw_gen2(hw);
1999 if (ret_val != 0)
2000 goto out;
11afc1b1 2001
50ac58ba
PWJ		 2002 /* We need to run link autotry after the driver loads */
2003 hw->mac.autotry_restart = true;
e09ad236 2004 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
50ac58ba 2005
794caeb2
PWJ		 2006 if (ret_val == 0)
2007 ret_val = ixgbe_verify_fw_version_82599(hw);
7184b7cf 2008out:
794caeb2 2009 return ret_val;
11afc1b1
PW		 2010}
2011
2012/**
2013 * ixgbe_identify_phy_82599 - Get physical layer module
2014 * @hw: pointer to hardware structure
2015 *
2016 * Determines the physical layer module found on the current adapter.
21cc5b4f
ET		 2017 * If PHY already detected, maintains current PHY type in hw struct,
2018 * otherwise executes the PHY detection routine.
11afc1b1 2019 **/
d6cd8e0e 2020static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2021{
2022 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
21cc5b4f
ET		 2023
2024 /* Detect PHY if not unknown - returns success if already detected. */
11afc1b1 2025 status = ixgbe_identify_phy_generic(hw);
21cc5b4f
ET		 2026 if (status != 0) {
2027 /* 82599 10GBASE-T requires an external PHY */
2028 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2029 goto out;
2030 else
8f58332b 2031 status = ixgbe_identify_module_generic(hw);
21cc5b4f
ET		 2032 }
2033
2034 /* Set PHY type none if no PHY detected */
2035 if (hw->phy.type == ixgbe_phy_unknown) {
2036 hw->phy.type = ixgbe_phy_none;
2037 status = 0;
2038 }
2039
2040 /* Return error if SFP module has been detected but is not supported */
2041 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2042 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
2043
2044out:
11afc1b1
PW		 2045 return status;
2046}
2047
2048/**
2049 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2050 * @hw: pointer to hardware structure
2051 *
2052 * Determines physical layer capabilities of the current configuration.
2053 **/
7b25cdba 2054static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2055{
2056 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 2057 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2058 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2059 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2060 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2061 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2062 u16 ext_ability = 0;
1339b9e9 2063 u8 comp_codes_10g = 0;
cb836a97 2064 u8 comp_codes_1g = 0;
11afc1b1 2065
04193058
PWJ		 2066 hw->phy.ops.identify(hw);
2067
21cc5b4f
ET		 2068 switch (hw->phy.type) {
2069 case ixgbe_phy_tn:
21cc5b4f 2070 case ixgbe_phy_cu_unknown:
6b73e10d 2071 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
21cc5b4f 2072 &ext_ability);
6b73e10d 2073 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2074 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2075 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2076 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2077 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2078 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2079 goto out;
21cc5b4f
ET		 2080 default:
2081 break;
04193058
PWJ		 2082 }
2083
2084 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2085 case IXGBE_AUTOC_LMS_1G_AN:
2086 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2087 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2088 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2089 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2090 goto out;
2091 } else
2092 /* SFI mode so read SFP module */
2093 goto sfp_check;
11afc1b1 2094 break;
04193058
PWJ		 2095 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2096 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2097 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2098 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2099 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2100 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2101 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2102 goto out;
2103 break;
2104 case IXGBE_AUTOC_LMS_10G_SERIAL:
2105 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2106 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2107 goto out;
2108 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2109 goto sfp_check;
2110 break;
2111 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2112 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2113 if (autoc & IXGBE_AUTOC_KX_SUPP)
2114 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2115 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2116 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2117 if (autoc & IXGBE_AUTOC_KR_SUPP)
2118 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2119 goto out;
2120 break;
2121 default:
2122 goto out;
2123 break;
2124 }
11afc1b1 2125
04193058
PWJ		 2126sfp_check:
2127 /* SFP check must be done last since DA modules are sometimes used to
2128 * test KR mode - we need to id KR mode correctly before SFP module.
2129 * Call identify_sfp because the pluggable module may have changed */
2130 hw->phy.ops.identify_sfp(hw);
2131 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2132 goto out;
2133
2134 switch (hw->phy.type) {
ea0a04df
DS		 2135 case ixgbe_phy_sfp_passive_tyco:
2136 case ixgbe_phy_sfp_passive_unknown:
8f58332b 2137 case ixgbe_phy_qsfp_passive_unknown:
04193058
PWJ		 2138 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2139 break;
ea0a04df
DS		 2140 case ixgbe_phy_sfp_ftl_active:
2141 case ixgbe_phy_sfp_active_unknown:
8f58332b 2142 case ixgbe_phy_qsfp_active_unknown:
ea0a04df
DS		 2143 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2144 break;
04193058
PWJ		 2145 case ixgbe_phy_sfp_avago:
2146 case ixgbe_phy_sfp_ftl:
2147 case ixgbe_phy_sfp_intel:
2148 case ixgbe_phy_sfp_unknown:
cb836a97
DS		 2149 hw->phy.ops.read_i2c_eeprom(hw,
2150 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
04193058
PWJ		 2151 hw->phy.ops.read_i2c_eeprom(hw,
2152 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2153 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2154 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2155 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2156 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
cb836a97
DS		 2157 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2158 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
11afc1b1 2159 break;
8f58332b
DS		 2160 case ixgbe_phy_qsfp_intel:
2161 case ixgbe_phy_qsfp_unknown:
2162 hw->phy.ops.read_i2c_eeprom(hw,
2163 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
2164 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2165 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2166 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2167 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2168 break;
11afc1b1 2169 default:
11afc1b1
PW		 2170 break;
2171 }
2172
04193058 2173out:
11afc1b1
PW		 2174 return physical_layer;
2175}
2176
2177/**
2178 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2179 * @hw: pointer to hardware structure
2180 * @regval: register value to write to RXCTRL
2181 *
2182 * Enables the Rx DMA unit for 82599
2183 **/
7b25cdba 2184static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1 2185{
11afc1b1
PW		 2186 /*
2187 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2188 * If traffic is incoming before we enable the Rx unit, it could hang
2189 * the Rx DMA unit. Therefore, make sure the security engine is
2190 * completely disabled prior to enabling the Rx unit.
2191 */
d2f5e7f3 2192 hw->mac.ops.disable_rx_buff(hw);
11afc1b1
PW		 2193
2194 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
d2f5e7f3
AS		 2195
2196 hw->mac.ops.enable_rx_buff(hw);
11afc1b1
PW		 2197
2198 return 0;
2199}
2200
794caeb2
PWJ		 2201/**
2202 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2203 * @hw: pointer to hardware structure
2204 *
2205 * Verifies that installed the firmware version is 0.6 or higher
2206 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2207 *
2208 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2209 * if the FW version is not supported.
2210 **/
2211static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2212{
2213 s32 status = IXGBE_ERR_EEPROM_VERSION;
2214 u16 fw_offset, fw_ptp_cfg_offset;
be0c27b4 2215 u16 offset;
794caeb2
PWJ		 2216 u16 fw_version = 0;
2217
2218 /* firmware check is only necessary for SFI devices */
2219 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2220 status = 0;
2221 goto fw_version_out;
2222 }
2223
2224 /* get the offset to the Firmware Module block */
be0c27b4
MR		 2225 offset = IXGBE_FW_PTR;
2226 if (hw->eeprom.ops.read(hw, offset, &fw_offset))
2227 goto fw_version_err;
794caeb2
PWJ		 2228
2229 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2230 goto fw_version_out;
2231
2232 /* get the offset to the Pass Through Patch Configuration block */
be0c27b4
MR		 2233 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR;
2234 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset))
2235 goto fw_version_err;
794caeb2
PWJ		 2236
2237 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2238 goto fw_version_out;
2239
2240 /* get the firmware version */
be0c27b4
MR		 2241 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4;
2242 if (hw->eeprom.ops.read(hw, offset, &fw_version))
2243 goto fw_version_err;
794caeb2
PWJ		 2244
2245 if (fw_version > 0x5)
2246 status = 0;
2247
2248fw_version_out:
2249 return status;
be0c27b4
MR		 2250
2251fw_version_err:
2252 hw_err(hw, "eeprom read at offset %d failed\n", offset);
2253 return IXGBE_ERR_EEPROM_VERSION;
794caeb2
PWJ		 2254}
2255
0fa6d832
ET		 2256/**
2257 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2258 * @hw: pointer to hardware structure
2259 *
2260 * Returns true if the LESM FW module is present and enabled. Otherwise
2261 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2262 **/
d7bbcd32 2263bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
0fa6d832
ET		 2264{
2265 bool lesm_enabled = false;
2266 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2267 s32 status;
2268
2269 /* get the offset to the Firmware Module block */
2270 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2271
2272 if ((status != 0) ||
2273 (fw_offset == 0) || (fw_offset == 0xFFFF))
2274 goto out;
2275
2276 /* get the offset to the LESM Parameters block */
2277 status = hw->eeprom.ops.read(hw, (fw_offset +
2278 IXGBE_FW_LESM_PARAMETERS_PTR),
2279 &fw_lesm_param_offset);
2280
2281 if ((status != 0) ||
2282 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2283 goto out;
2284
2285 /* get the lesm state word */
2286 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2287 IXGBE_FW_LESM_STATE_1),
2288 &fw_lesm_state);
2289
2290 if ((status == 0) &&
2291 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2292 lesm_enabled = true;
2293
2294out:
2295 return lesm_enabled;
2296}
2297
68c7005d
ET		 2298/**
2299 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2300 * fastest available method
2301 *
2302 * @hw: pointer to hardware structure
2303 * @offset: offset of word in EEPROM to read
2304 * @words: number of words
2305 * @data: word(s) read from the EEPROM
2306 *
2307 * Retrieves 16 bit word(s) read from EEPROM
2308 **/
2309static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2310 u16 words, u16 *data)
2311{
2312 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2313 s32 ret_val = IXGBE_ERR_CONFIG;
2314
2315 /*
2316 * If EEPROM is detected and can be addressed using 14 bits,
2317 * use EERD otherwise use bit bang
2318 */
2319 if ((eeprom->type == ixgbe_eeprom_spi) &&
2320 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2321 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2322 data);
2323 else
2324 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2325 words,
2326 data);
2327
2328 return ret_val;
2329}
2330
0665b09f
ET		 2331/**
2332 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2333 * fastest available method
2334 *
2335 * @hw: pointer to hardware structure
2336 * @offset: offset of word in the EEPROM to read
2337 * @data: word read from the EEPROM
2338 *
2339 * Reads a 16 bit word from the EEPROM
2340 **/
2341static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2342 u16 offset, u16 *data)
2343{
2344 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2345 s32 ret_val = IXGBE_ERR_CONFIG;
2346
2347 /*
2348 * If EEPROM is detected and can be addressed using 14 bits,
2349 * use EERD otherwise use bit bang
2350 */
2351 if ((eeprom->type == ixgbe_eeprom_spi) &&
2352 (offset <= IXGBE_EERD_MAX_ADDR))
2353 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2354 else
2355 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2356
2357 return ret_val;
2358}
2359
de52a12c
DS		 2360/**
2361 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2362 *
2363 * @hw: pointer to hardware structure
2364 *
2365 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2366 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2367 * to AUTOC, so this function assumes the semaphore is held.
2368 **/
2369s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2370{
46d5cedd
ET		 2371 s32 ret_val;
2372 u32 anlp1_reg = 0;
2373 u32 i, autoc_reg, autoc2_reg;
2374
2375 /* Enable link if disabled in NVM */
2376 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2377 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2378 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2379 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2380 IXGBE_WRITE_FLUSH(hw);
2381 }
de52a12c 2382
5e82f2f0 2383 autoc_reg = hw->mac.cached_autoc;
de52a12c
DS		 2384 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2385
2386 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2387 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2388
2389 /* Wait for AN to leave state 0 */
2390 for (i = 0; i < 10; i++) {
2391 usleep_range(4000, 8000);
2392 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2393 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2394 break;
2395 }
2396
2397 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2398 hw_dbg(hw, "auto negotiation not completed\n");
2399 ret_val = IXGBE_ERR_RESET_FAILED;
2400 goto reset_pipeline_out;
2401 }
2402
2403 ret_val = 0;
2404
2405reset_pipeline_out:
2406 /* Write AUTOC register with original LMS field and Restart_AN */
2407 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2408 IXGBE_WRITE_FLUSH(hw);
2409
2410 return ret_val;
2411}
2412
8f58332b
DS		 2413/**
2414 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2415 * @hw: pointer to hardware structure
2416 * @byte_offset: byte offset to read
2417 * @data: value read
2418 *
2419 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2420 * a specified device address.
2421 **/
2422static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2423 u8 dev_addr, u8 *data)
2424{
2425 u32 esdp;
2426 s32 status;
2427 s32 timeout = 200;
2428
2429 if (hw->phy.qsfp_shared_i2c_bus == true) {
2430 /* Acquire I2C bus ownership. */
2431 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2432 esdp |= IXGBE_ESDP_SDP0;
2433 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2434 IXGBE_WRITE_FLUSH(hw);
2435
2436 while (timeout) {
2437 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2438 if (esdp & IXGBE_ESDP_SDP1)
2439 break;
2440
2441 usleep_range(5000, 10000);
2442 timeout--;
2443 }
2444
2445 if (!timeout) {
2446 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2447 status = IXGBE_ERR_I2C;
2448 goto release_i2c_access;
2449 }
2450 }
2451
2452 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2453
2454release_i2c_access:
2455 if (hw->phy.qsfp_shared_i2c_bus == true) {
2456 /* Release I2C bus ownership. */
2457 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2458 esdp &= ~IXGBE_ESDP_SDP0;
2459 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2460 IXGBE_WRITE_FLUSH(hw);
2461 }
2462
2463 return status;
2464}
2465
2466/**
2467 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2468 * @hw: pointer to hardware structure
2469 * @byte_offset: byte offset to write
2470 * @data: value to write
2471 *
2472 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2473 * a specified device address.
2474 **/
2475static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2476 u8 dev_addr, u8 data)
2477{
2478 u32 esdp;
2479 s32 status;
2480 s32 timeout = 200;
2481
2482 if (hw->phy.qsfp_shared_i2c_bus == true) {
2483 /* Acquire I2C bus ownership. */
2484 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2485 esdp |= IXGBE_ESDP_SDP0;
2486 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2487 IXGBE_WRITE_FLUSH(hw);
2488
2489 while (timeout) {
2490 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2491 if (esdp & IXGBE_ESDP_SDP1)
2492 break;
2493
2494 usleep_range(5000, 10000);
2495 timeout--;
2496 }
2497
2498 if (!timeout) {
2499 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2500 status = IXGBE_ERR_I2C;
2501 goto release_i2c_access;
2502 }
2503 }
2504
2505 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2506
2507release_i2c_access:
2508 if (hw->phy.qsfp_shared_i2c_bus == true) {
2509 /* Release I2C bus ownership. */
2510 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2511 esdp &= ~IXGBE_ESDP_SDP0;
2512 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2513 IXGBE_WRITE_FLUSH(hw);
2514 }
2515
2516 return status;
2517}
2518
11afc1b1
PW		 2519static struct ixgbe_mac_operations mac_ops_82599 = {
2520 .init_hw = &ixgbe_init_hw_generic,
2521 .reset_hw = &ixgbe_reset_hw_82599,
2522 .start_hw = &ixgbe_start_hw_82599,
2523 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2524 .get_media_type = &ixgbe_get_media_type_82599,
2525 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2526 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
d2f5e7f3
AS		 2527 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2528 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
11afc1b1 2529 .get_mac_addr = &ixgbe_get_mac_addr_generic,
21ce849b 2530 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
b776d104 2531 .get_device_caps = &ixgbe_get_device_caps_generic,
a391f1d5 2532 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
11afc1b1
PW		 2533 .stop_adapter = &ixgbe_stop_adapter_generic,
2534 .get_bus_info = &ixgbe_get_bus_info_generic,
2535 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2536 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2537 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
f4f1040a 2538 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599,
11afc1b1 2539 .setup_link = &ixgbe_setup_mac_link_82599,
80605c65 2540 .set_rxpba = &ixgbe_set_rxpba_generic,
21ce849b 2541 .check_link = &ixgbe_check_mac_link_generic,
11afc1b1
PW		 2542 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2543 .led_on = &ixgbe_led_on_generic,
2544 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2545 .blink_led_start = &ixgbe_blink_led_start_generic,
2546 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2547 .set_rar = &ixgbe_set_rar_generic,
2548 .clear_rar = &ixgbe_clear_rar_generic,
21ce849b 2549 .set_vmdq = &ixgbe_set_vmdq_generic,
7fa7c9dc 2550 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
21ce849b 2551 .clear_vmdq = &ixgbe_clear_vmdq_generic,
11afc1b1 2552 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
11afc1b1
PW		 2553 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2554 .enable_mc = &ixgbe_enable_mc_generic,
2555 .disable_mc = &ixgbe_disable_mc_generic,
21ce849b
MC		 2556 .clear_vfta = &ixgbe_clear_vfta_generic,
2557 .set_vfta = &ixgbe_set_vfta_generic,
2558 .fc_enable = &ixgbe_fc_enable_generic,
9612de92 2559 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
21ce849b 2560 .init_uta_tables = &ixgbe_init_uta_tables_generic,
11afc1b1 2561 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
a985b6c3
GR		 2562 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2563 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
5e655105
DS		 2564 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2565 .release_swfw_sync = &ixgbe_release_swfw_sync,
3ca8bc6d
DS		 2566 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2567 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
0b2679d6 2568 .mng_fw_enabled = &ixgbe_mng_enabled,
11afc1b1
PW		 2569};
2570
2571static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
037c6d0a 2572 .init_params = &ixgbe_init_eeprom_params_generic,
0665b09f 2573 .read = &ixgbe_read_eeprom_82599,
68c7005d 2574 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
037c6d0a 2575 .write = &ixgbe_write_eeprom_generic,
68c7005d 2576 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
037c6d0a
ET		 2577 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2578 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2579 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
11afc1b1
PW		 2580};
2581
2582static struct ixgbe_phy_operations phy_ops_82599 = {
037c6d0a 2583 .identify = &ixgbe_identify_phy_82599,
8f58332b 2584 .identify_sfp = &ixgbe_identify_module_generic,
037c6d0a
ET		 2585 .init = &ixgbe_init_phy_ops_82599,
2586 .reset = &ixgbe_reset_phy_generic,
2587 .read_reg = &ixgbe_read_phy_reg_generic,
2588 .write_reg = &ixgbe_write_phy_reg_generic,
2589 .setup_link = &ixgbe_setup_phy_link_generic,
2590 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2591 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2592 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
07ce870b 2593 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
037c6d0a
ET		 2594 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2595 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2596 .check_overtemp = &ixgbe_tn_check_overtemp,
11afc1b1
PW		 2597};
2598
2599struct ixgbe_info ixgbe_82599_info = {
2600 .mac = ixgbe_mac_82599EB,
2601 .get_invariants = &ixgbe_get_invariants_82599,
2602 .mac_ops = &mac_ops_82599,
2603 .eeprom_ops = &eeprom_ops_82599,
2604 .phy_ops = &phy_ops_82599,
a391f1d5 2605 .mbx_ops = &mbx_ops_generic,
11afc1b1 2606};
Linux 6.x block layer and io_uring tree(s)