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ixgbe: clean up ixgbe_atr_compute_perfect_hash_82599
[linux-2.6-block.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
c97506ab 4 Copyright(c) 1999 - 2014 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
11afc1b1
PW		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
33#include "ixgbe.h"
34#include "ixgbe_phy.h"
096a58fd 35#include "ixgbe_mbx.h"
11afc1b1
PW		 36
37#define IXGBE_82599_MAX_TX_QUEUES 128
38#define IXGBE_82599_MAX_RX_QUEUES 128
39#define IXGBE_82599_RAR_ENTRIES 128
40#define IXGBE_82599_MC_TBL_SIZE 128
41#define IXGBE_82599_VFT_TBL_SIZE 128
e09ad236 42#define IXGBE_82599_RX_PB_SIZE 512
11afc1b1 43
5d5b7c39
ET		 44static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
47static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
5d5b7c39 49 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 50static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
cd7e1f0b 52 bool autoneg_wait_to_complete);
f4f1040a 53static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
5d5b7c39
ET		 54static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
8620a103 57 ixgbe_link_speed speed,
8620a103 58 bool autoneg_wait_to_complete);
8620a103
MC		 59static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
8620a103 61 bool autoneg_wait_to_complete);
794caeb2 62static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
8f58332b
DS		 63static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
64 u8 dev_addr, u8 *data);
65static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
66 u8 dev_addr, u8 data);
429d6a3b
DS		 67static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
68static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
11afc1b1 69
0b2679d6
DS		 70static bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
71{
72 u32 fwsm, manc, factps;
73
74 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
75 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
76 return false;
77
78 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
79 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
80 return false;
81
82 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
83 if (factps & IXGBE_FACTPS_MNGCG)
84 return false;
85
86 return true;
87}
88
7b25cdba 89static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 90{
91 struct ixgbe_mac_info *mac = &hw->mac;
c6ecf39a 92
0b2679d6
DS		 93 /* enable the laser control functions for SFP+ fiber
94 * and MNG not enabled
95 */
96 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
97 !hw->mng_fw_enabled) {
61fac744
PW		 98 mac->ops.disable_tx_laser =
99 &ixgbe_disable_tx_laser_multispeed_fiber;
100 mac->ops.enable_tx_laser =
101 &ixgbe_enable_tx_laser_multispeed_fiber;
1097cd17 102 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
11afc1b1 103 } else {
61fac744
PW		 104 mac->ops.disable_tx_laser = NULL;
105 mac->ops.enable_tx_laser = NULL;
1097cd17 106 mac->ops.flap_tx_laser = NULL;
c6ecf39a
DS		 107 }
108
109 if (hw->phy.multispeed_fiber) {
110 /* Set up dual speed SFP+ support */
111 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
112 } else {
cd7e1f0b
DS		 113 if ((mac->ops.get_media_type(hw) ==
114 ixgbe_media_type_backplane) &&
115 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
0fa6d832
ET		 116 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
117 !ixgbe_verify_lesm_fw_enabled_82599(hw))
cd7e1f0b
DS		 118 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
119 else
120 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 121 }
122}
123
7b25cdba 124static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 125{
126 s32 ret_val = 0;
127 u16 list_offset, data_offset, data_value;
128
129 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
130 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 131
132 hw->phy.ops.reset = NULL;
133
11afc1b1
PW		 134 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
135 &data_offset);
11afc1b1
PW		 136 if (ret_val != 0)
137 goto setup_sfp_out;
138
aa5aec88 139 /* PHY config will finish before releasing the semaphore */
5e655105
DS		 140 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
141 IXGBE_GSSR_MAC_CSR_SM);
aa5aec88
PWJ		 142 if (ret_val != 0) {
143 ret_val = IXGBE_ERR_SWFW_SYNC;
144 goto setup_sfp_out;
145 }
146
be0c27b4
MR		 147 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
148 goto setup_sfp_err;
11afc1b1
PW		 149 while (data_value != 0xffff) {
150 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
151 IXGBE_WRITE_FLUSH(hw);
be0c27b4
MR		 152 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
153 goto setup_sfp_err;
11afc1b1 154 }
aa5aec88
PWJ		 155
156 /* Release the semaphore */
6d980c3e 157 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
032b4325
DS		 158 /*
159 * Delay obtaining semaphore again to allow FW access,
160 * semaphore_delay is in ms usleep_range needs us.
161 */
162 usleep_range(hw->eeprom.semaphore_delay * 1000,
163 hw->eeprom.semaphore_delay * 2000);
a7f5a5fc 164
d7bbcd32 165 /* Restart DSP and set SFI mode */
429d6a3b
DS		 166 ret_val = hw->mac.ops.prot_autoc_write(hw,
167 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
168 false);
d7bbcd32
DS		 169
170 if (ret_val) {
171 hw_dbg(hw, " sfp module setup not complete\n");
a7f5a5fc
DS		 172 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
173 goto setup_sfp_out;
174 }
11afc1b1
PW		 175 }
176
177setup_sfp_out:
178 return ret_val;
be0c27b4
MR		 179
180setup_sfp_err:
181 /* Release the semaphore */
182 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
183 /* Delay obtaining semaphore again to allow FW access,
184 * semaphore_delay is in ms usleep_range needs us.
185 */
186 usleep_range(hw->eeprom.semaphore_delay * 1000,
187 hw->eeprom.semaphore_delay * 2000);
188 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
189 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
11afc1b1
PW		 190}
191
429d6a3b
DS		 192/**
193 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
194 * @hw: pointer to hardware structure
195 * @locked: Return the if we locked for this read.
196 * @reg_val: Value we read from AUTOC
197 *
198 * For this part (82599) we need to wrap read-modify-writes with a possible
199 * FW/SW lock. It is assumed this lock will be freed with the next
200 * prot_autoc_write_82599(). Note, that locked can only be true in cases
201 * where this function doesn't return an error.
202 **/
203static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked,
204 u32 *reg_val)
205{
206 s32 ret_val;
207
208 *locked = false;
209 /* If LESM is on then we need to hold the SW/FW semaphore. */
210 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
211 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
212 IXGBE_GSSR_MAC_CSR_SM);
f8cf7a00 213 if (ret_val)
429d6a3b
DS		 214 return IXGBE_ERR_SWFW_SYNC;
215
216 *locked = true;
217 }
218
219 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
220 return 0;
221}
222
223/**
224 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
225 * @hw: pointer to hardware structure
226 * @reg_val: value to write to AUTOC
227 * @locked: bool to indicate whether the SW/FW lock was already taken by
228 * previous proc_autoc_read_82599.
229 *
230 * This part (82599) may need to hold a the SW/FW lock around all writes to
231 * AUTOC. Likewise after a write we need to do a pipeline reset.
232 **/
233static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
234{
235 s32 ret_val = 0;
236
c97506ab
DS		 237 /* Blocked by MNG FW so bail */
238 if (ixgbe_check_reset_blocked(hw))
239 goto out;
240
429d6a3b
DS		 241 /* We only need to get the lock if:
242 * - We didn't do it already (in the read part of a read-modify-write)
243 * - LESM is enabled.
244 */
245 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
246 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
247 IXGBE_GSSR_MAC_CSR_SM);
f8cf7a00 248 if (ret_val)
429d6a3b 249 return IXGBE_ERR_SWFW_SYNC;
f8cf7a00
DS		 250
251 locked = true;
429d6a3b
DS		 252 }
253
254 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
255 ret_val = ixgbe_reset_pipeline_82599(hw);
256
c97506ab 257out:
429d6a3b
DS		 258 /* Free the SW/FW semaphore as we either grabbed it here or
259 * already had it when this function was called.
260 */
261 if (locked)
262 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
263
264 return ret_val;
265}
266
11afc1b1
PW		 267static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
268{
269 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 270
04f165ef 271 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 272
04f165ef
PW		 273 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
274 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
275 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
6997d4d1 276 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
04f165ef
PW		 277 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
278 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
21ce849b 279 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
11afc1b1 280
04f165ef
PW		 281 return 0;
282}
11afc1b1 283
04f165ef
PW		 284/**
285 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
286 * @hw: pointer to hardware structure
287 *
288 * Initialize any function pointers that were not able to be
289 * set during get_invariants because the PHY/SFP type was
290 * not known. Perform the SFP init if necessary.
291 *
292 **/
7b25cdba 293static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 294{
295 struct ixgbe_mac_info *mac = &hw->mac;
296 struct ixgbe_phy_info *phy = &hw->phy;
297 s32 ret_val = 0;
8f58332b
DS		 298 u32 esdp;
299
300 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
301 /* Store flag indicating I2C bus access control unit. */
302 hw->phy.qsfp_shared_i2c_bus = true;
303
304 /* Initialize access to QSFP+ I2C bus */
305 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
306 esdp |= IXGBE_ESDP_SDP0_DIR;
307 esdp &= ~IXGBE_ESDP_SDP1_DIR;
308 esdp &= ~IXGBE_ESDP_SDP0;
309 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
310 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
311 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
312 IXGBE_WRITE_FLUSH(hw);
313
314 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
315 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
316 }
11afc1b1 317
04f165ef
PW		 318 /* Identify the PHY or SFP module */
319 ret_val = phy->ops.identify(hw);
320
321 /* Setup function pointers based on detected SFP module and speeds */
322 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 323
324 /* If copper media, overwrite with copper function pointers */
325 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
326 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1 327 mac->ops.get_link_capabilities =
a391f1d5 328 &ixgbe_get_copper_link_capabilities_generic;
11afc1b1
PW		 329 }
330
04f165ef 331 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 332 switch (hw->phy.type) {
333 case ixgbe_phy_tn:
334 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
b57e35bd 335 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
11afc1b1 336 phy->ops.get_firmware_version =
04f165ef 337 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 338 break;
339 default:
340 break;
341 }
342
11afc1b1
PW		 343 return ret_val;
344}
345
346/**
347 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
348 * @hw: pointer to hardware structure
349 * @speed: pointer to link speed
3d292265 350 * @autoneg: true when autoneg or autotry is enabled
11afc1b1
PW		 351 *
352 * Determines the link capabilities by reading the AUTOC register.
353 **/
7b25cdba
DS		 354static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
355 ixgbe_link_speed *speed,
3d292265 356 bool *autoneg)
11afc1b1
PW		 357{
358 s32 status = 0;
1eb99d5a 359 u32 autoc = 0;
11afc1b1 360
cb836a97
DS		 361 /* Determine 1G link capabilities off of SFP+ type */
362 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
a49fda3e 363 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
345be204
DS		 364 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
365 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
a49fda3e
JK		 366 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
367 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
cb836a97 368 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3d292265 369 *autoneg = true;
cb836a97
DS		 370 goto out;
371 }
372
1eb99d5a
PW		 373 /*
374 * Determine link capabilities based on the stored value of AUTOC,
375 * which represents EEPROM defaults. If AUTOC value has not been
376 * stored, use the current register value.
377 */
378 if (hw->mac.orig_link_settings_stored)
379 autoc = hw->mac.orig_autoc;
380 else
381 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
382
383 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 384 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
385 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3d292265 386 *autoneg = false;
11afc1b1
PW		 387 break;
388
389 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
390 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3d292265 391 *autoneg = false;
11afc1b1
PW		 392 break;
393
394 case IXGBE_AUTOC_LMS_1G_AN:
395 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3d292265 396 *autoneg = true;
11afc1b1
PW		 397 break;
398
399 case IXGBE_AUTOC_LMS_10G_SERIAL:
400 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3d292265 401 *autoneg = false;
11afc1b1
PW		 402 break;
403
404 case IXGBE_AUTOC_LMS_KX4_KX_KR:
405 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
406 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 407 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 408 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 409 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 410 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 411 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1 412 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
3d292265 413 *autoneg = true;
11afc1b1
PW		 414 break;
415
416 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
417 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 418 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 419 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 420 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 421 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 422 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1 423 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
3d292265 424 *autoneg = true;
11afc1b1
PW		 425 break;
426
427 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
428 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
3d292265 429 *autoneg = false;
11afc1b1
PW		 430 break;
431
432 default:
433 status = IXGBE_ERR_LINK_SETUP;
434 goto out;
435 break;
436 }
437
438 if (hw->phy.multispeed_fiber) {
439 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
61aaf9e8
ET		 440 IXGBE_LINK_SPEED_1GB_FULL;
441
442 /* QSFP must not enable auto-negotiation */
443 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
444 *autoneg = false;
445 else
446 *autoneg = true;
11afc1b1
PW		 447 }
448
449out:
450 return status;
451}
452
11afc1b1
PW		 453/**
454 * ixgbe_get_media_type_82599 - Get media type
455 * @hw: pointer to hardware structure
456 *
457 * Returns the media type (fiber, copper, backplane)
458 **/
7b25cdba 459static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 460{
461 enum ixgbe_media_type media_type;
462
463 /* Detect if there is a copper PHY attached. */
21cc5b4f
ET		 464 switch (hw->phy.type) {
465 case ixgbe_phy_cu_unknown:
466 case ixgbe_phy_tn:
11afc1b1
PW		 467 media_type = ixgbe_media_type_copper;
468 goto out;
21cc5b4f
ET		 469 default:
470 break;
11afc1b1
PW		 471 }
472
473 switch (hw->device_id) {
11afc1b1 474 case IXGBE_DEV_ID_82599_KX4:
dbfec662 475 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 476 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 477 case IXGBE_DEV_ID_82599_KR:
dbffcb21 478 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
1fcf03e6 479 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 480 /* Default device ID is mezzanine card KX/KX4 */
481 media_type = ixgbe_media_type_backplane;
482 break;
483 case IXGBE_DEV_ID_82599_SFP:
dbffcb21 484 case IXGBE_DEV_ID_82599_SFP_FCOE:
38ad1c8e 485 case IXGBE_DEV_ID_82599_SFP_EM:
4c40ef02 486 case IXGBE_DEV_ID_82599_SFP_SF2:
9e791e4a 487 case IXGBE_DEV_ID_82599_SFP_SF_QP:
7d145282 488 case IXGBE_DEV_ID_82599EN_SFP:
11afc1b1
PW		 489 media_type = ixgbe_media_type_fiber;
490 break;
8911184f 491 case IXGBE_DEV_ID_82599_CX4:
6b1be199 492 media_type = ixgbe_media_type_cx4;
8911184f 493 break;
21cc5b4f
ET		 494 case IXGBE_DEV_ID_82599_T3_LOM:
495 media_type = ixgbe_media_type_copper;
496 break;
4f6290cf
DS		 497 case IXGBE_DEV_ID_82599_LS:
498 media_type = ixgbe_media_type_fiber_lco;
499 break;
8f58332b
DS		 500 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
501 media_type = ixgbe_media_type_fiber_qsfp;
502 break;
11afc1b1
PW		 503 default:
504 media_type = ixgbe_media_type_unknown;
505 break;
506 }
507out:
508 return media_type;
509}
510
f4f1040a
JK		 511/**
512 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
513 * @hw: pointer to hardware structure
514 *
515 * Disables link, should be called during D3 power down sequence.
516 *
305f8cec 517 **/
f4f1040a
JK		 518static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
519{
8036d29f 520 u32 autoc2_reg, fwsm;
f68bfdb1 521 u16 ee_ctrl_2 = 0;
f4f1040a 522
f68bfdb1
JK		 523 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
524
8036d29f
JK		 525 /* Check to see if MNG FW could be enabled */
526 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
527
528 if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
529 !hw->wol_enabled &&
f68bfdb1 530 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
f4f1040a
JK		 531 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
532 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
533 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
534 }
535}
536
11afc1b1 537/**
8620a103 538 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 539 * @hw: pointer to hardware structure
8620a103 540 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 541 *
542 * Configures link settings based on values in the ixgbe_hw struct.
543 * Restarts the link. Performs autonegotiation if needed.
544 **/
5d5b7c39 545static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
8620a103 546 bool autoneg_wait_to_complete)
11afc1b1
PW		 547{
548 u32 autoc_reg;
549 u32 links_reg;
550 u32 i;
551 s32 status = 0;
d7bbcd32
DS		 552 bool got_lock = false;
553
554 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
555 status = hw->mac.ops.acquire_swfw_sync(hw,
556 IXGBE_GSSR_MAC_CSR_SM);
557 if (status)
558 goto out;
559
560 got_lock = true;
561 }
11afc1b1
PW		 562
563 /* Restart link */
d7bbcd32
DS		 564 ixgbe_reset_pipeline_82599(hw);
565
566 if (got_lock)
567 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
11afc1b1
PW		 568
569 /* Only poll for autoneg to complete if specified to do so */
8620a103 570 if (autoneg_wait_to_complete) {
d7bbcd32 571 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
11afc1b1
PW		 572 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
573 IXGBE_AUTOC_LMS_KX4_KX_KR ||
574 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
575 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
576 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
577 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
578 links_reg = 0; /* Just in case Autoneg time = 0 */
579 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
580 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
581 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
582 break;
583 msleep(100);
584 }
585 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
586 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
587 hw_dbg(hw, "Autoneg did not complete.\n");
588 }
589 }
590 }
591
11afc1b1
PW		 592 /* Add delay to filter out noises during initial link setup */
593 msleep(50);
594
d7bbcd32 595out:
11afc1b1
PW		 596 return status;
597}
598
8c7bea32
ET		 599/**
600 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
601 * @hw: pointer to hardware structure
602 *
603 * The base drivers may require better control over SFP+ module
604 * PHY states. This includes selectively shutting down the Tx
605 * laser on the PHY, effectively halting physical link.
606 **/
5d5b7c39 607static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 608{
609 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
610
c97506ab
DS		 611 /* Blocked by MNG FW so bail */
612 if (ixgbe_check_reset_blocked(hw))
613 return;
614
61fac744
PW		 615 /* Disable tx laser; allow 100us to go dark per spec */
616 esdp_reg |= IXGBE_ESDP_SDP3;
617 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
618 IXGBE_WRITE_FLUSH(hw);
619 udelay(100);
620}
621
622/**
623 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
624 * @hw: pointer to hardware structure
625 *
626 * The base drivers may require better control over SFP+ module
627 * PHY states. This includes selectively turning on the Tx
628 * laser on the PHY, effectively starting physical link.
629 **/
5d5b7c39 630static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 631{
632 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
633
634 /* Enable tx laser; allow 100ms to light up */
635 esdp_reg &= ~IXGBE_ESDP_SDP3;
636 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
637 IXGBE_WRITE_FLUSH(hw);
638 msleep(100);
639}
640
1097cd17
MC		 641/**
642 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
643 * @hw: pointer to hardware structure
644 *
645 * When the driver changes the link speeds that it can support,
646 * it sets autotry_restart to true to indicate that we need to
647 * initiate a new autotry session with the link partner. To do
648 * so, we set the speed then disable and re-enable the tx laser, to
649 * alert the link partner that it also needs to restart autotry on its
650 * end. This is consistent with true clause 37 autoneg, which also
651 * involves a loss of signal.
652 **/
5d5b7c39 653static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
1097cd17 654{
c97506ab
DS		 655 /* Blocked by MNG FW so bail */
656 if (ixgbe_check_reset_blocked(hw))
657 return;
658
1097cd17 659 if (hw->mac.autotry_restart) {
61fac744
PW		 660 ixgbe_disable_tx_laser_multispeed_fiber(hw);
661 ixgbe_enable_tx_laser_multispeed_fiber(hw);
1097cd17
MC		 662 hw->mac.autotry_restart = false;
663 }
664}
665
11afc1b1 666/**
8620a103 667 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 668 * @hw: pointer to hardware structure
669 * @speed: new link speed
11afc1b1
PW		 670 * @autoneg_wait_to_complete: true when waiting for completion is needed
671 *
672 * Set the link speed in the AUTOC register and restarts link.
673 **/
b32c8dcc 674static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
8620a103 675 ixgbe_link_speed speed,
8620a103 676 bool autoneg_wait_to_complete)
11afc1b1
PW		 677{
678 s32 status = 0;
037c6d0a 679 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
11afc1b1
PW		 680 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
681 u32 speedcnt = 0;
682 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
037c6d0a 683 u32 i = 0;
11afc1b1 684 bool link_up = false;
fd0326f2 685 bool autoneg = false;
11afc1b1
PW		 686
687 /* Mask off requested but non-supported speeds */
037c6d0a 688 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
3d292265 689 &autoneg);
037c6d0a
ET		 690 if (status != 0)
691 return status;
692
693 speed &= link_speed;
11afc1b1
PW		 694
695 /*
696 * Try each speed one by one, highest priority first. We do this in
697 * software because 10gb fiber doesn't support speed autonegotiation.
698 */
699 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
700 speedcnt++;
701 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
702
50ac58ba 703 /* If we already have link at this speed, just jump out */
037c6d0a
ET		 704 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
705 false);
706 if (status != 0)
707 return status;
50ac58ba 708
037c6d0a 709 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
50ac58ba
PWJ		 710 goto out;
711
712 /* Set the module link speed */
61aaf9e8
ET		 713 switch (hw->phy.media_type) {
714 case ixgbe_media_type_fiber:
4e8e1bca
DS		 715 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
716 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
717 IXGBE_WRITE_FLUSH(hw);
61aaf9e8
ET		 718 break;
719 case ixgbe_media_type_fiber_qsfp:
720 /* QSFP module automatically detects MAC link speed */
721 break;
722 default:
723 hw_dbg(hw, "Unexpected media type.\n");
724 break;
4e8e1bca 725 }
11afc1b1 726
50ac58ba
PWJ		 727 /* Allow module to change analog characteristics (1G->10G) */
728 msleep(40);
11afc1b1 729
8620a103 730 status = ixgbe_setup_mac_link_82599(hw,
037c6d0a 731 IXGBE_LINK_SPEED_10GB_FULL,
037c6d0a 732 autoneg_wait_to_complete);
50ac58ba 733 if (status != 0)
c3c74327 734 return status;
50ac58ba
PWJ		 735
736 /* Flap the tx laser if it has not already been done */
0b2679d6
DS		 737 if (hw->mac.ops.flap_tx_laser)
738 hw->mac.ops.flap_tx_laser(hw);
50ac58ba 739
cd7e1f0b
DS		 740 /*
741 * Wait for the controller to acquire link. Per IEEE 802.3ap,
742 * Section 73.10.2, we may have to wait up to 500ms if KR is
743 * attempted. 82599 uses the same timing for 10g SFI.
744 */
50ac58ba
PWJ		 745 for (i = 0; i < 5; i++) {
746 /* Wait for the link partner to also set speed */
747 msleep(100);
748
749 /* If we have link, just jump out */
037c6d0a
ET		 750 status = hw->mac.ops.check_link(hw, &link_speed,
751 &link_up, false);
752 if (status != 0)
753 return status;
754
50ac58ba
PWJ		 755 if (link_up)
756 goto out;
757 }
11afc1b1
PW		 758 }
759
760 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
761 speedcnt++;
762 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
763 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
764
50ac58ba 765 /* If we already have link at this speed, just jump out */
037c6d0a
ET		 766 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
767 false);
768 if (status != 0)
769 return status;
50ac58ba 770
037c6d0a 771 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
50ac58ba
PWJ		 772 goto out;
773
774 /* Set the module link speed */
61aaf9e8 775 switch (hw->phy.media_type) {
61aaf9e8 776 case ixgbe_media_type_fiber:
4e8e1bca
DS		 777 esdp_reg &= ~IXGBE_ESDP_SDP5;
778 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
779 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
780 IXGBE_WRITE_FLUSH(hw);
61aaf9e8
ET		 781 break;
782 case ixgbe_media_type_fiber_qsfp:
783 /* QSFP module automatically detects MAC link speed */
784 break;
785 default:
786 hw_dbg(hw, "Unexpected media type.\n");
787 break;
4e8e1bca 788 }
11afc1b1 789
50ac58ba
PWJ		 790 /* Allow module to change analog characteristics (10G->1G) */
791 msleep(40);
11afc1b1 792
8620a103 793 status = ixgbe_setup_mac_link_82599(hw,
037c6d0a 794 IXGBE_LINK_SPEED_1GB_FULL,
037c6d0a 795 autoneg_wait_to_complete);
50ac58ba 796 if (status != 0)
c3c74327 797 return status;
50ac58ba
PWJ		 798
799 /* Flap the tx laser if it has not already been done */
0b2679d6
DS		 800 if (hw->mac.ops.flap_tx_laser)
801 hw->mac.ops.flap_tx_laser(hw);
50ac58ba
PWJ		 802
803 /* Wait for the link partner to also set speed */
804 msleep(100);
11afc1b1
PW		 805
806 /* If we have link, just jump out */
037c6d0a
ET		 807 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
808 false);
809 if (status != 0)
810 return status;
811
11afc1b1
PW		 812 if (link_up)
813 goto out;
814 }
815
816 /*
817 * We didn't get link. Configure back to the highest speed we tried,
818 * (if there was more than one). We call ourselves back with just the
819 * single highest speed that the user requested.
820 */
821 if (speedcnt > 1)
8620a103
MC		 822 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
823 highest_link_speed,
8620a103 824 autoneg_wait_to_complete);
11afc1b1
PW		 825
826out:
c3c74327
MC		 827 /* Set autoneg_advertised value based on input link speed */
828 hw->phy.autoneg_advertised = 0;
829
830 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
831 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
832
833 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
834 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
835
11afc1b1
PW		 836 return status;
837}
838
cd7e1f0b
DS		 839/**
840 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
841 * @hw: pointer to hardware structure
842 * @speed: new link speed
cd7e1f0b
DS		 843 * @autoneg_wait_to_complete: true when waiting for completion is needed
844 *
845 * Implements the Intel SmartSpeed algorithm.
846 **/
847static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
fd0326f2 848 ixgbe_link_speed speed,
cd7e1f0b
DS		 849 bool autoneg_wait_to_complete)
850{
851 s32 status = 0;
037c6d0a 852 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
cd7e1f0b
DS		 853 s32 i, j;
854 bool link_up = false;
855 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
cd7e1f0b
DS		 856
857 /* Set autoneg_advertised value based on input link speed */
858 hw->phy.autoneg_advertised = 0;
859
860 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
861 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
862
863 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
864 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
865
866 if (speed & IXGBE_LINK_SPEED_100_FULL)
867 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
868
869 /*
870 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
871 * autoneg advertisement if link is unable to be established at the
872 * highest negotiated rate. This can sometimes happen due to integrity
873 * issues with the physical media connection.
874 */
875
876 /* First, try to get link with full advertisement */
877 hw->phy.smart_speed_active = false;
878 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
fd0326f2 879 status = ixgbe_setup_mac_link_82599(hw, speed,
cd7e1f0b 880 autoneg_wait_to_complete);
037c6d0a 881 if (status != 0)
cd7e1f0b
DS		 882 goto out;
883
884 /*
885 * Wait for the controller to acquire link. Per IEEE 802.3ap,
886 * Section 73.10.2, we may have to wait up to 500ms if KR is
887 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
888 * Table 9 in the AN MAS.
889 */
890 for (i = 0; i < 5; i++) {
891 mdelay(100);
892
893 /* If we have link, just jump out */
037c6d0a
ET		 894 status = hw->mac.ops.check_link(hw, &link_speed,
895 &link_up, false);
896 if (status != 0)
897 goto out;
898
cd7e1f0b
DS		 899 if (link_up)
900 goto out;
901 }
902 }
903
904 /*
905 * We didn't get link. If we advertised KR plus one of KX4/KX
906 * (or BX4/BX), then disable KR and try again.
907 */
908 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
909 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
910 goto out;
911
912 /* Turn SmartSpeed on to disable KR support */
913 hw->phy.smart_speed_active = true;
fd0326f2 914 status = ixgbe_setup_mac_link_82599(hw, speed,
cd7e1f0b 915 autoneg_wait_to_complete);
037c6d0a 916 if (status != 0)
cd7e1f0b
DS		 917 goto out;
918
919 /*
920 * Wait for the controller to acquire link. 600ms will allow for
921 * the AN link_fail_inhibit_timer as well for multiple cycles of
922 * parallel detect, both 10g and 1g. This allows for the maximum
923 * connect attempts as defined in the AN MAS table 73-7.
924 */
925 for (i = 0; i < 6; i++) {
926 mdelay(100);
927
928 /* If we have link, just jump out */
037c6d0a
ET		 929 status = hw->mac.ops.check_link(hw, &link_speed,
930 &link_up, false);
931 if (status != 0)
932 goto out;
933
cd7e1f0b
DS		 934 if (link_up)
935 goto out;
936 }
937
938 /* We didn't get link. Turn SmartSpeed back off. */
939 hw->phy.smart_speed_active = false;
fd0326f2 940 status = ixgbe_setup_mac_link_82599(hw, speed,
cd7e1f0b
DS		 941 autoneg_wait_to_complete);
942
943out:
c4ee6a53 944 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
305f8cec 945 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n");
cd7e1f0b
DS		 946 return status;
947}
948
11afc1b1 949/**
8620a103 950 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 951 * @hw: pointer to hardware structure
952 * @speed: new link speed
11afc1b1
PW		 953 * @autoneg_wait_to_complete: true when waiting for completion is needed
954 *
955 * Set the link speed in the AUTOC register and restarts link.
956 **/
5d5b7c39 957static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
fd0326f2
JH		 958 ixgbe_link_speed speed,
959 bool autoneg_wait_to_complete)
11afc1b1 960{
ee98b577 961 bool autoneg = false;
11afc1b1 962 s32 status = 0;
ee98b577 963 u32 pma_pmd_1g, link_mode, links_reg, i;
11afc1b1 964 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
11afc1b1 965 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
11afc1b1 966 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
ee98b577
JK		 967
968 /* holds the value of AUTOC register at this current point in time */
969 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
970 /* holds the cached value of AUTOC register */
971 u32 orig_autoc = 0;
972 /* temporary variable used for comparison purposes */
973 u32 autoc = current_autoc;
11afc1b1
PW		 974
975 /* Check to see if speed passed in is supported. */
9cdcf098
DS		 976 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
977 &autoneg);
0b0c2b31
ET		 978 if (status != 0)
979 goto out;
980
11afc1b1
PW		 981 speed &= link_capabilities;
982
50ac58ba
PWJ		 983 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
984 status = IXGBE_ERR_LINK_SETUP;
985 goto out;
986 }
987
1eb99d5a
PW		 988 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
989 if (hw->mac.orig_link_settings_stored)
ee98b577 990 orig_autoc = hw->mac.orig_autoc;
1eb99d5a 991 else
ee98b577 992 orig_autoc = autoc;
5e82f2f0 993
5e82f2f0
ET		 994 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
995 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1eb99d5a 996
50ac58ba
PWJ		 997 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
998 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
999 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 1000 /* Set KX4/KX/KR support according to speed requested */
1001 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
55461ddb 1002 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1eb99d5a 1003 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 1004 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 1005 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
1006 (hw->phy.smart_speed_active == false))
11afc1b1 1007 autoc |= IXGBE_AUTOC_KR_SUPP;
55461ddb 1008 }
11afc1b1
PW		 1009 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1010 autoc |= IXGBE_AUTOC_KX_SUPP;
1011 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
1012 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1013 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
1014 /* Switch from 1G SFI to 10G SFI if requested */
1015 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
1016 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
1017 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1018 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1019 }
1020 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1021 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1022 /* Switch from 10G SFI to 1G SFI if requested */
1023 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1024 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1025 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1026 if (autoneg)
1027 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1028 else
1029 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1030 }
1031 }
1032
ee98b577 1033 if (autoc != current_autoc) {
11afc1b1 1034 /* Restart link */
429d6a3b 1035 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
f8cf7a00 1036 if (status)
429d6a3b 1037 goto out;
11afc1b1
PW		 1038
1039 /* Only poll for autoneg to complete if specified to do so */
1040 if (autoneg_wait_to_complete) {
1041 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1042 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1043 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1044 links_reg = 0; /*Just in case Autoneg time=0*/
1045 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1046 links_reg =
1047 IXGBE_READ_REG(hw, IXGBE_LINKS);
1048 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1049 break;
1050 msleep(100);
1051 }
1052 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1053 status =
1054 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
305f8cec 1055 hw_dbg(hw, "Autoneg did not complete.\n");
11afc1b1
PW		 1056 }
1057 }
1058 }
1059
11afc1b1
PW		 1060 /* Add delay to filter out noises during initial link setup */
1061 msleep(50);
1062 }
1063
50ac58ba 1064out:
11afc1b1
PW		 1065 return status;
1066}
1067
1068/**
8620a103 1069 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 1070 * @hw: pointer to hardware structure
1071 * @speed: new link speed
11afc1b1
PW		 1072 * @autoneg_wait_to_complete: true if waiting is needed to complete
1073 *
1074 * Restarts link on PHY and MAC based on settings passed in.
1075 **/
8620a103
MC		 1076static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1077 ixgbe_link_speed speed,
8620a103 1078 bool autoneg_wait_to_complete)
11afc1b1
PW		 1079{
1080 s32 status;
1081
1082 /* Setup the PHY according to input speed */
99b76642 1083 status = hw->phy.ops.setup_link_speed(hw, speed,
11afc1b1
PW		 1084 autoneg_wait_to_complete);
1085 /* Set up MAC */
8620a103 1086 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 1087
1088 return status;
1089}
1090
1091/**
1092 * ixgbe_reset_hw_82599 - Perform hardware reset
1093 * @hw: pointer to hardware structure
1094 *
1095 * Resets the hardware by resetting the transmit and receive units, masks
1096 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1097 * reset.
1098 **/
7b25cdba 1099static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1 1100{
8132b54e
AD		 1101 ixgbe_link_speed link_speed;
1102 s32 status;
429d6a3b 1103 u32 ctrl, i, autoc, autoc2;
0b2679d6 1104 u32 curr_lms;
8132b54e 1105 bool link_up = false;
11afc1b1
PW		 1106
1107 /* Call adapter stop to disable tx/rx and clear interrupts */
ff9d1a5a
ET		 1108 status = hw->mac.ops.stop_adapter(hw);
1109 if (status != 0)
1110 goto reset_hw_out;
1111
1112 /* flush pending Tx transactions */
1113 ixgbe_clear_tx_pending(hw);
11afc1b1 1114
553b4497 1115 /* PHY ops must be identified and initialized prior to reset */
04f165ef 1116
037c6d0a 1117 /* Identify PHY and related function pointers */
553b4497 1118 status = hw->phy.ops.init(hw);
04f165ef 1119
553b4497
PW		 1120 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1121 goto reset_hw_out;
04f165ef 1122
553b4497
PW		 1123 /* Setup SFP module if there is one present. */
1124 if (hw->phy.sfp_setup_needed) {
1125 status = hw->mac.ops.setup_sfp(hw);
1126 hw->phy.sfp_setup_needed = false;
04f165ef 1127 }
11afc1b1 1128
037c6d0a
ET		 1129 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1130 goto reset_hw_out;
1131
553b4497
PW		 1132 /* Reset PHY */
1133 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1134 hw->phy.ops.reset(hw);
1135
5e82f2f0 1136 /* remember AUTOC from before we reset */
429d6a3b 1137 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
0b2679d6 1138
a4297dc2 1139mac_reset_top:
11afc1b1 1140 /*
8132b54e
AD		 1141 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1142 * If link reset is used when link is up, it might reset the PHY when
1143 * mng is using it. If link is down or the flag to force full link
1144 * reset is set, then perform link reset.
11afc1b1 1145 */
8132b54e
AD		 1146 ctrl = IXGBE_CTRL_LNK_RST;
1147 if (!hw->force_full_reset) {
1148 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1149 if (link_up)
1150 ctrl = IXGBE_CTRL_RST;
1151 }
1152
1153 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1154 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
11afc1b1
PW		 1155 IXGBE_WRITE_FLUSH(hw);
1156
1157 /* Poll for reset bit to self-clear indicating reset is complete */
1158 for (i = 0; i < 10; i++) {
1159 udelay(1);
1160 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
8132b54e 1161 if (!(ctrl & IXGBE_CTRL_RST_MASK))
11afc1b1
PW		 1162 break;
1163 }
8132b54e
AD		 1164
1165 if (ctrl & IXGBE_CTRL_RST_MASK) {
11afc1b1
PW		 1166 status = IXGBE_ERR_RESET_FAILED;
1167 hw_dbg(hw, "Reset polling failed to complete.\n");
1168 }
11afc1b1 1169
8132b54e
AD		 1170 msleep(50);
1171
a4297dc2
ET		 1172 /*
1173 * Double resets are required for recovery from certain error
1174 * conditions. Between resets, it is necessary to stall to allow time
8132b54e 1175 * for any pending HW events to complete.
a4297dc2
ET		 1176 */
1177 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1178 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 1179 goto mac_reset_top;
1180 }
1181
11afc1b1
PW		 1182 /*
1183 * Store the original AUTOC/AUTOC2 values if they have not been
1184 * stored off yet. Otherwise restore the stored original
1185 * values since the reset operation sets back to defaults.
1186 */
429d6a3b 1187 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
11afc1b1 1188 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
46d5cedd
ET		 1189
1190 /* Enable link if disabled in NVM */
1191 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1192 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1193 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1194 IXGBE_WRITE_FLUSH(hw);
1195 }
1196
11afc1b1 1197 if (hw->mac.orig_link_settings_stored == false) {
429d6a3b 1198 hw->mac.orig_autoc = autoc;
11afc1b1
PW		 1199 hw->mac.orig_autoc2 = autoc2;
1200 hw->mac.orig_link_settings_stored = true;
4df10466 1201 } else {
0b2679d6
DS		 1202
1203 /* If MNG FW is running on a multi-speed device that
1204 * doesn't autoneg with out driver support we need to
1205 * leave LMS in the state it was before we MAC reset.
b8f83638
DS		 1206 * Likewise if we support WoL we don't want change the
1207 * LMS state either.
0b2679d6 1208 */
b8f83638 1209 if ((hw->phy.multispeed_fiber && hw->mng_fw_enabled) ||
6b92b0ba 1210 hw->wol_enabled)
0b2679d6
DS		 1211 hw->mac.orig_autoc =
1212 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1213 curr_lms;
1214
429d6a3b
DS		 1215 if (autoc != hw->mac.orig_autoc) {
1216 status = hw->mac.ops.prot_autoc_write(hw,
1217 hw->mac.orig_autoc,
1218 false);
f8cf7a00 1219 if (status)
429d6a3b 1220 goto reset_hw_out;
d7bbcd32 1221 }
11afc1b1
PW		 1222
1223 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1224 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1225 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1226 autoc2 |= (hw->mac.orig_autoc2 &
1227 IXGBE_AUTOC2_UPPER_MASK);
1228 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1229 }
1230 }
1231
278675d8
ET		 1232 /* Store the permanent mac address */
1233 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1234
aca6bee7
WJP		 1235 /*
1236 * Store MAC address from RAR0, clear receive address registers, and
1237 * clear the multicast table. Also reset num_rar_entries to 128,
1238 * since we modify this value when programming the SAN MAC address.
1239 */
1240 hw->mac.num_rar_entries = 128;
1241 hw->mac.ops.init_rx_addrs(hw);
1242
0365e6e4
PW		 1243 /* Store the permanent SAN mac address */
1244 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1245
aca6bee7 1246 /* Add the SAN MAC address to the RAR only if it's a valid address */
f8ebc683 1247 if (is_valid_ether_addr(hw->mac.san_addr)) {
aca6bee7
WJP		 1248 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1249 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1250
7fa7c9dc
AD		 1251 /* Save the SAN MAC RAR index */
1252 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1253
aca6bee7
WJP		 1254 /* Reserve the last RAR for the SAN MAC address */
1255 hw->mac.num_rar_entries--;
1256 }
1257
383ff34b
YZ		 1258 /* Store the alternative WWNN/WWPN prefix */
1259 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1260 &hw->mac.wwpn_prefix);
1261
04f165ef 1262reset_hw_out:
11afc1b1
PW		 1263 return status;
1264}
1265
ffff4772
PWJ		 1266/**
1267 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1268 * @hw: pointer to hardware structure
1269 **/
1270s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1271{
1272 int i;
1273 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1274 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1275
1276 /*
1277 * Before starting reinitialization process,
1278 * FDIRCMD.CMD must be zero.
1279 */
1280 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1281 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1282 IXGBE_FDIRCMD_CMD_MASK))
1283 break;
1284 udelay(10);
1285 }
1286 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
905e4a41 1287 hw_dbg(hw, "Flow Director previous command isn't complete, "
d6dbee86 1288 "aborting table re-initialization.\n");
ffff4772
PWJ		 1289 return IXGBE_ERR_FDIR_REINIT_FAILED;
1290 }
1291
1292 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1293 IXGBE_WRITE_FLUSH(hw);
1294 /*
1295 * 82599 adapters flow director init flow cannot be restarted,
1296 * Workaround 82599 silicon errata by performing the following steps
1297 * before re-writing the FDIRCTRL control register with the same value.
1298 * - write 1 to bit 8 of FDIRCMD register &
1299 * - write 0 to bit 8 of FDIRCMD register
1300 */
1301 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1302 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1303 IXGBE_FDIRCMD_CLEARHT));
1304 IXGBE_WRITE_FLUSH(hw);
1305 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1306 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1307 ~IXGBE_FDIRCMD_CLEARHT));
1308 IXGBE_WRITE_FLUSH(hw);
1309 /*
1310 * Clear FDIR Hash register to clear any leftover hashes
1311 * waiting to be programmed.
1312 */
1313 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1314 IXGBE_WRITE_FLUSH(hw);
1315
1316 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1317 IXGBE_WRITE_FLUSH(hw);
1318
1319 /* Poll init-done after we write FDIRCTRL register */
1320 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1321 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1322 IXGBE_FDIRCTRL_INIT_DONE)
1323 break;
4a97df0b 1324 usleep_range(1000, 2000);
ffff4772
PWJ		 1325 }
1326 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1327 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1328 return IXGBE_ERR_FDIR_REINIT_FAILED;
1329 }
1330
1331 /* Clear FDIR statistics registers (read to clear) */
1332 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1333 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1334 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1335 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1336 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1337
1338 return 0;
1339}
1340
ffff4772 1341/**
c04f6ca8 1342 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
ffff4772 1343 * @hw: pointer to hardware structure
c04f6ca8 1344 * @fdirctrl: value to write to flow director control register
ffff4772 1345 **/
c04f6ca8 1346static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
ffff4772 1347{
ffff4772
PWJ		 1348 int i;
1349
ffff4772 1350 /* Prime the keys for hashing */
905e4a41
AD		 1351 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1352 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
ffff4772
PWJ		 1353
1354 /*
1355 * Poll init-done after we write the register. Estimated times:
1356 * 10G: PBALLOC = 11b, timing is 60us
1357 * 1G: PBALLOC = 11b, timing is 600us
1358 * 100M: PBALLOC = 11b, timing is 6ms
1359 *
1360 * Multiple these timings by 4 if under full Rx load
1361 *
1362 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1363 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1364 * this might not finish in our poll time, but we can live with that
1365 * for now.
1366 */
ffff4772
PWJ		 1367 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1368 IXGBE_WRITE_FLUSH(hw);
1369 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1370 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1371 IXGBE_FDIRCTRL_INIT_DONE)
1372 break;
032b4325 1373 usleep_range(1000, 2000);
ffff4772 1374 }
ffff4772 1375
c04f6ca8
AD		 1376 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1377 hw_dbg(hw, "Flow Director poll time exceeded!\n");
ffff4772
PWJ		 1378}
1379
ffff4772 1380/**
c04f6ca8
AD		 1381 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1382 * @hw: pointer to hardware structure
1383 * @fdirctrl: value to write to flow director control register, initially
1384 * contains just the value of the Rx packet buffer allocation
ffff4772 1385 **/
c04f6ca8 1386s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
ffff4772 1387{
c04f6ca8
AD		 1388 /*
1389 * Continue setup of fdirctrl register bits:
1390 * Move the flexible bytes to use the ethertype - shift 6 words
1391 * Set the maximum length per hash bucket to 0xA filters
1392 * Send interrupt when 64 filters are left
1393 */
1394 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1395 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1396 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
ffff4772 1397
c04f6ca8
AD		 1398 /* write hashes and fdirctrl register, poll for completion */
1399 ixgbe_fdir_enable_82599(hw, fdirctrl);
ffff4772 1400
c04f6ca8
AD		 1401 return 0;
1402}
ffff4772 1403
c04f6ca8
AD		 1404/**
1405 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1406 * @hw: pointer to hardware structure
1407 * @fdirctrl: value to write to flow director control register, initially
1408 * contains just the value of the Rx packet buffer allocation
1409 **/
1410s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1411{
ffff4772 1412 /*
c04f6ca8
AD		 1413 * Continue setup of fdirctrl register bits:
1414 * Turn perfect match filtering on
1415 * Report hash in RSS field of Rx wb descriptor
1416 * Initialize the drop queue
1417 * Move the flexible bytes to use the ethertype - shift 6 words
1418 * Set the maximum length per hash bucket to 0xA filters
1419 * Send interrupt when 64 (0x4 * 16) filters are left
ffff4772 1420 */
c04f6ca8
AD		 1421 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1422 IXGBE_FDIRCTRL_REPORT_STATUS |
1423 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1424 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1425 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1426 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
ffff4772 1427
c04f6ca8
AD		 1428 /* write hashes and fdirctrl register, poll for completion */
1429 ixgbe_fdir_enable_82599(hw, fdirctrl);
905e4a41 1430
c04f6ca8 1431 return 0;
ffff4772
PWJ		 1432}
1433
69830529
AD		 1434/*
1435 * These defines allow us to quickly generate all of the necessary instructions
1436 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1437 * for values 0 through 15
1438 */
1439#define IXGBE_ATR_COMMON_HASH_KEY \
1440 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1441#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1442do { \
1443 u32 n = (_n); \
1444 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1445 common_hash ^= lo_hash_dword >> n; \
1446 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1447 bucket_hash ^= lo_hash_dword >> n; \
1448 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1449 sig_hash ^= lo_hash_dword << (16 - n); \
1450 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1451 common_hash ^= hi_hash_dword >> n; \
1452 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1453 bucket_hash ^= hi_hash_dword >> n; \
1454 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1455 sig_hash ^= hi_hash_dword << (16 - n); \
1456} while (0);
1457
1458/**
1459 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1460 * @stream: input bitstream to compute the hash on
1461 *
1462 * This function is almost identical to the function above but contains
1463 * several optomizations such as unwinding all of the loops, letting the
1464 * compiler work out all of the conditional ifs since the keys are static
1465 * defines, and computing two keys at once since the hashed dword stream
1466 * will be the same for both keys.
1467 **/
1468static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1469 union ixgbe_atr_hash_dword common)
1470{
1471 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1472 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1473
1474 /* record the flow_vm_vlan bits as they are a key part to the hash */
1475 flow_vm_vlan = ntohl(input.dword);
1476
1477 /* generate common hash dword */
1478 hi_hash_dword = ntohl(common.dword);
1479
1480 /* low dword is word swapped version of common */
1481 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1482
1483 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1484 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1485
1486 /* Process bits 0 and 16 */
1487 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1488
1489 /*
1490 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1491 * delay this because bit 0 of the stream should not be processed
1492 * so we do not add the vlan until after bit 0 was processed
1493 */
1494 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1495
1496 /* Process remaining 30 bit of the key */
1497 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1498 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1499 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1500 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1501 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1502 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1503 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1504 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1505 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1506 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1507 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1508 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1509 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1510 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1511 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1512
1513 /* combine common_hash result with signature and bucket hashes */
1514 bucket_hash ^= common_hash;
1515 bucket_hash &= IXGBE_ATR_HASH_MASK;
1516
1517 sig_hash ^= common_hash << 16;
1518 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1519
1520 /* return completed signature hash */
1521 return sig_hash ^ bucket_hash;
1522}
1523
ffff4772
PWJ		 1524/**
1525 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1526 * @hw: pointer to hardware structure
69830529
AD		 1527 * @input: unique input dword
1528 * @common: compressed common input dword
ffff4772
PWJ		 1529 * @queue: queue index to direct traffic to
1530 **/
1531s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 1532 union ixgbe_atr_hash_dword input,
1533 union ixgbe_atr_hash_dword common,
ffff4772
PWJ		 1534 u8 queue)
1535{
1536 u64 fdirhashcmd;
905e4a41 1537 u32 fdircmd;
ffff4772
PWJ		 1538
1539 /*
905e4a41
AD		 1540 * Get the flow_type in order to program FDIRCMD properly
1541 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
ffff4772 1542 */
69830529 1543 switch (input.formatted.flow_type) {
905e4a41
AD		 1544 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1545 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1546 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1547 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1548 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1549 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
ffff4772
PWJ		 1550 break;
1551 default:
905e4a41 1552 hw_dbg(hw, " Error on flow type input\n");
ffff4772
PWJ		 1553 return IXGBE_ERR_CONFIG;
1554 }
1555
905e4a41
AD		 1556 /* configure FDIRCMD register */
1557 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1558 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
69830529 1559 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
905e4a41
AD		 1560 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1561
1562 /*
1563 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1564 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1565 */
1566 fdirhashcmd = (u64)fdircmd << 32;
69830529 1567 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
ffff4772
PWJ		 1568 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1569
69830529
AD		 1570 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1571
ffff4772
PWJ		 1572 return 0;
1573}
1574
c04f6ca8
AD		 1575#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1576do { \
1577 u32 n = (_n); \
1578 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1579 bucket_hash ^= lo_hash_dword >> n; \
1580 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1581 bucket_hash ^= hi_hash_dword >> n; \
1582} while (0);
1583
1584/**
1585 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1586 * @atr_input: input bitstream to compute the hash on
1587 * @input_mask: mask for the input bitstream
1588 *
1589 * This function serves two main purposes. First it applys the input_mask
1590 * to the atr_input resulting in a cleaned up atr_input data stream.
1591 * Secondly it computes the hash and stores it in the bkt_hash field at
1592 * the end of the input byte stream. This way it will be available for
1593 * future use without needing to recompute the hash.
1594 **/
1595void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1596 union ixgbe_atr_input *input_mask)
1597{
1598
1599 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
65ce9dcd
JK		 1600 u32 bucket_hash = 0, hi_dword = 0;
1601 int i;
c04f6ca8
AD		 1602
1603 /* Apply masks to input data */
65ce9dcd
JK		 1604 for (i = 0; i <= 10; i++)
1605 input->dword_stream[i] &= input_mask->dword_stream[i];
c04f6ca8
AD		 1606
1607 /* record the flow_vm_vlan bits as they are a key part to the hash */
1608 flow_vm_vlan = ntohl(input->dword_stream[0]);
1609
1610 /* generate common hash dword */
65ce9dcd
JK		 1611 for (i = 1; i <= 10; i++)
1612 hi_dword ^= input->dword_stream[i];
1613 hi_hash_dword = ntohl(hi_dword);
c04f6ca8
AD		 1614
1615 /* low dword is word swapped version of common */
1616 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1617
1618 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1619 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1620
1621 /* Process bits 0 and 16 */
1622 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1623
1624 /*
1625 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1626 * delay this because bit 0 of the stream should not be processed
1627 * so we do not add the vlan until after bit 0 was processed
1628 */
1629 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1630
1631 /* Process remaining 30 bit of the key */
65ce9dcd
JK		 1632 for (i = 1; i <= 15; i++)
1633 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
c04f6ca8
AD		 1634
1635 /*
1636 * Limit hash to 13 bits since max bucket count is 8K.
1637 * Store result at the end of the input stream.
1638 */
1639 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1640}
1641
45b9f509
AD		 1642/**
1643 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1644 * @input_mask: mask to be bit swapped
1645 *
1646 * The source and destination port masks for flow director are bit swapped
1647 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1648 * generate a correctly swapped value we need to bit swap the mask and that
1649 * is what is accomplished by this function.
1650 **/
c04f6ca8 1651static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
45b9f509 1652{
c04f6ca8 1653 u32 mask = ntohs(input_mask->formatted.dst_port);
45b9f509 1654 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
c04f6ca8 1655 mask |= ntohs(input_mask->formatted.src_port);
45b9f509
AD		 1656 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1657 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1658 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1659 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1660}
1661
1662/*
1663 * These two macros are meant to address the fact that we have registers
1664 * that are either all or in part big-endian. As a result on big-endian
1665 * systems we will end up byte swapping the value to little-endian before
1666 * it is byte swapped again and written to the hardware in the original
1667 * big-endian format.
1668 */
1669#define IXGBE_STORE_AS_BE32(_value) \
1670 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1671 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1672
1673#define IXGBE_WRITE_REG_BE32(a, reg, value) \
1674 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1675
1676#define IXGBE_STORE_AS_BE16(_value) \
c04f6ca8 1677 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
45b9f509 1678
c04f6ca8
AD		 1679s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1680 union ixgbe_atr_input *input_mask)
ffff4772 1681{
c04f6ca8
AD		 1682 /* mask IPv6 since it is currently not supported */
1683 u32 fdirm = IXGBE_FDIRM_DIPv6;
1684 u32 fdirtcpm;
ffff4772 1685
9a713e7c 1686 /*
45b9f509
AD		 1687 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1688 * are zero, then assume a full mask for that field. Also assume that
1689 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1690 * cannot be masked out in this implementation.
9a713e7c
PW		 1691 *
1692 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1693 * point in time.
1694 */
45b9f509 1695
c04f6ca8
AD		 1696 /* verify bucket hash is cleared on hash generation */
1697 if (input_mask->formatted.bkt_hash)
1698 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1699
1700 /* Program FDIRM and verify partial masks */
1701 switch (input_mask->formatted.vm_pool & 0x7F) {
1702 case 0x0:
1703 fdirm |= IXGBE_FDIRM_POOL;
1704 case 0x7F:
9a713e7c 1705 break;
c04f6ca8
AD		 1706 default:
1707 hw_dbg(hw, " Error on vm pool mask\n");
1708 return IXGBE_ERR_CONFIG;
1709 }
1710
1711 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1712 case 0x0:
1713 fdirm |= IXGBE_FDIRM_L4P;
1714 if (input_mask->formatted.dst_port ||
1715 input_mask->formatted.src_port) {
1716 hw_dbg(hw, " Error on src/dst port mask\n");
1717 return IXGBE_ERR_CONFIG;
1718 }
1719 case IXGBE_ATR_L4TYPE_MASK:
9a713e7c 1720 break;
c04f6ca8
AD		 1721 default:
1722 hw_dbg(hw, " Error on flow type mask\n");
1723 return IXGBE_ERR_CONFIG;
1724 }
1725
1726 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
45b9f509 1727 case 0x0000:
c04f6ca8
AD		 1728 /* mask VLAN ID, fall through to mask VLAN priority */
1729 fdirm |= IXGBE_FDIRM_VLANID;
1730 case 0x0FFF:
1731 /* mask VLAN priority */
1732 fdirm |= IXGBE_FDIRM_VLANP;
1733 break;
1734 case 0xE000:
1735 /* mask VLAN ID only, fall through */
1736 fdirm |= IXGBE_FDIRM_VLANID;
1737 case 0xEFFF:
1738 /* no VLAN fields masked */
9a713e7c 1739 break;
45b9f509
AD		 1740 default:
1741 hw_dbg(hw, " Error on VLAN mask\n");
1742 return IXGBE_ERR_CONFIG;
9a713e7c
PW		 1743 }
1744
c04f6ca8
AD		 1745 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1746 case 0x0000:
1747 /* Mask Flex Bytes, fall through */
1748 fdirm |= IXGBE_FDIRM_FLEX;
1749 case 0xFFFF:
1750 break;
1751 default:
1752 hw_dbg(hw, " Error on flexible byte mask\n");
1753 return IXGBE_ERR_CONFIG;
45b9f509 1754 }
9a713e7c
PW		 1755
1756 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
9a713e7c 1757 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
ffff4772 1758
45b9f509 1759 /* store the TCP/UDP port masks, bit reversed from port layout */
c04f6ca8 1760 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
45b9f509
AD		 1761
1762 /* write both the same so that UDP and TCP use the same mask */
1763 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1764 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1765
1766 /* store source and destination IP masks (big-enian) */
1767 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
c04f6ca8 1768 ~input_mask->formatted.src_ip[0]);
45b9f509 1769 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
c04f6ca8 1770 ~input_mask->formatted.dst_ip[0]);
45b9f509 1771
c04f6ca8
AD		 1772 return 0;
1773}
45b9f509 1774
c04f6ca8
AD		 1775s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1776 union ixgbe_atr_input *input,
1777 u16 soft_id, u8 queue)
1778{
1779 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1780
1781 /* currently IPv6 is not supported, must be programmed with 0 */
1782 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1783 input->formatted.src_ip[0]);
1784 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1785 input->formatted.src_ip[1]);
1786 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1787 input->formatted.src_ip[2]);
1788
1789 /* record the source address (big-endian) */
1790 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1791
1792 /* record the first 32 bits of the destination address (big-endian) */
1793 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
45b9f509
AD		 1794
1795 /* record source and destination port (little-endian)*/
1796 fdirport = ntohs(input->formatted.dst_port);
1797 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1798 fdirport |= ntohs(input->formatted.src_port);
1799 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1800
c04f6ca8
AD		 1801 /* record vlan (little-endian) and flex_bytes(big-endian) */
1802 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1803 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1804 fdirvlan |= ntohs(input->formatted.vlan_id);
1805 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
45b9f509 1806
c04f6ca8
AD		 1807 /* configure FDIRHASH register */
1808 fdirhash = input->formatted.bkt_hash;
1809 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1810 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1811
1812 /*
1813 * flush all previous writes to make certain registers are
1814 * programmed prior to issuing the command
1815 */
1816 IXGBE_WRITE_FLUSH(hw);
45b9f509
AD		 1817
1818 /* configure FDIRCMD register */
1819 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1820 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
c04f6ca8
AD		 1821 if (queue == IXGBE_FDIR_DROP_QUEUE)
1822 fdircmd |= IXGBE_FDIRCMD_DROP;
45b9f509
AD		 1823 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1824 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
c04f6ca8 1825 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
45b9f509 1826
ffff4772
PWJ		 1827 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1828
1829 return 0;
1830}
45b9f509 1831
c04f6ca8
AD		 1832s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1833 union ixgbe_atr_input *input,
1834 u16 soft_id)
1835{
1836 u32 fdirhash;
1837 u32 fdircmd = 0;
1838 u32 retry_count;
1839 s32 err = 0;
1840
1841 /* configure FDIRHASH register */
1842 fdirhash = input->formatted.bkt_hash;
1843 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1844 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1845
1846 /* flush hash to HW */
1847 IXGBE_WRITE_FLUSH(hw);
1848
1849 /* Query if filter is present */
1850 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1851
1852 for (retry_count = 10; retry_count; retry_count--) {
1853 /* allow 10us for query to process */
1854 udelay(10);
1855 /* verify query completed successfully */
1856 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1857 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1858 break;
1859 }
1860
1861 if (!retry_count)
1862 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1863
1864 /* if filter exists in hardware then remove it */
1865 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1866 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1867 IXGBE_WRITE_FLUSH(hw);
1868 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1869 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1870 }
1871
1872 return err;
1873}
1874
11afc1b1
PW		 1875/**
1876 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1877 * @hw: pointer to hardware structure
1878 * @reg: analog register to read
1879 * @val: read value
1880 *
1881 * Performs read operation to Omer analog register specified.
1882 **/
7b25cdba 1883static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 1884{
1885 u32 core_ctl;
1886
1887 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1888 (reg << 8));
1889 IXGBE_WRITE_FLUSH(hw);
1890 udelay(10);
1891 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1892 *val = (u8)core_ctl;
1893
1894 return 0;
1895}
1896
1897/**
1898 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1899 * @hw: pointer to hardware structure
1900 * @reg: atlas register to write
1901 * @val: value to write
1902 *
1903 * Performs write operation to Omer analog register specified.
1904 **/
7b25cdba 1905static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 1906{
1907 u32 core_ctl;
1908
1909 core_ctl = (reg << 8) | val;
1910 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1911 IXGBE_WRITE_FLUSH(hw);
1912 udelay(10);
1913
1914 return 0;
1915}
1916
1917/**
1918 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1919 * @hw: pointer to hardware structure
1920 *
7184b7cf
ET		 1921 * Starts the hardware using the generic start_hw function
1922 * and the generation start_hw function.
1923 * Then performs revision-specific operations, if any.
11afc1b1 1924 **/
7b25cdba 1925static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1 1926{
7184b7cf 1927 s32 ret_val = 0;
11afc1b1 1928
794caeb2 1929 ret_val = ixgbe_start_hw_generic(hw);
7184b7cf
ET		 1930 if (ret_val != 0)
1931 goto out;
11afc1b1 1932
7184b7cf
ET		 1933 ret_val = ixgbe_start_hw_gen2(hw);
1934 if (ret_val != 0)
1935 goto out;
11afc1b1 1936
50ac58ba
PWJ		 1937 /* We need to run link autotry after the driver loads */
1938 hw->mac.autotry_restart = true;
1939
794caeb2
PWJ		 1940 if (ret_val == 0)
1941 ret_val = ixgbe_verify_fw_version_82599(hw);
7184b7cf 1942out:
794caeb2 1943 return ret_val;
11afc1b1
PW		 1944}
1945
1946/**
1947 * ixgbe_identify_phy_82599 - Get physical layer module
1948 * @hw: pointer to hardware structure
1949 *
1950 * Determines the physical layer module found on the current adapter.
21cc5b4f
ET		 1951 * If PHY already detected, maintains current PHY type in hw struct,
1952 * otherwise executes the PHY detection routine.
11afc1b1 1953 **/
d6cd8e0e 1954static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1955{
1956 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
21cc5b4f
ET		 1957
1958 /* Detect PHY if not unknown - returns success if already detected. */
11afc1b1 1959 status = ixgbe_identify_phy_generic(hw);
21cc5b4f
ET		 1960 if (status != 0) {
1961 /* 82599 10GBASE-T requires an external PHY */
1962 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1963 goto out;
1964 else
8f58332b 1965 status = ixgbe_identify_module_generic(hw);
21cc5b4f
ET		 1966 }
1967
1968 /* Set PHY type none if no PHY detected */
1969 if (hw->phy.type == ixgbe_phy_unknown) {
1970 hw->phy.type = ixgbe_phy_none;
1971 status = 0;
1972 }
1973
1974 /* Return error if SFP module has been detected but is not supported */
1975 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1976 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1977
1978out:
11afc1b1
PW		 1979 return status;
1980}
1981
1982/**
1983 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1984 * @hw: pointer to hardware structure
1985 *
1986 * Determines physical layer capabilities of the current configuration.
1987 **/
7b25cdba 1988static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1989{
1990 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 1991 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1992 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1993 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1994 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1995 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1996 u16 ext_ability = 0;
1339b9e9 1997 u8 comp_codes_10g = 0;
cb836a97 1998 u8 comp_codes_1g = 0;
11afc1b1 1999
04193058
PWJ		 2000 hw->phy.ops.identify(hw);
2001
21cc5b4f
ET		 2002 switch (hw->phy.type) {
2003 case ixgbe_phy_tn:
21cc5b4f 2004 case ixgbe_phy_cu_unknown:
6b73e10d 2005 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
21cc5b4f 2006 &ext_ability);
6b73e10d 2007 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2008 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2009 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2010 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2011 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2012 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2013 goto out;
21cc5b4f
ET		 2014 default:
2015 break;
04193058
PWJ		 2016 }
2017
2018 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2019 case IXGBE_AUTOC_LMS_1G_AN:
2020 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2021 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2022 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2023 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2024 goto out;
2025 } else
2026 /* SFI mode so read SFP module */
2027 goto sfp_check;
11afc1b1 2028 break;
04193058
PWJ		 2029 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2030 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2031 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2032 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2033 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2034 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2035 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2036 goto out;
2037 break;
2038 case IXGBE_AUTOC_LMS_10G_SERIAL:
2039 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2040 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2041 goto out;
2042 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2043 goto sfp_check;
2044 break;
2045 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2046 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2047 if (autoc & IXGBE_AUTOC_KX_SUPP)
2048 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2049 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2050 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2051 if (autoc & IXGBE_AUTOC_KR_SUPP)
2052 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2053 goto out;
2054 break;
2055 default:
2056 goto out;
2057 break;
2058 }
11afc1b1 2059
04193058
PWJ		 2060sfp_check:
2061 /* SFP check must be done last since DA modules are sometimes used to
2062 * test KR mode - we need to id KR mode correctly before SFP module.
2063 * Call identify_sfp because the pluggable module may have changed */
2064 hw->phy.ops.identify_sfp(hw);
2065 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2066 goto out;
2067
2068 switch (hw->phy.type) {
ea0a04df
DS		 2069 case ixgbe_phy_sfp_passive_tyco:
2070 case ixgbe_phy_sfp_passive_unknown:
8f58332b 2071 case ixgbe_phy_qsfp_passive_unknown:
04193058
PWJ		 2072 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2073 break;
ea0a04df
DS		 2074 case ixgbe_phy_sfp_ftl_active:
2075 case ixgbe_phy_sfp_active_unknown:
8f58332b 2076 case ixgbe_phy_qsfp_active_unknown:
ea0a04df
DS		 2077 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2078 break;
04193058
PWJ		 2079 case ixgbe_phy_sfp_avago:
2080 case ixgbe_phy_sfp_ftl:
2081 case ixgbe_phy_sfp_intel:
2082 case ixgbe_phy_sfp_unknown:
cb836a97
DS		 2083 hw->phy.ops.read_i2c_eeprom(hw,
2084 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
04193058
PWJ		 2085 hw->phy.ops.read_i2c_eeprom(hw,
2086 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2087 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2088 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2089 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2090 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
cb836a97
DS		 2091 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2092 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
11afc1b1 2093 break;
8f58332b
DS		 2094 case ixgbe_phy_qsfp_intel:
2095 case ixgbe_phy_qsfp_unknown:
2096 hw->phy.ops.read_i2c_eeprom(hw,
2097 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
2098 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2099 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2100 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2101 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2102 break;
11afc1b1 2103 default:
11afc1b1
PW		 2104 break;
2105 }
2106
04193058 2107out:
11afc1b1
PW		 2108 return physical_layer;
2109}
2110
2111/**
2112 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2113 * @hw: pointer to hardware structure
2114 * @regval: register value to write to RXCTRL
2115 *
2116 * Enables the Rx DMA unit for 82599
2117 **/
7b25cdba 2118static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1 2119{
11afc1b1
PW		 2120 /*
2121 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2122 * If traffic is incoming before we enable the Rx unit, it could hang
2123 * the Rx DMA unit. Therefore, make sure the security engine is
2124 * completely disabled prior to enabling the Rx unit.
2125 */
d2f5e7f3 2126 hw->mac.ops.disable_rx_buff(hw);
11afc1b1
PW		 2127
2128 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
d2f5e7f3
AS		 2129
2130 hw->mac.ops.enable_rx_buff(hw);
11afc1b1
PW		 2131
2132 return 0;
2133}
2134
794caeb2
PWJ		 2135/**
2136 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2137 * @hw: pointer to hardware structure
2138 *
2139 * Verifies that installed the firmware version is 0.6 or higher
2140 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2141 *
2142 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2143 * if the FW version is not supported.
2144 **/
2145static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2146{
2147 s32 status = IXGBE_ERR_EEPROM_VERSION;
2148 u16 fw_offset, fw_ptp_cfg_offset;
be0c27b4 2149 u16 offset;
794caeb2
PWJ		 2150 u16 fw_version = 0;
2151
2152 /* firmware check is only necessary for SFI devices */
2153 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2154 status = 0;
2155 goto fw_version_out;
2156 }
2157
2158 /* get the offset to the Firmware Module block */
be0c27b4
MR		 2159 offset = IXGBE_FW_PTR;
2160 if (hw->eeprom.ops.read(hw, offset, &fw_offset))
2161 goto fw_version_err;
794caeb2
PWJ		 2162
2163 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2164 goto fw_version_out;
2165
2166 /* get the offset to the Pass Through Patch Configuration block */
be0c27b4
MR		 2167 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR;
2168 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset))
2169 goto fw_version_err;
794caeb2
PWJ		 2170
2171 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2172 goto fw_version_out;
2173
2174 /* get the firmware version */
be0c27b4
MR		 2175 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4;
2176 if (hw->eeprom.ops.read(hw, offset, &fw_version))
2177 goto fw_version_err;
794caeb2
PWJ		 2178
2179 if (fw_version > 0x5)
2180 status = 0;
2181
2182fw_version_out:
2183 return status;
be0c27b4
MR		 2184
2185fw_version_err:
2186 hw_err(hw, "eeprom read at offset %d failed\n", offset);
2187 return IXGBE_ERR_EEPROM_VERSION;
794caeb2
PWJ		 2188}
2189
0fa6d832
ET		 2190/**
2191 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2192 * @hw: pointer to hardware structure
2193 *
2194 * Returns true if the LESM FW module is present and enabled. Otherwise
2195 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2196 **/
429d6a3b 2197static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
0fa6d832
ET		 2198{
2199 bool lesm_enabled = false;
2200 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2201 s32 status;
2202
2203 /* get the offset to the Firmware Module block */
2204 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2205
2206 if ((status != 0) ||
2207 (fw_offset == 0) || (fw_offset == 0xFFFF))
2208 goto out;
2209
2210 /* get the offset to the LESM Parameters block */
2211 status = hw->eeprom.ops.read(hw, (fw_offset +
2212 IXGBE_FW_LESM_PARAMETERS_PTR),
2213 &fw_lesm_param_offset);
2214
2215 if ((status != 0) ||
2216 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2217 goto out;
2218
2219 /* get the lesm state word */
2220 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2221 IXGBE_FW_LESM_STATE_1),
2222 &fw_lesm_state);
2223
2224 if ((status == 0) &&
2225 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2226 lesm_enabled = true;
2227
2228out:
2229 return lesm_enabled;
2230}
2231
68c7005d
ET		 2232/**
2233 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2234 * fastest available method
2235 *
2236 * @hw: pointer to hardware structure
2237 * @offset: offset of word in EEPROM to read
2238 * @words: number of words
2239 * @data: word(s) read from the EEPROM
2240 *
2241 * Retrieves 16 bit word(s) read from EEPROM
2242 **/
2243static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2244 u16 words, u16 *data)
2245{
2246 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2247 s32 ret_val = IXGBE_ERR_CONFIG;
2248
2249 /*
2250 * If EEPROM is detected and can be addressed using 14 bits,
2251 * use EERD otherwise use bit bang
2252 */
2253 if ((eeprom->type == ixgbe_eeprom_spi) &&
2254 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2255 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2256 data);
2257 else
2258 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2259 words,
2260 data);
2261
2262 return ret_val;
2263}
2264
0665b09f
ET		 2265/**
2266 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2267 * fastest available method
2268 *
2269 * @hw: pointer to hardware structure
2270 * @offset: offset of word in the EEPROM to read
2271 * @data: word read from the EEPROM
2272 *
2273 * Reads a 16 bit word from the EEPROM
2274 **/
2275static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2276 u16 offset, u16 *data)
2277{
2278 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2279 s32 ret_val = IXGBE_ERR_CONFIG;
2280
2281 /*
2282 * If EEPROM is detected and can be addressed using 14 bits,
2283 * use EERD otherwise use bit bang
2284 */
2285 if ((eeprom->type == ixgbe_eeprom_spi) &&
2286 (offset <= IXGBE_EERD_MAX_ADDR))
2287 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2288 else
2289 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2290
2291 return ret_val;
2292}
2293
de52a12c
DS		 2294/**
2295 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2296 *
2297 * @hw: pointer to hardware structure
2298 *
2299 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2300 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2301 * to AUTOC, so this function assumes the semaphore is held.
2302 **/
429d6a3b 2303static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
de52a12c 2304{
46d5cedd
ET		 2305 s32 ret_val;
2306 u32 anlp1_reg = 0;
2307 u32 i, autoc_reg, autoc2_reg;
2308
2309 /* Enable link if disabled in NVM */
2310 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2311 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2312 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2313 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2314 IXGBE_WRITE_FLUSH(hw);
2315 }
de52a12c 2316
429d6a3b 2317 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
de52a12c
DS		 2318 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2319
2320 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
9f4d278f
DS		 2321 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2322 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
de52a12c
DS		 2323
2324 /* Wait for AN to leave state 0 */
2325 for (i = 0; i < 10; i++) {
2326 usleep_range(4000, 8000);
2327 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2328 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2329 break;
2330 }
2331
2332 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2333 hw_dbg(hw, "auto negotiation not completed\n");
2334 ret_val = IXGBE_ERR_RESET_FAILED;
2335 goto reset_pipeline_out;
2336 }
2337
2338 ret_val = 0;
2339
2340reset_pipeline_out:
2341 /* Write AUTOC register with original LMS field and Restart_AN */
2342 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2343 IXGBE_WRITE_FLUSH(hw);
2344
2345 return ret_val;
2346}
2347
8f58332b
DS		 2348/**
2349 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2350 * @hw: pointer to hardware structure
2351 * @byte_offset: byte offset to read
2352 * @data: value read
2353 *
2354 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2355 * a specified device address.
2356 **/
2357static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2358 u8 dev_addr, u8 *data)
2359{
2360 u32 esdp;
2361 s32 status;
2362 s32 timeout = 200;
2363
2364 if (hw->phy.qsfp_shared_i2c_bus == true) {
2365 /* Acquire I2C bus ownership. */
2366 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2367 esdp |= IXGBE_ESDP_SDP0;
2368 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2369 IXGBE_WRITE_FLUSH(hw);
2370
2371 while (timeout) {
2372 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2373 if (esdp & IXGBE_ESDP_SDP1)
2374 break;
2375
2376 usleep_range(5000, 10000);
2377 timeout--;
2378 }
2379
2380 if (!timeout) {
2381 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2382 status = IXGBE_ERR_I2C;
2383 goto release_i2c_access;
2384 }
2385 }
2386
2387 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2388
2389release_i2c_access:
2390 if (hw->phy.qsfp_shared_i2c_bus == true) {
2391 /* Release I2C bus ownership. */
2392 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2393 esdp &= ~IXGBE_ESDP_SDP0;
2394 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2395 IXGBE_WRITE_FLUSH(hw);
2396 }
2397
2398 return status;
2399}
2400
2401/**
2402 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2403 * @hw: pointer to hardware structure
2404 * @byte_offset: byte offset to write
2405 * @data: value to write
2406 *
2407 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2408 * a specified device address.
2409 **/
2410static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2411 u8 dev_addr, u8 data)
2412{
2413 u32 esdp;
2414 s32 status;
2415 s32 timeout = 200;
2416
2417 if (hw->phy.qsfp_shared_i2c_bus == true) {
2418 /* Acquire I2C bus ownership. */
2419 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2420 esdp |= IXGBE_ESDP_SDP0;
2421 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2422 IXGBE_WRITE_FLUSH(hw);
2423
2424 while (timeout) {
2425 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2426 if (esdp & IXGBE_ESDP_SDP1)
2427 break;
2428
2429 usleep_range(5000, 10000);
2430 timeout--;
2431 }
2432
2433 if (!timeout) {
2434 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2435 status = IXGBE_ERR_I2C;
2436 goto release_i2c_access;
2437 }
2438 }
2439
2440 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2441
2442release_i2c_access:
2443 if (hw->phy.qsfp_shared_i2c_bus == true) {
2444 /* Release I2C bus ownership. */
2445 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2446 esdp &= ~IXGBE_ESDP_SDP0;
2447 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2448 IXGBE_WRITE_FLUSH(hw);
2449 }
2450
2451 return status;
2452}
2453
11afc1b1
PW		 2454static struct ixgbe_mac_operations mac_ops_82599 = {
2455 .init_hw = &ixgbe_init_hw_generic,
2456 .reset_hw = &ixgbe_reset_hw_82599,
2457 .start_hw = &ixgbe_start_hw_82599,
2458 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2459 .get_media_type = &ixgbe_get_media_type_82599,
2460 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2461 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
d2f5e7f3
AS		 2462 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2463 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
11afc1b1 2464 .get_mac_addr = &ixgbe_get_mac_addr_generic,
21ce849b 2465 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
b776d104 2466 .get_device_caps = &ixgbe_get_device_caps_generic,
a391f1d5 2467 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
11afc1b1
PW		 2468 .stop_adapter = &ixgbe_stop_adapter_generic,
2469 .get_bus_info = &ixgbe_get_bus_info_generic,
2470 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2471 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2472 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
f4f1040a 2473 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599,
11afc1b1 2474 .setup_link = &ixgbe_setup_mac_link_82599,
80605c65 2475 .set_rxpba = &ixgbe_set_rxpba_generic,
21ce849b 2476 .check_link = &ixgbe_check_mac_link_generic,
11afc1b1
PW		 2477 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2478 .led_on = &ixgbe_led_on_generic,
2479 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2480 .blink_led_start = &ixgbe_blink_led_start_generic,
2481 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2482 .set_rar = &ixgbe_set_rar_generic,
2483 .clear_rar = &ixgbe_clear_rar_generic,
21ce849b 2484 .set_vmdq = &ixgbe_set_vmdq_generic,
7fa7c9dc 2485 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
21ce849b 2486 .clear_vmdq = &ixgbe_clear_vmdq_generic,
11afc1b1 2487 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
11afc1b1
PW		 2488 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2489 .enable_mc = &ixgbe_enable_mc_generic,
2490 .disable_mc = &ixgbe_disable_mc_generic,
21ce849b
MC		 2491 .clear_vfta = &ixgbe_clear_vfta_generic,
2492 .set_vfta = &ixgbe_set_vfta_generic,
2493 .fc_enable = &ixgbe_fc_enable_generic,
9612de92 2494 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
21ce849b 2495 .init_uta_tables = &ixgbe_init_uta_tables_generic,
11afc1b1 2496 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
a985b6c3
GR		 2497 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2498 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
5e655105
DS		 2499 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2500 .release_swfw_sync = &ixgbe_release_swfw_sync,
3ca8bc6d
DS		 2501 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2502 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
0b2679d6 2503 .mng_fw_enabled = &ixgbe_mng_enabled,
429d6a3b
DS		 2504 .prot_autoc_read = &prot_autoc_read_82599,
2505 .prot_autoc_write = &prot_autoc_write_82599,
11afc1b1
PW		 2506};
2507
2508static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
037c6d0a 2509 .init_params = &ixgbe_init_eeprom_params_generic,
0665b09f 2510 .read = &ixgbe_read_eeprom_82599,
68c7005d 2511 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
037c6d0a 2512 .write = &ixgbe_write_eeprom_generic,
68c7005d 2513 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
037c6d0a
ET		 2514 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2515 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2516 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
11afc1b1
PW		 2517};
2518
2519static struct ixgbe_phy_operations phy_ops_82599 = {
037c6d0a 2520 .identify = &ixgbe_identify_phy_82599,
8f58332b 2521 .identify_sfp = &ixgbe_identify_module_generic,
037c6d0a
ET		 2522 .init = &ixgbe_init_phy_ops_82599,
2523 .reset = &ixgbe_reset_phy_generic,
2524 .read_reg = &ixgbe_read_phy_reg_generic,
2525 .write_reg = &ixgbe_write_phy_reg_generic,
2526 .setup_link = &ixgbe_setup_phy_link_generic,
2527 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2528 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2529 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
07ce870b 2530 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
037c6d0a
ET		 2531 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2532 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2533 .check_overtemp = &ixgbe_tn_check_overtemp,
11afc1b1
PW		 2534};
2535
2536struct ixgbe_info ixgbe_82599_info = {
2537 .mac = ixgbe_mac_82599EB,
2538 .get_invariants = &ixgbe_get_invariants_82599,
2539 .mac_ops = &mac_ops_82599,
2540 .eeprom_ops = &eeprom_ops_82599,
2541 .phy_ops = &phy_ops_82599,
a391f1d5 2542 .mbx_ops = &mbx_ops_generic,
11afc1b1 2543};
Linux 6.x block layer and io_uring tree(s)