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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
14438464 | 4 | Copyright(c) 1999 - 2014 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/pci.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/sched.h> | |
32 | ||
9c8eb720 | 33 | #include "ixgbe.h" |
9a799d71 AK |
34 | #include "ixgbe_phy.h" |
35 | ||
36 | #define IXGBE_82598_MAX_TX_QUEUES 32 | |
37 | #define IXGBE_82598_MAX_RX_QUEUES 64 | |
38 | #define IXGBE_82598_RAR_ENTRIES 16 | |
2c5645cf CL |
39 | #define IXGBE_82598_MC_TBL_SIZE 128 |
40 | #define IXGBE_82598_VFT_TBL_SIZE 128 | |
e09ad236 | 41 | #define IXGBE_82598_RX_PB_SIZE 512 |
9a799d71 | 42 | |
8620a103 | 43 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
e7cf745b JK |
44 | ixgbe_link_speed speed, |
45 | bool autoneg_wait_to_complete); | |
c4900be0 | 46 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
e7cf745b | 47 | u8 *eeprom_data); |
9a799d71 | 48 | |
202ff1ec MC |
49 | /** |
50 | * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout | |
51 | * @hw: pointer to the HW structure | |
52 | * | |
53 | * The defaults for 82598 should be in the range of 50us to 50ms, | |
54 | * however the hardware default for these parts is 500us to 1ms which is less | |
55 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
56 | * increase the value to either 10ms to 250ms for capability version 1 config, | |
57 | * or 16ms to 55ms for version 2. | |
58 | **/ | |
7b25cdba | 59 | static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) |
202ff1ec | 60 | { |
202ff1ec MC |
61 | u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); |
62 | u16 pcie_devctl2; | |
63 | ||
14438464 MR |
64 | if (ixgbe_removed(hw->hw_addr)) |
65 | return; | |
66 | ||
202ff1ec MC |
67 | /* only take action if timeout value is defaulted to 0 */ |
68 | if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) | |
69 | goto out; | |
70 | ||
71 | /* | |
72 | * if capababilities version is type 1 we can write the | |
73 | * timeout of 10ms to 250ms through the GCR register | |
74 | */ | |
75 | if (!(gcr & IXGBE_GCR_CAP_VER2)) { | |
76 | gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; | |
77 | goto out; | |
78 | } | |
79 | ||
80 | /* | |
81 | * for version 2 capabilities we need to write the config space | |
82 | * directly in order to set the completion timeout value for | |
83 | * 16ms to 55ms | |
84 | */ | |
14438464 | 85 | pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); |
202ff1ec | 86 | pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; |
ed19231c | 87 | ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); |
202ff1ec MC |
88 | out: |
89 | /* disable completion timeout resend */ | |
90 | gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; | |
91 | IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); | |
92 | } | |
93 | ||
9a799d71 | 94 | static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) |
04f165ef PW |
95 | { |
96 | struct ixgbe_mac_info *mac = &hw->mac; | |
97 | ||
98 | /* Call PHY identify routine to get the phy type */ | |
99 | ixgbe_identify_phy_generic(hw); | |
100 | ||
101 | mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; | |
102 | mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; | |
103 | mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; | |
6997d4d1 | 104 | mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE; |
04f165ef PW |
105 | mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; |
106 | mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; | |
71161302 | 107 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); |
04f165ef PW |
108 | |
109 | return 0; | |
110 | } | |
111 | ||
112 | /** | |
113 | * ixgbe_init_phy_ops_82598 - PHY/SFP specific init | |
114 | * @hw: pointer to hardware structure | |
115 | * | |
116 | * Initialize any function pointers that were not able to be | |
117 | * set during get_invariants because the PHY/SFP type was | |
118 | * not known. Perform the SFP init if necessary. | |
119 | * | |
120 | **/ | |
7b25cdba | 121 | static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) |
9a799d71 | 122 | { |
c44ade9e JB |
123 | struct ixgbe_mac_info *mac = &hw->mac; |
124 | struct ixgbe_phy_info *phy = &hw->phy; | |
e90dd264 | 125 | s32 ret_val; |
c4900be0 | 126 | u16 list_offset, data_offset; |
c44ade9e | 127 | |
04f165ef PW |
128 | /* Identify the PHY */ |
129 | phy->ops.identify(hw); | |
03cfa205 | 130 | |
04f165ef PW |
131 | /* Overwrite the link function pointers if copper PHY */ |
132 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { | |
133 | mac->ops.setup_link = &ixgbe_setup_copper_link_82598; | |
04f165ef | 134 | mac->ops.get_link_capabilities = |
a391f1d5 | 135 | &ixgbe_get_copper_link_capabilities_generic; |
04f165ef | 136 | } |
c44ade9e | 137 | |
04f165ef | 138 | switch (hw->phy.type) { |
0befdb3e | 139 | case ixgbe_phy_tn: |
9dda1736 | 140 | phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; |
0befdb3e JB |
141 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; |
142 | phy->ops.get_firmware_version = | |
e7cf745b | 143 | &ixgbe_get_phy_firmware_version_tnx; |
0befdb3e | 144 | break; |
c4900be0 DS |
145 | case ixgbe_phy_nl: |
146 | phy->ops.reset = &ixgbe_reset_phy_nl; | |
147 | ||
148 | /* Call SFP+ identify routine to get the SFP+ module type */ | |
149 | ret_val = phy->ops.identify_sfp(hw); | |
e90dd264 MR |
150 | if (ret_val) |
151 | return ret_val; | |
152 | if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) | |
153 | return IXGBE_ERR_SFP_NOT_SUPPORTED; | |
c4900be0 DS |
154 | |
155 | /* Check to see if SFP+ module is supported */ | |
156 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, | |
e7cf745b JK |
157 | &list_offset, |
158 | &data_offset); | |
e90dd264 MR |
159 | if (ret_val) |
160 | return IXGBE_ERR_SFP_NOT_SUPPORTED; | |
c4900be0 | 161 | break; |
c44ade9e JB |
162 | default: |
163 | break; | |
164 | } | |
165 | ||
e90dd264 | 166 | return 0; |
9a799d71 AK |
167 | } |
168 | ||
202ff1ec MC |
169 | /** |
170 | * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx | |
171 | * @hw: pointer to hardware structure | |
172 | * | |
173 | * Starts the hardware using the generic start_hw function. | |
3d5c5207 ET |
174 | * Disables relaxed ordering Then set pcie completion timeout |
175 | * | |
202ff1ec | 176 | **/ |
7b25cdba | 177 | static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) |
202ff1ec | 178 | { |
3d5c5207 ET |
179 | u32 regval; |
180 | u32 i; | |
e90dd264 | 181 | s32 ret_val; |
202ff1ec MC |
182 | |
183 | ret_val = ixgbe_start_hw_generic(hw); | |
184 | ||
3d5c5207 ET |
185 | /* Disable relaxed ordering */ |
186 | for (i = 0; ((i < hw->mac.max_tx_queues) && | |
187 | (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { | |
188 | regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); | |
bdda1a61 | 189 | regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; |
3d5c5207 ET |
190 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); |
191 | } | |
192 | ||
193 | for (i = 0; ((i < hw->mac.max_rx_queues) && | |
194 | (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { | |
195 | regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
bdda1a61 AD |
196 | regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | |
197 | IXGBE_DCA_RXCTRL_HEAD_WRO_EN); | |
3d5c5207 ET |
198 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); |
199 | } | |
200 | ||
e90dd264 MR |
201 | if (ret_val) |
202 | return ret_val; | |
203 | ||
202ff1ec | 204 | /* set the completion timeout for interface */ |
e90dd264 | 205 | ixgbe_set_pcie_completion_timeout(hw); |
202ff1ec | 206 | |
e90dd264 | 207 | return 0; |
202ff1ec MC |
208 | } |
209 | ||
9a799d71 | 210 | /** |
c44ade9e | 211 | * ixgbe_get_link_capabilities_82598 - Determines link capabilities |
9a799d71 AK |
212 | * @hw: pointer to hardware structure |
213 | * @speed: pointer to link speed | |
214 | * @autoneg: boolean auto-negotiation value | |
215 | * | |
c44ade9e | 216 | * Determines the link capabilities by reading the AUTOC register. |
9a799d71 | 217 | **/ |
c44ade9e | 218 | static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, |
e7cf745b JK |
219 | ixgbe_link_speed *speed, |
220 | bool *autoneg) | |
9a799d71 | 221 | { |
1eb99d5a | 222 | u32 autoc = 0; |
9a799d71 | 223 | |
3201d313 PWJ |
224 | /* |
225 | * Determine link capabilities based on the stored value of AUTOC, | |
1eb99d5a PW |
226 | * which represents EEPROM defaults. If AUTOC value has not been |
227 | * stored, use the current register value. | |
3201d313 | 228 | */ |
1eb99d5a PW |
229 | if (hw->mac.orig_link_settings_stored) |
230 | autoc = hw->mac.orig_autoc; | |
231 | else | |
232 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
233 | ||
234 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { | |
9a799d71 AK |
235 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
236 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
237 | *autoneg = false; | |
238 | break; | |
239 | ||
240 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: | |
241 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
242 | *autoneg = false; | |
243 | break; | |
244 | ||
245 | case IXGBE_AUTOC_LMS_1G_AN: | |
246 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
247 | *autoneg = true; | |
248 | break; | |
249 | ||
250 | case IXGBE_AUTOC_LMS_KX4_AN: | |
251 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
252 | *speed = IXGBE_LINK_SPEED_UNKNOWN; | |
1eb99d5a | 253 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
9a799d71 | 254 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 255 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
9a799d71 AK |
256 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
257 | *autoneg = true; | |
258 | break; | |
259 | ||
260 | default: | |
e90dd264 | 261 | return IXGBE_ERR_LINK_SETUP; |
9a799d71 AK |
262 | } |
263 | ||
e90dd264 | 264 | return 0; |
9a799d71 AK |
265 | } |
266 | ||
9a799d71 AK |
267 | /** |
268 | * ixgbe_get_media_type_82598 - Determines media type | |
269 | * @hw: pointer to hardware structure | |
270 | * | |
271 | * Returns the media type (fiber, copper, backplane) | |
272 | **/ | |
273 | static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) | |
274 | { | |
037c6d0a ET |
275 | /* Detect if there is a copper PHY attached. */ |
276 | switch (hw->phy.type) { | |
277 | case ixgbe_phy_cu_unknown: | |
278 | case ixgbe_phy_tn: | |
e90dd264 MR |
279 | return ixgbe_media_type_copper; |
280 | ||
037c6d0a ET |
281 | default: |
282 | break; | |
283 | } | |
284 | ||
9a799d71 AK |
285 | /* Media type for I82598 is based on device ID */ |
286 | switch (hw->device_id) { | |
1e336d0f | 287 | case IXGBE_DEV_ID_82598: |
2f21bdd3 | 288 | case IXGBE_DEV_ID_82598_BX: |
037c6d0a | 289 | /* Default device ID is mezzanine card KX/KX4 */ |
e90dd264 MR |
290 | return ixgbe_media_type_backplane; |
291 | ||
9a799d71 AK |
292 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: |
293 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
c4900be0 DS |
294 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: |
295 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
b95f5fcb | 296 | case IXGBE_DEV_ID_82598EB_XF_LR: |
c4900be0 | 297 | case IXGBE_DEV_ID_82598EB_SFP_LOM: |
e90dd264 MR |
298 | return ixgbe_media_type_fiber; |
299 | ||
6b1be199 PWJ |
300 | case IXGBE_DEV_ID_82598EB_CX4: |
301 | case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: | |
e90dd264 MR |
302 | return ixgbe_media_type_cx4; |
303 | ||
0befdb3e | 304 | case IXGBE_DEV_ID_82598AT: |
3845bec0 | 305 | case IXGBE_DEV_ID_82598AT2: |
e90dd264 MR |
306 | return ixgbe_media_type_copper; |
307 | ||
9a799d71 | 308 | default: |
e90dd264 | 309 | return ixgbe_media_type_unknown; |
9a799d71 | 310 | } |
9a799d71 AK |
311 | } |
312 | ||
c44ade9e | 313 | /** |
0ecc061d | 314 | * ixgbe_fc_enable_82598 - Enable flow control |
c44ade9e | 315 | * @hw: pointer to hardware structure |
c44ade9e | 316 | * |
0ecc061d | 317 | * Enable flow control according to the current settings. |
c44ade9e | 318 | **/ |
041441d0 | 319 | static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) |
c44ade9e | 320 | { |
0ecc061d | 321 | u32 fctrl_reg; |
c44ade9e | 322 | u32 rmcs_reg; |
0ecc061d | 323 | u32 reg; |
041441d0 | 324 | u32 fcrtl, fcrth; |
a626e847 | 325 | u32 link_speed = 0; |
041441d0 | 326 | int i; |
a626e847 | 327 | bool link_up; |
c44ade9e | 328 | |
e5776620 | 329 | /* Validate the water mark configuration */ |
e90dd264 MR |
330 | if (!hw->fc.pause_time) |
331 | return IXGBE_ERR_INVALID_LINK_SETTINGS; | |
620fa036 | 332 | |
e5776620 JK |
333 | /* Low water mark of zero causes XOFF floods */ |
334 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
335 | if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && | |
336 | hw->fc.high_water[i]) { | |
337 | if (!hw->fc.low_water[i] || | |
338 | hw->fc.low_water[i] >= hw->fc.high_water[i]) { | |
339 | hw_dbg(hw, "Invalid water mark configuration\n"); | |
e90dd264 | 340 | return IXGBE_ERR_INVALID_LINK_SETTINGS; |
e5776620 JK |
341 | } |
342 | } | |
343 | } | |
344 | ||
a626e847 DS |
345 | /* |
346 | * On 82598 having Rx FC on causes resets while doing 1G | |
347 | * so if it's on turn it off once we know link_speed. For | |
348 | * more details see 82598 Specification update. | |
349 | */ | |
350 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
351 | if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { | |
352 | switch (hw->fc.requested_mode) { | |
353 | case ixgbe_fc_full: | |
354 | hw->fc.requested_mode = ixgbe_fc_tx_pause; | |
355 | break; | |
356 | case ixgbe_fc_rx_pause: | |
357 | hw->fc.requested_mode = ixgbe_fc_none; | |
358 | break; | |
359 | default: | |
360 | /* no change */ | |
361 | break; | |
362 | } | |
363 | } | |
364 | ||
620fa036 | 365 | /* Negotiate the fc mode to use */ |
786e9a5f | 366 | ixgbe_fc_autoneg(hw); |
620fa036 MC |
367 | |
368 | /* Disable any previous flow control settings */ | |
0ecc061d PWJ |
369 | fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
370 | fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); | |
c44ade9e JB |
371 | |
372 | rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
373 | rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); | |
374 | ||
375 | /* | |
0ecc061d | 376 | * The possible values of fc.current_mode are: |
c44ade9e | 377 | * 0: Flow control is completely disabled |
0ecc061d PWJ |
378 | * 1: Rx flow control is enabled (we can receive pause frames, |
379 | * but not send pause frames). | |
620fa036 | 380 | * 2: Tx flow control is enabled (we can send pause frames but |
0ecc061d | 381 | * we do not support receiving pause frames). |
c44ade9e | 382 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
0b0c2b31 | 383 | * other: Invalid. |
c44ade9e | 384 | */ |
0ecc061d | 385 | switch (hw->fc.current_mode) { |
c44ade9e | 386 | case ixgbe_fc_none: |
620fa036 MC |
387 | /* |
388 | * Flow control is disabled by software override or autoneg. | |
389 | * The code below will actually disable it in the HW. | |
390 | */ | |
c44ade9e JB |
391 | break; |
392 | case ixgbe_fc_rx_pause: | |
393 | /* | |
0ecc061d PWJ |
394 | * Rx Flow control is enabled and Tx Flow control is |
395 | * disabled by software override. Since there really | |
396 | * isn't a way to advertise that we are capable of RX | |
397 | * Pause ONLY, we will advertise that we support both | |
398 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
399 | * disable the adapter's ability to send PAUSE frames. | |
c44ade9e | 400 | */ |
0ecc061d | 401 | fctrl_reg |= IXGBE_FCTRL_RFCE; |
c44ade9e JB |
402 | break; |
403 | case ixgbe_fc_tx_pause: | |
404 | /* | |
0ecc061d PWJ |
405 | * Tx Flow control is enabled, and Rx Flow control is |
406 | * disabled by software override. | |
c44ade9e JB |
407 | */ |
408 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | |
409 | break; | |
410 | case ixgbe_fc_full: | |
0ecc061d PWJ |
411 | /* Flow control (both Rx and Tx) is enabled by SW override. */ |
412 | fctrl_reg |= IXGBE_FCTRL_RFCE; | |
c44ade9e JB |
413 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; |
414 | break; | |
415 | default: | |
c44ade9e | 416 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
e90dd264 | 417 | return IXGBE_ERR_CONFIG; |
c44ade9e JB |
418 | } |
419 | ||
620fa036 | 420 | /* Set 802.3x based flow control settings. */ |
2132d381 | 421 | fctrl_reg |= IXGBE_FCTRL_DPF; |
0ecc061d | 422 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); |
c44ade9e JB |
423 | IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); |
424 | ||
041441d0 AD |
425 | /* Set up and enable Rx high/low water mark thresholds, enable XON. */ |
426 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
427 | if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && | |
428 | hw->fc.high_water[i]) { | |
e5776620 | 429 | fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; |
041441d0 AD |
430 | fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; |
431 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); | |
432 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); | |
433 | } else { | |
434 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); | |
435 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); | |
436 | } | |
0ecc061d | 437 | |
c44ade9e JB |
438 | } |
439 | ||
0ecc061d | 440 | /* Configure pause time (2 TCs per register) */ |
041441d0 AD |
441 | reg = hw->fc.pause_time * 0x00010001; |
442 | for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) | |
443 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); | |
0ecc061d | 444 | |
041441d0 AD |
445 | /* Configure flow control refresh threshold value */ |
446 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); | |
c44ade9e | 447 | |
e90dd264 | 448 | return 0; |
0ecc061d PWJ |
449 | } |
450 | ||
9a799d71 | 451 | /** |
8620a103 | 452 | * ixgbe_start_mac_link_82598 - Configures MAC link settings |
9a799d71 AK |
453 | * @hw: pointer to hardware structure |
454 | * | |
455 | * Configures link settings based on values in the ixgbe_hw struct. | |
456 | * Restarts the link. Performs autonegotiation if needed. | |
457 | **/ | |
8620a103 | 458 | static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, |
e7cf745b | 459 | bool autoneg_wait_to_complete) |
9a799d71 AK |
460 | { |
461 | u32 autoc_reg; | |
462 | u32 links_reg; | |
463 | u32 i; | |
464 | s32 status = 0; | |
465 | ||
9a799d71 | 466 | /* Restart link */ |
3201d313 | 467 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
9a799d71 AK |
468 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
469 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); | |
470 | ||
471 | /* Only poll for autoneg to complete if specified to do so */ | |
8620a103 | 472 | if (autoneg_wait_to_complete) { |
3201d313 PWJ |
473 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
474 | IXGBE_AUTOC_LMS_KX4_AN || | |
475 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == | |
476 | IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
9a799d71 AK |
477 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
478 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { | |
479 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
480 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) | |
481 | break; | |
482 | msleep(100); | |
483 | } | |
484 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { | |
485 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; | |
c44ade9e | 486 | hw_dbg(hw, "Autonegotiation did not complete.\n"); |
9a799d71 AK |
487 | } |
488 | } | |
489 | } | |
490 | ||
9a799d71 AK |
491 | /* Add delay to filter out noises during initial link setup */ |
492 | msleep(50); | |
493 | ||
494 | return status; | |
495 | } | |
496 | ||
734e979f MC |
497 | /** |
498 | * ixgbe_validate_link_ready - Function looks for phy link | |
499 | * @hw: pointer to hardware structure | |
500 | * | |
501 | * Function indicates success when phy link is available. If phy is not ready | |
502 | * within 5 seconds of MAC indicating link, the function returns error. | |
503 | **/ | |
504 | static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) | |
505 | { | |
506 | u32 timeout; | |
507 | u16 an_reg; | |
508 | ||
509 | if (hw->device_id != IXGBE_DEV_ID_82598AT2) | |
510 | return 0; | |
511 | ||
512 | for (timeout = 0; | |
513 | timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { | |
514 | hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); | |
515 | ||
516 | if ((an_reg & MDIO_AN_STAT1_COMPLETE) && | |
517 | (an_reg & MDIO_STAT1_LSTATUS)) | |
518 | break; | |
519 | ||
520 | msleep(100); | |
521 | } | |
522 | ||
523 | if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { | |
524 | hw_dbg(hw, "Link was indicated but link is down\n"); | |
525 | return IXGBE_ERR_LINK_SETUP; | |
526 | } | |
527 | ||
528 | return 0; | |
529 | } | |
530 | ||
9a799d71 AK |
531 | /** |
532 | * ixgbe_check_mac_link_82598 - Get link/speed status | |
533 | * @hw: pointer to hardware structure | |
534 | * @speed: pointer to link speed | |
535 | * @link_up: true is link is up, false otherwise | |
cf8280ee | 536 | * @link_up_wait_to_complete: bool used to wait for link up or not |
9a799d71 AK |
537 | * |
538 | * Reads the links register to determine if link is up and the current speed | |
539 | **/ | |
b4617240 | 540 | static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, |
e7cf745b JK |
541 | ixgbe_link_speed *speed, bool *link_up, |
542 | bool link_up_wait_to_complete) | |
9a799d71 AK |
543 | { |
544 | u32 links_reg; | |
cf8280ee | 545 | u32 i; |
c4900be0 DS |
546 | u16 link_reg, adapt_comp_reg; |
547 | ||
548 | /* | |
549 | * SERDES PHY requires us to read link status from register 0xC79F. | |
550 | * Bit 0 set indicates link is up/ready; clear indicates link down. | |
551 | * 0xC00C is read to check that the XAUI lanes are active. Bit 0 | |
552 | * clear indicates active; set indicates inactive. | |
553 | */ | |
554 | if (hw->phy.type == ixgbe_phy_nl) { | |
6b73e10d BH |
555 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); |
556 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); | |
557 | hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, | |
e7cf745b | 558 | &adapt_comp_reg); |
c4900be0 DS |
559 | if (link_up_wait_to_complete) { |
560 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
561 | if ((link_reg & 1) && | |
562 | ((adapt_comp_reg & 1) == 0)) { | |
563 | *link_up = true; | |
564 | break; | |
565 | } else { | |
566 | *link_up = false; | |
567 | } | |
568 | msleep(100); | |
569 | hw->phy.ops.read_reg(hw, 0xC79F, | |
e7cf745b JK |
570 | MDIO_MMD_PMAPMD, |
571 | &link_reg); | |
c4900be0 | 572 | hw->phy.ops.read_reg(hw, 0xC00C, |
e7cf745b JK |
573 | MDIO_MMD_PMAPMD, |
574 | &adapt_comp_reg); | |
c4900be0 DS |
575 | } |
576 | } else { | |
577 | if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) | |
578 | *link_up = true; | |
579 | else | |
580 | *link_up = false; | |
581 | } | |
582 | ||
23677ce3 | 583 | if (!*link_up) |
e90dd264 | 584 | return 0; |
c4900be0 | 585 | } |
9a799d71 AK |
586 | |
587 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
cf8280ee JB |
588 | if (link_up_wait_to_complete) { |
589 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
590 | if (links_reg & IXGBE_LINKS_UP) { | |
591 | *link_up = true; | |
592 | break; | |
593 | } else { | |
594 | *link_up = false; | |
595 | } | |
596 | msleep(100); | |
597 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
598 | } | |
599 | } else { | |
600 | if (links_reg & IXGBE_LINKS_UP) | |
601 | *link_up = true; | |
602 | else | |
603 | *link_up = false; | |
604 | } | |
9a799d71 AK |
605 | |
606 | if (links_reg & IXGBE_LINKS_SPEED) | |
607 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
608 | else | |
609 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
610 | ||
23677ce3 | 611 | if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up && |
734e979f MC |
612 | (ixgbe_validate_link_ready(hw) != 0)) |
613 | *link_up = false; | |
614 | ||
9a799d71 AK |
615 | return 0; |
616 | } | |
617 | ||
618 | /** | |
8620a103 | 619 | * ixgbe_setup_mac_link_82598 - Set MAC link speed |
9a799d71 AK |
620 | * @hw: pointer to hardware structure |
621 | * @speed: new link speed | |
037c6d0a | 622 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
9a799d71 AK |
623 | * |
624 | * Set the link speed in the AUTOC register and restarts link. | |
625 | **/ | |
8620a103 | 626 | static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, |
fd0326f2 JH |
627 | ixgbe_link_speed speed, |
628 | bool autoneg_wait_to_complete) | |
9a799d71 | 629 | { |
fd0326f2 | 630 | bool autoneg = false; |
3201d313 PWJ |
631 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; |
632 | u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
633 | u32 autoc = curr_autoc; | |
634 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; | |
9a799d71 | 635 | |
3201d313 PWJ |
636 | /* Check to see if speed passed in is supported. */ |
637 | ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); | |
638 | speed &= link_capabilities; | |
639 | ||
640 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) | |
e90dd264 | 641 | return IXGBE_ERR_LINK_SETUP; |
3201d313 PWJ |
642 | |
643 | /* Set KX4/KX support according to speed requested */ | |
644 | else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || | |
e7cf745b | 645 | link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { |
3201d313 PWJ |
646 | autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; |
647 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
648 | autoc |= IXGBE_AUTOC_KX4_SUPP; | |
649 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
650 | autoc |= IXGBE_AUTOC_KX_SUPP; | |
651 | if (autoc != curr_autoc) | |
652 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); | |
9a799d71 AK |
653 | } |
654 | ||
e90dd264 MR |
655 | /* Setup and restart the link based on the new values in |
656 | * ixgbe_hw This will write the AUTOC register based on the new | |
657 | * stored values | |
658 | */ | |
659 | return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); | |
9a799d71 AK |
660 | } |
661 | ||
662 | ||
663 | /** | |
8620a103 | 664 | * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field |
9a799d71 AK |
665 | * @hw: pointer to hardware structure |
666 | * @speed: new link speed | |
9a799d71 AK |
667 | * @autoneg_wait_to_complete: true if waiting is needed to complete |
668 | * | |
669 | * Sets the link speed in the AUTOC register in the MAC and restarts link. | |
670 | **/ | |
8620a103 | 671 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
e7cf745b JK |
672 | ixgbe_link_speed speed, |
673 | bool autoneg_wait_to_complete) | |
9a799d71 | 674 | { |
c44ade9e | 675 | s32 status; |
9a799d71 AK |
676 | |
677 | /* Setup the PHY according to input speed */ | |
99b76642 | 678 | status = hw->phy.ops.setup_link_speed(hw, speed, |
e7cf745b | 679 | autoneg_wait_to_complete); |
3957d63d | 680 | /* Set up MAC */ |
8620a103 | 681 | ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); |
9a799d71 AK |
682 | |
683 | return status; | |
684 | } | |
685 | ||
686 | /** | |
687 | * ixgbe_reset_hw_82598 - Performs hardware reset | |
688 | * @hw: pointer to hardware structure | |
689 | * | |
c44ade9e | 690 | * Resets the hardware by resetting the transmit and receive units, masks and |
9a799d71 AK |
691 | * clears all interrupts, performing a PHY reset, and performing a link (MAC) |
692 | * reset. | |
693 | **/ | |
694 | static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) | |
695 | { | |
e90dd264 | 696 | s32 status; |
8ca783ab | 697 | s32 phy_status = 0; |
9a799d71 AK |
698 | u32 ctrl; |
699 | u32 gheccr; | |
700 | u32 i; | |
701 | u32 autoc; | |
702 | u8 analog_val; | |
703 | ||
704 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
ff9d1a5a | 705 | status = hw->mac.ops.stop_adapter(hw); |
e90dd264 MR |
706 | if (status) |
707 | return status; | |
9a799d71 AK |
708 | |
709 | /* | |
c44ade9e JB |
710 | * Power up the Atlas Tx lanes if they are currently powered down. |
711 | * Atlas Tx lanes are powered down for MAC loopback tests, but | |
9a799d71 AK |
712 | * they are not automatically restored on reset. |
713 | */ | |
c44ade9e | 714 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); |
9a799d71 | 715 | if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { |
c44ade9e JB |
716 | /* Enable Tx Atlas so packets can be transmitted again */ |
717 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, | |
e7cf745b | 718 | &analog_val); |
9a799d71 | 719 | analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; |
c44ade9e | 720 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, |
e7cf745b | 721 | analog_val); |
9a799d71 | 722 | |
c44ade9e | 723 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
e7cf745b | 724 | &analog_val); |
9a799d71 | 725 | analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; |
c44ade9e | 726 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
e7cf745b | 727 | analog_val); |
9a799d71 | 728 | |
c44ade9e | 729 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
e7cf745b | 730 | &analog_val); |
9a799d71 | 731 | analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; |
c44ade9e | 732 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
e7cf745b | 733 | analog_val); |
9a799d71 | 734 | |
c44ade9e | 735 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
e7cf745b | 736 | &analog_val); |
9a799d71 | 737 | analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; |
c44ade9e | 738 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
e7cf745b | 739 | analog_val); |
9a799d71 AK |
740 | } |
741 | ||
742 | /* Reset PHY */ | |
04f165ef PW |
743 | if (hw->phy.reset_disable == false) { |
744 | /* PHY ops must be identified and initialized prior to reset */ | |
745 | ||
746 | /* Init PHY and function pointers, perform SFP setup */ | |
8ca783ab DS |
747 | phy_status = hw->phy.ops.init(hw); |
748 | if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
e90dd264 | 749 | return phy_status; |
ff9d1a5a ET |
750 | if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) |
751 | goto mac_reset_top; | |
8ca783ab | 752 | |
c44ade9e | 753 | hw->phy.ops.reset(hw); |
04f165ef | 754 | } |
9a799d71 | 755 | |
a4297dc2 | 756 | mac_reset_top: |
9a799d71 AK |
757 | /* |
758 | * Issue global reset to the MAC. This needs to be a SW reset. | |
759 | * If link reset is used, it might reset the MAC when mng is using it | |
760 | */ | |
8132b54e AD |
761 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; |
762 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
9a799d71 AK |
763 | IXGBE_WRITE_FLUSH(hw); |
764 | ||
765 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
766 | for (i = 0; i < 10; i++) { | |
767 | udelay(1); | |
768 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
769 | if (!(ctrl & IXGBE_CTRL_RST)) | |
770 | break; | |
771 | } | |
772 | if (ctrl & IXGBE_CTRL_RST) { | |
773 | status = IXGBE_ERR_RESET_FAILED; | |
774 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
775 | } | |
776 | ||
8132b54e AD |
777 | msleep(50); |
778 | ||
a4297dc2 ET |
779 | /* |
780 | * Double resets are required for recovery from certain error | |
781 | * conditions. Between resets, it is necessary to stall to allow time | |
8132b54e | 782 | * for any pending HW events to complete. |
a4297dc2 ET |
783 | */ |
784 | if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { | |
785 | hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; | |
a4297dc2 ET |
786 | goto mac_reset_top; |
787 | } | |
788 | ||
9a799d71 AK |
789 | gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); |
790 | gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); | |
791 | IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); | |
792 | ||
793 | /* | |
3201d313 PWJ |
794 | * Store the original AUTOC value if it has not been |
795 | * stored off yet. Otherwise restore the stored original | |
796 | * AUTOC value since the reset operation sets back to deaults. | |
9a799d71 AK |
797 | */ |
798 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
3201d313 PWJ |
799 | if (hw->mac.orig_link_settings_stored == false) { |
800 | hw->mac.orig_autoc = autoc; | |
801 | hw->mac.orig_link_settings_stored = true; | |
802 | } else if (autoc != hw->mac.orig_autoc) { | |
803 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); | |
9a799d71 AK |
804 | } |
805 | ||
278675d8 ET |
806 | /* Store the permanent mac address */ |
807 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); | |
808 | ||
aca6bee7 WJP |
809 | /* |
810 | * Store MAC address from RAR0, clear receive address registers, and | |
811 | * clear the multicast table | |
812 | */ | |
813 | hw->mac.ops.init_rx_addrs(hw); | |
814 | ||
8ca783ab DS |
815 | if (phy_status) |
816 | status = phy_status; | |
817 | ||
9a799d71 AK |
818 | return status; |
819 | } | |
820 | ||
c44ade9e JB |
821 | /** |
822 | * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address | |
823 | * @hw: pointer to hardware struct | |
824 | * @rar: receive address register index to associate with a VMDq index | |
825 | * @vmdq: VMDq set index | |
826 | **/ | |
e855aac8 | 827 | static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
c44ade9e JB |
828 | { |
829 | u32 rar_high; | |
c700f4e6 ET |
830 | u32 rar_entries = hw->mac.num_rar_entries; |
831 | ||
832 | /* Make sure we are using a valid rar index range */ | |
833 | if (rar >= rar_entries) { | |
834 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); | |
835 | return IXGBE_ERR_INVALID_ARGUMENT; | |
836 | } | |
c44ade9e JB |
837 | |
838 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
839 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
840 | rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); | |
841 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
842 | return 0; | |
843 | } | |
844 | ||
845 | /** | |
846 | * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address | |
847 | * @hw: pointer to hardware struct | |
848 | * @rar: receive address register index to associate with a VMDq index | |
849 | * @vmdq: VMDq clear index (not used in 82598, but elsewhere) | |
850 | **/ | |
851 | static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) | |
852 | { | |
853 | u32 rar_high; | |
854 | u32 rar_entries = hw->mac.num_rar_entries; | |
855 | ||
c700f4e6 ET |
856 | |
857 | /* Make sure we are using a valid rar index range */ | |
858 | if (rar >= rar_entries) { | |
c44ade9e | 859 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); |
c700f4e6 ET |
860 | return IXGBE_ERR_INVALID_ARGUMENT; |
861 | } | |
862 | ||
863 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
864 | if (rar_high & IXGBE_RAH_VIND_MASK) { | |
865 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
866 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
c44ade9e JB |
867 | } |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
872 | /** | |
873 | * ixgbe_set_vfta_82598 - Set VLAN filter table | |
874 | * @hw: pointer to hardware structure | |
875 | * @vlan: VLAN id to write to VLAN filter | |
876 | * @vind: VMDq output index that maps queue to VLAN id in VFTA | |
877 | * @vlan_on: boolean flag to turn on/off VLAN in VFTA | |
878 | * | |
879 | * Turn on/off specified VLAN in the VLAN filter table. | |
880 | **/ | |
e855aac8 HE |
881 | static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
882 | bool vlan_on) | |
c44ade9e JB |
883 | { |
884 | u32 regindex; | |
885 | u32 bitindex; | |
886 | u32 bits; | |
887 | u32 vftabyte; | |
888 | ||
889 | if (vlan > 4095) | |
890 | return IXGBE_ERR_PARAM; | |
891 | ||
892 | /* Determine 32-bit word position in array */ | |
893 | regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ | |
894 | ||
895 | /* Determine the location of the (VMD) queue index */ | |
896 | vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ | |
897 | bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ | |
898 | ||
899 | /* Set the nibble for VMD queue index */ | |
900 | bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); | |
901 | bits &= (~(0x0F << bitindex)); | |
902 | bits |= (vind << bitindex); | |
903 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); | |
904 | ||
905 | /* Determine the location of the bit for this VLAN id */ | |
906 | bitindex = vlan & 0x1F; /* lower five bits */ | |
907 | ||
908 | bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); | |
909 | if (vlan_on) | |
910 | /* Turn on this VLAN id */ | |
911 | bits |= (1 << bitindex); | |
912 | else | |
913 | /* Turn off this VLAN id */ | |
914 | bits &= ~(1 << bitindex); | |
915 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
920 | /** | |
921 | * ixgbe_clear_vfta_82598 - Clear VLAN filter table | |
922 | * @hw: pointer to hardware structure | |
923 | * | |
924 | * Clears the VLAN filer table, and the VMDq index associated with the filter | |
925 | **/ | |
926 | static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) | |
927 | { | |
928 | u32 offset; | |
929 | u32 vlanbyte; | |
930 | ||
931 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
932 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); | |
933 | ||
934 | for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) | |
935 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
936 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), | |
e7cf745b | 937 | 0); |
c44ade9e JB |
938 | |
939 | return 0; | |
940 | } | |
941 | ||
c44ade9e JB |
942 | /** |
943 | * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register | |
944 | * @hw: pointer to hardware structure | |
945 | * @reg: analog register to read | |
946 | * @val: read value | |
947 | * | |
948 | * Performs read operation to Atlas analog register specified. | |
949 | **/ | |
e855aac8 | 950 | static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) |
c44ade9e JB |
951 | { |
952 | u32 atlas_ctl; | |
953 | ||
954 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, | |
e7cf745b | 955 | IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); |
c44ade9e JB |
956 | IXGBE_WRITE_FLUSH(hw); |
957 | udelay(10); | |
958 | atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | |
959 | *val = (u8)atlas_ctl; | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
964 | /** | |
965 | * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register | |
966 | * @hw: pointer to hardware structure | |
967 | * @reg: atlas register to write | |
968 | * @val: value to write | |
969 | * | |
970 | * Performs write operation to Atlas analog register specified. | |
971 | **/ | |
e855aac8 | 972 | static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) |
c44ade9e JB |
973 | { |
974 | u32 atlas_ctl; | |
975 | ||
976 | atlas_ctl = (reg << 8) | val; | |
977 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); | |
978 | IXGBE_WRITE_FLUSH(hw); | |
979 | udelay(10); | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
c4900be0 | 984 | /** |
07ce870b | 985 | * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface. |
c4900be0 | 986 | * @hw: pointer to hardware structure |
07ce870b ET |
987 | * @dev_addr: address to read from |
988 | * @byte_offset: byte offset to read from dev_addr | |
c4900be0 DS |
989 | * @eeprom_data: value read |
990 | * | |
07ce870b | 991 | * Performs 8 byte read operation to SFP module's data over I2C interface. |
c4900be0 | 992 | **/ |
07ce870b ET |
993 | static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, |
994 | u8 byte_offset, u8 *eeprom_data) | |
c4900be0 DS |
995 | { |
996 | s32 status = 0; | |
997 | u16 sfp_addr = 0; | |
998 | u16 sfp_data = 0; | |
999 | u16 sfp_stat = 0; | |
3dcc2f41 | 1000 | u16 gssr; |
c4900be0 DS |
1001 | u32 i; |
1002 | ||
3dcc2f41 ET |
1003 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
1004 | gssr = IXGBE_GSSR_PHY1_SM; | |
1005 | else | |
1006 | gssr = IXGBE_GSSR_PHY0_SM; | |
1007 | ||
1008 | if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) | |
1009 | return IXGBE_ERR_SWFW_SYNC; | |
1010 | ||
c4900be0 DS |
1011 | if (hw->phy.type == ixgbe_phy_nl) { |
1012 | /* | |
1013 | * phy SDA/SCL registers are at addresses 0xC30A to | |
1014 | * 0xC30D. These registers are used to talk to the SFP+ | |
1015 | * module's EEPROM through the SDA/SCL (I2C) interface. | |
1016 | */ | |
07ce870b | 1017 | sfp_addr = (dev_addr << 8) + byte_offset; |
c4900be0 | 1018 | sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); |
3dcc2f41 ET |
1019 | hw->phy.ops.write_reg_mdi(hw, |
1020 | IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, | |
1021 | MDIO_MMD_PMAPMD, | |
1022 | sfp_addr); | |
c4900be0 DS |
1023 | |
1024 | /* Poll status */ | |
1025 | for (i = 0; i < 100; i++) { | |
3dcc2f41 ET |
1026 | hw->phy.ops.read_reg_mdi(hw, |
1027 | IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, | |
1028 | MDIO_MMD_PMAPMD, | |
1029 | &sfp_stat); | |
c4900be0 DS |
1030 | sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; |
1031 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) | |
1032 | break; | |
032b4325 | 1033 | usleep_range(10000, 20000); |
c4900be0 DS |
1034 | } |
1035 | ||
1036 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { | |
1037 | hw_dbg(hw, "EEPROM read did not pass.\n"); | |
1038 | status = IXGBE_ERR_SFP_NOT_PRESENT; | |
1039 | goto out; | |
1040 | } | |
1041 | ||
1042 | /* Read data */ | |
3dcc2f41 ET |
1043 | hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, |
1044 | MDIO_MMD_PMAPMD, &sfp_data); | |
c4900be0 DS |
1045 | |
1046 | *eeprom_data = (u8)(sfp_data >> 8); | |
1047 | } else { | |
1048 | status = IXGBE_ERR_PHY; | |
c4900be0 DS |
1049 | } |
1050 | ||
1051 | out: | |
3dcc2f41 | 1052 | hw->mac.ops.release_swfw_sync(hw, gssr); |
c4900be0 DS |
1053 | return status; |
1054 | } | |
1055 | ||
07ce870b ET |
1056 | /** |
1057 | * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. | |
1058 | * @hw: pointer to hardware structure | |
1059 | * @byte_offset: EEPROM byte offset to read | |
1060 | * @eeprom_data: value read | |
1061 | * | |
1062 | * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. | |
1063 | **/ | |
1064 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, | |
1065 | u8 *eeprom_data) | |
1066 | { | |
1067 | return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR, | |
1068 | byte_offset, eeprom_data); | |
1069 | } | |
1070 | ||
1071 | /** | |
1072 | * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface. | |
1073 | * @hw: pointer to hardware structure | |
1074 | * @byte_offset: byte offset at address 0xA2 | |
1075 | * @eeprom_data: value read | |
1076 | * | |
1077 | * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C | |
1078 | **/ | |
1079 | static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, | |
1080 | u8 *sff8472_data) | |
1081 | { | |
1082 | return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2, | |
1083 | byte_offset, sff8472_data); | |
1084 | } | |
1085 | ||
c9130180 ET |
1086 | /** |
1087 | * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple | |
1088 | * port devices. | |
1089 | * @hw: pointer to the HW structure | |
1090 | * | |
1091 | * Calls common function and corrects issue with some single port devices | |
1092 | * that enable LAN1 but not LAN0. | |
1093 | **/ | |
1094 | static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) | |
1095 | { | |
1096 | struct ixgbe_bus_info *bus = &hw->bus; | |
1097 | u16 pci_gen = 0; | |
1098 | u16 pci_ctrl2 = 0; | |
1099 | ||
1100 | ixgbe_set_lan_id_multi_port_pcie(hw); | |
1101 | ||
1102 | /* check if LAN0 is disabled */ | |
1103 | hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); | |
1104 | if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { | |
1105 | ||
1106 | hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); | |
1107 | ||
1108 | /* if LAN0 is completely disabled force function to 0 */ | |
1109 | if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && | |
1110 | !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && | |
1111 | !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { | |
1112 | ||
1113 | bus->func = 0; | |
1114 | } | |
1115 | } | |
1116 | } | |
1117 | ||
80605c65 | 1118 | /** |
44834700 | 1119 | * ixgbe_set_rxpba_82598 - Initialize RX packet buffer |
80605c65 | 1120 | * @hw: pointer to hardware structure |
44834700 JK |
1121 | * @num_pb: number of packet buffers to allocate |
1122 | * @headroom: reserve n KB of headroom | |
1123 | * @strategy: packet buffer allocation strategy | |
1124 | **/ | |
1125 | static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, | |
1126 | u32 headroom, int strategy) | |
80605c65 JF |
1127 | { |
1128 | u32 rxpktsize = IXGBE_RXPBSIZE_64KB; | |
1129 | u8 i = 0; | |
1130 | ||
1131 | if (!num_pb) | |
1132 | return; | |
1133 | ||
1134 | /* Setup Rx packet buffer sizes */ | |
1135 | switch (strategy) { | |
1136 | case PBA_STRATEGY_WEIGHTED: | |
1137 | /* Setup the first four at 80KB */ | |
1138 | rxpktsize = IXGBE_RXPBSIZE_80KB; | |
1139 | for (; i < 4; i++) | |
1140 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); | |
1141 | /* Setup the last four at 48KB...don't re-init i */ | |
1142 | rxpktsize = IXGBE_RXPBSIZE_48KB; | |
1143 | /* Fall Through */ | |
1144 | case PBA_STRATEGY_EQUAL: | |
1145 | default: | |
1146 | /* Divide the remaining Rx packet buffer evenly among the TCs */ | |
1147 | for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) | |
1148 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); | |
1149 | break; | |
1150 | } | |
1151 | ||
1152 | /* Setup Tx packet buffer sizes */ | |
1153 | for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) | |
1154 | IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); | |
80605c65 JF |
1155 | } |
1156 | ||
9a799d71 | 1157 | static struct ixgbe_mac_operations mac_ops_82598 = { |
c44ade9e JB |
1158 | .init_hw = &ixgbe_init_hw_generic, |
1159 | .reset_hw = &ixgbe_reset_hw_82598, | |
202ff1ec | 1160 | .start_hw = &ixgbe_start_hw_82598, |
c44ade9e | 1161 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
9a799d71 | 1162 | .get_media_type = &ixgbe_get_media_type_82598, |
11afc1b1 | 1163 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, |
c44ade9e JB |
1164 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
1165 | .stop_adapter = &ixgbe_stop_adapter_generic, | |
11afc1b1 | 1166 | .get_bus_info = &ixgbe_get_bus_info_generic, |
c9130180 | 1167 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598, |
c44ade9e JB |
1168 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, |
1169 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, | |
3957d63d | 1170 | .setup_link = &ixgbe_setup_mac_link_82598, |
80605c65 | 1171 | .set_rxpba = &ixgbe_set_rxpba_82598, |
c44ade9e JB |
1172 | .check_link = &ixgbe_check_mac_link_82598, |
1173 | .get_link_capabilities = &ixgbe_get_link_capabilities_82598, | |
1174 | .led_on = &ixgbe_led_on_generic, | |
1175 | .led_off = &ixgbe_led_off_generic, | |
87c12017 PW |
1176 | .blink_led_start = &ixgbe_blink_led_start_generic, |
1177 | .blink_led_stop = &ixgbe_blink_led_stop_generic, | |
c44ade9e JB |
1178 | .set_rar = &ixgbe_set_rar_generic, |
1179 | .clear_rar = &ixgbe_clear_rar_generic, | |
1180 | .set_vmdq = &ixgbe_set_vmdq_82598, | |
1181 | .clear_vmdq = &ixgbe_clear_vmdq_82598, | |
1182 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, | |
c44ade9e JB |
1183 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, |
1184 | .enable_mc = &ixgbe_enable_mc_generic, | |
1185 | .disable_mc = &ixgbe_disable_mc_generic, | |
1186 | .clear_vfta = &ixgbe_clear_vfta_82598, | |
1187 | .set_vfta = &ixgbe_set_vfta_82598, | |
620fa036 | 1188 | .fc_enable = &ixgbe_fc_enable_82598, |
9612de92 | 1189 | .set_fw_drv_ver = NULL, |
5e655105 DS |
1190 | .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, |
1191 | .release_swfw_sync = &ixgbe_release_swfw_sync, | |
3ca8bc6d DS |
1192 | .get_thermal_sensor_data = NULL, |
1193 | .init_thermal_sensor_thresh = NULL, | |
429d6a3b DS |
1194 | .prot_autoc_read = &prot_autoc_read_generic, |
1195 | .prot_autoc_write = &prot_autoc_write_generic, | |
c44ade9e JB |
1196 | }; |
1197 | ||
1198 | static struct ixgbe_eeprom_operations eeprom_ops_82598 = { | |
1199 | .init_params = &ixgbe_init_eeprom_params_generic, | |
21ce849b | 1200 | .read = &ixgbe_read_eerd_generic, |
2fa5eef4 ET |
1201 | .write = &ixgbe_write_eeprom_generic, |
1202 | .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, | |
68c7005d | 1203 | .read_buffer = &ixgbe_read_eerd_buffer_generic, |
a391f1d5 | 1204 | .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, |
c44ade9e JB |
1205 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, |
1206 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, | |
1207 | }; | |
1208 | ||
1209 | static struct ixgbe_phy_operations phy_ops_82598 = { | |
1210 | .identify = &ixgbe_identify_phy_generic, | |
8f58332b | 1211 | .identify_sfp = &ixgbe_identify_module_generic, |
04f165ef | 1212 | .init = &ixgbe_init_phy_ops_82598, |
c44ade9e JB |
1213 | .reset = &ixgbe_reset_phy_generic, |
1214 | .read_reg = &ixgbe_read_phy_reg_generic, | |
1215 | .write_reg = &ixgbe_write_phy_reg_generic, | |
3dcc2f41 ET |
1216 | .read_reg_mdi = &ixgbe_read_phy_reg_mdi, |
1217 | .write_reg_mdi = &ixgbe_write_phy_reg_mdi, | |
c44ade9e JB |
1218 | .setup_link = &ixgbe_setup_phy_link_generic, |
1219 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
07ce870b | 1220 | .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598, |
c4900be0 | 1221 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, |
119fc60a | 1222 | .check_overtemp = &ixgbe_tn_check_overtemp, |
9a799d71 AK |
1223 | }; |
1224 | ||
3957d63d | 1225 | struct ixgbe_info ixgbe_82598_info = { |
9a799d71 AK |
1226 | .mac = ixgbe_mac_82598EB, |
1227 | .get_invariants = &ixgbe_get_invariants_82598, | |
1228 | .mac_ops = &mac_ops_82598, | |
c44ade9e JB |
1229 | .eeprom_ops = &eeprom_ops_82598, |
1230 | .phy_ops = &phy_ops_82598, | |
9a799d71 | 1231 | }; |