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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
a52055e0 | 4 | Copyright(c) 1999 - 2011 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
9c8eb720 | 32 | #include "ixgbe.h" |
9a799d71 AK |
33 | #include "ixgbe_phy.h" |
34 | ||
35 | #define IXGBE_82598_MAX_TX_QUEUES 32 | |
36 | #define IXGBE_82598_MAX_RX_QUEUES 64 | |
37 | #define IXGBE_82598_RAR_ENTRIES 16 | |
2c5645cf CL |
38 | #define IXGBE_82598_MC_TBL_SIZE 128 |
39 | #define IXGBE_82598_VFT_TBL_SIZE 128 | |
e09ad236 | 40 | #define IXGBE_82598_RX_PB_SIZE 512 |
9a799d71 | 41 | |
8620a103 | 42 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
21ce849b MC |
43 | ixgbe_link_speed speed, |
44 | bool autoneg, | |
45 | bool autoneg_wait_to_complete); | |
c4900be0 DS |
46 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
47 | u8 *eeprom_data); | |
9a799d71 | 48 | |
202ff1ec MC |
49 | /** |
50 | * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout | |
51 | * @hw: pointer to the HW structure | |
52 | * | |
53 | * The defaults for 82598 should be in the range of 50us to 50ms, | |
54 | * however the hardware default for these parts is 500us to 1ms which is less | |
55 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
56 | * increase the value to either 10ms to 250ms for capability version 1 config, | |
57 | * or 16ms to 55ms for version 2. | |
58 | **/ | |
7b25cdba | 59 | static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) |
202ff1ec MC |
60 | { |
61 | struct ixgbe_adapter *adapter = hw->back; | |
62 | u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); | |
63 | u16 pcie_devctl2; | |
64 | ||
65 | /* only take action if timeout value is defaulted to 0 */ | |
66 | if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) | |
67 | goto out; | |
68 | ||
69 | /* | |
70 | * if capababilities version is type 1 we can write the | |
71 | * timeout of 10ms to 250ms through the GCR register | |
72 | */ | |
73 | if (!(gcr & IXGBE_GCR_CAP_VER2)) { | |
74 | gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; | |
75 | goto out; | |
76 | } | |
77 | ||
78 | /* | |
79 | * for version 2 capabilities we need to write the config space | |
80 | * directly in order to set the completion timeout value for | |
81 | * 16ms to 55ms | |
82 | */ | |
83 | pci_read_config_word(adapter->pdev, | |
84 | IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2); | |
85 | pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; | |
86 | pci_write_config_word(adapter->pdev, | |
87 | IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); | |
88 | out: | |
89 | /* disable completion timeout resend */ | |
90 | gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; | |
91 | IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); | |
92 | } | |
93 | ||
eb7f139c PWJ |
94 | /** |
95 | * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count | |
96 | * @hw: pointer to hardware structure | |
97 | * | |
98 | * Read PCIe configuration space, and get the MSI-X vector count from | |
99 | * the capabilities table. | |
100 | **/ | |
1aef47c4 | 101 | static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) |
eb7f139c PWJ |
102 | { |
103 | struct ixgbe_adapter *adapter = hw->back; | |
104 | u16 msix_count; | |
105 | pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS, | |
106 | &msix_count); | |
107 | msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; | |
108 | ||
109 | /* MSI-X count is zero-based in HW, so increment to give proper value */ | |
110 | msix_count++; | |
111 | ||
112 | return msix_count; | |
113 | } | |
114 | ||
c44ade9e JB |
115 | /** |
116 | */ | |
9a799d71 | 117 | static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) |
04f165ef PW |
118 | { |
119 | struct ixgbe_mac_info *mac = &hw->mac; | |
120 | ||
121 | /* Call PHY identify routine to get the phy type */ | |
122 | ixgbe_identify_phy_generic(hw); | |
123 | ||
124 | mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; | |
125 | mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; | |
126 | mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; | |
127 | mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; | |
128 | mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; | |
129 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | /** | |
135 | * ixgbe_init_phy_ops_82598 - PHY/SFP specific init | |
136 | * @hw: pointer to hardware structure | |
137 | * | |
138 | * Initialize any function pointers that were not able to be | |
139 | * set during get_invariants because the PHY/SFP type was | |
140 | * not known. Perform the SFP init if necessary. | |
141 | * | |
142 | **/ | |
7b25cdba | 143 | static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) |
9a799d71 | 144 | { |
c44ade9e JB |
145 | struct ixgbe_mac_info *mac = &hw->mac; |
146 | struct ixgbe_phy_info *phy = &hw->phy; | |
c4900be0 DS |
147 | s32 ret_val = 0; |
148 | u16 list_offset, data_offset; | |
c44ade9e | 149 | |
04f165ef PW |
150 | /* Identify the PHY */ |
151 | phy->ops.identify(hw); | |
03cfa205 | 152 | |
04f165ef PW |
153 | /* Overwrite the link function pointers if copper PHY */ |
154 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { | |
155 | mac->ops.setup_link = &ixgbe_setup_copper_link_82598; | |
04f165ef | 156 | mac->ops.get_link_capabilities = |
a391f1d5 | 157 | &ixgbe_get_copper_link_capabilities_generic; |
04f165ef | 158 | } |
c44ade9e | 159 | |
04f165ef | 160 | switch (hw->phy.type) { |
0befdb3e | 161 | case ixgbe_phy_tn: |
9dda1736 | 162 | phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; |
0befdb3e JB |
163 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; |
164 | phy->ops.get_firmware_version = | |
165 | &ixgbe_get_phy_firmware_version_tnx; | |
166 | break; | |
c4900be0 DS |
167 | case ixgbe_phy_nl: |
168 | phy->ops.reset = &ixgbe_reset_phy_nl; | |
169 | ||
170 | /* Call SFP+ identify routine to get the SFP+ module type */ | |
171 | ret_val = phy->ops.identify_sfp(hw); | |
172 | if (ret_val != 0) | |
173 | goto out; | |
174 | else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { | |
175 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
176 | goto out; | |
177 | } | |
178 | ||
179 | /* Check to see if SFP+ module is supported */ | |
180 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, | |
04f165ef PW |
181 | &list_offset, |
182 | &data_offset); | |
c4900be0 DS |
183 | if (ret_val != 0) { |
184 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
185 | goto out; | |
186 | } | |
187 | break; | |
c44ade9e JB |
188 | default: |
189 | break; | |
190 | } | |
191 | ||
c4900be0 DS |
192 | out: |
193 | return ret_val; | |
9a799d71 AK |
194 | } |
195 | ||
202ff1ec MC |
196 | /** |
197 | * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx | |
198 | * @hw: pointer to hardware structure | |
199 | * | |
200 | * Starts the hardware using the generic start_hw function. | |
3d5c5207 ET |
201 | * Disables relaxed ordering Then set pcie completion timeout |
202 | * | |
202ff1ec | 203 | **/ |
7b25cdba | 204 | static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) |
202ff1ec | 205 | { |
3d5c5207 ET |
206 | u32 regval; |
207 | u32 i; | |
202ff1ec MC |
208 | s32 ret_val = 0; |
209 | ||
210 | ret_val = ixgbe_start_hw_generic(hw); | |
211 | ||
3d5c5207 ET |
212 | /* Disable relaxed ordering */ |
213 | for (i = 0; ((i < hw->mac.max_tx_queues) && | |
214 | (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { | |
215 | regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); | |
216 | regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; | |
217 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); | |
218 | } | |
219 | ||
220 | for (i = 0; ((i < hw->mac.max_rx_queues) && | |
221 | (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { | |
222 | regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
223 | regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
224 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); | |
225 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); | |
226 | } | |
227 | ||
e09ad236 JF |
228 | hw->mac.rx_pb_size = IXGBE_82598_RX_PB_SIZE; |
229 | ||
202ff1ec MC |
230 | /* set the completion timeout for interface */ |
231 | if (ret_val == 0) | |
232 | ixgbe_set_pcie_completion_timeout(hw); | |
233 | ||
234 | return ret_val; | |
235 | } | |
236 | ||
9a799d71 | 237 | /** |
c44ade9e | 238 | * ixgbe_get_link_capabilities_82598 - Determines link capabilities |
9a799d71 AK |
239 | * @hw: pointer to hardware structure |
240 | * @speed: pointer to link speed | |
241 | * @autoneg: boolean auto-negotiation value | |
242 | * | |
c44ade9e | 243 | * Determines the link capabilities by reading the AUTOC register. |
9a799d71 | 244 | **/ |
c44ade9e | 245 | static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, |
b4617240 PW |
246 | ixgbe_link_speed *speed, |
247 | bool *autoneg) | |
9a799d71 AK |
248 | { |
249 | s32 status = 0; | |
1eb99d5a | 250 | u32 autoc = 0; |
9a799d71 | 251 | |
3201d313 PWJ |
252 | /* |
253 | * Determine link capabilities based on the stored value of AUTOC, | |
1eb99d5a PW |
254 | * which represents EEPROM defaults. If AUTOC value has not been |
255 | * stored, use the current register value. | |
3201d313 | 256 | */ |
1eb99d5a PW |
257 | if (hw->mac.orig_link_settings_stored) |
258 | autoc = hw->mac.orig_autoc; | |
259 | else | |
260 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
261 | ||
262 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { | |
9a799d71 AK |
263 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
264 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
265 | *autoneg = false; | |
266 | break; | |
267 | ||
268 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: | |
269 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
270 | *autoneg = false; | |
271 | break; | |
272 | ||
273 | case IXGBE_AUTOC_LMS_1G_AN: | |
274 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
275 | *autoneg = true; | |
276 | break; | |
277 | ||
278 | case IXGBE_AUTOC_LMS_KX4_AN: | |
279 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
280 | *speed = IXGBE_LINK_SPEED_UNKNOWN; | |
1eb99d5a | 281 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
9a799d71 | 282 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 283 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
9a799d71 AK |
284 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
285 | *autoneg = true; | |
286 | break; | |
287 | ||
288 | default: | |
289 | status = IXGBE_ERR_LINK_SETUP; | |
290 | break; | |
291 | } | |
292 | ||
293 | return status; | |
294 | } | |
295 | ||
9a799d71 AK |
296 | /** |
297 | * ixgbe_get_media_type_82598 - Determines media type | |
298 | * @hw: pointer to hardware structure | |
299 | * | |
300 | * Returns the media type (fiber, copper, backplane) | |
301 | **/ | |
302 | static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) | |
303 | { | |
304 | enum ixgbe_media_type media_type; | |
305 | ||
037c6d0a ET |
306 | /* Detect if there is a copper PHY attached. */ |
307 | switch (hw->phy.type) { | |
308 | case ixgbe_phy_cu_unknown: | |
309 | case ixgbe_phy_tn: | |
310 | case ixgbe_phy_aq: | |
311 | media_type = ixgbe_media_type_copper; | |
312 | goto out; | |
313 | default: | |
314 | break; | |
315 | } | |
316 | ||
9a799d71 AK |
317 | /* Media type for I82598 is based on device ID */ |
318 | switch (hw->device_id) { | |
1e336d0f | 319 | case IXGBE_DEV_ID_82598: |
2f21bdd3 | 320 | case IXGBE_DEV_ID_82598_BX: |
037c6d0a | 321 | /* Default device ID is mezzanine card KX/KX4 */ |
1e336d0f DS |
322 | media_type = ixgbe_media_type_backplane; |
323 | break; | |
9a799d71 AK |
324 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: |
325 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
c4900be0 DS |
326 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: |
327 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
b95f5fcb | 328 | case IXGBE_DEV_ID_82598EB_XF_LR: |
c4900be0 | 329 | case IXGBE_DEV_ID_82598EB_SFP_LOM: |
9a799d71 AK |
330 | media_type = ixgbe_media_type_fiber; |
331 | break; | |
6b1be199 PWJ |
332 | case IXGBE_DEV_ID_82598EB_CX4: |
333 | case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: | |
334 | media_type = ixgbe_media_type_cx4; | |
335 | break; | |
0befdb3e | 336 | case IXGBE_DEV_ID_82598AT: |
3845bec0 | 337 | case IXGBE_DEV_ID_82598AT2: |
0befdb3e JB |
338 | media_type = ixgbe_media_type_copper; |
339 | break; | |
9a799d71 AK |
340 | default: |
341 | media_type = ixgbe_media_type_unknown; | |
342 | break; | |
343 | } | |
037c6d0a | 344 | out: |
9a799d71 AK |
345 | return media_type; |
346 | } | |
347 | ||
c44ade9e | 348 | /** |
0ecc061d | 349 | * ixgbe_fc_enable_82598 - Enable flow control |
c44ade9e JB |
350 | * @hw: pointer to hardware structure |
351 | * @packetbuf_num: packet buffer number (0-7) | |
352 | * | |
0ecc061d | 353 | * Enable flow control according to the current settings. |
c44ade9e | 354 | **/ |
0ecc061d | 355 | static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) |
c44ade9e | 356 | { |
0ecc061d PWJ |
357 | s32 ret_val = 0; |
358 | u32 fctrl_reg; | |
c44ade9e | 359 | u32 rmcs_reg; |
0ecc061d | 360 | u32 reg; |
16b61beb | 361 | u32 rx_pba_size; |
a626e847 DS |
362 | u32 link_speed = 0; |
363 | bool link_up; | |
c44ade9e | 364 | |
620fa036 MC |
365 | #ifdef CONFIG_DCB |
366 | if (hw->fc.requested_mode == ixgbe_fc_pfc) | |
367 | goto out; | |
368 | ||
369 | #endif /* CONFIG_DCB */ | |
a626e847 DS |
370 | /* |
371 | * On 82598 having Rx FC on causes resets while doing 1G | |
372 | * so if it's on turn it off once we know link_speed. For | |
373 | * more details see 82598 Specification update. | |
374 | */ | |
375 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
376 | if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { | |
377 | switch (hw->fc.requested_mode) { | |
378 | case ixgbe_fc_full: | |
379 | hw->fc.requested_mode = ixgbe_fc_tx_pause; | |
380 | break; | |
381 | case ixgbe_fc_rx_pause: | |
382 | hw->fc.requested_mode = ixgbe_fc_none; | |
383 | break; | |
384 | default: | |
385 | /* no change */ | |
386 | break; | |
387 | } | |
388 | } | |
389 | ||
620fa036 MC |
390 | /* Negotiate the fc mode to use */ |
391 | ret_val = ixgbe_fc_autoneg(hw); | |
0b0c2b31 | 392 | if (ret_val == IXGBE_ERR_FLOW_CONTROL) |
620fa036 MC |
393 | goto out; |
394 | ||
395 | /* Disable any previous flow control settings */ | |
0ecc061d PWJ |
396 | fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
397 | fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); | |
c44ade9e JB |
398 | |
399 | rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
400 | rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); | |
401 | ||
402 | /* | |
0ecc061d | 403 | * The possible values of fc.current_mode are: |
c44ade9e | 404 | * 0: Flow control is completely disabled |
0ecc061d PWJ |
405 | * 1: Rx flow control is enabled (we can receive pause frames, |
406 | * but not send pause frames). | |
620fa036 | 407 | * 2: Tx flow control is enabled (we can send pause frames but |
0ecc061d | 408 | * we do not support receiving pause frames). |
c44ade9e | 409 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
620fa036 MC |
410 | #ifdef CONFIG_DCB |
411 | * 4: Priority Flow Control is enabled. | |
412 | #endif | |
0b0c2b31 | 413 | * other: Invalid. |
c44ade9e | 414 | */ |
0ecc061d | 415 | switch (hw->fc.current_mode) { |
c44ade9e | 416 | case ixgbe_fc_none: |
620fa036 MC |
417 | /* |
418 | * Flow control is disabled by software override or autoneg. | |
419 | * The code below will actually disable it in the HW. | |
420 | */ | |
c44ade9e JB |
421 | break; |
422 | case ixgbe_fc_rx_pause: | |
423 | /* | |
0ecc061d PWJ |
424 | * Rx Flow control is enabled and Tx Flow control is |
425 | * disabled by software override. Since there really | |
426 | * isn't a way to advertise that we are capable of RX | |
427 | * Pause ONLY, we will advertise that we support both | |
428 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
429 | * disable the adapter's ability to send PAUSE frames. | |
c44ade9e | 430 | */ |
0ecc061d | 431 | fctrl_reg |= IXGBE_FCTRL_RFCE; |
c44ade9e JB |
432 | break; |
433 | case ixgbe_fc_tx_pause: | |
434 | /* | |
0ecc061d PWJ |
435 | * Tx Flow control is enabled, and Rx Flow control is |
436 | * disabled by software override. | |
c44ade9e JB |
437 | */ |
438 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | |
439 | break; | |
440 | case ixgbe_fc_full: | |
0ecc061d PWJ |
441 | /* Flow control (both Rx and Tx) is enabled by SW override. */ |
442 | fctrl_reg |= IXGBE_FCTRL_RFCE; | |
c44ade9e JB |
443 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; |
444 | break; | |
620fa036 MC |
445 | #ifdef CONFIG_DCB |
446 | case ixgbe_fc_pfc: | |
447 | goto out; | |
448 | break; | |
449 | #endif /* CONFIG_DCB */ | |
c44ade9e | 450 | default: |
c44ade9e | 451 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
539e5f02 | 452 | ret_val = IXGBE_ERR_CONFIG; |
0ecc061d | 453 | goto out; |
c44ade9e JB |
454 | break; |
455 | } | |
456 | ||
620fa036 | 457 | /* Set 802.3x based flow control settings. */ |
2132d381 | 458 | fctrl_reg |= IXGBE_FCTRL_DPF; |
0ecc061d | 459 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); |
c44ade9e JB |
460 | IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); |
461 | ||
0ecc061d PWJ |
462 | /* Set up and enable Rx high/low water mark thresholds, enable XON. */ |
463 | if (hw->fc.current_mode & ixgbe_fc_tx_pause) { | |
16b61beb JF |
464 | rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); |
465 | rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT; | |
466 | ||
467 | reg = (rx_pba_size - hw->fc.low_water) << 6; | |
468 | if (hw->fc.send_xon) | |
469 | reg |= IXGBE_FCRTL_XONE; | |
0b0c2b31 | 470 | |
16b61beb JF |
471 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg); |
472 | ||
0b0c2b31 | 473 | reg = (rx_pba_size - hw->fc.high_water) << 6; |
16b61beb | 474 | reg |= IXGBE_FCRTH_FCEN; |
0ecc061d | 475 | |
16b61beb | 476 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg); |
c44ade9e JB |
477 | } |
478 | ||
0ecc061d | 479 | /* Configure pause time (2 TCs per register) */ |
264857b8 | 480 | reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); |
0ecc061d PWJ |
481 | if ((packetbuf_num & 1) == 0) |
482 | reg = (reg & 0xFFFF0000) | hw->fc.pause_time; | |
483 | else | |
484 | reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); | |
485 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); | |
486 | ||
c44ade9e JB |
487 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); |
488 | ||
0ecc061d PWJ |
489 | out: |
490 | return ret_val; | |
491 | } | |
492 | ||
9a799d71 | 493 | /** |
8620a103 | 494 | * ixgbe_start_mac_link_82598 - Configures MAC link settings |
9a799d71 AK |
495 | * @hw: pointer to hardware structure |
496 | * | |
497 | * Configures link settings based on values in the ixgbe_hw struct. | |
498 | * Restarts the link. Performs autonegotiation if needed. | |
499 | **/ | |
8620a103 MC |
500 | static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, |
501 | bool autoneg_wait_to_complete) | |
9a799d71 AK |
502 | { |
503 | u32 autoc_reg; | |
504 | u32 links_reg; | |
505 | u32 i; | |
506 | s32 status = 0; | |
507 | ||
9a799d71 | 508 | /* Restart link */ |
3201d313 | 509 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
9a799d71 AK |
510 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
511 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); | |
512 | ||
513 | /* Only poll for autoneg to complete if specified to do so */ | |
8620a103 | 514 | if (autoneg_wait_to_complete) { |
3201d313 PWJ |
515 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
516 | IXGBE_AUTOC_LMS_KX4_AN || | |
517 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == | |
518 | IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
9a799d71 AK |
519 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
520 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { | |
521 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
522 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) | |
523 | break; | |
524 | msleep(100); | |
525 | } | |
526 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { | |
527 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; | |
c44ade9e | 528 | hw_dbg(hw, "Autonegotiation did not complete.\n"); |
9a799d71 AK |
529 | } |
530 | } | |
531 | } | |
532 | ||
9a799d71 AK |
533 | /* Add delay to filter out noises during initial link setup */ |
534 | msleep(50); | |
535 | ||
536 | return status; | |
537 | } | |
538 | ||
734e979f MC |
539 | /** |
540 | * ixgbe_validate_link_ready - Function looks for phy link | |
541 | * @hw: pointer to hardware structure | |
542 | * | |
543 | * Function indicates success when phy link is available. If phy is not ready | |
544 | * within 5 seconds of MAC indicating link, the function returns error. | |
545 | **/ | |
546 | static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) | |
547 | { | |
548 | u32 timeout; | |
549 | u16 an_reg; | |
550 | ||
551 | if (hw->device_id != IXGBE_DEV_ID_82598AT2) | |
552 | return 0; | |
553 | ||
554 | for (timeout = 0; | |
555 | timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { | |
556 | hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); | |
557 | ||
558 | if ((an_reg & MDIO_AN_STAT1_COMPLETE) && | |
559 | (an_reg & MDIO_STAT1_LSTATUS)) | |
560 | break; | |
561 | ||
562 | msleep(100); | |
563 | } | |
564 | ||
565 | if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { | |
566 | hw_dbg(hw, "Link was indicated but link is down\n"); | |
567 | return IXGBE_ERR_LINK_SETUP; | |
568 | } | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
9a799d71 AK |
573 | /** |
574 | * ixgbe_check_mac_link_82598 - Get link/speed status | |
575 | * @hw: pointer to hardware structure | |
576 | * @speed: pointer to link speed | |
577 | * @link_up: true is link is up, false otherwise | |
cf8280ee | 578 | * @link_up_wait_to_complete: bool used to wait for link up or not |
9a799d71 AK |
579 | * |
580 | * Reads the links register to determine if link is up and the current speed | |
581 | **/ | |
b4617240 PW |
582 | static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, |
583 | ixgbe_link_speed *speed, bool *link_up, | |
584 | bool link_up_wait_to_complete) | |
9a799d71 AK |
585 | { |
586 | u32 links_reg; | |
cf8280ee | 587 | u32 i; |
c4900be0 DS |
588 | u16 link_reg, adapt_comp_reg; |
589 | ||
590 | /* | |
591 | * SERDES PHY requires us to read link status from register 0xC79F. | |
592 | * Bit 0 set indicates link is up/ready; clear indicates link down. | |
593 | * 0xC00C is read to check that the XAUI lanes are active. Bit 0 | |
594 | * clear indicates active; set indicates inactive. | |
595 | */ | |
596 | if (hw->phy.type == ixgbe_phy_nl) { | |
6b73e10d BH |
597 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); |
598 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); | |
599 | hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, | |
c4900be0 DS |
600 | &adapt_comp_reg); |
601 | if (link_up_wait_to_complete) { | |
602 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
603 | if ((link_reg & 1) && | |
604 | ((adapt_comp_reg & 1) == 0)) { | |
605 | *link_up = true; | |
606 | break; | |
607 | } else { | |
608 | *link_up = false; | |
609 | } | |
610 | msleep(100); | |
611 | hw->phy.ops.read_reg(hw, 0xC79F, | |
6b73e10d | 612 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
613 | &link_reg); |
614 | hw->phy.ops.read_reg(hw, 0xC00C, | |
6b73e10d | 615 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
616 | &adapt_comp_reg); |
617 | } | |
618 | } else { | |
619 | if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) | |
620 | *link_up = true; | |
621 | else | |
622 | *link_up = false; | |
623 | } | |
624 | ||
625 | if (*link_up == false) | |
626 | goto out; | |
627 | } | |
9a799d71 AK |
628 | |
629 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
cf8280ee JB |
630 | if (link_up_wait_to_complete) { |
631 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
632 | if (links_reg & IXGBE_LINKS_UP) { | |
633 | *link_up = true; | |
634 | break; | |
635 | } else { | |
636 | *link_up = false; | |
637 | } | |
638 | msleep(100); | |
639 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
640 | } | |
641 | } else { | |
642 | if (links_reg & IXGBE_LINKS_UP) | |
643 | *link_up = true; | |
644 | else | |
645 | *link_up = false; | |
646 | } | |
9a799d71 AK |
647 | |
648 | if (links_reg & IXGBE_LINKS_SPEED) | |
649 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
650 | else | |
651 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
652 | ||
734e979f MC |
653 | if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) && |
654 | (ixgbe_validate_link_ready(hw) != 0)) | |
655 | *link_up = false; | |
656 | ||
620fa036 MC |
657 | /* if link is down, zero out the current_mode */ |
658 | if (*link_up == false) { | |
659 | hw->fc.current_mode = ixgbe_fc_none; | |
660 | hw->fc.fc_was_autonegged = false; | |
661 | } | |
c4900be0 | 662 | out: |
9a799d71 AK |
663 | return 0; |
664 | } | |
665 | ||
666 | /** | |
8620a103 | 667 | * ixgbe_setup_mac_link_82598 - Set MAC link speed |
9a799d71 AK |
668 | * @hw: pointer to hardware structure |
669 | * @speed: new link speed | |
670 | * @autoneg: true if auto-negotiation enabled | |
037c6d0a | 671 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
9a799d71 AK |
672 | * |
673 | * Set the link speed in the AUTOC register and restarts link. | |
674 | **/ | |
8620a103 | 675 | static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, |
3201d313 PWJ |
676 | ixgbe_link_speed speed, bool autoneg, |
677 | bool autoneg_wait_to_complete) | |
9a799d71 | 678 | { |
3201d313 PWJ |
679 | s32 status = 0; |
680 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; | |
681 | u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
682 | u32 autoc = curr_autoc; | |
683 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; | |
9a799d71 | 684 | |
3201d313 PWJ |
685 | /* Check to see if speed passed in is supported. */ |
686 | ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); | |
687 | speed &= link_capabilities; | |
688 | ||
689 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) | |
9a799d71 | 690 | status = IXGBE_ERR_LINK_SETUP; |
3201d313 PWJ |
691 | |
692 | /* Set KX4/KX support according to speed requested */ | |
693 | else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || | |
694 | link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
695 | autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; | |
696 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
697 | autoc |= IXGBE_AUTOC_KX4_SUPP; | |
698 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
699 | autoc |= IXGBE_AUTOC_KX_SUPP; | |
700 | if (autoc != curr_autoc) | |
701 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); | |
9a799d71 AK |
702 | } |
703 | ||
704 | if (status == 0) { | |
9a799d71 AK |
705 | /* |
706 | * Setup and restart the link based on the new values in | |
707 | * ixgbe_hw This will write the AUTOC register based on the new | |
708 | * stored values | |
709 | */ | |
037c6d0a ET |
710 | status = ixgbe_start_mac_link_82598(hw, |
711 | autoneg_wait_to_complete); | |
9a799d71 AK |
712 | } |
713 | ||
714 | return status; | |
715 | } | |
716 | ||
717 | ||
718 | /** | |
8620a103 | 719 | * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field |
9a799d71 AK |
720 | * @hw: pointer to hardware structure |
721 | * @speed: new link speed | |
722 | * @autoneg: true if autonegotiation enabled | |
723 | * @autoneg_wait_to_complete: true if waiting is needed to complete | |
724 | * | |
725 | * Sets the link speed in the AUTOC register in the MAC and restarts link. | |
726 | **/ | |
8620a103 | 727 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
b4617240 PW |
728 | ixgbe_link_speed speed, |
729 | bool autoneg, | |
730 | bool autoneg_wait_to_complete) | |
9a799d71 | 731 | { |
c44ade9e | 732 | s32 status; |
9a799d71 AK |
733 | |
734 | /* Setup the PHY according to input speed */ | |
b4617240 PW |
735 | status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, |
736 | autoneg_wait_to_complete); | |
3957d63d | 737 | /* Set up MAC */ |
8620a103 | 738 | ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); |
9a799d71 AK |
739 | |
740 | return status; | |
741 | } | |
742 | ||
743 | /** | |
744 | * ixgbe_reset_hw_82598 - Performs hardware reset | |
745 | * @hw: pointer to hardware structure | |
746 | * | |
c44ade9e | 747 | * Resets the hardware by resetting the transmit and receive units, masks and |
9a799d71 AK |
748 | * clears all interrupts, performing a PHY reset, and performing a link (MAC) |
749 | * reset. | |
750 | **/ | |
751 | static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) | |
752 | { | |
753 | s32 status = 0; | |
8ca783ab | 754 | s32 phy_status = 0; |
9a799d71 AK |
755 | u32 ctrl; |
756 | u32 gheccr; | |
757 | u32 i; | |
758 | u32 autoc; | |
759 | u8 analog_val; | |
760 | ||
761 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
c44ade9e | 762 | hw->mac.ops.stop_adapter(hw); |
9a799d71 AK |
763 | |
764 | /* | |
c44ade9e JB |
765 | * Power up the Atlas Tx lanes if they are currently powered down. |
766 | * Atlas Tx lanes are powered down for MAC loopback tests, but | |
9a799d71 AK |
767 | * they are not automatically restored on reset. |
768 | */ | |
c44ade9e | 769 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); |
9a799d71 | 770 | if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { |
c44ade9e JB |
771 | /* Enable Tx Atlas so packets can be transmitted again */ |
772 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, | |
773 | &analog_val); | |
9a799d71 | 774 | analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; |
c44ade9e JB |
775 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, |
776 | analog_val); | |
9a799d71 | 777 | |
c44ade9e JB |
778 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
779 | &analog_val); | |
9a799d71 | 780 | analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; |
c44ade9e JB |
781 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
782 | analog_val); | |
9a799d71 | 783 | |
c44ade9e JB |
784 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
785 | &analog_val); | |
9a799d71 | 786 | analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; |
c44ade9e JB |
787 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
788 | analog_val); | |
9a799d71 | 789 | |
c44ade9e JB |
790 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
791 | &analog_val); | |
9a799d71 | 792 | analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; |
c44ade9e JB |
793 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
794 | analog_val); | |
9a799d71 AK |
795 | } |
796 | ||
797 | /* Reset PHY */ | |
04f165ef PW |
798 | if (hw->phy.reset_disable == false) { |
799 | /* PHY ops must be identified and initialized prior to reset */ | |
800 | ||
801 | /* Init PHY and function pointers, perform SFP setup */ | |
8ca783ab DS |
802 | phy_status = hw->phy.ops.init(hw); |
803 | if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
04f165ef | 804 | goto reset_hw_out; |
8ca783ab DS |
805 | else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) |
806 | goto no_phy_reset; | |
807 | ||
c44ade9e | 808 | hw->phy.ops.reset(hw); |
04f165ef | 809 | } |
9a799d71 | 810 | |
8ca783ab | 811 | no_phy_reset: |
9a799d71 AK |
812 | /* |
813 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
814 | * access and verify no pending requests before reset | |
815 | */ | |
a4297dc2 | 816 | ixgbe_disable_pcie_master(hw); |
9a799d71 | 817 | |
a4297dc2 | 818 | mac_reset_top: |
9a799d71 AK |
819 | /* |
820 | * Issue global reset to the MAC. This needs to be a SW reset. | |
821 | * If link reset is used, it might reset the MAC when mng is using it | |
822 | */ | |
823 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
824 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); | |
825 | IXGBE_WRITE_FLUSH(hw); | |
826 | ||
827 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
828 | for (i = 0; i < 10; i++) { | |
829 | udelay(1); | |
830 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
831 | if (!(ctrl & IXGBE_CTRL_RST)) | |
832 | break; | |
833 | } | |
834 | if (ctrl & IXGBE_CTRL_RST) { | |
835 | status = IXGBE_ERR_RESET_FAILED; | |
836 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
837 | } | |
838 | ||
a4297dc2 ET |
839 | /* |
840 | * Double resets are required for recovery from certain error | |
841 | * conditions. Between resets, it is necessary to stall to allow time | |
842 | * for any pending HW events to complete. We use 1usec since that is | |
843 | * what is needed for ixgbe_disable_pcie_master(). The second reset | |
844 | * then clears out any effects of those events. | |
845 | */ | |
846 | if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { | |
847 | hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; | |
848 | udelay(1); | |
849 | goto mac_reset_top; | |
850 | } | |
851 | ||
9a799d71 AK |
852 | msleep(50); |
853 | ||
854 | gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); | |
855 | gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); | |
856 | IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); | |
857 | ||
858 | /* | |
3201d313 PWJ |
859 | * Store the original AUTOC value if it has not been |
860 | * stored off yet. Otherwise restore the stored original | |
861 | * AUTOC value since the reset operation sets back to deaults. | |
9a799d71 AK |
862 | */ |
863 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
3201d313 PWJ |
864 | if (hw->mac.orig_link_settings_stored == false) { |
865 | hw->mac.orig_autoc = autoc; | |
866 | hw->mac.orig_link_settings_stored = true; | |
867 | } else if (autoc != hw->mac.orig_autoc) { | |
868 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); | |
9a799d71 AK |
869 | } |
870 | ||
278675d8 ET |
871 | /* Store the permanent mac address */ |
872 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); | |
873 | ||
aca6bee7 WJP |
874 | /* |
875 | * Store MAC address from RAR0, clear receive address registers, and | |
876 | * clear the multicast table | |
877 | */ | |
878 | hw->mac.ops.init_rx_addrs(hw); | |
879 | ||
04f165ef | 880 | reset_hw_out: |
8ca783ab DS |
881 | if (phy_status) |
882 | status = phy_status; | |
883 | ||
9a799d71 AK |
884 | return status; |
885 | } | |
886 | ||
c44ade9e JB |
887 | /** |
888 | * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address | |
889 | * @hw: pointer to hardware struct | |
890 | * @rar: receive address register index to associate with a VMDq index | |
891 | * @vmdq: VMDq set index | |
892 | **/ | |
e855aac8 | 893 | static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
c44ade9e JB |
894 | { |
895 | u32 rar_high; | |
c700f4e6 ET |
896 | u32 rar_entries = hw->mac.num_rar_entries; |
897 | ||
898 | /* Make sure we are using a valid rar index range */ | |
899 | if (rar >= rar_entries) { | |
900 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); | |
901 | return IXGBE_ERR_INVALID_ARGUMENT; | |
902 | } | |
c44ade9e JB |
903 | |
904 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
905 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
906 | rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); | |
907 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
908 | return 0; | |
909 | } | |
910 | ||
911 | /** | |
912 | * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address | |
913 | * @hw: pointer to hardware struct | |
914 | * @rar: receive address register index to associate with a VMDq index | |
915 | * @vmdq: VMDq clear index (not used in 82598, but elsewhere) | |
916 | **/ | |
917 | static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) | |
918 | { | |
919 | u32 rar_high; | |
920 | u32 rar_entries = hw->mac.num_rar_entries; | |
921 | ||
c700f4e6 ET |
922 | |
923 | /* Make sure we are using a valid rar index range */ | |
924 | if (rar >= rar_entries) { | |
c44ade9e | 925 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); |
c700f4e6 ET |
926 | return IXGBE_ERR_INVALID_ARGUMENT; |
927 | } | |
928 | ||
929 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
930 | if (rar_high & IXGBE_RAH_VIND_MASK) { | |
931 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
932 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
c44ade9e JB |
933 | } |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
938 | /** | |
939 | * ixgbe_set_vfta_82598 - Set VLAN filter table | |
940 | * @hw: pointer to hardware structure | |
941 | * @vlan: VLAN id to write to VLAN filter | |
942 | * @vind: VMDq output index that maps queue to VLAN id in VFTA | |
943 | * @vlan_on: boolean flag to turn on/off VLAN in VFTA | |
944 | * | |
945 | * Turn on/off specified VLAN in the VLAN filter table. | |
946 | **/ | |
e855aac8 HE |
947 | static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
948 | bool vlan_on) | |
c44ade9e JB |
949 | { |
950 | u32 regindex; | |
951 | u32 bitindex; | |
952 | u32 bits; | |
953 | u32 vftabyte; | |
954 | ||
955 | if (vlan > 4095) | |
956 | return IXGBE_ERR_PARAM; | |
957 | ||
958 | /* Determine 32-bit word position in array */ | |
959 | regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ | |
960 | ||
961 | /* Determine the location of the (VMD) queue index */ | |
962 | vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ | |
963 | bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ | |
964 | ||
965 | /* Set the nibble for VMD queue index */ | |
966 | bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); | |
967 | bits &= (~(0x0F << bitindex)); | |
968 | bits |= (vind << bitindex); | |
969 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); | |
970 | ||
971 | /* Determine the location of the bit for this VLAN id */ | |
972 | bitindex = vlan & 0x1F; /* lower five bits */ | |
973 | ||
974 | bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); | |
975 | if (vlan_on) | |
976 | /* Turn on this VLAN id */ | |
977 | bits |= (1 << bitindex); | |
978 | else | |
979 | /* Turn off this VLAN id */ | |
980 | bits &= ~(1 << bitindex); | |
981 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
986 | /** | |
987 | * ixgbe_clear_vfta_82598 - Clear VLAN filter table | |
988 | * @hw: pointer to hardware structure | |
989 | * | |
990 | * Clears the VLAN filer table, and the VMDq index associated with the filter | |
991 | **/ | |
992 | static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) | |
993 | { | |
994 | u32 offset; | |
995 | u32 vlanbyte; | |
996 | ||
997 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
998 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); | |
999 | ||
1000 | for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) | |
1001 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
1002 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), | |
b4617240 | 1003 | 0); |
c44ade9e JB |
1004 | |
1005 | return 0; | |
1006 | } | |
1007 | ||
c44ade9e JB |
1008 | /** |
1009 | * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register | |
1010 | * @hw: pointer to hardware structure | |
1011 | * @reg: analog register to read | |
1012 | * @val: read value | |
1013 | * | |
1014 | * Performs read operation to Atlas analog register specified. | |
1015 | **/ | |
e855aac8 | 1016 | static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) |
c44ade9e JB |
1017 | { |
1018 | u32 atlas_ctl; | |
1019 | ||
1020 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, | |
1021 | IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); | |
1022 | IXGBE_WRITE_FLUSH(hw); | |
1023 | udelay(10); | |
1024 | atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | |
1025 | *val = (u8)atlas_ctl; | |
1026 | ||
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | /** | |
1031 | * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register | |
1032 | * @hw: pointer to hardware structure | |
1033 | * @reg: atlas register to write | |
1034 | * @val: value to write | |
1035 | * | |
1036 | * Performs write operation to Atlas analog register specified. | |
1037 | **/ | |
e855aac8 | 1038 | static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) |
c44ade9e JB |
1039 | { |
1040 | u32 atlas_ctl; | |
1041 | ||
1042 | atlas_ctl = (reg << 8) | val; | |
1043 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); | |
1044 | IXGBE_WRITE_FLUSH(hw); | |
1045 | udelay(10); | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
c4900be0 | 1050 | /** |
8c7bea32 | 1051 | * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. |
c4900be0 DS |
1052 | * @hw: pointer to hardware structure |
1053 | * @byte_offset: EEPROM byte offset to read | |
1054 | * @eeprom_data: value read | |
1055 | * | |
8c7bea32 | 1056 | * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. |
c4900be0 | 1057 | **/ |
e855aac8 HE |
1058 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
1059 | u8 *eeprom_data) | |
c4900be0 DS |
1060 | { |
1061 | s32 status = 0; | |
1062 | u16 sfp_addr = 0; | |
1063 | u16 sfp_data = 0; | |
1064 | u16 sfp_stat = 0; | |
1065 | u32 i; | |
1066 | ||
1067 | if (hw->phy.type == ixgbe_phy_nl) { | |
1068 | /* | |
1069 | * phy SDA/SCL registers are at addresses 0xC30A to | |
1070 | * 0xC30D. These registers are used to talk to the SFP+ | |
1071 | * module's EEPROM through the SDA/SCL (I2C) interface. | |
1072 | */ | |
1073 | sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; | |
1074 | sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); | |
1075 | hw->phy.ops.write_reg(hw, | |
1076 | IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, | |
6b73e10d | 1077 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
1078 | sfp_addr); |
1079 | ||
1080 | /* Poll status */ | |
1081 | for (i = 0; i < 100; i++) { | |
1082 | hw->phy.ops.read_reg(hw, | |
1083 | IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, | |
6b73e10d | 1084 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
1085 | &sfp_stat); |
1086 | sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; | |
1087 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) | |
1088 | break; | |
032b4325 | 1089 | usleep_range(10000, 20000); |
c4900be0 DS |
1090 | } |
1091 | ||
1092 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { | |
1093 | hw_dbg(hw, "EEPROM read did not pass.\n"); | |
1094 | status = IXGBE_ERR_SFP_NOT_PRESENT; | |
1095 | goto out; | |
1096 | } | |
1097 | ||
1098 | /* Read data */ | |
1099 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, | |
6b73e10d | 1100 | MDIO_MMD_PMAPMD, &sfp_data); |
c4900be0 DS |
1101 | |
1102 | *eeprom_data = (u8)(sfp_data >> 8); | |
1103 | } else { | |
1104 | status = IXGBE_ERR_PHY; | |
1105 | goto out; | |
1106 | } | |
1107 | ||
1108 | out: | |
1109 | return status; | |
1110 | } | |
1111 | ||
c44ade9e JB |
1112 | /** |
1113 | * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type | |
1114 | * @hw: pointer to hardware structure | |
1115 | * | |
1116 | * Determines physical layer capabilities of the current configuration. | |
1117 | **/ | |
11afc1b1 | 1118 | static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) |
c44ade9e | 1119 | { |
11afc1b1 | 1120 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
04193058 PWJ |
1121 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
1122 | u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; | |
1123 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; | |
1124 | u16 ext_ability = 0; | |
1125 | ||
1126 | hw->phy.ops.identify(hw); | |
1127 | ||
1128 | /* Copper PHY must be checked before AUTOC LMS to determine correct | |
1129 | * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ | |
037c6d0a ET |
1130 | switch (hw->phy.type) { |
1131 | case ixgbe_phy_tn: | |
1132 | case ixgbe_phy_aq: | |
1133 | case ixgbe_phy_cu_unknown: | |
1134 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, | |
1135 | MDIO_MMD_PMAPMD, &ext_ability); | |
6b73e10d | 1136 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) |
04193058 | 1137 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
6b73e10d | 1138 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
04193058 | 1139 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
6b73e10d | 1140 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
04193058 PWJ |
1141 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
1142 | goto out; | |
037c6d0a ET |
1143 | default: |
1144 | break; | |
04193058 | 1145 | } |
c44ade9e | 1146 | |
04193058 PWJ |
1147 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
1148 | case IXGBE_AUTOC_LMS_1G_AN: | |
1149 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: | |
1150 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) | |
1151 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1152 | else | |
1153 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; | |
c4900be0 | 1154 | break; |
04193058 PWJ |
1155 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
1156 | if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) | |
1157 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; | |
1158 | else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) | |
1159 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
1160 | else /* XAUI */ | |
1161 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
c44ade9e | 1162 | break; |
04193058 PWJ |
1163 | case IXGBE_AUTOC_LMS_KX4_AN: |
1164 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
1165 | if (autoc & IXGBE_AUTOC_KX_SUPP) | |
1166 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1167 | if (autoc & IXGBE_AUTOC_KX4_SUPP) | |
1168 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
c44ade9e | 1169 | break; |
04193058 | 1170 | default: |
0befdb3e | 1171 | break; |
04193058 PWJ |
1172 | } |
1173 | ||
1174 | if (hw->phy.type == ixgbe_phy_nl) { | |
c4900be0 DS |
1175 | hw->phy.ops.identify_sfp(hw); |
1176 | ||
1177 | switch (hw->phy.sfp_type) { | |
1178 | case ixgbe_sfp_type_da_cu: | |
1179 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1180 | break; | |
1181 | case ixgbe_sfp_type_sr: | |
1182 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1183 | break; | |
1184 | case ixgbe_sfp_type_lr: | |
1185 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1186 | break; | |
1187 | default: | |
1188 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
1189 | break; | |
1190 | } | |
04193058 | 1191 | } |
c44ade9e | 1192 | |
04193058 PWJ |
1193 | switch (hw->device_id) { |
1194 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: | |
1195 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1196 | break; | |
1197 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: | |
1198 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
1199 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
1200 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1201 | break; | |
1202 | case IXGBE_DEV_ID_82598EB_XF_LR: | |
1203 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1204 | break; | |
c44ade9e | 1205 | default: |
c44ade9e JB |
1206 | break; |
1207 | } | |
1208 | ||
04193058 | 1209 | out: |
c44ade9e JB |
1210 | return physical_layer; |
1211 | } | |
1212 | ||
c9130180 ET |
1213 | /** |
1214 | * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple | |
1215 | * port devices. | |
1216 | * @hw: pointer to the HW structure | |
1217 | * | |
1218 | * Calls common function and corrects issue with some single port devices | |
1219 | * that enable LAN1 but not LAN0. | |
1220 | **/ | |
1221 | static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) | |
1222 | { | |
1223 | struct ixgbe_bus_info *bus = &hw->bus; | |
1224 | u16 pci_gen = 0; | |
1225 | u16 pci_ctrl2 = 0; | |
1226 | ||
1227 | ixgbe_set_lan_id_multi_port_pcie(hw); | |
1228 | ||
1229 | /* check if LAN0 is disabled */ | |
1230 | hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); | |
1231 | if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { | |
1232 | ||
1233 | hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); | |
1234 | ||
1235 | /* if LAN0 is completely disabled force function to 0 */ | |
1236 | if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && | |
1237 | !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && | |
1238 | !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { | |
1239 | ||
1240 | bus->func = 0; | |
1241 | } | |
1242 | } | |
1243 | } | |
1244 | ||
80605c65 JF |
1245 | /** |
1246 | * ixgbe_set_rxpba_82598 - Configure packet buffers | |
1247 | * @hw: pointer to hardware structure | |
1248 | * @dcb_config: pointer to ixgbe_dcb_config structure | |
1249 | * | |
1250 | * Configure packet buffers. | |
1251 | */ | |
1252 | static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom, | |
1253 | int strategy) | |
1254 | { | |
1255 | u32 rxpktsize = IXGBE_RXPBSIZE_64KB; | |
1256 | u8 i = 0; | |
1257 | ||
1258 | if (!num_pb) | |
1259 | return; | |
1260 | ||
1261 | /* Setup Rx packet buffer sizes */ | |
1262 | switch (strategy) { | |
1263 | case PBA_STRATEGY_WEIGHTED: | |
1264 | /* Setup the first four at 80KB */ | |
1265 | rxpktsize = IXGBE_RXPBSIZE_80KB; | |
1266 | for (; i < 4; i++) | |
1267 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); | |
1268 | /* Setup the last four at 48KB...don't re-init i */ | |
1269 | rxpktsize = IXGBE_RXPBSIZE_48KB; | |
1270 | /* Fall Through */ | |
1271 | case PBA_STRATEGY_EQUAL: | |
1272 | default: | |
1273 | /* Divide the remaining Rx packet buffer evenly among the TCs */ | |
1274 | for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) | |
1275 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); | |
1276 | break; | |
1277 | } | |
1278 | ||
1279 | /* Setup Tx packet buffer sizes */ | |
1280 | for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) | |
1281 | IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); | |
1282 | ||
1283 | return; | |
1284 | } | |
1285 | ||
9a799d71 | 1286 | static struct ixgbe_mac_operations mac_ops_82598 = { |
c44ade9e JB |
1287 | .init_hw = &ixgbe_init_hw_generic, |
1288 | .reset_hw = &ixgbe_reset_hw_82598, | |
202ff1ec | 1289 | .start_hw = &ixgbe_start_hw_82598, |
c44ade9e | 1290 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
9a799d71 | 1291 | .get_media_type = &ixgbe_get_media_type_82598, |
c44ade9e | 1292 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, |
11afc1b1 | 1293 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, |
c44ade9e JB |
1294 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
1295 | .stop_adapter = &ixgbe_stop_adapter_generic, | |
11afc1b1 | 1296 | .get_bus_info = &ixgbe_get_bus_info_generic, |
c9130180 | 1297 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598, |
c44ade9e JB |
1298 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, |
1299 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, | |
3957d63d | 1300 | .setup_link = &ixgbe_setup_mac_link_82598, |
80605c65 | 1301 | .set_rxpba = &ixgbe_set_rxpba_82598, |
c44ade9e JB |
1302 | .check_link = &ixgbe_check_mac_link_82598, |
1303 | .get_link_capabilities = &ixgbe_get_link_capabilities_82598, | |
1304 | .led_on = &ixgbe_led_on_generic, | |
1305 | .led_off = &ixgbe_led_off_generic, | |
87c12017 PW |
1306 | .blink_led_start = &ixgbe_blink_led_start_generic, |
1307 | .blink_led_stop = &ixgbe_blink_led_stop_generic, | |
c44ade9e JB |
1308 | .set_rar = &ixgbe_set_rar_generic, |
1309 | .clear_rar = &ixgbe_clear_rar_generic, | |
1310 | .set_vmdq = &ixgbe_set_vmdq_82598, | |
1311 | .clear_vmdq = &ixgbe_clear_vmdq_82598, | |
1312 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, | |
c44ade9e JB |
1313 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, |
1314 | .enable_mc = &ixgbe_enable_mc_generic, | |
1315 | .disable_mc = &ixgbe_disable_mc_generic, | |
1316 | .clear_vfta = &ixgbe_clear_vfta_82598, | |
1317 | .set_vfta = &ixgbe_set_vfta_82598, | |
620fa036 | 1318 | .fc_enable = &ixgbe_fc_enable_82598, |
9612de92 | 1319 | .set_fw_drv_ver = NULL, |
5e655105 DS |
1320 | .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, |
1321 | .release_swfw_sync = &ixgbe_release_swfw_sync, | |
c44ade9e JB |
1322 | }; |
1323 | ||
1324 | static struct ixgbe_eeprom_operations eeprom_ops_82598 = { | |
1325 | .init_params = &ixgbe_init_eeprom_params_generic, | |
21ce849b | 1326 | .read = &ixgbe_read_eerd_generic, |
68c7005d | 1327 | .read_buffer = &ixgbe_read_eerd_buffer_generic, |
a391f1d5 | 1328 | .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, |
c44ade9e JB |
1329 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, |
1330 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, | |
1331 | }; | |
1332 | ||
1333 | static struct ixgbe_phy_operations phy_ops_82598 = { | |
1334 | .identify = &ixgbe_identify_phy_generic, | |
c4900be0 | 1335 | .identify_sfp = &ixgbe_identify_sfp_module_generic, |
04f165ef | 1336 | .init = &ixgbe_init_phy_ops_82598, |
c44ade9e JB |
1337 | .reset = &ixgbe_reset_phy_generic, |
1338 | .read_reg = &ixgbe_read_phy_reg_generic, | |
1339 | .write_reg = &ixgbe_write_phy_reg_generic, | |
1340 | .setup_link = &ixgbe_setup_phy_link_generic, | |
1341 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
c4900be0 | 1342 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, |
119fc60a | 1343 | .check_overtemp = &ixgbe_tn_check_overtemp, |
9a799d71 AK |
1344 | }; |
1345 | ||
3957d63d | 1346 | struct ixgbe_info ixgbe_82598_info = { |
9a799d71 AK |
1347 | .mac = ixgbe_mac_82598EB, |
1348 | .get_invariants = &ixgbe_get_invariants_82598, | |
1349 | .mac_ops = &mac_ops_82598, | |
c44ade9e JB |
1350 | .eeprom_ops = &eeprom_ops_82598, |
1351 | .phy_ops = &phy_ops_82598, | |
9a799d71 AK |
1352 | }; |
1353 |