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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
14438464 | 4 | Copyright(c) 1999 - 2014 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
9c8eb720 | 32 | #include "ixgbe.h" |
9a799d71 AK |
33 | #include "ixgbe_phy.h" |
34 | ||
35 | #define IXGBE_82598_MAX_TX_QUEUES 32 | |
36 | #define IXGBE_82598_MAX_RX_QUEUES 64 | |
37 | #define IXGBE_82598_RAR_ENTRIES 16 | |
2c5645cf CL |
38 | #define IXGBE_82598_MC_TBL_SIZE 128 |
39 | #define IXGBE_82598_VFT_TBL_SIZE 128 | |
e09ad236 | 40 | #define IXGBE_82598_RX_PB_SIZE 512 |
9a799d71 | 41 | |
8620a103 | 42 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
21ce849b | 43 | ixgbe_link_speed speed, |
21ce849b | 44 | bool autoneg_wait_to_complete); |
c4900be0 DS |
45 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
46 | u8 *eeprom_data); | |
9a799d71 | 47 | |
202ff1ec MC |
48 | /** |
49 | * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout | |
50 | * @hw: pointer to the HW structure | |
51 | * | |
52 | * The defaults for 82598 should be in the range of 50us to 50ms, | |
53 | * however the hardware default for these parts is 500us to 1ms which is less | |
54 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
55 | * increase the value to either 10ms to 250ms for capability version 1 config, | |
56 | * or 16ms to 55ms for version 2. | |
57 | **/ | |
7b25cdba | 58 | static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) |
202ff1ec MC |
59 | { |
60 | struct ixgbe_adapter *adapter = hw->back; | |
61 | u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); | |
62 | u16 pcie_devctl2; | |
63 | ||
14438464 MR |
64 | if (ixgbe_removed(hw->hw_addr)) |
65 | return; | |
66 | ||
202ff1ec MC |
67 | /* only take action if timeout value is defaulted to 0 */ |
68 | if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) | |
69 | goto out; | |
70 | ||
71 | /* | |
72 | * if capababilities version is type 1 we can write the | |
73 | * timeout of 10ms to 250ms through the GCR register | |
74 | */ | |
75 | if (!(gcr & IXGBE_GCR_CAP_VER2)) { | |
76 | gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; | |
77 | goto out; | |
78 | } | |
79 | ||
80 | /* | |
81 | * for version 2 capabilities we need to write the config space | |
82 | * directly in order to set the completion timeout value for | |
83 | * 16ms to 55ms | |
84 | */ | |
14438464 MR |
85 | pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); |
86 | if (ixgbe_removed(hw->hw_addr)) | |
87 | return; | |
202ff1ec MC |
88 | pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; |
89 | pci_write_config_word(adapter->pdev, | |
90 | IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); | |
91 | out: | |
92 | /* disable completion timeout resend */ | |
93 | gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; | |
94 | IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); | |
95 | } | |
96 | ||
9a799d71 | 97 | static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) |
04f165ef PW |
98 | { |
99 | struct ixgbe_mac_info *mac = &hw->mac; | |
100 | ||
101 | /* Call PHY identify routine to get the phy type */ | |
102 | ixgbe_identify_phy_generic(hw); | |
103 | ||
104 | mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; | |
105 | mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; | |
106 | mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; | |
6997d4d1 | 107 | mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE; |
04f165ef PW |
108 | mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; |
109 | mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; | |
71161302 | 110 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); |
04f165ef PW |
111 | |
112 | return 0; | |
113 | } | |
114 | ||
115 | /** | |
116 | * ixgbe_init_phy_ops_82598 - PHY/SFP specific init | |
117 | * @hw: pointer to hardware structure | |
118 | * | |
119 | * Initialize any function pointers that were not able to be | |
120 | * set during get_invariants because the PHY/SFP type was | |
121 | * not known. Perform the SFP init if necessary. | |
122 | * | |
123 | **/ | |
7b25cdba | 124 | static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) |
9a799d71 | 125 | { |
c44ade9e JB |
126 | struct ixgbe_mac_info *mac = &hw->mac; |
127 | struct ixgbe_phy_info *phy = &hw->phy; | |
c4900be0 DS |
128 | s32 ret_val = 0; |
129 | u16 list_offset, data_offset; | |
c44ade9e | 130 | |
04f165ef PW |
131 | /* Identify the PHY */ |
132 | phy->ops.identify(hw); | |
03cfa205 | 133 | |
04f165ef PW |
134 | /* Overwrite the link function pointers if copper PHY */ |
135 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { | |
136 | mac->ops.setup_link = &ixgbe_setup_copper_link_82598; | |
04f165ef | 137 | mac->ops.get_link_capabilities = |
a391f1d5 | 138 | &ixgbe_get_copper_link_capabilities_generic; |
04f165ef | 139 | } |
c44ade9e | 140 | |
04f165ef | 141 | switch (hw->phy.type) { |
0befdb3e | 142 | case ixgbe_phy_tn: |
9dda1736 | 143 | phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; |
0befdb3e JB |
144 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; |
145 | phy->ops.get_firmware_version = | |
146 | &ixgbe_get_phy_firmware_version_tnx; | |
147 | break; | |
c4900be0 DS |
148 | case ixgbe_phy_nl: |
149 | phy->ops.reset = &ixgbe_reset_phy_nl; | |
150 | ||
151 | /* Call SFP+ identify routine to get the SFP+ module type */ | |
152 | ret_val = phy->ops.identify_sfp(hw); | |
153 | if (ret_val != 0) | |
154 | goto out; | |
155 | else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { | |
156 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
157 | goto out; | |
158 | } | |
159 | ||
160 | /* Check to see if SFP+ module is supported */ | |
161 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, | |
04f165ef PW |
162 | &list_offset, |
163 | &data_offset); | |
c4900be0 DS |
164 | if (ret_val != 0) { |
165 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
166 | goto out; | |
167 | } | |
168 | break; | |
c44ade9e JB |
169 | default: |
170 | break; | |
171 | } | |
172 | ||
c4900be0 DS |
173 | out: |
174 | return ret_val; | |
9a799d71 AK |
175 | } |
176 | ||
202ff1ec MC |
177 | /** |
178 | * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx | |
179 | * @hw: pointer to hardware structure | |
180 | * | |
181 | * Starts the hardware using the generic start_hw function. | |
3d5c5207 ET |
182 | * Disables relaxed ordering Then set pcie completion timeout |
183 | * | |
202ff1ec | 184 | **/ |
7b25cdba | 185 | static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) |
202ff1ec | 186 | { |
3d5c5207 ET |
187 | u32 regval; |
188 | u32 i; | |
202ff1ec MC |
189 | s32 ret_val = 0; |
190 | ||
191 | ret_val = ixgbe_start_hw_generic(hw); | |
192 | ||
3d5c5207 ET |
193 | /* Disable relaxed ordering */ |
194 | for (i = 0; ((i < hw->mac.max_tx_queues) && | |
195 | (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { | |
196 | regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); | |
bdda1a61 | 197 | regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; |
3d5c5207 ET |
198 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); |
199 | } | |
200 | ||
201 | for (i = 0; ((i < hw->mac.max_rx_queues) && | |
202 | (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { | |
203 | regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
bdda1a61 AD |
204 | regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | |
205 | IXGBE_DCA_RXCTRL_HEAD_WRO_EN); | |
3d5c5207 ET |
206 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); |
207 | } | |
208 | ||
202ff1ec MC |
209 | /* set the completion timeout for interface */ |
210 | if (ret_val == 0) | |
211 | ixgbe_set_pcie_completion_timeout(hw); | |
212 | ||
213 | return ret_val; | |
214 | } | |
215 | ||
9a799d71 | 216 | /** |
c44ade9e | 217 | * ixgbe_get_link_capabilities_82598 - Determines link capabilities |
9a799d71 AK |
218 | * @hw: pointer to hardware structure |
219 | * @speed: pointer to link speed | |
220 | * @autoneg: boolean auto-negotiation value | |
221 | * | |
c44ade9e | 222 | * Determines the link capabilities by reading the AUTOC register. |
9a799d71 | 223 | **/ |
c44ade9e | 224 | static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, |
b4617240 PW |
225 | ixgbe_link_speed *speed, |
226 | bool *autoneg) | |
9a799d71 AK |
227 | { |
228 | s32 status = 0; | |
1eb99d5a | 229 | u32 autoc = 0; |
9a799d71 | 230 | |
3201d313 PWJ |
231 | /* |
232 | * Determine link capabilities based on the stored value of AUTOC, | |
1eb99d5a PW |
233 | * which represents EEPROM defaults. If AUTOC value has not been |
234 | * stored, use the current register value. | |
3201d313 | 235 | */ |
1eb99d5a PW |
236 | if (hw->mac.orig_link_settings_stored) |
237 | autoc = hw->mac.orig_autoc; | |
238 | else | |
239 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
240 | ||
241 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { | |
9a799d71 AK |
242 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
243 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
244 | *autoneg = false; | |
245 | break; | |
246 | ||
247 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: | |
248 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
249 | *autoneg = false; | |
250 | break; | |
251 | ||
252 | case IXGBE_AUTOC_LMS_1G_AN: | |
253 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
254 | *autoneg = true; | |
255 | break; | |
256 | ||
257 | case IXGBE_AUTOC_LMS_KX4_AN: | |
258 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
259 | *speed = IXGBE_LINK_SPEED_UNKNOWN; | |
1eb99d5a | 260 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
9a799d71 | 261 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 262 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
9a799d71 AK |
263 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
264 | *autoneg = true; | |
265 | break; | |
266 | ||
267 | default: | |
268 | status = IXGBE_ERR_LINK_SETUP; | |
269 | break; | |
270 | } | |
271 | ||
272 | return status; | |
273 | } | |
274 | ||
9a799d71 AK |
275 | /** |
276 | * ixgbe_get_media_type_82598 - Determines media type | |
277 | * @hw: pointer to hardware structure | |
278 | * | |
279 | * Returns the media type (fiber, copper, backplane) | |
280 | **/ | |
281 | static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) | |
282 | { | |
283 | enum ixgbe_media_type media_type; | |
284 | ||
037c6d0a ET |
285 | /* Detect if there is a copper PHY attached. */ |
286 | switch (hw->phy.type) { | |
287 | case ixgbe_phy_cu_unknown: | |
288 | case ixgbe_phy_tn: | |
037c6d0a ET |
289 | media_type = ixgbe_media_type_copper; |
290 | goto out; | |
291 | default: | |
292 | break; | |
293 | } | |
294 | ||
9a799d71 AK |
295 | /* Media type for I82598 is based on device ID */ |
296 | switch (hw->device_id) { | |
1e336d0f | 297 | case IXGBE_DEV_ID_82598: |
2f21bdd3 | 298 | case IXGBE_DEV_ID_82598_BX: |
037c6d0a | 299 | /* Default device ID is mezzanine card KX/KX4 */ |
1e336d0f DS |
300 | media_type = ixgbe_media_type_backplane; |
301 | break; | |
9a799d71 AK |
302 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: |
303 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
c4900be0 DS |
304 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: |
305 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
b95f5fcb | 306 | case IXGBE_DEV_ID_82598EB_XF_LR: |
c4900be0 | 307 | case IXGBE_DEV_ID_82598EB_SFP_LOM: |
9a799d71 AK |
308 | media_type = ixgbe_media_type_fiber; |
309 | break; | |
6b1be199 PWJ |
310 | case IXGBE_DEV_ID_82598EB_CX4: |
311 | case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: | |
312 | media_type = ixgbe_media_type_cx4; | |
313 | break; | |
0befdb3e | 314 | case IXGBE_DEV_ID_82598AT: |
3845bec0 | 315 | case IXGBE_DEV_ID_82598AT2: |
0befdb3e JB |
316 | media_type = ixgbe_media_type_copper; |
317 | break; | |
9a799d71 AK |
318 | default: |
319 | media_type = ixgbe_media_type_unknown; | |
320 | break; | |
321 | } | |
037c6d0a | 322 | out: |
9a799d71 AK |
323 | return media_type; |
324 | } | |
325 | ||
c44ade9e | 326 | /** |
0ecc061d | 327 | * ixgbe_fc_enable_82598 - Enable flow control |
c44ade9e | 328 | * @hw: pointer to hardware structure |
c44ade9e | 329 | * |
0ecc061d | 330 | * Enable flow control according to the current settings. |
c44ade9e | 331 | **/ |
041441d0 | 332 | static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) |
c44ade9e | 333 | { |
0ecc061d PWJ |
334 | s32 ret_val = 0; |
335 | u32 fctrl_reg; | |
c44ade9e | 336 | u32 rmcs_reg; |
0ecc061d | 337 | u32 reg; |
041441d0 | 338 | u32 fcrtl, fcrth; |
a626e847 | 339 | u32 link_speed = 0; |
041441d0 | 340 | int i; |
a626e847 | 341 | bool link_up; |
c44ade9e | 342 | |
041441d0 AD |
343 | /* |
344 | * Validate the water mark configuration for packet buffer 0. Zero | |
345 | * water marks indicate that the packet buffer was not configured | |
346 | * and the watermarks for packet buffer 0 should always be configured. | |
347 | */ | |
348 | if (!hw->fc.low_water || | |
349 | !hw->fc.high_water[0] || | |
350 | !hw->fc.pause_time) { | |
351 | hw_dbg(hw, "Invalid water mark configuration\n"); | |
352 | ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; | |
620fa036 | 353 | goto out; |
041441d0 | 354 | } |
620fa036 | 355 | |
a626e847 DS |
356 | /* |
357 | * On 82598 having Rx FC on causes resets while doing 1G | |
358 | * so if it's on turn it off once we know link_speed. For | |
359 | * more details see 82598 Specification update. | |
360 | */ | |
361 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
362 | if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { | |
363 | switch (hw->fc.requested_mode) { | |
364 | case ixgbe_fc_full: | |
365 | hw->fc.requested_mode = ixgbe_fc_tx_pause; | |
366 | break; | |
367 | case ixgbe_fc_rx_pause: | |
368 | hw->fc.requested_mode = ixgbe_fc_none; | |
369 | break; | |
370 | default: | |
371 | /* no change */ | |
372 | break; | |
373 | } | |
374 | } | |
375 | ||
620fa036 | 376 | /* Negotiate the fc mode to use */ |
786e9a5f | 377 | ixgbe_fc_autoneg(hw); |
620fa036 MC |
378 | |
379 | /* Disable any previous flow control settings */ | |
0ecc061d PWJ |
380 | fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
381 | fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); | |
c44ade9e JB |
382 | |
383 | rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
384 | rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); | |
385 | ||
386 | /* | |
0ecc061d | 387 | * The possible values of fc.current_mode are: |
c44ade9e | 388 | * 0: Flow control is completely disabled |
0ecc061d PWJ |
389 | * 1: Rx flow control is enabled (we can receive pause frames, |
390 | * but not send pause frames). | |
620fa036 | 391 | * 2: Tx flow control is enabled (we can send pause frames but |
0ecc061d | 392 | * we do not support receiving pause frames). |
c44ade9e | 393 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
0b0c2b31 | 394 | * other: Invalid. |
c44ade9e | 395 | */ |
0ecc061d | 396 | switch (hw->fc.current_mode) { |
c44ade9e | 397 | case ixgbe_fc_none: |
620fa036 MC |
398 | /* |
399 | * Flow control is disabled by software override or autoneg. | |
400 | * The code below will actually disable it in the HW. | |
401 | */ | |
c44ade9e JB |
402 | break; |
403 | case ixgbe_fc_rx_pause: | |
404 | /* | |
0ecc061d PWJ |
405 | * Rx Flow control is enabled and Tx Flow control is |
406 | * disabled by software override. Since there really | |
407 | * isn't a way to advertise that we are capable of RX | |
408 | * Pause ONLY, we will advertise that we support both | |
409 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
410 | * disable the adapter's ability to send PAUSE frames. | |
c44ade9e | 411 | */ |
0ecc061d | 412 | fctrl_reg |= IXGBE_FCTRL_RFCE; |
c44ade9e JB |
413 | break; |
414 | case ixgbe_fc_tx_pause: | |
415 | /* | |
0ecc061d PWJ |
416 | * Tx Flow control is enabled, and Rx Flow control is |
417 | * disabled by software override. | |
c44ade9e JB |
418 | */ |
419 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | |
420 | break; | |
421 | case ixgbe_fc_full: | |
0ecc061d PWJ |
422 | /* Flow control (both Rx and Tx) is enabled by SW override. */ |
423 | fctrl_reg |= IXGBE_FCTRL_RFCE; | |
c44ade9e JB |
424 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; |
425 | break; | |
426 | default: | |
c44ade9e | 427 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
539e5f02 | 428 | ret_val = IXGBE_ERR_CONFIG; |
0ecc061d | 429 | goto out; |
c44ade9e JB |
430 | break; |
431 | } | |
432 | ||
620fa036 | 433 | /* Set 802.3x based flow control settings. */ |
2132d381 | 434 | fctrl_reg |= IXGBE_FCTRL_DPF; |
0ecc061d | 435 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); |
c44ade9e JB |
436 | IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); |
437 | ||
041441d0 | 438 | fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE; |
16b61beb | 439 | |
041441d0 AD |
440 | /* Set up and enable Rx high/low water mark thresholds, enable XON. */ |
441 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
442 | if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && | |
443 | hw->fc.high_water[i]) { | |
444 | fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; | |
445 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); | |
446 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); | |
447 | } else { | |
448 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); | |
449 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); | |
450 | } | |
0ecc061d | 451 | |
c44ade9e JB |
452 | } |
453 | ||
0ecc061d | 454 | /* Configure pause time (2 TCs per register) */ |
041441d0 AD |
455 | reg = hw->fc.pause_time * 0x00010001; |
456 | for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) | |
457 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); | |
0ecc061d | 458 | |
041441d0 AD |
459 | /* Configure flow control refresh threshold value */ |
460 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); | |
c44ade9e | 461 | |
0ecc061d PWJ |
462 | out: |
463 | return ret_val; | |
464 | } | |
465 | ||
9a799d71 | 466 | /** |
8620a103 | 467 | * ixgbe_start_mac_link_82598 - Configures MAC link settings |
9a799d71 AK |
468 | * @hw: pointer to hardware structure |
469 | * | |
470 | * Configures link settings based on values in the ixgbe_hw struct. | |
471 | * Restarts the link. Performs autonegotiation if needed. | |
472 | **/ | |
8620a103 MC |
473 | static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, |
474 | bool autoneg_wait_to_complete) | |
9a799d71 AK |
475 | { |
476 | u32 autoc_reg; | |
477 | u32 links_reg; | |
478 | u32 i; | |
479 | s32 status = 0; | |
480 | ||
9a799d71 | 481 | /* Restart link */ |
3201d313 | 482 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
9a799d71 AK |
483 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
484 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); | |
485 | ||
486 | /* Only poll for autoneg to complete if specified to do so */ | |
8620a103 | 487 | if (autoneg_wait_to_complete) { |
3201d313 PWJ |
488 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
489 | IXGBE_AUTOC_LMS_KX4_AN || | |
490 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == | |
491 | IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
9a799d71 AK |
492 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
493 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { | |
494 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
495 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) | |
496 | break; | |
497 | msleep(100); | |
498 | } | |
499 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { | |
500 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; | |
c44ade9e | 501 | hw_dbg(hw, "Autonegotiation did not complete.\n"); |
9a799d71 AK |
502 | } |
503 | } | |
504 | } | |
505 | ||
9a799d71 AK |
506 | /* Add delay to filter out noises during initial link setup */ |
507 | msleep(50); | |
508 | ||
509 | return status; | |
510 | } | |
511 | ||
734e979f MC |
512 | /** |
513 | * ixgbe_validate_link_ready - Function looks for phy link | |
514 | * @hw: pointer to hardware structure | |
515 | * | |
516 | * Function indicates success when phy link is available. If phy is not ready | |
517 | * within 5 seconds of MAC indicating link, the function returns error. | |
518 | **/ | |
519 | static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) | |
520 | { | |
521 | u32 timeout; | |
522 | u16 an_reg; | |
523 | ||
524 | if (hw->device_id != IXGBE_DEV_ID_82598AT2) | |
525 | return 0; | |
526 | ||
527 | for (timeout = 0; | |
528 | timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { | |
529 | hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); | |
530 | ||
531 | if ((an_reg & MDIO_AN_STAT1_COMPLETE) && | |
532 | (an_reg & MDIO_STAT1_LSTATUS)) | |
533 | break; | |
534 | ||
535 | msleep(100); | |
536 | } | |
537 | ||
538 | if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { | |
539 | hw_dbg(hw, "Link was indicated but link is down\n"); | |
540 | return IXGBE_ERR_LINK_SETUP; | |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
9a799d71 AK |
546 | /** |
547 | * ixgbe_check_mac_link_82598 - Get link/speed status | |
548 | * @hw: pointer to hardware structure | |
549 | * @speed: pointer to link speed | |
550 | * @link_up: true is link is up, false otherwise | |
cf8280ee | 551 | * @link_up_wait_to_complete: bool used to wait for link up or not |
9a799d71 AK |
552 | * |
553 | * Reads the links register to determine if link is up and the current speed | |
554 | **/ | |
b4617240 PW |
555 | static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, |
556 | ixgbe_link_speed *speed, bool *link_up, | |
557 | bool link_up_wait_to_complete) | |
9a799d71 AK |
558 | { |
559 | u32 links_reg; | |
cf8280ee | 560 | u32 i; |
c4900be0 DS |
561 | u16 link_reg, adapt_comp_reg; |
562 | ||
563 | /* | |
564 | * SERDES PHY requires us to read link status from register 0xC79F. | |
565 | * Bit 0 set indicates link is up/ready; clear indicates link down. | |
566 | * 0xC00C is read to check that the XAUI lanes are active. Bit 0 | |
567 | * clear indicates active; set indicates inactive. | |
568 | */ | |
569 | if (hw->phy.type == ixgbe_phy_nl) { | |
6b73e10d BH |
570 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); |
571 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); | |
572 | hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, | |
c4900be0 DS |
573 | &adapt_comp_reg); |
574 | if (link_up_wait_to_complete) { | |
575 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
576 | if ((link_reg & 1) && | |
577 | ((adapt_comp_reg & 1) == 0)) { | |
578 | *link_up = true; | |
579 | break; | |
580 | } else { | |
581 | *link_up = false; | |
582 | } | |
583 | msleep(100); | |
584 | hw->phy.ops.read_reg(hw, 0xC79F, | |
6b73e10d | 585 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
586 | &link_reg); |
587 | hw->phy.ops.read_reg(hw, 0xC00C, | |
6b73e10d | 588 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
589 | &adapt_comp_reg); |
590 | } | |
591 | } else { | |
592 | if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) | |
593 | *link_up = true; | |
594 | else | |
595 | *link_up = false; | |
596 | } | |
597 | ||
23677ce3 | 598 | if (!*link_up) |
c4900be0 DS |
599 | goto out; |
600 | } | |
9a799d71 AK |
601 | |
602 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
cf8280ee JB |
603 | if (link_up_wait_to_complete) { |
604 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
605 | if (links_reg & IXGBE_LINKS_UP) { | |
606 | *link_up = true; | |
607 | break; | |
608 | } else { | |
609 | *link_up = false; | |
610 | } | |
611 | msleep(100); | |
612 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
613 | } | |
614 | } else { | |
615 | if (links_reg & IXGBE_LINKS_UP) | |
616 | *link_up = true; | |
617 | else | |
618 | *link_up = false; | |
619 | } | |
9a799d71 AK |
620 | |
621 | if (links_reg & IXGBE_LINKS_SPEED) | |
622 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
623 | else | |
624 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
625 | ||
23677ce3 | 626 | if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up && |
734e979f MC |
627 | (ixgbe_validate_link_ready(hw) != 0)) |
628 | *link_up = false; | |
629 | ||
c4900be0 | 630 | out: |
9a799d71 AK |
631 | return 0; |
632 | } | |
633 | ||
634 | /** | |
8620a103 | 635 | * ixgbe_setup_mac_link_82598 - Set MAC link speed |
9a799d71 AK |
636 | * @hw: pointer to hardware structure |
637 | * @speed: new link speed | |
037c6d0a | 638 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
9a799d71 AK |
639 | * |
640 | * Set the link speed in the AUTOC register and restarts link. | |
641 | **/ | |
8620a103 | 642 | static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, |
fd0326f2 JH |
643 | ixgbe_link_speed speed, |
644 | bool autoneg_wait_to_complete) | |
9a799d71 | 645 | { |
fd0326f2 | 646 | bool autoneg = false; |
3201d313 PWJ |
647 | s32 status = 0; |
648 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; | |
649 | u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
650 | u32 autoc = curr_autoc; | |
651 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; | |
9a799d71 | 652 | |
3201d313 PWJ |
653 | /* Check to see if speed passed in is supported. */ |
654 | ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); | |
655 | speed &= link_capabilities; | |
656 | ||
657 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) | |
9a799d71 | 658 | status = IXGBE_ERR_LINK_SETUP; |
3201d313 PWJ |
659 | |
660 | /* Set KX4/KX support according to speed requested */ | |
661 | else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || | |
662 | link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
663 | autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; | |
664 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
665 | autoc |= IXGBE_AUTOC_KX4_SUPP; | |
666 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
667 | autoc |= IXGBE_AUTOC_KX_SUPP; | |
668 | if (autoc != curr_autoc) | |
669 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); | |
9a799d71 AK |
670 | } |
671 | ||
672 | if (status == 0) { | |
9a799d71 AK |
673 | /* |
674 | * Setup and restart the link based on the new values in | |
675 | * ixgbe_hw This will write the AUTOC register based on the new | |
676 | * stored values | |
677 | */ | |
037c6d0a ET |
678 | status = ixgbe_start_mac_link_82598(hw, |
679 | autoneg_wait_to_complete); | |
9a799d71 AK |
680 | } |
681 | ||
682 | return status; | |
683 | } | |
684 | ||
685 | ||
686 | /** | |
8620a103 | 687 | * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field |
9a799d71 AK |
688 | * @hw: pointer to hardware structure |
689 | * @speed: new link speed | |
9a799d71 AK |
690 | * @autoneg_wait_to_complete: true if waiting is needed to complete |
691 | * | |
692 | * Sets the link speed in the AUTOC register in the MAC and restarts link. | |
693 | **/ | |
8620a103 | 694 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
b4617240 | 695 | ixgbe_link_speed speed, |
b4617240 | 696 | bool autoneg_wait_to_complete) |
9a799d71 | 697 | { |
c44ade9e | 698 | s32 status; |
9a799d71 AK |
699 | |
700 | /* Setup the PHY according to input speed */ | |
99b76642 | 701 | status = hw->phy.ops.setup_link_speed(hw, speed, |
b4617240 | 702 | autoneg_wait_to_complete); |
3957d63d | 703 | /* Set up MAC */ |
8620a103 | 704 | ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); |
9a799d71 AK |
705 | |
706 | return status; | |
707 | } | |
708 | ||
709 | /** | |
710 | * ixgbe_reset_hw_82598 - Performs hardware reset | |
711 | * @hw: pointer to hardware structure | |
712 | * | |
c44ade9e | 713 | * Resets the hardware by resetting the transmit and receive units, masks and |
9a799d71 AK |
714 | * clears all interrupts, performing a PHY reset, and performing a link (MAC) |
715 | * reset. | |
716 | **/ | |
717 | static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) | |
718 | { | |
719 | s32 status = 0; | |
8ca783ab | 720 | s32 phy_status = 0; |
9a799d71 AK |
721 | u32 ctrl; |
722 | u32 gheccr; | |
723 | u32 i; | |
724 | u32 autoc; | |
725 | u8 analog_val; | |
726 | ||
727 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
ff9d1a5a ET |
728 | status = hw->mac.ops.stop_adapter(hw); |
729 | if (status != 0) | |
730 | goto reset_hw_out; | |
9a799d71 AK |
731 | |
732 | /* | |
c44ade9e JB |
733 | * Power up the Atlas Tx lanes if they are currently powered down. |
734 | * Atlas Tx lanes are powered down for MAC loopback tests, but | |
9a799d71 AK |
735 | * they are not automatically restored on reset. |
736 | */ | |
c44ade9e | 737 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); |
9a799d71 | 738 | if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { |
c44ade9e JB |
739 | /* Enable Tx Atlas so packets can be transmitted again */ |
740 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, | |
741 | &analog_val); | |
9a799d71 | 742 | analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; |
c44ade9e JB |
743 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, |
744 | analog_val); | |
9a799d71 | 745 | |
c44ade9e JB |
746 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
747 | &analog_val); | |
9a799d71 | 748 | analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; |
c44ade9e JB |
749 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
750 | analog_val); | |
9a799d71 | 751 | |
c44ade9e JB |
752 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
753 | &analog_val); | |
9a799d71 | 754 | analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; |
c44ade9e JB |
755 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
756 | analog_val); | |
9a799d71 | 757 | |
c44ade9e JB |
758 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
759 | &analog_val); | |
9a799d71 | 760 | analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; |
c44ade9e JB |
761 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
762 | analog_val); | |
9a799d71 AK |
763 | } |
764 | ||
765 | /* Reset PHY */ | |
04f165ef PW |
766 | if (hw->phy.reset_disable == false) { |
767 | /* PHY ops must be identified and initialized prior to reset */ | |
768 | ||
769 | /* Init PHY and function pointers, perform SFP setup */ | |
8ca783ab DS |
770 | phy_status = hw->phy.ops.init(hw); |
771 | if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
04f165ef | 772 | goto reset_hw_out; |
ff9d1a5a ET |
773 | if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) |
774 | goto mac_reset_top; | |
8ca783ab | 775 | |
c44ade9e | 776 | hw->phy.ops.reset(hw); |
04f165ef | 777 | } |
9a799d71 | 778 | |
a4297dc2 | 779 | mac_reset_top: |
9a799d71 AK |
780 | /* |
781 | * Issue global reset to the MAC. This needs to be a SW reset. | |
782 | * If link reset is used, it might reset the MAC when mng is using it | |
783 | */ | |
8132b54e AD |
784 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; |
785 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
9a799d71 AK |
786 | IXGBE_WRITE_FLUSH(hw); |
787 | ||
788 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
789 | for (i = 0; i < 10; i++) { | |
790 | udelay(1); | |
791 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
792 | if (!(ctrl & IXGBE_CTRL_RST)) | |
793 | break; | |
794 | } | |
795 | if (ctrl & IXGBE_CTRL_RST) { | |
796 | status = IXGBE_ERR_RESET_FAILED; | |
797 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
798 | } | |
799 | ||
8132b54e AD |
800 | msleep(50); |
801 | ||
a4297dc2 ET |
802 | /* |
803 | * Double resets are required for recovery from certain error | |
804 | * conditions. Between resets, it is necessary to stall to allow time | |
8132b54e | 805 | * for any pending HW events to complete. |
a4297dc2 ET |
806 | */ |
807 | if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { | |
808 | hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; | |
a4297dc2 ET |
809 | goto mac_reset_top; |
810 | } | |
811 | ||
9a799d71 AK |
812 | gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); |
813 | gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); | |
814 | IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); | |
815 | ||
816 | /* | |
3201d313 PWJ |
817 | * Store the original AUTOC value if it has not been |
818 | * stored off yet. Otherwise restore the stored original | |
819 | * AUTOC value since the reset operation sets back to deaults. | |
9a799d71 AK |
820 | */ |
821 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
3201d313 PWJ |
822 | if (hw->mac.orig_link_settings_stored == false) { |
823 | hw->mac.orig_autoc = autoc; | |
824 | hw->mac.orig_link_settings_stored = true; | |
825 | } else if (autoc != hw->mac.orig_autoc) { | |
826 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); | |
9a799d71 AK |
827 | } |
828 | ||
278675d8 ET |
829 | /* Store the permanent mac address */ |
830 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); | |
831 | ||
aca6bee7 WJP |
832 | /* |
833 | * Store MAC address from RAR0, clear receive address registers, and | |
834 | * clear the multicast table | |
835 | */ | |
836 | hw->mac.ops.init_rx_addrs(hw); | |
837 | ||
04f165ef | 838 | reset_hw_out: |
8ca783ab DS |
839 | if (phy_status) |
840 | status = phy_status; | |
841 | ||
9a799d71 AK |
842 | return status; |
843 | } | |
844 | ||
c44ade9e JB |
845 | /** |
846 | * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address | |
847 | * @hw: pointer to hardware struct | |
848 | * @rar: receive address register index to associate with a VMDq index | |
849 | * @vmdq: VMDq set index | |
850 | **/ | |
e855aac8 | 851 | static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
c44ade9e JB |
852 | { |
853 | u32 rar_high; | |
c700f4e6 ET |
854 | u32 rar_entries = hw->mac.num_rar_entries; |
855 | ||
856 | /* Make sure we are using a valid rar index range */ | |
857 | if (rar >= rar_entries) { | |
858 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); | |
859 | return IXGBE_ERR_INVALID_ARGUMENT; | |
860 | } | |
c44ade9e JB |
861 | |
862 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
863 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
864 | rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); | |
865 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
866 | return 0; | |
867 | } | |
868 | ||
869 | /** | |
870 | * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address | |
871 | * @hw: pointer to hardware struct | |
872 | * @rar: receive address register index to associate with a VMDq index | |
873 | * @vmdq: VMDq clear index (not used in 82598, but elsewhere) | |
874 | **/ | |
875 | static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) | |
876 | { | |
877 | u32 rar_high; | |
878 | u32 rar_entries = hw->mac.num_rar_entries; | |
879 | ||
c700f4e6 ET |
880 | |
881 | /* Make sure we are using a valid rar index range */ | |
882 | if (rar >= rar_entries) { | |
c44ade9e | 883 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); |
c700f4e6 ET |
884 | return IXGBE_ERR_INVALID_ARGUMENT; |
885 | } | |
886 | ||
887 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
888 | if (rar_high & IXGBE_RAH_VIND_MASK) { | |
889 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
890 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
c44ade9e JB |
891 | } |
892 | ||
893 | return 0; | |
894 | } | |
895 | ||
896 | /** | |
897 | * ixgbe_set_vfta_82598 - Set VLAN filter table | |
898 | * @hw: pointer to hardware structure | |
899 | * @vlan: VLAN id to write to VLAN filter | |
900 | * @vind: VMDq output index that maps queue to VLAN id in VFTA | |
901 | * @vlan_on: boolean flag to turn on/off VLAN in VFTA | |
902 | * | |
903 | * Turn on/off specified VLAN in the VLAN filter table. | |
904 | **/ | |
e855aac8 HE |
905 | static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
906 | bool vlan_on) | |
c44ade9e JB |
907 | { |
908 | u32 regindex; | |
909 | u32 bitindex; | |
910 | u32 bits; | |
911 | u32 vftabyte; | |
912 | ||
913 | if (vlan > 4095) | |
914 | return IXGBE_ERR_PARAM; | |
915 | ||
916 | /* Determine 32-bit word position in array */ | |
917 | regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ | |
918 | ||
919 | /* Determine the location of the (VMD) queue index */ | |
920 | vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ | |
921 | bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ | |
922 | ||
923 | /* Set the nibble for VMD queue index */ | |
924 | bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); | |
925 | bits &= (~(0x0F << bitindex)); | |
926 | bits |= (vind << bitindex); | |
927 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); | |
928 | ||
929 | /* Determine the location of the bit for this VLAN id */ | |
930 | bitindex = vlan & 0x1F; /* lower five bits */ | |
931 | ||
932 | bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); | |
933 | if (vlan_on) | |
934 | /* Turn on this VLAN id */ | |
935 | bits |= (1 << bitindex); | |
936 | else | |
937 | /* Turn off this VLAN id */ | |
938 | bits &= ~(1 << bitindex); | |
939 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); | |
940 | ||
941 | return 0; | |
942 | } | |
943 | ||
944 | /** | |
945 | * ixgbe_clear_vfta_82598 - Clear VLAN filter table | |
946 | * @hw: pointer to hardware structure | |
947 | * | |
948 | * Clears the VLAN filer table, and the VMDq index associated with the filter | |
949 | **/ | |
950 | static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) | |
951 | { | |
952 | u32 offset; | |
953 | u32 vlanbyte; | |
954 | ||
955 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
956 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); | |
957 | ||
958 | for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) | |
959 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
960 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), | |
b4617240 | 961 | 0); |
c44ade9e JB |
962 | |
963 | return 0; | |
964 | } | |
965 | ||
c44ade9e JB |
966 | /** |
967 | * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register | |
968 | * @hw: pointer to hardware structure | |
969 | * @reg: analog register to read | |
970 | * @val: read value | |
971 | * | |
972 | * Performs read operation to Atlas analog register specified. | |
973 | **/ | |
e855aac8 | 974 | static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) |
c44ade9e JB |
975 | { |
976 | u32 atlas_ctl; | |
977 | ||
978 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, | |
979 | IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); | |
980 | IXGBE_WRITE_FLUSH(hw); | |
981 | udelay(10); | |
982 | atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | |
983 | *val = (u8)atlas_ctl; | |
984 | ||
985 | return 0; | |
986 | } | |
987 | ||
988 | /** | |
989 | * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register | |
990 | * @hw: pointer to hardware structure | |
991 | * @reg: atlas register to write | |
992 | * @val: value to write | |
993 | * | |
994 | * Performs write operation to Atlas analog register specified. | |
995 | **/ | |
e855aac8 | 996 | static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) |
c44ade9e JB |
997 | { |
998 | u32 atlas_ctl; | |
999 | ||
1000 | atlas_ctl = (reg << 8) | val; | |
1001 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); | |
1002 | IXGBE_WRITE_FLUSH(hw); | |
1003 | udelay(10); | |
1004 | ||
1005 | return 0; | |
1006 | } | |
1007 | ||
c4900be0 | 1008 | /** |
07ce870b | 1009 | * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface. |
c4900be0 | 1010 | * @hw: pointer to hardware structure |
07ce870b ET |
1011 | * @dev_addr: address to read from |
1012 | * @byte_offset: byte offset to read from dev_addr | |
c4900be0 DS |
1013 | * @eeprom_data: value read |
1014 | * | |
07ce870b | 1015 | * Performs 8 byte read operation to SFP module's data over I2C interface. |
c4900be0 | 1016 | **/ |
07ce870b ET |
1017 | static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, |
1018 | u8 byte_offset, u8 *eeprom_data) | |
c4900be0 DS |
1019 | { |
1020 | s32 status = 0; | |
1021 | u16 sfp_addr = 0; | |
1022 | u16 sfp_data = 0; | |
1023 | u16 sfp_stat = 0; | |
3dcc2f41 | 1024 | u16 gssr; |
c4900be0 DS |
1025 | u32 i; |
1026 | ||
3dcc2f41 ET |
1027 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
1028 | gssr = IXGBE_GSSR_PHY1_SM; | |
1029 | else | |
1030 | gssr = IXGBE_GSSR_PHY0_SM; | |
1031 | ||
1032 | if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) | |
1033 | return IXGBE_ERR_SWFW_SYNC; | |
1034 | ||
c4900be0 DS |
1035 | if (hw->phy.type == ixgbe_phy_nl) { |
1036 | /* | |
1037 | * phy SDA/SCL registers are at addresses 0xC30A to | |
1038 | * 0xC30D. These registers are used to talk to the SFP+ | |
1039 | * module's EEPROM through the SDA/SCL (I2C) interface. | |
1040 | */ | |
07ce870b | 1041 | sfp_addr = (dev_addr << 8) + byte_offset; |
c4900be0 | 1042 | sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); |
3dcc2f41 ET |
1043 | hw->phy.ops.write_reg_mdi(hw, |
1044 | IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, | |
1045 | MDIO_MMD_PMAPMD, | |
1046 | sfp_addr); | |
c4900be0 DS |
1047 | |
1048 | /* Poll status */ | |
1049 | for (i = 0; i < 100; i++) { | |
3dcc2f41 ET |
1050 | hw->phy.ops.read_reg_mdi(hw, |
1051 | IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, | |
1052 | MDIO_MMD_PMAPMD, | |
1053 | &sfp_stat); | |
c4900be0 DS |
1054 | sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; |
1055 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) | |
1056 | break; | |
032b4325 | 1057 | usleep_range(10000, 20000); |
c4900be0 DS |
1058 | } |
1059 | ||
1060 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { | |
1061 | hw_dbg(hw, "EEPROM read did not pass.\n"); | |
1062 | status = IXGBE_ERR_SFP_NOT_PRESENT; | |
1063 | goto out; | |
1064 | } | |
1065 | ||
1066 | /* Read data */ | |
3dcc2f41 ET |
1067 | hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, |
1068 | MDIO_MMD_PMAPMD, &sfp_data); | |
c4900be0 DS |
1069 | |
1070 | *eeprom_data = (u8)(sfp_data >> 8); | |
1071 | } else { | |
1072 | status = IXGBE_ERR_PHY; | |
c4900be0 DS |
1073 | } |
1074 | ||
1075 | out: | |
3dcc2f41 | 1076 | hw->mac.ops.release_swfw_sync(hw, gssr); |
c4900be0 DS |
1077 | return status; |
1078 | } | |
1079 | ||
07ce870b ET |
1080 | /** |
1081 | * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. | |
1082 | * @hw: pointer to hardware structure | |
1083 | * @byte_offset: EEPROM byte offset to read | |
1084 | * @eeprom_data: value read | |
1085 | * | |
1086 | * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. | |
1087 | **/ | |
1088 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, | |
1089 | u8 *eeprom_data) | |
1090 | { | |
1091 | return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR, | |
1092 | byte_offset, eeprom_data); | |
1093 | } | |
1094 | ||
1095 | /** | |
1096 | * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface. | |
1097 | * @hw: pointer to hardware structure | |
1098 | * @byte_offset: byte offset at address 0xA2 | |
1099 | * @eeprom_data: value read | |
1100 | * | |
1101 | * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C | |
1102 | **/ | |
1103 | static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, | |
1104 | u8 *sff8472_data) | |
1105 | { | |
1106 | return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2, | |
1107 | byte_offset, sff8472_data); | |
1108 | } | |
1109 | ||
c44ade9e JB |
1110 | /** |
1111 | * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type | |
1112 | * @hw: pointer to hardware structure | |
1113 | * | |
1114 | * Determines physical layer capabilities of the current configuration. | |
1115 | **/ | |
11afc1b1 | 1116 | static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) |
c44ade9e | 1117 | { |
11afc1b1 | 1118 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
04193058 PWJ |
1119 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
1120 | u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; | |
1121 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; | |
1122 | u16 ext_ability = 0; | |
1123 | ||
1124 | hw->phy.ops.identify(hw); | |
1125 | ||
1126 | /* Copper PHY must be checked before AUTOC LMS to determine correct | |
1127 | * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ | |
037c6d0a ET |
1128 | switch (hw->phy.type) { |
1129 | case ixgbe_phy_tn: | |
037c6d0a ET |
1130 | case ixgbe_phy_cu_unknown: |
1131 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, | |
1132 | MDIO_MMD_PMAPMD, &ext_ability); | |
6b73e10d | 1133 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) |
04193058 | 1134 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
6b73e10d | 1135 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
04193058 | 1136 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
6b73e10d | 1137 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
04193058 PWJ |
1138 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
1139 | goto out; | |
037c6d0a ET |
1140 | default: |
1141 | break; | |
04193058 | 1142 | } |
c44ade9e | 1143 | |
04193058 PWJ |
1144 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
1145 | case IXGBE_AUTOC_LMS_1G_AN: | |
1146 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: | |
1147 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) | |
1148 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1149 | else | |
1150 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; | |
c4900be0 | 1151 | break; |
04193058 PWJ |
1152 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
1153 | if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) | |
1154 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; | |
1155 | else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) | |
1156 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
1157 | else /* XAUI */ | |
1158 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
c44ade9e | 1159 | break; |
04193058 PWJ |
1160 | case IXGBE_AUTOC_LMS_KX4_AN: |
1161 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
1162 | if (autoc & IXGBE_AUTOC_KX_SUPP) | |
1163 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1164 | if (autoc & IXGBE_AUTOC_KX4_SUPP) | |
1165 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
c44ade9e | 1166 | break; |
04193058 | 1167 | default: |
0befdb3e | 1168 | break; |
04193058 PWJ |
1169 | } |
1170 | ||
1171 | if (hw->phy.type == ixgbe_phy_nl) { | |
c4900be0 DS |
1172 | hw->phy.ops.identify_sfp(hw); |
1173 | ||
1174 | switch (hw->phy.sfp_type) { | |
1175 | case ixgbe_sfp_type_da_cu: | |
1176 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1177 | break; | |
1178 | case ixgbe_sfp_type_sr: | |
1179 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1180 | break; | |
1181 | case ixgbe_sfp_type_lr: | |
1182 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1183 | break; | |
1184 | default: | |
1185 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
1186 | break; | |
1187 | } | |
04193058 | 1188 | } |
c44ade9e | 1189 | |
04193058 PWJ |
1190 | switch (hw->device_id) { |
1191 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: | |
1192 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1193 | break; | |
1194 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: | |
1195 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
1196 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
1197 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1198 | break; | |
1199 | case IXGBE_DEV_ID_82598EB_XF_LR: | |
1200 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1201 | break; | |
c44ade9e | 1202 | default: |
c44ade9e JB |
1203 | break; |
1204 | } | |
1205 | ||
04193058 | 1206 | out: |
c44ade9e JB |
1207 | return physical_layer; |
1208 | } | |
1209 | ||
c9130180 ET |
1210 | /** |
1211 | * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple | |
1212 | * port devices. | |
1213 | * @hw: pointer to the HW structure | |
1214 | * | |
1215 | * Calls common function and corrects issue with some single port devices | |
1216 | * that enable LAN1 but not LAN0. | |
1217 | **/ | |
1218 | static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) | |
1219 | { | |
1220 | struct ixgbe_bus_info *bus = &hw->bus; | |
1221 | u16 pci_gen = 0; | |
1222 | u16 pci_ctrl2 = 0; | |
1223 | ||
1224 | ixgbe_set_lan_id_multi_port_pcie(hw); | |
1225 | ||
1226 | /* check if LAN0 is disabled */ | |
1227 | hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); | |
1228 | if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { | |
1229 | ||
1230 | hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); | |
1231 | ||
1232 | /* if LAN0 is completely disabled force function to 0 */ | |
1233 | if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && | |
1234 | !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && | |
1235 | !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { | |
1236 | ||
1237 | bus->func = 0; | |
1238 | } | |
1239 | } | |
1240 | } | |
1241 | ||
80605c65 JF |
1242 | /** |
1243 | * ixgbe_set_rxpba_82598 - Configure packet buffers | |
1244 | * @hw: pointer to hardware structure | |
1245 | * @dcb_config: pointer to ixgbe_dcb_config structure | |
1246 | * | |
1247 | * Configure packet buffers. | |
1248 | */ | |
1249 | static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom, | |
1250 | int strategy) | |
1251 | { | |
1252 | u32 rxpktsize = IXGBE_RXPBSIZE_64KB; | |
1253 | u8 i = 0; | |
1254 | ||
1255 | if (!num_pb) | |
1256 | return; | |
1257 | ||
1258 | /* Setup Rx packet buffer sizes */ | |
1259 | switch (strategy) { | |
1260 | case PBA_STRATEGY_WEIGHTED: | |
1261 | /* Setup the first four at 80KB */ | |
1262 | rxpktsize = IXGBE_RXPBSIZE_80KB; | |
1263 | for (; i < 4; i++) | |
1264 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); | |
1265 | /* Setup the last four at 48KB...don't re-init i */ | |
1266 | rxpktsize = IXGBE_RXPBSIZE_48KB; | |
1267 | /* Fall Through */ | |
1268 | case PBA_STRATEGY_EQUAL: | |
1269 | default: | |
1270 | /* Divide the remaining Rx packet buffer evenly among the TCs */ | |
1271 | for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) | |
1272 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); | |
1273 | break; | |
1274 | } | |
1275 | ||
1276 | /* Setup Tx packet buffer sizes */ | |
1277 | for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) | |
1278 | IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); | |
1279 | ||
1280 | return; | |
1281 | } | |
1282 | ||
9a799d71 | 1283 | static struct ixgbe_mac_operations mac_ops_82598 = { |
c44ade9e JB |
1284 | .init_hw = &ixgbe_init_hw_generic, |
1285 | .reset_hw = &ixgbe_reset_hw_82598, | |
202ff1ec | 1286 | .start_hw = &ixgbe_start_hw_82598, |
c44ade9e | 1287 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
9a799d71 | 1288 | .get_media_type = &ixgbe_get_media_type_82598, |
c44ade9e | 1289 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, |
11afc1b1 | 1290 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, |
c44ade9e JB |
1291 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
1292 | .stop_adapter = &ixgbe_stop_adapter_generic, | |
11afc1b1 | 1293 | .get_bus_info = &ixgbe_get_bus_info_generic, |
c9130180 | 1294 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598, |
c44ade9e JB |
1295 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, |
1296 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, | |
3957d63d | 1297 | .setup_link = &ixgbe_setup_mac_link_82598, |
80605c65 | 1298 | .set_rxpba = &ixgbe_set_rxpba_82598, |
c44ade9e JB |
1299 | .check_link = &ixgbe_check_mac_link_82598, |
1300 | .get_link_capabilities = &ixgbe_get_link_capabilities_82598, | |
1301 | .led_on = &ixgbe_led_on_generic, | |
1302 | .led_off = &ixgbe_led_off_generic, | |
87c12017 PW |
1303 | .blink_led_start = &ixgbe_blink_led_start_generic, |
1304 | .blink_led_stop = &ixgbe_blink_led_stop_generic, | |
c44ade9e JB |
1305 | .set_rar = &ixgbe_set_rar_generic, |
1306 | .clear_rar = &ixgbe_clear_rar_generic, | |
1307 | .set_vmdq = &ixgbe_set_vmdq_82598, | |
1308 | .clear_vmdq = &ixgbe_clear_vmdq_82598, | |
1309 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, | |
c44ade9e JB |
1310 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, |
1311 | .enable_mc = &ixgbe_enable_mc_generic, | |
1312 | .disable_mc = &ixgbe_disable_mc_generic, | |
1313 | .clear_vfta = &ixgbe_clear_vfta_82598, | |
1314 | .set_vfta = &ixgbe_set_vfta_82598, | |
620fa036 | 1315 | .fc_enable = &ixgbe_fc_enable_82598, |
9612de92 | 1316 | .set_fw_drv_ver = NULL, |
5e655105 DS |
1317 | .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, |
1318 | .release_swfw_sync = &ixgbe_release_swfw_sync, | |
3ca8bc6d DS |
1319 | .get_thermal_sensor_data = NULL, |
1320 | .init_thermal_sensor_thresh = NULL, | |
0b2679d6 | 1321 | .mng_fw_enabled = NULL, |
429d6a3b DS |
1322 | .prot_autoc_read = &prot_autoc_read_generic, |
1323 | .prot_autoc_write = &prot_autoc_write_generic, | |
c44ade9e JB |
1324 | }; |
1325 | ||
1326 | static struct ixgbe_eeprom_operations eeprom_ops_82598 = { | |
1327 | .init_params = &ixgbe_init_eeprom_params_generic, | |
21ce849b | 1328 | .read = &ixgbe_read_eerd_generic, |
2fa5eef4 ET |
1329 | .write = &ixgbe_write_eeprom_generic, |
1330 | .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, | |
68c7005d | 1331 | .read_buffer = &ixgbe_read_eerd_buffer_generic, |
a391f1d5 | 1332 | .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, |
c44ade9e JB |
1333 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, |
1334 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, | |
1335 | }; | |
1336 | ||
1337 | static struct ixgbe_phy_operations phy_ops_82598 = { | |
1338 | .identify = &ixgbe_identify_phy_generic, | |
8f58332b | 1339 | .identify_sfp = &ixgbe_identify_module_generic, |
04f165ef | 1340 | .init = &ixgbe_init_phy_ops_82598, |
c44ade9e JB |
1341 | .reset = &ixgbe_reset_phy_generic, |
1342 | .read_reg = &ixgbe_read_phy_reg_generic, | |
1343 | .write_reg = &ixgbe_write_phy_reg_generic, | |
3dcc2f41 ET |
1344 | .read_reg_mdi = &ixgbe_read_phy_reg_mdi, |
1345 | .write_reg_mdi = &ixgbe_write_phy_reg_mdi, | |
c44ade9e JB |
1346 | .setup_link = &ixgbe_setup_phy_link_generic, |
1347 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
07ce870b | 1348 | .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598, |
c4900be0 | 1349 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, |
119fc60a | 1350 | .check_overtemp = &ixgbe_tn_check_overtemp, |
9a799d71 AK |
1351 | }; |
1352 | ||
3957d63d | 1353 | struct ixgbe_info ixgbe_82598_info = { |
9a799d71 AK |
1354 | .mac = ixgbe_mac_82598EB, |
1355 | .get_invariants = &ixgbe_get_invariants_82598, | |
1356 | .mac_ops = &mac_ops_82598, | |
c44ade9e JB |
1357 | .eeprom_ops = &eeprom_ops_82598, |
1358 | .phy_ops = &phy_ops_82598, | |
9a799d71 | 1359 | }; |