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igb: Bump version number
[linux-2.6-block.git] / drivers / net / ethernet / intel / igc / igc_main.c
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d89f8841
SN		 1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018 Intel Corporation */
3
4#include <linux/module.h>
5#include <linux/types.h>
c9a11c23
SN		 6#include <linux/if_vlan.h>
7#include <linux/aer.h>
d89f8841
SN		 8
9#include "igc.h"
10#include "igc_hw.h"
11
12#define DRV_VERSION "0.0.1-k"
13#define DRV_SUMMARY "Intel(R) 2.5G Ethernet Linux Driver"
14
c9a11c23
SN		 15static int debug = -1;
16
d89f8841
SN		 17MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
18MODULE_DESCRIPTION(DRV_SUMMARY);
19MODULE_LICENSE("GPL v2");
20MODULE_VERSION(DRV_VERSION);
c9a11c23
SN		 21module_param(debug, int, 0);
22MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
d89f8841
SN		 23
24char igc_driver_name[] = "igc";
25char igc_driver_version[] = DRV_VERSION;
26static const char igc_driver_string[] = DRV_SUMMARY;
27static const char igc_copyright[] =
28 "Copyright(c) 2018 Intel Corporation.";
29
ab405612
SN		 30static const struct igc_info *igc_info_tbl[] = {
31 [board_base] = &igc_base_info,
32};
33
d89f8841 34static const struct pci_device_id igc_pci_tbl[] = {
ab405612
SN		 35 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base },
36 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base },
d89f8841
SN		 37 /* required last entry */
38 {0, }
39};
40
41MODULE_DEVICE_TABLE(pci, igc_pci_tbl);
42
146740f9 43/* forward declaration */
13b5b7fd 44static void igc_clean_tx_ring(struct igc_ring *tx_ring);
146740f9 45static int igc_sw_init(struct igc_adapter *);
c9a11c23
SN		 46static void igc_configure(struct igc_adapter *adapter);
47static void igc_power_down_link(struct igc_adapter *adapter);
48static void igc_set_default_mac_filter(struct igc_adapter *adapter);
13b5b7fd 49static void igc_set_rx_mode(struct net_device *netdev);
3df25e4c
SN		 50static void igc_write_itr(struct igc_q_vector *q_vector);
51static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector);
52static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx);
53static void igc_set_interrupt_capability(struct igc_adapter *adapter,
54 bool msix);
55static void igc_free_q_vectors(struct igc_adapter *adapter);
56static void igc_irq_disable(struct igc_adapter *adapter);
57static void igc_irq_enable(struct igc_adapter *adapter);
58static void igc_configure_msix(struct igc_adapter *adapter);
0507ef8a
SN		 59static bool igc_alloc_mapped_page(struct igc_ring *rx_ring,
60 struct igc_rx_buffer *bi);
3df25e4c
SN		 61
62enum latency_range {
63 lowest_latency = 0,
64 low_latency = 1,
65 bulk_latency = 2,
66 latency_invalid = 255
67};
c9a11c23
SN		 68
69static void igc_reset(struct igc_adapter *adapter)
70{
c0071c7a
SN		 71 struct pci_dev *pdev = adapter->pdev;
72 struct igc_hw *hw = &adapter->hw;
73
74 hw->mac.ops.reset_hw(hw);
75
76 if (hw->mac.ops.init_hw(hw))
77 dev_err(&pdev->dev, "Hardware Error\n");
78
c9a11c23
SN		 79 if (!netif_running(adapter->netdev))
80 igc_power_down_link(adapter);
5586838f
SN		 81
82 igc_get_phy_info(hw);
c9a11c23
SN		 83}
84
85/**
86 * igc_power_up_link - Power up the phy/serdes link
87 * @adapter: address of board private structure
88 */
89static void igc_power_up_link(struct igc_adapter *adapter)
90{
5586838f
SN		 91 igc_reset_phy(&adapter->hw);
92
93 if (adapter->hw.phy.media_type == igc_media_type_copper)
94 igc_power_up_phy_copper(&adapter->hw);
95
96 igc_setup_link(&adapter->hw);
c9a11c23
SN		 97}
98
99/**
100 * igc_power_down_link - Power down the phy/serdes link
101 * @adapter: address of board private structure
102 */
103static void igc_power_down_link(struct igc_adapter *adapter)
104{
5586838f
SN		 105 if (adapter->hw.phy.media_type == igc_media_type_copper)
106 igc_power_down_phy_copper_base(&adapter->hw);
c9a11c23
SN		 107}
108
109/**
110 * igc_release_hw_control - release control of the h/w to f/w
111 * @adapter: address of board private structure
112 *
113 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
114 * For ASF and Pass Through versions of f/w this means that the
115 * driver is no longer loaded.
116 */
117static void igc_release_hw_control(struct igc_adapter *adapter)
118{
119 struct igc_hw *hw = &adapter->hw;
120 u32 ctrl_ext;
121
122 /* Let firmware take over control of h/w */
123 ctrl_ext = rd32(IGC_CTRL_EXT);
124 wr32(IGC_CTRL_EXT,
125 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
126}
127
128/**
129 * igc_get_hw_control - get control of the h/w from f/w
130 * @adapter: address of board private structure
131 *
132 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
133 * For ASF and Pass Through versions of f/w this means that
134 * the driver is loaded.
135 */
136static void igc_get_hw_control(struct igc_adapter *adapter)
137{
138 struct igc_hw *hw = &adapter->hw;
139 u32 ctrl_ext;
140
141 /* Let firmware know the driver has taken over */
142 ctrl_ext = rd32(IGC_CTRL_EXT);
143 wr32(IGC_CTRL_EXT,
144 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
145}
146
13b5b7fd
SN		 147/**
148 * igc_free_tx_resources - Free Tx Resources per Queue
149 * @tx_ring: Tx descriptor ring for a specific queue
150 *
151 * Free all transmit software resources
152 */
153static void igc_free_tx_resources(struct igc_ring *tx_ring)
154{
155 igc_clean_tx_ring(tx_ring);
156
157 vfree(tx_ring->tx_buffer_info);
158 tx_ring->tx_buffer_info = NULL;
159
160 /* if not set, then don't free */
161 if (!tx_ring->desc)
162 return;
163
164 dma_free_coherent(tx_ring->dev, tx_ring->size,
165 tx_ring->desc, tx_ring->dma);
166
167 tx_ring->desc = NULL;
168}
169
170/**
171 * igc_free_all_tx_resources - Free Tx Resources for All Queues
172 * @adapter: board private structure
173 *
174 * Free all transmit software resources
175 */
176static void igc_free_all_tx_resources(struct igc_adapter *adapter)
177{
178 int i;
179
180 for (i = 0; i < adapter->num_tx_queues; i++)
181 igc_free_tx_resources(adapter->tx_ring[i]);
182}
183
184/**
185 * igc_clean_tx_ring - Free Tx Buffers
186 * @tx_ring: ring to be cleaned
187 */
188static void igc_clean_tx_ring(struct igc_ring *tx_ring)
189{
190 u16 i = tx_ring->next_to_clean;
191 struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
192
193 while (i != tx_ring->next_to_use) {
194 union igc_adv_tx_desc *eop_desc, *tx_desc;
195
196 /* Free all the Tx ring sk_buffs */
197 dev_kfree_skb_any(tx_buffer->skb);
198
199 /* unmap skb header data */
200 dma_unmap_single(tx_ring->dev,
201 dma_unmap_addr(tx_buffer, dma),
202 dma_unmap_len(tx_buffer, len),
203 DMA_TO_DEVICE);
204
205 /* check for eop_desc to determine the end of the packet */
206 eop_desc = tx_buffer->next_to_watch;
207 tx_desc = IGC_TX_DESC(tx_ring, i);
208
209 /* unmap remaining buffers */
210 while (tx_desc != eop_desc) {
211 tx_buffer++;
212 tx_desc++;
213 i++;
214 if (unlikely(i == tx_ring->count)) {
215 i = 0;
216 tx_buffer = tx_ring->tx_buffer_info;
217 tx_desc = IGC_TX_DESC(tx_ring, 0);
218 }
219
220 /* unmap any remaining paged data */
221 if (dma_unmap_len(tx_buffer, len))
222 dma_unmap_page(tx_ring->dev,
223 dma_unmap_addr(tx_buffer, dma),
224 dma_unmap_len(tx_buffer, len),
225 DMA_TO_DEVICE);
226 }
227
228 /* move us one more past the eop_desc for start of next pkt */
229 tx_buffer++;
230 i++;
231 if (unlikely(i == tx_ring->count)) {
232 i = 0;
233 tx_buffer = tx_ring->tx_buffer_info;
234 }
235 }
236
237 /* reset BQL for queue */
238 netdev_tx_reset_queue(txring_txq(tx_ring));
239
240 /* reset next_to_use and next_to_clean */
241 tx_ring->next_to_use = 0;
242 tx_ring->next_to_clean = 0;
243}
244
0507ef8a
SN		 245/**
246 * igc_clean_all_tx_rings - Free Tx Buffers for all queues
247 * @adapter: board private structure
248 */
249static void igc_clean_all_tx_rings(struct igc_adapter *adapter)
250{
251 int i;
252
253 for (i = 0; i < adapter->num_tx_queues; i++)
254 if (adapter->tx_ring[i])
255 igc_clean_tx_ring(adapter->tx_ring[i]);
256}
257
13b5b7fd
SN		 258/**
259 * igc_setup_tx_resources - allocate Tx resources (Descriptors)
260 * @tx_ring: tx descriptor ring (for a specific queue) to setup
261 *
262 * Return 0 on success, negative on failure
263 */
264static int igc_setup_tx_resources(struct igc_ring *tx_ring)
265{
266 struct device *dev = tx_ring->dev;
267 int size = 0;
268
269 size = sizeof(struct igc_tx_buffer) * tx_ring->count;
270 tx_ring->tx_buffer_info = vzalloc(size);
271 if (!tx_ring->tx_buffer_info)
272 goto err;
273
274 /* round up to nearest 4K */
275 tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc);
276 tx_ring->size = ALIGN(tx_ring->size, 4096);
277
278 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
279 &tx_ring->dma, GFP_KERNEL);
280
281 if (!tx_ring->desc)
282 goto err;
283
284 tx_ring->next_to_use = 0;
285 tx_ring->next_to_clean = 0;
286
287 return 0;
288
289err:
290 vfree(tx_ring->tx_buffer_info);
291 dev_err(dev,
292 "Unable to allocate memory for the transmit descriptor ring\n");
293 return -ENOMEM;
294}
295
296/**
297 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues
298 * @adapter: board private structure
299 *
300 * Return 0 on success, negative on failure
301 */
302static int igc_setup_all_tx_resources(struct igc_adapter *adapter)
303{
304 struct pci_dev *pdev = adapter->pdev;
305 int i, err = 0;
306
307 for (i = 0; i < adapter->num_tx_queues; i++) {
308 err = igc_setup_tx_resources(adapter->tx_ring[i]);
309 if (err) {
310 dev_err(&pdev->dev,
311 "Allocation for Tx Queue %u failed\n", i);
312 for (i--; i >= 0; i--)
313 igc_free_tx_resources(adapter->tx_ring[i]);
314 break;
315 }
316 }
317
318 return err;
319}
320
321/**
322 * igc_clean_rx_ring - Free Rx Buffers per Queue
323 * @rx_ring: ring to free buffers from
324 */
325static void igc_clean_rx_ring(struct igc_ring *rx_ring)
326{
327 u16 i = rx_ring->next_to_clean;
328
329 if (rx_ring->skb)
330 dev_kfree_skb(rx_ring->skb);
331 rx_ring->skb = NULL;
332
333 /* Free all the Rx ring sk_buffs */
334 while (i != rx_ring->next_to_alloc) {
335 struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
336
337 /* Invalidate cache lines that may have been written to by
338 * device so that we avoid corrupting memory.
339 */
340 dma_sync_single_range_for_cpu(rx_ring->dev,
341 buffer_info->dma,
342 buffer_info->page_offset,
343 igc_rx_bufsz(rx_ring),
344 DMA_FROM_DEVICE);
345
346 /* free resources associated with mapping */
347 dma_unmap_page_attrs(rx_ring->dev,
348 buffer_info->dma,
349 igc_rx_pg_size(rx_ring),
350 DMA_FROM_DEVICE,
351 IGC_RX_DMA_ATTR);
352 __page_frag_cache_drain(buffer_info->page,
353 buffer_info->pagecnt_bias);
354
355 i++;
356 if (i == rx_ring->count)
357 i = 0;
358 }
359
360 rx_ring->next_to_alloc = 0;
361 rx_ring->next_to_clean = 0;
362 rx_ring->next_to_use = 0;
363}
364
0507ef8a
SN		 365/**
366 * igc_clean_all_rx_rings - Free Rx Buffers for all queues
367 * @adapter: board private structure
368 */
369static void igc_clean_all_rx_rings(struct igc_adapter *adapter)
370{
371 int i;
372
373 for (i = 0; i < adapter->num_rx_queues; i++)
374 if (adapter->rx_ring[i])
375 igc_clean_rx_ring(adapter->rx_ring[i]);
376}
377
13b5b7fd
SN		 378/**
379 * igc_free_rx_resources - Free Rx Resources
380 * @rx_ring: ring to clean the resources from
381 *
382 * Free all receive software resources
383 */
384static void igc_free_rx_resources(struct igc_ring *rx_ring)
385{
386 igc_clean_rx_ring(rx_ring);
387
388 vfree(rx_ring->rx_buffer_info);
389 rx_ring->rx_buffer_info = NULL;
390
391 /* if not set, then don't free */
392 if (!rx_ring->desc)
393 return;
394
395 dma_free_coherent(rx_ring->dev, rx_ring->size,
396 rx_ring->desc, rx_ring->dma);
397
398 rx_ring->desc = NULL;
399}
400
401/**
402 * igc_free_all_rx_resources - Free Rx Resources for All Queues
403 * @adapter: board private structure
404 *
405 * Free all receive software resources
406 */
407static void igc_free_all_rx_resources(struct igc_adapter *adapter)
408{
409 int i;
410
411 for (i = 0; i < adapter->num_rx_queues; i++)
412 igc_free_rx_resources(adapter->rx_ring[i]);
413}
414
415/**
416 * igc_setup_rx_resources - allocate Rx resources (Descriptors)
417 * @rx_ring: rx descriptor ring (for a specific queue) to setup
418 *
419 * Returns 0 on success, negative on failure
420 */
421static int igc_setup_rx_resources(struct igc_ring *rx_ring)
422{
423 struct device *dev = rx_ring->dev;
424 int size, desc_len;
425
426 size = sizeof(struct igc_rx_buffer) * rx_ring->count;
427 rx_ring->rx_buffer_info = vzalloc(size);
428 if (!rx_ring->rx_buffer_info)
429 goto err;
430
431 desc_len = sizeof(union igc_adv_rx_desc);
432
433 /* Round up to nearest 4K */
434 rx_ring->size = rx_ring->count * desc_len;
435 rx_ring->size = ALIGN(rx_ring->size, 4096);
436
437 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
438 &rx_ring->dma, GFP_KERNEL);
439
440 if (!rx_ring->desc)
441 goto err;
442
443 rx_ring->next_to_alloc = 0;
444 rx_ring->next_to_clean = 0;
445 rx_ring->next_to_use = 0;
446
447 return 0;
448
449err:
450 vfree(rx_ring->rx_buffer_info);
451 rx_ring->rx_buffer_info = NULL;
452 dev_err(dev,
453 "Unable to allocate memory for the receive descriptor ring\n");
454 return -ENOMEM;
455}
456
457/**
458 * igc_setup_all_rx_resources - wrapper to allocate Rx resources
459 * (Descriptors) for all queues
460 * @adapter: board private structure
461 *
462 * Return 0 on success, negative on failure
463 */
464static int igc_setup_all_rx_resources(struct igc_adapter *adapter)
465{
466 struct pci_dev *pdev = adapter->pdev;
467 int i, err = 0;
468
469 for (i = 0; i < adapter->num_rx_queues; i++) {
470 err = igc_setup_rx_resources(adapter->rx_ring[i]);
471 if (err) {
472 dev_err(&pdev->dev,
473 "Allocation for Rx Queue %u failed\n", i);
474 for (i--; i >= 0; i--)
475 igc_free_rx_resources(adapter->rx_ring[i]);
476 break;
477 }
478 }
479
480 return err;
481}
482
483/**
484 * igc_configure_rx_ring - Configure a receive ring after Reset
485 * @adapter: board private structure
486 * @ring: receive ring to be configured
487 *
488 * Configure the Rx unit of the MAC after a reset.
489 */
490static void igc_configure_rx_ring(struct igc_adapter *adapter,
491 struct igc_ring *ring)
492{
493 struct igc_hw *hw = &adapter->hw;
494 union igc_adv_rx_desc *rx_desc;
495 int reg_idx = ring->reg_idx;
496 u32 srrctl = 0, rxdctl = 0;
497 u64 rdba = ring->dma;
498
499 /* disable the queue */
500 wr32(IGC_RXDCTL(reg_idx), 0);
501
502 /* Set DMA base address registers */
503 wr32(IGC_RDBAL(reg_idx),
504 rdba & 0x00000000ffffffffULL);
505 wr32(IGC_RDBAH(reg_idx), rdba >> 32);
506 wr32(IGC_RDLEN(reg_idx),
507 ring->count * sizeof(union igc_adv_rx_desc));
508
509 /* initialize head and tail */
510 ring->tail = adapter->io_addr + IGC_RDT(reg_idx);
511 wr32(IGC_RDH(reg_idx), 0);
512 writel(0, ring->tail);
513
514 /* reset next-to- use/clean to place SW in sync with hardware */
515 ring->next_to_clean = 0;
516 ring->next_to_use = 0;
517
518 /* set descriptor configuration */
519 srrctl = IGC_RX_HDR_LEN << IGC_SRRCTL_BSIZEHDRSIZE_SHIFT;
520 if (ring_uses_large_buffer(ring))
521 srrctl |= IGC_RXBUFFER_3072 >> IGC_SRRCTL_BSIZEPKT_SHIFT;
522 else
523 srrctl |= IGC_RXBUFFER_2048 >> IGC_SRRCTL_BSIZEPKT_SHIFT;
524 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF;
525
526 wr32(IGC_SRRCTL(reg_idx), srrctl);
527
528 rxdctl |= IGC_RX_PTHRESH;
529 rxdctl |= IGC_RX_HTHRESH << 8;
530 rxdctl |= IGC_RX_WTHRESH << 16;
531
532 /* initialize rx_buffer_info */
533 memset(ring->rx_buffer_info, 0,
534 sizeof(struct igc_rx_buffer) * ring->count);
535
536 /* initialize Rx descriptor 0 */
537 rx_desc = IGC_RX_DESC(ring, 0);
538 rx_desc->wb.upper.length = 0;
539
540 /* enable receive descriptor fetching */
541 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE;
542
543 wr32(IGC_RXDCTL(reg_idx), rxdctl);
544}
545
546/**
547 * igc_configure_rx - Configure receive Unit after Reset
548 * @adapter: board private structure
549 *
550 * Configure the Rx unit of the MAC after a reset.
551 */
552static void igc_configure_rx(struct igc_adapter *adapter)
553{
554 int i;
555
556 /* Setup the HW Rx Head and Tail Descriptor Pointers and
557 * the Base and Length of the Rx Descriptor Ring
558 */
559 for (i = 0; i < adapter->num_rx_queues; i++)
560 igc_configure_rx_ring(adapter, adapter->rx_ring[i]);
561}
562
563/**
564 * igc_configure_tx_ring - Configure transmit ring after Reset
565 * @adapter: board private structure
566 * @ring: tx ring to configure
567 *
568 * Configure a transmit ring after a reset.
569 */
570static void igc_configure_tx_ring(struct igc_adapter *adapter,
571 struct igc_ring *ring)
572{
573 struct igc_hw *hw = &adapter->hw;
574 int reg_idx = ring->reg_idx;
575 u64 tdba = ring->dma;
576 u32 txdctl = 0;
577
578 /* disable the queue */
579 wr32(IGC_TXDCTL(reg_idx), 0);
580 wrfl();
581 mdelay(10);
582
583 wr32(IGC_TDLEN(reg_idx),
584 ring->count * sizeof(union igc_adv_tx_desc));
585 wr32(IGC_TDBAL(reg_idx),
586 tdba & 0x00000000ffffffffULL);
587 wr32(IGC_TDBAH(reg_idx), tdba >> 32);
588
589 ring->tail = adapter->io_addr + IGC_TDT(reg_idx);
590 wr32(IGC_TDH(reg_idx), 0);
591 writel(0, ring->tail);
592
593 txdctl |= IGC_TX_PTHRESH;
594 txdctl |= IGC_TX_HTHRESH << 8;
595 txdctl |= IGC_TX_WTHRESH << 16;
596
597 txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
598 wr32(IGC_TXDCTL(reg_idx), txdctl);
599}
600
601/**
602 * igc_configure_tx - Configure transmit Unit after Reset
603 * @adapter: board private structure
604 *
605 * Configure the Tx unit of the MAC after a reset.
606 */
607static void igc_configure_tx(struct igc_adapter *adapter)
608{
609 int i;
610
611 for (i = 0; i < adapter->num_tx_queues; i++)
612 igc_configure_tx_ring(adapter, adapter->tx_ring[i]);
613}
614
615/**
616 * igc_setup_mrqc - configure the multiple receive queue control registers
617 * @adapter: Board private structure
618 */
619static void igc_setup_mrqc(struct igc_adapter *adapter)
620{
621}
622
623/**
624 * igc_setup_rctl - configure the receive control registers
625 * @adapter: Board private structure
626 */
627static void igc_setup_rctl(struct igc_adapter *adapter)
628{
629 struct igc_hw *hw = &adapter->hw;
630 u32 rctl;
631
632 rctl = rd32(IGC_RCTL);
633
634 rctl &= ~(3 << IGC_RCTL_MO_SHIFT);
635 rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC);
636
637 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF |
638 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT);
639
640 /* enable stripping of CRC. Newer features require
641 * that the HW strips the CRC.
642 */
643 rctl |= IGC_RCTL_SECRC;
644
645 /* disable store bad packets and clear size bits. */
646 rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256);
647
648 /* enable LPE to allow for reception of jumbo frames */
649 rctl |= IGC_RCTL_LPE;
650
651 /* disable queue 0 to prevent tail write w/o re-config */
652 wr32(IGC_RXDCTL(0), 0);
653
654 /* This is useful for sniffing bad packets. */
655 if (adapter->netdev->features & NETIF_F_RXALL) {
656 /* UPE and MPE will be handled by normal PROMISC logic
657 * in set_rx_mode
658 */
659 rctl |= (IGC_RCTL_SBP | /* Receive bad packets */
660 IGC_RCTL_BAM | /* RX All Bcast Pkts */
661 IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
662
663 rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */
664 IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */
665 }
666
667 wr32(IGC_RCTL, rctl);
668}
669
670/**
671 * igc_setup_tctl - configure the transmit control registers
672 * @adapter: Board private structure
673 */
674static void igc_setup_tctl(struct igc_adapter *adapter)
675{
676 struct igc_hw *hw = &adapter->hw;
677 u32 tctl;
678
679 /* disable queue 0 which icould be enabled by default */
680 wr32(IGC_TXDCTL(0), 0);
681
682 /* Program the Transmit Control Register */
683 tctl = rd32(IGC_TCTL);
684 tctl &= ~IGC_TCTL_CT;
685 tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC |
686 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT);
687
688 /* Enable transmits */
689 tctl |= IGC_TCTL_EN;
690
691 wr32(IGC_TCTL, tctl);
692}
693
c9a11c23
SN		 694/**
695 * igc_set_mac - Change the Ethernet Address of the NIC
696 * @netdev: network interface device structure
697 * @p: pointer to an address structure
698 *
699 * Returns 0 on success, negative on failure
700 */
701static int igc_set_mac(struct net_device *netdev, void *p)
702{
703 struct igc_adapter *adapter = netdev_priv(netdev);
704 struct igc_hw *hw = &adapter->hw;
705 struct sockaddr *addr = p;
706
707 if (!is_valid_ether_addr(addr->sa_data))
708 return -EADDRNOTAVAIL;
709
710 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
711 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
712
713 /* set the correct pool for the new PF MAC address in entry 0 */
714 igc_set_default_mac_filter(adapter);
715
716 return 0;
717}
718
0507ef8a
SN		 719static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first)
720{
721}
722
723static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
724{
725 struct net_device *netdev = tx_ring->netdev;
726
727 netif_stop_subqueue(netdev, tx_ring->queue_index);
728
729 /* memory barriier comment */
730 smp_mb();
731
732 /* We need to check again in a case another CPU has just
733 * made room available.
734 */
735 if (igc_desc_unused(tx_ring) < size)
736 return -EBUSY;
737
738 /* A reprieve! */
739 netif_wake_subqueue(netdev, tx_ring->queue_index);
740
741 u64_stats_update_begin(&tx_ring->tx_syncp2);
742 tx_ring->tx_stats.restart_queue2++;
743 u64_stats_update_end(&tx_ring->tx_syncp2);
744
745 return 0;
746}
747
748static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
749{
750 if (igc_desc_unused(tx_ring) >= size)
751 return 0;
752 return __igc_maybe_stop_tx(tx_ring, size);
753}
754
755static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
756{
757 /* set type for advanced descriptor with frame checksum insertion */
758 u32 cmd_type = IGC_ADVTXD_DTYP_DATA |
759 IGC_ADVTXD_DCMD_DEXT |
760 IGC_ADVTXD_DCMD_IFCS;
761
762 return cmd_type;
763}
764
765static void igc_tx_olinfo_status(struct igc_ring *tx_ring,
766 union igc_adv_tx_desc *tx_desc,
767 u32 tx_flags, unsigned int paylen)
768{
769 u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT;
770
771 /* insert L4 checksum */
772 olinfo_status |= (tx_flags & IGC_TX_FLAGS_CSUM) *
773 ((IGC_TXD_POPTS_TXSM << 8) /
774 IGC_TX_FLAGS_CSUM);
775
776 /* insert IPv4 checksum */
777 olinfo_status |= (tx_flags & IGC_TX_FLAGS_IPV4) *
778 (((IGC_TXD_POPTS_IXSM << 8)) /
779 IGC_TX_FLAGS_IPV4);
780
781 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
782}
783
784static int igc_tx_map(struct igc_ring *tx_ring,
785 struct igc_tx_buffer *first,
786 const u8 hdr_len)
787{
788 struct sk_buff *skb = first->skb;
789 struct igc_tx_buffer *tx_buffer;
790 union igc_adv_tx_desc *tx_desc;
791 u32 tx_flags = first->tx_flags;
792 struct skb_frag_struct *frag;
793 u16 i = tx_ring->next_to_use;
794 unsigned int data_len, size;
795 dma_addr_t dma;
796 u32 cmd_type = igc_tx_cmd_type(skb, tx_flags);
797
798 tx_desc = IGC_TX_DESC(tx_ring, i);
799
800 igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
801
802 size = skb_headlen(skb);
803 data_len = skb->data_len;
804
805 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
806
807 tx_buffer = first;
808
809 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
810 if (dma_mapping_error(tx_ring->dev, dma))
811 goto dma_error;
812
813 /* record length, and DMA address */
814 dma_unmap_len_set(tx_buffer, len, size);
815 dma_unmap_addr_set(tx_buffer, dma, dma);
816
817 tx_desc->read.buffer_addr = cpu_to_le64(dma);
818
819 while (unlikely(size > IGC_MAX_DATA_PER_TXD)) {
820 tx_desc->read.cmd_type_len =
821 cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD);
822
823 i++;
824 tx_desc++;
825 if (i == tx_ring->count) {
826 tx_desc = IGC_TX_DESC(tx_ring, 0);
827 i = 0;
828 }
829 tx_desc->read.olinfo_status = 0;
830
831 dma += IGC_MAX_DATA_PER_TXD;
832 size -= IGC_MAX_DATA_PER_TXD;
833
834 tx_desc->read.buffer_addr = cpu_to_le64(dma);
835 }
836
837 if (likely(!data_len))
838 break;
839
840 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
841
842 i++;
843 tx_desc++;
844 if (i == tx_ring->count) {
845 tx_desc = IGC_TX_DESC(tx_ring, 0);
846 i = 0;
847 }
848 tx_desc->read.olinfo_status = 0;
849
850 size = skb_frag_size(frag);
851 data_len -= size;
852
853 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
854 size, DMA_TO_DEVICE);
855
856 tx_buffer = &tx_ring->tx_buffer_info[i];
857 }
858
859 /* write last descriptor with RS and EOP bits */
860 cmd_type |= size | IGC_TXD_DCMD;
861 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
862
863 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
864
865 /* set the timestamp */
866 first->time_stamp = jiffies;
867
a9e51058
JK		 868 skb_tx_timestamp(skb);
869
0507ef8a
SN		 870 /* Force memory writes to complete before letting h/w know there
871 * are new descriptors to fetch. (Only applicable for weak-ordered
872 * memory model archs, such as IA-64).
873 *
874 * We also need this memory barrier to make certain all of the
875 * status bits have been updated before next_to_watch is written.
876 */
877 wmb();
878
879 /* set next_to_watch value indicating a packet is present */
880 first->next_to_watch = tx_desc;
881
882 i++;
883 if (i == tx_ring->count)
884 i = 0;
885
886 tx_ring->next_to_use = i;
887
888 /* Make sure there is space in the ring for the next send. */
889 igc_maybe_stop_tx(tx_ring, DESC_NEEDED);
890
891 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
892 writel(i, tx_ring->tail);
893
894 /* we need this if more than one processor can write to our tail
895 * at a time, it synchronizes IO on IA64/Altix systems
896 */
897 mmiowb();
898 }
899
900 return 0;
901dma_error:
902 dev_err(tx_ring->dev, "TX DMA map failed\n");
903 tx_buffer = &tx_ring->tx_buffer_info[i];
904
905 /* clear dma mappings for failed tx_buffer_info map */
906 while (tx_buffer != first) {
907 if (dma_unmap_len(tx_buffer, len))
908 dma_unmap_page(tx_ring->dev,
909 dma_unmap_addr(tx_buffer, dma),
910 dma_unmap_len(tx_buffer, len),
911 DMA_TO_DEVICE);
912 dma_unmap_len_set(tx_buffer, len, 0);
913
914 if (i-- == 0)
915 i += tx_ring->count;
916 tx_buffer = &tx_ring->tx_buffer_info[i];
917 }
918
919 if (dma_unmap_len(tx_buffer, len))
920 dma_unmap_single(tx_ring->dev,
921 dma_unmap_addr(tx_buffer, dma),
922 dma_unmap_len(tx_buffer, len),
923 DMA_TO_DEVICE);
924 dma_unmap_len_set(tx_buffer, len, 0);
925
926 dev_kfree_skb_any(tx_buffer->skb);
927 tx_buffer->skb = NULL;
928
929 tx_ring->next_to_use = i;
930
931 return -1;
932}
933
934static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb,
935 struct igc_ring *tx_ring)
936{
937 u16 count = TXD_USE_COUNT(skb_headlen(skb));
938 __be16 protocol = vlan_get_protocol(skb);
939 struct igc_tx_buffer *first;
940 u32 tx_flags = 0;
941 unsigned short f;
942 u8 hdr_len = 0;
943
944 /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD,
945 * + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD,
946 * + 2 desc gap to keep tail from touching head,
947 * + 1 desc for context descriptor,
948 * otherwise try next time
949 */
950 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
951 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
952
953 if (igc_maybe_stop_tx(tx_ring, count + 3)) {
954 /* this is a hard error */
955 return NETDEV_TX_BUSY;
956 }
957
958 /* record the location of the first descriptor for this packet */
959 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
960 first->skb = skb;
961 first->bytecount = skb->len;
962 first->gso_segs = 1;
963
0507ef8a
SN		 964 /* record initial flags and protocol */
965 first->tx_flags = tx_flags;
966 first->protocol = protocol;
967
968 igc_tx_csum(tx_ring, first);
969
970 igc_tx_map(tx_ring, first, hdr_len);
971
972 return NETDEV_TX_OK;
973}
974
975static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter,
976 struct sk_buff *skb)
977{
978 unsigned int r_idx = skb->queue_mapping;
979
980 if (r_idx >= adapter->num_tx_queues)
981 r_idx = r_idx % adapter->num_tx_queues;
982
983 return adapter->tx_ring[r_idx];
984}
985
c9a11c23
SN		 986static netdev_tx_t igc_xmit_frame(struct sk_buff *skb,
987 struct net_device *netdev)
988{
0507ef8a
SN		 989 struct igc_adapter *adapter = netdev_priv(netdev);
990
991 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
992 * in order to meet this minimum size requirement.
993 */
994 if (skb->len < 17) {
995 if (skb_padto(skb, 17))
996 return NETDEV_TX_OK;
997 skb->len = 17;
998 }
999
1000 return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb));
c9a11c23
SN		 1001}
1002
0507ef8a
SN		 1003static inline void igc_rx_hash(struct igc_ring *ring,
1004 union igc_adv_rx_desc *rx_desc,
1005 struct sk_buff *skb)
13b5b7fd 1006{
0507ef8a
SN		 1007 if (ring->netdev->features & NETIF_F_RXHASH)
1008 skb_set_hash(skb,
1009 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1010 PKT_HASH_TYPE_L3);
13b5b7fd
SN		 1011}
1012
0507ef8a
SN		 1013/**
1014 * igc_process_skb_fields - Populate skb header fields from Rx descriptor
1015 * @rx_ring: rx descriptor ring packet is being transacted on
1016 * @rx_desc: pointer to the EOP Rx descriptor
1017 * @skb: pointer to current skb being populated
1018 *
1019 * This function checks the ring, descriptor, and packet information in
1020 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1021 * other fields within the skb.
1022 */
1023static void igc_process_skb_fields(struct igc_ring *rx_ring,
1024 union igc_adv_rx_desc *rx_desc,
1025 struct sk_buff *skb)
13b5b7fd 1026{
0507ef8a 1027 igc_rx_hash(rx_ring, rx_desc, skb);
13b5b7fd 1028
0507ef8a 1029 skb_record_rx_queue(skb, rx_ring->queue_index);
13b5b7fd 1030
0507ef8a
SN		 1031 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1032}
1033
1034static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring,
1035 const unsigned int size)
1036{
1037 struct igc_rx_buffer *rx_buffer;
1038
1039 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1040 prefetchw(rx_buffer->page);
1041
1042 /* we are reusing so sync this buffer for CPU use */
1043 dma_sync_single_range_for_cpu(rx_ring->dev,
1044 rx_buffer->dma,
1045 rx_buffer->page_offset,
1046 size,
1047 DMA_FROM_DEVICE);
1048
1049 rx_buffer->pagecnt_bias--;
1050
1051 return rx_buffer;
1052}
1053
1054/**
1055 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff
1056 * @rx_ring: rx descriptor ring to transact packets on
1057 * @rx_buffer: buffer containing page to add
1058 * @skb: sk_buff to place the data into
1059 * @size: size of buffer to be added
1060 *
1061 * This function will add the data contained in rx_buffer->page to the skb.
1062 */
1063static void igc_add_rx_frag(struct igc_ring *rx_ring,
1064 struct igc_rx_buffer *rx_buffer,
1065 struct sk_buff *skb,
1066 unsigned int size)
1067{
1068#if (PAGE_SIZE < 8192)
1069 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2;
1070
1071 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1072 rx_buffer->page_offset, size, truesize);
1073 rx_buffer->page_offset ^= truesize;
1074#else
1075 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
1076 SKB_DATA_ALIGN(IGC_SKB_PAD + size) :
1077 SKB_DATA_ALIGN(size);
1078 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1079 rx_buffer->page_offset, size, truesize);
1080 rx_buffer->page_offset += truesize;
1081#endif
1082}
1083
1084static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring,
1085 struct igc_rx_buffer *rx_buffer,
1086 union igc_adv_rx_desc *rx_desc,
1087 unsigned int size)
1088{
1089 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
1090#if (PAGE_SIZE < 8192)
1091 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2;
1092#else
1093 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1094 SKB_DATA_ALIGN(IGC_SKB_PAD + size);
1095#endif
1096 struct sk_buff *skb;
1097
1098 /* prefetch first cache line of first page */
1099 prefetch(va);
1100#if L1_CACHE_BYTES < 128
1101 prefetch(va + L1_CACHE_BYTES);
1102#endif
1103
1104 /* build an skb around the page buffer */
1105 skb = build_skb(va - IGC_SKB_PAD, truesize);
1106 if (unlikely(!skb))
1107 return NULL;
1108
1109 /* update pointers within the skb to store the data */
1110 skb_reserve(skb, IGC_SKB_PAD);
bb9089b6 1111 __skb_put(skb, size);
0507ef8a
SN		 1112
1113 /* update buffer offset */
1114#if (PAGE_SIZE < 8192)
1115 rx_buffer->page_offset ^= truesize;
1116#else
1117 rx_buffer->page_offset += truesize;
1118#endif
1119
1120 return skb;
1121}
1122
1123static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring,
1124 struct igc_rx_buffer *rx_buffer,
1125 union igc_adv_rx_desc *rx_desc,
1126 unsigned int size)
1127{
1128 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
1129#if (PAGE_SIZE < 8192)
1130 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2;
1131#else
1132 unsigned int truesize = SKB_DATA_ALIGN(size);
1133#endif
1134 unsigned int headlen;
1135 struct sk_buff *skb;
1136
1137 /* prefetch first cache line of first page */
1138 prefetch(va);
1139#if L1_CACHE_BYTES < 128
1140 prefetch(va + L1_CACHE_BYTES);
1141#endif
1142
1143 /* allocate a skb to store the frags */
1144 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGC_RX_HDR_LEN);
1145 if (unlikely(!skb))
1146 return NULL;
1147
1148 /* Determine available headroom for copy */
1149 headlen = size;
1150 if (headlen > IGC_RX_HDR_LEN)
1151 headlen = eth_get_headlen(va, IGC_RX_HDR_LEN);
1152
1153 /* align pull length to size of long to optimize memcpy performance */
1154 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long)));
1155
1156 /* update all of the pointers */
1157 size -= headlen;
1158 if (size) {
1159 skb_add_rx_frag(skb, 0, rx_buffer->page,
1160 (va + headlen) - page_address(rx_buffer->page),
1161 size, truesize);
1162#if (PAGE_SIZE < 8192)
bb9089b6 1163 rx_buffer->page_offset ^= truesize;
0507ef8a 1164#else
bb9089b6 1165 rx_buffer->page_offset += truesize;
0507ef8a
SN		 1166#endif
1167 } else {
1168 rx_buffer->pagecnt_bias++;
13b5b7fd
SN		 1169 }
1170
0507ef8a
SN		 1171 return skb;
1172}
13b5b7fd 1173
0507ef8a
SN		 1174/**
1175 * igc_reuse_rx_page - page flip buffer and store it back on the ring
1176 * @rx_ring: rx descriptor ring to store buffers on
1177 * @old_buff: donor buffer to have page reused
1178 *
1179 * Synchronizes page for reuse by the adapter
1180 */
1181static void igc_reuse_rx_page(struct igc_ring *rx_ring,
1182 struct igc_rx_buffer *old_buff)
1183{
1184 u16 nta = rx_ring->next_to_alloc;
1185 struct igc_rx_buffer *new_buff;
1186
1187 new_buff = &rx_ring->rx_buffer_info[nta];
1188
1189 /* update, and store next to alloc */
1190 nta++;
1191 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1192
1193 /* Transfer page from old buffer to new buffer.
1194 * Move each member individually to avoid possible store
1195 * forwarding stalls.
13b5b7fd 1196 */
0507ef8a
SN		 1197 new_buff->dma = old_buff->dma;
1198 new_buff->page = old_buff->page;
1199 new_buff->page_offset = old_buff->page_offset;
1200 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1201}
13b5b7fd 1202
0507ef8a
SN		 1203static inline bool igc_page_is_reserved(struct page *page)
1204{
1205 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1206}
1207
1208static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer)
1209{
1210 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1211 struct page *page = rx_buffer->page;
1212
1213 /* avoid re-using remote pages */
1214 if (unlikely(igc_page_is_reserved(page)))
1215 return false;
1216
1217#if (PAGE_SIZE < 8192)
1218 /* if we are only owner of page we can reuse it */
1219 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
13b5b7fd 1220 return false;
0507ef8a
SN		 1221#else
1222#define IGC_LAST_OFFSET \
1223 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048)
1224
1225 if (rx_buffer->page_offset > IGC_LAST_OFFSET)
1226 return false;
1227#endif
1228
1229 /* If we have drained the page fragment pool we need to update
1230 * the pagecnt_bias and page count so that we fully restock the
1231 * number of references the driver holds.
1232 */
1233 if (unlikely(!pagecnt_bias)) {
1234 page_ref_add(page, USHRT_MAX);
1235 rx_buffer->pagecnt_bias = USHRT_MAX;
13b5b7fd
SN		 1236 }
1237
0507ef8a
SN		 1238 return true;
1239}
1240
1241/**
1242 * igc_is_non_eop - process handling of non-EOP buffers
1243 * @rx_ring: Rx ring being processed
1244 * @rx_desc: Rx descriptor for current buffer
1245 * @skb: current socket buffer containing buffer in progress
1246 *
1247 * This function updates next to clean. If the buffer is an EOP buffer
1248 * this function exits returning false, otherwise it will place the
1249 * sk_buff in the next buffer to be chained and return true indicating
1250 * that this is in fact a non-EOP buffer.
1251 */
1252static bool igc_is_non_eop(struct igc_ring *rx_ring,
1253 union igc_adv_rx_desc *rx_desc)
1254{
1255 u32 ntc = rx_ring->next_to_clean + 1;
1256
1257 /* fetch, update, and store next to clean */
1258 ntc = (ntc < rx_ring->count) ? ntc : 0;
1259 rx_ring->next_to_clean = ntc;
1260
1261 prefetch(IGC_RX_DESC(rx_ring, ntc));
1262
1263 if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP)))
1264 return false;
13b5b7fd
SN		 1265
1266 return true;
1267}
1268
0507ef8a
SN		 1269/**
1270 * igc_cleanup_headers - Correct corrupted or empty headers
1271 * @rx_ring: rx descriptor ring packet is being transacted on
1272 * @rx_desc: pointer to the EOP Rx descriptor
1273 * @skb: pointer to current skb being fixed
1274 *
1275 * Address the case where we are pulling data in on pages only
1276 * and as such no data is present in the skb header.
1277 *
1278 * In addition if skb is not at least 60 bytes we need to pad it so that
1279 * it is large enough to qualify as a valid Ethernet frame.
1280 *
1281 * Returns true if an error was encountered and skb was freed.
1282 */
1283static bool igc_cleanup_headers(struct igc_ring *rx_ring,
1284 union igc_adv_rx_desc *rx_desc,
1285 struct sk_buff *skb)
1286{
1287 if (unlikely((igc_test_staterr(rx_desc,
1288 IGC_RXDEXT_ERR_FRAME_ERR_MASK)))) {
1289 struct net_device *netdev = rx_ring->netdev;
1290
1291 if (!(netdev->features & NETIF_F_RXALL)) {
1292 dev_kfree_skb_any(skb);
1293 return true;
1294 }
1295 }
1296
1297 /* if eth_skb_pad returns an error the skb was freed */
1298 if (eth_skb_pad(skb))
1299 return true;
1300
1301 return false;
1302}
1303
1304static void igc_put_rx_buffer(struct igc_ring *rx_ring,
1305 struct igc_rx_buffer *rx_buffer)
1306{
1307 if (igc_can_reuse_rx_page(rx_buffer)) {
1308 /* hand second half of page back to the ring */
1309 igc_reuse_rx_page(rx_ring, rx_buffer);
1310 } else {
1311 /* We are not reusing the buffer so unmap it and free
1312 * any references we are holding to it
1313 */
1314 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
1315 igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
1316 IGC_RX_DMA_ATTR);
1317 __page_frag_cache_drain(rx_buffer->page,
1318 rx_buffer->pagecnt_bias);
1319 }
1320
1321 /* clear contents of rx_buffer */
1322 rx_buffer->page = NULL;
1323}
1324
13b5b7fd
SN		 1325/**
1326 * igc_alloc_rx_buffers - Replace used receive buffers; packet split
1327 * @adapter: address of board private structure
1328 */
1329static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count)
1330{
1331 union igc_adv_rx_desc *rx_desc;
1332 u16 i = rx_ring->next_to_use;
1333 struct igc_rx_buffer *bi;
1334 u16 bufsz;
1335
1336 /* nothing to do */
1337 if (!cleaned_count)
1338 return;
1339
1340 rx_desc = IGC_RX_DESC(rx_ring, i);
1341 bi = &rx_ring->rx_buffer_info[i];
1342 i -= rx_ring->count;
1343
1344 bufsz = igc_rx_bufsz(rx_ring);
1345
1346 do {
1347 if (!igc_alloc_mapped_page(rx_ring, bi))
1348 break;
1349
1350 /* sync the buffer for use by the device */
1351 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1352 bi->page_offset, bufsz,
1353 DMA_FROM_DEVICE);
1354
1355 /* Refresh the desc even if buffer_addrs didn't change
1356 * because each write-back erases this info.
1357 */
1358 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1359
1360 rx_desc++;
1361 bi++;
1362 i++;
1363 if (unlikely(!i)) {
1364 rx_desc = IGC_RX_DESC(rx_ring, 0);
1365 bi = rx_ring->rx_buffer_info;
1366 i -= rx_ring->count;
1367 }
1368
1369 /* clear the length for the next_to_use descriptor */
1370 rx_desc->wb.upper.length = 0;
1371
1372 cleaned_count--;
1373 } while (cleaned_count);
1374
1375 i += rx_ring->count;
1376
1377 if (rx_ring->next_to_use != i) {
1378 /* record the next descriptor to use */
1379 rx_ring->next_to_use = i;
1380
1381 /* update next to alloc since we have filled the ring */
1382 rx_ring->next_to_alloc = i;
1383
1384 /* Force memory writes to complete before letting h/w
1385 * know there are new descriptors to fetch. (Only
1386 * applicable for weak-ordered memory model archs,
1387 * such as IA-64).
1388 */
1389 wmb();
1390 writel(i, rx_ring->tail);
1391 }
1392}
1393
0507ef8a
SN		 1394static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget)
1395{
1396 unsigned int total_bytes = 0, total_packets = 0;
1397 struct igc_ring *rx_ring = q_vector->rx.ring;
1398 struct sk_buff *skb = rx_ring->skb;
1399 u16 cleaned_count = igc_desc_unused(rx_ring);
1400
1401 while (likely(total_packets < budget)) {
1402 union igc_adv_rx_desc *rx_desc;
1403 struct igc_rx_buffer *rx_buffer;
1404 unsigned int size;
1405
1406 /* return some buffers to hardware, one at a time is too slow */
1407 if (cleaned_count >= IGC_RX_BUFFER_WRITE) {
1408 igc_alloc_rx_buffers(rx_ring, cleaned_count);
1409 cleaned_count = 0;
1410 }
1411
1412 rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean);
1413 size = le16_to_cpu(rx_desc->wb.upper.length);
1414 if (!size)
1415 break;
1416
1417 /* This memory barrier is needed to keep us from reading
1418 * any other fields out of the rx_desc until we know the
1419 * descriptor has been written back
1420 */
1421 dma_rmb();
1422
1423 rx_buffer = igc_get_rx_buffer(rx_ring, size);
1424
1425 /* retrieve a buffer from the ring */
1426 if (skb)
1427 igc_add_rx_frag(rx_ring, rx_buffer, skb, size);
1428 else if (ring_uses_build_skb(rx_ring))
1429 skb = igc_build_skb(rx_ring, rx_buffer, rx_desc, size);
1430 else
1431 skb = igc_construct_skb(rx_ring, rx_buffer,
1432 rx_desc, size);
1433
1434 /* exit if we failed to retrieve a buffer */
1435 if (!skb) {
1436 rx_ring->rx_stats.alloc_failed++;
1437 rx_buffer->pagecnt_bias++;
1438 break;
1439 }
1440
1441 igc_put_rx_buffer(rx_ring, rx_buffer);
1442 cleaned_count++;
1443
1444 /* fetch next buffer in frame if non-eop */
1445 if (igc_is_non_eop(rx_ring, rx_desc))
1446 continue;
1447
1448 /* verify the packet layout is correct */
1449 if (igc_cleanup_headers(rx_ring, rx_desc, skb)) {
1450 skb = NULL;
1451 continue;
1452 }
1453
1454 /* probably a little skewed due to removing CRC */
1455 total_bytes += skb->len;
1456
1457 /* populate checksum, timestamp, VLAN, and protocol */
1458 igc_process_skb_fields(rx_ring, rx_desc, skb);
1459
1460 napi_gro_receive(&q_vector->napi, skb);
1461
1462 /* reset skb pointer */
1463 skb = NULL;
1464
1465 /* update budget accounting */
1466 total_packets++;
1467 }
1468
1469 /* place incomplete frames back on ring for completion */
1470 rx_ring->skb = skb;
1471
1472 u64_stats_update_begin(&rx_ring->rx_syncp);
1473 rx_ring->rx_stats.packets += total_packets;
1474 rx_ring->rx_stats.bytes += total_bytes;
1475 u64_stats_update_end(&rx_ring->rx_syncp);
1476 q_vector->rx.total_packets += total_packets;
1477 q_vector->rx.total_bytes += total_bytes;
1478
1479 if (cleaned_count)
1480 igc_alloc_rx_buffers(rx_ring, cleaned_count);
1481
1482 return total_packets;
1483}
1484
1485static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring)
1486{
1487 return ring_uses_build_skb(rx_ring) ? IGC_SKB_PAD : 0;
1488}
1489
1490static bool igc_alloc_mapped_page(struct igc_ring *rx_ring,
1491 struct igc_rx_buffer *bi)
1492{
1493 struct page *page = bi->page;
1494 dma_addr_t dma;
1495
1496 /* since we are recycling buffers we should seldom need to alloc */
1497 if (likely(page))
1498 return true;
1499
1500 /* alloc new page for storage */
1501 page = dev_alloc_pages(igc_rx_pg_order(rx_ring));
1502 if (unlikely(!page)) {
1503 rx_ring->rx_stats.alloc_failed++;
1504 return false;
1505 }
1506
1507 /* map page for use */
1508 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1509 igc_rx_pg_size(rx_ring),
1510 DMA_FROM_DEVICE,
1511 IGC_RX_DMA_ATTR);
1512
1513 /* if mapping failed free memory back to system since
1514 * there isn't much point in holding memory we can't use
1515 */
1516 if (dma_mapping_error(rx_ring->dev, dma)) {
1517 __free_page(page);
1518
1519 rx_ring->rx_stats.alloc_failed++;
1520 return false;
1521 }
1522
1523 bi->dma = dma;
1524 bi->page = page;
1525 bi->page_offset = igc_rx_offset(rx_ring);
1526 bi->pagecnt_bias = 1;
1527
1528 return true;
1529}
1530
1531/**
1532 * igc_clean_tx_irq - Reclaim resources after transmit completes
1533 * @q_vector: pointer to q_vector containing needed info
1534 * @napi_budget: Used to determine if we are in netpoll
1535 *
1536 * returns true if ring is completely cleaned
1537 */
1538static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget)
1539{
1540 struct igc_adapter *adapter = q_vector->adapter;
1541 unsigned int total_bytes = 0, total_packets = 0;
1542 unsigned int budget = q_vector->tx.work_limit;
1543 struct igc_ring *tx_ring = q_vector->tx.ring;
1544 unsigned int i = tx_ring->next_to_clean;
1545 struct igc_tx_buffer *tx_buffer;
1546 union igc_adv_tx_desc *tx_desc;
1547
1548 if (test_bit(__IGC_DOWN, &adapter->state))
1549 return true;
1550
1551 tx_buffer = &tx_ring->tx_buffer_info[i];
1552 tx_desc = IGC_TX_DESC(tx_ring, i);
1553 i -= tx_ring->count;
1554
1555 do {
1556 union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1557
1558 /* if next_to_watch is not set then there is no work pending */
1559 if (!eop_desc)
1560 break;
1561
1562 /* prevent any other reads prior to eop_desc */
1563 smp_rmb();
1564
1565 /* if DD is not set pending work has not been completed */
1566 if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD)))
1567 break;
1568
1569 /* clear next_to_watch to prevent false hangs */
1570 tx_buffer->next_to_watch = NULL;
1571
1572 /* update the statistics for this packet */
1573 total_bytes += tx_buffer->bytecount;
1574 total_packets += tx_buffer->gso_segs;
1575
1576 /* free the skb */
1577 napi_consume_skb(tx_buffer->skb, napi_budget);
1578
1579 /* unmap skb header data */
1580 dma_unmap_single(tx_ring->dev,
1581 dma_unmap_addr(tx_buffer, dma),
1582 dma_unmap_len(tx_buffer, len),
1583 DMA_TO_DEVICE);
1584
1585 /* clear tx_buffer data */
1586 dma_unmap_len_set(tx_buffer, len, 0);
1587
1588 /* clear last DMA location and unmap remaining buffers */
1589 while (tx_desc != eop_desc) {
1590 tx_buffer++;
1591 tx_desc++;
1592 i++;
1593 if (unlikely(!i)) {
1594 i -= tx_ring->count;
1595 tx_buffer = tx_ring->tx_buffer_info;
1596 tx_desc = IGC_TX_DESC(tx_ring, 0);
1597 }
1598
1599 /* unmap any remaining paged data */
1600 if (dma_unmap_len(tx_buffer, len)) {
1601 dma_unmap_page(tx_ring->dev,
1602 dma_unmap_addr(tx_buffer, dma),
1603 dma_unmap_len(tx_buffer, len),
1604 DMA_TO_DEVICE);
1605 dma_unmap_len_set(tx_buffer, len, 0);
1606 }
1607 }
1608
1609 /* move us one more past the eop_desc for start of next pkt */
1610 tx_buffer++;
1611 tx_desc++;
1612 i++;
1613 if (unlikely(!i)) {
1614 i -= tx_ring->count;
1615 tx_buffer = tx_ring->tx_buffer_info;
1616 tx_desc = IGC_TX_DESC(tx_ring, 0);
1617 }
1618
1619 /* issue prefetch for next Tx descriptor */
1620 prefetch(tx_desc);
1621
1622 /* update budget accounting */
1623 budget--;
1624 } while (likely(budget));
1625
1626 netdev_tx_completed_queue(txring_txq(tx_ring),
1627 total_packets, total_bytes);
1628
1629 i += tx_ring->count;
1630 tx_ring->next_to_clean = i;
1631 u64_stats_update_begin(&tx_ring->tx_syncp);
1632 tx_ring->tx_stats.bytes += total_bytes;
1633 tx_ring->tx_stats.packets += total_packets;
1634 u64_stats_update_end(&tx_ring->tx_syncp);
1635 q_vector->tx.total_bytes += total_bytes;
1636 q_vector->tx.total_packets += total_packets;
1637
1638 if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
1639 struct igc_hw *hw = &adapter->hw;
1640
1641 /* Detect a transmit hang in hardware, this serializes the
1642 * check with the clearing of time_stamp and movement of i
1643 */
1644 clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
1645 if (tx_buffer->next_to_watch &&
1646 time_after(jiffies, tx_buffer->time_stamp +
1647 (adapter->tx_timeout_factor * HZ)) &&
1648 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF)) {
1649 /* detected Tx unit hang */
1650 dev_err(tx_ring->dev,
1651 "Detected Tx Unit Hang\n"
1652 " Tx Queue <%d>\n"
1653 " TDH <%x>\n"
1654 " TDT <%x>\n"
1655 " next_to_use <%x>\n"
1656 " next_to_clean <%x>\n"
1657 "buffer_info[next_to_clean]\n"
1658 " time_stamp <%lx>\n"
1659 " next_to_watch <%p>\n"
1660 " jiffies <%lx>\n"
1661 " desc.status <%x>\n",
1662 tx_ring->queue_index,
1663 rd32(IGC_TDH(tx_ring->reg_idx)),
1664 readl(tx_ring->tail),
1665 tx_ring->next_to_use,
1666 tx_ring->next_to_clean,
1667 tx_buffer->time_stamp,
1668 tx_buffer->next_to_watch,
1669 jiffies,
1670 tx_buffer->next_to_watch->wb.status);
bb9089b6
DC		 1671 netif_stop_subqueue(tx_ring->netdev,
1672 tx_ring->queue_index);
0507ef8a
SN		 1673
1674 /* we are about to reset, no point in enabling stuff */
1675 return true;
1676 }
1677 }
1678
1679#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1680 if (unlikely(total_packets &&
1681 netif_carrier_ok(tx_ring->netdev) &&
1682 igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
1683 /* Make sure that anybody stopping the queue after this
1684 * sees the new next_to_clean.
1685 */
1686 smp_mb();
1687 if (__netif_subqueue_stopped(tx_ring->netdev,
1688 tx_ring->queue_index) &&
1689 !(test_bit(__IGC_DOWN, &adapter->state))) {
1690 netif_wake_subqueue(tx_ring->netdev,
1691 tx_ring->queue_index);
1692
1693 u64_stats_update_begin(&tx_ring->tx_syncp);
1694 tx_ring->tx_stats.restart_queue++;
1695 u64_stats_update_end(&tx_ring->tx_syncp);
1696 }
1697 }
1698
1699 return !!budget;
1700}
1701
c9a11c23
SN		 1702/**
1703 * igc_up - Open the interface and prepare it to handle traffic
1704 * @adapter: board private structure
1705 */
1706static void igc_up(struct igc_adapter *adapter)
1707{
3df25e4c 1708 struct igc_hw *hw = &adapter->hw;
c9a11c23
SN		 1709 int i = 0;
1710
1711 /* hardware has been reset, we need to reload some things */
1712 igc_configure(adapter);
1713
1714 clear_bit(__IGC_DOWN, &adapter->state);
1715
1716 for (i = 0; i < adapter->num_q_vectors; i++)
1717 napi_enable(&adapter->q_vector[i]->napi);
3df25e4c
SN		 1718
1719 if (adapter->msix_entries)
1720 igc_configure_msix(adapter);
1721 else
1722 igc_assign_vector(adapter->q_vector[0], 0);
1723
1724 /* Clear any pending interrupts. */
1725 rd32(IGC_ICR);
1726 igc_irq_enable(adapter);
13b5b7fd
SN		 1727
1728 netif_tx_start_all_queues(adapter->netdev);
1729
1730 /* start the watchdog. */
1731 hw->mac.get_link_status = 1;
208983f0 1732 schedule_work(&adapter->watchdog_task);
c9a11c23
SN		 1733}
1734
1735/**
1736 * igc_update_stats - Update the board statistics counters
1737 * @adapter: board private structure
1738 */
1739static void igc_update_stats(struct igc_adapter *adapter)
1740{
1741}
1742
0507ef8a
SN		 1743static void igc_nfc_filter_exit(struct igc_adapter *adapter)
1744{
1745}
1746
c9a11c23
SN		 1747/**
1748 * igc_down - Close the interface
1749 * @adapter: board private structure
1750 */
1751static void igc_down(struct igc_adapter *adapter)
1752{
1753 struct net_device *netdev = adapter->netdev;
0507ef8a
SN		 1754 struct igc_hw *hw = &adapter->hw;
1755 u32 tctl, rctl;
c9a11c23
SN		 1756 int i = 0;
1757
1758 set_bit(__IGC_DOWN, &adapter->state);
1759
0507ef8a
SN		 1760 /* disable receives in the hardware */
1761 rctl = rd32(IGC_RCTL);
1762 wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN);
1763 /* flush and sleep below */
1764
1765 igc_nfc_filter_exit(adapter);
1766
c9a11c23
SN		 1767 /* set trans_start so we don't get spurious watchdogs during reset */
1768 netif_trans_update(netdev);
1769
1770 netif_carrier_off(netdev);
1771 netif_tx_stop_all_queues(netdev);
1772
0507ef8a
SN		 1773 /* disable transmits in the hardware */
1774 tctl = rd32(IGC_TCTL);
1775 tctl &= ~IGC_TCTL_EN;
1776 wr32(IGC_TCTL, tctl);
1777 /* flush both disables and wait for them to finish */
1778 wrfl();
1779 usleep_range(10000, 20000);
1780
1781 igc_irq_disable(adapter);
1782
1783 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
1784
1785 for (i = 0; i < adapter->num_q_vectors; i++) {
1786 if (adapter->q_vector[i]) {
1787 napi_synchronize(&adapter->q_vector[i]->napi);
1788 napi_disable(&adapter->q_vector[i]->napi);
1789 }
1790 }
1791
1792 del_timer_sync(&adapter->watchdog_timer);
1793 del_timer_sync(&adapter->phy_info_timer);
1794
1795 /* record the stats before reset*/
1796 spin_lock(&adapter->stats64_lock);
1797 igc_update_stats(adapter);
1798 spin_unlock(&adapter->stats64_lock);
c9a11c23
SN		 1799
1800 adapter->link_speed = 0;
1801 adapter->link_duplex = 0;
0507ef8a
SN		 1802
1803 if (!pci_channel_offline(adapter->pdev))
1804 igc_reset(adapter);
1805
1806 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1807 adapter->flags &= ~IGC_FLAG_VLAN_PROMISC;
1808
1809 igc_clean_all_tx_rings(adapter);
1810 igc_clean_all_rx_rings(adapter);
1811}
1812
1813static void igc_reinit_locked(struct igc_adapter *adapter)
1814{
1815 WARN_ON(in_interrupt());
1816 while (test_and_set_bit(__IGC_RESETTING, &adapter->state))
1817 usleep_range(1000, 2000);
1818 igc_down(adapter);
1819 igc_up(adapter);
1820 clear_bit(__IGC_RESETTING, &adapter->state);
1821}
1822
1823static void igc_reset_task(struct work_struct *work)
1824{
1825 struct igc_adapter *adapter;
1826
1827 adapter = container_of(work, struct igc_adapter, reset_task);
1828
1829 netdev_err(adapter->netdev, "Reset adapter\n");
1830 igc_reinit_locked(adapter);
c9a11c23
SN		 1831}
1832
1833/**
1834 * igc_change_mtu - Change the Maximum Transfer Unit
1835 * @netdev: network interface device structure
1836 * @new_mtu: new value for maximum frame size
1837 *
1838 * Returns 0 on success, negative on failure
1839 */
1840static int igc_change_mtu(struct net_device *netdev, int new_mtu)
1841{
1842 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
1843 struct igc_adapter *adapter = netdev_priv(netdev);
1844 struct pci_dev *pdev = adapter->pdev;
1845
1846 /* adjust max frame to be at least the size of a standard frame */
1847 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
1848 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
1849
1850 while (test_and_set_bit(__IGC_RESETTING, &adapter->state))
1851 usleep_range(1000, 2000);
1852
1853 /* igc_down has a dependency on max_frame_size */
1854 adapter->max_frame_size = max_frame;
1855
1856 if (netif_running(netdev))
1857 igc_down(adapter);
1858
1859 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
1860 netdev->mtu, new_mtu);
1861 netdev->mtu = new_mtu;
1862
1863 if (netif_running(netdev))
1864 igc_up(adapter);
1865 else
1866 igc_reset(adapter);
1867
1868 clear_bit(__IGC_RESETTING, &adapter->state);
1869
1870 return 0;
1871}
1872
1873/**
1874 * igc_get_stats - Get System Network Statistics
1875 * @netdev: network interface device structure
1876 *
1877 * Returns the address of the device statistics structure.
1878 * The statistics are updated here and also from the timer callback.
1879 */
1880static struct net_device_stats *igc_get_stats(struct net_device *netdev)
1881{
1882 struct igc_adapter *adapter = netdev_priv(netdev);
1883
1884 if (!test_bit(__IGC_RESETTING, &adapter->state))
1885 igc_update_stats(adapter);
1886
1887 /* only return the current stats */
1888 return &netdev->stats;
1889}
1890
1891/**
1892 * igc_configure - configure the hardware for RX and TX
1893 * @adapter: private board structure
1894 */
1895static void igc_configure(struct igc_adapter *adapter)
1896{
13b5b7fd
SN		 1897 struct net_device *netdev = adapter->netdev;
1898 int i = 0;
1899
c9a11c23 1900 igc_get_hw_control(adapter);
13b5b7fd
SN		 1901 igc_set_rx_mode(netdev);
1902
1903 igc_setup_tctl(adapter);
1904 igc_setup_mrqc(adapter);
1905 igc_setup_rctl(adapter);
1906
1907 igc_configure_tx(adapter);
1908 igc_configure_rx(adapter);
1909
1910 igc_rx_fifo_flush_base(&adapter->hw);
1911
1912 /* call igc_desc_unused which always leaves
1913 * at least 1 descriptor unused to make sure
1914 * next_to_use != next_to_clean
1915 */
1916 for (i = 0; i < adapter->num_rx_queues; i++) {
1917 struct igc_ring *ring = adapter->rx_ring[i];
1918
1919 igc_alloc_rx_buffers(ring, igc_desc_unused(ring));
1920 }
c9a11c23
SN		 1921}
1922
1923/**
1924 * igc_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
1925 * @adapter: Pointer to adapter structure
1926 * @index: Index of the RAR entry which need to be synced with MAC table
1927 */
1928static void igc_rar_set_index(struct igc_adapter *adapter, u32 index)
1929{
1930 u8 *addr = adapter->mac_table[index].addr;
1931 struct igc_hw *hw = &adapter->hw;
1932 u32 rar_low, rar_high;
1933
1934 /* HW expects these to be in network order when they are plugged
1935 * into the registers which are little endian. In order to guarantee
1936 * that ordering we need to do an leXX_to_cpup here in order to be
1937 * ready for the byteswap that occurs with writel
1938 */
1939 rar_low = le32_to_cpup((__le32 *)(addr));
1940 rar_high = le16_to_cpup((__le16 *)(addr + 4));
1941
1942 /* Indicate to hardware the Address is Valid. */
1943 if (adapter->mac_table[index].state & IGC_MAC_STATE_IN_USE) {
1944 if (is_valid_ether_addr(addr))
1945 rar_high |= IGC_RAH_AV;
1946
1947 rar_high |= IGC_RAH_POOL_1 <<
1948 adapter->mac_table[index].queue;
1949 }
1950
1951 wr32(IGC_RAL(index), rar_low);
1952 wrfl();
1953 wr32(IGC_RAH(index), rar_high);
1954 wrfl();
1955}
1956
1957/* Set default MAC address for the PF in the first RAR entry */
1958static void igc_set_default_mac_filter(struct igc_adapter *adapter)
1959{
1960 struct igc_mac_addr *mac_table = &adapter->mac_table[0];
1961
1962 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
1963 mac_table->state = IGC_MAC_STATE_DEFAULT | IGC_MAC_STATE_IN_USE;
1964
1965 igc_rar_set_index(adapter, 0);
1966}
1967
13b5b7fd
SN		 1968/**
1969 * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
1970 * @netdev: network interface device structure
1971 *
1972 * The set_rx_mode entry point is called whenever the unicast or multicast
1973 * address lists or the network interface flags are updated. This routine is
1974 * responsible for configuring the hardware for proper unicast, multicast,
1975 * promiscuous mode, and all-multi behavior.
1976 */
1977static void igc_set_rx_mode(struct net_device *netdev)
1978{
1979}
1980
3df25e4c
SN		 1981/**
1982 * igc_msix_other - msix other interrupt handler
1983 * @irq: interrupt number
1984 * @data: pointer to a q_vector
1985 */
1986static irqreturn_t igc_msix_other(int irq, void *data)
1987{
1988 struct igc_adapter *adapter = data;
1989 struct igc_hw *hw = &adapter->hw;
1990 u32 icr = rd32(IGC_ICR);
1991
1992 /* reading ICR causes bit 31 of EICR to be cleared */
1993 if (icr & IGC_ICR_DRSTA)
1994 schedule_work(&adapter->reset_task);
1995
1996 if (icr & IGC_ICR_DOUTSYNC) {
1997 /* HW is reporting DMA is out of sync */
1998 adapter->stats.doosync++;
1999 }
2000
2001 if (icr & IGC_ICR_LSC) {
2002 hw->mac.get_link_status = 1;
2003 /* guard against interrupt when we're going down */
2004 if (!test_bit(__IGC_DOWN, &adapter->state))
2005 mod_timer(&adapter->watchdog_timer, jiffies + 1);
2006 }
2007
2008 wr32(IGC_EIMS, adapter->eims_other);
2009
2010 return IRQ_HANDLED;
2011}
2012
2013/**
2014 * igc_write_ivar - configure ivar for given MSI-X vector
2015 * @hw: pointer to the HW structure
2016 * @msix_vector: vector number we are allocating to a given ring
2017 * @index: row index of IVAR register to write within IVAR table
2018 * @offset: column offset of in IVAR, should be multiple of 8
2019 *
2020 * The IVAR table consists of 2 columns,
2021 * each containing an cause allocation for an Rx and Tx ring, and a
2022 * variable number of rows depending on the number of queues supported.
2023 */
2024static void igc_write_ivar(struct igc_hw *hw, int msix_vector,
2025 int index, int offset)
2026{
2027 u32 ivar = array_rd32(IGC_IVAR0, index);
2028
2029 /* clear any bits that are currently set */
2030 ivar &= ~((u32)0xFF << offset);
2031
2032 /* write vector and valid bit */
2033 ivar |= (msix_vector | IGC_IVAR_VALID) << offset;
2034
2035 array_wr32(IGC_IVAR0, index, ivar);
2036}
2037
2038static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector)
2039{
2040 struct igc_adapter *adapter = q_vector->adapter;
2041 struct igc_hw *hw = &adapter->hw;
2042 int rx_queue = IGC_N0_QUEUE;
2043 int tx_queue = IGC_N0_QUEUE;
2044
2045 if (q_vector->rx.ring)
2046 rx_queue = q_vector->rx.ring->reg_idx;
2047 if (q_vector->tx.ring)
2048 tx_queue = q_vector->tx.ring->reg_idx;
2049
2050 switch (hw->mac.type) {
2051 case igc_i225:
2052 if (rx_queue > IGC_N0_QUEUE)
2053 igc_write_ivar(hw, msix_vector,
2054 rx_queue >> 1,
2055 (rx_queue & 0x1) << 4);
2056 if (tx_queue > IGC_N0_QUEUE)
2057 igc_write_ivar(hw, msix_vector,
2058 tx_queue >> 1,
2059 ((tx_queue & 0x1) << 4) + 8);
2060 q_vector->eims_value = BIT(msix_vector);
2061 break;
2062 default:
2063 WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n");
2064 break;
2065 }
2066
2067 /* add q_vector eims value to global eims_enable_mask */
2068 adapter->eims_enable_mask |= q_vector->eims_value;
2069
2070 /* configure q_vector to set itr on first interrupt */
2071 q_vector->set_itr = 1;
2072}
2073
2074/**
2075 * igc_configure_msix - Configure MSI-X hardware
2076 * @adapter: Pointer to adapter structure
2077 *
2078 * igc_configure_msix sets up the hardware to properly
2079 * generate MSI-X interrupts.
2080 */
2081static void igc_configure_msix(struct igc_adapter *adapter)
2082{
2083 struct igc_hw *hw = &adapter->hw;
2084 int i, vector = 0;
2085 u32 tmp;
2086
2087 adapter->eims_enable_mask = 0;
2088
2089 /* set vector for other causes, i.e. link changes */
2090 switch (hw->mac.type) {
2091 case igc_i225:
2092 /* Turn on MSI-X capability first, or our settings
2093 * won't stick. And it will take days to debug.
2094 */
2095 wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE |
2096 IGC_GPIE_PBA | IGC_GPIE_EIAME |
2097 IGC_GPIE_NSICR);
2098
2099 /* enable msix_other interrupt */
2100 adapter->eims_other = BIT(vector);
2101 tmp = (vector++ | IGC_IVAR_VALID) << 8;
2102
2103 wr32(IGC_IVAR_MISC, tmp);
2104 break;
2105 default:
2106 /* do nothing, since nothing else supports MSI-X */
2107 break;
2108 } /* switch (hw->mac.type) */
2109
2110 adapter->eims_enable_mask |= adapter->eims_other;
2111
2112 for (i = 0; i < adapter->num_q_vectors; i++)
2113 igc_assign_vector(adapter->q_vector[i], vector++);
2114
2115 wrfl();
2116}
2117
2118static irqreturn_t igc_msix_ring(int irq, void *data)
2119{
2120 struct igc_q_vector *q_vector = data;
2121
2122 /* Write the ITR value calculated from the previous interrupt. */
2123 igc_write_itr(q_vector);
2124
2125 napi_schedule(&q_vector->napi);
2126
2127 return IRQ_HANDLED;
2128}
2129
2130/**
2131 * igc_request_msix - Initialize MSI-X interrupts
2132 * @adapter: Pointer to adapter structure
2133 *
2134 * igc_request_msix allocates MSI-X vectors and requests interrupts from the
2135 * kernel.
2136 */
2137static int igc_request_msix(struct igc_adapter *adapter)
2138{
2139 int i = 0, err = 0, vector = 0, free_vector = 0;
2140 struct net_device *netdev = adapter->netdev;
2141
2142 err = request_irq(adapter->msix_entries[vector].vector,
2143 &igc_msix_other, 0, netdev->name, adapter);
2144 if (err)
2145 goto err_out;
2146
2147 for (i = 0; i < adapter->num_q_vectors; i++) {
2148 struct igc_q_vector *q_vector = adapter->q_vector[i];
2149
2150 vector++;
2151
2152 q_vector->itr_register = adapter->io_addr + IGC_EITR(vector);
2153
2154 if (q_vector->rx.ring && q_vector->tx.ring)
2155 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
2156 q_vector->rx.ring->queue_index);
2157 else if (q_vector->tx.ring)
2158 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
2159 q_vector->tx.ring->queue_index);
2160 else if (q_vector->rx.ring)
2161 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
2162 q_vector->rx.ring->queue_index);
2163 else
2164 sprintf(q_vector->name, "%s-unused", netdev->name);
2165
2166 err = request_irq(adapter->msix_entries[vector].vector,
2167 igc_msix_ring, 0, q_vector->name,
2168 q_vector);
2169 if (err)
2170 goto err_free;
2171 }
2172
2173 igc_configure_msix(adapter);
2174 return 0;
2175
2176err_free:
2177 /* free already assigned IRQs */
2178 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
2179
2180 vector--;
2181 for (i = 0; i < vector; i++) {
2182 free_irq(adapter->msix_entries[free_vector++].vector,
2183 adapter->q_vector[i]);
2184 }
2185err_out:
2186 return err;
2187}
2188
2189/**
2190 * igc_reset_q_vector - Reset config for interrupt vector
2191 * @adapter: board private structure to initialize
2192 * @v_idx: Index of vector to be reset
2193 *
2194 * If NAPI is enabled it will delete any references to the
2195 * NAPI struct. This is preparation for igc_free_q_vector.
2196 */
2197static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx)
2198{
2199 struct igc_q_vector *q_vector = adapter->q_vector[v_idx];
2200
2201 /* if we're coming from igc_set_interrupt_capability, the vectors are
2202 * not yet allocated
2203 */
2204 if (!q_vector)
2205 return;
2206
2207 if (q_vector->tx.ring)
2208 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
2209
2210 if (q_vector->rx.ring)
2211 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
2212
2213 netif_napi_del(&q_vector->napi);
2214}
2215
2216static void igc_reset_interrupt_capability(struct igc_adapter *adapter)
2217{
2218 int v_idx = adapter->num_q_vectors;
2219
2220 if (adapter->msix_entries) {
2221 pci_disable_msix(adapter->pdev);
2222 kfree(adapter->msix_entries);
2223 adapter->msix_entries = NULL;
2224 } else if (adapter->flags & IGC_FLAG_HAS_MSI) {
2225 pci_disable_msi(adapter->pdev);
2226 }
2227
2228 while (v_idx--)
2229 igc_reset_q_vector(adapter, v_idx);
2230}
2231
2232/**
2233 * igc_clear_interrupt_scheme - reset the device to a state of no interrupts
2234 * @adapter: Pointer to adapter structure
2235 *
2236 * This function resets the device so that it has 0 rx queues, tx queues, and
2237 * MSI-X interrupts allocated.
2238 */
2239static void igc_clear_interrupt_scheme(struct igc_adapter *adapter)
2240{
2241 igc_free_q_vectors(adapter);
2242 igc_reset_interrupt_capability(adapter);
2243}
2244
2245/**
2246 * igc_free_q_vectors - Free memory allocated for interrupt vectors
2247 * @adapter: board private structure to initialize
2248 *
2249 * This function frees the memory allocated to the q_vectors. In addition if
2250 * NAPI is enabled it will delete any references to the NAPI struct prior
2251 * to freeing the q_vector.
2252 */
2253static void igc_free_q_vectors(struct igc_adapter *adapter)
2254{
2255 int v_idx = adapter->num_q_vectors;
2256
2257 adapter->num_tx_queues = 0;
2258 adapter->num_rx_queues = 0;
2259 adapter->num_q_vectors = 0;
2260
2261 while (v_idx--) {
2262 igc_reset_q_vector(adapter, v_idx);
2263 igc_free_q_vector(adapter, v_idx);
2264 }
2265}
2266
2267/**
2268 * igc_free_q_vector - Free memory allocated for specific interrupt vector
2269 * @adapter: board private structure to initialize
2270 * @v_idx: Index of vector to be freed
2271 *
2272 * This function frees the memory allocated to the q_vector.
2273 */
2274static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx)
2275{
2276 struct igc_q_vector *q_vector = adapter->q_vector[v_idx];
2277
2278 adapter->q_vector[v_idx] = NULL;
2279
2280 /* igc_get_stats64() might access the rings on this vector,
2281 * we must wait a grace period before freeing it.
2282 */
2283 if (q_vector)
2284 kfree_rcu(q_vector, rcu);
2285}
2286
208983f0
SN		 2287/* Need to wait a few seconds after link up to get diagnostic information from
2288 * the phy
2289 */
2290static void igc_update_phy_info(struct timer_list *t)
2291{
2292 struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer);
2293
2294 igc_get_phy_info(&adapter->hw);
2295}
2296
2297/**
2298 * igc_has_link - check shared code for link and determine up/down
2299 * @adapter: pointer to driver private info
2300 */
2301static bool igc_has_link(struct igc_adapter *adapter)
2302{
2303 struct igc_hw *hw = &adapter->hw;
2304 bool link_active = false;
2305
2306 /* get_link_status is set on LSC (link status) interrupt or
2307 * rx sequence error interrupt. get_link_status will stay
2308 * false until the igc_check_for_link establishes link
2309 * for copper adapters ONLY
2310 */
2311 switch (hw->phy.media_type) {
2312 case igc_media_type_copper:
2313 if (!hw->mac.get_link_status)
2314 return true;
2315 hw->mac.ops.check_for_link(hw);
2316 link_active = !hw->mac.get_link_status;
2317 break;
2318 default:
2319 case igc_media_type_unknown:
2320 break;
2321 }
2322
2323 if (hw->mac.type == igc_i225 &&
2324 hw->phy.id == I225_I_PHY_ID) {
2325 if (!netif_carrier_ok(adapter->netdev)) {
2326 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
2327 } else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) {
2328 adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE;
2329 adapter->link_check_timeout = jiffies;
2330 }
2331 }
2332
2333 return link_active;
2334}
2335
0507ef8a
SN		 2336/**
2337 * igc_watchdog - Timer Call-back
2338 * @data: pointer to adapter cast into an unsigned long
2339 */
2340static void igc_watchdog(struct timer_list *t)
2341{
2342 struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer);
208983f0
SN		 2343 /* Do the rest outside of interrupt context */
2344 schedule_work(&adapter->watchdog_task);
2345}
2346
2347static void igc_watchdog_task(struct work_struct *work)
2348{
2349 struct igc_adapter *adapter = container_of(work,
2350 struct igc_adapter,
2351 watchdog_task);
2352 struct net_device *netdev = adapter->netdev;
2353 struct igc_hw *hw = &adapter->hw;
2354 struct igc_phy_info *phy = &hw->phy;
2355 u16 phy_data, retry_count = 20;
2356 u32 connsw;
2357 u32 link;
2358 int i;
2359
2360 link = igc_has_link(adapter);
2361
2362 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) {
2363 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
2364 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
2365 else
2366 link = false;
2367 }
2368
2369 /* Force link down if we have fiber to swap to */
2370 if (adapter->flags & IGC_FLAG_MAS_ENABLE) {
2371 if (hw->phy.media_type == igc_media_type_copper) {
2372 connsw = rd32(IGC_CONNSW);
2373 if (!(connsw & IGC_CONNSW_AUTOSENSE_EN))
2374 link = 0;
2375 }
2376 }
2377 if (link) {
2378 if (!netif_carrier_ok(netdev)) {
2379 u32 ctrl;
2380
2381 hw->mac.ops.get_speed_and_duplex(hw,
2382 &adapter->link_speed,
2383 &adapter->link_duplex);
2384
2385 ctrl = rd32(IGC_CTRL);
2386 /* Link status message must follow this format */
2387 netdev_info(netdev,
2388 "igc: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
2389 netdev->name,
2390 adapter->link_speed,
2391 adapter->link_duplex == FULL_DUPLEX ?
2392 "Full" : "Half",
2393 (ctrl & IGC_CTRL_TFCE) &&
2394 (ctrl & IGC_CTRL_RFCE) ? "RX/TX" :
2395 (ctrl & IGC_CTRL_RFCE) ? "RX" :
2396 (ctrl & IGC_CTRL_TFCE) ? "TX" : "None");
2397
2398 /* check if SmartSpeed worked */
2399 igc_check_downshift(hw);
2400 if (phy->speed_downgraded)
2401 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
2402
2403 /* adjust timeout factor according to speed/duplex */
2404 adapter->tx_timeout_factor = 1;
2405 switch (adapter->link_speed) {
2406 case SPEED_10:
2407 adapter->tx_timeout_factor = 14;
2408 break;
2409 case SPEED_100:
2410 /* maybe add some timeout factor ? */
2411 break;
2412 }
2413
2414 if (adapter->link_speed != SPEED_1000)
2415 goto no_wait;
2416
2417 /* wait for Remote receiver status OK */
2418retry_read_status:
2419 if (!igc_read_phy_reg(hw, PHY_1000T_STATUS,
2420 &phy_data)) {
2421 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
2422 retry_count) {
2423 msleep(100);
2424 retry_count--;
2425 goto retry_read_status;
2426 } else if (!retry_count) {
2427 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
2428 }
2429 } else {
2430 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
2431 }
2432no_wait:
2433 netif_carrier_on(netdev);
2434
2435 /* link state has changed, schedule phy info update */
2436 if (!test_bit(__IGC_DOWN, &adapter->state))
2437 mod_timer(&adapter->phy_info_timer,
2438 round_jiffies(jiffies + 2 * HZ));
2439 }
2440 } else {
2441 if (netif_carrier_ok(netdev)) {
2442 adapter->link_speed = 0;
2443 adapter->link_duplex = 0;
2444
2445 /* Links status message must follow this format */
2446 netdev_info(netdev, "igc: %s NIC Link is Down\n",
2447 netdev->name);
2448 netif_carrier_off(netdev);
2449
2450 /* link state has changed, schedule phy info update */
2451 if (!test_bit(__IGC_DOWN, &adapter->state))
2452 mod_timer(&adapter->phy_info_timer,
2453 round_jiffies(jiffies + 2 * HZ));
2454
2455 /* link is down, time to check for alternate media */
2456 if (adapter->flags & IGC_FLAG_MAS_ENABLE) {
2457 if (adapter->flags & IGC_FLAG_MEDIA_RESET) {
2458 schedule_work(&adapter->reset_task);
2459 /* return immediately */
2460 return;
2461 }
2462 }
2463
2464 /* also check for alternate media here */
2465 } else if (!netif_carrier_ok(netdev) &&
2466 (adapter->flags & IGC_FLAG_MAS_ENABLE)) {
2467 if (adapter->flags & IGC_FLAG_MEDIA_RESET) {
2468 schedule_work(&adapter->reset_task);
2469 /* return immediately */
2470 return;
2471 }
2472 }
2473 }
2474
2475 spin_lock(&adapter->stats64_lock);
2476 igc_update_stats(adapter);
2477 spin_unlock(&adapter->stats64_lock);
2478
2479 for (i = 0; i < adapter->num_tx_queues; i++) {
2480 struct igc_ring *tx_ring = adapter->tx_ring[i];
2481
2482 if (!netif_carrier_ok(netdev)) {
2483 /* We've lost link, so the controller stops DMA,
2484 * but we've got queued Tx work that's never going
2485 * to get done, so reset controller to flush Tx.
2486 * (Do the reset outside of interrupt context).
2487 */
2488 if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) {
2489 adapter->tx_timeout_count++;
2490 schedule_work(&adapter->reset_task);
2491 /* return immediately since reset is imminent */
2492 return;
2493 }
2494 }
2495
2496 /* Force detection of hung controller every watchdog period */
2497 set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
2498 }
2499
2500 /* Cause software interrupt to ensure Rx ring is cleaned */
2501 if (adapter->flags & IGC_FLAG_HAS_MSIX) {
2502 u32 eics = 0;
2503
2504 for (i = 0; i < adapter->num_q_vectors; i++)
2505 eics |= adapter->q_vector[i]->eims_value;
2506 wr32(IGC_EICS, eics);
2507 } else {
2508 wr32(IGC_ICS, IGC_ICS_RXDMT0);
2509 }
2510
2511 /* Reset the timer */
2512 if (!test_bit(__IGC_DOWN, &adapter->state)) {
2513 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)
2514 mod_timer(&adapter->watchdog_timer,
2515 round_jiffies(jiffies + HZ));
2516 else
2517 mod_timer(&adapter->watchdog_timer,
2518 round_jiffies(jiffies + 2 * HZ));
2519 }
0507ef8a
SN		 2520}
2521
3df25e4c
SN		 2522/**
2523 * igc_update_ring_itr - update the dynamic ITR value based on packet size
2524 * @q_vector: pointer to q_vector
2525 *
2526 * Stores a new ITR value based on strictly on packet size. This
2527 * algorithm is less sophisticated than that used in igc_update_itr,
2528 * due to the difficulty of synchronizing statistics across multiple
2529 * receive rings. The divisors and thresholds used by this function
2530 * were determined based on theoretical maximum wire speed and testing
2531 * data, in order to minimize response time while increasing bulk
2532 * throughput.
2533 * NOTE: This function is called only when operating in a multiqueue
2534 * receive environment.
2535 */
2536static void igc_update_ring_itr(struct igc_q_vector *q_vector)
2537{
2538 struct igc_adapter *adapter = q_vector->adapter;
2539 int new_val = q_vector->itr_val;
2540 int avg_wire_size = 0;
2541 unsigned int packets;
2542
2543 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2544 * ints/sec - ITR timer value of 120 ticks.
2545 */
2546 switch (adapter->link_speed) {
2547 case SPEED_10:
2548 case SPEED_100:
2549 new_val = IGC_4K_ITR;
2550 goto set_itr_val;
2551 default:
2552 break;
2553 }
2554
2555 packets = q_vector->rx.total_packets;
2556 if (packets)
2557 avg_wire_size = q_vector->rx.total_bytes / packets;
2558
2559 packets = q_vector->tx.total_packets;
2560 if (packets)
2561 avg_wire_size = max_t(u32, avg_wire_size,
2562 q_vector->tx.total_bytes / packets);
2563
2564 /* if avg_wire_size isn't set no work was done */
2565 if (!avg_wire_size)
2566 goto clear_counts;
2567
2568 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2569 avg_wire_size += 24;
2570
2571 /* Don't starve jumbo frames */
2572 avg_wire_size = min(avg_wire_size, 3000);
2573
2574 /* Give a little boost to mid-size frames */
2575 if (avg_wire_size > 300 && avg_wire_size < 1200)
2576 new_val = avg_wire_size / 3;
2577 else
2578 new_val = avg_wire_size / 2;
2579
2580 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2581 if (new_val < IGC_20K_ITR &&
2582 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
2583 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
2584 new_val = IGC_20K_ITR;
2585
2586set_itr_val:
2587 if (new_val != q_vector->itr_val) {
2588 q_vector->itr_val = new_val;
2589 q_vector->set_itr = 1;
2590 }
2591clear_counts:
2592 q_vector->rx.total_bytes = 0;
2593 q_vector->rx.total_packets = 0;
2594 q_vector->tx.total_bytes = 0;
2595 q_vector->tx.total_packets = 0;
2596}
2597
2598/**
2599 * igc_update_itr - update the dynamic ITR value based on statistics
2600 * @q_vector: pointer to q_vector
2601 * @ring_container: ring info to update the itr for
2602 *
2603 * Stores a new ITR value based on packets and byte
2604 * counts during the last interrupt. The advantage of per interrupt
2605 * computation is faster updates and more accurate ITR for the current
2606 * traffic pattern. Constants in this function were computed
2607 * based on theoretical maximum wire speed and thresholds were set based
2608 * on testing data as well as attempting to minimize response time
2609 * while increasing bulk throughput.
2610 * NOTE: These calculations are only valid when operating in a single-
2611 * queue environment.
2612 */
2613static void igc_update_itr(struct igc_q_vector *q_vector,
2614 struct igc_ring_container *ring_container)
2615{
2616 unsigned int packets = ring_container->total_packets;
2617 unsigned int bytes = ring_container->total_bytes;
2618 u8 itrval = ring_container->itr;
2619
2620 /* no packets, exit with status unchanged */
2621 if (packets == 0)
2622 return;
2623
2624 switch (itrval) {
2625 case lowest_latency:
2626 /* handle TSO and jumbo frames */
2627 if (bytes / packets > 8000)
2628 itrval = bulk_latency;
2629 else if ((packets < 5) && (bytes > 512))
2630 itrval = low_latency;
2631 break;
2632 case low_latency: /* 50 usec aka 20000 ints/s */
2633 if (bytes > 10000) {
2634 /* this if handles the TSO accounting */
2635 if (bytes / packets > 8000)
2636 itrval = bulk_latency;
2637 else if ((packets < 10) || ((bytes / packets) > 1200))
2638 itrval = bulk_latency;
2639 else if ((packets > 35))
2640 itrval = lowest_latency;
2641 } else if (bytes / packets > 2000) {
2642 itrval = bulk_latency;
2643 } else if (packets <= 2 && bytes < 512) {
2644 itrval = lowest_latency;
2645 }
2646 break;
2647 case bulk_latency: /* 250 usec aka 4000 ints/s */
2648 if (bytes > 25000) {
2649 if (packets > 35)
2650 itrval = low_latency;
2651 } else if (bytes < 1500) {
2652 itrval = low_latency;
2653 }
2654 break;
2655 }
2656
2657 /* clear work counters since we have the values we need */
2658 ring_container->total_bytes = 0;
2659 ring_container->total_packets = 0;
2660
2661 /* write updated itr to ring container */
2662 ring_container->itr = itrval;
2663}
2664
13b5b7fd
SN		 2665/**
2666 * igc_intr_msi - Interrupt Handler
2667 * @irq: interrupt number
2668 * @data: pointer to a network interface device structure
2669 */
2670static irqreturn_t igc_intr_msi(int irq, void *data)
2671{
2672 struct igc_adapter *adapter = data;
2673 struct igc_q_vector *q_vector = adapter->q_vector[0];
2674 struct igc_hw *hw = &adapter->hw;
2675 /* read ICR disables interrupts using IAM */
2676 u32 icr = rd32(IGC_ICR);
2677
2678 igc_write_itr(q_vector);
2679
2680 if (icr & IGC_ICR_DRSTA)
2681 schedule_work(&adapter->reset_task);
2682
2683 if (icr & IGC_ICR_DOUTSYNC) {
2684 /* HW is reporting DMA is out of sync */
2685 adapter->stats.doosync++;
2686 }
2687
2688 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
2689 hw->mac.get_link_status = 1;
2690 if (!test_bit(__IGC_DOWN, &adapter->state))
2691 mod_timer(&adapter->watchdog_timer, jiffies + 1);
2692 }
2693
2694 napi_schedule(&q_vector->napi);
2695
2696 return IRQ_HANDLED;
2697}
2698
2699/**
2700 * igc_intr - Legacy Interrupt Handler
2701 * @irq: interrupt number
2702 * @data: pointer to a network interface device structure
2703 */
2704static irqreturn_t igc_intr(int irq, void *data)
2705{
2706 struct igc_adapter *adapter = data;
2707 struct igc_q_vector *q_vector = adapter->q_vector[0];
2708 struct igc_hw *hw = &adapter->hw;
2709 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
2710 * need for the IMC write
2711 */
2712 u32 icr = rd32(IGC_ICR);
2713
2714 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
2715 * not set, then the adapter didn't send an interrupt
2716 */
2717 if (!(icr & IGC_ICR_INT_ASSERTED))
2718 return IRQ_NONE;
2719
2720 igc_write_itr(q_vector);
2721
2722 if (icr & IGC_ICR_DRSTA)
2723 schedule_work(&adapter->reset_task);
2724
2725 if (icr & IGC_ICR_DOUTSYNC) {
2726 /* HW is reporting DMA is out of sync */
2727 adapter->stats.doosync++;
2728 }
2729
2730 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
2731 hw->mac.get_link_status = 1;
2732 /* guard against interrupt when we're going down */
2733 if (!test_bit(__IGC_DOWN, &adapter->state))
2734 mod_timer(&adapter->watchdog_timer, jiffies + 1);
2735 }
2736
2737 napi_schedule(&q_vector->napi);
2738
2739 return IRQ_HANDLED;
2740}
2741
3df25e4c
SN		 2742static void igc_set_itr(struct igc_q_vector *q_vector)
2743{
2744 struct igc_adapter *adapter = q_vector->adapter;
2745 u32 new_itr = q_vector->itr_val;
2746 u8 current_itr = 0;
2747
2748 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2749 switch (adapter->link_speed) {
2750 case SPEED_10:
2751 case SPEED_100:
2752 current_itr = 0;
2753 new_itr = IGC_4K_ITR;
2754 goto set_itr_now;
2755 default:
2756 break;
2757 }
2758
2759 igc_update_itr(q_vector, &q_vector->tx);
2760 igc_update_itr(q_vector, &q_vector->rx);
2761
2762 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2763
2764 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2765 if (current_itr == lowest_latency &&
2766 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
2767 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
2768 current_itr = low_latency;
2769
2770 switch (current_itr) {
2771 /* counts and packets in update_itr are dependent on these numbers */
2772 case lowest_latency:
2773 new_itr = IGC_70K_ITR; /* 70,000 ints/sec */
2774 break;
2775 case low_latency:
2776 new_itr = IGC_20K_ITR; /* 20,000 ints/sec */
2777 break;
2778 case bulk_latency:
2779 new_itr = IGC_4K_ITR; /* 4,000 ints/sec */
2780 break;
2781 default:
2782 break;
2783 }
2784
2785set_itr_now:
2786 if (new_itr != q_vector->itr_val) {
2787 /* this attempts to bias the interrupt rate towards Bulk
2788 * by adding intermediate steps when interrupt rate is
2789 * increasing
2790 */
2791 new_itr = new_itr > q_vector->itr_val ?
2792 max((new_itr * q_vector->itr_val) /
2793 (new_itr + (q_vector->itr_val >> 2)),
2794 new_itr) : new_itr;
2795 /* Don't write the value here; it resets the adapter's
2796 * internal timer, and causes us to delay far longer than
2797 * we should between interrupts. Instead, we write the ITR
2798 * value at the beginning of the next interrupt so the timing
2799 * ends up being correct.
2800 */
2801 q_vector->itr_val = new_itr;
2802 q_vector->set_itr = 1;
2803 }
2804}
2805
2806static void igc_ring_irq_enable(struct igc_q_vector *q_vector)
2807{
2808 struct igc_adapter *adapter = q_vector->adapter;
2809 struct igc_hw *hw = &adapter->hw;
2810
2811 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
2812 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
2813 if (adapter->num_q_vectors == 1)
2814 igc_set_itr(q_vector);
2815 else
2816 igc_update_ring_itr(q_vector);
2817 }
2818
2819 if (!test_bit(__IGC_DOWN, &adapter->state)) {
2820 if (adapter->msix_entries)
2821 wr32(IGC_EIMS, q_vector->eims_value);
2822 else
2823 igc_irq_enable(adapter);
2824 }
2825}
2826
2827/**
2828 * igc_poll - NAPI Rx polling callback
2829 * @napi: napi polling structure
2830 * @budget: count of how many packets we should handle
2831 */
2832static int igc_poll(struct napi_struct *napi, int budget)
2833{
2834 struct igc_q_vector *q_vector = container_of(napi,
2835 struct igc_q_vector,
2836 napi);
2837 bool clean_complete = true;
2838 int work_done = 0;
0507ef8a
SN		 2839
2840 if (q_vector->tx.ring)
2841 clean_complete = igc_clean_tx_irq(q_vector, budget);
3df25e4c
SN		 2842
2843 if (q_vector->rx.ring) {
0507ef8a
SN		 2844 int cleaned = igc_clean_rx_irq(q_vector, budget);
2845
3df25e4c
SN		 2846 work_done += cleaned;
2847 if (cleaned >= budget)
2848 clean_complete = false;
2849 }
2850
2851 /* If all work not completed, return budget and keep polling */
2852 if (!clean_complete)
2853 return budget;
2854
0bcd952f
JB		 2855 /* Exit the polling mode, but don't re-enable interrupts if stack might
2856 * poll us due to busy-polling
2857 */
2858 if (likely(napi_complete_done(napi, work_done)))
2859 igc_ring_irq_enable(q_vector);
3df25e4c 2860
0bcd952f 2861 return min(work_done, budget - 1);
3df25e4c
SN		 2862}
2863
2864/**
2865 * igc_set_interrupt_capability - set MSI or MSI-X if supported
2866 * @adapter: Pointer to adapter structure
2867 *
2868 * Attempt to configure interrupts using the best available
2869 * capabilities of the hardware and kernel.
2870 */
2871static void igc_set_interrupt_capability(struct igc_adapter *adapter,
2872 bool msix)
2873{
2874 int numvecs, i;
2875 int err;
2876
2877 if (!msix)
2878 goto msi_only;
2879 adapter->flags |= IGC_FLAG_HAS_MSIX;
2880
2881 /* Number of supported queues. */
2882 adapter->num_rx_queues = adapter->rss_queues;
2883
2884 adapter->num_tx_queues = adapter->rss_queues;
2885
2886 /* start with one vector for every Rx queue */
2887 numvecs = adapter->num_rx_queues;
2888
2889 /* if Tx handler is separate add 1 for every Tx queue */
2890 if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS))
2891 numvecs += adapter->num_tx_queues;
2892
2893 /* store the number of vectors reserved for queues */
2894 adapter->num_q_vectors = numvecs;
2895
2896 /* add 1 vector for link status interrupts */
2897 numvecs++;
2898
2899 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
2900 GFP_KERNEL);
2901
2902 if (!adapter->msix_entries)
2903 return;
2904
2905 /* populate entry values */
2906 for (i = 0; i < numvecs; i++)
2907 adapter->msix_entries[i].entry = i;
2908
2909 err = pci_enable_msix_range(adapter->pdev,
2910 adapter->msix_entries,
2911 numvecs,
2912 numvecs);
2913 if (err > 0)
2914 return;
2915
2916 kfree(adapter->msix_entries);
2917 adapter->msix_entries = NULL;
2918
2919 igc_reset_interrupt_capability(adapter);
2920
2921msi_only:
2922 adapter->flags &= ~IGC_FLAG_HAS_MSIX;
2923
2924 adapter->rss_queues = 1;
2925 adapter->flags |= IGC_FLAG_QUEUE_PAIRS;
2926 adapter->num_rx_queues = 1;
2927 adapter->num_tx_queues = 1;
2928 adapter->num_q_vectors = 1;
2929 if (!pci_enable_msi(adapter->pdev))
2930 adapter->flags |= IGC_FLAG_HAS_MSI;
2931}
2932
2933static void igc_add_ring(struct igc_ring *ring,
2934 struct igc_ring_container *head)
2935{
2936 head->ring = ring;
2937 head->count++;
2938}
2939
2940/**
2941 * igc_alloc_q_vector - Allocate memory for a single interrupt vector
2942 * @adapter: board private structure to initialize
2943 * @v_count: q_vectors allocated on adapter, used for ring interleaving
2944 * @v_idx: index of vector in adapter struct
2945 * @txr_count: total number of Tx rings to allocate
2946 * @txr_idx: index of first Tx ring to allocate
2947 * @rxr_count: total number of Rx rings to allocate
2948 * @rxr_idx: index of first Rx ring to allocate
2949 *
2950 * We allocate one q_vector. If allocation fails we return -ENOMEM.
2951 */
2952static int igc_alloc_q_vector(struct igc_adapter *adapter,
2953 unsigned int v_count, unsigned int v_idx,
2954 unsigned int txr_count, unsigned int txr_idx,
2955 unsigned int rxr_count, unsigned int rxr_idx)
2956{
2957 struct igc_q_vector *q_vector;
2958 struct igc_ring *ring;
2959 int ring_count, size;
2960
2961 /* igc only supports 1 Tx and/or 1 Rx queue per vector */
2962 if (txr_count > 1 || rxr_count > 1)
2963 return -ENOMEM;
2964
2965 ring_count = txr_count + rxr_count;
2966 size = sizeof(struct igc_q_vector) +
2967 (sizeof(struct igc_ring) * ring_count);
2968
2969 /* allocate q_vector and rings */
2970 q_vector = adapter->q_vector[v_idx];
2971 if (!q_vector)
2972 q_vector = kzalloc(size, GFP_KERNEL);
2973 else
2974 memset(q_vector, 0, size);
2975 if (!q_vector)
2976 return -ENOMEM;
2977
2978 /* initialize NAPI */
2979 netif_napi_add(adapter->netdev, &q_vector->napi,
2980 igc_poll, 64);
2981
2982 /* tie q_vector and adapter together */
2983 adapter->q_vector[v_idx] = q_vector;
2984 q_vector->adapter = adapter;
2985
2986 /* initialize work limits */
2987 q_vector->tx.work_limit = adapter->tx_work_limit;
2988
2989 /* initialize ITR configuration */
2990 q_vector->itr_register = adapter->io_addr + IGC_EITR(0);
2991 q_vector->itr_val = IGC_START_ITR;
2992
2993 /* initialize pointer to rings */
2994 ring = q_vector->ring;
2995
2996 /* initialize ITR */
2997 if (rxr_count) {
2998 /* rx or rx/tx vector */
2999 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
3000 q_vector->itr_val = adapter->rx_itr_setting;
3001 } else {
3002 /* tx only vector */
3003 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
3004 q_vector->itr_val = adapter->tx_itr_setting;
3005 }
3006
3007 if (txr_count) {
3008 /* assign generic ring traits */
3009 ring->dev = &adapter->pdev->dev;
3010 ring->netdev = adapter->netdev;
3011
3012 /* configure backlink on ring */
3013 ring->q_vector = q_vector;
3014
3015 /* update q_vector Tx values */
3016 igc_add_ring(ring, &q_vector->tx);
3017
3018 /* apply Tx specific ring traits */
3019 ring->count = adapter->tx_ring_count;
3020 ring->queue_index = txr_idx;
3021
3022 /* assign ring to adapter */
3023 adapter->tx_ring[txr_idx] = ring;
3024
3025 /* push pointer to next ring */
3026 ring++;
3027 }
3028
3029 if (rxr_count) {
3030 /* assign generic ring traits */
3031 ring->dev = &adapter->pdev->dev;
3032 ring->netdev = adapter->netdev;
3033
3034 /* configure backlink on ring */
3035 ring->q_vector = q_vector;
3036
3037 /* update q_vector Rx values */
3038 igc_add_ring(ring, &q_vector->rx);
3039
3040 /* apply Rx specific ring traits */
3041 ring->count = adapter->rx_ring_count;
3042 ring->queue_index = rxr_idx;
3043
3044 /* assign ring to adapter */
3045 adapter->rx_ring[rxr_idx] = ring;
3046 }
3047
3048 return 0;
3049}
3050
3051/**
3052 * igc_alloc_q_vectors - Allocate memory for interrupt vectors
3053 * @adapter: board private structure to initialize
3054 *
3055 * We allocate one q_vector per queue interrupt. If allocation fails we
3056 * return -ENOMEM.
3057 */
3058static int igc_alloc_q_vectors(struct igc_adapter *adapter)
3059{
3060 int rxr_remaining = adapter->num_rx_queues;
3061 int txr_remaining = adapter->num_tx_queues;
3062 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
3063 int q_vectors = adapter->num_q_vectors;
3064 int err;
3065
3066 if (q_vectors >= (rxr_remaining + txr_remaining)) {
3067 for (; rxr_remaining; v_idx++) {
3068 err = igc_alloc_q_vector(adapter, q_vectors, v_idx,
3069 0, 0, 1, rxr_idx);
3070
3071 if (err)
3072 goto err_out;
3073
3074 /* update counts and index */
3075 rxr_remaining--;
3076 rxr_idx++;
3077 }
3078 }
3079
3080 for (; v_idx < q_vectors; v_idx++) {
3081 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
3082 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
3083
3084 err = igc_alloc_q_vector(adapter, q_vectors, v_idx,
3085 tqpv, txr_idx, rqpv, rxr_idx);
3086
3087 if (err)
3088 goto err_out;
3089
3090 /* update counts and index */
3091 rxr_remaining -= rqpv;
3092 txr_remaining -= tqpv;
3093 rxr_idx++;
3094 txr_idx++;
3095 }
3096
3097 return 0;
3098
3099err_out:
3100 adapter->num_tx_queues = 0;
3101 adapter->num_rx_queues = 0;
3102 adapter->num_q_vectors = 0;
3103
3104 while (v_idx--)
3105 igc_free_q_vector(adapter, v_idx);
3106
3107 return -ENOMEM;
3108}
3109
13b5b7fd
SN		 3110/**
3111 * igc_cache_ring_register - Descriptor ring to register mapping
3112 * @adapter: board private structure to initialize
3113 *
3114 * Once we know the feature-set enabled for the device, we'll cache
3115 * the register offset the descriptor ring is assigned to.
3116 */
3117static void igc_cache_ring_register(struct igc_adapter *adapter)
3118{
3119 int i = 0, j = 0;
3120
3121 switch (adapter->hw.mac.type) {
3122 case igc_i225:
3123 /* Fall through */
3124 default:
3125 for (; i < adapter->num_rx_queues; i++)
3126 adapter->rx_ring[i]->reg_idx = i;
3127 for (; j < adapter->num_tx_queues; j++)
3128 adapter->tx_ring[j]->reg_idx = j;
3129 break;
3130 }
3131}
3132
3df25e4c
SN		 3133/**
3134 * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
3135 * @adapter: Pointer to adapter structure
3136 *
3137 * This function initializes the interrupts and allocates all of the queues.
3138 */
3139static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix)
3140{
3141 struct pci_dev *pdev = adapter->pdev;
3142 int err = 0;
3143
3144 igc_set_interrupt_capability(adapter, msix);
3145
3146 err = igc_alloc_q_vectors(adapter);
3147 if (err) {
3148 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
3149 goto err_alloc_q_vectors;
3150 }
3151
13b5b7fd
SN		 3152 igc_cache_ring_register(adapter);
3153
3df25e4c
SN		 3154 return 0;
3155
3156err_alloc_q_vectors:
3157 igc_reset_interrupt_capability(adapter);
3158 return err;
3159}
3160
3161static void igc_free_irq(struct igc_adapter *adapter)
3162{
3163 if (adapter->msix_entries) {
3164 int vector = 0, i;
3165
3166 free_irq(adapter->msix_entries[vector++].vector, adapter);
3167
3168 for (i = 0; i < adapter->num_q_vectors; i++)
3169 free_irq(adapter->msix_entries[vector++].vector,
3170 adapter->q_vector[i]);
3171 } else {
3172 free_irq(adapter->pdev->irq, adapter);
3173 }
3174}
3175
3176/**
3177 * igc_irq_disable - Mask off interrupt generation on the NIC
3178 * @adapter: board private structure
3179 */
3180static void igc_irq_disable(struct igc_adapter *adapter)
3181{
3182 struct igc_hw *hw = &adapter->hw;
3183
3184 if (adapter->msix_entries) {
3185 u32 regval = rd32(IGC_EIAM);
3186
3187 wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask);
3188 wr32(IGC_EIMC, adapter->eims_enable_mask);
3189 regval = rd32(IGC_EIAC);
3190 wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask);
3191 }
3192
3193 wr32(IGC_IAM, 0);
3194 wr32(IGC_IMC, ~0);
3195 wrfl();
3196
3197 if (adapter->msix_entries) {
3198 int vector = 0, i;
3199
3200 synchronize_irq(adapter->msix_entries[vector++].vector);
3201
3202 for (i = 0; i < adapter->num_q_vectors; i++)
3203 synchronize_irq(adapter->msix_entries[vector++].vector);
3204 } else {
3205 synchronize_irq(adapter->pdev->irq);
3206 }
3207}
3208
3209/**
3210 * igc_irq_enable - Enable default interrupt generation settings
3211 * @adapter: board private structure
3212 */
3213static void igc_irq_enable(struct igc_adapter *adapter)
3214{
3215 struct igc_hw *hw = &adapter->hw;
3216
3217 if (adapter->msix_entries) {
3218 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA;
3219 u32 regval = rd32(IGC_EIAC);
3220
3221 wr32(IGC_EIAC, regval | adapter->eims_enable_mask);
3222 regval = rd32(IGC_EIAM);
3223 wr32(IGC_EIAM, regval | adapter->eims_enable_mask);
3224 wr32(IGC_EIMS, adapter->eims_enable_mask);
3225 wr32(IGC_IMS, ims);
3226 } else {
3227 wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA);
3228 wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA);
3229 }
3230}
3231
3232/**
3233 * igc_request_irq - initialize interrupts
3234 * @adapter: Pointer to adapter structure
3235 *
3236 * Attempts to configure interrupts using the best available
3237 * capabilities of the hardware and kernel.
3238 */
3239static int igc_request_irq(struct igc_adapter *adapter)
3240{
13b5b7fd
SN		 3241 struct net_device *netdev = adapter->netdev;
3242 struct pci_dev *pdev = adapter->pdev;
3df25e4c
SN		 3243 int err = 0;
3244
3245 if (adapter->flags & IGC_FLAG_HAS_MSIX) {
3246 err = igc_request_msix(adapter);
3247 if (!err)
3248 goto request_done;
3249 /* fall back to MSI */
13b5b7fd
SN		 3250 igc_free_all_tx_resources(adapter);
3251 igc_free_all_rx_resources(adapter);
3df25e4c
SN		 3252
3253 igc_clear_interrupt_scheme(adapter);
3254 err = igc_init_interrupt_scheme(adapter, false);
3255 if (err)
3256 goto request_done;
13b5b7fd
SN		 3257 igc_setup_all_tx_resources(adapter);
3258 igc_setup_all_rx_resources(adapter);
3df25e4c
SN		 3259 igc_configure(adapter);
3260 }
3261
13b5b7fd
SN		 3262 igc_assign_vector(adapter->q_vector[0], 0);
3263
3264 if (adapter->flags & IGC_FLAG_HAS_MSI) {
3265 err = request_irq(pdev->irq, &igc_intr_msi, 0,
3266 netdev->name, adapter);
3267 if (!err)
3268 goto request_done;
3269
3270 /* fall back to legacy interrupts */
3271 igc_reset_interrupt_capability(adapter);
3272 adapter->flags &= ~IGC_FLAG_HAS_MSI;
3273 }
3274
3275 err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED,
3276 netdev->name, adapter);
3277
3278 if (err)
3279 dev_err(&pdev->dev, "Error %d getting interrupt\n",
3280 err);
3281
3df25e4c
SN		 3282request_done:
3283 return err;
3284}
3285
3286static void igc_write_itr(struct igc_q_vector *q_vector)
3287{
3288 u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK;
3289
3290 if (!q_vector->set_itr)
3291 return;
3292
3293 if (!itr_val)
3294 itr_val = IGC_ITR_VAL_MASK;
3295
3296 itr_val |= IGC_EITR_CNT_IGNR;
3297
3298 writel(itr_val, q_vector->itr_register);
3299 q_vector->set_itr = 0;
3300}
3301
c9a11c23
SN		 3302/**
3303 * igc_open - Called when a network interface is made active
3304 * @netdev: network interface device structure
3305 *
3306 * Returns 0 on success, negative value on failure
3307 *
3308 * The open entry point is called when a network interface is made
3309 * active by the system (IFF_UP). At this point all resources needed
3310 * for transmit and receive operations are allocated, the interrupt
3311 * handler is registered with the OS, the watchdog timer is started,
3312 * and the stack is notified that the interface is ready.
3313 */
3314static int __igc_open(struct net_device *netdev, bool resuming)
3315{
3316 struct igc_adapter *adapter = netdev_priv(netdev);
3317 struct igc_hw *hw = &adapter->hw;
3df25e4c 3318 int err = 0;
c9a11c23
SN		 3319 int i = 0;
3320
3321 /* disallow open during test */
3322
3323 if (test_bit(__IGC_TESTING, &adapter->state)) {
3324 WARN_ON(resuming);
3325 return -EBUSY;
3326 }
3327
3328 netif_carrier_off(netdev);
3329
13b5b7fd
SN		 3330 /* allocate transmit descriptors */
3331 err = igc_setup_all_tx_resources(adapter);
3332 if (err)
3333 goto err_setup_tx;
3334
3335 /* allocate receive descriptors */
3336 err = igc_setup_all_rx_resources(adapter);
3337 if (err)
3338 goto err_setup_rx;
3339
c9a11c23
SN		 3340 igc_power_up_link(adapter);
3341
3342 igc_configure(adapter);
3343
3df25e4c
SN		 3344 err = igc_request_irq(adapter);
3345 if (err)
3346 goto err_req_irq;
3347
3348 /* Notify the stack of the actual queue counts. */
14b21cec 3349 err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues);
3df25e4c
SN		 3350 if (err)
3351 goto err_set_queues;
3352
3353 err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues);
3354 if (err)
3355 goto err_set_queues;
3356
c9a11c23
SN		 3357 clear_bit(__IGC_DOWN, &adapter->state);
3358
3359 for (i = 0; i < adapter->num_q_vectors; i++)
3360 napi_enable(&adapter->q_vector[i]->napi);
3361
3df25e4c
SN		 3362 /* Clear any pending interrupts. */
3363 rd32(IGC_ICR);
3364 igc_irq_enable(adapter);
3365
13b5b7fd
SN		 3366 netif_tx_start_all_queues(netdev);
3367
c9a11c23
SN		 3368 /* start the watchdog. */
3369 hw->mac.get_link_status = 1;
208983f0 3370 schedule_work(&adapter->watchdog_task);
c9a11c23
SN		 3371
3372 return IGC_SUCCESS;
3df25e4c
SN		 3373
3374err_set_queues:
3375 igc_free_irq(adapter);
3376err_req_irq:
3377 igc_release_hw_control(adapter);
3378 igc_power_down_link(adapter);
13b5b7fd
SN		 3379 igc_free_all_rx_resources(adapter);
3380err_setup_rx:
3381 igc_free_all_tx_resources(adapter);
3382err_setup_tx:
3383 igc_reset(adapter);
3df25e4c
SN		 3384
3385 return err;
c9a11c23
SN		 3386}
3387
3388static int igc_open(struct net_device *netdev)
3389{
3390 return __igc_open(netdev, false);
3391}
3392
3393/**
3394 * igc_close - Disables a network interface
3395 * @netdev: network interface device structure
3396 *
3397 * Returns 0, this is not allowed to fail
3398 *
3399 * The close entry point is called when an interface is de-activated
3400 * by the OS. The hardware is still under the driver's control, but
3401 * needs to be disabled. A global MAC reset is issued to stop the
3402 * hardware, and all transmit and receive resources are freed.
3403 */
3404static int __igc_close(struct net_device *netdev, bool suspending)
3405{
3406 struct igc_adapter *adapter = netdev_priv(netdev);
3407
3408 WARN_ON(test_bit(__IGC_RESETTING, &adapter->state));
3409
3410 igc_down(adapter);
3411
3412 igc_release_hw_control(adapter);
3413
3df25e4c
SN		 3414 igc_free_irq(adapter);
3415
13b5b7fd
SN		 3416 igc_free_all_tx_resources(adapter);
3417 igc_free_all_rx_resources(adapter);
3418
c9a11c23
SN		 3419 return 0;
3420}
3421
3422static int igc_close(struct net_device *netdev)
3423{
3424 if (netif_device_present(netdev) || netdev->dismantle)
3425 return __igc_close(netdev, false);
3426 return 0;
3427}
3428
3429static const struct net_device_ops igc_netdev_ops = {
3430 .ndo_open = igc_open,
3431 .ndo_stop = igc_close,
3432 .ndo_start_xmit = igc_xmit_frame,
3433 .ndo_set_mac_address = igc_set_mac,
3434 .ndo_change_mtu = igc_change_mtu,
3435 .ndo_get_stats = igc_get_stats,
c9a11c23 3436};
146740f9
SN		 3437
3438/* PCIe configuration access */
3439void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
3440{
3441 struct igc_adapter *adapter = hw->back;
3442
3443 pci_read_config_word(adapter->pdev, reg, value);
3444}
3445
3446void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
3447{
3448 struct igc_adapter *adapter = hw->back;
3449
3450 pci_write_config_word(adapter->pdev, reg, *value);
3451}
3452
3453s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
3454{
3455 struct igc_adapter *adapter = hw->back;
3456 u16 cap_offset;
3457
3458 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
3459 if (!cap_offset)
3460 return -IGC_ERR_CONFIG;
3461
3462 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
3463
3464 return IGC_SUCCESS;
3465}
3466
3467s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
3468{
3469 struct igc_adapter *adapter = hw->back;
3470 u16 cap_offset;
3471
3472 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
3473 if (!cap_offset)
3474 return -IGC_ERR_CONFIG;
3475
3476 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
3477
3478 return IGC_SUCCESS;
3479}
3480
3481u32 igc_rd32(struct igc_hw *hw, u32 reg)
3482{
c9a11c23 3483 struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw);
146740f9
SN		 3484 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
3485 u32 value = 0;
3486
3487 if (IGC_REMOVED(hw_addr))
3488 return ~value;
3489
3490 value = readl(&hw_addr[reg]);
3491
3492 /* reads should not return all F's */
c9a11c23
SN		 3493 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
3494 struct net_device *netdev = igc->netdev;
3495
146740f9 3496 hw->hw_addr = NULL;
c9a11c23
SN		 3497 netif_device_detach(netdev);
3498 netdev_err(netdev, "PCIe link lost, device now detached\n");
3499 }
146740f9
SN		 3500
3501 return value;
3502}
3503
d89f8841
SN		 3504/**
3505 * igc_probe - Device Initialization Routine
3506 * @pdev: PCI device information struct
3507 * @ent: entry in igc_pci_tbl
3508 *
3509 * Returns 0 on success, negative on failure
3510 *
3511 * igc_probe initializes an adapter identified by a pci_dev structure.
3512 * The OS initialization, configuring the adapter private structure,
3513 * and a hardware reset occur.
3514 */
3515static int igc_probe(struct pci_dev *pdev,
3516 const struct pci_device_id *ent)
3517{
146740f9 3518 struct igc_adapter *adapter;
c9a11c23
SN		 3519 struct net_device *netdev;
3520 struct igc_hw *hw;
ab405612 3521 const struct igc_info *ei = igc_info_tbl[ent->driver_data];
84cfa537 3522 int err;
d89f8841
SN		 3523
3524 err = pci_enable_device_mem(pdev);
3525 if (err)
3526 return err;
3527
d89f8841
SN		 3528 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
3529 if (!err) {
3530 err = dma_set_coherent_mask(&pdev->dev,
3531 DMA_BIT_MASK(64));
d89f8841
SN		 3532 } else {
3533 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
3534 if (err) {
3535 err = dma_set_coherent_mask(&pdev->dev,
3536 DMA_BIT_MASK(32));
3537 if (err) {
6ed4babe 3538 dev_err(&pdev->dev, "igc: Wrong DMA config\n");
d89f8841
SN		 3539 goto err_dma;
3540 }
3541 }
3542 }
3543
3544 err = pci_request_selected_regions(pdev,
3545 pci_select_bars(pdev,
3546 IORESOURCE_MEM),
3547 igc_driver_name);
3548 if (err)
3549 goto err_pci_reg;
3550
c9a11c23
SN		 3551 pci_enable_pcie_error_reporting(pdev);
3552
d89f8841 3553 pci_set_master(pdev);
c9a11c23
SN		 3554
3555 err = -ENOMEM;
3556 netdev = alloc_etherdev_mq(sizeof(struct igc_adapter),
3557 IGC_MAX_TX_QUEUES);
3558
3559 if (!netdev)
3560 goto err_alloc_etherdev;
3561
3562 SET_NETDEV_DEV(netdev, &pdev->dev);
3563
3564 pci_set_drvdata(pdev, netdev);
3565 adapter = netdev_priv(netdev);
3566 adapter->netdev = netdev;
3567 adapter->pdev = pdev;
3568 hw = &adapter->hw;
3569 hw->back = adapter;
3570 adapter->port_num = hw->bus.func;
3571 adapter->msg_enable = GENMASK(debug - 1, 0);
3572
d89f8841 3573 err = pci_save_state(pdev);
c9a11c23
SN		 3574 if (err)
3575 goto err_ioremap;
3576
3577 err = -EIO;
3578 adapter->io_addr = ioremap(pci_resource_start(pdev, 0),
3579 pci_resource_len(pdev, 0));
3580 if (!adapter->io_addr)
3581 goto err_ioremap;
3582
3583 /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */
3584 hw->hw_addr = adapter->io_addr;
3585
3586 netdev->netdev_ops = &igc_netdev_ops;
3587
3588 netdev->watchdog_timeo = 5 * HZ;
3589
3590 netdev->mem_start = pci_resource_start(pdev, 0);
3591 netdev->mem_end = pci_resource_end(pdev, 0);
3592
3593 /* PCI config space info */
3594 hw->vendor_id = pdev->vendor;
3595 hw->device_id = pdev->device;
3596 hw->revision_id = pdev->revision;
3597 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3598 hw->subsystem_device_id = pdev->subsystem_device;
146740f9 3599
ab405612
SN		 3600 /* Copy the default MAC and PHY function pointers */
3601 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
5586838f 3602 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
ab405612
SN		 3603
3604 /* Initialize skew-specific constants */
3605 err = ei->get_invariants(hw);
3606 if (err)
3607 goto err_sw_init;
3608
146740f9
SN		 3609 /* setup the private structure */
3610 err = igc_sw_init(adapter);
3611 if (err)
3612 goto err_sw_init;
3613
c9a11c23
SN		 3614 /* MTU range: 68 - 9216 */
3615 netdev->min_mtu = ETH_MIN_MTU;
3616 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3617
4eb80801
SN		 3618 /* before reading the NVM, reset the controller to put the device in a
3619 * known good starting state
3620 */
3621 hw->mac.ops.reset_hw(hw);
3622
3623 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3624 /* copy the MAC address out of the NVM */
3625 if (hw->mac.ops.read_mac_addr(hw))
3626 dev_err(&pdev->dev, "NVM Read Error\n");
3627 }
3628
3629 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
3630
3631 if (!is_valid_ether_addr(netdev->dev_addr)) {
3632 dev_err(&pdev->dev, "Invalid MAC Address\n");
3633 err = -EIO;
3634 goto err_eeprom;
3635 }
3636
0507ef8a
SN		 3637 /* configure RXPBSIZE and TXPBSIZE */
3638 wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT);
3639 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT);
3640
3641 timer_setup(&adapter->watchdog_timer, igc_watchdog, 0);
208983f0 3642 timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0);
0507ef8a
SN		 3643
3644 INIT_WORK(&adapter->reset_task, igc_reset_task);
208983f0 3645 INIT_WORK(&adapter->watchdog_task, igc_watchdog_task);
0507ef8a 3646
4eb80801
SN		 3647 /* Initialize link properties that are user-changeable */
3648 adapter->fc_autoneg = true;
3649 hw->mac.autoneg = true;
3650 hw->phy.autoneg_advertised = 0xaf;
3651
3652 hw->fc.requested_mode = igc_fc_default;
3653 hw->fc.current_mode = igc_fc_default;
3654
c9a11c23
SN		 3655 /* reset the hardware with the new settings */
3656 igc_reset(adapter);
3657
3658 /* let the f/w know that the h/w is now under the control of the
3659 * driver.
3660 */
3661 igc_get_hw_control(adapter);
3662
3663 strncpy(netdev->name, "eth%d", IFNAMSIZ);
3664 err = register_netdev(netdev);
3665 if (err)
3666 goto err_register;
3667
3668 /* carrier off reporting is important to ethtool even BEFORE open */
3669 netif_carrier_off(netdev);
3670
ab405612
SN		 3671 /* Check if Media Autosense is enabled */
3672 adapter->ei = *ei;
3673
c9a11c23
SN		 3674 /* print pcie link status and MAC address */
3675 pcie_print_link_status(pdev);
3676 netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr);
3677
d89f8841
SN		 3678 return 0;
3679
c9a11c23
SN		 3680err_register:
3681 igc_release_hw_control(adapter);
4eb80801
SN		 3682err_eeprom:
3683 if (!igc_check_reset_block(hw))
3684 igc_reset_phy(hw);
146740f9 3685err_sw_init:
3df25e4c
SN		 3686 igc_clear_interrupt_scheme(adapter);
3687 iounmap(adapter->io_addr);
c9a11c23
SN		 3688err_ioremap:
3689 free_netdev(netdev);
3690err_alloc_etherdev:
3691 pci_release_selected_regions(pdev,
3692 pci_select_bars(pdev, IORESOURCE_MEM));
d89f8841
SN		 3693err_pci_reg:
3694err_dma:
3695 pci_disable_device(pdev);
3696 return err;
3697}
3698
3699/**
3700 * igc_remove - Device Removal Routine
3701 * @pdev: PCI device information struct
3702 *
3703 * igc_remove is called by the PCI subsystem to alert the driver
3704 * that it should release a PCI device. This could be caused by a
3705 * Hot-Plug event, or because the driver is going to be removed from
3706 * memory.
3707 */
3708static void igc_remove(struct pci_dev *pdev)
3709{
c9a11c23
SN		 3710 struct net_device *netdev = pci_get_drvdata(pdev);
3711 struct igc_adapter *adapter = netdev_priv(netdev);
3712
3713 set_bit(__IGC_DOWN, &adapter->state);
0507ef8a
SN		 3714
3715 del_timer_sync(&adapter->watchdog_timer);
208983f0 3716 del_timer_sync(&adapter->phy_info_timer);
0507ef8a
SN		 3717
3718 cancel_work_sync(&adapter->reset_task);
208983f0 3719 cancel_work_sync(&adapter->watchdog_task);
c9a11c23
SN		 3720
3721 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3722 * would have already happened in close and is redundant.
3723 */
3724 igc_release_hw_control(adapter);
3725 unregister_netdev(netdev);
3726
0507ef8a
SN		 3727 igc_clear_interrupt_scheme(adapter);
3728 pci_iounmap(pdev, adapter->io_addr);
3729 pci_release_mem_regions(pdev);
d89f8841 3730
0507ef8a
SN		 3731 kfree(adapter->mac_table);
3732 kfree(adapter->shadow_vfta);
c9a11c23 3733 free_netdev(netdev);
0507ef8a
SN		 3734
3735 pci_disable_pcie_error_reporting(pdev);
3736
d89f8841
SN		 3737 pci_disable_device(pdev);
3738}
3739
3740static struct pci_driver igc_driver = {
3741 .name = igc_driver_name,
3742 .id_table = igc_pci_tbl,
3743 .probe = igc_probe,
3744 .remove = igc_remove,
3745};
3746
0507ef8a
SN		 3747static void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
3748 const u32 max_rss_queues)
3749{
3750 /* Determine if we need to pair queues. */
3751 /* If rss_queues > half of max_rss_queues, pair the queues in
3752 * order to conserve interrupts due to limited supply.
3753 */
3754 if (adapter->rss_queues > (max_rss_queues / 2))
3755 adapter->flags |= IGC_FLAG_QUEUE_PAIRS;
3756 else
3757 adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS;
3758}
3759
3760static unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter)
3761{
3762 unsigned int max_rss_queues;
3763
3764 /* Determine the maximum number of RSS queues supported. */
3765 max_rss_queues = IGC_MAX_RX_QUEUES;
3766
3767 return max_rss_queues;
3768}
3769
3770static void igc_init_queue_configuration(struct igc_adapter *adapter)
3771{
3772 u32 max_rss_queues;
3773
3774 max_rss_queues = igc_get_max_rss_queues(adapter);
3775 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3776
3777 igc_set_flag_queue_pairs(adapter, max_rss_queues);
3778}
3779
146740f9
SN		 3780/**
3781 * igc_sw_init - Initialize general software structures (struct igc_adapter)
3782 * @adapter: board private structure to initialize
3783 *
3784 * igc_sw_init initializes the Adapter private data structure.
3785 * Fields are initialized based on PCI device information and
3786 * OS network device settings (MTU size).
3787 */
3788static int igc_sw_init(struct igc_adapter *adapter)
3789{
c9a11c23 3790 struct net_device *netdev = adapter->netdev;
146740f9
SN		 3791 struct pci_dev *pdev = adapter->pdev;
3792 struct igc_hw *hw = &adapter->hw;
3793
0507ef8a 3794 int size = sizeof(struct igc_mac_addr) * hw->mac.rar_entry_count;
146740f9 3795
0507ef8a 3796 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
146740f9 3797
0507ef8a
SN		 3798 /* set default ring sizes */
3799 adapter->tx_ring_count = IGC_DEFAULT_TXD;
3800 adapter->rx_ring_count = IGC_DEFAULT_RXD;
146740f9 3801
0507ef8a
SN		 3802 /* set default ITR values */
3803 adapter->rx_itr_setting = IGC_DEFAULT_ITR;
3804 adapter->tx_itr_setting = IGC_DEFAULT_ITR;
3805
3806 /* set default work limits */
3807 adapter->tx_work_limit = IGC_DEFAULT_TX_WORK;
146740f9 3808
c9a11c23
SN		 3809 /* adjust max frame to be at least the size of a standard frame */
3810 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
0507ef8a
SN		 3811 VLAN_HLEN;
3812 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3813
3814 spin_lock_init(&adapter->nfc_lock);
3815 spin_lock_init(&adapter->stats64_lock);
3816 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3817 adapter->flags |= IGC_FLAG_HAS_MSIX;
3818
3819 adapter->mac_table = kzalloc(size, GFP_ATOMIC);
3820 if (!adapter->mac_table)
3821 return -ENOMEM;
3822
3823 igc_init_queue_configuration(adapter);
c9a11c23 3824
0507ef8a 3825 /* This call may decrease the number of queues */
3df25e4c
SN		 3826 if (igc_init_interrupt_scheme(adapter, true)) {
3827 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3828 return -ENOMEM;
3829 }
3830
3831 /* Explicitly disable IRQ since the NIC can be in any state. */
3832 igc_irq_disable(adapter);
3833
c9a11c23
SN		 3834 set_bit(__IGC_DOWN, &adapter->state);
3835
146740f9
SN		 3836 return 0;
3837}
3838
c0071c7a
SN		 3839/**
3840 * igc_get_hw_dev - return device
3841 * @hw: pointer to hardware structure
3842 *
3843 * used by hardware layer to print debugging information
3844 */
3845struct net_device *igc_get_hw_dev(struct igc_hw *hw)
3846{
3847 struct igc_adapter *adapter = hw->back;
3848
3849 return adapter->netdev;
3850}
3851
d89f8841
SN		 3852/**
3853 * igc_init_module - Driver Registration Routine
3854 *
3855 * igc_init_module is the first routine called when the driver is
3856 * loaded. All it does is register with the PCI subsystem.
3857 */
3858static int __init igc_init_module(void)
3859{
3860 int ret;
3861
3862 pr_info("%s - version %s\n",
3863 igc_driver_string, igc_driver_version);
3864
3865 pr_info("%s\n", igc_copyright);
3866
3867 ret = pci_register_driver(&igc_driver);
3868 return ret;
3869}
3870
3871module_init(igc_init_module);
3872
3873/**
3874 * igc_exit_module - Driver Exit Cleanup Routine
3875 *
3876 * igc_exit_module is called just before the driver is removed
3877 * from memory.
3878 */
3879static void __exit igc_exit_module(void)
3880{
3881 pci_unregister_driver(&igc_driver);
3882}
3883
3884module_exit(igc_exit_module);
3885/* igc_main.c */
Linux 6.x block layer and io_uring tree(s)