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b980ac18 | 1 | /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580 |
d339b133 RC |
2 | * |
3 | * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
74cfb2e1 CW |
15 | * You should have received a copy of the GNU General Public License along with |
16 | * this program; if not, see <http://www.gnu.org/licenses/>. | |
d339b133 RC |
17 | */ |
18 | #include <linux/module.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/pci.h> | |
ba59814b | 21 | #include <linux/ptp_classify.h> |
d339b133 RC |
22 | |
23 | #include "igb.h" | |
24 | ||
25 | #define INCVALUE_MASK 0x7fffffff | |
26 | #define ISGN 0x80000000 | |
27 | ||
b980ac18 | 28 | /* The 82580 timesync updates the system timer every 8ns by 8ns, |
7ebae817 RC |
29 | * and this update value cannot be reprogrammed. |
30 | * | |
d339b133 RC |
31 | * Neither the 82576 nor the 82580 offer registers wide enough to hold |
32 | * nanoseconds time values for very long. For the 82580, SYSTIM always | |
dbedd44e | 33 | * counts nanoseconds, but the upper 24 bits are not available. The |
d339b133 RC |
34 | * frequency is adjusted by changing the 32 bit fractional nanoseconds |
35 | * register, TIMINCA. | |
36 | * | |
37 | * For the 82576, the SYSTIM register time unit is affect by the | |
38 | * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this | |
39 | * field are needed to provide the nominal 16 nanosecond period, | |
40 | * leaving 19 bits for fractional nanoseconds. | |
41 | * | |
7ebae817 RC |
42 | * We scale the NIC clock cycle by a large factor so that relatively |
43 | * small clock corrections can be added or subtracted at each clock | |
44 | * tick. The drawbacks of a large factor are a) that the clock | |
45 | * register overflows more quickly (not such a big deal) and b) that | |
46 | * the increment per tick has to fit into 24 bits. As a result we | |
47 | * need to use a shift of 19 so we can fit a value of 16 into the | |
48 | * TIMINCA register. | |
49 | * | |
d339b133 RC |
50 | * |
51 | * SYSTIMH SYSTIML | |
52 | * +--------------+ +---+---+------+ | |
53 | * 82576 | 32 | | 8 | 5 | 19 | | |
54 | * +--------------+ +---+---+------+ | |
55 | * \________ 45 bits _______/ fract | |
56 | * | |
57 | * +----------+---+ +--------------+ | |
58 | * 82580 | 24 | 8 | | 32 | | |
59 | * +----------+---+ +--------------+ | |
60 | * reserved \______ 40 bits _____/ | |
61 | * | |
62 | * | |
63 | * The 45 bit 82576 SYSTIM overflows every | |
64 | * 2^45 * 10^-9 / 3600 = 9.77 hours. | |
65 | * | |
66 | * The 40 bit 82580 SYSTIM overflows every | |
67 | * 2^40 * 10^-9 / 60 = 18.3 minutes. | |
68 | */ | |
69 | ||
a79f4f88 | 70 | #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) |
428f1f71 | 71 | #define IGB_PTP_TX_TIMEOUT (HZ * 15) |
a79f4f88 MV |
72 | #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) |
73 | #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1) | |
74 | #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) | |
75 | #define IGB_NBITS_82580 40 | |
d339b133 | 76 | |
167f3f71 JK |
77 | static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); |
78 | ||
b980ac18 | 79 | /* SYSTIM read access for the 82576 */ |
a79f4f88 | 80 | static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc) |
d339b133 | 81 | { |
d339b133 RC |
82 | struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
83 | struct e1000_hw *hw = &igb->hw; | |
a79f4f88 MV |
84 | u64 val; |
85 | u32 lo, hi; | |
d339b133 RC |
86 | |
87 | lo = rd32(E1000_SYSTIML); | |
88 | hi = rd32(E1000_SYSTIMH); | |
89 | ||
90 | val = ((u64) hi) << 32; | |
91 | val |= lo; | |
92 | ||
93 | return val; | |
94 | } | |
95 | ||
b980ac18 | 96 | /* SYSTIM read access for the 82580 */ |
a79f4f88 | 97 | static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc) |
d339b133 | 98 | { |
d339b133 RC |
99 | struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
100 | struct e1000_hw *hw = &igb->hw; | |
e5c3370f | 101 | u32 lo, hi; |
a79f4f88 | 102 | u64 val; |
d339b133 | 103 | |
b980ac18 | 104 | /* The timestamp latches on lowest register read. For the 82580 |
7ebae817 RC |
105 | * the lowest register is SYSTIMR instead of SYSTIML. However we only |
106 | * need to provide nanosecond resolution, so we just ignore it. | |
107 | */ | |
e5c3370f | 108 | rd32(E1000_SYSTIMR); |
d339b133 RC |
109 | lo = rd32(E1000_SYSTIML); |
110 | hi = rd32(E1000_SYSTIMH); | |
111 | ||
112 | val = ((u64) hi) << 32; | |
113 | val |= lo; | |
114 | ||
115 | return val; | |
116 | } | |
117 | ||
b980ac18 | 118 | /* SYSTIM read access for I210/I211 */ |
e57b8bdb MV |
119 | static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts) |
120 | { | |
121 | struct e1000_hw *hw = &adapter->hw; | |
e5c3370f | 122 | u32 sec, nsec; |
e57b8bdb | 123 | |
b980ac18 | 124 | /* The timestamp latches on lowest register read. For I210/I211, the |
e57b8bdb MV |
125 | * lowest register is SYSTIMR. Since we only need to provide nanosecond |
126 | * resolution, we can ignore it. | |
127 | */ | |
e5c3370f | 128 | rd32(E1000_SYSTIMR); |
e57b8bdb MV |
129 | nsec = rd32(E1000_SYSTIML); |
130 | sec = rd32(E1000_SYSTIMH); | |
131 | ||
132 | ts->tv_sec = sec; | |
133 | ts->tv_nsec = nsec; | |
134 | } | |
135 | ||
136 | static void igb_ptp_write_i210(struct igb_adapter *adapter, | |
137 | const struct timespec *ts) | |
138 | { | |
139 | struct e1000_hw *hw = &adapter->hw; | |
140 | ||
b980ac18 | 141 | /* Writing the SYSTIMR register is not necessary as it only provides |
e57b8bdb MV |
142 | * sub-nanosecond resolution. |
143 | */ | |
144 | wr32(E1000_SYSTIML, ts->tv_nsec); | |
145 | wr32(E1000_SYSTIMH, ts->tv_sec); | |
146 | } | |
147 | ||
a79f4f88 MV |
148 | /** |
149 | * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp | |
150 | * @adapter: board private structure | |
151 | * @hwtstamps: timestamp structure to update | |
152 | * @systim: unsigned 64bit system time value. | |
153 | * | |
154 | * We need to convert the system time value stored in the RX/TXSTMP registers | |
155 | * into a hwtstamp which can be used by the upper level timestamping functions. | |
156 | * | |
157 | * The 'tmreg_lock' spinlock is used to protect the consistency of the | |
158 | * system time value. This is needed because reading the 64 bit time | |
159 | * value involves reading two (or three) 32 bit registers. The first | |
160 | * read latches the value. Ditto for writing. | |
161 | * | |
162 | * In addition, here have extended the system time with an overflow | |
163 | * counter in software. | |
164 | **/ | |
165 | static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, | |
166 | struct skb_shared_hwtstamps *hwtstamps, | |
167 | u64 systim) | |
168 | { | |
169 | unsigned long flags; | |
170 | u64 ns; | |
171 | ||
172 | switch (adapter->hw.mac.type) { | |
e57b8bdb MV |
173 | case e1000_82576: |
174 | case e1000_82580: | |
ceb5f13b | 175 | case e1000_i354: |
e57b8bdb MV |
176 | case e1000_i350: |
177 | spin_lock_irqsave(&adapter->tmreg_lock, flags); | |
178 | ||
179 | ns = timecounter_cyc2time(&adapter->tc, systim); | |
180 | ||
181 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); | |
182 | ||
183 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
184 | hwtstamps->hwtstamp = ns_to_ktime(ns); | |
185 | break; | |
a79f4f88 MV |
186 | case e1000_i210: |
187 | case e1000_i211: | |
e57b8bdb MV |
188 | memset(hwtstamps, 0, sizeof(*hwtstamps)); |
189 | /* Upper 32 bits contain s, lower 32 bits contain ns. */ | |
190 | hwtstamps->hwtstamp = ktime_set(systim >> 32, | |
191 | systim & 0xFFFFFFFF); | |
a79f4f88 MV |
192 | break; |
193 | default: | |
e57b8bdb | 194 | break; |
a79f4f88 | 195 | } |
a79f4f88 MV |
196 | } |
197 | ||
b980ac18 | 198 | /* PTP clock operations */ |
a79f4f88 | 199 | static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) |
d339b133 | 200 | { |
a79f4f88 MV |
201 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
202 | ptp_caps); | |
203 | struct e1000_hw *hw = &igb->hw; | |
204 | int neg_adj = 0; | |
d339b133 RC |
205 | u64 rate; |
206 | u32 incvalue; | |
d339b133 RC |
207 | |
208 | if (ppb < 0) { | |
209 | neg_adj = 1; | |
210 | ppb = -ppb; | |
211 | } | |
212 | rate = ppb; | |
213 | rate <<= 14; | |
214 | rate = div_u64(rate, 1953125); | |
215 | ||
216 | incvalue = 16 << IGB_82576_TSYNC_SHIFT; | |
217 | ||
218 | if (neg_adj) | |
219 | incvalue -= rate; | |
220 | else | |
221 | incvalue += rate; | |
222 | ||
223 | wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
a79f4f88 | 228 | static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb) |
d339b133 | 229 | { |
a79f4f88 MV |
230 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
231 | ptp_caps); | |
232 | struct e1000_hw *hw = &igb->hw; | |
233 | int neg_adj = 0; | |
d339b133 RC |
234 | u64 rate; |
235 | u32 inca; | |
d339b133 RC |
236 | |
237 | if (ppb < 0) { | |
238 | neg_adj = 1; | |
239 | ppb = -ppb; | |
240 | } | |
241 | rate = ppb; | |
242 | rate <<= 26; | |
243 | rate = div_u64(rate, 1953125); | |
244 | ||
245 | inca = rate & INCVALUE_MASK; | |
246 | if (neg_adj) | |
247 | inca |= ISGN; | |
248 | ||
249 | wr32(E1000_TIMINCA, inca); | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
e57b8bdb | 254 | static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) |
d339b133 | 255 | { |
a79f4f88 MV |
256 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
257 | ptp_caps); | |
d339b133 | 258 | unsigned long flags; |
d339b133 RC |
259 | |
260 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
5ee698e3 | 261 | timecounter_adjtime(&igb->tc, delta); |
d339b133 RC |
262 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
e57b8bdb MV |
267 | static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) |
268 | { | |
269 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
270 | ptp_caps); | |
271 | unsigned long flags; | |
272 | struct timespec now, then = ns_to_timespec(delta); | |
273 | ||
274 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
275 | ||
276 | igb_ptp_read_i210(igb, &now); | |
277 | now = timespec_add(now, then); | |
278 | igb_ptp_write_i210(igb, (const struct timespec *)&now); | |
279 | ||
280 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
285 | static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, | |
286 | struct timespec *ts) | |
d339b133 | 287 | { |
a79f4f88 MV |
288 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
289 | ptp_caps); | |
290 | unsigned long flags; | |
d339b133 RC |
291 | u64 ns; |
292 | u32 remainder; | |
d339b133 RC |
293 | |
294 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
295 | ||
296 | ns = timecounter_read(&igb->tc); | |
297 | ||
298 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
299 | ||
300 | ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); | |
301 | ts->tv_nsec = remainder; | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
e57b8bdb MV |
306 | static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, |
307 | struct timespec *ts) | |
308 | { | |
309 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
310 | ptp_caps); | |
311 | unsigned long flags; | |
312 | ||
313 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
314 | ||
315 | igb_ptp_read_i210(igb, ts); | |
316 | ||
317 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
322 | static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, | |
323 | const struct timespec *ts) | |
d339b133 | 324 | { |
a79f4f88 MV |
325 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
326 | ptp_caps); | |
d339b133 | 327 | unsigned long flags; |
a79f4f88 | 328 | u64 ns; |
d339b133 RC |
329 | |
330 | ns = ts->tv_sec * 1000000000ULL; | |
331 | ns += ts->tv_nsec; | |
332 | ||
333 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
334 | ||
335 | timecounter_init(&igb->tc, &igb->cc, ns); | |
336 | ||
337 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
e57b8bdb MV |
342 | static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, |
343 | const struct timespec *ts) | |
344 | { | |
345 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
346 | ptp_caps); | |
347 | unsigned long flags; | |
348 | ||
349 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
350 | ||
351 | igb_ptp_write_i210(igb, ts); | |
352 | ||
353 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
720db4ff RC |
358 | static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) |
359 | { | |
360 | u32 *ptr = pin < 2 ? ctrl : ctrl_ext; | |
b23c0cc5 | 361 | static const u32 mask[IGB_N_SDP] = { |
720db4ff RC |
362 | E1000_CTRL_SDP0_DIR, |
363 | E1000_CTRL_SDP1_DIR, | |
364 | E1000_CTRL_EXT_SDP2_DIR, | |
365 | E1000_CTRL_EXT_SDP3_DIR, | |
366 | }; | |
367 | ||
368 | if (input) | |
369 | *ptr &= ~mask[pin]; | |
370 | else | |
371 | *ptr |= mask[pin]; | |
372 | } | |
373 | ||
374 | static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) | |
375 | { | |
b23c0cc5 | 376 | static const u32 aux0_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
377 | AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, |
378 | }; | |
b23c0cc5 | 379 | static const u32 aux1_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
380 | AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, |
381 | }; | |
b23c0cc5 | 382 | static const u32 ts_sdp_en[IGB_N_SDP] = { |
720db4ff RC |
383 | TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, |
384 | }; | |
b23c0cc5 | 385 | struct e1000_hw *hw = &igb->hw; |
720db4ff RC |
386 | u32 ctrl, ctrl_ext, tssdp = 0; |
387 | ||
388 | ctrl = rd32(E1000_CTRL); | |
389 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
390 | tssdp = rd32(E1000_TSSDP); | |
391 | ||
392 | igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); | |
393 | ||
394 | /* Make sure this pin is not enabled as an output. */ | |
395 | tssdp &= ~ts_sdp_en[pin]; | |
396 | ||
397 | if (chan == 1) { | |
398 | tssdp &= ~AUX1_SEL_SDP3; | |
399 | tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; | |
400 | } else { | |
401 | tssdp &= ~AUX0_SEL_SDP3; | |
402 | tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; | |
403 | } | |
404 | ||
405 | wr32(E1000_TSSDP, tssdp); | |
406 | wr32(E1000_CTRL, ctrl); | |
407 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
408 | } | |
409 | ||
410 | static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin) | |
411 | { | |
b23c0cc5 | 412 | static const u32 aux0_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
413 | AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, |
414 | }; | |
b23c0cc5 | 415 | static const u32 aux1_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
416 | AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, |
417 | }; | |
b23c0cc5 | 418 | static const u32 ts_sdp_en[IGB_N_SDP] = { |
720db4ff RC |
419 | TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, |
420 | }; | |
b23c0cc5 | 421 | static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = { |
720db4ff RC |
422 | TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0, |
423 | TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0, | |
424 | }; | |
b23c0cc5 | 425 | static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = { |
720db4ff RC |
426 | TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1, |
427 | TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1, | |
428 | }; | |
b23c0cc5 | 429 | static const u32 ts_sdp_sel_clr[IGB_N_SDP] = { |
720db4ff RC |
430 | TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, |
431 | TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, | |
432 | }; | |
b23c0cc5 | 433 | struct e1000_hw *hw = &igb->hw; |
720db4ff RC |
434 | u32 ctrl, ctrl_ext, tssdp = 0; |
435 | ||
436 | ctrl = rd32(E1000_CTRL); | |
437 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
438 | tssdp = rd32(E1000_TSSDP); | |
439 | ||
440 | igb_pin_direction(pin, 0, &ctrl, &ctrl_ext); | |
441 | ||
442 | /* Make sure this pin is not enabled as an input. */ | |
443 | if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin]) | |
444 | tssdp &= ~AUX0_TS_SDP_EN; | |
445 | ||
446 | if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin]) | |
447 | tssdp &= ~AUX1_TS_SDP_EN; | |
448 | ||
449 | tssdp &= ~ts_sdp_sel_clr[pin]; | |
450 | if (chan == 1) | |
451 | tssdp |= ts_sdp_sel_tt1[pin]; | |
452 | else | |
453 | tssdp |= ts_sdp_sel_tt0[pin]; | |
454 | ||
455 | tssdp |= ts_sdp_en[pin]; | |
456 | ||
457 | wr32(E1000_TSSDP, tssdp); | |
458 | wr32(E1000_CTRL, ctrl); | |
459 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
460 | } | |
461 | ||
00c65578 RC |
462 | static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp, |
463 | struct ptp_clock_request *rq, int on) | |
464 | { | |
465 | struct igb_adapter *igb = | |
466 | container_of(ptp, struct igb_adapter, ptp_caps); | |
467 | struct e1000_hw *hw = &igb->hw; | |
720db4ff | 468 | u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh; |
00c65578 | 469 | unsigned long flags; |
720db4ff | 470 | struct timespec ts; |
e357f0aa | 471 | int pin = -1; |
720db4ff | 472 | s64 ns; |
00c65578 RC |
473 | |
474 | switch (rq->type) { | |
720db4ff RC |
475 | case PTP_CLK_REQ_EXTTS: |
476 | if (on) { | |
477 | pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, | |
478 | rq->extts.index); | |
479 | if (pin < 0) | |
480 | return -EBUSY; | |
481 | } | |
482 | if (rq->extts.index == 1) { | |
483 | tsauxc_mask = TSAUXC_EN_TS1; | |
484 | tsim_mask = TSINTR_AUTT1; | |
485 | } else { | |
486 | tsauxc_mask = TSAUXC_EN_TS0; | |
487 | tsim_mask = TSINTR_AUTT0; | |
488 | } | |
489 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
490 | tsauxc = rd32(E1000_TSAUXC); | |
491 | tsim = rd32(E1000_TSIM); | |
492 | if (on) { | |
493 | igb_pin_extts(igb, rq->extts.index, pin); | |
494 | tsauxc |= tsauxc_mask; | |
495 | tsim |= tsim_mask; | |
496 | } else { | |
497 | tsauxc &= ~tsauxc_mask; | |
498 | tsim &= ~tsim_mask; | |
499 | } | |
500 | wr32(E1000_TSAUXC, tsauxc); | |
501 | wr32(E1000_TSIM, tsim); | |
502 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
503 | return 0; | |
504 | ||
505 | case PTP_CLK_REQ_PEROUT: | |
506 | if (on) { | |
507 | pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, | |
508 | rq->perout.index); | |
509 | if (pin < 0) | |
510 | return -EBUSY; | |
511 | } | |
512 | ts.tv_sec = rq->perout.period.sec; | |
513 | ts.tv_nsec = rq->perout.period.nsec; | |
514 | ns = timespec_to_ns(&ts); | |
515 | ns = ns >> 1; | |
516 | if (on && ns < 500000LL) { | |
517 | /* 2k interrupts per second is an awful lot. */ | |
518 | return -EINVAL; | |
519 | } | |
520 | ts = ns_to_timespec(ns); | |
521 | if (rq->perout.index == 1) { | |
522 | tsauxc_mask = TSAUXC_EN_TT1; | |
523 | tsim_mask = TSINTR_TT1; | |
524 | trgttiml = E1000_TRGTTIML1; | |
525 | trgttimh = E1000_TRGTTIMH1; | |
526 | } else { | |
527 | tsauxc_mask = TSAUXC_EN_TT0; | |
528 | tsim_mask = TSINTR_TT0; | |
529 | trgttiml = E1000_TRGTTIML0; | |
530 | trgttimh = E1000_TRGTTIMH0; | |
531 | } | |
532 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
533 | tsauxc = rd32(E1000_TSAUXC); | |
534 | tsim = rd32(E1000_TSIM); | |
535 | if (on) { | |
536 | int i = rq->perout.index; | |
537 | ||
538 | igb_pin_perout(igb, i, pin); | |
539 | igb->perout[i].start.tv_sec = rq->perout.start.sec; | |
540 | igb->perout[i].start.tv_nsec = rq->perout.start.nsec; | |
541 | igb->perout[i].period.tv_sec = ts.tv_sec; | |
542 | igb->perout[i].period.tv_nsec = ts.tv_nsec; | |
543 | wr32(trgttiml, rq->perout.start.sec); | |
544 | wr32(trgttimh, rq->perout.start.nsec); | |
545 | tsauxc |= tsauxc_mask; | |
546 | tsim |= tsim_mask; | |
547 | } else { | |
548 | tsauxc &= ~tsauxc_mask; | |
549 | tsim &= ~tsim_mask; | |
550 | } | |
551 | wr32(E1000_TSAUXC, tsauxc); | |
552 | wr32(E1000_TSIM, tsim); | |
553 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
554 | return 0; | |
555 | ||
00c65578 RC |
556 | case PTP_CLK_REQ_PPS: |
557 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
558 | tsim = rd32(E1000_TSIM); | |
559 | if (on) | |
560 | tsim |= TSINTR_SYS_WRAP; | |
561 | else | |
562 | tsim &= ~TSINTR_SYS_WRAP; | |
563 | wr32(E1000_TSIM, tsim); | |
564 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
565 | return 0; | |
00c65578 RC |
566 | } |
567 | ||
568 | return -EOPNOTSUPP; | |
569 | } | |
570 | ||
102be52f JK |
571 | static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, |
572 | struct ptp_clock_request *rq, int on) | |
d339b133 RC |
573 | { |
574 | return -EOPNOTSUPP; | |
575 | } | |
576 | ||
720db4ff RC |
577 | static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, |
578 | enum ptp_pin_function func, unsigned int chan) | |
579 | { | |
580 | switch (func) { | |
581 | case PTP_PF_NONE: | |
582 | case PTP_PF_EXTTS: | |
583 | case PTP_PF_PEROUT: | |
584 | break; | |
585 | case PTP_PF_PHYSYNC: | |
586 | return -1; | |
587 | } | |
588 | return 0; | |
589 | } | |
590 | ||
1f6e8178 MV |
591 | /** |
592 | * igb_ptp_tx_work | |
593 | * @work: pointer to work struct | |
594 | * | |
595 | * This work function polls the TSYNCTXCTL valid bit to determine when a | |
596 | * timestamp has been taken for the current stored skb. | |
b980ac18 | 597 | **/ |
167f3f71 | 598 | static void igb_ptp_tx_work(struct work_struct *work) |
1f6e8178 MV |
599 | { |
600 | struct igb_adapter *adapter = container_of(work, struct igb_adapter, | |
601 | ptp_tx_work); | |
602 | struct e1000_hw *hw = &adapter->hw; | |
603 | u32 tsynctxctl; | |
604 | ||
605 | if (!adapter->ptp_tx_skb) | |
606 | return; | |
607 | ||
428f1f71 MV |
608 | if (time_is_before_jiffies(adapter->ptp_tx_start + |
609 | IGB_PTP_TX_TIMEOUT)) { | |
610 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
611 | adapter->ptp_tx_skb = NULL; | |
ed4420a3 | 612 | clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
428f1f71 | 613 | adapter->tx_hwtstamp_timeouts++; |
c5ffe7e1 | 614 | dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); |
428f1f71 MV |
615 | return; |
616 | } | |
617 | ||
1f6e8178 MV |
618 | tsynctxctl = rd32(E1000_TSYNCTXCTL); |
619 | if (tsynctxctl & E1000_TSYNCTXCTL_VALID) | |
620 | igb_ptp_tx_hwtstamp(adapter); | |
621 | else | |
622 | /* reschedule to check later */ | |
623 | schedule_work(&adapter->ptp_tx_work); | |
624 | } | |
625 | ||
a79f4f88 | 626 | static void igb_ptp_overflow_check(struct work_struct *work) |
d339b133 | 627 | { |
a79f4f88 MV |
628 | struct igb_adapter *igb = |
629 | container_of(work, struct igb_adapter, ptp_overflow_work.work); | |
630 | struct timespec ts; | |
631 | ||
e57b8bdb | 632 | igb->ptp_caps.gettime(&igb->ptp_caps, &ts); |
a79f4f88 MV |
633 | |
634 | pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec); | |
635 | ||
636 | schedule_delayed_work(&igb->ptp_overflow_work, | |
637 | IGB_SYSTIM_OVERFLOW_PERIOD); | |
d339b133 RC |
638 | } |
639 | ||
fc580751 MV |
640 | /** |
641 | * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched | |
642 | * @adapter: private network adapter structure | |
643 | * | |
644 | * This watchdog task is scheduled to detect error case where hardware has | |
645 | * dropped an Rx packet that was timestamped when the ring is full. The | |
646 | * particular error is rare but leaves the device in a state unable to timestamp | |
647 | * any future packets. | |
b980ac18 | 648 | **/ |
fc580751 MV |
649 | void igb_ptp_rx_hang(struct igb_adapter *adapter) |
650 | { | |
651 | struct e1000_hw *hw = &adapter->hw; | |
fc580751 MV |
652 | u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); |
653 | unsigned long rx_event; | |
fc580751 MV |
654 | |
655 | if (hw->mac.type != e1000_82576) | |
656 | return; | |
657 | ||
658 | /* If we don't have a valid timestamp in the registers, just update the | |
659 | * timeout counter and exit | |
660 | */ | |
661 | if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { | |
662 | adapter->last_rx_ptp_check = jiffies; | |
663 | return; | |
664 | } | |
665 | ||
666 | /* Determine the most recent watchdog or rx_timestamp event */ | |
667 | rx_event = adapter->last_rx_ptp_check; | |
5499a968 JK |
668 | if (time_after(adapter->last_rx_timestamp, rx_event)) |
669 | rx_event = adapter->last_rx_timestamp; | |
fc580751 MV |
670 | |
671 | /* Only need to read the high RXSTMP register to clear the lock */ | |
672 | if (time_is_before_jiffies(rx_event + 5 * HZ)) { | |
673 | rd32(E1000_RXSTMPH); | |
674 | adapter->last_rx_ptp_check = jiffies; | |
675 | adapter->rx_hwtstamp_cleared++; | |
c5ffe7e1 | 676 | dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); |
fc580751 MV |
677 | } |
678 | } | |
679 | ||
a79f4f88 MV |
680 | /** |
681 | * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp | |
1f6e8178 | 682 | * @adapter: Board private structure. |
a79f4f88 MV |
683 | * |
684 | * If we were asked to do hardware stamping and such a time stamp is | |
685 | * available, then it must have been for this skb here because we only | |
686 | * allow only one such packet into the queue. | |
b980ac18 | 687 | **/ |
167f3f71 | 688 | static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) |
d339b133 | 689 | { |
a79f4f88 MV |
690 | struct e1000_hw *hw = &adapter->hw; |
691 | struct skb_shared_hwtstamps shhwtstamps; | |
692 | u64 regval; | |
d339b133 | 693 | |
a79f4f88 MV |
694 | regval = rd32(E1000_TXSTMPL); |
695 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
d339b133 | 696 | |
a79f4f88 | 697 | igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); |
1f6e8178 MV |
698 | skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); |
699 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
700 | adapter->ptp_tx_skb = NULL; | |
ed4420a3 | 701 | clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
a79f4f88 MV |
702 | } |
703 | ||
b534550a AD |
704 | /** |
705 | * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp | |
706 | * @q_vector: Pointer to interrupt specific structure | |
707 | * @va: Pointer to address containing Rx buffer | |
708 | * @skb: Buffer containing timestamp and packet | |
709 | * | |
710 | * This function is meant to retrieve a timestamp from the first buffer of an | |
711 | * incoming frame. The value is stored in little endian format starting on | |
712 | * byte 8. | |
b980ac18 | 713 | **/ |
b534550a AD |
714 | void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, |
715 | unsigned char *va, | |
716 | struct sk_buff *skb) | |
717 | { | |
ac61d515 | 718 | __le64 *regval = (__le64 *)va; |
b534550a | 719 | |
b980ac18 | 720 | /* The timestamp is recorded in little endian format. |
b534550a AD |
721 | * DWORD: 0 1 2 3 |
722 | * Field: Reserved Reserved SYSTIML SYSTIMH | |
723 | */ | |
724 | igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb), | |
725 | le64_to_cpu(regval[1])); | |
726 | } | |
727 | ||
728 | /** | |
729 | * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register | |
730 | * @q_vector: Pointer to interrupt specific structure | |
731 | * @skb: Buffer containing timestamp and packet | |
732 | * | |
733 | * This function is meant to retrieve a timestamp from the internal registers | |
734 | * of the adapter and store it in the skb. | |
b980ac18 | 735 | **/ |
b534550a | 736 | void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, |
a79f4f88 MV |
737 | struct sk_buff *skb) |
738 | { | |
739 | struct igb_adapter *adapter = q_vector->adapter; | |
740 | struct e1000_hw *hw = &adapter->hw; | |
741 | u64 regval; | |
742 | ||
b980ac18 | 743 | /* If this bit is set, then the RX registers contain the time stamp. No |
a79f4f88 MV |
744 | * other packet will be time stamped until we read these registers, so |
745 | * read the registers to make them available again. Because only one | |
746 | * packet can be time stamped at a time, we know that the register | |
747 | * values must belong to this one here and therefore we don't need to | |
748 | * compare any of the additional attributes stored for it. | |
749 | * | |
750 | * If nothing went wrong, then it should have a shared tx_flags that we | |
751 | * can turn into a skb_shared_hwtstamps. | |
752 | */ | |
b534550a AD |
753 | if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) |
754 | return; | |
755 | ||
756 | regval = rd32(E1000_RXSTMPL); | |
757 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
a79f4f88 MV |
758 | |
759 | igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); | |
5499a968 JK |
760 | |
761 | /* Update the last_rx_timestamp timer in order to enable watchdog check | |
762 | * for error case of latched timestamp on a dropped packet. | |
763 | */ | |
764 | adapter->last_rx_timestamp = jiffies; | |
a79f4f88 MV |
765 | } |
766 | ||
767 | /** | |
6ab5f7b2 JK |
768 | * igb_ptp_get_ts_config - get hardware time stamping config |
769 | * @netdev: | |
770 | * @ifreq: | |
771 | * | |
772 | * Get the hwtstamp_config settings to return to the user. Rather than attempt | |
773 | * to deconstruct the settings from the registers, just return a shadow copy | |
774 | * of the last known settings. | |
775 | **/ | |
776 | int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) | |
777 | { | |
778 | struct igb_adapter *adapter = netdev_priv(netdev); | |
779 | struct hwtstamp_config *config = &adapter->tstamp_config; | |
780 | ||
781 | return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? | |
782 | -EFAULT : 0; | |
783 | } | |
9f62ecf4 | 784 | |
6ab5f7b2 | 785 | /** |
9f62ecf4 JK |
786 | * igb_ptp_set_timestamp_mode - setup hardware for timestamping |
787 | * @adapter: networking device structure | |
788 | * @config: hwtstamp configuration | |
a79f4f88 MV |
789 | * |
790 | * Outgoing time stamping can be enabled and disabled. Play nice and | |
791 | * disable it when requested, although it shouldn't case any overhead | |
792 | * when no packet needs it. At most one packet in the queue may be | |
793 | * marked for time stamping, otherwise it would be impossible to tell | |
794 | * for sure to which packet the hardware time stamp belongs. | |
795 | * | |
796 | * Incoming time stamping has to be configured via the hardware | |
797 | * filters. Not all combinations are supported, in particular event | |
798 | * type has to be specified. Matching the kind of event packet is | |
799 | * not supported, with the exception of "all V2 events regardless of | |
800 | * level 2 or 4". | |
9f62ecf4 JK |
801 | */ |
802 | static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, | |
803 | struct hwtstamp_config *config) | |
a79f4f88 | 804 | { |
a79f4f88 | 805 | struct e1000_hw *hw = &adapter->hw; |
a79f4f88 MV |
806 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; |
807 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
808 | u32 tsync_rx_cfg = 0; | |
809 | bool is_l4 = false; | |
810 | bool is_l2 = false; | |
811 | u32 regval; | |
812 | ||
a79f4f88 | 813 | /* reserved for future extensions */ |
6ab5f7b2 | 814 | if (config->flags) |
a79f4f88 MV |
815 | return -EINVAL; |
816 | ||
6ab5f7b2 | 817 | switch (config->tx_type) { |
a79f4f88 MV |
818 | case HWTSTAMP_TX_OFF: |
819 | tsync_tx_ctl = 0; | |
820 | case HWTSTAMP_TX_ON: | |
821 | break; | |
822 | default: | |
823 | return -ERANGE; | |
824 | } | |
825 | ||
6ab5f7b2 | 826 | switch (config->rx_filter) { |
a79f4f88 MV |
827 | case HWTSTAMP_FILTER_NONE: |
828 | tsync_rx_ctl = 0; | |
829 | break; | |
a79f4f88 MV |
830 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
831 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
832 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; | |
833 | is_l4 = true; | |
834 | break; | |
835 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
836 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
837 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; | |
838 | is_l4 = true; | |
839 | break; | |
3e961a06 MV |
840 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
841 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
842 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
843 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
a79f4f88 MV |
844 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
845 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3e961a06 | 846 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
a79f4f88 MV |
847 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
848 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
a79f4f88 | 849 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; |
6ab5f7b2 | 850 | config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
a79f4f88 MV |
851 | is_l2 = true; |
852 | is_l4 = true; | |
853 | break; | |
3e961a06 MV |
854 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
855 | case HWTSTAMP_FILTER_ALL: | |
856 | /* 82576 cannot timestamp all packets, which it needs to do to | |
857 | * support both V1 Sync and Delay_Req messages | |
858 | */ | |
859 | if (hw->mac.type != e1000_82576) { | |
860 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
6ab5f7b2 | 861 | config->rx_filter = HWTSTAMP_FILTER_ALL; |
3e961a06 MV |
862 | break; |
863 | } | |
864 | /* fall through */ | |
a79f4f88 | 865 | default: |
6ab5f7b2 | 866 | config->rx_filter = HWTSTAMP_FILTER_NONE; |
a79f4f88 MV |
867 | return -ERANGE; |
868 | } | |
869 | ||
870 | if (hw->mac.type == e1000_82575) { | |
871 | if (tsync_rx_ctl | tsync_tx_ctl) | |
872 | return -EINVAL; | |
873 | return 0; | |
874 | } | |
875 | ||
b980ac18 | 876 | /* Per-packet timestamping only works if all packets are |
a79f4f88 | 877 | * timestamped, so enable timestamping in all packets as |
b980ac18 | 878 | * long as one Rx filter was configured. |
a79f4f88 MV |
879 | */ |
880 | if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { | |
881 | tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
882 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
6ab5f7b2 | 883 | config->rx_filter = HWTSTAMP_FILTER_ALL; |
3e961a06 MV |
884 | is_l2 = true; |
885 | is_l4 = true; | |
e57b8bdb MV |
886 | |
887 | if ((hw->mac.type == e1000_i210) || | |
888 | (hw->mac.type == e1000_i211)) { | |
889 | regval = rd32(E1000_RXPBS); | |
890 | regval |= E1000_RXPBS_CFG_TS_EN; | |
891 | wr32(E1000_RXPBS, regval); | |
892 | } | |
a79f4f88 MV |
893 | } |
894 | ||
895 | /* enable/disable TX */ | |
896 | regval = rd32(E1000_TSYNCTXCTL); | |
897 | regval &= ~E1000_TSYNCTXCTL_ENABLED; | |
898 | regval |= tsync_tx_ctl; | |
899 | wr32(E1000_TSYNCTXCTL, regval); | |
900 | ||
901 | /* enable/disable RX */ | |
902 | regval = rd32(E1000_TSYNCRXCTL); | |
903 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); | |
904 | regval |= tsync_rx_ctl; | |
905 | wr32(E1000_TSYNCRXCTL, regval); | |
906 | ||
907 | /* define which PTP packets are time stamped */ | |
908 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
909 | ||
910 | /* define ethertype filter for timestamped packets */ | |
911 | if (is_l2) | |
912 | wr32(E1000_ETQF(3), | |
913 | (E1000_ETQF_FILTER_ENABLE | /* enable filter */ | |
914 | E1000_ETQF_1588 | /* enable timestamping */ | |
915 | ETH_P_1588)); /* 1588 eth protocol type */ | |
916 | else | |
917 | wr32(E1000_ETQF(3), 0); | |
918 | ||
a79f4f88 MV |
919 | /* L4 Queue Filter[3]: filter by destination port and protocol */ |
920 | if (is_l4) { | |
921 | u32 ftqf = (IPPROTO_UDP /* UDP */ | |
922 | | E1000_FTQF_VF_BP /* VF not compared */ | |
923 | | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ | |
924 | | E1000_FTQF_MASK); /* mask all inputs */ | |
925 | ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ | |
926 | ||
ba59814b | 927 | wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); |
a79f4f88 MV |
928 | wr32(E1000_IMIREXT(3), |
929 | (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); | |
930 | if (hw->mac.type == e1000_82576) { | |
931 | /* enable source port check */ | |
ba59814b | 932 | wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); |
a79f4f88 MV |
933 | ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; |
934 | } | |
935 | wr32(E1000_FTQF(3), ftqf); | |
936 | } else { | |
937 | wr32(E1000_FTQF(3), E1000_FTQF_MASK); | |
938 | } | |
939 | wrfl(); | |
940 | ||
941 | /* clear TX/RX time stamp registers, just to be sure */ | |
e57b8bdb | 942 | regval = rd32(E1000_TXSTMPL); |
a79f4f88 | 943 | regval = rd32(E1000_TXSTMPH); |
e57b8bdb | 944 | regval = rd32(E1000_RXSTMPL); |
a79f4f88 MV |
945 | regval = rd32(E1000_RXSTMPH); |
946 | ||
9f62ecf4 JK |
947 | return 0; |
948 | } | |
949 | ||
950 | /** | |
951 | * igb_ptp_set_ts_config - set hardware time stamping config | |
952 | * @netdev: | |
953 | * @ifreq: | |
954 | * | |
955 | **/ | |
956 | int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) | |
957 | { | |
958 | struct igb_adapter *adapter = netdev_priv(netdev); | |
959 | struct hwtstamp_config config; | |
960 | int err; | |
961 | ||
962 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
963 | return -EFAULT; | |
964 | ||
965 | err = igb_ptp_set_timestamp_mode(adapter, &config); | |
966 | if (err) | |
967 | return err; | |
968 | ||
969 | /* save these settings for future reference */ | |
970 | memcpy(&adapter->tstamp_config, &config, | |
971 | sizeof(adapter->tstamp_config)); | |
972 | ||
973 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
a79f4f88 | 974 | -EFAULT : 0; |
d339b133 RC |
975 | } |
976 | ||
977 | void igb_ptp_init(struct igb_adapter *adapter) | |
978 | { | |
979 | struct e1000_hw *hw = &adapter->hw; | |
201987e3 | 980 | struct net_device *netdev = adapter->netdev; |
720db4ff | 981 | int i; |
d339b133 RC |
982 | |
983 | switch (hw->mac.type) { | |
e57b8bdb MV |
984 | case e1000_82576: |
985 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); | |
986 | adapter->ptp_caps.owner = THIS_MODULE; | |
75517d92 | 987 | adapter->ptp_caps.max_adj = 999999881; |
e57b8bdb MV |
988 | adapter->ptp_caps.n_ext_ts = 0; |
989 | adapter->ptp_caps.pps = 0; | |
990 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; | |
991 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; | |
992 | adapter->ptp_caps.gettime = igb_ptp_gettime_82576; | |
993 | adapter->ptp_caps.settime = igb_ptp_settime_82576; | |
102be52f | 994 | adapter->ptp_caps.enable = igb_ptp_feature_enable; |
e57b8bdb | 995 | adapter->cc.read = igb_ptp_read_82576; |
b57c8940 | 996 | adapter->cc.mask = CYCLECOUNTER_MASK(64); |
e57b8bdb MV |
997 | adapter->cc.mult = 1; |
998 | adapter->cc.shift = IGB_82576_TSYNC_SHIFT; | |
999 | /* Dial the nominal frequency. */ | |
1000 | wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); | |
1001 | break; | |
d339b133 | 1002 | case e1000_82580: |
ceb5f13b | 1003 | case e1000_i354: |
e57b8bdb | 1004 | case e1000_i350: |
201987e3 | 1005 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
a79f4f88 | 1006 | adapter->ptp_caps.owner = THIS_MODULE; |
a79f4f88 MV |
1007 | adapter->ptp_caps.max_adj = 62499999; |
1008 | adapter->ptp_caps.n_ext_ts = 0; | |
1009 | adapter->ptp_caps.pps = 0; | |
1010 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; | |
e57b8bdb MV |
1011 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; |
1012 | adapter->ptp_caps.gettime = igb_ptp_gettime_82576; | |
1013 | adapter->ptp_caps.settime = igb_ptp_settime_82576; | |
102be52f | 1014 | adapter->ptp_caps.enable = igb_ptp_feature_enable; |
a79f4f88 | 1015 | adapter->cc.read = igb_ptp_read_82580; |
b57c8940 | 1016 | adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); |
a79f4f88 MV |
1017 | adapter->cc.mult = 1; |
1018 | adapter->cc.shift = 0; | |
d339b133 RC |
1019 | /* Enable the timer functions by clearing bit 31. */ |
1020 | wr32(E1000_TSAUXC, 0x0); | |
1021 | break; | |
e57b8bdb MV |
1022 | case e1000_i210: |
1023 | case e1000_i211: | |
720db4ff RC |
1024 | for (i = 0; i < IGB_N_SDP; i++) { |
1025 | struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; | |
1026 | ||
1027 | snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); | |
1028 | ppd->index = i; | |
1029 | ppd->func = PTP_PF_NONE; | |
1030 | } | |
201987e3 | 1031 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
a79f4f88 | 1032 | adapter->ptp_caps.owner = THIS_MODULE; |
e57b8bdb | 1033 | adapter->ptp_caps.max_adj = 62499999; |
720db4ff RC |
1034 | adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; |
1035 | adapter->ptp_caps.n_per_out = IGB_N_PEROUT; | |
1036 | adapter->ptp_caps.n_pins = IGB_N_SDP; | |
00c65578 | 1037 | adapter->ptp_caps.pps = 1; |
720db4ff | 1038 | adapter->ptp_caps.pin_config = adapter->sdp_config; |
e57b8bdb MV |
1039 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; |
1040 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; | |
1041 | adapter->ptp_caps.gettime = igb_ptp_gettime_i210; | |
1042 | adapter->ptp_caps.settime = igb_ptp_settime_i210; | |
00c65578 | 1043 | adapter->ptp_caps.enable = igb_ptp_feature_enable_i210; |
720db4ff | 1044 | adapter->ptp_caps.verify = igb_ptp_verify_pin; |
e57b8bdb MV |
1045 | /* Enable the timer functions by clearing bit 31. */ |
1046 | wr32(E1000_TSAUXC, 0x0); | |
d339b133 | 1047 | break; |
d339b133 RC |
1048 | default: |
1049 | adapter->ptp_clock = NULL; | |
1050 | return; | |
1051 | } | |
1052 | ||
1053 | wrfl(); | |
1054 | ||
e57b8bdb MV |
1055 | spin_lock_init(&adapter->tmreg_lock); |
1056 | INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); | |
d339b133 | 1057 | |
e57b8bdb MV |
1058 | /* Initialize the clock and overflow work for devices that need it. */ |
1059 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { | |
1060 | struct timespec ts = ktime_to_timespec(ktime_get_real()); | |
d339b133 | 1061 | |
e57b8bdb MV |
1062 | igb_ptp_settime_i210(&adapter->ptp_caps, &ts); |
1063 | } else { | |
1064 | timecounter_init(&adapter->tc, &adapter->cc, | |
1065 | ktime_to_ns(ktime_get_real())); | |
d339b133 | 1066 | |
e57b8bdb MV |
1067 | INIT_DELAYED_WORK(&adapter->ptp_overflow_work, |
1068 | igb_ptp_overflow_check); | |
1f6e8178 | 1069 | |
e57b8bdb MV |
1070 | schedule_delayed_work(&adapter->ptp_overflow_work, |
1071 | IGB_SYSTIM_OVERFLOW_PERIOD); | |
1072 | } | |
d339b133 | 1073 | |
1f6e8178 MV |
1074 | /* Initialize the time sync interrupts for devices that support it. */ |
1075 | if (hw->mac.type >= e1000_82580) { | |
0c375ac1 | 1076 | wr32(E1000_TSIM, TSYNC_INTERRUPTS); |
1f6e8178 MV |
1077 | wr32(E1000_IMS, E1000_IMS_TS); |
1078 | } | |
1079 | ||
9f62ecf4 JK |
1080 | adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; |
1081 | adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; | |
1082 | ||
1ef76158 RC |
1083 | adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, |
1084 | &adapter->pdev->dev); | |
d339b133 RC |
1085 | if (IS_ERR(adapter->ptp_clock)) { |
1086 | adapter->ptp_clock = NULL; | |
1087 | dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); | |
1f6e8178 | 1088 | } else { |
d339b133 RC |
1089 | dev_info(&adapter->pdev->dev, "added PHC on %s\n", |
1090 | adapter->netdev->name); | |
1f6e8178 MV |
1091 | adapter->flags |= IGB_FLAG_PTP; |
1092 | } | |
d339b133 RC |
1093 | } |
1094 | ||
a79f4f88 MV |
1095 | /** |
1096 | * igb_ptp_stop - Disable PTP device and stop the overflow check. | |
1097 | * @adapter: Board private structure. | |
1098 | * | |
1099 | * This function stops the PTP support and cancels the delayed work. | |
1100 | **/ | |
1101 | void igb_ptp_stop(struct igb_adapter *adapter) | |
d339b133 | 1102 | { |
d3eef8c8 | 1103 | switch (adapter->hw.mac.type) { |
d3eef8c8 | 1104 | case e1000_82576: |
1f6e8178 | 1105 | case e1000_82580: |
ceb5f13b | 1106 | case e1000_i354: |
1f6e8178 | 1107 | case e1000_i350: |
a79f4f88 | 1108 | cancel_delayed_work_sync(&adapter->ptp_overflow_work); |
d3eef8c8 | 1109 | break; |
1f6e8178 MV |
1110 | case e1000_i210: |
1111 | case e1000_i211: | |
1112 | /* No delayed work to cancel. */ | |
1113 | break; | |
d3eef8c8 CW |
1114 | default: |
1115 | return; | |
1116 | } | |
d339b133 | 1117 | |
1f6e8178 | 1118 | cancel_work_sync(&adapter->ptp_tx_work); |
badc26dd MV |
1119 | if (adapter->ptp_tx_skb) { |
1120 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
1121 | adapter->ptp_tx_skb = NULL; | |
ed4420a3 | 1122 | clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
badc26dd | 1123 | } |
1f6e8178 | 1124 | |
d339b133 RC |
1125 | if (adapter->ptp_clock) { |
1126 | ptp_clock_unregister(adapter->ptp_clock); | |
1127 | dev_info(&adapter->pdev->dev, "removed PHC on %s\n", | |
1128 | adapter->netdev->name); | |
1f6e8178 | 1129 | adapter->flags &= ~IGB_FLAG_PTP; |
d339b133 RC |
1130 | } |
1131 | } | |
1f6e8178 MV |
1132 | |
1133 | /** | |
1134 | * igb_ptp_reset - Re-enable the adapter for PTP following a reset. | |
1135 | * @adapter: Board private structure. | |
1136 | * | |
1137 | * This function handles the reset work required to re-enable the PTP device. | |
1138 | **/ | |
1139 | void igb_ptp_reset(struct igb_adapter *adapter) | |
1140 | { | |
1141 | struct e1000_hw *hw = &adapter->hw; | |
8298c1ec | 1142 | unsigned long flags; |
1f6e8178 MV |
1143 | |
1144 | if (!(adapter->flags & IGB_FLAG_PTP)) | |
1145 | return; | |
1146 | ||
6ab5f7b2 | 1147 | /* reset the tstamp_config */ |
9f62ecf4 | 1148 | igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); |
6ab5f7b2 | 1149 | |
8298c1ec RC |
1150 | spin_lock_irqsave(&adapter->tmreg_lock, flags); |
1151 | ||
1f6e8178 MV |
1152 | switch (adapter->hw.mac.type) { |
1153 | case e1000_82576: | |
1154 | /* Dial the nominal frequency. */ | |
1155 | wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); | |
1156 | break; | |
1157 | case e1000_82580: | |
ceb5f13b | 1158 | case e1000_i354: |
1f6e8178 MV |
1159 | case e1000_i350: |
1160 | case e1000_i210: | |
1161 | case e1000_i211: | |
1f6e8178 | 1162 | wr32(E1000_TSAUXC, 0x0); |
720db4ff | 1163 | wr32(E1000_TSSDP, 0x0); |
0c375ac1 | 1164 | wr32(E1000_TSIM, TSYNC_INTERRUPTS); |
1f6e8178 MV |
1165 | wr32(E1000_IMS, E1000_IMS_TS); |
1166 | break; | |
1167 | default: | |
1168 | /* No work to do. */ | |
8298c1ec | 1169 | goto out; |
1f6e8178 MV |
1170 | } |
1171 | ||
e57b8bdb MV |
1172 | /* Re-initialize the timer. */ |
1173 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { | |
1174 | struct timespec ts = ktime_to_timespec(ktime_get_real()); | |
1175 | ||
8298c1ec | 1176 | igb_ptp_write_i210(adapter, &ts); |
e57b8bdb MV |
1177 | } else { |
1178 | timecounter_init(&adapter->tc, &adapter->cc, | |
1179 | ktime_to_ns(ktime_get_real())); | |
1180 | } | |
8298c1ec RC |
1181 | out: |
1182 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); | |
1f6e8178 | 1183 | } |