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b980ac18 | 1 | /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580 |
d339b133 RC |
2 | * |
3 | * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
74cfb2e1 CW |
15 | * You should have received a copy of the GNU General Public License along with |
16 | * this program; if not, see <http://www.gnu.org/licenses/>. | |
d339b133 RC |
17 | */ |
18 | #include <linux/module.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/pci.h> | |
ba59814b | 21 | #include <linux/ptp_classify.h> |
d339b133 RC |
22 | |
23 | #include "igb.h" | |
24 | ||
25 | #define INCVALUE_MASK 0x7fffffff | |
26 | #define ISGN 0x80000000 | |
27 | ||
b980ac18 | 28 | /* The 82580 timesync updates the system timer every 8ns by 8ns, |
7ebae817 RC |
29 | * and this update value cannot be reprogrammed. |
30 | * | |
d339b133 RC |
31 | * Neither the 82576 nor the 82580 offer registers wide enough to hold |
32 | * nanoseconds time values for very long. For the 82580, SYSTIM always | |
33 | * counts nanoseconds, but the upper 24 bits are not availible. The | |
34 | * frequency is adjusted by changing the 32 bit fractional nanoseconds | |
35 | * register, TIMINCA. | |
36 | * | |
37 | * For the 82576, the SYSTIM register time unit is affect by the | |
38 | * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this | |
39 | * field are needed to provide the nominal 16 nanosecond period, | |
40 | * leaving 19 bits for fractional nanoseconds. | |
41 | * | |
7ebae817 RC |
42 | * We scale the NIC clock cycle by a large factor so that relatively |
43 | * small clock corrections can be added or subtracted at each clock | |
44 | * tick. The drawbacks of a large factor are a) that the clock | |
45 | * register overflows more quickly (not such a big deal) and b) that | |
46 | * the increment per tick has to fit into 24 bits. As a result we | |
47 | * need to use a shift of 19 so we can fit a value of 16 into the | |
48 | * TIMINCA register. | |
49 | * | |
d339b133 RC |
50 | * |
51 | * SYSTIMH SYSTIML | |
52 | * +--------------+ +---+---+------+ | |
53 | * 82576 | 32 | | 8 | 5 | 19 | | |
54 | * +--------------+ +---+---+------+ | |
55 | * \________ 45 bits _______/ fract | |
56 | * | |
57 | * +----------+---+ +--------------+ | |
58 | * 82580 | 24 | 8 | | 32 | | |
59 | * +----------+---+ +--------------+ | |
60 | * reserved \______ 40 bits _____/ | |
61 | * | |
62 | * | |
63 | * The 45 bit 82576 SYSTIM overflows every | |
64 | * 2^45 * 10^-9 / 3600 = 9.77 hours. | |
65 | * | |
66 | * The 40 bit 82580 SYSTIM overflows every | |
67 | * 2^40 * 10^-9 / 60 = 18.3 minutes. | |
68 | */ | |
69 | ||
a79f4f88 | 70 | #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) |
428f1f71 | 71 | #define IGB_PTP_TX_TIMEOUT (HZ * 15) |
a79f4f88 MV |
72 | #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) |
73 | #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1) | |
74 | #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) | |
75 | #define IGB_NBITS_82580 40 | |
d339b133 | 76 | |
167f3f71 JK |
77 | static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); |
78 | ||
b980ac18 | 79 | /* SYSTIM read access for the 82576 */ |
a79f4f88 | 80 | static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc) |
d339b133 | 81 | { |
d339b133 RC |
82 | struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
83 | struct e1000_hw *hw = &igb->hw; | |
a79f4f88 MV |
84 | u64 val; |
85 | u32 lo, hi; | |
d339b133 RC |
86 | |
87 | lo = rd32(E1000_SYSTIML); | |
88 | hi = rd32(E1000_SYSTIMH); | |
89 | ||
90 | val = ((u64) hi) << 32; | |
91 | val |= lo; | |
92 | ||
93 | return val; | |
94 | } | |
95 | ||
b980ac18 | 96 | /* SYSTIM read access for the 82580 */ |
a79f4f88 | 97 | static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc) |
d339b133 | 98 | { |
d339b133 RC |
99 | struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
100 | struct e1000_hw *hw = &igb->hw; | |
e5c3370f | 101 | u32 lo, hi; |
a79f4f88 | 102 | u64 val; |
d339b133 | 103 | |
b980ac18 | 104 | /* The timestamp latches on lowest register read. For the 82580 |
7ebae817 RC |
105 | * the lowest register is SYSTIMR instead of SYSTIML. However we only |
106 | * need to provide nanosecond resolution, so we just ignore it. | |
107 | */ | |
e5c3370f | 108 | rd32(E1000_SYSTIMR); |
d339b133 RC |
109 | lo = rd32(E1000_SYSTIML); |
110 | hi = rd32(E1000_SYSTIMH); | |
111 | ||
112 | val = ((u64) hi) << 32; | |
113 | val |= lo; | |
114 | ||
115 | return val; | |
116 | } | |
117 | ||
b980ac18 | 118 | /* SYSTIM read access for I210/I211 */ |
e57b8bdb MV |
119 | static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts) |
120 | { | |
121 | struct e1000_hw *hw = &adapter->hw; | |
e5c3370f | 122 | u32 sec, nsec; |
e57b8bdb | 123 | |
b980ac18 | 124 | /* The timestamp latches on lowest register read. For I210/I211, the |
e57b8bdb MV |
125 | * lowest register is SYSTIMR. Since we only need to provide nanosecond |
126 | * resolution, we can ignore it. | |
127 | */ | |
e5c3370f | 128 | rd32(E1000_SYSTIMR); |
e57b8bdb MV |
129 | nsec = rd32(E1000_SYSTIML); |
130 | sec = rd32(E1000_SYSTIMH); | |
131 | ||
132 | ts->tv_sec = sec; | |
133 | ts->tv_nsec = nsec; | |
134 | } | |
135 | ||
136 | static void igb_ptp_write_i210(struct igb_adapter *adapter, | |
137 | const struct timespec *ts) | |
138 | { | |
139 | struct e1000_hw *hw = &adapter->hw; | |
140 | ||
b980ac18 | 141 | /* Writing the SYSTIMR register is not necessary as it only provides |
e57b8bdb MV |
142 | * sub-nanosecond resolution. |
143 | */ | |
144 | wr32(E1000_SYSTIML, ts->tv_nsec); | |
145 | wr32(E1000_SYSTIMH, ts->tv_sec); | |
146 | } | |
147 | ||
a79f4f88 MV |
148 | /** |
149 | * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp | |
150 | * @adapter: board private structure | |
151 | * @hwtstamps: timestamp structure to update | |
152 | * @systim: unsigned 64bit system time value. | |
153 | * | |
154 | * We need to convert the system time value stored in the RX/TXSTMP registers | |
155 | * into a hwtstamp which can be used by the upper level timestamping functions. | |
156 | * | |
157 | * The 'tmreg_lock' spinlock is used to protect the consistency of the | |
158 | * system time value. This is needed because reading the 64 bit time | |
159 | * value involves reading two (or three) 32 bit registers. The first | |
160 | * read latches the value. Ditto for writing. | |
161 | * | |
162 | * In addition, here have extended the system time with an overflow | |
163 | * counter in software. | |
164 | **/ | |
165 | static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, | |
166 | struct skb_shared_hwtstamps *hwtstamps, | |
167 | u64 systim) | |
168 | { | |
169 | unsigned long flags; | |
170 | u64 ns; | |
171 | ||
172 | switch (adapter->hw.mac.type) { | |
e57b8bdb MV |
173 | case e1000_82576: |
174 | case e1000_82580: | |
ceb5f13b | 175 | case e1000_i354: |
e57b8bdb MV |
176 | case e1000_i350: |
177 | spin_lock_irqsave(&adapter->tmreg_lock, flags); | |
178 | ||
179 | ns = timecounter_cyc2time(&adapter->tc, systim); | |
180 | ||
181 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); | |
182 | ||
183 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
184 | hwtstamps->hwtstamp = ns_to_ktime(ns); | |
185 | break; | |
a79f4f88 MV |
186 | case e1000_i210: |
187 | case e1000_i211: | |
e57b8bdb MV |
188 | memset(hwtstamps, 0, sizeof(*hwtstamps)); |
189 | /* Upper 32 bits contain s, lower 32 bits contain ns. */ | |
190 | hwtstamps->hwtstamp = ktime_set(systim >> 32, | |
191 | systim & 0xFFFFFFFF); | |
a79f4f88 MV |
192 | break; |
193 | default: | |
e57b8bdb | 194 | break; |
a79f4f88 | 195 | } |
a79f4f88 MV |
196 | } |
197 | ||
b980ac18 | 198 | /* PTP clock operations */ |
a79f4f88 | 199 | static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) |
d339b133 | 200 | { |
a79f4f88 MV |
201 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
202 | ptp_caps); | |
203 | struct e1000_hw *hw = &igb->hw; | |
204 | int neg_adj = 0; | |
d339b133 RC |
205 | u64 rate; |
206 | u32 incvalue; | |
d339b133 RC |
207 | |
208 | if (ppb < 0) { | |
209 | neg_adj = 1; | |
210 | ppb = -ppb; | |
211 | } | |
212 | rate = ppb; | |
213 | rate <<= 14; | |
214 | rate = div_u64(rate, 1953125); | |
215 | ||
216 | incvalue = 16 << IGB_82576_TSYNC_SHIFT; | |
217 | ||
218 | if (neg_adj) | |
219 | incvalue -= rate; | |
220 | else | |
221 | incvalue += rate; | |
222 | ||
223 | wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
a79f4f88 | 228 | static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb) |
d339b133 | 229 | { |
a79f4f88 MV |
230 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
231 | ptp_caps); | |
232 | struct e1000_hw *hw = &igb->hw; | |
233 | int neg_adj = 0; | |
d339b133 RC |
234 | u64 rate; |
235 | u32 inca; | |
d339b133 RC |
236 | |
237 | if (ppb < 0) { | |
238 | neg_adj = 1; | |
239 | ppb = -ppb; | |
240 | } | |
241 | rate = ppb; | |
242 | rate <<= 26; | |
243 | rate = div_u64(rate, 1953125); | |
244 | ||
245 | inca = rate & INCVALUE_MASK; | |
246 | if (neg_adj) | |
247 | inca |= ISGN; | |
248 | ||
249 | wr32(E1000_TIMINCA, inca); | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
e57b8bdb | 254 | static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) |
d339b133 | 255 | { |
a79f4f88 MV |
256 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
257 | ptp_caps); | |
d339b133 | 258 | unsigned long flags; |
a79f4f88 | 259 | s64 now; |
d339b133 RC |
260 | |
261 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
262 | ||
263 | now = timecounter_read(&igb->tc); | |
264 | now += delta; | |
265 | timecounter_init(&igb->tc, &igb->cc, now); | |
266 | ||
267 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
e57b8bdb MV |
272 | static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) |
273 | { | |
274 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
275 | ptp_caps); | |
276 | unsigned long flags; | |
277 | struct timespec now, then = ns_to_timespec(delta); | |
278 | ||
279 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
280 | ||
281 | igb_ptp_read_i210(igb, &now); | |
282 | now = timespec_add(now, then); | |
283 | igb_ptp_write_i210(igb, (const struct timespec *)&now); | |
284 | ||
285 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
290 | static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, | |
291 | struct timespec *ts) | |
d339b133 | 292 | { |
a79f4f88 MV |
293 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
294 | ptp_caps); | |
295 | unsigned long flags; | |
d339b133 RC |
296 | u64 ns; |
297 | u32 remainder; | |
d339b133 RC |
298 | |
299 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
300 | ||
301 | ns = timecounter_read(&igb->tc); | |
302 | ||
303 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
304 | ||
305 | ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); | |
306 | ts->tv_nsec = remainder; | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
e57b8bdb MV |
311 | static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, |
312 | struct timespec *ts) | |
313 | { | |
314 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
315 | ptp_caps); | |
316 | unsigned long flags; | |
317 | ||
318 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
319 | ||
320 | igb_ptp_read_i210(igb, ts); | |
321 | ||
322 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, | |
328 | const struct timespec *ts) | |
d339b133 | 329 | { |
a79f4f88 MV |
330 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
331 | ptp_caps); | |
d339b133 | 332 | unsigned long flags; |
a79f4f88 | 333 | u64 ns; |
d339b133 RC |
334 | |
335 | ns = ts->tv_sec * 1000000000ULL; | |
336 | ns += ts->tv_nsec; | |
337 | ||
338 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
339 | ||
340 | timecounter_init(&igb->tc, &igb->cc, ns); | |
341 | ||
342 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
e57b8bdb MV |
347 | static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, |
348 | const struct timespec *ts) | |
349 | { | |
350 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
351 | ptp_caps); | |
352 | unsigned long flags; | |
353 | ||
354 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
355 | ||
356 | igb_ptp_write_i210(igb, ts); | |
357 | ||
358 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
a79f4f88 MV |
363 | static int igb_ptp_enable(struct ptp_clock_info *ptp, |
364 | struct ptp_clock_request *rq, int on) | |
d339b133 RC |
365 | { |
366 | return -EOPNOTSUPP; | |
367 | } | |
368 | ||
1f6e8178 MV |
369 | /** |
370 | * igb_ptp_tx_work | |
371 | * @work: pointer to work struct | |
372 | * | |
373 | * This work function polls the TSYNCTXCTL valid bit to determine when a | |
374 | * timestamp has been taken for the current stored skb. | |
b980ac18 | 375 | **/ |
167f3f71 | 376 | static void igb_ptp_tx_work(struct work_struct *work) |
1f6e8178 MV |
377 | { |
378 | struct igb_adapter *adapter = container_of(work, struct igb_adapter, | |
379 | ptp_tx_work); | |
380 | struct e1000_hw *hw = &adapter->hw; | |
381 | u32 tsynctxctl; | |
382 | ||
383 | if (!adapter->ptp_tx_skb) | |
384 | return; | |
385 | ||
428f1f71 MV |
386 | if (time_is_before_jiffies(adapter->ptp_tx_start + |
387 | IGB_PTP_TX_TIMEOUT)) { | |
388 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
389 | adapter->ptp_tx_skb = NULL; | |
390 | adapter->tx_hwtstamp_timeouts++; | |
391 | dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang"); | |
392 | return; | |
393 | } | |
394 | ||
1f6e8178 MV |
395 | tsynctxctl = rd32(E1000_TSYNCTXCTL); |
396 | if (tsynctxctl & E1000_TSYNCTXCTL_VALID) | |
397 | igb_ptp_tx_hwtstamp(adapter); | |
398 | else | |
399 | /* reschedule to check later */ | |
400 | schedule_work(&adapter->ptp_tx_work); | |
401 | } | |
402 | ||
a79f4f88 | 403 | static void igb_ptp_overflow_check(struct work_struct *work) |
d339b133 | 404 | { |
a79f4f88 MV |
405 | struct igb_adapter *igb = |
406 | container_of(work, struct igb_adapter, ptp_overflow_work.work); | |
407 | struct timespec ts; | |
408 | ||
e57b8bdb | 409 | igb->ptp_caps.gettime(&igb->ptp_caps, &ts); |
a79f4f88 MV |
410 | |
411 | pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec); | |
412 | ||
413 | schedule_delayed_work(&igb->ptp_overflow_work, | |
414 | IGB_SYSTIM_OVERFLOW_PERIOD); | |
d339b133 RC |
415 | } |
416 | ||
fc580751 MV |
417 | /** |
418 | * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched | |
419 | * @adapter: private network adapter structure | |
420 | * | |
421 | * This watchdog task is scheduled to detect error case where hardware has | |
422 | * dropped an Rx packet that was timestamped when the ring is full. The | |
423 | * particular error is rare but leaves the device in a state unable to timestamp | |
424 | * any future packets. | |
b980ac18 | 425 | **/ |
fc580751 MV |
426 | void igb_ptp_rx_hang(struct igb_adapter *adapter) |
427 | { | |
428 | struct e1000_hw *hw = &adapter->hw; | |
429 | struct igb_ring *rx_ring; | |
430 | u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); | |
431 | unsigned long rx_event; | |
432 | int n; | |
433 | ||
434 | if (hw->mac.type != e1000_82576) | |
435 | return; | |
436 | ||
437 | /* If we don't have a valid timestamp in the registers, just update the | |
438 | * timeout counter and exit | |
439 | */ | |
440 | if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { | |
441 | adapter->last_rx_ptp_check = jiffies; | |
442 | return; | |
443 | } | |
444 | ||
445 | /* Determine the most recent watchdog or rx_timestamp event */ | |
446 | rx_event = adapter->last_rx_ptp_check; | |
447 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
448 | rx_ring = adapter->rx_ring[n]; | |
449 | if (time_after(rx_ring->last_rx_timestamp, rx_event)) | |
450 | rx_event = rx_ring->last_rx_timestamp; | |
451 | } | |
452 | ||
453 | /* Only need to read the high RXSTMP register to clear the lock */ | |
454 | if (time_is_before_jiffies(rx_event + 5 * HZ)) { | |
455 | rd32(E1000_RXSTMPH); | |
456 | adapter->last_rx_ptp_check = jiffies; | |
457 | adapter->rx_hwtstamp_cleared++; | |
458 | dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang"); | |
459 | } | |
460 | } | |
461 | ||
a79f4f88 MV |
462 | /** |
463 | * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp | |
1f6e8178 | 464 | * @adapter: Board private structure. |
a79f4f88 MV |
465 | * |
466 | * If we were asked to do hardware stamping and such a time stamp is | |
467 | * available, then it must have been for this skb here because we only | |
468 | * allow only one such packet into the queue. | |
b980ac18 | 469 | **/ |
167f3f71 | 470 | static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) |
d339b133 | 471 | { |
a79f4f88 MV |
472 | struct e1000_hw *hw = &adapter->hw; |
473 | struct skb_shared_hwtstamps shhwtstamps; | |
474 | u64 regval; | |
d339b133 | 475 | |
a79f4f88 MV |
476 | regval = rd32(E1000_TXSTMPL); |
477 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
d339b133 | 478 | |
a79f4f88 | 479 | igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); |
1f6e8178 MV |
480 | skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); |
481 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
482 | adapter->ptp_tx_skb = NULL; | |
a79f4f88 MV |
483 | } |
484 | ||
b534550a AD |
485 | /** |
486 | * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp | |
487 | * @q_vector: Pointer to interrupt specific structure | |
488 | * @va: Pointer to address containing Rx buffer | |
489 | * @skb: Buffer containing timestamp and packet | |
490 | * | |
491 | * This function is meant to retrieve a timestamp from the first buffer of an | |
492 | * incoming frame. The value is stored in little endian format starting on | |
493 | * byte 8. | |
b980ac18 | 494 | **/ |
b534550a AD |
495 | void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, |
496 | unsigned char *va, | |
497 | struct sk_buff *skb) | |
498 | { | |
ac61d515 | 499 | __le64 *regval = (__le64 *)va; |
b534550a | 500 | |
b980ac18 | 501 | /* The timestamp is recorded in little endian format. |
b534550a AD |
502 | * DWORD: 0 1 2 3 |
503 | * Field: Reserved Reserved SYSTIML SYSTIMH | |
504 | */ | |
505 | igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb), | |
506 | le64_to_cpu(regval[1])); | |
507 | } | |
508 | ||
509 | /** | |
510 | * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register | |
511 | * @q_vector: Pointer to interrupt specific structure | |
512 | * @skb: Buffer containing timestamp and packet | |
513 | * | |
514 | * This function is meant to retrieve a timestamp from the internal registers | |
515 | * of the adapter and store it in the skb. | |
b980ac18 | 516 | **/ |
b534550a | 517 | void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, |
a79f4f88 MV |
518 | struct sk_buff *skb) |
519 | { | |
520 | struct igb_adapter *adapter = q_vector->adapter; | |
521 | struct e1000_hw *hw = &adapter->hw; | |
522 | u64 regval; | |
523 | ||
b980ac18 | 524 | /* If this bit is set, then the RX registers contain the time stamp. No |
a79f4f88 MV |
525 | * other packet will be time stamped until we read these registers, so |
526 | * read the registers to make them available again. Because only one | |
527 | * packet can be time stamped at a time, we know that the register | |
528 | * values must belong to this one here and therefore we don't need to | |
529 | * compare any of the additional attributes stored for it. | |
530 | * | |
531 | * If nothing went wrong, then it should have a shared tx_flags that we | |
532 | * can turn into a skb_shared_hwtstamps. | |
533 | */ | |
b534550a AD |
534 | if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) |
535 | return; | |
536 | ||
537 | regval = rd32(E1000_RXSTMPL); | |
538 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
a79f4f88 MV |
539 | |
540 | igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); | |
541 | } | |
542 | ||
543 | /** | |
6ab5f7b2 JK |
544 | * igb_ptp_get_ts_config - get hardware time stamping config |
545 | * @netdev: | |
546 | * @ifreq: | |
547 | * | |
548 | * Get the hwtstamp_config settings to return to the user. Rather than attempt | |
549 | * to deconstruct the settings from the registers, just return a shadow copy | |
550 | * of the last known settings. | |
551 | **/ | |
552 | int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) | |
553 | { | |
554 | struct igb_adapter *adapter = netdev_priv(netdev); | |
555 | struct hwtstamp_config *config = &adapter->tstamp_config; | |
556 | ||
557 | return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? | |
558 | -EFAULT : 0; | |
559 | } | |
560 | /** | |
561 | * igb_ptp_set_ts_config - control hardware time stamping | |
a79f4f88 MV |
562 | * @netdev: |
563 | * @ifreq: | |
a79f4f88 MV |
564 | * |
565 | * Outgoing time stamping can be enabled and disabled. Play nice and | |
566 | * disable it when requested, although it shouldn't case any overhead | |
567 | * when no packet needs it. At most one packet in the queue may be | |
568 | * marked for time stamping, otherwise it would be impossible to tell | |
569 | * for sure to which packet the hardware time stamp belongs. | |
570 | * | |
571 | * Incoming time stamping has to be configured via the hardware | |
572 | * filters. Not all combinations are supported, in particular event | |
573 | * type has to be specified. Matching the kind of event packet is | |
574 | * not supported, with the exception of "all V2 events regardless of | |
575 | * level 2 or 4". | |
a79f4f88 | 576 | **/ |
6ab5f7b2 | 577 | int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) |
a79f4f88 MV |
578 | { |
579 | struct igb_adapter *adapter = netdev_priv(netdev); | |
580 | struct e1000_hw *hw = &adapter->hw; | |
6ab5f7b2 | 581 | struct hwtstamp_config *config = &adapter->tstamp_config; |
a79f4f88 MV |
582 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; |
583 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
584 | u32 tsync_rx_cfg = 0; | |
585 | bool is_l4 = false; | |
586 | bool is_l2 = false; | |
587 | u32 regval; | |
588 | ||
6ab5f7b2 | 589 | if (copy_from_user(config, ifr->ifr_data, sizeof(*config))) |
a79f4f88 MV |
590 | return -EFAULT; |
591 | ||
592 | /* reserved for future extensions */ | |
6ab5f7b2 | 593 | if (config->flags) |
a79f4f88 MV |
594 | return -EINVAL; |
595 | ||
6ab5f7b2 | 596 | switch (config->tx_type) { |
a79f4f88 MV |
597 | case HWTSTAMP_TX_OFF: |
598 | tsync_tx_ctl = 0; | |
599 | case HWTSTAMP_TX_ON: | |
600 | break; | |
601 | default: | |
602 | return -ERANGE; | |
603 | } | |
604 | ||
6ab5f7b2 | 605 | switch (config->rx_filter) { |
a79f4f88 MV |
606 | case HWTSTAMP_FILTER_NONE: |
607 | tsync_rx_ctl = 0; | |
608 | break; | |
a79f4f88 MV |
609 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
610 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
611 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; | |
612 | is_l4 = true; | |
613 | break; | |
614 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
615 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
616 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; | |
617 | is_l4 = true; | |
618 | break; | |
3e961a06 MV |
619 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
620 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
621 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
622 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
a79f4f88 MV |
623 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
624 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3e961a06 | 625 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
a79f4f88 MV |
626 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
627 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
a79f4f88 | 628 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; |
6ab5f7b2 | 629 | config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
a79f4f88 MV |
630 | is_l2 = true; |
631 | is_l4 = true; | |
632 | break; | |
3e961a06 MV |
633 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
634 | case HWTSTAMP_FILTER_ALL: | |
635 | /* 82576 cannot timestamp all packets, which it needs to do to | |
636 | * support both V1 Sync and Delay_Req messages | |
637 | */ | |
638 | if (hw->mac.type != e1000_82576) { | |
639 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
6ab5f7b2 | 640 | config->rx_filter = HWTSTAMP_FILTER_ALL; |
3e961a06 MV |
641 | break; |
642 | } | |
643 | /* fall through */ | |
a79f4f88 | 644 | default: |
6ab5f7b2 | 645 | config->rx_filter = HWTSTAMP_FILTER_NONE; |
a79f4f88 MV |
646 | return -ERANGE; |
647 | } | |
648 | ||
649 | if (hw->mac.type == e1000_82575) { | |
650 | if (tsync_rx_ctl | tsync_tx_ctl) | |
651 | return -EINVAL; | |
652 | return 0; | |
653 | } | |
654 | ||
b980ac18 | 655 | /* Per-packet timestamping only works if all packets are |
a79f4f88 | 656 | * timestamped, so enable timestamping in all packets as |
b980ac18 | 657 | * long as one Rx filter was configured. |
a79f4f88 MV |
658 | */ |
659 | if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { | |
660 | tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
661 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
6ab5f7b2 | 662 | config->rx_filter = HWTSTAMP_FILTER_ALL; |
3e961a06 MV |
663 | is_l2 = true; |
664 | is_l4 = true; | |
e57b8bdb MV |
665 | |
666 | if ((hw->mac.type == e1000_i210) || | |
667 | (hw->mac.type == e1000_i211)) { | |
668 | regval = rd32(E1000_RXPBS); | |
669 | regval |= E1000_RXPBS_CFG_TS_EN; | |
670 | wr32(E1000_RXPBS, regval); | |
671 | } | |
a79f4f88 MV |
672 | } |
673 | ||
674 | /* enable/disable TX */ | |
675 | regval = rd32(E1000_TSYNCTXCTL); | |
676 | regval &= ~E1000_TSYNCTXCTL_ENABLED; | |
677 | regval |= tsync_tx_ctl; | |
678 | wr32(E1000_TSYNCTXCTL, regval); | |
679 | ||
680 | /* enable/disable RX */ | |
681 | regval = rd32(E1000_TSYNCRXCTL); | |
682 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); | |
683 | regval |= tsync_rx_ctl; | |
684 | wr32(E1000_TSYNCRXCTL, regval); | |
685 | ||
686 | /* define which PTP packets are time stamped */ | |
687 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
688 | ||
689 | /* define ethertype filter for timestamped packets */ | |
690 | if (is_l2) | |
691 | wr32(E1000_ETQF(3), | |
692 | (E1000_ETQF_FILTER_ENABLE | /* enable filter */ | |
693 | E1000_ETQF_1588 | /* enable timestamping */ | |
694 | ETH_P_1588)); /* 1588 eth protocol type */ | |
695 | else | |
696 | wr32(E1000_ETQF(3), 0); | |
697 | ||
a79f4f88 MV |
698 | /* L4 Queue Filter[3]: filter by destination port and protocol */ |
699 | if (is_l4) { | |
700 | u32 ftqf = (IPPROTO_UDP /* UDP */ | |
701 | | E1000_FTQF_VF_BP /* VF not compared */ | |
702 | | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ | |
703 | | E1000_FTQF_MASK); /* mask all inputs */ | |
704 | ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ | |
705 | ||
ba59814b | 706 | wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); |
a79f4f88 MV |
707 | wr32(E1000_IMIREXT(3), |
708 | (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); | |
709 | if (hw->mac.type == e1000_82576) { | |
710 | /* enable source port check */ | |
ba59814b | 711 | wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); |
a79f4f88 MV |
712 | ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; |
713 | } | |
714 | wr32(E1000_FTQF(3), ftqf); | |
715 | } else { | |
716 | wr32(E1000_FTQF(3), E1000_FTQF_MASK); | |
717 | } | |
718 | wrfl(); | |
719 | ||
720 | /* clear TX/RX time stamp registers, just to be sure */ | |
e57b8bdb | 721 | regval = rd32(E1000_TXSTMPL); |
a79f4f88 | 722 | regval = rd32(E1000_TXSTMPH); |
e57b8bdb | 723 | regval = rd32(E1000_RXSTMPL); |
a79f4f88 MV |
724 | regval = rd32(E1000_RXSTMPH); |
725 | ||
6ab5f7b2 | 726 | return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? |
a79f4f88 | 727 | -EFAULT : 0; |
d339b133 RC |
728 | } |
729 | ||
730 | void igb_ptp_init(struct igb_adapter *adapter) | |
731 | { | |
732 | struct e1000_hw *hw = &adapter->hw; | |
201987e3 | 733 | struct net_device *netdev = adapter->netdev; |
d339b133 RC |
734 | |
735 | switch (hw->mac.type) { | |
e57b8bdb MV |
736 | case e1000_82576: |
737 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); | |
738 | adapter->ptp_caps.owner = THIS_MODULE; | |
75517d92 | 739 | adapter->ptp_caps.max_adj = 999999881; |
e57b8bdb MV |
740 | adapter->ptp_caps.n_ext_ts = 0; |
741 | adapter->ptp_caps.pps = 0; | |
742 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; | |
743 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; | |
744 | adapter->ptp_caps.gettime = igb_ptp_gettime_82576; | |
745 | adapter->ptp_caps.settime = igb_ptp_settime_82576; | |
746 | adapter->ptp_caps.enable = igb_ptp_enable; | |
747 | adapter->cc.read = igb_ptp_read_82576; | |
748 | adapter->cc.mask = CLOCKSOURCE_MASK(64); | |
749 | adapter->cc.mult = 1; | |
750 | adapter->cc.shift = IGB_82576_TSYNC_SHIFT; | |
751 | /* Dial the nominal frequency. */ | |
752 | wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); | |
753 | break; | |
d339b133 | 754 | case e1000_82580: |
ceb5f13b | 755 | case e1000_i354: |
e57b8bdb | 756 | case e1000_i350: |
201987e3 | 757 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
a79f4f88 | 758 | adapter->ptp_caps.owner = THIS_MODULE; |
a79f4f88 MV |
759 | adapter->ptp_caps.max_adj = 62499999; |
760 | adapter->ptp_caps.n_ext_ts = 0; | |
761 | adapter->ptp_caps.pps = 0; | |
762 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; | |
e57b8bdb MV |
763 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; |
764 | adapter->ptp_caps.gettime = igb_ptp_gettime_82576; | |
765 | adapter->ptp_caps.settime = igb_ptp_settime_82576; | |
a79f4f88 MV |
766 | adapter->ptp_caps.enable = igb_ptp_enable; |
767 | adapter->cc.read = igb_ptp_read_82580; | |
768 | adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580); | |
769 | adapter->cc.mult = 1; | |
770 | adapter->cc.shift = 0; | |
d339b133 RC |
771 | /* Enable the timer functions by clearing bit 31. */ |
772 | wr32(E1000_TSAUXC, 0x0); | |
773 | break; | |
e57b8bdb MV |
774 | case e1000_i210: |
775 | case e1000_i211: | |
201987e3 | 776 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
a79f4f88 | 777 | adapter->ptp_caps.owner = THIS_MODULE; |
e57b8bdb | 778 | adapter->ptp_caps.max_adj = 62499999; |
a79f4f88 MV |
779 | adapter->ptp_caps.n_ext_ts = 0; |
780 | adapter->ptp_caps.pps = 0; | |
e57b8bdb MV |
781 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; |
782 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; | |
783 | adapter->ptp_caps.gettime = igb_ptp_gettime_i210; | |
784 | adapter->ptp_caps.settime = igb_ptp_settime_i210; | |
a79f4f88 | 785 | adapter->ptp_caps.enable = igb_ptp_enable; |
e57b8bdb MV |
786 | /* Enable the timer functions by clearing bit 31. */ |
787 | wr32(E1000_TSAUXC, 0x0); | |
d339b133 | 788 | break; |
d339b133 RC |
789 | default: |
790 | adapter->ptp_clock = NULL; | |
791 | return; | |
792 | } | |
793 | ||
794 | wrfl(); | |
795 | ||
e57b8bdb MV |
796 | spin_lock_init(&adapter->tmreg_lock); |
797 | INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); | |
d339b133 | 798 | |
e57b8bdb MV |
799 | /* Initialize the clock and overflow work for devices that need it. */ |
800 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { | |
801 | struct timespec ts = ktime_to_timespec(ktime_get_real()); | |
d339b133 | 802 | |
e57b8bdb MV |
803 | igb_ptp_settime_i210(&adapter->ptp_caps, &ts); |
804 | } else { | |
805 | timecounter_init(&adapter->tc, &adapter->cc, | |
806 | ktime_to_ns(ktime_get_real())); | |
d339b133 | 807 | |
e57b8bdb MV |
808 | INIT_DELAYED_WORK(&adapter->ptp_overflow_work, |
809 | igb_ptp_overflow_check); | |
1f6e8178 | 810 | |
e57b8bdb MV |
811 | schedule_delayed_work(&adapter->ptp_overflow_work, |
812 | IGB_SYSTIM_OVERFLOW_PERIOD); | |
813 | } | |
d339b133 | 814 | |
1f6e8178 MV |
815 | /* Initialize the time sync interrupts for devices that support it. */ |
816 | if (hw->mac.type >= e1000_82580) { | |
0c375ac1 | 817 | wr32(E1000_TSIM, TSYNC_INTERRUPTS); |
1f6e8178 MV |
818 | wr32(E1000_IMS, E1000_IMS_TS); |
819 | } | |
820 | ||
1ef76158 RC |
821 | adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, |
822 | &adapter->pdev->dev); | |
d339b133 RC |
823 | if (IS_ERR(adapter->ptp_clock)) { |
824 | adapter->ptp_clock = NULL; | |
825 | dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); | |
1f6e8178 | 826 | } else { |
d339b133 RC |
827 | dev_info(&adapter->pdev->dev, "added PHC on %s\n", |
828 | adapter->netdev->name); | |
1f6e8178 MV |
829 | adapter->flags |= IGB_FLAG_PTP; |
830 | } | |
d339b133 RC |
831 | } |
832 | ||
a79f4f88 MV |
833 | /** |
834 | * igb_ptp_stop - Disable PTP device and stop the overflow check. | |
835 | * @adapter: Board private structure. | |
836 | * | |
837 | * This function stops the PTP support and cancels the delayed work. | |
838 | **/ | |
839 | void igb_ptp_stop(struct igb_adapter *adapter) | |
d339b133 | 840 | { |
d3eef8c8 | 841 | switch (adapter->hw.mac.type) { |
d3eef8c8 | 842 | case e1000_82576: |
1f6e8178 | 843 | case e1000_82580: |
ceb5f13b | 844 | case e1000_i354: |
1f6e8178 | 845 | case e1000_i350: |
a79f4f88 | 846 | cancel_delayed_work_sync(&adapter->ptp_overflow_work); |
d3eef8c8 | 847 | break; |
1f6e8178 MV |
848 | case e1000_i210: |
849 | case e1000_i211: | |
850 | /* No delayed work to cancel. */ | |
851 | break; | |
d3eef8c8 CW |
852 | default: |
853 | return; | |
854 | } | |
d339b133 | 855 | |
1f6e8178 | 856 | cancel_work_sync(&adapter->ptp_tx_work); |
badc26dd MV |
857 | if (adapter->ptp_tx_skb) { |
858 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
859 | adapter->ptp_tx_skb = NULL; | |
860 | } | |
1f6e8178 | 861 | |
d339b133 RC |
862 | if (adapter->ptp_clock) { |
863 | ptp_clock_unregister(adapter->ptp_clock); | |
864 | dev_info(&adapter->pdev->dev, "removed PHC on %s\n", | |
865 | adapter->netdev->name); | |
1f6e8178 | 866 | adapter->flags &= ~IGB_FLAG_PTP; |
d339b133 RC |
867 | } |
868 | } | |
1f6e8178 MV |
869 | |
870 | /** | |
871 | * igb_ptp_reset - Re-enable the adapter for PTP following a reset. | |
872 | * @adapter: Board private structure. | |
873 | * | |
874 | * This function handles the reset work required to re-enable the PTP device. | |
875 | **/ | |
876 | void igb_ptp_reset(struct igb_adapter *adapter) | |
877 | { | |
878 | struct e1000_hw *hw = &adapter->hw; | |
879 | ||
880 | if (!(adapter->flags & IGB_FLAG_PTP)) | |
881 | return; | |
882 | ||
6ab5f7b2 JK |
883 | /* reset the tstamp_config */ |
884 | memset(&adapter->tstamp_config, 0, sizeof(adapter->tstamp_config)); | |
885 | ||
1f6e8178 MV |
886 | switch (adapter->hw.mac.type) { |
887 | case e1000_82576: | |
888 | /* Dial the nominal frequency. */ | |
889 | wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); | |
890 | break; | |
891 | case e1000_82580: | |
ceb5f13b | 892 | case e1000_i354: |
1f6e8178 MV |
893 | case e1000_i350: |
894 | case e1000_i210: | |
895 | case e1000_i211: | |
896 | /* Enable the timer functions and interrupts. */ | |
897 | wr32(E1000_TSAUXC, 0x0); | |
0c375ac1 | 898 | wr32(E1000_TSIM, TSYNC_INTERRUPTS); |
1f6e8178 MV |
899 | wr32(E1000_IMS, E1000_IMS_TS); |
900 | break; | |
901 | default: | |
902 | /* No work to do. */ | |
903 | return; | |
904 | } | |
905 | ||
e57b8bdb MV |
906 | /* Re-initialize the timer. */ |
907 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { | |
908 | struct timespec ts = ktime_to_timespec(ktime_get_real()); | |
909 | ||
910 | igb_ptp_settime_i210(&adapter->ptp_caps, &ts); | |
911 | } else { | |
912 | timecounter_init(&adapter->tc, &adapter->cc, | |
913 | ktime_to_ns(ktime_get_real())); | |
914 | } | |
1f6e8178 | 915 | } |