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ae06c70b | 1 | // SPDX-License-Identifier: GPL-2.0+ |
51dce24b JK |
2 | /* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */ |
3 | ||
d339b133 RC |
4 | #include <linux/module.h> |
5 | #include <linux/device.h> | |
6 | #include <linux/pci.h> | |
ba59814b | 7 | #include <linux/ptp_classify.h> |
d339b133 RC |
8 | |
9 | #include "igb.h" | |
10 | ||
11 | #define INCVALUE_MASK 0x7fffffff | |
12 | #define ISGN 0x80000000 | |
13 | ||
b980ac18 | 14 | /* The 82580 timesync updates the system timer every 8ns by 8ns, |
7ebae817 RC |
15 | * and this update value cannot be reprogrammed. |
16 | * | |
d339b133 RC |
17 | * Neither the 82576 nor the 82580 offer registers wide enough to hold |
18 | * nanoseconds time values for very long. For the 82580, SYSTIM always | |
dbedd44e | 19 | * counts nanoseconds, but the upper 24 bits are not available. The |
d339b133 RC |
20 | * frequency is adjusted by changing the 32 bit fractional nanoseconds |
21 | * register, TIMINCA. | |
22 | * | |
23 | * For the 82576, the SYSTIM register time unit is affect by the | |
24 | * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this | |
25 | * field are needed to provide the nominal 16 nanosecond period, | |
26 | * leaving 19 bits for fractional nanoseconds. | |
27 | * | |
7ebae817 RC |
28 | * We scale the NIC clock cycle by a large factor so that relatively |
29 | * small clock corrections can be added or subtracted at each clock | |
30 | * tick. The drawbacks of a large factor are a) that the clock | |
31 | * register overflows more quickly (not such a big deal) and b) that | |
32 | * the increment per tick has to fit into 24 bits. As a result we | |
33 | * need to use a shift of 19 so we can fit a value of 16 into the | |
34 | * TIMINCA register. | |
35 | * | |
d339b133 RC |
36 | * |
37 | * SYSTIMH SYSTIML | |
38 | * +--------------+ +---+---+------+ | |
39 | * 82576 | 32 | | 8 | 5 | 19 | | |
40 | * +--------------+ +---+---+------+ | |
41 | * \________ 45 bits _______/ fract | |
42 | * | |
43 | * +----------+---+ +--------------+ | |
44 | * 82580 | 24 | 8 | | 32 | | |
45 | * +----------+---+ +--------------+ | |
46 | * reserved \______ 40 bits _____/ | |
47 | * | |
48 | * | |
49 | * The 45 bit 82576 SYSTIM overflows every | |
50 | * 2^45 * 10^-9 / 3600 = 9.77 hours. | |
51 | * | |
52 | * The 40 bit 82580 SYSTIM overflows every | |
53 | * 2^40 * 10^-9 / 60 = 18.3 minutes. | |
094bf4d0 ML |
54 | * |
55 | * SYSTIM is converted to real time using a timecounter. As | |
4c9b658e ML |
56 | * timecounter_cyc2time() allows old timestamps, the timecounter needs |
57 | * to be updated at least once per half of the SYSTIM interval. | |
58 | * Scheduling of delayed work is not very accurate, and also the NIC | |
59 | * clock can be adjusted to run up to 6% faster and the system clock | |
60 | * up to 10% slower, so we aim for 6 minutes to be sure the actual | |
61 | * interval in the NIC time is shorter than 9.16 minutes. | |
d339b133 RC |
62 | */ |
63 | ||
4c9b658e | 64 | #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 6) |
428f1f71 | 65 | #define IGB_PTP_TX_TIMEOUT (HZ * 15) |
a51d8c21 JK |
66 | #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT) |
67 | #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0) | |
68 | #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT) | |
a79f4f88 | 69 | #define IGB_NBITS_82580 40 |
d339b133 | 70 | |
167f3f71 | 71 | static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); |
8ab55aba | 72 | static void igb_ptp_sdp_init(struct igb_adapter *adapter); |
167f3f71 | 73 | |
b980ac18 | 74 | /* SYSTIM read access for the 82576 */ |
a5a1d1c2 | 75 | static u64 igb_ptp_read_82576(const struct cyclecounter *cc) |
d339b133 | 76 | { |
d339b133 RC |
77 | struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
78 | struct e1000_hw *hw = &igb->hw; | |
a79f4f88 MV |
79 | u64 val; |
80 | u32 lo, hi; | |
d339b133 RC |
81 | |
82 | lo = rd32(E1000_SYSTIML); | |
83 | hi = rd32(E1000_SYSTIMH); | |
84 | ||
85 | val = ((u64) hi) << 32; | |
86 | val |= lo; | |
87 | ||
88 | return val; | |
89 | } | |
90 | ||
b980ac18 | 91 | /* SYSTIM read access for the 82580 */ |
a5a1d1c2 | 92 | static u64 igb_ptp_read_82580(const struct cyclecounter *cc) |
d339b133 | 93 | { |
d339b133 RC |
94 | struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
95 | struct e1000_hw *hw = &igb->hw; | |
e5c3370f | 96 | u32 lo, hi; |
a79f4f88 | 97 | u64 val; |
d339b133 | 98 | |
b980ac18 | 99 | /* The timestamp latches on lowest register read. For the 82580 |
7ebae817 RC |
100 | * the lowest register is SYSTIMR instead of SYSTIML. However we only |
101 | * need to provide nanosecond resolution, so we just ignore it. | |
102 | */ | |
e5c3370f | 103 | rd32(E1000_SYSTIMR); |
d339b133 RC |
104 | lo = rd32(E1000_SYSTIML); |
105 | hi = rd32(E1000_SYSTIMH); | |
106 | ||
107 | val = ((u64) hi) << 32; | |
108 | val |= lo; | |
109 | ||
110 | return val; | |
111 | } | |
112 | ||
b980ac18 | 113 | /* SYSTIM read access for I210/I211 */ |
d4c496fe RC |
114 | static void igb_ptp_read_i210(struct igb_adapter *adapter, |
115 | struct timespec64 *ts) | |
e57b8bdb MV |
116 | { |
117 | struct e1000_hw *hw = &adapter->hw; | |
e5c3370f | 118 | u32 sec, nsec; |
e57b8bdb | 119 | |
b980ac18 | 120 | /* The timestamp latches on lowest register read. For I210/I211, the |
e57b8bdb MV |
121 | * lowest register is SYSTIMR. Since we only need to provide nanosecond |
122 | * resolution, we can ignore it. | |
123 | */ | |
e5c3370f | 124 | rd32(E1000_SYSTIMR); |
e57b8bdb MV |
125 | nsec = rd32(E1000_SYSTIML); |
126 | sec = rd32(E1000_SYSTIMH); | |
127 | ||
128 | ts->tv_sec = sec; | |
129 | ts->tv_nsec = nsec; | |
130 | } | |
131 | ||
132 | static void igb_ptp_write_i210(struct igb_adapter *adapter, | |
d4c496fe | 133 | const struct timespec64 *ts) |
e57b8bdb MV |
134 | { |
135 | struct e1000_hw *hw = &adapter->hw; | |
136 | ||
b980ac18 | 137 | /* Writing the SYSTIMR register is not necessary as it only provides |
e57b8bdb MV |
138 | * sub-nanosecond resolution. |
139 | */ | |
140 | wr32(E1000_SYSTIML, ts->tv_nsec); | |
40c9b079 | 141 | wr32(E1000_SYSTIMH, (u32)ts->tv_sec); |
e57b8bdb MV |
142 | } |
143 | ||
a79f4f88 MV |
144 | /** |
145 | * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp | |
146 | * @adapter: board private structure | |
147 | * @hwtstamps: timestamp structure to update | |
148 | * @systim: unsigned 64bit system time value. | |
149 | * | |
150 | * We need to convert the system time value stored in the RX/TXSTMP registers | |
151 | * into a hwtstamp which can be used by the upper level timestamping functions. | |
152 | * | |
153 | * The 'tmreg_lock' spinlock is used to protect the consistency of the | |
154 | * system time value. This is needed because reading the 64 bit time | |
155 | * value involves reading two (or three) 32 bit registers. The first | |
156 | * read latches the value. Ditto for writing. | |
157 | * | |
158 | * In addition, here have extended the system time with an overflow | |
159 | * counter in software. | |
160 | **/ | |
161 | static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, | |
162 | struct skb_shared_hwtstamps *hwtstamps, | |
163 | u64 systim) | |
164 | { | |
165 | unsigned long flags; | |
166 | u64 ns; | |
167 | ||
168 | switch (adapter->hw.mac.type) { | |
e57b8bdb MV |
169 | case e1000_82576: |
170 | case e1000_82580: | |
ceb5f13b | 171 | case e1000_i354: |
e57b8bdb MV |
172 | case e1000_i350: |
173 | spin_lock_irqsave(&adapter->tmreg_lock, flags); | |
174 | ||
175 | ns = timecounter_cyc2time(&adapter->tc, systim); | |
176 | ||
177 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); | |
178 | ||
179 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
180 | hwtstamps->hwtstamp = ns_to_ktime(ns); | |
181 | break; | |
a79f4f88 MV |
182 | case e1000_i210: |
183 | case e1000_i211: | |
e57b8bdb MV |
184 | memset(hwtstamps, 0, sizeof(*hwtstamps)); |
185 | /* Upper 32 bits contain s, lower 32 bits contain ns. */ | |
186 | hwtstamps->hwtstamp = ktime_set(systim >> 32, | |
187 | systim & 0xFFFFFFFF); | |
a79f4f88 MV |
188 | break; |
189 | default: | |
e57b8bdb | 190 | break; |
a79f4f88 | 191 | } |
a79f4f88 MV |
192 | } |
193 | ||
b980ac18 | 194 | /* PTP clock operations */ |
a79f4f88 | 195 | static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) |
d339b133 | 196 | { |
a79f4f88 MV |
197 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
198 | ptp_caps); | |
199 | struct e1000_hw *hw = &igb->hw; | |
200 | int neg_adj = 0; | |
d339b133 RC |
201 | u64 rate; |
202 | u32 incvalue; | |
d339b133 RC |
203 | |
204 | if (ppb < 0) { | |
205 | neg_adj = 1; | |
206 | ppb = -ppb; | |
207 | } | |
208 | rate = ppb; | |
209 | rate <<= 14; | |
210 | rate = div_u64(rate, 1953125); | |
211 | ||
212 | incvalue = 16 << IGB_82576_TSYNC_SHIFT; | |
213 | ||
214 | if (neg_adj) | |
215 | incvalue -= rate; | |
216 | else | |
217 | incvalue += rate; | |
218 | ||
219 | wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); | |
220 | ||
221 | return 0; | |
222 | } | |
223 | ||
c79e975e | 224 | static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm) |
d339b133 | 225 | { |
a79f4f88 MV |
226 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
227 | ptp_caps); | |
228 | struct e1000_hw *hw = &igb->hw; | |
229 | int neg_adj = 0; | |
d339b133 RC |
230 | u64 rate; |
231 | u32 inca; | |
d339b133 | 232 | |
c79e975e | 233 | if (scaled_ppm < 0) { |
d339b133 | 234 | neg_adj = 1; |
c79e975e | 235 | scaled_ppm = -scaled_ppm; |
d339b133 | 236 | } |
c79e975e RC |
237 | rate = scaled_ppm; |
238 | rate <<= 13; | |
239 | rate = div_u64(rate, 15625); | |
d339b133 RC |
240 | |
241 | inca = rate & INCVALUE_MASK; | |
242 | if (neg_adj) | |
243 | inca |= ISGN; | |
244 | ||
245 | wr32(E1000_TIMINCA, inca); | |
246 | ||
247 | return 0; | |
248 | } | |
249 | ||
e57b8bdb | 250 | static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) |
d339b133 | 251 | { |
a79f4f88 MV |
252 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
253 | ptp_caps); | |
d339b133 | 254 | unsigned long flags; |
d339b133 RC |
255 | |
256 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
5ee698e3 | 257 | timecounter_adjtime(&igb->tc, delta); |
d339b133 RC |
258 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
e57b8bdb MV |
263 | static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) |
264 | { | |
265 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
266 | ptp_caps); | |
267 | unsigned long flags; | |
d4c496fe | 268 | struct timespec64 now, then = ns_to_timespec64(delta); |
e57b8bdb MV |
269 | |
270 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
271 | ||
272 | igb_ptp_read_i210(igb, &now); | |
d4c496fe RC |
273 | now = timespec64_add(now, then); |
274 | igb_ptp_write_i210(igb, (const struct timespec64 *)&now); | |
e57b8bdb MV |
275 | |
276 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
cff8ba28 ML |
281 | static int igb_ptp_gettimex_82576(struct ptp_clock_info *ptp, |
282 | struct timespec64 *ts, | |
283 | struct ptp_system_timestamp *sts) | |
d339b133 | 284 | { |
a79f4f88 MV |
285 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
286 | ptp_caps); | |
cff8ba28 | 287 | struct e1000_hw *hw = &igb->hw; |
a79f4f88 | 288 | unsigned long flags; |
cff8ba28 | 289 | u32 lo, hi; |
d339b133 | 290 | u64 ns; |
d339b133 RC |
291 | |
292 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
293 | ||
cff8ba28 ML |
294 | ptp_read_system_prets(sts); |
295 | lo = rd32(E1000_SYSTIML); | |
296 | ptp_read_system_postts(sts); | |
297 | hi = rd32(E1000_SYSTIMH); | |
298 | ||
299 | ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); | |
300 | ||
301 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
302 | ||
303 | *ts = ns_to_timespec64(ns); | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | static int igb_ptp_gettimex_82580(struct ptp_clock_info *ptp, | |
309 | struct timespec64 *ts, | |
310 | struct ptp_system_timestamp *sts) | |
311 | { | |
312 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
313 | ptp_caps); | |
314 | struct e1000_hw *hw = &igb->hw; | |
315 | unsigned long flags; | |
316 | u32 lo, hi; | |
317 | u64 ns; | |
318 | ||
319 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
320 | ||
321 | ptp_read_system_prets(sts); | |
322 | rd32(E1000_SYSTIMR); | |
323 | ptp_read_system_postts(sts); | |
324 | lo = rd32(E1000_SYSTIML); | |
325 | hi = rd32(E1000_SYSTIMH); | |
326 | ||
327 | ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); | |
d339b133 RC |
328 | |
329 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
330 | ||
350f66d5 | 331 | *ts = ns_to_timespec64(ns); |
d339b133 RC |
332 | |
333 | return 0; | |
334 | } | |
335 | ||
cff8ba28 ML |
336 | static int igb_ptp_gettimex_i210(struct ptp_clock_info *ptp, |
337 | struct timespec64 *ts, | |
338 | struct ptp_system_timestamp *sts) | |
e57b8bdb MV |
339 | { |
340 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
341 | ptp_caps); | |
cff8ba28 | 342 | struct e1000_hw *hw = &igb->hw; |
e57b8bdb MV |
343 | unsigned long flags; |
344 | ||
345 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
346 | ||
cff8ba28 ML |
347 | ptp_read_system_prets(sts); |
348 | rd32(E1000_SYSTIMR); | |
349 | ptp_read_system_postts(sts); | |
350 | ts->tv_nsec = rd32(E1000_SYSTIML); | |
351 | ts->tv_sec = rd32(E1000_SYSTIMH); | |
e57b8bdb MV |
352 | |
353 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, | |
d4c496fe | 359 | const struct timespec64 *ts) |
d339b133 | 360 | { |
a79f4f88 MV |
361 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
362 | ptp_caps); | |
d339b133 | 363 | unsigned long flags; |
a79f4f88 | 364 | u64 ns; |
d339b133 | 365 | |
350f66d5 | 366 | ns = timespec64_to_ns(ts); |
d339b133 RC |
367 | |
368 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
369 | ||
370 | timecounter_init(&igb->tc, &igb->cc, ns); | |
371 | ||
372 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
e57b8bdb | 377 | static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, |
d4c496fe | 378 | const struct timespec64 *ts) |
e57b8bdb MV |
379 | { |
380 | struct igb_adapter *igb = container_of(ptp, struct igb_adapter, | |
381 | ptp_caps); | |
382 | unsigned long flags; | |
383 | ||
384 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
385 | ||
386 | igb_ptp_write_i210(igb, ts); | |
387 | ||
388 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
720db4ff RC |
393 | static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) |
394 | { | |
395 | u32 *ptr = pin < 2 ? ctrl : ctrl_ext; | |
b23c0cc5 | 396 | static const u32 mask[IGB_N_SDP] = { |
720db4ff RC |
397 | E1000_CTRL_SDP0_DIR, |
398 | E1000_CTRL_SDP1_DIR, | |
399 | E1000_CTRL_EXT_SDP2_DIR, | |
400 | E1000_CTRL_EXT_SDP3_DIR, | |
401 | }; | |
402 | ||
403 | if (input) | |
404 | *ptr &= ~mask[pin]; | |
405 | else | |
406 | *ptr |= mask[pin]; | |
407 | } | |
408 | ||
409 | static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) | |
410 | { | |
b23c0cc5 | 411 | static const u32 aux0_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
412 | AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, |
413 | }; | |
b23c0cc5 | 414 | static const u32 aux1_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
415 | AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, |
416 | }; | |
b23c0cc5 | 417 | static const u32 ts_sdp_en[IGB_N_SDP] = { |
720db4ff RC |
418 | TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, |
419 | }; | |
b23c0cc5 | 420 | struct e1000_hw *hw = &igb->hw; |
720db4ff RC |
421 | u32 ctrl, ctrl_ext, tssdp = 0; |
422 | ||
423 | ctrl = rd32(E1000_CTRL); | |
424 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
425 | tssdp = rd32(E1000_TSSDP); | |
426 | ||
427 | igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); | |
428 | ||
429 | /* Make sure this pin is not enabled as an output. */ | |
430 | tssdp &= ~ts_sdp_en[pin]; | |
431 | ||
432 | if (chan == 1) { | |
433 | tssdp &= ~AUX1_SEL_SDP3; | |
434 | tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; | |
435 | } else { | |
436 | tssdp &= ~AUX0_SEL_SDP3; | |
437 | tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; | |
438 | } | |
439 | ||
440 | wr32(E1000_TSSDP, tssdp); | |
441 | wr32(E1000_CTRL, ctrl); | |
442 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
443 | } | |
444 | ||
30c72916 | 445 | static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq) |
720db4ff | 446 | { |
b23c0cc5 | 447 | static const u32 aux0_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
448 | AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, |
449 | }; | |
b23c0cc5 | 450 | static const u32 aux1_sel_sdp[IGB_N_SDP] = { |
720db4ff RC |
451 | AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, |
452 | }; | |
b23c0cc5 | 453 | static const u32 ts_sdp_en[IGB_N_SDP] = { |
720db4ff RC |
454 | TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, |
455 | }; | |
b23c0cc5 | 456 | static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = { |
720db4ff RC |
457 | TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0, |
458 | TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0, | |
459 | }; | |
b23c0cc5 | 460 | static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = { |
720db4ff RC |
461 | TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1, |
462 | TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1, | |
463 | }; | |
30c72916 RC |
464 | static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = { |
465 | TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0, | |
466 | TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0, | |
467 | }; | |
468 | static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = { | |
469 | TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, | |
470 | TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, | |
471 | }; | |
b23c0cc5 | 472 | static const u32 ts_sdp_sel_clr[IGB_N_SDP] = { |
720db4ff RC |
473 | TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, |
474 | TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, | |
475 | }; | |
b23c0cc5 | 476 | struct e1000_hw *hw = &igb->hw; |
720db4ff RC |
477 | u32 ctrl, ctrl_ext, tssdp = 0; |
478 | ||
479 | ctrl = rd32(E1000_CTRL); | |
480 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
481 | tssdp = rd32(E1000_TSSDP); | |
482 | ||
483 | igb_pin_direction(pin, 0, &ctrl, &ctrl_ext); | |
484 | ||
485 | /* Make sure this pin is not enabled as an input. */ | |
486 | if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin]) | |
487 | tssdp &= ~AUX0_TS_SDP_EN; | |
488 | ||
489 | if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin]) | |
490 | tssdp &= ~AUX1_TS_SDP_EN; | |
491 | ||
492 | tssdp &= ~ts_sdp_sel_clr[pin]; | |
30c72916 RC |
493 | if (freq) { |
494 | if (chan == 1) | |
495 | tssdp |= ts_sdp_sel_fc1[pin]; | |
496 | else | |
497 | tssdp |= ts_sdp_sel_fc0[pin]; | |
498 | } else { | |
499 | if (chan == 1) | |
500 | tssdp |= ts_sdp_sel_tt1[pin]; | |
501 | else | |
502 | tssdp |= ts_sdp_sel_tt0[pin]; | |
503 | } | |
720db4ff RC |
504 | tssdp |= ts_sdp_en[pin]; |
505 | ||
506 | wr32(E1000_TSSDP, tssdp); | |
507 | wr32(E1000_CTRL, ctrl); | |
508 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
509 | } | |
510 | ||
1819fc75 RB |
511 | static int igb_ptp_feature_enable_82580(struct ptp_clock_info *ptp, |
512 | struct ptp_clock_request *rq, int on) | |
513 | { | |
514 | struct igb_adapter *igb = | |
515 | container_of(ptp, struct igb_adapter, ptp_caps); | |
516 | u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, systiml, | |
517 | systimh, level_mask, level, rem; | |
518 | struct e1000_hw *hw = &igb->hw; | |
519 | struct timespec64 ts, start; | |
520 | unsigned long flags; | |
521 | u64 systim, now; | |
522 | int pin = -1; | |
523 | s64 ns; | |
524 | ||
525 | switch (rq->type) { | |
526 | case PTP_CLK_REQ_EXTTS: | |
38970eac RB |
527 | /* Reject requests with unsupported flags */ |
528 | if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | | |
529 | PTP_RISING_EDGE | | |
530 | PTP_FALLING_EDGE | | |
531 | PTP_STRICT_FLAGS)) | |
532 | return -EOPNOTSUPP; | |
533 | ||
534 | if (on) { | |
535 | pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, | |
536 | rq->extts.index); | |
537 | if (pin < 0) | |
538 | return -EBUSY; | |
539 | } | |
540 | if (rq->extts.index == 1) { | |
541 | tsauxc_mask = TSAUXC_EN_TS1; | |
542 | tsim_mask = TSINTR_AUTT1; | |
543 | } else { | |
544 | tsauxc_mask = TSAUXC_EN_TS0; | |
545 | tsim_mask = TSINTR_AUTT0; | |
546 | } | |
547 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
548 | tsauxc = rd32(E1000_TSAUXC); | |
549 | tsim = rd32(E1000_TSIM); | |
550 | if (on) { | |
551 | igb_pin_extts(igb, rq->extts.index, pin); | |
552 | tsauxc |= tsauxc_mask; | |
553 | tsim |= tsim_mask; | |
554 | } else { | |
555 | tsauxc &= ~tsauxc_mask; | |
556 | tsim &= ~tsim_mask; | |
557 | } | |
558 | wr32(E1000_TSAUXC, tsauxc); | |
559 | wr32(E1000_TSIM, tsim); | |
560 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
561 | return 0; | |
1819fc75 RB |
562 | |
563 | case PTP_CLK_REQ_PEROUT: | |
564 | /* Reject requests with unsupported flags */ | |
565 | if (rq->perout.flags) | |
566 | return -EOPNOTSUPP; | |
567 | ||
568 | if (on) { | |
569 | pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, | |
570 | rq->perout.index); | |
571 | if (pin < 0) | |
572 | return -EBUSY; | |
573 | } | |
574 | ts.tv_sec = rq->perout.period.sec; | |
575 | ts.tv_nsec = rq->perout.period.nsec; | |
576 | ns = timespec64_to_ns(&ts); | |
577 | ns = ns >> 1; | |
578 | if (on && ns < 8LL) | |
579 | return -EINVAL; | |
580 | ts = ns_to_timespec64(ns); | |
581 | if (rq->perout.index == 1) { | |
582 | tsauxc_mask = TSAUXC_EN_TT1; | |
583 | tsim_mask = TSINTR_TT1; | |
584 | trgttiml = E1000_TRGTTIML1; | |
585 | trgttimh = E1000_TRGTTIMH1; | |
586 | } else { | |
587 | tsauxc_mask = TSAUXC_EN_TT0; | |
588 | tsim_mask = TSINTR_TT0; | |
589 | trgttiml = E1000_TRGTTIML0; | |
590 | trgttimh = E1000_TRGTTIMH0; | |
591 | } | |
592 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
593 | tsauxc = rd32(E1000_TSAUXC); | |
594 | tsim = rd32(E1000_TSIM); | |
595 | if (rq->perout.index == 1) { | |
596 | tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); | |
597 | tsim &= ~TSINTR_TT1; | |
598 | } else { | |
599 | tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); | |
600 | tsim &= ~TSINTR_TT0; | |
601 | } | |
602 | if (on) { | |
603 | int i = rq->perout.index; | |
604 | ||
605 | /* read systim registers in sequence */ | |
606 | rd32(E1000_SYSTIMR); | |
607 | systiml = rd32(E1000_SYSTIML); | |
608 | systimh = rd32(E1000_SYSTIMH); | |
609 | systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); | |
610 | now = timecounter_cyc2time(&igb->tc, systim); | |
611 | ||
612 | if (pin < 2) { | |
613 | level_mask = (i == 1) ? 0x80000 : 0x40000; | |
614 | level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; | |
615 | } else { | |
616 | level_mask = (i == 1) ? 0x80 : 0x40; | |
617 | level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; | |
618 | } | |
619 | ||
620 | div_u64_rem(now, ns, &rem); | |
621 | systim = systim + (ns - rem); | |
622 | ||
623 | /* synchronize pin level with rising/falling edges */ | |
624 | div_u64_rem(now, ns << 1, &rem); | |
625 | if (rem < ns) { | |
626 | /* first half of period */ | |
627 | if (level == 0) { | |
628 | /* output is already low, skip this period */ | |
629 | systim += ns; | |
630 | } | |
631 | } else { | |
632 | /* second half of period */ | |
633 | if (level == 1) { | |
634 | /* output is already high, skip this period */ | |
635 | systim += ns; | |
636 | } | |
637 | } | |
638 | ||
639 | start = ns_to_timespec64(systim + (ns - rem)); | |
640 | igb_pin_perout(igb, i, pin, 0); | |
641 | igb->perout[i].start.tv_sec = start.tv_sec; | |
642 | igb->perout[i].start.tv_nsec = start.tv_nsec; | |
643 | igb->perout[i].period.tv_sec = ts.tv_sec; | |
644 | igb->perout[i].period.tv_nsec = ts.tv_nsec; | |
645 | ||
646 | wr32(trgttiml, (u32)systim); | |
647 | wr32(trgttimh, ((u32)(systim >> 32)) & 0xFF); | |
648 | tsauxc |= tsauxc_mask; | |
649 | tsim |= tsim_mask; | |
650 | } | |
651 | wr32(E1000_TSAUXC, tsauxc); | |
652 | wr32(E1000_TSIM, tsim); | |
653 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
654 | return 0; | |
655 | ||
656 | case PTP_CLK_REQ_PPS: | |
657 | return -EOPNOTSUPP; | |
658 | } | |
659 | ||
660 | return -EOPNOTSUPP; | |
661 | } | |
662 | ||
00c65578 RC |
663 | static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp, |
664 | struct ptp_clock_request *rq, int on) | |
665 | { | |
666 | struct igb_adapter *igb = | |
667 | container_of(ptp, struct igb_adapter, ptp_caps); | |
668 | struct e1000_hw *hw = &igb->hw; | |
30c72916 | 669 | u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; |
00c65578 | 670 | unsigned long flags; |
40c9b079 | 671 | struct timespec64 ts; |
30c72916 | 672 | int use_freq = 0, pin = -1; |
720db4ff | 673 | s64 ns; |
00c65578 RC |
674 | |
675 | switch (rq->type) { | |
720db4ff | 676 | case PTP_CLK_REQ_EXTTS: |
6edd110b JK |
677 | /* Reject requests with unsupported flags */ |
678 | if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | | |
679 | PTP_RISING_EDGE | | |
6138e687 RC |
680 | PTP_FALLING_EDGE | |
681 | PTP_STRICT_FLAGS)) | |
6edd110b JK |
682 | return -EOPNOTSUPP; |
683 | ||
5a450eb3 RC |
684 | /* Reject requests failing to enable both edges. */ |
685 | if ((rq->extts.flags & PTP_STRICT_FLAGS) && | |
686 | (rq->extts.flags & PTP_ENABLE_FEATURE) && | |
687 | (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES) | |
688 | return -EOPNOTSUPP; | |
689 | ||
720db4ff RC |
690 | if (on) { |
691 | pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, | |
692 | rq->extts.index); | |
693 | if (pin < 0) | |
694 | return -EBUSY; | |
695 | } | |
696 | if (rq->extts.index == 1) { | |
697 | tsauxc_mask = TSAUXC_EN_TS1; | |
698 | tsim_mask = TSINTR_AUTT1; | |
699 | } else { | |
700 | tsauxc_mask = TSAUXC_EN_TS0; | |
701 | tsim_mask = TSINTR_AUTT0; | |
702 | } | |
703 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
704 | tsauxc = rd32(E1000_TSAUXC); | |
705 | tsim = rd32(E1000_TSIM); | |
706 | if (on) { | |
707 | igb_pin_extts(igb, rq->extts.index, pin); | |
708 | tsauxc |= tsauxc_mask; | |
709 | tsim |= tsim_mask; | |
710 | } else { | |
711 | tsauxc &= ~tsauxc_mask; | |
712 | tsim &= ~tsim_mask; | |
713 | } | |
714 | wr32(E1000_TSAUXC, tsauxc); | |
715 | wr32(E1000_TSIM, tsim); | |
716 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
717 | return 0; | |
718 | ||
719 | case PTP_CLK_REQ_PEROUT: | |
7f9048f1 JK |
720 | /* Reject requests with unsupported flags */ |
721 | if (rq->perout.flags) | |
722 | return -EOPNOTSUPP; | |
723 | ||
720db4ff RC |
724 | if (on) { |
725 | pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, | |
726 | rq->perout.index); | |
727 | if (pin < 0) | |
728 | return -EBUSY; | |
729 | } | |
730 | ts.tv_sec = rq->perout.period.sec; | |
731 | ts.tv_nsec = rq->perout.period.nsec; | |
40c9b079 | 732 | ns = timespec64_to_ns(&ts); |
720db4ff | 733 | ns = ns >> 1; |
569f3b3d RH |
734 | if (on && ((ns <= 70000000LL) || (ns == 125000000LL) || |
735 | (ns == 250000000LL) || (ns == 500000000LL))) { | |
30c72916 RC |
736 | if (ns < 8LL) |
737 | return -EINVAL; | |
738 | use_freq = 1; | |
720db4ff | 739 | } |
40c9b079 | 740 | ts = ns_to_timespec64(ns); |
720db4ff | 741 | if (rq->perout.index == 1) { |
30c72916 RC |
742 | if (use_freq) { |
743 | tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1; | |
744 | tsim_mask = 0; | |
745 | } else { | |
746 | tsauxc_mask = TSAUXC_EN_TT1; | |
747 | tsim_mask = TSINTR_TT1; | |
748 | } | |
720db4ff RC |
749 | trgttiml = E1000_TRGTTIML1; |
750 | trgttimh = E1000_TRGTTIMH1; | |
30c72916 | 751 | freqout = E1000_FREQOUT1; |
720db4ff | 752 | } else { |
30c72916 RC |
753 | if (use_freq) { |
754 | tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0; | |
755 | tsim_mask = 0; | |
756 | } else { | |
757 | tsauxc_mask = TSAUXC_EN_TT0; | |
758 | tsim_mask = TSINTR_TT0; | |
759 | } | |
720db4ff RC |
760 | trgttiml = E1000_TRGTTIML0; |
761 | trgttimh = E1000_TRGTTIMH0; | |
30c72916 | 762 | freqout = E1000_FREQOUT0; |
720db4ff RC |
763 | } |
764 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
765 | tsauxc = rd32(E1000_TSAUXC); | |
766 | tsim = rd32(E1000_TSIM); | |
30c72916 RC |
767 | if (rq->perout.index == 1) { |
768 | tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); | |
769 | tsim &= ~TSINTR_TT1; | |
770 | } else { | |
771 | tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); | |
772 | tsim &= ~TSINTR_TT0; | |
773 | } | |
720db4ff RC |
774 | if (on) { |
775 | int i = rq->perout.index; | |
30c72916 | 776 | igb_pin_perout(igb, i, pin, use_freq); |
720db4ff RC |
777 | igb->perout[i].start.tv_sec = rq->perout.start.sec; |
778 | igb->perout[i].start.tv_nsec = rq->perout.start.nsec; | |
779 | igb->perout[i].period.tv_sec = ts.tv_sec; | |
780 | igb->perout[i].period.tv_nsec = ts.tv_nsec; | |
58c98be1 RC |
781 | wr32(trgttimh, rq->perout.start.sec); |
782 | wr32(trgttiml, rq->perout.start.nsec); | |
30c72916 RC |
783 | if (use_freq) |
784 | wr32(freqout, ns); | |
720db4ff RC |
785 | tsauxc |= tsauxc_mask; |
786 | tsim |= tsim_mask; | |
720db4ff RC |
787 | } |
788 | wr32(E1000_TSAUXC, tsauxc); | |
789 | wr32(E1000_TSIM, tsim); | |
790 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
791 | return 0; | |
792 | ||
00c65578 RC |
793 | case PTP_CLK_REQ_PPS: |
794 | spin_lock_irqsave(&igb->tmreg_lock, flags); | |
795 | tsim = rd32(E1000_TSIM); | |
796 | if (on) | |
797 | tsim |= TSINTR_SYS_WRAP; | |
798 | else | |
799 | tsim &= ~TSINTR_SYS_WRAP; | |
ac28b41a | 800 | igb->pps_sys_wrap_on = !!on; |
00c65578 RC |
801 | wr32(E1000_TSIM, tsim); |
802 | spin_unlock_irqrestore(&igb->tmreg_lock, flags); | |
803 | return 0; | |
00c65578 RC |
804 | } |
805 | ||
806 | return -EOPNOTSUPP; | |
807 | } | |
808 | ||
102be52f JK |
809 | static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, |
810 | struct ptp_clock_request *rq, int on) | |
d339b133 RC |
811 | { |
812 | return -EOPNOTSUPP; | |
813 | } | |
814 | ||
720db4ff RC |
815 | static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, |
816 | enum ptp_pin_function func, unsigned int chan) | |
817 | { | |
818 | switch (func) { | |
819 | case PTP_PF_NONE: | |
820 | case PTP_PF_EXTTS: | |
821 | case PTP_PF_PEROUT: | |
822 | break; | |
823 | case PTP_PF_PHYSYNC: | |
824 | return -1; | |
825 | } | |
826 | return 0; | |
827 | } | |
828 | ||
1f6e8178 MV |
829 | /** |
830 | * igb_ptp_tx_work | |
831 | * @work: pointer to work struct | |
832 | * | |
833 | * This work function polls the TSYNCTXCTL valid bit to determine when a | |
834 | * timestamp has been taken for the current stored skb. | |
b980ac18 | 835 | **/ |
167f3f71 | 836 | static void igb_ptp_tx_work(struct work_struct *work) |
1f6e8178 MV |
837 | { |
838 | struct igb_adapter *adapter = container_of(work, struct igb_adapter, | |
839 | ptp_tx_work); | |
840 | struct e1000_hw *hw = &adapter->hw; | |
841 | u32 tsynctxctl; | |
842 | ||
843 | if (!adapter->ptp_tx_skb) | |
844 | return; | |
845 | ||
428f1f71 MV |
846 | if (time_is_before_jiffies(adapter->ptp_tx_start + |
847 | IGB_PTP_TX_TIMEOUT)) { | |
848 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
849 | adapter->ptp_tx_skb = NULL; | |
ed4420a3 | 850 | clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
428f1f71 | 851 | adapter->tx_hwtstamp_timeouts++; |
3a532852 DH |
852 | /* Clear the tx valid bit in TSYNCTXCTL register to enable |
853 | * interrupt | |
854 | */ | |
855 | rd32(E1000_TXSTMPH); | |
c5ffe7e1 | 856 | dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); |
428f1f71 MV |
857 | return; |
858 | } | |
859 | ||
1f6e8178 MV |
860 | tsynctxctl = rd32(E1000_TSYNCTXCTL); |
861 | if (tsynctxctl & E1000_TSYNCTXCTL_VALID) | |
862 | igb_ptp_tx_hwtstamp(adapter); | |
863 | else | |
864 | /* reschedule to check later */ | |
865 | schedule_work(&adapter->ptp_tx_work); | |
866 | } | |
867 | ||
a79f4f88 | 868 | static void igb_ptp_overflow_check(struct work_struct *work) |
d339b133 | 869 | { |
a79f4f88 MV |
870 | struct igb_adapter *igb = |
871 | container_of(work, struct igb_adapter, ptp_overflow_work.work); | |
d4c496fe | 872 | struct timespec64 ts; |
cff8ba28 | 873 | u64 ns; |
a79f4f88 | 874 | |
cff8ba28 ML |
875 | /* Update the timecounter */ |
876 | ns = timecounter_read(&igb->tc); | |
a79f4f88 | 877 | |
cff8ba28 | 878 | ts = ns_to_timespec64(ns); |
32eaf120 DM |
879 | pr_debug("igb overflow check at %lld.%09lu\n", |
880 | (long long) ts.tv_sec, ts.tv_nsec); | |
a79f4f88 MV |
881 | |
882 | schedule_delayed_work(&igb->ptp_overflow_work, | |
883 | IGB_SYSTIM_OVERFLOW_PERIOD); | |
d339b133 RC |
884 | } |
885 | ||
fc580751 MV |
886 | /** |
887 | * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched | |
888 | * @adapter: private network adapter structure | |
889 | * | |
890 | * This watchdog task is scheduled to detect error case where hardware has | |
891 | * dropped an Rx packet that was timestamped when the ring is full. The | |
892 | * particular error is rare but leaves the device in a state unable to timestamp | |
893 | * any future packets. | |
b980ac18 | 894 | **/ |
fc580751 MV |
895 | void igb_ptp_rx_hang(struct igb_adapter *adapter) |
896 | { | |
897 | struct e1000_hw *hw = &adapter->hw; | |
fc580751 MV |
898 | u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); |
899 | unsigned long rx_event; | |
fc580751 | 900 | |
462f1188 | 901 | /* Other hardware uses per-packet timestamps */ |
fc580751 MV |
902 | if (hw->mac.type != e1000_82576) |
903 | return; | |
904 | ||
905 | /* If we don't have a valid timestamp in the registers, just update the | |
906 | * timeout counter and exit | |
907 | */ | |
908 | if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { | |
909 | adapter->last_rx_ptp_check = jiffies; | |
910 | return; | |
911 | } | |
912 | ||
913 | /* Determine the most recent watchdog or rx_timestamp event */ | |
914 | rx_event = adapter->last_rx_ptp_check; | |
5499a968 JK |
915 | if (time_after(adapter->last_rx_timestamp, rx_event)) |
916 | rx_event = adapter->last_rx_timestamp; | |
fc580751 MV |
917 | |
918 | /* Only need to read the high RXSTMP register to clear the lock */ | |
919 | if (time_is_before_jiffies(rx_event + 5 * HZ)) { | |
920 | rd32(E1000_RXSTMPH); | |
921 | adapter->last_rx_ptp_check = jiffies; | |
922 | adapter->rx_hwtstamp_cleared++; | |
c5ffe7e1 | 923 | dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); |
fc580751 MV |
924 | } |
925 | } | |
926 | ||
e5f36ad1 JK |
927 | /** |
928 | * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes | |
929 | * @adapter: private network adapter structure | |
930 | */ | |
931 | void igb_ptp_tx_hang(struct igb_adapter *adapter) | |
932 | { | |
3a532852 | 933 | struct e1000_hw *hw = &adapter->hw; |
e5f36ad1 JK |
934 | bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + |
935 | IGB_PTP_TX_TIMEOUT); | |
936 | ||
937 | if (!adapter->ptp_tx_skb) | |
938 | return; | |
939 | ||
940 | if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state)) | |
941 | return; | |
942 | ||
943 | /* If we haven't received a timestamp within the timeout, it is | |
944 | * reasonable to assume that it will never occur, so we can unlock the | |
945 | * timestamp bit when this occurs. | |
946 | */ | |
947 | if (timeout) { | |
948 | cancel_work_sync(&adapter->ptp_tx_work); | |
949 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
950 | adapter->ptp_tx_skb = NULL; | |
951 | clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); | |
952 | adapter->tx_hwtstamp_timeouts++; | |
3a532852 DH |
953 | /* Clear the tx valid bit in TSYNCTXCTL register to enable |
954 | * interrupt | |
955 | */ | |
956 | rd32(E1000_TXSTMPH); | |
e5f36ad1 JK |
957 | dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); |
958 | } | |
959 | } | |
960 | ||
a79f4f88 MV |
961 | /** |
962 | * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp | |
1f6e8178 | 963 | * @adapter: Board private structure. |
a79f4f88 MV |
964 | * |
965 | * If we were asked to do hardware stamping and such a time stamp is | |
966 | * available, then it must have been for this skb here because we only | |
967 | * allow only one such packet into the queue. | |
b980ac18 | 968 | **/ |
167f3f71 | 969 | static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) |
d339b133 | 970 | { |
4ccdc013 | 971 | struct sk_buff *skb = adapter->ptp_tx_skb; |
a79f4f88 MV |
972 | struct e1000_hw *hw = &adapter->hw; |
973 | struct skb_shared_hwtstamps shhwtstamps; | |
974 | u64 regval; | |
3f544d2a | 975 | int adjust = 0; |
d339b133 | 976 | |
a79f4f88 MV |
977 | regval = rd32(E1000_TXSTMPL); |
978 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
d339b133 | 979 | |
a79f4f88 | 980 | igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); |
3f544d2a NS |
981 | /* adjust timestamp for the TX latency based on link speed */ |
982 | if (adapter->hw.mac.type == e1000_i210) { | |
983 | switch (adapter->link_speed) { | |
984 | case SPEED_10: | |
985 | adjust = IGB_I210_TX_LATENCY_10; | |
986 | break; | |
987 | case SPEED_100: | |
988 | adjust = IGB_I210_TX_LATENCY_100; | |
989 | break; | |
990 | case SPEED_1000: | |
991 | adjust = IGB_I210_TX_LATENCY_1000; | |
992 | break; | |
993 | } | |
994 | } | |
995 | ||
0066c8b6 KG |
996 | shhwtstamps.hwtstamp = |
997 | ktime_add_ns(shhwtstamps.hwtstamp, adjust); | |
3f544d2a | 998 | |
4ccdc013 JK |
999 | /* Clear the lock early before calling skb_tstamp_tx so that |
1000 | * applications are not woken up before the lock bit is clear. We use | |
1001 | * a copy of the skb pointer to ensure other threads can't change it | |
1002 | * while we're notifying the stack. | |
1003 | */ | |
1f6e8178 | 1004 | adapter->ptp_tx_skb = NULL; |
ed4420a3 | 1005 | clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
4ccdc013 JK |
1006 | |
1007 | /* Notify the stack and free the skb after we've unlocked */ | |
1008 | skb_tstamp_tx(skb, &shhwtstamps); | |
1009 | dev_kfree_skb_any(skb); | |
a79f4f88 MV |
1010 | } |
1011 | ||
b534550a AD |
1012 | /** |
1013 | * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp | |
1014 | * @q_vector: Pointer to interrupt specific structure | |
1015 | * @va: Pointer to address containing Rx buffer | |
53792608 | 1016 | * @timestamp: Pointer where timestamp will be stored |
b534550a AD |
1017 | * |
1018 | * This function is meant to retrieve a timestamp from the first buffer of an | |
1019 | * incoming frame. The value is stored in little endian format starting on | |
f0a03a02 JB |
1020 | * byte 8 |
1021 | * | |
53792608 | 1022 | * Returns: The timestamp header length or 0 if not available |
b980ac18 | 1023 | **/ |
f0a03a02 | 1024 | int igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va, |
53792608 | 1025 | ktime_t *timestamp) |
b534550a | 1026 | { |
0066c8b6 | 1027 | struct igb_adapter *adapter = q_vector->adapter; |
53792608 | 1028 | struct skb_shared_hwtstamps ts; |
f0a03a02 | 1029 | __le64 *regval = (__le64 *)va; |
0066c8b6 | 1030 | int adjust = 0; |
b534550a | 1031 | |
f0a03a02 | 1032 | if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) |
53792608 | 1033 | return 0; |
f0a03a02 | 1034 | |
b980ac18 | 1035 | /* The timestamp is recorded in little endian format. |
b534550a AD |
1036 | * DWORD: 0 1 2 3 |
1037 | * Field: Reserved Reserved SYSTIML SYSTIMH | |
1038 | */ | |
f0a03a02 JB |
1039 | |
1040 | /* check reserved dwords are zero, be/le doesn't matter for zero */ | |
1041 | if (regval[0]) | |
53792608 | 1042 | return 0; |
f0a03a02 | 1043 | |
53792608 | 1044 | igb_ptp_systim_to_hwtstamp(adapter, &ts, le64_to_cpu(regval[1])); |
0066c8b6 KG |
1045 | |
1046 | /* adjust timestamp for the RX latency based on link speed */ | |
1047 | if (adapter->hw.mac.type == e1000_i210) { | |
1048 | switch (adapter->link_speed) { | |
1049 | case SPEED_10: | |
1050 | adjust = IGB_I210_RX_LATENCY_10; | |
1051 | break; | |
1052 | case SPEED_100: | |
1053 | adjust = IGB_I210_RX_LATENCY_100; | |
1054 | break; | |
1055 | case SPEED_1000: | |
1056 | adjust = IGB_I210_RX_LATENCY_1000; | |
1057 | break; | |
1058 | } | |
1059 | } | |
f0a03a02 | 1060 | |
53792608 KK |
1061 | *timestamp = ktime_sub_ns(ts.hwtstamp, adjust); |
1062 | ||
1063 | return IGB_TS_HDR_LEN; | |
b534550a AD |
1064 | } |
1065 | ||
1066 | /** | |
1067 | * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register | |
1068 | * @q_vector: Pointer to interrupt specific structure | |
1069 | * @skb: Buffer containing timestamp and packet | |
1070 | * | |
1071 | * This function is meant to retrieve a timestamp from the internal registers | |
1072 | * of the adapter and store it in the skb. | |
b980ac18 | 1073 | **/ |
f0a03a02 | 1074 | void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb) |
a79f4f88 MV |
1075 | { |
1076 | struct igb_adapter *adapter = q_vector->adapter; | |
1077 | struct e1000_hw *hw = &adapter->hw; | |
3f544d2a | 1078 | int adjust = 0; |
f0a03a02 JB |
1079 | u64 regval; |
1080 | ||
1081 | if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) | |
1082 | return; | |
a79f4f88 | 1083 | |
b980ac18 | 1084 | /* If this bit is set, then the RX registers contain the time stamp. No |
a79f4f88 MV |
1085 | * other packet will be time stamped until we read these registers, so |
1086 | * read the registers to make them available again. Because only one | |
1087 | * packet can be time stamped at a time, we know that the register | |
1088 | * values must belong to this one here and therefore we don't need to | |
1089 | * compare any of the additional attributes stored for it. | |
1090 | * | |
1091 | * If nothing went wrong, then it should have a shared tx_flags that we | |
1092 | * can turn into a skb_shared_hwtstamps. | |
1093 | */ | |
b534550a AD |
1094 | if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) |
1095 | return; | |
1096 | ||
1097 | regval = rd32(E1000_RXSTMPL); | |
1098 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
a79f4f88 MV |
1099 | |
1100 | igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); | |
5499a968 | 1101 | |
3f544d2a NS |
1102 | /* adjust timestamp for the RX latency based on link speed */ |
1103 | if (adapter->hw.mac.type == e1000_i210) { | |
1104 | switch (adapter->link_speed) { | |
1105 | case SPEED_10: | |
1106 | adjust = IGB_I210_RX_LATENCY_10; | |
1107 | break; | |
1108 | case SPEED_100: | |
1109 | adjust = IGB_I210_RX_LATENCY_100; | |
1110 | break; | |
1111 | case SPEED_1000: | |
1112 | adjust = IGB_I210_RX_LATENCY_1000; | |
1113 | break; | |
1114 | } | |
1115 | } | |
1116 | skb_hwtstamps(skb)->hwtstamp = | |
0066c8b6 | 1117 | ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); |
3f544d2a | 1118 | |
5499a968 JK |
1119 | /* Update the last_rx_timestamp timer in order to enable watchdog check |
1120 | * for error case of latched timestamp on a dropped packet. | |
1121 | */ | |
1122 | adapter->last_rx_timestamp = jiffies; | |
a79f4f88 MV |
1123 | } |
1124 | ||
1125 | /** | |
6ab5f7b2 | 1126 | * igb_ptp_get_ts_config - get hardware time stamping config |
b50f7bca JB |
1127 | * @netdev: netdev struct |
1128 | * @ifr: interface struct | |
6ab5f7b2 JK |
1129 | * |
1130 | * Get the hwtstamp_config settings to return to the user. Rather than attempt | |
1131 | * to deconstruct the settings from the registers, just return a shadow copy | |
1132 | * of the last known settings. | |
1133 | **/ | |
1134 | int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) | |
1135 | { | |
1136 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1137 | struct hwtstamp_config *config = &adapter->tstamp_config; | |
1138 | ||
1139 | return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? | |
1140 | -EFAULT : 0; | |
1141 | } | |
9f62ecf4 | 1142 | |
6ab5f7b2 | 1143 | /** |
9f62ecf4 JK |
1144 | * igb_ptp_set_timestamp_mode - setup hardware for timestamping |
1145 | * @adapter: networking device structure | |
1146 | * @config: hwtstamp configuration | |
a79f4f88 MV |
1147 | * |
1148 | * Outgoing time stamping can be enabled and disabled. Play nice and | |
1149 | * disable it when requested, although it shouldn't case any overhead | |
1150 | * when no packet needs it. At most one packet in the queue may be | |
1151 | * marked for time stamping, otherwise it would be impossible to tell | |
1152 | * for sure to which packet the hardware time stamp belongs. | |
1153 | * | |
1154 | * Incoming time stamping has to be configured via the hardware | |
1155 | * filters. Not all combinations are supported, in particular event | |
1156 | * type has to be specified. Matching the kind of event packet is | |
1157 | * not supported, with the exception of "all V2 events regardless of | |
1158 | * level 2 or 4". | |
9f62ecf4 JK |
1159 | */ |
1160 | static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, | |
1161 | struct hwtstamp_config *config) | |
a79f4f88 | 1162 | { |
a79f4f88 | 1163 | struct e1000_hw *hw = &adapter->hw; |
a79f4f88 MV |
1164 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; |
1165 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
1166 | u32 tsync_rx_cfg = 0; | |
1167 | bool is_l4 = false; | |
1168 | bool is_l2 = false; | |
1169 | u32 regval; | |
1170 | ||
6ab5f7b2 | 1171 | switch (config->tx_type) { |
a79f4f88 MV |
1172 | case HWTSTAMP_TX_OFF: |
1173 | tsync_tx_ctl = 0; | |
52c40698 | 1174 | break; |
a79f4f88 MV |
1175 | case HWTSTAMP_TX_ON: |
1176 | break; | |
1177 | default: | |
1178 | return -ERANGE; | |
1179 | } | |
1180 | ||
6ab5f7b2 | 1181 | switch (config->rx_filter) { |
a79f4f88 MV |
1182 | case HWTSTAMP_FILTER_NONE: |
1183 | tsync_rx_ctl = 0; | |
1184 | break; | |
a79f4f88 MV |
1185 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
1186 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
1187 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; | |
1188 | is_l4 = true; | |
1189 | break; | |
1190 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
1191 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
1192 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; | |
1193 | is_l4 = true; | |
1194 | break; | |
3e961a06 MV |
1195 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
1196 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1197 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
1198 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
a79f4f88 MV |
1199 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
1200 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3e961a06 | 1201 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
a79f4f88 MV |
1202 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
1203 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
a79f4f88 | 1204 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; |
6ab5f7b2 | 1205 | config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
a79f4f88 MV |
1206 | is_l2 = true; |
1207 | is_l4 = true; | |
1208 | break; | |
3e961a06 | 1209 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
e3412575 | 1210 | case HWTSTAMP_FILTER_NTP_ALL: |
3e961a06 MV |
1211 | case HWTSTAMP_FILTER_ALL: |
1212 | /* 82576 cannot timestamp all packets, which it needs to do to | |
1213 | * support both V1 Sync and Delay_Req messages | |
1214 | */ | |
1215 | if (hw->mac.type != e1000_82576) { | |
1216 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
6ab5f7b2 | 1217 | config->rx_filter = HWTSTAMP_FILTER_ALL; |
3e961a06 MV |
1218 | break; |
1219 | } | |
5463fce6 | 1220 | fallthrough; |
a79f4f88 | 1221 | default: |
6ab5f7b2 | 1222 | config->rx_filter = HWTSTAMP_FILTER_NONE; |
a79f4f88 MV |
1223 | return -ERANGE; |
1224 | } | |
1225 | ||
1226 | if (hw->mac.type == e1000_82575) { | |
1227 | if (tsync_rx_ctl | tsync_tx_ctl) | |
1228 | return -EINVAL; | |
1229 | return 0; | |
1230 | } | |
1231 | ||
b980ac18 | 1232 | /* Per-packet timestamping only works if all packets are |
a79f4f88 | 1233 | * timestamped, so enable timestamping in all packets as |
b980ac18 | 1234 | * long as one Rx filter was configured. |
a79f4f88 MV |
1235 | */ |
1236 | if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { | |
1237 | tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
1238 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
6ab5f7b2 | 1239 | config->rx_filter = HWTSTAMP_FILTER_ALL; |
3e961a06 MV |
1240 | is_l2 = true; |
1241 | is_l4 = true; | |
e57b8bdb MV |
1242 | |
1243 | if ((hw->mac.type == e1000_i210) || | |
1244 | (hw->mac.type == e1000_i211)) { | |
1245 | regval = rd32(E1000_RXPBS); | |
1246 | regval |= E1000_RXPBS_CFG_TS_EN; | |
1247 | wr32(E1000_RXPBS, regval); | |
1248 | } | |
a79f4f88 MV |
1249 | } |
1250 | ||
1251 | /* enable/disable TX */ | |
1252 | regval = rd32(E1000_TSYNCTXCTL); | |
1253 | regval &= ~E1000_TSYNCTXCTL_ENABLED; | |
1254 | regval |= tsync_tx_ctl; | |
1255 | wr32(E1000_TSYNCTXCTL, regval); | |
1256 | ||
1257 | /* enable/disable RX */ | |
1258 | regval = rd32(E1000_TSYNCRXCTL); | |
1259 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); | |
1260 | regval |= tsync_rx_ctl; | |
1261 | wr32(E1000_TSYNCRXCTL, regval); | |
1262 | ||
1263 | /* define which PTP packets are time stamped */ | |
1264 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
1265 | ||
1266 | /* define ethertype filter for timestamped packets */ | |
1267 | if (is_l2) | |
64c75d41 | 1268 | wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), |
a79f4f88 MV |
1269 | (E1000_ETQF_FILTER_ENABLE | /* enable filter */ |
1270 | E1000_ETQF_1588 | /* enable timestamping */ | |
1271 | ETH_P_1588)); /* 1588 eth protocol type */ | |
1272 | else | |
64c75d41 | 1273 | wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0); |
a79f4f88 | 1274 | |
a79f4f88 MV |
1275 | /* L4 Queue Filter[3]: filter by destination port and protocol */ |
1276 | if (is_l4) { | |
1277 | u32 ftqf = (IPPROTO_UDP /* UDP */ | |
1278 | | E1000_FTQF_VF_BP /* VF not compared */ | |
1279 | | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ | |
1280 | | E1000_FTQF_MASK); /* mask all inputs */ | |
1281 | ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ | |
1282 | ||
9fb8602e | 1283 | wr32(E1000_IMIR(3), (__force unsigned int)htons(PTP_EV_PORT)); |
a79f4f88 MV |
1284 | wr32(E1000_IMIREXT(3), |
1285 | (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); | |
1286 | if (hw->mac.type == e1000_82576) { | |
1287 | /* enable source port check */ | |
9fb8602e | 1288 | wr32(E1000_SPQF(3), (__force unsigned int)htons(PTP_EV_PORT)); |
a79f4f88 MV |
1289 | ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; |
1290 | } | |
1291 | wr32(E1000_FTQF(3), ftqf); | |
1292 | } else { | |
1293 | wr32(E1000_FTQF(3), E1000_FTQF_MASK); | |
1294 | } | |
1295 | wrfl(); | |
1296 | ||
1297 | /* clear TX/RX time stamp registers, just to be sure */ | |
e57b8bdb | 1298 | regval = rd32(E1000_TXSTMPL); |
a79f4f88 | 1299 | regval = rd32(E1000_TXSTMPH); |
e57b8bdb | 1300 | regval = rd32(E1000_RXSTMPL); |
a79f4f88 MV |
1301 | regval = rd32(E1000_RXSTMPH); |
1302 | ||
9f62ecf4 JK |
1303 | return 0; |
1304 | } | |
1305 | ||
1306 | /** | |
1307 | * igb_ptp_set_ts_config - set hardware time stamping config | |
b50f7bca JB |
1308 | * @netdev: netdev struct |
1309 | * @ifr: interface struct | |
9f62ecf4 JK |
1310 | * |
1311 | **/ | |
1312 | int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) | |
1313 | { | |
1314 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1315 | struct hwtstamp_config config; | |
1316 | int err; | |
1317 | ||
1318 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
1319 | return -EFAULT; | |
1320 | ||
1321 | err = igb_ptp_set_timestamp_mode(adapter, &config); | |
1322 | if (err) | |
1323 | return err; | |
1324 | ||
1325 | /* save these settings for future reference */ | |
1326 | memcpy(&adapter->tstamp_config, &config, | |
1327 | sizeof(adapter->tstamp_config)); | |
1328 | ||
1329 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
a79f4f88 | 1330 | -EFAULT : 0; |
d339b133 RC |
1331 | } |
1332 | ||
4f3ce71b JK |
1333 | /** |
1334 | * igb_ptp_init - Initialize PTP functionality | |
1335 | * @adapter: Board private structure | |
1336 | * | |
1337 | * This function is called at device probe to initialize the PTP | |
1338 | * functionality. | |
1339 | */ | |
d339b133 RC |
1340 | void igb_ptp_init(struct igb_adapter *adapter) |
1341 | { | |
1342 | struct e1000_hw *hw = &adapter->hw; | |
201987e3 | 1343 | struct net_device *netdev = adapter->netdev; |
d339b133 RC |
1344 | |
1345 | switch (hw->mac.type) { | |
e57b8bdb MV |
1346 | case e1000_82576: |
1347 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); | |
1348 | adapter->ptp_caps.owner = THIS_MODULE; | |
75517d92 | 1349 | adapter->ptp_caps.max_adj = 999999881; |
e57b8bdb MV |
1350 | adapter->ptp_caps.n_ext_ts = 0; |
1351 | adapter->ptp_caps.pps = 0; | |
1352 | adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; | |
1353 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; | |
cff8ba28 | 1354 | adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82576; |
d4c496fe | 1355 | adapter->ptp_caps.settime64 = igb_ptp_settime_82576; |
102be52f | 1356 | adapter->ptp_caps.enable = igb_ptp_feature_enable; |
e57b8bdb | 1357 | adapter->cc.read = igb_ptp_read_82576; |
b57c8940 | 1358 | adapter->cc.mask = CYCLECOUNTER_MASK(64); |
e57b8bdb MV |
1359 | adapter->cc.mult = 1; |
1360 | adapter->cc.shift = IGB_82576_TSYNC_SHIFT; | |
63737166 | 1361 | adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; |
e57b8bdb | 1362 | break; |
d339b133 | 1363 | case e1000_82580: |
ceb5f13b | 1364 | case e1000_i354: |
e57b8bdb | 1365 | case e1000_i350: |
1819fc75 | 1366 | igb_ptp_sdp_init(adapter); |
201987e3 | 1367 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
a79f4f88 | 1368 | adapter->ptp_caps.owner = THIS_MODULE; |
a79f4f88 | 1369 | adapter->ptp_caps.max_adj = 62499999; |
1819fc75 RB |
1370 | adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; |
1371 | adapter->ptp_caps.n_per_out = IGB_N_PEROUT; | |
1372 | adapter->ptp_caps.n_pins = IGB_N_SDP; | |
a79f4f88 | 1373 | adapter->ptp_caps.pps = 0; |
1819fc75 | 1374 | adapter->ptp_caps.pin_config = adapter->sdp_config; |
c79e975e | 1375 | adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; |
e57b8bdb | 1376 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; |
cff8ba28 | 1377 | adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82580; |
d4c496fe | 1378 | adapter->ptp_caps.settime64 = igb_ptp_settime_82576; |
1819fc75 RB |
1379 | adapter->ptp_caps.enable = igb_ptp_feature_enable_82580; |
1380 | adapter->ptp_caps.verify = igb_ptp_verify_pin; | |
a79f4f88 | 1381 | adapter->cc.read = igb_ptp_read_82580; |
b57c8940 | 1382 | adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); |
a79f4f88 MV |
1383 | adapter->cc.mult = 1; |
1384 | adapter->cc.shift = 0; | |
63737166 | 1385 | adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; |
d339b133 | 1386 | break; |
e57b8bdb MV |
1387 | case e1000_i210: |
1388 | case e1000_i211: | |
8ab55aba | 1389 | igb_ptp_sdp_init(adapter); |
201987e3 | 1390 | snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
a79f4f88 | 1391 | adapter->ptp_caps.owner = THIS_MODULE; |
e57b8bdb | 1392 | adapter->ptp_caps.max_adj = 62499999; |
720db4ff RC |
1393 | adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; |
1394 | adapter->ptp_caps.n_per_out = IGB_N_PEROUT; | |
1395 | adapter->ptp_caps.n_pins = IGB_N_SDP; | |
00c65578 | 1396 | adapter->ptp_caps.pps = 1; |
720db4ff | 1397 | adapter->ptp_caps.pin_config = adapter->sdp_config; |
c79e975e | 1398 | adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; |
e57b8bdb | 1399 | adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; |
cff8ba28 | 1400 | adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_i210; |
d4c496fe | 1401 | adapter->ptp_caps.settime64 = igb_ptp_settime_i210; |
00c65578 | 1402 | adapter->ptp_caps.enable = igb_ptp_feature_enable_i210; |
720db4ff | 1403 | adapter->ptp_caps.verify = igb_ptp_verify_pin; |
d339b133 | 1404 | break; |
d339b133 RC |
1405 | default: |
1406 | adapter->ptp_clock = NULL; | |
1407 | return; | |
1408 | } | |
1409 | ||
e57b8bdb MV |
1410 | spin_lock_init(&adapter->tmreg_lock); |
1411 | INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); | |
d339b133 | 1412 | |
4f3ce71b | 1413 | if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) |
e57b8bdb MV |
1414 | INIT_DELAYED_WORK(&adapter->ptp_overflow_work, |
1415 | igb_ptp_overflow_check); | |
1f6e8178 | 1416 | |
9f62ecf4 JK |
1417 | adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; |
1418 | adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; | |
1419 | ||
4f3ce71b JK |
1420 | igb_ptp_reset(adapter); |
1421 | ||
1ef76158 RC |
1422 | adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, |
1423 | &adapter->pdev->dev); | |
d339b133 RC |
1424 | if (IS_ERR(adapter->ptp_clock)) { |
1425 | adapter->ptp_clock = NULL; | |
1426 | dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); | |
efee95f4 | 1427 | } else if (adapter->ptp_clock) { |
d339b133 RC |
1428 | dev_info(&adapter->pdev->dev, "added PHC on %s\n", |
1429 | adapter->netdev->name); | |
462f1188 | 1430 | adapter->ptp_flags |= IGB_PTP_ENABLED; |
1f6e8178 | 1431 | } |
d339b133 RC |
1432 | } |
1433 | ||
8ab55aba RB |
1434 | /** |
1435 | * igb_ptp_sdp_init - utility function which inits the SDP config structs | |
1436 | * @adapter: Board private structure. | |
1437 | **/ | |
1438 | void igb_ptp_sdp_init(struct igb_adapter *adapter) | |
1439 | { | |
1440 | int i; | |
1441 | ||
1442 | for (i = 0; i < IGB_N_SDP; i++) { | |
1443 | struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; | |
1444 | ||
1445 | snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); | |
1446 | ppd->index = i; | |
1447 | ppd->func = PTP_PF_NONE; | |
1448 | } | |
1449 | } | |
1450 | ||
a79f4f88 | 1451 | /** |
e3f2350d JK |
1452 | * igb_ptp_suspend - Disable PTP work items and prepare for suspend |
1453 | * @adapter: Board private structure | |
a79f4f88 | 1454 | * |
e3f2350d JK |
1455 | * This function stops the overflow check work and PTP Tx timestamp work, and |
1456 | * will prepare the device for OS suspend. | |
1457 | */ | |
1458 | void igb_ptp_suspend(struct igb_adapter *adapter) | |
d339b133 | 1459 | { |
63737166 | 1460 | if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) |
d3eef8c8 | 1461 | return; |
63737166 JK |
1462 | |
1463 | if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) | |
1464 | cancel_delayed_work_sync(&adapter->ptp_overflow_work); | |
d339b133 | 1465 | |
1f6e8178 | 1466 | cancel_work_sync(&adapter->ptp_tx_work); |
badc26dd MV |
1467 | if (adapter->ptp_tx_skb) { |
1468 | dev_kfree_skb_any(adapter->ptp_tx_skb); | |
1469 | adapter->ptp_tx_skb = NULL; | |
ed4420a3 | 1470 | clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
badc26dd | 1471 | } |
e3f2350d JK |
1472 | } |
1473 | ||
1474 | /** | |
1475 | * igb_ptp_stop - Disable PTP device and stop the overflow check. | |
1476 | * @adapter: Board private structure. | |
1477 | * | |
1478 | * This function stops the PTP support and cancels the delayed work. | |
1479 | **/ | |
1480 | void igb_ptp_stop(struct igb_adapter *adapter) | |
1481 | { | |
1482 | igb_ptp_suspend(adapter); | |
1f6e8178 | 1483 | |
d339b133 RC |
1484 | if (adapter->ptp_clock) { |
1485 | ptp_clock_unregister(adapter->ptp_clock); | |
1486 | dev_info(&adapter->pdev->dev, "removed PHC on %s\n", | |
1487 | adapter->netdev->name); | |
462f1188 | 1488 | adapter->ptp_flags &= ~IGB_PTP_ENABLED; |
d339b133 RC |
1489 | } |
1490 | } | |
1f6e8178 MV |
1491 | |
1492 | /** | |
1493 | * igb_ptp_reset - Re-enable the adapter for PTP following a reset. | |
1494 | * @adapter: Board private structure. | |
1495 | * | |
1496 | * This function handles the reset work required to re-enable the PTP device. | |
1497 | **/ | |
1498 | void igb_ptp_reset(struct igb_adapter *adapter) | |
1499 | { | |
1500 | struct e1000_hw *hw = &adapter->hw; | |
8298c1ec | 1501 | unsigned long flags; |
1f6e8178 | 1502 | |
6ab5f7b2 | 1503 | /* reset the tstamp_config */ |
9f62ecf4 | 1504 | igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); |
6ab5f7b2 | 1505 | |
8298c1ec RC |
1506 | spin_lock_irqsave(&adapter->tmreg_lock, flags); |
1507 | ||
1f6e8178 MV |
1508 | switch (adapter->hw.mac.type) { |
1509 | case e1000_82576: | |
1510 | /* Dial the nominal frequency. */ | |
1511 | wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); | |
1512 | break; | |
1513 | case e1000_82580: | |
ceb5f13b | 1514 | case e1000_i354: |
1f6e8178 MV |
1515 | case e1000_i350: |
1516 | case e1000_i210: | |
1517 | case e1000_i211: | |
1f6e8178 | 1518 | wr32(E1000_TSAUXC, 0x0); |
720db4ff | 1519 | wr32(E1000_TSSDP, 0x0); |
ac28b41a JK |
1520 | wr32(E1000_TSIM, |
1521 | TSYNC_INTERRUPTS | | |
1522 | (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0)); | |
1f6e8178 MV |
1523 | wr32(E1000_IMS, E1000_IMS_TS); |
1524 | break; | |
1525 | default: | |
1526 | /* No work to do. */ | |
8298c1ec | 1527 | goto out; |
1f6e8178 MV |
1528 | } |
1529 | ||
e57b8bdb MV |
1530 | /* Re-initialize the timer. */ |
1531 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { | |
d4c496fe | 1532 | struct timespec64 ts = ktime_to_timespec64(ktime_get_real()); |
e57b8bdb | 1533 | |
8298c1ec | 1534 | igb_ptp_write_i210(adapter, &ts); |
e57b8bdb MV |
1535 | } else { |
1536 | timecounter_init(&adapter->tc, &adapter->cc, | |
1537 | ktime_to_ns(ktime_get_real())); | |
1538 | } | |
8298c1ec RC |
1539 | out: |
1540 | spin_unlock_irqrestore(&adapter->tmreg_lock, flags); | |
4f3ce71b JK |
1541 | |
1542 | wrfl(); | |
1543 | ||
1544 | if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) | |
1545 | schedule_delayed_work(&adapter->ptp_overflow_work, | |
1546 | IGB_SYSTIM_OVERFLOW_PERIOD); | |
1f6e8178 | 1547 | } |