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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6-block.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for igb */
29
30#include <linux/vmalloc.h>
31#include <linux/netdevice.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/if_ether.h>
36#include <linux/ethtool.h>
d43c36dc 37#include <linux/sched.h>
5a0e3ad6 38#include <linux/slab.h>
749ab2cd 39#include <linux/pm_runtime.h>
1a1c225b 40#include <linux/highmem.h>
9d5c8243
AK		 41
42#include "igb.h"
43
44struct igb_stats {
45 char stat_string[ETH_GSTRING_LEN];
46 int sizeof_stat;
47 int stat_offset;
48};
49
128e45eb
AD		 50#define IGB_STAT(_name, _stat) { \
51 .stat_string = _name, \
52 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
53 .stat_offset = offsetof(struct igb_adapter, _stat) \
54}
9d5c8243 55static const struct igb_stats igb_gstrings_stats[] = {
128e45eb
AD		 56 IGB_STAT("rx_packets", stats.gprc),
57 IGB_STAT("tx_packets", stats.gptc),
58 IGB_STAT("rx_bytes", stats.gorc),
59 IGB_STAT("tx_bytes", stats.gotc),
60 IGB_STAT("rx_broadcast", stats.bprc),
61 IGB_STAT("tx_broadcast", stats.bptc),
62 IGB_STAT("rx_multicast", stats.mprc),
63 IGB_STAT("tx_multicast", stats.mptc),
64 IGB_STAT("multicast", stats.mprc),
65 IGB_STAT("collisions", stats.colc),
66 IGB_STAT("rx_crc_errors", stats.crcerrs),
67 IGB_STAT("rx_no_buffer_count", stats.rnbc),
68 IGB_STAT("rx_missed_errors", stats.mpc),
69 IGB_STAT("tx_aborted_errors", stats.ecol),
70 IGB_STAT("tx_carrier_errors", stats.tncrs),
71 IGB_STAT("tx_window_errors", stats.latecol),
72 IGB_STAT("tx_abort_late_coll", stats.latecol),
73 IGB_STAT("tx_deferred_ok", stats.dc),
74 IGB_STAT("tx_single_coll_ok", stats.scc),
75 IGB_STAT("tx_multi_coll_ok", stats.mcc),
76 IGB_STAT("tx_timeout_count", tx_timeout_count),
77 IGB_STAT("rx_long_length_errors", stats.roc),
78 IGB_STAT("rx_short_length_errors", stats.ruc),
79 IGB_STAT("rx_align_errors", stats.algnerrc),
80 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
81 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
82 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
83 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
84 IGB_STAT("tx_flow_control_xon", stats.xontxc),
85 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
86 IGB_STAT("rx_long_byte_count", stats.gorc),
87 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
88 IGB_STAT("tx_smbus", stats.mgptc),
89 IGB_STAT("rx_smbus", stats.mgprc),
90 IGB_STAT("dropped_smbus", stats.mgpdc),
0a915b95
CW		 91 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
92 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
93 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
94 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
428f1f71 95 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
fc580751 96 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
128e45eb
AD		 97};
98
99#define IGB_NETDEV_STAT(_net_stat) { \
100 .stat_string = __stringify(_net_stat), \
12dcd86b
ED		 101 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
102 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
128e45eb
AD		 103}
104static const struct igb_stats igb_gstrings_net_stats[] = {
105 IGB_NETDEV_STAT(rx_errors),
106 IGB_NETDEV_STAT(tx_errors),
107 IGB_NETDEV_STAT(tx_dropped),
108 IGB_NETDEV_STAT(rx_length_errors),
109 IGB_NETDEV_STAT(rx_over_errors),
110 IGB_NETDEV_STAT(rx_frame_errors),
111 IGB_NETDEV_STAT(rx_fifo_errors),
112 IGB_NETDEV_STAT(tx_fifo_errors),
113 IGB_NETDEV_STAT(tx_heartbeat_errors)
9d5c8243
AK		 114};
115
128e45eb
AD		 116#define IGB_GLOBAL_STATS_LEN \
117 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
118#define IGB_NETDEV_STATS_LEN \
119 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
120#define IGB_RX_QUEUE_STATS_LEN \
121 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
12dcd86b
ED		 122
123#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
124
9d5c8243 125#define IGB_QUEUE_STATS_LEN \
317f66bd 126 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
128e45eb 127 IGB_RX_QUEUE_STATS_LEN) + \
317f66bd 128 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
128e45eb
AD		 129 IGB_TX_QUEUE_STATS_LEN))
130#define IGB_STATS_LEN \
131 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
132
9d5c8243
AK		 133static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
134 "Register test (offline)", "Eeprom test (offline)",
135 "Interrupt test (offline)", "Loopback test (offline)",
136 "Link test (on/offline)"
137};
317f66bd 138#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
9d5c8243
AK		 139
140static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
141{
142 struct igb_adapter *adapter = netdev_priv(netdev);
143 struct e1000_hw *hw = &adapter->hw;
317f66bd 144 u32 status;
9d5c8243
AK		 145
146 if (hw->phy.media_type == e1000_media_type_copper) {
147
148 ecmd->supported = (SUPPORTED_10baseT_Half |
149 SUPPORTED_10baseT_Full |
150 SUPPORTED_100baseT_Half |
151 SUPPORTED_100baseT_Full |
152 SUPPORTED_1000baseT_Full|
153 SUPPORTED_Autoneg |
42f3c43b
AA		 154 SUPPORTED_TP |
155 SUPPORTED_Pause);
156 ecmd->advertising = ADVERTISED_TP;
9d5c8243
AK		 157
158 if (hw->mac.autoneg == 1) {
159 ecmd->advertising |= ADVERTISED_Autoneg;
160 /* the e1000 autoneg seems to match ethtool nicely */
161 ecmd->advertising |= hw->phy.autoneg_advertised;
162 }
163
42f3c43b
AA		 164 if (hw->mac.autoneg != 1)
165 ecmd->advertising &= ~(ADVERTISED_Pause |
166 ADVERTISED_Asym_Pause);
167
168 if (hw->fc.requested_mode == e1000_fc_full)
169 ecmd->advertising |= ADVERTISED_Pause;
170 else if (hw->fc.requested_mode == e1000_fc_rx_pause)
171 ecmd->advertising |= (ADVERTISED_Pause |
172 ADVERTISED_Asym_Pause);
173 else if (hw->fc.requested_mode == e1000_fc_tx_pause)
174 ecmd->advertising |= ADVERTISED_Asym_Pause;
175 else
176 ecmd->advertising &= ~(ADVERTISED_Pause |
177 ADVERTISED_Asym_Pause);
178
9d5c8243
AK		 179 ecmd->port = PORT_TP;
180 ecmd->phy_address = hw->phy.addr;
181 } else {
182 ecmd->supported = (SUPPORTED_1000baseT_Full |
183 SUPPORTED_FIBRE |
184 SUPPORTED_Autoneg);
185
186 ecmd->advertising = (ADVERTISED_1000baseT_Full |
187 ADVERTISED_FIBRE |
f83396ad
CW		 188 ADVERTISED_Autoneg |
189 ADVERTISED_Pause);
9d5c8243
AK		 190
191 ecmd->port = PORT_FIBRE;
192 }
193
194 ecmd->transceiver = XCVR_INTERNAL;
195
317f66bd 196 status = rd32(E1000_STATUS);
9d5c8243 197
317f66bd 198 if (status & E1000_STATUS_LU) {
9d5c8243 199
317f66bd
AD		 200 if ((status & E1000_STATUS_SPEED_1000) ||
201 hw->phy.media_type != e1000_media_type_copper)
70739497 202 ethtool_cmd_speed_set(ecmd, SPEED_1000);
317f66bd 203 else if (status & E1000_STATUS_SPEED_100)
70739497 204 ethtool_cmd_speed_set(ecmd, SPEED_100);
317f66bd 205 else
70739497 206 ethtool_cmd_speed_set(ecmd, SPEED_10);
9d5c8243 207
317f66bd
AD		 208 if ((status & E1000_STATUS_FD) ||
209 hw->phy.media_type != e1000_media_type_copper)
9d5c8243
AK		 210 ecmd->duplex = DUPLEX_FULL;
211 else
212 ecmd->duplex = DUPLEX_HALF;
213 } else {
70739497 214 ethtool_cmd_speed_set(ecmd, -1);
9d5c8243
AK		 215 ecmd->duplex = -1;
216 }
217
dcc3ae9a 218 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
8376dad0
JB		 219
220 /* MDI-X => 2; MDI =>1; Invalid =>0 */
221 if (hw->phy.media_type == e1000_media_type_copper)
222 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
223 ETH_TP_MDI;
224 else
225 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
226
227 if (hw->phy.mdix == AUTO_ALL_MODES)
228 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
229 else
230 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
231
9d5c8243
AK		 232 return 0;
233}
234
235static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
236{
237 struct igb_adapter *adapter = netdev_priv(netdev);
238 struct e1000_hw *hw = &adapter->hw;
239
240 /* When SoL/IDER sessions are active, autoneg/speed/duplex
241 * cannot be changed */
242 if (igb_check_reset_block(hw)) {
d836200a
JJ		 243 dev_err(&adapter->pdev->dev,
244 "Cannot change link characteristics when SoL/IDER is active.\n");
9d5c8243
AK		 245 return -EINVAL;
246 }
247
8376dad0
JB		 248 /*
249 * MDI setting is only allowed when autoneg enabled because
250 * some hardware doesn't allow MDI setting when speed or
251 * duplex is forced.
252 */
253 if (ecmd->eth_tp_mdix_ctrl) {
254 if (hw->phy.media_type != e1000_media_type_copper)
255 return -EOPNOTSUPP;
256
257 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
258 (ecmd->autoneg != AUTONEG_ENABLE)) {
259 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
260 return -EINVAL;
261 }
262 }
263
9d5c8243
AK		 264 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
265 msleep(1);
266
267 if (ecmd->autoneg == AUTONEG_ENABLE) {
268 hw->mac.autoneg = 1;
dcc3ae9a
AD		 269 hw->phy.autoneg_advertised = ecmd->advertising |
270 ADVERTISED_TP |
271 ADVERTISED_Autoneg;
9d5c8243 272 ecmd->advertising = hw->phy.autoneg_advertised;
0cce119a
AD		 273 if (adapter->fc_autoneg)
274 hw->fc.requested_mode = e1000_fc_default;
dcc3ae9a 275 } else {
25db0338 276 u32 speed = ethtool_cmd_speed(ecmd);
8376dad0 277 /* calling this overrides forced MDI setting */
14ad2513 278 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
9d5c8243
AK		 279 clear_bit(__IGB_RESETTING, &adapter->state);
280 return -EINVAL;
281 }
dcc3ae9a 282 }
9d5c8243 283
8376dad0
JB		 284 /* MDI-X => 2; MDI => 1; Auto => 3 */
285 if (ecmd->eth_tp_mdix_ctrl) {
286 /*
287 * fix up the value for auto (3 => 0) as zero is mapped
288 * internally to auto
289 */
290 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
291 hw->phy.mdix = AUTO_ALL_MODES;
292 else
293 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
294 }
295
9d5c8243 296 /* reset the link */
9d5c8243
AK		 297 if (netif_running(adapter->netdev)) {
298 igb_down(adapter);
299 igb_up(adapter);
300 } else
301 igb_reset(adapter);
302
303 clear_bit(__IGB_RESETTING, &adapter->state);
304 return 0;
305}
306
3145535a
NN		 307static u32 igb_get_link(struct net_device *netdev)
308{
309 struct igb_adapter *adapter = netdev_priv(netdev);
310 struct e1000_mac_info *mac = &adapter->hw.mac;
311
312 /*
313 * If the link is not reported up to netdev, interrupts are disabled,
314 * and so the physical link state may have changed since we last
315 * looked. Set get_link_status to make sure that the true link
316 * state is interrogated, rather than pulling a cached and possibly
317 * stale link state from the driver.
318 */
319 if (!netif_carrier_ok(netdev))
320 mac->get_link_status = 1;
321
322 return igb_has_link(adapter);
323}
324
9d5c8243
AK		 325static void igb_get_pauseparam(struct net_device *netdev,
326 struct ethtool_pauseparam *pause)
327{
328 struct igb_adapter *adapter = netdev_priv(netdev);
329 struct e1000_hw *hw = &adapter->hw;
330
331 pause->autoneg =
332 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
333
0cce119a 334 if (hw->fc.current_mode == e1000_fc_rx_pause)
9d5c8243 335 pause->rx_pause = 1;
0cce119a 336 else if (hw->fc.current_mode == e1000_fc_tx_pause)
9d5c8243 337 pause->tx_pause = 1;
0cce119a 338 else if (hw->fc.current_mode == e1000_fc_full) {
9d5c8243
AK		 339 pause->rx_pause = 1;
340 pause->tx_pause = 1;
341 }
342}
343
344static int igb_set_pauseparam(struct net_device *netdev,
345 struct ethtool_pauseparam *pause)
346{
347 struct igb_adapter *adapter = netdev_priv(netdev);
348 struct e1000_hw *hw = &adapter->hw;
349 int retval = 0;
350
351 adapter->fc_autoneg = pause->autoneg;
352
353 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
354 msleep(1);
355
9d5c8243 356 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
0cce119a 357 hw->fc.requested_mode = e1000_fc_default;
9d5c8243
AK		 358 if (netif_running(adapter->netdev)) {
359 igb_down(adapter);
360 igb_up(adapter);
317f66bd 361 } else {
9d5c8243 362 igb_reset(adapter);
317f66bd 363 }
0cce119a
AD		 364 } else {
365 if (pause->rx_pause && pause->tx_pause)
366 hw->fc.requested_mode = e1000_fc_full;
367 else if (pause->rx_pause && !pause->tx_pause)
368 hw->fc.requested_mode = e1000_fc_rx_pause;
369 else if (!pause->rx_pause && pause->tx_pause)
370 hw->fc.requested_mode = e1000_fc_tx_pause;
371 else if (!pause->rx_pause && !pause->tx_pause)
372 hw->fc.requested_mode = e1000_fc_none;
373
374 hw->fc.current_mode = hw->fc.requested_mode;
375
dcc3ae9a
AD		 376 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
377 igb_force_mac_fc(hw) : igb_setup_link(hw));
0cce119a 378 }
9d5c8243
AK		 379
380 clear_bit(__IGB_RESETTING, &adapter->state);
381 return retval;
382}
383
9d5c8243
AK		 384static u32 igb_get_msglevel(struct net_device *netdev)
385{
386 struct igb_adapter *adapter = netdev_priv(netdev);
387 return adapter->msg_enable;
388}
389
390static void igb_set_msglevel(struct net_device *netdev, u32 data)
391{
392 struct igb_adapter *adapter = netdev_priv(netdev);
393 adapter->msg_enable = data;
394}
395
396static int igb_get_regs_len(struct net_device *netdev)
397{
7e3b4ffb 398#define IGB_REGS_LEN 739
9d5c8243
AK		 399 return IGB_REGS_LEN * sizeof(u32);
400}
401
402static void igb_get_regs(struct net_device *netdev,
403 struct ethtool_regs *regs, void *p)
404{
405 struct igb_adapter *adapter = netdev_priv(netdev);
406 struct e1000_hw *hw = &adapter->hw;
407 u32 *regs_buff = p;
408 u8 i;
409
410 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
411
412 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
413
414 /* General Registers */
415 regs_buff[0] = rd32(E1000_CTRL);
416 regs_buff[1] = rd32(E1000_STATUS);
417 regs_buff[2] = rd32(E1000_CTRL_EXT);
418 regs_buff[3] = rd32(E1000_MDIC);
419 regs_buff[4] = rd32(E1000_SCTL);
420 regs_buff[5] = rd32(E1000_CONNSW);
421 regs_buff[6] = rd32(E1000_VET);
422 regs_buff[7] = rd32(E1000_LEDCTL);
423 regs_buff[8] = rd32(E1000_PBA);
424 regs_buff[9] = rd32(E1000_PBS);
425 regs_buff[10] = rd32(E1000_FRTIMER);
426 regs_buff[11] = rd32(E1000_TCPTIMER);
427
428 /* NVM Register */
429 regs_buff[12] = rd32(E1000_EECD);
430
431 /* Interrupt */
fe59de38
AD		 432 /* Reading EICS for EICR because they read the
433 * same but EICS does not clear on read */
434 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 435 regs_buff[14] = rd32(E1000_EICS);
436 regs_buff[15] = rd32(E1000_EIMS);
437 regs_buff[16] = rd32(E1000_EIMC);
438 regs_buff[17] = rd32(E1000_EIAC);
439 regs_buff[18] = rd32(E1000_EIAM);
fe59de38
AD		 440 /* Reading ICS for ICR because they read the
441 * same but ICS does not clear on read */
442 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 443 regs_buff[20] = rd32(E1000_ICS);
444 regs_buff[21] = rd32(E1000_IMS);
445 regs_buff[22] = rd32(E1000_IMC);
446 regs_buff[23] = rd32(E1000_IAC);
447 regs_buff[24] = rd32(E1000_IAM);
448 regs_buff[25] = rd32(E1000_IMIRVP);
449
450 /* Flow Control */
451 regs_buff[26] = rd32(E1000_FCAL);
452 regs_buff[27] = rd32(E1000_FCAH);
453 regs_buff[28] = rd32(E1000_FCTTV);
454 regs_buff[29] = rd32(E1000_FCRTL);
455 regs_buff[30] = rd32(E1000_FCRTH);
456 regs_buff[31] = rd32(E1000_FCRTV);
457
458 /* Receive */
459 regs_buff[32] = rd32(E1000_RCTL);
460 regs_buff[33] = rd32(E1000_RXCSUM);
461 regs_buff[34] = rd32(E1000_RLPML);
462 regs_buff[35] = rd32(E1000_RFCTL);
463 regs_buff[36] = rd32(E1000_MRQC);
e1739522 464 regs_buff[37] = rd32(E1000_VT_CTL);
9d5c8243
AK		 465
466 /* Transmit */
467 regs_buff[38] = rd32(E1000_TCTL);
468 regs_buff[39] = rd32(E1000_TCTL_EXT);
469 regs_buff[40] = rd32(E1000_TIPG);
470 regs_buff[41] = rd32(E1000_DTXCTL);
471
472 /* Wake Up */
473 regs_buff[42] = rd32(E1000_WUC);
474 regs_buff[43] = rd32(E1000_WUFC);
475 regs_buff[44] = rd32(E1000_WUS);
476 regs_buff[45] = rd32(E1000_IPAV);
477 regs_buff[46] = rd32(E1000_WUPL);
478
479 /* MAC */
480 regs_buff[47] = rd32(E1000_PCS_CFG0);
481 regs_buff[48] = rd32(E1000_PCS_LCTL);
482 regs_buff[49] = rd32(E1000_PCS_LSTAT);
483 regs_buff[50] = rd32(E1000_PCS_ANADV);
484 regs_buff[51] = rd32(E1000_PCS_LPAB);
485 regs_buff[52] = rd32(E1000_PCS_NPTX);
486 regs_buff[53] = rd32(E1000_PCS_LPABNP);
487
488 /* Statistics */
489 regs_buff[54] = adapter->stats.crcerrs;
490 regs_buff[55] = adapter->stats.algnerrc;
491 regs_buff[56] = adapter->stats.symerrs;
492 regs_buff[57] = adapter->stats.rxerrc;
493 regs_buff[58] = adapter->stats.mpc;
494 regs_buff[59] = adapter->stats.scc;
495 regs_buff[60] = adapter->stats.ecol;
496 regs_buff[61] = adapter->stats.mcc;
497 regs_buff[62] = adapter->stats.latecol;
498 regs_buff[63] = adapter->stats.colc;
499 regs_buff[64] = adapter->stats.dc;
500 regs_buff[65] = adapter->stats.tncrs;
501 regs_buff[66] = adapter->stats.sec;
502 regs_buff[67] = adapter->stats.htdpmc;
503 regs_buff[68] = adapter->stats.rlec;
504 regs_buff[69] = adapter->stats.xonrxc;
505 regs_buff[70] = adapter->stats.xontxc;
506 regs_buff[71] = adapter->stats.xoffrxc;
507 regs_buff[72] = adapter->stats.xofftxc;
508 regs_buff[73] = adapter->stats.fcruc;
509 regs_buff[74] = adapter->stats.prc64;
510 regs_buff[75] = adapter->stats.prc127;
511 regs_buff[76] = adapter->stats.prc255;
512 regs_buff[77] = adapter->stats.prc511;
513 regs_buff[78] = adapter->stats.prc1023;
514 regs_buff[79] = adapter->stats.prc1522;
515 regs_buff[80] = adapter->stats.gprc;
516 regs_buff[81] = adapter->stats.bprc;
517 regs_buff[82] = adapter->stats.mprc;
518 regs_buff[83] = adapter->stats.gptc;
519 regs_buff[84] = adapter->stats.gorc;
520 regs_buff[86] = adapter->stats.gotc;
521 regs_buff[88] = adapter->stats.rnbc;
522 regs_buff[89] = adapter->stats.ruc;
523 regs_buff[90] = adapter->stats.rfc;
524 regs_buff[91] = adapter->stats.roc;
525 regs_buff[92] = adapter->stats.rjc;
526 regs_buff[93] = adapter->stats.mgprc;
527 regs_buff[94] = adapter->stats.mgpdc;
528 regs_buff[95] = adapter->stats.mgptc;
529 regs_buff[96] = adapter->stats.tor;
530 regs_buff[98] = adapter->stats.tot;
531 regs_buff[100] = adapter->stats.tpr;
532 regs_buff[101] = adapter->stats.tpt;
533 regs_buff[102] = adapter->stats.ptc64;
534 regs_buff[103] = adapter->stats.ptc127;
535 regs_buff[104] = adapter->stats.ptc255;
536 regs_buff[105] = adapter->stats.ptc511;
537 regs_buff[106] = adapter->stats.ptc1023;
538 regs_buff[107] = adapter->stats.ptc1522;
539 regs_buff[108] = adapter->stats.mptc;
540 regs_buff[109] = adapter->stats.bptc;
541 regs_buff[110] = adapter->stats.tsctc;
542 regs_buff[111] = adapter->stats.iac;
543 regs_buff[112] = adapter->stats.rpthc;
544 regs_buff[113] = adapter->stats.hgptc;
545 regs_buff[114] = adapter->stats.hgorc;
546 regs_buff[116] = adapter->stats.hgotc;
547 regs_buff[118] = adapter->stats.lenerrs;
548 regs_buff[119] = adapter->stats.scvpc;
549 regs_buff[120] = adapter->stats.hrmpc;
550
9d5c8243
AK		 551 for (i = 0; i < 4; i++)
552 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
553 for (i = 0; i < 4; i++)
83ab50a5 554 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
9d5c8243
AK		 555 for (i = 0; i < 4; i++)
556 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
557 for (i = 0; i < 4; i++)
558 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
559 for (i = 0; i < 4; i++)
560 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
561 for (i = 0; i < 4; i++)
562 regs_buff[141 + i] = rd32(E1000_RDH(i));
563 for (i = 0; i < 4; i++)
564 regs_buff[145 + i] = rd32(E1000_RDT(i));
565 for (i = 0; i < 4; i++)
566 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
567
568 for (i = 0; i < 10; i++)
569 regs_buff[153 + i] = rd32(E1000_EITR(i));
570 for (i = 0; i < 8; i++)
571 regs_buff[163 + i] = rd32(E1000_IMIR(i));
572 for (i = 0; i < 8; i++)
573 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
574 for (i = 0; i < 16; i++)
575 regs_buff[179 + i] = rd32(E1000_RAL(i));
576 for (i = 0; i < 16; i++)
577 regs_buff[195 + i] = rd32(E1000_RAH(i));
578
579 for (i = 0; i < 4; i++)
580 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
581 for (i = 0; i < 4; i++)
582 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
583 for (i = 0; i < 4; i++)
584 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
585 for (i = 0; i < 4; i++)
586 regs_buff[223 + i] = rd32(E1000_TDH(i));
587 for (i = 0; i < 4; i++)
588 regs_buff[227 + i] = rd32(E1000_TDT(i));
589 for (i = 0; i < 4; i++)
590 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
591 for (i = 0; i < 4; i++)
592 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
593 for (i = 0; i < 4; i++)
594 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
595 for (i = 0; i < 4; i++)
596 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
597
598 for (i = 0; i < 4; i++)
599 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
600 for (i = 0; i < 4; i++)
601 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
602 for (i = 0; i < 32; i++)
603 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
604 for (i = 0; i < 128; i++)
605 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
606 for (i = 0; i < 128; i++)
607 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
608 for (i = 0; i < 4; i++)
609 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
610
611 regs_buff[547] = rd32(E1000_TDFH);
612 regs_buff[548] = rd32(E1000_TDFT);
613 regs_buff[549] = rd32(E1000_TDFHS);
614 regs_buff[550] = rd32(E1000_TDFPC);
f96a8a0b
CW		 615
616 if (hw->mac.type > e1000_82580) {
617 regs_buff[551] = adapter->stats.o2bgptc;
618 regs_buff[552] = adapter->stats.b2ospc;
619 regs_buff[553] = adapter->stats.o2bspc;
620 regs_buff[554] = adapter->stats.b2ogprc;
621 }
7e3b4ffb
KS		 622
623 if (hw->mac.type != e1000_82576)
624 return;
625 for (i = 0; i < 12; i++)
626 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
627 for (i = 0; i < 4; i++)
628 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
629 for (i = 0; i < 12; i++)
630 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
631 for (i = 0; i < 12; i++)
632 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
633 for (i = 0; i < 12; i++)
634 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
635 for (i = 0; i < 12; i++)
636 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
637 for (i = 0; i < 12; i++)
638 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
639 for (i = 0; i < 12; i++)
640 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
641
642 for (i = 0; i < 12; i++)
643 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
644 for (i = 0; i < 12; i++)
645 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
646 for (i = 0; i < 12; i++)
647 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
648 for (i = 0; i < 12; i++)
649 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
650 for (i = 0; i < 12; i++)
651 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
652 for (i = 0; i < 12; i++)
653 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
654 for (i = 0; i < 12; i++)
655 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
656 for (i = 0; i < 12; i++)
657 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
9d5c8243
AK		 658}
659
660static int igb_get_eeprom_len(struct net_device *netdev)
661{
662 struct igb_adapter *adapter = netdev_priv(netdev);
663 return adapter->hw.nvm.word_size * 2;
664}
665
666static int igb_get_eeprom(struct net_device *netdev,
667 struct ethtool_eeprom *eeprom, u8 *bytes)
668{
669 struct igb_adapter *adapter = netdev_priv(netdev);
670 struct e1000_hw *hw = &adapter->hw;
671 u16 *eeprom_buff;
672 int first_word, last_word;
673 int ret_val = 0;
674 u16 i;
675
676 if (eeprom->len == 0)
677 return -EINVAL;
678
679 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
680
681 first_word = eeprom->offset >> 1;
682 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
683
684 eeprom_buff = kmalloc(sizeof(u16) *
685 (last_word - first_word + 1), GFP_KERNEL);
686 if (!eeprom_buff)
687 return -ENOMEM;
688
689 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 690 ret_val = hw->nvm.ops.read(hw, first_word,
9d5c8243
AK		 691 last_word - first_word + 1,
692 eeprom_buff);
693 else {
694 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 695 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
9d5c8243
AK		 696 &eeprom_buff[i]);
697 if (ret_val)
698 break;
699 }
700 }
701
702 /* Device's eeprom is always little-endian, word addressable */
703 for (i = 0; i < last_word - first_word + 1; i++)
704 le16_to_cpus(&eeprom_buff[i]);
705
706 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
707 eeprom->len);
708 kfree(eeprom_buff);
709
710 return ret_val;
711}
712
713static int igb_set_eeprom(struct net_device *netdev,
714 struct ethtool_eeprom *eeprom, u8 *bytes)
715{
716 struct igb_adapter *adapter = netdev_priv(netdev);
717 struct e1000_hw *hw = &adapter->hw;
718 u16 *eeprom_buff;
719 void *ptr;
720 int max_len, first_word, last_word, ret_val = 0;
721 u16 i;
722
723 if (eeprom->len == 0)
724 return -EOPNOTSUPP;
725
f96a8a0b
CW		 726 if (hw->mac.type == e1000_i211)
727 return -EOPNOTSUPP;
728
9d5c8243
AK		 729 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
730 return -EFAULT;
731
732 max_len = hw->nvm.word_size * 2;
733
734 first_word = eeprom->offset >> 1;
735 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
736 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
737 if (!eeprom_buff)
738 return -ENOMEM;
739
740 ptr = (void *)eeprom_buff;
741
742 if (eeprom->offset & 1) {
743 /* need read/modify/write of first changed EEPROM word */
744 /* only the second byte of the word is being modified */
312c75ae 745 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 746 &eeprom_buff[0]);
747 ptr++;
748 }
749 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
750 /* need read/modify/write of last changed EEPROM word */
751 /* only the first byte of the word is being modified */
312c75ae 752 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 753 &eeprom_buff[last_word - first_word]);
754 }
755
756 /* Device's eeprom is always little-endian, word addressable */
757 for (i = 0; i < last_word - first_word + 1; i++)
758 le16_to_cpus(&eeprom_buff[i]);
759
760 memcpy(ptr, bytes, eeprom->len);
761
762 for (i = 0; i < last_word - first_word + 1; i++)
763 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
764
312c75ae 765 ret_val = hw->nvm.ops.write(hw, first_word,
9d5c8243
AK		 766 last_word - first_word + 1, eeprom_buff);
767
768 /* Update the checksum over the first part of the EEPROM if needed
769 * and flush shadow RAM for 82573 controllers */
770 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
4322e561 771 hw->nvm.ops.update(hw);
9d5c8243 772
d67974f0 773 igb_set_fw_version(adapter);
9d5c8243
AK		 774 kfree(eeprom_buff);
775 return ret_val;
776}
777
778static void igb_get_drvinfo(struct net_device *netdev,
779 struct ethtool_drvinfo *drvinfo)
780{
781 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 782
612a94d6
RJ		 783 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
784 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
9d5c8243 785
d67974f0
CW		 786 /*
787 * EEPROM image version # is reported as firmware version # for
788 * 82575 controllers
789 */
790 strlcpy(drvinfo->fw_version, adapter->fw_version,
791 sizeof(drvinfo->fw_version));
612a94d6
RJ		 792 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
793 sizeof(drvinfo->bus_info));
9d5c8243
AK		 794 drvinfo->n_stats = IGB_STATS_LEN;
795 drvinfo->testinfo_len = IGB_TEST_LEN;
796 drvinfo->regdump_len = igb_get_regs_len(netdev);
797 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
798}
799
800static void igb_get_ringparam(struct net_device *netdev,
801 struct ethtool_ringparam *ring)
802{
803 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 804
805 ring->rx_max_pending = IGB_MAX_RXD;
806 ring->tx_max_pending = IGB_MAX_TXD;
68fd9910
AD		 807 ring->rx_pending = adapter->rx_ring_count;
808 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 809}
810
811static int igb_set_ringparam(struct net_device *netdev,
812 struct ethtool_ringparam *ring)
813{
814 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 815 struct igb_ring *temp_ring;
6d9f4fc4 816 int i, err = 0;
0e15439a 817 u16 new_rx_count, new_tx_count;
9d5c8243
AK		 818
819 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
820 return -EINVAL;
821
0e15439a
AD		 822 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
823 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
9d5c8243
AK		 824 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
825
0e15439a
AD		 826 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
827 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
9d5c8243
AK		 828 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
829
68fd9910
AD		 830 if ((new_tx_count == adapter->tx_ring_count) &&
831 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 832 /* nothing to do */
833 return 0;
834 }
835
6d9f4fc4
AD		 836 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
837 msleep(1);
838
839 if (!netif_running(adapter->netdev)) {
840 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 841 adapter->tx_ring[i]->count = new_tx_count;
6d9f4fc4 842 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 843 adapter->rx_ring[i]->count = new_rx_count;
6d9f4fc4
AD		 844 adapter->tx_ring_count = new_tx_count;
845 adapter->rx_ring_count = new_rx_count;
846 goto clear_reset;
847 }
848
68fd9910
AD		 849 if (adapter->num_tx_queues > adapter->num_rx_queues)
850 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
851 else
852 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
68fd9910 853
6d9f4fc4
AD		 854 if (!temp_ring) {
855 err = -ENOMEM;
856 goto clear_reset;
857 }
9d5c8243 858
6d9f4fc4 859 igb_down(adapter);
9d5c8243
AK		 860
861 /*
862 * We can't just free everything and then setup again,
863 * because the ISRs in MSI-X mode get passed pointers
864 * to the tx and rx ring structs.
865 */
68fd9910 866 if (new_tx_count != adapter->tx_ring_count) {
9d5c8243 867 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 868 memcpy(&temp_ring[i], adapter->tx_ring[i],
869 sizeof(struct igb_ring));
870
68fd9910 871 temp_ring[i].count = new_tx_count;
80785298 872 err = igb_setup_tx_resources(&temp_ring[i]);
9d5c8243 873 if (err) {
68fd9910
AD		 874 while (i) {
875 i--;
876 igb_free_tx_resources(&temp_ring[i]);
877 }
9d5c8243
AK		 878 goto err_setup;
879 }
9d5c8243 880 }
68fd9910 881
3025a446
AD		 882 for (i = 0; i < adapter->num_tx_queues; i++) {
883 igb_free_tx_resources(adapter->tx_ring[i]);
68fd9910 884
3025a446
AD		 885 memcpy(adapter->tx_ring[i], &temp_ring[i],
886 sizeof(struct igb_ring));
887 }
68fd9910
AD		 888
889 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 890 }
891
3025a446 892 if (new_rx_count != adapter->rx_ring_count) {
68fd9910 893 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 894 memcpy(&temp_ring[i], adapter->rx_ring[i],
895 sizeof(struct igb_ring));
896
68fd9910 897 temp_ring[i].count = new_rx_count;
80785298 898 err = igb_setup_rx_resources(&temp_ring[i]);
9d5c8243 899 if (err) {
68fd9910
AD		 900 while (i) {
901 i--;
902 igb_free_rx_resources(&temp_ring[i]);
903 }
9d5c8243
AK		 904 goto err_setup;
905 }
906
9d5c8243 907 }
68fd9910 908
3025a446
AD		 909 for (i = 0; i < adapter->num_rx_queues; i++) {
910 igb_free_rx_resources(adapter->rx_ring[i]);
68fd9910 911
3025a446
AD		 912 memcpy(adapter->rx_ring[i], &temp_ring[i],
913 sizeof(struct igb_ring));
914 }
68fd9910
AD		 915
916 adapter->rx_ring_count = new_rx_count;
9d5c8243 917 }
9d5c8243 918err_setup:
6d9f4fc4 919 igb_up(adapter);
68fd9910 920 vfree(temp_ring);
6d9f4fc4
AD		 921clear_reset:
922 clear_bit(__IGB_RESETTING, &adapter->state);
9d5c8243
AK		 923 return err;
924}
925
926/* ethtool register test data */
927struct igb_reg_test {
928 u16 reg;
2d064c06
AD		 929 u16 reg_offset;
930 u16 array_len;
931 u16 test_type;
9d5c8243
AK		 932 u32 mask;
933 u32 write;
934};
935
936/* In the hardware, registers are laid out either singly, in arrays
937 * spaced 0x100 bytes apart, or in contiguous tables. We assume
938 * most tests take place on arrays or single registers (handled
939 * as a single-element array) and special-case the tables.
940 * Table tests are always pattern tests.
941 *
942 * We also make provision for some required setup steps by specifying
943 * registers to be written without any read-back testing.
944 */
945
946#define PATTERN_TEST 1
947#define SET_READ_TEST 2
948#define WRITE_NO_TEST 3
949#define TABLE32_TEST 4
950#define TABLE64_TEST_LO 5
951#define TABLE64_TEST_HI 6
952
f96a8a0b
CW		 953/* i210 reg test */
954static struct igb_reg_test reg_test_i210[] = {
955 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
956 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
957 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
958 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
959 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
960 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
961 /* RDH is read-only for i210, only test RDT. */
962 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
963 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
964 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
965 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
966 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
967 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
968 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
969 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
970 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
971 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
972 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
973 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
974 { E1000_RA, 0, 16, TABLE64_TEST_LO,
975 0xFFFFFFFF, 0xFFFFFFFF },
976 { E1000_RA, 0, 16, TABLE64_TEST_HI,
977 0x900FFFFF, 0xFFFFFFFF },
978 { E1000_MTA, 0, 128, TABLE32_TEST,
979 0xFFFFFFFF, 0xFFFFFFFF },
980 { 0, 0, 0, 0, 0 }
981};
982
d2ba2ed8
AD		 983/* i350 reg test */
984static struct igb_reg_test reg_test_i350[] = {
985 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
986 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
987 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
988 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
989 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
990 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 991 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 992 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
993 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 994 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 995 /* RDH is read-only for i350, only test RDT. */
996 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
997 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
998 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
999 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1000 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1001 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1002 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1003 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1004 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1005 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1006 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1007 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1008 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1009 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1010 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1011 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1012 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1013 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1014 0xFFFFFFFF, 0xFFFFFFFF },
1015 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1016 0xC3FFFFFF, 0xFFFFFFFF },
1017 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1018 0xFFFFFFFF, 0xFFFFFFFF },
1019 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1020 0xC3FFFFFF, 0xFFFFFFFF },
1021 { E1000_MTA, 0, 128, TABLE32_TEST,
1022 0xFFFFFFFF, 0xFFFFFFFF },
1023 { 0, 0, 0, 0 }
1024};
1025
55cac248
AD		 1026/* 82580 reg test */
1027static struct igb_reg_test reg_test_82580[] = {
1028 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1029 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1030 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1031 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1032 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1033 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1034 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1035 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1036 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1037 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1038 /* RDH is read-only for 82580, only test RDT. */
1039 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1040 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1041 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1042 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1043 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1044 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1045 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1046 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1047 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1048 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1049 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1050 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1051 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1052 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1053 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1054 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1055 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1056 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1057 0xFFFFFFFF, 0xFFFFFFFF },
1058 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1059 0x83FFFFFF, 0xFFFFFFFF },
1060 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1061 0xFFFFFFFF, 0xFFFFFFFF },
1062 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1063 0x83FFFFFF, 0xFFFFFFFF },
1064 { E1000_MTA, 0, 128, TABLE32_TEST,
1065 0xFFFFFFFF, 0xFFFFFFFF },
1066 { 0, 0, 0, 0 }
1067};
1068
2d064c06
AD		 1069/* 82576 reg test */
1070static struct igb_reg_test reg_test_82576[] = {
1071 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1072 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1073 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1074 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1075 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1076 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1077 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1078 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1079 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1080 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1081 /* Enable all RX queues before testing. */
1082 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1083 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 1084 /* RDH is read-only for 82576, only test RDT. */
1085 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 1086 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 1087 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 1088 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 1089 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1090 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1091 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1092 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1093 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1094 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1095 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1096 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1097 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06
AD		 1098 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1099 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1100 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1101 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1102 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1103 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1104 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1105 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1106 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1107 { 0, 0, 0, 0 }
1108};
1109
1110/* 82575 register test */
9d5c8243 1111static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 1112 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1113 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1114 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1115 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1116 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1117 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1118 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 1119 /* Enable all four RX queues before testing. */
2d064c06 1120 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 1121 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 1122 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1123 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1124 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1125 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1126 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1127 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1128 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1129 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1130 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1131 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1132 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1133 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1134 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1135 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1136 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1137 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 1138 { 0, 0, 0, 0 }
1139};
1140
1141static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1142 int reg, u32 mask, u32 write)
1143{
2753f4ce 1144 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1145 u32 pat, val;
317f66bd 1146 static const u32 _test[] =
9d5c8243
AK		 1147 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1148 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce 1149 wr32(reg, (_test[pat] & write));
93ed8359 1150 val = rd32(reg) & mask;
9d5c8243 1151 if (val != (_test[pat] & write & mask)) {
d836200a
JJ		 1152 dev_err(&adapter->pdev->dev,
1153 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
9d5c8243
AK		 1154 reg, val, (_test[pat] & write & mask));
1155 *data = reg;
1156 return 1;
1157 }
1158 }
317f66bd 1159
9d5c8243
AK		 1160 return 0;
1161}
1162
1163static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1164 int reg, u32 mask, u32 write)
1165{
2753f4ce 1166 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1167 u32 val;
2753f4ce
AD		 1168 wr32(reg, write & mask);
1169 val = rd32(reg);
9d5c8243 1170 if ((write & mask) != (val & mask)) {
d836200a
JJ		 1171 dev_err(&adapter->pdev->dev,
1172 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg,
9d5c8243
AK		 1173 (val & mask), (write & mask));
1174 *data = reg;
1175 return 1;
1176 }
317f66bd 1177
9d5c8243
AK		 1178 return 0;
1179}
1180
1181#define REG_PATTERN_TEST(reg, mask, write) \
1182 do { \
1183 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1184 return 1; \
1185 } while (0)
1186
1187#define REG_SET_AND_CHECK(reg, mask, write) \
1188 do { \
1189 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1190 return 1; \
1191 } while (0)
1192
1193static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1194{
1195 struct e1000_hw *hw = &adapter->hw;
1196 struct igb_reg_test *test;
1197 u32 value, before, after;
1198 u32 i, toggle;
1199
2d064c06 1200 switch (adapter->hw.mac.type) {
d2ba2ed8
AD		 1201 case e1000_i350:
1202 test = reg_test_i350;
1203 toggle = 0x7FEFF3FF;
1204 break;
f96a8a0b
CW		 1205 case e1000_i210:
1206 case e1000_i211:
1207 test = reg_test_i210;
1208 toggle = 0x7FEFF3FF;
1209 break;
55cac248
AD		 1210 case e1000_82580:
1211 test = reg_test_82580;
1212 toggle = 0x7FEFF3FF;
1213 break;
2d064c06
AD		 1214 case e1000_82576:
1215 test = reg_test_82576;
317f66bd 1216 toggle = 0x7FFFF3FF;
2d064c06
AD		 1217 break;
1218 default:
1219 test = reg_test_82575;
317f66bd 1220 toggle = 0x7FFFF3FF;
2d064c06
AD		 1221 break;
1222 }
9d5c8243
AK		 1223
1224 /* Because the status register is such a special case,
1225 * we handle it separately from the rest of the register
1226 * tests. Some bits are read-only, some toggle, and some
1227 * are writable on newer MACs.
1228 */
1229 before = rd32(E1000_STATUS);
1230 value = (rd32(E1000_STATUS) & toggle);
1231 wr32(E1000_STATUS, toggle);
1232 after = rd32(E1000_STATUS) & toggle;
1233 if (value != after) {
d836200a
JJ		 1234 dev_err(&adapter->pdev->dev,
1235 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1236 after, value);
9d5c8243
AK		 1237 *data = 1;
1238 return 1;
1239 }
1240 /* restore previous status */
1241 wr32(E1000_STATUS, before);
1242
1243 /* Perform the remainder of the register test, looping through
1244 * the test table until we either fail or reach the null entry.
1245 */
1246 while (test->reg) {
1247 for (i = 0; i < test->array_len; i++) {
1248 switch (test->test_type) {
1249 case PATTERN_TEST:
2753f4ce
AD		 1250 REG_PATTERN_TEST(test->reg +
1251 (i * test->reg_offset),
9d5c8243
AK		 1252 test->mask,
1253 test->write);
1254 break;
1255 case SET_READ_TEST:
2753f4ce
AD		 1256 REG_SET_AND_CHECK(test->reg +
1257 (i * test->reg_offset),
9d5c8243
AK		 1258 test->mask,
1259 test->write);
1260 break;
1261 case WRITE_NO_TEST:
1262 writel(test->write,
1263 (adapter->hw.hw_addr + test->reg)
2d064c06 1264 + (i * test->reg_offset));
9d5c8243
AK		 1265 break;
1266 case TABLE32_TEST:
1267 REG_PATTERN_TEST(test->reg + (i * 4),
1268 test->mask,
1269 test->write);
1270 break;
1271 case TABLE64_TEST_LO:
1272 REG_PATTERN_TEST(test->reg + (i * 8),
1273 test->mask,
1274 test->write);
1275 break;
1276 case TABLE64_TEST_HI:
1277 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1278 test->mask,
1279 test->write);
1280 break;
1281 }
1282 }
1283 test++;
1284 }
1285
1286 *data = 0;
1287 return 0;
1288}
1289
1290static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1291{
9d5c8243 1292 *data = 0;
9d5c8243 1293
f96a8a0b
CW		 1294 /* Validate eeprom on all parts but i211 */
1295 if (adapter->hw.mac.type != e1000_i211) {
1296 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1297 *data = 2;
1298 }
9d5c8243
AK		 1299
1300 return *data;
1301}
1302
1303static irqreturn_t igb_test_intr(int irq, void *data)
1304{
317f66bd 1305 struct igb_adapter *adapter = (struct igb_adapter *) data;
9d5c8243
AK		 1306 struct e1000_hw *hw = &adapter->hw;
1307
1308 adapter->test_icr |= rd32(E1000_ICR);
1309
1310 return IRQ_HANDLED;
1311}
1312
1313static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1314{
1315 struct e1000_hw *hw = &adapter->hw;
1316 struct net_device *netdev = adapter->netdev;
2753f4ce 1317 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1318 u32 irq = adapter->pdev->irq;
1319
1320 *data = 0;
1321
1322 /* Hook up test interrupt handler just for this test */
4eefa8f0
AD		 1323 if (adapter->msix_entries) {
1324 if (request_irq(adapter->msix_entries[0].vector,
a0607fd3 1325 igb_test_intr, 0, netdev->name, adapter)) {
4eefa8f0
AD		 1326 *data = 1;
1327 return -1;
1328 }
4eefa8f0 1329 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 1330 shared_int = false;
4eefa8f0 1331 if (request_irq(irq,
a0607fd3 1332 igb_test_intr, 0, netdev->name, adapter)) {
9d5c8243
AK		 1333 *data = 1;
1334 return -1;
1335 }
a0607fd3 1336 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
4eefa8f0 1337 netdev->name, adapter)) {
9d5c8243 1338 shared_int = false;
a0607fd3 1339 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
4eefa8f0 1340 netdev->name, adapter)) {
9d5c8243
AK		 1341 *data = 1;
1342 return -1;
1343 }
1344 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1345 (shared_int ? "shared" : "unshared"));
317f66bd 1346
9d5c8243 1347 /* Disable all the interrupts */
4eefa8f0 1348 wr32(E1000_IMC, ~0);
945a5151 1349 wrfl();
9d5c8243
AK		 1350 msleep(10);
1351
2753f4ce 1352 /* Define all writable bits for ICS */
4eefa8f0 1353 switch (hw->mac.type) {
2753f4ce
AD		 1354 case e1000_82575:
1355 ics_mask = 0x37F47EDD;
1356 break;
1357 case e1000_82576:
1358 ics_mask = 0x77D4FBFD;
1359 break;
55cac248
AD		 1360 case e1000_82580:
1361 ics_mask = 0x77DCFED5;
1362 break;
d2ba2ed8 1363 case e1000_i350:
f96a8a0b
CW		 1364 case e1000_i210:
1365 case e1000_i211:
d2ba2ed8
AD		 1366 ics_mask = 0x77DCFED5;
1367 break;
2753f4ce
AD		 1368 default:
1369 ics_mask = 0x7FFFFFFF;
1370 break;
1371 }
1372
9d5c8243 1373 /* Test each interrupt */
2753f4ce 1374 for (; i < 31; i++) {
9d5c8243
AK		 1375 /* Interrupt to test */
1376 mask = 1 << i;
1377
2753f4ce
AD		 1378 if (!(mask & ics_mask))
1379 continue;
1380
9d5c8243
AK		 1381 if (!shared_int) {
1382 /* Disable the interrupt to be reported in
1383 * the cause register and then force the same
1384 * interrupt and see if one gets posted. If
1385 * an interrupt was posted to the bus, the
1386 * test failed.
1387 */
1388 adapter->test_icr = 0;
2753f4ce
AD		 1389
1390 /* Flush any pending interrupts */
1391 wr32(E1000_ICR, ~0);
1392
1393 wr32(E1000_IMC, mask);
1394 wr32(E1000_ICS, mask);
945a5151 1395 wrfl();
9d5c8243
AK		 1396 msleep(10);
1397
1398 if (adapter->test_icr & mask) {
1399 *data = 3;
1400 break;
1401 }
1402 }
1403
1404 /* Enable the interrupt to be reported in
1405 * the cause register and then force the same
1406 * interrupt and see if one gets posted. If
1407 * an interrupt was not posted to the bus, the
1408 * test failed.
1409 */
1410 adapter->test_icr = 0;
2753f4ce
AD		 1411
1412 /* Flush any pending interrupts */
1413 wr32(E1000_ICR, ~0);
1414
9d5c8243
AK		 1415 wr32(E1000_IMS, mask);
1416 wr32(E1000_ICS, mask);
945a5151 1417 wrfl();
9d5c8243
AK		 1418 msleep(10);
1419
1420 if (!(adapter->test_icr & mask)) {
1421 *data = 4;
1422 break;
1423 }
1424
1425 if (!shared_int) {
1426 /* Disable the other interrupts to be reported in
1427 * the cause register and then force the other
1428 * interrupts and see if any get posted. If
1429 * an interrupt was posted to the bus, the
1430 * test failed.
1431 */
1432 adapter->test_icr = 0;
2753f4ce
AD		 1433
1434 /* Flush any pending interrupts */
1435 wr32(E1000_ICR, ~0);
1436
1437 wr32(E1000_IMC, ~mask);
1438 wr32(E1000_ICS, ~mask);
945a5151 1439 wrfl();
9d5c8243
AK		 1440 msleep(10);
1441
2753f4ce 1442 if (adapter->test_icr & mask) {
9d5c8243
AK		 1443 *data = 5;
1444 break;
1445 }
1446 }
1447 }
1448
1449 /* Disable all the interrupts */
2753f4ce 1450 wr32(E1000_IMC, ~0);
945a5151 1451 wrfl();
9d5c8243
AK		 1452 msleep(10);
1453
1454 /* Unhook test interrupt handler */
4eefa8f0
AD		 1455 if (adapter->msix_entries)
1456 free_irq(adapter->msix_entries[0].vector, adapter);
1457 else
1458 free_irq(irq, adapter);
9d5c8243
AK		 1459
1460 return *data;
1461}
1462
1463static void igb_free_desc_rings(struct igb_adapter *adapter)
1464{
d7ee5b3a
AD		 1465 igb_free_tx_resources(&adapter->test_tx_ring);
1466 igb_free_rx_resources(&adapter->test_rx_ring);
9d5c8243
AK		 1467}
1468
1469static int igb_setup_desc_rings(struct igb_adapter *adapter)
1470{
9d5c8243
AK		 1471 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1472 struct igb_ring *rx_ring = &adapter->test_rx_ring;
d7ee5b3a 1473 struct e1000_hw *hw = &adapter->hw;
ad93d17e 1474 int ret_val;
9d5c8243
AK		 1475
1476 /* Setup Tx descriptor ring and Tx buffers */
d7ee5b3a 1477 tx_ring->count = IGB_DEFAULT_TXD;
59d71989 1478 tx_ring->dev = &adapter->pdev->dev;
d7ee5b3a
AD		 1479 tx_ring->netdev = adapter->netdev;
1480 tx_ring->reg_idx = adapter->vfs_allocated_count;
9d5c8243 1481
d7ee5b3a 1482 if (igb_setup_tx_resources(tx_ring)) {
9d5c8243
AK		 1483 ret_val = 1;
1484 goto err_nomem;
1485 }
1486
d7ee5b3a
AD		 1487 igb_setup_tctl(adapter);
1488 igb_configure_tx_ring(adapter, tx_ring);
9d5c8243 1489
9d5c8243 1490 /* Setup Rx descriptor ring and Rx buffers */
d7ee5b3a 1491 rx_ring->count = IGB_DEFAULT_RXD;
59d71989 1492 rx_ring->dev = &adapter->pdev->dev;
d7ee5b3a 1493 rx_ring->netdev = adapter->netdev;
d7ee5b3a
AD		 1494 rx_ring->reg_idx = adapter->vfs_allocated_count;
1495
1496 if (igb_setup_rx_resources(rx_ring)) {
1497 ret_val = 3;
9d5c8243
AK		 1498 goto err_nomem;
1499 }
9d5c8243 1500
d7ee5b3a
AD		 1501 /* set the default queue to queue 0 of PF */
1502 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
9d5c8243 1503
d7ee5b3a
AD		 1504 /* enable receive ring */
1505 igb_setup_rctl(adapter);
1506 igb_configure_rx_ring(adapter, rx_ring);
9d5c8243 1507
cd392f5c 1508 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
9d5c8243
AK		 1509
1510 return 0;
1511
1512err_nomem:
1513 igb_free_desc_rings(adapter);
1514 return ret_val;
1515}
1516
1517static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1518{
1519 struct e1000_hw *hw = &adapter->hw;
1520
1521 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1522 igb_write_phy_reg(hw, 29, 0x001F);
1523 igb_write_phy_reg(hw, 30, 0x8FFC);
1524 igb_write_phy_reg(hw, 29, 0x001A);
1525 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1526}
1527
1528static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1529{
1530 struct e1000_hw *hw = &adapter->hw;
1531 u32 ctrl_reg = 0;
9d5c8243
AK		 1532
1533 hw->mac.autoneg = false;
1534
8aa23f0d
CW		 1535 if (hw->phy.type == e1000_phy_m88) {
1536 if (hw->phy.id != I210_I_PHY_ID) {
1537 /* Auto-MDI/MDIX Off */
1538 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1539 /* reset to update Auto-MDI/MDIX */
1540 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1541 /* autoneg off */
1542 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1543 } else {
1544 /* force 1000, set loopback */
1545 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1546 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1547 }
9d5c8243
AK		 1548 }
1549
119b0e03
SA		 1550 /* add small delay to avoid loopback test failure */
1551 msleep(50);
1552
9d5c8243 1553 /* force 1000, set loopback */
f5f4cf08 1554 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1555
1556 /* Now set up the MAC to the same speed/duplex as the PHY. */
1557 ctrl_reg = rd32(E1000_CTRL);
1558 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1559 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1560 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1561 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
cdfa9f64
AD		 1562 E1000_CTRL_FD | /* Force Duplex to FULL */
1563 E1000_CTRL_SLU); /* Set link up enable bit */
9d5c8243 1564
8aa23f0d 1565 if (hw->phy.type == e1000_phy_m88)
9d5c8243 1566 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
9d5c8243
AK		 1567
1568 wr32(E1000_CTRL, ctrl_reg);
1569
1570 /* Disable the receiver on the PHY so when a cable is plugged in, the
1571 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1572 */
8aa23f0d 1573 if (hw->phy.type == e1000_phy_m88)
9d5c8243
AK		 1574 igb_phy_disable_receiver(adapter);
1575
8aa23f0d 1576 mdelay(500);
9d5c8243
AK		 1577 return 0;
1578}
1579
1580static int igb_set_phy_loopback(struct igb_adapter *adapter)
1581{
1582 return igb_integrated_phy_loopback(adapter);
1583}
1584
1585static int igb_setup_loopback_test(struct igb_adapter *adapter)
1586{
1587 struct e1000_hw *hw = &adapter->hw;
2d064c06 1588 u32 reg;
9d5c8243 1589
317f66bd
AD		 1590 reg = rd32(E1000_CTRL_EXT);
1591
1592 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1593 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
a14bc2bb
RH		 1594 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1595 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1596 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1597 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1598
1599 /* Enable DH89xxCC MPHY for near end loopback */
1600 reg = rd32(E1000_MPHY_ADDR_CTL);
1601 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1602 E1000_MPHY_PCS_CLK_REG_OFFSET;
1603 wr32(E1000_MPHY_ADDR_CTL, reg);
1604
1605 reg = rd32(E1000_MPHY_DATA);
1606 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1607 wr32(E1000_MPHY_DATA, reg);
1608 }
1609
2d064c06
AD		 1610 reg = rd32(E1000_RCTL);
1611 reg |= E1000_RCTL_LBM_TCVR;
1612 wr32(E1000_RCTL, reg);
1613
1614 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1615
1616 reg = rd32(E1000_CTRL);
1617 reg &= ~(E1000_CTRL_RFCE |
1618 E1000_CTRL_TFCE |
1619 E1000_CTRL_LRST);
1620 reg |= E1000_CTRL_SLU |
2753f4ce 1621 E1000_CTRL_FD;
2d064c06
AD		 1622 wr32(E1000_CTRL, reg);
1623
1624 /* Unset switch control to serdes energy detect */
1625 reg = rd32(E1000_CONNSW);
1626 reg &= ~E1000_CONNSW_ENRGSRC;
1627 wr32(E1000_CONNSW, reg);
1628
3860a0bf
CW		 1629 /* Unset sigdetect for SERDES loopback on
1630 * 82580 and i350 devices.
1631 */
1632 switch (hw->mac.type) {
1633 case e1000_82580:
1634 case e1000_i350:
1635 reg = rd32(E1000_PCS_CFG0);
1636 reg |= E1000_PCS_CFG_IGN_SD;
1637 wr32(E1000_PCS_CFG0, reg);
1638 break;
1639 default:
1640 break;
1641 }
1642
2d064c06
AD		 1643 /* Set PCS register for forced speed */
1644 reg = rd32(E1000_PCS_LCTL);
1645 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1646 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1647 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1648 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1649 E1000_PCS_LCTL_FSD | /* Force Speed */
1650 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1651 wr32(E1000_PCS_LCTL, reg);
1652
9d5c8243 1653 return 0;
9d5c8243
AK		 1654 }
1655
317f66bd 1656 return igb_set_phy_loopback(adapter);
9d5c8243
AK		 1657}
1658
1659static void igb_loopback_cleanup(struct igb_adapter *adapter)
1660{
1661 struct e1000_hw *hw = &adapter->hw;
1662 u32 rctl;
1663 u16 phy_reg;
1664
a14bc2bb
RH		 1665 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1666 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1667 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1668 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1669 u32 reg;
1670
1671 /* Disable near end loopback on DH89xxCC */
1672 reg = rd32(E1000_MPHY_ADDR_CTL);
1673 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1674 E1000_MPHY_PCS_CLK_REG_OFFSET;
1675 wr32(E1000_MPHY_ADDR_CTL, reg);
1676
1677 reg = rd32(E1000_MPHY_DATA);
1678 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1679 wr32(E1000_MPHY_DATA, reg);
1680 }
1681
9d5c8243
AK		 1682 rctl = rd32(E1000_RCTL);
1683 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1684 wr32(E1000_RCTL, rctl);
1685
1686 hw->mac.autoneg = true;
f5f4cf08 1687 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1688 if (phy_reg & MII_CR_LOOPBACK) {
1689 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1690 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1691 igb_phy_sw_reset(hw);
1692 }
1693}
1694
1695static void igb_create_lbtest_frame(struct sk_buff *skb,
1696 unsigned int frame_size)
1697{
1698 memset(skb->data, 0xFF, frame_size);
317f66bd
AD		 1699 frame_size /= 2;
1700 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1701 memset(&skb->data[frame_size + 10], 0xBE, 1);
1702 memset(&skb->data[frame_size + 12], 0xAF, 1);
9d5c8243
AK		 1703}
1704
1a1c225b
AD		 1705static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1706 unsigned int frame_size)
9d5c8243 1707{
1a1c225b
AD		 1708 unsigned char *data;
1709 bool match = true;
1710
1711 frame_size >>= 1;
1712
cbc8e55f 1713 data = kmap(rx_buffer->page);
1a1c225b
AD		 1714
1715 if (data[3] != 0xFF ||
1716 data[frame_size + 10] != 0xBE ||
1717 data[frame_size + 12] != 0xAF)
1718 match = false;
1719
1720 kunmap(rx_buffer->page);
1721
1722 return match;
9d5c8243
AK		 1723}
1724
ad93d17e
AD		 1725static int igb_clean_test_rings(struct igb_ring *rx_ring,
1726 struct igb_ring *tx_ring,
1727 unsigned int size)
1728{
1729 union e1000_adv_rx_desc *rx_desc;
06034649
AD		 1730 struct igb_rx_buffer *rx_buffer_info;
1731 struct igb_tx_buffer *tx_buffer_info;
6ad4edfc 1732 u16 rx_ntc, tx_ntc, count = 0;
ad93d17e
AD		 1733
1734 /* initialize next to clean and descriptor values */
1735 rx_ntc = rx_ring->next_to_clean;
1736 tx_ntc = tx_ring->next_to_clean;
60136906 1737 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e 1738
3ceb90fd 1739 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
ad93d17e 1740 /* check rx buffer */
06034649 1741 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
ad93d17e 1742
cbc8e55f
AD		 1743 /* sync Rx buffer for CPU read */
1744 dma_sync_single_for_cpu(rx_ring->dev,
1745 rx_buffer_info->dma,
de78d1f9 1746 IGB_RX_BUFSZ,
cbc8e55f 1747 DMA_FROM_DEVICE);
ad93d17e
AD		 1748
1749 /* verify contents of skb */
1a1c225b 1750 if (igb_check_lbtest_frame(rx_buffer_info, size))
ad93d17e
AD		 1751 count++;
1752
cbc8e55f
AD		 1753 /* sync Rx buffer for device write */
1754 dma_sync_single_for_device(rx_ring->dev,
1755 rx_buffer_info->dma,
de78d1f9 1756 IGB_RX_BUFSZ,
cbc8e55f
AD		 1757 DMA_FROM_DEVICE);
1758
ad93d17e 1759 /* unmap buffer on tx side */
06034649
AD		 1760 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1761 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
ad93d17e
AD		 1762
1763 /* increment rx/tx next to clean counters */
1764 rx_ntc++;
1765 if (rx_ntc == rx_ring->count)
1766 rx_ntc = 0;
1767 tx_ntc++;
1768 if (tx_ntc == tx_ring->count)
1769 tx_ntc = 0;
1770
1771 /* fetch next descriptor */
60136906 1772 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e
AD		 1773 }
1774
cbc8e55f 1775 netdev_tx_reset_queue(txring_txq(tx_ring));
51a76c30 1776
ad93d17e 1777 /* re-map buffers to ring, store next to clean values */
cd392f5c 1778 igb_alloc_rx_buffers(rx_ring, count);
ad93d17e
AD		 1779 rx_ring->next_to_clean = rx_ntc;
1780 tx_ring->next_to_clean = tx_ntc;
1781
1782 return count;
1783}
1784
9d5c8243
AK		 1785static int igb_run_loopback_test(struct igb_adapter *adapter)
1786{
9d5c8243
AK		 1787 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1788 struct igb_ring *rx_ring = &adapter->test_rx_ring;
6ad4edfc
AD		 1789 u16 i, j, lc, good_cnt;
1790 int ret_val = 0;
44390ca6 1791 unsigned int size = IGB_RX_HDR_LEN;
ad93d17e
AD		 1792 netdev_tx_t tx_ret_val;
1793 struct sk_buff *skb;
1794
1795 /* allocate test skb */
1796 skb = alloc_skb(size, GFP_KERNEL);
1797 if (!skb)
1798 return 11;
9d5c8243 1799
ad93d17e
AD		 1800 /* place data into test skb */
1801 igb_create_lbtest_frame(skb, size);
1802 skb_put(skb, size);
9d5c8243 1803
317f66bd
AD		 1804 /*
1805 * Calculate the loop count based on the largest descriptor ring
9d5c8243
AK		 1806 * The idea is to wrap the largest ring a number of times using 64
1807 * send/receive pairs during each loop
1808 */
1809
1810 if (rx_ring->count <= tx_ring->count)
1811 lc = ((tx_ring->count / 64) * 2) + 1;
1812 else
1813 lc = ((rx_ring->count / 64) * 2) + 1;
1814
9d5c8243 1815 for (j = 0; j <= lc; j++) { /* loop count loop */
ad93d17e 1816 /* reset count of good packets */
9d5c8243 1817 good_cnt = 0;
ad93d17e
AD		 1818
1819 /* place 64 packets on the transmit queue*/
1820 for (i = 0; i < 64; i++) {
1821 skb_get(skb);
cd392f5c 1822 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
ad93d17e 1823 if (tx_ret_val == NETDEV_TX_OK)
9d5c8243 1824 good_cnt++;
ad93d17e
AD		 1825 }
1826
9d5c8243 1827 if (good_cnt != 64) {
ad93d17e 1828 ret_val = 12;
9d5c8243
AK		 1829 break;
1830 }
ad93d17e
AD		 1831
1832 /* allow 200 milliseconds for packets to go from tx to rx */
1833 msleep(200);
1834
1835 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1836 if (good_cnt != 64) {
1837 ret_val = 13;
9d5c8243
AK		 1838 break;
1839 }
1840 } /* end loop count loop */
ad93d17e
AD		 1841
1842 /* free the original skb */
1843 kfree_skb(skb);
1844
9d5c8243
AK		 1845 return ret_val;
1846}
1847
1848static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1849{
1850 /* PHY loopback cannot be performed if SoL/IDER
1851 * sessions are active */
1852 if (igb_check_reset_block(&adapter->hw)) {
1853 dev_err(&adapter->pdev->dev,
d836200a 1854 "Cannot do PHY loopback test when SoL/IDER is active.\n");
f96a8a0b
CW		 1855 *data = 0;
1856 goto out;
1857 }
9d5c8243
AK		 1858 *data = igb_setup_desc_rings(adapter);
1859 if (*data)
1860 goto out;
1861 *data = igb_setup_loopback_test(adapter);
1862 if (*data)
1863 goto err_loopback;
1864 *data = igb_run_loopback_test(adapter);
1865 igb_loopback_cleanup(adapter);
1866
1867err_loopback:
1868 igb_free_desc_rings(adapter);
1869out:
1870 return *data;
1871}
1872
1873static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1874{
1875 struct e1000_hw *hw = &adapter->hw;
1876 *data = 0;
1877 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1878 int i = 0;
1879 hw->mac.serdes_has_link = false;
1880
1881 /* On some blade server designs, link establishment
1882 * could take as long as 2-3 minutes */
1883 do {
1884 hw->mac.ops.check_for_link(&adapter->hw);
1885 if (hw->mac.serdes_has_link)
1886 return *data;
1887 msleep(20);
1888 } while (i++ < 3750);
1889
1890 *data = 1;
1891 } else {
1892 hw->mac.ops.check_for_link(&adapter->hw);
1893 if (hw->mac.autoneg)
1894 msleep(4000);
1895
317f66bd 1896 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
9d5c8243
AK		 1897 *data = 1;
1898 }
1899 return *data;
1900}
1901
1902static void igb_diag_test(struct net_device *netdev,
1903 struct ethtool_test *eth_test, u64 *data)
1904{
1905 struct igb_adapter *adapter = netdev_priv(netdev);
1906 u16 autoneg_advertised;
1907 u8 forced_speed_duplex, autoneg;
1908 bool if_running = netif_running(netdev);
1909
1910 set_bit(__IGB_TESTING, &adapter->state);
1911 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1912 /* Offline tests */
1913
1914 /* save speed, duplex, autoneg settings */
1915 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1916 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1917 autoneg = adapter->hw.mac.autoneg;
1918
1919 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1920
88a268c1
NN		 1921 /* power up link for link test */
1922 igb_power_up_link(adapter);
1923
9d5c8243
AK		 1924 /* Link test performed before hardware reset so autoneg doesn't
1925 * interfere with test result */
1926 if (igb_link_test(adapter, &data[4]))
1927 eth_test->flags |= ETH_TEST_FL_FAILED;
1928
1929 if (if_running)
1930 /* indicate we're in test mode */
1931 dev_close(netdev);
1932 else
1933 igb_reset(adapter);
1934
1935 if (igb_reg_test(adapter, &data[0]))
1936 eth_test->flags |= ETH_TEST_FL_FAILED;
1937
1938 igb_reset(adapter);
1939 if (igb_eeprom_test(adapter, &data[1]))
1940 eth_test->flags |= ETH_TEST_FL_FAILED;
1941
1942 igb_reset(adapter);
1943 if (igb_intr_test(adapter, &data[2]))
1944 eth_test->flags |= ETH_TEST_FL_FAILED;
1945
1946 igb_reset(adapter);
88a268c1
NN		 1947 /* power up link for loopback test */
1948 igb_power_up_link(adapter);
9d5c8243
AK		 1949 if (igb_loopback_test(adapter, &data[3]))
1950 eth_test->flags |= ETH_TEST_FL_FAILED;
1951
1952 /* restore speed, duplex, autoneg settings */
1953 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1954 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1955 adapter->hw.mac.autoneg = autoneg;
1956
1957 /* force this routine to wait until autoneg complete/timeout */
1958 adapter->hw.phy.autoneg_wait_to_complete = true;
1959 igb_reset(adapter);
1960 adapter->hw.phy.autoneg_wait_to_complete = false;
1961
1962 clear_bit(__IGB_TESTING, &adapter->state);
1963 if (if_running)
1964 dev_open(netdev);
1965 } else {
1966 dev_info(&adapter->pdev->dev, "online testing starting\n");
88a268c1
NN		 1967
1968 /* PHY is powered down when interface is down */
8d420a1b
AD		 1969 if (if_running && igb_link_test(adapter, &data[4]))
1970 eth_test->flags |= ETH_TEST_FL_FAILED;
1971 else
88a268c1 1972 data[4] = 0;
9d5c8243
AK		 1973
1974 /* Online tests aren't run; pass by default */
1975 data[0] = 0;
1976 data[1] = 0;
1977 data[2] = 0;
1978 data[3] = 0;
1979
1980 clear_bit(__IGB_TESTING, &adapter->state);
1981 }
1982 msleep_interruptible(4 * 1000);
1983}
1984
9d5c8243
AK		 1985static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1986{
1987 struct igb_adapter *adapter = netdev_priv(netdev);
1988
1989 wol->supported = WAKE_UCAST | WAKE_MCAST |
22939f06
NN		 1990 WAKE_BCAST | WAKE_MAGIC |
1991 WAKE_PHY;
9d5c8243
AK		 1992 wol->wolopts = 0;
1993
63d4a8f9 1994 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
9d5c8243
AK		 1995 return;
1996
1997 /* apply any specific unsupported masks here */
1998 switch (adapter->hw.device_id) {
1999 default:
2000 break;
2001 }
2002
2003 if (adapter->wol & E1000_WUFC_EX)
2004 wol->wolopts |= WAKE_UCAST;
2005 if (adapter->wol & E1000_WUFC_MC)
2006 wol->wolopts |= WAKE_MCAST;
2007 if (adapter->wol & E1000_WUFC_BC)
2008 wol->wolopts |= WAKE_BCAST;
2009 if (adapter->wol & E1000_WUFC_MAG)
2010 wol->wolopts |= WAKE_MAGIC;
22939f06
NN		 2011 if (adapter->wol & E1000_WUFC_LNKC)
2012 wol->wolopts |= WAKE_PHY;
9d5c8243
AK		 2013}
2014
2015static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2016{
2017 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 2018
22939f06 2019 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
9d5c8243
AK		 2020 return -EOPNOTSUPP;
2021
63d4a8f9 2022 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
9d5c8243
AK		 2023 return wol->wolopts ? -EOPNOTSUPP : 0;
2024
9d5c8243
AK		 2025 /* these settings will always override what we currently have */
2026 adapter->wol = 0;
2027
2028 if (wol->wolopts & WAKE_UCAST)
2029 adapter->wol |= E1000_WUFC_EX;
2030 if (wol->wolopts & WAKE_MCAST)
2031 adapter->wol |= E1000_WUFC_MC;
2032 if (wol->wolopts & WAKE_BCAST)
2033 adapter->wol |= E1000_WUFC_BC;
2034 if (wol->wolopts & WAKE_MAGIC)
2035 adapter->wol |= E1000_WUFC_MAG;
22939f06
NN		 2036 if (wol->wolopts & WAKE_PHY)
2037 adapter->wol |= E1000_WUFC_LNKC;
e1b86d84
RW		 2038 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2039
9d5c8243
AK		 2040 return 0;
2041}
2042
9d5c8243
AK		 2043/* bit defines for adapter->led_status */
2044#define IGB_LED_ON 0
2045
936db355
JK		 2046static int igb_set_phys_id(struct net_device *netdev,
2047 enum ethtool_phys_id_state state)
9d5c8243
AK		 2048{
2049 struct igb_adapter *adapter = netdev_priv(netdev);
2050 struct e1000_hw *hw = &adapter->hw;
2051
936db355
JK		 2052 switch (state) {
2053 case ETHTOOL_ID_ACTIVE:
2054 igb_blink_led(hw);
2055 return 2;
2056 case ETHTOOL_ID_ON:
2057 igb_blink_led(hw);
2058 break;
2059 case ETHTOOL_ID_OFF:
2060 igb_led_off(hw);
2061 break;
2062 case ETHTOOL_ID_INACTIVE:
2063 igb_led_off(hw);
2064 clear_bit(IGB_LED_ON, &adapter->led_status);
2065 igb_cleanup_led(hw);
2066 break;
2067 }
9d5c8243
AK		 2068
2069 return 0;
2070}
2071
2072static int igb_set_coalesce(struct net_device *netdev,
2073 struct ethtool_coalesce *ec)
2074{
2075 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1 2076 int i;
9d5c8243
AK		 2077
2078 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2079 ((ec->rx_coalesce_usecs > 3) &&
2080 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2081 (ec->rx_coalesce_usecs == 2))
2082 return -EINVAL;
2083
4fc82adf
AD		 2084 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2085 ((ec->tx_coalesce_usecs > 3) &&
2086 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2087 (ec->tx_coalesce_usecs == 2))
2088 return -EINVAL;
2089
2090 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2091 return -EINVAL;
2092
831ec0b4
CW		 2093 /* If ITR is disabled, disable DMAC */
2094 if (ec->rx_coalesce_usecs == 0) {
2095 if (adapter->flags & IGB_FLAG_DMAC)
2096 adapter->flags &= ~IGB_FLAG_DMAC;
2097 }
2098
9d5c8243 2099 /* convert to rate of irq's per second */
4fc82adf
AD		 2100 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2101 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2102 else
2103 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2104
2105 /* convert to rate of irq's per second */
2106 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2107 adapter->tx_itr_setting = adapter->rx_itr_setting;
2108 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2109 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2110 else
2111 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
9d5c8243 2112
047e0030
AD		 2113 for (i = 0; i < adapter->num_q_vectors; i++) {
2114 struct igb_q_vector *q_vector = adapter->q_vector[i];
0ba82994
AD		 2115 q_vector->tx.work_limit = adapter->tx_work_limit;
2116 if (q_vector->rx.ring)
4fc82adf
AD		 2117 q_vector->itr_val = adapter->rx_itr_setting;
2118 else
2119 q_vector->itr_val = adapter->tx_itr_setting;
2120 if (q_vector->itr_val && q_vector->itr_val <= 3)
2121 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 2122 q_vector->set_itr = 1;
2123 }
9d5c8243
AK		 2124
2125 return 0;
2126}
2127
2128static int igb_get_coalesce(struct net_device *netdev,
2129 struct ethtool_coalesce *ec)
2130{
2131 struct igb_adapter *adapter = netdev_priv(netdev);
2132
4fc82adf
AD		 2133 if (adapter->rx_itr_setting <= 3)
2134 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
9d5c8243 2135 else
4fc82adf
AD		 2136 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2137
2138 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2139 if (adapter->tx_itr_setting <= 3)
2140 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2141 else
2142 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2143 }
9d5c8243
AK		 2144
2145 return 0;
2146}
2147
9d5c8243
AK		 2148static int igb_nway_reset(struct net_device *netdev)
2149{
2150 struct igb_adapter *adapter = netdev_priv(netdev);
2151 if (netif_running(netdev))
2152 igb_reinit_locked(adapter);
2153 return 0;
2154}
2155
2156static int igb_get_sset_count(struct net_device *netdev, int sset)
2157{
2158 switch (sset) {
2159 case ETH_SS_STATS:
2160 return IGB_STATS_LEN;
2161 case ETH_SS_TEST:
2162 return IGB_TEST_LEN;
2163 default:
2164 return -ENOTSUPP;
2165 }
2166}
2167
2168static void igb_get_ethtool_stats(struct net_device *netdev,
2169 struct ethtool_stats *stats, u64 *data)
2170{
2171 struct igb_adapter *adapter = netdev_priv(netdev);
12dcd86b
ED		 2172 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2173 unsigned int start;
2174 struct igb_ring *ring;
2175 int i, j;
128e45eb 2176 char *p;
9d5c8243 2177
12dcd86b
ED		 2178 spin_lock(&adapter->stats64_lock);
2179 igb_update_stats(adapter, net_stats);
317f66bd 2180
9d5c8243 2181 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
128e45eb 2182 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
9d5c8243
AK		 2183 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2184 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2185 }
128e45eb
AD		 2186 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2187 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2188 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2189 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2190 }
e21ed353 2191 for (j = 0; j < adapter->num_tx_queues; j++) {
12dcd86b
ED		 2192 u64 restart2;
2193
2194 ring = adapter->tx_ring[j];
2195 do {
2196 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2197 data[i] = ring->tx_stats.packets;
2198 data[i+1] = ring->tx_stats.bytes;
2199 data[i+2] = ring->tx_stats.restart_queue;
2200 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2201 do {
2202 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2203 restart2 = ring->tx_stats.restart_queue2;
2204 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2205 data[i+2] += restart2;
2206
2207 i += IGB_TX_QUEUE_STATS_LEN;
e21ed353 2208 }
9d5c8243 2209 for (j = 0; j < adapter->num_rx_queues; j++) {
12dcd86b
ED		 2210 ring = adapter->rx_ring[j];
2211 do {
2212 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2213 data[i] = ring->rx_stats.packets;
2214 data[i+1] = ring->rx_stats.bytes;
2215 data[i+2] = ring->rx_stats.drops;
2216 data[i+3] = ring->rx_stats.csum_err;
2217 data[i+4] = ring->rx_stats.alloc_failed;
2218 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2219 i += IGB_RX_QUEUE_STATS_LEN;
9d5c8243 2220 }
12dcd86b 2221 spin_unlock(&adapter->stats64_lock);
9d5c8243
AK		 2222}
2223
2224static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2225{
2226 struct igb_adapter *adapter = netdev_priv(netdev);
2227 u8 *p = data;
2228 int i;
2229
2230 switch (stringset) {
2231 case ETH_SS_TEST:
2232 memcpy(data, *igb_gstrings_test,
2233 IGB_TEST_LEN*ETH_GSTRING_LEN);
2234 break;
2235 case ETH_SS_STATS:
2236 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2237 memcpy(p, igb_gstrings_stats[i].stat_string,
2238 ETH_GSTRING_LEN);
2239 p += ETH_GSTRING_LEN;
2240 }
128e45eb
AD		 2241 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2242 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2243 ETH_GSTRING_LEN);
2244 p += ETH_GSTRING_LEN;
2245 }
9d5c8243
AK		 2246 for (i = 0; i < adapter->num_tx_queues; i++) {
2247 sprintf(p, "tx_queue_%u_packets", i);
2248 p += ETH_GSTRING_LEN;
2249 sprintf(p, "tx_queue_%u_bytes", i);
2250 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2251 sprintf(p, "tx_queue_%u_restart", i);
2252 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2253 }
2254 for (i = 0; i < adapter->num_rx_queues; i++) {
2255 sprintf(p, "rx_queue_%u_packets", i);
2256 p += ETH_GSTRING_LEN;
2257 sprintf(p, "rx_queue_%u_bytes", i);
2258 p += ETH_GSTRING_LEN;
8c0ab70a
JDB		 2259 sprintf(p, "rx_queue_%u_drops", i);
2260 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2261 sprintf(p, "rx_queue_%u_csum_err", i);
2262 p += ETH_GSTRING_LEN;
2263 sprintf(p, "rx_queue_%u_alloc_failed", i);
2264 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2265 }
2266/* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2267 break;
2268 }
2269}
2270
a79f4f88 2271static int igb_get_ts_info(struct net_device *dev,
a9188028 2272 struct ethtool_ts_info *info)
cb41145e
CW		 2273{
2274 struct igb_adapter *adapter = netdev_priv(dev);
2275
a9188028 2276 switch (adapter->hw.mac.type) {
b66e2397
MV		 2277 case e1000_82575:
2278 info->so_timestamping =
2279 SOF_TIMESTAMPING_TX_SOFTWARE |
2280 SOF_TIMESTAMPING_RX_SOFTWARE |
2281 SOF_TIMESTAMPING_SOFTWARE;
2282 return 0;
a9188028
MV		 2283 case e1000_82576:
2284 case e1000_82580:
2285 case e1000_i350:
2286 case e1000_i210:
2287 case e1000_i211:
2288 info->so_timestamping =
b66e2397
MV		 2289 SOF_TIMESTAMPING_TX_SOFTWARE |
2290 SOF_TIMESTAMPING_RX_SOFTWARE |
2291 SOF_TIMESTAMPING_SOFTWARE |
a9188028
MV		 2292 SOF_TIMESTAMPING_TX_HARDWARE |
2293 SOF_TIMESTAMPING_RX_HARDWARE |
2294 SOF_TIMESTAMPING_RAW_HARDWARE;
cb41145e 2295
a9188028
MV		 2296 if (adapter->ptp_clock)
2297 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2298 else
2299 info->phc_index = -1;
cb41145e 2300
a9188028
MV		 2301 info->tx_types =
2302 (1 << HWTSTAMP_TX_OFF) |
2303 (1 << HWTSTAMP_TX_ON);
cb41145e 2304
a9188028 2305 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE;
cb41145e 2306
a9188028
MV		 2307 /* 82576 does not support timestamping all packets. */
2308 if (adapter->hw.mac.type >= e1000_82580)
2309 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;
2310 else
2311 info->rx_filters |=
2312 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2313 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2314 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2315 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2316 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2317 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2318 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2319
2320 return 0;
a9188028
MV		 2321 default:
2322 return -EOPNOTSUPP;
2323 }
2324}
cb41145e 2325
039454a8
AA		 2326static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2327 struct ethtool_rxnfc *cmd)
2328{
2329 cmd->data = 0;
2330
2331 /* Report default options for RSS on igb */
2332 switch (cmd->flow_type) {
2333 case TCP_V4_FLOW:
2334 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2335 case UDP_V4_FLOW:
2336 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2337 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2338 case SCTP_V4_FLOW:
2339 case AH_ESP_V4_FLOW:
2340 case AH_V4_FLOW:
2341 case ESP_V4_FLOW:
2342 case IPV4_FLOW:
2343 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2344 break;
2345 case TCP_V6_FLOW:
2346 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2347 case UDP_V6_FLOW:
2348 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2349 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2350 case SCTP_V6_FLOW:
2351 case AH_ESP_V6_FLOW:
2352 case AH_V6_FLOW:
2353 case ESP_V6_FLOW:
2354 case IPV6_FLOW:
2355 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2356 break;
2357 default:
2358 return -EINVAL;
2359 }
2360
2361 return 0;
2362}
2363
2364static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2365 u32 *rule_locs)
2366{
2367 struct igb_adapter *adapter = netdev_priv(dev);
2368 int ret = -EOPNOTSUPP;
2369
2370 switch (cmd->cmd) {
2371 case ETHTOOL_GRXRINGS:
2372 cmd->data = adapter->num_rx_queues;
2373 ret = 0;
2374 break;
2375 case ETHTOOL_GRXFH:
2376 ret = igb_get_rss_hash_opts(adapter, cmd);
2377 break;
2378 default:
2379 break;
2380 }
2381
2382 return ret;
2383}
2384
2385#define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2386 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2387static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2388 struct ethtool_rxnfc *nfc)
2389{
2390 u32 flags = adapter->flags;
2391
2392 /* RSS does not support anything other than hashing
2393 * to queues on src and dst IPs and ports
2394 */
2395 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2396 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2397 return -EINVAL;
2398
2399 switch (nfc->flow_type) {
2400 case TCP_V4_FLOW:
2401 case TCP_V6_FLOW:
2402 if (!(nfc->data & RXH_IP_SRC) ||
2403 !(nfc->data & RXH_IP_DST) ||
2404 !(nfc->data & RXH_L4_B_0_1) ||
2405 !(nfc->data & RXH_L4_B_2_3))
2406 return -EINVAL;
2407 break;
2408 case UDP_V4_FLOW:
2409 if (!(nfc->data & RXH_IP_SRC) ||
2410 !(nfc->data & RXH_IP_DST))
2411 return -EINVAL;
2412 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2413 case 0:
2414 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2415 break;
2416 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2417 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2418 break;
2419 default:
2420 return -EINVAL;
2421 }
2422 break;
2423 case UDP_V6_FLOW:
2424 if (!(nfc->data & RXH_IP_SRC) ||
2425 !(nfc->data & RXH_IP_DST))
2426 return -EINVAL;
2427 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2428 case 0:
2429 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2430 break;
2431 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2432 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2433 break;
2434 default:
2435 return -EINVAL;
2436 }
2437 break;
2438 case AH_ESP_V4_FLOW:
2439 case AH_V4_FLOW:
2440 case ESP_V4_FLOW:
2441 case SCTP_V4_FLOW:
2442 case AH_ESP_V6_FLOW:
2443 case AH_V6_FLOW:
2444 case ESP_V6_FLOW:
2445 case SCTP_V6_FLOW:
2446 if (!(nfc->data & RXH_IP_SRC) ||
2447 !(nfc->data & RXH_IP_DST) ||
2448 (nfc->data & RXH_L4_B_0_1) ||
2449 (nfc->data & RXH_L4_B_2_3))
2450 return -EINVAL;
2451 break;
2452 default:
2453 return -EINVAL;
2454 }
2455
2456 /* if we changed something we need to update flags */
2457 if (flags != adapter->flags) {
2458 struct e1000_hw *hw = &adapter->hw;
2459 u32 mrqc = rd32(E1000_MRQC);
2460
2461 if ((flags & UDP_RSS_FLAGS) &&
2462 !(adapter->flags & UDP_RSS_FLAGS))
2463 dev_err(&adapter->pdev->dev,
2464 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2465
2466 adapter->flags = flags;
2467
2468 /* Perform hash on these packet types */
2469 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2470 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2471 E1000_MRQC_RSS_FIELD_IPV6 |
2472 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2473
2474 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2475 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2476
2477 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2478 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2479
2480 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2481 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2482
2483 wr32(E1000_MRQC, mrqc);
2484 }
2485
2486 return 0;
2487}
2488
2489static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2490{
2491 struct igb_adapter *adapter = netdev_priv(dev);
2492 int ret = -EOPNOTSUPP;
2493
2494 switch (cmd->cmd) {
2495 case ETHTOOL_SRXFH:
2496 ret = igb_set_rss_hash_opt(adapter, cmd);
2497 break;
2498 default:
2499 break;
2500 }
2501
2502 return ret;
2503}
2504
24a372cd
AA		 2505static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2506{
2507 struct igb_adapter *adapter = netdev_priv(netdev);
2508 struct e1000_hw *hw = &adapter->hw;
2509 u32 ipcnfg, eeer;
2510
2511 if ((hw->mac.type < e1000_i350) ||
2512 (hw->phy.media_type != e1000_media_type_copper))
2513 return -EOPNOTSUPP;
2514
2515 edata->supported = (SUPPORTED_1000baseT_Full |
2516 SUPPORTED_100baseT_Full);
2517
2518 ipcnfg = rd32(E1000_IPCNFG);
2519 eeer = rd32(E1000_EEER);
2520
2521 /* EEE status on negotiated link */
2522 if (ipcnfg & E1000_IPCNFG_EEE_1G_AN)
2523 edata->advertised = ADVERTISED_1000baseT_Full;
2524
2525 if (ipcnfg & E1000_IPCNFG_EEE_100M_AN)
2526 edata->advertised |= ADVERTISED_100baseT_Full;
2527
2528 if (eeer & E1000_EEER_EEE_NEG)
2529 edata->eee_active = true;
2530
2531 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
2532
2533 if (eeer & E1000_EEER_TX_LPI_EN)
2534 edata->tx_lpi_enabled = true;
2535
2536 /* Report correct negotiated EEE status for devices that
2537 * wrongly report EEE at half-duplex
2538 */
2539 if (adapter->link_duplex == HALF_DUPLEX) {
2540 edata->eee_enabled = false;
2541 edata->eee_active = false;
2542 edata->tx_lpi_enabled = false;
2543 edata->advertised &= ~edata->advertised;
2544 }
2545
2546 return 0;
2547}
2548
2549static int igb_set_eee(struct net_device *netdev,
2550 struct ethtool_eee *edata)
2551{
2552 struct igb_adapter *adapter = netdev_priv(netdev);
2553 struct e1000_hw *hw = &adapter->hw;
2554 struct ethtool_eee eee_curr;
2555 s32 ret_val;
2556
2557 if ((hw->mac.type < e1000_i350) ||
2558 (hw->phy.media_type != e1000_media_type_copper))
2559 return -EOPNOTSUPP;
2560
2561 ret_val = igb_get_eee(netdev, &eee_curr);
2562 if (ret_val)
2563 return ret_val;
2564
2565 if (eee_curr.eee_enabled) {
2566 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
2567 dev_err(&adapter->pdev->dev,
2568 "Setting EEE tx-lpi is not supported\n");
2569 return -EINVAL;
2570 }
2571
2572 /* Tx LPI timer is not implemented currently */
2573 if (edata->tx_lpi_timer) {
2574 dev_err(&adapter->pdev->dev,
2575 "Setting EEE Tx LPI timer is not supported\n");
2576 return -EINVAL;
2577 }
2578
2579 if (eee_curr.advertised != edata->advertised) {
2580 dev_err(&adapter->pdev->dev,
2581 "Setting EEE Advertisement is not supported\n");
2582 return -EINVAL;
2583 }
2584
2585 } else if (!edata->eee_enabled) {
2586 dev_err(&adapter->pdev->dev,
2587 "Setting EEE options are not supported with EEE disabled\n");
2588 return -EINVAL;
2589 }
2590
2591 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
2592 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
2593 igb_set_eee_i350(hw);
2594
2595 /* reset link */
2596 if (!netif_running(netdev))
2597 igb_reset(adapter);
2598 }
2599
2600 return 0;
2601}
2602
a79f4f88
MV		 2603static int igb_ethtool_begin(struct net_device *netdev)
2604{
2605 struct igb_adapter *adapter = netdev_priv(netdev);
2606 pm_runtime_get_sync(&adapter->pdev->dev);
2607 return 0;
2608}
2609
2610static void igb_ethtool_complete(struct net_device *netdev)
2611{
2612 struct igb_adapter *adapter = netdev_priv(netdev);
2613 pm_runtime_put(&adapter->pdev->dev);
2614}
2615
0fc0b732 2616static const struct ethtool_ops igb_ethtool_ops = {
9d5c8243
AK		 2617 .get_settings = igb_get_settings,
2618 .set_settings = igb_set_settings,
2619 .get_drvinfo = igb_get_drvinfo,
2620 .get_regs_len = igb_get_regs_len,
2621 .get_regs = igb_get_regs,
2622 .get_wol = igb_get_wol,
2623 .set_wol = igb_set_wol,
2624 .get_msglevel = igb_get_msglevel,
2625 .set_msglevel = igb_set_msglevel,
2626 .nway_reset = igb_nway_reset,
3145535a 2627 .get_link = igb_get_link,
9d5c8243
AK		 2628 .get_eeprom_len = igb_get_eeprom_len,
2629 .get_eeprom = igb_get_eeprom,
2630 .set_eeprom = igb_set_eeprom,
2631 .get_ringparam = igb_get_ringparam,
2632 .set_ringparam = igb_set_ringparam,
2633 .get_pauseparam = igb_get_pauseparam,
2634 .set_pauseparam = igb_set_pauseparam,
9d5c8243
AK		 2635 .self_test = igb_diag_test,
2636 .get_strings = igb_get_strings,
936db355 2637 .set_phys_id = igb_set_phys_id,
9d5c8243
AK		 2638 .get_sset_count = igb_get_sset_count,
2639 .get_ethtool_stats = igb_get_ethtool_stats,
2640 .get_coalesce = igb_get_coalesce,
2641 .set_coalesce = igb_set_coalesce,
a79f4f88 2642 .get_ts_info = igb_get_ts_info,
039454a8
AA		 2643 .get_rxnfc = igb_get_rxnfc,
2644 .set_rxnfc = igb_set_rxnfc,
24a372cd
AA		 2645 .get_eee = igb_get_eee,
2646 .set_eee = igb_set_eee,
a79f4f88
MV		 2647 .begin = igb_ethtool_begin,
2648 .complete = igb_ethtool_complete,
9d5c8243
AK		 2649};
2650
2651void igb_set_ethtool_ops(struct net_device *netdev)
2652{
2653 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2654}
Linux 6.x block layer and io_uring tree(s)